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Merge branch 'fix/sun8i' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie...
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / aquantia / atlantic / hw_atl / hw_atl_a0.c
1 /*
2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */
9
10 /* File hw_atl_a0.c: Definition of Atlantic hardware specific functions. */
11
12 #include "../aq_hw.h"
13 #include "../aq_hw_utils.h"
14 #include "../aq_ring.h"
15 #include "hw_atl_a0.h"
16 #include "hw_atl_utils.h"
17 #include "hw_atl_llh.h"
18 #include "hw_atl_a0_internal.h"
19
20 static int hw_atl_a0_get_hw_caps(struct aq_hw_s *self,
21 struct aq_hw_caps_s *aq_hw_caps)
22 {
23 memcpy(aq_hw_caps, &hw_atl_a0_hw_caps_, sizeof(*aq_hw_caps));
24 return 0;
25 }
26
27 static struct aq_hw_s *hw_atl_a0_create(struct aq_pci_func_s *aq_pci_func,
28 unsigned int port,
29 struct aq_hw_ops *ops)
30 {
31 struct hw_atl_s *self = NULL;
32
33 self = kzalloc(sizeof(*self), GFP_KERNEL);
34 if (!self)
35 goto err_exit;
36
37 self->base.aq_pci_func = aq_pci_func;
38
39 self->base.not_ff_addr = 0x10U;
40
41 err_exit:
42 return (struct aq_hw_s *)self;
43 }
44
45 static void hw_atl_a0_destroy(struct aq_hw_s *self)
46 {
47 kfree(self);
48 }
49
50 static int hw_atl_a0_hw_reset(struct aq_hw_s *self)
51 {
52 int err = 0;
53
54 glb_glb_reg_res_dis_set(self, 1U);
55 pci_pci_reg_res_dis_set(self, 0U);
56 rx_rx_reg_res_dis_set(self, 0U);
57 tx_tx_reg_res_dis_set(self, 0U);
58
59 HW_ATL_FLUSH();
60 glb_soft_res_set(self, 1);
61
62 /* check 10 times by 1ms */
63 AQ_HW_WAIT_FOR(glb_soft_res_get(self) == 0, 1000U, 10U);
64 if (err < 0)
65 goto err_exit;
66
67 itr_irq_reg_res_dis_set(self, 0U);
68 itr_res_irq_set(self, 1U);
69
70 /* check 10 times by 1ms */
71 AQ_HW_WAIT_FOR(itr_res_irq_get(self) == 0, 1000U, 10U);
72 if (err < 0)
73 goto err_exit;
74
75 hw_atl_utils_mpi_set(self, MPI_RESET, 0x0U);
76
77 err = aq_hw_err_from_flags(self);
78
79 err_exit:
80 return err;
81 }
82
83 static int hw_atl_a0_hw_qos_set(struct aq_hw_s *self)
84 {
85 u32 tc = 0U;
86 u32 buff_size = 0U;
87 unsigned int i_priority = 0U;
88 bool is_rx_flow_control = false;
89
90 /* TPS Descriptor rate init */
91 tps_tx_pkt_shed_desc_rate_curr_time_res_set(self, 0x0U);
92 tps_tx_pkt_shed_desc_rate_lim_set(self, 0xA);
93
94 /* TPS VM init */
95 tps_tx_pkt_shed_desc_vm_arb_mode_set(self, 0U);
96
97 /* TPS TC credits init */
98 tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U);
99 tps_tx_pkt_shed_data_arb_mode_set(self, 0U);
100
101 tps_tx_pkt_shed_tc_data_max_credit_set(self, 0xFFF, 0U);
102 tps_tx_pkt_shed_tc_data_weight_set(self, 0x64, 0U);
103 tps_tx_pkt_shed_desc_tc_max_credit_set(self, 0x50, 0U);
104 tps_tx_pkt_shed_desc_tc_weight_set(self, 0x1E, 0U);
105
106 /* Tx buf size */
107 buff_size = HW_ATL_A0_TXBUF_MAX;
108
109 tpb_tx_pkt_buff_size_per_tc_set(self, buff_size, tc);
110 tpb_tx_buff_hi_threshold_per_tc_set(self,
111 (buff_size * (1024 / 32U) * 66U) /
112 100U, tc);
113 tpb_tx_buff_lo_threshold_per_tc_set(self,
114 (buff_size * (1024 / 32U) * 50U) /
115 100U, tc);
116
117 /* QoS Rx buf size per TC */
118 tc = 0;
119 is_rx_flow_control = (AQ_NIC_FC_RX & self->aq_nic_cfg->flow_control);
120 buff_size = HW_ATL_A0_RXBUF_MAX;
121
122 rpb_rx_pkt_buff_size_per_tc_set(self, buff_size, tc);
123 rpb_rx_buff_hi_threshold_per_tc_set(self,
124 (buff_size *
125 (1024U / 32U) * 66U) /
126 100U, tc);
127 rpb_rx_buff_lo_threshold_per_tc_set(self,
128 (buff_size *
129 (1024U / 32U) * 50U) /
130 100U, tc);
131 rpb_rx_xoff_en_per_tc_set(self, is_rx_flow_control ? 1U : 0U, tc);
132
133 /* QoS 802.1p priority -> TC mapping */
134 for (i_priority = 8U; i_priority--;)
135 rpf_rpb_user_priority_tc_map_set(self, i_priority, 0U);
136
137 return aq_hw_err_from_flags(self);
138 }
139
140 static int hw_atl_a0_hw_rss_hash_set(struct aq_hw_s *self,
141 struct aq_rss_parameters *rss_params)
142 {
143 struct aq_nic_cfg_s *cfg = NULL;
144 int err = 0;
145 unsigned int i = 0U;
146 unsigned int addr = 0U;
147
148 cfg = self->aq_nic_cfg;
149
150 for (i = 10, addr = 0U; i--; ++addr) {
151 u32 key_data = cfg->is_rss ?
152 __swab32(rss_params->hash_secret_key[i]) : 0U;
153 rpf_rss_key_wr_data_set(self, key_data);
154 rpf_rss_key_addr_set(self, addr);
155 rpf_rss_key_wr_en_set(self, 1U);
156 AQ_HW_WAIT_FOR(rpf_rss_key_wr_en_get(self) == 0, 1000U, 10U);
157 if (err < 0)
158 goto err_exit;
159 }
160
161 err = aq_hw_err_from_flags(self);
162
163 err_exit:
164 return err;
165 }
166
167 static int hw_atl_a0_hw_rss_set(struct aq_hw_s *self,
168 struct aq_rss_parameters *rss_params)
169 {
170 u8 *indirection_table = rss_params->indirection_table;
171 u32 i = 0U;
172 u32 num_rss_queues = max(1U, self->aq_nic_cfg->num_rss_queues);
173 int err = 0;
174 u16 bitary[(HW_ATL_A0_RSS_REDIRECTION_MAX *
175 HW_ATL_A0_RSS_REDIRECTION_BITS / 16U)];
176
177 memset(bitary, 0, sizeof(bitary));
178
179 for (i = HW_ATL_A0_RSS_REDIRECTION_MAX; i--; ) {
180 (*(u32 *)(bitary + ((i * 3U) / 16U))) |=
181 ((indirection_table[i] % num_rss_queues) <<
182 ((i * 3U) & 0xFU));
183 }
184
185 for (i = AQ_DIMOF(bitary); i--;) {
186 rpf_rss_redir_tbl_wr_data_set(self, bitary[i]);
187 rpf_rss_redir_tbl_addr_set(self, i);
188 rpf_rss_redir_wr_en_set(self, 1U);
189 AQ_HW_WAIT_FOR(rpf_rss_redir_wr_en_get(self) == 0, 1000U, 10U);
190 if (err < 0)
191 goto err_exit;
192 }
193
194 err = aq_hw_err_from_flags(self);
195
196 err_exit:
197 return err;
198 }
199
200 static int hw_atl_a0_hw_offload_set(struct aq_hw_s *self,
201 struct aq_nic_cfg_s *aq_nic_cfg)
202 {
203 int err = 0;
204
205 /* TX checksums offloads*/
206 tpo_ipv4header_crc_offload_en_set(self, 1);
207 tpo_tcp_udp_crc_offload_en_set(self, 1);
208 if (err < 0)
209 goto err_exit;
210
211 /* RX checksums offloads*/
212 rpo_ipv4header_crc_offload_en_set(self, 1);
213 rpo_tcp_udp_crc_offload_en_set(self, 1);
214 if (err < 0)
215 goto err_exit;
216
217 /* LSO offloads*/
218 tdm_large_send_offload_en_set(self, 0xFFFFFFFFU);
219 if (err < 0)
220 goto err_exit;
221
222 err = aq_hw_err_from_flags(self);
223
224 err_exit:
225 return err;
226 }
227
228 static int hw_atl_a0_hw_init_tx_path(struct aq_hw_s *self)
229 {
230 thm_lso_tcp_flag_of_first_pkt_set(self, 0x0FF6U);
231 thm_lso_tcp_flag_of_middle_pkt_set(self, 0x0FF6U);
232 thm_lso_tcp_flag_of_last_pkt_set(self, 0x0F7FU);
233
234 /* Tx interrupts */
235 tdm_tx_desc_wr_wb_irq_en_set(self, 1U);
236
237 /* misc */
238 aq_hw_write_reg(self, 0x00007040U, IS_CHIP_FEATURE(TPO2) ?
239 0x00010000U : 0x00000000U);
240 tdm_tx_dca_en_set(self, 0U);
241 tdm_tx_dca_mode_set(self, 0U);
242
243 tpb_tx_path_scp_ins_en_set(self, 1U);
244
245 return aq_hw_err_from_flags(self);
246 }
247
248 static int hw_atl_a0_hw_init_rx_path(struct aq_hw_s *self)
249 {
250 struct aq_nic_cfg_s *cfg = self->aq_nic_cfg;
251 int i;
252
253 /* Rx TC/RSS number config */
254 rpb_rpf_rx_traf_class_mode_set(self, 1U);
255
256 /* Rx flow control */
257 rpb_rx_flow_ctl_mode_set(self, 1U);
258
259 /* RSS Ring selection */
260 reg_rx_flr_rss_control1set(self, cfg->is_rss ?
261 0xB3333333U : 0x00000000U);
262
263 /* Multicast filters */
264 for (i = HW_ATL_A0_MAC_MAX; i--;) {
265 rpfl2_uc_flr_en_set(self, (i == 0U) ? 1U : 0U, i);
266 rpfl2unicast_flr_act_set(self, 1U, i);
267 }
268
269 reg_rx_flr_mcst_flr_msk_set(self, 0x00000000U);
270 reg_rx_flr_mcst_flr_set(self, 0x00010FFFU, 0U);
271
272 /* Vlan filters */
273 rpf_vlan_outer_etht_set(self, 0x88A8U);
274 rpf_vlan_inner_etht_set(self, 0x8100U);
275 rpf_vlan_prom_mode_en_set(self, 1);
276
277 /* Rx Interrupts */
278 rdm_rx_desc_wr_wb_irq_en_set(self, 1U);
279
280 /* misc */
281 rpfl2broadcast_flr_act_set(self, 1U);
282 rpfl2broadcast_count_threshold_set(self, 0xFFFFU & (~0U / 256U));
283
284 rdm_rx_dca_en_set(self, 0U);
285 rdm_rx_dca_mode_set(self, 0U);
286
287 return aq_hw_err_from_flags(self);
288 }
289
290 static int hw_atl_a0_hw_mac_addr_set(struct aq_hw_s *self, u8 *mac_addr)
291 {
292 int err = 0;
293 unsigned int h = 0U;
294 unsigned int l = 0U;
295
296 if (!mac_addr) {
297 err = -EINVAL;
298 goto err_exit;
299 }
300 h = (mac_addr[0] << 8) | (mac_addr[1]);
301 l = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
302 (mac_addr[4] << 8) | mac_addr[5];
303
304 rpfl2_uc_flr_en_set(self, 0U, HW_ATL_A0_MAC);
305 rpfl2unicast_dest_addresslsw_set(self, l, HW_ATL_A0_MAC);
306 rpfl2unicast_dest_addressmsw_set(self, h, HW_ATL_A0_MAC);
307 rpfl2_uc_flr_en_set(self, 1U, HW_ATL_A0_MAC);
308
309 err = aq_hw_err_from_flags(self);
310
311 err_exit:
312 return err;
313 }
314
315 static int hw_atl_a0_hw_init(struct aq_hw_s *self,
316 struct aq_nic_cfg_s *aq_nic_cfg,
317 u8 *mac_addr)
318 {
319 static u32 aq_hw_atl_igcr_table_[4][2] = {
320 { 0x20000000U, 0x20000000U }, /* AQ_IRQ_INVALID */
321 { 0x20000080U, 0x20000080U }, /* AQ_IRQ_LEGACY */
322 { 0x20000021U, 0x20000025U }, /* AQ_IRQ_MSI */
323 { 0x20000022U, 0x20000026U } /* AQ_IRQ_MSIX */
324 };
325
326 int err = 0;
327
328 self->aq_nic_cfg = aq_nic_cfg;
329
330 hw_atl_utils_hw_chip_features_init(self,
331 &PHAL_ATLANTIC_A0->chip_features);
332
333 hw_atl_a0_hw_init_tx_path(self);
334 hw_atl_a0_hw_init_rx_path(self);
335
336 hw_atl_a0_hw_mac_addr_set(self, mac_addr);
337
338 hw_atl_utils_mpi_set(self, MPI_INIT, aq_nic_cfg->link_speed_msk);
339
340 reg_tx_dma_debug_ctl_set(self, 0x800000b8U);
341 reg_tx_dma_debug_ctl_set(self, 0x000000b8U);
342
343 hw_atl_a0_hw_qos_set(self);
344 hw_atl_a0_hw_rss_set(self, &aq_nic_cfg->aq_rss);
345 hw_atl_a0_hw_rss_hash_set(self, &aq_nic_cfg->aq_rss);
346
347 err = aq_hw_err_from_flags(self);
348 if (err < 0)
349 goto err_exit;
350
351 /* Interrupts */
352 reg_irq_glb_ctl_set(self,
353 aq_hw_atl_igcr_table_[aq_nic_cfg->irq_type]
354 [(aq_nic_cfg->vecs > 1U) ?
355 1 : 0]);
356
357 itr_irq_auto_masklsw_set(self, aq_nic_cfg->aq_hw_caps->irq_mask);
358
359 /* Interrupts */
360 reg_gen_irq_map_set(self,
361 ((HW_ATL_A0_ERR_INT << 0x18) | (1U << 0x1F)) |
362 ((HW_ATL_A0_ERR_INT << 0x10) | (1U << 0x17)) |
363 ((HW_ATL_A0_ERR_INT << 8) | (1U << 0xF)) |
364 ((HW_ATL_A0_ERR_INT) | (1U << 0x7)), 0U);
365
366 hw_atl_a0_hw_offload_set(self, aq_nic_cfg);
367
368 err_exit:
369 return err;
370 }
371
372 static int hw_atl_a0_hw_ring_tx_start(struct aq_hw_s *self,
373 struct aq_ring_s *ring)
374 {
375 tdm_tx_desc_en_set(self, 1, ring->idx);
376 return aq_hw_err_from_flags(self);
377 }
378
379 static int hw_atl_a0_hw_ring_rx_start(struct aq_hw_s *self,
380 struct aq_ring_s *ring)
381 {
382 rdm_rx_desc_en_set(self, 1, ring->idx);
383 return aq_hw_err_from_flags(self);
384 }
385
386 static int hw_atl_a0_hw_start(struct aq_hw_s *self)
387 {
388 tpb_tx_buff_en_set(self, 1);
389 rpb_rx_buff_en_set(self, 1);
390 return aq_hw_err_from_flags(self);
391 }
392
393 static int hw_atl_a0_hw_tx_ring_tail_update(struct aq_hw_s *self,
394 struct aq_ring_s *ring)
395 {
396 reg_tx_dma_desc_tail_ptr_set(self, ring->sw_tail, ring->idx);
397 return 0;
398 }
399
400 static int hw_atl_a0_hw_ring_tx_xmit(struct aq_hw_s *self,
401 struct aq_ring_s *ring,
402 unsigned int frags)
403 {
404 struct aq_ring_buff_s *buff = NULL;
405 struct hw_atl_txd_s *txd = NULL;
406 unsigned int buff_pa_len = 0U;
407 unsigned int pkt_len = 0U;
408 unsigned int frag_count = 0U;
409 bool is_gso = false;
410
411 buff = &ring->buff_ring[ring->sw_tail];
412 pkt_len = (buff->is_eop && buff->is_sop) ? buff->len : buff->len_pkt;
413
414 for (frag_count = 0; frag_count < frags; frag_count++) {
415 txd = (struct hw_atl_txd_s *)&ring->dx_ring[ring->sw_tail *
416 HW_ATL_A0_TXD_SIZE];
417 txd->ctl = 0;
418 txd->ctl2 = 0;
419 txd->buf_addr = 0;
420
421 buff = &ring->buff_ring[ring->sw_tail];
422
423 if (buff->is_txc) {
424 txd->ctl |= (buff->len_l3 << 31) |
425 (buff->len_l2 << 24) |
426 HW_ATL_A0_TXD_CTL_CMD_TCP |
427 HW_ATL_A0_TXD_CTL_DESC_TYPE_TXC;
428 txd->ctl2 |= (buff->mss << 16) |
429 (buff->len_l4 << 8) |
430 (buff->len_l3 >> 1);
431
432 pkt_len -= (buff->len_l4 +
433 buff->len_l3 +
434 buff->len_l2);
435 is_gso = true;
436 } else {
437 buff_pa_len = buff->len;
438
439 txd->buf_addr = buff->pa;
440 txd->ctl |= (HW_ATL_A0_TXD_CTL_BLEN &
441 ((u32)buff_pa_len << 4));
442 txd->ctl |= HW_ATL_A0_TXD_CTL_DESC_TYPE_TXD;
443 /* PAY_LEN */
444 txd->ctl2 |= HW_ATL_A0_TXD_CTL2_LEN & (pkt_len << 14);
445
446 if (is_gso) {
447 txd->ctl |= HW_ATL_A0_TXD_CTL_CMD_LSO;
448 txd->ctl2 |= HW_ATL_A0_TXD_CTL2_CTX_EN;
449 }
450
451 /* Tx checksum offloads */
452 if (buff->is_ip_cso)
453 txd->ctl |= HW_ATL_A0_TXD_CTL_CMD_IPCSO;
454
455 if (buff->is_udp_cso || buff->is_tcp_cso)
456 txd->ctl |= HW_ATL_A0_TXD_CTL_CMD_TUCSO;
457
458 if (unlikely(buff->is_eop)) {
459 txd->ctl |= HW_ATL_A0_TXD_CTL_EOP;
460 txd->ctl |= HW_ATL_A0_TXD_CTL_CMD_WB;
461 }
462 }
463
464 ring->sw_tail = aq_ring_next_dx(ring, ring->sw_tail);
465 }
466
467 hw_atl_a0_hw_tx_ring_tail_update(self, ring);
468 return aq_hw_err_from_flags(self);
469 }
470
471 static int hw_atl_a0_hw_ring_rx_init(struct aq_hw_s *self,
472 struct aq_ring_s *aq_ring,
473 struct aq_ring_param_s *aq_ring_param)
474 {
475 u32 dma_desc_addr_lsw = (u32)aq_ring->dx_ring_pa;
476 u32 dma_desc_addr_msw = (u32)(((u64)aq_ring->dx_ring_pa) >> 32);
477
478 rdm_rx_desc_en_set(self, false, aq_ring->idx);
479
480 rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx);
481
482 reg_rx_dma_desc_base_addresslswset(self, dma_desc_addr_lsw,
483 aq_ring->idx);
484
485 reg_rx_dma_desc_base_addressmswset(self,
486 dma_desc_addr_msw, aq_ring->idx);
487
488 rdm_rx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx);
489
490 rdm_rx_desc_data_buff_size_set(self,
491 AQ_CFG_RX_FRAME_MAX / 1024U,
492 aq_ring->idx);
493
494 rdm_rx_desc_head_buff_size_set(self, 0U, aq_ring->idx);
495 rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx);
496 rpo_rx_desc_vlan_stripping_set(self, 0U, aq_ring->idx);
497
498 /* Rx ring set mode */
499
500 /* Mapping interrupt vector */
501 itr_irq_map_rx_set(self, aq_ring_param->vec_idx, aq_ring->idx);
502 itr_irq_map_en_rx_set(self, true, aq_ring->idx);
503
504 rdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx);
505 rdm_rx_desc_dca_en_set(self, 0U, aq_ring->idx);
506 rdm_rx_head_dca_en_set(self, 0U, aq_ring->idx);
507 rdm_rx_pld_dca_en_set(self, 0U, aq_ring->idx);
508
509 return aq_hw_err_from_flags(self);
510 }
511
512 static int hw_atl_a0_hw_ring_tx_init(struct aq_hw_s *self,
513 struct aq_ring_s *aq_ring,
514 struct aq_ring_param_s *aq_ring_param)
515 {
516 u32 dma_desc_lsw_addr = (u32)aq_ring->dx_ring_pa;
517 u32 dma_desc_msw_addr = (u32)(((u64)aq_ring->dx_ring_pa) >> 32);
518
519 reg_tx_dma_desc_base_addresslswset(self, dma_desc_lsw_addr,
520 aq_ring->idx);
521
522 reg_tx_dma_desc_base_addressmswset(self, dma_desc_msw_addr,
523 aq_ring->idx);
524
525 tdm_tx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx);
526
527 hw_atl_a0_hw_tx_ring_tail_update(self, aq_ring);
528
529 /* Set Tx threshold */
530 tdm_tx_desc_wr_wb_threshold_set(self, 0U, aq_ring->idx);
531
532 /* Mapping interrupt vector */
533 itr_irq_map_tx_set(self, aq_ring_param->vec_idx, aq_ring->idx);
534 itr_irq_map_en_tx_set(self, true, aq_ring->idx);
535
536 tdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx);
537 tdm_tx_desc_dca_en_set(self, 0U, aq_ring->idx);
538
539 return aq_hw_err_from_flags(self);
540 }
541
542 static int hw_atl_a0_hw_ring_rx_fill(struct aq_hw_s *self,
543 struct aq_ring_s *ring,
544 unsigned int sw_tail_old)
545 {
546 for (; sw_tail_old != ring->sw_tail;
547 sw_tail_old = aq_ring_next_dx(ring, sw_tail_old)) {
548 struct hw_atl_rxd_s *rxd =
549 (struct hw_atl_rxd_s *)&ring->dx_ring[sw_tail_old *
550 HW_ATL_A0_RXD_SIZE];
551
552 struct aq_ring_buff_s *buff = &ring->buff_ring[sw_tail_old];
553
554 rxd->buf_addr = buff->pa;
555 rxd->hdr_addr = 0U;
556 }
557
558 reg_rx_dma_desc_tail_ptr_set(self, sw_tail_old, ring->idx);
559
560 return aq_hw_err_from_flags(self);
561 }
562
563 static int hw_atl_a0_hw_ring_tx_head_update(struct aq_hw_s *self,
564 struct aq_ring_s *ring)
565 {
566 int err = 0;
567 unsigned int hw_head_ = tdm_tx_desc_head_ptr_get(self, ring->idx);
568
569 if (aq_utils_obj_test(&self->header.flags, AQ_HW_FLAG_ERR_UNPLUG)) {
570 err = -ENXIO;
571 goto err_exit;
572 }
573 ring->hw_head = hw_head_;
574 err = aq_hw_err_from_flags(self);
575
576 err_exit:
577 return err;
578 }
579
580 static int hw_atl_a0_hw_ring_rx_receive(struct aq_hw_s *self,
581 struct aq_ring_s *ring)
582 {
583 struct device *ndev = aq_nic_get_dev(ring->aq_nic);
584
585 for (; ring->hw_head != ring->sw_tail;
586 ring->hw_head = aq_ring_next_dx(ring, ring->hw_head)) {
587 struct aq_ring_buff_s *buff = NULL;
588 struct hw_atl_rxd_wb_s *rxd_wb = (struct hw_atl_rxd_wb_s *)
589 &ring->dx_ring[ring->hw_head * HW_ATL_A0_RXD_SIZE];
590
591 unsigned int is_err = 1U;
592 unsigned int is_rx_check_sum_enabled = 0U;
593 unsigned int pkt_type = 0U;
594
595 if (!(rxd_wb->status & 0x5U)) { /* RxD is not done */
596 if ((1U << 4) &
597 reg_rx_dma_desc_status_get(self, ring->idx)) {
598 rdm_rx_desc_en_set(self, false, ring->idx);
599 rdm_rx_desc_res_set(self, true, ring->idx);
600 rdm_rx_desc_res_set(self, false, ring->idx);
601 rdm_rx_desc_en_set(self, true, ring->idx);
602 }
603
604 if (ring->hw_head ||
605 (rdm_rx_desc_head_ptr_get(self, ring->idx) < 2U)) {
606 break;
607 } else if (!(rxd_wb->status & 0x1U)) {
608 struct hw_atl_rxd_wb_s *rxd_wb1 =
609 (struct hw_atl_rxd_wb_s *)
610 (&ring->dx_ring[(1U) *
611 HW_ATL_A0_RXD_SIZE]);
612
613 if ((rxd_wb1->status & 0x1U)) {
614 rxd_wb->pkt_len = 1514U;
615 rxd_wb->status = 3U;
616 } else {
617 break;
618 }
619 }
620 }
621
622 buff = &ring->buff_ring[ring->hw_head];
623
624 if (0x3U != (rxd_wb->status & 0x3U))
625 rxd_wb->status |= 4;
626
627 is_err = (0x0000001CU & rxd_wb->status);
628 is_rx_check_sum_enabled = (rxd_wb->type) & (0x3U << 19);
629 pkt_type = 0xFFU & (rxd_wb->type >> 4);
630
631 if (is_rx_check_sum_enabled) {
632 if (0x0U == (pkt_type & 0x3U))
633 buff->is_ip_cso = (is_err & 0x08U) ? 0 : 1;
634
635 if (0x4U == (pkt_type & 0x1CU))
636 buff->is_udp_cso = (is_err & 0x10U) ? 0 : 1;
637 else if (0x0U == (pkt_type & 0x1CU))
638 buff->is_tcp_cso = (is_err & 0x10U) ? 0 : 1;
639 }
640
641 is_err &= ~0x18U;
642 is_err &= ~0x04U;
643
644 dma_unmap_page(ndev, buff->pa, buff->len, DMA_FROM_DEVICE);
645
646 if (is_err || rxd_wb->type & 0x1000U) {
647 /* status error or DMA error */
648 buff->is_error = 1U;
649 } else {
650 if (self->aq_nic_cfg->is_rss) {
651 /* last 4 byte */
652 u16 rss_type = rxd_wb->type & 0xFU;
653
654 if (rss_type && rss_type < 0x8U) {
655 buff->is_hash_l4 = (rss_type == 0x4 ||
656 rss_type == 0x5);
657 buff->rss_hash = rxd_wb->rss_hash;
658 }
659 }
660
661 if (HW_ATL_A0_RXD_WB_STAT2_EOP & rxd_wb->status) {
662 buff->len = rxd_wb->pkt_len %
663 AQ_CFG_RX_FRAME_MAX;
664 buff->len = buff->len ?
665 buff->len : AQ_CFG_RX_FRAME_MAX;
666 buff->next = 0U;
667 buff->is_eop = 1U;
668 } else {
669 /* jumbo */
670 buff->next = aq_ring_next_dx(ring,
671 ring->hw_head);
672 ++ring->stats.rx.jumbo_packets;
673 }
674 }
675 }
676
677 return aq_hw_err_from_flags(self);
678 }
679
680 static int hw_atl_a0_hw_irq_enable(struct aq_hw_s *self, u64 mask)
681 {
682 itr_irq_msk_setlsw_set(self, LODWORD(mask) |
683 (1U << HW_ATL_A0_ERR_INT));
684 return aq_hw_err_from_flags(self);
685 }
686
687 static int hw_atl_a0_hw_irq_disable(struct aq_hw_s *self, u64 mask)
688 {
689 itr_irq_msk_clearlsw_set(self, LODWORD(mask));
690 itr_irq_status_clearlsw_set(self, LODWORD(mask));
691
692 if ((1U << 16) & reg_gen_irq_status_get(self))
693
694 atomic_inc(&PHAL_ATLANTIC_A0->dpc);
695
696 return aq_hw_err_from_flags(self);
697 }
698
699 static int hw_atl_a0_hw_irq_read(struct aq_hw_s *self, u64 *mask)
700 {
701 *mask = itr_irq_statuslsw_get(self);
702 return aq_hw_err_from_flags(self);
703 }
704
705 #define IS_FILTER_ENABLED(_F_) ((packet_filter & (_F_)) ? 1U : 0U)
706
707 static int hw_atl_a0_hw_packet_filter_set(struct aq_hw_s *self,
708 unsigned int packet_filter)
709 {
710 unsigned int i = 0U;
711
712 rpfl2promiscuous_mode_en_set(self, IS_FILTER_ENABLED(IFF_PROMISC));
713 rpfl2multicast_flr_en_set(self, IS_FILTER_ENABLED(IFF_MULTICAST), 0);
714 rpfl2broadcast_en_set(self, IS_FILTER_ENABLED(IFF_BROADCAST));
715
716 self->aq_nic_cfg->is_mc_list_enabled =
717 IS_FILTER_ENABLED(IFF_MULTICAST);
718
719 for (i = HW_ATL_A0_MAC_MIN; i < HW_ATL_A0_MAC_MAX; ++i)
720 rpfl2_uc_flr_en_set(self,
721 (self->aq_nic_cfg->is_mc_list_enabled &&
722 (i <= self->aq_nic_cfg->mc_list_count)) ?
723 1U : 0U, i);
724
725 return aq_hw_err_from_flags(self);
726 }
727
728 #undef IS_FILTER_ENABLED
729
730 static int hw_atl_a0_hw_multicast_list_set(struct aq_hw_s *self,
731 u8 ar_mac
732 [AQ_CFG_MULTICAST_ADDRESS_MAX]
733 [ETH_ALEN],
734 u32 count)
735 {
736 int err = 0;
737
738 if (count > (HW_ATL_A0_MAC_MAX - HW_ATL_A0_MAC_MIN)) {
739 err = EBADRQC;
740 goto err_exit;
741 }
742 for (self->aq_nic_cfg->mc_list_count = 0U;
743 self->aq_nic_cfg->mc_list_count < count;
744 ++self->aq_nic_cfg->mc_list_count) {
745 u32 i = self->aq_nic_cfg->mc_list_count;
746 u32 h = (ar_mac[i][0] << 8) | (ar_mac[i][1]);
747 u32 l = (ar_mac[i][2] << 24) | (ar_mac[i][3] << 16) |
748 (ar_mac[i][4] << 8) | ar_mac[i][5];
749
750 rpfl2_uc_flr_en_set(self, 0U, HW_ATL_A0_MAC_MIN + i);
751
752 rpfl2unicast_dest_addresslsw_set(self,
753 l, HW_ATL_A0_MAC_MIN + i);
754
755 rpfl2unicast_dest_addressmsw_set(self,
756 h, HW_ATL_A0_MAC_MIN + i);
757
758 rpfl2_uc_flr_en_set(self,
759 (self->aq_nic_cfg->is_mc_list_enabled),
760 HW_ATL_A0_MAC_MIN + i);
761 }
762
763 err = aq_hw_err_from_flags(self);
764
765 err_exit:
766 return err;
767 }
768
769 static int hw_atl_a0_hw_interrupt_moderation_set(struct aq_hw_s *self,
770 bool itr_enabled)
771 {
772 unsigned int i = 0U;
773
774 if (itr_enabled && self->aq_nic_cfg->itr) {
775 if (self->aq_nic_cfg->itr != 0xFFFFU) {
776 u32 itr_ = (self->aq_nic_cfg->itr >> 1);
777
778 itr_ = min(AQ_CFG_IRQ_MASK, itr_);
779
780 PHAL_ATLANTIC_A0->itr_rx = 0x80000000U |
781 (itr_ << 0x10);
782 } else {
783 u32 n = 0xFFFFU & aq_hw_read_reg(self, 0x00002A00U);
784
785 if (n < self->aq_link_status.mbps) {
786 PHAL_ATLANTIC_A0->itr_rx = 0U;
787 } else {
788 static unsigned int hw_timers_tbl_[] = {
789 0x01CU, /* 10Gbit */
790 0x039U, /* 5Gbit */
791 0x039U, /* 5Gbit 5GS */
792 0x073U, /* 2.5Gbit */
793 0x120U, /* 1Gbit */
794 0x1FFU, /* 100Mbit */
795 };
796
797 unsigned int speed_index =
798 hw_atl_utils_mbps_2_speed_index(
799 self->aq_link_status.mbps);
800
801 PHAL_ATLANTIC_A0->itr_rx =
802 0x80000000U |
803 (hw_timers_tbl_[speed_index] << 0x10U);
804 }
805
806 aq_hw_write_reg(self, 0x00002A00U, 0x40000000U);
807 aq_hw_write_reg(self, 0x00002A00U, 0x8D000000U);
808 }
809 } else {
810 PHAL_ATLANTIC_A0->itr_rx = 0U;
811 }
812
813 for (i = HW_ATL_A0_RINGS_MAX; i--;)
814 reg_irq_thr_set(self, PHAL_ATLANTIC_A0->itr_rx, i);
815
816 return aq_hw_err_from_flags(self);
817 }
818
819 static int hw_atl_a0_hw_stop(struct aq_hw_s *self)
820 {
821 hw_atl_a0_hw_irq_disable(self, HW_ATL_A0_INT_MASK);
822 return aq_hw_err_from_flags(self);
823 }
824
825 static int hw_atl_a0_hw_ring_tx_stop(struct aq_hw_s *self,
826 struct aq_ring_s *ring)
827 {
828 tdm_tx_desc_en_set(self, 0U, ring->idx);
829 return aq_hw_err_from_flags(self);
830 }
831
832 static int hw_atl_a0_hw_ring_rx_stop(struct aq_hw_s *self,
833 struct aq_ring_s *ring)
834 {
835 rdm_rx_desc_en_set(self, 0U, ring->idx);
836 return aq_hw_err_from_flags(self);
837 }
838
839 static int hw_atl_a0_hw_set_speed(struct aq_hw_s *self, u32 speed)
840 {
841 int err = 0;
842
843 err = hw_atl_utils_mpi_set_speed(self, speed, MPI_INIT);
844 if (err < 0)
845 goto err_exit;
846
847 err_exit:
848 return err;
849 }
850
851 static struct aq_hw_ops hw_atl_ops_ = {
852 .create = hw_atl_a0_create,
853 .destroy = hw_atl_a0_destroy,
854 .get_hw_caps = hw_atl_a0_get_hw_caps,
855
856 .hw_get_mac_permanent = hw_atl_utils_get_mac_permanent,
857 .hw_set_mac_address = hw_atl_a0_hw_mac_addr_set,
858 .hw_get_link_status = hw_atl_utils_mpi_get_link_status,
859 .hw_set_link_speed = hw_atl_a0_hw_set_speed,
860 .hw_init = hw_atl_a0_hw_init,
861 .hw_deinit = hw_atl_utils_hw_deinit,
862 .hw_set_power = hw_atl_utils_hw_set_power,
863 .hw_reset = hw_atl_a0_hw_reset,
864 .hw_start = hw_atl_a0_hw_start,
865 .hw_ring_tx_start = hw_atl_a0_hw_ring_tx_start,
866 .hw_ring_tx_stop = hw_atl_a0_hw_ring_tx_stop,
867 .hw_ring_rx_start = hw_atl_a0_hw_ring_rx_start,
868 .hw_ring_rx_stop = hw_atl_a0_hw_ring_rx_stop,
869 .hw_stop = hw_atl_a0_hw_stop,
870
871 .hw_ring_tx_xmit = hw_atl_a0_hw_ring_tx_xmit,
872 .hw_ring_tx_head_update = hw_atl_a0_hw_ring_tx_head_update,
873
874 .hw_ring_rx_receive = hw_atl_a0_hw_ring_rx_receive,
875 .hw_ring_rx_fill = hw_atl_a0_hw_ring_rx_fill,
876
877 .hw_irq_enable = hw_atl_a0_hw_irq_enable,
878 .hw_irq_disable = hw_atl_a0_hw_irq_disable,
879 .hw_irq_read = hw_atl_a0_hw_irq_read,
880
881 .hw_ring_rx_init = hw_atl_a0_hw_ring_rx_init,
882 .hw_ring_tx_init = hw_atl_a0_hw_ring_tx_init,
883 .hw_packet_filter_set = hw_atl_a0_hw_packet_filter_set,
884 .hw_multicast_list_set = hw_atl_a0_hw_multicast_list_set,
885 .hw_interrupt_moderation_set = hw_atl_a0_hw_interrupt_moderation_set,
886 .hw_rss_set = hw_atl_a0_hw_rss_set,
887 .hw_rss_hash_set = hw_atl_a0_hw_rss_hash_set,
888 .hw_get_regs = hw_atl_utils_hw_get_regs,
889 .hw_get_hw_stats = hw_atl_utils_get_hw_stats,
890 .hw_get_fw_version = hw_atl_utils_get_fw_version,
891 };
892
893 struct aq_hw_ops *hw_atl_a0_get_ops_by_id(struct pci_dev *pdev)
894 {
895 bool is_vid_ok = (pdev->vendor == PCI_VENDOR_ID_AQUANTIA);
896 bool is_did_ok = ((pdev->device == HW_ATL_DEVICE_ID_0001) ||
897 (pdev->device == HW_ATL_DEVICE_ID_D100) ||
898 (pdev->device == HW_ATL_DEVICE_ID_D107) ||
899 (pdev->device == HW_ATL_DEVICE_ID_D108) ||
900 (pdev->device == HW_ATL_DEVICE_ID_D109));
901
902 bool is_rev_ok = (pdev->revision == 1U);
903
904 return (is_vid_ok && is_did_ok && is_rev_ok) ? &hw_atl_ops_ : NULL;
905 }
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