2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
10 /* File hw_atl_b0.c: Definition of Atlantic hardware specific functions. */
13 #include "../aq_hw_utils.h"
14 #include "../aq_ring.h"
15 #include "hw_atl_b0.h"
16 #include "hw_atl_utils.h"
17 #include "hw_atl_llh.h"
18 #include "hw_atl_b0_internal.h"
20 static int hw_atl_b0_get_hw_caps(struct aq_hw_s
*self
,
21 struct aq_hw_caps_s
*aq_hw_caps
)
23 memcpy(aq_hw_caps
, &hw_atl_b0_hw_caps_
, sizeof(*aq_hw_caps
));
27 static struct aq_hw_s
*hw_atl_b0_create(struct aq_pci_func_s
*aq_pci_func
,
29 struct aq_hw_ops
*ops
)
31 struct hw_atl_s
*self
= NULL
;
33 self
= kzalloc(sizeof(*self
), GFP_KERNEL
);
37 self
->base
.aq_pci_func
= aq_pci_func
;
39 self
->base
.not_ff_addr
= 0x10U
;
42 return (struct aq_hw_s
*)self
;
45 static void hw_atl_b0_destroy(struct aq_hw_s
*self
)
50 static int hw_atl_b0_hw_reset(struct aq_hw_s
*self
)
54 glb_glb_reg_res_dis_set(self
, 1U);
55 pci_pci_reg_res_dis_set(self
, 0U);
56 rx_rx_reg_res_dis_set(self
, 0U);
57 tx_tx_reg_res_dis_set(self
, 0U);
60 glb_soft_res_set(self
, 1);
62 /* check 10 times by 1ms */
63 AQ_HW_WAIT_FOR(glb_soft_res_get(self
) == 0, 1000U, 10U);
67 itr_irq_reg_res_dis_set(self
, 0U);
68 itr_res_irq_set(self
, 1U);
70 /* check 10 times by 1ms */
71 AQ_HW_WAIT_FOR(itr_res_irq_get(self
) == 0, 1000U, 10U);
75 hw_atl_utils_mpi_set(self
, MPI_RESET
, 0x0U
);
77 err
= aq_hw_err_from_flags(self
);
83 static int hw_atl_b0_hw_qos_set(struct aq_hw_s
*self
)
87 unsigned int i_priority
= 0U;
88 bool is_rx_flow_control
= false;
90 /* TPS Descriptor rate init */
91 tps_tx_pkt_shed_desc_rate_curr_time_res_set(self
, 0x0U
);
92 tps_tx_pkt_shed_desc_rate_lim_set(self
, 0xA);
95 tps_tx_pkt_shed_desc_vm_arb_mode_set(self
, 0U);
97 /* TPS TC credits init */
98 tps_tx_pkt_shed_desc_tc_arb_mode_set(self
, 0U);
99 tps_tx_pkt_shed_data_arb_mode_set(self
, 0U);
101 tps_tx_pkt_shed_tc_data_max_credit_set(self
, 0xFFF, 0U);
102 tps_tx_pkt_shed_tc_data_weight_set(self
, 0x64, 0U);
103 tps_tx_pkt_shed_desc_tc_max_credit_set(self
, 0x50, 0U);
104 tps_tx_pkt_shed_desc_tc_weight_set(self
, 0x1E, 0U);
107 buff_size
= HW_ATL_B0_TXBUF_MAX
;
109 tpb_tx_pkt_buff_size_per_tc_set(self
, buff_size
, tc
);
110 tpb_tx_buff_hi_threshold_per_tc_set(self
,
111 (buff_size
* (1024 / 32U) * 66U) /
113 tpb_tx_buff_lo_threshold_per_tc_set(self
,
114 (buff_size
* (1024 / 32U) * 50U) /
117 /* QoS Rx buf size per TC */
119 is_rx_flow_control
= (AQ_NIC_FC_RX
& self
->aq_nic_cfg
->flow_control
);
120 buff_size
= HW_ATL_B0_RXBUF_MAX
;
122 rpb_rx_pkt_buff_size_per_tc_set(self
, buff_size
, tc
);
123 rpb_rx_buff_hi_threshold_per_tc_set(self
,
125 (1024U / 32U) * 66U) /
127 rpb_rx_buff_lo_threshold_per_tc_set(self
,
129 (1024U / 32U) * 50U) /
131 rpb_rx_xoff_en_per_tc_set(self
, is_rx_flow_control
? 1U : 0U, tc
);
133 /* QoS 802.1p priority -> TC mapping */
134 for (i_priority
= 8U; i_priority
--;)
135 rpf_rpb_user_priority_tc_map_set(self
, i_priority
, 0U);
137 return aq_hw_err_from_flags(self
);
140 static int hw_atl_b0_hw_rss_hash_set(struct aq_hw_s
*self
,
141 struct aq_rss_parameters
*rss_params
)
143 struct aq_nic_cfg_s
*cfg
= NULL
;
146 unsigned int addr
= 0U;
148 cfg
= self
->aq_nic_cfg
;
150 for (i
= 10, addr
= 0U; i
--; ++addr
) {
151 u32 key_data
= cfg
->is_rss
?
152 __swab32(rss_params
->hash_secret_key
[i
]) : 0U;
153 rpf_rss_key_wr_data_set(self
, key_data
);
154 rpf_rss_key_addr_set(self
, addr
);
155 rpf_rss_key_wr_en_set(self
, 1U);
156 AQ_HW_WAIT_FOR(rpf_rss_key_wr_en_get(self
) == 0, 1000U, 10U);
161 err
= aq_hw_err_from_flags(self
);
167 static int hw_atl_b0_hw_rss_set(struct aq_hw_s
*self
,
168 struct aq_rss_parameters
*rss_params
)
170 u8
*indirection_table
= rss_params
->indirection_table
;
172 u32 num_rss_queues
= max(1U, self
->aq_nic_cfg
->num_rss_queues
);
174 u16 bitary
[(HW_ATL_B0_RSS_REDIRECTION_MAX
*
175 HW_ATL_B0_RSS_REDIRECTION_BITS
/ 16U)];
177 memset(bitary
, 0, sizeof(bitary
));
179 for (i
= HW_ATL_B0_RSS_REDIRECTION_MAX
; i
--;) {
180 (*(u32
*)(bitary
+ ((i
* 3U) / 16U))) |=
181 ((indirection_table
[i
] % num_rss_queues
) <<
185 for (i
= AQ_DIMOF(bitary
); i
--;) {
186 rpf_rss_redir_tbl_wr_data_set(self
, bitary
[i
]);
187 rpf_rss_redir_tbl_addr_set(self
, i
);
188 rpf_rss_redir_wr_en_set(self
, 1U);
189 AQ_HW_WAIT_FOR(rpf_rss_redir_wr_en_get(self
) == 0, 1000U, 10U);
194 err
= aq_hw_err_from_flags(self
);
200 static int hw_atl_b0_hw_offload_set(struct aq_hw_s
*self
,
201 struct aq_nic_cfg_s
*aq_nic_cfg
)
206 /* TX checksums offloads*/
207 tpo_ipv4header_crc_offload_en_set(self
, 1);
208 tpo_tcp_udp_crc_offload_en_set(self
, 1);
212 /* RX checksums offloads*/
213 rpo_ipv4header_crc_offload_en_set(self
, 1);
214 rpo_tcp_udp_crc_offload_en_set(self
, 1);
219 tdm_large_send_offload_en_set(self
, 0xFFFFFFFFU
);
225 unsigned int val
= (8U < HW_ATL_B0_LRO_RXD_MAX
) ? 0x3U
:
226 ((4U < HW_ATL_B0_LRO_RXD_MAX
) ? 0x2U
:
227 ((2U < HW_ATL_B0_LRO_RXD_MAX
) ? 0x1U
: 0x0));
229 for (i
= 0; i
< HW_ATL_B0_RINGS_MAX
; i
++)
230 rpo_lro_max_num_of_descriptors_set(self
, val
, i
);
232 rpo_lro_time_base_divider_set(self
, 0x61AU
);
233 rpo_lro_inactive_interval_set(self
, 0);
234 rpo_lro_max_coalescing_interval_set(self
, 2);
236 rpo_lro_qsessions_lim_set(self
, 1U);
238 rpo_lro_total_desc_lim_set(self
, 2U);
240 rpo_lro_patch_optimization_en_set(self
, 0U);
242 rpo_lro_min_pay_of_first_pkt_set(self
, 10U);
244 rpo_lro_pkt_lim_set(self
, 1U);
246 rpo_lro_en_set(self
, aq_nic_cfg
->is_lro
? 0xFFFFFFFFU
: 0U);
248 err
= aq_hw_err_from_flags(self
);
254 static int hw_atl_b0_hw_init_tx_path(struct aq_hw_s
*self
)
256 thm_lso_tcp_flag_of_first_pkt_set(self
, 0x0FF6U
);
257 thm_lso_tcp_flag_of_middle_pkt_set(self
, 0x0FF6U
);
258 thm_lso_tcp_flag_of_last_pkt_set(self
, 0x0F7FU
);
261 tdm_tx_desc_wr_wb_irq_en_set(self
, 1U);
264 aq_hw_write_reg(self
, 0x00007040U
, IS_CHIP_FEATURE(TPO2
) ?
265 0x00010000U
: 0x00000000U
);
266 tdm_tx_dca_en_set(self
, 0U);
267 tdm_tx_dca_mode_set(self
, 0U);
269 tpb_tx_path_scp_ins_en_set(self
, 1U);
271 return aq_hw_err_from_flags(self
);
274 static int hw_atl_b0_hw_init_rx_path(struct aq_hw_s
*self
)
276 struct aq_nic_cfg_s
*cfg
= self
->aq_nic_cfg
;
279 /* Rx TC/RSS number config */
280 rpb_rpf_rx_traf_class_mode_set(self
, 1U);
282 /* Rx flow control */
283 rpb_rx_flow_ctl_mode_set(self
, 1U);
285 /* RSS Ring selection */
286 reg_rx_flr_rss_control1set(self
, cfg
->is_rss
?
287 0xB3333333U
: 0x00000000U
);
289 /* Multicast filters */
290 for (i
= HW_ATL_B0_MAC_MAX
; i
--;) {
291 rpfl2_uc_flr_en_set(self
, (i
== 0U) ? 1U : 0U, i
);
292 rpfl2unicast_flr_act_set(self
, 1U, i
);
295 reg_rx_flr_mcst_flr_msk_set(self
, 0x00000000U
);
296 reg_rx_flr_mcst_flr_set(self
, 0x00010FFFU
, 0U);
299 rpf_vlan_outer_etht_set(self
, 0x88A8U
);
300 rpf_vlan_inner_etht_set(self
, 0x8100U
);
303 rpf_vlan_flr_act_set(self
, 1U, 0U);
304 rpf_vlan_id_flr_set(self
, 0U, 0U);
305 rpf_vlan_flr_en_set(self
, 0U, 0U);
307 rpf_vlan_accept_untagged_packets_set(self
, 1U);
308 rpf_vlan_untagged_act_set(self
, 1U);
310 rpf_vlan_flr_act_set(self
, 1U, 1U);
311 rpf_vlan_id_flr_set(self
, cfg
->vlan_id
, 0U);
312 rpf_vlan_flr_en_set(self
, 1U, 1U);
314 rpf_vlan_prom_mode_en_set(self
, 1);
318 rdm_rx_desc_wr_wb_irq_en_set(self
, 1U);
321 aq_hw_write_reg(self
, 0x00005040U
,
322 IS_CHIP_FEATURE(RPF2
) ? 0x000F0000U
: 0x00000000U
);
324 rpfl2broadcast_flr_act_set(self
, 1U);
325 rpfl2broadcast_count_threshold_set(self
, 0xFFFFU
& (~0U / 256U));
327 rdm_rx_dca_en_set(self
, 0U);
328 rdm_rx_dca_mode_set(self
, 0U);
330 return aq_hw_err_from_flags(self
);
333 static int hw_atl_b0_hw_mac_addr_set(struct aq_hw_s
*self
, u8
*mac_addr
)
343 h
= (mac_addr
[0] << 8) | (mac_addr
[1]);
344 l
= (mac_addr
[2] << 24) | (mac_addr
[3] << 16) |
345 (mac_addr
[4] << 8) | mac_addr
[5];
347 rpfl2_uc_flr_en_set(self
, 0U, HW_ATL_B0_MAC
);
348 rpfl2unicast_dest_addresslsw_set(self
, l
, HW_ATL_B0_MAC
);
349 rpfl2unicast_dest_addressmsw_set(self
, h
, HW_ATL_B0_MAC
);
350 rpfl2_uc_flr_en_set(self
, 1U, HW_ATL_B0_MAC
);
352 err
= aq_hw_err_from_flags(self
);
358 static int hw_atl_b0_hw_init(struct aq_hw_s
*self
,
359 struct aq_nic_cfg_s
*aq_nic_cfg
,
362 static u32 aq_hw_atl_igcr_table_
[4][2] = {
363 { 0x20000000U
, 0x20000000U
}, /* AQ_IRQ_INVALID */
364 { 0x20000080U
, 0x20000080U
}, /* AQ_IRQ_LEGACY */
365 { 0x20000021U
, 0x20000025U
}, /* AQ_IRQ_MSI */
366 { 0x20000022U
, 0x20000026U
} /* AQ_IRQ_MSIX */
371 self
->aq_nic_cfg
= aq_nic_cfg
;
373 hw_atl_utils_hw_chip_features_init(self
,
374 &PHAL_ATLANTIC_B0
->chip_features
);
376 hw_atl_b0_hw_init_tx_path(self
);
377 hw_atl_b0_hw_init_rx_path(self
);
379 hw_atl_b0_hw_mac_addr_set(self
, mac_addr
);
381 hw_atl_utils_mpi_set(self
, MPI_INIT
, aq_nic_cfg
->link_speed_msk
);
383 hw_atl_b0_hw_qos_set(self
);
384 hw_atl_b0_hw_rss_set(self
, &aq_nic_cfg
->aq_rss
);
385 hw_atl_b0_hw_rss_hash_set(self
, &aq_nic_cfg
->aq_rss
);
387 err
= aq_hw_err_from_flags(self
);
392 reg_irq_glb_ctl_set(self
,
393 aq_hw_atl_igcr_table_
[aq_nic_cfg
->irq_type
]
394 [(aq_nic_cfg
->vecs
> 1U) ?
397 itr_irq_auto_masklsw_set(self
, aq_nic_cfg
->aq_hw_caps
->irq_mask
);
400 reg_gen_irq_map_set(self
,
401 ((HW_ATL_B0_ERR_INT
<< 0x18) | (1U << 0x1F)) |
402 ((HW_ATL_B0_ERR_INT
<< 0x10) | (1U << 0x17)), 0U);
404 hw_atl_b0_hw_offload_set(self
, aq_nic_cfg
);
410 static int hw_atl_b0_hw_ring_tx_start(struct aq_hw_s
*self
,
411 struct aq_ring_s
*ring
)
413 tdm_tx_desc_en_set(self
, 1, ring
->idx
);
414 return aq_hw_err_from_flags(self
);
417 static int hw_atl_b0_hw_ring_rx_start(struct aq_hw_s
*self
,
418 struct aq_ring_s
*ring
)
420 rdm_rx_desc_en_set(self
, 1, ring
->idx
);
421 return aq_hw_err_from_flags(self
);
424 static int hw_atl_b0_hw_start(struct aq_hw_s
*self
)
426 tpb_tx_buff_en_set(self
, 1);
427 rpb_rx_buff_en_set(self
, 1);
428 return aq_hw_err_from_flags(self
);
431 static int hw_atl_b0_hw_tx_ring_tail_update(struct aq_hw_s
*self
,
432 struct aq_ring_s
*ring
)
434 reg_tx_dma_desc_tail_ptr_set(self
, ring
->sw_tail
, ring
->idx
);
438 static int hw_atl_b0_hw_ring_tx_xmit(struct aq_hw_s
*self
,
439 struct aq_ring_s
*ring
,
442 struct aq_ring_buff_s
*buff
= NULL
;
443 struct hw_atl_txd_s
*txd
= NULL
;
444 unsigned int buff_pa_len
= 0U;
445 unsigned int pkt_len
= 0U;
446 unsigned int frag_count
= 0U;
449 buff
= &ring
->buff_ring
[ring
->sw_tail
];
450 pkt_len
= (buff
->is_eop
&& buff
->is_sop
) ? buff
->len
: buff
->len_pkt
;
452 for (frag_count
= 0; frag_count
< frags
; frag_count
++) {
453 txd
= (struct hw_atl_txd_s
*)&ring
->dx_ring
[ring
->sw_tail
*
459 buff
= &ring
->buff_ring
[ring
->sw_tail
];
462 txd
->ctl
|= (buff
->len_l3
<< 31) |
463 (buff
->len_l2
<< 24) |
464 HW_ATL_B0_TXD_CTL_CMD_TCP
|
465 HW_ATL_B0_TXD_CTL_DESC_TYPE_TXC
;
466 txd
->ctl2
|= (buff
->mss
<< 16) |
467 (buff
->len_l4
<< 8) |
470 pkt_len
-= (buff
->len_l4
+
476 txd
->ctl
|= HW_ATL_B0_TXD_CTL_CMD_IPV6
;
478 buff_pa_len
= buff
->len
;
480 txd
->buf_addr
= buff
->pa
;
481 txd
->ctl
|= (HW_ATL_B0_TXD_CTL_BLEN
&
482 ((u32
)buff_pa_len
<< 4));
483 txd
->ctl
|= HW_ATL_B0_TXD_CTL_DESC_TYPE_TXD
;
485 txd
->ctl2
|= HW_ATL_B0_TXD_CTL2_LEN
& (pkt_len
<< 14);
488 txd
->ctl
|= HW_ATL_B0_TXD_CTL_CMD_LSO
;
489 txd
->ctl2
|= HW_ATL_B0_TXD_CTL2_CTX_EN
;
492 /* Tx checksum offloads */
494 txd
->ctl
|= HW_ATL_B0_TXD_CTL_CMD_IPCSO
;
496 if (buff
->is_udp_cso
|| buff
->is_tcp_cso
)
497 txd
->ctl
|= HW_ATL_B0_TXD_CTL_CMD_TUCSO
;
499 if (unlikely(buff
->is_eop
)) {
500 txd
->ctl
|= HW_ATL_B0_TXD_CTL_EOP
;
501 txd
->ctl
|= HW_ATL_B0_TXD_CTL_CMD_WB
;
506 ring
->sw_tail
= aq_ring_next_dx(ring
, ring
->sw_tail
);
509 hw_atl_b0_hw_tx_ring_tail_update(self
, ring
);
510 return aq_hw_err_from_flags(self
);
513 static int hw_atl_b0_hw_ring_rx_init(struct aq_hw_s
*self
,
514 struct aq_ring_s
*aq_ring
,
515 struct aq_ring_param_s
*aq_ring_param
)
517 u32 dma_desc_addr_lsw
= (u32
)aq_ring
->dx_ring_pa
;
518 u32 dma_desc_addr_msw
= (u32
)(((u64
)aq_ring
->dx_ring_pa
) >> 32);
520 rdm_rx_desc_en_set(self
, false, aq_ring
->idx
);
522 rdm_rx_desc_head_splitting_set(self
, 0U, aq_ring
->idx
);
524 reg_rx_dma_desc_base_addresslswset(self
, dma_desc_addr_lsw
,
527 reg_rx_dma_desc_base_addressmswset(self
,
528 dma_desc_addr_msw
, aq_ring
->idx
);
530 rdm_rx_desc_len_set(self
, aq_ring
->size
/ 8U, aq_ring
->idx
);
532 rdm_rx_desc_data_buff_size_set(self
,
533 AQ_CFG_RX_FRAME_MAX
/ 1024U,
536 rdm_rx_desc_head_buff_size_set(self
, 0U, aq_ring
->idx
);
537 rdm_rx_desc_head_splitting_set(self
, 0U, aq_ring
->idx
);
538 rpo_rx_desc_vlan_stripping_set(self
, 0U, aq_ring
->idx
);
540 /* Rx ring set mode */
542 /* Mapping interrupt vector */
543 itr_irq_map_rx_set(self
, aq_ring_param
->vec_idx
, aq_ring
->idx
);
544 itr_irq_map_en_rx_set(self
, true, aq_ring
->idx
);
546 rdm_cpu_id_set(self
, aq_ring_param
->cpu
, aq_ring
->idx
);
547 rdm_rx_desc_dca_en_set(self
, 0U, aq_ring
->idx
);
548 rdm_rx_head_dca_en_set(self
, 0U, aq_ring
->idx
);
549 rdm_rx_pld_dca_en_set(self
, 0U, aq_ring
->idx
);
551 return aq_hw_err_from_flags(self
);
554 static int hw_atl_b0_hw_ring_tx_init(struct aq_hw_s
*self
,
555 struct aq_ring_s
*aq_ring
,
556 struct aq_ring_param_s
*aq_ring_param
)
558 u32 dma_desc_lsw_addr
= (u32
)aq_ring
->dx_ring_pa
;
559 u32 dma_desc_msw_addr
= (u32
)(((u64
)aq_ring
->dx_ring_pa
) >> 32);
561 reg_tx_dma_desc_base_addresslswset(self
, dma_desc_lsw_addr
,
564 reg_tx_dma_desc_base_addressmswset(self
, dma_desc_msw_addr
,
567 tdm_tx_desc_len_set(self
, aq_ring
->size
/ 8U, aq_ring
->idx
);
569 hw_atl_b0_hw_tx_ring_tail_update(self
, aq_ring
);
571 /* Set Tx threshold */
572 tdm_tx_desc_wr_wb_threshold_set(self
, 0U, aq_ring
->idx
);
574 /* Mapping interrupt vector */
575 itr_irq_map_tx_set(self
, aq_ring_param
->vec_idx
, aq_ring
->idx
);
576 itr_irq_map_en_tx_set(self
, true, aq_ring
->idx
);
578 tdm_cpu_id_set(self
, aq_ring_param
->cpu
, aq_ring
->idx
);
579 tdm_tx_desc_dca_en_set(self
, 0U, aq_ring
->idx
);
581 return aq_hw_err_from_flags(self
);
584 static int hw_atl_b0_hw_ring_rx_fill(struct aq_hw_s
*self
,
585 struct aq_ring_s
*ring
,
586 unsigned int sw_tail_old
)
588 for (; sw_tail_old
!= ring
->sw_tail
;
589 sw_tail_old
= aq_ring_next_dx(ring
, sw_tail_old
)) {
590 struct hw_atl_rxd_s
*rxd
=
591 (struct hw_atl_rxd_s
*)&ring
->dx_ring
[sw_tail_old
*
594 struct aq_ring_buff_s
*buff
= &ring
->buff_ring
[sw_tail_old
];
596 rxd
->buf_addr
= buff
->pa
;
600 reg_rx_dma_desc_tail_ptr_set(self
, sw_tail_old
, ring
->idx
);
602 return aq_hw_err_from_flags(self
);
605 static int hw_atl_b0_hw_ring_tx_head_update(struct aq_hw_s
*self
,
606 struct aq_ring_s
*ring
)
609 unsigned int hw_head_
= tdm_tx_desc_head_ptr_get(self
, ring
->idx
);
611 if (aq_utils_obj_test(&self
->header
.flags
, AQ_HW_FLAG_ERR_UNPLUG
)) {
615 ring
->hw_head
= hw_head_
;
616 err
= aq_hw_err_from_flags(self
);
622 static int hw_atl_b0_hw_ring_rx_receive(struct aq_hw_s
*self
,
623 struct aq_ring_s
*ring
)
625 struct device
*ndev
= aq_nic_get_dev(ring
->aq_nic
);
627 for (; ring
->hw_head
!= ring
->sw_tail
;
628 ring
->hw_head
= aq_ring_next_dx(ring
, ring
->hw_head
)) {
629 struct aq_ring_buff_s
*buff
= NULL
;
630 struct hw_atl_rxd_wb_s
*rxd_wb
= (struct hw_atl_rxd_wb_s
*)
631 &ring
->dx_ring
[ring
->hw_head
* HW_ATL_B0_RXD_SIZE
];
633 unsigned int is_err
= 1U;
634 unsigned int is_rx_check_sum_enabled
= 0U;
635 unsigned int pkt_type
= 0U;
637 if (!(rxd_wb
->status
& 0x1U
)) { /* RxD is not done */
641 buff
= &ring
->buff_ring
[ring
->hw_head
];
643 is_err
= (0x0000003CU
& rxd_wb
->status
);
645 is_rx_check_sum_enabled
= (rxd_wb
->type
) & (0x3U
<< 19);
646 is_err
&= ~0x20U
; /* exclude validity bit */
648 pkt_type
= 0xFFU
& (rxd_wb
->type
>> 4);
650 if (is_rx_check_sum_enabled
) {
651 if (0x0U
== (pkt_type
& 0x3U
))
652 buff
->is_ip_cso
= (is_err
& 0x08U
) ? 0U : 1U;
654 if (0x4U
== (pkt_type
& 0x1CU
))
655 buff
->is_udp_cso
= buff
->is_cso_err
? 0U : 1U;
656 else if (0x0U
== (pkt_type
& 0x1CU
))
657 buff
->is_tcp_cso
= buff
->is_cso_err
? 0U : 1U;
662 dma_unmap_page(ndev
, buff
->pa
, buff
->len
, DMA_FROM_DEVICE
);
664 if (is_err
|| rxd_wb
->type
& 0x1000U
) {
665 /* status error or DMA error */
668 if (self
->aq_nic_cfg
->is_rss
) {
670 u16 rss_type
= rxd_wb
->type
& 0xFU
;
672 if (rss_type
&& rss_type
< 0x8U
) {
673 buff
->is_hash_l4
= (rss_type
== 0x4 ||
675 buff
->rss_hash
= rxd_wb
->rss_hash
;
679 if (HW_ATL_B0_RXD_WB_STAT2_EOP
& rxd_wb
->status
) {
680 buff
->len
= rxd_wb
->pkt_len
%
682 buff
->len
= buff
->len
?
683 buff
->len
: AQ_CFG_RX_FRAME_MAX
;
687 if (HW_ATL_B0_RXD_WB_STAT2_RSCCNT
&
690 buff
->next
= rxd_wb
->next_desc_ptr
;
691 ++ring
->stats
.rx
.lro_packets
;
695 aq_ring_next_dx(ring
,
697 ++ring
->stats
.rx
.jumbo_packets
;
703 return aq_hw_err_from_flags(self
);
706 static int hw_atl_b0_hw_irq_enable(struct aq_hw_s
*self
, u64 mask
)
708 itr_irq_msk_setlsw_set(self
, LODWORD(mask
));
709 return aq_hw_err_from_flags(self
);
712 static int hw_atl_b0_hw_irq_disable(struct aq_hw_s
*self
, u64 mask
)
714 itr_irq_msk_clearlsw_set(self
, LODWORD(mask
));
715 itr_irq_status_clearlsw_set(self
, LODWORD(mask
));
717 atomic_inc(&PHAL_ATLANTIC_B0
->dpc
);
718 return aq_hw_err_from_flags(self
);
721 static int hw_atl_b0_hw_irq_read(struct aq_hw_s
*self
, u64
*mask
)
723 *mask
= itr_irq_statuslsw_get(self
);
724 return aq_hw_err_from_flags(self
);
727 #define IS_FILTER_ENABLED(_F_) ((packet_filter & (_F_)) ? 1U : 0U)
729 static int hw_atl_b0_hw_packet_filter_set(struct aq_hw_s
*self
,
730 unsigned int packet_filter
)
734 rpfl2promiscuous_mode_en_set(self
, IS_FILTER_ENABLED(IFF_PROMISC
));
735 rpfl2multicast_flr_en_set(self
,
736 IS_FILTER_ENABLED(IFF_MULTICAST
), 0);
738 rpfl2_accept_all_mc_packets_set(self
,
739 IS_FILTER_ENABLED(IFF_ALLMULTI
));
741 rpfl2broadcast_en_set(self
, IS_FILTER_ENABLED(IFF_BROADCAST
));
743 self
->aq_nic_cfg
->is_mc_list_enabled
= IS_FILTER_ENABLED(IFF_MULTICAST
);
745 for (i
= HW_ATL_B0_MAC_MIN
; i
< HW_ATL_B0_MAC_MAX
; ++i
)
746 rpfl2_uc_flr_en_set(self
,
747 (self
->aq_nic_cfg
->is_mc_list_enabled
&&
748 (i
<= self
->aq_nic_cfg
->mc_list_count
)) ?
751 return aq_hw_err_from_flags(self
);
754 #undef IS_FILTER_ENABLED
756 static int hw_atl_b0_hw_multicast_list_set(struct aq_hw_s
*self
,
758 [AQ_CFG_MULTICAST_ADDRESS_MAX
]
764 if (count
> (HW_ATL_B0_MAC_MAX
- HW_ATL_B0_MAC_MIN
)) {
768 for (self
->aq_nic_cfg
->mc_list_count
= 0U;
769 self
->aq_nic_cfg
->mc_list_count
< count
;
770 ++self
->aq_nic_cfg
->mc_list_count
) {
771 u32 i
= self
->aq_nic_cfg
->mc_list_count
;
772 u32 h
= (ar_mac
[i
][0] << 8) | (ar_mac
[i
][1]);
773 u32 l
= (ar_mac
[i
][2] << 24) | (ar_mac
[i
][3] << 16) |
774 (ar_mac
[i
][4] << 8) | ar_mac
[i
][5];
776 rpfl2_uc_flr_en_set(self
, 0U, HW_ATL_B0_MAC_MIN
+ i
);
778 rpfl2unicast_dest_addresslsw_set(self
,
779 l
, HW_ATL_B0_MAC_MIN
+ i
);
781 rpfl2unicast_dest_addressmsw_set(self
,
782 h
, HW_ATL_B0_MAC_MIN
+ i
);
784 rpfl2_uc_flr_en_set(self
,
785 (self
->aq_nic_cfg
->is_mc_list_enabled
),
786 HW_ATL_B0_MAC_MIN
+ i
);
789 err
= aq_hw_err_from_flags(self
);
795 static int hw_atl_b0_hw_interrupt_moderation_set(struct aq_hw_s
*self
,
800 if (itr_enabled
&& self
->aq_nic_cfg
->itr
) {
801 tdm_tx_desc_wr_wb_irq_en_set(self
, 0U);
802 tdm_tdm_intr_moder_en_set(self
, 1U);
803 rdm_rx_desc_wr_wb_irq_en_set(self
, 0U);
804 rdm_rdm_intr_moder_en_set(self
, 1U);
806 PHAL_ATLANTIC_B0
->itr_tx
= 2U;
807 PHAL_ATLANTIC_B0
->itr_rx
= 2U;
809 if (self
->aq_nic_cfg
->itr
!= 0xFFFFU
) {
810 unsigned int max_timer
= self
->aq_nic_cfg
->itr
/ 2U;
811 unsigned int min_timer
= self
->aq_nic_cfg
->itr
/ 32U;
813 max_timer
= min(0x1FFU
, max_timer
);
814 min_timer
= min(0xFFU
, min_timer
);
816 PHAL_ATLANTIC_B0
->itr_tx
|= min_timer
<< 0x8U
;
817 PHAL_ATLANTIC_B0
->itr_tx
|= max_timer
<< 0x10U
;
818 PHAL_ATLANTIC_B0
->itr_rx
|= min_timer
<< 0x8U
;
819 PHAL_ATLANTIC_B0
->itr_rx
|= max_timer
<< 0x10U
;
821 static unsigned int hw_atl_b0_timers_table_tx_
[][2] = {
822 {0xffU
, 0xffU
}, /* 10Gbit */
823 {0xffU
, 0x1ffU
}, /* 5Gbit */
824 {0xffU
, 0x1ffU
}, /* 5Gbit 5GS */
825 {0xffU
, 0x1ffU
}, /* 2.5Gbit */
826 {0xffU
, 0x1ffU
}, /* 1Gbit */
827 {0xffU
, 0x1ffU
}, /* 100Mbit */
830 static unsigned int hw_atl_b0_timers_table_rx_
[][2] = {
831 {0x6U
, 0x38U
},/* 10Gbit */
832 {0xCU
, 0x70U
},/* 5Gbit */
833 {0xCU
, 0x70U
},/* 5Gbit 5GS */
834 {0x18U
, 0xE0U
},/* 2.5Gbit */
835 {0x30U
, 0x80U
},/* 1Gbit */
836 {0x4U
, 0x50U
},/* 100Mbit */
839 unsigned int speed_index
=
840 hw_atl_utils_mbps_2_speed_index(
841 self
->aq_link_status
.mbps
);
843 PHAL_ATLANTIC_B0
->itr_tx
|=
844 hw_atl_b0_timers_table_tx_
[speed_index
]
845 [0] << 0x8U
; /* set min timer value */
846 PHAL_ATLANTIC_B0
->itr_tx
|=
847 hw_atl_b0_timers_table_tx_
[speed_index
]
848 [1] << 0x10U
; /* set max timer value */
850 PHAL_ATLANTIC_B0
->itr_rx
|=
851 hw_atl_b0_timers_table_rx_
[speed_index
]
852 [0] << 0x8U
; /* set min timer value */
853 PHAL_ATLANTIC_B0
->itr_rx
|=
854 hw_atl_b0_timers_table_rx_
[speed_index
]
855 [1] << 0x10U
; /* set max timer value */
858 tdm_tx_desc_wr_wb_irq_en_set(self
, 1U);
859 tdm_tdm_intr_moder_en_set(self
, 0U);
860 rdm_rx_desc_wr_wb_irq_en_set(self
, 1U);
861 rdm_rdm_intr_moder_en_set(self
, 0U);
862 PHAL_ATLANTIC_B0
->itr_tx
= 0U;
863 PHAL_ATLANTIC_B0
->itr_rx
= 0U;
866 for (i
= HW_ATL_B0_RINGS_MAX
; i
--;) {
867 reg_tx_intr_moder_ctrl_set(self
,
868 PHAL_ATLANTIC_B0
->itr_tx
, i
);
869 reg_rx_intr_moder_ctrl_set(self
,
870 PHAL_ATLANTIC_B0
->itr_rx
, i
);
873 return aq_hw_err_from_flags(self
);
876 static int hw_atl_b0_hw_stop(struct aq_hw_s
*self
)
878 hw_atl_b0_hw_irq_disable(self
, HW_ATL_B0_INT_MASK
);
879 return aq_hw_err_from_flags(self
);
882 static int hw_atl_b0_hw_ring_tx_stop(struct aq_hw_s
*self
,
883 struct aq_ring_s
*ring
)
885 tdm_tx_desc_en_set(self
, 0U, ring
->idx
);
886 return aq_hw_err_from_flags(self
);
889 static int hw_atl_b0_hw_ring_rx_stop(struct aq_hw_s
*self
,
890 struct aq_ring_s
*ring
)
892 rdm_rx_desc_en_set(self
, 0U, ring
->idx
);
893 return aq_hw_err_from_flags(self
);
896 static int hw_atl_b0_hw_set_speed(struct aq_hw_s
*self
, u32 speed
)
900 err
= hw_atl_utils_mpi_set_speed(self
, speed
, MPI_INIT
);
908 static struct aq_hw_ops hw_atl_ops_
= {
909 .create
= hw_atl_b0_create
,
910 .destroy
= hw_atl_b0_destroy
,
911 .get_hw_caps
= hw_atl_b0_get_hw_caps
,
913 .hw_get_mac_permanent
= hw_atl_utils_get_mac_permanent
,
914 .hw_set_mac_address
= hw_atl_b0_hw_mac_addr_set
,
915 .hw_get_link_status
= hw_atl_utils_mpi_get_link_status
,
916 .hw_set_link_speed
= hw_atl_b0_hw_set_speed
,
917 .hw_init
= hw_atl_b0_hw_init
,
918 .hw_deinit
= hw_atl_utils_hw_deinit
,
919 .hw_set_power
= hw_atl_utils_hw_set_power
,
920 .hw_reset
= hw_atl_b0_hw_reset
,
921 .hw_start
= hw_atl_b0_hw_start
,
922 .hw_ring_tx_start
= hw_atl_b0_hw_ring_tx_start
,
923 .hw_ring_tx_stop
= hw_atl_b0_hw_ring_tx_stop
,
924 .hw_ring_rx_start
= hw_atl_b0_hw_ring_rx_start
,
925 .hw_ring_rx_stop
= hw_atl_b0_hw_ring_rx_stop
,
926 .hw_stop
= hw_atl_b0_hw_stop
,
928 .hw_ring_tx_xmit
= hw_atl_b0_hw_ring_tx_xmit
,
929 .hw_ring_tx_head_update
= hw_atl_b0_hw_ring_tx_head_update
,
931 .hw_ring_rx_receive
= hw_atl_b0_hw_ring_rx_receive
,
932 .hw_ring_rx_fill
= hw_atl_b0_hw_ring_rx_fill
,
934 .hw_irq_enable
= hw_atl_b0_hw_irq_enable
,
935 .hw_irq_disable
= hw_atl_b0_hw_irq_disable
,
936 .hw_irq_read
= hw_atl_b0_hw_irq_read
,
938 .hw_ring_rx_init
= hw_atl_b0_hw_ring_rx_init
,
939 .hw_ring_tx_init
= hw_atl_b0_hw_ring_tx_init
,
940 .hw_packet_filter_set
= hw_atl_b0_hw_packet_filter_set
,
941 .hw_multicast_list_set
= hw_atl_b0_hw_multicast_list_set
,
942 .hw_interrupt_moderation_set
= hw_atl_b0_hw_interrupt_moderation_set
,
943 .hw_rss_set
= hw_atl_b0_hw_rss_set
,
944 .hw_rss_hash_set
= hw_atl_b0_hw_rss_hash_set
,
945 .hw_get_regs
= hw_atl_utils_hw_get_regs
,
946 .hw_get_hw_stats
= hw_atl_utils_get_hw_stats
,
947 .hw_get_fw_version
= hw_atl_utils_get_fw_version
,
950 struct aq_hw_ops
*hw_atl_b0_get_ops_by_id(struct pci_dev
*pdev
)
952 bool is_vid_ok
= (pdev
->vendor
== PCI_VENDOR_ID_AQUANTIA
);
953 bool is_did_ok
= ((pdev
->device
== HW_ATL_DEVICE_ID_0001
) ||
954 (pdev
->device
== HW_ATL_DEVICE_ID_D100
) ||
955 (pdev
->device
== HW_ATL_DEVICE_ID_D107
) ||
956 (pdev
->device
== HW_ATL_DEVICE_ID_D108
) ||
957 (pdev
->device
== HW_ATL_DEVICE_ID_D109
));
959 bool is_rev_ok
= (pdev
->revision
== 2U);
961 return (is_vid_ok
&& is_did_ok
&& is_rev_ok
) ? &hw_atl_ops_
: NULL
;