2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
10 /* File hw_atl_b0.c: Definition of Atlantic hardware specific functions. */
13 #include "../aq_hw_utils.h"
14 #include "../aq_ring.h"
15 #include "hw_atl_b0.h"
16 #include "hw_atl_utils.h"
17 #include "hw_atl_llh.h"
18 #include "hw_atl_b0_internal.h"
20 static int hw_atl_b0_get_hw_caps(struct aq_hw_s
*self
,
21 struct aq_hw_caps_s
*aq_hw_caps
,
22 unsigned short device
,
23 unsigned short subsystem_device
)
25 memcpy(aq_hw_caps
, &hw_atl_b0_hw_caps_
, sizeof(*aq_hw_caps
));
27 if (device
== HW_ATL_DEVICE_ID_D108
&& subsystem_device
== 0x0001)
28 aq_hw_caps
->link_speed_msk
&= ~HW_ATL_B0_RATE_10G
;
30 if (device
== HW_ATL_DEVICE_ID_D109
&& subsystem_device
== 0x0001) {
31 aq_hw_caps
->link_speed_msk
&= ~HW_ATL_B0_RATE_10G
;
32 aq_hw_caps
->link_speed_msk
&= ~HW_ATL_B0_RATE_5G
;
38 static struct aq_hw_s
*hw_atl_b0_create(struct aq_pci_func_s
*aq_pci_func
,
40 struct aq_hw_ops
*ops
)
42 struct hw_atl_s
*self
= NULL
;
44 self
= kzalloc(sizeof(*self
), GFP_KERNEL
);
48 self
->base
.aq_pci_func
= aq_pci_func
;
50 self
->base
.not_ff_addr
= 0x10U
;
53 return (struct aq_hw_s
*)self
;
56 static void hw_atl_b0_destroy(struct aq_hw_s
*self
)
61 static int hw_atl_b0_hw_reset(struct aq_hw_s
*self
)
65 glb_glb_reg_res_dis_set(self
, 1U);
66 pci_pci_reg_res_dis_set(self
, 0U);
67 rx_rx_reg_res_dis_set(self
, 0U);
68 tx_tx_reg_res_dis_set(self
, 0U);
71 glb_soft_res_set(self
, 1);
73 /* check 10 times by 1ms */
74 AQ_HW_WAIT_FOR(glb_soft_res_get(self
) == 0, 1000U, 10U);
78 itr_irq_reg_res_dis_set(self
, 0U);
79 itr_res_irq_set(self
, 1U);
81 /* check 10 times by 1ms */
82 AQ_HW_WAIT_FOR(itr_res_irq_get(self
) == 0, 1000U, 10U);
86 hw_atl_utils_mpi_set(self
, MPI_RESET
, 0x0U
);
88 err
= aq_hw_err_from_flags(self
);
94 static int hw_atl_b0_hw_qos_set(struct aq_hw_s
*self
)
98 unsigned int i_priority
= 0U;
99 bool is_rx_flow_control
= false;
101 /* TPS Descriptor rate init */
102 tps_tx_pkt_shed_desc_rate_curr_time_res_set(self
, 0x0U
);
103 tps_tx_pkt_shed_desc_rate_lim_set(self
, 0xA);
106 tps_tx_pkt_shed_desc_vm_arb_mode_set(self
, 0U);
108 /* TPS TC credits init */
109 tps_tx_pkt_shed_desc_tc_arb_mode_set(self
, 0U);
110 tps_tx_pkt_shed_data_arb_mode_set(self
, 0U);
112 tps_tx_pkt_shed_tc_data_max_credit_set(self
, 0xFFF, 0U);
113 tps_tx_pkt_shed_tc_data_weight_set(self
, 0x64, 0U);
114 tps_tx_pkt_shed_desc_tc_max_credit_set(self
, 0x50, 0U);
115 tps_tx_pkt_shed_desc_tc_weight_set(self
, 0x1E, 0U);
118 buff_size
= HW_ATL_B0_TXBUF_MAX
;
120 tpb_tx_pkt_buff_size_per_tc_set(self
, buff_size
, tc
);
121 tpb_tx_buff_hi_threshold_per_tc_set(self
,
122 (buff_size
* (1024 / 32U) * 66U) /
124 tpb_tx_buff_lo_threshold_per_tc_set(self
,
125 (buff_size
* (1024 / 32U) * 50U) /
128 /* QoS Rx buf size per TC */
130 is_rx_flow_control
= (AQ_NIC_FC_RX
& self
->aq_nic_cfg
->flow_control
);
131 buff_size
= HW_ATL_B0_RXBUF_MAX
;
133 rpb_rx_pkt_buff_size_per_tc_set(self
, buff_size
, tc
);
134 rpb_rx_buff_hi_threshold_per_tc_set(self
,
136 (1024U / 32U) * 66U) /
138 rpb_rx_buff_lo_threshold_per_tc_set(self
,
140 (1024U / 32U) * 50U) /
142 rpb_rx_xoff_en_per_tc_set(self
, is_rx_flow_control
? 1U : 0U, tc
);
144 /* QoS 802.1p priority -> TC mapping */
145 for (i_priority
= 8U; i_priority
--;)
146 rpf_rpb_user_priority_tc_map_set(self
, i_priority
, 0U);
148 return aq_hw_err_from_flags(self
);
151 static int hw_atl_b0_hw_rss_hash_set(struct aq_hw_s
*self
,
152 struct aq_rss_parameters
*rss_params
)
154 struct aq_nic_cfg_s
*cfg
= NULL
;
157 unsigned int addr
= 0U;
159 cfg
= self
->aq_nic_cfg
;
161 for (i
= 10, addr
= 0U; i
--; ++addr
) {
162 u32 key_data
= cfg
->is_rss
?
163 __swab32(rss_params
->hash_secret_key
[i
]) : 0U;
164 rpf_rss_key_wr_data_set(self
, key_data
);
165 rpf_rss_key_addr_set(self
, addr
);
166 rpf_rss_key_wr_en_set(self
, 1U);
167 AQ_HW_WAIT_FOR(rpf_rss_key_wr_en_get(self
) == 0, 1000U, 10U);
172 err
= aq_hw_err_from_flags(self
);
178 static int hw_atl_b0_hw_rss_set(struct aq_hw_s
*self
,
179 struct aq_rss_parameters
*rss_params
)
181 u8
*indirection_table
= rss_params
->indirection_table
;
183 u32 num_rss_queues
= max(1U, self
->aq_nic_cfg
->num_rss_queues
);
185 u16 bitary
[(HW_ATL_B0_RSS_REDIRECTION_MAX
*
186 HW_ATL_B0_RSS_REDIRECTION_BITS
/ 16U)];
188 memset(bitary
, 0, sizeof(bitary
));
190 for (i
= HW_ATL_B0_RSS_REDIRECTION_MAX
; i
--;) {
191 (*(u32
*)(bitary
+ ((i
* 3U) / 16U))) |=
192 ((indirection_table
[i
] % num_rss_queues
) <<
196 for (i
= AQ_DIMOF(bitary
); i
--;) {
197 rpf_rss_redir_tbl_wr_data_set(self
, bitary
[i
]);
198 rpf_rss_redir_tbl_addr_set(self
, i
);
199 rpf_rss_redir_wr_en_set(self
, 1U);
200 AQ_HW_WAIT_FOR(rpf_rss_redir_wr_en_get(self
) == 0, 1000U, 10U);
205 err
= aq_hw_err_from_flags(self
);
211 static int hw_atl_b0_hw_offload_set(struct aq_hw_s
*self
,
212 struct aq_nic_cfg_s
*aq_nic_cfg
)
216 /* TX checksums offloads*/
217 tpo_ipv4header_crc_offload_en_set(self
, 1);
218 tpo_tcp_udp_crc_offload_en_set(self
, 1);
220 /* RX checksums offloads*/
221 rpo_ipv4header_crc_offload_en_set(self
, 1);
222 rpo_tcp_udp_crc_offload_en_set(self
, 1);
225 tdm_large_send_offload_en_set(self
, 0xFFFFFFFFU
);
229 unsigned int val
= (8U < HW_ATL_B0_LRO_RXD_MAX
) ? 0x3U
:
230 ((4U < HW_ATL_B0_LRO_RXD_MAX
) ? 0x2U
:
231 ((2U < HW_ATL_B0_LRO_RXD_MAX
) ? 0x1U
: 0x0));
233 for (i
= 0; i
< HW_ATL_B0_RINGS_MAX
; i
++)
234 rpo_lro_max_num_of_descriptors_set(self
, val
, i
);
236 rpo_lro_time_base_divider_set(self
, 0x61AU
);
237 rpo_lro_inactive_interval_set(self
, 0);
238 rpo_lro_max_coalescing_interval_set(self
, 2);
240 rpo_lro_qsessions_lim_set(self
, 1U);
242 rpo_lro_total_desc_lim_set(self
, 2U);
244 rpo_lro_patch_optimization_en_set(self
, 0U);
246 rpo_lro_min_pay_of_first_pkt_set(self
, 10U);
248 rpo_lro_pkt_lim_set(self
, 1U);
250 rpo_lro_en_set(self
, aq_nic_cfg
->is_lro
? 0xFFFFFFFFU
: 0U);
252 return aq_hw_err_from_flags(self
);
255 static int hw_atl_b0_hw_init_tx_path(struct aq_hw_s
*self
)
257 thm_lso_tcp_flag_of_first_pkt_set(self
, 0x0FF6U
);
258 thm_lso_tcp_flag_of_middle_pkt_set(self
, 0x0FF6U
);
259 thm_lso_tcp_flag_of_last_pkt_set(self
, 0x0F7FU
);
262 tdm_tx_desc_wr_wb_irq_en_set(self
, 1U);
265 aq_hw_write_reg(self
, 0x00007040U
, IS_CHIP_FEATURE(TPO2
) ?
266 0x00010000U
: 0x00000000U
);
267 tdm_tx_dca_en_set(self
, 0U);
268 tdm_tx_dca_mode_set(self
, 0U);
270 tpb_tx_path_scp_ins_en_set(self
, 1U);
272 return aq_hw_err_from_flags(self
);
275 static int hw_atl_b0_hw_init_rx_path(struct aq_hw_s
*self
)
277 struct aq_nic_cfg_s
*cfg
= self
->aq_nic_cfg
;
280 /* Rx TC/RSS number config */
281 rpb_rpf_rx_traf_class_mode_set(self
, 1U);
283 /* Rx flow control */
284 rpb_rx_flow_ctl_mode_set(self
, 1U);
286 /* RSS Ring selection */
287 reg_rx_flr_rss_control1set(self
, cfg
->is_rss
?
288 0xB3333333U
: 0x00000000U
);
290 /* Multicast filters */
291 for (i
= HW_ATL_B0_MAC_MAX
; i
--;) {
292 rpfl2_uc_flr_en_set(self
, (i
== 0U) ? 1U : 0U, i
);
293 rpfl2unicast_flr_act_set(self
, 1U, i
);
296 reg_rx_flr_mcst_flr_msk_set(self
, 0x00000000U
);
297 reg_rx_flr_mcst_flr_set(self
, 0x00010FFFU
, 0U);
300 rpf_vlan_outer_etht_set(self
, 0x88A8U
);
301 rpf_vlan_inner_etht_set(self
, 0x8100U
);
304 rpf_vlan_flr_act_set(self
, 1U, 0U);
305 rpf_vlan_id_flr_set(self
, 0U, 0U);
306 rpf_vlan_flr_en_set(self
, 0U, 0U);
308 rpf_vlan_accept_untagged_packets_set(self
, 1U);
309 rpf_vlan_untagged_act_set(self
, 1U);
311 rpf_vlan_flr_act_set(self
, 1U, 1U);
312 rpf_vlan_id_flr_set(self
, cfg
->vlan_id
, 0U);
313 rpf_vlan_flr_en_set(self
, 1U, 1U);
315 rpf_vlan_prom_mode_en_set(self
, 1);
319 rdm_rx_desc_wr_wb_irq_en_set(self
, 1U);
322 aq_hw_write_reg(self
, 0x00005040U
,
323 IS_CHIP_FEATURE(RPF2
) ? 0x000F0000U
: 0x00000000U
);
325 rpfl2broadcast_flr_act_set(self
, 1U);
326 rpfl2broadcast_count_threshold_set(self
, 0xFFFFU
& (~0U / 256U));
328 rdm_rx_dca_en_set(self
, 0U);
329 rdm_rx_dca_mode_set(self
, 0U);
331 return aq_hw_err_from_flags(self
);
334 static int hw_atl_b0_hw_mac_addr_set(struct aq_hw_s
*self
, u8
*mac_addr
)
344 h
= (mac_addr
[0] << 8) | (mac_addr
[1]);
345 l
= (mac_addr
[2] << 24) | (mac_addr
[3] << 16) |
346 (mac_addr
[4] << 8) | mac_addr
[5];
348 rpfl2_uc_flr_en_set(self
, 0U, HW_ATL_B0_MAC
);
349 rpfl2unicast_dest_addresslsw_set(self
, l
, HW_ATL_B0_MAC
);
350 rpfl2unicast_dest_addressmsw_set(self
, h
, HW_ATL_B0_MAC
);
351 rpfl2_uc_flr_en_set(self
, 1U, HW_ATL_B0_MAC
);
353 err
= aq_hw_err_from_flags(self
);
359 static int hw_atl_b0_hw_init(struct aq_hw_s
*self
,
360 struct aq_nic_cfg_s
*aq_nic_cfg
,
363 static u32 aq_hw_atl_igcr_table_
[4][2] = {
364 { 0x20000000U
, 0x20000000U
}, /* AQ_IRQ_INVALID */
365 { 0x20000080U
, 0x20000080U
}, /* AQ_IRQ_LEGACY */
366 { 0x20000021U
, 0x20000025U
}, /* AQ_IRQ_MSI */
367 { 0x20000022U
, 0x20000026U
} /* AQ_IRQ_MSIX */
372 self
->aq_nic_cfg
= aq_nic_cfg
;
374 hw_atl_utils_hw_chip_features_init(self
,
375 &PHAL_ATLANTIC_B0
->chip_features
);
377 hw_atl_b0_hw_init_tx_path(self
);
378 hw_atl_b0_hw_init_rx_path(self
);
380 hw_atl_b0_hw_mac_addr_set(self
, mac_addr
);
382 hw_atl_utils_mpi_set(self
, MPI_INIT
, aq_nic_cfg
->link_speed_msk
);
384 hw_atl_b0_hw_qos_set(self
);
385 hw_atl_b0_hw_rss_set(self
, &aq_nic_cfg
->aq_rss
);
386 hw_atl_b0_hw_rss_hash_set(self
, &aq_nic_cfg
->aq_rss
);
388 err
= aq_hw_err_from_flags(self
);
393 reg_irq_glb_ctl_set(self
,
394 aq_hw_atl_igcr_table_
[aq_nic_cfg
->irq_type
]
395 [(aq_nic_cfg
->vecs
> 1U) ?
398 itr_irq_auto_masklsw_set(self
, aq_nic_cfg
->aq_hw_caps
->irq_mask
);
401 reg_gen_irq_map_set(self
,
402 ((HW_ATL_B0_ERR_INT
<< 0x18) | (1U << 0x1F)) |
403 ((HW_ATL_B0_ERR_INT
<< 0x10) | (1U << 0x17)), 0U);
405 hw_atl_b0_hw_offload_set(self
, aq_nic_cfg
);
411 static int hw_atl_b0_hw_ring_tx_start(struct aq_hw_s
*self
,
412 struct aq_ring_s
*ring
)
414 tdm_tx_desc_en_set(self
, 1, ring
->idx
);
415 return aq_hw_err_from_flags(self
);
418 static int hw_atl_b0_hw_ring_rx_start(struct aq_hw_s
*self
,
419 struct aq_ring_s
*ring
)
421 rdm_rx_desc_en_set(self
, 1, ring
->idx
);
422 return aq_hw_err_from_flags(self
);
425 static int hw_atl_b0_hw_start(struct aq_hw_s
*self
)
427 tpb_tx_buff_en_set(self
, 1);
428 rpb_rx_buff_en_set(self
, 1);
429 return aq_hw_err_from_flags(self
);
432 static int hw_atl_b0_hw_tx_ring_tail_update(struct aq_hw_s
*self
,
433 struct aq_ring_s
*ring
)
435 reg_tx_dma_desc_tail_ptr_set(self
, ring
->sw_tail
, ring
->idx
);
439 static int hw_atl_b0_hw_ring_tx_xmit(struct aq_hw_s
*self
,
440 struct aq_ring_s
*ring
,
443 struct aq_ring_buff_s
*buff
= NULL
;
444 struct hw_atl_txd_s
*txd
= NULL
;
445 unsigned int buff_pa_len
= 0U;
446 unsigned int pkt_len
= 0U;
447 unsigned int frag_count
= 0U;
450 buff
= &ring
->buff_ring
[ring
->sw_tail
];
451 pkt_len
= (buff
->is_eop
&& buff
->is_sop
) ? buff
->len
: buff
->len_pkt
;
453 for (frag_count
= 0; frag_count
< frags
; frag_count
++) {
454 txd
= (struct hw_atl_txd_s
*)&ring
->dx_ring
[ring
->sw_tail
*
460 buff
= &ring
->buff_ring
[ring
->sw_tail
];
463 txd
->ctl
|= (buff
->len_l3
<< 31) |
464 (buff
->len_l2
<< 24) |
465 HW_ATL_B0_TXD_CTL_CMD_TCP
|
466 HW_ATL_B0_TXD_CTL_DESC_TYPE_TXC
;
467 txd
->ctl2
|= (buff
->mss
<< 16) |
468 (buff
->len_l4
<< 8) |
471 pkt_len
-= (buff
->len_l4
+
477 txd
->ctl
|= HW_ATL_B0_TXD_CTL_CMD_IPV6
;
479 buff_pa_len
= buff
->len
;
481 txd
->buf_addr
= buff
->pa
;
482 txd
->ctl
|= (HW_ATL_B0_TXD_CTL_BLEN
&
483 ((u32
)buff_pa_len
<< 4));
484 txd
->ctl
|= HW_ATL_B0_TXD_CTL_DESC_TYPE_TXD
;
486 txd
->ctl2
|= HW_ATL_B0_TXD_CTL2_LEN
& (pkt_len
<< 14);
489 txd
->ctl
|= HW_ATL_B0_TXD_CTL_CMD_LSO
;
490 txd
->ctl2
|= HW_ATL_B0_TXD_CTL2_CTX_EN
;
493 /* Tx checksum offloads */
495 txd
->ctl
|= HW_ATL_B0_TXD_CTL_CMD_IPCSO
;
497 if (buff
->is_udp_cso
|| buff
->is_tcp_cso
)
498 txd
->ctl
|= HW_ATL_B0_TXD_CTL_CMD_TUCSO
;
500 if (unlikely(buff
->is_eop
)) {
501 txd
->ctl
|= HW_ATL_B0_TXD_CTL_EOP
;
502 txd
->ctl
|= HW_ATL_B0_TXD_CTL_CMD_WB
;
507 ring
->sw_tail
= aq_ring_next_dx(ring
, ring
->sw_tail
);
510 hw_atl_b0_hw_tx_ring_tail_update(self
, ring
);
511 return aq_hw_err_from_flags(self
);
514 static int hw_atl_b0_hw_ring_rx_init(struct aq_hw_s
*self
,
515 struct aq_ring_s
*aq_ring
,
516 struct aq_ring_param_s
*aq_ring_param
)
518 u32 dma_desc_addr_lsw
= (u32
)aq_ring
->dx_ring_pa
;
519 u32 dma_desc_addr_msw
= (u32
)(((u64
)aq_ring
->dx_ring_pa
) >> 32);
521 rdm_rx_desc_en_set(self
, false, aq_ring
->idx
);
523 rdm_rx_desc_head_splitting_set(self
, 0U, aq_ring
->idx
);
525 reg_rx_dma_desc_base_addresslswset(self
, dma_desc_addr_lsw
,
528 reg_rx_dma_desc_base_addressmswset(self
,
529 dma_desc_addr_msw
, aq_ring
->idx
);
531 rdm_rx_desc_len_set(self
, aq_ring
->size
/ 8U, aq_ring
->idx
);
533 rdm_rx_desc_data_buff_size_set(self
,
534 AQ_CFG_RX_FRAME_MAX
/ 1024U,
537 rdm_rx_desc_head_buff_size_set(self
, 0U, aq_ring
->idx
);
538 rdm_rx_desc_head_splitting_set(self
, 0U, aq_ring
->idx
);
539 rpo_rx_desc_vlan_stripping_set(self
, 0U, aq_ring
->idx
);
541 /* Rx ring set mode */
543 /* Mapping interrupt vector */
544 itr_irq_map_rx_set(self
, aq_ring_param
->vec_idx
, aq_ring
->idx
);
545 itr_irq_map_en_rx_set(self
, true, aq_ring
->idx
);
547 rdm_cpu_id_set(self
, aq_ring_param
->cpu
, aq_ring
->idx
);
548 rdm_rx_desc_dca_en_set(self
, 0U, aq_ring
->idx
);
549 rdm_rx_head_dca_en_set(self
, 0U, aq_ring
->idx
);
550 rdm_rx_pld_dca_en_set(self
, 0U, aq_ring
->idx
);
552 return aq_hw_err_from_flags(self
);
555 static int hw_atl_b0_hw_ring_tx_init(struct aq_hw_s
*self
,
556 struct aq_ring_s
*aq_ring
,
557 struct aq_ring_param_s
*aq_ring_param
)
559 u32 dma_desc_lsw_addr
= (u32
)aq_ring
->dx_ring_pa
;
560 u32 dma_desc_msw_addr
= (u32
)(((u64
)aq_ring
->dx_ring_pa
) >> 32);
562 reg_tx_dma_desc_base_addresslswset(self
, dma_desc_lsw_addr
,
565 reg_tx_dma_desc_base_addressmswset(self
, dma_desc_msw_addr
,
568 tdm_tx_desc_len_set(self
, aq_ring
->size
/ 8U, aq_ring
->idx
);
570 hw_atl_b0_hw_tx_ring_tail_update(self
, aq_ring
);
572 /* Set Tx threshold */
573 tdm_tx_desc_wr_wb_threshold_set(self
, 0U, aq_ring
->idx
);
575 /* Mapping interrupt vector */
576 itr_irq_map_tx_set(self
, aq_ring_param
->vec_idx
, aq_ring
->idx
);
577 itr_irq_map_en_tx_set(self
, true, aq_ring
->idx
);
579 tdm_cpu_id_set(self
, aq_ring_param
->cpu
, aq_ring
->idx
);
580 tdm_tx_desc_dca_en_set(self
, 0U, aq_ring
->idx
);
582 return aq_hw_err_from_flags(self
);
585 static int hw_atl_b0_hw_ring_rx_fill(struct aq_hw_s
*self
,
586 struct aq_ring_s
*ring
,
587 unsigned int sw_tail_old
)
589 for (; sw_tail_old
!= ring
->sw_tail
;
590 sw_tail_old
= aq_ring_next_dx(ring
, sw_tail_old
)) {
591 struct hw_atl_rxd_s
*rxd
=
592 (struct hw_atl_rxd_s
*)&ring
->dx_ring
[sw_tail_old
*
595 struct aq_ring_buff_s
*buff
= &ring
->buff_ring
[sw_tail_old
];
597 rxd
->buf_addr
= buff
->pa
;
601 reg_rx_dma_desc_tail_ptr_set(self
, sw_tail_old
, ring
->idx
);
603 return aq_hw_err_from_flags(self
);
606 static int hw_atl_b0_hw_ring_tx_head_update(struct aq_hw_s
*self
,
607 struct aq_ring_s
*ring
)
610 unsigned int hw_head_
= tdm_tx_desc_head_ptr_get(self
, ring
->idx
);
612 if (aq_utils_obj_test(&self
->header
.flags
, AQ_HW_FLAG_ERR_UNPLUG
)) {
616 ring
->hw_head
= hw_head_
;
617 err
= aq_hw_err_from_flags(self
);
623 static int hw_atl_b0_hw_ring_rx_receive(struct aq_hw_s
*self
,
624 struct aq_ring_s
*ring
)
626 struct device
*ndev
= aq_nic_get_dev(ring
->aq_nic
);
628 for (; ring
->hw_head
!= ring
->sw_tail
;
629 ring
->hw_head
= aq_ring_next_dx(ring
, ring
->hw_head
)) {
630 struct aq_ring_buff_s
*buff
= NULL
;
631 struct hw_atl_rxd_wb_s
*rxd_wb
= (struct hw_atl_rxd_wb_s
*)
632 &ring
->dx_ring
[ring
->hw_head
* HW_ATL_B0_RXD_SIZE
];
634 unsigned int is_err
= 1U;
635 unsigned int is_rx_check_sum_enabled
= 0U;
636 unsigned int pkt_type
= 0U;
638 if (!(rxd_wb
->status
& 0x1U
)) { /* RxD is not done */
642 buff
= &ring
->buff_ring
[ring
->hw_head
];
644 is_err
= (0x0000003CU
& rxd_wb
->status
);
646 is_rx_check_sum_enabled
= (rxd_wb
->type
) & (0x3U
<< 19);
647 is_err
&= ~0x20U
; /* exclude validity bit */
649 pkt_type
= 0xFFU
& (rxd_wb
->type
>> 4);
651 if (is_rx_check_sum_enabled
) {
652 if (0x0U
== (pkt_type
& 0x3U
))
653 buff
->is_ip_cso
= (is_err
& 0x08U
) ? 0U : 1U;
655 if (0x4U
== (pkt_type
& 0x1CU
))
656 buff
->is_udp_cso
= buff
->is_cso_err
? 0U : 1U;
657 else if (0x0U
== (pkt_type
& 0x1CU
))
658 buff
->is_tcp_cso
= buff
->is_cso_err
? 0U : 1U;
660 /* Checksum offload workaround for small packets */
661 if (rxd_wb
->pkt_len
<= 60) {
662 buff
->is_ip_cso
= 0U;
663 buff
->is_cso_err
= 0U;
669 dma_unmap_page(ndev
, buff
->pa
, buff
->len
, DMA_FROM_DEVICE
);
671 if (is_err
|| rxd_wb
->type
& 0x1000U
) {
672 /* status error or DMA error */
675 if (self
->aq_nic_cfg
->is_rss
) {
677 u16 rss_type
= rxd_wb
->type
& 0xFU
;
679 if (rss_type
&& rss_type
< 0x8U
) {
680 buff
->is_hash_l4
= (rss_type
== 0x4 ||
682 buff
->rss_hash
= rxd_wb
->rss_hash
;
686 if (HW_ATL_B0_RXD_WB_STAT2_EOP
& rxd_wb
->status
) {
687 buff
->len
= rxd_wb
->pkt_len
%
689 buff
->len
= buff
->len
?
690 buff
->len
: AQ_CFG_RX_FRAME_MAX
;
694 if (HW_ATL_B0_RXD_WB_STAT2_RSCCNT
&
697 buff
->next
= rxd_wb
->next_desc_ptr
;
698 ++ring
->stats
.rx
.lro_packets
;
702 aq_ring_next_dx(ring
,
704 ++ring
->stats
.rx
.jumbo_packets
;
710 return aq_hw_err_from_flags(self
);
713 static int hw_atl_b0_hw_irq_enable(struct aq_hw_s
*self
, u64 mask
)
715 itr_irq_msk_setlsw_set(self
, LODWORD(mask
));
716 return aq_hw_err_from_flags(self
);
719 static int hw_atl_b0_hw_irq_disable(struct aq_hw_s
*self
, u64 mask
)
721 itr_irq_msk_clearlsw_set(self
, LODWORD(mask
));
722 itr_irq_status_clearlsw_set(self
, LODWORD(mask
));
724 atomic_inc(&PHAL_ATLANTIC_B0
->dpc
);
725 return aq_hw_err_from_flags(self
);
728 static int hw_atl_b0_hw_irq_read(struct aq_hw_s
*self
, u64
*mask
)
730 *mask
= itr_irq_statuslsw_get(self
);
731 return aq_hw_err_from_flags(self
);
734 #define IS_FILTER_ENABLED(_F_) ((packet_filter & (_F_)) ? 1U : 0U)
736 static int hw_atl_b0_hw_packet_filter_set(struct aq_hw_s
*self
,
737 unsigned int packet_filter
)
741 rpfl2promiscuous_mode_en_set(self
, IS_FILTER_ENABLED(IFF_PROMISC
));
742 rpfl2multicast_flr_en_set(self
,
743 IS_FILTER_ENABLED(IFF_MULTICAST
), 0);
745 rpfl2_accept_all_mc_packets_set(self
,
746 IS_FILTER_ENABLED(IFF_ALLMULTI
));
748 rpfl2broadcast_en_set(self
, IS_FILTER_ENABLED(IFF_BROADCAST
));
750 self
->aq_nic_cfg
->is_mc_list_enabled
= IS_FILTER_ENABLED(IFF_MULTICAST
);
752 for (i
= HW_ATL_B0_MAC_MIN
; i
< HW_ATL_B0_MAC_MAX
; ++i
)
753 rpfl2_uc_flr_en_set(self
,
754 (self
->aq_nic_cfg
->is_mc_list_enabled
&&
755 (i
<= self
->aq_nic_cfg
->mc_list_count
)) ?
758 return aq_hw_err_from_flags(self
);
761 #undef IS_FILTER_ENABLED
763 static int hw_atl_b0_hw_multicast_list_set(struct aq_hw_s
*self
,
765 [AQ_CFG_MULTICAST_ADDRESS_MAX
]
771 if (count
> (HW_ATL_B0_MAC_MAX
- HW_ATL_B0_MAC_MIN
)) {
775 for (self
->aq_nic_cfg
->mc_list_count
= 0U;
776 self
->aq_nic_cfg
->mc_list_count
< count
;
777 ++self
->aq_nic_cfg
->mc_list_count
) {
778 u32 i
= self
->aq_nic_cfg
->mc_list_count
;
779 u32 h
= (ar_mac
[i
][0] << 8) | (ar_mac
[i
][1]);
780 u32 l
= (ar_mac
[i
][2] << 24) | (ar_mac
[i
][3] << 16) |
781 (ar_mac
[i
][4] << 8) | ar_mac
[i
][5];
783 rpfl2_uc_flr_en_set(self
, 0U, HW_ATL_B0_MAC_MIN
+ i
);
785 rpfl2unicast_dest_addresslsw_set(self
,
786 l
, HW_ATL_B0_MAC_MIN
+ i
);
788 rpfl2unicast_dest_addressmsw_set(self
,
789 h
, HW_ATL_B0_MAC_MIN
+ i
);
791 rpfl2_uc_flr_en_set(self
,
792 (self
->aq_nic_cfg
->is_mc_list_enabled
),
793 HW_ATL_B0_MAC_MIN
+ i
);
796 err
= aq_hw_err_from_flags(self
);
802 static int hw_atl_b0_hw_interrupt_moderation_set(struct aq_hw_s
*self
)
808 switch (self
->aq_nic_cfg
->itr
) {
809 case AQ_CFG_INTERRUPT_MODERATION_ON
:
810 case AQ_CFG_INTERRUPT_MODERATION_AUTO
:
811 tdm_tx_desc_wr_wb_irq_en_set(self
, 0U);
812 tdm_tdm_intr_moder_en_set(self
, 1U);
813 rdm_rx_desc_wr_wb_irq_en_set(self
, 0U);
814 rdm_rdm_intr_moder_en_set(self
, 1U);
816 if (self
->aq_nic_cfg
->itr
== AQ_CFG_INTERRUPT_MODERATION_ON
) {
817 /* HW timers are in 2us units */
818 int tx_max_timer
= self
->aq_nic_cfg
->tx_itr
/ 2;
819 int tx_min_timer
= tx_max_timer
/ 2;
821 int rx_max_timer
= self
->aq_nic_cfg
->rx_itr
/ 2;
822 int rx_min_timer
= rx_max_timer
/ 2;
824 tx_max_timer
= min(HW_ATL_INTR_MODER_MAX
, tx_max_timer
);
825 tx_min_timer
= min(HW_ATL_INTR_MODER_MIN
, tx_min_timer
);
826 rx_max_timer
= min(HW_ATL_INTR_MODER_MAX
, rx_max_timer
);
827 rx_min_timer
= min(HW_ATL_INTR_MODER_MIN
, rx_min_timer
);
829 itr_tx
|= tx_min_timer
<< 0x8U
;
830 itr_tx
|= tx_max_timer
<< 0x10U
;
831 itr_rx
|= rx_min_timer
<< 0x8U
;
832 itr_rx
|= rx_max_timer
<< 0x10U
;
834 static unsigned int hw_atl_b0_timers_table_tx_
[][2] = {
835 {0xfU
, 0xffU
}, /* 10Gbit */
836 {0xfU
, 0x1ffU
}, /* 5Gbit */
837 {0xfU
, 0x1ffU
}, /* 5Gbit 5GS */
838 {0xfU
, 0x1ffU
}, /* 2.5Gbit */
839 {0xfU
, 0x1ffU
}, /* 1Gbit */
840 {0xfU
, 0x1ffU
}, /* 100Mbit */
843 static unsigned int hw_atl_b0_timers_table_rx_
[][2] = {
844 {0x6U
, 0x38U
},/* 10Gbit */
845 {0xCU
, 0x70U
},/* 5Gbit */
846 {0xCU
, 0x70U
},/* 5Gbit 5GS */
847 {0x18U
, 0xE0U
},/* 2.5Gbit */
848 {0x30U
, 0x80U
},/* 1Gbit */
849 {0x4U
, 0x50U
},/* 100Mbit */
852 unsigned int speed_index
=
853 hw_atl_utils_mbps_2_speed_index(
854 self
->aq_link_status
.mbps
);
856 /* Update user visible ITR settings */
857 self
->aq_nic_cfg
->tx_itr
= hw_atl_b0_timers_table_tx_
858 [speed_index
][1] * 2;
859 self
->aq_nic_cfg
->rx_itr
= hw_atl_b0_timers_table_rx_
860 [speed_index
][1] * 2;
862 itr_tx
|= hw_atl_b0_timers_table_tx_
863 [speed_index
][0] << 0x8U
;
864 itr_tx
|= hw_atl_b0_timers_table_tx_
865 [speed_index
][1] << 0x10U
;
867 itr_rx
|= hw_atl_b0_timers_table_rx_
868 [speed_index
][0] << 0x8U
;
869 itr_rx
|= hw_atl_b0_timers_table_rx_
870 [speed_index
][1] << 0x10U
;
873 case AQ_CFG_INTERRUPT_MODERATION_OFF
:
874 tdm_tx_desc_wr_wb_irq_en_set(self
, 1U);
875 tdm_tdm_intr_moder_en_set(self
, 0U);
876 rdm_rx_desc_wr_wb_irq_en_set(self
, 1U);
877 rdm_rdm_intr_moder_en_set(self
, 0U);
883 for (i
= HW_ATL_B0_RINGS_MAX
; i
--;) {
884 reg_tx_intr_moder_ctrl_set(self
, itr_tx
, i
);
885 reg_rx_intr_moder_ctrl_set(self
, itr_rx
, i
);
888 return aq_hw_err_from_flags(self
);
891 static int hw_atl_b0_hw_stop(struct aq_hw_s
*self
)
893 hw_atl_b0_hw_irq_disable(self
, HW_ATL_B0_INT_MASK
);
894 return aq_hw_err_from_flags(self
);
897 static int hw_atl_b0_hw_ring_tx_stop(struct aq_hw_s
*self
,
898 struct aq_ring_s
*ring
)
900 tdm_tx_desc_en_set(self
, 0U, ring
->idx
);
901 return aq_hw_err_from_flags(self
);
904 static int hw_atl_b0_hw_ring_rx_stop(struct aq_hw_s
*self
,
905 struct aq_ring_s
*ring
)
907 rdm_rx_desc_en_set(self
, 0U, ring
->idx
);
908 return aq_hw_err_from_flags(self
);
911 static int hw_atl_b0_hw_set_speed(struct aq_hw_s
*self
, u32 speed
)
915 err
= hw_atl_utils_mpi_set_speed(self
, speed
, MPI_INIT
);
923 static struct aq_hw_ops hw_atl_ops_
= {
924 .create
= hw_atl_b0_create
,
925 .destroy
= hw_atl_b0_destroy
,
926 .get_hw_caps
= hw_atl_b0_get_hw_caps
,
928 .hw_get_mac_permanent
= hw_atl_utils_get_mac_permanent
,
929 .hw_set_mac_address
= hw_atl_b0_hw_mac_addr_set
,
930 .hw_get_link_status
= hw_atl_utils_mpi_get_link_status
,
931 .hw_set_link_speed
= hw_atl_b0_hw_set_speed
,
932 .hw_init
= hw_atl_b0_hw_init
,
933 .hw_deinit
= hw_atl_utils_hw_deinit
,
934 .hw_set_power
= hw_atl_utils_hw_set_power
,
935 .hw_reset
= hw_atl_b0_hw_reset
,
936 .hw_start
= hw_atl_b0_hw_start
,
937 .hw_ring_tx_start
= hw_atl_b0_hw_ring_tx_start
,
938 .hw_ring_tx_stop
= hw_atl_b0_hw_ring_tx_stop
,
939 .hw_ring_rx_start
= hw_atl_b0_hw_ring_rx_start
,
940 .hw_ring_rx_stop
= hw_atl_b0_hw_ring_rx_stop
,
941 .hw_stop
= hw_atl_b0_hw_stop
,
943 .hw_ring_tx_xmit
= hw_atl_b0_hw_ring_tx_xmit
,
944 .hw_ring_tx_head_update
= hw_atl_b0_hw_ring_tx_head_update
,
946 .hw_ring_rx_receive
= hw_atl_b0_hw_ring_rx_receive
,
947 .hw_ring_rx_fill
= hw_atl_b0_hw_ring_rx_fill
,
949 .hw_irq_enable
= hw_atl_b0_hw_irq_enable
,
950 .hw_irq_disable
= hw_atl_b0_hw_irq_disable
,
951 .hw_irq_read
= hw_atl_b0_hw_irq_read
,
953 .hw_ring_rx_init
= hw_atl_b0_hw_ring_rx_init
,
954 .hw_ring_tx_init
= hw_atl_b0_hw_ring_tx_init
,
955 .hw_packet_filter_set
= hw_atl_b0_hw_packet_filter_set
,
956 .hw_multicast_list_set
= hw_atl_b0_hw_multicast_list_set
,
957 .hw_interrupt_moderation_set
= hw_atl_b0_hw_interrupt_moderation_set
,
958 .hw_rss_set
= hw_atl_b0_hw_rss_set
,
959 .hw_rss_hash_set
= hw_atl_b0_hw_rss_hash_set
,
960 .hw_get_regs
= hw_atl_utils_hw_get_regs
,
961 .hw_update_stats
= hw_atl_utils_update_stats
,
962 .hw_get_hw_stats
= hw_atl_utils_get_hw_stats
,
963 .hw_get_fw_version
= hw_atl_utils_get_fw_version
,
966 struct aq_hw_ops
*hw_atl_b0_get_ops_by_id(struct pci_dev
*pdev
)
968 bool is_vid_ok
= (pdev
->vendor
== PCI_VENDOR_ID_AQUANTIA
);
969 bool is_did_ok
= ((pdev
->device
== HW_ATL_DEVICE_ID_0001
) ||
970 (pdev
->device
== HW_ATL_DEVICE_ID_D100
) ||
971 (pdev
->device
== HW_ATL_DEVICE_ID_D107
) ||
972 (pdev
->device
== HW_ATL_DEVICE_ID_D108
) ||
973 (pdev
->device
== HW_ATL_DEVICE_ID_D109
));
975 bool is_rev_ok
= (pdev
->revision
== 2U);
977 return (is_vid_ok
&& is_did_ok
&& is_rev_ok
) ? &hw_atl_ops_
: NULL
;