2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
10 /* File hw_atl_b0.c: Definition of Atlantic hardware specific functions. */
13 #include "../aq_hw_utils.h"
14 #include "../aq_ring.h"
15 #include "hw_atl_b0.h"
16 #include "hw_atl_utils.h"
17 #include "hw_atl_llh.h"
18 #include "hw_atl_b0_internal.h"
20 static int hw_atl_b0_get_hw_caps(struct aq_hw_s
*self
,
21 struct aq_hw_caps_s
*aq_hw_caps
)
23 memcpy(aq_hw_caps
, &hw_atl_b0_hw_caps_
, sizeof(*aq_hw_caps
));
27 static struct aq_hw_s
*hw_atl_b0_create(struct aq_pci_func_s
*aq_pci_func
,
29 struct aq_hw_ops
*ops
)
31 struct hw_atl_s
*self
= NULL
;
33 self
= kzalloc(sizeof(*self
), GFP_KERNEL
);
37 self
->base
.aq_pci_func
= aq_pci_func
;
39 self
->base
.not_ff_addr
= 0x10U
;
42 return (struct aq_hw_s
*)self
;
45 static void hw_atl_b0_destroy(struct aq_hw_s
*self
)
50 static int hw_atl_b0_hw_reset(struct aq_hw_s
*self
)
54 glb_glb_reg_res_dis_set(self
, 1U);
55 pci_pci_reg_res_dis_set(self
, 0U);
56 rx_rx_reg_res_dis_set(self
, 0U);
57 tx_tx_reg_res_dis_set(self
, 0U);
60 glb_soft_res_set(self
, 1);
62 /* check 10 times by 1ms */
63 AQ_HW_WAIT_FOR(glb_soft_res_get(self
) == 0, 1000U, 10U);
67 itr_irq_reg_res_dis_set(self
, 0U);
68 itr_res_irq_set(self
, 1U);
70 /* check 10 times by 1ms */
71 AQ_HW_WAIT_FOR(itr_res_irq_get(self
) == 0, 1000U, 10U);
75 hw_atl_utils_mpi_set(self
, MPI_RESET
, 0x0U
);
77 err
= aq_hw_err_from_flags(self
);
83 static int hw_atl_b0_hw_qos_set(struct aq_hw_s
*self
)
87 unsigned int i_priority
= 0U;
88 bool is_rx_flow_control
= false;
90 /* TPS Descriptor rate init */
91 tps_tx_pkt_shed_desc_rate_curr_time_res_set(self
, 0x0U
);
92 tps_tx_pkt_shed_desc_rate_lim_set(self
, 0xA);
95 tps_tx_pkt_shed_desc_vm_arb_mode_set(self
, 0U);
97 /* TPS TC credits init */
98 tps_tx_pkt_shed_desc_tc_arb_mode_set(self
, 0U);
99 tps_tx_pkt_shed_data_arb_mode_set(self
, 0U);
101 tps_tx_pkt_shed_tc_data_max_credit_set(self
, 0xFFF, 0U);
102 tps_tx_pkt_shed_tc_data_weight_set(self
, 0x64, 0U);
103 tps_tx_pkt_shed_desc_tc_max_credit_set(self
, 0x50, 0U);
104 tps_tx_pkt_shed_desc_tc_weight_set(self
, 0x1E, 0U);
107 buff_size
= HW_ATL_B0_TXBUF_MAX
;
109 tpb_tx_pkt_buff_size_per_tc_set(self
, buff_size
, tc
);
110 tpb_tx_buff_hi_threshold_per_tc_set(self
,
111 (buff_size
* (1024 / 32U) * 66U) /
113 tpb_tx_buff_lo_threshold_per_tc_set(self
,
114 (buff_size
* (1024 / 32U) * 50U) /
117 /* QoS Rx buf size per TC */
119 is_rx_flow_control
= (AQ_NIC_FC_RX
& self
->aq_nic_cfg
->flow_control
);
120 buff_size
= HW_ATL_B0_RXBUF_MAX
;
122 rpb_rx_pkt_buff_size_per_tc_set(self
, buff_size
, tc
);
123 rpb_rx_buff_hi_threshold_per_tc_set(self
,
125 (1024U / 32U) * 66U) /
127 rpb_rx_buff_lo_threshold_per_tc_set(self
,
129 (1024U / 32U) * 50U) /
131 rpb_rx_xoff_en_per_tc_set(self
, is_rx_flow_control
? 1U : 0U, tc
);
133 /* QoS 802.1p priority -> TC mapping */
134 for (i_priority
= 8U; i_priority
--;)
135 rpf_rpb_user_priority_tc_map_set(self
, i_priority
, 0U);
137 return aq_hw_err_from_flags(self
);
140 static int hw_atl_b0_hw_rss_hash_set(struct aq_hw_s
*self
,
141 struct aq_rss_parameters
*rss_params
)
143 struct aq_nic_cfg_s
*cfg
= NULL
;
146 unsigned int addr
= 0U;
148 cfg
= self
->aq_nic_cfg
;
150 for (i
= 10, addr
= 0U; i
--; ++addr
) {
151 u32 key_data
= cfg
->is_rss
?
152 __swab32(rss_params
->hash_secret_key
[i
]) : 0U;
153 rpf_rss_key_wr_data_set(self
, key_data
);
154 rpf_rss_key_addr_set(self
, addr
);
155 rpf_rss_key_wr_en_set(self
, 1U);
156 AQ_HW_WAIT_FOR(rpf_rss_key_wr_en_get(self
) == 0, 1000U, 10U);
161 err
= aq_hw_err_from_flags(self
);
167 static int hw_atl_b0_hw_rss_set(struct aq_hw_s
*self
,
168 struct aq_rss_parameters
*rss_params
)
170 u8
*indirection_table
= rss_params
->indirection_table
;
172 u32 num_rss_queues
= max(1U, self
->aq_nic_cfg
->num_rss_queues
);
174 u16 bitary
[(HW_ATL_B0_RSS_REDIRECTION_MAX
*
175 HW_ATL_B0_RSS_REDIRECTION_BITS
/ 16U)];
177 memset(bitary
, 0, sizeof(bitary
));
179 for (i
= HW_ATL_B0_RSS_REDIRECTION_MAX
; i
--;) {
180 (*(u32
*)(bitary
+ ((i
* 3U) / 16U))) |=
181 ((indirection_table
[i
] % num_rss_queues
) <<
185 for (i
= AQ_DIMOF(bitary
); i
--;) {
186 rpf_rss_redir_tbl_wr_data_set(self
, bitary
[i
]);
187 rpf_rss_redir_tbl_addr_set(self
, i
);
188 rpf_rss_redir_wr_en_set(self
, 1U);
189 AQ_HW_WAIT_FOR(rpf_rss_redir_wr_en_get(self
) == 0, 1000U, 10U);
194 err
= aq_hw_err_from_flags(self
);
200 static int hw_atl_b0_hw_offload_set(struct aq_hw_s
*self
,
201 struct aq_nic_cfg_s
*aq_nic_cfg
)
205 /* TX checksums offloads*/
206 tpo_ipv4header_crc_offload_en_set(self
, 1);
207 tpo_tcp_udp_crc_offload_en_set(self
, 1);
209 /* RX checksums offloads*/
210 rpo_ipv4header_crc_offload_en_set(self
, 1);
211 rpo_tcp_udp_crc_offload_en_set(self
, 1);
214 tdm_large_send_offload_en_set(self
, 0xFFFFFFFFU
);
218 unsigned int val
= (8U < HW_ATL_B0_LRO_RXD_MAX
) ? 0x3U
:
219 ((4U < HW_ATL_B0_LRO_RXD_MAX
) ? 0x2U
:
220 ((2U < HW_ATL_B0_LRO_RXD_MAX
) ? 0x1U
: 0x0));
222 for (i
= 0; i
< HW_ATL_B0_RINGS_MAX
; i
++)
223 rpo_lro_max_num_of_descriptors_set(self
, val
, i
);
225 rpo_lro_time_base_divider_set(self
, 0x61AU
);
226 rpo_lro_inactive_interval_set(self
, 0);
227 rpo_lro_max_coalescing_interval_set(self
, 2);
229 rpo_lro_qsessions_lim_set(self
, 1U);
231 rpo_lro_total_desc_lim_set(self
, 2U);
233 rpo_lro_patch_optimization_en_set(self
, 0U);
235 rpo_lro_min_pay_of_first_pkt_set(self
, 10U);
237 rpo_lro_pkt_lim_set(self
, 1U);
239 rpo_lro_en_set(self
, aq_nic_cfg
->is_lro
? 0xFFFFFFFFU
: 0U);
241 return aq_hw_err_from_flags(self
);
244 static int hw_atl_b0_hw_init_tx_path(struct aq_hw_s
*self
)
246 thm_lso_tcp_flag_of_first_pkt_set(self
, 0x0FF6U
);
247 thm_lso_tcp_flag_of_middle_pkt_set(self
, 0x0FF6U
);
248 thm_lso_tcp_flag_of_last_pkt_set(self
, 0x0F7FU
);
251 tdm_tx_desc_wr_wb_irq_en_set(self
, 1U);
254 aq_hw_write_reg(self
, 0x00007040U
, IS_CHIP_FEATURE(TPO2
) ?
255 0x00010000U
: 0x00000000U
);
256 tdm_tx_dca_en_set(self
, 0U);
257 tdm_tx_dca_mode_set(self
, 0U);
259 tpb_tx_path_scp_ins_en_set(self
, 1U);
261 return aq_hw_err_from_flags(self
);
264 static int hw_atl_b0_hw_init_rx_path(struct aq_hw_s
*self
)
266 struct aq_nic_cfg_s
*cfg
= self
->aq_nic_cfg
;
269 /* Rx TC/RSS number config */
270 rpb_rpf_rx_traf_class_mode_set(self
, 1U);
272 /* Rx flow control */
273 rpb_rx_flow_ctl_mode_set(self
, 1U);
275 /* RSS Ring selection */
276 reg_rx_flr_rss_control1set(self
, cfg
->is_rss
?
277 0xB3333333U
: 0x00000000U
);
279 /* Multicast filters */
280 for (i
= HW_ATL_B0_MAC_MAX
; i
--;) {
281 rpfl2_uc_flr_en_set(self
, (i
== 0U) ? 1U : 0U, i
);
282 rpfl2unicast_flr_act_set(self
, 1U, i
);
285 reg_rx_flr_mcst_flr_msk_set(self
, 0x00000000U
);
286 reg_rx_flr_mcst_flr_set(self
, 0x00010FFFU
, 0U);
289 rpf_vlan_outer_etht_set(self
, 0x88A8U
);
290 rpf_vlan_inner_etht_set(self
, 0x8100U
);
293 rpf_vlan_flr_act_set(self
, 1U, 0U);
294 rpf_vlan_id_flr_set(self
, 0U, 0U);
295 rpf_vlan_flr_en_set(self
, 0U, 0U);
297 rpf_vlan_accept_untagged_packets_set(self
, 1U);
298 rpf_vlan_untagged_act_set(self
, 1U);
300 rpf_vlan_flr_act_set(self
, 1U, 1U);
301 rpf_vlan_id_flr_set(self
, cfg
->vlan_id
, 0U);
302 rpf_vlan_flr_en_set(self
, 1U, 1U);
304 rpf_vlan_prom_mode_en_set(self
, 1);
308 rdm_rx_desc_wr_wb_irq_en_set(self
, 1U);
311 aq_hw_write_reg(self
, 0x00005040U
,
312 IS_CHIP_FEATURE(RPF2
) ? 0x000F0000U
: 0x00000000U
);
314 rpfl2broadcast_flr_act_set(self
, 1U);
315 rpfl2broadcast_count_threshold_set(self
, 0xFFFFU
& (~0U / 256U));
317 rdm_rx_dca_en_set(self
, 0U);
318 rdm_rx_dca_mode_set(self
, 0U);
320 return aq_hw_err_from_flags(self
);
323 static int hw_atl_b0_hw_mac_addr_set(struct aq_hw_s
*self
, u8
*mac_addr
)
333 h
= (mac_addr
[0] << 8) | (mac_addr
[1]);
334 l
= (mac_addr
[2] << 24) | (mac_addr
[3] << 16) |
335 (mac_addr
[4] << 8) | mac_addr
[5];
337 rpfl2_uc_flr_en_set(self
, 0U, HW_ATL_B0_MAC
);
338 rpfl2unicast_dest_addresslsw_set(self
, l
, HW_ATL_B0_MAC
);
339 rpfl2unicast_dest_addressmsw_set(self
, h
, HW_ATL_B0_MAC
);
340 rpfl2_uc_flr_en_set(self
, 1U, HW_ATL_B0_MAC
);
342 err
= aq_hw_err_from_flags(self
);
348 static int hw_atl_b0_hw_init(struct aq_hw_s
*self
,
349 struct aq_nic_cfg_s
*aq_nic_cfg
,
352 static u32 aq_hw_atl_igcr_table_
[4][2] = {
353 { 0x20000000U
, 0x20000000U
}, /* AQ_IRQ_INVALID */
354 { 0x20000080U
, 0x20000080U
}, /* AQ_IRQ_LEGACY */
355 { 0x20000021U
, 0x20000025U
}, /* AQ_IRQ_MSI */
356 { 0x20000022U
, 0x20000026U
} /* AQ_IRQ_MSIX */
361 self
->aq_nic_cfg
= aq_nic_cfg
;
363 hw_atl_utils_hw_chip_features_init(self
,
364 &PHAL_ATLANTIC_B0
->chip_features
);
366 hw_atl_b0_hw_init_tx_path(self
);
367 hw_atl_b0_hw_init_rx_path(self
);
369 hw_atl_b0_hw_mac_addr_set(self
, mac_addr
);
371 hw_atl_utils_mpi_set(self
, MPI_INIT
, aq_nic_cfg
->link_speed_msk
);
373 hw_atl_b0_hw_qos_set(self
);
374 hw_atl_b0_hw_rss_set(self
, &aq_nic_cfg
->aq_rss
);
375 hw_atl_b0_hw_rss_hash_set(self
, &aq_nic_cfg
->aq_rss
);
377 err
= aq_hw_err_from_flags(self
);
382 reg_irq_glb_ctl_set(self
,
383 aq_hw_atl_igcr_table_
[aq_nic_cfg
->irq_type
]
384 [(aq_nic_cfg
->vecs
> 1U) ?
387 itr_irq_auto_masklsw_set(self
, aq_nic_cfg
->aq_hw_caps
->irq_mask
);
390 reg_gen_irq_map_set(self
,
391 ((HW_ATL_B0_ERR_INT
<< 0x18) | (1U << 0x1F)) |
392 ((HW_ATL_B0_ERR_INT
<< 0x10) | (1U << 0x17)), 0U);
394 hw_atl_b0_hw_offload_set(self
, aq_nic_cfg
);
400 static int hw_atl_b0_hw_ring_tx_start(struct aq_hw_s
*self
,
401 struct aq_ring_s
*ring
)
403 tdm_tx_desc_en_set(self
, 1, ring
->idx
);
404 return aq_hw_err_from_flags(self
);
407 static int hw_atl_b0_hw_ring_rx_start(struct aq_hw_s
*self
,
408 struct aq_ring_s
*ring
)
410 rdm_rx_desc_en_set(self
, 1, ring
->idx
);
411 return aq_hw_err_from_flags(self
);
414 static int hw_atl_b0_hw_start(struct aq_hw_s
*self
)
416 tpb_tx_buff_en_set(self
, 1);
417 rpb_rx_buff_en_set(self
, 1);
418 return aq_hw_err_from_flags(self
);
421 static int hw_atl_b0_hw_tx_ring_tail_update(struct aq_hw_s
*self
,
422 struct aq_ring_s
*ring
)
424 reg_tx_dma_desc_tail_ptr_set(self
, ring
->sw_tail
, ring
->idx
);
428 static int hw_atl_b0_hw_ring_tx_xmit(struct aq_hw_s
*self
,
429 struct aq_ring_s
*ring
,
432 struct aq_ring_buff_s
*buff
= NULL
;
433 struct hw_atl_txd_s
*txd
= NULL
;
434 unsigned int buff_pa_len
= 0U;
435 unsigned int pkt_len
= 0U;
436 unsigned int frag_count
= 0U;
439 buff
= &ring
->buff_ring
[ring
->sw_tail
];
440 pkt_len
= (buff
->is_eop
&& buff
->is_sop
) ? buff
->len
: buff
->len_pkt
;
442 for (frag_count
= 0; frag_count
< frags
; frag_count
++) {
443 txd
= (struct hw_atl_txd_s
*)&ring
->dx_ring
[ring
->sw_tail
*
449 buff
= &ring
->buff_ring
[ring
->sw_tail
];
452 txd
->ctl
|= (buff
->len_l3
<< 31) |
453 (buff
->len_l2
<< 24) |
454 HW_ATL_B0_TXD_CTL_CMD_TCP
|
455 HW_ATL_B0_TXD_CTL_DESC_TYPE_TXC
;
456 txd
->ctl2
|= (buff
->mss
<< 16) |
457 (buff
->len_l4
<< 8) |
460 pkt_len
-= (buff
->len_l4
+
466 txd
->ctl
|= HW_ATL_B0_TXD_CTL_CMD_IPV6
;
468 buff_pa_len
= buff
->len
;
470 txd
->buf_addr
= buff
->pa
;
471 txd
->ctl
|= (HW_ATL_B0_TXD_CTL_BLEN
&
472 ((u32
)buff_pa_len
<< 4));
473 txd
->ctl
|= HW_ATL_B0_TXD_CTL_DESC_TYPE_TXD
;
475 txd
->ctl2
|= HW_ATL_B0_TXD_CTL2_LEN
& (pkt_len
<< 14);
478 txd
->ctl
|= HW_ATL_B0_TXD_CTL_CMD_LSO
;
479 txd
->ctl2
|= HW_ATL_B0_TXD_CTL2_CTX_EN
;
482 /* Tx checksum offloads */
484 txd
->ctl
|= HW_ATL_B0_TXD_CTL_CMD_IPCSO
;
486 if (buff
->is_udp_cso
|| buff
->is_tcp_cso
)
487 txd
->ctl
|= HW_ATL_B0_TXD_CTL_CMD_TUCSO
;
489 if (unlikely(buff
->is_eop
)) {
490 txd
->ctl
|= HW_ATL_B0_TXD_CTL_EOP
;
491 txd
->ctl
|= HW_ATL_B0_TXD_CTL_CMD_WB
;
496 ring
->sw_tail
= aq_ring_next_dx(ring
, ring
->sw_tail
);
499 hw_atl_b0_hw_tx_ring_tail_update(self
, ring
);
500 return aq_hw_err_from_flags(self
);
503 static int hw_atl_b0_hw_ring_rx_init(struct aq_hw_s
*self
,
504 struct aq_ring_s
*aq_ring
,
505 struct aq_ring_param_s
*aq_ring_param
)
507 u32 dma_desc_addr_lsw
= (u32
)aq_ring
->dx_ring_pa
;
508 u32 dma_desc_addr_msw
= (u32
)(((u64
)aq_ring
->dx_ring_pa
) >> 32);
510 rdm_rx_desc_en_set(self
, false, aq_ring
->idx
);
512 rdm_rx_desc_head_splitting_set(self
, 0U, aq_ring
->idx
);
514 reg_rx_dma_desc_base_addresslswset(self
, dma_desc_addr_lsw
,
517 reg_rx_dma_desc_base_addressmswset(self
,
518 dma_desc_addr_msw
, aq_ring
->idx
);
520 rdm_rx_desc_len_set(self
, aq_ring
->size
/ 8U, aq_ring
->idx
);
522 rdm_rx_desc_data_buff_size_set(self
,
523 AQ_CFG_RX_FRAME_MAX
/ 1024U,
526 rdm_rx_desc_head_buff_size_set(self
, 0U, aq_ring
->idx
);
527 rdm_rx_desc_head_splitting_set(self
, 0U, aq_ring
->idx
);
528 rpo_rx_desc_vlan_stripping_set(self
, 0U, aq_ring
->idx
);
530 /* Rx ring set mode */
532 /* Mapping interrupt vector */
533 itr_irq_map_rx_set(self
, aq_ring_param
->vec_idx
, aq_ring
->idx
);
534 itr_irq_map_en_rx_set(self
, true, aq_ring
->idx
);
536 rdm_cpu_id_set(self
, aq_ring_param
->cpu
, aq_ring
->idx
);
537 rdm_rx_desc_dca_en_set(self
, 0U, aq_ring
->idx
);
538 rdm_rx_head_dca_en_set(self
, 0U, aq_ring
->idx
);
539 rdm_rx_pld_dca_en_set(self
, 0U, aq_ring
->idx
);
541 return aq_hw_err_from_flags(self
);
544 static int hw_atl_b0_hw_ring_tx_init(struct aq_hw_s
*self
,
545 struct aq_ring_s
*aq_ring
,
546 struct aq_ring_param_s
*aq_ring_param
)
548 u32 dma_desc_lsw_addr
= (u32
)aq_ring
->dx_ring_pa
;
549 u32 dma_desc_msw_addr
= (u32
)(((u64
)aq_ring
->dx_ring_pa
) >> 32);
551 reg_tx_dma_desc_base_addresslswset(self
, dma_desc_lsw_addr
,
554 reg_tx_dma_desc_base_addressmswset(self
, dma_desc_msw_addr
,
557 tdm_tx_desc_len_set(self
, aq_ring
->size
/ 8U, aq_ring
->idx
);
559 hw_atl_b0_hw_tx_ring_tail_update(self
, aq_ring
);
561 /* Set Tx threshold */
562 tdm_tx_desc_wr_wb_threshold_set(self
, 0U, aq_ring
->idx
);
564 /* Mapping interrupt vector */
565 itr_irq_map_tx_set(self
, aq_ring_param
->vec_idx
, aq_ring
->idx
);
566 itr_irq_map_en_tx_set(self
, true, aq_ring
->idx
);
568 tdm_cpu_id_set(self
, aq_ring_param
->cpu
, aq_ring
->idx
);
569 tdm_tx_desc_dca_en_set(self
, 0U, aq_ring
->idx
);
571 return aq_hw_err_from_flags(self
);
574 static int hw_atl_b0_hw_ring_rx_fill(struct aq_hw_s
*self
,
575 struct aq_ring_s
*ring
,
576 unsigned int sw_tail_old
)
578 for (; sw_tail_old
!= ring
->sw_tail
;
579 sw_tail_old
= aq_ring_next_dx(ring
, sw_tail_old
)) {
580 struct hw_atl_rxd_s
*rxd
=
581 (struct hw_atl_rxd_s
*)&ring
->dx_ring
[sw_tail_old
*
584 struct aq_ring_buff_s
*buff
= &ring
->buff_ring
[sw_tail_old
];
586 rxd
->buf_addr
= buff
->pa
;
590 reg_rx_dma_desc_tail_ptr_set(self
, sw_tail_old
, ring
->idx
);
592 return aq_hw_err_from_flags(self
);
595 static int hw_atl_b0_hw_ring_tx_head_update(struct aq_hw_s
*self
,
596 struct aq_ring_s
*ring
)
599 unsigned int hw_head_
= tdm_tx_desc_head_ptr_get(self
, ring
->idx
);
601 if (aq_utils_obj_test(&self
->header
.flags
, AQ_HW_FLAG_ERR_UNPLUG
)) {
605 ring
->hw_head
= hw_head_
;
606 err
= aq_hw_err_from_flags(self
);
612 static int hw_atl_b0_hw_ring_rx_receive(struct aq_hw_s
*self
,
613 struct aq_ring_s
*ring
)
615 struct device
*ndev
= aq_nic_get_dev(ring
->aq_nic
);
617 for (; ring
->hw_head
!= ring
->sw_tail
;
618 ring
->hw_head
= aq_ring_next_dx(ring
, ring
->hw_head
)) {
619 struct aq_ring_buff_s
*buff
= NULL
;
620 struct hw_atl_rxd_wb_s
*rxd_wb
= (struct hw_atl_rxd_wb_s
*)
621 &ring
->dx_ring
[ring
->hw_head
* HW_ATL_B0_RXD_SIZE
];
623 unsigned int is_err
= 1U;
624 unsigned int is_rx_check_sum_enabled
= 0U;
625 unsigned int pkt_type
= 0U;
627 if (!(rxd_wb
->status
& 0x1U
)) { /* RxD is not done */
631 buff
= &ring
->buff_ring
[ring
->hw_head
];
633 is_err
= (0x0000003CU
& rxd_wb
->status
);
635 is_rx_check_sum_enabled
= (rxd_wb
->type
) & (0x3U
<< 19);
636 is_err
&= ~0x20U
; /* exclude validity bit */
638 pkt_type
= 0xFFU
& (rxd_wb
->type
>> 4);
640 if (is_rx_check_sum_enabled
) {
641 if (0x0U
== (pkt_type
& 0x3U
))
642 buff
->is_ip_cso
= (is_err
& 0x08U
) ? 0U : 1U;
644 if (0x4U
== (pkt_type
& 0x1CU
))
645 buff
->is_udp_cso
= buff
->is_cso_err
? 0U : 1U;
646 else if (0x0U
== (pkt_type
& 0x1CU
))
647 buff
->is_tcp_cso
= buff
->is_cso_err
? 0U : 1U;
652 dma_unmap_page(ndev
, buff
->pa
, buff
->len
, DMA_FROM_DEVICE
);
654 if (is_err
|| rxd_wb
->type
& 0x1000U
) {
655 /* status error or DMA error */
658 if (self
->aq_nic_cfg
->is_rss
) {
660 u16 rss_type
= rxd_wb
->type
& 0xFU
;
662 if (rss_type
&& rss_type
< 0x8U
) {
663 buff
->is_hash_l4
= (rss_type
== 0x4 ||
665 buff
->rss_hash
= rxd_wb
->rss_hash
;
669 if (HW_ATL_B0_RXD_WB_STAT2_EOP
& rxd_wb
->status
) {
670 buff
->len
= rxd_wb
->pkt_len
%
672 buff
->len
= buff
->len
?
673 buff
->len
: AQ_CFG_RX_FRAME_MAX
;
677 if (HW_ATL_B0_RXD_WB_STAT2_RSCCNT
&
680 buff
->next
= rxd_wb
->next_desc_ptr
;
681 ++ring
->stats
.rx
.lro_packets
;
685 aq_ring_next_dx(ring
,
687 ++ring
->stats
.rx
.jumbo_packets
;
693 return aq_hw_err_from_flags(self
);
696 static int hw_atl_b0_hw_irq_enable(struct aq_hw_s
*self
, u64 mask
)
698 itr_irq_msk_setlsw_set(self
, LODWORD(mask
));
699 return aq_hw_err_from_flags(self
);
702 static int hw_atl_b0_hw_irq_disable(struct aq_hw_s
*self
, u64 mask
)
704 itr_irq_msk_clearlsw_set(self
, LODWORD(mask
));
705 itr_irq_status_clearlsw_set(self
, LODWORD(mask
));
707 atomic_inc(&PHAL_ATLANTIC_B0
->dpc
);
708 return aq_hw_err_from_flags(self
);
711 static int hw_atl_b0_hw_irq_read(struct aq_hw_s
*self
, u64
*mask
)
713 *mask
= itr_irq_statuslsw_get(self
);
714 return aq_hw_err_from_flags(self
);
717 #define IS_FILTER_ENABLED(_F_) ((packet_filter & (_F_)) ? 1U : 0U)
719 static int hw_atl_b0_hw_packet_filter_set(struct aq_hw_s
*self
,
720 unsigned int packet_filter
)
724 rpfl2promiscuous_mode_en_set(self
, IS_FILTER_ENABLED(IFF_PROMISC
));
725 rpfl2multicast_flr_en_set(self
,
726 IS_FILTER_ENABLED(IFF_MULTICAST
), 0);
728 rpfl2_accept_all_mc_packets_set(self
,
729 IS_FILTER_ENABLED(IFF_ALLMULTI
));
731 rpfl2broadcast_en_set(self
, IS_FILTER_ENABLED(IFF_BROADCAST
));
733 self
->aq_nic_cfg
->is_mc_list_enabled
= IS_FILTER_ENABLED(IFF_MULTICAST
);
735 for (i
= HW_ATL_B0_MAC_MIN
; i
< HW_ATL_B0_MAC_MAX
; ++i
)
736 rpfl2_uc_flr_en_set(self
,
737 (self
->aq_nic_cfg
->is_mc_list_enabled
&&
738 (i
<= self
->aq_nic_cfg
->mc_list_count
)) ?
741 return aq_hw_err_from_flags(self
);
744 #undef IS_FILTER_ENABLED
746 static int hw_atl_b0_hw_multicast_list_set(struct aq_hw_s
*self
,
748 [AQ_CFG_MULTICAST_ADDRESS_MAX
]
754 if (count
> (HW_ATL_B0_MAC_MAX
- HW_ATL_B0_MAC_MIN
)) {
758 for (self
->aq_nic_cfg
->mc_list_count
= 0U;
759 self
->aq_nic_cfg
->mc_list_count
< count
;
760 ++self
->aq_nic_cfg
->mc_list_count
) {
761 u32 i
= self
->aq_nic_cfg
->mc_list_count
;
762 u32 h
= (ar_mac
[i
][0] << 8) | (ar_mac
[i
][1]);
763 u32 l
= (ar_mac
[i
][2] << 24) | (ar_mac
[i
][3] << 16) |
764 (ar_mac
[i
][4] << 8) | ar_mac
[i
][5];
766 rpfl2_uc_flr_en_set(self
, 0U, HW_ATL_B0_MAC_MIN
+ i
);
768 rpfl2unicast_dest_addresslsw_set(self
,
769 l
, HW_ATL_B0_MAC_MIN
+ i
);
771 rpfl2unicast_dest_addressmsw_set(self
,
772 h
, HW_ATL_B0_MAC_MIN
+ i
);
774 rpfl2_uc_flr_en_set(self
,
775 (self
->aq_nic_cfg
->is_mc_list_enabled
),
776 HW_ATL_B0_MAC_MIN
+ i
);
779 err
= aq_hw_err_from_flags(self
);
785 static int hw_atl_b0_hw_interrupt_moderation_set(struct aq_hw_s
*self
,
790 if (itr_enabled
&& self
->aq_nic_cfg
->itr
) {
791 tdm_tx_desc_wr_wb_irq_en_set(self
, 0U);
792 tdm_tdm_intr_moder_en_set(self
, 1U);
793 rdm_rx_desc_wr_wb_irq_en_set(self
, 0U);
794 rdm_rdm_intr_moder_en_set(self
, 1U);
796 PHAL_ATLANTIC_B0
->itr_tx
= 2U;
797 PHAL_ATLANTIC_B0
->itr_rx
= 2U;
799 if (self
->aq_nic_cfg
->itr
!= 0xFFFFU
) {
800 unsigned int max_timer
= self
->aq_nic_cfg
->itr
/ 2U;
801 unsigned int min_timer
= self
->aq_nic_cfg
->itr
/ 32U;
803 max_timer
= min(0x1FFU
, max_timer
);
804 min_timer
= min(0xFFU
, min_timer
);
806 PHAL_ATLANTIC_B0
->itr_tx
|= min_timer
<< 0x8U
;
807 PHAL_ATLANTIC_B0
->itr_tx
|= max_timer
<< 0x10U
;
808 PHAL_ATLANTIC_B0
->itr_rx
|= min_timer
<< 0x8U
;
809 PHAL_ATLANTIC_B0
->itr_rx
|= max_timer
<< 0x10U
;
811 static unsigned int hw_atl_b0_timers_table_tx_
[][2] = {
812 {0xffU
, 0xffU
}, /* 10Gbit */
813 {0xffU
, 0x1ffU
}, /* 5Gbit */
814 {0xffU
, 0x1ffU
}, /* 5Gbit 5GS */
815 {0xffU
, 0x1ffU
}, /* 2.5Gbit */
816 {0xffU
, 0x1ffU
}, /* 1Gbit */
817 {0xffU
, 0x1ffU
}, /* 100Mbit */
820 static unsigned int hw_atl_b0_timers_table_rx_
[][2] = {
821 {0x6U
, 0x38U
},/* 10Gbit */
822 {0xCU
, 0x70U
},/* 5Gbit */
823 {0xCU
, 0x70U
},/* 5Gbit 5GS */
824 {0x18U
, 0xE0U
},/* 2.5Gbit */
825 {0x30U
, 0x80U
},/* 1Gbit */
826 {0x4U
, 0x50U
},/* 100Mbit */
829 unsigned int speed_index
=
830 hw_atl_utils_mbps_2_speed_index(
831 self
->aq_link_status
.mbps
);
833 PHAL_ATLANTIC_B0
->itr_tx
|=
834 hw_atl_b0_timers_table_tx_
[speed_index
]
835 [0] << 0x8U
; /* set min timer value */
836 PHAL_ATLANTIC_B0
->itr_tx
|=
837 hw_atl_b0_timers_table_tx_
[speed_index
]
838 [1] << 0x10U
; /* set max timer value */
840 PHAL_ATLANTIC_B0
->itr_rx
|=
841 hw_atl_b0_timers_table_rx_
[speed_index
]
842 [0] << 0x8U
; /* set min timer value */
843 PHAL_ATLANTIC_B0
->itr_rx
|=
844 hw_atl_b0_timers_table_rx_
[speed_index
]
845 [1] << 0x10U
; /* set max timer value */
848 tdm_tx_desc_wr_wb_irq_en_set(self
, 1U);
849 tdm_tdm_intr_moder_en_set(self
, 0U);
850 rdm_rx_desc_wr_wb_irq_en_set(self
, 1U);
851 rdm_rdm_intr_moder_en_set(self
, 0U);
852 PHAL_ATLANTIC_B0
->itr_tx
= 0U;
853 PHAL_ATLANTIC_B0
->itr_rx
= 0U;
856 for (i
= HW_ATL_B0_RINGS_MAX
; i
--;) {
857 reg_tx_intr_moder_ctrl_set(self
,
858 PHAL_ATLANTIC_B0
->itr_tx
, i
);
859 reg_rx_intr_moder_ctrl_set(self
,
860 PHAL_ATLANTIC_B0
->itr_rx
, i
);
863 return aq_hw_err_from_flags(self
);
866 static int hw_atl_b0_hw_stop(struct aq_hw_s
*self
)
868 hw_atl_b0_hw_irq_disable(self
, HW_ATL_B0_INT_MASK
);
869 return aq_hw_err_from_flags(self
);
872 static int hw_atl_b0_hw_ring_tx_stop(struct aq_hw_s
*self
,
873 struct aq_ring_s
*ring
)
875 tdm_tx_desc_en_set(self
, 0U, ring
->idx
);
876 return aq_hw_err_from_flags(self
);
879 static int hw_atl_b0_hw_ring_rx_stop(struct aq_hw_s
*self
,
880 struct aq_ring_s
*ring
)
882 rdm_rx_desc_en_set(self
, 0U, ring
->idx
);
883 return aq_hw_err_from_flags(self
);
886 static int hw_atl_b0_hw_set_speed(struct aq_hw_s
*self
, u32 speed
)
890 err
= hw_atl_utils_mpi_set_speed(self
, speed
, MPI_INIT
);
898 static struct aq_hw_ops hw_atl_ops_
= {
899 .create
= hw_atl_b0_create
,
900 .destroy
= hw_atl_b0_destroy
,
901 .get_hw_caps
= hw_atl_b0_get_hw_caps
,
903 .hw_get_mac_permanent
= hw_atl_utils_get_mac_permanent
,
904 .hw_set_mac_address
= hw_atl_b0_hw_mac_addr_set
,
905 .hw_get_link_status
= hw_atl_utils_mpi_get_link_status
,
906 .hw_set_link_speed
= hw_atl_b0_hw_set_speed
,
907 .hw_init
= hw_atl_b0_hw_init
,
908 .hw_deinit
= hw_atl_utils_hw_deinit
,
909 .hw_set_power
= hw_atl_utils_hw_set_power
,
910 .hw_reset
= hw_atl_b0_hw_reset
,
911 .hw_start
= hw_atl_b0_hw_start
,
912 .hw_ring_tx_start
= hw_atl_b0_hw_ring_tx_start
,
913 .hw_ring_tx_stop
= hw_atl_b0_hw_ring_tx_stop
,
914 .hw_ring_rx_start
= hw_atl_b0_hw_ring_rx_start
,
915 .hw_ring_rx_stop
= hw_atl_b0_hw_ring_rx_stop
,
916 .hw_stop
= hw_atl_b0_hw_stop
,
918 .hw_ring_tx_xmit
= hw_atl_b0_hw_ring_tx_xmit
,
919 .hw_ring_tx_head_update
= hw_atl_b0_hw_ring_tx_head_update
,
921 .hw_ring_rx_receive
= hw_atl_b0_hw_ring_rx_receive
,
922 .hw_ring_rx_fill
= hw_atl_b0_hw_ring_rx_fill
,
924 .hw_irq_enable
= hw_atl_b0_hw_irq_enable
,
925 .hw_irq_disable
= hw_atl_b0_hw_irq_disable
,
926 .hw_irq_read
= hw_atl_b0_hw_irq_read
,
928 .hw_ring_rx_init
= hw_atl_b0_hw_ring_rx_init
,
929 .hw_ring_tx_init
= hw_atl_b0_hw_ring_tx_init
,
930 .hw_packet_filter_set
= hw_atl_b0_hw_packet_filter_set
,
931 .hw_multicast_list_set
= hw_atl_b0_hw_multicast_list_set
,
932 .hw_interrupt_moderation_set
= hw_atl_b0_hw_interrupt_moderation_set
,
933 .hw_rss_set
= hw_atl_b0_hw_rss_set
,
934 .hw_rss_hash_set
= hw_atl_b0_hw_rss_hash_set
,
935 .hw_get_regs
= hw_atl_utils_hw_get_regs
,
936 .hw_get_hw_stats
= hw_atl_utils_get_hw_stats
,
937 .hw_get_fw_version
= hw_atl_utils_get_fw_version
,
940 struct aq_hw_ops
*hw_atl_b0_get_ops_by_id(struct pci_dev
*pdev
)
942 bool is_vid_ok
= (pdev
->vendor
== PCI_VENDOR_ID_AQUANTIA
);
943 bool is_did_ok
= ((pdev
->device
== HW_ATL_DEVICE_ID_0001
) ||
944 (pdev
->device
== HW_ATL_DEVICE_ID_D100
) ||
945 (pdev
->device
== HW_ATL_DEVICE_ID_D107
) ||
946 (pdev
->device
== HW_ATL_DEVICE_ID_D108
) ||
947 (pdev
->device
== HW_ATL_DEVICE_ID_D109
));
949 bool is_rev_ok
= (pdev
->revision
== 2U);
951 return (is_vid_ok
&& is_did_ok
&& is_rev_ok
) ? &hw_atl_ops_
: NULL
;