2 * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved.
4 * Derived from Intel e1000 driver
5 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 2 of the License, or (at your option)
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 59
19 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/types.h>
28 #include <linux/errno.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/ioport.h>
35 #include <linux/slab.h>
36 #include <linux/list.h>
37 #include <linux/delay.h>
38 #include <linux/sched.h>
41 #include <linux/ipv6.h>
42 #include <linux/udp.h>
43 #include <linux/mii.h>
45 #include <linux/vmalloc.h>
46 #include <linux/pagemap.h>
47 #include <linux/tcp.h>
48 #include <linux/ethtool.h>
49 #include <linux/if_vlan.h>
50 #include <linux/workqueue.h>
51 #include <net/checksum.h>
52 #include <net/ip6_checksum.h>
56 /* Wake Up Filter Control */
57 #define AT_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
58 #define AT_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
59 #define AT_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
60 #define AT_WUFC_MC 0x00000008 /* Multicast Wakeup Enable */
61 #define AT_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
63 #define AT_VLAN_TO_TAG(_vlan, _tag) \
64 _tag = ((((_vlan) >> 8) & 0xFF) |\
65 (((_vlan) & 0xFF) << 8))
67 #define AT_TAG_TO_VLAN(_tag, _vlan) \
68 _vlan = ((((_tag) >> 8) & 0xFF) |\
69 (((_tag) & 0xFF) << 8))
71 #define SPEED_0 0xffff
75 #define AT_RX_BUF_SIZE (ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN)
76 #define MAX_JUMBO_FRAME_SIZE (6*1024)
77 #define MAX_TSO_FRAME_SIZE (7*1024)
78 #define MAX_TX_OFFLOAD_THRESH (9*1024)
80 #define AT_MAX_RECEIVE_QUEUE 4
81 #define AT_DEF_RECEIVE_QUEUE 1
82 #define AT_MAX_TRANSMIT_QUEUE 2
84 #define AT_DMA_HI_ADDR_MASK 0xffffffff00000000ULL
85 #define AT_DMA_LO_ADDR_MASK 0x00000000ffffffffULL
87 #define AT_TX_WATCHDOG (5 * HZ)
88 #define AT_MAX_INT_WORK 5
89 #define AT_TWSI_EEPROM_TIMEOUT 100
90 #define AT_HW_MAX_IDLE_DELAY 10
91 #define AT_SUSPEND_LINK_TIMEOUT 100
93 #define AT_ASPM_L0S_TIMER 6
94 #define AT_ASPM_L1_TIMER 12
95 #define AT_LCKDET_TIMER 12
97 #define ATL1C_PCIE_L0S_L1_DISABLE 0x01
98 #define ATL1C_PCIE_PHY_RESET 0x02
100 #define ATL1C_ASPM_L0s_ENABLE 0x0001
101 #define ATL1C_ASPM_L1_ENABLE 0x0002
103 #define AT_REGS_LEN (74 * sizeof(u32))
104 #define AT_EEPROM_LEN 512
106 #define ATL1C_GET_DESC(R, i, type) (&(((type *)((R)->desc))[i]))
107 #define ATL1C_RFD_DESC(R, i) ATL1C_GET_DESC(R, i, struct atl1c_rx_free_desc)
108 #define ATL1C_TPD_DESC(R, i) ATL1C_GET_DESC(R, i, struct atl1c_tpd_desc)
109 #define ATL1C_RRD_DESC(R, i) ATL1C_GET_DESC(R, i, struct atl1c_recv_ret_status)
111 /* tpd word 1 bit 0:7 General Checksum task offload */
112 #define TPD_L4HDR_OFFSET_MASK 0x00FF
113 #define TPD_L4HDR_OFFSET_SHIFT 0
115 /* tpd word 1 bit 0:7 Large Send task offload (IPv4/IPV6) */
116 #define TPD_TCPHDR_OFFSET_MASK 0x00FF
117 #define TPD_TCPHDR_OFFSET_SHIFT 0
119 /* tpd word 1 bit 0:7 Custom Checksum task offload */
120 #define TPD_PLOADOFFSET_MASK 0x00FF
121 #define TPD_PLOADOFFSET_SHIFT 0
123 /* tpd word 1 bit 8:17 */
124 #define TPD_CCSUM_EN_MASK 0x0001
125 #define TPD_CCSUM_EN_SHIFT 8
126 #define TPD_IP_CSUM_MASK 0x0001
127 #define TPD_IP_CSUM_SHIFT 9
128 #define TPD_TCP_CSUM_MASK 0x0001
129 #define TPD_TCP_CSUM_SHIFT 10
130 #define TPD_UDP_CSUM_MASK 0x0001
131 #define TPD_UDP_CSUM_SHIFT 11
132 #define TPD_LSO_EN_MASK 0x0001 /* TCP Large Send Offload */
133 #define TPD_LSO_EN_SHIFT 12
134 #define TPD_LSO_VER_MASK 0x0001
135 #define TPD_LSO_VER_SHIFT 13 /* 0 : ipv4; 1 : ipv4/ipv6 */
136 #define TPD_CON_VTAG_MASK 0x0001
137 #define TPD_CON_VTAG_SHIFT 14
138 #define TPD_INS_VTAG_MASK 0x0001
139 #define TPD_INS_VTAG_SHIFT 15
140 #define TPD_IPV4_PACKET_MASK 0x0001 /* valid when LSO VER is 1 */
141 #define TPD_IPV4_PACKET_SHIFT 16
142 #define TPD_ETH_TYPE_MASK 0x0001
143 #define TPD_ETH_TYPE_SHIFT 17 /* 0 : 802.3 frame; 1 : Ethernet */
145 /* tpd word 18:25 Custom Checksum task offload */
146 #define TPD_CCSUM_OFFSET_MASK 0x00FF
147 #define TPD_CCSUM_OFFSET_SHIFT 18
148 #define TPD_CCSUM_EPAD_MASK 0x0001
149 #define TPD_CCSUM_EPAD_SHIFT 30
151 /* tpd word 18:30 Large Send task offload (IPv4/IPV6) */
152 #define TPD_MSS_MASK 0x1FFF
153 #define TPD_MSS_SHIFT 18
155 #define TPD_EOP_MASK 0x0001
156 #define TPD_EOP_SHIFT 31
158 struct atl1c_tpd_desc
{
159 __le16 buffer_len
; /* include 4-byte CRC */
165 struct atl1c_tpd_ext_desc
{
171 /* rrs word 0 bit 0:31 */
172 #define RRS_RX_CSUM_MASK 0xFFFF
173 #define RRS_RX_CSUM_SHIFT 0
174 #define RRS_RX_RFD_CNT_MASK 0x000F
175 #define RRS_RX_RFD_CNT_SHIFT 16
176 #define RRS_RX_RFD_INDEX_MASK 0x0FFF
177 #define RRS_RX_RFD_INDEX_SHIFT 20
179 /* rrs flag bit 0:16 */
180 #define RRS_HEAD_LEN_MASK 0x00FF
181 #define RRS_HEAD_LEN_SHIFT 0
182 #define RRS_HDS_TYPE_MASK 0x0003
183 #define RRS_HDS_TYPE_SHIFT 8
184 #define RRS_CPU_NUM_MASK 0x0003
185 #define RRS_CPU_NUM_SHIFT 10
186 #define RRS_HASH_FLG_MASK 0x000F
187 #define RRS_HASH_FLG_SHIFT 12
189 #define RRS_HDS_TYPE_HEAD 1
190 #define RRS_HDS_TYPE_DATA 2
192 #define RRS_IS_NO_HDS_TYPE(flag) \
193 ((((flag) >> (RRS_HDS_TYPE_SHIFT)) & RRS_HDS_TYPE_MASK) == 0)
195 #define RRS_IS_HDS_HEAD(flag) \
196 ((((flag) >> (RRS_HDS_TYPE_SHIFT)) & RRS_HDS_TYPE_MASK) == \
199 #define RRS_IS_HDS_DATA(flag) \
200 ((((flag) >> (RRS_HDS_TYPE_SHIFT)) & RRS_HDS_TYPE_MASK) == \
203 /* rrs word 3 bit 0:31 */
204 #define RRS_PKT_SIZE_MASK 0x3FFF
205 #define RRS_PKT_SIZE_SHIFT 0
206 #define RRS_ERR_L4_CSUM_MASK 0x0001
207 #define RRS_ERR_L4_CSUM_SHIFT 14
208 #define RRS_ERR_IP_CSUM_MASK 0x0001
209 #define RRS_ERR_IP_CSUM_SHIFT 15
210 #define RRS_VLAN_INS_MASK 0x0001
211 #define RRS_VLAN_INS_SHIFT 16
212 #define RRS_PROT_ID_MASK 0x0007
213 #define RRS_PROT_ID_SHIFT 17
214 #define RRS_RX_ERR_SUM_MASK 0x0001
215 #define RRS_RX_ERR_SUM_SHIFT 20
216 #define RRS_RX_ERR_CRC_MASK 0x0001
217 #define RRS_RX_ERR_CRC_SHIFT 21
218 #define RRS_RX_ERR_FAE_MASK 0x0001
219 #define RRS_RX_ERR_FAE_SHIFT 22
220 #define RRS_RX_ERR_TRUNC_MASK 0x0001
221 #define RRS_RX_ERR_TRUNC_SHIFT 23
222 #define RRS_RX_ERR_RUNC_MASK 0x0001
223 #define RRS_RX_ERR_RUNC_SHIFT 24
224 #define RRS_RX_ERR_ICMP_MASK 0x0001
225 #define RRS_RX_ERR_ICMP_SHIFT 25
226 #define RRS_PACKET_BCAST_MASK 0x0001
227 #define RRS_PACKET_BCAST_SHIFT 26
228 #define RRS_PACKET_MCAST_MASK 0x0001
229 #define RRS_PACKET_MCAST_SHIFT 27
230 #define RRS_PACKET_TYPE_MASK 0x0001
231 #define RRS_PACKET_TYPE_SHIFT 28
232 #define RRS_FIFO_FULL_MASK 0x0001
233 #define RRS_FIFO_FULL_SHIFT 29
234 #define RRS_802_3_LEN_ERR_MASK 0x0001
235 #define RRS_802_3_LEN_ERR_SHIFT 30
236 #define RRS_RXD_UPDATED_MASK 0x0001
237 #define RRS_RXD_UPDATED_SHIFT 31
239 #define RRS_ERR_L4_CSUM 0x00004000
240 #define RRS_ERR_IP_CSUM 0x00008000
241 #define RRS_VLAN_INS 0x00010000
242 #define RRS_RX_ERR_SUM 0x00100000
243 #define RRS_RX_ERR_CRC 0x00200000
244 #define RRS_802_3_LEN_ERR 0x40000000
245 #define RRS_RXD_UPDATED 0x80000000
247 #define RRS_PACKET_TYPE_802_3 1
248 #define RRS_PACKET_TYPE_ETH 0
249 #define RRS_PACKET_IS_ETH(word) \
250 ((((word) >> RRS_PACKET_TYPE_SHIFT) & RRS_PACKET_TYPE_MASK) == \
252 #define RRS_RXD_IS_VALID(word) \
253 ((((word) >> RRS_RXD_UPDATED_SHIFT) & RRS_RXD_UPDATED_MASK) == 1)
255 #define RRS_PACKET_PROT_IS_IPV4_ONLY(word) \
256 ((((word) >> RRS_PROT_ID_SHIFT) & RRS_PROT_ID_MASK) == 1)
257 #define RRS_PACKET_PROT_IS_IPV6_ONLY(word) \
258 ((((word) >> RRS_PROT_ID_SHIFT) & RRS_PROT_ID_MASK) == 6)
260 struct atl1c_recv_ret_status
{
269 struct atl1c_rx_free_desc
{
273 /* DMA Order Settings */
274 enum atl1c_dma_order
{
275 atl1c_dma_ord_in
= 1,
276 atl1c_dma_ord_enh
= 2,
277 atl1c_dma_ord_out
= 4
285 enum atl1c_mac_speed
{
286 atl1c_mac_speed_0
= 0,
287 atl1c_mac_speed_10_100
= 1,
288 atl1c_mac_speed_1000
= 2
291 enum atl1c_dma_req_block
{
292 atl1c_dma_req_128
= 0,
293 atl1c_dma_req_256
= 1,
294 atl1c_dma_req_512
= 2,
295 atl1c_dma_req_1024
= 3,
296 atl1c_dma_req_2048
= 4,
297 atl1c_dma_req_4096
= 5
301 enum atl1c_nic_type
{
310 enum atl1c_trans_queue
{
311 atl1c_trans_normal
= 0,
315 struct atl1c_hw_stats
{
317 unsigned long rx_ok
; /* The number of good packet received. */
318 unsigned long rx_bcast
; /* The number of good broadcast packet received. */
319 unsigned long rx_mcast
; /* The number of good multicast packet received. */
320 unsigned long rx_pause
; /* The number of Pause packet received. */
321 unsigned long rx_ctrl
; /* The number of Control packet received other than Pause frame. */
322 unsigned long rx_fcs_err
; /* The number of packets with bad FCS. */
323 unsigned long rx_len_err
; /* The number of packets with mismatch of length field and actual size. */
324 unsigned long rx_byte_cnt
; /* The number of bytes of good packet received. FCS is NOT included. */
325 unsigned long rx_runt
; /* The number of packets received that are less than 64 byte long and with good FCS. */
326 unsigned long rx_frag
; /* The number of packets received that are less than 64 byte long and with bad FCS. */
327 unsigned long rx_sz_64
; /* The number of good and bad packets received that are 64 byte long. */
328 unsigned long rx_sz_65_127
; /* The number of good and bad packets received that are between 65 and 127-byte long. */
329 unsigned long rx_sz_128_255
; /* The number of good and bad packets received that are between 128 and 255-byte long. */
330 unsigned long rx_sz_256_511
; /* The number of good and bad packets received that are between 256 and 511-byte long. */
331 unsigned long rx_sz_512_1023
; /* The number of good and bad packets received that are between 512 and 1023-byte long. */
332 unsigned long rx_sz_1024_1518
; /* The number of good and bad packets received that are between 1024 and 1518-byte long. */
333 unsigned long rx_sz_1519_max
; /* The number of good and bad packets received that are between 1519-byte and MTU. */
334 unsigned long rx_sz_ov
; /* The number of good and bad packets received that are more than MTU size truncated by Selene. */
335 unsigned long rx_rxf_ov
; /* The number of frame dropped due to occurrence of RX FIFO overflow. */
336 unsigned long rx_rrd_ov
; /* The number of frame dropped due to occurrence of RRD overflow. */
337 unsigned long rx_align_err
; /* Alignment Error */
338 unsigned long rx_bcast_byte_cnt
; /* The byte count of broadcast packet received, excluding FCS. */
339 unsigned long rx_mcast_byte_cnt
; /* The byte count of multicast packet received, excluding FCS. */
340 unsigned long rx_err_addr
; /* The number of packets dropped due to address filtering. */
343 unsigned long tx_ok
; /* The number of good packet transmitted. */
344 unsigned long tx_bcast
; /* The number of good broadcast packet transmitted. */
345 unsigned long tx_mcast
; /* The number of good multicast packet transmitted. */
346 unsigned long tx_pause
; /* The number of Pause packet transmitted. */
347 unsigned long tx_exc_defer
; /* The number of packets transmitted with excessive deferral. */
348 unsigned long tx_ctrl
; /* The number of packets transmitted is a control frame, excluding Pause frame. */
349 unsigned long tx_defer
; /* The number of packets transmitted that is deferred. */
350 unsigned long tx_byte_cnt
; /* The number of bytes of data transmitted. FCS is NOT included. */
351 unsigned long tx_sz_64
; /* The number of good and bad packets transmitted that are 64 byte long. */
352 unsigned long tx_sz_65_127
; /* The number of good and bad packets transmitted that are between 65 and 127-byte long. */
353 unsigned long tx_sz_128_255
; /* The number of good and bad packets transmitted that are between 128 and 255-byte long. */
354 unsigned long tx_sz_256_511
; /* The number of good and bad packets transmitted that are between 256 and 511-byte long. */
355 unsigned long tx_sz_512_1023
; /* The number of good and bad packets transmitted that are between 512 and 1023-byte long. */
356 unsigned long tx_sz_1024_1518
; /* The number of good and bad packets transmitted that are between 1024 and 1518-byte long. */
357 unsigned long tx_sz_1519_max
; /* The number of good and bad packets transmitted that are between 1519-byte and MTU. */
358 unsigned long tx_1_col
; /* The number of packets subsequently transmitted successfully with a single prior collision. */
359 unsigned long tx_2_col
; /* The number of packets subsequently transmitted successfully with multiple prior collisions. */
360 unsigned long tx_late_col
; /* The number of packets transmitted with late collisions. */
361 unsigned long tx_abort_col
; /* The number of transmit packets aborted due to excessive collisions. */
362 unsigned long tx_underrun
; /* The number of transmit packets aborted due to transmit FIFO underrun, or TRD FIFO underrun */
363 unsigned long tx_rd_eop
; /* The number of times that read beyond the EOP into the next frame area when TRD was not written timely */
364 unsigned long tx_len_err
; /* The number of transmit packets with length field does NOT match the actual frame size. */
365 unsigned long tx_trunc
; /* The number of transmit packets truncated due to size exceeding MTU. */
366 unsigned long tx_bcast_byte
; /* The byte count of broadcast packet transmitted, excluding FCS. */
367 unsigned long tx_mcast_byte
; /* The byte count of multicast packet transmitted, excluding FCS. */
371 u8 __iomem
*hw_addr
; /* inner register address */
372 struct atl1c_adapter
*adapter
;
373 enum atl1c_nic_type nic_type
;
374 enum atl1c_dma_order dma_order
;
375 enum atl1c_dma_rcb rcb_value
;
376 enum atl1c_dma_req_block dmar_block
;
381 u16 subsystem_vendor_id
;
394 enum atl1c_mac_speed mac_speed
;
398 #define MEDIA_TYPE_AUTO_SENSOR 0
399 #define MEDIA_TYPE_100M_FULL 1
400 #define MEDIA_TYPE_100M_HALF 2
401 #define MEDIA_TYPE_10M_FULL 3
402 #define MEDIA_TYPE_10M_HALF 4
404 u16 autoneg_advertised
;
405 u16 mii_autoneg_adv_reg
;
406 u16 mii_1000t_ctrl_reg
;
408 u16 tx_imt
; /* TX Interrupt Moderator timer ( 2us resolution) */
409 u16 rx_imt
; /* RX Interrupt Moderator timer ( 2us resolution) */
410 u16 ict
; /* Interrupt Clear timer (2us resolution) */
412 #define ATL1C_INTR_CLEAR_ON_READ 0x0001
413 #define ATL1C_INTR_MODRT_ENABLE 0x0002
414 #define ATL1C_CMB_ENABLE 0x0004
415 #define ATL1C_SMB_ENABLE 0x0010
416 #define ATL1C_TXQ_MODE_ENHANCE 0x0020
417 #define ATL1C_RX_IPV6_CHKSUM 0x0040
418 #define ATL1C_ASPM_L0S_SUPPORT 0x0080
419 #define ATL1C_ASPM_L1_SUPPORT 0x0100
420 #define ATL1C_ASPM_CTRL_MON 0x0200
421 #define ATL1C_HIB_DISABLE 0x0400
422 #define ATL1C_APS_MODE_ENABLE 0x0800
423 #define ATL1C_LINK_EXT_SYNC 0x1000
424 #define ATL1C_CLK_GATING_EN 0x2000
425 #define ATL1C_FPGA_VERSION 0x8000
427 #define ATL1C_LINK_CAP_1000M 0x0001
430 u16 rrd_thresh
; /* Threshold of number of RRD produced to trigger
433 u8 tpd_burst
; /* Number of TPD to prefetch in cache-aligned burst. */
437 u8 mac_addr
[ETH_ALEN
];
438 u8 perm_mac_addr
[ETH_ALEN
];
446 * atl1c_ring_header represents a single, contiguous block of DMA space
447 * mapped for the three descriptor rings (tpd, rfd, rrd) described below
449 struct atl1c_ring_header
{
450 void *desc
; /* virtual address */
451 dma_addr_t dma
; /* physical address*/
452 unsigned int size
; /* length in bytes */
456 * atl1c_buffer is wrapper around a pointer to a socket buffer
457 * so a DMA handle can be stored along with the skb
459 struct atl1c_buffer
{
460 struct sk_buff
*skb
; /* socket buffer */
461 u16 length
; /* rx buffer length */
462 u16 flags
; /* information of buffer */
463 #define ATL1C_BUFFER_FREE 0x0001
464 #define ATL1C_BUFFER_BUSY 0x0002
465 #define ATL1C_BUFFER_STATE_MASK 0x0003
467 #define ATL1C_PCIMAP_SINGLE 0x0004
468 #define ATL1C_PCIMAP_PAGE 0x0008
469 #define ATL1C_PCIMAP_TYPE_MASK 0x000C
471 #define ATL1C_PCIMAP_TODEVICE 0x0010
472 #define ATL1C_PCIMAP_FROMDEVICE 0x0020
473 #define ATL1C_PCIMAP_DIRECTION_MASK 0x0030
477 #define ATL1C_SET_BUFFER_STATE(buff, state) do { \
478 ((buff)->flags) &= ~ATL1C_BUFFER_STATE_MASK; \
479 ((buff)->flags) |= (state); \
482 #define ATL1C_SET_PCIMAP_TYPE(buff, type, direction) do { \
483 ((buff)->flags) &= ~ATL1C_PCIMAP_TYPE_MASK; \
484 ((buff)->flags) |= (type); \
485 ((buff)->flags) &= ~ATL1C_PCIMAP_DIRECTION_MASK; \
486 ((buff)->flags) |= (direction); \
489 /* transimit packet descriptor (tpd) ring */
490 struct atl1c_tpd_ring
{
491 void *desc
; /* descriptor ring virtual address */
492 dma_addr_t dma
; /* descriptor ring physical address */
493 u16 size
; /* descriptor ring length in bytes */
494 u16 count
; /* number of descriptors in the ring */
495 u16 next_to_use
; /* this is protectd by adapter->tx_lock */
496 atomic_t next_to_clean
;
497 struct atl1c_buffer
*buffer_info
;
500 /* receive free descriptor (rfd) ring */
501 struct atl1c_rfd_ring
{
502 void *desc
; /* descriptor ring virtual address */
503 dma_addr_t dma
; /* descriptor ring physical address */
504 u16 size
; /* descriptor ring length in bytes */
505 u16 count
; /* number of descriptors in the ring */
508 struct atl1c_buffer
*buffer_info
;
511 /* receive return descriptor (rrd) ring */
512 struct atl1c_rrd_ring
{
513 void *desc
; /* descriptor ring virtual address */
514 dma_addr_t dma
; /* descriptor ring physical address */
515 u16 size
; /* descriptor ring length in bytes */
516 u16 count
; /* number of descriptors in the ring */
521 /* board specific private data structure */
522 struct atl1c_adapter
{
523 struct net_device
*netdev
;
524 struct pci_dev
*pdev
;
525 struct napi_struct napi
;
527 struct atl1c_hw_stats hw_stats
;
528 struct mii_if_info mii
; /* MII interface info */
532 #define __AT_TESTING 0x0001
533 #define __AT_RESETTING 0x0002
534 #define __AT_DOWN 0x0003
535 unsigned long work_event
;
536 #define ATL1C_WORK_EVENT_RESET 0
537 #define ATL1C_WORK_EVENT_LINK_CHANGE 1
545 spinlock_t mdio_lock
;
549 struct work_struct common_task
;
550 struct timer_list watchdog_timer
;
551 struct timer_list phy_config_timer
;
553 /* All Descriptor memory */
554 struct atl1c_ring_header ring_header
;
555 struct atl1c_tpd_ring tpd_ring
[AT_MAX_TRANSMIT_QUEUE
];
556 struct atl1c_rfd_ring rfd_ring
;
557 struct atl1c_rrd_ring rrd_ring
;
558 u32 bd_number
; /* board number;*/
561 #define AT_WRITE_REG(a, reg, value) ( \
562 writel((value), ((a)->hw_addr + reg)))
564 #define AT_WRITE_FLUSH(a) (\
567 #define AT_READ_REG(a, reg, pdata) do { \
568 if (unlikely((a)->hibernate)) { \
569 readl((a)->hw_addr + reg); \
570 *(u32 *)pdata = readl((a)->hw_addr + reg); \
572 *(u32 *)pdata = readl((a)->hw_addr + reg); \
576 #define AT_WRITE_REGB(a, reg, value) (\
577 writeb((value), ((a)->hw_addr + reg)))
579 #define AT_READ_REGB(a, reg) (\
580 readb((a)->hw_addr + reg))
582 #define AT_WRITE_REGW(a, reg, value) (\
583 writew((value), ((a)->hw_addr + reg)))
585 #define AT_READ_REGW(a, reg, pdata) do { \
586 if (unlikely((a)->hibernate)) { \
587 readw((a)->hw_addr + reg); \
588 *(u16 *)pdata = readw((a)->hw_addr + reg); \
590 *(u16 *)pdata = readw((a)->hw_addr + reg); \
594 #define AT_WRITE_REG_ARRAY(a, reg, offset, value) ( \
595 writel((value), (((a)->hw_addr + reg) + ((offset) << 2))))
597 #define AT_READ_REG_ARRAY(a, reg, offset) ( \
598 readl(((a)->hw_addr + reg) + ((offset) << 2)))
600 extern char atl1c_driver_name
[];
601 extern char atl1c_driver_version
[];
603 extern void atl1c_reinit_locked(struct atl1c_adapter
*adapter
);
604 extern s32
atl1c_reset_hw(struct atl1c_hw
*hw
);
605 extern void atl1c_set_ethtool_ops(struct net_device
*netdev
);
606 #endif /* _ATL1C_H_ */