1 /* b44.c: Broadcom 44xx/47xx Fast Ethernet device driver.
3 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
4 * Copyright (C) 2004 Pekka Pietikainen (pp@ee.oulu.fi)
5 * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
6 * Copyright (C) 2006 Felix Fietkau (nbd@openwrt.org)
7 * Copyright (C) 2006 Broadcom Corporation.
8 * Copyright (C) 2007 Michael Buesch <m@bues.ch>
10 * Distribute under GPL.
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/moduleparam.h>
18 #include <linux/types.h>
19 #include <linux/netdevice.h>
20 #include <linux/ethtool.h>
21 #include <linux/mii.h>
22 #include <linux/if_ether.h>
23 #include <linux/if_vlan.h>
24 #include <linux/etherdevice.h>
25 #include <linux/pci.h>
26 #include <linux/delay.h>
27 #include <linux/init.h>
28 #include <linux/interrupt.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/ssb/ssb.h>
31 #include <linux/slab.h>
33 #include <asm/uaccess.h>
40 #define DRV_MODULE_NAME "b44"
41 #define DRV_MODULE_VERSION "2.0"
42 #define DRV_DESCRIPTION "Broadcom 44xx/47xx 10/100 PCI ethernet driver"
44 #define B44_DEF_MSG_ENABLE \
54 /* length of time before we decide the hardware is borked,
55 * and dev->tx_timeout() should be called to fix the problem
57 #define B44_TX_TIMEOUT (5 * HZ)
59 /* hardware minimum and maximum for a single frame's data payload */
60 #define B44_MIN_MTU 60
61 #define B44_MAX_MTU 1500
63 #define B44_RX_RING_SIZE 512
64 #define B44_DEF_RX_RING_PENDING 200
65 #define B44_RX_RING_BYTES (sizeof(struct dma_desc) * \
67 #define B44_TX_RING_SIZE 512
68 #define B44_DEF_TX_RING_PENDING (B44_TX_RING_SIZE - 1)
69 #define B44_TX_RING_BYTES (sizeof(struct dma_desc) * \
72 #define TX_RING_GAP(BP) \
73 (B44_TX_RING_SIZE - (BP)->tx_pending)
74 #define TX_BUFFS_AVAIL(BP) \
75 (((BP)->tx_cons <= (BP)->tx_prod) ? \
76 (BP)->tx_cons + (BP)->tx_pending - (BP)->tx_prod : \
77 (BP)->tx_cons - (BP)->tx_prod - TX_RING_GAP(BP))
78 #define NEXT_TX(N) (((N) + 1) & (B44_TX_RING_SIZE - 1))
80 #define RX_PKT_OFFSET (RX_HEADER_LEN + 2)
81 #define RX_PKT_BUF_SZ (1536 + RX_PKT_OFFSET)
83 /* minimum number of free TX descriptors required to wake up TX process */
84 #define B44_TX_WAKEUP_THRESH (B44_TX_RING_SIZE / 4)
86 /* b44 internal pattern match filter info */
87 #define B44_PATTERN_BASE 0x400
88 #define B44_PATTERN_SIZE 0x80
89 #define B44_PMASK_BASE 0x600
90 #define B44_PMASK_SIZE 0x10
91 #define B44_MAX_PATTERNS 16
92 #define B44_ETHIPV6UDP_HLEN 62
93 #define B44_ETHIPV4UDP_HLEN 42
95 MODULE_AUTHOR("Felix Fietkau, Florian Schirmer, Pekka Pietikainen, David S. Miller");
96 MODULE_DESCRIPTION(DRV_DESCRIPTION
);
97 MODULE_LICENSE("GPL");
98 MODULE_VERSION(DRV_MODULE_VERSION
);
100 static int b44_debug
= -1; /* -1 == use B44_DEF_MSG_ENABLE as value */
101 module_param(b44_debug
, int, 0);
102 MODULE_PARM_DESC(b44_debug
, "B44 bitmapped debugging message enable value");
105 #ifdef CONFIG_B44_PCI
106 static DEFINE_PCI_DEVICE_TABLE(b44_pci_tbl
) = {
107 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_BCM4401
) },
108 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_BCM4401B0
) },
109 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_BCM4401B1
) },
110 { 0 } /* terminate list with empty entry */
112 MODULE_DEVICE_TABLE(pci
, b44_pci_tbl
);
114 static struct pci_driver b44_pci_driver
= {
115 .name
= DRV_MODULE_NAME
,
116 .id_table
= b44_pci_tbl
,
118 #endif /* CONFIG_B44_PCI */
120 static const struct ssb_device_id b44_ssb_tbl
[] = {
121 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_ETHERNET
, SSB_ANY_REV
),
124 MODULE_DEVICE_TABLE(ssb
, b44_ssb_tbl
);
126 static void b44_halt(struct b44
*);
127 static void b44_init_rings(struct b44
*);
129 #define B44_FULL_RESET 1
130 #define B44_FULL_RESET_SKIP_PHY 2
131 #define B44_PARTIAL_RESET 3
132 #define B44_CHIP_RESET_FULL 4
133 #define B44_CHIP_RESET_PARTIAL 5
135 static void b44_init_hw(struct b44
*, int);
137 static int dma_desc_sync_size
;
140 static const char b44_gstrings
[][ETH_GSTRING_LEN
] = {
141 #define _B44(x...) # x,
146 static inline void b44_sync_dma_desc_for_device(struct ssb_device
*sdev
,
148 unsigned long offset
,
149 enum dma_data_direction dir
)
151 dma_sync_single_for_device(sdev
->dma_dev
, dma_base
+ offset
,
152 dma_desc_sync_size
, dir
);
155 static inline void b44_sync_dma_desc_for_cpu(struct ssb_device
*sdev
,
157 unsigned long offset
,
158 enum dma_data_direction dir
)
160 dma_sync_single_for_cpu(sdev
->dma_dev
, dma_base
+ offset
,
161 dma_desc_sync_size
, dir
);
164 static inline unsigned long br32(const struct b44
*bp
, unsigned long reg
)
166 return ssb_read32(bp
->sdev
, reg
);
169 static inline void bw32(const struct b44
*bp
,
170 unsigned long reg
, unsigned long val
)
172 ssb_write32(bp
->sdev
, reg
, val
);
175 static int b44_wait_bit(struct b44
*bp
, unsigned long reg
,
176 u32 bit
, unsigned long timeout
, const int clear
)
180 for (i
= 0; i
< timeout
; i
++) {
181 u32 val
= br32(bp
, reg
);
183 if (clear
&& !(val
& bit
))
185 if (!clear
&& (val
& bit
))
191 netdev_err(bp
->dev
, "BUG! Timeout waiting for bit %08x of register %lx to %s\n",
192 bit
, reg
, clear
? "clear" : "set");
199 static inline void __b44_cam_read(struct b44
*bp
, unsigned char *data
, int index
)
203 bw32(bp
, B44_CAM_CTRL
, (CAM_CTRL_READ
|
204 (index
<< CAM_CTRL_INDEX_SHIFT
)));
206 b44_wait_bit(bp
, B44_CAM_CTRL
, CAM_CTRL_BUSY
, 100, 1);
208 val
= br32(bp
, B44_CAM_DATA_LO
);
210 data
[2] = (val
>> 24) & 0xFF;
211 data
[3] = (val
>> 16) & 0xFF;
212 data
[4] = (val
>> 8) & 0xFF;
213 data
[5] = (val
>> 0) & 0xFF;
215 val
= br32(bp
, B44_CAM_DATA_HI
);
217 data
[0] = (val
>> 8) & 0xFF;
218 data
[1] = (val
>> 0) & 0xFF;
221 static inline void __b44_cam_write(struct b44
*bp
, unsigned char *data
, int index
)
225 val
= ((u32
) data
[2]) << 24;
226 val
|= ((u32
) data
[3]) << 16;
227 val
|= ((u32
) data
[4]) << 8;
228 val
|= ((u32
) data
[5]) << 0;
229 bw32(bp
, B44_CAM_DATA_LO
, val
);
230 val
= (CAM_DATA_HI_VALID
|
231 (((u32
) data
[0]) << 8) |
232 (((u32
) data
[1]) << 0));
233 bw32(bp
, B44_CAM_DATA_HI
, val
);
234 bw32(bp
, B44_CAM_CTRL
, (CAM_CTRL_WRITE
|
235 (index
<< CAM_CTRL_INDEX_SHIFT
)));
236 b44_wait_bit(bp
, B44_CAM_CTRL
, CAM_CTRL_BUSY
, 100, 1);
239 static inline void __b44_disable_ints(struct b44
*bp
)
241 bw32(bp
, B44_IMASK
, 0);
244 static void b44_disable_ints(struct b44
*bp
)
246 __b44_disable_ints(bp
);
248 /* Flush posted writes. */
252 static void b44_enable_ints(struct b44
*bp
)
254 bw32(bp
, B44_IMASK
, bp
->imask
);
257 static int __b44_readphy(struct b44
*bp
, int phy_addr
, int reg
, u32
*val
)
261 bw32(bp
, B44_EMAC_ISTAT
, EMAC_INT_MII
);
262 bw32(bp
, B44_MDIO_DATA
, (MDIO_DATA_SB_START
|
263 (MDIO_OP_READ
<< MDIO_DATA_OP_SHIFT
) |
264 (phy_addr
<< MDIO_DATA_PMD_SHIFT
) |
265 (reg
<< MDIO_DATA_RA_SHIFT
) |
266 (MDIO_TA_VALID
<< MDIO_DATA_TA_SHIFT
)));
267 err
= b44_wait_bit(bp
, B44_EMAC_ISTAT
, EMAC_INT_MII
, 100, 0);
268 *val
= br32(bp
, B44_MDIO_DATA
) & MDIO_DATA_DATA
;
273 static int __b44_writephy(struct b44
*bp
, int phy_addr
, int reg
, u32 val
)
275 bw32(bp
, B44_EMAC_ISTAT
, EMAC_INT_MII
);
276 bw32(bp
, B44_MDIO_DATA
, (MDIO_DATA_SB_START
|
277 (MDIO_OP_WRITE
<< MDIO_DATA_OP_SHIFT
) |
278 (phy_addr
<< MDIO_DATA_PMD_SHIFT
) |
279 (reg
<< MDIO_DATA_RA_SHIFT
) |
280 (MDIO_TA_VALID
<< MDIO_DATA_TA_SHIFT
) |
281 (val
& MDIO_DATA_DATA
)));
282 return b44_wait_bit(bp
, B44_EMAC_ISTAT
, EMAC_INT_MII
, 100, 0);
285 static inline int b44_readphy(struct b44
*bp
, int reg
, u32
*val
)
287 if (bp
->phy_addr
== B44_PHY_ADDR_NO_PHY
)
290 return __b44_readphy(bp
, bp
->phy_addr
, reg
, val
);
293 static inline int b44_writephy(struct b44
*bp
, int reg
, u32 val
)
295 if (bp
->phy_addr
== B44_PHY_ADDR_NO_PHY
)
298 return __b44_writephy(bp
, bp
->phy_addr
, reg
, val
);
301 /* miilib interface */
302 static int b44_mii_read(struct net_device
*dev
, int phy_id
, int location
)
305 struct b44
*bp
= netdev_priv(dev
);
306 int rc
= __b44_readphy(bp
, phy_id
, location
, &val
);
312 static void b44_mii_write(struct net_device
*dev
, int phy_id
, int location
,
315 struct b44
*bp
= netdev_priv(dev
);
316 __b44_writephy(bp
, phy_id
, location
, val
);
319 static int b44_phy_reset(struct b44
*bp
)
324 if (bp
->phy_addr
== B44_PHY_ADDR_NO_PHY
)
326 err
= b44_writephy(bp
, MII_BMCR
, BMCR_RESET
);
330 err
= b44_readphy(bp
, MII_BMCR
, &val
);
332 if (val
& BMCR_RESET
) {
333 netdev_err(bp
->dev
, "PHY Reset would not complete\n");
341 static void __b44_set_flow_ctrl(struct b44
*bp
, u32 pause_flags
)
345 bp
->flags
&= ~(B44_FLAG_TX_PAUSE
| B44_FLAG_RX_PAUSE
);
346 bp
->flags
|= pause_flags
;
348 val
= br32(bp
, B44_RXCONFIG
);
349 if (pause_flags
& B44_FLAG_RX_PAUSE
)
350 val
|= RXCONFIG_FLOW
;
352 val
&= ~RXCONFIG_FLOW
;
353 bw32(bp
, B44_RXCONFIG
, val
);
355 val
= br32(bp
, B44_MAC_FLOW
);
356 if (pause_flags
& B44_FLAG_TX_PAUSE
)
357 val
|= (MAC_FLOW_PAUSE_ENAB
|
358 (0xc0 & MAC_FLOW_RX_HI_WATER
));
360 val
&= ~MAC_FLOW_PAUSE_ENAB
;
361 bw32(bp
, B44_MAC_FLOW
, val
);
364 static void b44_set_flow_ctrl(struct b44
*bp
, u32 local
, u32 remote
)
368 /* The driver supports only rx pause by default because
369 the b44 mac tx pause mechanism generates excessive
371 Use ethtool to turn on b44 tx pause if necessary.
373 if ((local
& ADVERTISE_PAUSE_CAP
) &&
374 (local
& ADVERTISE_PAUSE_ASYM
)){
375 if ((remote
& LPA_PAUSE_ASYM
) &&
376 !(remote
& LPA_PAUSE_CAP
))
377 pause_enab
|= B44_FLAG_RX_PAUSE
;
380 __b44_set_flow_ctrl(bp
, pause_enab
);
383 #ifdef CONFIG_BCM47XX
384 #include <asm/mach-bcm47xx/nvram.h>
385 static void b44_wap54g10_workaround(struct b44
*bp
)
392 * workaround for bad hardware design in Linksys WAP54G v1.0
393 * see https://dev.openwrt.org/ticket/146
394 * check and reset bit "isolate"
396 if (nvram_getenv("boardnum", buf
, sizeof(buf
)) < 0)
398 if (simple_strtoul(buf
, NULL
, 0) == 2) {
399 err
= __b44_readphy(bp
, 0, MII_BMCR
, &val
);
402 if (!(val
& BMCR_ISOLATE
))
404 val
&= ~BMCR_ISOLATE
;
405 err
= __b44_writephy(bp
, 0, MII_BMCR
, val
);
411 pr_warning("PHY: cannot reset MII transceiver isolate bit\n");
414 static inline void b44_wap54g10_workaround(struct b44
*bp
)
419 static int b44_setup_phy(struct b44
*bp
)
424 b44_wap54g10_workaround(bp
);
426 if (bp
->phy_addr
== B44_PHY_ADDR_NO_PHY
)
428 if ((err
= b44_readphy(bp
, B44_MII_ALEDCTRL
, &val
)) != 0)
430 if ((err
= b44_writephy(bp
, B44_MII_ALEDCTRL
,
431 val
& MII_ALEDCTRL_ALLMSK
)) != 0)
433 if ((err
= b44_readphy(bp
, B44_MII_TLEDCTRL
, &val
)) != 0)
435 if ((err
= b44_writephy(bp
, B44_MII_TLEDCTRL
,
436 val
| MII_TLEDCTRL_ENABLE
)) != 0)
439 if (!(bp
->flags
& B44_FLAG_FORCE_LINK
)) {
440 u32 adv
= ADVERTISE_CSMA
;
442 if (bp
->flags
& B44_FLAG_ADV_10HALF
)
443 adv
|= ADVERTISE_10HALF
;
444 if (bp
->flags
& B44_FLAG_ADV_10FULL
)
445 adv
|= ADVERTISE_10FULL
;
446 if (bp
->flags
& B44_FLAG_ADV_100HALF
)
447 adv
|= ADVERTISE_100HALF
;
448 if (bp
->flags
& B44_FLAG_ADV_100FULL
)
449 adv
|= ADVERTISE_100FULL
;
451 if (bp
->flags
& B44_FLAG_PAUSE_AUTO
)
452 adv
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
454 if ((err
= b44_writephy(bp
, MII_ADVERTISE
, adv
)) != 0)
456 if ((err
= b44_writephy(bp
, MII_BMCR
, (BMCR_ANENABLE
|
457 BMCR_ANRESTART
))) != 0)
462 if ((err
= b44_readphy(bp
, MII_BMCR
, &bmcr
)) != 0)
464 bmcr
&= ~(BMCR_FULLDPLX
| BMCR_ANENABLE
| BMCR_SPEED100
);
465 if (bp
->flags
& B44_FLAG_100_BASE_T
)
466 bmcr
|= BMCR_SPEED100
;
467 if (bp
->flags
& B44_FLAG_FULL_DUPLEX
)
468 bmcr
|= BMCR_FULLDPLX
;
469 if ((err
= b44_writephy(bp
, MII_BMCR
, bmcr
)) != 0)
472 /* Since we will not be negotiating there is no safe way
473 * to determine if the link partner supports flow control
474 * or not. So just disable it completely in this case.
476 b44_set_flow_ctrl(bp
, 0, 0);
483 static void b44_stats_update(struct b44
*bp
)
488 val
= &bp
->hw_stats
.tx_good_octets
;
489 u64_stats_update_begin(&bp
->hw_stats
.syncp
);
491 for (reg
= B44_TX_GOOD_O
; reg
<= B44_TX_PAUSE
; reg
+= 4UL) {
492 *val
++ += br32(bp
, reg
);
498 for (reg
= B44_RX_GOOD_O
; reg
<= B44_RX_NPAUSE
; reg
+= 4UL) {
499 *val
++ += br32(bp
, reg
);
502 u64_stats_update_end(&bp
->hw_stats
.syncp
);
505 static void b44_link_report(struct b44
*bp
)
507 if (!netif_carrier_ok(bp
->dev
)) {
508 netdev_info(bp
->dev
, "Link is down\n");
510 netdev_info(bp
->dev
, "Link is up at %d Mbps, %s duplex\n",
511 (bp
->flags
& B44_FLAG_100_BASE_T
) ? 100 : 10,
512 (bp
->flags
& B44_FLAG_FULL_DUPLEX
) ? "full" : "half");
514 netdev_info(bp
->dev
, "Flow control is %s for TX and %s for RX\n",
515 (bp
->flags
& B44_FLAG_TX_PAUSE
) ? "on" : "off",
516 (bp
->flags
& B44_FLAG_RX_PAUSE
) ? "on" : "off");
520 static void b44_check_phy(struct b44
*bp
)
524 if (bp
->phy_addr
== B44_PHY_ADDR_NO_PHY
) {
525 bp
->flags
|= B44_FLAG_100_BASE_T
;
526 bp
->flags
|= B44_FLAG_FULL_DUPLEX
;
527 if (!netif_carrier_ok(bp
->dev
)) {
528 u32 val
= br32(bp
, B44_TX_CTRL
);
529 val
|= TX_CTRL_DUPLEX
;
530 bw32(bp
, B44_TX_CTRL
, val
);
531 netif_carrier_on(bp
->dev
);
537 if (!b44_readphy(bp
, MII_BMSR
, &bmsr
) &&
538 !b44_readphy(bp
, B44_MII_AUXCTRL
, &aux
) &&
540 if (aux
& MII_AUXCTRL_SPEED
)
541 bp
->flags
|= B44_FLAG_100_BASE_T
;
543 bp
->flags
&= ~B44_FLAG_100_BASE_T
;
544 if (aux
& MII_AUXCTRL_DUPLEX
)
545 bp
->flags
|= B44_FLAG_FULL_DUPLEX
;
547 bp
->flags
&= ~B44_FLAG_FULL_DUPLEX
;
549 if (!netif_carrier_ok(bp
->dev
) &&
550 (bmsr
& BMSR_LSTATUS
)) {
551 u32 val
= br32(bp
, B44_TX_CTRL
);
552 u32 local_adv
, remote_adv
;
554 if (bp
->flags
& B44_FLAG_FULL_DUPLEX
)
555 val
|= TX_CTRL_DUPLEX
;
557 val
&= ~TX_CTRL_DUPLEX
;
558 bw32(bp
, B44_TX_CTRL
, val
);
560 if (!(bp
->flags
& B44_FLAG_FORCE_LINK
) &&
561 !b44_readphy(bp
, MII_ADVERTISE
, &local_adv
) &&
562 !b44_readphy(bp
, MII_LPA
, &remote_adv
))
563 b44_set_flow_ctrl(bp
, local_adv
, remote_adv
);
566 netif_carrier_on(bp
->dev
);
568 } else if (netif_carrier_ok(bp
->dev
) && !(bmsr
& BMSR_LSTATUS
)) {
570 netif_carrier_off(bp
->dev
);
574 if (bmsr
& BMSR_RFAULT
)
575 netdev_warn(bp
->dev
, "Remote fault detected in PHY\n");
577 netdev_warn(bp
->dev
, "Jabber detected in PHY\n");
581 static void b44_timer(unsigned long __opaque
)
583 struct b44
*bp
= (struct b44
*) __opaque
;
585 spin_lock_irq(&bp
->lock
);
589 b44_stats_update(bp
);
591 spin_unlock_irq(&bp
->lock
);
593 mod_timer(&bp
->timer
, round_jiffies(jiffies
+ HZ
));
596 static void b44_tx(struct b44
*bp
)
600 cur
= br32(bp
, B44_DMATX_STAT
) & DMATX_STAT_CDMASK
;
601 cur
/= sizeof(struct dma_desc
);
603 /* XXX needs updating when NETIF_F_SG is supported */
604 for (cons
= bp
->tx_cons
; cons
!= cur
; cons
= NEXT_TX(cons
)) {
605 struct ring_info
*rp
= &bp
->tx_buffers
[cons
];
606 struct sk_buff
*skb
= rp
->skb
;
610 dma_unmap_single(bp
->sdev
->dma_dev
,
615 dev_kfree_skb_irq(skb
);
619 if (netif_queue_stopped(bp
->dev
) &&
620 TX_BUFFS_AVAIL(bp
) > B44_TX_WAKEUP_THRESH
)
621 netif_wake_queue(bp
->dev
);
623 bw32(bp
, B44_GPTIMER
, 0);
626 /* Works like this. This chip writes a 'struct rx_header" 30 bytes
627 * before the DMA address you give it. So we allocate 30 more bytes
628 * for the RX buffer, DMA map all of it, skb_reserve the 30 bytes, then
629 * point the chip at 30 bytes past where the rx_header will go.
631 static int b44_alloc_rx_skb(struct b44
*bp
, int src_idx
, u32 dest_idx_unmasked
)
634 struct ring_info
*src_map
, *map
;
635 struct rx_header
*rh
;
643 src_map
= &bp
->rx_buffers
[src_idx
];
644 dest_idx
= dest_idx_unmasked
& (B44_RX_RING_SIZE
- 1);
645 map
= &bp
->rx_buffers
[dest_idx
];
646 skb
= netdev_alloc_skb(bp
->dev
, RX_PKT_BUF_SZ
);
650 mapping
= dma_map_single(bp
->sdev
->dma_dev
, skb
->data
,
654 /* Hardware bug work-around, the chip is unable to do PCI DMA
655 to/from anything above 1GB :-( */
656 if (dma_mapping_error(bp
->sdev
->dma_dev
, mapping
) ||
657 mapping
+ RX_PKT_BUF_SZ
> DMA_BIT_MASK(30)) {
659 if (!dma_mapping_error(bp
->sdev
->dma_dev
, mapping
))
660 dma_unmap_single(bp
->sdev
->dma_dev
, mapping
,
661 RX_PKT_BUF_SZ
, DMA_FROM_DEVICE
);
662 dev_kfree_skb_any(skb
);
663 skb
= alloc_skb(RX_PKT_BUF_SZ
, GFP_ATOMIC
| GFP_DMA
);
666 mapping
= dma_map_single(bp
->sdev
->dma_dev
, skb
->data
,
669 if (dma_mapping_error(bp
->sdev
->dma_dev
, mapping
) ||
670 mapping
+ RX_PKT_BUF_SZ
> DMA_BIT_MASK(30)) {
671 if (!dma_mapping_error(bp
->sdev
->dma_dev
, mapping
))
672 dma_unmap_single(bp
->sdev
->dma_dev
, mapping
, RX_PKT_BUF_SZ
,DMA_FROM_DEVICE
);
673 dev_kfree_skb_any(skb
);
676 bp
->force_copybreak
= 1;
679 rh
= (struct rx_header
*) skb
->data
;
685 map
->mapping
= mapping
;
690 ctrl
= (DESC_CTRL_LEN
& RX_PKT_BUF_SZ
);
691 if (dest_idx
== (B44_RX_RING_SIZE
- 1))
692 ctrl
|= DESC_CTRL_EOT
;
694 dp
= &bp
->rx_ring
[dest_idx
];
695 dp
->ctrl
= cpu_to_le32(ctrl
);
696 dp
->addr
= cpu_to_le32((u32
) mapping
+ bp
->dma_offset
);
698 if (bp
->flags
& B44_FLAG_RX_RING_HACK
)
699 b44_sync_dma_desc_for_device(bp
->sdev
, bp
->rx_ring_dma
,
700 dest_idx
* sizeof(*dp
),
703 return RX_PKT_BUF_SZ
;
706 static void b44_recycle_rx(struct b44
*bp
, int src_idx
, u32 dest_idx_unmasked
)
708 struct dma_desc
*src_desc
, *dest_desc
;
709 struct ring_info
*src_map
, *dest_map
;
710 struct rx_header
*rh
;
714 dest_idx
= dest_idx_unmasked
& (B44_RX_RING_SIZE
- 1);
715 dest_desc
= &bp
->rx_ring
[dest_idx
];
716 dest_map
= &bp
->rx_buffers
[dest_idx
];
717 src_desc
= &bp
->rx_ring
[src_idx
];
718 src_map
= &bp
->rx_buffers
[src_idx
];
720 dest_map
->skb
= src_map
->skb
;
721 rh
= (struct rx_header
*) src_map
->skb
->data
;
724 dest_map
->mapping
= src_map
->mapping
;
726 if (bp
->flags
& B44_FLAG_RX_RING_HACK
)
727 b44_sync_dma_desc_for_cpu(bp
->sdev
, bp
->rx_ring_dma
,
728 src_idx
* sizeof(*src_desc
),
731 ctrl
= src_desc
->ctrl
;
732 if (dest_idx
== (B44_RX_RING_SIZE
- 1))
733 ctrl
|= cpu_to_le32(DESC_CTRL_EOT
);
735 ctrl
&= cpu_to_le32(~DESC_CTRL_EOT
);
737 dest_desc
->ctrl
= ctrl
;
738 dest_desc
->addr
= src_desc
->addr
;
742 if (bp
->flags
& B44_FLAG_RX_RING_HACK
)
743 b44_sync_dma_desc_for_device(bp
->sdev
, bp
->rx_ring_dma
,
744 dest_idx
* sizeof(*dest_desc
),
747 dma_sync_single_for_device(bp
->sdev
->dma_dev
, dest_map
->mapping
,
752 static int b44_rx(struct b44
*bp
, int budget
)
758 prod
= br32(bp
, B44_DMARX_STAT
) & DMARX_STAT_CDMASK
;
759 prod
/= sizeof(struct dma_desc
);
762 while (cons
!= prod
&& budget
> 0) {
763 struct ring_info
*rp
= &bp
->rx_buffers
[cons
];
764 struct sk_buff
*skb
= rp
->skb
;
765 dma_addr_t map
= rp
->mapping
;
766 struct rx_header
*rh
;
769 dma_sync_single_for_cpu(bp
->sdev
->dma_dev
, map
,
772 rh
= (struct rx_header
*) skb
->data
;
773 len
= le16_to_cpu(rh
->len
);
774 if ((len
> (RX_PKT_BUF_SZ
- RX_PKT_OFFSET
)) ||
775 (rh
->flags
& cpu_to_le16(RX_FLAG_ERRORS
))) {
777 b44_recycle_rx(bp
, cons
, bp
->rx_prod
);
779 bp
->dev
->stats
.rx_dropped
++;
789 len
= le16_to_cpu(rh
->len
);
790 } while (len
== 0 && i
++ < 5);
798 if (!bp
->force_copybreak
&& len
> RX_COPY_THRESHOLD
) {
800 skb_size
= b44_alloc_rx_skb(bp
, cons
, bp
->rx_prod
);
803 dma_unmap_single(bp
->sdev
->dma_dev
, map
,
804 skb_size
, DMA_FROM_DEVICE
);
805 /* Leave out rx_header */
806 skb_put(skb
, len
+ RX_PKT_OFFSET
);
807 skb_pull(skb
, RX_PKT_OFFSET
);
809 struct sk_buff
*copy_skb
;
811 b44_recycle_rx(bp
, cons
, bp
->rx_prod
);
812 copy_skb
= netdev_alloc_skb(bp
->dev
, len
+ 2);
813 if (copy_skb
== NULL
)
814 goto drop_it_no_recycle
;
816 skb_reserve(copy_skb
, 2);
817 skb_put(copy_skb
, len
);
818 /* DMA sync done above, copy just the actual packet */
819 skb_copy_from_linear_data_offset(skb
, RX_PKT_OFFSET
,
820 copy_skb
->data
, len
);
823 skb_checksum_none_assert(skb
);
824 skb
->protocol
= eth_type_trans(skb
, bp
->dev
);
825 netif_receive_skb(skb
);
829 bp
->rx_prod
= (bp
->rx_prod
+ 1) &
830 (B44_RX_RING_SIZE
- 1);
831 cons
= (cons
+ 1) & (B44_RX_RING_SIZE
- 1);
835 bw32(bp
, B44_DMARX_PTR
, cons
* sizeof(struct dma_desc
));
840 static int b44_poll(struct napi_struct
*napi
, int budget
)
842 struct b44
*bp
= container_of(napi
, struct b44
, napi
);
846 spin_lock_irqsave(&bp
->lock
, flags
);
848 if (bp
->istat
& (ISTAT_TX
| ISTAT_TO
)) {
849 /* spin_lock(&bp->tx_lock); */
851 /* spin_unlock(&bp->tx_lock); */
853 if (bp
->istat
& ISTAT_RFO
) { /* fast recovery, in ~20msec */
854 bp
->istat
&= ~ISTAT_RFO
;
855 b44_disable_ints(bp
);
856 ssb_device_enable(bp
->sdev
, 0); /* resets ISTAT_RFO */
858 b44_init_hw(bp
, B44_FULL_RESET_SKIP_PHY
);
859 netif_wake_queue(bp
->dev
);
862 spin_unlock_irqrestore(&bp
->lock
, flags
);
865 if (bp
->istat
& ISTAT_RX
)
866 work_done
+= b44_rx(bp
, budget
);
868 if (bp
->istat
& ISTAT_ERRORS
) {
869 spin_lock_irqsave(&bp
->lock
, flags
);
872 b44_init_hw(bp
, B44_FULL_RESET_SKIP_PHY
);
873 netif_wake_queue(bp
->dev
);
874 spin_unlock_irqrestore(&bp
->lock
, flags
);
878 if (work_done
< budget
) {
886 static irqreturn_t
b44_interrupt(int irq
, void *dev_id
)
888 struct net_device
*dev
= dev_id
;
889 struct b44
*bp
= netdev_priv(dev
);
893 spin_lock(&bp
->lock
);
895 istat
= br32(bp
, B44_ISTAT
);
896 imask
= br32(bp
, B44_IMASK
);
898 /* The interrupt mask register controls which interrupt bits
899 * will actually raise an interrupt to the CPU when set by hw/firmware,
900 * but doesn't mask off the bits.
906 if (unlikely(!netif_running(dev
))) {
907 netdev_info(dev
, "late interrupt\n");
911 if (napi_schedule_prep(&bp
->napi
)) {
912 /* NOTE: These writes are posted by the readback of
913 * the ISTAT register below.
916 __b44_disable_ints(bp
);
917 __napi_schedule(&bp
->napi
);
921 bw32(bp
, B44_ISTAT
, istat
);
924 spin_unlock(&bp
->lock
);
925 return IRQ_RETVAL(handled
);
928 static void b44_tx_timeout(struct net_device
*dev
)
930 struct b44
*bp
= netdev_priv(dev
);
932 netdev_err(dev
, "transmit timed out, resetting\n");
934 spin_lock_irq(&bp
->lock
);
938 b44_init_hw(bp
, B44_FULL_RESET
);
940 spin_unlock_irq(&bp
->lock
);
944 netif_wake_queue(dev
);
947 static netdev_tx_t
b44_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
949 struct b44
*bp
= netdev_priv(dev
);
950 int rc
= NETDEV_TX_OK
;
952 u32 len
, entry
, ctrl
;
956 spin_lock_irqsave(&bp
->lock
, flags
);
958 /* This is a hard error, log it. */
959 if (unlikely(TX_BUFFS_AVAIL(bp
) < 1)) {
960 netif_stop_queue(dev
);
961 netdev_err(dev
, "BUG! Tx Ring full when queue awake!\n");
965 mapping
= dma_map_single(bp
->sdev
->dma_dev
, skb
->data
, len
, DMA_TO_DEVICE
);
966 if (dma_mapping_error(bp
->sdev
->dma_dev
, mapping
) || mapping
+ len
> DMA_BIT_MASK(30)) {
967 struct sk_buff
*bounce_skb
;
969 /* Chip can't handle DMA to/from >1GB, use bounce buffer */
970 if (!dma_mapping_error(bp
->sdev
->dma_dev
, mapping
))
971 dma_unmap_single(bp
->sdev
->dma_dev
, mapping
, len
,
974 bounce_skb
= alloc_skb(len
, GFP_ATOMIC
| GFP_DMA
);
978 mapping
= dma_map_single(bp
->sdev
->dma_dev
, bounce_skb
->data
,
980 if (dma_mapping_error(bp
->sdev
->dma_dev
, mapping
) || mapping
+ len
> DMA_BIT_MASK(30)) {
981 if (!dma_mapping_error(bp
->sdev
->dma_dev
, mapping
))
982 dma_unmap_single(bp
->sdev
->dma_dev
, mapping
,
984 dev_kfree_skb_any(bounce_skb
);
988 skb_copy_from_linear_data(skb
, skb_put(bounce_skb
, len
), len
);
989 dev_kfree_skb_any(skb
);
994 bp
->tx_buffers
[entry
].skb
= skb
;
995 bp
->tx_buffers
[entry
].mapping
= mapping
;
997 ctrl
= (len
& DESC_CTRL_LEN
);
998 ctrl
|= DESC_CTRL_IOC
| DESC_CTRL_SOF
| DESC_CTRL_EOF
;
999 if (entry
== (B44_TX_RING_SIZE
- 1))
1000 ctrl
|= DESC_CTRL_EOT
;
1002 bp
->tx_ring
[entry
].ctrl
= cpu_to_le32(ctrl
);
1003 bp
->tx_ring
[entry
].addr
= cpu_to_le32((u32
) mapping
+bp
->dma_offset
);
1005 if (bp
->flags
& B44_FLAG_TX_RING_HACK
)
1006 b44_sync_dma_desc_for_device(bp
->sdev
, bp
->tx_ring_dma
,
1007 entry
* sizeof(bp
->tx_ring
[0]),
1010 entry
= NEXT_TX(entry
);
1012 bp
->tx_prod
= entry
;
1016 bw32(bp
, B44_DMATX_PTR
, entry
* sizeof(struct dma_desc
));
1017 if (bp
->flags
& B44_FLAG_BUGGY_TXPTR
)
1018 bw32(bp
, B44_DMATX_PTR
, entry
* sizeof(struct dma_desc
));
1019 if (bp
->flags
& B44_FLAG_REORDER_BUG
)
1020 br32(bp
, B44_DMATX_PTR
);
1022 if (TX_BUFFS_AVAIL(bp
) < 1)
1023 netif_stop_queue(dev
);
1026 spin_unlock_irqrestore(&bp
->lock
, flags
);
1031 rc
= NETDEV_TX_BUSY
;
1035 static int b44_change_mtu(struct net_device
*dev
, int new_mtu
)
1037 struct b44
*bp
= netdev_priv(dev
);
1039 if (new_mtu
< B44_MIN_MTU
|| new_mtu
> B44_MAX_MTU
)
1042 if (!netif_running(dev
)) {
1043 /* We'll just catch it later when the
1050 spin_lock_irq(&bp
->lock
);
1054 b44_init_hw(bp
, B44_FULL_RESET
);
1055 spin_unlock_irq(&bp
->lock
);
1057 b44_enable_ints(bp
);
1062 /* Free up pending packets in all rx/tx rings.
1064 * The chip has been shut down and the driver detached from
1065 * the networking, so no interrupts or new tx packets will
1066 * end up in the driver. bp->lock is not held and we are not
1067 * in an interrupt context and thus may sleep.
1069 static void b44_free_rings(struct b44
*bp
)
1071 struct ring_info
*rp
;
1074 for (i
= 0; i
< B44_RX_RING_SIZE
; i
++) {
1075 rp
= &bp
->rx_buffers
[i
];
1077 if (rp
->skb
== NULL
)
1079 dma_unmap_single(bp
->sdev
->dma_dev
, rp
->mapping
, RX_PKT_BUF_SZ
,
1081 dev_kfree_skb_any(rp
->skb
);
1085 /* XXX needs changes once NETIF_F_SG is set... */
1086 for (i
= 0; i
< B44_TX_RING_SIZE
; i
++) {
1087 rp
= &bp
->tx_buffers
[i
];
1089 if (rp
->skb
== NULL
)
1091 dma_unmap_single(bp
->sdev
->dma_dev
, rp
->mapping
, rp
->skb
->len
,
1093 dev_kfree_skb_any(rp
->skb
);
1098 /* Initialize tx/rx rings for packet processing.
1100 * The chip has been shut down and the driver detached from
1101 * the networking, so no interrupts or new tx packets will
1102 * end up in the driver.
1104 static void b44_init_rings(struct b44
*bp
)
1110 memset(bp
->rx_ring
, 0, B44_RX_RING_BYTES
);
1111 memset(bp
->tx_ring
, 0, B44_TX_RING_BYTES
);
1113 if (bp
->flags
& B44_FLAG_RX_RING_HACK
)
1114 dma_sync_single_for_device(bp
->sdev
->dma_dev
, bp
->rx_ring_dma
,
1115 DMA_TABLE_BYTES
, DMA_BIDIRECTIONAL
);
1117 if (bp
->flags
& B44_FLAG_TX_RING_HACK
)
1118 dma_sync_single_for_device(bp
->sdev
->dma_dev
, bp
->tx_ring_dma
,
1119 DMA_TABLE_BYTES
, DMA_TO_DEVICE
);
1121 for (i
= 0; i
< bp
->rx_pending
; i
++) {
1122 if (b44_alloc_rx_skb(bp
, -1, i
) < 0)
1128 * Must not be invoked with interrupt sources disabled and
1129 * the hardware shutdown down.
1131 static void b44_free_consistent(struct b44
*bp
)
1133 kfree(bp
->rx_buffers
);
1134 bp
->rx_buffers
= NULL
;
1135 kfree(bp
->tx_buffers
);
1136 bp
->tx_buffers
= NULL
;
1138 if (bp
->flags
& B44_FLAG_RX_RING_HACK
) {
1139 dma_unmap_single(bp
->sdev
->dma_dev
, bp
->rx_ring_dma
,
1140 DMA_TABLE_BYTES
, DMA_BIDIRECTIONAL
);
1143 dma_free_coherent(bp
->sdev
->dma_dev
, DMA_TABLE_BYTES
,
1144 bp
->rx_ring
, bp
->rx_ring_dma
);
1146 bp
->flags
&= ~B44_FLAG_RX_RING_HACK
;
1149 if (bp
->flags
& B44_FLAG_TX_RING_HACK
) {
1150 dma_unmap_single(bp
->sdev
->dma_dev
, bp
->tx_ring_dma
,
1151 DMA_TABLE_BYTES
, DMA_TO_DEVICE
);
1154 dma_free_coherent(bp
->sdev
->dma_dev
, DMA_TABLE_BYTES
,
1155 bp
->tx_ring
, bp
->tx_ring_dma
);
1157 bp
->flags
&= ~B44_FLAG_TX_RING_HACK
;
1162 * Must not be invoked with interrupt sources disabled and
1163 * the hardware shutdown down. Can sleep.
1165 static int b44_alloc_consistent(struct b44
*bp
, gfp_t gfp
)
1169 size
= B44_RX_RING_SIZE
* sizeof(struct ring_info
);
1170 bp
->rx_buffers
= kzalloc(size
, gfp
);
1171 if (!bp
->rx_buffers
)
1174 size
= B44_TX_RING_SIZE
* sizeof(struct ring_info
);
1175 bp
->tx_buffers
= kzalloc(size
, gfp
);
1176 if (!bp
->tx_buffers
)
1179 size
= DMA_TABLE_BYTES
;
1180 bp
->rx_ring
= dma_alloc_coherent(bp
->sdev
->dma_dev
, size
,
1181 &bp
->rx_ring_dma
, gfp
);
1183 /* Allocation may have failed due to pci_alloc_consistent
1184 insisting on use of GFP_DMA, which is more restrictive
1185 than necessary... */
1186 struct dma_desc
*rx_ring
;
1187 dma_addr_t rx_ring_dma
;
1189 rx_ring
= kzalloc(size
, gfp
);
1193 rx_ring_dma
= dma_map_single(bp
->sdev
->dma_dev
, rx_ring
,
1197 if (dma_mapping_error(bp
->sdev
->dma_dev
, rx_ring_dma
) ||
1198 rx_ring_dma
+ size
> DMA_BIT_MASK(30)) {
1203 bp
->rx_ring
= rx_ring
;
1204 bp
->rx_ring_dma
= rx_ring_dma
;
1205 bp
->flags
|= B44_FLAG_RX_RING_HACK
;
1208 bp
->tx_ring
= dma_alloc_coherent(bp
->sdev
->dma_dev
, size
,
1209 &bp
->tx_ring_dma
, gfp
);
1211 /* Allocation may have failed due to ssb_dma_alloc_consistent
1212 insisting on use of GFP_DMA, which is more restrictive
1213 than necessary... */
1214 struct dma_desc
*tx_ring
;
1215 dma_addr_t tx_ring_dma
;
1217 tx_ring
= kzalloc(size
, gfp
);
1221 tx_ring_dma
= dma_map_single(bp
->sdev
->dma_dev
, tx_ring
,
1225 if (dma_mapping_error(bp
->sdev
->dma_dev
, tx_ring_dma
) ||
1226 tx_ring_dma
+ size
> DMA_BIT_MASK(30)) {
1231 bp
->tx_ring
= tx_ring
;
1232 bp
->tx_ring_dma
= tx_ring_dma
;
1233 bp
->flags
|= B44_FLAG_TX_RING_HACK
;
1239 b44_free_consistent(bp
);
1243 /* bp->lock is held. */
1244 static void b44_clear_stats(struct b44
*bp
)
1248 bw32(bp
, B44_MIB_CTRL
, MIB_CTRL_CLR_ON_READ
);
1249 for (reg
= B44_TX_GOOD_O
; reg
<= B44_TX_PAUSE
; reg
+= 4UL)
1251 for (reg
= B44_RX_GOOD_O
; reg
<= B44_RX_NPAUSE
; reg
+= 4UL)
1255 /* bp->lock is held. */
1256 static void b44_chip_reset(struct b44
*bp
, int reset_kind
)
1258 struct ssb_device
*sdev
= bp
->sdev
;
1261 was_enabled
= ssb_device_is_enabled(bp
->sdev
);
1263 ssb_device_enable(bp
->sdev
, 0);
1264 ssb_pcicore_dev_irqvecs_enable(&sdev
->bus
->pcicore
, sdev
);
1267 bw32(bp
, B44_RCV_LAZY
, 0);
1268 bw32(bp
, B44_ENET_CTRL
, ENET_CTRL_DISABLE
);
1269 b44_wait_bit(bp
, B44_ENET_CTRL
, ENET_CTRL_DISABLE
, 200, 1);
1270 bw32(bp
, B44_DMATX_CTRL
, 0);
1271 bp
->tx_prod
= bp
->tx_cons
= 0;
1272 if (br32(bp
, B44_DMARX_STAT
) & DMARX_STAT_EMASK
) {
1273 b44_wait_bit(bp
, B44_DMARX_STAT
, DMARX_STAT_SIDLE
,
1276 bw32(bp
, B44_DMARX_CTRL
, 0);
1277 bp
->rx_prod
= bp
->rx_cons
= 0;
1280 b44_clear_stats(bp
);
1283 * Don't enable PHY if we are doing a partial reset
1284 * we are probably going to power down
1286 if (reset_kind
== B44_CHIP_RESET_PARTIAL
)
1289 switch (sdev
->bus
->bustype
) {
1290 case SSB_BUSTYPE_SSB
:
1291 bw32(bp
, B44_MDIO_CTRL
, (MDIO_CTRL_PREAMBLE
|
1292 (DIV_ROUND_CLOSEST(ssb_clockspeed(sdev
->bus
),
1294 & MDIO_CTRL_MAXF_MASK
)));
1296 case SSB_BUSTYPE_PCI
:
1297 bw32(bp
, B44_MDIO_CTRL
, (MDIO_CTRL_PREAMBLE
|
1298 (0x0d & MDIO_CTRL_MAXF_MASK
)));
1300 case SSB_BUSTYPE_PCMCIA
:
1301 case SSB_BUSTYPE_SDIO
:
1302 WARN_ON(1); /* A device with this bus does not exist. */
1306 br32(bp
, B44_MDIO_CTRL
);
1308 if (!(br32(bp
, B44_DEVCTRL
) & DEVCTRL_IPP
)) {
1309 bw32(bp
, B44_ENET_CTRL
, ENET_CTRL_EPSEL
);
1310 br32(bp
, B44_ENET_CTRL
);
1311 bp
->flags
&= ~B44_FLAG_INTERNAL_PHY
;
1313 u32 val
= br32(bp
, B44_DEVCTRL
);
1315 if (val
& DEVCTRL_EPR
) {
1316 bw32(bp
, B44_DEVCTRL
, (val
& ~DEVCTRL_EPR
));
1317 br32(bp
, B44_DEVCTRL
);
1320 bp
->flags
|= B44_FLAG_INTERNAL_PHY
;
1324 /* bp->lock is held. */
1325 static void b44_halt(struct b44
*bp
)
1327 b44_disable_ints(bp
);
1330 /* power down PHY */
1331 netdev_info(bp
->dev
, "powering down PHY\n");
1332 bw32(bp
, B44_MAC_CTRL
, MAC_CTRL_PHY_PDOWN
);
1333 /* now reset the chip, but without enabling the MAC&PHY
1334 * part of it. This has to be done _after_ we shut down the PHY */
1335 b44_chip_reset(bp
, B44_CHIP_RESET_PARTIAL
);
1338 /* bp->lock is held. */
1339 static void __b44_set_mac_addr(struct b44
*bp
)
1341 bw32(bp
, B44_CAM_CTRL
, 0);
1342 if (!(bp
->dev
->flags
& IFF_PROMISC
)) {
1345 __b44_cam_write(bp
, bp
->dev
->dev_addr
, 0);
1346 val
= br32(bp
, B44_CAM_CTRL
);
1347 bw32(bp
, B44_CAM_CTRL
, val
| CAM_CTRL_ENABLE
);
1351 static int b44_set_mac_addr(struct net_device
*dev
, void *p
)
1353 struct b44
*bp
= netdev_priv(dev
);
1354 struct sockaddr
*addr
= p
;
1357 if (netif_running(dev
))
1360 if (!is_valid_ether_addr(addr
->sa_data
))
1363 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
1365 spin_lock_irq(&bp
->lock
);
1367 val
= br32(bp
, B44_RXCONFIG
);
1368 if (!(val
& RXCONFIG_CAM_ABSENT
))
1369 __b44_set_mac_addr(bp
);
1371 spin_unlock_irq(&bp
->lock
);
1376 /* Called at device open time to get the chip ready for
1377 * packet processing. Invoked with bp->lock held.
1379 static void __b44_set_rx_mode(struct net_device
*);
1380 static void b44_init_hw(struct b44
*bp
, int reset_kind
)
1384 b44_chip_reset(bp
, B44_CHIP_RESET_FULL
);
1385 if (reset_kind
== B44_FULL_RESET
) {
1390 /* Enable CRC32, set proper LED modes and power on PHY */
1391 bw32(bp
, B44_MAC_CTRL
, MAC_CTRL_CRC32_ENAB
| MAC_CTRL_PHY_LEDCTRL
);
1392 bw32(bp
, B44_RCV_LAZY
, (1 << RCV_LAZY_FC_SHIFT
));
1394 /* This sets the MAC address too. */
1395 __b44_set_rx_mode(bp
->dev
);
1397 /* MTU + eth header + possible VLAN tag + struct rx_header */
1398 bw32(bp
, B44_RXMAXLEN
, bp
->dev
->mtu
+ ETH_HLEN
+ 8 + RX_HEADER_LEN
);
1399 bw32(bp
, B44_TXMAXLEN
, bp
->dev
->mtu
+ ETH_HLEN
+ 8 + RX_HEADER_LEN
);
1401 bw32(bp
, B44_TX_WMARK
, 56); /* XXX magic */
1402 if (reset_kind
== B44_PARTIAL_RESET
) {
1403 bw32(bp
, B44_DMARX_CTRL
, (DMARX_CTRL_ENABLE
|
1404 (RX_PKT_OFFSET
<< DMARX_CTRL_ROSHIFT
)));
1406 bw32(bp
, B44_DMATX_CTRL
, DMATX_CTRL_ENABLE
);
1407 bw32(bp
, B44_DMATX_ADDR
, bp
->tx_ring_dma
+ bp
->dma_offset
);
1408 bw32(bp
, B44_DMARX_CTRL
, (DMARX_CTRL_ENABLE
|
1409 (RX_PKT_OFFSET
<< DMARX_CTRL_ROSHIFT
)));
1410 bw32(bp
, B44_DMARX_ADDR
, bp
->rx_ring_dma
+ bp
->dma_offset
);
1412 bw32(bp
, B44_DMARX_PTR
, bp
->rx_pending
);
1413 bp
->rx_prod
= bp
->rx_pending
;
1415 bw32(bp
, B44_MIB_CTRL
, MIB_CTRL_CLR_ON_READ
);
1418 val
= br32(bp
, B44_ENET_CTRL
);
1419 bw32(bp
, B44_ENET_CTRL
, (val
| ENET_CTRL_ENABLE
));
1422 static int b44_open(struct net_device
*dev
)
1424 struct b44
*bp
= netdev_priv(dev
);
1427 err
= b44_alloc_consistent(bp
, GFP_KERNEL
);
1431 napi_enable(&bp
->napi
);
1434 b44_init_hw(bp
, B44_FULL_RESET
);
1438 err
= request_irq(dev
->irq
, b44_interrupt
, IRQF_SHARED
, dev
->name
, dev
);
1439 if (unlikely(err
< 0)) {
1440 napi_disable(&bp
->napi
);
1441 b44_chip_reset(bp
, B44_CHIP_RESET_PARTIAL
);
1443 b44_free_consistent(bp
);
1447 init_timer(&bp
->timer
);
1448 bp
->timer
.expires
= jiffies
+ HZ
;
1449 bp
->timer
.data
= (unsigned long) bp
;
1450 bp
->timer
.function
= b44_timer
;
1451 add_timer(&bp
->timer
);
1453 b44_enable_ints(bp
);
1454 netif_start_queue(dev
);
1459 #ifdef CONFIG_NET_POLL_CONTROLLER
1461 * Polling receive - used by netconsole and other diagnostic tools
1462 * to allow network i/o with interrupts disabled.
1464 static void b44_poll_controller(struct net_device
*dev
)
1466 disable_irq(dev
->irq
);
1467 b44_interrupt(dev
->irq
, dev
);
1468 enable_irq(dev
->irq
);
1472 static void bwfilter_table(struct b44
*bp
, u8
*pp
, u32 bytes
, u32 table_offset
)
1475 u32
*pattern
= (u32
*) pp
;
1477 for (i
= 0; i
< bytes
; i
+= sizeof(u32
)) {
1478 bw32(bp
, B44_FILT_ADDR
, table_offset
+ i
);
1479 bw32(bp
, B44_FILT_DATA
, pattern
[i
/ sizeof(u32
)]);
1483 static int b44_magic_pattern(u8
*macaddr
, u8
*ppattern
, u8
*pmask
, int offset
)
1486 int k
, j
, len
= offset
;
1487 int ethaddr_bytes
= ETH_ALEN
;
1489 memset(ppattern
+ offset
, 0xff, magicsync
);
1490 for (j
= 0; j
< magicsync
; j
++)
1491 set_bit(len
++, (unsigned long *) pmask
);
1493 for (j
= 0; j
< B44_MAX_PATTERNS
; j
++) {
1494 if ((B44_PATTERN_SIZE
- len
) >= ETH_ALEN
)
1495 ethaddr_bytes
= ETH_ALEN
;
1497 ethaddr_bytes
= B44_PATTERN_SIZE
- len
;
1498 if (ethaddr_bytes
<=0)
1500 for (k
= 0; k
< ethaddr_bytes
; k
++) {
1501 ppattern
[offset
+ magicsync
+
1502 (j
* ETH_ALEN
) + k
] = macaddr
[k
];
1503 set_bit(len
++, (unsigned long *) pmask
);
1509 /* Setup magic packet patterns in the b44 WOL
1510 * pattern matching filter.
1512 static void b44_setup_pseudo_magicp(struct b44
*bp
)
1516 int plen0
, plen1
, plen2
;
1518 u8 pwol_mask
[B44_PMASK_SIZE
];
1520 pwol_pattern
= kzalloc(B44_PATTERN_SIZE
, GFP_KERNEL
);
1521 if (!pwol_pattern
) {
1522 pr_err("Memory not available for WOL\n");
1526 /* Ipv4 magic packet pattern - pattern 0.*/
1527 memset(pwol_mask
, 0, B44_PMASK_SIZE
);
1528 plen0
= b44_magic_pattern(bp
->dev
->dev_addr
, pwol_pattern
, pwol_mask
,
1529 B44_ETHIPV4UDP_HLEN
);
1531 bwfilter_table(bp
, pwol_pattern
, B44_PATTERN_SIZE
, B44_PATTERN_BASE
);
1532 bwfilter_table(bp
, pwol_mask
, B44_PMASK_SIZE
, B44_PMASK_BASE
);
1534 /* Raw ethernet II magic packet pattern - pattern 1 */
1535 memset(pwol_pattern
, 0, B44_PATTERN_SIZE
);
1536 memset(pwol_mask
, 0, B44_PMASK_SIZE
);
1537 plen1
= b44_magic_pattern(bp
->dev
->dev_addr
, pwol_pattern
, pwol_mask
,
1540 bwfilter_table(bp
, pwol_pattern
, B44_PATTERN_SIZE
,
1541 B44_PATTERN_BASE
+ B44_PATTERN_SIZE
);
1542 bwfilter_table(bp
, pwol_mask
, B44_PMASK_SIZE
,
1543 B44_PMASK_BASE
+ B44_PMASK_SIZE
);
1545 /* Ipv6 magic packet pattern - pattern 2 */
1546 memset(pwol_pattern
, 0, B44_PATTERN_SIZE
);
1547 memset(pwol_mask
, 0, B44_PMASK_SIZE
);
1548 plen2
= b44_magic_pattern(bp
->dev
->dev_addr
, pwol_pattern
, pwol_mask
,
1549 B44_ETHIPV6UDP_HLEN
);
1551 bwfilter_table(bp
, pwol_pattern
, B44_PATTERN_SIZE
,
1552 B44_PATTERN_BASE
+ B44_PATTERN_SIZE
+ B44_PATTERN_SIZE
);
1553 bwfilter_table(bp
, pwol_mask
, B44_PMASK_SIZE
,
1554 B44_PMASK_BASE
+ B44_PMASK_SIZE
+ B44_PMASK_SIZE
);
1556 kfree(pwol_pattern
);
1558 /* set these pattern's lengths: one less than each real length */
1559 val
= plen0
| (plen1
<< 8) | (plen2
<< 16) | WKUP_LEN_ENABLE_THREE
;
1560 bw32(bp
, B44_WKUP_LEN
, val
);
1562 /* enable wakeup pattern matching */
1563 val
= br32(bp
, B44_DEVCTRL
);
1564 bw32(bp
, B44_DEVCTRL
, val
| DEVCTRL_PFE
);
1568 #ifdef CONFIG_B44_PCI
1569 static void b44_setup_wol_pci(struct b44
*bp
)
1573 if (bp
->sdev
->bus
->bustype
!= SSB_BUSTYPE_SSB
) {
1574 bw32(bp
, SSB_TMSLOW
, br32(bp
, SSB_TMSLOW
) | SSB_TMSLOW_PE
);
1575 pci_read_config_word(bp
->sdev
->bus
->host_pci
, SSB_PMCSR
, &val
);
1576 pci_write_config_word(bp
->sdev
->bus
->host_pci
, SSB_PMCSR
, val
| SSB_PE
);
1580 static inline void b44_setup_wol_pci(struct b44
*bp
) { }
1581 #endif /* CONFIG_B44_PCI */
1583 static void b44_setup_wol(struct b44
*bp
)
1587 bw32(bp
, B44_RXCONFIG
, RXCONFIG_ALLMULTI
);
1589 if (bp
->flags
& B44_FLAG_B0_ANDLATER
) {
1591 bw32(bp
, B44_WKUP_LEN
, WKUP_LEN_DISABLE
);
1593 val
= bp
->dev
->dev_addr
[2] << 24 |
1594 bp
->dev
->dev_addr
[3] << 16 |
1595 bp
->dev
->dev_addr
[4] << 8 |
1596 bp
->dev
->dev_addr
[5];
1597 bw32(bp
, B44_ADDR_LO
, val
);
1599 val
= bp
->dev
->dev_addr
[0] << 8 |
1600 bp
->dev
->dev_addr
[1];
1601 bw32(bp
, B44_ADDR_HI
, val
);
1603 val
= br32(bp
, B44_DEVCTRL
);
1604 bw32(bp
, B44_DEVCTRL
, val
| DEVCTRL_MPM
| DEVCTRL_PFE
);
1607 b44_setup_pseudo_magicp(bp
);
1609 b44_setup_wol_pci(bp
);
1612 static int b44_close(struct net_device
*dev
)
1614 struct b44
*bp
= netdev_priv(dev
);
1616 netif_stop_queue(dev
);
1618 napi_disable(&bp
->napi
);
1620 del_timer_sync(&bp
->timer
);
1622 spin_lock_irq(&bp
->lock
);
1626 netif_carrier_off(dev
);
1628 spin_unlock_irq(&bp
->lock
);
1630 free_irq(dev
->irq
, dev
);
1632 if (bp
->flags
& B44_FLAG_WOL_ENABLE
) {
1633 b44_init_hw(bp
, B44_PARTIAL_RESET
);
1637 b44_free_consistent(bp
);
1642 static struct rtnl_link_stats64
*b44_get_stats64(struct net_device
*dev
,
1643 struct rtnl_link_stats64
*nstat
)
1645 struct b44
*bp
= netdev_priv(dev
);
1646 struct b44_hw_stats
*hwstat
= &bp
->hw_stats
;
1650 start
= u64_stats_fetch_begin_bh(&hwstat
->syncp
);
1652 /* Convert HW stats into rtnl_link_stats64 stats. */
1653 nstat
->rx_packets
= hwstat
->rx_pkts
;
1654 nstat
->tx_packets
= hwstat
->tx_pkts
;
1655 nstat
->rx_bytes
= hwstat
->rx_octets
;
1656 nstat
->tx_bytes
= hwstat
->tx_octets
;
1657 nstat
->tx_errors
= (hwstat
->tx_jabber_pkts
+
1658 hwstat
->tx_oversize_pkts
+
1659 hwstat
->tx_underruns
+
1660 hwstat
->tx_excessive_cols
+
1661 hwstat
->tx_late_cols
);
1662 nstat
->multicast
= hwstat
->tx_multicast_pkts
;
1663 nstat
->collisions
= hwstat
->tx_total_cols
;
1665 nstat
->rx_length_errors
= (hwstat
->rx_oversize_pkts
+
1666 hwstat
->rx_undersize
);
1667 nstat
->rx_over_errors
= hwstat
->rx_missed_pkts
;
1668 nstat
->rx_frame_errors
= hwstat
->rx_align_errs
;
1669 nstat
->rx_crc_errors
= hwstat
->rx_crc_errs
;
1670 nstat
->rx_errors
= (hwstat
->rx_jabber_pkts
+
1671 hwstat
->rx_oversize_pkts
+
1672 hwstat
->rx_missed_pkts
+
1673 hwstat
->rx_crc_align_errs
+
1674 hwstat
->rx_undersize
+
1675 hwstat
->rx_crc_errs
+
1676 hwstat
->rx_align_errs
+
1677 hwstat
->rx_symbol_errs
);
1679 nstat
->tx_aborted_errors
= hwstat
->tx_underruns
;
1681 /* Carrier lost counter seems to be broken for some devices */
1682 nstat
->tx_carrier_errors
= hwstat
->tx_carrier_lost
;
1684 } while (u64_stats_fetch_retry_bh(&hwstat
->syncp
, start
));
1689 static int __b44_load_mcast(struct b44
*bp
, struct net_device
*dev
)
1691 struct netdev_hw_addr
*ha
;
1694 num_ents
= min_t(int, netdev_mc_count(dev
), B44_MCAST_TABLE_SIZE
);
1696 netdev_for_each_mc_addr(ha
, dev
) {
1699 __b44_cam_write(bp
, ha
->addr
, i
++ + 1);
1704 static void __b44_set_rx_mode(struct net_device
*dev
)
1706 struct b44
*bp
= netdev_priv(dev
);
1709 val
= br32(bp
, B44_RXCONFIG
);
1710 val
&= ~(RXCONFIG_PROMISC
| RXCONFIG_ALLMULTI
);
1711 if ((dev
->flags
& IFF_PROMISC
) || (val
& RXCONFIG_CAM_ABSENT
)) {
1712 val
|= RXCONFIG_PROMISC
;
1713 bw32(bp
, B44_RXCONFIG
, val
);
1715 unsigned char zero
[6] = {0, 0, 0, 0, 0, 0};
1718 __b44_set_mac_addr(bp
);
1720 if ((dev
->flags
& IFF_ALLMULTI
) ||
1721 (netdev_mc_count(dev
) > B44_MCAST_TABLE_SIZE
))
1722 val
|= RXCONFIG_ALLMULTI
;
1724 i
= __b44_load_mcast(bp
, dev
);
1727 __b44_cam_write(bp
, zero
, i
);
1729 bw32(bp
, B44_RXCONFIG
, val
);
1730 val
= br32(bp
, B44_CAM_CTRL
);
1731 bw32(bp
, B44_CAM_CTRL
, val
| CAM_CTRL_ENABLE
);
1735 static void b44_set_rx_mode(struct net_device
*dev
)
1737 struct b44
*bp
= netdev_priv(dev
);
1739 spin_lock_irq(&bp
->lock
);
1740 __b44_set_rx_mode(dev
);
1741 spin_unlock_irq(&bp
->lock
);
1744 static u32
b44_get_msglevel(struct net_device
*dev
)
1746 struct b44
*bp
= netdev_priv(dev
);
1747 return bp
->msg_enable
;
1750 static void b44_set_msglevel(struct net_device
*dev
, u32 value
)
1752 struct b44
*bp
= netdev_priv(dev
);
1753 bp
->msg_enable
= value
;
1756 static void b44_get_drvinfo (struct net_device
*dev
, struct ethtool_drvinfo
*info
)
1758 struct b44
*bp
= netdev_priv(dev
);
1759 struct ssb_bus
*bus
= bp
->sdev
->bus
;
1761 strlcpy(info
->driver
, DRV_MODULE_NAME
, sizeof(info
->driver
));
1762 strlcpy(info
->version
, DRV_MODULE_VERSION
, sizeof(info
->version
));
1763 switch (bus
->bustype
) {
1764 case SSB_BUSTYPE_PCI
:
1765 strlcpy(info
->bus_info
, pci_name(bus
->host_pci
), sizeof(info
->bus_info
));
1767 case SSB_BUSTYPE_SSB
:
1768 strlcpy(info
->bus_info
, "SSB", sizeof(info
->bus_info
));
1770 case SSB_BUSTYPE_PCMCIA
:
1771 case SSB_BUSTYPE_SDIO
:
1772 WARN_ON(1); /* A device with this bus does not exist. */
1777 static int b44_nway_reset(struct net_device
*dev
)
1779 struct b44
*bp
= netdev_priv(dev
);
1783 spin_lock_irq(&bp
->lock
);
1784 b44_readphy(bp
, MII_BMCR
, &bmcr
);
1785 b44_readphy(bp
, MII_BMCR
, &bmcr
);
1787 if (bmcr
& BMCR_ANENABLE
) {
1788 b44_writephy(bp
, MII_BMCR
,
1789 bmcr
| BMCR_ANRESTART
);
1792 spin_unlock_irq(&bp
->lock
);
1797 static int b44_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1799 struct b44
*bp
= netdev_priv(dev
);
1801 cmd
->supported
= (SUPPORTED_Autoneg
);
1802 cmd
->supported
|= (SUPPORTED_100baseT_Half
|
1803 SUPPORTED_100baseT_Full
|
1804 SUPPORTED_10baseT_Half
|
1805 SUPPORTED_10baseT_Full
|
1808 cmd
->advertising
= 0;
1809 if (bp
->flags
& B44_FLAG_ADV_10HALF
)
1810 cmd
->advertising
|= ADVERTISED_10baseT_Half
;
1811 if (bp
->flags
& B44_FLAG_ADV_10FULL
)
1812 cmd
->advertising
|= ADVERTISED_10baseT_Full
;
1813 if (bp
->flags
& B44_FLAG_ADV_100HALF
)
1814 cmd
->advertising
|= ADVERTISED_100baseT_Half
;
1815 if (bp
->flags
& B44_FLAG_ADV_100FULL
)
1816 cmd
->advertising
|= ADVERTISED_100baseT_Full
;
1817 cmd
->advertising
|= ADVERTISED_Pause
| ADVERTISED_Asym_Pause
;
1818 ethtool_cmd_speed_set(cmd
, ((bp
->flags
& B44_FLAG_100_BASE_T
) ?
1819 SPEED_100
: SPEED_10
));
1820 cmd
->duplex
= (bp
->flags
& B44_FLAG_FULL_DUPLEX
) ?
1821 DUPLEX_FULL
: DUPLEX_HALF
;
1823 cmd
->phy_address
= bp
->phy_addr
;
1824 cmd
->transceiver
= (bp
->flags
& B44_FLAG_INTERNAL_PHY
) ?
1825 XCVR_INTERNAL
: XCVR_EXTERNAL
;
1826 cmd
->autoneg
= (bp
->flags
& B44_FLAG_FORCE_LINK
) ?
1827 AUTONEG_DISABLE
: AUTONEG_ENABLE
;
1828 if (cmd
->autoneg
== AUTONEG_ENABLE
)
1829 cmd
->advertising
|= ADVERTISED_Autoneg
;
1830 if (!netif_running(dev
)){
1831 ethtool_cmd_speed_set(cmd
, 0);
1839 static int b44_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1841 struct b44
*bp
= netdev_priv(dev
);
1842 u32 speed
= ethtool_cmd_speed(cmd
);
1844 /* We do not support gigabit. */
1845 if (cmd
->autoneg
== AUTONEG_ENABLE
) {
1846 if (cmd
->advertising
&
1847 (ADVERTISED_1000baseT_Half
|
1848 ADVERTISED_1000baseT_Full
))
1850 } else if ((speed
!= SPEED_100
&&
1851 speed
!= SPEED_10
) ||
1852 (cmd
->duplex
!= DUPLEX_HALF
&&
1853 cmd
->duplex
!= DUPLEX_FULL
)) {
1857 spin_lock_irq(&bp
->lock
);
1859 if (cmd
->autoneg
== AUTONEG_ENABLE
) {
1860 bp
->flags
&= ~(B44_FLAG_FORCE_LINK
|
1861 B44_FLAG_100_BASE_T
|
1862 B44_FLAG_FULL_DUPLEX
|
1863 B44_FLAG_ADV_10HALF
|
1864 B44_FLAG_ADV_10FULL
|
1865 B44_FLAG_ADV_100HALF
|
1866 B44_FLAG_ADV_100FULL
);
1867 if (cmd
->advertising
== 0) {
1868 bp
->flags
|= (B44_FLAG_ADV_10HALF
|
1869 B44_FLAG_ADV_10FULL
|
1870 B44_FLAG_ADV_100HALF
|
1871 B44_FLAG_ADV_100FULL
);
1873 if (cmd
->advertising
& ADVERTISED_10baseT_Half
)
1874 bp
->flags
|= B44_FLAG_ADV_10HALF
;
1875 if (cmd
->advertising
& ADVERTISED_10baseT_Full
)
1876 bp
->flags
|= B44_FLAG_ADV_10FULL
;
1877 if (cmd
->advertising
& ADVERTISED_100baseT_Half
)
1878 bp
->flags
|= B44_FLAG_ADV_100HALF
;
1879 if (cmd
->advertising
& ADVERTISED_100baseT_Full
)
1880 bp
->flags
|= B44_FLAG_ADV_100FULL
;
1883 bp
->flags
|= B44_FLAG_FORCE_LINK
;
1884 bp
->flags
&= ~(B44_FLAG_100_BASE_T
| B44_FLAG_FULL_DUPLEX
);
1885 if (speed
== SPEED_100
)
1886 bp
->flags
|= B44_FLAG_100_BASE_T
;
1887 if (cmd
->duplex
== DUPLEX_FULL
)
1888 bp
->flags
|= B44_FLAG_FULL_DUPLEX
;
1891 if (netif_running(dev
))
1894 spin_unlock_irq(&bp
->lock
);
1899 static void b44_get_ringparam(struct net_device
*dev
,
1900 struct ethtool_ringparam
*ering
)
1902 struct b44
*bp
= netdev_priv(dev
);
1904 ering
->rx_max_pending
= B44_RX_RING_SIZE
- 1;
1905 ering
->rx_pending
= bp
->rx_pending
;
1907 /* XXX ethtool lacks a tx_max_pending, oops... */
1910 static int b44_set_ringparam(struct net_device
*dev
,
1911 struct ethtool_ringparam
*ering
)
1913 struct b44
*bp
= netdev_priv(dev
);
1915 if ((ering
->rx_pending
> B44_RX_RING_SIZE
- 1) ||
1916 (ering
->rx_mini_pending
!= 0) ||
1917 (ering
->rx_jumbo_pending
!= 0) ||
1918 (ering
->tx_pending
> B44_TX_RING_SIZE
- 1))
1921 spin_lock_irq(&bp
->lock
);
1923 bp
->rx_pending
= ering
->rx_pending
;
1924 bp
->tx_pending
= ering
->tx_pending
;
1928 b44_init_hw(bp
, B44_FULL_RESET
);
1929 netif_wake_queue(bp
->dev
);
1930 spin_unlock_irq(&bp
->lock
);
1932 b44_enable_ints(bp
);
1937 static void b44_get_pauseparam(struct net_device
*dev
,
1938 struct ethtool_pauseparam
*epause
)
1940 struct b44
*bp
= netdev_priv(dev
);
1943 (bp
->flags
& B44_FLAG_PAUSE_AUTO
) != 0;
1945 (bp
->flags
& B44_FLAG_RX_PAUSE
) != 0;
1947 (bp
->flags
& B44_FLAG_TX_PAUSE
) != 0;
1950 static int b44_set_pauseparam(struct net_device
*dev
,
1951 struct ethtool_pauseparam
*epause
)
1953 struct b44
*bp
= netdev_priv(dev
);
1955 spin_lock_irq(&bp
->lock
);
1956 if (epause
->autoneg
)
1957 bp
->flags
|= B44_FLAG_PAUSE_AUTO
;
1959 bp
->flags
&= ~B44_FLAG_PAUSE_AUTO
;
1960 if (epause
->rx_pause
)
1961 bp
->flags
|= B44_FLAG_RX_PAUSE
;
1963 bp
->flags
&= ~B44_FLAG_RX_PAUSE
;
1964 if (epause
->tx_pause
)
1965 bp
->flags
|= B44_FLAG_TX_PAUSE
;
1967 bp
->flags
&= ~B44_FLAG_TX_PAUSE
;
1968 if (bp
->flags
& B44_FLAG_PAUSE_AUTO
) {
1971 b44_init_hw(bp
, B44_FULL_RESET
);
1973 __b44_set_flow_ctrl(bp
, bp
->flags
);
1975 spin_unlock_irq(&bp
->lock
);
1977 b44_enable_ints(bp
);
1982 static void b44_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
1986 memcpy(data
, *b44_gstrings
, sizeof(b44_gstrings
));
1991 static int b44_get_sset_count(struct net_device
*dev
, int sset
)
1995 return ARRAY_SIZE(b44_gstrings
);
2001 static void b44_get_ethtool_stats(struct net_device
*dev
,
2002 struct ethtool_stats
*stats
, u64
*data
)
2004 struct b44
*bp
= netdev_priv(dev
);
2005 struct b44_hw_stats
*hwstat
= &bp
->hw_stats
;
2006 u64
*data_src
, *data_dst
;
2010 spin_lock_irq(&bp
->lock
);
2011 b44_stats_update(bp
);
2012 spin_unlock_irq(&bp
->lock
);
2015 data_src
= &hwstat
->tx_good_octets
;
2017 start
= u64_stats_fetch_begin_bh(&hwstat
->syncp
);
2019 for (i
= 0; i
< ARRAY_SIZE(b44_gstrings
); i
++)
2020 *data_dst
++ = *data_src
++;
2022 } while (u64_stats_fetch_retry_bh(&hwstat
->syncp
, start
));
2025 static void b44_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
2027 struct b44
*bp
= netdev_priv(dev
);
2029 wol
->supported
= WAKE_MAGIC
;
2030 if (bp
->flags
& B44_FLAG_WOL_ENABLE
)
2031 wol
->wolopts
= WAKE_MAGIC
;
2034 memset(&wol
->sopass
, 0, sizeof(wol
->sopass
));
2037 static int b44_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
2039 struct b44
*bp
= netdev_priv(dev
);
2041 spin_lock_irq(&bp
->lock
);
2042 if (wol
->wolopts
& WAKE_MAGIC
)
2043 bp
->flags
|= B44_FLAG_WOL_ENABLE
;
2045 bp
->flags
&= ~B44_FLAG_WOL_ENABLE
;
2046 spin_unlock_irq(&bp
->lock
);
2051 static const struct ethtool_ops b44_ethtool_ops
= {
2052 .get_drvinfo
= b44_get_drvinfo
,
2053 .get_settings
= b44_get_settings
,
2054 .set_settings
= b44_set_settings
,
2055 .nway_reset
= b44_nway_reset
,
2056 .get_link
= ethtool_op_get_link
,
2057 .get_wol
= b44_get_wol
,
2058 .set_wol
= b44_set_wol
,
2059 .get_ringparam
= b44_get_ringparam
,
2060 .set_ringparam
= b44_set_ringparam
,
2061 .get_pauseparam
= b44_get_pauseparam
,
2062 .set_pauseparam
= b44_set_pauseparam
,
2063 .get_msglevel
= b44_get_msglevel
,
2064 .set_msglevel
= b44_set_msglevel
,
2065 .get_strings
= b44_get_strings
,
2066 .get_sset_count
= b44_get_sset_count
,
2067 .get_ethtool_stats
= b44_get_ethtool_stats
,
2070 static int b44_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
2072 struct mii_ioctl_data
*data
= if_mii(ifr
);
2073 struct b44
*bp
= netdev_priv(dev
);
2076 if (!netif_running(dev
))
2079 spin_lock_irq(&bp
->lock
);
2080 err
= generic_mii_ioctl(&bp
->mii_if
, data
, cmd
, NULL
);
2081 spin_unlock_irq(&bp
->lock
);
2086 static int __devinit
b44_get_invariants(struct b44
*bp
)
2088 struct ssb_device
*sdev
= bp
->sdev
;
2092 bp
->dma_offset
= ssb_dma_translation(sdev
);
2094 if (sdev
->bus
->bustype
== SSB_BUSTYPE_SSB
&&
2096 addr
= sdev
->bus
->sprom
.et1mac
;
2097 bp
->phy_addr
= sdev
->bus
->sprom
.et1phyaddr
;
2099 addr
= sdev
->bus
->sprom
.et0mac
;
2100 bp
->phy_addr
= sdev
->bus
->sprom
.et0phyaddr
;
2102 /* Some ROMs have buggy PHY addresses with the high
2103 * bits set (sign extension?). Truncate them to a
2104 * valid PHY address. */
2105 bp
->phy_addr
&= 0x1F;
2107 memcpy(bp
->dev
->dev_addr
, addr
, 6);
2109 if (!is_valid_ether_addr(&bp
->dev
->dev_addr
[0])){
2110 pr_err("Invalid MAC address found in EEPROM\n");
2114 memcpy(bp
->dev
->perm_addr
, bp
->dev
->dev_addr
, bp
->dev
->addr_len
);
2116 bp
->imask
= IMASK_DEF
;
2118 /* XXX - really required?
2119 bp->flags |= B44_FLAG_BUGGY_TXPTR;
2122 if (bp
->sdev
->id
.revision
>= 7)
2123 bp
->flags
|= B44_FLAG_B0_ANDLATER
;
2128 static const struct net_device_ops b44_netdev_ops
= {
2129 .ndo_open
= b44_open
,
2130 .ndo_stop
= b44_close
,
2131 .ndo_start_xmit
= b44_start_xmit
,
2132 .ndo_get_stats64
= b44_get_stats64
,
2133 .ndo_set_rx_mode
= b44_set_rx_mode
,
2134 .ndo_set_mac_address
= b44_set_mac_addr
,
2135 .ndo_validate_addr
= eth_validate_addr
,
2136 .ndo_do_ioctl
= b44_ioctl
,
2137 .ndo_tx_timeout
= b44_tx_timeout
,
2138 .ndo_change_mtu
= b44_change_mtu
,
2139 #ifdef CONFIG_NET_POLL_CONTROLLER
2140 .ndo_poll_controller
= b44_poll_controller
,
2144 static int __devinit
b44_init_one(struct ssb_device
*sdev
,
2145 const struct ssb_device_id
*ent
)
2147 struct net_device
*dev
;
2153 pr_info_once("%s version %s\n", DRV_DESCRIPTION
, DRV_MODULE_VERSION
);
2155 dev
= alloc_etherdev(sizeof(*bp
));
2161 SET_NETDEV_DEV(dev
, sdev
->dev
);
2163 /* No interesting netdevice features in this card... */
2166 bp
= netdev_priv(dev
);
2169 bp
->force_copybreak
= 0;
2171 bp
->msg_enable
= netif_msg_init(b44_debug
, B44_DEF_MSG_ENABLE
);
2173 spin_lock_init(&bp
->lock
);
2175 bp
->rx_pending
= B44_DEF_RX_RING_PENDING
;
2176 bp
->tx_pending
= B44_DEF_TX_RING_PENDING
;
2178 dev
->netdev_ops
= &b44_netdev_ops
;
2179 netif_napi_add(dev
, &bp
->napi
, b44_poll
, 64);
2180 dev
->watchdog_timeo
= B44_TX_TIMEOUT
;
2181 dev
->irq
= sdev
->irq
;
2182 SET_ETHTOOL_OPS(dev
, &b44_ethtool_ops
);
2184 err
= ssb_bus_powerup(sdev
->bus
, 0);
2187 "Failed to powerup the bus\n");
2188 goto err_out_free_dev
;
2191 if (dma_set_mask(sdev
->dma_dev
, DMA_BIT_MASK(30)) ||
2192 dma_set_coherent_mask(sdev
->dma_dev
, DMA_BIT_MASK(30))) {
2194 "Required 30BIT DMA mask unsupported by the system\n");
2195 goto err_out_powerdown
;
2198 err
= b44_get_invariants(bp
);
2201 "Problem fetching invariants of chip, aborting\n");
2202 goto err_out_powerdown
;
2205 bp
->mii_if
.dev
= dev
;
2206 bp
->mii_if
.mdio_read
= b44_mii_read
;
2207 bp
->mii_if
.mdio_write
= b44_mii_write
;
2208 bp
->mii_if
.phy_id
= bp
->phy_addr
;
2209 bp
->mii_if
.phy_id_mask
= 0x1f;
2210 bp
->mii_if
.reg_num_mask
= 0x1f;
2212 /* By default, advertise all speed/duplex settings. */
2213 bp
->flags
|= (B44_FLAG_ADV_10HALF
| B44_FLAG_ADV_10FULL
|
2214 B44_FLAG_ADV_100HALF
| B44_FLAG_ADV_100FULL
);
2216 /* By default, auto-negotiate PAUSE. */
2217 bp
->flags
|= B44_FLAG_PAUSE_AUTO
;
2219 err
= register_netdev(dev
);
2221 dev_err(sdev
->dev
, "Cannot register net device, aborting\n");
2222 goto err_out_powerdown
;
2225 netif_carrier_off(dev
);
2227 ssb_set_drvdata(sdev
, dev
);
2229 /* Chip reset provides power to the b44 MAC & PCI cores, which
2230 * is necessary for MAC register access.
2232 b44_chip_reset(bp
, B44_CHIP_RESET_FULL
);
2234 /* do a phy reset to test if there is an active phy */
2235 if (b44_phy_reset(bp
) < 0)
2236 bp
->phy_addr
= B44_PHY_ADDR_NO_PHY
;
2238 netdev_info(dev
, "%s %pM\n", DRV_DESCRIPTION
, dev
->dev_addr
);
2243 ssb_bus_may_powerdown(sdev
->bus
);
2252 static void __devexit
b44_remove_one(struct ssb_device
*sdev
)
2254 struct net_device
*dev
= ssb_get_drvdata(sdev
);
2256 unregister_netdev(dev
);
2257 ssb_device_disable(sdev
, 0);
2258 ssb_bus_may_powerdown(sdev
->bus
);
2260 ssb_pcihost_set_power_state(sdev
, PCI_D3hot
);
2261 ssb_set_drvdata(sdev
, NULL
);
2264 static int b44_suspend(struct ssb_device
*sdev
, pm_message_t state
)
2266 struct net_device
*dev
= ssb_get_drvdata(sdev
);
2267 struct b44
*bp
= netdev_priv(dev
);
2269 if (!netif_running(dev
))
2272 del_timer_sync(&bp
->timer
);
2274 spin_lock_irq(&bp
->lock
);
2277 netif_carrier_off(bp
->dev
);
2278 netif_device_detach(bp
->dev
);
2281 spin_unlock_irq(&bp
->lock
);
2283 free_irq(dev
->irq
, dev
);
2284 if (bp
->flags
& B44_FLAG_WOL_ENABLE
) {
2285 b44_init_hw(bp
, B44_PARTIAL_RESET
);
2289 ssb_pcihost_set_power_state(sdev
, PCI_D3hot
);
2293 static int b44_resume(struct ssb_device
*sdev
)
2295 struct net_device
*dev
= ssb_get_drvdata(sdev
);
2296 struct b44
*bp
= netdev_priv(dev
);
2299 rc
= ssb_bus_powerup(sdev
->bus
, 0);
2302 "Failed to powerup the bus\n");
2306 if (!netif_running(dev
))
2309 spin_lock_irq(&bp
->lock
);
2311 b44_init_hw(bp
, B44_FULL_RESET
);
2312 spin_unlock_irq(&bp
->lock
);
2315 * As a shared interrupt, the handler can be called immediately. To be
2316 * able to check the interrupt status the hardware must already be
2317 * powered back on (b44_init_hw).
2319 rc
= request_irq(dev
->irq
, b44_interrupt
, IRQF_SHARED
, dev
->name
, dev
);
2321 netdev_err(dev
, "request_irq failed\n");
2322 spin_lock_irq(&bp
->lock
);
2325 spin_unlock_irq(&bp
->lock
);
2329 netif_device_attach(bp
->dev
);
2331 b44_enable_ints(bp
);
2332 netif_wake_queue(dev
);
2334 mod_timer(&bp
->timer
, jiffies
+ 1);
2339 static struct ssb_driver b44_ssb_driver
= {
2340 .name
= DRV_MODULE_NAME
,
2341 .id_table
= b44_ssb_tbl
,
2342 .probe
= b44_init_one
,
2343 .remove
= __devexit_p(b44_remove_one
),
2344 .suspend
= b44_suspend
,
2345 .resume
= b44_resume
,
2348 static inline int __init
b44_pci_init(void)
2351 #ifdef CONFIG_B44_PCI
2352 err
= ssb_pcihost_register(&b44_pci_driver
);
2357 static inline void b44_pci_exit(void)
2359 #ifdef CONFIG_B44_PCI
2360 ssb_pcihost_unregister(&b44_pci_driver
);
2364 static int __init
b44_init(void)
2366 unsigned int dma_desc_align_size
= dma_get_cache_alignment();
2369 /* Setup paramaters for syncing RX/TX DMA descriptors */
2370 dma_desc_sync_size
= max_t(unsigned int, dma_desc_align_size
, sizeof(struct dma_desc
));
2372 err
= b44_pci_init();
2375 err
= ssb_driver_register(&b44_ssb_driver
);
2381 static void __exit
b44_cleanup(void)
2383 ssb_driver_unregister(&b44_ssb_driver
);
2387 module_init(b44_init
);
2388 module_exit(b44_cleanup
);