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UBUNTU: Ubuntu-4.15.0-96.97
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / broadcom / bcm63xx_enet.c
1 /*
2 * Driver for BCM963xx builtin Ethernet mac
3 *
4 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/module.h>
23 #include <linux/clk.h>
24 #include <linux/etherdevice.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
27 #include <linux/ethtool.h>
28 #include <linux/crc32.h>
29 #include <linux/err.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/platform_device.h>
32 #include <linux/if_vlan.h>
33
34 #include <bcm63xx_dev_enet.h>
35 #include "bcm63xx_enet.h"
36
37 static char bcm_enet_driver_name[] = "bcm63xx_enet";
38 static char bcm_enet_driver_version[] = "1.0";
39
40 static int copybreak __read_mostly = 128;
41 module_param(copybreak, int, 0);
42 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
43
44 /* io registers memory shared between all devices */
45 static void __iomem *bcm_enet_shared_base[3];
46
47 /*
48 * io helpers to access mac registers
49 */
50 static inline u32 enet_readl(struct bcm_enet_priv *priv, u32 off)
51 {
52 return bcm_readl(priv->base + off);
53 }
54
55 static inline void enet_writel(struct bcm_enet_priv *priv,
56 u32 val, u32 off)
57 {
58 bcm_writel(val, priv->base + off);
59 }
60
61 /*
62 * io helpers to access switch registers
63 */
64 static inline u32 enetsw_readl(struct bcm_enet_priv *priv, u32 off)
65 {
66 return bcm_readl(priv->base + off);
67 }
68
69 static inline void enetsw_writel(struct bcm_enet_priv *priv,
70 u32 val, u32 off)
71 {
72 bcm_writel(val, priv->base + off);
73 }
74
75 static inline u16 enetsw_readw(struct bcm_enet_priv *priv, u32 off)
76 {
77 return bcm_readw(priv->base + off);
78 }
79
80 static inline void enetsw_writew(struct bcm_enet_priv *priv,
81 u16 val, u32 off)
82 {
83 bcm_writew(val, priv->base + off);
84 }
85
86 static inline u8 enetsw_readb(struct bcm_enet_priv *priv, u32 off)
87 {
88 return bcm_readb(priv->base + off);
89 }
90
91 static inline void enetsw_writeb(struct bcm_enet_priv *priv,
92 u8 val, u32 off)
93 {
94 bcm_writeb(val, priv->base + off);
95 }
96
97
98 /* io helpers to access shared registers */
99 static inline u32 enet_dma_readl(struct bcm_enet_priv *priv, u32 off)
100 {
101 return bcm_readl(bcm_enet_shared_base[0] + off);
102 }
103
104 static inline void enet_dma_writel(struct bcm_enet_priv *priv,
105 u32 val, u32 off)
106 {
107 bcm_writel(val, bcm_enet_shared_base[0] + off);
108 }
109
110 static inline u32 enet_dmac_readl(struct bcm_enet_priv *priv, u32 off, int chan)
111 {
112 return bcm_readl(bcm_enet_shared_base[1] +
113 bcm63xx_enetdmacreg(off) + chan * priv->dma_chan_width);
114 }
115
116 static inline void enet_dmac_writel(struct bcm_enet_priv *priv,
117 u32 val, u32 off, int chan)
118 {
119 bcm_writel(val, bcm_enet_shared_base[1] +
120 bcm63xx_enetdmacreg(off) + chan * priv->dma_chan_width);
121 }
122
123 static inline u32 enet_dmas_readl(struct bcm_enet_priv *priv, u32 off, int chan)
124 {
125 return bcm_readl(bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width);
126 }
127
128 static inline void enet_dmas_writel(struct bcm_enet_priv *priv,
129 u32 val, u32 off, int chan)
130 {
131 bcm_writel(val, bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width);
132 }
133
134 /*
135 * write given data into mii register and wait for transfer to end
136 * with timeout (average measured transfer time is 25us)
137 */
138 static int do_mdio_op(struct bcm_enet_priv *priv, unsigned int data)
139 {
140 int limit;
141
142 /* make sure mii interrupt status is cleared */
143 enet_writel(priv, ENET_IR_MII, ENET_IR_REG);
144
145 enet_writel(priv, data, ENET_MIIDATA_REG);
146 wmb();
147
148 /* busy wait on mii interrupt bit, with timeout */
149 limit = 1000;
150 do {
151 if (enet_readl(priv, ENET_IR_REG) & ENET_IR_MII)
152 break;
153 udelay(1);
154 } while (limit-- > 0);
155
156 return (limit < 0) ? 1 : 0;
157 }
158
159 /*
160 * MII internal read callback
161 */
162 static int bcm_enet_mdio_read(struct bcm_enet_priv *priv, int mii_id,
163 int regnum)
164 {
165 u32 tmp, val;
166
167 tmp = regnum << ENET_MIIDATA_REG_SHIFT;
168 tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
169 tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
170 tmp |= ENET_MIIDATA_OP_READ_MASK;
171
172 if (do_mdio_op(priv, tmp))
173 return -1;
174
175 val = enet_readl(priv, ENET_MIIDATA_REG);
176 val &= 0xffff;
177 return val;
178 }
179
180 /*
181 * MII internal write callback
182 */
183 static int bcm_enet_mdio_write(struct bcm_enet_priv *priv, int mii_id,
184 int regnum, u16 value)
185 {
186 u32 tmp;
187
188 tmp = (value & 0xffff) << ENET_MIIDATA_DATA_SHIFT;
189 tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
190 tmp |= regnum << ENET_MIIDATA_REG_SHIFT;
191 tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
192 tmp |= ENET_MIIDATA_OP_WRITE_MASK;
193
194 (void)do_mdio_op(priv, tmp);
195 return 0;
196 }
197
198 /*
199 * MII read callback from phylib
200 */
201 static int bcm_enet_mdio_read_phylib(struct mii_bus *bus, int mii_id,
202 int regnum)
203 {
204 return bcm_enet_mdio_read(bus->priv, mii_id, regnum);
205 }
206
207 /*
208 * MII write callback from phylib
209 */
210 static int bcm_enet_mdio_write_phylib(struct mii_bus *bus, int mii_id,
211 int regnum, u16 value)
212 {
213 return bcm_enet_mdio_write(bus->priv, mii_id, regnum, value);
214 }
215
216 /*
217 * MII read callback from mii core
218 */
219 static int bcm_enet_mdio_read_mii(struct net_device *dev, int mii_id,
220 int regnum)
221 {
222 return bcm_enet_mdio_read(netdev_priv(dev), mii_id, regnum);
223 }
224
225 /*
226 * MII write callback from mii core
227 */
228 static void bcm_enet_mdio_write_mii(struct net_device *dev, int mii_id,
229 int regnum, int value)
230 {
231 bcm_enet_mdio_write(netdev_priv(dev), mii_id, regnum, value);
232 }
233
234 /*
235 * refill rx queue
236 */
237 static int bcm_enet_refill_rx(struct net_device *dev)
238 {
239 struct bcm_enet_priv *priv;
240
241 priv = netdev_priv(dev);
242
243 while (priv->rx_desc_count < priv->rx_ring_size) {
244 struct bcm_enet_desc *desc;
245 struct sk_buff *skb;
246 dma_addr_t p;
247 int desc_idx;
248 u32 len_stat;
249
250 desc_idx = priv->rx_dirty_desc;
251 desc = &priv->rx_desc_cpu[desc_idx];
252
253 if (!priv->rx_skb[desc_idx]) {
254 skb = netdev_alloc_skb(dev, priv->rx_skb_size);
255 if (!skb)
256 break;
257 priv->rx_skb[desc_idx] = skb;
258 p = dma_map_single(&priv->pdev->dev, skb->data,
259 priv->rx_skb_size,
260 DMA_FROM_DEVICE);
261 desc->address = p;
262 }
263
264 len_stat = priv->rx_skb_size << DMADESC_LENGTH_SHIFT;
265 len_stat |= DMADESC_OWNER_MASK;
266 if (priv->rx_dirty_desc == priv->rx_ring_size - 1) {
267 len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
268 priv->rx_dirty_desc = 0;
269 } else {
270 priv->rx_dirty_desc++;
271 }
272 wmb();
273 desc->len_stat = len_stat;
274
275 priv->rx_desc_count++;
276
277 /* tell dma engine we allocated one buffer */
278 if (priv->dma_has_sram)
279 enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan));
280 else
281 enet_dmac_writel(priv, 1, ENETDMAC_BUFALLOC, priv->rx_chan);
282 }
283
284 /* If rx ring is still empty, set a timer to try allocating
285 * again at a later time. */
286 if (priv->rx_desc_count == 0 && netif_running(dev)) {
287 dev_warn(&priv->pdev->dev, "unable to refill rx ring\n");
288 priv->rx_timeout.expires = jiffies + HZ;
289 add_timer(&priv->rx_timeout);
290 }
291
292 return 0;
293 }
294
295 /*
296 * timer callback to defer refill rx queue in case we're OOM
297 */
298 static void bcm_enet_refill_rx_timer(struct timer_list *t)
299 {
300 struct bcm_enet_priv *priv = from_timer(priv, t, rx_timeout);
301 struct net_device *dev = priv->net_dev;
302
303 spin_lock(&priv->rx_lock);
304 bcm_enet_refill_rx(dev);
305 spin_unlock(&priv->rx_lock);
306 }
307
308 /*
309 * extract packet from rx queue
310 */
311 static int bcm_enet_receive_queue(struct net_device *dev, int budget)
312 {
313 struct bcm_enet_priv *priv;
314 struct device *kdev;
315 int processed;
316
317 priv = netdev_priv(dev);
318 kdev = &priv->pdev->dev;
319 processed = 0;
320
321 /* don't scan ring further than number of refilled
322 * descriptor */
323 if (budget > priv->rx_desc_count)
324 budget = priv->rx_desc_count;
325
326 do {
327 struct bcm_enet_desc *desc;
328 struct sk_buff *skb;
329 int desc_idx;
330 u32 len_stat;
331 unsigned int len;
332
333 desc_idx = priv->rx_curr_desc;
334 desc = &priv->rx_desc_cpu[desc_idx];
335
336 /* make sure we actually read the descriptor status at
337 * each loop */
338 rmb();
339
340 len_stat = desc->len_stat;
341
342 /* break if dma ownership belongs to hw */
343 if (len_stat & DMADESC_OWNER_MASK)
344 break;
345
346 processed++;
347 priv->rx_curr_desc++;
348 if (priv->rx_curr_desc == priv->rx_ring_size)
349 priv->rx_curr_desc = 0;
350 priv->rx_desc_count--;
351
352 /* if the packet does not have start of packet _and_
353 * end of packet flag set, then just recycle it */
354 if ((len_stat & (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) !=
355 (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) {
356 dev->stats.rx_dropped++;
357 continue;
358 }
359
360 /* recycle packet if it's marked as bad */
361 if (!priv->enet_is_sw &&
362 unlikely(len_stat & DMADESC_ERR_MASK)) {
363 dev->stats.rx_errors++;
364
365 if (len_stat & DMADESC_OVSIZE_MASK)
366 dev->stats.rx_length_errors++;
367 if (len_stat & DMADESC_CRC_MASK)
368 dev->stats.rx_crc_errors++;
369 if (len_stat & DMADESC_UNDER_MASK)
370 dev->stats.rx_frame_errors++;
371 if (len_stat & DMADESC_OV_MASK)
372 dev->stats.rx_fifo_errors++;
373 continue;
374 }
375
376 /* valid packet */
377 skb = priv->rx_skb[desc_idx];
378 len = (len_stat & DMADESC_LENGTH_MASK) >> DMADESC_LENGTH_SHIFT;
379 /* don't include FCS */
380 len -= 4;
381
382 if (len < copybreak) {
383 struct sk_buff *nskb;
384
385 nskb = napi_alloc_skb(&priv->napi, len);
386 if (!nskb) {
387 /* forget packet, just rearm desc */
388 dev->stats.rx_dropped++;
389 continue;
390 }
391
392 dma_sync_single_for_cpu(kdev, desc->address,
393 len, DMA_FROM_DEVICE);
394 memcpy(nskb->data, skb->data, len);
395 dma_sync_single_for_device(kdev, desc->address,
396 len, DMA_FROM_DEVICE);
397 skb = nskb;
398 } else {
399 dma_unmap_single(&priv->pdev->dev, desc->address,
400 priv->rx_skb_size, DMA_FROM_DEVICE);
401 priv->rx_skb[desc_idx] = NULL;
402 }
403
404 skb_put(skb, len);
405 skb->protocol = eth_type_trans(skb, dev);
406 dev->stats.rx_packets++;
407 dev->stats.rx_bytes += len;
408 netif_receive_skb(skb);
409
410 } while (--budget > 0);
411
412 if (processed || !priv->rx_desc_count) {
413 bcm_enet_refill_rx(dev);
414
415 /* kick rx dma */
416 enet_dmac_writel(priv, priv->dma_chan_en_mask,
417 ENETDMAC_CHANCFG, priv->rx_chan);
418 }
419
420 return processed;
421 }
422
423
424 /*
425 * try to or force reclaim of transmitted buffers
426 */
427 static int bcm_enet_tx_reclaim(struct net_device *dev, int force)
428 {
429 struct bcm_enet_priv *priv;
430 int released;
431
432 priv = netdev_priv(dev);
433 released = 0;
434
435 while (priv->tx_desc_count < priv->tx_ring_size) {
436 struct bcm_enet_desc *desc;
437 struct sk_buff *skb;
438
439 /* We run in a bh and fight against start_xmit, which
440 * is called with bh disabled */
441 spin_lock(&priv->tx_lock);
442
443 desc = &priv->tx_desc_cpu[priv->tx_dirty_desc];
444
445 if (!force && (desc->len_stat & DMADESC_OWNER_MASK)) {
446 spin_unlock(&priv->tx_lock);
447 break;
448 }
449
450 /* ensure other field of the descriptor were not read
451 * before we checked ownership */
452 rmb();
453
454 skb = priv->tx_skb[priv->tx_dirty_desc];
455 priv->tx_skb[priv->tx_dirty_desc] = NULL;
456 dma_unmap_single(&priv->pdev->dev, desc->address, skb->len,
457 DMA_TO_DEVICE);
458
459 priv->tx_dirty_desc++;
460 if (priv->tx_dirty_desc == priv->tx_ring_size)
461 priv->tx_dirty_desc = 0;
462 priv->tx_desc_count++;
463
464 spin_unlock(&priv->tx_lock);
465
466 if (desc->len_stat & DMADESC_UNDER_MASK)
467 dev->stats.tx_errors++;
468
469 dev_kfree_skb(skb);
470 released++;
471 }
472
473 if (netif_queue_stopped(dev) && released)
474 netif_wake_queue(dev);
475
476 return released;
477 }
478
479 /*
480 * poll func, called by network core
481 */
482 static int bcm_enet_poll(struct napi_struct *napi, int budget)
483 {
484 struct bcm_enet_priv *priv;
485 struct net_device *dev;
486 int rx_work_done;
487
488 priv = container_of(napi, struct bcm_enet_priv, napi);
489 dev = priv->net_dev;
490
491 /* ack interrupts */
492 enet_dmac_writel(priv, priv->dma_chan_int_mask,
493 ENETDMAC_IR, priv->rx_chan);
494 enet_dmac_writel(priv, priv->dma_chan_int_mask,
495 ENETDMAC_IR, priv->tx_chan);
496
497 /* reclaim sent skb */
498 bcm_enet_tx_reclaim(dev, 0);
499
500 spin_lock(&priv->rx_lock);
501 rx_work_done = bcm_enet_receive_queue(dev, budget);
502 spin_unlock(&priv->rx_lock);
503
504 if (rx_work_done >= budget) {
505 /* rx queue is not yet empty/clean */
506 return rx_work_done;
507 }
508
509 /* no more packet in rx/tx queue, remove device from poll
510 * queue */
511 napi_complete_done(napi, rx_work_done);
512
513 /* restore rx/tx interrupt */
514 enet_dmac_writel(priv, priv->dma_chan_int_mask,
515 ENETDMAC_IRMASK, priv->rx_chan);
516 enet_dmac_writel(priv, priv->dma_chan_int_mask,
517 ENETDMAC_IRMASK, priv->tx_chan);
518
519 return rx_work_done;
520 }
521
522 /*
523 * mac interrupt handler
524 */
525 static irqreturn_t bcm_enet_isr_mac(int irq, void *dev_id)
526 {
527 struct net_device *dev;
528 struct bcm_enet_priv *priv;
529 u32 stat;
530
531 dev = dev_id;
532 priv = netdev_priv(dev);
533
534 stat = enet_readl(priv, ENET_IR_REG);
535 if (!(stat & ENET_IR_MIB))
536 return IRQ_NONE;
537
538 /* clear & mask interrupt */
539 enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
540 enet_writel(priv, 0, ENET_IRMASK_REG);
541
542 /* read mib registers in workqueue */
543 schedule_work(&priv->mib_update_task);
544
545 return IRQ_HANDLED;
546 }
547
548 /*
549 * rx/tx dma interrupt handler
550 */
551 static irqreturn_t bcm_enet_isr_dma(int irq, void *dev_id)
552 {
553 struct net_device *dev;
554 struct bcm_enet_priv *priv;
555
556 dev = dev_id;
557 priv = netdev_priv(dev);
558
559 /* mask rx/tx interrupts */
560 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
561 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
562
563 napi_schedule(&priv->napi);
564
565 return IRQ_HANDLED;
566 }
567
568 /*
569 * tx request callback
570 */
571 static netdev_tx_t
572 bcm_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
573 {
574 struct bcm_enet_priv *priv;
575 struct bcm_enet_desc *desc;
576 u32 len_stat;
577 netdev_tx_t ret;
578
579 priv = netdev_priv(dev);
580
581 /* lock against tx reclaim */
582 spin_lock(&priv->tx_lock);
583
584 /* make sure the tx hw queue is not full, should not happen
585 * since we stop queue before it's the case */
586 if (unlikely(!priv->tx_desc_count)) {
587 netif_stop_queue(dev);
588 dev_err(&priv->pdev->dev, "xmit called with no tx desc "
589 "available?\n");
590 ret = NETDEV_TX_BUSY;
591 goto out_unlock;
592 }
593
594 /* pad small packets sent on a switch device */
595 if (priv->enet_is_sw && skb->len < 64) {
596 int needed = 64 - skb->len;
597 char *data;
598
599 if (unlikely(skb_tailroom(skb) < needed)) {
600 struct sk_buff *nskb;
601
602 nskb = skb_copy_expand(skb, 0, needed, GFP_ATOMIC);
603 if (!nskb) {
604 ret = NETDEV_TX_BUSY;
605 goto out_unlock;
606 }
607 dev_kfree_skb(skb);
608 skb = nskb;
609 }
610 data = skb_put_zero(skb, needed);
611 }
612
613 /* point to the next available desc */
614 desc = &priv->tx_desc_cpu[priv->tx_curr_desc];
615 priv->tx_skb[priv->tx_curr_desc] = skb;
616
617 /* fill descriptor */
618 desc->address = dma_map_single(&priv->pdev->dev, skb->data, skb->len,
619 DMA_TO_DEVICE);
620
621 len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK;
622 len_stat |= (DMADESC_ESOP_MASK >> priv->dma_desc_shift) |
623 DMADESC_APPEND_CRC |
624 DMADESC_OWNER_MASK;
625
626 priv->tx_curr_desc++;
627 if (priv->tx_curr_desc == priv->tx_ring_size) {
628 priv->tx_curr_desc = 0;
629 len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
630 }
631 priv->tx_desc_count--;
632
633 /* dma might be already polling, make sure we update desc
634 * fields in correct order */
635 wmb();
636 desc->len_stat = len_stat;
637 wmb();
638
639 /* kick tx dma */
640 enet_dmac_writel(priv, priv->dma_chan_en_mask,
641 ENETDMAC_CHANCFG, priv->tx_chan);
642
643 /* stop queue if no more desc available */
644 if (!priv->tx_desc_count)
645 netif_stop_queue(dev);
646
647 dev->stats.tx_bytes += skb->len;
648 dev->stats.tx_packets++;
649 ret = NETDEV_TX_OK;
650
651 out_unlock:
652 spin_unlock(&priv->tx_lock);
653 return ret;
654 }
655
656 /*
657 * Change the interface's mac address.
658 */
659 static int bcm_enet_set_mac_address(struct net_device *dev, void *p)
660 {
661 struct bcm_enet_priv *priv;
662 struct sockaddr *addr = p;
663 u32 val;
664
665 priv = netdev_priv(dev);
666 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
667
668 /* use perfect match register 0 to store my mac address */
669 val = (dev->dev_addr[2] << 24) | (dev->dev_addr[3] << 16) |
670 (dev->dev_addr[4] << 8) | dev->dev_addr[5];
671 enet_writel(priv, val, ENET_PML_REG(0));
672
673 val = (dev->dev_addr[0] << 8 | dev->dev_addr[1]);
674 val |= ENET_PMH_DATAVALID_MASK;
675 enet_writel(priv, val, ENET_PMH_REG(0));
676
677 return 0;
678 }
679
680 /*
681 * Change rx mode (promiscuous/allmulti) and update multicast list
682 */
683 static void bcm_enet_set_multicast_list(struct net_device *dev)
684 {
685 struct bcm_enet_priv *priv;
686 struct netdev_hw_addr *ha;
687 u32 val;
688 int i;
689
690 priv = netdev_priv(dev);
691
692 val = enet_readl(priv, ENET_RXCFG_REG);
693
694 if (dev->flags & IFF_PROMISC)
695 val |= ENET_RXCFG_PROMISC_MASK;
696 else
697 val &= ~ENET_RXCFG_PROMISC_MASK;
698
699 /* only 3 perfect match registers left, first one is used for
700 * own mac address */
701 if ((dev->flags & IFF_ALLMULTI) || netdev_mc_count(dev) > 3)
702 val |= ENET_RXCFG_ALLMCAST_MASK;
703 else
704 val &= ~ENET_RXCFG_ALLMCAST_MASK;
705
706 /* no need to set perfect match registers if we catch all
707 * multicast */
708 if (val & ENET_RXCFG_ALLMCAST_MASK) {
709 enet_writel(priv, val, ENET_RXCFG_REG);
710 return;
711 }
712
713 i = 0;
714 netdev_for_each_mc_addr(ha, dev) {
715 u8 *dmi_addr;
716 u32 tmp;
717
718 if (i == 3)
719 break;
720 /* update perfect match registers */
721 dmi_addr = ha->addr;
722 tmp = (dmi_addr[2] << 24) | (dmi_addr[3] << 16) |
723 (dmi_addr[4] << 8) | dmi_addr[5];
724 enet_writel(priv, tmp, ENET_PML_REG(i + 1));
725
726 tmp = (dmi_addr[0] << 8 | dmi_addr[1]);
727 tmp |= ENET_PMH_DATAVALID_MASK;
728 enet_writel(priv, tmp, ENET_PMH_REG(i++ + 1));
729 }
730
731 for (; i < 3; i++) {
732 enet_writel(priv, 0, ENET_PML_REG(i + 1));
733 enet_writel(priv, 0, ENET_PMH_REG(i + 1));
734 }
735
736 enet_writel(priv, val, ENET_RXCFG_REG);
737 }
738
739 /*
740 * set mac duplex parameters
741 */
742 static void bcm_enet_set_duplex(struct bcm_enet_priv *priv, int fullduplex)
743 {
744 u32 val;
745
746 val = enet_readl(priv, ENET_TXCTL_REG);
747 if (fullduplex)
748 val |= ENET_TXCTL_FD_MASK;
749 else
750 val &= ~ENET_TXCTL_FD_MASK;
751 enet_writel(priv, val, ENET_TXCTL_REG);
752 }
753
754 /*
755 * set mac flow control parameters
756 */
757 static void bcm_enet_set_flow(struct bcm_enet_priv *priv, int rx_en, int tx_en)
758 {
759 u32 val;
760
761 /* rx flow control (pause frame handling) */
762 val = enet_readl(priv, ENET_RXCFG_REG);
763 if (rx_en)
764 val |= ENET_RXCFG_ENFLOW_MASK;
765 else
766 val &= ~ENET_RXCFG_ENFLOW_MASK;
767 enet_writel(priv, val, ENET_RXCFG_REG);
768
769 if (!priv->dma_has_sram)
770 return;
771
772 /* tx flow control (pause frame generation) */
773 val = enet_dma_readl(priv, ENETDMA_CFG_REG);
774 if (tx_en)
775 val |= ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
776 else
777 val &= ~ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
778 enet_dma_writel(priv, val, ENETDMA_CFG_REG);
779 }
780
781 /*
782 * link changed callback (from phylib)
783 */
784 static void bcm_enet_adjust_phy_link(struct net_device *dev)
785 {
786 struct bcm_enet_priv *priv;
787 struct phy_device *phydev;
788 int status_changed;
789
790 priv = netdev_priv(dev);
791 phydev = dev->phydev;
792 status_changed = 0;
793
794 if (priv->old_link != phydev->link) {
795 status_changed = 1;
796 priv->old_link = phydev->link;
797 }
798
799 /* reflect duplex change in mac configuration */
800 if (phydev->link && phydev->duplex != priv->old_duplex) {
801 bcm_enet_set_duplex(priv,
802 (phydev->duplex == DUPLEX_FULL) ? 1 : 0);
803 status_changed = 1;
804 priv->old_duplex = phydev->duplex;
805 }
806
807 /* enable flow control if remote advertise it (trust phylib to
808 * check that duplex is full */
809 if (phydev->link && phydev->pause != priv->old_pause) {
810 int rx_pause_en, tx_pause_en;
811
812 if (phydev->pause) {
813 /* pause was advertised by lpa and us */
814 rx_pause_en = 1;
815 tx_pause_en = 1;
816 } else if (!priv->pause_auto) {
817 /* pause setting overridden by user */
818 rx_pause_en = priv->pause_rx;
819 tx_pause_en = priv->pause_tx;
820 } else {
821 rx_pause_en = 0;
822 tx_pause_en = 0;
823 }
824
825 bcm_enet_set_flow(priv, rx_pause_en, tx_pause_en);
826 status_changed = 1;
827 priv->old_pause = phydev->pause;
828 }
829
830 if (status_changed) {
831 pr_info("%s: link %s", dev->name, phydev->link ?
832 "UP" : "DOWN");
833 if (phydev->link)
834 pr_cont(" - %d/%s - flow control %s", phydev->speed,
835 DUPLEX_FULL == phydev->duplex ? "full" : "half",
836 phydev->pause == 1 ? "rx&tx" : "off");
837
838 pr_cont("\n");
839 }
840 }
841
842 /*
843 * link changed callback (if phylib is not used)
844 */
845 static void bcm_enet_adjust_link(struct net_device *dev)
846 {
847 struct bcm_enet_priv *priv;
848
849 priv = netdev_priv(dev);
850 bcm_enet_set_duplex(priv, priv->force_duplex_full);
851 bcm_enet_set_flow(priv, priv->pause_rx, priv->pause_tx);
852 netif_carrier_on(dev);
853
854 pr_info("%s: link forced UP - %d/%s - flow control %s/%s\n",
855 dev->name,
856 priv->force_speed_100 ? 100 : 10,
857 priv->force_duplex_full ? "full" : "half",
858 priv->pause_rx ? "rx" : "off",
859 priv->pause_tx ? "tx" : "off");
860 }
861
862 /*
863 * open callback, allocate dma rings & buffers and start rx operation
864 */
865 static int bcm_enet_open(struct net_device *dev)
866 {
867 struct bcm_enet_priv *priv;
868 struct sockaddr addr;
869 struct device *kdev;
870 struct phy_device *phydev;
871 int i, ret;
872 unsigned int size;
873 char phy_id[MII_BUS_ID_SIZE + 3];
874 void *p;
875 u32 val;
876
877 priv = netdev_priv(dev);
878 kdev = &priv->pdev->dev;
879
880 if (priv->has_phy) {
881 /* connect to PHY */
882 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
883 priv->mii_bus->id, priv->phy_id);
884
885 phydev = phy_connect(dev, phy_id, bcm_enet_adjust_phy_link,
886 PHY_INTERFACE_MODE_MII);
887
888 if (IS_ERR(phydev)) {
889 dev_err(kdev, "could not attach to PHY\n");
890 return PTR_ERR(phydev);
891 }
892
893 /* mask with MAC supported features */
894 phydev->supported &= (SUPPORTED_10baseT_Half |
895 SUPPORTED_10baseT_Full |
896 SUPPORTED_100baseT_Half |
897 SUPPORTED_100baseT_Full |
898 SUPPORTED_Autoneg |
899 SUPPORTED_Pause |
900 SUPPORTED_MII);
901 phydev->advertising = phydev->supported;
902
903 if (priv->pause_auto && priv->pause_rx && priv->pause_tx)
904 phydev->advertising |= SUPPORTED_Pause;
905 else
906 phydev->advertising &= ~SUPPORTED_Pause;
907
908 phy_attached_info(phydev);
909
910 priv->old_link = 0;
911 priv->old_duplex = -1;
912 priv->old_pause = -1;
913 } else {
914 phydev = NULL;
915 }
916
917 /* mask all interrupts and request them */
918 enet_writel(priv, 0, ENET_IRMASK_REG);
919 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
920 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
921
922 ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev);
923 if (ret)
924 goto out_phy_disconnect;
925
926 ret = request_irq(priv->irq_rx, bcm_enet_isr_dma, 0,
927 dev->name, dev);
928 if (ret)
929 goto out_freeirq;
930
931 ret = request_irq(priv->irq_tx, bcm_enet_isr_dma,
932 0, dev->name, dev);
933 if (ret)
934 goto out_freeirq_rx;
935
936 /* initialize perfect match registers */
937 for (i = 0; i < 4; i++) {
938 enet_writel(priv, 0, ENET_PML_REG(i));
939 enet_writel(priv, 0, ENET_PMH_REG(i));
940 }
941
942 /* write device mac address */
943 memcpy(addr.sa_data, dev->dev_addr, ETH_ALEN);
944 bcm_enet_set_mac_address(dev, &addr);
945
946 /* allocate rx dma ring */
947 size = priv->rx_ring_size * sizeof(struct bcm_enet_desc);
948 p = dma_zalloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
949 if (!p) {
950 ret = -ENOMEM;
951 goto out_freeirq_tx;
952 }
953
954 priv->rx_desc_alloc_size = size;
955 priv->rx_desc_cpu = p;
956
957 /* allocate tx dma ring */
958 size = priv->tx_ring_size * sizeof(struct bcm_enet_desc);
959 p = dma_zalloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
960 if (!p) {
961 ret = -ENOMEM;
962 goto out_free_rx_ring;
963 }
964
965 priv->tx_desc_alloc_size = size;
966 priv->tx_desc_cpu = p;
967
968 priv->tx_skb = kcalloc(priv->tx_ring_size, sizeof(struct sk_buff *),
969 GFP_KERNEL);
970 if (!priv->tx_skb) {
971 ret = -ENOMEM;
972 goto out_free_tx_ring;
973 }
974
975 priv->tx_desc_count = priv->tx_ring_size;
976 priv->tx_dirty_desc = 0;
977 priv->tx_curr_desc = 0;
978 spin_lock_init(&priv->tx_lock);
979
980 /* init & fill rx ring with skbs */
981 priv->rx_skb = kcalloc(priv->rx_ring_size, sizeof(struct sk_buff *),
982 GFP_KERNEL);
983 if (!priv->rx_skb) {
984 ret = -ENOMEM;
985 goto out_free_tx_skb;
986 }
987
988 priv->rx_desc_count = 0;
989 priv->rx_dirty_desc = 0;
990 priv->rx_curr_desc = 0;
991
992 /* initialize flow control buffer allocation */
993 if (priv->dma_has_sram)
994 enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
995 ENETDMA_BUFALLOC_REG(priv->rx_chan));
996 else
997 enet_dmac_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
998 ENETDMAC_BUFALLOC, priv->rx_chan);
999
1000 if (bcm_enet_refill_rx(dev)) {
1001 dev_err(kdev, "cannot allocate rx skb queue\n");
1002 ret = -ENOMEM;
1003 goto out;
1004 }
1005
1006 /* write rx & tx ring addresses */
1007 if (priv->dma_has_sram) {
1008 enet_dmas_writel(priv, priv->rx_desc_dma,
1009 ENETDMAS_RSTART_REG, priv->rx_chan);
1010 enet_dmas_writel(priv, priv->tx_desc_dma,
1011 ENETDMAS_RSTART_REG, priv->tx_chan);
1012 } else {
1013 enet_dmac_writel(priv, priv->rx_desc_dma,
1014 ENETDMAC_RSTART, priv->rx_chan);
1015 enet_dmac_writel(priv, priv->tx_desc_dma,
1016 ENETDMAC_RSTART, priv->tx_chan);
1017 }
1018
1019 /* clear remaining state ram for rx & tx channel */
1020 if (priv->dma_has_sram) {
1021 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
1022 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
1023 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
1024 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
1025 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
1026 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
1027 } else {
1028 enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->rx_chan);
1029 enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->tx_chan);
1030 }
1031
1032 /* set max rx/tx length */
1033 enet_writel(priv, priv->hw_mtu, ENET_RXMAXLEN_REG);
1034 enet_writel(priv, priv->hw_mtu, ENET_TXMAXLEN_REG);
1035
1036 /* set dma maximum burst len */
1037 enet_dmac_writel(priv, priv->dma_maxburst,
1038 ENETDMAC_MAXBURST, priv->rx_chan);
1039 enet_dmac_writel(priv, priv->dma_maxburst,
1040 ENETDMAC_MAXBURST, priv->tx_chan);
1041
1042 /* set correct transmit fifo watermark */
1043 enet_writel(priv, BCMENET_TX_FIFO_TRESH, ENET_TXWMARK_REG);
1044
1045 /* set flow control low/high threshold to 1/3 / 2/3 */
1046 if (priv->dma_has_sram) {
1047 val = priv->rx_ring_size / 3;
1048 enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
1049 val = (priv->rx_ring_size * 2) / 3;
1050 enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
1051 } else {
1052 enet_dmac_writel(priv, 5, ENETDMAC_FC, priv->rx_chan);
1053 enet_dmac_writel(priv, priv->rx_ring_size, ENETDMAC_LEN, priv->rx_chan);
1054 enet_dmac_writel(priv, priv->tx_ring_size, ENETDMAC_LEN, priv->tx_chan);
1055 }
1056
1057 /* all set, enable mac and interrupts, start dma engine and
1058 * kick rx dma channel */
1059 wmb();
1060 val = enet_readl(priv, ENET_CTL_REG);
1061 val |= ENET_CTL_ENABLE_MASK;
1062 enet_writel(priv, val, ENET_CTL_REG);
1063 if (priv->dma_has_sram)
1064 enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
1065 enet_dmac_writel(priv, priv->dma_chan_en_mask,
1066 ENETDMAC_CHANCFG, priv->rx_chan);
1067
1068 /* watch "mib counters about to overflow" interrupt */
1069 enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
1070 enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
1071
1072 /* watch "packet transferred" interrupt in rx and tx */
1073 enet_dmac_writel(priv, priv->dma_chan_int_mask,
1074 ENETDMAC_IR, priv->rx_chan);
1075 enet_dmac_writel(priv, priv->dma_chan_int_mask,
1076 ENETDMAC_IR, priv->tx_chan);
1077
1078 /* make sure we enable napi before rx interrupt */
1079 napi_enable(&priv->napi);
1080
1081 enet_dmac_writel(priv, priv->dma_chan_int_mask,
1082 ENETDMAC_IRMASK, priv->rx_chan);
1083 enet_dmac_writel(priv, priv->dma_chan_int_mask,
1084 ENETDMAC_IRMASK, priv->tx_chan);
1085
1086 if (phydev)
1087 phy_start(phydev);
1088 else
1089 bcm_enet_adjust_link(dev);
1090
1091 netif_start_queue(dev);
1092 return 0;
1093
1094 out:
1095 for (i = 0; i < priv->rx_ring_size; i++) {
1096 struct bcm_enet_desc *desc;
1097
1098 if (!priv->rx_skb[i])
1099 continue;
1100
1101 desc = &priv->rx_desc_cpu[i];
1102 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
1103 DMA_FROM_DEVICE);
1104 kfree_skb(priv->rx_skb[i]);
1105 }
1106 kfree(priv->rx_skb);
1107
1108 out_free_tx_skb:
1109 kfree(priv->tx_skb);
1110
1111 out_free_tx_ring:
1112 dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1113 priv->tx_desc_cpu, priv->tx_desc_dma);
1114
1115 out_free_rx_ring:
1116 dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1117 priv->rx_desc_cpu, priv->rx_desc_dma);
1118
1119 out_freeirq_tx:
1120 free_irq(priv->irq_tx, dev);
1121
1122 out_freeirq_rx:
1123 free_irq(priv->irq_rx, dev);
1124
1125 out_freeirq:
1126 free_irq(dev->irq, dev);
1127
1128 out_phy_disconnect:
1129 if (phydev)
1130 phy_disconnect(phydev);
1131
1132 return ret;
1133 }
1134
1135 /*
1136 * disable mac
1137 */
1138 static void bcm_enet_disable_mac(struct bcm_enet_priv *priv)
1139 {
1140 int limit;
1141 u32 val;
1142
1143 val = enet_readl(priv, ENET_CTL_REG);
1144 val |= ENET_CTL_DISABLE_MASK;
1145 enet_writel(priv, val, ENET_CTL_REG);
1146
1147 limit = 1000;
1148 do {
1149 u32 val;
1150
1151 val = enet_readl(priv, ENET_CTL_REG);
1152 if (!(val & ENET_CTL_DISABLE_MASK))
1153 break;
1154 udelay(1);
1155 } while (limit--);
1156 }
1157
1158 /*
1159 * disable dma in given channel
1160 */
1161 static void bcm_enet_disable_dma(struct bcm_enet_priv *priv, int chan)
1162 {
1163 int limit;
1164
1165 enet_dmac_writel(priv, 0, ENETDMAC_CHANCFG, chan);
1166
1167 limit = 1000;
1168 do {
1169 u32 val;
1170
1171 val = enet_dmac_readl(priv, ENETDMAC_CHANCFG, chan);
1172 if (!(val & ENETDMAC_CHANCFG_EN_MASK))
1173 break;
1174 udelay(1);
1175 } while (limit--);
1176 }
1177
1178 /*
1179 * stop callback
1180 */
1181 static int bcm_enet_stop(struct net_device *dev)
1182 {
1183 struct bcm_enet_priv *priv;
1184 struct device *kdev;
1185 int i;
1186
1187 priv = netdev_priv(dev);
1188 kdev = &priv->pdev->dev;
1189
1190 netif_stop_queue(dev);
1191 napi_disable(&priv->napi);
1192 if (priv->has_phy)
1193 phy_stop(dev->phydev);
1194 del_timer_sync(&priv->rx_timeout);
1195
1196 /* mask all interrupts */
1197 enet_writel(priv, 0, ENET_IRMASK_REG);
1198 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
1199 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
1200
1201 /* make sure no mib update is scheduled */
1202 cancel_work_sync(&priv->mib_update_task);
1203
1204 /* disable dma & mac */
1205 bcm_enet_disable_dma(priv, priv->tx_chan);
1206 bcm_enet_disable_dma(priv, priv->rx_chan);
1207 bcm_enet_disable_mac(priv);
1208
1209 /* force reclaim of all tx buffers */
1210 bcm_enet_tx_reclaim(dev, 1);
1211
1212 /* free the rx skb ring */
1213 for (i = 0; i < priv->rx_ring_size; i++) {
1214 struct bcm_enet_desc *desc;
1215
1216 if (!priv->rx_skb[i])
1217 continue;
1218
1219 desc = &priv->rx_desc_cpu[i];
1220 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
1221 DMA_FROM_DEVICE);
1222 kfree_skb(priv->rx_skb[i]);
1223 }
1224
1225 /* free remaining allocated memory */
1226 kfree(priv->rx_skb);
1227 kfree(priv->tx_skb);
1228 dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1229 priv->rx_desc_cpu, priv->rx_desc_dma);
1230 dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1231 priv->tx_desc_cpu, priv->tx_desc_dma);
1232 free_irq(priv->irq_tx, dev);
1233 free_irq(priv->irq_rx, dev);
1234 free_irq(dev->irq, dev);
1235
1236 /* release phy */
1237 if (priv->has_phy)
1238 phy_disconnect(dev->phydev);
1239
1240 return 0;
1241 }
1242
1243 /*
1244 * ethtool callbacks
1245 */
1246 struct bcm_enet_stats {
1247 char stat_string[ETH_GSTRING_LEN];
1248 int sizeof_stat;
1249 int stat_offset;
1250 int mib_reg;
1251 };
1252
1253 #define GEN_STAT(m) sizeof(((struct bcm_enet_priv *)0)->m), \
1254 offsetof(struct bcm_enet_priv, m)
1255 #define DEV_STAT(m) sizeof(((struct net_device_stats *)0)->m), \
1256 offsetof(struct net_device_stats, m)
1257
1258 static const struct bcm_enet_stats bcm_enet_gstrings_stats[] = {
1259 { "rx_packets", DEV_STAT(rx_packets), -1 },
1260 { "tx_packets", DEV_STAT(tx_packets), -1 },
1261 { "rx_bytes", DEV_STAT(rx_bytes), -1 },
1262 { "tx_bytes", DEV_STAT(tx_bytes), -1 },
1263 { "rx_errors", DEV_STAT(rx_errors), -1 },
1264 { "tx_errors", DEV_STAT(tx_errors), -1 },
1265 { "rx_dropped", DEV_STAT(rx_dropped), -1 },
1266 { "tx_dropped", DEV_STAT(tx_dropped), -1 },
1267
1268 { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETH_MIB_RX_GD_OCTETS},
1269 { "rx_good_pkts", GEN_STAT(mib.rx_gd_pkts), ETH_MIB_RX_GD_PKTS },
1270 { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETH_MIB_RX_BRDCAST },
1271 { "rx_multicast", GEN_STAT(mib.rx_mult), ETH_MIB_RX_MULT },
1272 { "rx_64_octets", GEN_STAT(mib.rx_64), ETH_MIB_RX_64 },
1273 { "rx_65_127_oct", GEN_STAT(mib.rx_65_127), ETH_MIB_RX_65_127 },
1274 { "rx_128_255_oct", GEN_STAT(mib.rx_128_255), ETH_MIB_RX_128_255 },
1275 { "rx_256_511_oct", GEN_STAT(mib.rx_256_511), ETH_MIB_RX_256_511 },
1276 { "rx_512_1023_oct", GEN_STAT(mib.rx_512_1023), ETH_MIB_RX_512_1023 },
1277 { "rx_1024_max_oct", GEN_STAT(mib.rx_1024_max), ETH_MIB_RX_1024_MAX },
1278 { "rx_jabber", GEN_STAT(mib.rx_jab), ETH_MIB_RX_JAB },
1279 { "rx_oversize", GEN_STAT(mib.rx_ovr), ETH_MIB_RX_OVR },
1280 { "rx_fragment", GEN_STAT(mib.rx_frag), ETH_MIB_RX_FRAG },
1281 { "rx_dropped", GEN_STAT(mib.rx_drop), ETH_MIB_RX_DROP },
1282 { "rx_crc_align", GEN_STAT(mib.rx_crc_align), ETH_MIB_RX_CRC_ALIGN },
1283 { "rx_undersize", GEN_STAT(mib.rx_und), ETH_MIB_RX_UND },
1284 { "rx_crc", GEN_STAT(mib.rx_crc), ETH_MIB_RX_CRC },
1285 { "rx_align", GEN_STAT(mib.rx_align), ETH_MIB_RX_ALIGN },
1286 { "rx_symbol_error", GEN_STAT(mib.rx_sym), ETH_MIB_RX_SYM },
1287 { "rx_pause", GEN_STAT(mib.rx_pause), ETH_MIB_RX_PAUSE },
1288 { "rx_control", GEN_STAT(mib.rx_cntrl), ETH_MIB_RX_CNTRL },
1289
1290 { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETH_MIB_TX_GD_OCTETS },
1291 { "tx_good_pkts", GEN_STAT(mib.tx_gd_pkts), ETH_MIB_TX_GD_PKTS },
1292 { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETH_MIB_TX_BRDCAST },
1293 { "tx_multicast", GEN_STAT(mib.tx_mult), ETH_MIB_TX_MULT },
1294 { "tx_64_oct", GEN_STAT(mib.tx_64), ETH_MIB_TX_64 },
1295 { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETH_MIB_TX_65_127 },
1296 { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETH_MIB_TX_128_255 },
1297 { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETH_MIB_TX_256_511 },
1298 { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETH_MIB_TX_512_1023},
1299 { "tx_1024_max_oct", GEN_STAT(mib.tx_1024_max), ETH_MIB_TX_1024_MAX },
1300 { "tx_jabber", GEN_STAT(mib.tx_jab), ETH_MIB_TX_JAB },
1301 { "tx_oversize", GEN_STAT(mib.tx_ovr), ETH_MIB_TX_OVR },
1302 { "tx_fragment", GEN_STAT(mib.tx_frag), ETH_MIB_TX_FRAG },
1303 { "tx_underrun", GEN_STAT(mib.tx_underrun), ETH_MIB_TX_UNDERRUN },
1304 { "tx_collisions", GEN_STAT(mib.tx_col), ETH_MIB_TX_COL },
1305 { "tx_single_collision", GEN_STAT(mib.tx_1_col), ETH_MIB_TX_1_COL },
1306 { "tx_multiple_collision", GEN_STAT(mib.tx_m_col), ETH_MIB_TX_M_COL },
1307 { "tx_excess_collision", GEN_STAT(mib.tx_ex_col), ETH_MIB_TX_EX_COL },
1308 { "tx_late_collision", GEN_STAT(mib.tx_late), ETH_MIB_TX_LATE },
1309 { "tx_deferred", GEN_STAT(mib.tx_def), ETH_MIB_TX_DEF },
1310 { "tx_carrier_sense", GEN_STAT(mib.tx_crs), ETH_MIB_TX_CRS },
1311 { "tx_pause", GEN_STAT(mib.tx_pause), ETH_MIB_TX_PAUSE },
1312
1313 };
1314
1315 #define BCM_ENET_STATS_LEN ARRAY_SIZE(bcm_enet_gstrings_stats)
1316
1317 static const u32 unused_mib_regs[] = {
1318 ETH_MIB_TX_ALL_OCTETS,
1319 ETH_MIB_TX_ALL_PKTS,
1320 ETH_MIB_RX_ALL_OCTETS,
1321 ETH_MIB_RX_ALL_PKTS,
1322 };
1323
1324
1325 static void bcm_enet_get_drvinfo(struct net_device *netdev,
1326 struct ethtool_drvinfo *drvinfo)
1327 {
1328 strlcpy(drvinfo->driver, bcm_enet_driver_name, sizeof(drvinfo->driver));
1329 strlcpy(drvinfo->version, bcm_enet_driver_version,
1330 sizeof(drvinfo->version));
1331 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
1332 strlcpy(drvinfo->bus_info, "bcm63xx", sizeof(drvinfo->bus_info));
1333 }
1334
1335 static int bcm_enet_get_sset_count(struct net_device *netdev,
1336 int string_set)
1337 {
1338 switch (string_set) {
1339 case ETH_SS_STATS:
1340 return BCM_ENET_STATS_LEN;
1341 default:
1342 return -EINVAL;
1343 }
1344 }
1345
1346 static void bcm_enet_get_strings(struct net_device *netdev,
1347 u32 stringset, u8 *data)
1348 {
1349 int i;
1350
1351 switch (stringset) {
1352 case ETH_SS_STATS:
1353 for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1354 memcpy(data + i * ETH_GSTRING_LEN,
1355 bcm_enet_gstrings_stats[i].stat_string,
1356 ETH_GSTRING_LEN);
1357 }
1358 break;
1359 }
1360 }
1361
1362 static void update_mib_counters(struct bcm_enet_priv *priv)
1363 {
1364 int i;
1365
1366 for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1367 const struct bcm_enet_stats *s;
1368 u32 val;
1369 char *p;
1370
1371 s = &bcm_enet_gstrings_stats[i];
1372 if (s->mib_reg == -1)
1373 continue;
1374
1375 val = enet_readl(priv, ENET_MIB_REG(s->mib_reg));
1376 p = (char *)priv + s->stat_offset;
1377
1378 if (s->sizeof_stat == sizeof(u64))
1379 *(u64 *)p += val;
1380 else
1381 *(u32 *)p += val;
1382 }
1383
1384 /* also empty unused mib counters to make sure mib counter
1385 * overflow interrupt is cleared */
1386 for (i = 0; i < ARRAY_SIZE(unused_mib_regs); i++)
1387 (void)enet_readl(priv, ENET_MIB_REG(unused_mib_regs[i]));
1388 }
1389
1390 static void bcm_enet_update_mib_counters_defer(struct work_struct *t)
1391 {
1392 struct bcm_enet_priv *priv;
1393
1394 priv = container_of(t, struct bcm_enet_priv, mib_update_task);
1395 mutex_lock(&priv->mib_update_lock);
1396 update_mib_counters(priv);
1397 mutex_unlock(&priv->mib_update_lock);
1398
1399 /* reenable mib interrupt */
1400 if (netif_running(priv->net_dev))
1401 enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
1402 }
1403
1404 static void bcm_enet_get_ethtool_stats(struct net_device *netdev,
1405 struct ethtool_stats *stats,
1406 u64 *data)
1407 {
1408 struct bcm_enet_priv *priv;
1409 int i;
1410
1411 priv = netdev_priv(netdev);
1412
1413 mutex_lock(&priv->mib_update_lock);
1414 update_mib_counters(priv);
1415
1416 for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1417 const struct bcm_enet_stats *s;
1418 char *p;
1419
1420 s = &bcm_enet_gstrings_stats[i];
1421 if (s->mib_reg == -1)
1422 p = (char *)&netdev->stats;
1423 else
1424 p = (char *)priv;
1425 p += s->stat_offset;
1426 data[i] = (s->sizeof_stat == sizeof(u64)) ?
1427 *(u64 *)p : *(u32 *)p;
1428 }
1429 mutex_unlock(&priv->mib_update_lock);
1430 }
1431
1432 static int bcm_enet_nway_reset(struct net_device *dev)
1433 {
1434 struct bcm_enet_priv *priv;
1435
1436 priv = netdev_priv(dev);
1437 if (priv->has_phy)
1438 return phy_ethtool_nway_reset(dev);
1439
1440 return -EOPNOTSUPP;
1441 }
1442
1443 static int bcm_enet_get_link_ksettings(struct net_device *dev,
1444 struct ethtool_link_ksettings *cmd)
1445 {
1446 struct bcm_enet_priv *priv;
1447 u32 supported, advertising;
1448
1449 priv = netdev_priv(dev);
1450
1451 if (priv->has_phy) {
1452 if (!dev->phydev)
1453 return -ENODEV;
1454
1455 phy_ethtool_ksettings_get(dev->phydev, cmd);
1456
1457 return 0;
1458 } else {
1459 cmd->base.autoneg = 0;
1460 cmd->base.speed = (priv->force_speed_100) ?
1461 SPEED_100 : SPEED_10;
1462 cmd->base.duplex = (priv->force_duplex_full) ?
1463 DUPLEX_FULL : DUPLEX_HALF;
1464 supported = ADVERTISED_10baseT_Half |
1465 ADVERTISED_10baseT_Full |
1466 ADVERTISED_100baseT_Half |
1467 ADVERTISED_100baseT_Full;
1468 advertising = 0;
1469 ethtool_convert_legacy_u32_to_link_mode(
1470 cmd->link_modes.supported, supported);
1471 ethtool_convert_legacy_u32_to_link_mode(
1472 cmd->link_modes.advertising, advertising);
1473 cmd->base.port = PORT_MII;
1474 }
1475 return 0;
1476 }
1477
1478 static int bcm_enet_set_link_ksettings(struct net_device *dev,
1479 const struct ethtool_link_ksettings *cmd)
1480 {
1481 struct bcm_enet_priv *priv;
1482
1483 priv = netdev_priv(dev);
1484 if (priv->has_phy) {
1485 if (!dev->phydev)
1486 return -ENODEV;
1487 return phy_ethtool_ksettings_set(dev->phydev, cmd);
1488 } else {
1489
1490 if (cmd->base.autoneg ||
1491 (cmd->base.speed != SPEED_100 &&
1492 cmd->base.speed != SPEED_10) ||
1493 cmd->base.port != PORT_MII)
1494 return -EINVAL;
1495
1496 priv->force_speed_100 =
1497 (cmd->base.speed == SPEED_100) ? 1 : 0;
1498 priv->force_duplex_full =
1499 (cmd->base.duplex == DUPLEX_FULL) ? 1 : 0;
1500
1501 if (netif_running(dev))
1502 bcm_enet_adjust_link(dev);
1503 return 0;
1504 }
1505 }
1506
1507 static void bcm_enet_get_ringparam(struct net_device *dev,
1508 struct ethtool_ringparam *ering)
1509 {
1510 struct bcm_enet_priv *priv;
1511
1512 priv = netdev_priv(dev);
1513
1514 /* rx/tx ring is actually only limited by memory */
1515 ering->rx_max_pending = 8192;
1516 ering->tx_max_pending = 8192;
1517 ering->rx_pending = priv->rx_ring_size;
1518 ering->tx_pending = priv->tx_ring_size;
1519 }
1520
1521 static int bcm_enet_set_ringparam(struct net_device *dev,
1522 struct ethtool_ringparam *ering)
1523 {
1524 struct bcm_enet_priv *priv;
1525 int was_running;
1526
1527 priv = netdev_priv(dev);
1528
1529 was_running = 0;
1530 if (netif_running(dev)) {
1531 bcm_enet_stop(dev);
1532 was_running = 1;
1533 }
1534
1535 priv->rx_ring_size = ering->rx_pending;
1536 priv->tx_ring_size = ering->tx_pending;
1537
1538 if (was_running) {
1539 int err;
1540
1541 err = bcm_enet_open(dev);
1542 if (err)
1543 dev_close(dev);
1544 else
1545 bcm_enet_set_multicast_list(dev);
1546 }
1547 return 0;
1548 }
1549
1550 static void bcm_enet_get_pauseparam(struct net_device *dev,
1551 struct ethtool_pauseparam *ecmd)
1552 {
1553 struct bcm_enet_priv *priv;
1554
1555 priv = netdev_priv(dev);
1556 ecmd->autoneg = priv->pause_auto;
1557 ecmd->rx_pause = priv->pause_rx;
1558 ecmd->tx_pause = priv->pause_tx;
1559 }
1560
1561 static int bcm_enet_set_pauseparam(struct net_device *dev,
1562 struct ethtool_pauseparam *ecmd)
1563 {
1564 struct bcm_enet_priv *priv;
1565
1566 priv = netdev_priv(dev);
1567
1568 if (priv->has_phy) {
1569 if (ecmd->autoneg && (ecmd->rx_pause != ecmd->tx_pause)) {
1570 /* asymetric pause mode not supported,
1571 * actually possible but integrated PHY has RO
1572 * asym_pause bit */
1573 return -EINVAL;
1574 }
1575 } else {
1576 /* no pause autoneg on direct mii connection */
1577 if (ecmd->autoneg)
1578 return -EINVAL;
1579 }
1580
1581 priv->pause_auto = ecmd->autoneg;
1582 priv->pause_rx = ecmd->rx_pause;
1583 priv->pause_tx = ecmd->tx_pause;
1584
1585 return 0;
1586 }
1587
1588 static const struct ethtool_ops bcm_enet_ethtool_ops = {
1589 .get_strings = bcm_enet_get_strings,
1590 .get_sset_count = bcm_enet_get_sset_count,
1591 .get_ethtool_stats = bcm_enet_get_ethtool_stats,
1592 .nway_reset = bcm_enet_nway_reset,
1593 .get_drvinfo = bcm_enet_get_drvinfo,
1594 .get_link = ethtool_op_get_link,
1595 .get_ringparam = bcm_enet_get_ringparam,
1596 .set_ringparam = bcm_enet_set_ringparam,
1597 .get_pauseparam = bcm_enet_get_pauseparam,
1598 .set_pauseparam = bcm_enet_set_pauseparam,
1599 .get_link_ksettings = bcm_enet_get_link_ksettings,
1600 .set_link_ksettings = bcm_enet_set_link_ksettings,
1601 };
1602
1603 static int bcm_enet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1604 {
1605 struct bcm_enet_priv *priv;
1606
1607 priv = netdev_priv(dev);
1608 if (priv->has_phy) {
1609 if (!dev->phydev)
1610 return -ENODEV;
1611 return phy_mii_ioctl(dev->phydev, rq, cmd);
1612 } else {
1613 struct mii_if_info mii;
1614
1615 mii.dev = dev;
1616 mii.mdio_read = bcm_enet_mdio_read_mii;
1617 mii.mdio_write = bcm_enet_mdio_write_mii;
1618 mii.phy_id = 0;
1619 mii.phy_id_mask = 0x3f;
1620 mii.reg_num_mask = 0x1f;
1621 return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL);
1622 }
1623 }
1624
1625 /*
1626 * adjust mtu, can't be called while device is running
1627 */
1628 static int bcm_enet_change_mtu(struct net_device *dev, int new_mtu)
1629 {
1630 struct bcm_enet_priv *priv = netdev_priv(dev);
1631 int actual_mtu = new_mtu;
1632
1633 if (netif_running(dev))
1634 return -EBUSY;
1635
1636 /* add ethernet header + vlan tag size */
1637 actual_mtu += VLAN_ETH_HLEN;
1638
1639 /*
1640 * setup maximum size before we get overflow mark in
1641 * descriptor, note that this will not prevent reception of
1642 * big frames, they will be split into multiple buffers
1643 * anyway
1644 */
1645 priv->hw_mtu = actual_mtu;
1646
1647 /*
1648 * align rx buffer size to dma burst len, account FCS since
1649 * it's appended
1650 */
1651 priv->rx_skb_size = ALIGN(actual_mtu + ETH_FCS_LEN,
1652 priv->dma_maxburst * 4);
1653
1654 dev->mtu = new_mtu;
1655 return 0;
1656 }
1657
1658 /*
1659 * preinit hardware to allow mii operation while device is down
1660 */
1661 static void bcm_enet_hw_preinit(struct bcm_enet_priv *priv)
1662 {
1663 u32 val;
1664 int limit;
1665
1666 /* make sure mac is disabled */
1667 bcm_enet_disable_mac(priv);
1668
1669 /* soft reset mac */
1670 val = ENET_CTL_SRESET_MASK;
1671 enet_writel(priv, val, ENET_CTL_REG);
1672 wmb();
1673
1674 limit = 1000;
1675 do {
1676 val = enet_readl(priv, ENET_CTL_REG);
1677 if (!(val & ENET_CTL_SRESET_MASK))
1678 break;
1679 udelay(1);
1680 } while (limit--);
1681
1682 /* select correct mii interface */
1683 val = enet_readl(priv, ENET_CTL_REG);
1684 if (priv->use_external_mii)
1685 val |= ENET_CTL_EPHYSEL_MASK;
1686 else
1687 val &= ~ENET_CTL_EPHYSEL_MASK;
1688 enet_writel(priv, val, ENET_CTL_REG);
1689
1690 /* turn on mdc clock */
1691 enet_writel(priv, (0x1f << ENET_MIISC_MDCFREQDIV_SHIFT) |
1692 ENET_MIISC_PREAMBLEEN_MASK, ENET_MIISC_REG);
1693
1694 /* set mib counters to self-clear when read */
1695 val = enet_readl(priv, ENET_MIBCTL_REG);
1696 val |= ENET_MIBCTL_RDCLEAR_MASK;
1697 enet_writel(priv, val, ENET_MIBCTL_REG);
1698 }
1699
1700 static const struct net_device_ops bcm_enet_ops = {
1701 .ndo_open = bcm_enet_open,
1702 .ndo_stop = bcm_enet_stop,
1703 .ndo_start_xmit = bcm_enet_start_xmit,
1704 .ndo_set_mac_address = bcm_enet_set_mac_address,
1705 .ndo_set_rx_mode = bcm_enet_set_multicast_list,
1706 .ndo_do_ioctl = bcm_enet_ioctl,
1707 .ndo_change_mtu = bcm_enet_change_mtu,
1708 };
1709
1710 /*
1711 * allocate netdevice, request register memory and register device.
1712 */
1713 static int bcm_enet_probe(struct platform_device *pdev)
1714 {
1715 struct bcm_enet_priv *priv;
1716 struct net_device *dev;
1717 struct bcm63xx_enet_platform_data *pd;
1718 struct resource *res_mem, *res_irq, *res_irq_rx, *res_irq_tx;
1719 struct mii_bus *bus;
1720 const char *clk_name;
1721 int i, ret;
1722
1723 if (!bcm_enet_shared_base[0])
1724 return -EPROBE_DEFER;
1725
1726 res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1727 res_irq_rx = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
1728 res_irq_tx = platform_get_resource(pdev, IORESOURCE_IRQ, 2);
1729 if (!res_irq || !res_irq_rx || !res_irq_tx)
1730 return -ENODEV;
1731
1732 ret = 0;
1733 dev = alloc_etherdev(sizeof(*priv));
1734 if (!dev)
1735 return -ENOMEM;
1736 priv = netdev_priv(dev);
1737
1738 priv->enet_is_sw = false;
1739 priv->dma_maxburst = BCMENET_DMA_MAXBURST;
1740
1741 ret = bcm_enet_change_mtu(dev, dev->mtu);
1742 if (ret)
1743 goto out;
1744
1745 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1746 priv->base = devm_ioremap_resource(&pdev->dev, res_mem);
1747 if (IS_ERR(priv->base)) {
1748 ret = PTR_ERR(priv->base);
1749 goto out;
1750 }
1751
1752 dev->irq = priv->irq = res_irq->start;
1753 priv->irq_rx = res_irq_rx->start;
1754 priv->irq_tx = res_irq_tx->start;
1755 priv->mac_id = pdev->id;
1756
1757 /* get rx & tx dma channel id for this mac */
1758 if (priv->mac_id == 0) {
1759 priv->rx_chan = 0;
1760 priv->tx_chan = 1;
1761 clk_name = "enet0";
1762 } else {
1763 priv->rx_chan = 2;
1764 priv->tx_chan = 3;
1765 clk_name = "enet1";
1766 }
1767
1768 priv->mac_clk = devm_clk_get(&pdev->dev, clk_name);
1769 if (IS_ERR(priv->mac_clk)) {
1770 ret = PTR_ERR(priv->mac_clk);
1771 goto out;
1772 }
1773 ret = clk_prepare_enable(priv->mac_clk);
1774 if (ret)
1775 goto out;
1776
1777 /* initialize default and fetch platform data */
1778 priv->rx_ring_size = BCMENET_DEF_RX_DESC;
1779 priv->tx_ring_size = BCMENET_DEF_TX_DESC;
1780
1781 pd = dev_get_platdata(&pdev->dev);
1782 if (pd) {
1783 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
1784 priv->has_phy = pd->has_phy;
1785 priv->phy_id = pd->phy_id;
1786 priv->has_phy_interrupt = pd->has_phy_interrupt;
1787 priv->phy_interrupt = pd->phy_interrupt;
1788 priv->use_external_mii = !pd->use_internal_phy;
1789 priv->pause_auto = pd->pause_auto;
1790 priv->pause_rx = pd->pause_rx;
1791 priv->pause_tx = pd->pause_tx;
1792 priv->force_duplex_full = pd->force_duplex_full;
1793 priv->force_speed_100 = pd->force_speed_100;
1794 priv->dma_chan_en_mask = pd->dma_chan_en_mask;
1795 priv->dma_chan_int_mask = pd->dma_chan_int_mask;
1796 priv->dma_chan_width = pd->dma_chan_width;
1797 priv->dma_has_sram = pd->dma_has_sram;
1798 priv->dma_desc_shift = pd->dma_desc_shift;
1799 }
1800
1801 if (priv->mac_id == 0 && priv->has_phy && !priv->use_external_mii) {
1802 /* using internal PHY, enable clock */
1803 priv->phy_clk = devm_clk_get(&pdev->dev, "ephy");
1804 if (IS_ERR(priv->phy_clk)) {
1805 ret = PTR_ERR(priv->phy_clk);
1806 priv->phy_clk = NULL;
1807 goto out_disable_clk_mac;
1808 }
1809 ret = clk_prepare_enable(priv->phy_clk);
1810 if (ret)
1811 goto out_disable_clk_mac;
1812 }
1813
1814 /* do minimal hardware init to be able to probe mii bus */
1815 bcm_enet_hw_preinit(priv);
1816
1817 /* MII bus registration */
1818 if (priv->has_phy) {
1819
1820 priv->mii_bus = mdiobus_alloc();
1821 if (!priv->mii_bus) {
1822 ret = -ENOMEM;
1823 goto out_uninit_hw;
1824 }
1825
1826 bus = priv->mii_bus;
1827 bus->name = "bcm63xx_enet MII bus";
1828 bus->parent = &pdev->dev;
1829 bus->priv = priv;
1830 bus->read = bcm_enet_mdio_read_phylib;
1831 bus->write = bcm_enet_mdio_write_phylib;
1832 sprintf(bus->id, "%s-%d", pdev->name, priv->mac_id);
1833
1834 /* only probe bus where we think the PHY is, because
1835 * the mdio read operation return 0 instead of 0xffff
1836 * if a slave is not present on hw */
1837 bus->phy_mask = ~(1 << priv->phy_id);
1838
1839 if (priv->has_phy_interrupt)
1840 bus->irq[priv->phy_id] = priv->phy_interrupt;
1841
1842 ret = mdiobus_register(bus);
1843 if (ret) {
1844 dev_err(&pdev->dev, "unable to register mdio bus\n");
1845 goto out_free_mdio;
1846 }
1847 } else {
1848
1849 /* run platform code to initialize PHY device */
1850 if (pd && pd->mii_config &&
1851 pd->mii_config(dev, 1, bcm_enet_mdio_read_mii,
1852 bcm_enet_mdio_write_mii)) {
1853 dev_err(&pdev->dev, "unable to configure mdio bus\n");
1854 goto out_uninit_hw;
1855 }
1856 }
1857
1858 spin_lock_init(&priv->rx_lock);
1859
1860 /* init rx timeout (used for oom) */
1861 timer_setup(&priv->rx_timeout, bcm_enet_refill_rx_timer, 0);
1862
1863 /* init the mib update lock&work */
1864 mutex_init(&priv->mib_update_lock);
1865 INIT_WORK(&priv->mib_update_task, bcm_enet_update_mib_counters_defer);
1866
1867 /* zero mib counters */
1868 for (i = 0; i < ENET_MIB_REG_COUNT; i++)
1869 enet_writel(priv, 0, ENET_MIB_REG(i));
1870
1871 /* register netdevice */
1872 dev->netdev_ops = &bcm_enet_ops;
1873 netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);
1874
1875 dev->ethtool_ops = &bcm_enet_ethtool_ops;
1876 /* MTU range: 46 - 2028 */
1877 dev->min_mtu = ETH_ZLEN - ETH_HLEN;
1878 dev->max_mtu = BCMENET_MAX_MTU - VLAN_ETH_HLEN;
1879 SET_NETDEV_DEV(dev, &pdev->dev);
1880
1881 ret = register_netdev(dev);
1882 if (ret)
1883 goto out_unregister_mdio;
1884
1885 netif_carrier_off(dev);
1886 platform_set_drvdata(pdev, dev);
1887 priv->pdev = pdev;
1888 priv->net_dev = dev;
1889
1890 return 0;
1891
1892 out_unregister_mdio:
1893 if (priv->mii_bus)
1894 mdiobus_unregister(priv->mii_bus);
1895
1896 out_free_mdio:
1897 if (priv->mii_bus)
1898 mdiobus_free(priv->mii_bus);
1899
1900 out_uninit_hw:
1901 /* turn off mdc clock */
1902 enet_writel(priv, 0, ENET_MIISC_REG);
1903 clk_disable_unprepare(priv->phy_clk);
1904
1905 out_disable_clk_mac:
1906 clk_disable_unprepare(priv->mac_clk);
1907 out:
1908 free_netdev(dev);
1909 return ret;
1910 }
1911
1912
1913 /*
1914 * exit func, stops hardware and unregisters netdevice
1915 */
1916 static int bcm_enet_remove(struct platform_device *pdev)
1917 {
1918 struct bcm_enet_priv *priv;
1919 struct net_device *dev;
1920
1921 /* stop netdevice */
1922 dev = platform_get_drvdata(pdev);
1923 priv = netdev_priv(dev);
1924 unregister_netdev(dev);
1925
1926 /* turn off mdc clock */
1927 enet_writel(priv, 0, ENET_MIISC_REG);
1928
1929 if (priv->has_phy) {
1930 mdiobus_unregister(priv->mii_bus);
1931 mdiobus_free(priv->mii_bus);
1932 } else {
1933 struct bcm63xx_enet_platform_data *pd;
1934
1935 pd = dev_get_platdata(&pdev->dev);
1936 if (pd && pd->mii_config)
1937 pd->mii_config(dev, 0, bcm_enet_mdio_read_mii,
1938 bcm_enet_mdio_write_mii);
1939 }
1940
1941 /* disable hw block clocks */
1942 clk_disable_unprepare(priv->phy_clk);
1943 clk_disable_unprepare(priv->mac_clk);
1944
1945 free_netdev(dev);
1946 return 0;
1947 }
1948
1949 struct platform_driver bcm63xx_enet_driver = {
1950 .probe = bcm_enet_probe,
1951 .remove = bcm_enet_remove,
1952 .driver = {
1953 .name = "bcm63xx_enet",
1954 .owner = THIS_MODULE,
1955 },
1956 };
1957
1958 /*
1959 * switch mii access callbacks
1960 */
1961 static int bcmenet_sw_mdio_read(struct bcm_enet_priv *priv,
1962 int ext, int phy_id, int location)
1963 {
1964 u32 reg;
1965 int ret;
1966
1967 spin_lock_bh(&priv->enetsw_mdio_lock);
1968 enetsw_writel(priv, 0, ENETSW_MDIOC_REG);
1969
1970 reg = ENETSW_MDIOC_RD_MASK |
1971 (phy_id << ENETSW_MDIOC_PHYID_SHIFT) |
1972 (location << ENETSW_MDIOC_REG_SHIFT);
1973
1974 if (ext)
1975 reg |= ENETSW_MDIOC_EXT_MASK;
1976
1977 enetsw_writel(priv, reg, ENETSW_MDIOC_REG);
1978 udelay(50);
1979 ret = enetsw_readw(priv, ENETSW_MDIOD_REG);
1980 spin_unlock_bh(&priv->enetsw_mdio_lock);
1981 return ret;
1982 }
1983
1984 static void bcmenet_sw_mdio_write(struct bcm_enet_priv *priv,
1985 int ext, int phy_id, int location,
1986 uint16_t data)
1987 {
1988 u32 reg;
1989
1990 spin_lock_bh(&priv->enetsw_mdio_lock);
1991 enetsw_writel(priv, 0, ENETSW_MDIOC_REG);
1992
1993 reg = ENETSW_MDIOC_WR_MASK |
1994 (phy_id << ENETSW_MDIOC_PHYID_SHIFT) |
1995 (location << ENETSW_MDIOC_REG_SHIFT);
1996
1997 if (ext)
1998 reg |= ENETSW_MDIOC_EXT_MASK;
1999
2000 reg |= data;
2001
2002 enetsw_writel(priv, reg, ENETSW_MDIOC_REG);
2003 udelay(50);
2004 spin_unlock_bh(&priv->enetsw_mdio_lock);
2005 }
2006
2007 static inline int bcm_enet_port_is_rgmii(int portid)
2008 {
2009 return portid >= ENETSW_RGMII_PORT0;
2010 }
2011
2012 /*
2013 * enet sw PHY polling
2014 */
2015 static void swphy_poll_timer(struct timer_list *t)
2016 {
2017 struct bcm_enet_priv *priv = from_timer(priv, t, swphy_poll);
2018 unsigned int i;
2019
2020 for (i = 0; i < priv->num_ports; i++) {
2021 struct bcm63xx_enetsw_port *port;
2022 int val, j, up, advertise, lpa, speed, duplex, media;
2023 int external_phy = bcm_enet_port_is_rgmii(i);
2024 u8 override;
2025
2026 port = &priv->used_ports[i];
2027 if (!port->used)
2028 continue;
2029
2030 if (port->bypass_link)
2031 continue;
2032
2033 /* dummy read to clear */
2034 for (j = 0; j < 2; j++)
2035 val = bcmenet_sw_mdio_read(priv, external_phy,
2036 port->phy_id, MII_BMSR);
2037
2038 if (val == 0xffff)
2039 continue;
2040
2041 up = (val & BMSR_LSTATUS) ? 1 : 0;
2042 if (!(up ^ priv->sw_port_link[i]))
2043 continue;
2044
2045 priv->sw_port_link[i] = up;
2046
2047 /* link changed */
2048 if (!up) {
2049 dev_info(&priv->pdev->dev, "link DOWN on %s\n",
2050 port->name);
2051 enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK,
2052 ENETSW_PORTOV_REG(i));
2053 enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK |
2054 ENETSW_PTCTRL_TXDIS_MASK,
2055 ENETSW_PTCTRL_REG(i));
2056 continue;
2057 }
2058
2059 advertise = bcmenet_sw_mdio_read(priv, external_phy,
2060 port->phy_id, MII_ADVERTISE);
2061
2062 lpa = bcmenet_sw_mdio_read(priv, external_phy, port->phy_id,
2063 MII_LPA);
2064
2065 /* figure out media and duplex from advertise and LPA values */
2066 media = mii_nway_result(lpa & advertise);
2067 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
2068
2069 if (media & (ADVERTISE_100FULL | ADVERTISE_100HALF))
2070 speed = 100;
2071 else
2072 speed = 10;
2073
2074 if (val & BMSR_ESTATEN) {
2075 advertise = bcmenet_sw_mdio_read(priv, external_phy,
2076 port->phy_id, MII_CTRL1000);
2077
2078 lpa = bcmenet_sw_mdio_read(priv, external_phy,
2079 port->phy_id, MII_STAT1000);
2080
2081 if (advertise & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)
2082 && lpa & (LPA_1000FULL | LPA_1000HALF)) {
2083 speed = 1000;
2084 duplex = (lpa & LPA_1000FULL);
2085 }
2086 }
2087
2088 dev_info(&priv->pdev->dev,
2089 "link UP on %s, %dMbps, %s-duplex\n",
2090 port->name, speed, duplex ? "full" : "half");
2091
2092 override = ENETSW_PORTOV_ENABLE_MASK |
2093 ENETSW_PORTOV_LINKUP_MASK;
2094
2095 if (speed == 1000)
2096 override |= ENETSW_IMPOV_1000_MASK;
2097 else if (speed == 100)
2098 override |= ENETSW_IMPOV_100_MASK;
2099 if (duplex)
2100 override |= ENETSW_IMPOV_FDX_MASK;
2101
2102 enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i));
2103 enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i));
2104 }
2105
2106 priv->swphy_poll.expires = jiffies + HZ;
2107 add_timer(&priv->swphy_poll);
2108 }
2109
2110 /*
2111 * open callback, allocate dma rings & buffers and start rx operation
2112 */
2113 static int bcm_enetsw_open(struct net_device *dev)
2114 {
2115 struct bcm_enet_priv *priv;
2116 struct device *kdev;
2117 int i, ret;
2118 unsigned int size;
2119 void *p;
2120 u32 val;
2121
2122 priv = netdev_priv(dev);
2123 kdev = &priv->pdev->dev;
2124
2125 /* mask all interrupts and request them */
2126 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
2127 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
2128
2129 ret = request_irq(priv->irq_rx, bcm_enet_isr_dma,
2130 0, dev->name, dev);
2131 if (ret)
2132 goto out_freeirq;
2133
2134 if (priv->irq_tx != -1) {
2135 ret = request_irq(priv->irq_tx, bcm_enet_isr_dma,
2136 0, dev->name, dev);
2137 if (ret)
2138 goto out_freeirq_rx;
2139 }
2140
2141 /* allocate rx dma ring */
2142 size = priv->rx_ring_size * sizeof(struct bcm_enet_desc);
2143 p = dma_alloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
2144 if (!p) {
2145 dev_err(kdev, "cannot allocate rx ring %u\n", size);
2146 ret = -ENOMEM;
2147 goto out_freeirq_tx;
2148 }
2149
2150 memset(p, 0, size);
2151 priv->rx_desc_alloc_size = size;
2152 priv->rx_desc_cpu = p;
2153
2154 /* allocate tx dma ring */
2155 size = priv->tx_ring_size * sizeof(struct bcm_enet_desc);
2156 p = dma_alloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
2157 if (!p) {
2158 dev_err(kdev, "cannot allocate tx ring\n");
2159 ret = -ENOMEM;
2160 goto out_free_rx_ring;
2161 }
2162
2163 memset(p, 0, size);
2164 priv->tx_desc_alloc_size = size;
2165 priv->tx_desc_cpu = p;
2166
2167 priv->tx_skb = kzalloc(sizeof(struct sk_buff *) * priv->tx_ring_size,
2168 GFP_KERNEL);
2169 if (!priv->tx_skb) {
2170 dev_err(kdev, "cannot allocate rx skb queue\n");
2171 ret = -ENOMEM;
2172 goto out_free_tx_ring;
2173 }
2174
2175 priv->tx_desc_count = priv->tx_ring_size;
2176 priv->tx_dirty_desc = 0;
2177 priv->tx_curr_desc = 0;
2178 spin_lock_init(&priv->tx_lock);
2179
2180 /* init & fill rx ring with skbs */
2181 priv->rx_skb = kzalloc(sizeof(struct sk_buff *) * priv->rx_ring_size,
2182 GFP_KERNEL);
2183 if (!priv->rx_skb) {
2184 dev_err(kdev, "cannot allocate rx skb queue\n");
2185 ret = -ENOMEM;
2186 goto out_free_tx_skb;
2187 }
2188
2189 priv->rx_desc_count = 0;
2190 priv->rx_dirty_desc = 0;
2191 priv->rx_curr_desc = 0;
2192
2193 /* disable all ports */
2194 for (i = 0; i < priv->num_ports; i++) {
2195 enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK,
2196 ENETSW_PORTOV_REG(i));
2197 enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK |
2198 ENETSW_PTCTRL_TXDIS_MASK,
2199 ENETSW_PTCTRL_REG(i));
2200
2201 priv->sw_port_link[i] = 0;
2202 }
2203
2204 /* reset mib */
2205 val = enetsw_readb(priv, ENETSW_GMCR_REG);
2206 val |= ENETSW_GMCR_RST_MIB_MASK;
2207 enetsw_writeb(priv, val, ENETSW_GMCR_REG);
2208 mdelay(1);
2209 val &= ~ENETSW_GMCR_RST_MIB_MASK;
2210 enetsw_writeb(priv, val, ENETSW_GMCR_REG);
2211 mdelay(1);
2212
2213 /* force CPU port state */
2214 val = enetsw_readb(priv, ENETSW_IMPOV_REG);
2215 val |= ENETSW_IMPOV_FORCE_MASK | ENETSW_IMPOV_LINKUP_MASK;
2216 enetsw_writeb(priv, val, ENETSW_IMPOV_REG);
2217
2218 /* enable switch forward engine */
2219 val = enetsw_readb(priv, ENETSW_SWMODE_REG);
2220 val |= ENETSW_SWMODE_FWD_EN_MASK;
2221 enetsw_writeb(priv, val, ENETSW_SWMODE_REG);
2222
2223 /* enable jumbo on all ports */
2224 enetsw_writel(priv, 0x1ff, ENETSW_JMBCTL_PORT_REG);
2225 enetsw_writew(priv, 9728, ENETSW_JMBCTL_MAXSIZE_REG);
2226
2227 /* initialize flow control buffer allocation */
2228 enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
2229 ENETDMA_BUFALLOC_REG(priv->rx_chan));
2230
2231 if (bcm_enet_refill_rx(dev)) {
2232 dev_err(kdev, "cannot allocate rx skb queue\n");
2233 ret = -ENOMEM;
2234 goto out;
2235 }
2236
2237 /* write rx & tx ring addresses */
2238 enet_dmas_writel(priv, priv->rx_desc_dma,
2239 ENETDMAS_RSTART_REG, priv->rx_chan);
2240 enet_dmas_writel(priv, priv->tx_desc_dma,
2241 ENETDMAS_RSTART_REG, priv->tx_chan);
2242
2243 /* clear remaining state ram for rx & tx channel */
2244 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
2245 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
2246 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
2247 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
2248 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
2249 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
2250
2251 /* set dma maximum burst len */
2252 enet_dmac_writel(priv, priv->dma_maxburst,
2253 ENETDMAC_MAXBURST, priv->rx_chan);
2254 enet_dmac_writel(priv, priv->dma_maxburst,
2255 ENETDMAC_MAXBURST, priv->tx_chan);
2256
2257 /* set flow control low/high threshold to 1/3 / 2/3 */
2258 val = priv->rx_ring_size / 3;
2259 enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
2260 val = (priv->rx_ring_size * 2) / 3;
2261 enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
2262
2263 /* all set, enable mac and interrupts, start dma engine and
2264 * kick rx dma channel
2265 */
2266 wmb();
2267 enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
2268 enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
2269 ENETDMAC_CHANCFG, priv->rx_chan);
2270
2271 /* watch "packet transferred" interrupt in rx and tx */
2272 enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2273 ENETDMAC_IR, priv->rx_chan);
2274 enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2275 ENETDMAC_IR, priv->tx_chan);
2276
2277 /* make sure we enable napi before rx interrupt */
2278 napi_enable(&priv->napi);
2279
2280 enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2281 ENETDMAC_IRMASK, priv->rx_chan);
2282 enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2283 ENETDMAC_IRMASK, priv->tx_chan);
2284
2285 netif_carrier_on(dev);
2286 netif_start_queue(dev);
2287
2288 /* apply override config for bypass_link ports here. */
2289 for (i = 0; i < priv->num_ports; i++) {
2290 struct bcm63xx_enetsw_port *port;
2291 u8 override;
2292 port = &priv->used_ports[i];
2293 if (!port->used)
2294 continue;
2295
2296 if (!port->bypass_link)
2297 continue;
2298
2299 override = ENETSW_PORTOV_ENABLE_MASK |
2300 ENETSW_PORTOV_LINKUP_MASK;
2301
2302 switch (port->force_speed) {
2303 case 1000:
2304 override |= ENETSW_IMPOV_1000_MASK;
2305 break;
2306 case 100:
2307 override |= ENETSW_IMPOV_100_MASK;
2308 break;
2309 case 10:
2310 break;
2311 default:
2312 pr_warn("invalid forced speed on port %s: assume 10\n",
2313 port->name);
2314 break;
2315 }
2316
2317 if (port->force_duplex_full)
2318 override |= ENETSW_IMPOV_FDX_MASK;
2319
2320
2321 enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i));
2322 enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i));
2323 }
2324
2325 /* start phy polling timer */
2326 timer_setup(&priv->swphy_poll, swphy_poll_timer, 0);
2327 mod_timer(&priv->swphy_poll, jiffies);
2328 return 0;
2329
2330 out:
2331 for (i = 0; i < priv->rx_ring_size; i++) {
2332 struct bcm_enet_desc *desc;
2333
2334 if (!priv->rx_skb[i])
2335 continue;
2336
2337 desc = &priv->rx_desc_cpu[i];
2338 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
2339 DMA_FROM_DEVICE);
2340 kfree_skb(priv->rx_skb[i]);
2341 }
2342 kfree(priv->rx_skb);
2343
2344 out_free_tx_skb:
2345 kfree(priv->tx_skb);
2346
2347 out_free_tx_ring:
2348 dma_free_coherent(kdev, priv->tx_desc_alloc_size,
2349 priv->tx_desc_cpu, priv->tx_desc_dma);
2350
2351 out_free_rx_ring:
2352 dma_free_coherent(kdev, priv->rx_desc_alloc_size,
2353 priv->rx_desc_cpu, priv->rx_desc_dma);
2354
2355 out_freeirq_tx:
2356 if (priv->irq_tx != -1)
2357 free_irq(priv->irq_tx, dev);
2358
2359 out_freeirq_rx:
2360 free_irq(priv->irq_rx, dev);
2361
2362 out_freeirq:
2363 return ret;
2364 }
2365
2366 /* stop callback */
2367 static int bcm_enetsw_stop(struct net_device *dev)
2368 {
2369 struct bcm_enet_priv *priv;
2370 struct device *kdev;
2371 int i;
2372
2373 priv = netdev_priv(dev);
2374 kdev = &priv->pdev->dev;
2375
2376 del_timer_sync(&priv->swphy_poll);
2377 netif_stop_queue(dev);
2378 napi_disable(&priv->napi);
2379 del_timer_sync(&priv->rx_timeout);
2380
2381 /* mask all interrupts */
2382 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
2383 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
2384
2385 /* disable dma & mac */
2386 bcm_enet_disable_dma(priv, priv->tx_chan);
2387 bcm_enet_disable_dma(priv, priv->rx_chan);
2388
2389 /* force reclaim of all tx buffers */
2390 bcm_enet_tx_reclaim(dev, 1);
2391
2392 /* free the rx skb ring */
2393 for (i = 0; i < priv->rx_ring_size; i++) {
2394 struct bcm_enet_desc *desc;
2395
2396 if (!priv->rx_skb[i])
2397 continue;
2398
2399 desc = &priv->rx_desc_cpu[i];
2400 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
2401 DMA_FROM_DEVICE);
2402 kfree_skb(priv->rx_skb[i]);
2403 }
2404
2405 /* free remaining allocated memory */
2406 kfree(priv->rx_skb);
2407 kfree(priv->tx_skb);
2408 dma_free_coherent(kdev, priv->rx_desc_alloc_size,
2409 priv->rx_desc_cpu, priv->rx_desc_dma);
2410 dma_free_coherent(kdev, priv->tx_desc_alloc_size,
2411 priv->tx_desc_cpu, priv->tx_desc_dma);
2412 if (priv->irq_tx != -1)
2413 free_irq(priv->irq_tx, dev);
2414 free_irq(priv->irq_rx, dev);
2415
2416 return 0;
2417 }
2418
2419 /* try to sort out phy external status by walking the used_port field
2420 * in the bcm_enet_priv structure. in case the phy address is not
2421 * assigned to any physical port on the switch, assume it is external
2422 * (and yell at the user).
2423 */
2424 static int bcm_enetsw_phy_is_external(struct bcm_enet_priv *priv, int phy_id)
2425 {
2426 int i;
2427
2428 for (i = 0; i < priv->num_ports; ++i) {
2429 if (!priv->used_ports[i].used)
2430 continue;
2431 if (priv->used_ports[i].phy_id == phy_id)
2432 return bcm_enet_port_is_rgmii(i);
2433 }
2434
2435 printk_once(KERN_WARNING "bcm63xx_enet: could not find a used port with phy_id %i, assuming phy is external\n",
2436 phy_id);
2437 return 1;
2438 }
2439
2440 /* can't use bcmenet_sw_mdio_read directly as we need to sort out
2441 * external/internal status of the given phy_id first.
2442 */
2443 static int bcm_enetsw_mii_mdio_read(struct net_device *dev, int phy_id,
2444 int location)
2445 {
2446 struct bcm_enet_priv *priv;
2447
2448 priv = netdev_priv(dev);
2449 return bcmenet_sw_mdio_read(priv,
2450 bcm_enetsw_phy_is_external(priv, phy_id),
2451 phy_id, location);
2452 }
2453
2454 /* can't use bcmenet_sw_mdio_write directly as we need to sort out
2455 * external/internal status of the given phy_id first.
2456 */
2457 static void bcm_enetsw_mii_mdio_write(struct net_device *dev, int phy_id,
2458 int location,
2459 int val)
2460 {
2461 struct bcm_enet_priv *priv;
2462
2463 priv = netdev_priv(dev);
2464 bcmenet_sw_mdio_write(priv, bcm_enetsw_phy_is_external(priv, phy_id),
2465 phy_id, location, val);
2466 }
2467
2468 static int bcm_enetsw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2469 {
2470 struct mii_if_info mii;
2471
2472 mii.dev = dev;
2473 mii.mdio_read = bcm_enetsw_mii_mdio_read;
2474 mii.mdio_write = bcm_enetsw_mii_mdio_write;
2475 mii.phy_id = 0;
2476 mii.phy_id_mask = 0x3f;
2477 mii.reg_num_mask = 0x1f;
2478 return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL);
2479
2480 }
2481
2482 static const struct net_device_ops bcm_enetsw_ops = {
2483 .ndo_open = bcm_enetsw_open,
2484 .ndo_stop = bcm_enetsw_stop,
2485 .ndo_start_xmit = bcm_enet_start_xmit,
2486 .ndo_change_mtu = bcm_enet_change_mtu,
2487 .ndo_do_ioctl = bcm_enetsw_ioctl,
2488 };
2489
2490
2491 static const struct bcm_enet_stats bcm_enetsw_gstrings_stats[] = {
2492 { "rx_packets", DEV_STAT(rx_packets), -1 },
2493 { "tx_packets", DEV_STAT(tx_packets), -1 },
2494 { "rx_bytes", DEV_STAT(rx_bytes), -1 },
2495 { "tx_bytes", DEV_STAT(tx_bytes), -1 },
2496 { "rx_errors", DEV_STAT(rx_errors), -1 },
2497 { "tx_errors", DEV_STAT(tx_errors), -1 },
2498 { "rx_dropped", DEV_STAT(rx_dropped), -1 },
2499 { "tx_dropped", DEV_STAT(tx_dropped), -1 },
2500
2501 { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETHSW_MIB_RX_GD_OCT },
2502 { "tx_unicast", GEN_STAT(mib.tx_unicast), ETHSW_MIB_RX_BRDCAST },
2503 { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETHSW_MIB_RX_BRDCAST },
2504 { "tx_multicast", GEN_STAT(mib.tx_mult), ETHSW_MIB_RX_MULT },
2505 { "tx_64_octets", GEN_STAT(mib.tx_64), ETHSW_MIB_RX_64 },
2506 { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETHSW_MIB_RX_65_127 },
2507 { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETHSW_MIB_RX_128_255 },
2508 { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETHSW_MIB_RX_256_511 },
2509 { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETHSW_MIB_RX_512_1023},
2510 { "tx_1024_1522_oct", GEN_STAT(mib.tx_1024_max),
2511 ETHSW_MIB_RX_1024_1522 },
2512 { "tx_1523_2047_oct", GEN_STAT(mib.tx_1523_2047),
2513 ETHSW_MIB_RX_1523_2047 },
2514 { "tx_2048_4095_oct", GEN_STAT(mib.tx_2048_4095),
2515 ETHSW_MIB_RX_2048_4095 },
2516 { "tx_4096_8191_oct", GEN_STAT(mib.tx_4096_8191),
2517 ETHSW_MIB_RX_4096_8191 },
2518 { "tx_8192_9728_oct", GEN_STAT(mib.tx_8192_9728),
2519 ETHSW_MIB_RX_8192_9728 },
2520 { "tx_oversize", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR },
2521 { "tx_oversize_drop", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR_DISC },
2522 { "tx_dropped", GEN_STAT(mib.tx_drop), ETHSW_MIB_RX_DROP },
2523 { "tx_undersize", GEN_STAT(mib.tx_underrun), ETHSW_MIB_RX_UND },
2524 { "tx_pause", GEN_STAT(mib.tx_pause), ETHSW_MIB_RX_PAUSE },
2525
2526 { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETHSW_MIB_TX_ALL_OCT },
2527 { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETHSW_MIB_TX_BRDCAST },
2528 { "rx_multicast", GEN_STAT(mib.rx_mult), ETHSW_MIB_TX_MULT },
2529 { "rx_unicast", GEN_STAT(mib.rx_unicast), ETHSW_MIB_TX_MULT },
2530 { "rx_pause", GEN_STAT(mib.rx_pause), ETHSW_MIB_TX_PAUSE },
2531 { "rx_dropped", GEN_STAT(mib.rx_drop), ETHSW_MIB_TX_DROP_PKTS },
2532
2533 };
2534
2535 #define BCM_ENETSW_STATS_LEN \
2536 (sizeof(bcm_enetsw_gstrings_stats) / sizeof(struct bcm_enet_stats))
2537
2538 static void bcm_enetsw_get_strings(struct net_device *netdev,
2539 u32 stringset, u8 *data)
2540 {
2541 int i;
2542
2543 switch (stringset) {
2544 case ETH_SS_STATS:
2545 for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2546 memcpy(data + i * ETH_GSTRING_LEN,
2547 bcm_enetsw_gstrings_stats[i].stat_string,
2548 ETH_GSTRING_LEN);
2549 }
2550 break;
2551 }
2552 }
2553
2554 static int bcm_enetsw_get_sset_count(struct net_device *netdev,
2555 int string_set)
2556 {
2557 switch (string_set) {
2558 case ETH_SS_STATS:
2559 return BCM_ENETSW_STATS_LEN;
2560 default:
2561 return -EINVAL;
2562 }
2563 }
2564
2565 static void bcm_enetsw_get_drvinfo(struct net_device *netdev,
2566 struct ethtool_drvinfo *drvinfo)
2567 {
2568 strncpy(drvinfo->driver, bcm_enet_driver_name, 32);
2569 strncpy(drvinfo->version, bcm_enet_driver_version, 32);
2570 strncpy(drvinfo->fw_version, "N/A", 32);
2571 strncpy(drvinfo->bus_info, "bcm63xx", 32);
2572 }
2573
2574 static void bcm_enetsw_get_ethtool_stats(struct net_device *netdev,
2575 struct ethtool_stats *stats,
2576 u64 *data)
2577 {
2578 struct bcm_enet_priv *priv;
2579 int i;
2580
2581 priv = netdev_priv(netdev);
2582
2583 for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2584 const struct bcm_enet_stats *s;
2585 u32 lo, hi;
2586 char *p;
2587 int reg;
2588
2589 s = &bcm_enetsw_gstrings_stats[i];
2590
2591 reg = s->mib_reg;
2592 if (reg == -1)
2593 continue;
2594
2595 lo = enetsw_readl(priv, ENETSW_MIB_REG(reg));
2596 p = (char *)priv + s->stat_offset;
2597
2598 if (s->sizeof_stat == sizeof(u64)) {
2599 hi = enetsw_readl(priv, ENETSW_MIB_REG(reg + 1));
2600 *(u64 *)p = ((u64)hi << 32 | lo);
2601 } else {
2602 *(u32 *)p = lo;
2603 }
2604 }
2605
2606 for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2607 const struct bcm_enet_stats *s;
2608 char *p;
2609
2610 s = &bcm_enetsw_gstrings_stats[i];
2611
2612 if (s->mib_reg == -1)
2613 p = (char *)&netdev->stats + s->stat_offset;
2614 else
2615 p = (char *)priv + s->stat_offset;
2616
2617 data[i] = (s->sizeof_stat == sizeof(u64)) ?
2618 *(u64 *)p : *(u32 *)p;
2619 }
2620 }
2621
2622 static void bcm_enetsw_get_ringparam(struct net_device *dev,
2623 struct ethtool_ringparam *ering)
2624 {
2625 struct bcm_enet_priv *priv;
2626
2627 priv = netdev_priv(dev);
2628
2629 /* rx/tx ring is actually only limited by memory */
2630 ering->rx_max_pending = 8192;
2631 ering->tx_max_pending = 8192;
2632 ering->rx_mini_max_pending = 0;
2633 ering->rx_jumbo_max_pending = 0;
2634 ering->rx_pending = priv->rx_ring_size;
2635 ering->tx_pending = priv->tx_ring_size;
2636 }
2637
2638 static int bcm_enetsw_set_ringparam(struct net_device *dev,
2639 struct ethtool_ringparam *ering)
2640 {
2641 struct bcm_enet_priv *priv;
2642 int was_running;
2643
2644 priv = netdev_priv(dev);
2645
2646 was_running = 0;
2647 if (netif_running(dev)) {
2648 bcm_enetsw_stop(dev);
2649 was_running = 1;
2650 }
2651
2652 priv->rx_ring_size = ering->rx_pending;
2653 priv->tx_ring_size = ering->tx_pending;
2654
2655 if (was_running) {
2656 int err;
2657
2658 err = bcm_enetsw_open(dev);
2659 if (err)
2660 dev_close(dev);
2661 }
2662 return 0;
2663 }
2664
2665 static const struct ethtool_ops bcm_enetsw_ethtool_ops = {
2666 .get_strings = bcm_enetsw_get_strings,
2667 .get_sset_count = bcm_enetsw_get_sset_count,
2668 .get_ethtool_stats = bcm_enetsw_get_ethtool_stats,
2669 .get_drvinfo = bcm_enetsw_get_drvinfo,
2670 .get_ringparam = bcm_enetsw_get_ringparam,
2671 .set_ringparam = bcm_enetsw_set_ringparam,
2672 };
2673
2674 /* allocate netdevice, request register memory and register device. */
2675 static int bcm_enetsw_probe(struct platform_device *pdev)
2676 {
2677 struct bcm_enet_priv *priv;
2678 struct net_device *dev;
2679 struct bcm63xx_enetsw_platform_data *pd;
2680 struct resource *res_mem;
2681 int ret, irq_rx, irq_tx;
2682
2683 if (!bcm_enet_shared_base[0])
2684 return -EPROBE_DEFER;
2685
2686 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2687 irq_rx = platform_get_irq(pdev, 0);
2688 irq_tx = platform_get_irq(pdev, 1);
2689 if (!res_mem || irq_rx < 0)
2690 return -ENODEV;
2691
2692 ret = 0;
2693 dev = alloc_etherdev(sizeof(*priv));
2694 if (!dev)
2695 return -ENOMEM;
2696 priv = netdev_priv(dev);
2697 memset(priv, 0, sizeof(*priv));
2698
2699 /* initialize default and fetch platform data */
2700 priv->enet_is_sw = true;
2701 priv->irq_rx = irq_rx;
2702 priv->irq_tx = irq_tx;
2703 priv->rx_ring_size = BCMENET_DEF_RX_DESC;
2704 priv->tx_ring_size = BCMENET_DEF_TX_DESC;
2705 priv->dma_maxburst = BCMENETSW_DMA_MAXBURST;
2706
2707 pd = dev_get_platdata(&pdev->dev);
2708 if (pd) {
2709 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
2710 memcpy(priv->used_ports, pd->used_ports,
2711 sizeof(pd->used_ports));
2712 priv->num_ports = pd->num_ports;
2713 priv->dma_has_sram = pd->dma_has_sram;
2714 priv->dma_chan_en_mask = pd->dma_chan_en_mask;
2715 priv->dma_chan_int_mask = pd->dma_chan_int_mask;
2716 priv->dma_chan_width = pd->dma_chan_width;
2717 }
2718
2719 ret = bcm_enet_change_mtu(dev, dev->mtu);
2720 if (ret)
2721 goto out;
2722
2723 priv->base = devm_ioremap_resource(&pdev->dev, res_mem);
2724 if (IS_ERR(priv->base)) {
2725 ret = PTR_ERR(priv->base);
2726 goto out;
2727 }
2728
2729 priv->mac_clk = devm_clk_get(&pdev->dev, "enetsw");
2730 if (IS_ERR(priv->mac_clk)) {
2731 ret = PTR_ERR(priv->mac_clk);
2732 goto out;
2733 }
2734 ret = clk_prepare_enable(priv->mac_clk);
2735 if (ret)
2736 goto out;
2737
2738 priv->rx_chan = 0;
2739 priv->tx_chan = 1;
2740 spin_lock_init(&priv->rx_lock);
2741
2742 /* init rx timeout (used for oom) */
2743 timer_setup(&priv->rx_timeout, bcm_enet_refill_rx_timer, 0);
2744
2745 /* register netdevice */
2746 dev->netdev_ops = &bcm_enetsw_ops;
2747 netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);
2748 dev->ethtool_ops = &bcm_enetsw_ethtool_ops;
2749 SET_NETDEV_DEV(dev, &pdev->dev);
2750
2751 spin_lock_init(&priv->enetsw_mdio_lock);
2752
2753 ret = register_netdev(dev);
2754 if (ret)
2755 goto out_disable_clk;
2756
2757 netif_carrier_off(dev);
2758 platform_set_drvdata(pdev, dev);
2759 priv->pdev = pdev;
2760 priv->net_dev = dev;
2761
2762 return 0;
2763
2764 out_disable_clk:
2765 clk_disable_unprepare(priv->mac_clk);
2766 out:
2767 free_netdev(dev);
2768 return ret;
2769 }
2770
2771
2772 /* exit func, stops hardware and unregisters netdevice */
2773 static int bcm_enetsw_remove(struct platform_device *pdev)
2774 {
2775 struct bcm_enet_priv *priv;
2776 struct net_device *dev;
2777
2778 /* stop netdevice */
2779 dev = platform_get_drvdata(pdev);
2780 priv = netdev_priv(dev);
2781 unregister_netdev(dev);
2782
2783 clk_disable_unprepare(priv->mac_clk);
2784
2785 free_netdev(dev);
2786 return 0;
2787 }
2788
2789 struct platform_driver bcm63xx_enetsw_driver = {
2790 .probe = bcm_enetsw_probe,
2791 .remove = bcm_enetsw_remove,
2792 .driver = {
2793 .name = "bcm63xx_enetsw",
2794 .owner = THIS_MODULE,
2795 },
2796 };
2797
2798 /* reserve & remap memory space shared between all macs */
2799 static int bcm_enet_shared_probe(struct platform_device *pdev)
2800 {
2801 struct resource *res;
2802 void __iomem *p[3];
2803 unsigned int i;
2804
2805 memset(bcm_enet_shared_base, 0, sizeof(bcm_enet_shared_base));
2806
2807 for (i = 0; i < 3; i++) {
2808 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
2809 p[i] = devm_ioremap_resource(&pdev->dev, res);
2810 if (IS_ERR(p[i]))
2811 return PTR_ERR(p[i]);
2812 }
2813
2814 memcpy(bcm_enet_shared_base, p, sizeof(bcm_enet_shared_base));
2815
2816 return 0;
2817 }
2818
2819 static int bcm_enet_shared_remove(struct platform_device *pdev)
2820 {
2821 return 0;
2822 }
2823
2824 /* this "shared" driver is needed because both macs share a single
2825 * address space
2826 */
2827 struct platform_driver bcm63xx_enet_shared_driver = {
2828 .probe = bcm_enet_shared_probe,
2829 .remove = bcm_enet_shared_remove,
2830 .driver = {
2831 .name = "bcm63xx_enet_shared",
2832 .owner = THIS_MODULE,
2833 },
2834 };
2835
2836 static struct platform_driver * const drivers[] = {
2837 &bcm63xx_enet_shared_driver,
2838 &bcm63xx_enet_driver,
2839 &bcm63xx_enetsw_driver,
2840 };
2841
2842 /* entry point */
2843 static int __init bcm_enet_init(void)
2844 {
2845 return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
2846 }
2847
2848 static void __exit bcm_enet_exit(void)
2849 {
2850 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
2851 }
2852
2853
2854 module_init(bcm_enet_init);
2855 module_exit(bcm_enet_exit);
2856
2857 MODULE_DESCRIPTION("BCM63xx internal ethernet mac driver");
2858 MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>");
2859 MODULE_LICENSE("GPL");
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