2 * Broadcom BCM7xxx System Port Ethernet MAC driver
4 * Copyright (C) 2014 Broadcom Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #ifndef __BCM_SYSPORT_H
12 #define __BCM_SYSPORT_H
14 #include <linux/bitmap.h>
15 #include <linux/if_vlan.h>
16 #include <linux/net_dim.h>
18 /* Receive/transmit descriptor format */
19 #define DESC_ADDR_HI_STATUS_LEN 0x00
20 #define DESC_ADDR_HI_SHIFT 0
21 #define DESC_ADDR_HI_MASK 0xff
22 #define DESC_STATUS_SHIFT 8
23 #define DESC_STATUS_MASK 0x3ff
24 #define DESC_LEN_SHIFT 18
25 #define DESC_LEN_MASK 0x7fff
26 #define DESC_ADDR_LO 0x04
28 /* HW supports 40-bit addressing hence the */
29 #define DESC_SIZE (WORDS_PER_DESC * sizeof(u32))
31 /* Default RX buffer allocation size */
32 #define RX_BUF_LENGTH 2048
34 /* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(4) + FCS(4) = 1526.
35 * 1536 is multiple of 256 bytes
37 #define ENET_BRCM_TAG_LEN 4
39 #define UMAC_MAX_MTU_SIZE (ETH_DATA_LEN + ETH_HLEN + VLAN_HLEN + \
40 ENET_BRCM_TAG_LEN + ETH_FCS_LEN + ENET_PAD)
42 /* Transmit status block */
45 #define PCP_DEI_MASK 0xf
47 #define VID_MASK 0xfff
49 #define L4_CSUM_PTR_MASK 0x1ff
50 #define L4_PTR_SHIFT 9
51 #define L4_PTR_MASK 0x1ff
52 #define L4_UDP (1 << 18)
53 #define L4_LENGTH_VALID (1 << 19)
54 #define DEST_MAP_SHIFT 20
55 #define DEST_MAP_MASK 0x1ff
58 /* Receive status block uses the same
59 * definitions as the DMA descriptor
66 /* Common Receive/Transmit status bits */
67 #define DESC_L4_CSUM (1 << 7)
68 #define DESC_SOP (1 << 8)
69 #define DESC_EOP (1 << 9)
71 /* Receive Status bits */
72 #define RX_STATUS_UCAST 0
73 #define RX_STATUS_BCAST 0x04
74 #define RX_STATUS_MCAST 0x08
75 #define RX_STATUS_L2_MCAST 0x0c
76 #define RX_STATUS_ERR (1 << 4)
77 #define RX_STATUS_OVFLOW (1 << 5)
78 #define RX_STATUS_PARSE_FAIL (1 << 6)
80 /* Transmit Status bits */
81 #define TX_STATUS_VLAN_NO_ACT 0x00
82 #define TX_STATUS_VLAN_PCP_TSB 0x01
83 #define TX_STATUS_VLAN_QUEUE 0x02
84 #define TX_STATUS_VLAN_VID_TSB 0x03
85 #define TX_STATUS_OWR_CRC (1 << 2)
86 #define TX_STATUS_APP_CRC (1 << 3)
87 #define TX_STATUS_BRCM_TAG_NO_ACT 0
88 #define TX_STATUS_BRCM_TAG_ZERO 0x10
89 #define TX_STATUS_BRCM_TAG_ONE_QUEUE 0x20
90 #define TX_STATUS_BRCM_TAG_ONE_TSB 0x30
91 #define TX_STATUS_SKIP_BYTES (1 << 6)
93 /* Specific register definitions */
94 #define SYS_PORT_TOPCTRL_OFFSET 0
96 #define REV_MASK 0xffff
98 #define RX_FLUSH_CNTL 0x04
99 #define RX_FLUSH (1 << 0)
101 #define TX_FLUSH_CNTL 0x08
102 #define TX_FLUSH (1 << 0)
104 #define MISC_CNTL 0x0c
105 #define SYS_CLK_SEL (1 << 0)
106 #define TDMA_EOP_SEL (1 << 1)
108 /* Level-2 Interrupt controller offsets and defines */
109 #define SYS_PORT_INTRL2_0_OFFSET 0x200
110 #define SYS_PORT_INTRL2_1_OFFSET 0x240
111 #define INTRL2_CPU_STATUS 0x00
112 #define INTRL2_CPU_SET 0x04
113 #define INTRL2_CPU_CLEAR 0x08
114 #define INTRL2_CPU_MASK_STATUS 0x0c
115 #define INTRL2_CPU_MASK_SET 0x10
116 #define INTRL2_CPU_MASK_CLEAR 0x14
118 /* Level-2 instance 0 interrupt bits */
119 #define INTRL2_0_GISB_ERR (1 << 0)
120 #define INTRL2_0_RBUF_OVFLOW (1 << 1)
121 #define INTRL2_0_TBUF_UNDFLOW (1 << 2)
122 #define INTRL2_0_MPD (1 << 3)
123 #define INTRL2_0_BRCM_MATCH_TAG (1 << 4)
124 #define INTRL2_0_RDMA_MBDONE (1 << 5)
125 #define INTRL2_0_OVER_MAX_THRESH (1 << 6)
126 #define INTRL2_0_BELOW_HYST_THRESH (1 << 7)
127 #define INTRL2_0_FREE_LIST_EMPTY (1 << 8)
128 #define INTRL2_0_TX_RING_FULL (1 << 9)
129 #define INTRL2_0_DESC_ALLOC_ERR (1 << 10)
130 #define INTRL2_0_UNEXP_PKTSIZE_ACK (1 << 11)
132 /* SYSTEMPORT Lite groups the TX queues interrupts on instance 0 */
133 #define INTRL2_0_TDMA_MBDONE_SHIFT 12
134 #define INTRL2_0_TDMA_MBDONE_MASK (0xffff << INTRL2_0_TDMA_MBDONE_SHIFT)
136 /* RXCHK offset and defines */
137 #define SYS_PORT_RXCHK_OFFSET 0x300
139 #define RXCHK_CONTROL 0x00
140 #define RXCHK_EN (1 << 0)
141 #define RXCHK_SKIP_FCS (1 << 1)
142 #define RXCHK_BAD_CSUM_DIS (1 << 2)
143 #define RXCHK_BRCM_TAG_EN (1 << 3)
144 #define RXCHK_BRCM_TAG_MATCH_SHIFT 4
145 #define RXCHK_BRCM_TAG_MATCH_MASK 0xff
146 #define RXCHK_PARSE_TNL (1 << 12)
147 #define RXCHK_VIOL_EN (1 << 13)
148 #define RXCHK_VIOL_DIS (1 << 14)
149 #define RXCHK_INCOM_PKT (1 << 15)
150 #define RXCHK_V6_DUPEXT_EN (1 << 16)
151 #define RXCHK_V6_DUPEXT_DIS (1 << 17)
152 #define RXCHK_ETHERTYPE_DIS (1 << 18)
153 #define RXCHK_L2_HDR_DIS (1 << 19)
154 #define RXCHK_L3_HDR_DIS (1 << 20)
155 #define RXCHK_MAC_RX_ERR_DIS (1 << 21)
156 #define RXCHK_PARSE_AUTH (1 << 22)
158 #define RXCHK_BRCM_TAG0 0x04
159 #define RXCHK_BRCM_TAG(i) ((i) * 0x4 + RXCHK_BRCM_TAG0)
160 #define RXCHK_BRCM_TAG0_MASK 0x24
161 #define RXCHK_BRCM_TAG_MASK(i) ((i) * 0x4 + RXCHK_BRCM_TAG0_MASK)
162 #define RXCHK_BRCM_TAG_MATCH_STATUS 0x44
163 #define RXCHK_ETHERTYPE 0x48
164 #define RXCHK_BAD_CSUM_CNTR 0x4C
165 #define RXCHK_OTHER_DISC_CNTR 0x50
167 #define RXCHK_BRCM_TAG_MAX 8
168 #define RXCHK_BRCM_TAG_CID_SHIFT 16
169 #define RXCHK_BRCM_TAG_CID_MASK 0xff
171 /* TXCHCK offsets and defines */
172 #define SYS_PORT_TXCHK_OFFSET 0x380
173 #define TXCHK_PKT_RDY_THRESH 0x00
175 /* Receive buffer offset and defines */
176 #define SYS_PORT_RBUF_OFFSET 0x400
178 #define RBUF_CONTROL 0x00
179 #define RBUF_RSB_EN (1 << 0)
180 #define RBUF_4B_ALGN (1 << 1)
181 #define RBUF_BRCM_TAG_STRIP (1 << 2)
182 #define RBUF_BAD_PKT_DISC (1 << 3)
183 #define RBUF_RESUME_THRESH_SHIFT 4
184 #define RBUF_RESUME_THRESH_MASK 0xff
185 #define RBUF_OK_TO_SEND_SHIFT 12
186 #define RBUF_OK_TO_SEND_MASK 0xff
187 #define RBUF_CRC_REPLACE (1 << 20)
188 #define RBUF_OK_TO_SEND_MODE (1 << 21)
189 /* SYSTEMPORT Lite uses two bits here */
190 #define RBUF_RSB_SWAP0 (1 << 22)
191 #define RBUF_RSB_SWAP1 (1 << 23)
192 #define RBUF_ACPI_EN (1 << 23)
193 #define RBUF_ACPI_EN_LITE (1 << 24)
195 #define RBUF_PKT_RDY_THRESH 0x04
197 #define RBUF_STATUS 0x08
198 #define RBUF_WOL_MODE (1 << 0)
199 #define RBUF_MPD (1 << 1)
200 #define RBUF_ACPI (1 << 2)
202 #define RBUF_OVFL_DISC_CNTR 0x0c
203 #define RBUF_ERR_PKT_CNTR 0x10
205 /* Transmit buffer offset and defines */
206 #define SYS_PORT_TBUF_OFFSET 0x600
208 #define TBUF_CONTROL 0x00
209 #define TBUF_BP_EN (1 << 0)
210 #define TBUF_MAX_PKT_THRESH_SHIFT 1
211 #define TBUF_MAX_PKT_THRESH_MASK 0x1f
212 #define TBUF_FULL_THRESH_SHIFT 8
213 #define TBUF_FULL_THRESH_MASK 0x1f
215 /* UniMAC offset and defines */
216 #define SYS_PORT_UMAC_OFFSET 0x800
218 #define UMAC_CMD 0x008
219 #define CMD_TX_EN (1 << 0)
220 #define CMD_RX_EN (1 << 1)
221 #define CMD_SPEED_SHIFT 2
222 #define CMD_SPEED_10 0
223 #define CMD_SPEED_100 1
224 #define CMD_SPEED_1000 2
225 #define CMD_SPEED_2500 3
226 #define CMD_SPEED_MASK 3
227 #define CMD_PROMISC (1 << 4)
228 #define CMD_PAD_EN (1 << 5)
229 #define CMD_CRC_FWD (1 << 6)
230 #define CMD_PAUSE_FWD (1 << 7)
231 #define CMD_RX_PAUSE_IGNORE (1 << 8)
232 #define CMD_TX_ADDR_INS (1 << 9)
233 #define CMD_HD_EN (1 << 10)
234 #define CMD_SW_RESET (1 << 13)
235 #define CMD_LCL_LOOP_EN (1 << 15)
236 #define CMD_AUTO_CONFIG (1 << 22)
237 #define CMD_CNTL_FRM_EN (1 << 23)
238 #define CMD_NO_LEN_CHK (1 << 24)
239 #define CMD_RMT_LOOP_EN (1 << 25)
240 #define CMD_PRBL_EN (1 << 27)
241 #define CMD_TX_PAUSE_IGNORE (1 << 28)
242 #define CMD_TX_RX_EN (1 << 29)
243 #define CMD_RUNT_FILTER_DIS (1 << 30)
245 #define UMAC_MAC0 0x00c
246 #define UMAC_MAC1 0x010
247 #define UMAC_MAX_FRAME_LEN 0x014
249 #define UMAC_TX_FLUSH 0x334
251 #define UMAC_MIB_START 0x400
253 /* There is a 0xC gap between the end of RX and beginning of TX stats and then
254 * between the end of TX stats and the beginning of the RX RUNT
256 #define UMAC_MIB_STAT_OFFSET 0xc
258 #define UMAC_MIB_CTRL 0x580
259 #define MIB_RX_CNT_RST (1 << 0)
260 #define MIB_RUNT_CNT_RST (1 << 1)
261 #define MIB_TX_CNT_RST (1 << 2)
263 /* These offsets are valid for SYSTEMPORT and SYSTEMPORT Lite */
264 #define UMAC_MPD_CTRL 0x620
265 #define MPD_EN (1 << 0)
266 #define MSEQ_LEN_SHIFT 16
267 #define MSEQ_LEN_MASK 0xff
268 #define PSW_EN (1 << 27)
270 #define UMAC_PSW_MS 0x624
271 #define UMAC_PSW_LS 0x628
272 #define UMAC_MDF_CTRL 0x650
273 #define UMAC_MDF_ADDR 0x654
275 /* Only valid on SYSTEMPORT Lite */
276 #define SYS_PORT_GIB_OFFSET 0x1000
278 #define GIB_CONTROL 0x00
279 #define GIB_TX_EN (1 << 0)
280 #define GIB_RX_EN (1 << 1)
281 #define GIB_TX_FLUSH (1 << 2)
282 #define GIB_RX_FLUSH (1 << 3)
283 #define GIB_GTX_CLK_SEL_SHIFT 4
284 #define GIB_GTX_CLK_EXT_CLK (0 << GIB_GTX_CLK_SEL_SHIFT)
285 #define GIB_GTX_CLK_125MHZ (1 << GIB_GTX_CLK_SEL_SHIFT)
286 #define GIB_GTX_CLK_250MHZ (2 << GIB_GTX_CLK_SEL_SHIFT)
287 #define GIB_FCS_STRIP_SHIFT 6
288 #define GIB_FCS_STRIP (1 << GIB_FCS_STRIP_SHIFT)
289 #define GIB_LCL_LOOP_EN (1 << 7)
290 #define GIB_LCL_LOOP_TXEN (1 << 8)
291 #define GIB_RMT_LOOP_EN (1 << 9)
292 #define GIB_RMT_LOOP_RXEN (1 << 10)
293 #define GIB_RX_PAUSE_EN (1 << 11)
294 #define GIB_PREAMBLE_LEN_SHIFT 12
295 #define GIB_PREAMBLE_LEN_MASK 0xf
296 #define GIB_IPG_LEN_SHIFT 16
297 #define GIB_IPG_LEN_MASK 0x3f
298 #define GIB_PAD_EXTENSION_SHIFT 22
299 #define GIB_PAD_EXTENSION_MASK 0x3f
301 #define GIB_MAC1 0x08
302 #define GIB_MAC0 0x0c
304 /* Receive DMA offset and defines */
305 #define SYS_PORT_RDMA_OFFSET 0x2000
307 #define RDMA_CONTROL 0x1000
308 #define RDMA_EN (1 << 0)
309 #define RDMA_RING_CFG (1 << 1)
310 #define RDMA_DISC_EN (1 << 2)
311 #define RDMA_BUF_DATA_OFFSET_SHIFT 4
312 #define RDMA_BUF_DATA_OFFSET_MASK 0x3ff
314 #define RDMA_STATUS 0x1004
315 #define RDMA_DISABLED (1 << 0)
316 #define RDMA_DESC_RAM_INIT_BUSY (1 << 1)
317 #define RDMA_BP_STATUS (1 << 2)
319 #define RDMA_SCB_BURST_SIZE 0x1008
321 #define RDMA_RING_BUF_SIZE 0x100c
322 #define RDMA_RING_SIZE_SHIFT 16
324 #define RDMA_WRITE_PTR_HI 0x1010
325 #define RDMA_WRITE_PTR_LO 0x1014
326 #define RDMA_PROD_INDEX 0x1018
327 #define RDMA_PROD_INDEX_MASK 0xffff
329 #define RDMA_CONS_INDEX 0x101c
330 #define RDMA_CONS_INDEX_MASK 0xffff
332 #define RDMA_START_ADDR_HI 0x1020
333 #define RDMA_START_ADDR_LO 0x1024
334 #define RDMA_END_ADDR_HI 0x1028
335 #define RDMA_END_ADDR_LO 0x102c
337 #define RDMA_MBDONE_INTR 0x1030
338 #define RDMA_INTR_THRESH_MASK 0x1ff
339 #define RDMA_TIMEOUT_SHIFT 16
340 #define RDMA_TIMEOUT_MASK 0xffff
342 #define RDMA_XON_XOFF_THRESH 0x1034
343 #define RDMA_XON_XOFF_THRESH_MASK 0xffff
344 #define RDMA_XOFF_THRESH_SHIFT 16
346 #define RDMA_READ_PTR_HI 0x1038
347 #define RDMA_READ_PTR_LO 0x103c
349 #define RDMA_OVERRIDE 0x1040
350 #define RDMA_LE_MODE (1 << 0)
351 #define RDMA_REG_MODE (1 << 1)
353 #define RDMA_TEST 0x1044
354 #define RDMA_TP_OUT_SEL (1 << 0)
355 #define RDMA_MEM_SEL (1 << 1)
357 #define RDMA_DEBUG 0x1048
359 /* Transmit DMA offset and defines */
360 #define TDMA_NUM_RINGS 32 /* rings = queues */
361 #define TDMA_PORT_SIZE DESC_SIZE /* two 32-bits words */
363 #define SYS_PORT_TDMA_OFFSET 0x4000
364 #define TDMA_WRITE_PORT_OFFSET 0x0000
365 #define TDMA_WRITE_PORT_HI(i) (TDMA_WRITE_PORT_OFFSET + \
366 (i) * TDMA_PORT_SIZE)
367 #define TDMA_WRITE_PORT_LO(i) (TDMA_WRITE_PORT_OFFSET + \
368 sizeof(u32) + (i) * TDMA_PORT_SIZE)
370 #define TDMA_READ_PORT_OFFSET (TDMA_WRITE_PORT_OFFSET + \
371 (TDMA_NUM_RINGS * TDMA_PORT_SIZE))
372 #define TDMA_READ_PORT_HI(i) (TDMA_READ_PORT_OFFSET + \
373 (i) * TDMA_PORT_SIZE)
374 #define TDMA_READ_PORT_LO(i) (TDMA_READ_PORT_OFFSET + \
375 sizeof(u32) + (i) * TDMA_PORT_SIZE)
377 #define TDMA_READ_PORT_CMD_OFFSET (TDMA_READ_PORT_OFFSET + \
378 (TDMA_NUM_RINGS * TDMA_PORT_SIZE))
379 #define TDMA_READ_PORT_CMD(i) (TDMA_READ_PORT_CMD_OFFSET + \
382 #define TDMA_DESC_RING_00_BASE (TDMA_READ_PORT_CMD_OFFSET + \
383 (TDMA_NUM_RINGS * sizeof(u32)))
385 /* Register offsets and defines relatives to a specific ring number */
386 #define RING_HEAD_TAIL_PTR 0x00
387 #define RING_HEAD_MASK 0x7ff
388 #define RING_TAIL_SHIFT 11
389 #define RING_TAIL_MASK 0x7ff
390 #define RING_FLUSH (1 << 24)
391 #define RING_EN (1 << 25)
393 #define RING_COUNT 0x04
394 #define RING_COUNT_MASK 0x7ff
395 #define RING_BUFF_DONE_SHIFT 11
396 #define RING_BUFF_DONE_MASK 0x7ff
398 #define RING_MAX_HYST 0x08
399 #define RING_MAX_THRESH_MASK 0x7ff
400 #define RING_HYST_THRESH_SHIFT 11
401 #define RING_HYST_THRESH_MASK 0x7ff
403 #define RING_INTR_CONTROL 0x0c
404 #define RING_INTR_THRESH_MASK 0x7ff
405 #define RING_EMPTY_INTR_EN (1 << 15)
406 #define RING_TIMEOUT_SHIFT 16
407 #define RING_TIMEOUT_MASK 0xffff
409 #define RING_PROD_CONS_INDEX 0x10
410 #define RING_PROD_INDEX_MASK 0xffff
411 #define RING_CONS_INDEX_SHIFT 16
412 #define RING_CONS_INDEX_MASK 0xffff
414 #define RING_MAPPING 0x14
415 #define RING_QID_MASK 0x7
416 #define RING_PORT_ID_SHIFT 3
417 #define RING_PORT_ID_MASK 0x7
418 #define RING_IGNORE_STATUS (1 << 6)
419 #define RING_FAILOVER_EN (1 << 7)
420 #define RING_CREDIT_SHIFT 8
421 #define RING_CREDIT_MASK 0xffff
423 #define RING_PCP_DEI_VID 0x18
424 #define RING_VID_MASK 0x7ff
425 #define RING_DEI (1 << 12)
426 #define RING_PCP_SHIFT 13
427 #define RING_PCP_MASK 0x7
428 #define RING_PKT_SIZE_ADJ_SHIFT 16
429 #define RING_PKT_SIZE_ADJ_MASK 0xf
431 #define TDMA_DESC_RING_SIZE 28
433 /* Defininition for a given TX ring base address */
434 #define TDMA_DESC_RING_BASE(i) (TDMA_DESC_RING_00_BASE + \
435 ((i) * TDMA_DESC_RING_SIZE))
437 /* Ring indexed register addreses */
438 #define TDMA_DESC_RING_HEAD_TAIL_PTR(i) (TDMA_DESC_RING_BASE(i) + \
440 #define TDMA_DESC_RING_COUNT(i) (TDMA_DESC_RING_BASE(i) + \
442 #define TDMA_DESC_RING_MAX_HYST(i) (TDMA_DESC_RING_BASE(i) + \
444 #define TDMA_DESC_RING_INTR_CONTROL(i) (TDMA_DESC_RING_BASE(i) + \
446 #define TDMA_DESC_RING_PROD_CONS_INDEX(i) \
447 (TDMA_DESC_RING_BASE(i) + \
448 RING_PROD_CONS_INDEX)
449 #define TDMA_DESC_RING_MAPPING(i) (TDMA_DESC_RING_BASE(i) + \
451 #define TDMA_DESC_RING_PCP_DEI_VID(i) (TDMA_DESC_RING_BASE(i) + \
454 #define TDMA_CONTROL 0x600
457 /* Uses 2 bits on SYSTEMPORT Lite and shifts everything by 1 bit, we
458 * keep the SYSTEMPORT layout here and adjust with tdma_control_bit()
463 #define BUF_DATA_OFFSET_SHIFT 4
464 #define BUF_DATA_OFFSET_MASK 0x3ff
466 #define SW_BRCM_TAG 15
467 #define WNC_KPT_SIZE_UPDATE 16
468 #define SYNC_PKT_SIZE 17
469 #define ACH_TXDONE_DELAY_SHIFT 18
470 #define ACH_TXDONE_DELAY_MASK 0xff
472 #define TDMA_STATUS 0x604
473 #define TDMA_DISABLED (1 << 0)
474 #define TDMA_LL_RAM_INIT_BUSY (1 << 1)
476 #define TDMA_SCB_BURST_SIZE 0x608
477 #define TDMA_OVER_MAX_THRESH_STATUS 0x60c
478 #define TDMA_OVER_HYST_THRESH_STATUS 0x610
479 #define TDMA_TPID 0x614
481 #define TDMA_FREE_LIST_HEAD_TAIL_PTR 0x618
482 #define TDMA_FREE_HEAD_MASK 0x7ff
483 #define TDMA_FREE_TAIL_SHIFT 11
484 #define TDMA_FREE_TAIL_MASK 0x7ff
486 #define TDMA_FREE_LIST_COUNT 0x61c
487 #define TDMA_FREE_LIST_COUNT_MASK 0x7ff
489 #define TDMA_TIER2_ARB_CTRL 0x620
490 #define TDMA_ARB_MODE_RR 0
491 #define TDMA_ARB_MODE_WEIGHT_RR 0x1
492 #define TDMA_ARB_MODE_STRICT 0x2
493 #define TDMA_ARB_MODE_DEFICIT_RR 0x3
494 #define TDMA_CREDIT_SHIFT 4
495 #define TDMA_CREDIT_MASK 0xffff
497 #define TDMA_TIER1_ARB_0_CTRL 0x624
498 #define TDMA_ARB_EN (1 << 0)
500 #define TDMA_TIER1_ARB_0_QUEUE_EN 0x628
501 #define TDMA_TIER1_ARB_1_CTRL 0x62c
502 #define TDMA_TIER1_ARB_1_QUEUE_EN 0x630
503 #define TDMA_TIER1_ARB_2_CTRL 0x634
504 #define TDMA_TIER1_ARB_2_QUEUE_EN 0x638
505 #define TDMA_TIER1_ARB_3_CTRL 0x63c
506 #define TDMA_TIER1_ARB_3_QUEUE_EN 0x640
508 #define TDMA_SCB_ENDIAN_OVERRIDE 0x644
509 #define TDMA_LE_MODE (1 << 0)
510 #define TDMA_REG_MODE (1 << 1)
512 #define TDMA_TEST 0x648
513 #define TDMA_TP_OUT_SEL (1 << 0)
514 #define TDMA_MEM_TM (1 << 1)
516 #define TDMA_DEBUG 0x64c
518 /* Transmit/Receive descriptor */
524 /* Number of Receive hardware descriptor words */
525 #define SP_NUM_HW_RX_DESC_WORDS 1024
526 #define SP_LT_NUM_HW_RX_DESC_WORDS 256
528 /* Internal linked-list RAM size */
529 #define SP_NUM_TX_DESC 1536
530 #define SP_LT_NUM_TX_DESC 256
532 #define WORDS_PER_DESC (sizeof(struct dma_desc) / sizeof(u32))
534 /* Rx/Tx common counter group.*/
535 struct bcm_sysport_pkt_counters
{
536 u32 cnt_64
; /* RO Received/Transmited 64 bytes packet */
537 u32 cnt_127
; /* RO Rx/Tx 127 bytes packet */
538 u32 cnt_255
; /* RO Rx/Tx 65-255 bytes packet */
539 u32 cnt_511
; /* RO Rx/Tx 256-511 bytes packet */
540 u32 cnt_1023
; /* RO Rx/Tx 512-1023 bytes packet */
541 u32 cnt_1518
; /* RO Rx/Tx 1024-1518 bytes packet */
542 u32 cnt_mgv
; /* RO Rx/Tx 1519-1522 good VLAN packet */
543 u32 cnt_2047
; /* RO Rx/Tx 1522-2047 bytes packet*/
544 u32 cnt_4095
; /* RO Rx/Tx 2048-4095 bytes packet*/
545 u32 cnt_9216
; /* RO Rx/Tx 4096-9216 bytes packet*/
548 /* RSV, Receive Status Vector */
549 struct bcm_sysport_rx_counters
{
550 struct bcm_sysport_pkt_counters pkt_cnt
;
551 u32 pkt
; /* RO (0x428) Received pkt count*/
552 u32 bytes
; /* RO Received byte count */
553 u32 mca
; /* RO # of Received multicast pkt */
554 u32 bca
; /* RO # of Receive broadcast pkt */
555 u32 fcs
; /* RO # of Received FCS error */
556 u32 cf
; /* RO # of Received control frame pkt*/
557 u32 pf
; /* RO # of Received pause frame pkt */
558 u32 uo
; /* RO # of unknown op code pkt */
559 u32 aln
; /* RO # of alignment error count */
560 u32 flr
; /* RO # of frame length out of range count */
561 u32 cde
; /* RO # of code error pkt */
562 u32 fcr
; /* RO # of carrier sense error pkt */
563 u32 ovr
; /* RO # of oversize pkt*/
564 u32 jbr
; /* RO # of jabber count */
565 u32 mtue
; /* RO # of MTU error pkt*/
566 u32 pok
; /* RO # of Received good pkt */
567 u32 uc
; /* RO # of unicast pkt */
568 u32 ppp
; /* RO # of PPP pkt */
569 u32 rcrc
; /* RO (0x470),# of CRC match pkt */
572 /* TSV, Transmit Status Vector */
573 struct bcm_sysport_tx_counters
{
574 struct bcm_sysport_pkt_counters pkt_cnt
;
575 u32 pkts
; /* RO (0x4a8) Transmited pkt */
576 u32 mca
; /* RO # of xmited multicast pkt */
577 u32 bca
; /* RO # of xmited broadcast pkt */
578 u32 pf
; /* RO # of xmited pause frame count */
579 u32 cf
; /* RO # of xmited control frame count */
580 u32 fcs
; /* RO # of xmited FCS error count */
581 u32 ovr
; /* RO # of xmited oversize pkt */
582 u32 drf
; /* RO # of xmited deferral pkt */
583 u32 edf
; /* RO # of xmited Excessive deferral pkt*/
584 u32 scl
; /* RO # of xmited single collision pkt */
585 u32 mcl
; /* RO # of xmited multiple collision pkt*/
586 u32 lcl
; /* RO # of xmited late collision pkt */
587 u32 ecl
; /* RO # of xmited excessive collision pkt*/
588 u32 frg
; /* RO # of xmited fragments pkt*/
589 u32 ncl
; /* RO # of xmited total collision count */
590 u32 jbr
; /* RO # of xmited jabber count*/
591 u32 bytes
; /* RO # of xmited byte count */
592 u32 pok
; /* RO # of xmited good pkt */
593 u32 uc
; /* RO (0x4f0) # of xmited unicast pkt */
596 struct bcm_sysport_mib
{
597 struct bcm_sysport_rx_counters rx
;
598 struct bcm_sysport_tx_counters tx
;
601 u32 rx_runt_fcs_align
;
604 u32 rxchk_other_pkt_disc
;
607 u32 alloc_rx_buff_failed
;
611 u32 tx_realloc_tsb_failed
;
614 /* HW maintains a large list of counters */
615 enum bcm_sysport_stat_type
{
616 BCM_SYSPORT_STAT_NETDEV
= -1,
617 BCM_SYSPORT_STAT_NETDEV64
,
618 BCM_SYSPORT_STAT_MIB_RX
,
619 BCM_SYSPORT_STAT_MIB_TX
,
620 BCM_SYSPORT_STAT_RUNT
,
621 BCM_SYSPORT_STAT_RXCHK
,
622 BCM_SYSPORT_STAT_RBUF
,
623 BCM_SYSPORT_STAT_SOFT
,
626 /* Macros to help define ethtool statistics */
627 #define STAT_NETDEV(m) { \
628 .stat_string = __stringify(m), \
629 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
630 .stat_offset = offsetof(struct net_device_stats, m), \
631 .type = BCM_SYSPORT_STAT_NETDEV, \
634 #define STAT_NETDEV64(m) { \
635 .stat_string = __stringify(m), \
636 .stat_sizeof = sizeof(((struct bcm_sysport_stats64 *)0)->m), \
637 .stat_offset = offsetof(struct bcm_sysport_stats64, m), \
638 .type = BCM_SYSPORT_STAT_NETDEV64, \
641 #define STAT_MIB(str, m, _type) { \
642 .stat_string = str, \
643 .stat_sizeof = sizeof(((struct bcm_sysport_priv *)0)->m), \
644 .stat_offset = offsetof(struct bcm_sysport_priv, m), \
648 #define STAT_MIB_RX(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_MIB_RX)
649 #define STAT_MIB_TX(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_MIB_TX)
650 #define STAT_RUNT(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_RUNT)
651 #define STAT_MIB_SOFT(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_SOFT)
653 #define STAT_RXCHK(str, m, ofs) { \
654 .stat_string = str, \
655 .stat_sizeof = sizeof(((struct bcm_sysport_priv *)0)->m), \
656 .stat_offset = offsetof(struct bcm_sysport_priv, m), \
657 .type = BCM_SYSPORT_STAT_RXCHK, \
661 #define STAT_RBUF(str, m, ofs) { \
662 .stat_string = str, \
663 .stat_sizeof = sizeof(((struct bcm_sysport_priv *)0)->m), \
664 .stat_offset = offsetof(struct bcm_sysport_priv, m), \
665 .type = BCM_SYSPORT_STAT_RBUF, \
669 /* TX bytes and packets */
670 #define NUM_SYSPORT_TXQ_STAT 2
672 struct bcm_sysport_stats
{
673 char stat_string
[ETH_GSTRING_LEN
];
676 enum bcm_sysport_stat_type type
;
677 /* reg offset from UMAC base for misc counters */
681 struct bcm_sysport_stats64
{
682 /* 64bit stats on 32bit/64bit Machine */
689 /* Software house keeping helper structure */
690 struct bcm_sysport_cb
{
691 struct sk_buff
*skb
; /* SKB for RX packets */
692 void __iomem
*bd_addr
; /* Buffer descriptor PHYS addr */
694 DEFINE_DMA_UNMAP_ADDR(dma_addr
);
695 DEFINE_DMA_UNMAP_LEN(dma_len
);
698 enum bcm_sysport_type
{
703 struct bcm_sysport_hw_params
{
705 unsigned int num_rx_desc_words
;
708 struct bcm_sysport_net_dim
{
711 unsigned long packets
;
716 /* Software view of the TX ring */
717 struct bcm_sysport_tx_ring
{
718 spinlock_t lock
; /* Ring lock for tx reclaim/xmit */
719 struct napi_struct napi
; /* NAPI per tx queue */
720 dma_addr_t desc_dma
; /* DMA cookie */
721 unsigned int index
; /* Ring index */
722 unsigned int size
; /* Ring current size */
723 unsigned int alloc_size
; /* Ring one-time allocated size */
724 unsigned int desc_count
; /* Number of descriptors */
725 unsigned int curr_desc
; /* Current descriptor */
726 unsigned int c_index
; /* Last consumer index */
727 unsigned int clean_index
; /* Current clean index */
728 struct bcm_sysport_cb
*cbs
; /* Transmit control blocks */
729 struct dma_desc
*desc_cpu
; /* CPU view of the descriptor */
730 struct bcm_sysport_priv
*priv
; /* private context backpointer */
731 unsigned long packets
; /* packets statistics */
732 unsigned long bytes
; /* bytes statistics */
733 unsigned int switch_queue
; /* switch port queue number */
734 unsigned int switch_port
; /* switch port queue number */
735 bool inspect
; /* inspect switch port and queue */
738 /* Driver private structure */
739 struct bcm_sysport_priv
{
746 unsigned int num_rx_desc_words
;
747 struct napi_struct napi ____cacheline_aligned
;
748 struct net_device
*netdev
;
749 struct platform_device
*pdev
;
755 struct bcm_sysport_tx_ring
*tx_rings
;
758 void __iomem
*rx_bds
;
759 struct bcm_sysport_cb
*rx_cbs
;
760 unsigned int num_rx_bds
;
761 unsigned int rx_read_ptr
;
762 unsigned int rx_c_index
;
764 struct bcm_sysport_net_dim dim
;
765 u32 rx_max_coalesced_frames
;
766 u32 rx_coalesce_usecs
;
769 struct device_node
*phy_dn
;
770 phy_interface_t phy_interface
;
776 unsigned int rx_chk_en
:1;
777 unsigned int tsb_en
:1;
778 unsigned int crc_fwd
:1;
781 unsigned int wol_irq_disabled
:1;
783 /* MIB related fields */
784 struct bcm_sysport_mib mib
;
788 DECLARE_BITMAP(filters
, RXCHK_BRCM_TAG_MAX
);
789 u32 filters_loc
[RXCHK_BRCM_TAG_MAX
];
791 struct bcm_sysport_stats64 stats64
;
793 /* For atomic update generic 64bit value on 32bit Machine */
794 struct u64_stats_sync syncp
;
796 /* map information between switch port queues and local queues */
797 struct notifier_block dsa_notifier
;
798 unsigned int per_port_num_tx_queues
;
799 struct bcm_sysport_tx_ring
*ring_map
[DSA_MAX_PORTS
* 8];
802 #endif /* __BCM_SYSPORT_H */