2 * Driver for (BCM4706)? GBit MAC core on BCMA bus.
4 * Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com>
6 * Licensed under the GNU/GPL. See COPYING for details.
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/etherdevice.h>
15 #include <linux/mii.h>
16 #include <linux/phy.h>
17 #include <linux/interrupt.h>
18 #include <linux/dma-mapping.h>
19 #include <bcm47xx_nvram.h>
21 static const struct bcma_device_id bgmac_bcma_tbl
[] = {
22 BCMA_CORE(BCMA_MANUF_BCM
, BCMA_CORE_4706_MAC_GBIT
, BCMA_ANY_REV
, BCMA_ANY_CLASS
),
23 BCMA_CORE(BCMA_MANUF_BCM
, BCMA_CORE_MAC_GBIT
, BCMA_ANY_REV
, BCMA_ANY_CLASS
),
26 MODULE_DEVICE_TABLE(bcma
, bgmac_bcma_tbl
);
28 static bool bgmac_wait_value(struct bcma_device
*core
, u16 reg
, u32 mask
,
29 u32 value
, int timeout
)
34 for (i
= 0; i
< timeout
/ 10; i
++) {
35 val
= bcma_read32(core
, reg
);
36 if ((val
& mask
) == value
)
40 pr_err("Timeout waiting for reg 0x%X\n", reg
);
44 /**************************************************
46 **************************************************/
48 static void bgmac_dma_tx_reset(struct bgmac
*bgmac
, struct bgmac_dma_ring
*ring
)
56 /* Suspend DMA TX ring first.
57 * bgmac_wait_value doesn't support waiting for any of few values, so
58 * implement whole loop here.
60 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_CTL
,
61 BGMAC_DMA_TX_SUSPEND
);
62 for (i
= 0; i
< 10000 / 10; i
++) {
63 val
= bgmac_read(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_STATUS
);
64 val
&= BGMAC_DMA_TX_STAT
;
65 if (val
== BGMAC_DMA_TX_STAT_DISABLED
||
66 val
== BGMAC_DMA_TX_STAT_IDLEWAIT
||
67 val
== BGMAC_DMA_TX_STAT_STOPPED
) {
74 bgmac_err(bgmac
, "Timeout suspending DMA TX ring 0x%X (BGMAC_DMA_TX_STAT: 0x%08X)\n",
75 ring
->mmio_base
, val
);
77 /* Remove SUSPEND bit */
78 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_CTL
, 0);
79 if (!bgmac_wait_value(bgmac
->core
,
80 ring
->mmio_base
+ BGMAC_DMA_TX_STATUS
,
81 BGMAC_DMA_TX_STAT
, BGMAC_DMA_TX_STAT_DISABLED
,
83 bgmac_warn(bgmac
, "DMA TX ring 0x%X wasn't disabled on time, waiting additional 300us\n",
86 val
= bgmac_read(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_STATUS
);
87 if ((val
& BGMAC_DMA_TX_STAT
) != BGMAC_DMA_TX_STAT_DISABLED
)
88 bgmac_err(bgmac
, "Reset of DMA TX ring 0x%X failed\n",
93 static void bgmac_dma_tx_enable(struct bgmac
*bgmac
,
94 struct bgmac_dma_ring
*ring
)
98 ctl
= bgmac_read(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_CTL
);
99 ctl
|= BGMAC_DMA_TX_ENABLE
;
100 ctl
|= BGMAC_DMA_TX_PARITY_DISABLE
;
101 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_CTL
, ctl
);
104 static netdev_tx_t
bgmac_dma_tx_add(struct bgmac
*bgmac
,
105 struct bgmac_dma_ring
*ring
,
108 struct device
*dma_dev
= bgmac
->core
->dma_dev
;
109 struct net_device
*net_dev
= bgmac
->net_dev
;
110 struct bgmac_dma_desc
*dma_desc
;
111 struct bgmac_slot_info
*slot
;
115 if (skb
->len
> BGMAC_DESC_CTL1_LEN
) {
116 bgmac_err(bgmac
, "Too long skb (%d)\n", skb
->len
);
120 if (ring
->start
<= ring
->end
)
121 free_slots
= ring
->start
- ring
->end
+ BGMAC_TX_RING_SLOTS
;
123 free_slots
= ring
->start
- ring
->end
;
124 if (free_slots
== 1) {
125 bgmac_err(bgmac
, "TX ring is full, queue should be stopped!\n");
126 netif_stop_queue(net_dev
);
127 return NETDEV_TX_BUSY
;
130 slot
= &ring
->slots
[ring
->end
];
132 slot
->dma_addr
= dma_map_single(dma_dev
, skb
->data
, skb
->len
,
134 if (dma_mapping_error(dma_dev
, slot
->dma_addr
)) {
135 bgmac_err(bgmac
, "Mapping error of skb on ring 0x%X\n",
140 ctl0
= BGMAC_DESC_CTL0_IOC
| BGMAC_DESC_CTL0_SOF
| BGMAC_DESC_CTL0_EOF
;
141 if (ring
->end
== ring
->num_slots
- 1)
142 ctl0
|= BGMAC_DESC_CTL0_EOT
;
143 ctl1
= skb
->len
& BGMAC_DESC_CTL1_LEN
;
145 dma_desc
= ring
->cpu_base
;
146 dma_desc
+= ring
->end
;
147 dma_desc
->addr_low
= cpu_to_le32(lower_32_bits(slot
->dma_addr
));
148 dma_desc
->addr_high
= cpu_to_le32(upper_32_bits(slot
->dma_addr
));
149 dma_desc
->ctl0
= cpu_to_le32(ctl0
);
150 dma_desc
->ctl1
= cpu_to_le32(ctl1
);
152 netdev_sent_queue(net_dev
, skb
->len
);
156 /* Increase ring->end to point empty slot. We tell hardware the first
157 * slot it should *not* read.
159 if (++ring
->end
>= BGMAC_TX_RING_SLOTS
)
161 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_INDEX
,
163 ring
->end
* sizeof(struct bgmac_dma_desc
));
165 /* Always keep one slot free to allow detecting bugged calls. */
166 if (--free_slots
== 1)
167 netif_stop_queue(net_dev
);
172 netif_stop_queue(net_dev
);
177 /* Free transmitted packets */
178 static void bgmac_dma_tx_free(struct bgmac
*bgmac
, struct bgmac_dma_ring
*ring
)
180 struct device
*dma_dev
= bgmac
->core
->dma_dev
;
183 unsigned bytes_compl
= 0, pkts_compl
= 0;
185 /* The last slot that hardware didn't consume yet */
186 empty_slot
= bgmac_read(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_STATUS
);
187 empty_slot
&= BGMAC_DMA_TX_STATDPTR
;
188 empty_slot
-= ring
->index_base
;
189 empty_slot
&= BGMAC_DMA_TX_STATDPTR
;
190 empty_slot
/= sizeof(struct bgmac_dma_desc
);
192 while (ring
->start
!= empty_slot
) {
193 struct bgmac_slot_info
*slot
= &ring
->slots
[ring
->start
];
196 /* Unmap no longer used buffer */
197 dma_unmap_single(dma_dev
, slot
->dma_addr
,
198 slot
->skb
->len
, DMA_TO_DEVICE
);
201 bytes_compl
+= slot
->skb
->len
;
204 /* Free memory! :) */
205 dev_kfree_skb(slot
->skb
);
208 bgmac_err(bgmac
, "Hardware reported transmission for empty TX ring slot %d! End of ring: %d\n",
209 ring
->start
, ring
->end
);
212 if (++ring
->start
>= BGMAC_TX_RING_SLOTS
)
217 netdev_completed_queue(bgmac
->net_dev
, pkts_compl
, bytes_compl
);
219 if (freed
&& netif_queue_stopped(bgmac
->net_dev
))
220 netif_wake_queue(bgmac
->net_dev
);
223 static void bgmac_dma_rx_reset(struct bgmac
*bgmac
, struct bgmac_dma_ring
*ring
)
225 if (!ring
->mmio_base
)
228 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_RX_CTL
, 0);
229 if (!bgmac_wait_value(bgmac
->core
,
230 ring
->mmio_base
+ BGMAC_DMA_RX_STATUS
,
231 BGMAC_DMA_RX_STAT
, BGMAC_DMA_RX_STAT_DISABLED
,
233 bgmac_err(bgmac
, "Reset of ring 0x%X RX failed\n",
237 static void bgmac_dma_rx_enable(struct bgmac
*bgmac
,
238 struct bgmac_dma_ring
*ring
)
242 ctl
= bgmac_read(bgmac
, ring
->mmio_base
+ BGMAC_DMA_RX_CTL
);
243 ctl
&= BGMAC_DMA_RX_ADDREXT_MASK
;
244 ctl
|= BGMAC_DMA_RX_ENABLE
;
245 ctl
|= BGMAC_DMA_RX_PARITY_DISABLE
;
246 ctl
|= BGMAC_DMA_RX_OVERFLOW_CONT
;
247 ctl
|= BGMAC_RX_FRAME_OFFSET
<< BGMAC_DMA_RX_FRAME_OFFSET_SHIFT
;
248 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_RX_CTL
, ctl
);
251 static int bgmac_dma_rx_skb_for_slot(struct bgmac
*bgmac
,
252 struct bgmac_slot_info
*slot
)
254 struct device
*dma_dev
= bgmac
->core
->dma_dev
;
257 struct bgmac_rx_header
*rx
;
260 skb
= netdev_alloc_skb(bgmac
->net_dev
, BGMAC_RX_BUF_SIZE
);
264 /* Poison - if everything goes fine, hardware will overwrite it */
265 rx
= (struct bgmac_rx_header
*)skb
->data
;
266 rx
->len
= cpu_to_le16(0xdead);
267 rx
->flags
= cpu_to_le16(0xbeef);
269 /* Map skb for the DMA */
270 dma_addr
= dma_map_single(dma_dev
, skb
->data
,
271 BGMAC_RX_BUF_SIZE
, DMA_FROM_DEVICE
);
272 if (dma_mapping_error(dma_dev
, dma_addr
)) {
273 bgmac_err(bgmac
, "DMA mapping error\n");
278 /* Update the slot */
280 slot
->dma_addr
= dma_addr
;
282 if (slot
->dma_addr
& 0xC0000000)
283 bgmac_warn(bgmac
, "DMA address using 0xC0000000 bit(s), it may need translation trick\n");
288 static void bgmac_dma_rx_setup_desc(struct bgmac
*bgmac
,
289 struct bgmac_dma_ring
*ring
, int desc_idx
)
291 struct bgmac_dma_desc
*dma_desc
= ring
->cpu_base
+ desc_idx
;
292 u32 ctl0
= 0, ctl1
= 0;
294 if (desc_idx
== ring
->num_slots
- 1)
295 ctl0
|= BGMAC_DESC_CTL0_EOT
;
296 ctl1
|= BGMAC_RX_BUF_SIZE
& BGMAC_DESC_CTL1_LEN
;
297 /* Is there any BGMAC device that requires extension? */
298 /* ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT) &
299 * B43_DMA64_DCTL1_ADDREXT_MASK;
302 dma_desc
->addr_low
= cpu_to_le32(lower_32_bits(ring
->slots
[desc_idx
].dma_addr
));
303 dma_desc
->addr_high
= cpu_to_le32(upper_32_bits(ring
->slots
[desc_idx
].dma_addr
));
304 dma_desc
->ctl0
= cpu_to_le32(ctl0
);
305 dma_desc
->ctl1
= cpu_to_le32(ctl1
);
308 static int bgmac_dma_rx_read(struct bgmac
*bgmac
, struct bgmac_dma_ring
*ring
,
314 end_slot
= bgmac_read(bgmac
, ring
->mmio_base
+ BGMAC_DMA_RX_STATUS
);
315 end_slot
&= BGMAC_DMA_RX_STATDPTR
;
316 end_slot
-= ring
->index_base
;
317 end_slot
&= BGMAC_DMA_RX_STATDPTR
;
318 end_slot
/= sizeof(struct bgmac_dma_desc
);
320 ring
->end
= end_slot
;
322 while (ring
->start
!= ring
->end
) {
323 struct device
*dma_dev
= bgmac
->core
->dma_dev
;
324 struct bgmac_slot_info
*slot
= &ring
->slots
[ring
->start
];
325 struct sk_buff
*skb
= slot
->skb
;
326 struct bgmac_rx_header
*rx
;
329 /* Unmap buffer to make it accessible to the CPU */
330 dma_sync_single_for_cpu(dma_dev
, slot
->dma_addr
,
331 BGMAC_RX_BUF_SIZE
, DMA_FROM_DEVICE
);
333 /* Get info from the header */
334 rx
= (struct bgmac_rx_header
*)skb
->data
;
335 len
= le16_to_cpu(rx
->len
);
336 flags
= le16_to_cpu(rx
->flags
);
339 dma_addr_t old_dma_addr
= slot
->dma_addr
;
342 /* Check for poison and drop or pass the packet */
343 if (len
== 0xdead && flags
== 0xbeef) {
344 bgmac_err(bgmac
, "Found poisoned packet at slot %d, DMA issue!\n",
346 dma_sync_single_for_device(dma_dev
,
356 /* Prepare new skb as replacement */
357 err
= bgmac_dma_rx_skb_for_slot(bgmac
, slot
);
359 /* Poison the old skb */
360 rx
->len
= cpu_to_le16(0xdead);
361 rx
->flags
= cpu_to_le16(0xbeef);
363 dma_sync_single_for_device(dma_dev
,
369 bgmac_dma_rx_setup_desc(bgmac
, ring
, ring
->start
);
371 /* Unmap old skb, we'll pass it to the netfif */
372 dma_unmap_single(dma_dev
, old_dma_addr
,
373 BGMAC_RX_BUF_SIZE
, DMA_FROM_DEVICE
);
375 skb_put(skb
, BGMAC_RX_FRAME_OFFSET
+ len
);
376 skb_pull(skb
, BGMAC_RX_FRAME_OFFSET
);
378 skb_checksum_none_assert(skb
);
379 skb
->protocol
= eth_type_trans(skb
, bgmac
->net_dev
);
380 netif_receive_skb(skb
);
384 if (++ring
->start
>= BGMAC_RX_RING_SLOTS
)
387 if (handled
>= weight
) /* Should never be greater */
394 /* Does ring support unaligned addressing? */
395 static bool bgmac_dma_unaligned(struct bgmac
*bgmac
,
396 struct bgmac_dma_ring
*ring
,
397 enum bgmac_dma_ring_type ring_type
)
400 case BGMAC_DMA_RING_TX
:
401 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_RINGLO
,
403 if (bgmac_read(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_RINGLO
))
406 case BGMAC_DMA_RING_RX
:
407 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_RX_RINGLO
,
409 if (bgmac_read(bgmac
, ring
->mmio_base
+ BGMAC_DMA_RX_RINGLO
))
416 static void bgmac_dma_ring_free(struct bgmac
*bgmac
,
417 struct bgmac_dma_ring
*ring
)
419 struct device
*dma_dev
= bgmac
->core
->dma_dev
;
420 struct bgmac_slot_info
*slot
;
424 for (i
= 0; i
< ring
->num_slots
; i
++) {
425 slot
= &ring
->slots
[i
];
428 dma_unmap_single(dma_dev
, slot
->dma_addr
,
429 slot
->skb
->len
, DMA_TO_DEVICE
);
430 dev_kfree_skb(slot
->skb
);
434 if (ring
->cpu_base
) {
435 /* Free ring of descriptors */
436 size
= ring
->num_slots
* sizeof(struct bgmac_dma_desc
);
437 dma_free_coherent(dma_dev
, size
, ring
->cpu_base
,
442 static void bgmac_dma_free(struct bgmac
*bgmac
)
446 for (i
= 0; i
< BGMAC_MAX_TX_RINGS
; i
++)
447 bgmac_dma_ring_free(bgmac
, &bgmac
->tx_ring
[i
]);
448 for (i
= 0; i
< BGMAC_MAX_RX_RINGS
; i
++)
449 bgmac_dma_ring_free(bgmac
, &bgmac
->rx_ring
[i
]);
452 static int bgmac_dma_alloc(struct bgmac
*bgmac
)
454 struct device
*dma_dev
= bgmac
->core
->dma_dev
;
455 struct bgmac_dma_ring
*ring
;
456 static const u16 ring_base
[] = { BGMAC_DMA_BASE0
, BGMAC_DMA_BASE1
,
457 BGMAC_DMA_BASE2
, BGMAC_DMA_BASE3
, };
458 int size
; /* ring size: different for Tx and Rx */
462 BUILD_BUG_ON(BGMAC_MAX_TX_RINGS
> ARRAY_SIZE(ring_base
));
463 BUILD_BUG_ON(BGMAC_MAX_RX_RINGS
> ARRAY_SIZE(ring_base
));
465 if (!(bcma_aread32(bgmac
->core
, BCMA_IOST
) & BCMA_IOST_DMA64
)) {
466 bgmac_err(bgmac
, "Core does not report 64-bit DMA\n");
470 for (i
= 0; i
< BGMAC_MAX_TX_RINGS
; i
++) {
471 ring
= &bgmac
->tx_ring
[i
];
472 ring
->num_slots
= BGMAC_TX_RING_SLOTS
;
473 ring
->mmio_base
= ring_base
[i
];
475 /* Alloc ring of descriptors */
476 size
= ring
->num_slots
* sizeof(struct bgmac_dma_desc
);
477 ring
->cpu_base
= dma_zalloc_coherent(dma_dev
, size
,
480 if (!ring
->cpu_base
) {
481 bgmac_err(bgmac
, "Allocation of TX ring 0x%X failed\n",
485 if (ring
->dma_base
& 0xC0000000)
486 bgmac_warn(bgmac
, "DMA address using 0xC0000000 bit(s), it may need translation trick\n");
488 ring
->unaligned
= bgmac_dma_unaligned(bgmac
, ring
,
491 ring
->index_base
= lower_32_bits(ring
->dma_base
);
493 ring
->index_base
= 0;
495 /* No need to alloc TX slots yet */
498 for (i
= 0; i
< BGMAC_MAX_RX_RINGS
; i
++) {
501 ring
= &bgmac
->rx_ring
[i
];
502 ring
->num_slots
= BGMAC_RX_RING_SLOTS
;
503 ring
->mmio_base
= ring_base
[i
];
505 /* Alloc ring of descriptors */
506 size
= ring
->num_slots
* sizeof(struct bgmac_dma_desc
);
507 ring
->cpu_base
= dma_zalloc_coherent(dma_dev
, size
,
510 if (!ring
->cpu_base
) {
511 bgmac_err(bgmac
, "Allocation of RX ring 0x%X failed\n",
516 if (ring
->dma_base
& 0xC0000000)
517 bgmac_warn(bgmac
, "DMA address using 0xC0000000 bit(s), it may need translation trick\n");
519 ring
->unaligned
= bgmac_dma_unaligned(bgmac
, ring
,
522 ring
->index_base
= lower_32_bits(ring
->dma_base
);
524 ring
->index_base
= 0;
527 for (j
= 0; j
< ring
->num_slots
; j
++) {
528 err
= bgmac_dma_rx_skb_for_slot(bgmac
, &ring
->slots
[j
]);
530 bgmac_err(bgmac
, "Can't allocate skb for slot in RX ring\n");
539 bgmac_dma_free(bgmac
);
543 static void bgmac_dma_init(struct bgmac
*bgmac
)
545 struct bgmac_dma_ring
*ring
;
548 for (i
= 0; i
< BGMAC_MAX_TX_RINGS
; i
++) {
549 ring
= &bgmac
->tx_ring
[i
];
551 if (!ring
->unaligned
)
552 bgmac_dma_tx_enable(bgmac
, ring
);
553 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_RINGLO
,
554 lower_32_bits(ring
->dma_base
));
555 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_RINGHI
,
556 upper_32_bits(ring
->dma_base
));
558 bgmac_dma_tx_enable(bgmac
, ring
);
561 ring
->end
= 0; /* Points the slot that should *not* be read */
564 for (i
= 0; i
< BGMAC_MAX_RX_RINGS
; i
++) {
567 ring
= &bgmac
->rx_ring
[i
];
569 if (!ring
->unaligned
)
570 bgmac_dma_rx_enable(bgmac
, ring
);
571 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_RX_RINGLO
,
572 lower_32_bits(ring
->dma_base
));
573 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_RX_RINGHI
,
574 upper_32_bits(ring
->dma_base
));
576 bgmac_dma_rx_enable(bgmac
, ring
);
578 for (j
= 0; j
< ring
->num_slots
; j
++)
579 bgmac_dma_rx_setup_desc(bgmac
, ring
, j
);
581 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_RX_INDEX
,
583 ring
->num_slots
* sizeof(struct bgmac_dma_desc
));
590 /**************************************************
592 **************************************************/
594 static u16
bgmac_phy_read(struct bgmac
*bgmac
, u8 phyaddr
, u8 reg
)
596 struct bcma_device
*core
;
601 BUILD_BUG_ON(BGMAC_PA_DATA_MASK
!= BCMA_GMAC_CMN_PA_DATA_MASK
);
602 BUILD_BUG_ON(BGMAC_PA_ADDR_MASK
!= BCMA_GMAC_CMN_PA_ADDR_MASK
);
603 BUILD_BUG_ON(BGMAC_PA_ADDR_SHIFT
!= BCMA_GMAC_CMN_PA_ADDR_SHIFT
);
604 BUILD_BUG_ON(BGMAC_PA_REG_MASK
!= BCMA_GMAC_CMN_PA_REG_MASK
);
605 BUILD_BUG_ON(BGMAC_PA_REG_SHIFT
!= BCMA_GMAC_CMN_PA_REG_SHIFT
);
606 BUILD_BUG_ON(BGMAC_PA_WRITE
!= BCMA_GMAC_CMN_PA_WRITE
);
607 BUILD_BUG_ON(BGMAC_PA_START
!= BCMA_GMAC_CMN_PA_START
);
608 BUILD_BUG_ON(BGMAC_PC_EPA_MASK
!= BCMA_GMAC_CMN_PC_EPA_MASK
);
609 BUILD_BUG_ON(BGMAC_PC_MCT_MASK
!= BCMA_GMAC_CMN_PC_MCT_MASK
);
610 BUILD_BUG_ON(BGMAC_PC_MCT_SHIFT
!= BCMA_GMAC_CMN_PC_MCT_SHIFT
);
611 BUILD_BUG_ON(BGMAC_PC_MTE
!= BCMA_GMAC_CMN_PC_MTE
);
613 if (bgmac
->core
->id
.id
== BCMA_CORE_4706_MAC_GBIT
) {
614 core
= bgmac
->core
->bus
->drv_gmac_cmn
.core
;
615 phy_access_addr
= BCMA_GMAC_CMN_PHY_ACCESS
;
616 phy_ctl_addr
= BCMA_GMAC_CMN_PHY_CTL
;
619 phy_access_addr
= BGMAC_PHY_ACCESS
;
620 phy_ctl_addr
= BGMAC_PHY_CNTL
;
623 tmp
= bcma_read32(core
, phy_ctl_addr
);
624 tmp
&= ~BGMAC_PC_EPA_MASK
;
626 bcma_write32(core
, phy_ctl_addr
, tmp
);
628 tmp
= BGMAC_PA_START
;
629 tmp
|= phyaddr
<< BGMAC_PA_ADDR_SHIFT
;
630 tmp
|= reg
<< BGMAC_PA_REG_SHIFT
;
631 bcma_write32(core
, phy_access_addr
, tmp
);
633 if (!bgmac_wait_value(core
, phy_access_addr
, BGMAC_PA_START
, 0, 1000)) {
634 bgmac_err(bgmac
, "Reading PHY %d register 0x%X failed\n",
639 return bcma_read32(core
, phy_access_addr
) & BGMAC_PA_DATA_MASK
;
642 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphywr */
643 static int bgmac_phy_write(struct bgmac
*bgmac
, u8 phyaddr
, u8 reg
, u16 value
)
645 struct bcma_device
*core
;
650 if (bgmac
->core
->id
.id
== BCMA_CORE_4706_MAC_GBIT
) {
651 core
= bgmac
->core
->bus
->drv_gmac_cmn
.core
;
652 phy_access_addr
= BCMA_GMAC_CMN_PHY_ACCESS
;
653 phy_ctl_addr
= BCMA_GMAC_CMN_PHY_CTL
;
656 phy_access_addr
= BGMAC_PHY_ACCESS
;
657 phy_ctl_addr
= BGMAC_PHY_CNTL
;
660 tmp
= bcma_read32(core
, phy_ctl_addr
);
661 tmp
&= ~BGMAC_PC_EPA_MASK
;
663 bcma_write32(core
, phy_ctl_addr
, tmp
);
665 bgmac_write(bgmac
, BGMAC_INT_STATUS
, BGMAC_IS_MDIO
);
666 if (bgmac_read(bgmac
, BGMAC_INT_STATUS
) & BGMAC_IS_MDIO
)
667 bgmac_warn(bgmac
, "Error setting MDIO int\n");
669 tmp
= BGMAC_PA_START
;
670 tmp
|= BGMAC_PA_WRITE
;
671 tmp
|= phyaddr
<< BGMAC_PA_ADDR_SHIFT
;
672 tmp
|= reg
<< BGMAC_PA_REG_SHIFT
;
674 bcma_write32(core
, phy_access_addr
, tmp
);
676 if (!bgmac_wait_value(core
, phy_access_addr
, BGMAC_PA_START
, 0, 1000)) {
677 bgmac_err(bgmac
, "Writing to PHY %d register 0x%X failed\n",
685 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyinit */
686 static void bgmac_phy_init(struct bgmac
*bgmac
)
688 struct bcma_chipinfo
*ci
= &bgmac
->core
->bus
->chipinfo
;
689 struct bcma_drv_cc
*cc
= &bgmac
->core
->bus
->drv_cc
;
692 if (ci
->id
== BCMA_CHIP_ID_BCM5356
) {
693 for (i
= 0; i
< 5; i
++) {
694 bgmac_phy_write(bgmac
, i
, 0x1f, 0x008b);
695 bgmac_phy_write(bgmac
, i
, 0x15, 0x0100);
696 bgmac_phy_write(bgmac
, i
, 0x1f, 0x000f);
697 bgmac_phy_write(bgmac
, i
, 0x12, 0x2aaa);
698 bgmac_phy_write(bgmac
, i
, 0x1f, 0x000b);
701 if ((ci
->id
== BCMA_CHIP_ID_BCM5357
&& ci
->pkg
!= 10) ||
702 (ci
->id
== BCMA_CHIP_ID_BCM4749
&& ci
->pkg
!= 10) ||
703 (ci
->id
== BCMA_CHIP_ID_BCM53572
&& ci
->pkg
!= 9)) {
704 bcma_chipco_chipctl_maskset(cc
, 2, ~0xc0000000, 0);
705 bcma_chipco_chipctl_maskset(cc
, 4, ~0x80000000, 0);
706 for (i
= 0; i
< 5; i
++) {
707 bgmac_phy_write(bgmac
, i
, 0x1f, 0x000f);
708 bgmac_phy_write(bgmac
, i
, 0x16, 0x5284);
709 bgmac_phy_write(bgmac
, i
, 0x1f, 0x000b);
710 bgmac_phy_write(bgmac
, i
, 0x17, 0x0010);
711 bgmac_phy_write(bgmac
, i
, 0x1f, 0x000f);
712 bgmac_phy_write(bgmac
, i
, 0x16, 0x5296);
713 bgmac_phy_write(bgmac
, i
, 0x17, 0x1073);
714 bgmac_phy_write(bgmac
, i
, 0x17, 0x9073);
715 bgmac_phy_write(bgmac
, i
, 0x16, 0x52b6);
716 bgmac_phy_write(bgmac
, i
, 0x17, 0x9273);
717 bgmac_phy_write(bgmac
, i
, 0x1f, 0x000b);
722 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyreset */
723 static void bgmac_phy_reset(struct bgmac
*bgmac
)
725 if (bgmac
->phyaddr
== BGMAC_PHY_NOREGS
)
728 bgmac_phy_write(bgmac
, bgmac
->phyaddr
, BGMAC_PHY_CTL
,
729 BGMAC_PHY_CTL_RESET
);
731 if (bgmac_phy_read(bgmac
, bgmac
->phyaddr
, BGMAC_PHY_CTL
) &
733 bgmac_err(bgmac
, "PHY reset failed\n");
734 bgmac_phy_init(bgmac
);
737 /**************************************************
739 **************************************************/
741 /* TODO: can we just drop @force? Can we don't reset MAC at all if there is
742 * nothing to change? Try if after stabilizng driver.
744 static void bgmac_cmdcfg_maskset(struct bgmac
*bgmac
, u32 mask
, u32 set
,
747 u32 cmdcfg
= bgmac_read(bgmac
, BGMAC_CMDCFG
);
748 u32 new_val
= (cmdcfg
& mask
) | set
;
750 bgmac_set(bgmac
, BGMAC_CMDCFG
, BGMAC_CMDCFG_SR
);
753 if (new_val
!= cmdcfg
|| force
)
754 bgmac_write(bgmac
, BGMAC_CMDCFG
, new_val
);
756 bgmac_mask(bgmac
, BGMAC_CMDCFG
, ~BGMAC_CMDCFG_SR
);
760 static void bgmac_write_mac_address(struct bgmac
*bgmac
, u8
*addr
)
764 tmp
= (addr
[0] << 24) | (addr
[1] << 16) | (addr
[2] << 8) | addr
[3];
765 bgmac_write(bgmac
, BGMAC_MACADDR_HIGH
, tmp
);
766 tmp
= (addr
[4] << 8) | addr
[5];
767 bgmac_write(bgmac
, BGMAC_MACADDR_LOW
, tmp
);
770 static void bgmac_set_rx_mode(struct net_device
*net_dev
)
772 struct bgmac
*bgmac
= netdev_priv(net_dev
);
774 if (net_dev
->flags
& IFF_PROMISC
)
775 bgmac_cmdcfg_maskset(bgmac
, ~0, BGMAC_CMDCFG_PROM
, true);
777 bgmac_cmdcfg_maskset(bgmac
, ~BGMAC_CMDCFG_PROM
, 0, true);
780 #if 0 /* We don't use that regs yet */
781 static void bgmac_chip_stats_update(struct bgmac
*bgmac
)
785 if (bgmac
->core
->id
.id
!= BCMA_CORE_4706_MAC_GBIT
) {
786 for (i
= 0; i
< BGMAC_NUM_MIB_TX_REGS
; i
++)
787 bgmac
->mib_tx_regs
[i
] =
789 BGMAC_TX_GOOD_OCTETS
+ (i
* 4));
790 for (i
= 0; i
< BGMAC_NUM_MIB_RX_REGS
; i
++)
791 bgmac
->mib_rx_regs
[i
] =
793 BGMAC_RX_GOOD_OCTETS
+ (i
* 4));
796 /* TODO: what else? how to handle BCM4706? Specs are needed */
800 static void bgmac_clear_mib(struct bgmac
*bgmac
)
804 if (bgmac
->core
->id
.id
== BCMA_CORE_4706_MAC_GBIT
)
807 bgmac_set(bgmac
, BGMAC_DEV_CTL
, BGMAC_DC_MROR
);
808 for (i
= 0; i
< BGMAC_NUM_MIB_TX_REGS
; i
++)
809 bgmac_read(bgmac
, BGMAC_TX_GOOD_OCTETS
+ (i
* 4));
810 for (i
= 0; i
< BGMAC_NUM_MIB_RX_REGS
; i
++)
811 bgmac_read(bgmac
, BGMAC_RX_GOOD_OCTETS
+ (i
* 4));
814 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_speed */
815 static void bgmac_mac_speed(struct bgmac
*bgmac
)
817 u32 mask
= ~(BGMAC_CMDCFG_ES_MASK
| BGMAC_CMDCFG_HD
);
820 switch (bgmac
->mac_speed
) {
822 set
|= BGMAC_CMDCFG_ES_10
;
825 set
|= BGMAC_CMDCFG_ES_100
;
828 set
|= BGMAC_CMDCFG_ES_1000
;
831 bgmac_err(bgmac
, "Unsupported speed: %d\n", bgmac
->mac_speed
);
834 if (bgmac
->mac_duplex
== DUPLEX_HALF
)
835 set
|= BGMAC_CMDCFG_HD
;
837 bgmac_cmdcfg_maskset(bgmac
, mask
, set
, true);
840 static void bgmac_miiconfig(struct bgmac
*bgmac
)
842 u8 imode
= (bgmac_read(bgmac
, BGMAC_DEV_STATUS
) & BGMAC_DS_MM_MASK
) >>
844 if (imode
== 0 || imode
== 1) {
845 bgmac
->mac_speed
= SPEED_100
;
846 bgmac
->mac_duplex
= DUPLEX_FULL
;
847 bgmac_mac_speed(bgmac
);
851 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipreset */
852 static void bgmac_chip_reset(struct bgmac
*bgmac
)
854 struct bcma_device
*core
= bgmac
->core
;
855 struct bcma_bus
*bus
= core
->bus
;
856 struct bcma_chipinfo
*ci
= &bus
->chipinfo
;
861 if (bcma_core_is_enabled(core
)) {
862 if (!bgmac
->stats_grabbed
) {
863 /* bgmac_chip_stats_update(bgmac); */
864 bgmac
->stats_grabbed
= true;
867 for (i
= 0; i
< BGMAC_MAX_TX_RINGS
; i
++)
868 bgmac_dma_tx_reset(bgmac
, &bgmac
->tx_ring
[i
]);
870 bgmac_cmdcfg_maskset(bgmac
, ~0, BGMAC_CMDCFG_ML
, false);
873 for (i
= 0; i
< BGMAC_MAX_RX_RINGS
; i
++)
874 bgmac_dma_rx_reset(bgmac
, &bgmac
->rx_ring
[i
]);
876 /* TODO: Clear software multicast filter list */
879 iost
= bcma_aread32(core
, BCMA_IOST
);
880 if ((ci
->id
== BCMA_CHIP_ID_BCM5357
&& ci
->pkg
== 10) ||
881 (ci
->id
== BCMA_CHIP_ID_BCM4749
&& ci
->pkg
== 10) ||
882 (ci
->id
== BCMA_CHIP_ID_BCM53572
&& ci
->pkg
== 9))
883 iost
&= ~BGMAC_BCMA_IOST_ATTACHED
;
885 if (iost
& BGMAC_BCMA_IOST_ATTACHED
) {
886 flags
= BGMAC_BCMA_IOCTL_SW_CLKEN
;
887 if (!bgmac
->has_robosw
)
888 flags
|= BGMAC_BCMA_IOCTL_SW_RESET
;
891 bcma_core_enable(core
, flags
);
893 if (core
->id
.rev
> 2) {
894 bgmac_set(bgmac
, BCMA_CLKCTLST
, 1 << 8);
895 bgmac_wait_value(bgmac
->core
, BCMA_CLKCTLST
, 1 << 24, 1 << 24,
899 if (ci
->id
== BCMA_CHIP_ID_BCM5357
|| ci
->id
== BCMA_CHIP_ID_BCM4749
||
900 ci
->id
== BCMA_CHIP_ID_BCM53572
) {
901 struct bcma_drv_cc
*cc
= &bgmac
->core
->bus
->drv_cc
;
903 u8 sw_type
= BGMAC_CHIPCTL_1_SW_TYPE_EPHY
|
904 BGMAC_CHIPCTL_1_IF_TYPE_MII
;
907 if (bcm47xx_nvram_getenv("et_swtype", buf
, sizeof(buf
)) > 0) {
908 if (kstrtou8(buf
, 0, &et_swtype
))
909 bgmac_err(bgmac
, "Failed to parse et_swtype (%s)\n",
914 } else if (ci
->id
== BCMA_CHIP_ID_BCM5357
&& ci
->pkg
== 9) {
915 sw_type
= BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII
;
916 } else if ((ci
->id
!= BCMA_CHIP_ID_BCM53572
&& ci
->pkg
== 10) ||
917 (ci
->id
== BCMA_CHIP_ID_BCM53572
&& ci
->pkg
== 9)) {
918 sw_type
= BGMAC_CHIPCTL_1_IF_TYPE_RGMII
|
919 BGMAC_CHIPCTL_1_SW_TYPE_RGMII
;
921 bcma_chipco_chipctl_maskset(cc
, 1,
922 ~(BGMAC_CHIPCTL_1_IF_TYPE_MASK
|
923 BGMAC_CHIPCTL_1_SW_TYPE_MASK
),
927 if (iost
& BGMAC_BCMA_IOST_ATTACHED
&& !bgmac
->has_robosw
)
928 bcma_awrite32(core
, BCMA_IOCTL
,
929 bcma_aread32(core
, BCMA_IOCTL
) &
930 ~BGMAC_BCMA_IOCTL_SW_RESET
);
932 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_reset
933 * Specs don't say about using BGMAC_CMDCFG_SR, but in this routine
934 * BGMAC_CMDCFG is read _after_ putting chip in a reset. So it has to
935 * be keps until taking MAC out of the reset.
937 bgmac_cmdcfg_maskset(bgmac
,
949 BGMAC_CMDCFG_PAD_EN
|
957 bgmac_clear_mib(bgmac
);
958 if (core
->id
.id
== BCMA_CORE_4706_MAC_GBIT
)
959 bcma_maskset32(bgmac
->cmn
, BCMA_GMAC_CMN_PHY_CTL
, ~0,
960 BCMA_GMAC_CMN_PC_MTE
);
962 bgmac_set(bgmac
, BGMAC_PHY_CNTL
, BGMAC_PC_MTE
);
963 bgmac_miiconfig(bgmac
);
964 bgmac_phy_init(bgmac
);
966 netdev_reset_queue(bgmac
->net_dev
);
968 bgmac
->int_status
= 0;
971 static void bgmac_chip_intrs_on(struct bgmac
*bgmac
)
973 bgmac_write(bgmac
, BGMAC_INT_MASK
, bgmac
->int_mask
);
976 static void bgmac_chip_intrs_off(struct bgmac
*bgmac
)
978 bgmac_write(bgmac
, BGMAC_INT_MASK
, 0);
979 bgmac_read(bgmac
, BGMAC_INT_MASK
);
982 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_enable */
983 static void bgmac_enable(struct bgmac
*bgmac
)
985 struct bcma_chipinfo
*ci
= &bgmac
->core
->bus
->chipinfo
;
993 cmdcfg
= bgmac_read(bgmac
, BGMAC_CMDCFG
);
994 bgmac_cmdcfg_maskset(bgmac
, ~(BGMAC_CMDCFG_TE
| BGMAC_CMDCFG_RE
),
995 BGMAC_CMDCFG_SR
, true);
997 cmdcfg
|= BGMAC_CMDCFG_TE
| BGMAC_CMDCFG_RE
;
998 bgmac_write(bgmac
, BGMAC_CMDCFG
, cmdcfg
);
1000 mode
= (bgmac_read(bgmac
, BGMAC_DEV_STATUS
) & BGMAC_DS_MM_MASK
) >>
1002 if (ci
->id
!= BCMA_CHIP_ID_BCM47162
|| mode
!= 0)
1003 bgmac_set(bgmac
, BCMA_CLKCTLST
, BCMA_CLKCTLST_FORCEHT
);
1004 if (ci
->id
== BCMA_CHIP_ID_BCM47162
&& mode
== 2)
1005 bcma_chipco_chipctl_maskset(&bgmac
->core
->bus
->drv_cc
, 1, ~0,
1006 BGMAC_CHIPCTL_1_RXC_DLL_BYPASS
);
1009 case BCMA_CHIP_ID_BCM5357
:
1010 case BCMA_CHIP_ID_BCM4749
:
1011 case BCMA_CHIP_ID_BCM53572
:
1012 case BCMA_CHIP_ID_BCM4716
:
1013 case BCMA_CHIP_ID_BCM47162
:
1014 fl_ctl
= 0x03cb04cb;
1015 if (ci
->id
== BCMA_CHIP_ID_BCM5357
||
1016 ci
->id
== BCMA_CHIP_ID_BCM4749
||
1017 ci
->id
== BCMA_CHIP_ID_BCM53572
)
1019 bgmac_write(bgmac
, BGMAC_FLOW_CTL_THRESH
, fl_ctl
);
1020 bgmac_write(bgmac
, BGMAC_PAUSE_CTL
, 0x27fff);
1024 rxq_ctl
= bgmac_read(bgmac
, BGMAC_RXQ_CTL
);
1025 rxq_ctl
&= ~BGMAC_RXQ_CTL_MDP_MASK
;
1026 bp_clk
= bcma_pmu_get_bus_clock(&bgmac
->core
->bus
->drv_cc
) / 1000000;
1027 mdp
= (bp_clk
* 128 / 1000) - 3;
1028 rxq_ctl
|= (mdp
<< BGMAC_RXQ_CTL_MDP_SHIFT
);
1029 bgmac_write(bgmac
, BGMAC_RXQ_CTL
, rxq_ctl
);
1032 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */
1033 static void bgmac_chip_init(struct bgmac
*bgmac
, bool full_init
)
1035 struct bgmac_dma_ring
*ring
;
1038 /* 1 interrupt per received frame */
1039 bgmac_write(bgmac
, BGMAC_INT_RECV_LAZY
, 1 << BGMAC_IRL_FC_SHIFT
);
1041 /* Enable 802.3x tx flow control (honor received PAUSE frames) */
1042 bgmac_cmdcfg_maskset(bgmac
, ~BGMAC_CMDCFG_RPI
, 0, true);
1044 bgmac_set_rx_mode(bgmac
->net_dev
);
1046 bgmac_write_mac_address(bgmac
, bgmac
->net_dev
->dev_addr
);
1048 if (bgmac
->loopback
)
1049 bgmac_cmdcfg_maskset(bgmac
, ~0, BGMAC_CMDCFG_ML
, false);
1051 bgmac_cmdcfg_maskset(bgmac
, ~BGMAC_CMDCFG_ML
, 0, false);
1053 bgmac_write(bgmac
, BGMAC_RXMAX_LENGTH
, 32 + ETHER_MAX_LEN
);
1056 bgmac_dma_init(bgmac
);
1057 if (1) /* FIXME: is there any case we don't want IRQs? */
1058 bgmac_chip_intrs_on(bgmac
);
1060 for (i
= 0; i
< BGMAC_MAX_RX_RINGS
; i
++) {
1061 ring
= &bgmac
->rx_ring
[i
];
1062 bgmac_dma_rx_enable(bgmac
, ring
);
1066 bgmac_enable(bgmac
);
1069 static irqreturn_t
bgmac_interrupt(int irq
, void *dev_id
)
1071 struct bgmac
*bgmac
= netdev_priv(dev_id
);
1073 u32 int_status
= bgmac_read(bgmac
, BGMAC_INT_STATUS
);
1074 int_status
&= bgmac
->int_mask
;
1080 bgmac_write(bgmac
, BGMAC_INT_STATUS
, int_status
);
1082 /* Disable new interrupts until handling existing ones */
1083 bgmac_chip_intrs_off(bgmac
);
1085 bgmac
->int_status
= int_status
;
1087 napi_schedule(&bgmac
->napi
);
1092 static int bgmac_poll(struct napi_struct
*napi
, int weight
)
1094 struct bgmac
*bgmac
= container_of(napi
, struct bgmac
, napi
);
1095 struct bgmac_dma_ring
*ring
;
1098 if (bgmac
->int_status
& BGMAC_IS_TX0
) {
1099 ring
= &bgmac
->tx_ring
[0];
1100 bgmac_dma_tx_free(bgmac
, ring
);
1101 bgmac
->int_status
&= ~BGMAC_IS_TX0
;
1104 if (bgmac
->int_status
& BGMAC_IS_RX
) {
1105 ring
= &bgmac
->rx_ring
[0];
1106 handled
+= bgmac_dma_rx_read(bgmac
, ring
, weight
);
1107 bgmac
->int_status
&= ~BGMAC_IS_RX
;
1110 if (bgmac
->int_status
) {
1111 bgmac_err(bgmac
, "Unknown IRQs: 0x%08X\n", bgmac
->int_status
);
1112 bgmac
->int_status
= 0;
1115 if (handled
< weight
)
1116 napi_complete(napi
);
1118 bgmac_chip_intrs_on(bgmac
);
1123 /**************************************************
1125 **************************************************/
1127 static int bgmac_open(struct net_device
*net_dev
)
1129 struct bgmac
*bgmac
= netdev_priv(net_dev
);
1132 bgmac_chip_reset(bgmac
);
1133 /* Specs say about reclaiming rings here, but we do that in DMA init */
1134 bgmac_chip_init(bgmac
, true);
1136 err
= request_irq(bgmac
->core
->irq
, bgmac_interrupt
, IRQF_SHARED
,
1137 KBUILD_MODNAME
, net_dev
);
1139 bgmac_err(bgmac
, "IRQ request error: %d!\n", err
);
1142 napi_enable(&bgmac
->napi
);
1144 netif_carrier_on(net_dev
);
1150 static int bgmac_stop(struct net_device
*net_dev
)
1152 struct bgmac
*bgmac
= netdev_priv(net_dev
);
1154 netif_carrier_off(net_dev
);
1156 napi_disable(&bgmac
->napi
);
1157 bgmac_chip_intrs_off(bgmac
);
1158 free_irq(bgmac
->core
->irq
, net_dev
);
1160 bgmac_chip_reset(bgmac
);
1165 static netdev_tx_t
bgmac_start_xmit(struct sk_buff
*skb
,
1166 struct net_device
*net_dev
)
1168 struct bgmac
*bgmac
= netdev_priv(net_dev
);
1169 struct bgmac_dma_ring
*ring
;
1171 /* No QOS support yet */
1172 ring
= &bgmac
->tx_ring
[0];
1173 return bgmac_dma_tx_add(bgmac
, ring
, skb
);
1176 static int bgmac_set_mac_address(struct net_device
*net_dev
, void *addr
)
1178 struct bgmac
*bgmac
= netdev_priv(net_dev
);
1181 ret
= eth_prepare_mac_addr_change(net_dev
, addr
);
1184 bgmac_write_mac_address(bgmac
, (u8
*)addr
);
1185 eth_commit_mac_addr_change(net_dev
, addr
);
1189 static int bgmac_ioctl(struct net_device
*net_dev
, struct ifreq
*ifr
, int cmd
)
1191 struct bgmac
*bgmac
= netdev_priv(net_dev
);
1192 struct mii_ioctl_data
*data
= if_mii(ifr
);
1196 data
->phy_id
= bgmac
->phyaddr
;
1199 if (!netif_running(net_dev
))
1201 data
->val_out
= bgmac_phy_read(bgmac
, data
->phy_id
,
1202 data
->reg_num
& 0x1f);
1205 if (!netif_running(net_dev
))
1207 bgmac_phy_write(bgmac
, data
->phy_id
, data
->reg_num
& 0x1f,
1215 static const struct net_device_ops bgmac_netdev_ops
= {
1216 .ndo_open
= bgmac_open
,
1217 .ndo_stop
= bgmac_stop
,
1218 .ndo_start_xmit
= bgmac_start_xmit
,
1219 .ndo_set_rx_mode
= bgmac_set_rx_mode
,
1220 .ndo_set_mac_address
= bgmac_set_mac_address
,
1221 .ndo_validate_addr
= eth_validate_addr
,
1222 .ndo_do_ioctl
= bgmac_ioctl
,
1225 /**************************************************
1227 **************************************************/
1229 static int bgmac_get_settings(struct net_device
*net_dev
,
1230 struct ethtool_cmd
*cmd
)
1232 struct bgmac
*bgmac
= netdev_priv(net_dev
);
1234 return phy_ethtool_gset(bgmac
->phy_dev
, cmd
);
1237 static int bgmac_set_settings(struct net_device
*net_dev
,
1238 struct ethtool_cmd
*cmd
)
1240 struct bgmac
*bgmac
= netdev_priv(net_dev
);
1242 return phy_ethtool_sset(bgmac
->phy_dev
, cmd
);
1245 static void bgmac_get_drvinfo(struct net_device
*net_dev
,
1246 struct ethtool_drvinfo
*info
)
1248 strlcpy(info
->driver
, KBUILD_MODNAME
, sizeof(info
->driver
));
1249 strlcpy(info
->bus_info
, "BCMA", sizeof(info
->bus_info
));
1252 static const struct ethtool_ops bgmac_ethtool_ops
= {
1253 .get_settings
= bgmac_get_settings
,
1254 .set_settings
= bgmac_set_settings
,
1255 .get_drvinfo
= bgmac_get_drvinfo
,
1258 /**************************************************
1260 **************************************************/
1262 static int bgmac_mii_read(struct mii_bus
*bus
, int mii_id
, int regnum
)
1264 return bgmac_phy_read(bus
->priv
, mii_id
, regnum
);
1267 static int bgmac_mii_write(struct mii_bus
*bus
, int mii_id
, int regnum
,
1270 return bgmac_phy_write(bus
->priv
, mii_id
, regnum
, value
);
1273 static void bgmac_adjust_link(struct net_device
*net_dev
)
1275 struct bgmac
*bgmac
= netdev_priv(net_dev
);
1276 struct phy_device
*phy_dev
= bgmac
->phy_dev
;
1277 bool update
= false;
1279 if (phy_dev
->link
) {
1280 if (phy_dev
->speed
!= bgmac
->mac_speed
) {
1281 bgmac
->mac_speed
= phy_dev
->speed
;
1285 if (phy_dev
->duplex
!= bgmac
->mac_duplex
) {
1286 bgmac
->mac_duplex
= phy_dev
->duplex
;
1292 bgmac_mac_speed(bgmac
);
1293 phy_print_status(phy_dev
);
1297 static int bgmac_mii_register(struct bgmac
*bgmac
)
1299 struct mii_bus
*mii_bus
;
1300 struct phy_device
*phy_dev
;
1301 char bus_id
[MII_BUS_ID_SIZE
+ 3];
1304 mii_bus
= mdiobus_alloc();
1308 mii_bus
->name
= "bgmac mii bus";
1309 sprintf(mii_bus
->id
, "%s-%d-%d", "bgmac", bgmac
->core
->bus
->num
,
1310 bgmac
->core
->core_unit
);
1311 mii_bus
->priv
= bgmac
;
1312 mii_bus
->read
= bgmac_mii_read
;
1313 mii_bus
->write
= bgmac_mii_write
;
1314 mii_bus
->parent
= &bgmac
->core
->dev
;
1315 mii_bus
->phy_mask
= ~(1 << bgmac
->phyaddr
);
1317 mii_bus
->irq
= kmalloc_array(PHY_MAX_ADDR
, sizeof(int), GFP_KERNEL
);
1318 if (!mii_bus
->irq
) {
1322 for (i
= 0; i
< PHY_MAX_ADDR
; i
++)
1323 mii_bus
->irq
[i
] = PHY_POLL
;
1325 err
= mdiobus_register(mii_bus
);
1327 bgmac_err(bgmac
, "Registration of mii bus failed\n");
1331 bgmac
->mii_bus
= mii_bus
;
1333 /* Connect to the PHY */
1334 snprintf(bus_id
, sizeof(bus_id
), PHY_ID_FMT
, mii_bus
->id
,
1336 phy_dev
= phy_connect(bgmac
->net_dev
, bus_id
, &bgmac_adjust_link
,
1337 PHY_INTERFACE_MODE_MII
);
1338 if (IS_ERR(phy_dev
)) {
1339 bgmac_err(bgmac
, "PHY connecton failed\n");
1340 err
= PTR_ERR(phy_dev
);
1341 goto err_unregister_bus
;
1343 bgmac
->phy_dev
= phy_dev
;
1348 mdiobus_unregister(mii_bus
);
1350 kfree(mii_bus
->irq
);
1352 mdiobus_free(mii_bus
);
1356 static void bgmac_mii_unregister(struct bgmac
*bgmac
)
1358 struct mii_bus
*mii_bus
= bgmac
->mii_bus
;
1360 mdiobus_unregister(mii_bus
);
1361 kfree(mii_bus
->irq
);
1362 mdiobus_free(mii_bus
);
1365 /**************************************************
1367 **************************************************/
1369 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipattach */
1370 static int bgmac_probe(struct bcma_device
*core
)
1372 struct net_device
*net_dev
;
1373 struct bgmac
*bgmac
;
1374 struct ssb_sprom
*sprom
= &core
->bus
->sprom
;
1375 u8
*mac
= core
->core_unit
? sprom
->et1mac
: sprom
->et0mac
;
1378 /* We don't support 2nd, 3rd, ... units, SPROM has to be adjusted */
1379 if (core
->core_unit
> 1) {
1380 pr_err("Unsupported core_unit %d\n", core
->core_unit
);
1384 if (!is_valid_ether_addr(mac
)) {
1385 dev_err(&core
->dev
, "Invalid MAC addr: %pM\n", mac
);
1386 eth_random_addr(mac
);
1387 dev_warn(&core
->dev
, "Using random MAC: %pM\n", mac
);
1390 /* Allocation and references */
1391 net_dev
= alloc_etherdev(sizeof(*bgmac
));
1394 net_dev
->netdev_ops
= &bgmac_netdev_ops
;
1395 net_dev
->irq
= core
->irq
;
1396 SET_ETHTOOL_OPS(net_dev
, &bgmac_ethtool_ops
);
1397 bgmac
= netdev_priv(net_dev
);
1398 bgmac
->net_dev
= net_dev
;
1400 bcma_set_drvdata(core
, bgmac
);
1403 memcpy(bgmac
->net_dev
->dev_addr
, mac
, ETH_ALEN
);
1405 /* On BCM4706 we need common core to access PHY */
1406 if (core
->id
.id
== BCMA_CORE_4706_MAC_GBIT
&&
1407 !core
->bus
->drv_gmac_cmn
.core
) {
1408 bgmac_err(bgmac
, "GMAC CMN core not found (required for BCM4706)\n");
1410 goto err_netdev_free
;
1412 bgmac
->cmn
= core
->bus
->drv_gmac_cmn
.core
;
1414 bgmac
->phyaddr
= core
->core_unit
? sprom
->et1phyaddr
:
1416 bgmac
->phyaddr
&= BGMAC_PHY_MASK
;
1417 if (bgmac
->phyaddr
== BGMAC_PHY_MASK
) {
1418 bgmac_err(bgmac
, "No PHY found\n");
1420 goto err_netdev_free
;
1422 bgmac_info(bgmac
, "Found PHY addr: %d%s\n", bgmac
->phyaddr
,
1423 bgmac
->phyaddr
== BGMAC_PHY_NOREGS
? " (NOREGS)" : "");
1425 if (core
->bus
->hosttype
== BCMA_HOSTTYPE_PCI
) {
1426 bgmac_err(bgmac
, "PCI setup not implemented\n");
1428 goto err_netdev_free
;
1431 bgmac_chip_reset(bgmac
);
1433 err
= bgmac_dma_alloc(bgmac
);
1435 bgmac_err(bgmac
, "Unable to alloc memory for DMA\n");
1436 goto err_netdev_free
;
1439 bgmac
->int_mask
= BGMAC_IS_ERRMASK
| BGMAC_IS_RX
| BGMAC_IS_TX_MASK
;
1440 if (bcm47xx_nvram_getenv("et0_no_txint", NULL
, 0) == 0)
1441 bgmac
->int_mask
&= ~BGMAC_IS_TX_MASK
;
1443 /* TODO: reset the external phy. Specs are needed */
1444 bgmac_phy_reset(bgmac
);
1446 bgmac
->has_robosw
= !!(core
->bus
->sprom
.boardflags_lo
&
1447 BGMAC_BFL_ENETROBO
);
1448 if (bgmac
->has_robosw
)
1449 bgmac_warn(bgmac
, "Support for Roboswitch not implemented\n");
1451 if (core
->bus
->sprom
.boardflags_lo
& BGMAC_BFL_ENETADM
)
1452 bgmac_warn(bgmac
, "Support for ADMtek ethernet switch not implemented\n");
1454 err
= bgmac_mii_register(bgmac
);
1456 bgmac_err(bgmac
, "Cannot register MDIO\n");
1461 err
= register_netdev(bgmac
->net_dev
);
1463 bgmac_err(bgmac
, "Cannot register net device\n");
1465 goto err_mii_unregister
;
1468 netif_carrier_off(net_dev
);
1470 netif_napi_add(net_dev
, &bgmac
->napi
, bgmac_poll
, BGMAC_WEIGHT
);
1475 bgmac_mii_unregister(bgmac
);
1477 bgmac_dma_free(bgmac
);
1480 bcma_set_drvdata(core
, NULL
);
1481 free_netdev(net_dev
);
1486 static void bgmac_remove(struct bcma_device
*core
)
1488 struct bgmac
*bgmac
= bcma_get_drvdata(core
);
1490 netif_napi_del(&bgmac
->napi
);
1491 unregister_netdev(bgmac
->net_dev
);
1492 bgmac_mii_unregister(bgmac
);
1493 bgmac_dma_free(bgmac
);
1494 bcma_set_drvdata(core
, NULL
);
1495 free_netdev(bgmac
->net_dev
);
1498 static struct bcma_driver bgmac_bcma_driver
= {
1499 .name
= KBUILD_MODNAME
,
1500 .id_table
= bgmac_bcma_tbl
,
1501 .probe
= bgmac_probe
,
1502 .remove
= bgmac_remove
,
1505 static int __init
bgmac_init(void)
1509 err
= bcma_driver_register(&bgmac_bcma_driver
);
1512 pr_info("Broadcom 47xx GBit MAC driver loaded\n");
1517 static void __exit
bgmac_exit(void)
1519 bcma_driver_unregister(&bgmac_bcma_driver
);
1522 module_init(bgmac_init
)
1523 module_exit(bgmac_exit
)
1525 MODULE_AUTHOR("Rafał Miłecki");
1526 MODULE_LICENSE("GPL");