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[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / broadcom / bgmac.c
1 /*
2 * Driver for (BCM4706)? GBit MAC core on BCMA bus.
3 *
4 * Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com>
5 *
6 * Licensed under the GNU/GPL. See COPYING for details.
7 */
8
9
10 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
11
12 #include <linux/bcma/bcma.h>
13 #include <linux/etherdevice.h>
14 #include <linux/interrupt.h>
15 #include <linux/bcm47xx_nvram.h>
16 #include <linux/phy.h>
17 #include <linux/phy_fixed.h>
18 #include "bgmac.h"
19
20 static bool bgmac_wait_value(struct bgmac *bgmac, u16 reg, u32 mask,
21 u32 value, int timeout)
22 {
23 u32 val;
24 int i;
25
26 for (i = 0; i < timeout / 10; i++) {
27 val = bgmac_read(bgmac, reg);
28 if ((val & mask) == value)
29 return true;
30 udelay(10);
31 }
32 dev_err(bgmac->dev, "Timeout waiting for reg 0x%X\n", reg);
33 return false;
34 }
35
36 /**************************************************
37 * DMA
38 **************************************************/
39
40 static void bgmac_dma_tx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
41 {
42 u32 val;
43 int i;
44
45 if (!ring->mmio_base)
46 return;
47
48 /* Suspend DMA TX ring first.
49 * bgmac_wait_value doesn't support waiting for any of few values, so
50 * implement whole loop here.
51 */
52 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL,
53 BGMAC_DMA_TX_SUSPEND);
54 for (i = 0; i < 10000 / 10; i++) {
55 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
56 val &= BGMAC_DMA_TX_STAT;
57 if (val == BGMAC_DMA_TX_STAT_DISABLED ||
58 val == BGMAC_DMA_TX_STAT_IDLEWAIT ||
59 val == BGMAC_DMA_TX_STAT_STOPPED) {
60 i = 0;
61 break;
62 }
63 udelay(10);
64 }
65 if (i)
66 dev_err(bgmac->dev, "Timeout suspending DMA TX ring 0x%X (BGMAC_DMA_TX_STAT: 0x%08X)\n",
67 ring->mmio_base, val);
68
69 /* Remove SUSPEND bit */
70 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 0);
71 if (!bgmac_wait_value(bgmac,
72 ring->mmio_base + BGMAC_DMA_TX_STATUS,
73 BGMAC_DMA_TX_STAT, BGMAC_DMA_TX_STAT_DISABLED,
74 10000)) {
75 dev_warn(bgmac->dev, "DMA TX ring 0x%X wasn't disabled on time, waiting additional 300us\n",
76 ring->mmio_base);
77 udelay(300);
78 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
79 if ((val & BGMAC_DMA_TX_STAT) != BGMAC_DMA_TX_STAT_DISABLED)
80 dev_err(bgmac->dev, "Reset of DMA TX ring 0x%X failed\n",
81 ring->mmio_base);
82 }
83 }
84
85 static void bgmac_dma_tx_enable(struct bgmac *bgmac,
86 struct bgmac_dma_ring *ring)
87 {
88 u32 ctl;
89
90 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL);
91 if (bgmac->feature_flags & BGMAC_FEAT_TX_MASK_SETUP) {
92 ctl &= ~BGMAC_DMA_TX_BL_MASK;
93 ctl |= BGMAC_DMA_TX_BL_128 << BGMAC_DMA_TX_BL_SHIFT;
94
95 ctl &= ~BGMAC_DMA_TX_MR_MASK;
96 ctl |= BGMAC_DMA_TX_MR_2 << BGMAC_DMA_TX_MR_SHIFT;
97
98 ctl &= ~BGMAC_DMA_TX_PC_MASK;
99 ctl |= BGMAC_DMA_TX_PC_16 << BGMAC_DMA_TX_PC_SHIFT;
100
101 ctl &= ~BGMAC_DMA_TX_PT_MASK;
102 ctl |= BGMAC_DMA_TX_PT_8 << BGMAC_DMA_TX_PT_SHIFT;
103 }
104 ctl |= BGMAC_DMA_TX_ENABLE;
105 ctl |= BGMAC_DMA_TX_PARITY_DISABLE;
106 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl);
107 }
108
109 static void
110 bgmac_dma_tx_add_buf(struct bgmac *bgmac, struct bgmac_dma_ring *ring,
111 int i, int len, u32 ctl0)
112 {
113 struct bgmac_slot_info *slot;
114 struct bgmac_dma_desc *dma_desc;
115 u32 ctl1;
116
117 if (i == BGMAC_TX_RING_SLOTS - 1)
118 ctl0 |= BGMAC_DESC_CTL0_EOT;
119
120 ctl1 = len & BGMAC_DESC_CTL1_LEN;
121
122 slot = &ring->slots[i];
123 dma_desc = &ring->cpu_base[i];
124 dma_desc->addr_low = cpu_to_le32(lower_32_bits(slot->dma_addr));
125 dma_desc->addr_high = cpu_to_le32(upper_32_bits(slot->dma_addr));
126 dma_desc->ctl0 = cpu_to_le32(ctl0);
127 dma_desc->ctl1 = cpu_to_le32(ctl1);
128 }
129
130 static netdev_tx_t bgmac_dma_tx_add(struct bgmac *bgmac,
131 struct bgmac_dma_ring *ring,
132 struct sk_buff *skb)
133 {
134 struct device *dma_dev = bgmac->dma_dev;
135 struct net_device *net_dev = bgmac->net_dev;
136 int index = ring->end % BGMAC_TX_RING_SLOTS;
137 struct bgmac_slot_info *slot = &ring->slots[index];
138 int nr_frags;
139 u32 flags;
140 int i;
141
142 if (skb->len > BGMAC_DESC_CTL1_LEN) {
143 netdev_err(bgmac->net_dev, "Too long skb (%d)\n", skb->len);
144 goto err_drop;
145 }
146
147 if (skb->ip_summed == CHECKSUM_PARTIAL)
148 skb_checksum_help(skb);
149
150 nr_frags = skb_shinfo(skb)->nr_frags;
151
152 /* ring->end - ring->start will return the number of valid slots,
153 * even when ring->end overflows
154 */
155 if (ring->end - ring->start + nr_frags + 1 >= BGMAC_TX_RING_SLOTS) {
156 netdev_err(bgmac->net_dev, "TX ring is full, queue should be stopped!\n");
157 netif_stop_queue(net_dev);
158 return NETDEV_TX_BUSY;
159 }
160
161 slot->dma_addr = dma_map_single(dma_dev, skb->data, skb_headlen(skb),
162 DMA_TO_DEVICE);
163 if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr)))
164 goto err_dma_head;
165
166 flags = BGMAC_DESC_CTL0_SOF;
167 if (!nr_frags)
168 flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC;
169
170 bgmac_dma_tx_add_buf(bgmac, ring, index, skb_headlen(skb), flags);
171 flags = 0;
172
173 for (i = 0; i < nr_frags; i++) {
174 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
175 int len = skb_frag_size(frag);
176
177 index = (index + 1) % BGMAC_TX_RING_SLOTS;
178 slot = &ring->slots[index];
179 slot->dma_addr = skb_frag_dma_map(dma_dev, frag, 0,
180 len, DMA_TO_DEVICE);
181 if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr)))
182 goto err_dma;
183
184 if (i == nr_frags - 1)
185 flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC;
186
187 bgmac_dma_tx_add_buf(bgmac, ring, index, len, flags);
188 }
189
190 slot->skb = skb;
191 ring->end += nr_frags + 1;
192 netdev_sent_queue(net_dev, skb->len);
193
194 wmb();
195
196 /* Increase ring->end to point empty slot. We tell hardware the first
197 * slot it should *not* read.
198 */
199 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_INDEX,
200 ring->index_base +
201 (ring->end % BGMAC_TX_RING_SLOTS) *
202 sizeof(struct bgmac_dma_desc));
203
204 if (ring->end - ring->start >= BGMAC_TX_RING_SLOTS - 8)
205 netif_stop_queue(net_dev);
206
207 return NETDEV_TX_OK;
208
209 err_dma:
210 dma_unmap_single(dma_dev, slot->dma_addr, skb_headlen(skb),
211 DMA_TO_DEVICE);
212
213 while (i-- > 0) {
214 int index = (ring->end + i) % BGMAC_TX_RING_SLOTS;
215 struct bgmac_slot_info *slot = &ring->slots[index];
216 u32 ctl1 = le32_to_cpu(ring->cpu_base[index].ctl1);
217 int len = ctl1 & BGMAC_DESC_CTL1_LEN;
218
219 dma_unmap_page(dma_dev, slot->dma_addr, len, DMA_TO_DEVICE);
220 }
221
222 err_dma_head:
223 netdev_err(bgmac->net_dev, "Mapping error of skb on ring 0x%X\n",
224 ring->mmio_base);
225
226 err_drop:
227 dev_kfree_skb(skb);
228 net_dev->stats.tx_dropped++;
229 net_dev->stats.tx_errors++;
230 return NETDEV_TX_OK;
231 }
232
233 /* Free transmitted packets */
234 static void bgmac_dma_tx_free(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
235 {
236 struct device *dma_dev = bgmac->dma_dev;
237 int empty_slot;
238 bool freed = false;
239 unsigned bytes_compl = 0, pkts_compl = 0;
240
241 /* The last slot that hardware didn't consume yet */
242 empty_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
243 empty_slot &= BGMAC_DMA_TX_STATDPTR;
244 empty_slot -= ring->index_base;
245 empty_slot &= BGMAC_DMA_TX_STATDPTR;
246 empty_slot /= sizeof(struct bgmac_dma_desc);
247
248 while (ring->start != ring->end) {
249 int slot_idx = ring->start % BGMAC_TX_RING_SLOTS;
250 struct bgmac_slot_info *slot = &ring->slots[slot_idx];
251 u32 ctl0, ctl1;
252 int len;
253
254 if (slot_idx == empty_slot)
255 break;
256
257 ctl0 = le32_to_cpu(ring->cpu_base[slot_idx].ctl0);
258 ctl1 = le32_to_cpu(ring->cpu_base[slot_idx].ctl1);
259 len = ctl1 & BGMAC_DESC_CTL1_LEN;
260 if (ctl0 & BGMAC_DESC_CTL0_SOF)
261 /* Unmap no longer used buffer */
262 dma_unmap_single(dma_dev, slot->dma_addr, len,
263 DMA_TO_DEVICE);
264 else
265 dma_unmap_page(dma_dev, slot->dma_addr, len,
266 DMA_TO_DEVICE);
267
268 if (slot->skb) {
269 bgmac->net_dev->stats.tx_bytes += slot->skb->len;
270 bgmac->net_dev->stats.tx_packets++;
271 bytes_compl += slot->skb->len;
272 pkts_compl++;
273
274 /* Free memory! :) */
275 dev_kfree_skb(slot->skb);
276 slot->skb = NULL;
277 }
278
279 slot->dma_addr = 0;
280 ring->start++;
281 freed = true;
282 }
283
284 if (!pkts_compl)
285 return;
286
287 netdev_completed_queue(bgmac->net_dev, pkts_compl, bytes_compl);
288
289 if (netif_queue_stopped(bgmac->net_dev))
290 netif_wake_queue(bgmac->net_dev);
291 }
292
293 static void bgmac_dma_rx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
294 {
295 if (!ring->mmio_base)
296 return;
297
298 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, 0);
299 if (!bgmac_wait_value(bgmac,
300 ring->mmio_base + BGMAC_DMA_RX_STATUS,
301 BGMAC_DMA_RX_STAT, BGMAC_DMA_RX_STAT_DISABLED,
302 10000))
303 dev_err(bgmac->dev, "Reset of ring 0x%X RX failed\n",
304 ring->mmio_base);
305 }
306
307 static void bgmac_dma_rx_enable(struct bgmac *bgmac,
308 struct bgmac_dma_ring *ring)
309 {
310 u32 ctl;
311
312 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL);
313
314 /* preserve ONLY bits 16-17 from current hardware value */
315 ctl &= BGMAC_DMA_RX_ADDREXT_MASK;
316
317 if (bgmac->feature_flags & BGMAC_FEAT_RX_MASK_SETUP) {
318 ctl &= ~BGMAC_DMA_RX_BL_MASK;
319 ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT;
320
321 ctl &= ~BGMAC_DMA_RX_PC_MASK;
322 ctl |= BGMAC_DMA_RX_PC_8 << BGMAC_DMA_RX_PC_SHIFT;
323
324 ctl &= ~BGMAC_DMA_RX_PT_MASK;
325 ctl |= BGMAC_DMA_RX_PT_1 << BGMAC_DMA_RX_PT_SHIFT;
326 }
327 ctl |= BGMAC_DMA_RX_ENABLE;
328 ctl |= BGMAC_DMA_RX_PARITY_DISABLE;
329 ctl |= BGMAC_DMA_RX_OVERFLOW_CONT;
330 ctl |= BGMAC_RX_FRAME_OFFSET << BGMAC_DMA_RX_FRAME_OFFSET_SHIFT;
331 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, ctl);
332 }
333
334 static int bgmac_dma_rx_skb_for_slot(struct bgmac *bgmac,
335 struct bgmac_slot_info *slot)
336 {
337 struct device *dma_dev = bgmac->dma_dev;
338 dma_addr_t dma_addr;
339 struct bgmac_rx_header *rx;
340 void *buf;
341
342 /* Alloc skb */
343 buf = netdev_alloc_frag(BGMAC_RX_ALLOC_SIZE);
344 if (!buf)
345 return -ENOMEM;
346
347 /* Poison - if everything goes fine, hardware will overwrite it */
348 rx = buf + BGMAC_RX_BUF_OFFSET;
349 rx->len = cpu_to_le16(0xdead);
350 rx->flags = cpu_to_le16(0xbeef);
351
352 /* Map skb for the DMA */
353 dma_addr = dma_map_single(dma_dev, buf + BGMAC_RX_BUF_OFFSET,
354 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
355 if (dma_mapping_error(dma_dev, dma_addr)) {
356 netdev_err(bgmac->net_dev, "DMA mapping error\n");
357 put_page(virt_to_head_page(buf));
358 return -ENOMEM;
359 }
360
361 /* Update the slot */
362 slot->buf = buf;
363 slot->dma_addr = dma_addr;
364
365 return 0;
366 }
367
368 static void bgmac_dma_rx_update_index(struct bgmac *bgmac,
369 struct bgmac_dma_ring *ring)
370 {
371 dma_wmb();
372
373 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX,
374 ring->index_base +
375 ring->end * sizeof(struct bgmac_dma_desc));
376 }
377
378 static void bgmac_dma_rx_setup_desc(struct bgmac *bgmac,
379 struct bgmac_dma_ring *ring, int desc_idx)
380 {
381 struct bgmac_dma_desc *dma_desc = ring->cpu_base + desc_idx;
382 u32 ctl0 = 0, ctl1 = 0;
383
384 if (desc_idx == BGMAC_RX_RING_SLOTS - 1)
385 ctl0 |= BGMAC_DESC_CTL0_EOT;
386 ctl1 |= BGMAC_RX_BUF_SIZE & BGMAC_DESC_CTL1_LEN;
387 /* Is there any BGMAC device that requires extension? */
388 /* ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT) &
389 * B43_DMA64_DCTL1_ADDREXT_MASK;
390 */
391
392 dma_desc->addr_low = cpu_to_le32(lower_32_bits(ring->slots[desc_idx].dma_addr));
393 dma_desc->addr_high = cpu_to_le32(upper_32_bits(ring->slots[desc_idx].dma_addr));
394 dma_desc->ctl0 = cpu_to_le32(ctl0);
395 dma_desc->ctl1 = cpu_to_le32(ctl1);
396
397 ring->end = desc_idx;
398 }
399
400 static void bgmac_dma_rx_poison_buf(struct device *dma_dev,
401 struct bgmac_slot_info *slot)
402 {
403 struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET;
404
405 dma_sync_single_for_cpu(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE,
406 DMA_FROM_DEVICE);
407 rx->len = cpu_to_le16(0xdead);
408 rx->flags = cpu_to_le16(0xbeef);
409 dma_sync_single_for_device(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE,
410 DMA_FROM_DEVICE);
411 }
412
413 static int bgmac_dma_rx_read(struct bgmac *bgmac, struct bgmac_dma_ring *ring,
414 int weight)
415 {
416 u32 end_slot;
417 int handled = 0;
418
419 end_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_STATUS);
420 end_slot &= BGMAC_DMA_RX_STATDPTR;
421 end_slot -= ring->index_base;
422 end_slot &= BGMAC_DMA_RX_STATDPTR;
423 end_slot /= sizeof(struct bgmac_dma_desc);
424
425 while (ring->start != end_slot) {
426 struct device *dma_dev = bgmac->dma_dev;
427 struct bgmac_slot_info *slot = &ring->slots[ring->start];
428 struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET;
429 struct sk_buff *skb;
430 void *buf = slot->buf;
431 dma_addr_t dma_addr = slot->dma_addr;
432 u16 len, flags;
433
434 do {
435 /* Prepare new skb as replacement */
436 if (bgmac_dma_rx_skb_for_slot(bgmac, slot)) {
437 bgmac_dma_rx_poison_buf(dma_dev, slot);
438 break;
439 }
440
441 /* Unmap buffer to make it accessible to the CPU */
442 dma_unmap_single(dma_dev, dma_addr,
443 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
444
445 /* Get info from the header */
446 len = le16_to_cpu(rx->len);
447 flags = le16_to_cpu(rx->flags);
448
449 /* Check for poison and drop or pass the packet */
450 if (len == 0xdead && flags == 0xbeef) {
451 netdev_err(bgmac->net_dev, "Found poisoned packet at slot %d, DMA issue!\n",
452 ring->start);
453 put_page(virt_to_head_page(buf));
454 bgmac->net_dev->stats.rx_errors++;
455 break;
456 }
457
458 if (len > BGMAC_RX_ALLOC_SIZE) {
459 netdev_err(bgmac->net_dev, "Found oversized packet at slot %d, DMA issue!\n",
460 ring->start);
461 put_page(virt_to_head_page(buf));
462 bgmac->net_dev->stats.rx_length_errors++;
463 bgmac->net_dev->stats.rx_errors++;
464 break;
465 }
466
467 /* Omit CRC. */
468 len -= ETH_FCS_LEN;
469
470 skb = build_skb(buf, BGMAC_RX_ALLOC_SIZE);
471 if (unlikely(!skb)) {
472 netdev_err(bgmac->net_dev, "build_skb failed\n");
473 put_page(virt_to_head_page(buf));
474 bgmac->net_dev->stats.rx_errors++;
475 break;
476 }
477 skb_put(skb, BGMAC_RX_FRAME_OFFSET +
478 BGMAC_RX_BUF_OFFSET + len);
479 skb_pull(skb, BGMAC_RX_FRAME_OFFSET +
480 BGMAC_RX_BUF_OFFSET);
481
482 skb_checksum_none_assert(skb);
483 skb->protocol = eth_type_trans(skb, bgmac->net_dev);
484 bgmac->net_dev->stats.rx_bytes += len;
485 bgmac->net_dev->stats.rx_packets++;
486 napi_gro_receive(&bgmac->napi, skb);
487 handled++;
488 } while (0);
489
490 bgmac_dma_rx_setup_desc(bgmac, ring, ring->start);
491
492 if (++ring->start >= BGMAC_RX_RING_SLOTS)
493 ring->start = 0;
494
495 if (handled >= weight) /* Should never be greater */
496 break;
497 }
498
499 bgmac_dma_rx_update_index(bgmac, ring);
500
501 return handled;
502 }
503
504 /* Does ring support unaligned addressing? */
505 static bool bgmac_dma_unaligned(struct bgmac *bgmac,
506 struct bgmac_dma_ring *ring,
507 enum bgmac_dma_ring_type ring_type)
508 {
509 switch (ring_type) {
510 case BGMAC_DMA_RING_TX:
511 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
512 0xff0);
513 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO))
514 return true;
515 break;
516 case BGMAC_DMA_RING_RX:
517 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
518 0xff0);
519 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO))
520 return true;
521 break;
522 }
523 return false;
524 }
525
526 static void bgmac_dma_tx_ring_free(struct bgmac *bgmac,
527 struct bgmac_dma_ring *ring)
528 {
529 struct device *dma_dev = bgmac->dma_dev;
530 struct bgmac_dma_desc *dma_desc = ring->cpu_base;
531 struct bgmac_slot_info *slot;
532 int i;
533
534 for (i = 0; i < BGMAC_TX_RING_SLOTS; i++) {
535 int len = dma_desc[i].ctl1 & BGMAC_DESC_CTL1_LEN;
536
537 slot = &ring->slots[i];
538 dev_kfree_skb(slot->skb);
539
540 if (!slot->dma_addr)
541 continue;
542
543 if (slot->skb)
544 dma_unmap_single(dma_dev, slot->dma_addr,
545 len, DMA_TO_DEVICE);
546 else
547 dma_unmap_page(dma_dev, slot->dma_addr,
548 len, DMA_TO_DEVICE);
549 }
550 }
551
552 static void bgmac_dma_rx_ring_free(struct bgmac *bgmac,
553 struct bgmac_dma_ring *ring)
554 {
555 struct device *dma_dev = bgmac->dma_dev;
556 struct bgmac_slot_info *slot;
557 int i;
558
559 for (i = 0; i < BGMAC_RX_RING_SLOTS; i++) {
560 slot = &ring->slots[i];
561 if (!slot->dma_addr)
562 continue;
563
564 dma_unmap_single(dma_dev, slot->dma_addr,
565 BGMAC_RX_BUF_SIZE,
566 DMA_FROM_DEVICE);
567 put_page(virt_to_head_page(slot->buf));
568 slot->dma_addr = 0;
569 }
570 }
571
572 static void bgmac_dma_ring_desc_free(struct bgmac *bgmac,
573 struct bgmac_dma_ring *ring,
574 int num_slots)
575 {
576 struct device *dma_dev = bgmac->dma_dev;
577 int size;
578
579 if (!ring->cpu_base)
580 return;
581
582 /* Free ring of descriptors */
583 size = num_slots * sizeof(struct bgmac_dma_desc);
584 dma_free_coherent(dma_dev, size, ring->cpu_base,
585 ring->dma_base);
586 }
587
588 static void bgmac_dma_cleanup(struct bgmac *bgmac)
589 {
590 int i;
591
592 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
593 bgmac_dma_tx_ring_free(bgmac, &bgmac->tx_ring[i]);
594
595 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
596 bgmac_dma_rx_ring_free(bgmac, &bgmac->rx_ring[i]);
597 }
598
599 static void bgmac_dma_free(struct bgmac *bgmac)
600 {
601 int i;
602
603 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
604 bgmac_dma_ring_desc_free(bgmac, &bgmac->tx_ring[i],
605 BGMAC_TX_RING_SLOTS);
606
607 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
608 bgmac_dma_ring_desc_free(bgmac, &bgmac->rx_ring[i],
609 BGMAC_RX_RING_SLOTS);
610 }
611
612 static int bgmac_dma_alloc(struct bgmac *bgmac)
613 {
614 struct device *dma_dev = bgmac->dma_dev;
615 struct bgmac_dma_ring *ring;
616 static const u16 ring_base[] = { BGMAC_DMA_BASE0, BGMAC_DMA_BASE1,
617 BGMAC_DMA_BASE2, BGMAC_DMA_BASE3, };
618 int size; /* ring size: different for Tx and Rx */
619 int err;
620 int i;
621
622 BUILD_BUG_ON(BGMAC_MAX_TX_RINGS > ARRAY_SIZE(ring_base));
623 BUILD_BUG_ON(BGMAC_MAX_RX_RINGS > ARRAY_SIZE(ring_base));
624
625 if (!(bgmac_idm_read(bgmac, BCMA_IOST) & BCMA_IOST_DMA64)) {
626 dev_err(bgmac->dev, "Core does not report 64-bit DMA\n");
627 return -ENOTSUPP;
628 }
629
630 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
631 ring = &bgmac->tx_ring[i];
632 ring->mmio_base = ring_base[i];
633
634 /* Alloc ring of descriptors */
635 size = BGMAC_TX_RING_SLOTS * sizeof(struct bgmac_dma_desc);
636 ring->cpu_base = dma_zalloc_coherent(dma_dev, size,
637 &ring->dma_base,
638 GFP_KERNEL);
639 if (!ring->cpu_base) {
640 dev_err(bgmac->dev, "Allocation of TX ring 0x%X failed\n",
641 ring->mmio_base);
642 goto err_dma_free;
643 }
644
645 ring->unaligned = bgmac_dma_unaligned(bgmac, ring,
646 BGMAC_DMA_RING_TX);
647 if (ring->unaligned)
648 ring->index_base = lower_32_bits(ring->dma_base);
649 else
650 ring->index_base = 0;
651
652 /* No need to alloc TX slots yet */
653 }
654
655 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
656 ring = &bgmac->rx_ring[i];
657 ring->mmio_base = ring_base[i];
658
659 /* Alloc ring of descriptors */
660 size = BGMAC_RX_RING_SLOTS * sizeof(struct bgmac_dma_desc);
661 ring->cpu_base = dma_zalloc_coherent(dma_dev, size,
662 &ring->dma_base,
663 GFP_KERNEL);
664 if (!ring->cpu_base) {
665 dev_err(bgmac->dev, "Allocation of RX ring 0x%X failed\n",
666 ring->mmio_base);
667 err = -ENOMEM;
668 goto err_dma_free;
669 }
670
671 ring->unaligned = bgmac_dma_unaligned(bgmac, ring,
672 BGMAC_DMA_RING_RX);
673 if (ring->unaligned)
674 ring->index_base = lower_32_bits(ring->dma_base);
675 else
676 ring->index_base = 0;
677 }
678
679 return 0;
680
681 err_dma_free:
682 bgmac_dma_free(bgmac);
683 return -ENOMEM;
684 }
685
686 static int bgmac_dma_init(struct bgmac *bgmac)
687 {
688 struct bgmac_dma_ring *ring;
689 int i, err;
690
691 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
692 ring = &bgmac->tx_ring[i];
693
694 if (!ring->unaligned)
695 bgmac_dma_tx_enable(bgmac, ring);
696 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
697 lower_32_bits(ring->dma_base));
698 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGHI,
699 upper_32_bits(ring->dma_base));
700 if (ring->unaligned)
701 bgmac_dma_tx_enable(bgmac, ring);
702
703 ring->start = 0;
704 ring->end = 0; /* Points the slot that should *not* be read */
705 }
706
707 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
708 int j;
709
710 ring = &bgmac->rx_ring[i];
711
712 if (!ring->unaligned)
713 bgmac_dma_rx_enable(bgmac, ring);
714 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
715 lower_32_bits(ring->dma_base));
716 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGHI,
717 upper_32_bits(ring->dma_base));
718 if (ring->unaligned)
719 bgmac_dma_rx_enable(bgmac, ring);
720
721 ring->start = 0;
722 ring->end = 0;
723 for (j = 0; j < BGMAC_RX_RING_SLOTS; j++) {
724 err = bgmac_dma_rx_skb_for_slot(bgmac, &ring->slots[j]);
725 if (err)
726 goto error;
727
728 bgmac_dma_rx_setup_desc(bgmac, ring, j);
729 }
730
731 bgmac_dma_rx_update_index(bgmac, ring);
732 }
733
734 return 0;
735
736 error:
737 bgmac_dma_cleanup(bgmac);
738 return err;
739 }
740
741
742 /**************************************************
743 * Chip ops
744 **************************************************/
745
746 /* TODO: can we just drop @force? Can we don't reset MAC at all if there is
747 * nothing to change? Try if after stabilizng driver.
748 */
749 static void bgmac_cmdcfg_maskset(struct bgmac *bgmac, u32 mask, u32 set,
750 bool force)
751 {
752 u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
753 u32 new_val = (cmdcfg & mask) | set;
754 u32 cmdcfg_sr;
755
756 if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4)
757 cmdcfg_sr = BGMAC_CMDCFG_SR_REV4;
758 else
759 cmdcfg_sr = BGMAC_CMDCFG_SR_REV0;
760
761 bgmac_set(bgmac, BGMAC_CMDCFG, cmdcfg_sr);
762 udelay(2);
763
764 if (new_val != cmdcfg || force)
765 bgmac_write(bgmac, BGMAC_CMDCFG, new_val);
766
767 bgmac_mask(bgmac, BGMAC_CMDCFG, ~cmdcfg_sr);
768 udelay(2);
769 }
770
771 static void bgmac_write_mac_address(struct bgmac *bgmac, u8 *addr)
772 {
773 u32 tmp;
774
775 tmp = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
776 bgmac_write(bgmac, BGMAC_MACADDR_HIGH, tmp);
777 tmp = (addr[4] << 8) | addr[5];
778 bgmac_write(bgmac, BGMAC_MACADDR_LOW, tmp);
779 }
780
781 static void bgmac_set_rx_mode(struct net_device *net_dev)
782 {
783 struct bgmac *bgmac = netdev_priv(net_dev);
784
785 if (net_dev->flags & IFF_PROMISC)
786 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_PROM, true);
787 else
788 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_PROM, 0, true);
789 }
790
791 #if 0 /* We don't use that regs yet */
792 static void bgmac_chip_stats_update(struct bgmac *bgmac)
793 {
794 int i;
795
796 if (!(bgmac->feature_flags & BGMAC_FEAT_NO_CLR_MIB)) {
797 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
798 bgmac->mib_tx_regs[i] =
799 bgmac_read(bgmac,
800 BGMAC_TX_GOOD_OCTETS + (i * 4));
801 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++)
802 bgmac->mib_rx_regs[i] =
803 bgmac_read(bgmac,
804 BGMAC_RX_GOOD_OCTETS + (i * 4));
805 }
806
807 /* TODO: what else? how to handle BCM4706? Specs are needed */
808 }
809 #endif
810
811 static void bgmac_clear_mib(struct bgmac *bgmac)
812 {
813 int i;
814
815 if (bgmac->feature_flags & BGMAC_FEAT_NO_CLR_MIB)
816 return;
817
818 bgmac_set(bgmac, BGMAC_DEV_CTL, BGMAC_DC_MROR);
819 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
820 bgmac_read(bgmac, BGMAC_TX_GOOD_OCTETS + (i * 4));
821 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++)
822 bgmac_read(bgmac, BGMAC_RX_GOOD_OCTETS + (i * 4));
823 }
824
825 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_speed */
826 static void bgmac_mac_speed(struct bgmac *bgmac)
827 {
828 u32 mask = ~(BGMAC_CMDCFG_ES_MASK | BGMAC_CMDCFG_HD);
829 u32 set = 0;
830
831 switch (bgmac->mac_speed) {
832 case SPEED_10:
833 set |= BGMAC_CMDCFG_ES_10;
834 break;
835 case SPEED_100:
836 set |= BGMAC_CMDCFG_ES_100;
837 break;
838 case SPEED_1000:
839 set |= BGMAC_CMDCFG_ES_1000;
840 break;
841 case SPEED_2500:
842 set |= BGMAC_CMDCFG_ES_2500;
843 break;
844 default:
845 dev_err(bgmac->dev, "Unsupported speed: %d\n",
846 bgmac->mac_speed);
847 }
848
849 if (bgmac->mac_duplex == DUPLEX_HALF)
850 set |= BGMAC_CMDCFG_HD;
851
852 bgmac_cmdcfg_maskset(bgmac, mask, set, true);
853 }
854
855 static void bgmac_miiconfig(struct bgmac *bgmac)
856 {
857 if (bgmac->feature_flags & BGMAC_FEAT_FORCE_SPEED_2500) {
858 bgmac_idm_write(bgmac, BCMA_IOCTL,
859 bgmac_idm_read(bgmac, BCMA_IOCTL) | 0x40 |
860 BGMAC_BCMA_IOCTL_SW_CLKEN);
861 bgmac->mac_speed = SPEED_2500;
862 bgmac->mac_duplex = DUPLEX_FULL;
863 bgmac_mac_speed(bgmac);
864 } else {
865 u8 imode;
866
867 imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) &
868 BGMAC_DS_MM_MASK) >> BGMAC_DS_MM_SHIFT;
869 if (imode == 0 || imode == 1) {
870 bgmac->mac_speed = SPEED_100;
871 bgmac->mac_duplex = DUPLEX_FULL;
872 bgmac_mac_speed(bgmac);
873 }
874 }
875 }
876
877 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipreset */
878 static void bgmac_chip_reset(struct bgmac *bgmac)
879 {
880 u32 cmdcfg_sr;
881 u32 iost;
882 int i;
883
884 if (bgmac_clk_enabled(bgmac)) {
885 if (!bgmac->stats_grabbed) {
886 /* bgmac_chip_stats_update(bgmac); */
887 bgmac->stats_grabbed = true;
888 }
889
890 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
891 bgmac_dma_tx_reset(bgmac, &bgmac->tx_ring[i]);
892
893 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false);
894 udelay(1);
895
896 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
897 bgmac_dma_rx_reset(bgmac, &bgmac->rx_ring[i]);
898
899 /* TODO: Clear software multicast filter list */
900 }
901
902 iost = bgmac_idm_read(bgmac, BCMA_IOST);
903 if (bgmac->feature_flags & BGMAC_FEAT_IOST_ATTACHED)
904 iost &= ~BGMAC_BCMA_IOST_ATTACHED;
905
906 /* 3GMAC: for BCM4707 & BCM47094, only do core reset at bgmac_probe() */
907 if (!(bgmac->feature_flags & BGMAC_FEAT_NO_RESET)) {
908 u32 flags = 0;
909 if (iost & BGMAC_BCMA_IOST_ATTACHED) {
910 flags = BGMAC_BCMA_IOCTL_SW_CLKEN;
911 if (!bgmac->has_robosw)
912 flags |= BGMAC_BCMA_IOCTL_SW_RESET;
913 }
914 bgmac_clk_enable(bgmac, flags);
915 }
916
917 /* Request Misc PLL for corerev > 2 */
918 if (bgmac->feature_flags & BGMAC_FEAT_MISC_PLL_REQ) {
919 bgmac_set(bgmac, BCMA_CLKCTLST,
920 BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ);
921 bgmac_wait_value(bgmac, BCMA_CLKCTLST,
922 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST,
923 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST,
924 1000);
925 }
926
927 if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_PHY) {
928 u8 et_swtype = 0;
929 u8 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHY |
930 BGMAC_CHIPCTL_1_IF_TYPE_MII;
931 char buf[4];
932
933 if (bcm47xx_nvram_getenv("et_swtype", buf, sizeof(buf)) > 0) {
934 if (kstrtou8(buf, 0, &et_swtype))
935 dev_err(bgmac->dev, "Failed to parse et_swtype (%s)\n",
936 buf);
937 et_swtype &= 0x0f;
938 et_swtype <<= 4;
939 sw_type = et_swtype;
940 } else if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_EPHYRMII) {
941 sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RMII |
942 BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII;
943 } else if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_RGMII) {
944 sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RGMII |
945 BGMAC_CHIPCTL_1_SW_TYPE_RGMII;
946 }
947 bgmac_cco_ctl_maskset(bgmac, 1, ~(BGMAC_CHIPCTL_1_IF_TYPE_MASK |
948 BGMAC_CHIPCTL_1_SW_TYPE_MASK),
949 sw_type);
950 } else if (bgmac->feature_flags & BGMAC_FEAT_CC4_IF_SW_TYPE) {
951 u32 sw_type = BGMAC_CHIPCTL_4_IF_TYPE_MII |
952 BGMAC_CHIPCTL_4_SW_TYPE_EPHY;
953 u8 et_swtype = 0;
954 char buf[4];
955
956 if (bcm47xx_nvram_getenv("et_swtype", buf, sizeof(buf)) > 0) {
957 if (kstrtou8(buf, 0, &et_swtype))
958 dev_err(bgmac->dev, "Failed to parse et_swtype (%s)\n",
959 buf);
960 sw_type = (et_swtype & 0x0f) << 12;
961 } else if (bgmac->feature_flags & BGMAC_FEAT_CC4_IF_SW_TYPE_RGMII) {
962 sw_type = BGMAC_CHIPCTL_4_IF_TYPE_RGMII |
963 BGMAC_CHIPCTL_4_SW_TYPE_RGMII;
964 }
965 bgmac_cco_ctl_maskset(bgmac, 4, ~(BGMAC_CHIPCTL_4_IF_TYPE_MASK |
966 BGMAC_CHIPCTL_4_SW_TYPE_MASK),
967 sw_type);
968 } else if (bgmac->feature_flags & BGMAC_FEAT_CC7_IF_TYPE_RGMII) {
969 bgmac_cco_ctl_maskset(bgmac, 7, ~BGMAC_CHIPCTL_7_IF_TYPE_MASK,
970 BGMAC_CHIPCTL_7_IF_TYPE_RGMII);
971 }
972
973 if (iost & BGMAC_BCMA_IOST_ATTACHED && !bgmac->has_robosw)
974 bgmac_idm_write(bgmac, BCMA_IOCTL,
975 bgmac_idm_read(bgmac, BCMA_IOCTL) &
976 ~BGMAC_BCMA_IOCTL_SW_RESET);
977
978 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_reset
979 * Specs don't say about using BGMAC_CMDCFG_SR, but in this routine
980 * BGMAC_CMDCFG is read _after_ putting chip in a reset. So it has to
981 * be keps until taking MAC out of the reset.
982 */
983 if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4)
984 cmdcfg_sr = BGMAC_CMDCFG_SR_REV4;
985 else
986 cmdcfg_sr = BGMAC_CMDCFG_SR_REV0;
987
988 bgmac_cmdcfg_maskset(bgmac,
989 ~(BGMAC_CMDCFG_TE |
990 BGMAC_CMDCFG_RE |
991 BGMAC_CMDCFG_RPI |
992 BGMAC_CMDCFG_TAI |
993 BGMAC_CMDCFG_HD |
994 BGMAC_CMDCFG_ML |
995 BGMAC_CMDCFG_CFE |
996 BGMAC_CMDCFG_RL |
997 BGMAC_CMDCFG_RED |
998 BGMAC_CMDCFG_PE |
999 BGMAC_CMDCFG_TPI |
1000 BGMAC_CMDCFG_PAD_EN |
1001 BGMAC_CMDCFG_PF),
1002 BGMAC_CMDCFG_PROM |
1003 BGMAC_CMDCFG_NLC |
1004 BGMAC_CMDCFG_CFE |
1005 cmdcfg_sr,
1006 false);
1007 bgmac->mac_speed = SPEED_UNKNOWN;
1008 bgmac->mac_duplex = DUPLEX_UNKNOWN;
1009
1010 bgmac_clear_mib(bgmac);
1011 if (bgmac->feature_flags & BGMAC_FEAT_CMN_PHY_CTL)
1012 bgmac_cmn_maskset32(bgmac, BCMA_GMAC_CMN_PHY_CTL, ~0,
1013 BCMA_GMAC_CMN_PC_MTE);
1014 else
1015 bgmac_set(bgmac, BGMAC_PHY_CNTL, BGMAC_PC_MTE);
1016 bgmac_miiconfig(bgmac);
1017 if (bgmac->mii_bus)
1018 bgmac->mii_bus->reset(bgmac->mii_bus);
1019
1020 netdev_reset_queue(bgmac->net_dev);
1021 }
1022
1023 static void bgmac_chip_intrs_on(struct bgmac *bgmac)
1024 {
1025 bgmac_write(bgmac, BGMAC_INT_MASK, bgmac->int_mask);
1026 }
1027
1028 static void bgmac_chip_intrs_off(struct bgmac *bgmac)
1029 {
1030 bgmac_write(bgmac, BGMAC_INT_MASK, 0);
1031 bgmac_read(bgmac, BGMAC_INT_MASK);
1032 }
1033
1034 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_enable */
1035 static void bgmac_enable(struct bgmac *bgmac)
1036 {
1037 u32 cmdcfg_sr;
1038 u32 cmdcfg;
1039 u32 mode;
1040
1041 if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4)
1042 cmdcfg_sr = BGMAC_CMDCFG_SR_REV4;
1043 else
1044 cmdcfg_sr = BGMAC_CMDCFG_SR_REV0;
1045
1046 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
1047 bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE),
1048 cmdcfg_sr, true);
1049 udelay(2);
1050 cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE;
1051 bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg);
1052
1053 mode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >>
1054 BGMAC_DS_MM_SHIFT;
1055 if (bgmac->feature_flags & BGMAC_FEAT_CLKCTLST || mode != 0)
1056 bgmac_set(bgmac, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
1057 if (!(bgmac->feature_flags & BGMAC_FEAT_CLKCTLST) && mode == 2)
1058 bgmac_cco_ctl_maskset(bgmac, 1, ~0,
1059 BGMAC_CHIPCTL_1_RXC_DLL_BYPASS);
1060
1061 if (bgmac->feature_flags & (BGMAC_FEAT_FLW_CTRL1 |
1062 BGMAC_FEAT_FLW_CTRL2)) {
1063 u32 fl_ctl;
1064
1065 if (bgmac->feature_flags & BGMAC_FEAT_FLW_CTRL1)
1066 fl_ctl = 0x2300e1;
1067 else
1068 fl_ctl = 0x03cb04cb;
1069
1070 bgmac_write(bgmac, BGMAC_FLOW_CTL_THRESH, fl_ctl);
1071 bgmac_write(bgmac, BGMAC_PAUSE_CTL, 0x27fff);
1072 }
1073
1074 if (bgmac->feature_flags & BGMAC_FEAT_SET_RXQ_CLK) {
1075 u32 rxq_ctl;
1076 u16 bp_clk;
1077 u8 mdp;
1078
1079 rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL);
1080 rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK;
1081 bp_clk = bgmac_get_bus_clock(bgmac) / 1000000;
1082 mdp = (bp_clk * 128 / 1000) - 3;
1083 rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT);
1084 bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl);
1085 }
1086 }
1087
1088 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */
1089 static void bgmac_chip_init(struct bgmac *bgmac)
1090 {
1091 /* Clear any erroneously pending interrupts */
1092 bgmac_write(bgmac, BGMAC_INT_STATUS, ~0);
1093
1094 /* 1 interrupt per received frame */
1095 bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT);
1096
1097 /* Enable 802.3x tx flow control (honor received PAUSE frames) */
1098 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_RPI, 0, true);
1099
1100 bgmac_set_rx_mode(bgmac->net_dev);
1101
1102 bgmac_write_mac_address(bgmac, bgmac->net_dev->dev_addr);
1103
1104 if (bgmac->loopback)
1105 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false);
1106 else
1107 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_ML, 0, false);
1108
1109 bgmac_write(bgmac, BGMAC_RXMAX_LENGTH, 32 + ETHER_MAX_LEN);
1110
1111 bgmac_chip_intrs_on(bgmac);
1112
1113 bgmac_enable(bgmac);
1114 }
1115
1116 static irqreturn_t bgmac_interrupt(int irq, void *dev_id)
1117 {
1118 struct bgmac *bgmac = netdev_priv(dev_id);
1119
1120 u32 int_status = bgmac_read(bgmac, BGMAC_INT_STATUS);
1121 int_status &= bgmac->int_mask;
1122
1123 if (!int_status)
1124 return IRQ_NONE;
1125
1126 int_status &= ~(BGMAC_IS_TX0 | BGMAC_IS_RX);
1127 if (int_status)
1128 dev_err(bgmac->dev, "Unknown IRQs: 0x%08X\n", int_status);
1129
1130 /* Disable new interrupts until handling existing ones */
1131 bgmac_chip_intrs_off(bgmac);
1132
1133 napi_schedule(&bgmac->napi);
1134
1135 return IRQ_HANDLED;
1136 }
1137
1138 static int bgmac_poll(struct napi_struct *napi, int weight)
1139 {
1140 struct bgmac *bgmac = container_of(napi, struct bgmac, napi);
1141 int handled = 0;
1142
1143 /* Ack */
1144 bgmac_write(bgmac, BGMAC_INT_STATUS, ~0);
1145
1146 bgmac_dma_tx_free(bgmac, &bgmac->tx_ring[0]);
1147 handled += bgmac_dma_rx_read(bgmac, &bgmac->rx_ring[0], weight);
1148
1149 /* Poll again if more events arrived in the meantime */
1150 if (bgmac_read(bgmac, BGMAC_INT_STATUS) & (BGMAC_IS_TX0 | BGMAC_IS_RX))
1151 return weight;
1152
1153 if (handled < weight) {
1154 napi_complete_done(napi, handled);
1155 bgmac_chip_intrs_on(bgmac);
1156 }
1157
1158 return handled;
1159 }
1160
1161 /**************************************************
1162 * net_device_ops
1163 **************************************************/
1164
1165 static int bgmac_open(struct net_device *net_dev)
1166 {
1167 struct bgmac *bgmac = netdev_priv(net_dev);
1168 int err = 0;
1169
1170 bgmac_chip_reset(bgmac);
1171
1172 err = bgmac_dma_init(bgmac);
1173 if (err)
1174 return err;
1175
1176 /* Specs say about reclaiming rings here, but we do that in DMA init */
1177 bgmac_chip_init(bgmac);
1178
1179 err = request_irq(bgmac->irq, bgmac_interrupt, IRQF_SHARED,
1180 KBUILD_MODNAME, net_dev);
1181 if (err < 0) {
1182 dev_err(bgmac->dev, "IRQ request error: %d!\n", err);
1183 bgmac_dma_cleanup(bgmac);
1184 return err;
1185 }
1186 napi_enable(&bgmac->napi);
1187
1188 phy_start(net_dev->phydev);
1189
1190 netif_start_queue(net_dev);
1191
1192 return 0;
1193 }
1194
1195 static int bgmac_stop(struct net_device *net_dev)
1196 {
1197 struct bgmac *bgmac = netdev_priv(net_dev);
1198
1199 netif_carrier_off(net_dev);
1200
1201 phy_stop(net_dev->phydev);
1202
1203 napi_disable(&bgmac->napi);
1204 bgmac_chip_intrs_off(bgmac);
1205 free_irq(bgmac->irq, net_dev);
1206
1207 bgmac_chip_reset(bgmac);
1208 bgmac_dma_cleanup(bgmac);
1209
1210 return 0;
1211 }
1212
1213 static netdev_tx_t bgmac_start_xmit(struct sk_buff *skb,
1214 struct net_device *net_dev)
1215 {
1216 struct bgmac *bgmac = netdev_priv(net_dev);
1217 struct bgmac_dma_ring *ring;
1218
1219 /* No QOS support yet */
1220 ring = &bgmac->tx_ring[0];
1221 return bgmac_dma_tx_add(bgmac, ring, skb);
1222 }
1223
1224 static int bgmac_set_mac_address(struct net_device *net_dev, void *addr)
1225 {
1226 struct bgmac *bgmac = netdev_priv(net_dev);
1227 struct sockaddr *sa = addr;
1228 int ret;
1229
1230 ret = eth_prepare_mac_addr_change(net_dev, addr);
1231 if (ret < 0)
1232 return ret;
1233
1234 ether_addr_copy(net_dev->dev_addr, sa->sa_data);
1235 bgmac_write_mac_address(bgmac, net_dev->dev_addr);
1236
1237 eth_commit_mac_addr_change(net_dev, addr);
1238 return 0;
1239 }
1240
1241 static int bgmac_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
1242 {
1243 if (!netif_running(net_dev))
1244 return -EINVAL;
1245
1246 return phy_mii_ioctl(net_dev->phydev, ifr, cmd);
1247 }
1248
1249 static const struct net_device_ops bgmac_netdev_ops = {
1250 .ndo_open = bgmac_open,
1251 .ndo_stop = bgmac_stop,
1252 .ndo_start_xmit = bgmac_start_xmit,
1253 .ndo_set_rx_mode = bgmac_set_rx_mode,
1254 .ndo_set_mac_address = bgmac_set_mac_address,
1255 .ndo_validate_addr = eth_validate_addr,
1256 .ndo_do_ioctl = bgmac_ioctl,
1257 };
1258
1259 /**************************************************
1260 * ethtool_ops
1261 **************************************************/
1262
1263 struct bgmac_stat {
1264 u8 size;
1265 u32 offset;
1266 const char *name;
1267 };
1268
1269 static struct bgmac_stat bgmac_get_strings_stats[] = {
1270 { 8, BGMAC_TX_GOOD_OCTETS, "tx_good_octets" },
1271 { 4, BGMAC_TX_GOOD_PKTS, "tx_good" },
1272 { 8, BGMAC_TX_OCTETS, "tx_octets" },
1273 { 4, BGMAC_TX_PKTS, "tx_pkts" },
1274 { 4, BGMAC_TX_BROADCAST_PKTS, "tx_broadcast" },
1275 { 4, BGMAC_TX_MULTICAST_PKTS, "tx_multicast" },
1276 { 4, BGMAC_TX_LEN_64, "tx_64" },
1277 { 4, BGMAC_TX_LEN_65_TO_127, "tx_65_127" },
1278 { 4, BGMAC_TX_LEN_128_TO_255, "tx_128_255" },
1279 { 4, BGMAC_TX_LEN_256_TO_511, "tx_256_511" },
1280 { 4, BGMAC_TX_LEN_512_TO_1023, "tx_512_1023" },
1281 { 4, BGMAC_TX_LEN_1024_TO_1522, "tx_1024_1522" },
1282 { 4, BGMAC_TX_LEN_1523_TO_2047, "tx_1523_2047" },
1283 { 4, BGMAC_TX_LEN_2048_TO_4095, "tx_2048_4095" },
1284 { 4, BGMAC_TX_LEN_4096_TO_8191, "tx_4096_8191" },
1285 { 4, BGMAC_TX_LEN_8192_TO_MAX, "tx_8192_max" },
1286 { 4, BGMAC_TX_JABBER_PKTS, "tx_jabber" },
1287 { 4, BGMAC_TX_OVERSIZE_PKTS, "tx_oversize" },
1288 { 4, BGMAC_TX_FRAGMENT_PKTS, "tx_fragment" },
1289 { 4, BGMAC_TX_UNDERRUNS, "tx_underruns" },
1290 { 4, BGMAC_TX_TOTAL_COLS, "tx_total_cols" },
1291 { 4, BGMAC_TX_SINGLE_COLS, "tx_single_cols" },
1292 { 4, BGMAC_TX_MULTIPLE_COLS, "tx_multiple_cols" },
1293 { 4, BGMAC_TX_EXCESSIVE_COLS, "tx_excessive_cols" },
1294 { 4, BGMAC_TX_LATE_COLS, "tx_late_cols" },
1295 { 4, BGMAC_TX_DEFERED, "tx_defered" },
1296 { 4, BGMAC_TX_CARRIER_LOST, "tx_carrier_lost" },
1297 { 4, BGMAC_TX_PAUSE_PKTS, "tx_pause" },
1298 { 4, BGMAC_TX_UNI_PKTS, "tx_unicast" },
1299 { 4, BGMAC_TX_Q0_PKTS, "tx_q0" },
1300 { 8, BGMAC_TX_Q0_OCTETS, "tx_q0_octets" },
1301 { 4, BGMAC_TX_Q1_PKTS, "tx_q1" },
1302 { 8, BGMAC_TX_Q1_OCTETS, "tx_q1_octets" },
1303 { 4, BGMAC_TX_Q2_PKTS, "tx_q2" },
1304 { 8, BGMAC_TX_Q2_OCTETS, "tx_q2_octets" },
1305 { 4, BGMAC_TX_Q3_PKTS, "tx_q3" },
1306 { 8, BGMAC_TX_Q3_OCTETS, "tx_q3_octets" },
1307 { 8, BGMAC_RX_GOOD_OCTETS, "rx_good_octets" },
1308 { 4, BGMAC_RX_GOOD_PKTS, "rx_good" },
1309 { 8, BGMAC_RX_OCTETS, "rx_octets" },
1310 { 4, BGMAC_RX_PKTS, "rx_pkts" },
1311 { 4, BGMAC_RX_BROADCAST_PKTS, "rx_broadcast" },
1312 { 4, BGMAC_RX_MULTICAST_PKTS, "rx_multicast" },
1313 { 4, BGMAC_RX_LEN_64, "rx_64" },
1314 { 4, BGMAC_RX_LEN_65_TO_127, "rx_65_127" },
1315 { 4, BGMAC_RX_LEN_128_TO_255, "rx_128_255" },
1316 { 4, BGMAC_RX_LEN_256_TO_511, "rx_256_511" },
1317 { 4, BGMAC_RX_LEN_512_TO_1023, "rx_512_1023" },
1318 { 4, BGMAC_RX_LEN_1024_TO_1522, "rx_1024_1522" },
1319 { 4, BGMAC_RX_LEN_1523_TO_2047, "rx_1523_2047" },
1320 { 4, BGMAC_RX_LEN_2048_TO_4095, "rx_2048_4095" },
1321 { 4, BGMAC_RX_LEN_4096_TO_8191, "rx_4096_8191" },
1322 { 4, BGMAC_RX_LEN_8192_TO_MAX, "rx_8192_max" },
1323 { 4, BGMAC_RX_JABBER_PKTS, "rx_jabber" },
1324 { 4, BGMAC_RX_OVERSIZE_PKTS, "rx_oversize" },
1325 { 4, BGMAC_RX_FRAGMENT_PKTS, "rx_fragment" },
1326 { 4, BGMAC_RX_MISSED_PKTS, "rx_missed" },
1327 { 4, BGMAC_RX_CRC_ALIGN_ERRS, "rx_crc_align" },
1328 { 4, BGMAC_RX_UNDERSIZE, "rx_undersize" },
1329 { 4, BGMAC_RX_CRC_ERRS, "rx_crc" },
1330 { 4, BGMAC_RX_ALIGN_ERRS, "rx_align" },
1331 { 4, BGMAC_RX_SYMBOL_ERRS, "rx_symbol" },
1332 { 4, BGMAC_RX_PAUSE_PKTS, "rx_pause" },
1333 { 4, BGMAC_RX_NONPAUSE_PKTS, "rx_nonpause" },
1334 { 4, BGMAC_RX_SACHANGES, "rx_sa_changes" },
1335 { 4, BGMAC_RX_UNI_PKTS, "rx_unicast" },
1336 };
1337
1338 #define BGMAC_STATS_LEN ARRAY_SIZE(bgmac_get_strings_stats)
1339
1340 static int bgmac_get_sset_count(struct net_device *dev, int string_set)
1341 {
1342 switch (string_set) {
1343 case ETH_SS_STATS:
1344 return BGMAC_STATS_LEN;
1345 }
1346
1347 return -EOPNOTSUPP;
1348 }
1349
1350 static void bgmac_get_strings(struct net_device *dev, u32 stringset,
1351 u8 *data)
1352 {
1353 int i;
1354
1355 if (stringset != ETH_SS_STATS)
1356 return;
1357
1358 for (i = 0; i < BGMAC_STATS_LEN; i++)
1359 strlcpy(data + i * ETH_GSTRING_LEN,
1360 bgmac_get_strings_stats[i].name, ETH_GSTRING_LEN);
1361 }
1362
1363 static void bgmac_get_ethtool_stats(struct net_device *dev,
1364 struct ethtool_stats *ss, uint64_t *data)
1365 {
1366 struct bgmac *bgmac = netdev_priv(dev);
1367 const struct bgmac_stat *s;
1368 unsigned int i;
1369 u64 val;
1370
1371 if (!netif_running(dev))
1372 return;
1373
1374 for (i = 0; i < BGMAC_STATS_LEN; i++) {
1375 s = &bgmac_get_strings_stats[i];
1376 val = 0;
1377 if (s->size == 8)
1378 val = (u64)bgmac_read(bgmac, s->offset + 4) << 32;
1379 val |= bgmac_read(bgmac, s->offset);
1380 data[i] = val;
1381 }
1382 }
1383
1384 static void bgmac_get_drvinfo(struct net_device *net_dev,
1385 struct ethtool_drvinfo *info)
1386 {
1387 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1388 strlcpy(info->bus_info, "AXI", sizeof(info->bus_info));
1389 }
1390
1391 static const struct ethtool_ops bgmac_ethtool_ops = {
1392 .get_strings = bgmac_get_strings,
1393 .get_sset_count = bgmac_get_sset_count,
1394 .get_ethtool_stats = bgmac_get_ethtool_stats,
1395 .get_drvinfo = bgmac_get_drvinfo,
1396 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1397 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1398 };
1399
1400 /**************************************************
1401 * MII
1402 **************************************************/
1403
1404 void bgmac_adjust_link(struct net_device *net_dev)
1405 {
1406 struct bgmac *bgmac = netdev_priv(net_dev);
1407 struct phy_device *phy_dev = net_dev->phydev;
1408 bool update = false;
1409
1410 if (phy_dev->link) {
1411 if (phy_dev->speed != bgmac->mac_speed) {
1412 bgmac->mac_speed = phy_dev->speed;
1413 update = true;
1414 }
1415
1416 if (phy_dev->duplex != bgmac->mac_duplex) {
1417 bgmac->mac_duplex = phy_dev->duplex;
1418 update = true;
1419 }
1420 }
1421
1422 if (update) {
1423 bgmac_mac_speed(bgmac);
1424 phy_print_status(phy_dev);
1425 }
1426 }
1427 EXPORT_SYMBOL_GPL(bgmac_adjust_link);
1428
1429 int bgmac_phy_connect_direct(struct bgmac *bgmac)
1430 {
1431 struct fixed_phy_status fphy_status = {
1432 .link = 1,
1433 .speed = SPEED_1000,
1434 .duplex = DUPLEX_FULL,
1435 };
1436 struct phy_device *phy_dev;
1437 int err;
1438
1439 phy_dev = fixed_phy_register(PHY_POLL, &fphy_status, -1, NULL);
1440 if (!phy_dev || IS_ERR(phy_dev)) {
1441 dev_err(bgmac->dev, "Failed to register fixed PHY device\n");
1442 return -ENODEV;
1443 }
1444
1445 err = phy_connect_direct(bgmac->net_dev, phy_dev, bgmac_adjust_link,
1446 PHY_INTERFACE_MODE_MII);
1447 if (err) {
1448 dev_err(bgmac->dev, "Connecting PHY failed\n");
1449 return err;
1450 }
1451
1452 return err;
1453 }
1454 EXPORT_SYMBOL_GPL(bgmac_phy_connect_direct);
1455
1456 struct bgmac *bgmac_alloc(struct device *dev)
1457 {
1458 struct net_device *net_dev;
1459 struct bgmac *bgmac;
1460
1461 /* Allocation and references */
1462 net_dev = devm_alloc_etherdev(dev, sizeof(*bgmac));
1463 if (!net_dev)
1464 return NULL;
1465
1466 net_dev->netdev_ops = &bgmac_netdev_ops;
1467 net_dev->ethtool_ops = &bgmac_ethtool_ops;
1468
1469 bgmac = netdev_priv(net_dev);
1470 bgmac->dev = dev;
1471 bgmac->net_dev = net_dev;
1472
1473 return bgmac;
1474 }
1475 EXPORT_SYMBOL_GPL(bgmac_alloc);
1476
1477 int bgmac_enet_probe(struct bgmac *bgmac)
1478 {
1479 struct net_device *net_dev = bgmac->net_dev;
1480 int err;
1481
1482 net_dev->irq = bgmac->irq;
1483 SET_NETDEV_DEV(net_dev, bgmac->dev);
1484 dev_set_drvdata(bgmac->dev, bgmac);
1485
1486 if (!is_valid_ether_addr(net_dev->dev_addr)) {
1487 dev_err(bgmac->dev, "Invalid MAC addr: %pM\n",
1488 net_dev->dev_addr);
1489 eth_hw_addr_random(net_dev);
1490 dev_warn(bgmac->dev, "Using random MAC: %pM\n",
1491 net_dev->dev_addr);
1492 }
1493
1494 /* This (reset &) enable is not preset in specs or reference driver but
1495 * Broadcom does it in arch PCI code when enabling fake PCI device.
1496 */
1497 bgmac_clk_enable(bgmac, 0);
1498
1499 /* This seems to be fixing IRQ by assigning OOB #6 to the core */
1500 if (bgmac->feature_flags & BGMAC_FEAT_IRQ_ID_OOB_6)
1501 bgmac_idm_write(bgmac, BCMA_OOB_SEL_OUT_A30, 0x86);
1502
1503 bgmac_chip_reset(bgmac);
1504
1505 err = bgmac_dma_alloc(bgmac);
1506 if (err) {
1507 dev_err(bgmac->dev, "Unable to alloc memory for DMA\n");
1508 goto err_out;
1509 }
1510
1511 bgmac->int_mask = BGMAC_IS_ERRMASK | BGMAC_IS_RX | BGMAC_IS_TX_MASK;
1512 if (bcm47xx_nvram_getenv("et0_no_txint", NULL, 0) == 0)
1513 bgmac->int_mask &= ~BGMAC_IS_TX_MASK;
1514
1515 netif_napi_add(net_dev, &bgmac->napi, bgmac_poll, BGMAC_WEIGHT);
1516
1517 err = bgmac_phy_connect(bgmac);
1518 if (err) {
1519 dev_err(bgmac->dev, "Cannot connect to phy\n");
1520 goto err_dma_free;
1521 }
1522
1523 net_dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1524 net_dev->hw_features = net_dev->features;
1525 net_dev->vlan_features = net_dev->features;
1526
1527 err = register_netdev(bgmac->net_dev);
1528 if (err) {
1529 dev_err(bgmac->dev, "Cannot register net device\n");
1530 goto err_phy_disconnect;
1531 }
1532
1533 netif_carrier_off(net_dev);
1534
1535 return 0;
1536
1537 err_phy_disconnect:
1538 phy_disconnect(net_dev->phydev);
1539 err_dma_free:
1540 bgmac_dma_free(bgmac);
1541 err_out:
1542
1543 return err;
1544 }
1545 EXPORT_SYMBOL_GPL(bgmac_enet_probe);
1546
1547 void bgmac_enet_remove(struct bgmac *bgmac)
1548 {
1549 unregister_netdev(bgmac->net_dev);
1550 phy_disconnect(bgmac->net_dev->phydev);
1551 netif_napi_del(&bgmac->napi);
1552 bgmac_dma_free(bgmac);
1553 free_netdev(bgmac->net_dev);
1554 }
1555 EXPORT_SYMBOL_GPL(bgmac_enet_remove);
1556
1557 int bgmac_enet_suspend(struct bgmac *bgmac)
1558 {
1559 if (!netif_running(bgmac->net_dev))
1560 return 0;
1561
1562 phy_stop(bgmac->net_dev->phydev);
1563
1564 netif_stop_queue(bgmac->net_dev);
1565
1566 napi_disable(&bgmac->napi);
1567
1568 netif_tx_lock(bgmac->net_dev);
1569 netif_device_detach(bgmac->net_dev);
1570 netif_tx_unlock(bgmac->net_dev);
1571
1572 bgmac_chip_intrs_off(bgmac);
1573 bgmac_chip_reset(bgmac);
1574 bgmac_dma_cleanup(bgmac);
1575
1576 return 0;
1577 }
1578 EXPORT_SYMBOL_GPL(bgmac_enet_suspend);
1579
1580 int bgmac_enet_resume(struct bgmac *bgmac)
1581 {
1582 int rc;
1583
1584 if (!netif_running(bgmac->net_dev))
1585 return 0;
1586
1587 rc = bgmac_dma_init(bgmac);
1588 if (rc)
1589 return rc;
1590
1591 bgmac_chip_init(bgmac);
1592
1593 napi_enable(&bgmac->napi);
1594
1595 netif_tx_lock(bgmac->net_dev);
1596 netif_device_attach(bgmac->net_dev);
1597 netif_tx_unlock(bgmac->net_dev);
1598
1599 netif_start_queue(bgmac->net_dev);
1600
1601 phy_start(bgmac->net_dev->phydev);
1602
1603 return 0;
1604 }
1605 EXPORT_SYMBOL_GPL(bgmac_enet_resume);
1606
1607 MODULE_AUTHOR("Rafał Miłecki");
1608 MODULE_LICENSE("GPL");
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