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Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_cmn.c
1 /* bnx2x_cmn.c: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2013 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
20 #include <linux/etherdevice.h>
21 #include <linux/if_vlan.h>
22 #include <linux/interrupt.h>
23 #include <linux/ip.h>
24 #include <net/tcp.h>
25 #include <net/ipv6.h>
26 #include <net/ip6_checksum.h>
27 #include <linux/prefetch.h>
28 #include "bnx2x_cmn.h"
29 #include "bnx2x_init.h"
30 #include "bnx2x_sp.h"
31
32 /**
33 * bnx2x_move_fp - move content of the fastpath structure.
34 *
35 * @bp: driver handle
36 * @from: source FP index
37 * @to: destination FP index
38 *
39 * Makes sure the contents of the bp->fp[to].napi is kept
40 * intact. This is done by first copying the napi struct from
41 * the target to the source, and then mem copying the entire
42 * source onto the target. Update txdata pointers and related
43 * content.
44 */
45 static inline void bnx2x_move_fp(struct bnx2x *bp, int from, int to)
46 {
47 struct bnx2x_fastpath *from_fp = &bp->fp[from];
48 struct bnx2x_fastpath *to_fp = &bp->fp[to];
49 struct bnx2x_sp_objs *from_sp_objs = &bp->sp_objs[from];
50 struct bnx2x_sp_objs *to_sp_objs = &bp->sp_objs[to];
51 struct bnx2x_fp_stats *from_fp_stats = &bp->fp_stats[from];
52 struct bnx2x_fp_stats *to_fp_stats = &bp->fp_stats[to];
53 int old_max_eth_txqs, new_max_eth_txqs;
54 int old_txdata_index = 0, new_txdata_index = 0;
55
56 /* Copy the NAPI object as it has been already initialized */
57 from_fp->napi = to_fp->napi;
58
59 /* Move bnx2x_fastpath contents */
60 memcpy(to_fp, from_fp, sizeof(*to_fp));
61 to_fp->index = to;
62
63 /* move sp_objs contents as well, as their indices match fp ones */
64 memcpy(to_sp_objs, from_sp_objs, sizeof(*to_sp_objs));
65
66 /* move fp_stats contents as well, as their indices match fp ones */
67 memcpy(to_fp_stats, from_fp_stats, sizeof(*to_fp_stats));
68
69 /* Update txdata pointers in fp and move txdata content accordingly:
70 * Each fp consumes 'max_cos' txdata structures, so the index should be
71 * decremented by max_cos x delta.
72 */
73
74 old_max_eth_txqs = BNX2X_NUM_ETH_QUEUES(bp) * (bp)->max_cos;
75 new_max_eth_txqs = (BNX2X_NUM_ETH_QUEUES(bp) - from + to) *
76 (bp)->max_cos;
77 if (from == FCOE_IDX(bp)) {
78 old_txdata_index = old_max_eth_txqs + FCOE_TXQ_IDX_OFFSET;
79 new_txdata_index = new_max_eth_txqs + FCOE_TXQ_IDX_OFFSET;
80 }
81
82 memcpy(&bp->bnx2x_txq[new_txdata_index],
83 &bp->bnx2x_txq[old_txdata_index],
84 sizeof(struct bnx2x_fp_txdata));
85 to_fp->txdata_ptr[0] = &bp->bnx2x_txq[new_txdata_index];
86 }
87
88 /**
89 * bnx2x_fill_fw_str - Fill buffer with FW version string.
90 *
91 * @bp: driver handle
92 * @buf: character buffer to fill with the fw name
93 * @buf_len: length of the above buffer
94 *
95 */
96 void bnx2x_fill_fw_str(struct bnx2x *bp, char *buf, size_t buf_len)
97 {
98 if (IS_PF(bp)) {
99 u8 phy_fw_ver[PHY_FW_VER_LEN];
100
101 phy_fw_ver[0] = '\0';
102 bnx2x_get_ext_phy_fw_version(&bp->link_params,
103 phy_fw_ver, PHY_FW_VER_LEN);
104 strlcpy(buf, bp->fw_ver, buf_len);
105 snprintf(buf + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver),
106 "bc %d.%d.%d%s%s",
107 (bp->common.bc_ver & 0xff0000) >> 16,
108 (bp->common.bc_ver & 0xff00) >> 8,
109 (bp->common.bc_ver & 0xff),
110 ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver);
111 } else {
112 bnx2x_vf_fill_fw_str(bp, buf, buf_len);
113 }
114 }
115
116 /**
117 * bnx2x_shrink_eth_fp - guarantees fastpath structures stay intact
118 *
119 * @bp: driver handle
120 * @delta: number of eth queues which were not allocated
121 */
122 static void bnx2x_shrink_eth_fp(struct bnx2x *bp, int delta)
123 {
124 int i, cos, old_eth_num = BNX2X_NUM_ETH_QUEUES(bp);
125
126 /* Queue pointer cannot be re-set on an fp-basis, as moving pointer
127 * backward along the array could cause memory to be overriden
128 */
129 for (cos = 1; cos < bp->max_cos; cos++) {
130 for (i = 0; i < old_eth_num - delta; i++) {
131 struct bnx2x_fastpath *fp = &bp->fp[i];
132 int new_idx = cos * (old_eth_num - delta) + i;
133
134 memcpy(&bp->bnx2x_txq[new_idx], fp->txdata_ptr[cos],
135 sizeof(struct bnx2x_fp_txdata));
136 fp->txdata_ptr[cos] = &bp->bnx2x_txq[new_idx];
137 }
138 }
139 }
140
141 int load_count[2][3] = { {0} }; /* per-path: 0-common, 1-port0, 2-port1 */
142
143 /* free skb in the packet ring at pos idx
144 * return idx of last bd freed
145 */
146 static u16 bnx2x_free_tx_pkt(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata,
147 u16 idx, unsigned int *pkts_compl,
148 unsigned int *bytes_compl)
149 {
150 struct sw_tx_bd *tx_buf = &txdata->tx_buf_ring[idx];
151 struct eth_tx_start_bd *tx_start_bd;
152 struct eth_tx_bd *tx_data_bd;
153 struct sk_buff *skb = tx_buf->skb;
154 u16 bd_idx = TX_BD(tx_buf->first_bd), new_cons;
155 int nbd;
156
157 /* prefetch skb end pointer to speedup dev_kfree_skb() */
158 prefetch(&skb->end);
159
160 DP(NETIF_MSG_TX_DONE, "fp[%d]: pkt_idx %d buff @(%p)->skb %p\n",
161 txdata->txq_index, idx, tx_buf, skb);
162
163 /* unmap first bd */
164 tx_start_bd = &txdata->tx_desc_ring[bd_idx].start_bd;
165 dma_unmap_single(&bp->pdev->dev, BD_UNMAP_ADDR(tx_start_bd),
166 BD_UNMAP_LEN(tx_start_bd), DMA_TO_DEVICE);
167
168
169 nbd = le16_to_cpu(tx_start_bd->nbd) - 1;
170 #ifdef BNX2X_STOP_ON_ERROR
171 if ((nbd - 1) > (MAX_SKB_FRAGS + 2)) {
172 BNX2X_ERR("BAD nbd!\n");
173 bnx2x_panic();
174 }
175 #endif
176 new_cons = nbd + tx_buf->first_bd;
177
178 /* Get the next bd */
179 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
180
181 /* Skip a parse bd... */
182 --nbd;
183 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
184
185 /* ...and the TSO split header bd since they have no mapping */
186 if (tx_buf->flags & BNX2X_TSO_SPLIT_BD) {
187 --nbd;
188 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
189 }
190
191 /* now free frags */
192 while (nbd > 0) {
193
194 tx_data_bd = &txdata->tx_desc_ring[bd_idx].reg_bd;
195 dma_unmap_page(&bp->pdev->dev, BD_UNMAP_ADDR(tx_data_bd),
196 BD_UNMAP_LEN(tx_data_bd), DMA_TO_DEVICE);
197 if (--nbd)
198 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
199 }
200
201 /* release skb */
202 WARN_ON(!skb);
203 if (likely(skb)) {
204 (*pkts_compl)++;
205 (*bytes_compl) += skb->len;
206 }
207
208 dev_kfree_skb_any(skb);
209 tx_buf->first_bd = 0;
210 tx_buf->skb = NULL;
211
212 return new_cons;
213 }
214
215 int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata)
216 {
217 struct netdev_queue *txq;
218 u16 hw_cons, sw_cons, bd_cons = txdata->tx_bd_cons;
219 unsigned int pkts_compl = 0, bytes_compl = 0;
220
221 #ifdef BNX2X_STOP_ON_ERROR
222 if (unlikely(bp->panic))
223 return -1;
224 #endif
225
226 txq = netdev_get_tx_queue(bp->dev, txdata->txq_index);
227 hw_cons = le16_to_cpu(*txdata->tx_cons_sb);
228 sw_cons = txdata->tx_pkt_cons;
229
230 while (sw_cons != hw_cons) {
231 u16 pkt_cons;
232
233 pkt_cons = TX_BD(sw_cons);
234
235 DP(NETIF_MSG_TX_DONE,
236 "queue[%d]: hw_cons %u sw_cons %u pkt_cons %u\n",
237 txdata->txq_index, hw_cons, sw_cons, pkt_cons);
238
239 bd_cons = bnx2x_free_tx_pkt(bp, txdata, pkt_cons,
240 &pkts_compl, &bytes_compl);
241
242 sw_cons++;
243 }
244
245 netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
246
247 txdata->tx_pkt_cons = sw_cons;
248 txdata->tx_bd_cons = bd_cons;
249
250 /* Need to make the tx_bd_cons update visible to start_xmit()
251 * before checking for netif_tx_queue_stopped(). Without the
252 * memory barrier, there is a small possibility that
253 * start_xmit() will miss it and cause the queue to be stopped
254 * forever.
255 * On the other hand we need an rmb() here to ensure the proper
256 * ordering of bit testing in the following
257 * netif_tx_queue_stopped(txq) call.
258 */
259 smp_mb();
260
261 if (unlikely(netif_tx_queue_stopped(txq))) {
262 /* Taking tx_lock() is needed to prevent reenabling the queue
263 * while it's empty. This could have happen if rx_action() gets
264 * suspended in bnx2x_tx_int() after the condition before
265 * netif_tx_wake_queue(), while tx_action (bnx2x_start_xmit()):
266 *
267 * stops the queue->sees fresh tx_bd_cons->releases the queue->
268 * sends some packets consuming the whole queue again->
269 * stops the queue
270 */
271
272 __netif_tx_lock(txq, smp_processor_id());
273
274 if ((netif_tx_queue_stopped(txq)) &&
275 (bp->state == BNX2X_STATE_OPEN) &&
276 (bnx2x_tx_avail(bp, txdata) >= MAX_DESC_PER_TX_PKT))
277 netif_tx_wake_queue(txq);
278
279 __netif_tx_unlock(txq);
280 }
281 return 0;
282 }
283
284 static inline void bnx2x_update_last_max_sge(struct bnx2x_fastpath *fp,
285 u16 idx)
286 {
287 u16 last_max = fp->last_max_sge;
288
289 if (SUB_S16(idx, last_max) > 0)
290 fp->last_max_sge = idx;
291 }
292
293 static inline void bnx2x_update_sge_prod(struct bnx2x_fastpath *fp,
294 u16 sge_len,
295 struct eth_end_agg_rx_cqe *cqe)
296 {
297 struct bnx2x *bp = fp->bp;
298 u16 last_max, last_elem, first_elem;
299 u16 delta = 0;
300 u16 i;
301
302 if (!sge_len)
303 return;
304
305 /* First mark all used pages */
306 for (i = 0; i < sge_len; i++)
307 BIT_VEC64_CLEAR_BIT(fp->sge_mask,
308 RX_SGE(le16_to_cpu(cqe->sgl_or_raw_data.sgl[i])));
309
310 DP(NETIF_MSG_RX_STATUS, "fp_cqe->sgl[%d] = %d\n",
311 sge_len - 1, le16_to_cpu(cqe->sgl_or_raw_data.sgl[sge_len - 1]));
312
313 /* Here we assume that the last SGE index is the biggest */
314 prefetch((void *)(fp->sge_mask));
315 bnx2x_update_last_max_sge(fp,
316 le16_to_cpu(cqe->sgl_or_raw_data.sgl[sge_len - 1]));
317
318 last_max = RX_SGE(fp->last_max_sge);
319 last_elem = last_max >> BIT_VEC64_ELEM_SHIFT;
320 first_elem = RX_SGE(fp->rx_sge_prod) >> BIT_VEC64_ELEM_SHIFT;
321
322 /* If ring is not full */
323 if (last_elem + 1 != first_elem)
324 last_elem++;
325
326 /* Now update the prod */
327 for (i = first_elem; i != last_elem; i = NEXT_SGE_MASK_ELEM(i)) {
328 if (likely(fp->sge_mask[i]))
329 break;
330
331 fp->sge_mask[i] = BIT_VEC64_ELEM_ONE_MASK;
332 delta += BIT_VEC64_ELEM_SZ;
333 }
334
335 if (delta > 0) {
336 fp->rx_sge_prod += delta;
337 /* clear page-end entries */
338 bnx2x_clear_sge_mask_next_elems(fp);
339 }
340
341 DP(NETIF_MSG_RX_STATUS,
342 "fp->last_max_sge = %d fp->rx_sge_prod = %d\n",
343 fp->last_max_sge, fp->rx_sge_prod);
344 }
345
346 /* Get Toeplitz hash value in the skb using the value from the
347 * CQE (calculated by HW).
348 */
349 static u32 bnx2x_get_rxhash(const struct bnx2x *bp,
350 const struct eth_fast_path_rx_cqe *cqe,
351 bool *l4_rxhash)
352 {
353 /* Get Toeplitz hash from CQE */
354 if ((bp->dev->features & NETIF_F_RXHASH) &&
355 (cqe->status_flags & ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG)) {
356 enum eth_rss_hash_type htype;
357
358 htype = cqe->status_flags & ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE;
359 *l4_rxhash = (htype == TCP_IPV4_HASH_TYPE) ||
360 (htype == TCP_IPV6_HASH_TYPE);
361 return le32_to_cpu(cqe->rss_hash_result);
362 }
363 *l4_rxhash = false;
364 return 0;
365 }
366
367 static void bnx2x_tpa_start(struct bnx2x_fastpath *fp, u16 queue,
368 u16 cons, u16 prod,
369 struct eth_fast_path_rx_cqe *cqe)
370 {
371 struct bnx2x *bp = fp->bp;
372 struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
373 struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
374 struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
375 dma_addr_t mapping;
376 struct bnx2x_agg_info *tpa_info = &fp->tpa_info[queue];
377 struct sw_rx_bd *first_buf = &tpa_info->first_buf;
378
379 /* print error if current state != stop */
380 if (tpa_info->tpa_state != BNX2X_TPA_STOP)
381 BNX2X_ERR("start of bin not in stop [%d]\n", queue);
382
383 /* Try to map an empty data buffer from the aggregation info */
384 mapping = dma_map_single(&bp->pdev->dev,
385 first_buf->data + NET_SKB_PAD,
386 fp->rx_buf_size, DMA_FROM_DEVICE);
387 /*
388 * ...if it fails - move the skb from the consumer to the producer
389 * and set the current aggregation state as ERROR to drop it
390 * when TPA_STOP arrives.
391 */
392
393 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
394 /* Move the BD from the consumer to the producer */
395 bnx2x_reuse_rx_data(fp, cons, prod);
396 tpa_info->tpa_state = BNX2X_TPA_ERROR;
397 return;
398 }
399
400 /* move empty data from pool to prod */
401 prod_rx_buf->data = first_buf->data;
402 dma_unmap_addr_set(prod_rx_buf, mapping, mapping);
403 /* point prod_bd to new data */
404 prod_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
405 prod_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
406
407 /* move partial skb from cons to pool (don't unmap yet) */
408 *first_buf = *cons_rx_buf;
409
410 /* mark bin state as START */
411 tpa_info->parsing_flags =
412 le16_to_cpu(cqe->pars_flags.flags);
413 tpa_info->vlan_tag = le16_to_cpu(cqe->vlan_tag);
414 tpa_info->tpa_state = BNX2X_TPA_START;
415 tpa_info->len_on_bd = le16_to_cpu(cqe->len_on_bd);
416 tpa_info->placement_offset = cqe->placement_offset;
417 tpa_info->rxhash = bnx2x_get_rxhash(bp, cqe, &tpa_info->l4_rxhash);
418 if (fp->mode == TPA_MODE_GRO) {
419 u16 gro_size = le16_to_cpu(cqe->pkt_len_or_gro_seg_len);
420 tpa_info->full_page = SGE_PAGES / gro_size * gro_size;
421 tpa_info->gro_size = gro_size;
422 }
423
424 #ifdef BNX2X_STOP_ON_ERROR
425 fp->tpa_queue_used |= (1 << queue);
426 #ifdef _ASM_GENERIC_INT_L64_H
427 DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%lx\n",
428 #else
429 DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%llx\n",
430 #endif
431 fp->tpa_queue_used);
432 #endif
433 }
434
435 /* Timestamp option length allowed for TPA aggregation:
436 *
437 * nop nop kind length echo val
438 */
439 #define TPA_TSTAMP_OPT_LEN 12
440 /**
441 * bnx2x_set_gro_params - compute GRO values
442 *
443 * @skb: packet skb
444 * @parsing_flags: parsing flags from the START CQE
445 * @len_on_bd: total length of the first packet for the
446 * aggregation.
447 * @pkt_len: length of all segments
448 *
449 * Approximate value of the MSS for this aggregation calculated using
450 * the first packet of it.
451 * Compute number of aggregated segments, and gso_type.
452 */
453 static void bnx2x_set_gro_params(struct sk_buff *skb, u16 parsing_flags,
454 u16 len_on_bd, unsigned int pkt_len)
455 {
456 /* TPA aggregation won't have either IP options or TCP options
457 * other than timestamp or IPv6 extension headers.
458 */
459 u16 hdrs_len = ETH_HLEN + sizeof(struct tcphdr);
460
461 if (GET_FLAG(parsing_flags, PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) ==
462 PRS_FLAG_OVERETH_IPV6) {
463 hdrs_len += sizeof(struct ipv6hdr);
464 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
465 } else {
466 hdrs_len += sizeof(struct iphdr);
467 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
468 }
469
470 /* Check if there was a TCP timestamp, if there is it's will
471 * always be 12 bytes length: nop nop kind length echo val.
472 *
473 * Otherwise FW would close the aggregation.
474 */
475 if (parsing_flags & PARSING_FLAGS_TIME_STAMP_EXIST_FLAG)
476 hdrs_len += TPA_TSTAMP_OPT_LEN;
477
478 skb_shinfo(skb)->gso_size = len_on_bd - hdrs_len;
479
480 /* tcp_gro_complete() will copy NAPI_GRO_CB(skb)->count
481 * to skb_shinfo(skb)->gso_segs
482 */
483 NAPI_GRO_CB(skb)->count = DIV_ROUND_UP(pkt_len - hdrs_len,
484 skb_shinfo(skb)->gso_size);
485 }
486
487 static int bnx2x_alloc_rx_sge(struct bnx2x *bp,
488 struct bnx2x_fastpath *fp, u16 index)
489 {
490 struct page *page = alloc_pages(GFP_ATOMIC, PAGES_PER_SGE_SHIFT);
491 struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
492 struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
493 dma_addr_t mapping;
494
495 if (unlikely(page == NULL)) {
496 BNX2X_ERR("Can't alloc sge\n");
497 return -ENOMEM;
498 }
499
500 mapping = dma_map_page(&bp->pdev->dev, page, 0,
501 SGE_PAGES, DMA_FROM_DEVICE);
502 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
503 __free_pages(page, PAGES_PER_SGE_SHIFT);
504 BNX2X_ERR("Can't map sge\n");
505 return -ENOMEM;
506 }
507
508 sw_buf->page = page;
509 dma_unmap_addr_set(sw_buf, mapping, mapping);
510
511 sge->addr_hi = cpu_to_le32(U64_HI(mapping));
512 sge->addr_lo = cpu_to_le32(U64_LO(mapping));
513
514 return 0;
515 }
516
517 static int bnx2x_fill_frag_skb(struct bnx2x *bp, struct bnx2x_fastpath *fp,
518 struct bnx2x_agg_info *tpa_info,
519 u16 pages,
520 struct sk_buff *skb,
521 struct eth_end_agg_rx_cqe *cqe,
522 u16 cqe_idx)
523 {
524 struct sw_rx_page *rx_pg, old_rx_pg;
525 u32 i, frag_len, frag_size;
526 int err, j, frag_id = 0;
527 u16 len_on_bd = tpa_info->len_on_bd;
528 u16 full_page = 0, gro_size = 0;
529
530 frag_size = le16_to_cpu(cqe->pkt_len) - len_on_bd;
531
532 if (fp->mode == TPA_MODE_GRO) {
533 gro_size = tpa_info->gro_size;
534 full_page = tpa_info->full_page;
535 }
536
537 /* This is needed in order to enable forwarding support */
538 if (frag_size)
539 bnx2x_set_gro_params(skb, tpa_info->parsing_flags, len_on_bd,
540 le16_to_cpu(cqe->pkt_len));
541
542 #ifdef BNX2X_STOP_ON_ERROR
543 if (pages > min_t(u32, 8, MAX_SKB_FRAGS) * SGE_PAGES) {
544 BNX2X_ERR("SGL length is too long: %d. CQE index is %d\n",
545 pages, cqe_idx);
546 BNX2X_ERR("cqe->pkt_len = %d\n", cqe->pkt_len);
547 bnx2x_panic();
548 return -EINVAL;
549 }
550 #endif
551
552 /* Run through the SGL and compose the fragmented skb */
553 for (i = 0, j = 0; i < pages; i += PAGES_PER_SGE, j++) {
554 u16 sge_idx = RX_SGE(le16_to_cpu(cqe->sgl_or_raw_data.sgl[j]));
555
556 /* FW gives the indices of the SGE as if the ring is an array
557 (meaning that "next" element will consume 2 indices) */
558 if (fp->mode == TPA_MODE_GRO)
559 frag_len = min_t(u32, frag_size, (u32)full_page);
560 else /* LRO */
561 frag_len = min_t(u32, frag_size, (u32)SGE_PAGES);
562
563 rx_pg = &fp->rx_page_ring[sge_idx];
564 old_rx_pg = *rx_pg;
565
566 /* If we fail to allocate a substitute page, we simply stop
567 where we are and drop the whole packet */
568 err = bnx2x_alloc_rx_sge(bp, fp, sge_idx);
569 if (unlikely(err)) {
570 bnx2x_fp_qstats(bp, fp)->rx_skb_alloc_failed++;
571 return err;
572 }
573
574 /* Unmap the page as we r going to pass it to the stack */
575 dma_unmap_page(&bp->pdev->dev,
576 dma_unmap_addr(&old_rx_pg, mapping),
577 SGE_PAGES, DMA_FROM_DEVICE);
578 /* Add one frag and update the appropriate fields in the skb */
579 if (fp->mode == TPA_MODE_LRO)
580 skb_fill_page_desc(skb, j, old_rx_pg.page, 0, frag_len);
581 else { /* GRO */
582 int rem;
583 int offset = 0;
584 for (rem = frag_len; rem > 0; rem -= gro_size) {
585 int len = rem > gro_size ? gro_size : rem;
586 skb_fill_page_desc(skb, frag_id++,
587 old_rx_pg.page, offset, len);
588 if (offset)
589 get_page(old_rx_pg.page);
590 offset += len;
591 }
592 }
593
594 skb->data_len += frag_len;
595 skb->truesize += SGE_PAGES;
596 skb->len += frag_len;
597
598 frag_size -= frag_len;
599 }
600
601 return 0;
602 }
603
604 static void bnx2x_frag_free(const struct bnx2x_fastpath *fp, void *data)
605 {
606 if (fp->rx_frag_size)
607 put_page(virt_to_head_page(data));
608 else
609 kfree(data);
610 }
611
612 static void *bnx2x_frag_alloc(const struct bnx2x_fastpath *fp)
613 {
614 if (fp->rx_frag_size)
615 return netdev_alloc_frag(fp->rx_frag_size);
616
617 return kmalloc(fp->rx_buf_size + NET_SKB_PAD, GFP_ATOMIC);
618 }
619
620 #ifdef CONFIG_INET
621 static void bnx2x_gro_ip_csum(struct bnx2x *bp, struct sk_buff *skb)
622 {
623 const struct iphdr *iph = ip_hdr(skb);
624 struct tcphdr *th;
625
626 skb_set_transport_header(skb, sizeof(struct iphdr));
627 th = tcp_hdr(skb);
628
629 th->check = ~tcp_v4_check(skb->len - skb_transport_offset(skb),
630 iph->saddr, iph->daddr, 0);
631 }
632
633 static void bnx2x_gro_ipv6_csum(struct bnx2x *bp, struct sk_buff *skb)
634 {
635 struct ipv6hdr *iph = ipv6_hdr(skb);
636 struct tcphdr *th;
637
638 skb_set_transport_header(skb, sizeof(struct ipv6hdr));
639 th = tcp_hdr(skb);
640
641 th->check = ~tcp_v6_check(skb->len - skb_transport_offset(skb),
642 &iph->saddr, &iph->daddr, 0);
643 }
644 #endif
645
646 static void bnx2x_gro_receive(struct bnx2x *bp, struct bnx2x_fastpath *fp,
647 struct sk_buff *skb)
648 {
649 #ifdef CONFIG_INET
650 if (skb_shinfo(skb)->gso_size) {
651 skb_set_network_header(skb, 0);
652 switch (be16_to_cpu(skb->protocol)) {
653 case ETH_P_IP:
654 bnx2x_gro_ip_csum(bp, skb);
655 break;
656 case ETH_P_IPV6:
657 bnx2x_gro_ipv6_csum(bp, skb);
658 break;
659 default:
660 BNX2X_ERR("FW GRO supports only IPv4/IPv6, not 0x%04x\n",
661 be16_to_cpu(skb->protocol));
662 }
663 tcp_gro_complete(skb);
664 }
665 #endif
666 napi_gro_receive(&fp->napi, skb);
667 }
668
669 static void bnx2x_tpa_stop(struct bnx2x *bp, struct bnx2x_fastpath *fp,
670 struct bnx2x_agg_info *tpa_info,
671 u16 pages,
672 struct eth_end_agg_rx_cqe *cqe,
673 u16 cqe_idx)
674 {
675 struct sw_rx_bd *rx_buf = &tpa_info->first_buf;
676 u8 pad = tpa_info->placement_offset;
677 u16 len = tpa_info->len_on_bd;
678 struct sk_buff *skb = NULL;
679 u8 *new_data, *data = rx_buf->data;
680 u8 old_tpa_state = tpa_info->tpa_state;
681
682 tpa_info->tpa_state = BNX2X_TPA_STOP;
683
684 /* If we there was an error during the handling of the TPA_START -
685 * drop this aggregation.
686 */
687 if (old_tpa_state == BNX2X_TPA_ERROR)
688 goto drop;
689
690 /* Try to allocate the new data */
691 new_data = bnx2x_frag_alloc(fp);
692 /* Unmap skb in the pool anyway, as we are going to change
693 pool entry status to BNX2X_TPA_STOP even if new skb allocation
694 fails. */
695 dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(rx_buf, mapping),
696 fp->rx_buf_size, DMA_FROM_DEVICE);
697 if (likely(new_data))
698 skb = build_skb(data, fp->rx_frag_size);
699
700 if (likely(skb)) {
701 #ifdef BNX2X_STOP_ON_ERROR
702 if (pad + len > fp->rx_buf_size) {
703 BNX2X_ERR("skb_put is about to fail... pad %d len %d rx_buf_size %d\n",
704 pad, len, fp->rx_buf_size);
705 bnx2x_panic();
706 return;
707 }
708 #endif
709
710 skb_reserve(skb, pad + NET_SKB_PAD);
711 skb_put(skb, len);
712 skb->rxhash = tpa_info->rxhash;
713 skb->l4_rxhash = tpa_info->l4_rxhash;
714
715 skb->protocol = eth_type_trans(skb, bp->dev);
716 skb->ip_summed = CHECKSUM_UNNECESSARY;
717
718 if (!bnx2x_fill_frag_skb(bp, fp, tpa_info, pages,
719 skb, cqe, cqe_idx)) {
720 if (tpa_info->parsing_flags & PARSING_FLAGS_VLAN)
721 __vlan_hwaccel_put_tag(skb, tpa_info->vlan_tag);
722 bnx2x_gro_receive(bp, fp, skb);
723 } else {
724 DP(NETIF_MSG_RX_STATUS,
725 "Failed to allocate new pages - dropping packet!\n");
726 dev_kfree_skb_any(skb);
727 }
728
729
730 /* put new data in bin */
731 rx_buf->data = new_data;
732
733 return;
734 }
735 bnx2x_frag_free(fp, new_data);
736 drop:
737 /* drop the packet and keep the buffer in the bin */
738 DP(NETIF_MSG_RX_STATUS,
739 "Failed to allocate or map a new skb - dropping packet!\n");
740 bnx2x_fp_stats(bp, fp)->eth_q_stats.rx_skb_alloc_failed++;
741 }
742
743 static int bnx2x_alloc_rx_data(struct bnx2x *bp,
744 struct bnx2x_fastpath *fp, u16 index)
745 {
746 u8 *data;
747 struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[index];
748 struct eth_rx_bd *rx_bd = &fp->rx_desc_ring[index];
749 dma_addr_t mapping;
750
751 data = bnx2x_frag_alloc(fp);
752 if (unlikely(data == NULL))
753 return -ENOMEM;
754
755 mapping = dma_map_single(&bp->pdev->dev, data + NET_SKB_PAD,
756 fp->rx_buf_size,
757 DMA_FROM_DEVICE);
758 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
759 bnx2x_frag_free(fp, data);
760 BNX2X_ERR("Can't map rx data\n");
761 return -ENOMEM;
762 }
763
764 rx_buf->data = data;
765 dma_unmap_addr_set(rx_buf, mapping, mapping);
766
767 rx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
768 rx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
769
770 return 0;
771 }
772
773 static
774 void bnx2x_csum_validate(struct sk_buff *skb, union eth_rx_cqe *cqe,
775 struct bnx2x_fastpath *fp,
776 struct bnx2x_eth_q_stats *qstats)
777 {
778 /* Do nothing if no L4 csum validation was done.
779 * We do not check whether IP csum was validated. For IPv4 we assume
780 * that if the card got as far as validating the L4 csum, it also
781 * validated the IP csum. IPv6 has no IP csum.
782 */
783 if (cqe->fast_path_cqe.status_flags &
784 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG)
785 return;
786
787 /* If L4 validation was done, check if an error was found. */
788
789 if (cqe->fast_path_cqe.type_error_flags &
790 (ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG |
791 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
792 qstats->hw_csum_err++;
793 else
794 skb->ip_summed = CHECKSUM_UNNECESSARY;
795 }
796
797 int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
798 {
799 struct bnx2x *bp = fp->bp;
800 u16 bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
801 u16 hw_comp_cons, sw_comp_cons, sw_comp_prod;
802 int rx_pkt = 0;
803
804 #ifdef BNX2X_STOP_ON_ERROR
805 if (unlikely(bp->panic))
806 return 0;
807 #endif
808
809 /* CQ "next element" is of the size of the regular element,
810 that's why it's ok here */
811 hw_comp_cons = le16_to_cpu(*fp->rx_cons_sb);
812 if ((hw_comp_cons & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT)
813 hw_comp_cons++;
814
815 bd_cons = fp->rx_bd_cons;
816 bd_prod = fp->rx_bd_prod;
817 bd_prod_fw = bd_prod;
818 sw_comp_cons = fp->rx_comp_cons;
819 sw_comp_prod = fp->rx_comp_prod;
820
821 /* Memory barrier necessary as speculative reads of the rx
822 * buffer can be ahead of the index in the status block
823 */
824 rmb();
825
826 DP(NETIF_MSG_RX_STATUS,
827 "queue[%d]: hw_comp_cons %u sw_comp_cons %u\n",
828 fp->index, hw_comp_cons, sw_comp_cons);
829
830 while (sw_comp_cons != hw_comp_cons) {
831 struct sw_rx_bd *rx_buf = NULL;
832 struct sk_buff *skb;
833 union eth_rx_cqe *cqe;
834 struct eth_fast_path_rx_cqe *cqe_fp;
835 u8 cqe_fp_flags;
836 enum eth_rx_cqe_type cqe_fp_type;
837 u16 len, pad, queue;
838 u8 *data;
839 bool l4_rxhash;
840
841 #ifdef BNX2X_STOP_ON_ERROR
842 if (unlikely(bp->panic))
843 return 0;
844 #endif
845
846 comp_ring_cons = RCQ_BD(sw_comp_cons);
847 bd_prod = RX_BD(bd_prod);
848 bd_cons = RX_BD(bd_cons);
849
850 cqe = &fp->rx_comp_ring[comp_ring_cons];
851 cqe_fp = &cqe->fast_path_cqe;
852 cqe_fp_flags = cqe_fp->type_error_flags;
853 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
854
855 DP(NETIF_MSG_RX_STATUS,
856 "CQE type %x err %x status %x queue %x vlan %x len %u\n",
857 CQE_TYPE(cqe_fp_flags),
858 cqe_fp_flags, cqe_fp->status_flags,
859 le32_to_cpu(cqe_fp->rss_hash_result),
860 le16_to_cpu(cqe_fp->vlan_tag),
861 le16_to_cpu(cqe_fp->pkt_len_or_gro_seg_len));
862
863 /* is this a slowpath msg? */
864 if (unlikely(CQE_TYPE_SLOW(cqe_fp_type))) {
865 bnx2x_sp_event(fp, cqe);
866 goto next_cqe;
867 }
868
869 rx_buf = &fp->rx_buf_ring[bd_cons];
870 data = rx_buf->data;
871
872 if (!CQE_TYPE_FAST(cqe_fp_type)) {
873 struct bnx2x_agg_info *tpa_info;
874 u16 frag_size, pages;
875 #ifdef BNX2X_STOP_ON_ERROR
876 /* sanity check */
877 if (fp->disable_tpa &&
878 (CQE_TYPE_START(cqe_fp_type) ||
879 CQE_TYPE_STOP(cqe_fp_type)))
880 BNX2X_ERR("START/STOP packet while disable_tpa type %x\n",
881 CQE_TYPE(cqe_fp_type));
882 #endif
883
884 if (CQE_TYPE_START(cqe_fp_type)) {
885 u16 queue = cqe_fp->queue_index;
886 DP(NETIF_MSG_RX_STATUS,
887 "calling tpa_start on queue %d\n",
888 queue);
889
890 bnx2x_tpa_start(fp, queue,
891 bd_cons, bd_prod,
892 cqe_fp);
893
894 goto next_rx;
895
896 }
897 queue = cqe->end_agg_cqe.queue_index;
898 tpa_info = &fp->tpa_info[queue];
899 DP(NETIF_MSG_RX_STATUS,
900 "calling tpa_stop on queue %d\n",
901 queue);
902
903 frag_size = le16_to_cpu(cqe->end_agg_cqe.pkt_len) -
904 tpa_info->len_on_bd;
905
906 if (fp->mode == TPA_MODE_GRO)
907 pages = (frag_size + tpa_info->full_page - 1) /
908 tpa_info->full_page;
909 else
910 pages = SGE_PAGE_ALIGN(frag_size) >>
911 SGE_PAGE_SHIFT;
912
913 bnx2x_tpa_stop(bp, fp, tpa_info, pages,
914 &cqe->end_agg_cqe, comp_ring_cons);
915 #ifdef BNX2X_STOP_ON_ERROR
916 if (bp->panic)
917 return 0;
918 #endif
919
920 bnx2x_update_sge_prod(fp, pages, &cqe->end_agg_cqe);
921 goto next_cqe;
922 }
923 /* non TPA */
924 len = le16_to_cpu(cqe_fp->pkt_len_or_gro_seg_len);
925 pad = cqe_fp->placement_offset;
926 dma_sync_single_for_cpu(&bp->pdev->dev,
927 dma_unmap_addr(rx_buf, mapping),
928 pad + RX_COPY_THRESH,
929 DMA_FROM_DEVICE);
930 pad += NET_SKB_PAD;
931 prefetch(data + pad); /* speedup eth_type_trans() */
932 /* is this an error packet? */
933 if (unlikely(cqe_fp_flags & ETH_RX_ERROR_FALGS)) {
934 DP(NETIF_MSG_RX_ERR | NETIF_MSG_RX_STATUS,
935 "ERROR flags %x rx packet %u\n",
936 cqe_fp_flags, sw_comp_cons);
937 bnx2x_fp_qstats(bp, fp)->rx_err_discard_pkt++;
938 goto reuse_rx;
939 }
940
941 /* Since we don't have a jumbo ring
942 * copy small packets if mtu > 1500
943 */
944 if ((bp->dev->mtu > ETH_MAX_PACKET_SIZE) &&
945 (len <= RX_COPY_THRESH)) {
946 skb = netdev_alloc_skb_ip_align(bp->dev, len);
947 if (skb == NULL) {
948 DP(NETIF_MSG_RX_ERR | NETIF_MSG_RX_STATUS,
949 "ERROR packet dropped because of alloc failure\n");
950 bnx2x_fp_qstats(bp, fp)->rx_skb_alloc_failed++;
951 goto reuse_rx;
952 }
953 memcpy(skb->data, data + pad, len);
954 bnx2x_reuse_rx_data(fp, bd_cons, bd_prod);
955 } else {
956 if (likely(bnx2x_alloc_rx_data(bp, fp, bd_prod) == 0)) {
957 dma_unmap_single(&bp->pdev->dev,
958 dma_unmap_addr(rx_buf, mapping),
959 fp->rx_buf_size,
960 DMA_FROM_DEVICE);
961 skb = build_skb(data, fp->rx_frag_size);
962 if (unlikely(!skb)) {
963 bnx2x_frag_free(fp, data);
964 bnx2x_fp_qstats(bp, fp)->
965 rx_skb_alloc_failed++;
966 goto next_rx;
967 }
968 skb_reserve(skb, pad);
969 } else {
970 DP(NETIF_MSG_RX_ERR | NETIF_MSG_RX_STATUS,
971 "ERROR packet dropped because of alloc failure\n");
972 bnx2x_fp_qstats(bp, fp)->rx_skb_alloc_failed++;
973 reuse_rx:
974 bnx2x_reuse_rx_data(fp, bd_cons, bd_prod);
975 goto next_rx;
976 }
977 }
978
979 skb_put(skb, len);
980 skb->protocol = eth_type_trans(skb, bp->dev);
981
982 /* Set Toeplitz hash for a none-LRO skb */
983 skb->rxhash = bnx2x_get_rxhash(bp, cqe_fp, &l4_rxhash);
984 skb->l4_rxhash = l4_rxhash;
985
986 skb_checksum_none_assert(skb);
987
988 if (bp->dev->features & NETIF_F_RXCSUM)
989 bnx2x_csum_validate(skb, cqe, fp,
990 bnx2x_fp_qstats(bp, fp));
991
992 skb_record_rx_queue(skb, fp->rx_queue);
993
994 if (le16_to_cpu(cqe_fp->pars_flags.flags) &
995 PARSING_FLAGS_VLAN)
996 __vlan_hwaccel_put_tag(skb,
997 le16_to_cpu(cqe_fp->vlan_tag));
998 napi_gro_receive(&fp->napi, skb);
999
1000
1001 next_rx:
1002 rx_buf->data = NULL;
1003
1004 bd_cons = NEXT_RX_IDX(bd_cons);
1005 bd_prod = NEXT_RX_IDX(bd_prod);
1006 bd_prod_fw = NEXT_RX_IDX(bd_prod_fw);
1007 rx_pkt++;
1008 next_cqe:
1009 sw_comp_prod = NEXT_RCQ_IDX(sw_comp_prod);
1010 sw_comp_cons = NEXT_RCQ_IDX(sw_comp_cons);
1011
1012 if (rx_pkt == budget)
1013 break;
1014 } /* while */
1015
1016 fp->rx_bd_cons = bd_cons;
1017 fp->rx_bd_prod = bd_prod_fw;
1018 fp->rx_comp_cons = sw_comp_cons;
1019 fp->rx_comp_prod = sw_comp_prod;
1020
1021 /* Update producers */
1022 bnx2x_update_rx_prod(bp, fp, bd_prod_fw, sw_comp_prod,
1023 fp->rx_sge_prod);
1024
1025 fp->rx_pkt += rx_pkt;
1026 fp->rx_calls++;
1027
1028 return rx_pkt;
1029 }
1030
1031 static irqreturn_t bnx2x_msix_fp_int(int irq, void *fp_cookie)
1032 {
1033 struct bnx2x_fastpath *fp = fp_cookie;
1034 struct bnx2x *bp = fp->bp;
1035 u8 cos;
1036
1037 DP(NETIF_MSG_INTR,
1038 "got an MSI-X interrupt on IDX:SB [fp %d fw_sd %d igusb %d]\n",
1039 fp->index, fp->fw_sb_id, fp->igu_sb_id);
1040 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0);
1041
1042 #ifdef BNX2X_STOP_ON_ERROR
1043 if (unlikely(bp->panic))
1044 return IRQ_HANDLED;
1045 #endif
1046
1047 /* Handle Rx and Tx according to MSI-X vector */
1048 prefetch(fp->rx_cons_sb);
1049
1050 for_each_cos_in_tx_queue(fp, cos)
1051 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1052
1053 prefetch(&fp->sb_running_index[SM_RX_ID]);
1054 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1055
1056 return IRQ_HANDLED;
1057 }
1058
1059 /* HW Lock for shared dual port PHYs */
1060 void bnx2x_acquire_phy_lock(struct bnx2x *bp)
1061 {
1062 mutex_lock(&bp->port.phy_mutex);
1063
1064 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_MDIO);
1065 }
1066
1067 void bnx2x_release_phy_lock(struct bnx2x *bp)
1068 {
1069 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_MDIO);
1070
1071 mutex_unlock(&bp->port.phy_mutex);
1072 }
1073
1074 /* calculates MF speed according to current linespeed and MF configuration */
1075 u16 bnx2x_get_mf_speed(struct bnx2x *bp)
1076 {
1077 u16 line_speed = bp->link_vars.line_speed;
1078 if (IS_MF(bp)) {
1079 u16 maxCfg = bnx2x_extract_max_cfg(bp,
1080 bp->mf_config[BP_VN(bp)]);
1081
1082 /* Calculate the current MAX line speed limit for the MF
1083 * devices
1084 */
1085 if (IS_MF_SI(bp))
1086 line_speed = (line_speed * maxCfg) / 100;
1087 else { /* SD mode */
1088 u16 vn_max_rate = maxCfg * 100;
1089
1090 if (vn_max_rate < line_speed)
1091 line_speed = vn_max_rate;
1092 }
1093 }
1094
1095 return line_speed;
1096 }
1097
1098 /**
1099 * bnx2x_fill_report_data - fill link report data to report
1100 *
1101 * @bp: driver handle
1102 * @data: link state to update
1103 *
1104 * It uses a none-atomic bit operations because is called under the mutex.
1105 */
1106 static void bnx2x_fill_report_data(struct bnx2x *bp,
1107 struct bnx2x_link_report_data *data)
1108 {
1109 u16 line_speed = bnx2x_get_mf_speed(bp);
1110
1111 memset(data, 0, sizeof(*data));
1112
1113 /* Fill the report data: efective line speed */
1114 data->line_speed = line_speed;
1115
1116 /* Link is down */
1117 if (!bp->link_vars.link_up || (bp->flags & MF_FUNC_DIS))
1118 __set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1119 &data->link_report_flags);
1120
1121 /* Full DUPLEX */
1122 if (bp->link_vars.duplex == DUPLEX_FULL)
1123 __set_bit(BNX2X_LINK_REPORT_FD, &data->link_report_flags);
1124
1125 /* Rx Flow Control is ON */
1126 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX)
1127 __set_bit(BNX2X_LINK_REPORT_RX_FC_ON, &data->link_report_flags);
1128
1129 /* Tx Flow Control is ON */
1130 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
1131 __set_bit(BNX2X_LINK_REPORT_TX_FC_ON, &data->link_report_flags);
1132 }
1133
1134 /**
1135 * bnx2x_link_report - report link status to OS.
1136 *
1137 * @bp: driver handle
1138 *
1139 * Calls the __bnx2x_link_report() under the same locking scheme
1140 * as a link/PHY state managing code to ensure a consistent link
1141 * reporting.
1142 */
1143
1144 void bnx2x_link_report(struct bnx2x *bp)
1145 {
1146 bnx2x_acquire_phy_lock(bp);
1147 __bnx2x_link_report(bp);
1148 bnx2x_release_phy_lock(bp);
1149 }
1150
1151 /**
1152 * __bnx2x_link_report - report link status to OS.
1153 *
1154 * @bp: driver handle
1155 *
1156 * None atomic inmlementation.
1157 * Should be called under the phy_lock.
1158 */
1159 void __bnx2x_link_report(struct bnx2x *bp)
1160 {
1161 struct bnx2x_link_report_data cur_data;
1162
1163 /* reread mf_cfg */
1164 if (IS_PF(bp) && !CHIP_IS_E1(bp))
1165 bnx2x_read_mf_cfg(bp);
1166
1167 /* Read the current link report info */
1168 bnx2x_fill_report_data(bp, &cur_data);
1169
1170 /* Don't report link down or exactly the same link status twice */
1171 if (!memcmp(&cur_data, &bp->last_reported_link, sizeof(cur_data)) ||
1172 (test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1173 &bp->last_reported_link.link_report_flags) &&
1174 test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1175 &cur_data.link_report_flags)))
1176 return;
1177
1178 bp->link_cnt++;
1179
1180 /* We are going to report a new link parameters now -
1181 * remember the current data for the next time.
1182 */
1183 memcpy(&bp->last_reported_link, &cur_data, sizeof(cur_data));
1184
1185 if (test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1186 &cur_data.link_report_flags)) {
1187 netif_carrier_off(bp->dev);
1188 netdev_err(bp->dev, "NIC Link is Down\n");
1189 return;
1190 } else {
1191 const char *duplex;
1192 const char *flow;
1193
1194 netif_carrier_on(bp->dev);
1195
1196 if (test_and_clear_bit(BNX2X_LINK_REPORT_FD,
1197 &cur_data.link_report_flags))
1198 duplex = "full";
1199 else
1200 duplex = "half";
1201
1202 /* Handle the FC at the end so that only these flags would be
1203 * possibly set. This way we may easily check if there is no FC
1204 * enabled.
1205 */
1206 if (cur_data.link_report_flags) {
1207 if (test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
1208 &cur_data.link_report_flags)) {
1209 if (test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
1210 &cur_data.link_report_flags))
1211 flow = "ON - receive & transmit";
1212 else
1213 flow = "ON - receive";
1214 } else {
1215 flow = "ON - transmit";
1216 }
1217 } else {
1218 flow = "none";
1219 }
1220 netdev_info(bp->dev, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
1221 cur_data.line_speed, duplex, flow);
1222 }
1223 }
1224
1225 static void bnx2x_set_next_page_sgl(struct bnx2x_fastpath *fp)
1226 {
1227 int i;
1228
1229 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
1230 struct eth_rx_sge *sge;
1231
1232 sge = &fp->rx_sge_ring[RX_SGE_CNT * i - 2];
1233 sge->addr_hi =
1234 cpu_to_le32(U64_HI(fp->rx_sge_mapping +
1235 BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
1236
1237 sge->addr_lo =
1238 cpu_to_le32(U64_LO(fp->rx_sge_mapping +
1239 BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
1240 }
1241 }
1242
1243 static void bnx2x_free_tpa_pool(struct bnx2x *bp,
1244 struct bnx2x_fastpath *fp, int last)
1245 {
1246 int i;
1247
1248 for (i = 0; i < last; i++) {
1249 struct bnx2x_agg_info *tpa_info = &fp->tpa_info[i];
1250 struct sw_rx_bd *first_buf = &tpa_info->first_buf;
1251 u8 *data = first_buf->data;
1252
1253 if (data == NULL) {
1254 DP(NETIF_MSG_IFDOWN, "tpa bin %d empty on free\n", i);
1255 continue;
1256 }
1257 if (tpa_info->tpa_state == BNX2X_TPA_START)
1258 dma_unmap_single(&bp->pdev->dev,
1259 dma_unmap_addr(first_buf, mapping),
1260 fp->rx_buf_size, DMA_FROM_DEVICE);
1261 bnx2x_frag_free(fp, data);
1262 first_buf->data = NULL;
1263 }
1264 }
1265
1266 void bnx2x_init_rx_rings_cnic(struct bnx2x *bp)
1267 {
1268 int j;
1269
1270 for_each_rx_queue_cnic(bp, j) {
1271 struct bnx2x_fastpath *fp = &bp->fp[j];
1272
1273 fp->rx_bd_cons = 0;
1274
1275 /* Activate BD ring */
1276 /* Warning!
1277 * this will generate an interrupt (to the TSTORM)
1278 * must only be done after chip is initialized
1279 */
1280 bnx2x_update_rx_prod(bp, fp, fp->rx_bd_prod, fp->rx_comp_prod,
1281 fp->rx_sge_prod);
1282 }
1283 }
1284
1285 void bnx2x_init_rx_rings(struct bnx2x *bp)
1286 {
1287 int func = BP_FUNC(bp);
1288 u16 ring_prod;
1289 int i, j;
1290
1291 /* Allocate TPA resources */
1292 for_each_eth_queue(bp, j) {
1293 struct bnx2x_fastpath *fp = &bp->fp[j];
1294
1295 DP(NETIF_MSG_IFUP,
1296 "mtu %d rx_buf_size %d\n", bp->dev->mtu, fp->rx_buf_size);
1297
1298 if (!fp->disable_tpa) {
1299 /* Fill the per-aggregtion pool */
1300 for (i = 0; i < MAX_AGG_QS(bp); i++) {
1301 struct bnx2x_agg_info *tpa_info =
1302 &fp->tpa_info[i];
1303 struct sw_rx_bd *first_buf =
1304 &tpa_info->first_buf;
1305
1306 first_buf->data = bnx2x_frag_alloc(fp);
1307 if (!first_buf->data) {
1308 BNX2X_ERR("Failed to allocate TPA skb pool for queue[%d] - disabling TPA on this queue!\n",
1309 j);
1310 bnx2x_free_tpa_pool(bp, fp, i);
1311 fp->disable_tpa = 1;
1312 break;
1313 }
1314 dma_unmap_addr_set(first_buf, mapping, 0);
1315 tpa_info->tpa_state = BNX2X_TPA_STOP;
1316 }
1317
1318 /* "next page" elements initialization */
1319 bnx2x_set_next_page_sgl(fp);
1320
1321 /* set SGEs bit mask */
1322 bnx2x_init_sge_ring_bit_mask(fp);
1323
1324 /* Allocate SGEs and initialize the ring elements */
1325 for (i = 0, ring_prod = 0;
1326 i < MAX_RX_SGE_CNT*NUM_RX_SGE_PAGES; i++) {
1327
1328 if (bnx2x_alloc_rx_sge(bp, fp, ring_prod) < 0) {
1329 BNX2X_ERR("was only able to allocate %d rx sges\n",
1330 i);
1331 BNX2X_ERR("disabling TPA for queue[%d]\n",
1332 j);
1333 /* Cleanup already allocated elements */
1334 bnx2x_free_rx_sge_range(bp, fp,
1335 ring_prod);
1336 bnx2x_free_tpa_pool(bp, fp,
1337 MAX_AGG_QS(bp));
1338 fp->disable_tpa = 1;
1339 ring_prod = 0;
1340 break;
1341 }
1342 ring_prod = NEXT_SGE_IDX(ring_prod);
1343 }
1344
1345 fp->rx_sge_prod = ring_prod;
1346 }
1347 }
1348
1349 for_each_eth_queue(bp, j) {
1350 struct bnx2x_fastpath *fp = &bp->fp[j];
1351
1352 fp->rx_bd_cons = 0;
1353
1354 /* Activate BD ring */
1355 /* Warning!
1356 * this will generate an interrupt (to the TSTORM)
1357 * must only be done after chip is initialized
1358 */
1359 bnx2x_update_rx_prod(bp, fp, fp->rx_bd_prod, fp->rx_comp_prod,
1360 fp->rx_sge_prod);
1361
1362 if (j != 0)
1363 continue;
1364
1365 if (CHIP_IS_E1(bp)) {
1366 REG_WR(bp, BAR_USTRORM_INTMEM +
1367 USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func),
1368 U64_LO(fp->rx_comp_mapping));
1369 REG_WR(bp, BAR_USTRORM_INTMEM +
1370 USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func) + 4,
1371 U64_HI(fp->rx_comp_mapping));
1372 }
1373 }
1374 }
1375
1376 static void bnx2x_free_tx_skbs_queue(struct bnx2x_fastpath *fp)
1377 {
1378 u8 cos;
1379 struct bnx2x *bp = fp->bp;
1380
1381 for_each_cos_in_tx_queue(fp, cos) {
1382 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1383 unsigned pkts_compl = 0, bytes_compl = 0;
1384
1385 u16 sw_prod = txdata->tx_pkt_prod;
1386 u16 sw_cons = txdata->tx_pkt_cons;
1387
1388 while (sw_cons != sw_prod) {
1389 bnx2x_free_tx_pkt(bp, txdata, TX_BD(sw_cons),
1390 &pkts_compl, &bytes_compl);
1391 sw_cons++;
1392 }
1393
1394 netdev_tx_reset_queue(
1395 netdev_get_tx_queue(bp->dev,
1396 txdata->txq_index));
1397 }
1398 }
1399
1400 static void bnx2x_free_tx_skbs_cnic(struct bnx2x *bp)
1401 {
1402 int i;
1403
1404 for_each_tx_queue_cnic(bp, i) {
1405 bnx2x_free_tx_skbs_queue(&bp->fp[i]);
1406 }
1407 }
1408
1409 static void bnx2x_free_tx_skbs(struct bnx2x *bp)
1410 {
1411 int i;
1412
1413 for_each_eth_queue(bp, i) {
1414 bnx2x_free_tx_skbs_queue(&bp->fp[i]);
1415 }
1416 }
1417
1418 static void bnx2x_free_rx_bds(struct bnx2x_fastpath *fp)
1419 {
1420 struct bnx2x *bp = fp->bp;
1421 int i;
1422
1423 /* ring wasn't allocated */
1424 if (fp->rx_buf_ring == NULL)
1425 return;
1426
1427 for (i = 0; i < NUM_RX_BD; i++) {
1428 struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[i];
1429 u8 *data = rx_buf->data;
1430
1431 if (data == NULL)
1432 continue;
1433 dma_unmap_single(&bp->pdev->dev,
1434 dma_unmap_addr(rx_buf, mapping),
1435 fp->rx_buf_size, DMA_FROM_DEVICE);
1436
1437 rx_buf->data = NULL;
1438 bnx2x_frag_free(fp, data);
1439 }
1440 }
1441
1442 static void bnx2x_free_rx_skbs_cnic(struct bnx2x *bp)
1443 {
1444 int j;
1445
1446 for_each_rx_queue_cnic(bp, j) {
1447 bnx2x_free_rx_bds(&bp->fp[j]);
1448 }
1449 }
1450
1451 static void bnx2x_free_rx_skbs(struct bnx2x *bp)
1452 {
1453 int j;
1454
1455 for_each_eth_queue(bp, j) {
1456 struct bnx2x_fastpath *fp = &bp->fp[j];
1457
1458 bnx2x_free_rx_bds(fp);
1459
1460 if (!fp->disable_tpa)
1461 bnx2x_free_tpa_pool(bp, fp, MAX_AGG_QS(bp));
1462 }
1463 }
1464
1465 void bnx2x_free_skbs_cnic(struct bnx2x *bp)
1466 {
1467 bnx2x_free_tx_skbs_cnic(bp);
1468 bnx2x_free_rx_skbs_cnic(bp);
1469 }
1470
1471 void bnx2x_free_skbs(struct bnx2x *bp)
1472 {
1473 bnx2x_free_tx_skbs(bp);
1474 bnx2x_free_rx_skbs(bp);
1475 }
1476
1477 void bnx2x_update_max_mf_config(struct bnx2x *bp, u32 value)
1478 {
1479 /* load old values */
1480 u32 mf_cfg = bp->mf_config[BP_VN(bp)];
1481
1482 if (value != bnx2x_extract_max_cfg(bp, mf_cfg)) {
1483 /* leave all but MAX value */
1484 mf_cfg &= ~FUNC_MF_CFG_MAX_BW_MASK;
1485
1486 /* set new MAX value */
1487 mf_cfg |= (value << FUNC_MF_CFG_MAX_BW_SHIFT)
1488 & FUNC_MF_CFG_MAX_BW_MASK;
1489
1490 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW, mf_cfg);
1491 }
1492 }
1493
1494 /**
1495 * bnx2x_free_msix_irqs - free previously requested MSI-X IRQ vectors
1496 *
1497 * @bp: driver handle
1498 * @nvecs: number of vectors to be released
1499 */
1500 static void bnx2x_free_msix_irqs(struct bnx2x *bp, int nvecs)
1501 {
1502 int i, offset = 0;
1503
1504 if (nvecs == offset)
1505 return;
1506
1507 /* VFs don't have a default SB */
1508 if (IS_PF(bp)) {
1509 free_irq(bp->msix_table[offset].vector, bp->dev);
1510 DP(NETIF_MSG_IFDOWN, "released sp irq (%d)\n",
1511 bp->msix_table[offset].vector);
1512 offset++;
1513 }
1514
1515 if (CNIC_SUPPORT(bp)) {
1516 if (nvecs == offset)
1517 return;
1518 offset++;
1519 }
1520
1521 for_each_eth_queue(bp, i) {
1522 if (nvecs == offset)
1523 return;
1524 DP(NETIF_MSG_IFDOWN, "about to release fp #%d->%d irq\n",
1525 i, bp->msix_table[offset].vector);
1526
1527 free_irq(bp->msix_table[offset++].vector, &bp->fp[i]);
1528 }
1529 }
1530
1531 void bnx2x_free_irq(struct bnx2x *bp)
1532 {
1533 if (bp->flags & USING_MSIX_FLAG &&
1534 !(bp->flags & USING_SINGLE_MSIX_FLAG)) {
1535 int nvecs = BNX2X_NUM_ETH_QUEUES(bp) + CNIC_SUPPORT(bp);
1536
1537 /* vfs don't have a default status block */
1538 if (IS_PF(bp))
1539 nvecs++;
1540
1541 bnx2x_free_msix_irqs(bp, nvecs);
1542 } else {
1543 free_irq(bp->dev->irq, bp->dev);
1544 }
1545 }
1546
1547 int bnx2x_enable_msix(struct bnx2x *bp)
1548 {
1549 int msix_vec = 0, i, rc;
1550
1551 /* VFs don't have a default status block */
1552 if (IS_PF(bp)) {
1553 bp->msix_table[msix_vec].entry = msix_vec;
1554 BNX2X_DEV_INFO("msix_table[0].entry = %d (slowpath)\n",
1555 bp->msix_table[0].entry);
1556 msix_vec++;
1557 }
1558
1559 /* Cnic requires an msix vector for itself */
1560 if (CNIC_SUPPORT(bp)) {
1561 bp->msix_table[msix_vec].entry = msix_vec;
1562 BNX2X_DEV_INFO("msix_table[%d].entry = %d (CNIC)\n",
1563 msix_vec, bp->msix_table[msix_vec].entry);
1564 msix_vec++;
1565 }
1566
1567 /* We need separate vectors for ETH queues only (not FCoE) */
1568 for_each_eth_queue(bp, i) {
1569 bp->msix_table[msix_vec].entry = msix_vec;
1570 BNX2X_DEV_INFO("msix_table[%d].entry = %d (fastpath #%u)\n",
1571 msix_vec, msix_vec, i);
1572 msix_vec++;
1573 }
1574
1575 DP(BNX2X_MSG_SP, "about to request enable msix with %d vectors\n",
1576 msix_vec);
1577
1578 rc = pci_enable_msix(bp->pdev, &bp->msix_table[0], msix_vec);
1579
1580 /*
1581 * reconfigure number of tx/rx queues according to available
1582 * MSI-X vectors
1583 */
1584 if (rc >= BNX2X_MIN_MSIX_VEC_CNT(bp)) {
1585 /* how less vectors we will have? */
1586 int diff = msix_vec - rc;
1587
1588 BNX2X_DEV_INFO("Trying to use less MSI-X vectors: %d\n", rc);
1589
1590 rc = pci_enable_msix(bp->pdev, &bp->msix_table[0], rc);
1591
1592 if (rc) {
1593 BNX2X_DEV_INFO("MSI-X is not attainable rc %d\n", rc);
1594 goto no_msix;
1595 }
1596 /*
1597 * decrease number of queues by number of unallocated entries
1598 */
1599 bp->num_ethernet_queues -= diff;
1600 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
1601
1602 BNX2X_DEV_INFO("New queue configuration set: %d\n",
1603 bp->num_queues);
1604 } else if (rc > 0) {
1605 /* Get by with single vector */
1606 rc = pci_enable_msix(bp->pdev, &bp->msix_table[0], 1);
1607 if (rc) {
1608 BNX2X_DEV_INFO("Single MSI-X is not attainable rc %d\n",
1609 rc);
1610 goto no_msix;
1611 }
1612
1613 BNX2X_DEV_INFO("Using single MSI-X vector\n");
1614 bp->flags |= USING_SINGLE_MSIX_FLAG;
1615
1616 BNX2X_DEV_INFO("set number of queues to 1\n");
1617 bp->num_ethernet_queues = 1;
1618 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
1619 } else if (rc < 0) {
1620 BNX2X_DEV_INFO("MSI-X is not attainable rc %d\n", rc);
1621 goto no_msix;
1622 }
1623
1624 bp->flags |= USING_MSIX_FLAG;
1625
1626 return 0;
1627
1628 no_msix:
1629 /* fall to INTx if not enough memory */
1630 if (rc == -ENOMEM)
1631 bp->flags |= DISABLE_MSI_FLAG;
1632
1633 return rc;
1634 }
1635
1636 static int bnx2x_req_msix_irqs(struct bnx2x *bp)
1637 {
1638 int i, rc, offset = 0;
1639
1640 /* no default status block for vf */
1641 if (IS_PF(bp)) {
1642 rc = request_irq(bp->msix_table[offset++].vector,
1643 bnx2x_msix_sp_int, 0,
1644 bp->dev->name, bp->dev);
1645 if (rc) {
1646 BNX2X_ERR("request sp irq failed\n");
1647 return -EBUSY;
1648 }
1649 }
1650
1651 if (CNIC_SUPPORT(bp))
1652 offset++;
1653
1654 for_each_eth_queue(bp, i) {
1655 struct bnx2x_fastpath *fp = &bp->fp[i];
1656 snprintf(fp->name, sizeof(fp->name), "%s-fp-%d",
1657 bp->dev->name, i);
1658
1659 rc = request_irq(bp->msix_table[offset].vector,
1660 bnx2x_msix_fp_int, 0, fp->name, fp);
1661 if (rc) {
1662 BNX2X_ERR("request fp #%d irq (%d) failed rc %d\n", i,
1663 bp->msix_table[offset].vector, rc);
1664 bnx2x_free_msix_irqs(bp, offset);
1665 return -EBUSY;
1666 }
1667
1668 offset++;
1669 }
1670
1671 i = BNX2X_NUM_ETH_QUEUES(bp);
1672 if (IS_PF(bp)) {
1673 offset = 1 + CNIC_SUPPORT(bp);
1674 netdev_info(bp->dev,
1675 "using MSI-X IRQs: sp %d fp[%d] %d ... fp[%d] %d\n",
1676 bp->msix_table[0].vector,
1677 0, bp->msix_table[offset].vector,
1678 i - 1, bp->msix_table[offset + i - 1].vector);
1679 } else {
1680 offset = CNIC_SUPPORT(bp);
1681 netdev_info(bp->dev,
1682 "using MSI-X IRQs: fp[%d] %d ... fp[%d] %d\n",
1683 0, bp->msix_table[offset].vector,
1684 i - 1, bp->msix_table[offset + i - 1].vector);
1685 }
1686 return 0;
1687 }
1688
1689 int bnx2x_enable_msi(struct bnx2x *bp)
1690 {
1691 int rc;
1692
1693 rc = pci_enable_msi(bp->pdev);
1694 if (rc) {
1695 BNX2X_DEV_INFO("MSI is not attainable\n");
1696 return -1;
1697 }
1698 bp->flags |= USING_MSI_FLAG;
1699
1700 return 0;
1701 }
1702
1703 static int bnx2x_req_irq(struct bnx2x *bp)
1704 {
1705 unsigned long flags;
1706 unsigned int irq;
1707
1708 if (bp->flags & (USING_MSI_FLAG | USING_MSIX_FLAG))
1709 flags = 0;
1710 else
1711 flags = IRQF_SHARED;
1712
1713 if (bp->flags & USING_MSIX_FLAG)
1714 irq = bp->msix_table[0].vector;
1715 else
1716 irq = bp->pdev->irq;
1717
1718 return request_irq(irq, bnx2x_interrupt, flags, bp->dev->name, bp->dev);
1719 }
1720
1721 static int bnx2x_setup_irqs(struct bnx2x *bp)
1722 {
1723 int rc = 0;
1724 if (bp->flags & USING_MSIX_FLAG &&
1725 !(bp->flags & USING_SINGLE_MSIX_FLAG)) {
1726 rc = bnx2x_req_msix_irqs(bp);
1727 if (rc)
1728 return rc;
1729 } else {
1730 rc = bnx2x_req_irq(bp);
1731 if (rc) {
1732 BNX2X_ERR("IRQ request failed rc %d, aborting\n", rc);
1733 return rc;
1734 }
1735 if (bp->flags & USING_MSI_FLAG) {
1736 bp->dev->irq = bp->pdev->irq;
1737 netdev_info(bp->dev, "using MSI IRQ %d\n",
1738 bp->dev->irq);
1739 }
1740 if (bp->flags & USING_MSIX_FLAG) {
1741 bp->dev->irq = bp->msix_table[0].vector;
1742 netdev_info(bp->dev, "using MSIX IRQ %d\n",
1743 bp->dev->irq);
1744 }
1745 }
1746
1747 return 0;
1748 }
1749
1750 static void bnx2x_napi_enable_cnic(struct bnx2x *bp)
1751 {
1752 int i;
1753
1754 for_each_rx_queue_cnic(bp, i)
1755 napi_enable(&bnx2x_fp(bp, i, napi));
1756 }
1757
1758 static void bnx2x_napi_enable(struct bnx2x *bp)
1759 {
1760 int i;
1761
1762 for_each_eth_queue(bp, i)
1763 napi_enable(&bnx2x_fp(bp, i, napi));
1764 }
1765
1766 static void bnx2x_napi_disable_cnic(struct bnx2x *bp)
1767 {
1768 int i;
1769
1770 for_each_rx_queue_cnic(bp, i)
1771 napi_disable(&bnx2x_fp(bp, i, napi));
1772 }
1773
1774 static void bnx2x_napi_disable(struct bnx2x *bp)
1775 {
1776 int i;
1777
1778 for_each_eth_queue(bp, i)
1779 napi_disable(&bnx2x_fp(bp, i, napi));
1780 }
1781
1782 void bnx2x_netif_start(struct bnx2x *bp)
1783 {
1784 if (netif_running(bp->dev)) {
1785 bnx2x_napi_enable(bp);
1786 if (CNIC_LOADED(bp))
1787 bnx2x_napi_enable_cnic(bp);
1788 bnx2x_int_enable(bp);
1789 if (bp->state == BNX2X_STATE_OPEN)
1790 netif_tx_wake_all_queues(bp->dev);
1791 }
1792 }
1793
1794 void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw)
1795 {
1796 bnx2x_int_disable_sync(bp, disable_hw);
1797 bnx2x_napi_disable(bp);
1798 if (CNIC_LOADED(bp))
1799 bnx2x_napi_disable_cnic(bp);
1800 }
1801
1802 u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb)
1803 {
1804 struct bnx2x *bp = netdev_priv(dev);
1805
1806 if (CNIC_LOADED(bp) && !NO_FCOE(bp)) {
1807 struct ethhdr *hdr = (struct ethhdr *)skb->data;
1808 u16 ether_type = ntohs(hdr->h_proto);
1809
1810 /* Skip VLAN tag if present */
1811 if (ether_type == ETH_P_8021Q) {
1812 struct vlan_ethhdr *vhdr =
1813 (struct vlan_ethhdr *)skb->data;
1814
1815 ether_type = ntohs(vhdr->h_vlan_encapsulated_proto);
1816 }
1817
1818 /* If ethertype is FCoE or FIP - use FCoE ring */
1819 if ((ether_type == ETH_P_FCOE) || (ether_type == ETH_P_FIP))
1820 return bnx2x_fcoe_tx(bp, txq_index);
1821 }
1822
1823 /* select a non-FCoE queue */
1824 return __skb_tx_hash(dev, skb, BNX2X_NUM_ETH_QUEUES(bp));
1825 }
1826
1827 void bnx2x_set_num_queues(struct bnx2x *bp)
1828 {
1829 /* RSS queues */
1830 bp->num_ethernet_queues = bnx2x_calc_num_queues(bp);
1831
1832 /* override in STORAGE SD modes */
1833 if (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))
1834 bp->num_ethernet_queues = 1;
1835
1836 /* Add special queues */
1837 bp->num_cnic_queues = CNIC_SUPPORT(bp); /* For FCOE */
1838 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
1839
1840 BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues);
1841 }
1842
1843 /**
1844 * bnx2x_set_real_num_queues - configure netdev->real_num_[tx,rx]_queues
1845 *
1846 * @bp: Driver handle
1847 *
1848 * We currently support for at most 16 Tx queues for each CoS thus we will
1849 * allocate a multiple of 16 for ETH L2 rings according to the value of the
1850 * bp->max_cos.
1851 *
1852 * If there is an FCoE L2 queue the appropriate Tx queue will have the next
1853 * index after all ETH L2 indices.
1854 *
1855 * If the actual number of Tx queues (for each CoS) is less than 16 then there
1856 * will be the holes at the end of each group of 16 ETh L2 indices (0..15,
1857 * 16..31,...) with indicies that are not coupled with any real Tx queue.
1858 *
1859 * The proper configuration of skb->queue_mapping is handled by
1860 * bnx2x_select_queue() and __skb_tx_hash().
1861 *
1862 * bnx2x_setup_tc() takes care of the proper TC mappings so that __skb_tx_hash()
1863 * will return a proper Tx index if TC is enabled (netdev->num_tc > 0).
1864 */
1865 static int bnx2x_set_real_num_queues(struct bnx2x *bp, int include_cnic)
1866 {
1867 int rc, tx, rx;
1868
1869 tx = BNX2X_NUM_ETH_QUEUES(bp) * bp->max_cos;
1870 rx = BNX2X_NUM_ETH_QUEUES(bp);
1871
1872 /* account for fcoe queue */
1873 if (include_cnic && !NO_FCOE(bp)) {
1874 rx++;
1875 tx++;
1876 }
1877
1878 rc = netif_set_real_num_tx_queues(bp->dev, tx);
1879 if (rc) {
1880 BNX2X_ERR("Failed to set real number of Tx queues: %d\n", rc);
1881 return rc;
1882 }
1883 rc = netif_set_real_num_rx_queues(bp->dev, rx);
1884 if (rc) {
1885 BNX2X_ERR("Failed to set real number of Rx queues: %d\n", rc);
1886 return rc;
1887 }
1888
1889 DP(NETIF_MSG_IFUP, "Setting real num queues to (tx, rx) (%d, %d)\n",
1890 tx, rx);
1891
1892 return rc;
1893 }
1894
1895 static void bnx2x_set_rx_buf_size(struct bnx2x *bp)
1896 {
1897 int i;
1898
1899 for_each_queue(bp, i) {
1900 struct bnx2x_fastpath *fp = &bp->fp[i];
1901 u32 mtu;
1902
1903 /* Always use a mini-jumbo MTU for the FCoE L2 ring */
1904 if (IS_FCOE_IDX(i))
1905 /*
1906 * Although there are no IP frames expected to arrive to
1907 * this ring we still want to add an
1908 * IP_HEADER_ALIGNMENT_PADDING to prevent a buffer
1909 * overrun attack.
1910 */
1911 mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
1912 else
1913 mtu = bp->dev->mtu;
1914 fp->rx_buf_size = BNX2X_FW_RX_ALIGN_START +
1915 IP_HEADER_ALIGNMENT_PADDING +
1916 ETH_OVREHEAD +
1917 mtu +
1918 BNX2X_FW_RX_ALIGN_END;
1919 /* Note : rx_buf_size doesnt take into account NET_SKB_PAD */
1920 if (fp->rx_buf_size + NET_SKB_PAD <= PAGE_SIZE)
1921 fp->rx_frag_size = fp->rx_buf_size + NET_SKB_PAD;
1922 else
1923 fp->rx_frag_size = 0;
1924 }
1925 }
1926
1927 static int bnx2x_init_rss_pf(struct bnx2x *bp)
1928 {
1929 int i;
1930 u8 num_eth_queues = BNX2X_NUM_ETH_QUEUES(bp);
1931
1932 /* Prepare the initial contents fo the indirection table if RSS is
1933 * enabled
1934 */
1935 for (i = 0; i < sizeof(bp->rss_conf_obj.ind_table); i++)
1936 bp->rss_conf_obj.ind_table[i] =
1937 bp->fp->cl_id +
1938 ethtool_rxfh_indir_default(i, num_eth_queues);
1939
1940 /*
1941 * For 57710 and 57711 SEARCHER configuration (rss_keys) is
1942 * per-port, so if explicit configuration is needed , do it only
1943 * for a PMF.
1944 *
1945 * For 57712 and newer on the other hand it's a per-function
1946 * configuration.
1947 */
1948 return bnx2x_config_rss_eth(bp, bp->port.pmf || !CHIP_IS_E1x(bp));
1949 }
1950
1951 int bnx2x_config_rss_pf(struct bnx2x *bp, struct bnx2x_rss_config_obj *rss_obj,
1952 bool config_hash)
1953 {
1954 struct bnx2x_config_rss_params params = {NULL};
1955
1956 /* Although RSS is meaningless when there is a single HW queue we
1957 * still need it enabled in order to have HW Rx hash generated.
1958 *
1959 * if (!is_eth_multi(bp))
1960 * bp->multi_mode = ETH_RSS_MODE_DISABLED;
1961 */
1962
1963 params.rss_obj = rss_obj;
1964
1965 __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
1966
1967 __set_bit(BNX2X_RSS_MODE_REGULAR, &params.rss_flags);
1968
1969 /* RSS configuration */
1970 __set_bit(BNX2X_RSS_IPV4, &params.rss_flags);
1971 __set_bit(BNX2X_RSS_IPV4_TCP, &params.rss_flags);
1972 __set_bit(BNX2X_RSS_IPV6, &params.rss_flags);
1973 __set_bit(BNX2X_RSS_IPV6_TCP, &params.rss_flags);
1974 if (rss_obj->udp_rss_v4)
1975 __set_bit(BNX2X_RSS_IPV4_UDP, &params.rss_flags);
1976 if (rss_obj->udp_rss_v6)
1977 __set_bit(BNX2X_RSS_IPV6_UDP, &params.rss_flags);
1978
1979 /* Hash bits */
1980 params.rss_result_mask = MULTI_MASK;
1981
1982 memcpy(params.ind_table, rss_obj->ind_table, sizeof(params.ind_table));
1983
1984 if (config_hash) {
1985 /* RSS keys */
1986 prandom_bytes(params.rss_key, sizeof(params.rss_key));
1987 __set_bit(BNX2X_RSS_SET_SRCH, &params.rss_flags);
1988 }
1989
1990 return bnx2x_config_rss(bp, &params);
1991 }
1992
1993 static int bnx2x_init_hw(struct bnx2x *bp, u32 load_code)
1994 {
1995 struct bnx2x_func_state_params func_params = {NULL};
1996
1997 /* Prepare parameters for function state transitions */
1998 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1999
2000 func_params.f_obj = &bp->func_obj;
2001 func_params.cmd = BNX2X_F_CMD_HW_INIT;
2002
2003 func_params.params.hw_init.load_phase = load_code;
2004
2005 return bnx2x_func_state_change(bp, &func_params);
2006 }
2007
2008 /*
2009 * Cleans the object that have internal lists without sending
2010 * ramrods. Should be run when interrutps are disabled.
2011 */
2012 static void bnx2x_squeeze_objects(struct bnx2x *bp)
2013 {
2014 int rc;
2015 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
2016 struct bnx2x_mcast_ramrod_params rparam = {NULL};
2017 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
2018
2019 /***************** Cleanup MACs' object first *************************/
2020
2021 /* Wait for completion of requested */
2022 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
2023 /* Perform a dry cleanup */
2024 __set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
2025
2026 /* Clean ETH primary MAC */
2027 __set_bit(BNX2X_ETH_MAC, &vlan_mac_flags);
2028 rc = mac_obj->delete_all(bp, &bp->sp_objs->mac_obj, &vlan_mac_flags,
2029 &ramrod_flags);
2030 if (rc != 0)
2031 BNX2X_ERR("Failed to clean ETH MACs: %d\n", rc);
2032
2033 /* Cleanup UC list */
2034 vlan_mac_flags = 0;
2035 __set_bit(BNX2X_UC_LIST_MAC, &vlan_mac_flags);
2036 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags,
2037 &ramrod_flags);
2038 if (rc != 0)
2039 BNX2X_ERR("Failed to clean UC list MACs: %d\n", rc);
2040
2041 /***************** Now clean mcast object *****************************/
2042 rparam.mcast_obj = &bp->mcast_obj;
2043 __set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
2044
2045 /* Add a DEL command... */
2046 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
2047 if (rc < 0)
2048 BNX2X_ERR("Failed to add a new DEL command to a multi-cast object: %d\n",
2049 rc);
2050
2051 /* ...and wait until all pending commands are cleared */
2052 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
2053 while (rc != 0) {
2054 if (rc < 0) {
2055 BNX2X_ERR("Failed to clean multi-cast object: %d\n",
2056 rc);
2057 return;
2058 }
2059
2060 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
2061 }
2062 }
2063
2064 #ifndef BNX2X_STOP_ON_ERROR
2065 #define LOAD_ERROR_EXIT(bp, label) \
2066 do { \
2067 (bp)->state = BNX2X_STATE_ERROR; \
2068 goto label; \
2069 } while (0)
2070
2071 #define LOAD_ERROR_EXIT_CNIC(bp, label) \
2072 do { \
2073 bp->cnic_loaded = false; \
2074 goto label; \
2075 } while (0)
2076 #else /*BNX2X_STOP_ON_ERROR*/
2077 #define LOAD_ERROR_EXIT(bp, label) \
2078 do { \
2079 (bp)->state = BNX2X_STATE_ERROR; \
2080 (bp)->panic = 1; \
2081 return -EBUSY; \
2082 } while (0)
2083 #define LOAD_ERROR_EXIT_CNIC(bp, label) \
2084 do { \
2085 bp->cnic_loaded = false; \
2086 (bp)->panic = 1; \
2087 return -EBUSY; \
2088 } while (0)
2089 #endif /*BNX2X_STOP_ON_ERROR*/
2090
2091 static void bnx2x_free_fw_stats_mem(struct bnx2x *bp)
2092 {
2093 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
2094 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
2095 return;
2096 }
2097
2098 static int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
2099 {
2100 int num_groups, vf_headroom = 0;
2101 int is_fcoe_stats = NO_FCOE(bp) ? 0 : 1;
2102
2103 /* number of queues for statistics is number of eth queues + FCoE */
2104 u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe_stats;
2105
2106 /* Total number of FW statistics requests =
2107 * 1 for port stats + 1 for PF stats + potential 2 for FCoE (fcoe proper
2108 * and fcoe l2 queue) stats + num of queues (which includes another 1
2109 * for fcoe l2 queue if applicable)
2110 */
2111 bp->fw_stats_num = 2 + is_fcoe_stats + num_queue_stats;
2112
2113 /* vf stats appear in the request list, but their data is allocated by
2114 * the VFs themselves. We don't include them in the bp->fw_stats_num as
2115 * it is used to determine where to place the vf stats queries in the
2116 * request struct
2117 */
2118 if (IS_SRIOV(bp))
2119 vf_headroom = bnx2x_vf_headroom(bp);
2120
2121 /* Request is built from stats_query_header and an array of
2122 * stats_query_cmd_group each of which contains
2123 * STATS_QUERY_CMD_COUNT rules. The real number or requests is
2124 * configured in the stats_query_header.
2125 */
2126 num_groups =
2127 (((bp->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT) +
2128 (((bp->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT) ?
2129 1 : 0));
2130
2131 DP(BNX2X_MSG_SP, "stats fw_stats_num %d, vf headroom %d, num_groups %d\n",
2132 bp->fw_stats_num, vf_headroom, num_groups);
2133 bp->fw_stats_req_sz = sizeof(struct stats_query_header) +
2134 num_groups * sizeof(struct stats_query_cmd_group);
2135
2136 /* Data for statistics requests + stats_counter
2137 * stats_counter holds per-STORM counters that are incremented
2138 * when STORM has finished with the current request.
2139 * memory for FCoE offloaded statistics are counted anyway,
2140 * even if they will not be sent.
2141 * VF stats are not accounted for here as the data of VF stats is stored
2142 * in memory allocated by the VF, not here.
2143 */
2144 bp->fw_stats_data_sz = sizeof(struct per_port_stats) +
2145 sizeof(struct per_pf_stats) +
2146 sizeof(struct fcoe_statistics_params) +
2147 sizeof(struct per_queue_stats) * num_queue_stats +
2148 sizeof(struct stats_counter);
2149
2150 BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping,
2151 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
2152
2153 /* Set shortcuts */
2154 bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats;
2155 bp->fw_stats_req_mapping = bp->fw_stats_mapping;
2156 bp->fw_stats_data = (struct bnx2x_fw_stats_data *)
2157 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz);
2158 bp->fw_stats_data_mapping = bp->fw_stats_mapping +
2159 bp->fw_stats_req_sz;
2160
2161 DP(BNX2X_MSG_SP, "statistics request base address set to %x %x",
2162 U64_HI(bp->fw_stats_req_mapping),
2163 U64_LO(bp->fw_stats_req_mapping));
2164 DP(BNX2X_MSG_SP, "statistics data base address set to %x %x",
2165 U64_HI(bp->fw_stats_data_mapping),
2166 U64_LO(bp->fw_stats_data_mapping));
2167 return 0;
2168
2169 alloc_mem_err:
2170 bnx2x_free_fw_stats_mem(bp);
2171 BNX2X_ERR("Can't allocate FW stats memory\n");
2172 return -ENOMEM;
2173 }
2174
2175 /* send load request to mcp and analyze response */
2176 static int bnx2x_nic_load_request(struct bnx2x *bp, u32 *load_code)
2177 {
2178 /* init fw_seq */
2179 bp->fw_seq =
2180 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
2181 DRV_MSG_SEQ_NUMBER_MASK);
2182 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
2183
2184 /* Get current FW pulse sequence */
2185 bp->fw_drv_pulse_wr_seq =
2186 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb) &
2187 DRV_PULSE_SEQ_MASK);
2188 BNX2X_DEV_INFO("drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq);
2189
2190 /* load request */
2191 (*load_code) = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
2192 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
2193
2194 /* if mcp fails to respond we must abort */
2195 if (!(*load_code)) {
2196 BNX2X_ERR("MCP response failure, aborting\n");
2197 return -EBUSY;
2198 }
2199
2200 /* If mcp refused (e.g. other port is in diagnostic mode) we
2201 * must abort
2202 */
2203 if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
2204 BNX2X_ERR("MCP refused load request, aborting\n");
2205 return -EBUSY;
2206 }
2207 return 0;
2208 }
2209
2210 /* check whether another PF has already loaded FW to chip. In
2211 * virtualized environments a pf from another VM may have already
2212 * initialized the device including loading FW
2213 */
2214 int bnx2x_nic_load_analyze_req(struct bnx2x *bp, u32 load_code)
2215 {
2216 /* is another pf loaded on this engine? */
2217 if (load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP &&
2218 load_code != FW_MSG_CODE_DRV_LOAD_COMMON) {
2219 /* build my FW version dword */
2220 u32 my_fw = (BCM_5710_FW_MAJOR_VERSION) +
2221 (BCM_5710_FW_MINOR_VERSION << 8) +
2222 (BCM_5710_FW_REVISION_VERSION << 16) +
2223 (BCM_5710_FW_ENGINEERING_VERSION << 24);
2224
2225 /* read loaded FW from chip */
2226 u32 loaded_fw = REG_RD(bp, XSEM_REG_PRAM);
2227
2228 DP(BNX2X_MSG_SP, "loaded fw %x, my fw %x\n",
2229 loaded_fw, my_fw);
2230
2231 /* abort nic load if version mismatch */
2232 if (my_fw != loaded_fw) {
2233 BNX2X_ERR("bnx2x with FW %x was already loaded which mismatches my %x FW. aborting\n",
2234 loaded_fw, my_fw);
2235 return -EBUSY;
2236 }
2237 }
2238 return 0;
2239 }
2240
2241 /* returns the "mcp load_code" according to global load_count array */
2242 static int bnx2x_nic_load_no_mcp(struct bnx2x *bp, int port)
2243 {
2244 int path = BP_PATH(bp);
2245
2246 DP(NETIF_MSG_IFUP, "NO MCP - load counts[%d] %d, %d, %d\n",
2247 path, load_count[path][0], load_count[path][1],
2248 load_count[path][2]);
2249 load_count[path][0]++;
2250 load_count[path][1 + port]++;
2251 DP(NETIF_MSG_IFUP, "NO MCP - new load counts[%d] %d, %d, %d\n",
2252 path, load_count[path][0], load_count[path][1],
2253 load_count[path][2]);
2254 if (load_count[path][0] == 1)
2255 return FW_MSG_CODE_DRV_LOAD_COMMON;
2256 else if (load_count[path][1 + port] == 1)
2257 return FW_MSG_CODE_DRV_LOAD_PORT;
2258 else
2259 return FW_MSG_CODE_DRV_LOAD_FUNCTION;
2260 }
2261
2262 /* mark PMF if applicable */
2263 static void bnx2x_nic_load_pmf(struct bnx2x *bp, u32 load_code)
2264 {
2265 if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2266 (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
2267 (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
2268 bp->port.pmf = 1;
2269 /* We need the barrier to ensure the ordering between the
2270 * writing to bp->port.pmf here and reading it from the
2271 * bnx2x_periodic_task().
2272 */
2273 smp_mb();
2274 } else {
2275 bp->port.pmf = 0;
2276 }
2277
2278 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2279 }
2280
2281 static void bnx2x_nic_load_afex_dcc(struct bnx2x *bp, int load_code)
2282 {
2283 if (((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2284 (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP)) &&
2285 (bp->common.shmem2_base)) {
2286 if (SHMEM2_HAS(bp, dcc_support))
2287 SHMEM2_WR(bp, dcc_support,
2288 (SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV |
2289 SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV));
2290 if (SHMEM2_HAS(bp, afex_driver_support))
2291 SHMEM2_WR(bp, afex_driver_support,
2292 SHMEM_AFEX_SUPPORTED_VERSION_ONE);
2293 }
2294
2295 /* Set AFEX default VLAN tag to an invalid value */
2296 bp->afex_def_vlan_tag = -1;
2297 }
2298
2299 /**
2300 * bnx2x_bz_fp - zero content of the fastpath structure.
2301 *
2302 * @bp: driver handle
2303 * @index: fastpath index to be zeroed
2304 *
2305 * Makes sure the contents of the bp->fp[index].napi is kept
2306 * intact.
2307 */
2308 static void bnx2x_bz_fp(struct bnx2x *bp, int index)
2309 {
2310 struct bnx2x_fastpath *fp = &bp->fp[index];
2311
2312 int cos;
2313 struct napi_struct orig_napi = fp->napi;
2314 struct bnx2x_agg_info *orig_tpa_info = fp->tpa_info;
2315 /* bzero bnx2x_fastpath contents */
2316 if (fp->tpa_info)
2317 memset(fp->tpa_info, 0, ETH_MAX_AGGREGATION_QUEUES_E1H_E2 *
2318 sizeof(struct bnx2x_agg_info));
2319 memset(fp, 0, sizeof(*fp));
2320
2321 /* Restore the NAPI object as it has been already initialized */
2322 fp->napi = orig_napi;
2323 fp->tpa_info = orig_tpa_info;
2324 fp->bp = bp;
2325 fp->index = index;
2326 if (IS_ETH_FP(fp))
2327 fp->max_cos = bp->max_cos;
2328 else
2329 /* Special queues support only one CoS */
2330 fp->max_cos = 1;
2331
2332 /* Init txdata pointers */
2333 if (IS_FCOE_FP(fp))
2334 fp->txdata_ptr[0] = &bp->bnx2x_txq[FCOE_TXQ_IDX(bp)];
2335 if (IS_ETH_FP(fp))
2336 for_each_cos_in_tx_queue(fp, cos)
2337 fp->txdata_ptr[cos] = &bp->bnx2x_txq[cos *
2338 BNX2X_NUM_ETH_QUEUES(bp) + index];
2339
2340 /*
2341 * set the tpa flag for each queue. The tpa flag determines the queue
2342 * minimal size so it must be set prior to queue memory allocation
2343 */
2344 fp->disable_tpa = !(bp->flags & TPA_ENABLE_FLAG ||
2345 (bp->flags & GRO_ENABLE_FLAG &&
2346 bnx2x_mtu_allows_gro(bp->dev->mtu)));
2347 if (bp->flags & TPA_ENABLE_FLAG)
2348 fp->mode = TPA_MODE_LRO;
2349 else if (bp->flags & GRO_ENABLE_FLAG)
2350 fp->mode = TPA_MODE_GRO;
2351
2352 /* We don't want TPA on an FCoE L2 ring */
2353 if (IS_FCOE_FP(fp))
2354 fp->disable_tpa = 1;
2355 }
2356
2357 int bnx2x_load_cnic(struct bnx2x *bp)
2358 {
2359 int i, rc, port = BP_PORT(bp);
2360
2361 DP(NETIF_MSG_IFUP, "Starting CNIC-related load\n");
2362
2363 mutex_init(&bp->cnic_mutex);
2364
2365 if (IS_PF(bp)) {
2366 rc = bnx2x_alloc_mem_cnic(bp);
2367 if (rc) {
2368 BNX2X_ERR("Unable to allocate bp memory for cnic\n");
2369 LOAD_ERROR_EXIT_CNIC(bp, load_error_cnic0);
2370 }
2371 }
2372
2373 rc = bnx2x_alloc_fp_mem_cnic(bp);
2374 if (rc) {
2375 BNX2X_ERR("Unable to allocate memory for cnic fps\n");
2376 LOAD_ERROR_EXIT_CNIC(bp, load_error_cnic0);
2377 }
2378
2379 /* Update the number of queues with the cnic queues */
2380 rc = bnx2x_set_real_num_queues(bp, 1);
2381 if (rc) {
2382 BNX2X_ERR("Unable to set real_num_queues including cnic\n");
2383 LOAD_ERROR_EXIT_CNIC(bp, load_error_cnic0);
2384 }
2385
2386 /* Add all CNIC NAPI objects */
2387 bnx2x_add_all_napi_cnic(bp);
2388 DP(NETIF_MSG_IFUP, "cnic napi added\n");
2389 bnx2x_napi_enable_cnic(bp);
2390
2391 rc = bnx2x_init_hw_func_cnic(bp);
2392 if (rc)
2393 LOAD_ERROR_EXIT_CNIC(bp, load_error_cnic1);
2394
2395 bnx2x_nic_init_cnic(bp);
2396
2397 if (IS_PF(bp)) {
2398 /* Enable Timer scan */
2399 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 1);
2400
2401 /* setup cnic queues */
2402 for_each_cnic_queue(bp, i) {
2403 rc = bnx2x_setup_queue(bp, &bp->fp[i], 0);
2404 if (rc) {
2405 BNX2X_ERR("Queue setup failed\n");
2406 LOAD_ERROR_EXIT(bp, load_error_cnic2);
2407 }
2408 }
2409 }
2410
2411 /* Initialize Rx filter. */
2412 netif_addr_lock_bh(bp->dev);
2413 bnx2x_set_rx_mode(bp->dev);
2414 netif_addr_unlock_bh(bp->dev);
2415
2416 /* re-read iscsi info */
2417 bnx2x_get_iscsi_info(bp);
2418 bnx2x_setup_cnic_irq_info(bp);
2419 bnx2x_setup_cnic_info(bp);
2420 bp->cnic_loaded = true;
2421 if (bp->state == BNX2X_STATE_OPEN)
2422 bnx2x_cnic_notify(bp, CNIC_CTL_START_CMD);
2423
2424
2425 DP(NETIF_MSG_IFUP, "Ending successfully CNIC-related load\n");
2426
2427 return 0;
2428
2429 #ifndef BNX2X_STOP_ON_ERROR
2430 load_error_cnic2:
2431 /* Disable Timer scan */
2432 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
2433
2434 load_error_cnic1:
2435 bnx2x_napi_disable_cnic(bp);
2436 /* Update the number of queues without the cnic queues */
2437 rc = bnx2x_set_real_num_queues(bp, 0);
2438 if (rc)
2439 BNX2X_ERR("Unable to set real_num_queues not including cnic\n");
2440 load_error_cnic0:
2441 BNX2X_ERR("CNIC-related load failed\n");
2442 bnx2x_free_fp_mem_cnic(bp);
2443 bnx2x_free_mem_cnic(bp);
2444 return rc;
2445 #endif /* ! BNX2X_STOP_ON_ERROR */
2446 }
2447
2448 /* must be called with rtnl_lock */
2449 int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
2450 {
2451 int port = BP_PORT(bp);
2452 int i, rc = 0, load_code = 0;
2453
2454 DP(NETIF_MSG_IFUP, "Starting NIC load\n");
2455 DP(NETIF_MSG_IFUP,
2456 "CNIC is %s\n", CNIC_ENABLED(bp) ? "enabled" : "disabled");
2457
2458 #ifdef BNX2X_STOP_ON_ERROR
2459 if (unlikely(bp->panic)) {
2460 BNX2X_ERR("Can't load NIC when there is panic\n");
2461 return -EPERM;
2462 }
2463 #endif
2464
2465 bp->state = BNX2X_STATE_OPENING_WAIT4_LOAD;
2466
2467 memset(&bp->last_reported_link, 0, sizeof(bp->last_reported_link));
2468 __set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
2469 &bp->last_reported_link.link_report_flags);
2470
2471 if (IS_PF(bp))
2472 /* must be called before memory allocation and HW init */
2473 bnx2x_ilt_set_info(bp);
2474
2475 /*
2476 * Zero fastpath structures preserving invariants like napi, which are
2477 * allocated only once, fp index, max_cos, bp pointer.
2478 * Also set fp->disable_tpa and txdata_ptr.
2479 */
2480 DP(NETIF_MSG_IFUP, "num queues: %d", bp->num_queues);
2481 for_each_queue(bp, i)
2482 bnx2x_bz_fp(bp, i);
2483 memset(bp->bnx2x_txq, 0, (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS +
2484 bp->num_cnic_queues) *
2485 sizeof(struct bnx2x_fp_txdata));
2486
2487 bp->fcoe_init = false;
2488
2489 /* Set the receive queues buffer size */
2490 bnx2x_set_rx_buf_size(bp);
2491
2492 if (IS_PF(bp)) {
2493 rc = bnx2x_alloc_mem(bp);
2494 if (rc) {
2495 BNX2X_ERR("Unable to allocate bp memory\n");
2496 return rc;
2497 }
2498 }
2499
2500 /* Allocated memory for FW statistics */
2501 if (bnx2x_alloc_fw_stats_mem(bp))
2502 LOAD_ERROR_EXIT(bp, load_error0);
2503
2504 /* need to be done after alloc mem, since it's self adjusting to amount
2505 * of memory available for RSS queues
2506 */
2507 rc = bnx2x_alloc_fp_mem(bp);
2508 if (rc) {
2509 BNX2X_ERR("Unable to allocate memory for fps\n");
2510 LOAD_ERROR_EXIT(bp, load_error0);
2511 }
2512
2513 /* request pf to initialize status blocks */
2514 if (IS_VF(bp)) {
2515 rc = bnx2x_vfpf_init(bp);
2516 if (rc)
2517 LOAD_ERROR_EXIT(bp, load_error0);
2518 }
2519
2520 /* As long as bnx2x_alloc_mem() may possibly update
2521 * bp->num_queues, bnx2x_set_real_num_queues() should always
2522 * come after it. At this stage cnic queues are not counted.
2523 */
2524 rc = bnx2x_set_real_num_queues(bp, 0);
2525 if (rc) {
2526 BNX2X_ERR("Unable to set real_num_queues\n");
2527 LOAD_ERROR_EXIT(bp, load_error0);
2528 }
2529
2530 /* configure multi cos mappings in kernel.
2531 * this configuration may be overriden by a multi class queue discipline
2532 * or by a dcbx negotiation result.
2533 */
2534 bnx2x_setup_tc(bp->dev, bp->max_cos);
2535
2536 /* Add all NAPI objects */
2537 bnx2x_add_all_napi(bp);
2538 DP(NETIF_MSG_IFUP, "napi added\n");
2539 bnx2x_napi_enable(bp);
2540
2541 if (IS_PF(bp)) {
2542 /* set pf load just before approaching the MCP */
2543 bnx2x_set_pf_load(bp);
2544
2545 /* if mcp exists send load request and analyze response */
2546 if (!BP_NOMCP(bp)) {
2547 /* attempt to load pf */
2548 rc = bnx2x_nic_load_request(bp, &load_code);
2549 if (rc)
2550 LOAD_ERROR_EXIT(bp, load_error1);
2551
2552 /* what did mcp say? */
2553 rc = bnx2x_nic_load_analyze_req(bp, load_code);
2554 if (rc) {
2555 bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
2556 LOAD_ERROR_EXIT(bp, load_error2);
2557 }
2558 } else {
2559 load_code = bnx2x_nic_load_no_mcp(bp, port);
2560 }
2561
2562 /* mark pmf if applicable */
2563 bnx2x_nic_load_pmf(bp, load_code);
2564
2565 /* Init Function state controlling object */
2566 bnx2x__init_func_obj(bp);
2567
2568 /* Initialize HW */
2569 rc = bnx2x_init_hw(bp, load_code);
2570 if (rc) {
2571 BNX2X_ERR("HW init failed, aborting\n");
2572 bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
2573 LOAD_ERROR_EXIT(bp, load_error2);
2574 }
2575 }
2576
2577 /* Connect to IRQs */
2578 rc = bnx2x_setup_irqs(bp);
2579 if (rc) {
2580 BNX2X_ERR("setup irqs failed\n");
2581 if (IS_PF(bp))
2582 bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
2583 LOAD_ERROR_EXIT(bp, load_error2);
2584 }
2585
2586 /* Setup NIC internals and enable interrupts */
2587 bnx2x_nic_init(bp, load_code);
2588
2589 /* Init per-function objects */
2590 if (IS_PF(bp)) {
2591 bnx2x_init_bp_objs(bp);
2592 bnx2x_iov_nic_init(bp);
2593
2594 /* Set AFEX default VLAN tag to an invalid value */
2595 bp->afex_def_vlan_tag = -1;
2596 bnx2x_nic_load_afex_dcc(bp, load_code);
2597 bp->state = BNX2X_STATE_OPENING_WAIT4_PORT;
2598 rc = bnx2x_func_start(bp);
2599 if (rc) {
2600 BNX2X_ERR("Function start failed!\n");
2601 bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
2602
2603 LOAD_ERROR_EXIT(bp, load_error3);
2604 }
2605
2606 /* Send LOAD_DONE command to MCP */
2607 if (!BP_NOMCP(bp)) {
2608 load_code = bnx2x_fw_command(bp,
2609 DRV_MSG_CODE_LOAD_DONE, 0);
2610 if (!load_code) {
2611 BNX2X_ERR("MCP response failure, aborting\n");
2612 rc = -EBUSY;
2613 LOAD_ERROR_EXIT(bp, load_error3);
2614 }
2615 }
2616
2617 /* initialize FW coalescing state machines in RAM */
2618 bnx2x_update_coalesce(bp);
2619
2620 /* setup the leading queue */
2621 rc = bnx2x_setup_leading(bp);
2622 if (rc) {
2623 BNX2X_ERR("Setup leading failed!\n");
2624 LOAD_ERROR_EXIT(bp, load_error3);
2625 }
2626
2627 /* set up the rest of the queues */
2628 for_each_nondefault_eth_queue(bp, i) {
2629 rc = bnx2x_setup_queue(bp, &bp->fp[i], 0);
2630 if (rc) {
2631 BNX2X_ERR("Queue setup failed\n");
2632 LOAD_ERROR_EXIT(bp, load_error3);
2633 }
2634 }
2635
2636 /* setup rss */
2637 rc = bnx2x_init_rss_pf(bp);
2638 if (rc) {
2639 BNX2X_ERR("PF RSS init failed\n");
2640 LOAD_ERROR_EXIT(bp, load_error3);
2641 }
2642
2643 } else { /* vf */
2644 for_each_eth_queue(bp, i) {
2645 rc = bnx2x_vfpf_setup_q(bp, i);
2646 if (rc) {
2647 BNX2X_ERR("Queue setup failed\n");
2648 LOAD_ERROR_EXIT(bp, load_error3);
2649 }
2650 }
2651 }
2652
2653 /* Now when Clients are configured we are ready to work */
2654 bp->state = BNX2X_STATE_OPEN;
2655
2656 /* Configure a ucast MAC */
2657 if (IS_PF(bp))
2658 rc = bnx2x_set_eth_mac(bp, true);
2659 else /* vf */
2660 rc = bnx2x_vfpf_set_mac(bp);
2661 if (rc) {
2662 BNX2X_ERR("Setting Ethernet MAC failed\n");
2663 LOAD_ERROR_EXIT(bp, load_error3);
2664 }
2665
2666 if (IS_PF(bp) && bp->pending_max) {
2667 bnx2x_update_max_mf_config(bp, bp->pending_max);
2668 bp->pending_max = 0;
2669 }
2670
2671 if (bp->port.pmf) {
2672 rc = bnx2x_initial_phy_init(bp, load_mode);
2673 if (rc)
2674 LOAD_ERROR_EXIT(bp, load_error3);
2675 }
2676 bp->link_params.feature_config_flags &= ~FEATURE_CONFIG_BOOT_FROM_SAN;
2677
2678 /* Start fast path */
2679
2680 /* Initialize Rx filter. */
2681 netif_addr_lock_bh(bp->dev);
2682 bnx2x_set_rx_mode(bp->dev);
2683 netif_addr_unlock_bh(bp->dev);
2684
2685 /* Start the Tx */
2686 switch (load_mode) {
2687 case LOAD_NORMAL:
2688 /* Tx queue should be only reenabled */
2689 netif_tx_wake_all_queues(bp->dev);
2690 break;
2691
2692 case LOAD_OPEN:
2693 netif_tx_start_all_queues(bp->dev);
2694 smp_mb__after_clear_bit();
2695 break;
2696
2697 case LOAD_DIAG:
2698 case LOAD_LOOPBACK_EXT:
2699 bp->state = BNX2X_STATE_DIAG;
2700 break;
2701
2702 default:
2703 break;
2704 }
2705
2706 if (bp->port.pmf)
2707 bnx2x_update_drv_flags(bp, 1 << DRV_FLAGS_PORT_MASK, 0);
2708 else
2709 bnx2x__link_status_update(bp);
2710
2711 /* start the timer */
2712 mod_timer(&bp->timer, jiffies + bp->current_interval);
2713
2714 if (CNIC_ENABLED(bp))
2715 bnx2x_load_cnic(bp);
2716
2717 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
2718 /* mark driver is loaded in shmem2 */
2719 u32 val;
2720 val = SHMEM2_RD(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
2721 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
2722 val | DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
2723 DRV_FLAGS_CAPABILITIES_LOADED_L2);
2724 }
2725
2726 /* Wait for all pending SP commands to complete */
2727 if (IS_PF(bp) && !bnx2x_wait_sp_comp(bp, ~0x0UL)) {
2728 BNX2X_ERR("Timeout waiting for SP elements to complete\n");
2729 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
2730 return -EBUSY;
2731 }
2732
2733 /* If PMF - send ADMIN DCBX msg to MFW to initiate DCBX FSM */
2734 if (bp->port.pmf && (bp->state != BNX2X_STATE_DIAG))
2735 bnx2x_dcbx_init(bp, false);
2736
2737 DP(NETIF_MSG_IFUP, "Ending successfully NIC load\n");
2738
2739 return 0;
2740
2741 #ifndef BNX2X_STOP_ON_ERROR
2742 load_error3:
2743 if (IS_PF(bp)) {
2744 bnx2x_int_disable_sync(bp, 1);
2745
2746 /* Clean queueable objects */
2747 bnx2x_squeeze_objects(bp);
2748 }
2749
2750 /* Free SKBs, SGEs, TPA pool and driver internals */
2751 bnx2x_free_skbs(bp);
2752 for_each_rx_queue(bp, i)
2753 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
2754
2755 /* Release IRQs */
2756 bnx2x_free_irq(bp);
2757 load_error2:
2758 if (IS_PF(bp) && !BP_NOMCP(bp)) {
2759 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
2760 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
2761 }
2762
2763 bp->port.pmf = 0;
2764 load_error1:
2765 bnx2x_napi_disable(bp);
2766 bnx2x_del_all_napi(bp);
2767
2768 /* clear pf_load status, as it was already set */
2769 if (IS_PF(bp))
2770 bnx2x_clear_pf_load(bp);
2771 load_error0:
2772 bnx2x_free_fp_mem(bp);
2773 bnx2x_free_fw_stats_mem(bp);
2774 bnx2x_free_mem(bp);
2775
2776 return rc;
2777 #endif /* ! BNX2X_STOP_ON_ERROR */
2778 }
2779
2780 static int bnx2x_drain_tx_queues(struct bnx2x *bp)
2781 {
2782 u8 rc = 0, cos, i;
2783
2784 /* Wait until tx fastpath tasks complete */
2785 for_each_tx_queue(bp, i) {
2786 struct bnx2x_fastpath *fp = &bp->fp[i];
2787
2788 for_each_cos_in_tx_queue(fp, cos)
2789 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
2790 if (rc)
2791 return rc;
2792 }
2793 return 0;
2794 }
2795
2796 /* must be called with rtnl_lock */
2797 int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode, bool keep_link)
2798 {
2799 int i;
2800 bool global = false;
2801
2802 DP(NETIF_MSG_IFUP, "Starting NIC unload\n");
2803
2804 /* mark driver is unloaded in shmem2 */
2805 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
2806 u32 val;
2807 val = SHMEM2_RD(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
2808 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
2809 val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
2810 }
2811
2812 if (IS_PF(bp) && bp->recovery_state != BNX2X_RECOVERY_DONE &&
2813 (bp->state == BNX2X_STATE_CLOSED ||
2814 bp->state == BNX2X_STATE_ERROR)) {
2815 /* We can get here if the driver has been unloaded
2816 * during parity error recovery and is either waiting for a
2817 * leader to complete or for other functions to unload and
2818 * then ifdown has been issued. In this case we want to
2819 * unload and let other functions to complete a recovery
2820 * process.
2821 */
2822 bp->recovery_state = BNX2X_RECOVERY_DONE;
2823 bp->is_leader = 0;
2824 bnx2x_release_leader_lock(bp);
2825 smp_mb();
2826
2827 DP(NETIF_MSG_IFDOWN, "Releasing a leadership...\n");
2828 BNX2X_ERR("Can't unload in closed or error state\n");
2829 return -EINVAL;
2830 }
2831
2832 /* Nothing to do during unload if previous bnx2x_nic_load()
2833 * have not completed succesfully - all resourses are released.
2834 *
2835 * we can get here only after unsuccessful ndo_* callback, during which
2836 * dev->IFF_UP flag is still on.
2837 */
2838 if (bp->state == BNX2X_STATE_CLOSED || bp->state == BNX2X_STATE_ERROR)
2839 return 0;
2840
2841 /* It's important to set the bp->state to the value different from
2842 * BNX2X_STATE_OPEN and only then stop the Tx. Otherwise bnx2x_tx_int()
2843 * may restart the Tx from the NAPI context (see bnx2x_tx_int()).
2844 */
2845 bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
2846 smp_mb();
2847
2848 if (CNIC_LOADED(bp))
2849 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
2850
2851 /* Stop Tx */
2852 bnx2x_tx_disable(bp);
2853 netdev_reset_tc(bp->dev);
2854
2855 bp->rx_mode = BNX2X_RX_MODE_NONE;
2856
2857 del_timer_sync(&bp->timer);
2858
2859 if (IS_PF(bp)) {
2860 /* Set ALWAYS_ALIVE bit in shmem */
2861 bp->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2862 bnx2x_drv_pulse(bp);
2863 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2864 bnx2x_save_statistics(bp);
2865 }
2866
2867 /* wait till consumers catch up with producers in all queues */
2868 bnx2x_drain_tx_queues(bp);
2869
2870 /* if VF indicate to PF this function is going down (PF will delete sp
2871 * elements and clear initializations
2872 */
2873 if (IS_VF(bp))
2874 bnx2x_vfpf_close_vf(bp);
2875 else if (unload_mode != UNLOAD_RECOVERY)
2876 /* if this is a normal/close unload need to clean up chip*/
2877 bnx2x_chip_cleanup(bp, unload_mode, keep_link);
2878 else {
2879 /* Send the UNLOAD_REQUEST to the MCP */
2880 bnx2x_send_unload_req(bp, unload_mode);
2881
2882 /*
2883 * Prevent transactions to host from the functions on the
2884 * engine that doesn't reset global blocks in case of global
2885 * attention once gloabl blocks are reset and gates are opened
2886 * (the engine which leader will perform the recovery
2887 * last).
2888 */
2889 if (!CHIP_IS_E1x(bp))
2890 bnx2x_pf_disable(bp);
2891
2892 /* Disable HW interrupts, NAPI */
2893 bnx2x_netif_stop(bp, 1);
2894 /* Delete all NAPI objects */
2895 bnx2x_del_all_napi(bp);
2896 if (CNIC_LOADED(bp))
2897 bnx2x_del_all_napi_cnic(bp);
2898 /* Release IRQs */
2899 bnx2x_free_irq(bp);
2900
2901 /* Report UNLOAD_DONE to MCP */
2902 bnx2x_send_unload_done(bp, false);
2903 }
2904
2905 /*
2906 * At this stage no more interrupts will arrive so we may safly clean
2907 * the queueable objects here in case they failed to get cleaned so far.
2908 */
2909 if (IS_PF(bp))
2910 bnx2x_squeeze_objects(bp);
2911
2912 /* There should be no more pending SP commands at this stage */
2913 bp->sp_state = 0;
2914
2915 bp->port.pmf = 0;
2916
2917 /* Free SKBs, SGEs, TPA pool and driver internals */
2918 bnx2x_free_skbs(bp);
2919 if (CNIC_LOADED(bp))
2920 bnx2x_free_skbs_cnic(bp);
2921 for_each_rx_queue(bp, i)
2922 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
2923
2924 bnx2x_free_fp_mem(bp);
2925 if (CNIC_LOADED(bp))
2926 bnx2x_free_fp_mem_cnic(bp);
2927
2928 if (IS_PF(bp)) {
2929 bnx2x_free_mem(bp);
2930 if (CNIC_LOADED(bp))
2931 bnx2x_free_mem_cnic(bp);
2932 }
2933 bp->state = BNX2X_STATE_CLOSED;
2934 bp->cnic_loaded = false;
2935
2936 /* Check if there are pending parity attentions. If there are - set
2937 * RECOVERY_IN_PROGRESS.
2938 */
2939 if (IS_PF(bp) && bnx2x_chk_parity_attn(bp, &global, false)) {
2940 bnx2x_set_reset_in_progress(bp);
2941
2942 /* Set RESET_IS_GLOBAL if needed */
2943 if (global)
2944 bnx2x_set_reset_global(bp);
2945 }
2946
2947
2948 /* The last driver must disable a "close the gate" if there is no
2949 * parity attention or "process kill" pending.
2950 */
2951 if (IS_PF(bp) &&
2952 !bnx2x_clear_pf_load(bp) &&
2953 bnx2x_reset_is_done(bp, BP_PATH(bp)))
2954 bnx2x_disable_close_the_gate(bp);
2955
2956 DP(NETIF_MSG_IFUP, "Ending NIC unload\n");
2957
2958 return 0;
2959 }
2960
2961 int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state)
2962 {
2963 u16 pmcsr;
2964
2965 /* If there is no power capability, silently succeed */
2966 if (!bp->pm_cap) {
2967 BNX2X_DEV_INFO("No power capability. Breaking.\n");
2968 return 0;
2969 }
2970
2971 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
2972
2973 switch (state) {
2974 case PCI_D0:
2975 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2976 ((pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
2977 PCI_PM_CTRL_PME_STATUS));
2978
2979 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
2980 /* delay required during transition out of D3hot */
2981 msleep(20);
2982 break;
2983
2984 case PCI_D3hot:
2985 /* If there are other clients above don't
2986 shut down the power */
2987 if (atomic_read(&bp->pdev->enable_cnt) != 1)
2988 return 0;
2989 /* Don't shut down the power for emulation and FPGA */
2990 if (CHIP_REV_IS_SLOW(bp))
2991 return 0;
2992
2993 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
2994 pmcsr |= 3;
2995
2996 if (bp->wol)
2997 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2998
2999 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3000 pmcsr);
3001
3002 /* No more memory access after this point until
3003 * device is brought back to D0.
3004 */
3005 break;
3006
3007 default:
3008 dev_err(&bp->pdev->dev, "Can't support state = %d\n", state);
3009 return -EINVAL;
3010 }
3011 return 0;
3012 }
3013
3014 /*
3015 * net_device service functions
3016 */
3017 int bnx2x_poll(struct napi_struct *napi, int budget)
3018 {
3019 int work_done = 0;
3020 u8 cos;
3021 struct bnx2x_fastpath *fp = container_of(napi, struct bnx2x_fastpath,
3022 napi);
3023 struct bnx2x *bp = fp->bp;
3024
3025 while (1) {
3026 #ifdef BNX2X_STOP_ON_ERROR
3027 if (unlikely(bp->panic)) {
3028 napi_complete(napi);
3029 return 0;
3030 }
3031 #endif
3032
3033 for_each_cos_in_tx_queue(fp, cos)
3034 if (bnx2x_tx_queue_has_work(fp->txdata_ptr[cos]))
3035 bnx2x_tx_int(bp, fp->txdata_ptr[cos]);
3036
3037 if (bnx2x_has_rx_work(fp)) {
3038 work_done += bnx2x_rx_int(fp, budget - work_done);
3039
3040 /* must not complete if we consumed full budget */
3041 if (work_done >= budget)
3042 break;
3043 }
3044
3045 /* Fall out from the NAPI loop if needed */
3046 if (!(bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
3047
3048 /* No need to update SB for FCoE L2 ring as long as
3049 * it's connected to the default SB and the SB
3050 * has been updated when NAPI was scheduled.
3051 */
3052 if (IS_FCOE_FP(fp)) {
3053 napi_complete(napi);
3054 break;
3055 }
3056 bnx2x_update_fpsb_idx(fp);
3057 /* bnx2x_has_rx_work() reads the status block,
3058 * thus we need to ensure that status block indices
3059 * have been actually read (bnx2x_update_fpsb_idx)
3060 * prior to this check (bnx2x_has_rx_work) so that
3061 * we won't write the "newer" value of the status block
3062 * to IGU (if there was a DMA right after
3063 * bnx2x_has_rx_work and if there is no rmb, the memory
3064 * reading (bnx2x_update_fpsb_idx) may be postponed
3065 * to right before bnx2x_ack_sb). In this case there
3066 * will never be another interrupt until there is
3067 * another update of the status block, while there
3068 * is still unhandled work.
3069 */
3070 rmb();
3071
3072 if (!(bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
3073 napi_complete(napi);
3074 /* Re-enable interrupts */
3075 DP(NETIF_MSG_RX_STATUS,
3076 "Update index to %d\n", fp->fp_hc_idx);
3077 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID,
3078 le16_to_cpu(fp->fp_hc_idx),
3079 IGU_INT_ENABLE, 1);
3080 break;
3081 }
3082 }
3083 }
3084
3085 return work_done;
3086 }
3087
3088 /* we split the first BD into headers and data BDs
3089 * to ease the pain of our fellow microcode engineers
3090 * we use one mapping for both BDs
3091 */
3092 static noinline u16 bnx2x_tx_split(struct bnx2x *bp,
3093 struct bnx2x_fp_txdata *txdata,
3094 struct sw_tx_bd *tx_buf,
3095 struct eth_tx_start_bd **tx_bd, u16 hlen,
3096 u16 bd_prod, int nbd)
3097 {
3098 struct eth_tx_start_bd *h_tx_bd = *tx_bd;
3099 struct eth_tx_bd *d_tx_bd;
3100 dma_addr_t mapping;
3101 int old_len = le16_to_cpu(h_tx_bd->nbytes);
3102
3103 /* first fix first BD */
3104 h_tx_bd->nbd = cpu_to_le16(nbd);
3105 h_tx_bd->nbytes = cpu_to_le16(hlen);
3106
3107 DP(NETIF_MSG_TX_QUEUED, "TSO split header size is %d (%x:%x) nbd %d\n",
3108 h_tx_bd->nbytes, h_tx_bd->addr_hi, h_tx_bd->addr_lo, h_tx_bd->nbd);
3109
3110 /* now get a new data BD
3111 * (after the pbd) and fill it */
3112 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
3113 d_tx_bd = &txdata->tx_desc_ring[bd_prod].reg_bd;
3114
3115 mapping = HILO_U64(le32_to_cpu(h_tx_bd->addr_hi),
3116 le32_to_cpu(h_tx_bd->addr_lo)) + hlen;
3117
3118 d_tx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
3119 d_tx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
3120 d_tx_bd->nbytes = cpu_to_le16(old_len - hlen);
3121
3122 /* this marks the BD as one that has no individual mapping */
3123 tx_buf->flags |= BNX2X_TSO_SPLIT_BD;
3124
3125 DP(NETIF_MSG_TX_QUEUED,
3126 "TSO split data size is %d (%x:%x)\n",
3127 d_tx_bd->nbytes, d_tx_bd->addr_hi, d_tx_bd->addr_lo);
3128
3129 /* update tx_bd */
3130 *tx_bd = (struct eth_tx_start_bd *)d_tx_bd;
3131
3132 return bd_prod;
3133 }
3134
3135 #define bswab32(b32) ((__force __le32) swab32((__force __u32) (b32)))
3136 #define bswab16(b16) ((__force __le16) swab16((__force __u16) (b16)))
3137 static inline __le16 bnx2x_csum_fix(unsigned char *t_header, u16 csum, s8 fix)
3138 {
3139 __sum16 tsum = (__force __sum16) csum;
3140
3141 if (fix > 0)
3142 tsum = ~csum_fold(csum_sub((__force __wsum) csum,
3143 csum_partial(t_header - fix, fix, 0)));
3144
3145 else if (fix < 0)
3146 tsum = ~csum_fold(csum_add((__force __wsum) csum,
3147 csum_partial(t_header, -fix, 0)));
3148
3149 return bswab16(tsum);
3150 }
3151
3152 static inline u32 bnx2x_xmit_type(struct bnx2x *bp, struct sk_buff *skb)
3153 {
3154 u32 rc;
3155
3156 if (skb->ip_summed != CHECKSUM_PARTIAL)
3157 rc = XMIT_PLAIN;
3158
3159 else {
3160 if (vlan_get_protocol(skb) == htons(ETH_P_IPV6)) {
3161 rc = XMIT_CSUM_V6;
3162 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3163 rc |= XMIT_CSUM_TCP;
3164
3165 } else {
3166 rc = XMIT_CSUM_V4;
3167 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3168 rc |= XMIT_CSUM_TCP;
3169 }
3170 }
3171
3172 if (skb_is_gso_v6(skb))
3173 rc |= XMIT_GSO_V6 | XMIT_CSUM_TCP | XMIT_CSUM_V6;
3174 else if (skb_is_gso(skb))
3175 rc |= XMIT_GSO_V4 | XMIT_CSUM_V4 | XMIT_CSUM_TCP;
3176
3177 return rc;
3178 }
3179
3180 #if (MAX_SKB_FRAGS >= MAX_FETCH_BD - 3)
3181 /* check if packet requires linearization (packet is too fragmented)
3182 no need to check fragmentation if page size > 8K (there will be no
3183 violation to FW restrictions) */
3184 static int bnx2x_pkt_req_lin(struct bnx2x *bp, struct sk_buff *skb,
3185 u32 xmit_type)
3186 {
3187 int to_copy = 0;
3188 int hlen = 0;
3189 int first_bd_sz = 0;
3190
3191 /* 3 = 1 (for linear data BD) + 2 (for PBD and last BD) */
3192 if (skb_shinfo(skb)->nr_frags >= (MAX_FETCH_BD - 3)) {
3193
3194 if (xmit_type & XMIT_GSO) {
3195 unsigned short lso_mss = skb_shinfo(skb)->gso_size;
3196 /* Check if LSO packet needs to be copied:
3197 3 = 1 (for headers BD) + 2 (for PBD and last BD) */
3198 int wnd_size = MAX_FETCH_BD - 3;
3199 /* Number of windows to check */
3200 int num_wnds = skb_shinfo(skb)->nr_frags - wnd_size;
3201 int wnd_idx = 0;
3202 int frag_idx = 0;
3203 u32 wnd_sum = 0;
3204
3205 /* Headers length */
3206 hlen = (int)(skb_transport_header(skb) - skb->data) +
3207 tcp_hdrlen(skb);
3208
3209 /* Amount of data (w/o headers) on linear part of SKB*/
3210 first_bd_sz = skb_headlen(skb) - hlen;
3211
3212 wnd_sum = first_bd_sz;
3213
3214 /* Calculate the first sum - it's special */
3215 for (frag_idx = 0; frag_idx < wnd_size - 1; frag_idx++)
3216 wnd_sum +=
3217 skb_frag_size(&skb_shinfo(skb)->frags[frag_idx]);
3218
3219 /* If there was data on linear skb data - check it */
3220 if (first_bd_sz > 0) {
3221 if (unlikely(wnd_sum < lso_mss)) {
3222 to_copy = 1;
3223 goto exit_lbl;
3224 }
3225
3226 wnd_sum -= first_bd_sz;
3227 }
3228
3229 /* Others are easier: run through the frag list and
3230 check all windows */
3231 for (wnd_idx = 0; wnd_idx <= num_wnds; wnd_idx++) {
3232 wnd_sum +=
3233 skb_frag_size(&skb_shinfo(skb)->frags[wnd_idx + wnd_size - 1]);
3234
3235 if (unlikely(wnd_sum < lso_mss)) {
3236 to_copy = 1;
3237 break;
3238 }
3239 wnd_sum -=
3240 skb_frag_size(&skb_shinfo(skb)->frags[wnd_idx]);
3241 }
3242 } else {
3243 /* in non-LSO too fragmented packet should always
3244 be linearized */
3245 to_copy = 1;
3246 }
3247 }
3248
3249 exit_lbl:
3250 if (unlikely(to_copy))
3251 DP(NETIF_MSG_TX_QUEUED,
3252 "Linearization IS REQUIRED for %s packet. num_frags %d hlen %d first_bd_sz %d\n",
3253 (xmit_type & XMIT_GSO) ? "LSO" : "non-LSO",
3254 skb_shinfo(skb)->nr_frags, hlen, first_bd_sz);
3255
3256 return to_copy;
3257 }
3258 #endif
3259
3260 static inline void bnx2x_set_pbd_gso_e2(struct sk_buff *skb, u32 *parsing_data,
3261 u32 xmit_type)
3262 {
3263 *parsing_data |= (skb_shinfo(skb)->gso_size <<
3264 ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT) &
3265 ETH_TX_PARSE_BD_E2_LSO_MSS;
3266 if ((xmit_type & XMIT_GSO_V6) &&
3267 (ipv6_hdr(skb)->nexthdr == NEXTHDR_IPV6))
3268 *parsing_data |= ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR;
3269 }
3270
3271 /**
3272 * bnx2x_set_pbd_gso - update PBD in GSO case.
3273 *
3274 * @skb: packet skb
3275 * @pbd: parse BD
3276 * @xmit_type: xmit flags
3277 */
3278 static inline void bnx2x_set_pbd_gso(struct sk_buff *skb,
3279 struct eth_tx_parse_bd_e1x *pbd,
3280 u32 xmit_type)
3281 {
3282 pbd->lso_mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
3283 pbd->tcp_send_seq = bswab32(tcp_hdr(skb)->seq);
3284 pbd->tcp_flags = pbd_tcp_flags(skb);
3285
3286 if (xmit_type & XMIT_GSO_V4) {
3287 pbd->ip_id = bswab16(ip_hdr(skb)->id);
3288 pbd->tcp_pseudo_csum =
3289 bswab16(~csum_tcpudp_magic(ip_hdr(skb)->saddr,
3290 ip_hdr(skb)->daddr,
3291 0, IPPROTO_TCP, 0));
3292
3293 } else
3294 pbd->tcp_pseudo_csum =
3295 bswab16(~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
3296 &ipv6_hdr(skb)->daddr,
3297 0, IPPROTO_TCP, 0));
3298
3299 pbd->global_data |=
3300 cpu_to_le16(ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN);
3301 }
3302
3303 /**
3304 * bnx2x_set_pbd_csum_e2 - update PBD with checksum and return header length
3305 *
3306 * @bp: driver handle
3307 * @skb: packet skb
3308 * @parsing_data: data to be updated
3309 * @xmit_type: xmit flags
3310 *
3311 * 57712 related
3312 */
3313 static inline u8 bnx2x_set_pbd_csum_e2(struct bnx2x *bp, struct sk_buff *skb,
3314 u32 *parsing_data, u32 xmit_type)
3315 {
3316 *parsing_data |=
3317 ((((u8 *)skb_transport_header(skb) - skb->data) >> 1) <<
3318 ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W_SHIFT) &
3319 ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W;
3320
3321 if (xmit_type & XMIT_CSUM_TCP) {
3322 *parsing_data |= ((tcp_hdrlen(skb) / 4) <<
3323 ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT) &
3324 ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW;
3325
3326 return skb_transport_header(skb) + tcp_hdrlen(skb) - skb->data;
3327 }
3328 /* We support checksum offload for TCP and UDP only.
3329 * No need to pass the UDP header length - it's a constant.
3330 */
3331 return skb_transport_header(skb) + sizeof(struct udphdr) - skb->data;
3332 }
3333
3334 static inline void bnx2x_set_sbd_csum(struct bnx2x *bp, struct sk_buff *skb,
3335 struct eth_tx_start_bd *tx_start_bd, u32 xmit_type)
3336 {
3337 tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_L4_CSUM;
3338
3339 if (xmit_type & XMIT_CSUM_V4)
3340 tx_start_bd->bd_flags.as_bitfield |=
3341 ETH_TX_BD_FLAGS_IP_CSUM;
3342 else
3343 tx_start_bd->bd_flags.as_bitfield |=
3344 ETH_TX_BD_FLAGS_IPV6;
3345
3346 if (!(xmit_type & XMIT_CSUM_TCP))
3347 tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_IS_UDP;
3348 }
3349
3350 /**
3351 * bnx2x_set_pbd_csum - update PBD with checksum and return header length
3352 *
3353 * @bp: driver handle
3354 * @skb: packet skb
3355 * @pbd: parse BD to be updated
3356 * @xmit_type: xmit flags
3357 */
3358 static inline u8 bnx2x_set_pbd_csum(struct bnx2x *bp, struct sk_buff *skb,
3359 struct eth_tx_parse_bd_e1x *pbd,
3360 u32 xmit_type)
3361 {
3362 u8 hlen = (skb_network_header(skb) - skb->data) >> 1;
3363
3364 /* for now NS flag is not used in Linux */
3365 pbd->global_data =
3366 cpu_to_le16(hlen |
3367 ((skb->protocol == cpu_to_be16(ETH_P_8021Q)) <<
3368 ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT));
3369
3370 pbd->ip_hlen_w = (skb_transport_header(skb) -
3371 skb_network_header(skb)) >> 1;
3372
3373 hlen += pbd->ip_hlen_w;
3374
3375 /* We support checksum offload for TCP and UDP only */
3376 if (xmit_type & XMIT_CSUM_TCP)
3377 hlen += tcp_hdrlen(skb) / 2;
3378 else
3379 hlen += sizeof(struct udphdr) / 2;
3380
3381 pbd->total_hlen_w = cpu_to_le16(hlen);
3382 hlen = hlen*2;
3383
3384 if (xmit_type & XMIT_CSUM_TCP) {
3385 pbd->tcp_pseudo_csum = bswab16(tcp_hdr(skb)->check);
3386
3387 } else {
3388 s8 fix = SKB_CS_OFF(skb); /* signed! */
3389
3390 DP(NETIF_MSG_TX_QUEUED,
3391 "hlen %d fix %d csum before fix %x\n",
3392 le16_to_cpu(pbd->total_hlen_w), fix, SKB_CS(skb));
3393
3394 /* HW bug: fixup the CSUM */
3395 pbd->tcp_pseudo_csum =
3396 bnx2x_csum_fix(skb_transport_header(skb),
3397 SKB_CS(skb), fix);
3398
3399 DP(NETIF_MSG_TX_QUEUED, "csum after fix %x\n",
3400 pbd->tcp_pseudo_csum);
3401 }
3402
3403 return hlen;
3404 }
3405
3406 /* called with netif_tx_lock
3407 * bnx2x_tx_int() runs without netif_tx_lock unless it needs to call
3408 * netif_wake_queue()
3409 */
3410 netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
3411 {
3412 struct bnx2x *bp = netdev_priv(dev);
3413
3414 struct netdev_queue *txq;
3415 struct bnx2x_fp_txdata *txdata;
3416 struct sw_tx_bd *tx_buf;
3417 struct eth_tx_start_bd *tx_start_bd, *first_bd;
3418 struct eth_tx_bd *tx_data_bd, *total_pkt_bd = NULL;
3419 struct eth_tx_parse_bd_e1x *pbd_e1x = NULL;
3420 struct eth_tx_parse_bd_e2 *pbd_e2 = NULL;
3421 u32 pbd_e2_parsing_data = 0;
3422 u16 pkt_prod, bd_prod;
3423 int nbd, txq_index;
3424 dma_addr_t mapping;
3425 u32 xmit_type = bnx2x_xmit_type(bp, skb);
3426 int i;
3427 u8 hlen = 0;
3428 __le16 pkt_size = 0;
3429 struct ethhdr *eth;
3430 u8 mac_type = UNICAST_ADDRESS;
3431
3432 #ifdef BNX2X_STOP_ON_ERROR
3433 if (unlikely(bp->panic))
3434 return NETDEV_TX_BUSY;
3435 #endif
3436
3437 txq_index = skb_get_queue_mapping(skb);
3438 txq = netdev_get_tx_queue(dev, txq_index);
3439
3440 BUG_ON(txq_index >= MAX_ETH_TXQ_IDX(bp) + (CNIC_LOADED(bp) ? 1 : 0));
3441
3442 txdata = &bp->bnx2x_txq[txq_index];
3443
3444 /* enable this debug print to view the transmission queue being used
3445 DP(NETIF_MSG_TX_QUEUED, "indices: txq %d, fp %d, txdata %d\n",
3446 txq_index, fp_index, txdata_index); */
3447
3448 /* enable this debug print to view the tranmission details
3449 DP(NETIF_MSG_TX_QUEUED,
3450 "transmitting packet cid %d fp index %d txdata_index %d tx_data ptr %p fp pointer %p\n",
3451 txdata->cid, fp_index, txdata_index, txdata, fp); */
3452
3453 if (unlikely(bnx2x_tx_avail(bp, txdata) <
3454 skb_shinfo(skb)->nr_frags +
3455 BDS_PER_TX_PKT +
3456 NEXT_CNT_PER_TX_PKT(MAX_BDS_PER_TX_PKT))) {
3457 /* Handle special storage cases separately */
3458 if (txdata->tx_ring_size == 0) {
3459 struct bnx2x_eth_q_stats *q_stats =
3460 bnx2x_fp_qstats(bp, txdata->parent_fp);
3461 q_stats->driver_filtered_tx_pkt++;
3462 dev_kfree_skb(skb);
3463 return NETDEV_TX_OK;
3464 }
3465 bnx2x_fp_qstats(bp, txdata->parent_fp)->driver_xoff++;
3466 netif_tx_stop_queue(txq);
3467 BNX2X_ERR("BUG! Tx ring full when queue awake!\n");
3468
3469 return NETDEV_TX_BUSY;
3470 }
3471
3472 DP(NETIF_MSG_TX_QUEUED,
3473 "queue[%d]: SKB: summed %x protocol %x protocol(%x,%x) gso type %x xmit_type %x len %d\n",
3474 txq_index, skb->ip_summed, skb->protocol, ipv6_hdr(skb)->nexthdr,
3475 ip_hdr(skb)->protocol, skb_shinfo(skb)->gso_type, xmit_type,
3476 skb->len);
3477
3478 eth = (struct ethhdr *)skb->data;
3479
3480 /* set flag according to packet type (UNICAST_ADDRESS is default)*/
3481 if (unlikely(is_multicast_ether_addr(eth->h_dest))) {
3482 if (is_broadcast_ether_addr(eth->h_dest))
3483 mac_type = BROADCAST_ADDRESS;
3484 else
3485 mac_type = MULTICAST_ADDRESS;
3486 }
3487
3488 #if (MAX_SKB_FRAGS >= MAX_FETCH_BD - 3)
3489 /* First, check if we need to linearize the skb (due to FW
3490 restrictions). No need to check fragmentation if page size > 8K
3491 (there will be no violation to FW restrictions) */
3492 if (bnx2x_pkt_req_lin(bp, skb, xmit_type)) {
3493 /* Statistics of linearization */
3494 bp->lin_cnt++;
3495 if (skb_linearize(skb) != 0) {
3496 DP(NETIF_MSG_TX_QUEUED,
3497 "SKB linearization failed - silently dropping this SKB\n");
3498 dev_kfree_skb_any(skb);
3499 return NETDEV_TX_OK;
3500 }
3501 }
3502 #endif
3503 /* Map skb linear data for DMA */
3504 mapping = dma_map_single(&bp->pdev->dev, skb->data,
3505 skb_headlen(skb), DMA_TO_DEVICE);
3506 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
3507 DP(NETIF_MSG_TX_QUEUED,
3508 "SKB mapping failed - silently dropping this SKB\n");
3509 dev_kfree_skb_any(skb);
3510 return NETDEV_TX_OK;
3511 }
3512 /*
3513 Please read carefully. First we use one BD which we mark as start,
3514 then we have a parsing info BD (used for TSO or xsum),
3515 and only then we have the rest of the TSO BDs.
3516 (don't forget to mark the last one as last,
3517 and to unmap only AFTER you write to the BD ...)
3518 And above all, all pdb sizes are in words - NOT DWORDS!
3519 */
3520
3521 /* get current pkt produced now - advance it just before sending packet
3522 * since mapping of pages may fail and cause packet to be dropped
3523 */
3524 pkt_prod = txdata->tx_pkt_prod;
3525 bd_prod = TX_BD(txdata->tx_bd_prod);
3526
3527 /* get a tx_buf and first BD
3528 * tx_start_bd may be changed during SPLIT,
3529 * but first_bd will always stay first
3530 */
3531 tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
3532 tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
3533 first_bd = tx_start_bd;
3534
3535 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
3536 SET_FLAG(tx_start_bd->general_data,
3537 ETH_TX_START_BD_PARSE_NBDS,
3538 0);
3539
3540 /* header nbd */
3541 SET_FLAG(tx_start_bd->general_data, ETH_TX_START_BD_HDR_NBDS, 1);
3542
3543 /* remember the first BD of the packet */
3544 tx_buf->first_bd = txdata->tx_bd_prod;
3545 tx_buf->skb = skb;
3546 tx_buf->flags = 0;
3547
3548 DP(NETIF_MSG_TX_QUEUED,
3549 "sending pkt %u @%p next_idx %u bd %u @%p\n",
3550 pkt_prod, tx_buf, txdata->tx_pkt_prod, bd_prod, tx_start_bd);
3551
3552 if (vlan_tx_tag_present(skb)) {
3553 tx_start_bd->vlan_or_ethertype =
3554 cpu_to_le16(vlan_tx_tag_get(skb));
3555 tx_start_bd->bd_flags.as_bitfield |=
3556 (X_ETH_OUTBAND_VLAN << ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
3557 } else {
3558 /* when transmitting in a vf, start bd must hold the ethertype
3559 * for fw to enforce it
3560 */
3561 #ifndef BNX2X_STOP_ON_ERROR
3562 if (IS_VF(bp)) {
3563 #endif
3564 tx_start_bd->vlan_or_ethertype =
3565 cpu_to_le16(ntohs(eth->h_proto));
3566 #ifndef BNX2X_STOP_ON_ERROR
3567 } else {
3568 /* used by FW for packet accounting */
3569 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
3570 }
3571 #endif
3572 }
3573
3574 /* turn on parsing and get a BD */
3575 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
3576
3577 if (xmit_type & XMIT_CSUM)
3578 bnx2x_set_sbd_csum(bp, skb, tx_start_bd, xmit_type);
3579
3580 if (!CHIP_IS_E1x(bp)) {
3581 pbd_e2 = &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
3582 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
3583 /* Set PBD in checksum offload case */
3584 if (xmit_type & XMIT_CSUM)
3585 hlen = bnx2x_set_pbd_csum_e2(bp, skb,
3586 &pbd_e2_parsing_data,
3587 xmit_type);
3588
3589 if (IS_MF_SI(bp) || IS_VF(bp)) {
3590 /* fill in the MAC addresses in the PBD - for local
3591 * switching
3592 */
3593 bnx2x_set_fw_mac_addr(&pbd_e2->src_mac_addr_hi,
3594 &pbd_e2->src_mac_addr_mid,
3595 &pbd_e2->src_mac_addr_lo,
3596 eth->h_source);
3597 bnx2x_set_fw_mac_addr(&pbd_e2->dst_mac_addr_hi,
3598 &pbd_e2->dst_mac_addr_mid,
3599 &pbd_e2->dst_mac_addr_lo,
3600 eth->h_dest);
3601 }
3602
3603 SET_FLAG(pbd_e2_parsing_data,
3604 ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, mac_type);
3605 } else {
3606 u16 global_data = 0;
3607 pbd_e1x = &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
3608 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
3609 /* Set PBD in checksum offload case */
3610 if (xmit_type & XMIT_CSUM)
3611 hlen = bnx2x_set_pbd_csum(bp, skb, pbd_e1x, xmit_type);
3612
3613 SET_FLAG(global_data,
3614 ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, mac_type);
3615 pbd_e1x->global_data |= cpu_to_le16(global_data);
3616 }
3617
3618 /* Setup the data pointer of the first BD of the packet */
3619 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
3620 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
3621 nbd = 2; /* start_bd + pbd + frags (updated when pages are mapped) */
3622 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
3623 pkt_size = tx_start_bd->nbytes;
3624
3625 DP(NETIF_MSG_TX_QUEUED,
3626 "first bd @%p addr (%x:%x) nbd %d nbytes %d flags %x vlan %x\n",
3627 tx_start_bd, tx_start_bd->addr_hi, tx_start_bd->addr_lo,
3628 le16_to_cpu(tx_start_bd->nbd), le16_to_cpu(tx_start_bd->nbytes),
3629 tx_start_bd->bd_flags.as_bitfield,
3630 le16_to_cpu(tx_start_bd->vlan_or_ethertype));
3631
3632 if (xmit_type & XMIT_GSO) {
3633
3634 DP(NETIF_MSG_TX_QUEUED,
3635 "TSO packet len %d hlen %d total len %d tso size %d\n",
3636 skb->len, hlen, skb_headlen(skb),
3637 skb_shinfo(skb)->gso_size);
3638
3639 tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_SW_LSO;
3640
3641 if (unlikely(skb_headlen(skb) > hlen))
3642 bd_prod = bnx2x_tx_split(bp, txdata, tx_buf,
3643 &tx_start_bd, hlen,
3644 bd_prod, ++nbd);
3645 if (!CHIP_IS_E1x(bp))
3646 bnx2x_set_pbd_gso_e2(skb, &pbd_e2_parsing_data,
3647 xmit_type);
3648 else
3649 bnx2x_set_pbd_gso(skb, pbd_e1x, xmit_type);
3650 }
3651
3652 /* Set the PBD's parsing_data field if not zero
3653 * (for the chips newer than 57711).
3654 */
3655 if (pbd_e2_parsing_data)
3656 pbd_e2->parsing_data = cpu_to_le32(pbd_e2_parsing_data);
3657
3658 tx_data_bd = (struct eth_tx_bd *)tx_start_bd;
3659
3660 /* Handle fragmented skb */
3661 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3662 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3663
3664 mapping = skb_frag_dma_map(&bp->pdev->dev, frag, 0,
3665 skb_frag_size(frag), DMA_TO_DEVICE);
3666 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
3667 unsigned int pkts_compl = 0, bytes_compl = 0;
3668
3669 DP(NETIF_MSG_TX_QUEUED,
3670 "Unable to map page - dropping packet...\n");
3671
3672 /* we need unmap all buffers already mapped
3673 * for this SKB;
3674 * first_bd->nbd need to be properly updated
3675 * before call to bnx2x_free_tx_pkt
3676 */
3677 first_bd->nbd = cpu_to_le16(nbd);
3678 bnx2x_free_tx_pkt(bp, txdata,
3679 TX_BD(txdata->tx_pkt_prod),
3680 &pkts_compl, &bytes_compl);
3681 return NETDEV_TX_OK;
3682 }
3683
3684 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
3685 tx_data_bd = &txdata->tx_desc_ring[bd_prod].reg_bd;
3686 if (total_pkt_bd == NULL)
3687 total_pkt_bd = &txdata->tx_desc_ring[bd_prod].reg_bd;
3688
3689 tx_data_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
3690 tx_data_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
3691 tx_data_bd->nbytes = cpu_to_le16(skb_frag_size(frag));
3692 le16_add_cpu(&pkt_size, skb_frag_size(frag));
3693 nbd++;
3694
3695 DP(NETIF_MSG_TX_QUEUED,
3696 "frag %d bd @%p addr (%x:%x) nbytes %d\n",
3697 i, tx_data_bd, tx_data_bd->addr_hi, tx_data_bd->addr_lo,
3698 le16_to_cpu(tx_data_bd->nbytes));
3699 }
3700
3701 DP(NETIF_MSG_TX_QUEUED, "last bd @%p\n", tx_data_bd);
3702
3703 /* update with actual num BDs */
3704 first_bd->nbd = cpu_to_le16(nbd);
3705
3706 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
3707
3708 /* now send a tx doorbell, counting the next BD
3709 * if the packet contains or ends with it
3710 */
3711 if (TX_BD_POFF(bd_prod) < nbd)
3712 nbd++;
3713
3714 /* total_pkt_bytes should be set on the first data BD if
3715 * it's not an LSO packet and there is more than one
3716 * data BD. In this case pkt_size is limited by an MTU value.
3717 * However we prefer to set it for an LSO packet (while we don't
3718 * have to) in order to save some CPU cycles in a none-LSO
3719 * case, when we much more care about them.
3720 */
3721 if (total_pkt_bd != NULL)
3722 total_pkt_bd->total_pkt_bytes = pkt_size;
3723
3724 if (pbd_e1x)
3725 DP(NETIF_MSG_TX_QUEUED,
3726 "PBD (E1X) @%p ip_data %x ip_hlen %u ip_id %u lso_mss %u tcp_flags %x xsum %x seq %u hlen %u\n",
3727 pbd_e1x, pbd_e1x->global_data, pbd_e1x->ip_hlen_w,
3728 pbd_e1x->ip_id, pbd_e1x->lso_mss, pbd_e1x->tcp_flags,
3729 pbd_e1x->tcp_pseudo_csum, pbd_e1x->tcp_send_seq,
3730 le16_to_cpu(pbd_e1x->total_hlen_w));
3731 if (pbd_e2)
3732 DP(NETIF_MSG_TX_QUEUED,
3733 "PBD (E2) @%p dst %x %x %x src %x %x %x parsing_data %x\n",
3734 pbd_e2, pbd_e2->dst_mac_addr_hi, pbd_e2->dst_mac_addr_mid,
3735 pbd_e2->dst_mac_addr_lo, pbd_e2->src_mac_addr_hi,
3736 pbd_e2->src_mac_addr_mid, pbd_e2->src_mac_addr_lo,
3737 pbd_e2->parsing_data);
3738 DP(NETIF_MSG_TX_QUEUED, "doorbell: nbd %d bd %u\n", nbd, bd_prod);
3739
3740 netdev_tx_sent_queue(txq, skb->len);
3741
3742 skb_tx_timestamp(skb);
3743
3744 txdata->tx_pkt_prod++;
3745 /*
3746 * Make sure that the BD data is updated before updating the producer
3747 * since FW might read the BD right after the producer is updated.
3748 * This is only applicable for weak-ordered memory model archs such
3749 * as IA-64. The following barrier is also mandatory since FW will
3750 * assumes packets must have BDs.
3751 */
3752 wmb();
3753
3754 txdata->tx_db.data.prod += nbd;
3755 barrier();
3756
3757 DOORBELL(bp, txdata->cid, txdata->tx_db.raw);
3758
3759 mmiowb();
3760
3761 txdata->tx_bd_prod += nbd;
3762
3763 if (unlikely(bnx2x_tx_avail(bp, txdata) < MAX_DESC_PER_TX_PKT)) {
3764 netif_tx_stop_queue(txq);
3765
3766 /* paired memory barrier is in bnx2x_tx_int(), we have to keep
3767 * ordering of set_bit() in netif_tx_stop_queue() and read of
3768 * fp->bd_tx_cons */
3769 smp_mb();
3770
3771 bnx2x_fp_qstats(bp, txdata->parent_fp)->driver_xoff++;
3772 if (bnx2x_tx_avail(bp, txdata) >= MAX_DESC_PER_TX_PKT)
3773 netif_tx_wake_queue(txq);
3774 }
3775 txdata->tx_pkt++;
3776
3777 return NETDEV_TX_OK;
3778 }
3779
3780 /**
3781 * bnx2x_setup_tc - routine to configure net_device for multi tc
3782 *
3783 * @netdev: net device to configure
3784 * @tc: number of traffic classes to enable
3785 *
3786 * callback connected to the ndo_setup_tc function pointer
3787 */
3788 int bnx2x_setup_tc(struct net_device *dev, u8 num_tc)
3789 {
3790 int cos, prio, count, offset;
3791 struct bnx2x *bp = netdev_priv(dev);
3792
3793 /* setup tc must be called under rtnl lock */
3794 ASSERT_RTNL();
3795
3796 /* no traffic classes requested. aborting */
3797 if (!num_tc) {
3798 netdev_reset_tc(dev);
3799 return 0;
3800 }
3801
3802 /* requested to support too many traffic classes */
3803 if (num_tc > bp->max_cos) {
3804 BNX2X_ERR("support for too many traffic classes requested: %d. max supported is %d\n",
3805 num_tc, bp->max_cos);
3806 return -EINVAL;
3807 }
3808
3809 /* declare amount of supported traffic classes */
3810 if (netdev_set_num_tc(dev, num_tc)) {
3811 BNX2X_ERR("failed to declare %d traffic classes\n", num_tc);
3812 return -EINVAL;
3813 }
3814
3815 /* configure priority to traffic class mapping */
3816 for (prio = 0; prio < BNX2X_MAX_PRIORITY; prio++) {
3817 netdev_set_prio_tc_map(dev, prio, bp->prio_to_cos[prio]);
3818 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
3819 "mapping priority %d to tc %d\n",
3820 prio, bp->prio_to_cos[prio]);
3821 }
3822
3823
3824 /* Use this configuration to diffrentiate tc0 from other COSes
3825 This can be used for ets or pfc, and save the effort of setting
3826 up a multio class queue disc or negotiating DCBX with a switch
3827 netdev_set_prio_tc_map(dev, 0, 0);
3828 DP(BNX2X_MSG_SP, "mapping priority %d to tc %d\n", 0, 0);
3829 for (prio = 1; prio < 16; prio++) {
3830 netdev_set_prio_tc_map(dev, prio, 1);
3831 DP(BNX2X_MSG_SP, "mapping priority %d to tc %d\n", prio, 1);
3832 } */
3833
3834 /* configure traffic class to transmission queue mapping */
3835 for (cos = 0; cos < bp->max_cos; cos++) {
3836 count = BNX2X_NUM_ETH_QUEUES(bp);
3837 offset = cos * BNX2X_NUM_NON_CNIC_QUEUES(bp);
3838 netdev_set_tc_queue(dev, cos, count, offset);
3839 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
3840 "mapping tc %d to offset %d count %d\n",
3841 cos, offset, count);
3842 }
3843
3844 return 0;
3845 }
3846
3847 /* called with rtnl_lock */
3848 int bnx2x_change_mac_addr(struct net_device *dev, void *p)
3849 {
3850 struct sockaddr *addr = p;
3851 struct bnx2x *bp = netdev_priv(dev);
3852 int rc = 0;
3853
3854 if (!bnx2x_is_valid_ether_addr(bp, addr->sa_data)) {
3855 BNX2X_ERR("Requested MAC address is not valid\n");
3856 return -EINVAL;
3857 }
3858
3859 if ((IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp)) &&
3860 !is_zero_ether_addr(addr->sa_data)) {
3861 BNX2X_ERR("Can't configure non-zero address on iSCSI or FCoE functions in MF-SD mode\n");
3862 return -EINVAL;
3863 }
3864
3865 if (netif_running(dev)) {
3866 rc = bnx2x_set_eth_mac(bp, false);
3867 if (rc)
3868 return rc;
3869 }
3870
3871 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3872
3873 if (netif_running(dev))
3874 rc = bnx2x_set_eth_mac(bp, true);
3875
3876 return rc;
3877 }
3878
3879 static void bnx2x_free_fp_mem_at(struct bnx2x *bp, int fp_index)
3880 {
3881 union host_hc_status_block *sb = &bnx2x_fp(bp, fp_index, status_blk);
3882 struct bnx2x_fastpath *fp = &bp->fp[fp_index];
3883 u8 cos;
3884
3885 /* Common */
3886
3887 if (IS_FCOE_IDX(fp_index)) {
3888 memset(sb, 0, sizeof(union host_hc_status_block));
3889 fp->status_blk_mapping = 0;
3890 } else {
3891 /* status blocks */
3892 if (!CHIP_IS_E1x(bp))
3893 BNX2X_PCI_FREE(sb->e2_sb,
3894 bnx2x_fp(bp, fp_index,
3895 status_blk_mapping),
3896 sizeof(struct host_hc_status_block_e2));
3897 else
3898 BNX2X_PCI_FREE(sb->e1x_sb,
3899 bnx2x_fp(bp, fp_index,
3900 status_blk_mapping),
3901 sizeof(struct host_hc_status_block_e1x));
3902 }
3903
3904 /* Rx */
3905 if (!skip_rx_queue(bp, fp_index)) {
3906 bnx2x_free_rx_bds(fp);
3907
3908 /* fastpath rx rings: rx_buf rx_desc rx_comp */
3909 BNX2X_FREE(bnx2x_fp(bp, fp_index, rx_buf_ring));
3910 BNX2X_PCI_FREE(bnx2x_fp(bp, fp_index, rx_desc_ring),
3911 bnx2x_fp(bp, fp_index, rx_desc_mapping),
3912 sizeof(struct eth_rx_bd) * NUM_RX_BD);
3913
3914 BNX2X_PCI_FREE(bnx2x_fp(bp, fp_index, rx_comp_ring),
3915 bnx2x_fp(bp, fp_index, rx_comp_mapping),
3916 sizeof(struct eth_fast_path_rx_cqe) *
3917 NUM_RCQ_BD);
3918
3919 /* SGE ring */
3920 BNX2X_FREE(bnx2x_fp(bp, fp_index, rx_page_ring));
3921 BNX2X_PCI_FREE(bnx2x_fp(bp, fp_index, rx_sge_ring),
3922 bnx2x_fp(bp, fp_index, rx_sge_mapping),
3923 BCM_PAGE_SIZE * NUM_RX_SGE_PAGES);
3924 }
3925
3926 /* Tx */
3927 if (!skip_tx_queue(bp, fp_index)) {
3928 /* fastpath tx rings: tx_buf tx_desc */
3929 for_each_cos_in_tx_queue(fp, cos) {
3930 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
3931
3932 DP(NETIF_MSG_IFDOWN,
3933 "freeing tx memory of fp %d cos %d cid %d\n",
3934 fp_index, cos, txdata->cid);
3935
3936 BNX2X_FREE(txdata->tx_buf_ring);
3937 BNX2X_PCI_FREE(txdata->tx_desc_ring,
3938 txdata->tx_desc_mapping,
3939 sizeof(union eth_tx_bd_types) * NUM_TX_BD);
3940 }
3941 }
3942 /* end of fastpath */
3943 }
3944
3945 void bnx2x_free_fp_mem_cnic(struct bnx2x *bp)
3946 {
3947 int i;
3948 for_each_cnic_queue(bp, i)
3949 bnx2x_free_fp_mem_at(bp, i);
3950 }
3951
3952 void bnx2x_free_fp_mem(struct bnx2x *bp)
3953 {
3954 int i;
3955 for_each_eth_queue(bp, i)
3956 bnx2x_free_fp_mem_at(bp, i);
3957 }
3958
3959 static void set_sb_shortcuts(struct bnx2x *bp, int index)
3960 {
3961 union host_hc_status_block status_blk = bnx2x_fp(bp, index, status_blk);
3962 if (!CHIP_IS_E1x(bp)) {
3963 bnx2x_fp(bp, index, sb_index_values) =
3964 (__le16 *)status_blk.e2_sb->sb.index_values;
3965 bnx2x_fp(bp, index, sb_running_index) =
3966 (__le16 *)status_blk.e2_sb->sb.running_index;
3967 } else {
3968 bnx2x_fp(bp, index, sb_index_values) =
3969 (__le16 *)status_blk.e1x_sb->sb.index_values;
3970 bnx2x_fp(bp, index, sb_running_index) =
3971 (__le16 *)status_blk.e1x_sb->sb.running_index;
3972 }
3973 }
3974
3975 /* Returns the number of actually allocated BDs */
3976 static int bnx2x_alloc_rx_bds(struct bnx2x_fastpath *fp,
3977 int rx_ring_size)
3978 {
3979 struct bnx2x *bp = fp->bp;
3980 u16 ring_prod, cqe_ring_prod;
3981 int i, failure_cnt = 0;
3982
3983 fp->rx_comp_cons = 0;
3984 cqe_ring_prod = ring_prod = 0;
3985
3986 /* This routine is called only during fo init so
3987 * fp->eth_q_stats.rx_skb_alloc_failed = 0
3988 */
3989 for (i = 0; i < rx_ring_size; i++) {
3990 if (bnx2x_alloc_rx_data(bp, fp, ring_prod) < 0) {
3991 failure_cnt++;
3992 continue;
3993 }
3994 ring_prod = NEXT_RX_IDX(ring_prod);
3995 cqe_ring_prod = NEXT_RCQ_IDX(cqe_ring_prod);
3996 WARN_ON(ring_prod <= (i - failure_cnt));
3997 }
3998
3999 if (failure_cnt)
4000 BNX2X_ERR("was only able to allocate %d rx skbs on queue[%d]\n",
4001 i - failure_cnt, fp->index);
4002
4003 fp->rx_bd_prod = ring_prod;
4004 /* Limit the CQE producer by the CQE ring size */
4005 fp->rx_comp_prod = min_t(u16, NUM_RCQ_RINGS*RCQ_DESC_CNT,
4006 cqe_ring_prod);
4007 fp->rx_pkt = fp->rx_calls = 0;
4008
4009 bnx2x_fp_stats(bp, fp)->eth_q_stats.rx_skb_alloc_failed += failure_cnt;
4010
4011 return i - failure_cnt;
4012 }
4013
4014 static void bnx2x_set_next_page_rx_cq(struct bnx2x_fastpath *fp)
4015 {
4016 int i;
4017
4018 for (i = 1; i <= NUM_RCQ_RINGS; i++) {
4019 struct eth_rx_cqe_next_page *nextpg;
4020
4021 nextpg = (struct eth_rx_cqe_next_page *)
4022 &fp->rx_comp_ring[RCQ_DESC_CNT * i - 1];
4023 nextpg->addr_hi =
4024 cpu_to_le32(U64_HI(fp->rx_comp_mapping +
4025 BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
4026 nextpg->addr_lo =
4027 cpu_to_le32(U64_LO(fp->rx_comp_mapping +
4028 BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
4029 }
4030 }
4031
4032 static int bnx2x_alloc_fp_mem_at(struct bnx2x *bp, int index)
4033 {
4034 union host_hc_status_block *sb;
4035 struct bnx2x_fastpath *fp = &bp->fp[index];
4036 int ring_size = 0;
4037 u8 cos;
4038 int rx_ring_size = 0;
4039
4040 if (!bp->rx_ring_size &&
4041 (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) {
4042 rx_ring_size = MIN_RX_SIZE_NONTPA;
4043 bp->rx_ring_size = rx_ring_size;
4044 } else if (!bp->rx_ring_size) {
4045 rx_ring_size = MAX_RX_AVAIL/BNX2X_NUM_RX_QUEUES(bp);
4046
4047 if (CHIP_IS_E3(bp)) {
4048 u32 cfg = SHMEM_RD(bp,
4049 dev_info.port_hw_config[BP_PORT(bp)].
4050 default_cfg);
4051
4052 /* Decrease ring size for 1G functions */
4053 if ((cfg & PORT_HW_CFG_NET_SERDES_IF_MASK) ==
4054 PORT_HW_CFG_NET_SERDES_IF_SGMII)
4055 rx_ring_size /= 10;
4056 }
4057
4058 /* allocate at least number of buffers required by FW */
4059 rx_ring_size = max_t(int, bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
4060 MIN_RX_SIZE_TPA, rx_ring_size);
4061
4062 bp->rx_ring_size = rx_ring_size;
4063 } else /* if rx_ring_size specified - use it */
4064 rx_ring_size = bp->rx_ring_size;
4065
4066 DP(BNX2X_MSG_SP, "calculated rx_ring_size %d\n", rx_ring_size);
4067
4068 /* Common */
4069 sb = &bnx2x_fp(bp, index, status_blk);
4070
4071 if (!IS_FCOE_IDX(index)) {
4072 /* status blocks */
4073 if (!CHIP_IS_E1x(bp))
4074 BNX2X_PCI_ALLOC(sb->e2_sb,
4075 &bnx2x_fp(bp, index, status_blk_mapping),
4076 sizeof(struct host_hc_status_block_e2));
4077 else
4078 BNX2X_PCI_ALLOC(sb->e1x_sb,
4079 &bnx2x_fp(bp, index, status_blk_mapping),
4080 sizeof(struct host_hc_status_block_e1x));
4081 }
4082
4083 /* FCoE Queue uses Default SB and doesn't ACK the SB, thus no need to
4084 * set shortcuts for it.
4085 */
4086 if (!IS_FCOE_IDX(index))
4087 set_sb_shortcuts(bp, index);
4088
4089 /* Tx */
4090 if (!skip_tx_queue(bp, index)) {
4091 /* fastpath tx rings: tx_buf tx_desc */
4092 for_each_cos_in_tx_queue(fp, cos) {
4093 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
4094
4095 DP(NETIF_MSG_IFUP,
4096 "allocating tx memory of fp %d cos %d\n",
4097 index, cos);
4098
4099 BNX2X_ALLOC(txdata->tx_buf_ring,
4100 sizeof(struct sw_tx_bd) * NUM_TX_BD);
4101 BNX2X_PCI_ALLOC(txdata->tx_desc_ring,
4102 &txdata->tx_desc_mapping,
4103 sizeof(union eth_tx_bd_types) * NUM_TX_BD);
4104 }
4105 }
4106
4107 /* Rx */
4108 if (!skip_rx_queue(bp, index)) {
4109 /* fastpath rx rings: rx_buf rx_desc rx_comp */
4110 BNX2X_ALLOC(bnx2x_fp(bp, index, rx_buf_ring),
4111 sizeof(struct sw_rx_bd) * NUM_RX_BD);
4112 BNX2X_PCI_ALLOC(bnx2x_fp(bp, index, rx_desc_ring),
4113 &bnx2x_fp(bp, index, rx_desc_mapping),
4114 sizeof(struct eth_rx_bd) * NUM_RX_BD);
4115
4116 BNX2X_PCI_ALLOC(bnx2x_fp(bp, index, rx_comp_ring),
4117 &bnx2x_fp(bp, index, rx_comp_mapping),
4118 sizeof(struct eth_fast_path_rx_cqe) *
4119 NUM_RCQ_BD);
4120
4121 /* SGE ring */
4122 BNX2X_ALLOC(bnx2x_fp(bp, index, rx_page_ring),
4123 sizeof(struct sw_rx_page) * NUM_RX_SGE);
4124 BNX2X_PCI_ALLOC(bnx2x_fp(bp, index, rx_sge_ring),
4125 &bnx2x_fp(bp, index, rx_sge_mapping),
4126 BCM_PAGE_SIZE * NUM_RX_SGE_PAGES);
4127 /* RX BD ring */
4128 bnx2x_set_next_page_rx_bd(fp);
4129
4130 /* CQ ring */
4131 bnx2x_set_next_page_rx_cq(fp);
4132
4133 /* BDs */
4134 ring_size = bnx2x_alloc_rx_bds(fp, rx_ring_size);
4135 if (ring_size < rx_ring_size)
4136 goto alloc_mem_err;
4137 }
4138
4139 return 0;
4140
4141 /* handles low memory cases */
4142 alloc_mem_err:
4143 BNX2X_ERR("Unable to allocate full memory for queue %d (size %d)\n",
4144 index, ring_size);
4145 /* FW will drop all packets if queue is not big enough,
4146 * In these cases we disable the queue
4147 * Min size is different for OOO, TPA and non-TPA queues
4148 */
4149 if (ring_size < (fp->disable_tpa ?
4150 MIN_RX_SIZE_NONTPA : MIN_RX_SIZE_TPA)) {
4151 /* release memory allocated for this queue */
4152 bnx2x_free_fp_mem_at(bp, index);
4153 return -ENOMEM;
4154 }
4155 return 0;
4156 }
4157
4158 int bnx2x_alloc_fp_mem_cnic(struct bnx2x *bp)
4159 {
4160 if (!NO_FCOE(bp))
4161 /* FCoE */
4162 if (bnx2x_alloc_fp_mem_at(bp, FCOE_IDX(bp)))
4163 /* we will fail load process instead of mark
4164 * NO_FCOE_FLAG
4165 */
4166 return -ENOMEM;
4167
4168 return 0;
4169 }
4170
4171 int bnx2x_alloc_fp_mem(struct bnx2x *bp)
4172 {
4173 int i;
4174
4175 /* 1. Allocate FP for leading - fatal if error
4176 * 2. Allocate RSS - fix number of queues if error
4177 */
4178
4179 /* leading */
4180 if (bnx2x_alloc_fp_mem_at(bp, 0))
4181 return -ENOMEM;
4182
4183 /* RSS */
4184 for_each_nondefault_eth_queue(bp, i)
4185 if (bnx2x_alloc_fp_mem_at(bp, i))
4186 break;
4187
4188 /* handle memory failures */
4189 if (i != BNX2X_NUM_ETH_QUEUES(bp)) {
4190 int delta = BNX2X_NUM_ETH_QUEUES(bp) - i;
4191
4192 WARN_ON(delta < 0);
4193 bnx2x_shrink_eth_fp(bp, delta);
4194 if (CNIC_SUPPORT(bp))
4195 /* move non eth FPs next to last eth FP
4196 * must be done in that order
4197 * FCOE_IDX < FWD_IDX < OOO_IDX
4198 */
4199
4200 /* move FCoE fp even NO_FCOE_FLAG is on */
4201 bnx2x_move_fp(bp, FCOE_IDX(bp), FCOE_IDX(bp) - delta);
4202 bp->num_ethernet_queues -= delta;
4203 bp->num_queues = bp->num_ethernet_queues +
4204 bp->num_cnic_queues;
4205 BNX2X_ERR("Adjusted num of queues from %d to %d\n",
4206 bp->num_queues + delta, bp->num_queues);
4207 }
4208
4209 return 0;
4210 }
4211
4212 void bnx2x_free_mem_bp(struct bnx2x *bp)
4213 {
4214 int i;
4215
4216 for (i = 0; i < bp->fp_array_size; i++)
4217 kfree(bp->fp[i].tpa_info);
4218 kfree(bp->fp);
4219 kfree(bp->sp_objs);
4220 kfree(bp->fp_stats);
4221 kfree(bp->bnx2x_txq);
4222 kfree(bp->msix_table);
4223 kfree(bp->ilt);
4224 }
4225
4226 int bnx2x_alloc_mem_bp(struct bnx2x *bp)
4227 {
4228 struct bnx2x_fastpath *fp;
4229 struct msix_entry *tbl;
4230 struct bnx2x_ilt *ilt;
4231 int msix_table_size = 0;
4232 int fp_array_size, txq_array_size;
4233 int i;
4234
4235 /*
4236 * The biggest MSI-X table we might need is as a maximum number of fast
4237 * path IGU SBs plus default SB (for PF only).
4238 */
4239 msix_table_size = bp->igu_sb_cnt;
4240 if (IS_PF(bp))
4241 msix_table_size++;
4242 BNX2X_DEV_INFO("msix_table_size %d\n", msix_table_size);
4243
4244 /* fp array: RSS plus CNIC related L2 queues */
4245 fp_array_size = BNX2X_MAX_RSS_COUNT(bp) + CNIC_SUPPORT(bp);
4246 bp->fp_array_size = fp_array_size;
4247 BNX2X_DEV_INFO("fp_array_size %d\n", bp->fp_array_size);
4248
4249 fp = kcalloc(bp->fp_array_size, sizeof(*fp), GFP_KERNEL);
4250 if (!fp)
4251 goto alloc_err;
4252 for (i = 0; i < bp->fp_array_size; i++) {
4253 fp[i].tpa_info =
4254 kcalloc(ETH_MAX_AGGREGATION_QUEUES_E1H_E2,
4255 sizeof(struct bnx2x_agg_info), GFP_KERNEL);
4256 if (!(fp[i].tpa_info))
4257 goto alloc_err;
4258 }
4259
4260 bp->fp = fp;
4261
4262 /* allocate sp objs */
4263 bp->sp_objs = kcalloc(bp->fp_array_size, sizeof(struct bnx2x_sp_objs),
4264 GFP_KERNEL);
4265 if (!bp->sp_objs)
4266 goto alloc_err;
4267
4268 /* allocate fp_stats */
4269 bp->fp_stats = kcalloc(bp->fp_array_size, sizeof(struct bnx2x_fp_stats),
4270 GFP_KERNEL);
4271 if (!bp->fp_stats)
4272 goto alloc_err;
4273
4274 /* Allocate memory for the transmission queues array */
4275 txq_array_size =
4276 BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS + CNIC_SUPPORT(bp);
4277 BNX2X_DEV_INFO("txq_array_size %d", txq_array_size);
4278
4279 bp->bnx2x_txq = kcalloc(txq_array_size, sizeof(struct bnx2x_fp_txdata),
4280 GFP_KERNEL);
4281 if (!bp->bnx2x_txq)
4282 goto alloc_err;
4283
4284 /* msix table */
4285 tbl = kcalloc(msix_table_size, sizeof(*tbl), GFP_KERNEL);
4286 if (!tbl)
4287 goto alloc_err;
4288 bp->msix_table = tbl;
4289
4290 /* ilt */
4291 ilt = kzalloc(sizeof(*ilt), GFP_KERNEL);
4292 if (!ilt)
4293 goto alloc_err;
4294 bp->ilt = ilt;
4295
4296 return 0;
4297 alloc_err:
4298 bnx2x_free_mem_bp(bp);
4299 return -ENOMEM;
4300
4301 }
4302
4303 int bnx2x_reload_if_running(struct net_device *dev)
4304 {
4305 struct bnx2x *bp = netdev_priv(dev);
4306
4307 if (unlikely(!netif_running(dev)))
4308 return 0;
4309
4310 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
4311 return bnx2x_nic_load(bp, LOAD_NORMAL);
4312 }
4313
4314 int bnx2x_get_cur_phy_idx(struct bnx2x *bp)
4315 {
4316 u32 sel_phy_idx = 0;
4317 if (bp->link_params.num_phys <= 1)
4318 return INT_PHY;
4319
4320 if (bp->link_vars.link_up) {
4321 sel_phy_idx = EXT_PHY1;
4322 /* In case link is SERDES, check if the EXT_PHY2 is the one */
4323 if ((bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
4324 (bp->link_params.phy[EXT_PHY2].supported & SUPPORTED_FIBRE))
4325 sel_phy_idx = EXT_PHY2;
4326 } else {
4327
4328 switch (bnx2x_phy_selection(&bp->link_params)) {
4329 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
4330 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
4331 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
4332 sel_phy_idx = EXT_PHY1;
4333 break;
4334 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
4335 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
4336 sel_phy_idx = EXT_PHY2;
4337 break;
4338 }
4339 }
4340
4341 return sel_phy_idx;
4342
4343 }
4344 int bnx2x_get_link_cfg_idx(struct bnx2x *bp)
4345 {
4346 u32 sel_phy_idx = bnx2x_get_cur_phy_idx(bp);
4347 /*
4348 * The selected activated PHY is always after swapping (in case PHY
4349 * swapping is enabled). So when swapping is enabled, we need to reverse
4350 * the configuration
4351 */
4352
4353 if (bp->link_params.multi_phy_config &
4354 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
4355 if (sel_phy_idx == EXT_PHY1)
4356 sel_phy_idx = EXT_PHY2;
4357 else if (sel_phy_idx == EXT_PHY2)
4358 sel_phy_idx = EXT_PHY1;
4359 }
4360 return LINK_CONFIG_IDX(sel_phy_idx);
4361 }
4362
4363 #ifdef NETDEV_FCOE_WWNN
4364 int bnx2x_fcoe_get_wwn(struct net_device *dev, u64 *wwn, int type)
4365 {
4366 struct bnx2x *bp = netdev_priv(dev);
4367 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
4368
4369 switch (type) {
4370 case NETDEV_FCOE_WWNN:
4371 *wwn = HILO_U64(cp->fcoe_wwn_node_name_hi,
4372 cp->fcoe_wwn_node_name_lo);
4373 break;
4374 case NETDEV_FCOE_WWPN:
4375 *wwn = HILO_U64(cp->fcoe_wwn_port_name_hi,
4376 cp->fcoe_wwn_port_name_lo);
4377 break;
4378 default:
4379 BNX2X_ERR("Wrong WWN type requested - %d\n", type);
4380 return -EINVAL;
4381 }
4382
4383 return 0;
4384 }
4385 #endif
4386
4387 /* called with rtnl_lock */
4388 int bnx2x_change_mtu(struct net_device *dev, int new_mtu)
4389 {
4390 struct bnx2x *bp = netdev_priv(dev);
4391
4392 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
4393 BNX2X_ERR("Can't perform change MTU during parity recovery\n");
4394 return -EAGAIN;
4395 }
4396
4397 if ((new_mtu > ETH_MAX_JUMBO_PACKET_SIZE) ||
4398 ((new_mtu + ETH_HLEN) < ETH_MIN_PACKET_SIZE)) {
4399 BNX2X_ERR("Can't support requested MTU size\n");
4400 return -EINVAL;
4401 }
4402
4403 /* This does not race with packet allocation
4404 * because the actual alloc size is
4405 * only updated as part of load
4406 */
4407 dev->mtu = new_mtu;
4408
4409 return bnx2x_reload_if_running(dev);
4410 }
4411
4412 netdev_features_t bnx2x_fix_features(struct net_device *dev,
4413 netdev_features_t features)
4414 {
4415 struct bnx2x *bp = netdev_priv(dev);
4416
4417 /* TPA requires Rx CSUM offloading */
4418 if (!(features & NETIF_F_RXCSUM) || bp->disable_tpa) {
4419 features &= ~NETIF_F_LRO;
4420 features &= ~NETIF_F_GRO;
4421 }
4422
4423 return features;
4424 }
4425
4426 int bnx2x_set_features(struct net_device *dev, netdev_features_t features)
4427 {
4428 struct bnx2x *bp = netdev_priv(dev);
4429 u32 flags = bp->flags;
4430 bool bnx2x_reload = false;
4431
4432 if (features & NETIF_F_LRO)
4433 flags |= TPA_ENABLE_FLAG;
4434 else
4435 flags &= ~TPA_ENABLE_FLAG;
4436
4437 if (features & NETIF_F_GRO)
4438 flags |= GRO_ENABLE_FLAG;
4439 else
4440 flags &= ~GRO_ENABLE_FLAG;
4441
4442 if (features & NETIF_F_LOOPBACK) {
4443 if (bp->link_params.loopback_mode != LOOPBACK_BMAC) {
4444 bp->link_params.loopback_mode = LOOPBACK_BMAC;
4445 bnx2x_reload = true;
4446 }
4447 } else {
4448 if (bp->link_params.loopback_mode != LOOPBACK_NONE) {
4449 bp->link_params.loopback_mode = LOOPBACK_NONE;
4450 bnx2x_reload = true;
4451 }
4452 }
4453
4454 if (flags ^ bp->flags) {
4455 bp->flags = flags;
4456 bnx2x_reload = true;
4457 }
4458
4459 if (bnx2x_reload) {
4460 if (bp->recovery_state == BNX2X_RECOVERY_DONE)
4461 return bnx2x_reload_if_running(dev);
4462 /* else: bnx2x_nic_load() will be called at end of recovery */
4463 }
4464
4465 return 0;
4466 }
4467
4468 void bnx2x_tx_timeout(struct net_device *dev)
4469 {
4470 struct bnx2x *bp = netdev_priv(dev);
4471
4472 #ifdef BNX2X_STOP_ON_ERROR
4473 if (!bp->panic)
4474 bnx2x_panic();
4475 #endif
4476
4477 smp_mb__before_clear_bit();
4478 set_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state);
4479 smp_mb__after_clear_bit();
4480
4481 /* This allows the netif to be shutdown gracefully before resetting */
4482 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4483 }
4484
4485 int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state)
4486 {
4487 struct net_device *dev = pci_get_drvdata(pdev);
4488 struct bnx2x *bp;
4489
4490 if (!dev) {
4491 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
4492 return -ENODEV;
4493 }
4494 bp = netdev_priv(dev);
4495
4496 rtnl_lock();
4497
4498 pci_save_state(pdev);
4499
4500 if (!netif_running(dev)) {
4501 rtnl_unlock();
4502 return 0;
4503 }
4504
4505 netif_device_detach(dev);
4506
4507 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
4508
4509 bnx2x_set_power_state(bp, pci_choose_state(pdev, state));
4510
4511 rtnl_unlock();
4512
4513 return 0;
4514 }
4515
4516 int bnx2x_resume(struct pci_dev *pdev)
4517 {
4518 struct net_device *dev = pci_get_drvdata(pdev);
4519 struct bnx2x *bp;
4520 int rc;
4521
4522 if (!dev) {
4523 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
4524 return -ENODEV;
4525 }
4526 bp = netdev_priv(dev);
4527
4528 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
4529 BNX2X_ERR("Handling parity error recovery. Try again later\n");
4530 return -EAGAIN;
4531 }
4532
4533 rtnl_lock();
4534
4535 pci_restore_state(pdev);
4536
4537 if (!netif_running(dev)) {
4538 rtnl_unlock();
4539 return 0;
4540 }
4541
4542 bnx2x_set_power_state(bp, PCI_D0);
4543 netif_device_attach(dev);
4544
4545 rc = bnx2x_nic_load(bp, LOAD_OPEN);
4546
4547 rtnl_unlock();
4548
4549 return rc;
4550 }
4551
4552
4553 void bnx2x_set_ctx_validation(struct bnx2x *bp, struct eth_context *cxt,
4554 u32 cid)
4555 {
4556 /* ustorm cxt validation */
4557 cxt->ustorm_ag_context.cdu_usage =
4558 CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, cid),
4559 CDU_REGION_NUMBER_UCM_AG, ETH_CONNECTION_TYPE);
4560 /* xcontext validation */
4561 cxt->xstorm_ag_context.cdu_reserved =
4562 CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, cid),
4563 CDU_REGION_NUMBER_XCM_AG, ETH_CONNECTION_TYPE);
4564 }
4565
4566 static void storm_memset_hc_timeout(struct bnx2x *bp, u8 port,
4567 u8 fw_sb_id, u8 sb_index,
4568 u8 ticks)
4569 {
4570
4571 u32 addr = BAR_CSTRORM_INTMEM +
4572 CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index);
4573 REG_WR8(bp, addr, ticks);
4574 DP(NETIF_MSG_IFUP,
4575 "port %x fw_sb_id %d sb_index %d ticks %d\n",
4576 port, fw_sb_id, sb_index, ticks);
4577 }
4578
4579 static void storm_memset_hc_disable(struct bnx2x *bp, u8 port,
4580 u16 fw_sb_id, u8 sb_index,
4581 u8 disable)
4582 {
4583 u32 enable_flag = disable ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
4584 u32 addr = BAR_CSTRORM_INTMEM +
4585 CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index);
4586 u8 flags = REG_RD8(bp, addr);
4587 /* clear and set */
4588 flags &= ~HC_INDEX_DATA_HC_ENABLED;
4589 flags |= enable_flag;
4590 REG_WR8(bp, addr, flags);
4591 DP(NETIF_MSG_IFUP,
4592 "port %x fw_sb_id %d sb_index %d disable %d\n",
4593 port, fw_sb_id, sb_index, disable);
4594 }
4595
4596 void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u8 fw_sb_id,
4597 u8 sb_index, u8 disable, u16 usec)
4598 {
4599 int port = BP_PORT(bp);
4600 u8 ticks = usec / BNX2X_BTR;
4601
4602 storm_memset_hc_timeout(bp, port, fw_sb_id, sb_index, ticks);
4603
4604 disable = disable ? 1 : (usec ? 0 : 1);
4605 storm_memset_hc_disable(bp, port, fw_sb_id, sb_index, disable);
4606 }
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