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Merge tag 'armsoc-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
[mirror_ubuntu-eoan-kernel.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_ethtool.c
1 /* bnx2x_ethtool.c: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2013 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
20 #include <linux/ethtool.h>
21 #include <linux/netdevice.h>
22 #include <linux/types.h>
23 #include <linux/sched.h>
24 #include <linux/crc32.h>
25 #include "bnx2x.h"
26 #include "bnx2x_cmn.h"
27 #include "bnx2x_dump.h"
28 #include "bnx2x_init.h"
29
30 /* Note: in the format strings below %s is replaced by the queue-name which is
31 * either its index or 'fcoe' for the fcoe queue. Make sure the format string
32 * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
33 */
34 #define MAX_QUEUE_NAME_LEN 4
35 static const struct {
36 long offset;
37 int size;
38 char string[ETH_GSTRING_LEN];
39 } bnx2x_q_stats_arr[] = {
40 /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
41 { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
42 8, "[%s]: rx_ucast_packets" },
43 { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
44 8, "[%s]: rx_mcast_packets" },
45 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
46 8, "[%s]: rx_bcast_packets" },
47 { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
48 { Q_STATS_OFFSET32(rx_err_discard_pkt),
49 4, "[%s]: rx_phy_ip_err_discards"},
50 { Q_STATS_OFFSET32(rx_skb_alloc_failed),
51 4, "[%s]: rx_skb_alloc_discard" },
52 { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
53
54 { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
55 /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
56 8, "[%s]: tx_ucast_packets" },
57 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
58 8, "[%s]: tx_mcast_packets" },
59 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
60 8, "[%s]: tx_bcast_packets" },
61 { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
62 8, "[%s]: tpa_aggregations" },
63 { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
64 8, "[%s]: tpa_aggregated_frames"},
65 { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"},
66 { Q_STATS_OFFSET32(driver_filtered_tx_pkt),
67 4, "[%s]: driver_filtered_tx_pkt" }
68 };
69
70 #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
71
72 static const struct {
73 long offset;
74 int size;
75 u32 flags;
76 #define STATS_FLAGS_PORT 1
77 #define STATS_FLAGS_FUNC 2
78 #define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
79 char string[ETH_GSTRING_LEN];
80 } bnx2x_stats_arr[] = {
81 /* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
82 8, STATS_FLAGS_BOTH, "rx_bytes" },
83 { STATS_OFFSET32(error_bytes_received_hi),
84 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
85 { STATS_OFFSET32(total_unicast_packets_received_hi),
86 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
87 { STATS_OFFSET32(total_multicast_packets_received_hi),
88 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
89 { STATS_OFFSET32(total_broadcast_packets_received_hi),
90 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
91 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
92 8, STATS_FLAGS_PORT, "rx_crc_errors" },
93 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
94 8, STATS_FLAGS_PORT, "rx_align_errors" },
95 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
96 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
97 { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
98 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
99 /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
100 8, STATS_FLAGS_PORT, "rx_fragments" },
101 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
102 8, STATS_FLAGS_PORT, "rx_jabbers" },
103 { STATS_OFFSET32(no_buff_discard_hi),
104 8, STATS_FLAGS_BOTH, "rx_discards" },
105 { STATS_OFFSET32(mac_filter_discard),
106 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
107 { STATS_OFFSET32(mf_tag_discard),
108 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" },
109 { STATS_OFFSET32(pfc_frames_received_hi),
110 8, STATS_FLAGS_PORT, "pfc_frames_received" },
111 { STATS_OFFSET32(pfc_frames_sent_hi),
112 8, STATS_FLAGS_PORT, "pfc_frames_sent" },
113 { STATS_OFFSET32(brb_drop_hi),
114 8, STATS_FLAGS_PORT, "rx_brb_discard" },
115 { STATS_OFFSET32(brb_truncate_hi),
116 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
117 { STATS_OFFSET32(pause_frames_received_hi),
118 8, STATS_FLAGS_PORT, "rx_pause_frames" },
119 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
120 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
121 { STATS_OFFSET32(nig_timer_max),
122 4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
123 /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
124 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
125 { STATS_OFFSET32(rx_skb_alloc_failed),
126 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
127 { STATS_OFFSET32(hw_csum_err),
128 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
129
130 { STATS_OFFSET32(total_bytes_transmitted_hi),
131 8, STATS_FLAGS_BOTH, "tx_bytes" },
132 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
133 8, STATS_FLAGS_PORT, "tx_error_bytes" },
134 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
135 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
136 { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
137 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
138 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
139 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
140 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
141 8, STATS_FLAGS_PORT, "tx_mac_errors" },
142 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
143 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
144 /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
145 8, STATS_FLAGS_PORT, "tx_single_collisions" },
146 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
147 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
148 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
149 8, STATS_FLAGS_PORT, "tx_deferred" },
150 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
151 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
152 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
153 8, STATS_FLAGS_PORT, "tx_late_collisions" },
154 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
155 8, STATS_FLAGS_PORT, "tx_total_collisions" },
156 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
157 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
158 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
159 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
160 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
161 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
162 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
163 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
164 /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
165 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
166 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
167 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
168 { STATS_OFFSET32(etherstatspktsover1522octets_hi),
169 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
170 { STATS_OFFSET32(pause_frames_sent_hi),
171 8, STATS_FLAGS_PORT, "tx_pause_frames" },
172 { STATS_OFFSET32(total_tpa_aggregations_hi),
173 8, STATS_FLAGS_FUNC, "tpa_aggregations" },
174 { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
175 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"},
176 { STATS_OFFSET32(total_tpa_bytes_hi),
177 8, STATS_FLAGS_FUNC, "tpa_bytes"},
178 { STATS_OFFSET32(recoverable_error),
179 4, STATS_FLAGS_FUNC, "recoverable_errors" },
180 { STATS_OFFSET32(unrecoverable_error),
181 4, STATS_FLAGS_FUNC, "unrecoverable_errors" },
182 { STATS_OFFSET32(driver_filtered_tx_pkt),
183 4, STATS_FLAGS_FUNC, "driver_filtered_tx_pkt" },
184 { STATS_OFFSET32(eee_tx_lpi),
185 4, STATS_FLAGS_PORT, "Tx LPI entry count"}
186 };
187
188 #define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr)
189
190 static int bnx2x_get_port_type(struct bnx2x *bp)
191 {
192 int port_type;
193 u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
194 switch (bp->link_params.phy[phy_idx].media_type) {
195 case ETH_PHY_SFPP_10G_FIBER:
196 case ETH_PHY_SFP_1G_FIBER:
197 case ETH_PHY_XFP_FIBER:
198 case ETH_PHY_KR:
199 case ETH_PHY_CX4:
200 port_type = PORT_FIBRE;
201 break;
202 case ETH_PHY_DA_TWINAX:
203 port_type = PORT_DA;
204 break;
205 case ETH_PHY_BASE_T:
206 port_type = PORT_TP;
207 break;
208 case ETH_PHY_NOT_PRESENT:
209 port_type = PORT_NONE;
210 break;
211 case ETH_PHY_UNSPECIFIED:
212 default:
213 port_type = PORT_OTHER;
214 break;
215 }
216 return port_type;
217 }
218
219 static int bnx2x_get_vf_settings(struct net_device *dev,
220 struct ethtool_cmd *cmd)
221 {
222 struct bnx2x *bp = netdev_priv(dev);
223
224 if (bp->state == BNX2X_STATE_OPEN) {
225 if (test_bit(BNX2X_LINK_REPORT_FD,
226 &bp->vf_link_vars.link_report_flags))
227 cmd->duplex = DUPLEX_FULL;
228 else
229 cmd->duplex = DUPLEX_HALF;
230
231 ethtool_cmd_speed_set(cmd, bp->vf_link_vars.line_speed);
232 } else {
233 cmd->duplex = DUPLEX_UNKNOWN;
234 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
235 }
236
237 cmd->port = PORT_OTHER;
238 cmd->phy_address = 0;
239 cmd->transceiver = XCVR_INTERNAL;
240 cmd->autoneg = AUTONEG_DISABLE;
241 cmd->maxtxpkt = 0;
242 cmd->maxrxpkt = 0;
243
244 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
245 " supported 0x%x advertising 0x%x speed %u\n"
246 " duplex %d port %d phy_address %d transceiver %d\n"
247 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
248 cmd->cmd, cmd->supported, cmd->advertising,
249 ethtool_cmd_speed(cmd),
250 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
251 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
252
253 return 0;
254 }
255
256 static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
257 {
258 struct bnx2x *bp = netdev_priv(dev);
259 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
260 u32 media_type;
261
262 /* Dual Media boards present all available port types */
263 cmd->supported = bp->port.supported[cfg_idx] |
264 (bp->port.supported[cfg_idx ^ 1] &
265 (SUPPORTED_TP | SUPPORTED_FIBRE));
266 cmd->advertising = bp->port.advertising[cfg_idx];
267 media_type = bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type;
268 if (media_type == ETH_PHY_SFP_1G_FIBER) {
269 cmd->supported &= ~(SUPPORTED_10000baseT_Full);
270 cmd->advertising &= ~(ADVERTISED_10000baseT_Full);
271 }
272
273 if ((bp->state == BNX2X_STATE_OPEN) && bp->link_vars.link_up &&
274 !(bp->flags & MF_FUNC_DIS)) {
275 cmd->duplex = bp->link_vars.duplex;
276
277 if (IS_MF(bp) && !BP_NOMCP(bp))
278 ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
279 else
280 ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
281 } else {
282 cmd->duplex = DUPLEX_UNKNOWN;
283 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
284 }
285
286 cmd->port = bnx2x_get_port_type(bp);
287
288 cmd->phy_address = bp->mdio.prtad;
289 cmd->transceiver = XCVR_INTERNAL;
290
291 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
292 cmd->autoneg = AUTONEG_ENABLE;
293 else
294 cmd->autoneg = AUTONEG_DISABLE;
295
296 /* Publish LP advertised speeds and FC */
297 if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
298 u32 status = bp->link_vars.link_status;
299
300 cmd->lp_advertising |= ADVERTISED_Autoneg;
301 if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE)
302 cmd->lp_advertising |= ADVERTISED_Pause;
303 if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
304 cmd->lp_advertising |= ADVERTISED_Asym_Pause;
305
306 if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE)
307 cmd->lp_advertising |= ADVERTISED_10baseT_Half;
308 if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE)
309 cmd->lp_advertising |= ADVERTISED_10baseT_Full;
310 if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE)
311 cmd->lp_advertising |= ADVERTISED_100baseT_Half;
312 if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE)
313 cmd->lp_advertising |= ADVERTISED_100baseT_Full;
314 if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE)
315 cmd->lp_advertising |= ADVERTISED_1000baseT_Half;
316 if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) {
317 if (media_type == ETH_PHY_KR) {
318 cmd->lp_advertising |=
319 ADVERTISED_1000baseKX_Full;
320 } else {
321 cmd->lp_advertising |=
322 ADVERTISED_1000baseT_Full;
323 }
324 }
325 if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE)
326 cmd->lp_advertising |= ADVERTISED_2500baseX_Full;
327 if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE) {
328 if (media_type == ETH_PHY_KR) {
329 cmd->lp_advertising |=
330 ADVERTISED_10000baseKR_Full;
331 } else {
332 cmd->lp_advertising |=
333 ADVERTISED_10000baseT_Full;
334 }
335 }
336 if (status & LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE)
337 cmd->lp_advertising |= ADVERTISED_20000baseKR2_Full;
338 }
339
340 cmd->maxtxpkt = 0;
341 cmd->maxrxpkt = 0;
342
343 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
344 " supported 0x%x advertising 0x%x speed %u\n"
345 " duplex %d port %d phy_address %d transceiver %d\n"
346 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
347 cmd->cmd, cmd->supported, cmd->advertising,
348 ethtool_cmd_speed(cmd),
349 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
350 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
351
352 return 0;
353 }
354
355 static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
356 {
357 struct bnx2x *bp = netdev_priv(dev);
358 u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
359 u32 speed, phy_idx;
360
361 if (IS_MF_SD(bp))
362 return 0;
363
364 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
365 " supported 0x%x advertising 0x%x speed %u\n"
366 " duplex %d port %d phy_address %d transceiver %d\n"
367 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
368 cmd->cmd, cmd->supported, cmd->advertising,
369 ethtool_cmd_speed(cmd),
370 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
371 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
372
373 speed = ethtool_cmd_speed(cmd);
374
375 /* If received a request for an unknown duplex, assume full*/
376 if (cmd->duplex == DUPLEX_UNKNOWN)
377 cmd->duplex = DUPLEX_FULL;
378
379 if (IS_MF_SI(bp)) {
380 u32 part;
381 u32 line_speed = bp->link_vars.line_speed;
382
383 /* use 10G if no link detected */
384 if (!line_speed)
385 line_speed = 10000;
386
387 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
388 DP(BNX2X_MSG_ETHTOOL,
389 "To set speed BC %X or higher is required, please upgrade BC\n",
390 REQ_BC_VER_4_SET_MF_BW);
391 return -EINVAL;
392 }
393
394 part = (speed * 100) / line_speed;
395
396 if (line_speed < speed || !part) {
397 DP(BNX2X_MSG_ETHTOOL,
398 "Speed setting should be in a range from 1%% to 100%% of actual line speed\n");
399 return -EINVAL;
400 }
401
402 if (bp->state != BNX2X_STATE_OPEN)
403 /* store value for following "load" */
404 bp->pending_max = part;
405 else
406 bnx2x_update_max_mf_config(bp, part);
407
408 return 0;
409 }
410
411 cfg_idx = bnx2x_get_link_cfg_idx(bp);
412 old_multi_phy_config = bp->link_params.multi_phy_config;
413 if (cmd->port != bnx2x_get_port_type(bp)) {
414 switch (cmd->port) {
415 case PORT_TP:
416 if (!(bp->port.supported[0] & SUPPORTED_TP ||
417 bp->port.supported[1] & SUPPORTED_TP)) {
418 DP(BNX2X_MSG_ETHTOOL,
419 "Unsupported port type\n");
420 return -EINVAL;
421 }
422 bp->link_params.multi_phy_config &=
423 ~PORT_HW_CFG_PHY_SELECTION_MASK;
424 if (bp->link_params.multi_phy_config &
425 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
426 bp->link_params.multi_phy_config |=
427 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
428 else
429 bp->link_params.multi_phy_config |=
430 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
431 break;
432 case PORT_FIBRE:
433 case PORT_DA:
434 case PORT_NONE:
435 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
436 bp->port.supported[1] & SUPPORTED_FIBRE)) {
437 DP(BNX2X_MSG_ETHTOOL,
438 "Unsupported port type\n");
439 return -EINVAL;
440 }
441 bp->link_params.multi_phy_config &=
442 ~PORT_HW_CFG_PHY_SELECTION_MASK;
443 if (bp->link_params.multi_phy_config &
444 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
445 bp->link_params.multi_phy_config |=
446 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
447 else
448 bp->link_params.multi_phy_config |=
449 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
450 break;
451 default:
452 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
453 return -EINVAL;
454 }
455 }
456 /* Save new config in case command complete successfully */
457 new_multi_phy_config = bp->link_params.multi_phy_config;
458 /* Get the new cfg_idx */
459 cfg_idx = bnx2x_get_link_cfg_idx(bp);
460 /* Restore old config in case command failed */
461 bp->link_params.multi_phy_config = old_multi_phy_config;
462 DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx);
463
464 if (cmd->autoneg == AUTONEG_ENABLE) {
465 u32 an_supported_speed = bp->port.supported[cfg_idx];
466 if (bp->link_params.phy[EXT_PHY1].type ==
467 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
468 an_supported_speed |= (SUPPORTED_100baseT_Half |
469 SUPPORTED_100baseT_Full);
470 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
471 DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n");
472 return -EINVAL;
473 }
474
475 /* advertise the requested speed and duplex if supported */
476 if (cmd->advertising & ~an_supported_speed) {
477 DP(BNX2X_MSG_ETHTOOL,
478 "Advertisement parameters are not supported\n");
479 return -EINVAL;
480 }
481
482 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
483 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
484 bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg |
485 cmd->advertising);
486 if (cmd->advertising) {
487
488 bp->link_params.speed_cap_mask[cfg_idx] = 0;
489 if (cmd->advertising & ADVERTISED_10baseT_Half) {
490 bp->link_params.speed_cap_mask[cfg_idx] |=
491 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF;
492 }
493 if (cmd->advertising & ADVERTISED_10baseT_Full)
494 bp->link_params.speed_cap_mask[cfg_idx] |=
495 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL;
496
497 if (cmd->advertising & ADVERTISED_100baseT_Full)
498 bp->link_params.speed_cap_mask[cfg_idx] |=
499 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL;
500
501 if (cmd->advertising & ADVERTISED_100baseT_Half) {
502 bp->link_params.speed_cap_mask[cfg_idx] |=
503 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF;
504 }
505 if (cmd->advertising & ADVERTISED_1000baseT_Half) {
506 bp->link_params.speed_cap_mask[cfg_idx] |=
507 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
508 }
509 if (cmd->advertising & (ADVERTISED_1000baseT_Full |
510 ADVERTISED_1000baseKX_Full))
511 bp->link_params.speed_cap_mask[cfg_idx] |=
512 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
513
514 if (cmd->advertising & (ADVERTISED_10000baseT_Full |
515 ADVERTISED_10000baseKX4_Full |
516 ADVERTISED_10000baseKR_Full))
517 bp->link_params.speed_cap_mask[cfg_idx] |=
518 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G;
519
520 if (cmd->advertising & ADVERTISED_20000baseKR2_Full)
521 bp->link_params.speed_cap_mask[cfg_idx] |=
522 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G;
523 }
524 } else { /* forced speed */
525 /* advertise the requested speed and duplex if supported */
526 switch (speed) {
527 case SPEED_10:
528 if (cmd->duplex == DUPLEX_FULL) {
529 if (!(bp->port.supported[cfg_idx] &
530 SUPPORTED_10baseT_Full)) {
531 DP(BNX2X_MSG_ETHTOOL,
532 "10M full not supported\n");
533 return -EINVAL;
534 }
535
536 advertising = (ADVERTISED_10baseT_Full |
537 ADVERTISED_TP);
538 } else {
539 if (!(bp->port.supported[cfg_idx] &
540 SUPPORTED_10baseT_Half)) {
541 DP(BNX2X_MSG_ETHTOOL,
542 "10M half not supported\n");
543 return -EINVAL;
544 }
545
546 advertising = (ADVERTISED_10baseT_Half |
547 ADVERTISED_TP);
548 }
549 break;
550
551 case SPEED_100:
552 if (cmd->duplex == DUPLEX_FULL) {
553 if (!(bp->port.supported[cfg_idx] &
554 SUPPORTED_100baseT_Full)) {
555 DP(BNX2X_MSG_ETHTOOL,
556 "100M full not supported\n");
557 return -EINVAL;
558 }
559
560 advertising = (ADVERTISED_100baseT_Full |
561 ADVERTISED_TP);
562 } else {
563 if (!(bp->port.supported[cfg_idx] &
564 SUPPORTED_100baseT_Half)) {
565 DP(BNX2X_MSG_ETHTOOL,
566 "100M half not supported\n");
567 return -EINVAL;
568 }
569
570 advertising = (ADVERTISED_100baseT_Half |
571 ADVERTISED_TP);
572 }
573 break;
574
575 case SPEED_1000:
576 if (cmd->duplex != DUPLEX_FULL) {
577 DP(BNX2X_MSG_ETHTOOL,
578 "1G half not supported\n");
579 return -EINVAL;
580 }
581
582 if (bp->port.supported[cfg_idx] &
583 SUPPORTED_1000baseT_Full) {
584 advertising = (ADVERTISED_1000baseT_Full |
585 ADVERTISED_TP);
586
587 } else if (bp->port.supported[cfg_idx] &
588 SUPPORTED_1000baseKX_Full) {
589 advertising = ADVERTISED_1000baseKX_Full;
590 } else {
591 DP(BNX2X_MSG_ETHTOOL,
592 "1G full not supported\n");
593 return -EINVAL;
594 }
595
596 break;
597
598 case SPEED_2500:
599 if (cmd->duplex != DUPLEX_FULL) {
600 DP(BNX2X_MSG_ETHTOOL,
601 "2.5G half not supported\n");
602 return -EINVAL;
603 }
604
605 if (!(bp->port.supported[cfg_idx]
606 & SUPPORTED_2500baseX_Full)) {
607 DP(BNX2X_MSG_ETHTOOL,
608 "2.5G full not supported\n");
609 return -EINVAL;
610 }
611
612 advertising = (ADVERTISED_2500baseX_Full |
613 ADVERTISED_TP);
614 break;
615
616 case SPEED_10000:
617 if (cmd->duplex != DUPLEX_FULL) {
618 DP(BNX2X_MSG_ETHTOOL,
619 "10G half not supported\n");
620 return -EINVAL;
621 }
622 phy_idx = bnx2x_get_cur_phy_idx(bp);
623 if ((bp->port.supported[cfg_idx] &
624 SUPPORTED_10000baseT_Full) &&
625 (bp->link_params.phy[phy_idx].media_type !=
626 ETH_PHY_SFP_1G_FIBER)) {
627 advertising = (ADVERTISED_10000baseT_Full |
628 ADVERTISED_FIBRE);
629 } else if (bp->port.supported[cfg_idx] &
630 SUPPORTED_10000baseKR_Full) {
631 advertising = (ADVERTISED_10000baseKR_Full |
632 ADVERTISED_FIBRE);
633 } else {
634 DP(BNX2X_MSG_ETHTOOL,
635 "10G full not supported\n");
636 return -EINVAL;
637 }
638
639 break;
640
641 default:
642 DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed);
643 return -EINVAL;
644 }
645
646 bp->link_params.req_line_speed[cfg_idx] = speed;
647 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
648 bp->port.advertising[cfg_idx] = advertising;
649 }
650
651 DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n"
652 " req_duplex %d advertising 0x%x\n",
653 bp->link_params.req_line_speed[cfg_idx],
654 bp->link_params.req_duplex[cfg_idx],
655 bp->port.advertising[cfg_idx]);
656
657 /* Set new config */
658 bp->link_params.multi_phy_config = new_multi_phy_config;
659 if (netif_running(dev)) {
660 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
661 bnx2x_force_link_reset(bp);
662 bnx2x_link_set(bp);
663 }
664
665 return 0;
666 }
667
668 #define DUMP_ALL_PRESETS 0x1FFF
669 #define DUMP_MAX_PRESETS 13
670
671 static int __bnx2x_get_preset_regs_len(struct bnx2x *bp, u32 preset)
672 {
673 if (CHIP_IS_E1(bp))
674 return dump_num_registers[0][preset-1];
675 else if (CHIP_IS_E1H(bp))
676 return dump_num_registers[1][preset-1];
677 else if (CHIP_IS_E2(bp))
678 return dump_num_registers[2][preset-1];
679 else if (CHIP_IS_E3A0(bp))
680 return dump_num_registers[3][preset-1];
681 else if (CHIP_IS_E3B0(bp))
682 return dump_num_registers[4][preset-1];
683 else
684 return 0;
685 }
686
687 static int __bnx2x_get_regs_len(struct bnx2x *bp)
688 {
689 u32 preset_idx;
690 int regdump_len = 0;
691
692 /* Calculate the total preset regs length */
693 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++)
694 regdump_len += __bnx2x_get_preset_regs_len(bp, preset_idx);
695
696 return regdump_len;
697 }
698
699 static int bnx2x_get_regs_len(struct net_device *dev)
700 {
701 struct bnx2x *bp = netdev_priv(dev);
702 int regdump_len = 0;
703
704 if (IS_VF(bp))
705 return 0;
706
707 regdump_len = __bnx2x_get_regs_len(bp);
708 regdump_len *= 4;
709 regdump_len += sizeof(struct dump_header);
710
711 return regdump_len;
712 }
713
714 #define IS_E1_REG(chips) ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1)
715 #define IS_E1H_REG(chips) ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H)
716 #define IS_E2_REG(chips) ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2)
717 #define IS_E3A0_REG(chips) ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0)
718 #define IS_E3B0_REG(chips) ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0)
719
720 #define IS_REG_IN_PRESET(presets, idx) \
721 ((presets & (1 << (idx-1))) == (1 << (idx-1)))
722
723 /******* Paged registers info selectors ********/
724 static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
725 {
726 if (CHIP_IS_E2(bp))
727 return page_vals_e2;
728 else if (CHIP_IS_E3(bp))
729 return page_vals_e3;
730 else
731 return NULL;
732 }
733
734 static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
735 {
736 if (CHIP_IS_E2(bp))
737 return PAGE_MODE_VALUES_E2;
738 else if (CHIP_IS_E3(bp))
739 return PAGE_MODE_VALUES_E3;
740 else
741 return 0;
742 }
743
744 static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
745 {
746 if (CHIP_IS_E2(bp))
747 return page_write_regs_e2;
748 else if (CHIP_IS_E3(bp))
749 return page_write_regs_e3;
750 else
751 return NULL;
752 }
753
754 static u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
755 {
756 if (CHIP_IS_E2(bp))
757 return PAGE_WRITE_REGS_E2;
758 else if (CHIP_IS_E3(bp))
759 return PAGE_WRITE_REGS_E3;
760 else
761 return 0;
762 }
763
764 static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
765 {
766 if (CHIP_IS_E2(bp))
767 return page_read_regs_e2;
768 else if (CHIP_IS_E3(bp))
769 return page_read_regs_e3;
770 else
771 return NULL;
772 }
773
774 static u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
775 {
776 if (CHIP_IS_E2(bp))
777 return PAGE_READ_REGS_E2;
778 else if (CHIP_IS_E3(bp))
779 return PAGE_READ_REGS_E3;
780 else
781 return 0;
782 }
783
784 static bool bnx2x_is_reg_in_chip(struct bnx2x *bp,
785 const struct reg_addr *reg_info)
786 {
787 if (CHIP_IS_E1(bp))
788 return IS_E1_REG(reg_info->chips);
789 else if (CHIP_IS_E1H(bp))
790 return IS_E1H_REG(reg_info->chips);
791 else if (CHIP_IS_E2(bp))
792 return IS_E2_REG(reg_info->chips);
793 else if (CHIP_IS_E3A0(bp))
794 return IS_E3A0_REG(reg_info->chips);
795 else if (CHIP_IS_E3B0(bp))
796 return IS_E3B0_REG(reg_info->chips);
797 else
798 return false;
799 }
800
801 static bool bnx2x_is_wreg_in_chip(struct bnx2x *bp,
802 const struct wreg_addr *wreg_info)
803 {
804 if (CHIP_IS_E1(bp))
805 return IS_E1_REG(wreg_info->chips);
806 else if (CHIP_IS_E1H(bp))
807 return IS_E1H_REG(wreg_info->chips);
808 else if (CHIP_IS_E2(bp))
809 return IS_E2_REG(wreg_info->chips);
810 else if (CHIP_IS_E3A0(bp))
811 return IS_E3A0_REG(wreg_info->chips);
812 else if (CHIP_IS_E3B0(bp))
813 return IS_E3B0_REG(wreg_info->chips);
814 else
815 return false;
816 }
817
818 /**
819 * bnx2x_read_pages_regs - read "paged" registers
820 *
821 * @bp device handle
822 * @p output buffer
823 *
824 * Reads "paged" memories: memories that may only be read by first writing to a
825 * specific address ("write address") and then reading from a specific address
826 * ("read address"). There may be more than one write address per "page" and
827 * more than one read address per write address.
828 */
829 static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p, u32 preset)
830 {
831 u32 i, j, k, n;
832
833 /* addresses of the paged registers */
834 const u32 *page_addr = __bnx2x_get_page_addr_ar(bp);
835 /* number of paged registers */
836 int num_pages = __bnx2x_get_page_reg_num(bp);
837 /* write addresses */
838 const u32 *write_addr = __bnx2x_get_page_write_ar(bp);
839 /* number of write addresses */
840 int write_num = __bnx2x_get_page_write_num(bp);
841 /* read addresses info */
842 const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
843 /* number of read addresses */
844 int read_num = __bnx2x_get_page_read_num(bp);
845 u32 addr, size;
846
847 for (i = 0; i < num_pages; i++) {
848 for (j = 0; j < write_num; j++) {
849 REG_WR(bp, write_addr[j], page_addr[i]);
850
851 for (k = 0; k < read_num; k++) {
852 if (IS_REG_IN_PRESET(read_addr[k].presets,
853 preset)) {
854 size = read_addr[k].size;
855 for (n = 0; n < size; n++) {
856 addr = read_addr[k].addr + n*4;
857 *p++ = REG_RD(bp, addr);
858 }
859 }
860 }
861 }
862 }
863 }
864
865 static int __bnx2x_get_preset_regs(struct bnx2x *bp, u32 *p, u32 preset)
866 {
867 u32 i, j, addr;
868 const struct wreg_addr *wreg_addr_p = NULL;
869
870 if (CHIP_IS_E1(bp))
871 wreg_addr_p = &wreg_addr_e1;
872 else if (CHIP_IS_E1H(bp))
873 wreg_addr_p = &wreg_addr_e1h;
874 else if (CHIP_IS_E2(bp))
875 wreg_addr_p = &wreg_addr_e2;
876 else if (CHIP_IS_E3A0(bp))
877 wreg_addr_p = &wreg_addr_e3;
878 else if (CHIP_IS_E3B0(bp))
879 wreg_addr_p = &wreg_addr_e3b0;
880
881 /* Read the idle_chk registers */
882 for (i = 0; i < IDLE_REGS_COUNT; i++) {
883 if (bnx2x_is_reg_in_chip(bp, &idle_reg_addrs[i]) &&
884 IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) {
885 for (j = 0; j < idle_reg_addrs[i].size; j++)
886 *p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4);
887 }
888 }
889
890 /* Read the regular registers */
891 for (i = 0; i < REGS_COUNT; i++) {
892 if (bnx2x_is_reg_in_chip(bp, &reg_addrs[i]) &&
893 IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) {
894 for (j = 0; j < reg_addrs[i].size; j++)
895 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
896 }
897 }
898
899 /* Read the CAM registers */
900 if (bnx2x_is_wreg_in_chip(bp, wreg_addr_p) &&
901 IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) {
902 for (i = 0; i < wreg_addr_p->size; i++) {
903 *p++ = REG_RD(bp, wreg_addr_p->addr + i*4);
904
905 /* In case of wreg_addr register, read additional
906 registers from read_regs array
907 */
908 for (j = 0; j < wreg_addr_p->read_regs_count; j++) {
909 addr = *(wreg_addr_p->read_regs);
910 *p++ = REG_RD(bp, addr + j*4);
911 }
912 }
913 }
914
915 /* Paged registers are supported in E2 & E3 only */
916 if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) {
917 /* Read "paged" registers */
918 bnx2x_read_pages_regs(bp, p, preset);
919 }
920
921 return 0;
922 }
923
924 static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
925 {
926 u32 preset_idx;
927
928 /* Read all registers, by reading all preset registers */
929 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) {
930 /* Skip presets with IOR */
931 if ((preset_idx == 2) ||
932 (preset_idx == 5) ||
933 (preset_idx == 8) ||
934 (preset_idx == 11))
935 continue;
936 __bnx2x_get_preset_regs(bp, p, preset_idx);
937 p += __bnx2x_get_preset_regs_len(bp, preset_idx);
938 }
939 }
940
941 static void bnx2x_get_regs(struct net_device *dev,
942 struct ethtool_regs *regs, void *_p)
943 {
944 u32 *p = _p;
945 struct bnx2x *bp = netdev_priv(dev);
946 struct dump_header dump_hdr = {0};
947
948 regs->version = 2;
949 memset(p, 0, regs->len);
950
951 if (!netif_running(bp->dev))
952 return;
953
954 /* Disable parity attentions as long as following dump may
955 * cause false alarms by reading never written registers. We
956 * will re-enable parity attentions right after the dump.
957 */
958
959 bnx2x_disable_blocks_parity(bp);
960
961 dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
962 dump_hdr.preset = DUMP_ALL_PRESETS;
963 dump_hdr.version = BNX2X_DUMP_VERSION;
964
965 /* dump_meta_data presents OR of CHIP and PATH. */
966 if (CHIP_IS_E1(bp)) {
967 dump_hdr.dump_meta_data = DUMP_CHIP_E1;
968 } else if (CHIP_IS_E1H(bp)) {
969 dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
970 } else if (CHIP_IS_E2(bp)) {
971 dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
972 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
973 } else if (CHIP_IS_E3A0(bp)) {
974 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
975 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
976 } else if (CHIP_IS_E3B0(bp)) {
977 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
978 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
979 }
980
981 memcpy(p, &dump_hdr, sizeof(struct dump_header));
982 p += dump_hdr.header_size + 1;
983
984 /* Actually read the registers */
985 __bnx2x_get_regs(bp, p);
986
987 /* Re-enable parity attentions */
988 bnx2x_clear_blocks_parity(bp);
989 bnx2x_enable_blocks_parity(bp);
990 }
991
992 static int bnx2x_get_preset_regs_len(struct net_device *dev, u32 preset)
993 {
994 struct bnx2x *bp = netdev_priv(dev);
995 int regdump_len = 0;
996
997 regdump_len = __bnx2x_get_preset_regs_len(bp, preset);
998 regdump_len *= 4;
999 regdump_len += sizeof(struct dump_header);
1000
1001 return regdump_len;
1002 }
1003
1004 static int bnx2x_set_dump(struct net_device *dev, struct ethtool_dump *val)
1005 {
1006 struct bnx2x *bp = netdev_priv(dev);
1007
1008 /* Use the ethtool_dump "flag" field as the dump preset index */
1009 if (val->flag < 1 || val->flag > DUMP_MAX_PRESETS)
1010 return -EINVAL;
1011
1012 bp->dump_preset_idx = val->flag;
1013 return 0;
1014 }
1015
1016 static int bnx2x_get_dump_flag(struct net_device *dev,
1017 struct ethtool_dump *dump)
1018 {
1019 struct bnx2x *bp = netdev_priv(dev);
1020
1021 dump->version = BNX2X_DUMP_VERSION;
1022 dump->flag = bp->dump_preset_idx;
1023 /* Calculate the requested preset idx length */
1024 dump->len = bnx2x_get_preset_regs_len(dev, bp->dump_preset_idx);
1025 DP(BNX2X_MSG_ETHTOOL, "Get dump preset %d length=%d\n",
1026 bp->dump_preset_idx, dump->len);
1027 return 0;
1028 }
1029
1030 static int bnx2x_get_dump_data(struct net_device *dev,
1031 struct ethtool_dump *dump,
1032 void *buffer)
1033 {
1034 u32 *p = buffer;
1035 struct bnx2x *bp = netdev_priv(dev);
1036 struct dump_header dump_hdr = {0};
1037
1038 /* Disable parity attentions as long as following dump may
1039 * cause false alarms by reading never written registers. We
1040 * will re-enable parity attentions right after the dump.
1041 */
1042
1043 bnx2x_disable_blocks_parity(bp);
1044
1045 dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
1046 dump_hdr.preset = bp->dump_preset_idx;
1047 dump_hdr.version = BNX2X_DUMP_VERSION;
1048
1049 DP(BNX2X_MSG_ETHTOOL, "Get dump data of preset %d\n", dump_hdr.preset);
1050
1051 /* dump_meta_data presents OR of CHIP and PATH. */
1052 if (CHIP_IS_E1(bp)) {
1053 dump_hdr.dump_meta_data = DUMP_CHIP_E1;
1054 } else if (CHIP_IS_E1H(bp)) {
1055 dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
1056 } else if (CHIP_IS_E2(bp)) {
1057 dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
1058 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1059 } else if (CHIP_IS_E3A0(bp)) {
1060 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
1061 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1062 } else if (CHIP_IS_E3B0(bp)) {
1063 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
1064 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1065 }
1066
1067 memcpy(p, &dump_hdr, sizeof(struct dump_header));
1068 p += dump_hdr.header_size + 1;
1069
1070 /* Actually read the registers */
1071 __bnx2x_get_preset_regs(bp, p, dump_hdr.preset);
1072
1073 /* Re-enable parity attentions */
1074 bnx2x_clear_blocks_parity(bp);
1075 bnx2x_enable_blocks_parity(bp);
1076
1077 return 0;
1078 }
1079
1080 static void bnx2x_get_drvinfo(struct net_device *dev,
1081 struct ethtool_drvinfo *info)
1082 {
1083 struct bnx2x *bp = netdev_priv(dev);
1084
1085 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1086 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
1087
1088 bnx2x_fill_fw_str(bp, info->fw_version, sizeof(info->fw_version));
1089
1090 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
1091 info->n_stats = BNX2X_NUM_STATS;
1092 info->testinfo_len = BNX2X_NUM_TESTS(bp);
1093 info->eedump_len = bp->common.flash_size;
1094 info->regdump_len = bnx2x_get_regs_len(dev);
1095 }
1096
1097 static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1098 {
1099 struct bnx2x *bp = netdev_priv(dev);
1100
1101 if (bp->flags & NO_WOL_FLAG) {
1102 wol->supported = 0;
1103 wol->wolopts = 0;
1104 } else {
1105 wol->supported = WAKE_MAGIC;
1106 if (bp->wol)
1107 wol->wolopts = WAKE_MAGIC;
1108 else
1109 wol->wolopts = 0;
1110 }
1111 memset(&wol->sopass, 0, sizeof(wol->sopass));
1112 }
1113
1114 static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1115 {
1116 struct bnx2x *bp = netdev_priv(dev);
1117
1118 if (wol->wolopts & ~WAKE_MAGIC) {
1119 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
1120 return -EINVAL;
1121 }
1122
1123 if (wol->wolopts & WAKE_MAGIC) {
1124 if (bp->flags & NO_WOL_FLAG) {
1125 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
1126 return -EINVAL;
1127 }
1128 bp->wol = 1;
1129 } else
1130 bp->wol = 0;
1131
1132 return 0;
1133 }
1134
1135 static u32 bnx2x_get_msglevel(struct net_device *dev)
1136 {
1137 struct bnx2x *bp = netdev_priv(dev);
1138
1139 return bp->msg_enable;
1140 }
1141
1142 static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
1143 {
1144 struct bnx2x *bp = netdev_priv(dev);
1145
1146 if (capable(CAP_NET_ADMIN)) {
1147 /* dump MCP trace */
1148 if (IS_PF(bp) && (level & BNX2X_MSG_MCP))
1149 bnx2x_fw_dump_lvl(bp, KERN_INFO);
1150 bp->msg_enable = level;
1151 }
1152 }
1153
1154 static int bnx2x_nway_reset(struct net_device *dev)
1155 {
1156 struct bnx2x *bp = netdev_priv(dev);
1157
1158 if (!bp->port.pmf)
1159 return 0;
1160
1161 if (netif_running(dev)) {
1162 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1163 bnx2x_force_link_reset(bp);
1164 bnx2x_link_set(bp);
1165 }
1166
1167 return 0;
1168 }
1169
1170 static u32 bnx2x_get_link(struct net_device *dev)
1171 {
1172 struct bnx2x *bp = netdev_priv(dev);
1173
1174 if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
1175 return 0;
1176
1177 if (IS_VF(bp))
1178 return !test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1179 &bp->vf_link_vars.link_report_flags);
1180
1181 return bp->link_vars.link_up;
1182 }
1183
1184 static int bnx2x_get_eeprom_len(struct net_device *dev)
1185 {
1186 struct bnx2x *bp = netdev_priv(dev);
1187
1188 return bp->common.flash_size;
1189 }
1190
1191 /* Per pf misc lock must be acquired before the per port mcp lock. Otherwise,
1192 * had we done things the other way around, if two pfs from the same port would
1193 * attempt to access nvram at the same time, we could run into a scenario such
1194 * as:
1195 * pf A takes the port lock.
1196 * pf B succeeds in taking the same lock since they are from the same port.
1197 * pf A takes the per pf misc lock. Performs eeprom access.
1198 * pf A finishes. Unlocks the per pf misc lock.
1199 * Pf B takes the lock and proceeds to perform it's own access.
1200 * pf A unlocks the per port lock, while pf B is still working (!).
1201 * mcp takes the per port lock and corrupts pf B's access (and/or has it's own
1202 * access corrupted by pf B)
1203 */
1204 static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
1205 {
1206 int port = BP_PORT(bp);
1207 int count, i;
1208 u32 val;
1209
1210 /* acquire HW lock: protect against other PFs in PF Direct Assignment */
1211 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1212
1213 /* adjust timeout for emulation/FPGA */
1214 count = BNX2X_NVRAM_TIMEOUT_COUNT;
1215 if (CHIP_REV_IS_SLOW(bp))
1216 count *= 100;
1217
1218 /* request access to nvram interface */
1219 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1220 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
1221
1222 for (i = 0; i < count*10; i++) {
1223 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1224 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
1225 break;
1226
1227 udelay(5);
1228 }
1229
1230 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
1231 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1232 "cannot get access to nvram interface\n");
1233 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1234 return -EBUSY;
1235 }
1236
1237 return 0;
1238 }
1239
1240 static int bnx2x_release_nvram_lock(struct bnx2x *bp)
1241 {
1242 int port = BP_PORT(bp);
1243 int count, i;
1244 u32 val;
1245
1246 /* adjust timeout for emulation/FPGA */
1247 count = BNX2X_NVRAM_TIMEOUT_COUNT;
1248 if (CHIP_REV_IS_SLOW(bp))
1249 count *= 100;
1250
1251 /* relinquish nvram interface */
1252 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1253 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
1254
1255 for (i = 0; i < count*10; i++) {
1256 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1257 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
1258 break;
1259
1260 udelay(5);
1261 }
1262
1263 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
1264 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1265 "cannot free access to nvram interface\n");
1266 return -EBUSY;
1267 }
1268
1269 /* release HW lock: protect against other PFs in PF Direct Assignment */
1270 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1271 return 0;
1272 }
1273
1274 static void bnx2x_enable_nvram_access(struct bnx2x *bp)
1275 {
1276 u32 val;
1277
1278 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1279
1280 /* enable both bits, even on read */
1281 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1282 (val | MCPR_NVM_ACCESS_ENABLE_EN |
1283 MCPR_NVM_ACCESS_ENABLE_WR_EN));
1284 }
1285
1286 static void bnx2x_disable_nvram_access(struct bnx2x *bp)
1287 {
1288 u32 val;
1289
1290 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1291
1292 /* disable both bits, even after read */
1293 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1294 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
1295 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
1296 }
1297
1298 static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
1299 u32 cmd_flags)
1300 {
1301 int count, i, rc;
1302 u32 val;
1303
1304 /* build the command word */
1305 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
1306
1307 /* need to clear DONE bit separately */
1308 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1309
1310 /* address of the NVRAM to read from */
1311 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1312 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1313
1314 /* issue a read command */
1315 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1316
1317 /* adjust timeout for emulation/FPGA */
1318 count = BNX2X_NVRAM_TIMEOUT_COUNT;
1319 if (CHIP_REV_IS_SLOW(bp))
1320 count *= 100;
1321
1322 /* wait for completion */
1323 *ret_val = 0;
1324 rc = -EBUSY;
1325 for (i = 0; i < count; i++) {
1326 udelay(5);
1327 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1328
1329 if (val & MCPR_NVM_COMMAND_DONE) {
1330 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
1331 /* we read nvram data in cpu order
1332 * but ethtool sees it as an array of bytes
1333 * converting to big-endian will do the work
1334 */
1335 *ret_val = cpu_to_be32(val);
1336 rc = 0;
1337 break;
1338 }
1339 }
1340 if (rc == -EBUSY)
1341 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1342 "nvram read timeout expired\n");
1343 return rc;
1344 }
1345
1346 static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
1347 int buf_size)
1348 {
1349 int rc;
1350 u32 cmd_flags;
1351 __be32 val;
1352
1353 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1354 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1355 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1356 offset, buf_size);
1357 return -EINVAL;
1358 }
1359
1360 if (offset + buf_size > bp->common.flash_size) {
1361 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1362 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1363 offset, buf_size, bp->common.flash_size);
1364 return -EINVAL;
1365 }
1366
1367 /* request access to nvram interface */
1368 rc = bnx2x_acquire_nvram_lock(bp);
1369 if (rc)
1370 return rc;
1371
1372 /* enable access to nvram interface */
1373 bnx2x_enable_nvram_access(bp);
1374
1375 /* read the first word(s) */
1376 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1377 while ((buf_size > sizeof(u32)) && (rc == 0)) {
1378 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1379 memcpy(ret_buf, &val, 4);
1380
1381 /* advance to the next dword */
1382 offset += sizeof(u32);
1383 ret_buf += sizeof(u32);
1384 buf_size -= sizeof(u32);
1385 cmd_flags = 0;
1386 }
1387
1388 if (rc == 0) {
1389 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1390 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1391 memcpy(ret_buf, &val, 4);
1392 }
1393
1394 /* disable access to nvram interface */
1395 bnx2x_disable_nvram_access(bp);
1396 bnx2x_release_nvram_lock(bp);
1397
1398 return rc;
1399 }
1400
1401 static int bnx2x_nvram_read32(struct bnx2x *bp, u32 offset, u32 *buf,
1402 int buf_size)
1403 {
1404 int rc;
1405
1406 rc = bnx2x_nvram_read(bp, offset, (u8 *)buf, buf_size);
1407
1408 if (!rc) {
1409 __be32 *be = (__be32 *)buf;
1410
1411 while ((buf_size -= 4) >= 0)
1412 *buf++ = be32_to_cpu(*be++);
1413 }
1414
1415 return rc;
1416 }
1417
1418 static bool bnx2x_is_nvm_accessible(struct bnx2x *bp)
1419 {
1420 int rc = 1;
1421 u16 pm = 0;
1422 struct net_device *dev = pci_get_drvdata(bp->pdev);
1423
1424 if (bp->pdev->pm_cap)
1425 rc = pci_read_config_word(bp->pdev,
1426 bp->pdev->pm_cap + PCI_PM_CTRL, &pm);
1427
1428 if ((rc && !netif_running(dev)) ||
1429 (!rc && ((pm & PCI_PM_CTRL_STATE_MASK) != (__force u16)PCI_D0)))
1430 return false;
1431
1432 return true;
1433 }
1434
1435 static int bnx2x_get_eeprom(struct net_device *dev,
1436 struct ethtool_eeprom *eeprom, u8 *eebuf)
1437 {
1438 struct bnx2x *bp = netdev_priv(dev);
1439
1440 if (!bnx2x_is_nvm_accessible(bp)) {
1441 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1442 "cannot access eeprom when the interface is down\n");
1443 return -EAGAIN;
1444 }
1445
1446 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1447 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
1448 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1449 eeprom->len, eeprom->len);
1450
1451 /* parameters already validated in ethtool_get_eeprom */
1452
1453 return bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
1454 }
1455
1456 static int bnx2x_get_module_eeprom(struct net_device *dev,
1457 struct ethtool_eeprom *ee,
1458 u8 *data)
1459 {
1460 struct bnx2x *bp = netdev_priv(dev);
1461 int rc = -EINVAL, phy_idx;
1462 u8 *user_data = data;
1463 unsigned int start_addr = ee->offset, xfer_size = 0;
1464
1465 if (!bnx2x_is_nvm_accessible(bp)) {
1466 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1467 "cannot access eeprom when the interface is down\n");
1468 return -EAGAIN;
1469 }
1470
1471 phy_idx = bnx2x_get_cur_phy_idx(bp);
1472
1473 /* Read A0 section */
1474 if (start_addr < ETH_MODULE_SFF_8079_LEN) {
1475 /* Limit transfer size to the A0 section boundary */
1476 if (start_addr + ee->len > ETH_MODULE_SFF_8079_LEN)
1477 xfer_size = ETH_MODULE_SFF_8079_LEN - start_addr;
1478 else
1479 xfer_size = ee->len;
1480 bnx2x_acquire_phy_lock(bp);
1481 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1482 &bp->link_params,
1483 I2C_DEV_ADDR_A0,
1484 start_addr,
1485 xfer_size,
1486 user_data);
1487 bnx2x_release_phy_lock(bp);
1488 if (rc) {
1489 DP(BNX2X_MSG_ETHTOOL, "Failed reading A0 section\n");
1490
1491 return -EINVAL;
1492 }
1493 user_data += xfer_size;
1494 start_addr += xfer_size;
1495 }
1496
1497 /* Read A2 section */
1498 if ((start_addr >= ETH_MODULE_SFF_8079_LEN) &&
1499 (start_addr < ETH_MODULE_SFF_8472_LEN)) {
1500 xfer_size = ee->len - xfer_size;
1501 /* Limit transfer size to the A2 section boundary */
1502 if (start_addr + xfer_size > ETH_MODULE_SFF_8472_LEN)
1503 xfer_size = ETH_MODULE_SFF_8472_LEN - start_addr;
1504 start_addr -= ETH_MODULE_SFF_8079_LEN;
1505 bnx2x_acquire_phy_lock(bp);
1506 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1507 &bp->link_params,
1508 I2C_DEV_ADDR_A2,
1509 start_addr,
1510 xfer_size,
1511 user_data);
1512 bnx2x_release_phy_lock(bp);
1513 if (rc) {
1514 DP(BNX2X_MSG_ETHTOOL, "Failed reading A2 section\n");
1515 return -EINVAL;
1516 }
1517 }
1518 return rc;
1519 }
1520
1521 static int bnx2x_get_module_info(struct net_device *dev,
1522 struct ethtool_modinfo *modinfo)
1523 {
1524 struct bnx2x *bp = netdev_priv(dev);
1525 int phy_idx, rc;
1526 u8 sff8472_comp, diag_type;
1527
1528 if (!bnx2x_is_nvm_accessible(bp)) {
1529 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1530 "cannot access eeprom when the interface is down\n");
1531 return -EAGAIN;
1532 }
1533 phy_idx = bnx2x_get_cur_phy_idx(bp);
1534 bnx2x_acquire_phy_lock(bp);
1535 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1536 &bp->link_params,
1537 I2C_DEV_ADDR_A0,
1538 SFP_EEPROM_SFF_8472_COMP_ADDR,
1539 SFP_EEPROM_SFF_8472_COMP_SIZE,
1540 &sff8472_comp);
1541 bnx2x_release_phy_lock(bp);
1542 if (rc) {
1543 DP(BNX2X_MSG_ETHTOOL, "Failed reading SFF-8472 comp field\n");
1544 return -EINVAL;
1545 }
1546
1547 bnx2x_acquire_phy_lock(bp);
1548 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1549 &bp->link_params,
1550 I2C_DEV_ADDR_A0,
1551 SFP_EEPROM_DIAG_TYPE_ADDR,
1552 SFP_EEPROM_DIAG_TYPE_SIZE,
1553 &diag_type);
1554 bnx2x_release_phy_lock(bp);
1555 if (rc) {
1556 DP(BNX2X_MSG_ETHTOOL, "Failed reading Diag Type field\n");
1557 return -EINVAL;
1558 }
1559
1560 if (!sff8472_comp ||
1561 (diag_type & SFP_EEPROM_DIAG_ADDR_CHANGE_REQ)) {
1562 modinfo->type = ETH_MODULE_SFF_8079;
1563 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
1564 } else {
1565 modinfo->type = ETH_MODULE_SFF_8472;
1566 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1567 }
1568 return 0;
1569 }
1570
1571 static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
1572 u32 cmd_flags)
1573 {
1574 int count, i, rc;
1575
1576 /* build the command word */
1577 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
1578
1579 /* need to clear DONE bit separately */
1580 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1581
1582 /* write the data */
1583 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
1584
1585 /* address of the NVRAM to write to */
1586 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1587 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1588
1589 /* issue the write command */
1590 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1591
1592 /* adjust timeout for emulation/FPGA */
1593 count = BNX2X_NVRAM_TIMEOUT_COUNT;
1594 if (CHIP_REV_IS_SLOW(bp))
1595 count *= 100;
1596
1597 /* wait for completion */
1598 rc = -EBUSY;
1599 for (i = 0; i < count; i++) {
1600 udelay(5);
1601 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1602 if (val & MCPR_NVM_COMMAND_DONE) {
1603 rc = 0;
1604 break;
1605 }
1606 }
1607
1608 if (rc == -EBUSY)
1609 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1610 "nvram write timeout expired\n");
1611 return rc;
1612 }
1613
1614 #define BYTE_OFFSET(offset) (8 * (offset & 0x03))
1615
1616 static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
1617 int buf_size)
1618 {
1619 int rc;
1620 u32 cmd_flags, align_offset, val;
1621 __be32 val_be;
1622
1623 if (offset + buf_size > bp->common.flash_size) {
1624 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1625 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1626 offset, buf_size, bp->common.flash_size);
1627 return -EINVAL;
1628 }
1629
1630 /* request access to nvram interface */
1631 rc = bnx2x_acquire_nvram_lock(bp);
1632 if (rc)
1633 return rc;
1634
1635 /* enable access to nvram interface */
1636 bnx2x_enable_nvram_access(bp);
1637
1638 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1639 align_offset = (offset & ~0x03);
1640 rc = bnx2x_nvram_read_dword(bp, align_offset, &val_be, cmd_flags);
1641
1642 if (rc == 0) {
1643 /* nvram data is returned as an array of bytes
1644 * convert it back to cpu order
1645 */
1646 val = be32_to_cpu(val_be);
1647
1648 val &= ~le32_to_cpu((__force __le32)
1649 (0xff << BYTE_OFFSET(offset)));
1650 val |= le32_to_cpu((__force __le32)
1651 (*data_buf << BYTE_OFFSET(offset)));
1652
1653 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1654 cmd_flags);
1655 }
1656
1657 /* disable access to nvram interface */
1658 bnx2x_disable_nvram_access(bp);
1659 bnx2x_release_nvram_lock(bp);
1660
1661 return rc;
1662 }
1663
1664 static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1665 int buf_size)
1666 {
1667 int rc;
1668 u32 cmd_flags;
1669 u32 val;
1670 u32 written_so_far;
1671
1672 if (buf_size == 1) /* ethtool */
1673 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1674
1675 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1676 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1677 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1678 offset, buf_size);
1679 return -EINVAL;
1680 }
1681
1682 if (offset + buf_size > bp->common.flash_size) {
1683 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1684 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1685 offset, buf_size, bp->common.flash_size);
1686 return -EINVAL;
1687 }
1688
1689 /* request access to nvram interface */
1690 rc = bnx2x_acquire_nvram_lock(bp);
1691 if (rc)
1692 return rc;
1693
1694 /* enable access to nvram interface */
1695 bnx2x_enable_nvram_access(bp);
1696
1697 written_so_far = 0;
1698 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1699 while ((written_so_far < buf_size) && (rc == 0)) {
1700 if (written_so_far == (buf_size - sizeof(u32)))
1701 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1702 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
1703 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1704 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
1705 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1706
1707 memcpy(&val, data_buf, 4);
1708
1709 /* Notice unlike bnx2x_nvram_read_dword() this will not
1710 * change val using be32_to_cpu(), which causes data to flip
1711 * if the eeprom is read and then written back. This is due
1712 * to tools utilizing this functionality that would break
1713 * if this would be resolved.
1714 */
1715 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1716
1717 /* advance to the next dword */
1718 offset += sizeof(u32);
1719 data_buf += sizeof(u32);
1720 written_so_far += sizeof(u32);
1721
1722 /* At end of each 4Kb page, release nvram lock to allow MFW
1723 * chance to take it for its own use.
1724 */
1725 if ((cmd_flags & MCPR_NVM_COMMAND_LAST) &&
1726 (written_so_far < buf_size)) {
1727 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1728 "Releasing NVM lock after offset 0x%x\n",
1729 (u32)(offset - sizeof(u32)));
1730 bnx2x_release_nvram_lock(bp);
1731 usleep_range(1000, 2000);
1732 rc = bnx2x_acquire_nvram_lock(bp);
1733 if (rc)
1734 return rc;
1735 }
1736
1737 cmd_flags = 0;
1738 }
1739
1740 /* disable access to nvram interface */
1741 bnx2x_disable_nvram_access(bp);
1742 bnx2x_release_nvram_lock(bp);
1743
1744 return rc;
1745 }
1746
1747 static int bnx2x_set_eeprom(struct net_device *dev,
1748 struct ethtool_eeprom *eeprom, u8 *eebuf)
1749 {
1750 struct bnx2x *bp = netdev_priv(dev);
1751 int port = BP_PORT(bp);
1752 int rc = 0;
1753 u32 ext_phy_config;
1754
1755 if (!bnx2x_is_nvm_accessible(bp)) {
1756 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1757 "cannot access eeprom when the interface is down\n");
1758 return -EAGAIN;
1759 }
1760
1761 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1762 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
1763 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1764 eeprom->len, eeprom->len);
1765
1766 /* parameters already validated in ethtool_set_eeprom */
1767
1768 /* PHY eeprom can be accessed only by the PMF */
1769 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
1770 !bp->port.pmf) {
1771 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1772 "wrong magic or interface is not pmf\n");
1773 return -EINVAL;
1774 }
1775
1776 ext_phy_config =
1777 SHMEM_RD(bp,
1778 dev_info.port_hw_config[port].external_phy_config);
1779
1780 if (eeprom->magic == 0x50485950) {
1781 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1782 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1783
1784 bnx2x_acquire_phy_lock(bp);
1785 rc |= bnx2x_link_reset(&bp->link_params,
1786 &bp->link_vars, 0);
1787 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1788 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1789 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1790 MISC_REGISTERS_GPIO_HIGH, port);
1791 bnx2x_release_phy_lock(bp);
1792 bnx2x_link_report(bp);
1793
1794 } else if (eeprom->magic == 0x50485952) {
1795 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1796 if (bp->state == BNX2X_STATE_OPEN) {
1797 bnx2x_acquire_phy_lock(bp);
1798 rc |= bnx2x_link_reset(&bp->link_params,
1799 &bp->link_vars, 1);
1800
1801 rc |= bnx2x_phy_init(&bp->link_params,
1802 &bp->link_vars);
1803 bnx2x_release_phy_lock(bp);
1804 bnx2x_calc_fc_adv(bp);
1805 }
1806 } else if (eeprom->magic == 0x53985943) {
1807 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
1808 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1809 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
1810
1811 /* DSP Remove Download Mode */
1812 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1813 MISC_REGISTERS_GPIO_LOW, port);
1814
1815 bnx2x_acquire_phy_lock(bp);
1816
1817 bnx2x_sfx7101_sp_sw_reset(bp,
1818 &bp->link_params.phy[EXT_PHY1]);
1819
1820 /* wait 0.5 sec to allow it to run */
1821 msleep(500);
1822 bnx2x_ext_phy_hw_reset(bp, port);
1823 msleep(500);
1824 bnx2x_release_phy_lock(bp);
1825 }
1826 } else
1827 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1828
1829 return rc;
1830 }
1831
1832 static int bnx2x_get_coalesce(struct net_device *dev,
1833 struct ethtool_coalesce *coal)
1834 {
1835 struct bnx2x *bp = netdev_priv(dev);
1836
1837 memset(coal, 0, sizeof(struct ethtool_coalesce));
1838
1839 coal->rx_coalesce_usecs = bp->rx_ticks;
1840 coal->tx_coalesce_usecs = bp->tx_ticks;
1841
1842 return 0;
1843 }
1844
1845 static int bnx2x_set_coalesce(struct net_device *dev,
1846 struct ethtool_coalesce *coal)
1847 {
1848 struct bnx2x *bp = netdev_priv(dev);
1849
1850 bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1851 if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1852 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1853
1854 bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1855 if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1856 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1857
1858 if (netif_running(dev))
1859 bnx2x_update_coalesce(bp);
1860
1861 return 0;
1862 }
1863
1864 static void bnx2x_get_ringparam(struct net_device *dev,
1865 struct ethtool_ringparam *ering)
1866 {
1867 struct bnx2x *bp = netdev_priv(dev);
1868
1869 ering->rx_max_pending = MAX_RX_AVAIL;
1870
1871 if (bp->rx_ring_size)
1872 ering->rx_pending = bp->rx_ring_size;
1873 else
1874 ering->rx_pending = MAX_RX_AVAIL;
1875
1876 ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
1877 ering->tx_pending = bp->tx_ring_size;
1878 }
1879
1880 static int bnx2x_set_ringparam(struct net_device *dev,
1881 struct ethtool_ringparam *ering)
1882 {
1883 struct bnx2x *bp = netdev_priv(dev);
1884
1885 DP(BNX2X_MSG_ETHTOOL,
1886 "set ring params command parameters: rx_pending = %d, tx_pending = %d\n",
1887 ering->rx_pending, ering->tx_pending);
1888
1889 if (pci_num_vf(bp->pdev)) {
1890 DP(BNX2X_MSG_IOV,
1891 "VFs are enabled, can not change ring parameters\n");
1892 return -EPERM;
1893 }
1894
1895 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1896 DP(BNX2X_MSG_ETHTOOL,
1897 "Handling parity error recovery. Try again later\n");
1898 return -EAGAIN;
1899 }
1900
1901 if ((ering->rx_pending > MAX_RX_AVAIL) ||
1902 (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1903 MIN_RX_SIZE_TPA)) ||
1904 (ering->tx_pending > (IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL)) ||
1905 (ering->tx_pending <= MAX_SKB_FRAGS + 4)) {
1906 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
1907 return -EINVAL;
1908 }
1909
1910 bp->rx_ring_size = ering->rx_pending;
1911 bp->tx_ring_size = ering->tx_pending;
1912
1913 return bnx2x_reload_if_running(dev);
1914 }
1915
1916 static void bnx2x_get_pauseparam(struct net_device *dev,
1917 struct ethtool_pauseparam *epause)
1918 {
1919 struct bnx2x *bp = netdev_priv(dev);
1920 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1921 int cfg_reg;
1922
1923 epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1924 BNX2X_FLOW_CTRL_AUTO);
1925
1926 if (!epause->autoneg)
1927 cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx];
1928 else
1929 cfg_reg = bp->link_params.req_fc_auto_adv;
1930
1931 epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) ==
1932 BNX2X_FLOW_CTRL_RX);
1933 epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) ==
1934 BNX2X_FLOW_CTRL_TX);
1935
1936 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
1937 " autoneg %d rx_pause %d tx_pause %d\n",
1938 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1939 }
1940
1941 static int bnx2x_set_pauseparam(struct net_device *dev,
1942 struct ethtool_pauseparam *epause)
1943 {
1944 struct bnx2x *bp = netdev_priv(dev);
1945 u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
1946 if (IS_MF(bp))
1947 return 0;
1948
1949 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
1950 " autoneg %d rx_pause %d tx_pause %d\n",
1951 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1952
1953 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
1954
1955 if (epause->rx_pause)
1956 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
1957
1958 if (epause->tx_pause)
1959 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
1960
1961 if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1962 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
1963
1964 if (epause->autoneg) {
1965 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
1966 DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n");
1967 return -EINVAL;
1968 }
1969
1970 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1971 bp->link_params.req_flow_ctrl[cfg_idx] =
1972 BNX2X_FLOW_CTRL_AUTO;
1973 }
1974 bp->link_params.req_fc_auto_adv = 0;
1975 if (epause->rx_pause)
1976 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX;
1977
1978 if (epause->tx_pause)
1979 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX;
1980
1981 if (!bp->link_params.req_fc_auto_adv)
1982 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_NONE;
1983 }
1984
1985 DP(BNX2X_MSG_ETHTOOL,
1986 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
1987
1988 if (netif_running(dev)) {
1989 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1990 bnx2x_force_link_reset(bp);
1991 bnx2x_link_set(bp);
1992 }
1993
1994 return 0;
1995 }
1996
1997 static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = {
1998 "register_test (offline) ",
1999 "memory_test (offline) ",
2000 "int_loopback_test (offline)",
2001 "ext_loopback_test (offline)",
2002 "nvram_test (online) ",
2003 "interrupt_test (online) ",
2004 "link_test (online) "
2005 };
2006
2007 enum {
2008 BNX2X_PRI_FLAG_ISCSI,
2009 BNX2X_PRI_FLAG_FCOE,
2010 BNX2X_PRI_FLAG_STORAGE,
2011 BNX2X_PRI_FLAG_LEN,
2012 };
2013
2014 static const char bnx2x_private_arr[BNX2X_PRI_FLAG_LEN][ETH_GSTRING_LEN] = {
2015 "iSCSI offload support",
2016 "FCoE offload support",
2017 "Storage only interface"
2018 };
2019
2020 static u32 bnx2x_eee_to_adv(u32 eee_adv)
2021 {
2022 u32 modes = 0;
2023
2024 if (eee_adv & SHMEM_EEE_100M_ADV)
2025 modes |= ADVERTISED_100baseT_Full;
2026 if (eee_adv & SHMEM_EEE_1G_ADV)
2027 modes |= ADVERTISED_1000baseT_Full;
2028 if (eee_adv & SHMEM_EEE_10G_ADV)
2029 modes |= ADVERTISED_10000baseT_Full;
2030
2031 return modes;
2032 }
2033
2034 static u32 bnx2x_adv_to_eee(u32 modes, u32 shift)
2035 {
2036 u32 eee_adv = 0;
2037 if (modes & ADVERTISED_100baseT_Full)
2038 eee_adv |= SHMEM_EEE_100M_ADV;
2039 if (modes & ADVERTISED_1000baseT_Full)
2040 eee_adv |= SHMEM_EEE_1G_ADV;
2041 if (modes & ADVERTISED_10000baseT_Full)
2042 eee_adv |= SHMEM_EEE_10G_ADV;
2043
2044 return eee_adv << shift;
2045 }
2046
2047 static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata)
2048 {
2049 struct bnx2x *bp = netdev_priv(dev);
2050 u32 eee_cfg;
2051
2052 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
2053 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
2054 return -EOPNOTSUPP;
2055 }
2056
2057 eee_cfg = bp->link_vars.eee_status;
2058
2059 edata->supported =
2060 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >>
2061 SHMEM_EEE_SUPPORTED_SHIFT);
2062
2063 edata->advertised =
2064 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >>
2065 SHMEM_EEE_ADV_STATUS_SHIFT);
2066 edata->lp_advertised =
2067 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >>
2068 SHMEM_EEE_LP_ADV_STATUS_SHIFT);
2069
2070 /* SHMEM value is in 16u units --> Convert to 1u units. */
2071 edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4;
2072
2073 edata->eee_enabled = (eee_cfg & SHMEM_EEE_REQUESTED_BIT) ? 1 : 0;
2074 edata->eee_active = (eee_cfg & SHMEM_EEE_ACTIVE_BIT) ? 1 : 0;
2075 edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0;
2076
2077 return 0;
2078 }
2079
2080 static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata)
2081 {
2082 struct bnx2x *bp = netdev_priv(dev);
2083 u32 eee_cfg;
2084 u32 advertised;
2085
2086 if (IS_MF(bp))
2087 return 0;
2088
2089 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
2090 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
2091 return -EOPNOTSUPP;
2092 }
2093
2094 eee_cfg = bp->link_vars.eee_status;
2095
2096 if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) {
2097 DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n");
2098 return -EOPNOTSUPP;
2099 }
2100
2101 advertised = bnx2x_adv_to_eee(edata->advertised,
2102 SHMEM_EEE_ADV_STATUS_SHIFT);
2103 if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) {
2104 DP(BNX2X_MSG_ETHTOOL,
2105 "Direct manipulation of EEE advertisement is not supported\n");
2106 return -EINVAL;
2107 }
2108
2109 if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) {
2110 DP(BNX2X_MSG_ETHTOOL,
2111 "Maximal Tx Lpi timer supported is %x(u)\n",
2112 EEE_MODE_TIMER_MASK);
2113 return -EINVAL;
2114 }
2115 if (edata->tx_lpi_enabled &&
2116 (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) {
2117 DP(BNX2X_MSG_ETHTOOL,
2118 "Minimal Tx Lpi timer supported is %d(u)\n",
2119 EEE_MODE_NVRAM_AGGRESSIVE_TIME);
2120 return -EINVAL;
2121 }
2122
2123 /* All is well; Apply changes*/
2124 if (edata->eee_enabled)
2125 bp->link_params.eee_mode |= EEE_MODE_ADV_LPI;
2126 else
2127 bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI;
2128
2129 if (edata->tx_lpi_enabled)
2130 bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI;
2131 else
2132 bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI;
2133
2134 bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK;
2135 bp->link_params.eee_mode |= (edata->tx_lpi_timer &
2136 EEE_MODE_TIMER_MASK) |
2137 EEE_MODE_OVERRIDE_NVRAM |
2138 EEE_MODE_OUTPUT_TIME;
2139
2140 /* Restart link to propagate changes */
2141 if (netif_running(dev)) {
2142 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2143 bnx2x_force_link_reset(bp);
2144 bnx2x_link_set(bp);
2145 }
2146
2147 return 0;
2148 }
2149
2150 enum {
2151 BNX2X_CHIP_E1_OFST = 0,
2152 BNX2X_CHIP_E1H_OFST,
2153 BNX2X_CHIP_E2_OFST,
2154 BNX2X_CHIP_E3_OFST,
2155 BNX2X_CHIP_E3B0_OFST,
2156 BNX2X_CHIP_MAX_OFST
2157 };
2158
2159 #define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST)
2160 #define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST)
2161 #define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST)
2162 #define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST)
2163 #define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST)
2164
2165 #define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1)
2166 #define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
2167
2168 static int bnx2x_test_registers(struct bnx2x *bp)
2169 {
2170 int idx, i, rc = -ENODEV;
2171 u32 wr_val = 0, hw;
2172 int port = BP_PORT(bp);
2173 static const struct {
2174 u32 hw;
2175 u32 offset0;
2176 u32 offset1;
2177 u32 mask;
2178 } reg_tbl[] = {
2179 /* 0 */ { BNX2X_CHIP_MASK_ALL,
2180 BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
2181 { BNX2X_CHIP_MASK_ALL,
2182 DORQ_REG_DB_ADDR0, 4, 0xffffffff },
2183 { BNX2X_CHIP_MASK_E1X,
2184 HC_REG_AGG_INT_0, 4, 0x000003ff },
2185 { BNX2X_CHIP_MASK_ALL,
2186 PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 },
2187 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
2188 PBF_REG_P0_INIT_CRD, 4, 0x000007ff },
2189 { BNX2X_CHIP_MASK_E3B0,
2190 PBF_REG_INIT_CRD_Q0, 4, 0x000007ff },
2191 { BNX2X_CHIP_MASK_ALL,
2192 PRS_REG_CID_PORT_0, 4, 0x00ffffff },
2193 { BNX2X_CHIP_MASK_ALL,
2194 PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff },
2195 { BNX2X_CHIP_MASK_ALL,
2196 PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2197 { BNX2X_CHIP_MASK_ALL,
2198 PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff },
2199 /* 10 */ { BNX2X_CHIP_MASK_ALL,
2200 PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2201 { BNX2X_CHIP_MASK_ALL,
2202 PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff },
2203 { BNX2X_CHIP_MASK_ALL,
2204 QM_REG_CONNNUM_0, 4, 0x000fffff },
2205 { BNX2X_CHIP_MASK_ALL,
2206 TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff },
2207 { BNX2X_CHIP_MASK_ALL,
2208 SRC_REG_KEYRSS0_0, 40, 0xffffffff },
2209 { BNX2X_CHIP_MASK_ALL,
2210 SRC_REG_KEYRSS0_7, 40, 0xffffffff },
2211 { BNX2X_CHIP_MASK_ALL,
2212 XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
2213 { BNX2X_CHIP_MASK_ALL,
2214 XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 },
2215 { BNX2X_CHIP_MASK_ALL,
2216 XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff },
2217 { BNX2X_CHIP_MASK_ALL,
2218 NIG_REG_LLH0_T_BIT, 4, 0x00000001 },
2219 /* 20 */ { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2220 NIG_REG_EMAC0_IN_EN, 4, 0x00000001 },
2221 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2222 NIG_REG_BMAC0_IN_EN, 4, 0x00000001 },
2223 { BNX2X_CHIP_MASK_ALL,
2224 NIG_REG_XCM0_OUT_EN, 4, 0x00000001 },
2225 { BNX2X_CHIP_MASK_ALL,
2226 NIG_REG_BRB0_OUT_EN, 4, 0x00000001 },
2227 { BNX2X_CHIP_MASK_ALL,
2228 NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 },
2229 { BNX2X_CHIP_MASK_ALL,
2230 NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff },
2231 { BNX2X_CHIP_MASK_ALL,
2232 NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff },
2233 { BNX2X_CHIP_MASK_ALL,
2234 NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff },
2235 { BNX2X_CHIP_MASK_ALL,
2236 NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff },
2237 { BNX2X_CHIP_MASK_ALL,
2238 NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 },
2239 /* 30 */ { BNX2X_CHIP_MASK_ALL,
2240 NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff },
2241 { BNX2X_CHIP_MASK_ALL,
2242 NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff },
2243 { BNX2X_CHIP_MASK_ALL,
2244 NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
2245 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2246 NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 },
2247 { BNX2X_CHIP_MASK_ALL,
2248 NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
2249 { BNX2X_CHIP_MASK_ALL,
2250 NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
2251 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2252 NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
2253 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2254 NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f },
2255
2256 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
2257 };
2258
2259 if (!bnx2x_is_nvm_accessible(bp)) {
2260 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2261 "cannot access eeprom when the interface is down\n");
2262 return rc;
2263 }
2264
2265 if (CHIP_IS_E1(bp))
2266 hw = BNX2X_CHIP_MASK_E1;
2267 else if (CHIP_IS_E1H(bp))
2268 hw = BNX2X_CHIP_MASK_E1H;
2269 else if (CHIP_IS_E2(bp))
2270 hw = BNX2X_CHIP_MASK_E2;
2271 else if (CHIP_IS_E3B0(bp))
2272 hw = BNX2X_CHIP_MASK_E3B0;
2273 else /* e3 A0 */
2274 hw = BNX2X_CHIP_MASK_E3;
2275
2276 /* Repeat the test twice:
2277 * First by writing 0x00000000, second by writing 0xffffffff
2278 */
2279 for (idx = 0; idx < 2; idx++) {
2280
2281 switch (idx) {
2282 case 0:
2283 wr_val = 0;
2284 break;
2285 case 1:
2286 wr_val = 0xffffffff;
2287 break;
2288 }
2289
2290 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
2291 u32 offset, mask, save_val, val;
2292 if (!(hw & reg_tbl[i].hw))
2293 continue;
2294
2295 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
2296 mask = reg_tbl[i].mask;
2297
2298 save_val = REG_RD(bp, offset);
2299
2300 REG_WR(bp, offset, wr_val & mask);
2301
2302 val = REG_RD(bp, offset);
2303
2304 /* Restore the original register's value */
2305 REG_WR(bp, offset, save_val);
2306
2307 /* verify value is as expected */
2308 if ((val & mask) != (wr_val & mask)) {
2309 DP(BNX2X_MSG_ETHTOOL,
2310 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
2311 offset, val, wr_val, mask);
2312 goto test_reg_exit;
2313 }
2314 }
2315 }
2316
2317 rc = 0;
2318
2319 test_reg_exit:
2320 return rc;
2321 }
2322
2323 static int bnx2x_test_memory(struct bnx2x *bp)
2324 {
2325 int i, j, rc = -ENODEV;
2326 u32 val, index;
2327 static const struct {
2328 u32 offset;
2329 int size;
2330 } mem_tbl[] = {
2331 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE },
2332 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
2333 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE },
2334 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE },
2335 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE },
2336 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE },
2337 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE },
2338
2339 { 0xffffffff, 0 }
2340 };
2341
2342 static const struct {
2343 char *name;
2344 u32 offset;
2345 u32 hw_mask[BNX2X_CHIP_MAX_OFST];
2346 } prty_tbl[] = {
2347 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS,
2348 {0x3ffc0, 0, 0, 0} },
2349 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS,
2350 {0x2, 0x2, 0, 0} },
2351 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
2352 {0, 0, 0, 0} },
2353 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS,
2354 {0x3ffc0, 0, 0, 0} },
2355 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS,
2356 {0x3ffc0, 0, 0, 0} },
2357 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS,
2358 {0x3ffc1, 0, 0, 0} },
2359
2360 { NULL, 0xffffffff, {0, 0, 0, 0} }
2361 };
2362
2363 if (!bnx2x_is_nvm_accessible(bp)) {
2364 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2365 "cannot access eeprom when the interface is down\n");
2366 return rc;
2367 }
2368
2369 if (CHIP_IS_E1(bp))
2370 index = BNX2X_CHIP_E1_OFST;
2371 else if (CHIP_IS_E1H(bp))
2372 index = BNX2X_CHIP_E1H_OFST;
2373 else if (CHIP_IS_E2(bp))
2374 index = BNX2X_CHIP_E2_OFST;
2375 else /* e3 */
2376 index = BNX2X_CHIP_E3_OFST;
2377
2378 /* pre-Check the parity status */
2379 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2380 val = REG_RD(bp, prty_tbl[i].offset);
2381 if (val & ~(prty_tbl[i].hw_mask[index])) {
2382 DP(BNX2X_MSG_ETHTOOL,
2383 "%s is 0x%x\n", prty_tbl[i].name, val);
2384 goto test_mem_exit;
2385 }
2386 }
2387
2388 /* Go through all the memories */
2389 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
2390 for (j = 0; j < mem_tbl[i].size; j++)
2391 REG_RD(bp, mem_tbl[i].offset + j*4);
2392
2393 /* Check the parity status */
2394 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2395 val = REG_RD(bp, prty_tbl[i].offset);
2396 if (val & ~(prty_tbl[i].hw_mask[index])) {
2397 DP(BNX2X_MSG_ETHTOOL,
2398 "%s is 0x%x\n", prty_tbl[i].name, val);
2399 goto test_mem_exit;
2400 }
2401 }
2402
2403 rc = 0;
2404
2405 test_mem_exit:
2406 return rc;
2407 }
2408
2409 static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
2410 {
2411 int cnt = 1400;
2412
2413 if (link_up) {
2414 while (bnx2x_link_test(bp, is_serdes) && cnt--)
2415 msleep(20);
2416
2417 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
2418 DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n");
2419
2420 cnt = 1400;
2421 while (!bp->link_vars.link_up && cnt--)
2422 msleep(20);
2423
2424 if (cnt <= 0 && !bp->link_vars.link_up)
2425 DP(BNX2X_MSG_ETHTOOL,
2426 "Timeout waiting for link init\n");
2427 }
2428 }
2429
2430 static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
2431 {
2432 unsigned int pkt_size, num_pkts, i;
2433 struct sk_buff *skb;
2434 unsigned char *packet;
2435 struct bnx2x_fastpath *fp_rx = &bp->fp[0];
2436 struct bnx2x_fastpath *fp_tx = &bp->fp[0];
2437 struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0];
2438 u16 tx_start_idx, tx_idx;
2439 u16 rx_start_idx, rx_idx;
2440 u16 pkt_prod, bd_prod;
2441 struct sw_tx_bd *tx_buf;
2442 struct eth_tx_start_bd *tx_start_bd;
2443 dma_addr_t mapping;
2444 union eth_rx_cqe *cqe;
2445 u8 cqe_fp_flags, cqe_fp_type;
2446 struct sw_rx_bd *rx_buf;
2447 u16 len;
2448 int rc = -ENODEV;
2449 u8 *data;
2450 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev,
2451 txdata->txq_index);
2452
2453 /* check the loopback mode */
2454 switch (loopback_mode) {
2455 case BNX2X_PHY_LOOPBACK:
2456 if (bp->link_params.loopback_mode != LOOPBACK_XGXS) {
2457 DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n");
2458 return -EINVAL;
2459 }
2460 break;
2461 case BNX2X_MAC_LOOPBACK:
2462 if (CHIP_IS_E3(bp)) {
2463 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
2464 if (bp->port.supported[cfg_idx] &
2465 (SUPPORTED_10000baseT_Full |
2466 SUPPORTED_20000baseMLD2_Full |
2467 SUPPORTED_20000baseKR2_Full))
2468 bp->link_params.loopback_mode = LOOPBACK_XMAC;
2469 else
2470 bp->link_params.loopback_mode = LOOPBACK_UMAC;
2471 } else
2472 bp->link_params.loopback_mode = LOOPBACK_BMAC;
2473
2474 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2475 break;
2476 case BNX2X_EXT_LOOPBACK:
2477 if (bp->link_params.loopback_mode != LOOPBACK_EXT) {
2478 DP(BNX2X_MSG_ETHTOOL,
2479 "Can't configure external loopback\n");
2480 return -EINVAL;
2481 }
2482 break;
2483 default:
2484 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
2485 return -EINVAL;
2486 }
2487
2488 /* prepare the loopback packet */
2489 pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
2490 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
2491 skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
2492 if (!skb) {
2493 DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n");
2494 rc = -ENOMEM;
2495 goto test_loopback_exit;
2496 }
2497 packet = skb_put(skb, pkt_size);
2498 memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
2499 eth_zero_addr(packet + ETH_ALEN);
2500 memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
2501 for (i = ETH_HLEN; i < pkt_size; i++)
2502 packet[i] = (unsigned char) (i & 0xff);
2503 mapping = dma_map_single(&bp->pdev->dev, skb->data,
2504 skb_headlen(skb), DMA_TO_DEVICE);
2505 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
2506 rc = -ENOMEM;
2507 dev_kfree_skb(skb);
2508 DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n");
2509 goto test_loopback_exit;
2510 }
2511
2512 /* send the loopback packet */
2513 num_pkts = 0;
2514 tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
2515 rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2516
2517 netdev_tx_sent_queue(txq, skb->len);
2518
2519 pkt_prod = txdata->tx_pkt_prod++;
2520 tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
2521 tx_buf->first_bd = txdata->tx_bd_prod;
2522 tx_buf->skb = skb;
2523 tx_buf->flags = 0;
2524
2525 bd_prod = TX_BD(txdata->tx_bd_prod);
2526 tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
2527 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
2528 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
2529 tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
2530 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
2531 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
2532 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2533 SET_FLAG(tx_start_bd->general_data,
2534 ETH_TX_START_BD_HDR_NBDS,
2535 1);
2536 SET_FLAG(tx_start_bd->general_data,
2537 ETH_TX_START_BD_PARSE_NBDS,
2538 0);
2539
2540 /* turn on parsing and get a BD */
2541 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
2542
2543 if (CHIP_IS_E1x(bp)) {
2544 u16 global_data = 0;
2545 struct eth_tx_parse_bd_e1x *pbd_e1x =
2546 &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
2547 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
2548 SET_FLAG(global_data,
2549 ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2550 pbd_e1x->global_data = cpu_to_le16(global_data);
2551 } else {
2552 u32 parsing_data = 0;
2553 struct eth_tx_parse_bd_e2 *pbd_e2 =
2554 &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
2555 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
2556 SET_FLAG(parsing_data,
2557 ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2558 pbd_e2->parsing_data = cpu_to_le32(parsing_data);
2559 }
2560 wmb();
2561
2562 txdata->tx_db.data.prod += 2;
2563 barrier();
2564 DOORBELL(bp, txdata->cid, txdata->tx_db.raw);
2565
2566 mmiowb();
2567 barrier();
2568
2569 num_pkts++;
2570 txdata->tx_bd_prod += 2; /* start + pbd */
2571
2572 udelay(100);
2573
2574 tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
2575 if (tx_idx != tx_start_idx + num_pkts)
2576 goto test_loopback_exit;
2577
2578 /* Unlike HC IGU won't generate an interrupt for status block
2579 * updates that have been performed while interrupts were
2580 * disabled.
2581 */
2582 if (bp->common.int_block == INT_BLOCK_IGU) {
2583 /* Disable local BHes to prevent a dead-lock situation between
2584 * sch_direct_xmit() and bnx2x_run_loopback() (calling
2585 * bnx2x_tx_int()), as both are taking netif_tx_lock().
2586 */
2587 local_bh_disable();
2588 bnx2x_tx_int(bp, txdata);
2589 local_bh_enable();
2590 }
2591
2592 rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2593 if (rx_idx != rx_start_idx + num_pkts)
2594 goto test_loopback_exit;
2595
2596 cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
2597 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
2598 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
2599 if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
2600 goto test_loopback_rx_exit;
2601
2602 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len);
2603 if (len != pkt_size)
2604 goto test_loopback_rx_exit;
2605
2606 rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
2607 dma_sync_single_for_cpu(&bp->pdev->dev,
2608 dma_unmap_addr(rx_buf, mapping),
2609 fp_rx->rx_buf_size, DMA_FROM_DEVICE);
2610 data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset;
2611 for (i = ETH_HLEN; i < pkt_size; i++)
2612 if (*(data + i) != (unsigned char) (i & 0xff))
2613 goto test_loopback_rx_exit;
2614
2615 rc = 0;
2616
2617 test_loopback_rx_exit:
2618
2619 fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
2620 fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
2621 fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
2622 fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
2623
2624 /* Update producers */
2625 bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
2626 fp_rx->rx_sge_prod);
2627
2628 test_loopback_exit:
2629 bp->link_params.loopback_mode = LOOPBACK_NONE;
2630
2631 return rc;
2632 }
2633
2634 static int bnx2x_test_loopback(struct bnx2x *bp)
2635 {
2636 int rc = 0, res;
2637
2638 if (BP_NOMCP(bp))
2639 return rc;
2640
2641 if (!netif_running(bp->dev))
2642 return BNX2X_LOOPBACK_FAILED;
2643
2644 bnx2x_netif_stop(bp, 1);
2645 bnx2x_acquire_phy_lock(bp);
2646
2647 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
2648 if (res) {
2649 DP(BNX2X_MSG_ETHTOOL, " PHY loopback failed (res %d)\n", res);
2650 rc |= BNX2X_PHY_LOOPBACK_FAILED;
2651 }
2652
2653 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
2654 if (res) {
2655 DP(BNX2X_MSG_ETHTOOL, " MAC loopback failed (res %d)\n", res);
2656 rc |= BNX2X_MAC_LOOPBACK_FAILED;
2657 }
2658
2659 bnx2x_release_phy_lock(bp);
2660 bnx2x_netif_start(bp);
2661
2662 return rc;
2663 }
2664
2665 static int bnx2x_test_ext_loopback(struct bnx2x *bp)
2666 {
2667 int rc;
2668 u8 is_serdes =
2669 (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2670
2671 if (BP_NOMCP(bp))
2672 return -ENODEV;
2673
2674 if (!netif_running(bp->dev))
2675 return BNX2X_EXT_LOOPBACK_FAILED;
2676
2677 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
2678 rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT);
2679 if (rc) {
2680 DP(BNX2X_MSG_ETHTOOL,
2681 "Can't perform self-test, nic_load (for external lb) failed\n");
2682 return -ENODEV;
2683 }
2684 bnx2x_wait_for_link(bp, 1, is_serdes);
2685
2686 bnx2x_netif_stop(bp, 1);
2687
2688 rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK);
2689 if (rc)
2690 DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed (res %d)\n", rc);
2691
2692 bnx2x_netif_start(bp);
2693
2694 return rc;
2695 }
2696
2697 struct code_entry {
2698 u32 sram_start_addr;
2699 u32 code_attribute;
2700 #define CODE_IMAGE_TYPE_MASK 0xf0800003
2701 #define CODE_IMAGE_VNTAG_PROFILES_DATA 0xd0000003
2702 #define CODE_IMAGE_LENGTH_MASK 0x007ffffc
2703 #define CODE_IMAGE_TYPE_EXTENDED_DIR 0xe0000000
2704 u32 nvm_start_addr;
2705 };
2706
2707 #define CODE_ENTRY_MAX 16
2708 #define CODE_ENTRY_EXTENDED_DIR_IDX 15
2709 #define MAX_IMAGES_IN_EXTENDED_DIR 64
2710 #define NVRAM_DIR_OFFSET 0x14
2711
2712 #define EXTENDED_DIR_EXISTS(code) \
2713 ((code & CODE_IMAGE_TYPE_MASK) == CODE_IMAGE_TYPE_EXTENDED_DIR && \
2714 (code & CODE_IMAGE_LENGTH_MASK) != 0)
2715
2716 #define CRC32_RESIDUAL 0xdebb20e3
2717 #define CRC_BUFF_SIZE 256
2718
2719 static int bnx2x_nvram_crc(struct bnx2x *bp,
2720 int offset,
2721 int size,
2722 u8 *buff)
2723 {
2724 u32 crc = ~0;
2725 int rc = 0, done = 0;
2726
2727 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2728 "NVRAM CRC from 0x%08x to 0x%08x\n", offset, offset + size);
2729
2730 while (done < size) {
2731 int count = min_t(int, size - done, CRC_BUFF_SIZE);
2732
2733 rc = bnx2x_nvram_read(bp, offset + done, buff, count);
2734
2735 if (rc)
2736 return rc;
2737
2738 crc = crc32_le(crc, buff, count);
2739 done += count;
2740 }
2741
2742 if (crc != CRC32_RESIDUAL)
2743 rc = -EINVAL;
2744
2745 return rc;
2746 }
2747
2748 static int bnx2x_test_nvram_dir(struct bnx2x *bp,
2749 struct code_entry *entry,
2750 u8 *buff)
2751 {
2752 size_t size = entry->code_attribute & CODE_IMAGE_LENGTH_MASK;
2753 u32 type = entry->code_attribute & CODE_IMAGE_TYPE_MASK;
2754 int rc;
2755
2756 /* Zero-length images and AFEX profiles do not have CRC */
2757 if (size == 0 || type == CODE_IMAGE_VNTAG_PROFILES_DATA)
2758 return 0;
2759
2760 rc = bnx2x_nvram_crc(bp, entry->nvm_start_addr, size, buff);
2761 if (rc)
2762 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2763 "image %x has failed crc test (rc %d)\n", type, rc);
2764
2765 return rc;
2766 }
2767
2768 static int bnx2x_test_dir_entry(struct bnx2x *bp, u32 addr, u8 *buff)
2769 {
2770 int rc;
2771 struct code_entry entry;
2772
2773 rc = bnx2x_nvram_read32(bp, addr, (u32 *)&entry, sizeof(entry));
2774 if (rc)
2775 return rc;
2776
2777 return bnx2x_test_nvram_dir(bp, &entry, buff);
2778 }
2779
2780 static int bnx2x_test_nvram_ext_dirs(struct bnx2x *bp, u8 *buff)
2781 {
2782 u32 rc, cnt, dir_offset = NVRAM_DIR_OFFSET;
2783 struct code_entry entry;
2784 int i;
2785
2786 rc = bnx2x_nvram_read32(bp,
2787 dir_offset +
2788 sizeof(entry) * CODE_ENTRY_EXTENDED_DIR_IDX,
2789 (u32 *)&entry, sizeof(entry));
2790 if (rc)
2791 return rc;
2792
2793 if (!EXTENDED_DIR_EXISTS(entry.code_attribute))
2794 return 0;
2795
2796 rc = bnx2x_nvram_read32(bp, entry.nvm_start_addr,
2797 &cnt, sizeof(u32));
2798 if (rc)
2799 return rc;
2800
2801 dir_offset = entry.nvm_start_addr + 8;
2802
2803 for (i = 0; i < cnt && i < MAX_IMAGES_IN_EXTENDED_DIR; i++) {
2804 rc = bnx2x_test_dir_entry(bp, dir_offset +
2805 sizeof(struct code_entry) * i,
2806 buff);
2807 if (rc)
2808 return rc;
2809 }
2810
2811 return 0;
2812 }
2813
2814 static int bnx2x_test_nvram_dirs(struct bnx2x *bp, u8 *buff)
2815 {
2816 u32 rc, dir_offset = NVRAM_DIR_OFFSET;
2817 int i;
2818
2819 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "NVRAM DIRS CRC test-set\n");
2820
2821 for (i = 0; i < CODE_ENTRY_EXTENDED_DIR_IDX; i++) {
2822 rc = bnx2x_test_dir_entry(bp, dir_offset +
2823 sizeof(struct code_entry) * i,
2824 buff);
2825 if (rc)
2826 return rc;
2827 }
2828
2829 return bnx2x_test_nvram_ext_dirs(bp, buff);
2830 }
2831
2832 struct crc_pair {
2833 int offset;
2834 int size;
2835 };
2836
2837 static int bnx2x_test_nvram_tbl(struct bnx2x *bp,
2838 const struct crc_pair *nvram_tbl, u8 *buf)
2839 {
2840 int i;
2841
2842 for (i = 0; nvram_tbl[i].size; i++) {
2843 int rc = bnx2x_nvram_crc(bp, nvram_tbl[i].offset,
2844 nvram_tbl[i].size, buf);
2845 if (rc) {
2846 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2847 "nvram_tbl[%d] has failed crc test (rc %d)\n",
2848 i, rc);
2849 return rc;
2850 }
2851 }
2852
2853 return 0;
2854 }
2855
2856 static int bnx2x_test_nvram(struct bnx2x *bp)
2857 {
2858 const struct crc_pair nvram_tbl[] = {
2859 { 0, 0x14 }, /* bootstrap */
2860 { 0x14, 0xec }, /* dir */
2861 { 0x100, 0x350 }, /* manuf_info */
2862 { 0x450, 0xf0 }, /* feature_info */
2863 { 0x640, 0x64 }, /* upgrade_key_info */
2864 { 0x708, 0x70 }, /* manuf_key_info */
2865 { 0, 0 }
2866 };
2867 const struct crc_pair nvram_tbl2[] = {
2868 { 0x7e8, 0x350 }, /* manuf_info2 */
2869 { 0xb38, 0xf0 }, /* feature_info */
2870 { 0, 0 }
2871 };
2872
2873 u8 *buf;
2874 int rc;
2875 u32 magic;
2876
2877 if (BP_NOMCP(bp))
2878 return 0;
2879
2880 buf = kmalloc(CRC_BUFF_SIZE, GFP_KERNEL);
2881 if (!buf) {
2882 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n");
2883 rc = -ENOMEM;
2884 goto test_nvram_exit;
2885 }
2886
2887 rc = bnx2x_nvram_read32(bp, 0, &magic, sizeof(magic));
2888 if (rc) {
2889 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2890 "magic value read (rc %d)\n", rc);
2891 goto test_nvram_exit;
2892 }
2893
2894 if (magic != 0x669955aa) {
2895 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2896 "wrong magic value (0x%08x)\n", magic);
2897 rc = -ENODEV;
2898 goto test_nvram_exit;
2899 }
2900
2901 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "Port 0 CRC test-set\n");
2902 rc = bnx2x_test_nvram_tbl(bp, nvram_tbl, buf);
2903 if (rc)
2904 goto test_nvram_exit;
2905
2906 if (!CHIP_IS_E1x(bp) && !CHIP_IS_57811xx(bp)) {
2907 u32 hide = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
2908 SHARED_HW_CFG_HIDE_PORT1;
2909
2910 if (!hide) {
2911 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2912 "Port 1 CRC test-set\n");
2913 rc = bnx2x_test_nvram_tbl(bp, nvram_tbl2, buf);
2914 if (rc)
2915 goto test_nvram_exit;
2916 }
2917 }
2918
2919 rc = bnx2x_test_nvram_dirs(bp, buf);
2920
2921 test_nvram_exit:
2922 kfree(buf);
2923 return rc;
2924 }
2925
2926 /* Send an EMPTY ramrod on the first queue */
2927 static int bnx2x_test_intr(struct bnx2x *bp)
2928 {
2929 struct bnx2x_queue_state_params params = {NULL};
2930
2931 if (!netif_running(bp->dev)) {
2932 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2933 "cannot access eeprom when the interface is down\n");
2934 return -ENODEV;
2935 }
2936
2937 params.q_obj = &bp->sp_objs->q_obj;
2938 params.cmd = BNX2X_Q_CMD_EMPTY;
2939
2940 __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
2941
2942 return bnx2x_queue_state_change(bp, &params);
2943 }
2944
2945 static void bnx2x_self_test(struct net_device *dev,
2946 struct ethtool_test *etest, u64 *buf)
2947 {
2948 struct bnx2x *bp = netdev_priv(dev);
2949 u8 is_serdes, link_up;
2950 int rc, cnt = 0;
2951
2952 if (pci_num_vf(bp->pdev)) {
2953 DP(BNX2X_MSG_IOV,
2954 "VFs are enabled, can not perform self test\n");
2955 return;
2956 }
2957
2958 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
2959 netdev_err(bp->dev,
2960 "Handling parity error recovery. Try again later\n");
2961 etest->flags |= ETH_TEST_FL_FAILED;
2962 return;
2963 }
2964
2965 DP(BNX2X_MSG_ETHTOOL,
2966 "Self-test command parameters: offline = %d, external_lb = %d\n",
2967 (etest->flags & ETH_TEST_FL_OFFLINE),
2968 (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2);
2969
2970 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp));
2971
2972 if (bnx2x_test_nvram(bp) != 0) {
2973 if (!IS_MF(bp))
2974 buf[4] = 1;
2975 else
2976 buf[0] = 1;
2977 etest->flags |= ETH_TEST_FL_FAILED;
2978 }
2979
2980 if (!netif_running(dev)) {
2981 DP(BNX2X_MSG_ETHTOOL, "Interface is down\n");
2982 return;
2983 }
2984
2985 is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2986 link_up = bp->link_vars.link_up;
2987 /* offline tests are not supported in MF mode */
2988 if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) {
2989 int port = BP_PORT(bp);
2990 u32 val;
2991
2992 /* save current value of input enable for TX port IF */
2993 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
2994 /* disable input for TX port IF */
2995 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
2996
2997 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
2998 rc = bnx2x_nic_load(bp, LOAD_DIAG);
2999 if (rc) {
3000 etest->flags |= ETH_TEST_FL_FAILED;
3001 DP(BNX2X_MSG_ETHTOOL,
3002 "Can't perform self-test, nic_load (for offline) failed\n");
3003 return;
3004 }
3005
3006 /* wait until link state is restored */
3007 bnx2x_wait_for_link(bp, 1, is_serdes);
3008
3009 if (bnx2x_test_registers(bp) != 0) {
3010 buf[0] = 1;
3011 etest->flags |= ETH_TEST_FL_FAILED;
3012 }
3013 if (bnx2x_test_memory(bp) != 0) {
3014 buf[1] = 1;
3015 etest->flags |= ETH_TEST_FL_FAILED;
3016 }
3017
3018 buf[2] = bnx2x_test_loopback(bp); /* internal LB */
3019 if (buf[2] != 0)
3020 etest->flags |= ETH_TEST_FL_FAILED;
3021
3022 if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) {
3023 buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */
3024 if (buf[3] != 0)
3025 etest->flags |= ETH_TEST_FL_FAILED;
3026 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
3027 }
3028
3029 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
3030
3031 /* restore input for TX port IF */
3032 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
3033 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
3034 if (rc) {
3035 etest->flags |= ETH_TEST_FL_FAILED;
3036 DP(BNX2X_MSG_ETHTOOL,
3037 "Can't perform self-test, nic_load (for online) failed\n");
3038 return;
3039 }
3040 /* wait until link state is restored */
3041 bnx2x_wait_for_link(bp, link_up, is_serdes);
3042 }
3043
3044 if (bnx2x_test_intr(bp) != 0) {
3045 if (!IS_MF(bp))
3046 buf[5] = 1;
3047 else
3048 buf[1] = 1;
3049 etest->flags |= ETH_TEST_FL_FAILED;
3050 }
3051
3052 if (link_up) {
3053 cnt = 100;
3054 while (bnx2x_link_test(bp, is_serdes) && --cnt)
3055 msleep(20);
3056 }
3057
3058 if (!cnt) {
3059 if (!IS_MF(bp))
3060 buf[6] = 1;
3061 else
3062 buf[2] = 1;
3063 etest->flags |= ETH_TEST_FL_FAILED;
3064 }
3065 }
3066
3067 #define IS_PORT_STAT(i) \
3068 ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
3069 #define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
3070 #define HIDE_PORT_STAT(bp) \
3071 ((IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS)) || \
3072 IS_VF(bp))
3073
3074 /* ethtool statistics are displayed for all regular ethernet queues and the
3075 * fcoe L2 queue if not disabled
3076 */
3077 static int bnx2x_num_stat_queues(struct bnx2x *bp)
3078 {
3079 return BNX2X_NUM_ETH_QUEUES(bp);
3080 }
3081
3082 static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
3083 {
3084 struct bnx2x *bp = netdev_priv(dev);
3085 int i, num_strings = 0;
3086
3087 switch (stringset) {
3088 case ETH_SS_STATS:
3089 if (is_multi(bp)) {
3090 num_strings = bnx2x_num_stat_queues(bp) *
3091 BNX2X_NUM_Q_STATS;
3092 } else
3093 num_strings = 0;
3094 if (HIDE_PORT_STAT(bp)) {
3095 for (i = 0; i < BNX2X_NUM_STATS; i++)
3096 if (IS_FUNC_STAT(i))
3097 num_strings++;
3098 } else
3099 num_strings += BNX2X_NUM_STATS;
3100
3101 return num_strings;
3102
3103 case ETH_SS_TEST:
3104 return BNX2X_NUM_TESTS(bp);
3105
3106 case ETH_SS_PRIV_FLAGS:
3107 return BNX2X_PRI_FLAG_LEN;
3108
3109 default:
3110 return -EINVAL;
3111 }
3112 }
3113
3114 static u32 bnx2x_get_private_flags(struct net_device *dev)
3115 {
3116 struct bnx2x *bp = netdev_priv(dev);
3117 u32 flags = 0;
3118
3119 flags |= (!(bp->flags & NO_ISCSI_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_ISCSI;
3120 flags |= (!(bp->flags & NO_FCOE_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_FCOE;
3121 flags |= (!!IS_MF_STORAGE_ONLY(bp)) << BNX2X_PRI_FLAG_STORAGE;
3122
3123 return flags;
3124 }
3125
3126 static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
3127 {
3128 struct bnx2x *bp = netdev_priv(dev);
3129 int i, j, k, start;
3130 char queue_name[MAX_QUEUE_NAME_LEN+1];
3131
3132 switch (stringset) {
3133 case ETH_SS_STATS:
3134 k = 0;
3135 if (is_multi(bp)) {
3136 for_each_eth_queue(bp, i) {
3137 memset(queue_name, 0, sizeof(queue_name));
3138 sprintf(queue_name, "%d", i);
3139 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
3140 snprintf(buf + (k + j)*ETH_GSTRING_LEN,
3141 ETH_GSTRING_LEN,
3142 bnx2x_q_stats_arr[j].string,
3143 queue_name);
3144 k += BNX2X_NUM_Q_STATS;
3145 }
3146 }
3147
3148 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
3149 if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i))
3150 continue;
3151 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
3152 bnx2x_stats_arr[i].string);
3153 j++;
3154 }
3155
3156 break;
3157
3158 case ETH_SS_TEST:
3159 /* First 4 tests cannot be done in MF mode */
3160 if (!IS_MF(bp))
3161 start = 0;
3162 else
3163 start = 4;
3164 memcpy(buf, bnx2x_tests_str_arr + start,
3165 ETH_GSTRING_LEN * BNX2X_NUM_TESTS(bp));
3166 break;
3167
3168 case ETH_SS_PRIV_FLAGS:
3169 memcpy(buf, bnx2x_private_arr,
3170 ETH_GSTRING_LEN * BNX2X_PRI_FLAG_LEN);
3171 break;
3172 }
3173 }
3174
3175 static void bnx2x_get_ethtool_stats(struct net_device *dev,
3176 struct ethtool_stats *stats, u64 *buf)
3177 {
3178 struct bnx2x *bp = netdev_priv(dev);
3179 u32 *hw_stats, *offset;
3180 int i, j, k = 0;
3181
3182 if (is_multi(bp)) {
3183 for_each_eth_queue(bp, i) {
3184 hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats;
3185 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
3186 if (bnx2x_q_stats_arr[j].size == 0) {
3187 /* skip this counter */
3188 buf[k + j] = 0;
3189 continue;
3190 }
3191 offset = (hw_stats +
3192 bnx2x_q_stats_arr[j].offset);
3193 if (bnx2x_q_stats_arr[j].size == 4) {
3194 /* 4-byte counter */
3195 buf[k + j] = (u64) *offset;
3196 continue;
3197 }
3198 /* 8-byte counter */
3199 buf[k + j] = HILO_U64(*offset, *(offset + 1));
3200 }
3201 k += BNX2X_NUM_Q_STATS;
3202 }
3203 }
3204
3205 hw_stats = (u32 *)&bp->eth_stats;
3206 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
3207 if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i))
3208 continue;
3209 if (bnx2x_stats_arr[i].size == 0) {
3210 /* skip this counter */
3211 buf[k + j] = 0;
3212 j++;
3213 continue;
3214 }
3215 offset = (hw_stats + bnx2x_stats_arr[i].offset);
3216 if (bnx2x_stats_arr[i].size == 4) {
3217 /* 4-byte counter */
3218 buf[k + j] = (u64) *offset;
3219 j++;
3220 continue;
3221 }
3222 /* 8-byte counter */
3223 buf[k + j] = HILO_U64(*offset, *(offset + 1));
3224 j++;
3225 }
3226 }
3227
3228 static int bnx2x_set_phys_id(struct net_device *dev,
3229 enum ethtool_phys_id_state state)
3230 {
3231 struct bnx2x *bp = netdev_priv(dev);
3232
3233 if (!bnx2x_is_nvm_accessible(bp)) {
3234 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
3235 "cannot access eeprom when the interface is down\n");
3236 return -EAGAIN;
3237 }
3238
3239 switch (state) {
3240 case ETHTOOL_ID_ACTIVE:
3241 return 1; /* cycle on/off once per second */
3242
3243 case ETHTOOL_ID_ON:
3244 bnx2x_acquire_phy_lock(bp);
3245 bnx2x_set_led(&bp->link_params, &bp->link_vars,
3246 LED_MODE_ON, SPEED_1000);
3247 bnx2x_release_phy_lock(bp);
3248 break;
3249
3250 case ETHTOOL_ID_OFF:
3251 bnx2x_acquire_phy_lock(bp);
3252 bnx2x_set_led(&bp->link_params, &bp->link_vars,
3253 LED_MODE_FRONT_PANEL_OFF, 0);
3254 bnx2x_release_phy_lock(bp);
3255 break;
3256
3257 case ETHTOOL_ID_INACTIVE:
3258 bnx2x_acquire_phy_lock(bp);
3259 bnx2x_set_led(&bp->link_params, &bp->link_vars,
3260 LED_MODE_OPER,
3261 bp->link_vars.line_speed);
3262 bnx2x_release_phy_lock(bp);
3263 }
3264
3265 return 0;
3266 }
3267
3268 static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
3269 {
3270 switch (info->flow_type) {
3271 case TCP_V4_FLOW:
3272 case TCP_V6_FLOW:
3273 info->data = RXH_IP_SRC | RXH_IP_DST |
3274 RXH_L4_B_0_1 | RXH_L4_B_2_3;
3275 break;
3276 case UDP_V4_FLOW:
3277 if (bp->rss_conf_obj.udp_rss_v4)
3278 info->data = RXH_IP_SRC | RXH_IP_DST |
3279 RXH_L4_B_0_1 | RXH_L4_B_2_3;
3280 else
3281 info->data = RXH_IP_SRC | RXH_IP_DST;
3282 break;
3283 case UDP_V6_FLOW:
3284 if (bp->rss_conf_obj.udp_rss_v6)
3285 info->data = RXH_IP_SRC | RXH_IP_DST |
3286 RXH_L4_B_0_1 | RXH_L4_B_2_3;
3287 else
3288 info->data = RXH_IP_SRC | RXH_IP_DST;
3289 break;
3290 case IPV4_FLOW:
3291 case IPV6_FLOW:
3292 info->data = RXH_IP_SRC | RXH_IP_DST;
3293 break;
3294 default:
3295 info->data = 0;
3296 break;
3297 }
3298
3299 return 0;
3300 }
3301
3302 static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
3303 u32 *rules __always_unused)
3304 {
3305 struct bnx2x *bp = netdev_priv(dev);
3306
3307 switch (info->cmd) {
3308 case ETHTOOL_GRXRINGS:
3309 info->data = BNX2X_NUM_ETH_QUEUES(bp);
3310 return 0;
3311 case ETHTOOL_GRXFH:
3312 return bnx2x_get_rss_flags(bp, info);
3313 default:
3314 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
3315 return -EOPNOTSUPP;
3316 }
3317 }
3318
3319 static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
3320 {
3321 int udp_rss_requested;
3322
3323 DP(BNX2X_MSG_ETHTOOL,
3324 "Set rss flags command parameters: flow type = %d, data = %llu\n",
3325 info->flow_type, info->data);
3326
3327 switch (info->flow_type) {
3328 case TCP_V4_FLOW:
3329 case TCP_V6_FLOW:
3330 /* For TCP only 4-tupple hash is supported */
3331 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST |
3332 RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
3333 DP(BNX2X_MSG_ETHTOOL,
3334 "Command parameters not supported\n");
3335 return -EINVAL;
3336 }
3337 return 0;
3338
3339 case UDP_V4_FLOW:
3340 case UDP_V6_FLOW:
3341 /* For UDP either 2-tupple hash or 4-tupple hash is supported */
3342 if (info->data == (RXH_IP_SRC | RXH_IP_DST |
3343 RXH_L4_B_0_1 | RXH_L4_B_2_3))
3344 udp_rss_requested = 1;
3345 else if (info->data == (RXH_IP_SRC | RXH_IP_DST))
3346 udp_rss_requested = 0;
3347 else
3348 return -EINVAL;
3349 if ((info->flow_type == UDP_V4_FLOW) &&
3350 (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) {
3351 bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested;
3352 DP(BNX2X_MSG_ETHTOOL,
3353 "rss re-configured, UDP 4-tupple %s\n",
3354 udp_rss_requested ? "enabled" : "disabled");
3355 return bnx2x_rss(bp, &bp->rss_conf_obj, false, true);
3356 } else if ((info->flow_type == UDP_V6_FLOW) &&
3357 (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) {
3358 bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested;
3359 DP(BNX2X_MSG_ETHTOOL,
3360 "rss re-configured, UDP 4-tupple %s\n",
3361 udp_rss_requested ? "enabled" : "disabled");
3362 return bnx2x_rss(bp, &bp->rss_conf_obj, false, true);
3363 }
3364 return 0;
3365
3366 case IPV4_FLOW:
3367 case IPV6_FLOW:
3368 /* For IP only 2-tupple hash is supported */
3369 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) {
3370 DP(BNX2X_MSG_ETHTOOL,
3371 "Command parameters not supported\n");
3372 return -EINVAL;
3373 }
3374 return 0;
3375
3376 case SCTP_V4_FLOW:
3377 case AH_ESP_V4_FLOW:
3378 case AH_V4_FLOW:
3379 case ESP_V4_FLOW:
3380 case SCTP_V6_FLOW:
3381 case AH_ESP_V6_FLOW:
3382 case AH_V6_FLOW:
3383 case ESP_V6_FLOW:
3384 case IP_USER_FLOW:
3385 case ETHER_FLOW:
3386 /* RSS is not supported for these protocols */
3387 if (info->data) {
3388 DP(BNX2X_MSG_ETHTOOL,
3389 "Command parameters not supported\n");
3390 return -EINVAL;
3391 }
3392 return 0;
3393
3394 default:
3395 return -EINVAL;
3396 }
3397 }
3398
3399 static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info)
3400 {
3401 struct bnx2x *bp = netdev_priv(dev);
3402
3403 switch (info->cmd) {
3404 case ETHTOOL_SRXFH:
3405 return bnx2x_set_rss_flags(bp, info);
3406 default:
3407 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
3408 return -EOPNOTSUPP;
3409 }
3410 }
3411
3412 static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev)
3413 {
3414 return T_ETH_INDIRECTION_TABLE_SIZE;
3415 }
3416
3417 static int bnx2x_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
3418 u8 *hfunc)
3419 {
3420 struct bnx2x *bp = netdev_priv(dev);
3421 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
3422 size_t i;
3423
3424 if (hfunc)
3425 *hfunc = ETH_RSS_HASH_TOP;
3426 if (!indir)
3427 return 0;
3428
3429 /* Get the current configuration of the RSS indirection table */
3430 bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table);
3431
3432 /*
3433 * We can't use a memcpy() as an internal storage of an
3434 * indirection table is a u8 array while indir->ring_index
3435 * points to an array of u32.
3436 *
3437 * Indirection table contains the FW Client IDs, so we need to
3438 * align the returned table to the Client ID of the leading RSS
3439 * queue.
3440 */
3441 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++)
3442 indir[i] = ind_table[i] - bp->fp->cl_id;
3443
3444 return 0;
3445 }
3446
3447 static int bnx2x_set_rxfh(struct net_device *dev, const u32 *indir,
3448 const u8 *key, const u8 hfunc)
3449 {
3450 struct bnx2x *bp = netdev_priv(dev);
3451 size_t i;
3452
3453 /* We require at least one supported parameter to be changed and no
3454 * change in any of the unsupported parameters
3455 */
3456 if (key ||
3457 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
3458 return -EOPNOTSUPP;
3459
3460 if (!indir)
3461 return 0;
3462
3463 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
3464 /*
3465 * The same as in bnx2x_get_rxfh: we can't use a memcpy()
3466 * as an internal storage of an indirection table is a u8 array
3467 * while indir->ring_index points to an array of u32.
3468 *
3469 * Indirection table contains the FW Client IDs, so we need to
3470 * align the received table to the Client ID of the leading RSS
3471 * queue
3472 */
3473 bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id;
3474 }
3475
3476 return bnx2x_config_rss_eth(bp, false);
3477 }
3478
3479 /**
3480 * bnx2x_get_channels - gets the number of RSS queues.
3481 *
3482 * @dev: net device
3483 * @channels: returns the number of max / current queues
3484 */
3485 static void bnx2x_get_channels(struct net_device *dev,
3486 struct ethtool_channels *channels)
3487 {
3488 struct bnx2x *bp = netdev_priv(dev);
3489
3490 channels->max_combined = BNX2X_MAX_RSS_COUNT(bp);
3491 channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp);
3492 }
3493
3494 /**
3495 * bnx2x_change_num_queues - change the number of RSS queues.
3496 *
3497 * @bp: bnx2x private structure
3498 *
3499 * Re-configure interrupt mode to get the new number of MSI-X
3500 * vectors and re-add NAPI objects.
3501 */
3502 static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss)
3503 {
3504 bnx2x_disable_msi(bp);
3505 bp->num_ethernet_queues = num_rss;
3506 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
3507 BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues);
3508 bnx2x_set_int_mode(bp);
3509 }
3510
3511 /**
3512 * bnx2x_set_channels - sets the number of RSS queues.
3513 *
3514 * @dev: net device
3515 * @channels: includes the number of queues requested
3516 */
3517 static int bnx2x_set_channels(struct net_device *dev,
3518 struct ethtool_channels *channels)
3519 {
3520 struct bnx2x *bp = netdev_priv(dev);
3521
3522 DP(BNX2X_MSG_ETHTOOL,
3523 "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n",
3524 channels->rx_count, channels->tx_count, channels->other_count,
3525 channels->combined_count);
3526
3527 if (pci_num_vf(bp->pdev)) {
3528 DP(BNX2X_MSG_IOV, "VFs are enabled, can not set channels\n");
3529 return -EPERM;
3530 }
3531
3532 /* We don't support separate rx / tx channels.
3533 * We don't allow setting 'other' channels.
3534 */
3535 if (channels->rx_count || channels->tx_count || channels->other_count
3536 || (channels->combined_count == 0) ||
3537 (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) {
3538 DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n");
3539 return -EINVAL;
3540 }
3541
3542 /* Check if there was a change in the active parameters */
3543 if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) {
3544 DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n");
3545 return 0;
3546 }
3547
3548 /* Set the requested number of queues in bp context.
3549 * Note that the actual number of queues created during load may be
3550 * less than requested if memory is low.
3551 */
3552 if (unlikely(!netif_running(dev))) {
3553 bnx2x_change_num_queues(bp, channels->combined_count);
3554 return 0;
3555 }
3556 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
3557 bnx2x_change_num_queues(bp, channels->combined_count);
3558 return bnx2x_nic_load(bp, LOAD_NORMAL);
3559 }
3560
3561 static int bnx2x_get_ts_info(struct net_device *dev,
3562 struct ethtool_ts_info *info)
3563 {
3564 struct bnx2x *bp = netdev_priv(dev);
3565
3566 if (bp->flags & PTP_SUPPORTED) {
3567 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
3568 SOF_TIMESTAMPING_RX_SOFTWARE |
3569 SOF_TIMESTAMPING_SOFTWARE |
3570 SOF_TIMESTAMPING_TX_HARDWARE |
3571 SOF_TIMESTAMPING_RX_HARDWARE |
3572 SOF_TIMESTAMPING_RAW_HARDWARE;
3573
3574 if (bp->ptp_clock)
3575 info->phc_index = ptp_clock_index(bp->ptp_clock);
3576 else
3577 info->phc_index = -1;
3578
3579 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
3580 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
3581 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
3582 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
3583 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
3584 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
3585 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
3586 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
3587 (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
3588 (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) |
3589 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) |
3590 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) |
3591 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ);
3592
3593 info->tx_types = (1 << HWTSTAMP_TX_OFF)|(1 << HWTSTAMP_TX_ON);
3594
3595 return 0;
3596 }
3597
3598 return ethtool_op_get_ts_info(dev, info);
3599 }
3600
3601 static const struct ethtool_ops bnx2x_ethtool_ops = {
3602 .get_settings = bnx2x_get_settings,
3603 .set_settings = bnx2x_set_settings,
3604 .get_drvinfo = bnx2x_get_drvinfo,
3605 .get_regs_len = bnx2x_get_regs_len,
3606 .get_regs = bnx2x_get_regs,
3607 .get_dump_flag = bnx2x_get_dump_flag,
3608 .get_dump_data = bnx2x_get_dump_data,
3609 .set_dump = bnx2x_set_dump,
3610 .get_wol = bnx2x_get_wol,
3611 .set_wol = bnx2x_set_wol,
3612 .get_msglevel = bnx2x_get_msglevel,
3613 .set_msglevel = bnx2x_set_msglevel,
3614 .nway_reset = bnx2x_nway_reset,
3615 .get_link = bnx2x_get_link,
3616 .get_eeprom_len = bnx2x_get_eeprom_len,
3617 .get_eeprom = bnx2x_get_eeprom,
3618 .set_eeprom = bnx2x_set_eeprom,
3619 .get_coalesce = bnx2x_get_coalesce,
3620 .set_coalesce = bnx2x_set_coalesce,
3621 .get_ringparam = bnx2x_get_ringparam,
3622 .set_ringparam = bnx2x_set_ringparam,
3623 .get_pauseparam = bnx2x_get_pauseparam,
3624 .set_pauseparam = bnx2x_set_pauseparam,
3625 .self_test = bnx2x_self_test,
3626 .get_sset_count = bnx2x_get_sset_count,
3627 .get_priv_flags = bnx2x_get_private_flags,
3628 .get_strings = bnx2x_get_strings,
3629 .set_phys_id = bnx2x_set_phys_id,
3630 .get_ethtool_stats = bnx2x_get_ethtool_stats,
3631 .get_rxnfc = bnx2x_get_rxnfc,
3632 .set_rxnfc = bnx2x_set_rxnfc,
3633 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size,
3634 .get_rxfh = bnx2x_get_rxfh,
3635 .set_rxfh = bnx2x_set_rxfh,
3636 .get_channels = bnx2x_get_channels,
3637 .set_channels = bnx2x_set_channels,
3638 .get_module_info = bnx2x_get_module_info,
3639 .get_module_eeprom = bnx2x_get_module_eeprom,
3640 .get_eee = bnx2x_get_eee,
3641 .set_eee = bnx2x_set_eee,
3642 .get_ts_info = bnx2x_get_ts_info,
3643 };
3644
3645 static const struct ethtool_ops bnx2x_vf_ethtool_ops = {
3646 .get_settings = bnx2x_get_vf_settings,
3647 .get_drvinfo = bnx2x_get_drvinfo,
3648 .get_msglevel = bnx2x_get_msglevel,
3649 .set_msglevel = bnx2x_set_msglevel,
3650 .get_link = bnx2x_get_link,
3651 .get_coalesce = bnx2x_get_coalesce,
3652 .get_ringparam = bnx2x_get_ringparam,
3653 .set_ringparam = bnx2x_set_ringparam,
3654 .get_sset_count = bnx2x_get_sset_count,
3655 .get_strings = bnx2x_get_strings,
3656 .get_ethtool_stats = bnx2x_get_ethtool_stats,
3657 .get_rxnfc = bnx2x_get_rxnfc,
3658 .set_rxnfc = bnx2x_set_rxnfc,
3659 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size,
3660 .get_rxfh = bnx2x_get_rxfh,
3661 .set_rxfh = bnx2x_set_rxfh,
3662 .get_channels = bnx2x_get_channels,
3663 .set_channels = bnx2x_set_channels,
3664 };
3665
3666 void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev)
3667 {
3668 netdev->ethtool_ops = (IS_PF(bp)) ?
3669 &bnx2x_ethtool_ops : &bnx2x_vf_ethtool_ops;
3670 }
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