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[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_ethtool.c
1 /* bnx2x_ethtool.c: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2013 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
20 #include <linux/ethtool.h>
21 #include <linux/netdevice.h>
22 #include <linux/types.h>
23 #include <linux/sched.h>
24 #include <linux/crc32.h>
25 #include "bnx2x.h"
26 #include "bnx2x_cmn.h"
27 #include "bnx2x_dump.h"
28 #include "bnx2x_init.h"
29
30 /* Note: in the format strings below %s is replaced by the queue-name which is
31 * either its index or 'fcoe' for the fcoe queue. Make sure the format string
32 * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
33 */
34 #define MAX_QUEUE_NAME_LEN 4
35 static const struct {
36 long offset;
37 int size;
38 char string[ETH_GSTRING_LEN];
39 } bnx2x_q_stats_arr[] = {
40 /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
41 { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
42 8, "[%s]: rx_ucast_packets" },
43 { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
44 8, "[%s]: rx_mcast_packets" },
45 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
46 8, "[%s]: rx_bcast_packets" },
47 { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
48 { Q_STATS_OFFSET32(rx_err_discard_pkt),
49 4, "[%s]: rx_phy_ip_err_discards"},
50 { Q_STATS_OFFSET32(rx_skb_alloc_failed),
51 4, "[%s]: rx_skb_alloc_discard" },
52 { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
53
54 { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
55 /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
56 8, "[%s]: tx_ucast_packets" },
57 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
58 8, "[%s]: tx_mcast_packets" },
59 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
60 8, "[%s]: tx_bcast_packets" },
61 { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
62 8, "[%s]: tpa_aggregations" },
63 { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
64 8, "[%s]: tpa_aggregated_frames"},
65 { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"},
66 { Q_STATS_OFFSET32(driver_filtered_tx_pkt),
67 4, "[%s]: driver_filtered_tx_pkt" }
68 };
69
70 #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
71
72 static const struct {
73 long offset;
74 int size;
75 u32 flags;
76 #define STATS_FLAGS_PORT 1
77 #define STATS_FLAGS_FUNC 2
78 #define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
79 char string[ETH_GSTRING_LEN];
80 } bnx2x_stats_arr[] = {
81 /* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
82 8, STATS_FLAGS_BOTH, "rx_bytes" },
83 { STATS_OFFSET32(error_bytes_received_hi),
84 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
85 { STATS_OFFSET32(total_unicast_packets_received_hi),
86 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
87 { STATS_OFFSET32(total_multicast_packets_received_hi),
88 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
89 { STATS_OFFSET32(total_broadcast_packets_received_hi),
90 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
91 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
92 8, STATS_FLAGS_PORT, "rx_crc_errors" },
93 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
94 8, STATS_FLAGS_PORT, "rx_align_errors" },
95 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
96 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
97 { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
98 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
99 /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
100 8, STATS_FLAGS_PORT, "rx_fragments" },
101 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
102 8, STATS_FLAGS_PORT, "rx_jabbers" },
103 { STATS_OFFSET32(no_buff_discard_hi),
104 8, STATS_FLAGS_BOTH, "rx_discards" },
105 { STATS_OFFSET32(mac_filter_discard),
106 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
107 { STATS_OFFSET32(mf_tag_discard),
108 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" },
109 { STATS_OFFSET32(pfc_frames_received_hi),
110 8, STATS_FLAGS_PORT, "pfc_frames_received" },
111 { STATS_OFFSET32(pfc_frames_sent_hi),
112 8, STATS_FLAGS_PORT, "pfc_frames_sent" },
113 { STATS_OFFSET32(brb_drop_hi),
114 8, STATS_FLAGS_PORT, "rx_brb_discard" },
115 { STATS_OFFSET32(brb_truncate_hi),
116 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
117 { STATS_OFFSET32(pause_frames_received_hi),
118 8, STATS_FLAGS_PORT, "rx_pause_frames" },
119 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
120 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
121 { STATS_OFFSET32(nig_timer_max),
122 4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
123 /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
124 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
125 { STATS_OFFSET32(rx_skb_alloc_failed),
126 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
127 { STATS_OFFSET32(hw_csum_err),
128 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
129
130 { STATS_OFFSET32(total_bytes_transmitted_hi),
131 8, STATS_FLAGS_BOTH, "tx_bytes" },
132 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
133 8, STATS_FLAGS_PORT, "tx_error_bytes" },
134 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
135 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
136 { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
137 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
138 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
139 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
140 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
141 8, STATS_FLAGS_PORT, "tx_mac_errors" },
142 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
143 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
144 /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
145 8, STATS_FLAGS_PORT, "tx_single_collisions" },
146 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
147 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
148 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
149 8, STATS_FLAGS_PORT, "tx_deferred" },
150 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
151 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
152 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
153 8, STATS_FLAGS_PORT, "tx_late_collisions" },
154 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
155 8, STATS_FLAGS_PORT, "tx_total_collisions" },
156 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
157 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
158 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
159 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
160 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
161 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
162 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
163 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
164 /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
165 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
166 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
167 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
168 { STATS_OFFSET32(etherstatspktsover1522octets_hi),
169 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
170 { STATS_OFFSET32(pause_frames_sent_hi),
171 8, STATS_FLAGS_PORT, "tx_pause_frames" },
172 { STATS_OFFSET32(total_tpa_aggregations_hi),
173 8, STATS_FLAGS_FUNC, "tpa_aggregations" },
174 { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
175 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"},
176 { STATS_OFFSET32(total_tpa_bytes_hi),
177 8, STATS_FLAGS_FUNC, "tpa_bytes"},
178 { STATS_OFFSET32(recoverable_error),
179 4, STATS_FLAGS_FUNC, "recoverable_errors" },
180 { STATS_OFFSET32(unrecoverable_error),
181 4, STATS_FLAGS_FUNC, "unrecoverable_errors" },
182 { STATS_OFFSET32(driver_filtered_tx_pkt),
183 4, STATS_FLAGS_FUNC, "driver_filtered_tx_pkt" },
184 { STATS_OFFSET32(eee_tx_lpi),
185 4, STATS_FLAGS_PORT, "Tx LPI entry count"}
186 };
187
188 #define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr)
189
190 static int bnx2x_get_port_type(struct bnx2x *bp)
191 {
192 int port_type;
193 u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
194 switch (bp->link_params.phy[phy_idx].media_type) {
195 case ETH_PHY_SFPP_10G_FIBER:
196 case ETH_PHY_SFP_1G_FIBER:
197 case ETH_PHY_XFP_FIBER:
198 case ETH_PHY_KR:
199 case ETH_PHY_CX4:
200 port_type = PORT_FIBRE;
201 break;
202 case ETH_PHY_DA_TWINAX:
203 port_type = PORT_DA;
204 break;
205 case ETH_PHY_BASE_T:
206 port_type = PORT_TP;
207 break;
208 case ETH_PHY_NOT_PRESENT:
209 port_type = PORT_NONE;
210 break;
211 case ETH_PHY_UNSPECIFIED:
212 default:
213 port_type = PORT_OTHER;
214 break;
215 }
216 return port_type;
217 }
218
219 static int bnx2x_get_vf_settings(struct net_device *dev,
220 struct ethtool_cmd *cmd)
221 {
222 struct bnx2x *bp = netdev_priv(dev);
223
224 if (bp->state == BNX2X_STATE_OPEN) {
225 if (test_bit(BNX2X_LINK_REPORT_FD,
226 &bp->vf_link_vars.link_report_flags))
227 cmd->duplex = DUPLEX_FULL;
228 else
229 cmd->duplex = DUPLEX_HALF;
230
231 ethtool_cmd_speed_set(cmd, bp->vf_link_vars.line_speed);
232 } else {
233 cmd->duplex = DUPLEX_UNKNOWN;
234 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
235 }
236
237 cmd->port = PORT_OTHER;
238 cmd->phy_address = 0;
239 cmd->transceiver = XCVR_INTERNAL;
240 cmd->autoneg = AUTONEG_DISABLE;
241 cmd->maxtxpkt = 0;
242 cmd->maxrxpkt = 0;
243
244 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
245 " supported 0x%x advertising 0x%x speed %u\n"
246 " duplex %d port %d phy_address %d transceiver %d\n"
247 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
248 cmd->cmd, cmd->supported, cmd->advertising,
249 ethtool_cmd_speed(cmd),
250 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
251 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
252
253 return 0;
254 }
255
256 static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
257 {
258 struct bnx2x *bp = netdev_priv(dev);
259 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
260 u32 media_type;
261
262 /* Dual Media boards present all available port types */
263 cmd->supported = bp->port.supported[cfg_idx] |
264 (bp->port.supported[cfg_idx ^ 1] &
265 (SUPPORTED_TP | SUPPORTED_FIBRE));
266 cmd->advertising = bp->port.advertising[cfg_idx];
267 media_type = bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type;
268 if (media_type == ETH_PHY_SFP_1G_FIBER) {
269 cmd->supported &= ~(SUPPORTED_10000baseT_Full);
270 cmd->advertising &= ~(ADVERTISED_10000baseT_Full);
271 }
272
273 if ((bp->state == BNX2X_STATE_OPEN) && bp->link_vars.link_up &&
274 !(bp->flags & MF_FUNC_DIS)) {
275 cmd->duplex = bp->link_vars.duplex;
276
277 if (IS_MF(bp) && !BP_NOMCP(bp))
278 ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
279 else
280 ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
281 } else {
282 cmd->duplex = DUPLEX_UNKNOWN;
283 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
284 }
285
286 cmd->port = bnx2x_get_port_type(bp);
287
288 cmd->phy_address = bp->mdio.prtad;
289 cmd->transceiver = XCVR_INTERNAL;
290
291 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
292 cmd->autoneg = AUTONEG_ENABLE;
293 else
294 cmd->autoneg = AUTONEG_DISABLE;
295
296 /* Publish LP advertised speeds and FC */
297 if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
298 u32 status = bp->link_vars.link_status;
299
300 cmd->lp_advertising |= ADVERTISED_Autoneg;
301 if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE)
302 cmd->lp_advertising |= ADVERTISED_Pause;
303 if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
304 cmd->lp_advertising |= ADVERTISED_Asym_Pause;
305
306 if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE)
307 cmd->lp_advertising |= ADVERTISED_10baseT_Half;
308 if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE)
309 cmd->lp_advertising |= ADVERTISED_10baseT_Full;
310 if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE)
311 cmd->lp_advertising |= ADVERTISED_100baseT_Half;
312 if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE)
313 cmd->lp_advertising |= ADVERTISED_100baseT_Full;
314 if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE)
315 cmd->lp_advertising |= ADVERTISED_1000baseT_Half;
316 if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) {
317 if (media_type == ETH_PHY_KR) {
318 cmd->lp_advertising |=
319 ADVERTISED_1000baseKX_Full;
320 } else {
321 cmd->lp_advertising |=
322 ADVERTISED_1000baseT_Full;
323 }
324 }
325 if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE)
326 cmd->lp_advertising |= ADVERTISED_2500baseX_Full;
327 if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE) {
328 if (media_type == ETH_PHY_KR) {
329 cmd->lp_advertising |=
330 ADVERTISED_10000baseKR_Full;
331 } else {
332 cmd->lp_advertising |=
333 ADVERTISED_10000baseT_Full;
334 }
335 }
336 if (status & LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE)
337 cmd->lp_advertising |= ADVERTISED_20000baseKR2_Full;
338 }
339
340 cmd->maxtxpkt = 0;
341 cmd->maxrxpkt = 0;
342
343 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
344 " supported 0x%x advertising 0x%x speed %u\n"
345 " duplex %d port %d phy_address %d transceiver %d\n"
346 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
347 cmd->cmd, cmd->supported, cmd->advertising,
348 ethtool_cmd_speed(cmd),
349 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
350 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
351
352 return 0;
353 }
354
355 static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
356 {
357 struct bnx2x *bp = netdev_priv(dev);
358 u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
359 u32 speed, phy_idx;
360
361 if (IS_MF_SD(bp))
362 return 0;
363
364 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
365 " supported 0x%x advertising 0x%x speed %u\n"
366 " duplex %d port %d phy_address %d transceiver %d\n"
367 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
368 cmd->cmd, cmd->supported, cmd->advertising,
369 ethtool_cmd_speed(cmd),
370 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
371 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
372
373 speed = ethtool_cmd_speed(cmd);
374
375 /* If received a request for an unknown duplex, assume full*/
376 if (cmd->duplex == DUPLEX_UNKNOWN)
377 cmd->duplex = DUPLEX_FULL;
378
379 if (IS_MF_SI(bp)) {
380 u32 part;
381 u32 line_speed = bp->link_vars.line_speed;
382
383 /* use 10G if no link detected */
384 if (!line_speed)
385 line_speed = 10000;
386
387 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
388 DP(BNX2X_MSG_ETHTOOL,
389 "To set speed BC %X or higher is required, please upgrade BC\n",
390 REQ_BC_VER_4_SET_MF_BW);
391 return -EINVAL;
392 }
393
394 part = (speed * 100) / line_speed;
395
396 if (line_speed < speed || !part) {
397 DP(BNX2X_MSG_ETHTOOL,
398 "Speed setting should be in a range from 1%% to 100%% of actual line speed\n");
399 return -EINVAL;
400 }
401
402 if (bp->state != BNX2X_STATE_OPEN)
403 /* store value for following "load" */
404 bp->pending_max = part;
405 else
406 bnx2x_update_max_mf_config(bp, part);
407
408 return 0;
409 }
410
411 cfg_idx = bnx2x_get_link_cfg_idx(bp);
412 old_multi_phy_config = bp->link_params.multi_phy_config;
413 if (cmd->port != bnx2x_get_port_type(bp)) {
414 switch (cmd->port) {
415 case PORT_TP:
416 if (!(bp->port.supported[0] & SUPPORTED_TP ||
417 bp->port.supported[1] & SUPPORTED_TP)) {
418 DP(BNX2X_MSG_ETHTOOL,
419 "Unsupported port type\n");
420 return -EINVAL;
421 }
422 bp->link_params.multi_phy_config &=
423 ~PORT_HW_CFG_PHY_SELECTION_MASK;
424 if (bp->link_params.multi_phy_config &
425 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
426 bp->link_params.multi_phy_config |=
427 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
428 else
429 bp->link_params.multi_phy_config |=
430 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
431 break;
432 case PORT_FIBRE:
433 case PORT_DA:
434 case PORT_NONE:
435 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
436 bp->port.supported[1] & SUPPORTED_FIBRE)) {
437 DP(BNX2X_MSG_ETHTOOL,
438 "Unsupported port type\n");
439 return -EINVAL;
440 }
441 bp->link_params.multi_phy_config &=
442 ~PORT_HW_CFG_PHY_SELECTION_MASK;
443 if (bp->link_params.multi_phy_config &
444 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
445 bp->link_params.multi_phy_config |=
446 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
447 else
448 bp->link_params.multi_phy_config |=
449 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
450 break;
451 default:
452 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
453 return -EINVAL;
454 }
455 }
456 /* Save new config in case command complete successfully */
457 new_multi_phy_config = bp->link_params.multi_phy_config;
458 /* Get the new cfg_idx */
459 cfg_idx = bnx2x_get_link_cfg_idx(bp);
460 /* Restore old config in case command failed */
461 bp->link_params.multi_phy_config = old_multi_phy_config;
462 DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx);
463
464 if (cmd->autoneg == AUTONEG_ENABLE) {
465 u32 an_supported_speed = bp->port.supported[cfg_idx];
466 if (bp->link_params.phy[EXT_PHY1].type ==
467 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
468 an_supported_speed |= (SUPPORTED_100baseT_Half |
469 SUPPORTED_100baseT_Full);
470 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
471 DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n");
472 return -EINVAL;
473 }
474
475 /* advertise the requested speed and duplex if supported */
476 if (cmd->advertising & ~an_supported_speed) {
477 DP(BNX2X_MSG_ETHTOOL,
478 "Advertisement parameters are not supported\n");
479 return -EINVAL;
480 }
481
482 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
483 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
484 bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg |
485 cmd->advertising);
486 if (cmd->advertising) {
487
488 bp->link_params.speed_cap_mask[cfg_idx] = 0;
489 if (cmd->advertising & ADVERTISED_10baseT_Half) {
490 bp->link_params.speed_cap_mask[cfg_idx] |=
491 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF;
492 }
493 if (cmd->advertising & ADVERTISED_10baseT_Full)
494 bp->link_params.speed_cap_mask[cfg_idx] |=
495 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL;
496
497 if (cmd->advertising & ADVERTISED_100baseT_Full)
498 bp->link_params.speed_cap_mask[cfg_idx] |=
499 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL;
500
501 if (cmd->advertising & ADVERTISED_100baseT_Half) {
502 bp->link_params.speed_cap_mask[cfg_idx] |=
503 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF;
504 }
505 if (cmd->advertising & ADVERTISED_1000baseT_Half) {
506 bp->link_params.speed_cap_mask[cfg_idx] |=
507 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
508 }
509 if (cmd->advertising & (ADVERTISED_1000baseT_Full |
510 ADVERTISED_1000baseKX_Full))
511 bp->link_params.speed_cap_mask[cfg_idx] |=
512 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
513
514 if (cmd->advertising & (ADVERTISED_10000baseT_Full |
515 ADVERTISED_10000baseKX4_Full |
516 ADVERTISED_10000baseKR_Full))
517 bp->link_params.speed_cap_mask[cfg_idx] |=
518 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G;
519
520 if (cmd->advertising & ADVERTISED_20000baseKR2_Full)
521 bp->link_params.speed_cap_mask[cfg_idx] |=
522 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G;
523 }
524 } else { /* forced speed */
525 /* advertise the requested speed and duplex if supported */
526 switch (speed) {
527 case SPEED_10:
528 if (cmd->duplex == DUPLEX_FULL) {
529 if (!(bp->port.supported[cfg_idx] &
530 SUPPORTED_10baseT_Full)) {
531 DP(BNX2X_MSG_ETHTOOL,
532 "10M full not supported\n");
533 return -EINVAL;
534 }
535
536 advertising = (ADVERTISED_10baseT_Full |
537 ADVERTISED_TP);
538 } else {
539 if (!(bp->port.supported[cfg_idx] &
540 SUPPORTED_10baseT_Half)) {
541 DP(BNX2X_MSG_ETHTOOL,
542 "10M half not supported\n");
543 return -EINVAL;
544 }
545
546 advertising = (ADVERTISED_10baseT_Half |
547 ADVERTISED_TP);
548 }
549 break;
550
551 case SPEED_100:
552 if (cmd->duplex == DUPLEX_FULL) {
553 if (!(bp->port.supported[cfg_idx] &
554 SUPPORTED_100baseT_Full)) {
555 DP(BNX2X_MSG_ETHTOOL,
556 "100M full not supported\n");
557 return -EINVAL;
558 }
559
560 advertising = (ADVERTISED_100baseT_Full |
561 ADVERTISED_TP);
562 } else {
563 if (!(bp->port.supported[cfg_idx] &
564 SUPPORTED_100baseT_Half)) {
565 DP(BNX2X_MSG_ETHTOOL,
566 "100M half not supported\n");
567 return -EINVAL;
568 }
569
570 advertising = (ADVERTISED_100baseT_Half |
571 ADVERTISED_TP);
572 }
573 break;
574
575 case SPEED_1000:
576 if (cmd->duplex != DUPLEX_FULL) {
577 DP(BNX2X_MSG_ETHTOOL,
578 "1G half not supported\n");
579 return -EINVAL;
580 }
581
582 if (bp->port.supported[cfg_idx] &
583 SUPPORTED_1000baseT_Full) {
584 advertising = (ADVERTISED_1000baseT_Full |
585 ADVERTISED_TP);
586
587 } else if (bp->port.supported[cfg_idx] &
588 SUPPORTED_1000baseKX_Full) {
589 advertising = ADVERTISED_1000baseKX_Full;
590 } else {
591 DP(BNX2X_MSG_ETHTOOL,
592 "1G full not supported\n");
593 return -EINVAL;
594 }
595
596 break;
597
598 case SPEED_2500:
599 if (cmd->duplex != DUPLEX_FULL) {
600 DP(BNX2X_MSG_ETHTOOL,
601 "2.5G half not supported\n");
602 return -EINVAL;
603 }
604
605 if (!(bp->port.supported[cfg_idx]
606 & SUPPORTED_2500baseX_Full)) {
607 DP(BNX2X_MSG_ETHTOOL,
608 "2.5G full not supported\n");
609 return -EINVAL;
610 }
611
612 advertising = (ADVERTISED_2500baseX_Full |
613 ADVERTISED_TP);
614 break;
615
616 case SPEED_10000:
617 if (cmd->duplex != DUPLEX_FULL) {
618 DP(BNX2X_MSG_ETHTOOL,
619 "10G half not supported\n");
620 return -EINVAL;
621 }
622 phy_idx = bnx2x_get_cur_phy_idx(bp);
623 if ((bp->port.supported[cfg_idx] &
624 SUPPORTED_10000baseT_Full) &&
625 (bp->link_params.phy[phy_idx].media_type !=
626 ETH_PHY_SFP_1G_FIBER)) {
627 advertising = (ADVERTISED_10000baseT_Full |
628 ADVERTISED_FIBRE);
629 } else if (bp->port.supported[cfg_idx] &
630 SUPPORTED_10000baseKR_Full) {
631 advertising = (ADVERTISED_10000baseKR_Full |
632 ADVERTISED_FIBRE);
633 } else {
634 DP(BNX2X_MSG_ETHTOOL,
635 "10G full not supported\n");
636 return -EINVAL;
637 }
638
639 break;
640
641 default:
642 DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed);
643 return -EINVAL;
644 }
645
646 bp->link_params.req_line_speed[cfg_idx] = speed;
647 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
648 bp->port.advertising[cfg_idx] = advertising;
649 }
650
651 DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n"
652 " req_duplex %d advertising 0x%x\n",
653 bp->link_params.req_line_speed[cfg_idx],
654 bp->link_params.req_duplex[cfg_idx],
655 bp->port.advertising[cfg_idx]);
656
657 /* Set new config */
658 bp->link_params.multi_phy_config = new_multi_phy_config;
659 if (netif_running(dev)) {
660 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
661 bnx2x_force_link_reset(bp);
662 bnx2x_link_set(bp);
663 }
664
665 return 0;
666 }
667
668 #define DUMP_ALL_PRESETS 0x1FFF
669 #define DUMP_MAX_PRESETS 13
670
671 static int __bnx2x_get_preset_regs_len(struct bnx2x *bp, u32 preset)
672 {
673 if (CHIP_IS_E1(bp))
674 return dump_num_registers[0][preset-1];
675 else if (CHIP_IS_E1H(bp))
676 return dump_num_registers[1][preset-1];
677 else if (CHIP_IS_E2(bp))
678 return dump_num_registers[2][preset-1];
679 else if (CHIP_IS_E3A0(bp))
680 return dump_num_registers[3][preset-1];
681 else if (CHIP_IS_E3B0(bp))
682 return dump_num_registers[4][preset-1];
683 else
684 return 0;
685 }
686
687 static int __bnx2x_get_regs_len(struct bnx2x *bp)
688 {
689 u32 preset_idx;
690 int regdump_len = 0;
691
692 /* Calculate the total preset regs length */
693 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++)
694 regdump_len += __bnx2x_get_preset_regs_len(bp, preset_idx);
695
696 return regdump_len;
697 }
698
699 static int bnx2x_get_regs_len(struct net_device *dev)
700 {
701 struct bnx2x *bp = netdev_priv(dev);
702 int regdump_len = 0;
703
704 if (IS_VF(bp))
705 return 0;
706
707 regdump_len = __bnx2x_get_regs_len(bp);
708 regdump_len *= 4;
709 regdump_len += sizeof(struct dump_header);
710
711 return regdump_len;
712 }
713
714 #define IS_E1_REG(chips) ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1)
715 #define IS_E1H_REG(chips) ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H)
716 #define IS_E2_REG(chips) ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2)
717 #define IS_E3A0_REG(chips) ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0)
718 #define IS_E3B0_REG(chips) ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0)
719
720 #define IS_REG_IN_PRESET(presets, idx) \
721 ((presets & (1 << (idx-1))) == (1 << (idx-1)))
722
723 /******* Paged registers info selectors ********/
724 static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
725 {
726 if (CHIP_IS_E2(bp))
727 return page_vals_e2;
728 else if (CHIP_IS_E3(bp))
729 return page_vals_e3;
730 else
731 return NULL;
732 }
733
734 static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
735 {
736 if (CHIP_IS_E2(bp))
737 return PAGE_MODE_VALUES_E2;
738 else if (CHIP_IS_E3(bp))
739 return PAGE_MODE_VALUES_E3;
740 else
741 return 0;
742 }
743
744 static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
745 {
746 if (CHIP_IS_E2(bp))
747 return page_write_regs_e2;
748 else if (CHIP_IS_E3(bp))
749 return page_write_regs_e3;
750 else
751 return NULL;
752 }
753
754 static u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
755 {
756 if (CHIP_IS_E2(bp))
757 return PAGE_WRITE_REGS_E2;
758 else if (CHIP_IS_E3(bp))
759 return PAGE_WRITE_REGS_E3;
760 else
761 return 0;
762 }
763
764 static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
765 {
766 if (CHIP_IS_E2(bp))
767 return page_read_regs_e2;
768 else if (CHIP_IS_E3(bp))
769 return page_read_regs_e3;
770 else
771 return NULL;
772 }
773
774 static u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
775 {
776 if (CHIP_IS_E2(bp))
777 return PAGE_READ_REGS_E2;
778 else if (CHIP_IS_E3(bp))
779 return PAGE_READ_REGS_E3;
780 else
781 return 0;
782 }
783
784 static bool bnx2x_is_reg_in_chip(struct bnx2x *bp,
785 const struct reg_addr *reg_info)
786 {
787 if (CHIP_IS_E1(bp))
788 return IS_E1_REG(reg_info->chips);
789 else if (CHIP_IS_E1H(bp))
790 return IS_E1H_REG(reg_info->chips);
791 else if (CHIP_IS_E2(bp))
792 return IS_E2_REG(reg_info->chips);
793 else if (CHIP_IS_E3A0(bp))
794 return IS_E3A0_REG(reg_info->chips);
795 else if (CHIP_IS_E3B0(bp))
796 return IS_E3B0_REG(reg_info->chips);
797 else
798 return false;
799 }
800
801 static bool bnx2x_is_wreg_in_chip(struct bnx2x *bp,
802 const struct wreg_addr *wreg_info)
803 {
804 if (CHIP_IS_E1(bp))
805 return IS_E1_REG(wreg_info->chips);
806 else if (CHIP_IS_E1H(bp))
807 return IS_E1H_REG(wreg_info->chips);
808 else if (CHIP_IS_E2(bp))
809 return IS_E2_REG(wreg_info->chips);
810 else if (CHIP_IS_E3A0(bp))
811 return IS_E3A0_REG(wreg_info->chips);
812 else if (CHIP_IS_E3B0(bp))
813 return IS_E3B0_REG(wreg_info->chips);
814 else
815 return false;
816 }
817
818 /**
819 * bnx2x_read_pages_regs - read "paged" registers
820 *
821 * @bp device handle
822 * @p output buffer
823 *
824 * Reads "paged" memories: memories that may only be read by first writing to a
825 * specific address ("write address") and then reading from a specific address
826 * ("read address"). There may be more than one write address per "page" and
827 * more than one read address per write address.
828 */
829 static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p, u32 preset)
830 {
831 u32 i, j, k, n;
832
833 /* addresses of the paged registers */
834 const u32 *page_addr = __bnx2x_get_page_addr_ar(bp);
835 /* number of paged registers */
836 int num_pages = __bnx2x_get_page_reg_num(bp);
837 /* write addresses */
838 const u32 *write_addr = __bnx2x_get_page_write_ar(bp);
839 /* number of write addresses */
840 int write_num = __bnx2x_get_page_write_num(bp);
841 /* read addresses info */
842 const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
843 /* number of read addresses */
844 int read_num = __bnx2x_get_page_read_num(bp);
845 u32 addr, size;
846
847 for (i = 0; i < num_pages; i++) {
848 for (j = 0; j < write_num; j++) {
849 REG_WR(bp, write_addr[j], page_addr[i]);
850
851 for (k = 0; k < read_num; k++) {
852 if (IS_REG_IN_PRESET(read_addr[k].presets,
853 preset)) {
854 size = read_addr[k].size;
855 for (n = 0; n < size; n++) {
856 addr = read_addr[k].addr + n*4;
857 *p++ = REG_RD(bp, addr);
858 }
859 }
860 }
861 }
862 }
863 }
864
865 static int __bnx2x_get_preset_regs(struct bnx2x *bp, u32 *p, u32 preset)
866 {
867 u32 i, j, addr;
868 const struct wreg_addr *wreg_addr_p = NULL;
869
870 if (CHIP_IS_E1(bp))
871 wreg_addr_p = &wreg_addr_e1;
872 else if (CHIP_IS_E1H(bp))
873 wreg_addr_p = &wreg_addr_e1h;
874 else if (CHIP_IS_E2(bp))
875 wreg_addr_p = &wreg_addr_e2;
876 else if (CHIP_IS_E3A0(bp))
877 wreg_addr_p = &wreg_addr_e3;
878 else if (CHIP_IS_E3B0(bp))
879 wreg_addr_p = &wreg_addr_e3b0;
880
881 /* Read the idle_chk registers */
882 for (i = 0; i < IDLE_REGS_COUNT; i++) {
883 if (bnx2x_is_reg_in_chip(bp, &idle_reg_addrs[i]) &&
884 IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) {
885 for (j = 0; j < idle_reg_addrs[i].size; j++)
886 *p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4);
887 }
888 }
889
890 /* Read the regular registers */
891 for (i = 0; i < REGS_COUNT; i++) {
892 if (bnx2x_is_reg_in_chip(bp, &reg_addrs[i]) &&
893 IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) {
894 for (j = 0; j < reg_addrs[i].size; j++)
895 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
896 }
897 }
898
899 /* Read the CAM registers */
900 if (bnx2x_is_wreg_in_chip(bp, wreg_addr_p) &&
901 IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) {
902 for (i = 0; i < wreg_addr_p->size; i++) {
903 *p++ = REG_RD(bp, wreg_addr_p->addr + i*4);
904
905 /* In case of wreg_addr register, read additional
906 registers from read_regs array
907 */
908 for (j = 0; j < wreg_addr_p->read_regs_count; j++) {
909 addr = *(wreg_addr_p->read_regs);
910 *p++ = REG_RD(bp, addr + j*4);
911 }
912 }
913 }
914
915 /* Paged registers are supported in E2 & E3 only */
916 if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) {
917 /* Read "paged" registers */
918 bnx2x_read_pages_regs(bp, p, preset);
919 }
920
921 return 0;
922 }
923
924 static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
925 {
926 u32 preset_idx;
927
928 /* Read all registers, by reading all preset registers */
929 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) {
930 /* Skip presets with IOR */
931 if ((preset_idx == 2) ||
932 (preset_idx == 5) ||
933 (preset_idx == 8) ||
934 (preset_idx == 11))
935 continue;
936 __bnx2x_get_preset_regs(bp, p, preset_idx);
937 p += __bnx2x_get_preset_regs_len(bp, preset_idx);
938 }
939 }
940
941 static void bnx2x_get_regs(struct net_device *dev,
942 struct ethtool_regs *regs, void *_p)
943 {
944 u32 *p = _p;
945 struct bnx2x *bp = netdev_priv(dev);
946 struct dump_header dump_hdr = {0};
947
948 regs->version = 2;
949 memset(p, 0, regs->len);
950
951 if (!netif_running(bp->dev))
952 return;
953
954 /* Disable parity attentions as long as following dump may
955 * cause false alarms by reading never written registers. We
956 * will re-enable parity attentions right after the dump.
957 */
958
959 bnx2x_disable_blocks_parity(bp);
960
961 dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
962 dump_hdr.preset = DUMP_ALL_PRESETS;
963 dump_hdr.version = BNX2X_DUMP_VERSION;
964
965 /* dump_meta_data presents OR of CHIP and PATH. */
966 if (CHIP_IS_E1(bp)) {
967 dump_hdr.dump_meta_data = DUMP_CHIP_E1;
968 } else if (CHIP_IS_E1H(bp)) {
969 dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
970 } else if (CHIP_IS_E2(bp)) {
971 dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
972 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
973 } else if (CHIP_IS_E3A0(bp)) {
974 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
975 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
976 } else if (CHIP_IS_E3B0(bp)) {
977 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
978 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
979 }
980
981 memcpy(p, &dump_hdr, sizeof(struct dump_header));
982 p += dump_hdr.header_size + 1;
983
984 /* Actually read the registers */
985 __bnx2x_get_regs(bp, p);
986
987 /* Re-enable parity attentions */
988 bnx2x_clear_blocks_parity(bp);
989 bnx2x_enable_blocks_parity(bp);
990 }
991
992 static int bnx2x_get_preset_regs_len(struct net_device *dev, u32 preset)
993 {
994 struct bnx2x *bp = netdev_priv(dev);
995 int regdump_len = 0;
996
997 regdump_len = __bnx2x_get_preset_regs_len(bp, preset);
998 regdump_len *= 4;
999 regdump_len += sizeof(struct dump_header);
1000
1001 return regdump_len;
1002 }
1003
1004 static int bnx2x_set_dump(struct net_device *dev, struct ethtool_dump *val)
1005 {
1006 struct bnx2x *bp = netdev_priv(dev);
1007
1008 /* Use the ethtool_dump "flag" field as the dump preset index */
1009 if (val->flag < 1 || val->flag > DUMP_MAX_PRESETS)
1010 return -EINVAL;
1011
1012 bp->dump_preset_idx = val->flag;
1013 return 0;
1014 }
1015
1016 static int bnx2x_get_dump_flag(struct net_device *dev,
1017 struct ethtool_dump *dump)
1018 {
1019 struct bnx2x *bp = netdev_priv(dev);
1020
1021 dump->version = BNX2X_DUMP_VERSION;
1022 dump->flag = bp->dump_preset_idx;
1023 /* Calculate the requested preset idx length */
1024 dump->len = bnx2x_get_preset_regs_len(dev, bp->dump_preset_idx);
1025 DP(BNX2X_MSG_ETHTOOL, "Get dump preset %d length=%d\n",
1026 bp->dump_preset_idx, dump->len);
1027 return 0;
1028 }
1029
1030 static int bnx2x_get_dump_data(struct net_device *dev,
1031 struct ethtool_dump *dump,
1032 void *buffer)
1033 {
1034 u32 *p = buffer;
1035 struct bnx2x *bp = netdev_priv(dev);
1036 struct dump_header dump_hdr = {0};
1037
1038 /* Disable parity attentions as long as following dump may
1039 * cause false alarms by reading never written registers. We
1040 * will re-enable parity attentions right after the dump.
1041 */
1042
1043 bnx2x_disable_blocks_parity(bp);
1044
1045 dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
1046 dump_hdr.preset = bp->dump_preset_idx;
1047 dump_hdr.version = BNX2X_DUMP_VERSION;
1048
1049 DP(BNX2X_MSG_ETHTOOL, "Get dump data of preset %d\n", dump_hdr.preset);
1050
1051 /* dump_meta_data presents OR of CHIP and PATH. */
1052 if (CHIP_IS_E1(bp)) {
1053 dump_hdr.dump_meta_data = DUMP_CHIP_E1;
1054 } else if (CHIP_IS_E1H(bp)) {
1055 dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
1056 } else if (CHIP_IS_E2(bp)) {
1057 dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
1058 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1059 } else if (CHIP_IS_E3A0(bp)) {
1060 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
1061 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1062 } else if (CHIP_IS_E3B0(bp)) {
1063 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
1064 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1065 }
1066
1067 memcpy(p, &dump_hdr, sizeof(struct dump_header));
1068 p += dump_hdr.header_size + 1;
1069
1070 /* Actually read the registers */
1071 __bnx2x_get_preset_regs(bp, p, dump_hdr.preset);
1072
1073 /* Re-enable parity attentions */
1074 bnx2x_clear_blocks_parity(bp);
1075 bnx2x_enable_blocks_parity(bp);
1076
1077 return 0;
1078 }
1079
1080 static void bnx2x_get_drvinfo(struct net_device *dev,
1081 struct ethtool_drvinfo *info)
1082 {
1083 struct bnx2x *bp = netdev_priv(dev);
1084
1085 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1086 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
1087
1088 bnx2x_fill_fw_str(bp, info->fw_version, sizeof(info->fw_version));
1089
1090 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
1091 info->n_stats = BNX2X_NUM_STATS;
1092 info->testinfo_len = BNX2X_NUM_TESTS(bp);
1093 info->eedump_len = bp->common.flash_size;
1094 info->regdump_len = bnx2x_get_regs_len(dev);
1095 }
1096
1097 static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1098 {
1099 struct bnx2x *bp = netdev_priv(dev);
1100
1101 if (bp->flags & NO_WOL_FLAG) {
1102 wol->supported = 0;
1103 wol->wolopts = 0;
1104 } else {
1105 wol->supported = WAKE_MAGIC;
1106 if (bp->wol)
1107 wol->wolopts = WAKE_MAGIC;
1108 else
1109 wol->wolopts = 0;
1110 }
1111 memset(&wol->sopass, 0, sizeof(wol->sopass));
1112 }
1113
1114 static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1115 {
1116 struct bnx2x *bp = netdev_priv(dev);
1117
1118 if (wol->wolopts & ~WAKE_MAGIC) {
1119 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
1120 return -EINVAL;
1121 }
1122
1123 if (wol->wolopts & WAKE_MAGIC) {
1124 if (bp->flags & NO_WOL_FLAG) {
1125 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
1126 return -EINVAL;
1127 }
1128 bp->wol = 1;
1129 } else
1130 bp->wol = 0;
1131
1132 return 0;
1133 }
1134
1135 static u32 bnx2x_get_msglevel(struct net_device *dev)
1136 {
1137 struct bnx2x *bp = netdev_priv(dev);
1138
1139 return bp->msg_enable;
1140 }
1141
1142 static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
1143 {
1144 struct bnx2x *bp = netdev_priv(dev);
1145
1146 if (capable(CAP_NET_ADMIN)) {
1147 /* dump MCP trace */
1148 if (IS_PF(bp) && (level & BNX2X_MSG_MCP))
1149 bnx2x_fw_dump_lvl(bp, KERN_INFO);
1150 bp->msg_enable = level;
1151 }
1152 }
1153
1154 static int bnx2x_nway_reset(struct net_device *dev)
1155 {
1156 struct bnx2x *bp = netdev_priv(dev);
1157
1158 if (!bp->port.pmf)
1159 return 0;
1160
1161 if (netif_running(dev)) {
1162 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1163 bnx2x_force_link_reset(bp);
1164 bnx2x_link_set(bp);
1165 }
1166
1167 return 0;
1168 }
1169
1170 static u32 bnx2x_get_link(struct net_device *dev)
1171 {
1172 struct bnx2x *bp = netdev_priv(dev);
1173
1174 if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
1175 return 0;
1176
1177 if (IS_VF(bp))
1178 return !test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1179 &bp->vf_link_vars.link_report_flags);
1180
1181 return bp->link_vars.link_up;
1182 }
1183
1184 static int bnx2x_get_eeprom_len(struct net_device *dev)
1185 {
1186 struct bnx2x *bp = netdev_priv(dev);
1187
1188 return bp->common.flash_size;
1189 }
1190
1191 /* Per pf misc lock must be acquired before the per port mcp lock. Otherwise,
1192 * had we done things the other way around, if two pfs from the same port would
1193 * attempt to access nvram at the same time, we could run into a scenario such
1194 * as:
1195 * pf A takes the port lock.
1196 * pf B succeeds in taking the same lock since they are from the same port.
1197 * pf A takes the per pf misc lock. Performs eeprom access.
1198 * pf A finishes. Unlocks the per pf misc lock.
1199 * Pf B takes the lock and proceeds to perform it's own access.
1200 * pf A unlocks the per port lock, while pf B is still working (!).
1201 * mcp takes the per port lock and corrupts pf B's access (and/or has it's own
1202 * access corrupted by pf B)
1203 */
1204 static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
1205 {
1206 int port = BP_PORT(bp);
1207 int count, i;
1208 u32 val;
1209
1210 /* acquire HW lock: protect against other PFs in PF Direct Assignment */
1211 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1212
1213 /* adjust timeout for emulation/FPGA */
1214 count = BNX2X_NVRAM_TIMEOUT_COUNT;
1215 if (CHIP_REV_IS_SLOW(bp))
1216 count *= 100;
1217
1218 /* request access to nvram interface */
1219 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1220 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
1221
1222 for (i = 0; i < count*10; i++) {
1223 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1224 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
1225 break;
1226
1227 udelay(5);
1228 }
1229
1230 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
1231 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1232 "cannot get access to nvram interface\n");
1233 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1234 return -EBUSY;
1235 }
1236
1237 return 0;
1238 }
1239
1240 static int bnx2x_release_nvram_lock(struct bnx2x *bp)
1241 {
1242 int port = BP_PORT(bp);
1243 int count, i;
1244 u32 val;
1245
1246 /* adjust timeout for emulation/FPGA */
1247 count = BNX2X_NVRAM_TIMEOUT_COUNT;
1248 if (CHIP_REV_IS_SLOW(bp))
1249 count *= 100;
1250
1251 /* relinquish nvram interface */
1252 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1253 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
1254
1255 for (i = 0; i < count*10; i++) {
1256 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1257 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
1258 break;
1259
1260 udelay(5);
1261 }
1262
1263 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
1264 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1265 "cannot free access to nvram interface\n");
1266 return -EBUSY;
1267 }
1268
1269 /* release HW lock: protect against other PFs in PF Direct Assignment */
1270 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1271 return 0;
1272 }
1273
1274 static void bnx2x_enable_nvram_access(struct bnx2x *bp)
1275 {
1276 u32 val;
1277
1278 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1279
1280 /* enable both bits, even on read */
1281 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1282 (val | MCPR_NVM_ACCESS_ENABLE_EN |
1283 MCPR_NVM_ACCESS_ENABLE_WR_EN));
1284 }
1285
1286 static void bnx2x_disable_nvram_access(struct bnx2x *bp)
1287 {
1288 u32 val;
1289
1290 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1291
1292 /* disable both bits, even after read */
1293 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1294 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
1295 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
1296 }
1297
1298 static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
1299 u32 cmd_flags)
1300 {
1301 int count, i, rc;
1302 u32 val;
1303
1304 /* build the command word */
1305 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
1306
1307 /* need to clear DONE bit separately */
1308 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1309
1310 /* address of the NVRAM to read from */
1311 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1312 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1313
1314 /* issue a read command */
1315 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1316
1317 /* adjust timeout for emulation/FPGA */
1318 count = BNX2X_NVRAM_TIMEOUT_COUNT;
1319 if (CHIP_REV_IS_SLOW(bp))
1320 count *= 100;
1321
1322 /* wait for completion */
1323 *ret_val = 0;
1324 rc = -EBUSY;
1325 for (i = 0; i < count; i++) {
1326 udelay(5);
1327 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1328
1329 if (val & MCPR_NVM_COMMAND_DONE) {
1330 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
1331 /* we read nvram data in cpu order
1332 * but ethtool sees it as an array of bytes
1333 * converting to big-endian will do the work
1334 */
1335 *ret_val = cpu_to_be32(val);
1336 rc = 0;
1337 break;
1338 }
1339 }
1340 if (rc == -EBUSY)
1341 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1342 "nvram read timeout expired\n");
1343 return rc;
1344 }
1345
1346 static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
1347 int buf_size)
1348 {
1349 int rc;
1350 u32 cmd_flags;
1351 __be32 val;
1352
1353 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1354 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1355 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1356 offset, buf_size);
1357 return -EINVAL;
1358 }
1359
1360 if (offset + buf_size > bp->common.flash_size) {
1361 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1362 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1363 offset, buf_size, bp->common.flash_size);
1364 return -EINVAL;
1365 }
1366
1367 /* request access to nvram interface */
1368 rc = bnx2x_acquire_nvram_lock(bp);
1369 if (rc)
1370 return rc;
1371
1372 /* enable access to nvram interface */
1373 bnx2x_enable_nvram_access(bp);
1374
1375 /* read the first word(s) */
1376 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1377 while ((buf_size > sizeof(u32)) && (rc == 0)) {
1378 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1379 memcpy(ret_buf, &val, 4);
1380
1381 /* advance to the next dword */
1382 offset += sizeof(u32);
1383 ret_buf += sizeof(u32);
1384 buf_size -= sizeof(u32);
1385 cmd_flags = 0;
1386 }
1387
1388 if (rc == 0) {
1389 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1390 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1391 memcpy(ret_buf, &val, 4);
1392 }
1393
1394 /* disable access to nvram interface */
1395 bnx2x_disable_nvram_access(bp);
1396 bnx2x_release_nvram_lock(bp);
1397
1398 return rc;
1399 }
1400
1401 static int bnx2x_nvram_read32(struct bnx2x *bp, u32 offset, u32 *buf,
1402 int buf_size)
1403 {
1404 int rc;
1405
1406 rc = bnx2x_nvram_read(bp, offset, (u8 *)buf, buf_size);
1407
1408 if (!rc) {
1409 __be32 *be = (__be32 *)buf;
1410
1411 while ((buf_size -= 4) >= 0)
1412 *buf++ = be32_to_cpu(*be++);
1413 }
1414
1415 return rc;
1416 }
1417
1418 static bool bnx2x_is_nvm_accessible(struct bnx2x *bp)
1419 {
1420 int rc = 1;
1421 u16 pm = 0;
1422 struct net_device *dev = pci_get_drvdata(bp->pdev);
1423
1424 if (bp->pdev->pm_cap)
1425 rc = pci_read_config_word(bp->pdev,
1426 bp->pdev->pm_cap + PCI_PM_CTRL, &pm);
1427
1428 if ((rc && !netif_running(dev)) ||
1429 (!rc && ((pm & PCI_PM_CTRL_STATE_MASK) != (__force u16)PCI_D0)))
1430 return false;
1431
1432 return true;
1433 }
1434
1435 static int bnx2x_get_eeprom(struct net_device *dev,
1436 struct ethtool_eeprom *eeprom, u8 *eebuf)
1437 {
1438 struct bnx2x *bp = netdev_priv(dev);
1439
1440 if (!bnx2x_is_nvm_accessible(bp)) {
1441 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1442 "cannot access eeprom when the interface is down\n");
1443 return -EAGAIN;
1444 }
1445
1446 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1447 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
1448 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1449 eeprom->len, eeprom->len);
1450
1451 /* parameters already validated in ethtool_get_eeprom */
1452
1453 return bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
1454 }
1455
1456 static int bnx2x_get_module_eeprom(struct net_device *dev,
1457 struct ethtool_eeprom *ee,
1458 u8 *data)
1459 {
1460 struct bnx2x *bp = netdev_priv(dev);
1461 int rc = -EINVAL, phy_idx;
1462 u8 *user_data = data;
1463 unsigned int start_addr = ee->offset, xfer_size = 0;
1464
1465 if (!bnx2x_is_nvm_accessible(bp)) {
1466 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1467 "cannot access eeprom when the interface is down\n");
1468 return -EAGAIN;
1469 }
1470
1471 phy_idx = bnx2x_get_cur_phy_idx(bp);
1472
1473 /* Read A0 section */
1474 if (start_addr < ETH_MODULE_SFF_8079_LEN) {
1475 /* Limit transfer size to the A0 section boundary */
1476 if (start_addr + ee->len > ETH_MODULE_SFF_8079_LEN)
1477 xfer_size = ETH_MODULE_SFF_8079_LEN - start_addr;
1478 else
1479 xfer_size = ee->len;
1480 bnx2x_acquire_phy_lock(bp);
1481 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1482 &bp->link_params,
1483 I2C_DEV_ADDR_A0,
1484 start_addr,
1485 xfer_size,
1486 user_data);
1487 bnx2x_release_phy_lock(bp);
1488 if (rc) {
1489 DP(BNX2X_MSG_ETHTOOL, "Failed reading A0 section\n");
1490
1491 return -EINVAL;
1492 }
1493 user_data += xfer_size;
1494 start_addr += xfer_size;
1495 }
1496
1497 /* Read A2 section */
1498 if ((start_addr >= ETH_MODULE_SFF_8079_LEN) &&
1499 (start_addr < ETH_MODULE_SFF_8472_LEN)) {
1500 xfer_size = ee->len - xfer_size;
1501 /* Limit transfer size to the A2 section boundary */
1502 if (start_addr + xfer_size > ETH_MODULE_SFF_8472_LEN)
1503 xfer_size = ETH_MODULE_SFF_8472_LEN - start_addr;
1504 start_addr -= ETH_MODULE_SFF_8079_LEN;
1505 bnx2x_acquire_phy_lock(bp);
1506 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1507 &bp->link_params,
1508 I2C_DEV_ADDR_A2,
1509 start_addr,
1510 xfer_size,
1511 user_data);
1512 bnx2x_release_phy_lock(bp);
1513 if (rc) {
1514 DP(BNX2X_MSG_ETHTOOL, "Failed reading A2 section\n");
1515 return -EINVAL;
1516 }
1517 }
1518 return rc;
1519 }
1520
1521 static int bnx2x_get_module_info(struct net_device *dev,
1522 struct ethtool_modinfo *modinfo)
1523 {
1524 struct bnx2x *bp = netdev_priv(dev);
1525 int phy_idx, rc;
1526 u8 sff8472_comp, diag_type;
1527
1528 if (!bnx2x_is_nvm_accessible(bp)) {
1529 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1530 "cannot access eeprom when the interface is down\n");
1531 return -EAGAIN;
1532 }
1533 phy_idx = bnx2x_get_cur_phy_idx(bp);
1534 bnx2x_acquire_phy_lock(bp);
1535 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1536 &bp->link_params,
1537 I2C_DEV_ADDR_A0,
1538 SFP_EEPROM_SFF_8472_COMP_ADDR,
1539 SFP_EEPROM_SFF_8472_COMP_SIZE,
1540 &sff8472_comp);
1541 bnx2x_release_phy_lock(bp);
1542 if (rc) {
1543 DP(BNX2X_MSG_ETHTOOL, "Failed reading SFF-8472 comp field\n");
1544 return -EINVAL;
1545 }
1546
1547 bnx2x_acquire_phy_lock(bp);
1548 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1549 &bp->link_params,
1550 I2C_DEV_ADDR_A0,
1551 SFP_EEPROM_DIAG_TYPE_ADDR,
1552 SFP_EEPROM_DIAG_TYPE_SIZE,
1553 &diag_type);
1554 bnx2x_release_phy_lock(bp);
1555 if (rc) {
1556 DP(BNX2X_MSG_ETHTOOL, "Failed reading Diag Type field\n");
1557 return -EINVAL;
1558 }
1559
1560 if (!sff8472_comp ||
1561 (diag_type & SFP_EEPROM_DIAG_ADDR_CHANGE_REQ)) {
1562 modinfo->type = ETH_MODULE_SFF_8079;
1563 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
1564 } else {
1565 modinfo->type = ETH_MODULE_SFF_8472;
1566 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1567 }
1568 return 0;
1569 }
1570
1571 static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
1572 u32 cmd_flags)
1573 {
1574 int count, i, rc;
1575
1576 /* build the command word */
1577 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
1578
1579 /* need to clear DONE bit separately */
1580 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1581
1582 /* write the data */
1583 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
1584
1585 /* address of the NVRAM to write to */
1586 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1587 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1588
1589 /* issue the write command */
1590 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1591
1592 /* adjust timeout for emulation/FPGA */
1593 count = BNX2X_NVRAM_TIMEOUT_COUNT;
1594 if (CHIP_REV_IS_SLOW(bp))
1595 count *= 100;
1596
1597 /* wait for completion */
1598 rc = -EBUSY;
1599 for (i = 0; i < count; i++) {
1600 udelay(5);
1601 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1602 if (val & MCPR_NVM_COMMAND_DONE) {
1603 rc = 0;
1604 break;
1605 }
1606 }
1607
1608 if (rc == -EBUSY)
1609 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1610 "nvram write timeout expired\n");
1611 return rc;
1612 }
1613
1614 #define BYTE_OFFSET(offset) (8 * (offset & 0x03))
1615
1616 static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
1617 int buf_size)
1618 {
1619 int rc;
1620 u32 cmd_flags, align_offset, val;
1621 __be32 val_be;
1622
1623 if (offset + buf_size > bp->common.flash_size) {
1624 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1625 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1626 offset, buf_size, bp->common.flash_size);
1627 return -EINVAL;
1628 }
1629
1630 /* request access to nvram interface */
1631 rc = bnx2x_acquire_nvram_lock(bp);
1632 if (rc)
1633 return rc;
1634
1635 /* enable access to nvram interface */
1636 bnx2x_enable_nvram_access(bp);
1637
1638 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1639 align_offset = (offset & ~0x03);
1640 rc = bnx2x_nvram_read_dword(bp, align_offset, &val_be, cmd_flags);
1641
1642 if (rc == 0) {
1643 /* nvram data is returned as an array of bytes
1644 * convert it back to cpu order
1645 */
1646 val = be32_to_cpu(val_be);
1647
1648 val &= ~le32_to_cpu((__force __le32)
1649 (0xff << BYTE_OFFSET(offset)));
1650 val |= le32_to_cpu((__force __le32)
1651 (*data_buf << BYTE_OFFSET(offset)));
1652
1653 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1654 cmd_flags);
1655 }
1656
1657 /* disable access to nvram interface */
1658 bnx2x_disable_nvram_access(bp);
1659 bnx2x_release_nvram_lock(bp);
1660
1661 return rc;
1662 }
1663
1664 static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1665 int buf_size)
1666 {
1667 int rc;
1668 u32 cmd_flags;
1669 u32 val;
1670 u32 written_so_far;
1671
1672 if (buf_size == 1) /* ethtool */
1673 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1674
1675 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1676 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1677 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1678 offset, buf_size);
1679 return -EINVAL;
1680 }
1681
1682 if (offset + buf_size > bp->common.flash_size) {
1683 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1684 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1685 offset, buf_size, bp->common.flash_size);
1686 return -EINVAL;
1687 }
1688
1689 /* request access to nvram interface */
1690 rc = bnx2x_acquire_nvram_lock(bp);
1691 if (rc)
1692 return rc;
1693
1694 /* enable access to nvram interface */
1695 bnx2x_enable_nvram_access(bp);
1696
1697 written_so_far = 0;
1698 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1699 while ((written_so_far < buf_size) && (rc == 0)) {
1700 if (written_so_far == (buf_size - sizeof(u32)))
1701 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1702 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
1703 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1704 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
1705 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1706
1707 memcpy(&val, data_buf, 4);
1708
1709 /* Notice unlike bnx2x_nvram_read_dword() this will not
1710 * change val using be32_to_cpu(), which causes data to flip
1711 * if the eeprom is read and then written back. This is due
1712 * to tools utilizing this functionality that would break
1713 * if this would be resolved.
1714 */
1715 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1716
1717 /* advance to the next dword */
1718 offset += sizeof(u32);
1719 data_buf += sizeof(u32);
1720 written_so_far += sizeof(u32);
1721 cmd_flags = 0;
1722 }
1723
1724 /* disable access to nvram interface */
1725 bnx2x_disable_nvram_access(bp);
1726 bnx2x_release_nvram_lock(bp);
1727
1728 return rc;
1729 }
1730
1731 static int bnx2x_set_eeprom(struct net_device *dev,
1732 struct ethtool_eeprom *eeprom, u8 *eebuf)
1733 {
1734 struct bnx2x *bp = netdev_priv(dev);
1735 int port = BP_PORT(bp);
1736 int rc = 0;
1737 u32 ext_phy_config;
1738
1739 if (!bnx2x_is_nvm_accessible(bp)) {
1740 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1741 "cannot access eeprom when the interface is down\n");
1742 return -EAGAIN;
1743 }
1744
1745 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1746 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
1747 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1748 eeprom->len, eeprom->len);
1749
1750 /* parameters already validated in ethtool_set_eeprom */
1751
1752 /* PHY eeprom can be accessed only by the PMF */
1753 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
1754 !bp->port.pmf) {
1755 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1756 "wrong magic or interface is not pmf\n");
1757 return -EINVAL;
1758 }
1759
1760 ext_phy_config =
1761 SHMEM_RD(bp,
1762 dev_info.port_hw_config[port].external_phy_config);
1763
1764 if (eeprom->magic == 0x50485950) {
1765 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1766 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1767
1768 bnx2x_acquire_phy_lock(bp);
1769 rc |= bnx2x_link_reset(&bp->link_params,
1770 &bp->link_vars, 0);
1771 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1772 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1773 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1774 MISC_REGISTERS_GPIO_HIGH, port);
1775 bnx2x_release_phy_lock(bp);
1776 bnx2x_link_report(bp);
1777
1778 } else if (eeprom->magic == 0x50485952) {
1779 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1780 if (bp->state == BNX2X_STATE_OPEN) {
1781 bnx2x_acquire_phy_lock(bp);
1782 rc |= bnx2x_link_reset(&bp->link_params,
1783 &bp->link_vars, 1);
1784
1785 rc |= bnx2x_phy_init(&bp->link_params,
1786 &bp->link_vars);
1787 bnx2x_release_phy_lock(bp);
1788 bnx2x_calc_fc_adv(bp);
1789 }
1790 } else if (eeprom->magic == 0x53985943) {
1791 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
1792 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1793 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
1794
1795 /* DSP Remove Download Mode */
1796 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1797 MISC_REGISTERS_GPIO_LOW, port);
1798
1799 bnx2x_acquire_phy_lock(bp);
1800
1801 bnx2x_sfx7101_sp_sw_reset(bp,
1802 &bp->link_params.phy[EXT_PHY1]);
1803
1804 /* wait 0.5 sec to allow it to run */
1805 msleep(500);
1806 bnx2x_ext_phy_hw_reset(bp, port);
1807 msleep(500);
1808 bnx2x_release_phy_lock(bp);
1809 }
1810 } else
1811 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1812
1813 return rc;
1814 }
1815
1816 static int bnx2x_get_coalesce(struct net_device *dev,
1817 struct ethtool_coalesce *coal)
1818 {
1819 struct bnx2x *bp = netdev_priv(dev);
1820
1821 memset(coal, 0, sizeof(struct ethtool_coalesce));
1822
1823 coal->rx_coalesce_usecs = bp->rx_ticks;
1824 coal->tx_coalesce_usecs = bp->tx_ticks;
1825
1826 return 0;
1827 }
1828
1829 static int bnx2x_set_coalesce(struct net_device *dev,
1830 struct ethtool_coalesce *coal)
1831 {
1832 struct bnx2x *bp = netdev_priv(dev);
1833
1834 bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1835 if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1836 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1837
1838 bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1839 if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1840 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1841
1842 if (netif_running(dev))
1843 bnx2x_update_coalesce(bp);
1844
1845 return 0;
1846 }
1847
1848 static void bnx2x_get_ringparam(struct net_device *dev,
1849 struct ethtool_ringparam *ering)
1850 {
1851 struct bnx2x *bp = netdev_priv(dev);
1852
1853 ering->rx_max_pending = MAX_RX_AVAIL;
1854
1855 if (bp->rx_ring_size)
1856 ering->rx_pending = bp->rx_ring_size;
1857 else
1858 ering->rx_pending = MAX_RX_AVAIL;
1859
1860 ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
1861 ering->tx_pending = bp->tx_ring_size;
1862 }
1863
1864 static int bnx2x_set_ringparam(struct net_device *dev,
1865 struct ethtool_ringparam *ering)
1866 {
1867 struct bnx2x *bp = netdev_priv(dev);
1868
1869 DP(BNX2X_MSG_ETHTOOL,
1870 "set ring params command parameters: rx_pending = %d, tx_pending = %d\n",
1871 ering->rx_pending, ering->tx_pending);
1872
1873 if (pci_num_vf(bp->pdev)) {
1874 DP(BNX2X_MSG_IOV,
1875 "VFs are enabled, can not change ring parameters\n");
1876 return -EPERM;
1877 }
1878
1879 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1880 DP(BNX2X_MSG_ETHTOOL,
1881 "Handling parity error recovery. Try again later\n");
1882 return -EAGAIN;
1883 }
1884
1885 if ((ering->rx_pending > MAX_RX_AVAIL) ||
1886 (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1887 MIN_RX_SIZE_TPA)) ||
1888 (ering->tx_pending > (IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL)) ||
1889 (ering->tx_pending <= MAX_SKB_FRAGS + 4)) {
1890 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
1891 return -EINVAL;
1892 }
1893
1894 bp->rx_ring_size = ering->rx_pending;
1895 bp->tx_ring_size = ering->tx_pending;
1896
1897 return bnx2x_reload_if_running(dev);
1898 }
1899
1900 static void bnx2x_get_pauseparam(struct net_device *dev,
1901 struct ethtool_pauseparam *epause)
1902 {
1903 struct bnx2x *bp = netdev_priv(dev);
1904 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1905 int cfg_reg;
1906
1907 epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1908 BNX2X_FLOW_CTRL_AUTO);
1909
1910 if (!epause->autoneg)
1911 cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx];
1912 else
1913 cfg_reg = bp->link_params.req_fc_auto_adv;
1914
1915 epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) ==
1916 BNX2X_FLOW_CTRL_RX);
1917 epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) ==
1918 BNX2X_FLOW_CTRL_TX);
1919
1920 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
1921 " autoneg %d rx_pause %d tx_pause %d\n",
1922 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1923 }
1924
1925 static int bnx2x_set_pauseparam(struct net_device *dev,
1926 struct ethtool_pauseparam *epause)
1927 {
1928 struct bnx2x *bp = netdev_priv(dev);
1929 u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
1930 if (IS_MF(bp))
1931 return 0;
1932
1933 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
1934 " autoneg %d rx_pause %d tx_pause %d\n",
1935 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1936
1937 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
1938
1939 if (epause->rx_pause)
1940 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
1941
1942 if (epause->tx_pause)
1943 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
1944
1945 if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1946 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
1947
1948 if (epause->autoneg) {
1949 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
1950 DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n");
1951 return -EINVAL;
1952 }
1953
1954 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1955 bp->link_params.req_flow_ctrl[cfg_idx] =
1956 BNX2X_FLOW_CTRL_AUTO;
1957 }
1958 bp->link_params.req_fc_auto_adv = 0;
1959 if (epause->rx_pause)
1960 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX;
1961
1962 if (epause->tx_pause)
1963 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX;
1964
1965 if (!bp->link_params.req_fc_auto_adv)
1966 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_NONE;
1967 }
1968
1969 DP(BNX2X_MSG_ETHTOOL,
1970 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
1971
1972 if (netif_running(dev)) {
1973 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1974 bnx2x_force_link_reset(bp);
1975 bnx2x_link_set(bp);
1976 }
1977
1978 return 0;
1979 }
1980
1981 static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = {
1982 "register_test (offline) ",
1983 "memory_test (offline) ",
1984 "int_loopback_test (offline)",
1985 "ext_loopback_test (offline)",
1986 "nvram_test (online) ",
1987 "interrupt_test (online) ",
1988 "link_test (online) "
1989 };
1990
1991 enum {
1992 BNX2X_PRI_FLAG_ISCSI,
1993 BNX2X_PRI_FLAG_FCOE,
1994 BNX2X_PRI_FLAG_STORAGE,
1995 BNX2X_PRI_FLAG_LEN,
1996 };
1997
1998 static const char bnx2x_private_arr[BNX2X_PRI_FLAG_LEN][ETH_GSTRING_LEN] = {
1999 "iSCSI offload support",
2000 "FCoE offload support",
2001 "Storage only interface"
2002 };
2003
2004 static u32 bnx2x_eee_to_adv(u32 eee_adv)
2005 {
2006 u32 modes = 0;
2007
2008 if (eee_adv & SHMEM_EEE_100M_ADV)
2009 modes |= ADVERTISED_100baseT_Full;
2010 if (eee_adv & SHMEM_EEE_1G_ADV)
2011 modes |= ADVERTISED_1000baseT_Full;
2012 if (eee_adv & SHMEM_EEE_10G_ADV)
2013 modes |= ADVERTISED_10000baseT_Full;
2014
2015 return modes;
2016 }
2017
2018 static u32 bnx2x_adv_to_eee(u32 modes, u32 shift)
2019 {
2020 u32 eee_adv = 0;
2021 if (modes & ADVERTISED_100baseT_Full)
2022 eee_adv |= SHMEM_EEE_100M_ADV;
2023 if (modes & ADVERTISED_1000baseT_Full)
2024 eee_adv |= SHMEM_EEE_1G_ADV;
2025 if (modes & ADVERTISED_10000baseT_Full)
2026 eee_adv |= SHMEM_EEE_10G_ADV;
2027
2028 return eee_adv << shift;
2029 }
2030
2031 static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata)
2032 {
2033 struct bnx2x *bp = netdev_priv(dev);
2034 u32 eee_cfg;
2035
2036 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
2037 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
2038 return -EOPNOTSUPP;
2039 }
2040
2041 eee_cfg = bp->link_vars.eee_status;
2042
2043 edata->supported =
2044 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >>
2045 SHMEM_EEE_SUPPORTED_SHIFT);
2046
2047 edata->advertised =
2048 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >>
2049 SHMEM_EEE_ADV_STATUS_SHIFT);
2050 edata->lp_advertised =
2051 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >>
2052 SHMEM_EEE_LP_ADV_STATUS_SHIFT);
2053
2054 /* SHMEM value is in 16u units --> Convert to 1u units. */
2055 edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4;
2056
2057 edata->eee_enabled = (eee_cfg & SHMEM_EEE_REQUESTED_BIT) ? 1 : 0;
2058 edata->eee_active = (eee_cfg & SHMEM_EEE_ACTIVE_BIT) ? 1 : 0;
2059 edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0;
2060
2061 return 0;
2062 }
2063
2064 static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata)
2065 {
2066 struct bnx2x *bp = netdev_priv(dev);
2067 u32 eee_cfg;
2068 u32 advertised;
2069
2070 if (IS_MF(bp))
2071 return 0;
2072
2073 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
2074 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
2075 return -EOPNOTSUPP;
2076 }
2077
2078 eee_cfg = bp->link_vars.eee_status;
2079
2080 if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) {
2081 DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n");
2082 return -EOPNOTSUPP;
2083 }
2084
2085 advertised = bnx2x_adv_to_eee(edata->advertised,
2086 SHMEM_EEE_ADV_STATUS_SHIFT);
2087 if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) {
2088 DP(BNX2X_MSG_ETHTOOL,
2089 "Direct manipulation of EEE advertisement is not supported\n");
2090 return -EINVAL;
2091 }
2092
2093 if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) {
2094 DP(BNX2X_MSG_ETHTOOL,
2095 "Maximal Tx Lpi timer supported is %x(u)\n",
2096 EEE_MODE_TIMER_MASK);
2097 return -EINVAL;
2098 }
2099 if (edata->tx_lpi_enabled &&
2100 (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) {
2101 DP(BNX2X_MSG_ETHTOOL,
2102 "Minimal Tx Lpi timer supported is %d(u)\n",
2103 EEE_MODE_NVRAM_AGGRESSIVE_TIME);
2104 return -EINVAL;
2105 }
2106
2107 /* All is well; Apply changes*/
2108 if (edata->eee_enabled)
2109 bp->link_params.eee_mode |= EEE_MODE_ADV_LPI;
2110 else
2111 bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI;
2112
2113 if (edata->tx_lpi_enabled)
2114 bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI;
2115 else
2116 bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI;
2117
2118 bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK;
2119 bp->link_params.eee_mode |= (edata->tx_lpi_timer &
2120 EEE_MODE_TIMER_MASK) |
2121 EEE_MODE_OVERRIDE_NVRAM |
2122 EEE_MODE_OUTPUT_TIME;
2123
2124 /* Restart link to propagate changes */
2125 if (netif_running(dev)) {
2126 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2127 bnx2x_force_link_reset(bp);
2128 bnx2x_link_set(bp);
2129 }
2130
2131 return 0;
2132 }
2133
2134 enum {
2135 BNX2X_CHIP_E1_OFST = 0,
2136 BNX2X_CHIP_E1H_OFST,
2137 BNX2X_CHIP_E2_OFST,
2138 BNX2X_CHIP_E3_OFST,
2139 BNX2X_CHIP_E3B0_OFST,
2140 BNX2X_CHIP_MAX_OFST
2141 };
2142
2143 #define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST)
2144 #define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST)
2145 #define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST)
2146 #define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST)
2147 #define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST)
2148
2149 #define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1)
2150 #define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
2151
2152 static int bnx2x_test_registers(struct bnx2x *bp)
2153 {
2154 int idx, i, rc = -ENODEV;
2155 u32 wr_val = 0, hw;
2156 int port = BP_PORT(bp);
2157 static const struct {
2158 u32 hw;
2159 u32 offset0;
2160 u32 offset1;
2161 u32 mask;
2162 } reg_tbl[] = {
2163 /* 0 */ { BNX2X_CHIP_MASK_ALL,
2164 BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
2165 { BNX2X_CHIP_MASK_ALL,
2166 DORQ_REG_DB_ADDR0, 4, 0xffffffff },
2167 { BNX2X_CHIP_MASK_E1X,
2168 HC_REG_AGG_INT_0, 4, 0x000003ff },
2169 { BNX2X_CHIP_MASK_ALL,
2170 PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 },
2171 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
2172 PBF_REG_P0_INIT_CRD, 4, 0x000007ff },
2173 { BNX2X_CHIP_MASK_E3B0,
2174 PBF_REG_INIT_CRD_Q0, 4, 0x000007ff },
2175 { BNX2X_CHIP_MASK_ALL,
2176 PRS_REG_CID_PORT_0, 4, 0x00ffffff },
2177 { BNX2X_CHIP_MASK_ALL,
2178 PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff },
2179 { BNX2X_CHIP_MASK_ALL,
2180 PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2181 { BNX2X_CHIP_MASK_ALL,
2182 PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff },
2183 /* 10 */ { BNX2X_CHIP_MASK_ALL,
2184 PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2185 { BNX2X_CHIP_MASK_ALL,
2186 PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff },
2187 { BNX2X_CHIP_MASK_ALL,
2188 QM_REG_CONNNUM_0, 4, 0x000fffff },
2189 { BNX2X_CHIP_MASK_ALL,
2190 TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff },
2191 { BNX2X_CHIP_MASK_ALL,
2192 SRC_REG_KEYRSS0_0, 40, 0xffffffff },
2193 { BNX2X_CHIP_MASK_ALL,
2194 SRC_REG_KEYRSS0_7, 40, 0xffffffff },
2195 { BNX2X_CHIP_MASK_ALL,
2196 XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
2197 { BNX2X_CHIP_MASK_ALL,
2198 XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 },
2199 { BNX2X_CHIP_MASK_ALL,
2200 XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff },
2201 { BNX2X_CHIP_MASK_ALL,
2202 NIG_REG_LLH0_T_BIT, 4, 0x00000001 },
2203 /* 20 */ { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2204 NIG_REG_EMAC0_IN_EN, 4, 0x00000001 },
2205 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2206 NIG_REG_BMAC0_IN_EN, 4, 0x00000001 },
2207 { BNX2X_CHIP_MASK_ALL,
2208 NIG_REG_XCM0_OUT_EN, 4, 0x00000001 },
2209 { BNX2X_CHIP_MASK_ALL,
2210 NIG_REG_BRB0_OUT_EN, 4, 0x00000001 },
2211 { BNX2X_CHIP_MASK_ALL,
2212 NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 },
2213 { BNX2X_CHIP_MASK_ALL,
2214 NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff },
2215 { BNX2X_CHIP_MASK_ALL,
2216 NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff },
2217 { BNX2X_CHIP_MASK_ALL,
2218 NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff },
2219 { BNX2X_CHIP_MASK_ALL,
2220 NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff },
2221 { BNX2X_CHIP_MASK_ALL,
2222 NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 },
2223 /* 30 */ { BNX2X_CHIP_MASK_ALL,
2224 NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff },
2225 { BNX2X_CHIP_MASK_ALL,
2226 NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff },
2227 { BNX2X_CHIP_MASK_ALL,
2228 NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
2229 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2230 NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 },
2231 { BNX2X_CHIP_MASK_ALL,
2232 NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
2233 { BNX2X_CHIP_MASK_ALL,
2234 NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
2235 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2236 NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
2237 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2238 NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f },
2239
2240 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
2241 };
2242
2243 if (!bnx2x_is_nvm_accessible(bp)) {
2244 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2245 "cannot access eeprom when the interface is down\n");
2246 return rc;
2247 }
2248
2249 if (CHIP_IS_E1(bp))
2250 hw = BNX2X_CHIP_MASK_E1;
2251 else if (CHIP_IS_E1H(bp))
2252 hw = BNX2X_CHIP_MASK_E1H;
2253 else if (CHIP_IS_E2(bp))
2254 hw = BNX2X_CHIP_MASK_E2;
2255 else if (CHIP_IS_E3B0(bp))
2256 hw = BNX2X_CHIP_MASK_E3B0;
2257 else /* e3 A0 */
2258 hw = BNX2X_CHIP_MASK_E3;
2259
2260 /* Repeat the test twice:
2261 * First by writing 0x00000000, second by writing 0xffffffff
2262 */
2263 for (idx = 0; idx < 2; idx++) {
2264
2265 switch (idx) {
2266 case 0:
2267 wr_val = 0;
2268 break;
2269 case 1:
2270 wr_val = 0xffffffff;
2271 break;
2272 }
2273
2274 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
2275 u32 offset, mask, save_val, val;
2276 if (!(hw & reg_tbl[i].hw))
2277 continue;
2278
2279 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
2280 mask = reg_tbl[i].mask;
2281
2282 save_val = REG_RD(bp, offset);
2283
2284 REG_WR(bp, offset, wr_val & mask);
2285
2286 val = REG_RD(bp, offset);
2287
2288 /* Restore the original register's value */
2289 REG_WR(bp, offset, save_val);
2290
2291 /* verify value is as expected */
2292 if ((val & mask) != (wr_val & mask)) {
2293 DP(BNX2X_MSG_ETHTOOL,
2294 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
2295 offset, val, wr_val, mask);
2296 goto test_reg_exit;
2297 }
2298 }
2299 }
2300
2301 rc = 0;
2302
2303 test_reg_exit:
2304 return rc;
2305 }
2306
2307 static int bnx2x_test_memory(struct bnx2x *bp)
2308 {
2309 int i, j, rc = -ENODEV;
2310 u32 val, index;
2311 static const struct {
2312 u32 offset;
2313 int size;
2314 } mem_tbl[] = {
2315 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE },
2316 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
2317 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE },
2318 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE },
2319 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE },
2320 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE },
2321 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE },
2322
2323 { 0xffffffff, 0 }
2324 };
2325
2326 static const struct {
2327 char *name;
2328 u32 offset;
2329 u32 hw_mask[BNX2X_CHIP_MAX_OFST];
2330 } prty_tbl[] = {
2331 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS,
2332 {0x3ffc0, 0, 0, 0} },
2333 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS,
2334 {0x2, 0x2, 0, 0} },
2335 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
2336 {0, 0, 0, 0} },
2337 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS,
2338 {0x3ffc0, 0, 0, 0} },
2339 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS,
2340 {0x3ffc0, 0, 0, 0} },
2341 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS,
2342 {0x3ffc1, 0, 0, 0} },
2343
2344 { NULL, 0xffffffff, {0, 0, 0, 0} }
2345 };
2346
2347 if (!bnx2x_is_nvm_accessible(bp)) {
2348 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2349 "cannot access eeprom when the interface is down\n");
2350 return rc;
2351 }
2352
2353 if (CHIP_IS_E1(bp))
2354 index = BNX2X_CHIP_E1_OFST;
2355 else if (CHIP_IS_E1H(bp))
2356 index = BNX2X_CHIP_E1H_OFST;
2357 else if (CHIP_IS_E2(bp))
2358 index = BNX2X_CHIP_E2_OFST;
2359 else /* e3 */
2360 index = BNX2X_CHIP_E3_OFST;
2361
2362 /* pre-Check the parity status */
2363 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2364 val = REG_RD(bp, prty_tbl[i].offset);
2365 if (val & ~(prty_tbl[i].hw_mask[index])) {
2366 DP(BNX2X_MSG_ETHTOOL,
2367 "%s is 0x%x\n", prty_tbl[i].name, val);
2368 goto test_mem_exit;
2369 }
2370 }
2371
2372 /* Go through all the memories */
2373 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
2374 for (j = 0; j < mem_tbl[i].size; j++)
2375 REG_RD(bp, mem_tbl[i].offset + j*4);
2376
2377 /* Check the parity status */
2378 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2379 val = REG_RD(bp, prty_tbl[i].offset);
2380 if (val & ~(prty_tbl[i].hw_mask[index])) {
2381 DP(BNX2X_MSG_ETHTOOL,
2382 "%s is 0x%x\n", prty_tbl[i].name, val);
2383 goto test_mem_exit;
2384 }
2385 }
2386
2387 rc = 0;
2388
2389 test_mem_exit:
2390 return rc;
2391 }
2392
2393 static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
2394 {
2395 int cnt = 1400;
2396
2397 if (link_up) {
2398 while (bnx2x_link_test(bp, is_serdes) && cnt--)
2399 msleep(20);
2400
2401 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
2402 DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n");
2403
2404 cnt = 1400;
2405 while (!bp->link_vars.link_up && cnt--)
2406 msleep(20);
2407
2408 if (cnt <= 0 && !bp->link_vars.link_up)
2409 DP(BNX2X_MSG_ETHTOOL,
2410 "Timeout waiting for link init\n");
2411 }
2412 }
2413
2414 static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
2415 {
2416 unsigned int pkt_size, num_pkts, i;
2417 struct sk_buff *skb;
2418 unsigned char *packet;
2419 struct bnx2x_fastpath *fp_rx = &bp->fp[0];
2420 struct bnx2x_fastpath *fp_tx = &bp->fp[0];
2421 struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0];
2422 u16 tx_start_idx, tx_idx;
2423 u16 rx_start_idx, rx_idx;
2424 u16 pkt_prod, bd_prod;
2425 struct sw_tx_bd *tx_buf;
2426 struct eth_tx_start_bd *tx_start_bd;
2427 dma_addr_t mapping;
2428 union eth_rx_cqe *cqe;
2429 u8 cqe_fp_flags, cqe_fp_type;
2430 struct sw_rx_bd *rx_buf;
2431 u16 len;
2432 int rc = -ENODEV;
2433 u8 *data;
2434 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev,
2435 txdata->txq_index);
2436
2437 /* check the loopback mode */
2438 switch (loopback_mode) {
2439 case BNX2X_PHY_LOOPBACK:
2440 if (bp->link_params.loopback_mode != LOOPBACK_XGXS) {
2441 DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n");
2442 return -EINVAL;
2443 }
2444 break;
2445 case BNX2X_MAC_LOOPBACK:
2446 if (CHIP_IS_E3(bp)) {
2447 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
2448 if (bp->port.supported[cfg_idx] &
2449 (SUPPORTED_10000baseT_Full |
2450 SUPPORTED_20000baseMLD2_Full |
2451 SUPPORTED_20000baseKR2_Full))
2452 bp->link_params.loopback_mode = LOOPBACK_XMAC;
2453 else
2454 bp->link_params.loopback_mode = LOOPBACK_UMAC;
2455 } else
2456 bp->link_params.loopback_mode = LOOPBACK_BMAC;
2457
2458 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2459 break;
2460 case BNX2X_EXT_LOOPBACK:
2461 if (bp->link_params.loopback_mode != LOOPBACK_EXT) {
2462 DP(BNX2X_MSG_ETHTOOL,
2463 "Can't configure external loopback\n");
2464 return -EINVAL;
2465 }
2466 break;
2467 default:
2468 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
2469 return -EINVAL;
2470 }
2471
2472 /* prepare the loopback packet */
2473 pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
2474 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
2475 skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
2476 if (!skb) {
2477 DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n");
2478 rc = -ENOMEM;
2479 goto test_loopback_exit;
2480 }
2481 packet = skb_put(skb, pkt_size);
2482 memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
2483 eth_zero_addr(packet + ETH_ALEN);
2484 memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
2485 for (i = ETH_HLEN; i < pkt_size; i++)
2486 packet[i] = (unsigned char) (i & 0xff);
2487 mapping = dma_map_single(&bp->pdev->dev, skb->data,
2488 skb_headlen(skb), DMA_TO_DEVICE);
2489 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
2490 rc = -ENOMEM;
2491 dev_kfree_skb(skb);
2492 DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n");
2493 goto test_loopback_exit;
2494 }
2495
2496 /* send the loopback packet */
2497 num_pkts = 0;
2498 tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
2499 rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2500
2501 netdev_tx_sent_queue(txq, skb->len);
2502
2503 pkt_prod = txdata->tx_pkt_prod++;
2504 tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
2505 tx_buf->first_bd = txdata->tx_bd_prod;
2506 tx_buf->skb = skb;
2507 tx_buf->flags = 0;
2508
2509 bd_prod = TX_BD(txdata->tx_bd_prod);
2510 tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
2511 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
2512 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
2513 tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
2514 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
2515 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
2516 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2517 SET_FLAG(tx_start_bd->general_data,
2518 ETH_TX_START_BD_HDR_NBDS,
2519 1);
2520 SET_FLAG(tx_start_bd->general_data,
2521 ETH_TX_START_BD_PARSE_NBDS,
2522 0);
2523
2524 /* turn on parsing and get a BD */
2525 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
2526
2527 if (CHIP_IS_E1x(bp)) {
2528 u16 global_data = 0;
2529 struct eth_tx_parse_bd_e1x *pbd_e1x =
2530 &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
2531 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
2532 SET_FLAG(global_data,
2533 ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2534 pbd_e1x->global_data = cpu_to_le16(global_data);
2535 } else {
2536 u32 parsing_data = 0;
2537 struct eth_tx_parse_bd_e2 *pbd_e2 =
2538 &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
2539 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
2540 SET_FLAG(parsing_data,
2541 ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2542 pbd_e2->parsing_data = cpu_to_le32(parsing_data);
2543 }
2544 wmb();
2545
2546 txdata->tx_db.data.prod += 2;
2547 barrier();
2548 DOORBELL(bp, txdata->cid, txdata->tx_db.raw);
2549
2550 mmiowb();
2551 barrier();
2552
2553 num_pkts++;
2554 txdata->tx_bd_prod += 2; /* start + pbd */
2555
2556 udelay(100);
2557
2558 tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
2559 if (tx_idx != tx_start_idx + num_pkts)
2560 goto test_loopback_exit;
2561
2562 /* Unlike HC IGU won't generate an interrupt for status block
2563 * updates that have been performed while interrupts were
2564 * disabled.
2565 */
2566 if (bp->common.int_block == INT_BLOCK_IGU) {
2567 /* Disable local BHes to prevent a dead-lock situation between
2568 * sch_direct_xmit() and bnx2x_run_loopback() (calling
2569 * bnx2x_tx_int()), as both are taking netif_tx_lock().
2570 */
2571 local_bh_disable();
2572 bnx2x_tx_int(bp, txdata);
2573 local_bh_enable();
2574 }
2575
2576 rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2577 if (rx_idx != rx_start_idx + num_pkts)
2578 goto test_loopback_exit;
2579
2580 cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
2581 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
2582 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
2583 if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
2584 goto test_loopback_rx_exit;
2585
2586 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len);
2587 if (len != pkt_size)
2588 goto test_loopback_rx_exit;
2589
2590 rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
2591 dma_sync_single_for_cpu(&bp->pdev->dev,
2592 dma_unmap_addr(rx_buf, mapping),
2593 fp_rx->rx_buf_size, DMA_FROM_DEVICE);
2594 data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset;
2595 for (i = ETH_HLEN; i < pkt_size; i++)
2596 if (*(data + i) != (unsigned char) (i & 0xff))
2597 goto test_loopback_rx_exit;
2598
2599 rc = 0;
2600
2601 test_loopback_rx_exit:
2602
2603 fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
2604 fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
2605 fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
2606 fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
2607
2608 /* Update producers */
2609 bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
2610 fp_rx->rx_sge_prod);
2611
2612 test_loopback_exit:
2613 bp->link_params.loopback_mode = LOOPBACK_NONE;
2614
2615 return rc;
2616 }
2617
2618 static int bnx2x_test_loopback(struct bnx2x *bp)
2619 {
2620 int rc = 0, res;
2621
2622 if (BP_NOMCP(bp))
2623 return rc;
2624
2625 if (!netif_running(bp->dev))
2626 return BNX2X_LOOPBACK_FAILED;
2627
2628 bnx2x_netif_stop(bp, 1);
2629 bnx2x_acquire_phy_lock(bp);
2630
2631 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
2632 if (res) {
2633 DP(BNX2X_MSG_ETHTOOL, " PHY loopback failed (res %d)\n", res);
2634 rc |= BNX2X_PHY_LOOPBACK_FAILED;
2635 }
2636
2637 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
2638 if (res) {
2639 DP(BNX2X_MSG_ETHTOOL, " MAC loopback failed (res %d)\n", res);
2640 rc |= BNX2X_MAC_LOOPBACK_FAILED;
2641 }
2642
2643 bnx2x_release_phy_lock(bp);
2644 bnx2x_netif_start(bp);
2645
2646 return rc;
2647 }
2648
2649 static int bnx2x_test_ext_loopback(struct bnx2x *bp)
2650 {
2651 int rc;
2652 u8 is_serdes =
2653 (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2654
2655 if (BP_NOMCP(bp))
2656 return -ENODEV;
2657
2658 if (!netif_running(bp->dev))
2659 return BNX2X_EXT_LOOPBACK_FAILED;
2660
2661 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
2662 rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT);
2663 if (rc) {
2664 DP(BNX2X_MSG_ETHTOOL,
2665 "Can't perform self-test, nic_load (for external lb) failed\n");
2666 return -ENODEV;
2667 }
2668 bnx2x_wait_for_link(bp, 1, is_serdes);
2669
2670 bnx2x_netif_stop(bp, 1);
2671
2672 rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK);
2673 if (rc)
2674 DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed (res %d)\n", rc);
2675
2676 bnx2x_netif_start(bp);
2677
2678 return rc;
2679 }
2680
2681 struct code_entry {
2682 u32 sram_start_addr;
2683 u32 code_attribute;
2684 #define CODE_IMAGE_TYPE_MASK 0xf0800003
2685 #define CODE_IMAGE_VNTAG_PROFILES_DATA 0xd0000003
2686 #define CODE_IMAGE_LENGTH_MASK 0x007ffffc
2687 #define CODE_IMAGE_TYPE_EXTENDED_DIR 0xe0000000
2688 u32 nvm_start_addr;
2689 };
2690
2691 #define CODE_ENTRY_MAX 16
2692 #define CODE_ENTRY_EXTENDED_DIR_IDX 15
2693 #define MAX_IMAGES_IN_EXTENDED_DIR 64
2694 #define NVRAM_DIR_OFFSET 0x14
2695
2696 #define EXTENDED_DIR_EXISTS(code) \
2697 ((code & CODE_IMAGE_TYPE_MASK) == CODE_IMAGE_TYPE_EXTENDED_DIR && \
2698 (code & CODE_IMAGE_LENGTH_MASK) != 0)
2699
2700 #define CRC32_RESIDUAL 0xdebb20e3
2701 #define CRC_BUFF_SIZE 256
2702
2703 static int bnx2x_nvram_crc(struct bnx2x *bp,
2704 int offset,
2705 int size,
2706 u8 *buff)
2707 {
2708 u32 crc = ~0;
2709 int rc = 0, done = 0;
2710
2711 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2712 "NVRAM CRC from 0x%08x to 0x%08x\n", offset, offset + size);
2713
2714 while (done < size) {
2715 int count = min_t(int, size - done, CRC_BUFF_SIZE);
2716
2717 rc = bnx2x_nvram_read(bp, offset + done, buff, count);
2718
2719 if (rc)
2720 return rc;
2721
2722 crc = crc32_le(crc, buff, count);
2723 done += count;
2724 }
2725
2726 if (crc != CRC32_RESIDUAL)
2727 rc = -EINVAL;
2728
2729 return rc;
2730 }
2731
2732 static int bnx2x_test_nvram_dir(struct bnx2x *bp,
2733 struct code_entry *entry,
2734 u8 *buff)
2735 {
2736 size_t size = entry->code_attribute & CODE_IMAGE_LENGTH_MASK;
2737 u32 type = entry->code_attribute & CODE_IMAGE_TYPE_MASK;
2738 int rc;
2739
2740 /* Zero-length images and AFEX profiles do not have CRC */
2741 if (size == 0 || type == CODE_IMAGE_VNTAG_PROFILES_DATA)
2742 return 0;
2743
2744 rc = bnx2x_nvram_crc(bp, entry->nvm_start_addr, size, buff);
2745 if (rc)
2746 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2747 "image %x has failed crc test (rc %d)\n", type, rc);
2748
2749 return rc;
2750 }
2751
2752 static int bnx2x_test_dir_entry(struct bnx2x *bp, u32 addr, u8 *buff)
2753 {
2754 int rc;
2755 struct code_entry entry;
2756
2757 rc = bnx2x_nvram_read32(bp, addr, (u32 *)&entry, sizeof(entry));
2758 if (rc)
2759 return rc;
2760
2761 return bnx2x_test_nvram_dir(bp, &entry, buff);
2762 }
2763
2764 static int bnx2x_test_nvram_ext_dirs(struct bnx2x *bp, u8 *buff)
2765 {
2766 u32 rc, cnt, dir_offset = NVRAM_DIR_OFFSET;
2767 struct code_entry entry;
2768 int i;
2769
2770 rc = bnx2x_nvram_read32(bp,
2771 dir_offset +
2772 sizeof(entry) * CODE_ENTRY_EXTENDED_DIR_IDX,
2773 (u32 *)&entry, sizeof(entry));
2774 if (rc)
2775 return rc;
2776
2777 if (!EXTENDED_DIR_EXISTS(entry.code_attribute))
2778 return 0;
2779
2780 rc = bnx2x_nvram_read32(bp, entry.nvm_start_addr,
2781 &cnt, sizeof(u32));
2782 if (rc)
2783 return rc;
2784
2785 dir_offset = entry.nvm_start_addr + 8;
2786
2787 for (i = 0; i < cnt && i < MAX_IMAGES_IN_EXTENDED_DIR; i++) {
2788 rc = bnx2x_test_dir_entry(bp, dir_offset +
2789 sizeof(struct code_entry) * i,
2790 buff);
2791 if (rc)
2792 return rc;
2793 }
2794
2795 return 0;
2796 }
2797
2798 static int bnx2x_test_nvram_dirs(struct bnx2x *bp, u8 *buff)
2799 {
2800 u32 rc, dir_offset = NVRAM_DIR_OFFSET;
2801 int i;
2802
2803 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "NVRAM DIRS CRC test-set\n");
2804
2805 for (i = 0; i < CODE_ENTRY_EXTENDED_DIR_IDX; i++) {
2806 rc = bnx2x_test_dir_entry(bp, dir_offset +
2807 sizeof(struct code_entry) * i,
2808 buff);
2809 if (rc)
2810 return rc;
2811 }
2812
2813 return bnx2x_test_nvram_ext_dirs(bp, buff);
2814 }
2815
2816 struct crc_pair {
2817 int offset;
2818 int size;
2819 };
2820
2821 static int bnx2x_test_nvram_tbl(struct bnx2x *bp,
2822 const struct crc_pair *nvram_tbl, u8 *buf)
2823 {
2824 int i;
2825
2826 for (i = 0; nvram_tbl[i].size; i++) {
2827 int rc = bnx2x_nvram_crc(bp, nvram_tbl[i].offset,
2828 nvram_tbl[i].size, buf);
2829 if (rc) {
2830 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2831 "nvram_tbl[%d] has failed crc test (rc %d)\n",
2832 i, rc);
2833 return rc;
2834 }
2835 }
2836
2837 return 0;
2838 }
2839
2840 static int bnx2x_test_nvram(struct bnx2x *bp)
2841 {
2842 const struct crc_pair nvram_tbl[] = {
2843 { 0, 0x14 }, /* bootstrap */
2844 { 0x14, 0xec }, /* dir */
2845 { 0x100, 0x350 }, /* manuf_info */
2846 { 0x450, 0xf0 }, /* feature_info */
2847 { 0x640, 0x64 }, /* upgrade_key_info */
2848 { 0x708, 0x70 }, /* manuf_key_info */
2849 { 0, 0 }
2850 };
2851 const struct crc_pair nvram_tbl2[] = {
2852 { 0x7e8, 0x350 }, /* manuf_info2 */
2853 { 0xb38, 0xf0 }, /* feature_info */
2854 { 0, 0 }
2855 };
2856
2857 u8 *buf;
2858 int rc;
2859 u32 magic;
2860
2861 if (BP_NOMCP(bp))
2862 return 0;
2863
2864 buf = kmalloc(CRC_BUFF_SIZE, GFP_KERNEL);
2865 if (!buf) {
2866 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n");
2867 rc = -ENOMEM;
2868 goto test_nvram_exit;
2869 }
2870
2871 rc = bnx2x_nvram_read32(bp, 0, &magic, sizeof(magic));
2872 if (rc) {
2873 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2874 "magic value read (rc %d)\n", rc);
2875 goto test_nvram_exit;
2876 }
2877
2878 if (magic != 0x669955aa) {
2879 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2880 "wrong magic value (0x%08x)\n", magic);
2881 rc = -ENODEV;
2882 goto test_nvram_exit;
2883 }
2884
2885 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "Port 0 CRC test-set\n");
2886 rc = bnx2x_test_nvram_tbl(bp, nvram_tbl, buf);
2887 if (rc)
2888 goto test_nvram_exit;
2889
2890 if (!CHIP_IS_E1x(bp) && !CHIP_IS_57811xx(bp)) {
2891 u32 hide = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
2892 SHARED_HW_CFG_HIDE_PORT1;
2893
2894 if (!hide) {
2895 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2896 "Port 1 CRC test-set\n");
2897 rc = bnx2x_test_nvram_tbl(bp, nvram_tbl2, buf);
2898 if (rc)
2899 goto test_nvram_exit;
2900 }
2901 }
2902
2903 rc = bnx2x_test_nvram_dirs(bp, buf);
2904
2905 test_nvram_exit:
2906 kfree(buf);
2907 return rc;
2908 }
2909
2910 /* Send an EMPTY ramrod on the first queue */
2911 static int bnx2x_test_intr(struct bnx2x *bp)
2912 {
2913 struct bnx2x_queue_state_params params = {NULL};
2914
2915 if (!netif_running(bp->dev)) {
2916 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2917 "cannot access eeprom when the interface is down\n");
2918 return -ENODEV;
2919 }
2920
2921 params.q_obj = &bp->sp_objs->q_obj;
2922 params.cmd = BNX2X_Q_CMD_EMPTY;
2923
2924 __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
2925
2926 return bnx2x_queue_state_change(bp, &params);
2927 }
2928
2929 static void bnx2x_self_test(struct net_device *dev,
2930 struct ethtool_test *etest, u64 *buf)
2931 {
2932 struct bnx2x *bp = netdev_priv(dev);
2933 u8 is_serdes, link_up;
2934 int rc, cnt = 0;
2935
2936 if (pci_num_vf(bp->pdev)) {
2937 DP(BNX2X_MSG_IOV,
2938 "VFs are enabled, can not perform self test\n");
2939 return;
2940 }
2941
2942 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
2943 netdev_err(bp->dev,
2944 "Handling parity error recovery. Try again later\n");
2945 etest->flags |= ETH_TEST_FL_FAILED;
2946 return;
2947 }
2948
2949 DP(BNX2X_MSG_ETHTOOL,
2950 "Self-test command parameters: offline = %d, external_lb = %d\n",
2951 (etest->flags & ETH_TEST_FL_OFFLINE),
2952 (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2);
2953
2954 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp));
2955
2956 if (bnx2x_test_nvram(bp) != 0) {
2957 if (!IS_MF(bp))
2958 buf[4] = 1;
2959 else
2960 buf[0] = 1;
2961 etest->flags |= ETH_TEST_FL_FAILED;
2962 }
2963
2964 if (!netif_running(dev)) {
2965 DP(BNX2X_MSG_ETHTOOL, "Interface is down\n");
2966 return;
2967 }
2968
2969 is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2970 link_up = bp->link_vars.link_up;
2971 /* offline tests are not supported in MF mode */
2972 if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) {
2973 int port = BP_PORT(bp);
2974 u32 val;
2975
2976 /* save current value of input enable for TX port IF */
2977 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
2978 /* disable input for TX port IF */
2979 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
2980
2981 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
2982 rc = bnx2x_nic_load(bp, LOAD_DIAG);
2983 if (rc) {
2984 etest->flags |= ETH_TEST_FL_FAILED;
2985 DP(BNX2X_MSG_ETHTOOL,
2986 "Can't perform self-test, nic_load (for offline) failed\n");
2987 return;
2988 }
2989
2990 /* wait until link state is restored */
2991 bnx2x_wait_for_link(bp, 1, is_serdes);
2992
2993 if (bnx2x_test_registers(bp) != 0) {
2994 buf[0] = 1;
2995 etest->flags |= ETH_TEST_FL_FAILED;
2996 }
2997 if (bnx2x_test_memory(bp) != 0) {
2998 buf[1] = 1;
2999 etest->flags |= ETH_TEST_FL_FAILED;
3000 }
3001
3002 buf[2] = bnx2x_test_loopback(bp); /* internal LB */
3003 if (buf[2] != 0)
3004 etest->flags |= ETH_TEST_FL_FAILED;
3005
3006 if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) {
3007 buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */
3008 if (buf[3] != 0)
3009 etest->flags |= ETH_TEST_FL_FAILED;
3010 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
3011 }
3012
3013 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
3014
3015 /* restore input for TX port IF */
3016 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
3017 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
3018 if (rc) {
3019 etest->flags |= ETH_TEST_FL_FAILED;
3020 DP(BNX2X_MSG_ETHTOOL,
3021 "Can't perform self-test, nic_load (for online) failed\n");
3022 return;
3023 }
3024 /* wait until link state is restored */
3025 bnx2x_wait_for_link(bp, link_up, is_serdes);
3026 }
3027
3028 if (bnx2x_test_intr(bp) != 0) {
3029 if (!IS_MF(bp))
3030 buf[5] = 1;
3031 else
3032 buf[1] = 1;
3033 etest->flags |= ETH_TEST_FL_FAILED;
3034 }
3035
3036 if (link_up) {
3037 cnt = 100;
3038 while (bnx2x_link_test(bp, is_serdes) && --cnt)
3039 msleep(20);
3040 }
3041
3042 if (!cnt) {
3043 if (!IS_MF(bp))
3044 buf[6] = 1;
3045 else
3046 buf[2] = 1;
3047 etest->flags |= ETH_TEST_FL_FAILED;
3048 }
3049 }
3050
3051 #define IS_PORT_STAT(i) \
3052 ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
3053 #define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
3054 #define HIDE_PORT_STAT(bp) \
3055 ((IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS)) || \
3056 IS_VF(bp))
3057
3058 /* ethtool statistics are displayed for all regular ethernet queues and the
3059 * fcoe L2 queue if not disabled
3060 */
3061 static int bnx2x_num_stat_queues(struct bnx2x *bp)
3062 {
3063 return BNX2X_NUM_ETH_QUEUES(bp);
3064 }
3065
3066 static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
3067 {
3068 struct bnx2x *bp = netdev_priv(dev);
3069 int i, num_strings = 0;
3070
3071 switch (stringset) {
3072 case ETH_SS_STATS:
3073 if (is_multi(bp)) {
3074 num_strings = bnx2x_num_stat_queues(bp) *
3075 BNX2X_NUM_Q_STATS;
3076 } else
3077 num_strings = 0;
3078 if (HIDE_PORT_STAT(bp)) {
3079 for (i = 0; i < BNX2X_NUM_STATS; i++)
3080 if (IS_FUNC_STAT(i))
3081 num_strings++;
3082 } else
3083 num_strings += BNX2X_NUM_STATS;
3084
3085 return num_strings;
3086
3087 case ETH_SS_TEST:
3088 return BNX2X_NUM_TESTS(bp);
3089
3090 case ETH_SS_PRIV_FLAGS:
3091 return BNX2X_PRI_FLAG_LEN;
3092
3093 default:
3094 return -EINVAL;
3095 }
3096 }
3097
3098 static u32 bnx2x_get_private_flags(struct net_device *dev)
3099 {
3100 struct bnx2x *bp = netdev_priv(dev);
3101 u32 flags = 0;
3102
3103 flags |= (!(bp->flags & NO_ISCSI_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_ISCSI;
3104 flags |= (!(bp->flags & NO_FCOE_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_FCOE;
3105 flags |= (!!IS_MF_STORAGE_ONLY(bp)) << BNX2X_PRI_FLAG_STORAGE;
3106
3107 return flags;
3108 }
3109
3110 static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
3111 {
3112 struct bnx2x *bp = netdev_priv(dev);
3113 int i, j, k, start;
3114 char queue_name[MAX_QUEUE_NAME_LEN+1];
3115
3116 switch (stringset) {
3117 case ETH_SS_STATS:
3118 k = 0;
3119 if (is_multi(bp)) {
3120 for_each_eth_queue(bp, i) {
3121 memset(queue_name, 0, sizeof(queue_name));
3122 sprintf(queue_name, "%d", i);
3123 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
3124 snprintf(buf + (k + j)*ETH_GSTRING_LEN,
3125 ETH_GSTRING_LEN,
3126 bnx2x_q_stats_arr[j].string,
3127 queue_name);
3128 k += BNX2X_NUM_Q_STATS;
3129 }
3130 }
3131
3132 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
3133 if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i))
3134 continue;
3135 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
3136 bnx2x_stats_arr[i].string);
3137 j++;
3138 }
3139
3140 break;
3141
3142 case ETH_SS_TEST:
3143 /* First 4 tests cannot be done in MF mode */
3144 if (!IS_MF(bp))
3145 start = 0;
3146 else
3147 start = 4;
3148 memcpy(buf, bnx2x_tests_str_arr + start,
3149 ETH_GSTRING_LEN * BNX2X_NUM_TESTS(bp));
3150 break;
3151
3152 case ETH_SS_PRIV_FLAGS:
3153 memcpy(buf, bnx2x_private_arr,
3154 ETH_GSTRING_LEN * BNX2X_PRI_FLAG_LEN);
3155 break;
3156 }
3157 }
3158
3159 static void bnx2x_get_ethtool_stats(struct net_device *dev,
3160 struct ethtool_stats *stats, u64 *buf)
3161 {
3162 struct bnx2x *bp = netdev_priv(dev);
3163 u32 *hw_stats, *offset;
3164 int i, j, k = 0;
3165
3166 if (is_multi(bp)) {
3167 for_each_eth_queue(bp, i) {
3168 hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats;
3169 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
3170 if (bnx2x_q_stats_arr[j].size == 0) {
3171 /* skip this counter */
3172 buf[k + j] = 0;
3173 continue;
3174 }
3175 offset = (hw_stats +
3176 bnx2x_q_stats_arr[j].offset);
3177 if (bnx2x_q_stats_arr[j].size == 4) {
3178 /* 4-byte counter */
3179 buf[k + j] = (u64) *offset;
3180 continue;
3181 }
3182 /* 8-byte counter */
3183 buf[k + j] = HILO_U64(*offset, *(offset + 1));
3184 }
3185 k += BNX2X_NUM_Q_STATS;
3186 }
3187 }
3188
3189 hw_stats = (u32 *)&bp->eth_stats;
3190 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
3191 if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i))
3192 continue;
3193 if (bnx2x_stats_arr[i].size == 0) {
3194 /* skip this counter */
3195 buf[k + j] = 0;
3196 j++;
3197 continue;
3198 }
3199 offset = (hw_stats + bnx2x_stats_arr[i].offset);
3200 if (bnx2x_stats_arr[i].size == 4) {
3201 /* 4-byte counter */
3202 buf[k + j] = (u64) *offset;
3203 j++;
3204 continue;
3205 }
3206 /* 8-byte counter */
3207 buf[k + j] = HILO_U64(*offset, *(offset + 1));
3208 j++;
3209 }
3210 }
3211
3212 static int bnx2x_set_phys_id(struct net_device *dev,
3213 enum ethtool_phys_id_state state)
3214 {
3215 struct bnx2x *bp = netdev_priv(dev);
3216
3217 if (!bnx2x_is_nvm_accessible(bp)) {
3218 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
3219 "cannot access eeprom when the interface is down\n");
3220 return -EAGAIN;
3221 }
3222
3223 switch (state) {
3224 case ETHTOOL_ID_ACTIVE:
3225 return 1; /* cycle on/off once per second */
3226
3227 case ETHTOOL_ID_ON:
3228 bnx2x_acquire_phy_lock(bp);
3229 bnx2x_set_led(&bp->link_params, &bp->link_vars,
3230 LED_MODE_ON, SPEED_1000);
3231 bnx2x_release_phy_lock(bp);
3232 break;
3233
3234 case ETHTOOL_ID_OFF:
3235 bnx2x_acquire_phy_lock(bp);
3236 bnx2x_set_led(&bp->link_params, &bp->link_vars,
3237 LED_MODE_FRONT_PANEL_OFF, 0);
3238 bnx2x_release_phy_lock(bp);
3239 break;
3240
3241 case ETHTOOL_ID_INACTIVE:
3242 bnx2x_acquire_phy_lock(bp);
3243 bnx2x_set_led(&bp->link_params, &bp->link_vars,
3244 LED_MODE_OPER,
3245 bp->link_vars.line_speed);
3246 bnx2x_release_phy_lock(bp);
3247 }
3248
3249 return 0;
3250 }
3251
3252 static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
3253 {
3254 switch (info->flow_type) {
3255 case TCP_V4_FLOW:
3256 case TCP_V6_FLOW:
3257 info->data = RXH_IP_SRC | RXH_IP_DST |
3258 RXH_L4_B_0_1 | RXH_L4_B_2_3;
3259 break;
3260 case UDP_V4_FLOW:
3261 if (bp->rss_conf_obj.udp_rss_v4)
3262 info->data = RXH_IP_SRC | RXH_IP_DST |
3263 RXH_L4_B_0_1 | RXH_L4_B_2_3;
3264 else
3265 info->data = RXH_IP_SRC | RXH_IP_DST;
3266 break;
3267 case UDP_V6_FLOW:
3268 if (bp->rss_conf_obj.udp_rss_v6)
3269 info->data = RXH_IP_SRC | RXH_IP_DST |
3270 RXH_L4_B_0_1 | RXH_L4_B_2_3;
3271 else
3272 info->data = RXH_IP_SRC | RXH_IP_DST;
3273 break;
3274 case IPV4_FLOW:
3275 case IPV6_FLOW:
3276 info->data = RXH_IP_SRC | RXH_IP_DST;
3277 break;
3278 default:
3279 info->data = 0;
3280 break;
3281 }
3282
3283 return 0;
3284 }
3285
3286 static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
3287 u32 *rules __always_unused)
3288 {
3289 struct bnx2x *bp = netdev_priv(dev);
3290
3291 switch (info->cmd) {
3292 case ETHTOOL_GRXRINGS:
3293 info->data = BNX2X_NUM_ETH_QUEUES(bp);
3294 return 0;
3295 case ETHTOOL_GRXFH:
3296 return bnx2x_get_rss_flags(bp, info);
3297 default:
3298 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
3299 return -EOPNOTSUPP;
3300 }
3301 }
3302
3303 static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
3304 {
3305 int udp_rss_requested;
3306
3307 DP(BNX2X_MSG_ETHTOOL,
3308 "Set rss flags command parameters: flow type = %d, data = %llu\n",
3309 info->flow_type, info->data);
3310
3311 switch (info->flow_type) {
3312 case TCP_V4_FLOW:
3313 case TCP_V6_FLOW:
3314 /* For TCP only 4-tupple hash is supported */
3315 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST |
3316 RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
3317 DP(BNX2X_MSG_ETHTOOL,
3318 "Command parameters not supported\n");
3319 return -EINVAL;
3320 }
3321 return 0;
3322
3323 case UDP_V4_FLOW:
3324 case UDP_V6_FLOW:
3325 /* For UDP either 2-tupple hash or 4-tupple hash is supported */
3326 if (info->data == (RXH_IP_SRC | RXH_IP_DST |
3327 RXH_L4_B_0_1 | RXH_L4_B_2_3))
3328 udp_rss_requested = 1;
3329 else if (info->data == (RXH_IP_SRC | RXH_IP_DST))
3330 udp_rss_requested = 0;
3331 else
3332 return -EINVAL;
3333 if ((info->flow_type == UDP_V4_FLOW) &&
3334 (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) {
3335 bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested;
3336 DP(BNX2X_MSG_ETHTOOL,
3337 "rss re-configured, UDP 4-tupple %s\n",
3338 udp_rss_requested ? "enabled" : "disabled");
3339 return bnx2x_rss(bp, &bp->rss_conf_obj, false, true);
3340 } else if ((info->flow_type == UDP_V6_FLOW) &&
3341 (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) {
3342 bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested;
3343 DP(BNX2X_MSG_ETHTOOL,
3344 "rss re-configured, UDP 4-tupple %s\n",
3345 udp_rss_requested ? "enabled" : "disabled");
3346 return bnx2x_rss(bp, &bp->rss_conf_obj, false, true);
3347 }
3348 return 0;
3349
3350 case IPV4_FLOW:
3351 case IPV6_FLOW:
3352 /* For IP only 2-tupple hash is supported */
3353 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) {
3354 DP(BNX2X_MSG_ETHTOOL,
3355 "Command parameters not supported\n");
3356 return -EINVAL;
3357 }
3358 return 0;
3359
3360 case SCTP_V4_FLOW:
3361 case AH_ESP_V4_FLOW:
3362 case AH_V4_FLOW:
3363 case ESP_V4_FLOW:
3364 case SCTP_V6_FLOW:
3365 case AH_ESP_V6_FLOW:
3366 case AH_V6_FLOW:
3367 case ESP_V6_FLOW:
3368 case IP_USER_FLOW:
3369 case ETHER_FLOW:
3370 /* RSS is not supported for these protocols */
3371 if (info->data) {
3372 DP(BNX2X_MSG_ETHTOOL,
3373 "Command parameters not supported\n");
3374 return -EINVAL;
3375 }
3376 return 0;
3377
3378 default:
3379 return -EINVAL;
3380 }
3381 }
3382
3383 static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info)
3384 {
3385 struct bnx2x *bp = netdev_priv(dev);
3386
3387 switch (info->cmd) {
3388 case ETHTOOL_SRXFH:
3389 return bnx2x_set_rss_flags(bp, info);
3390 default:
3391 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
3392 return -EOPNOTSUPP;
3393 }
3394 }
3395
3396 static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev)
3397 {
3398 return T_ETH_INDIRECTION_TABLE_SIZE;
3399 }
3400
3401 static int bnx2x_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
3402 u8 *hfunc)
3403 {
3404 struct bnx2x *bp = netdev_priv(dev);
3405 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
3406 size_t i;
3407
3408 if (hfunc)
3409 *hfunc = ETH_RSS_HASH_TOP;
3410 if (!indir)
3411 return 0;
3412
3413 /* Get the current configuration of the RSS indirection table */
3414 bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table);
3415
3416 /*
3417 * We can't use a memcpy() as an internal storage of an
3418 * indirection table is a u8 array while indir->ring_index
3419 * points to an array of u32.
3420 *
3421 * Indirection table contains the FW Client IDs, so we need to
3422 * align the returned table to the Client ID of the leading RSS
3423 * queue.
3424 */
3425 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++)
3426 indir[i] = ind_table[i] - bp->fp->cl_id;
3427
3428 return 0;
3429 }
3430
3431 static int bnx2x_set_rxfh(struct net_device *dev, const u32 *indir,
3432 const u8 *key, const u8 hfunc)
3433 {
3434 struct bnx2x *bp = netdev_priv(dev);
3435 size_t i;
3436
3437 /* We require at least one supported parameter to be changed and no
3438 * change in any of the unsupported parameters
3439 */
3440 if (key ||
3441 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
3442 return -EOPNOTSUPP;
3443
3444 if (!indir)
3445 return 0;
3446
3447 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
3448 /*
3449 * The same as in bnx2x_get_rxfh: we can't use a memcpy()
3450 * as an internal storage of an indirection table is a u8 array
3451 * while indir->ring_index points to an array of u32.
3452 *
3453 * Indirection table contains the FW Client IDs, so we need to
3454 * align the received table to the Client ID of the leading RSS
3455 * queue
3456 */
3457 bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id;
3458 }
3459
3460 return bnx2x_config_rss_eth(bp, false);
3461 }
3462
3463 /**
3464 * bnx2x_get_channels - gets the number of RSS queues.
3465 *
3466 * @dev: net device
3467 * @channels: returns the number of max / current queues
3468 */
3469 static void bnx2x_get_channels(struct net_device *dev,
3470 struct ethtool_channels *channels)
3471 {
3472 struct bnx2x *bp = netdev_priv(dev);
3473
3474 channels->max_combined = BNX2X_MAX_RSS_COUNT(bp);
3475 channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp);
3476 }
3477
3478 /**
3479 * bnx2x_change_num_queues - change the number of RSS queues.
3480 *
3481 * @bp: bnx2x private structure
3482 *
3483 * Re-configure interrupt mode to get the new number of MSI-X
3484 * vectors and re-add NAPI objects.
3485 */
3486 static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss)
3487 {
3488 bnx2x_disable_msi(bp);
3489 bp->num_ethernet_queues = num_rss;
3490 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
3491 BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues);
3492 bnx2x_set_int_mode(bp);
3493 }
3494
3495 /**
3496 * bnx2x_set_channels - sets the number of RSS queues.
3497 *
3498 * @dev: net device
3499 * @channels: includes the number of queues requested
3500 */
3501 static int bnx2x_set_channels(struct net_device *dev,
3502 struct ethtool_channels *channels)
3503 {
3504 struct bnx2x *bp = netdev_priv(dev);
3505
3506 DP(BNX2X_MSG_ETHTOOL,
3507 "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n",
3508 channels->rx_count, channels->tx_count, channels->other_count,
3509 channels->combined_count);
3510
3511 if (pci_num_vf(bp->pdev)) {
3512 DP(BNX2X_MSG_IOV, "VFs are enabled, can not set channels\n");
3513 return -EPERM;
3514 }
3515
3516 /* We don't support separate rx / tx channels.
3517 * We don't allow setting 'other' channels.
3518 */
3519 if (channels->rx_count || channels->tx_count || channels->other_count
3520 || (channels->combined_count == 0) ||
3521 (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) {
3522 DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n");
3523 return -EINVAL;
3524 }
3525
3526 /* Check if there was a change in the active parameters */
3527 if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) {
3528 DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n");
3529 return 0;
3530 }
3531
3532 /* Set the requested number of queues in bp context.
3533 * Note that the actual number of queues created during load may be
3534 * less than requested if memory is low.
3535 */
3536 if (unlikely(!netif_running(dev))) {
3537 bnx2x_change_num_queues(bp, channels->combined_count);
3538 return 0;
3539 }
3540 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
3541 bnx2x_change_num_queues(bp, channels->combined_count);
3542 return bnx2x_nic_load(bp, LOAD_NORMAL);
3543 }
3544
3545 static int bnx2x_get_ts_info(struct net_device *dev,
3546 struct ethtool_ts_info *info)
3547 {
3548 struct bnx2x *bp = netdev_priv(dev);
3549
3550 if (bp->flags & PTP_SUPPORTED) {
3551 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
3552 SOF_TIMESTAMPING_RX_SOFTWARE |
3553 SOF_TIMESTAMPING_SOFTWARE |
3554 SOF_TIMESTAMPING_TX_HARDWARE |
3555 SOF_TIMESTAMPING_RX_HARDWARE |
3556 SOF_TIMESTAMPING_RAW_HARDWARE;
3557
3558 if (bp->ptp_clock)
3559 info->phc_index = ptp_clock_index(bp->ptp_clock);
3560 else
3561 info->phc_index = -1;
3562
3563 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
3564 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
3565 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
3566 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
3567 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
3568 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
3569 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
3570 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
3571 (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
3572 (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) |
3573 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) |
3574 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) |
3575 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ);
3576
3577 info->tx_types = (1 << HWTSTAMP_TX_OFF)|(1 << HWTSTAMP_TX_ON);
3578
3579 return 0;
3580 }
3581
3582 return ethtool_op_get_ts_info(dev, info);
3583 }
3584
3585 static const struct ethtool_ops bnx2x_ethtool_ops = {
3586 .get_settings = bnx2x_get_settings,
3587 .set_settings = bnx2x_set_settings,
3588 .get_drvinfo = bnx2x_get_drvinfo,
3589 .get_regs_len = bnx2x_get_regs_len,
3590 .get_regs = bnx2x_get_regs,
3591 .get_dump_flag = bnx2x_get_dump_flag,
3592 .get_dump_data = bnx2x_get_dump_data,
3593 .set_dump = bnx2x_set_dump,
3594 .get_wol = bnx2x_get_wol,
3595 .set_wol = bnx2x_set_wol,
3596 .get_msglevel = bnx2x_get_msglevel,
3597 .set_msglevel = bnx2x_set_msglevel,
3598 .nway_reset = bnx2x_nway_reset,
3599 .get_link = bnx2x_get_link,
3600 .get_eeprom_len = bnx2x_get_eeprom_len,
3601 .get_eeprom = bnx2x_get_eeprom,
3602 .set_eeprom = bnx2x_set_eeprom,
3603 .get_coalesce = bnx2x_get_coalesce,
3604 .set_coalesce = bnx2x_set_coalesce,
3605 .get_ringparam = bnx2x_get_ringparam,
3606 .set_ringparam = bnx2x_set_ringparam,
3607 .get_pauseparam = bnx2x_get_pauseparam,
3608 .set_pauseparam = bnx2x_set_pauseparam,
3609 .self_test = bnx2x_self_test,
3610 .get_sset_count = bnx2x_get_sset_count,
3611 .get_priv_flags = bnx2x_get_private_flags,
3612 .get_strings = bnx2x_get_strings,
3613 .set_phys_id = bnx2x_set_phys_id,
3614 .get_ethtool_stats = bnx2x_get_ethtool_stats,
3615 .get_rxnfc = bnx2x_get_rxnfc,
3616 .set_rxnfc = bnx2x_set_rxnfc,
3617 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size,
3618 .get_rxfh = bnx2x_get_rxfh,
3619 .set_rxfh = bnx2x_set_rxfh,
3620 .get_channels = bnx2x_get_channels,
3621 .set_channels = bnx2x_set_channels,
3622 .get_module_info = bnx2x_get_module_info,
3623 .get_module_eeprom = bnx2x_get_module_eeprom,
3624 .get_eee = bnx2x_get_eee,
3625 .set_eee = bnx2x_set_eee,
3626 .get_ts_info = bnx2x_get_ts_info,
3627 };
3628
3629 static const struct ethtool_ops bnx2x_vf_ethtool_ops = {
3630 .get_settings = bnx2x_get_vf_settings,
3631 .get_drvinfo = bnx2x_get_drvinfo,
3632 .get_msglevel = bnx2x_get_msglevel,
3633 .set_msglevel = bnx2x_set_msglevel,
3634 .get_link = bnx2x_get_link,
3635 .get_coalesce = bnx2x_get_coalesce,
3636 .get_ringparam = bnx2x_get_ringparam,
3637 .set_ringparam = bnx2x_set_ringparam,
3638 .get_sset_count = bnx2x_get_sset_count,
3639 .get_strings = bnx2x_get_strings,
3640 .get_ethtool_stats = bnx2x_get_ethtool_stats,
3641 .get_rxnfc = bnx2x_get_rxnfc,
3642 .set_rxnfc = bnx2x_set_rxnfc,
3643 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size,
3644 .get_rxfh = bnx2x_get_rxfh,
3645 .set_rxfh = bnx2x_set_rxfh,
3646 .get_channels = bnx2x_get_channels,
3647 .set_channels = bnx2x_set_channels,
3648 };
3649
3650 void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev)
3651 {
3652 netdev->ethtool_ops = (IS_PF(bp)) ?
3653 &bnx2x_ethtool_ops : &bnx2x_vf_ethtool_ops;
3654 }
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