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[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_link.c
1 /* Copyright 2008-2012 Broadcom Corporation
2 *
3 * Unless you and Broadcom execute a separate written software license
4 * agreement governing use of this software, this software is licensed to you
5 * under the terms of the GNU General Public License version 2, available
6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
7 *
8 * Notwithstanding the above, under no circumstances may you combine this
9 * software in any way with any other Broadcom software provided under a
10 * license other than the GPL, without Broadcom's express prior written
11 * consent.
12 *
13 * Written by Yaniv Rosner
14 *
15 */
16
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
23 #include <linux/delay.h>
24 #include <linux/ethtool.h>
25 #include <linux/mutex.h>
26
27 #include "bnx2x.h"
28 #include "bnx2x_cmn.h"
29
30 /********************************************************/
31 #define ETH_HLEN 14
32 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
33 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
34 #define ETH_MIN_PACKET_SIZE 60
35 #define ETH_MAX_PACKET_SIZE 1500
36 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
37 #define MDIO_ACCESS_TIMEOUT 1000
38 #define WC_LANE_MAX 4
39 #define I2C_SWITCH_WIDTH 2
40 #define I2C_BSC0 0
41 #define I2C_BSC1 1
42 #define I2C_WA_RETRY_CNT 3
43 #define MCPR_IMC_COMMAND_READ_OP 1
44 #define MCPR_IMC_COMMAND_WRITE_OP 2
45
46 /* LED Blink rate that will achieve ~15.9Hz */
47 #define LED_BLINK_RATE_VAL_E3 354
48 #define LED_BLINK_RATE_VAL_E1X_E2 480
49 /***********************************************************/
50 /* Shortcut definitions */
51 /***********************************************************/
52
53 #define NIG_LATCH_BC_ENABLE_MI_INT 0
54
55 #define NIG_STATUS_EMAC0_MI_INT \
56 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
57 #define NIG_STATUS_XGXS0_LINK10G \
58 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
59 #define NIG_STATUS_XGXS0_LINK_STATUS \
60 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
61 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
62 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
63 #define NIG_STATUS_SERDES0_LINK_STATUS \
64 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
65 #define NIG_MASK_MI_INT \
66 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
67 #define NIG_MASK_XGXS0_LINK10G \
68 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
69 #define NIG_MASK_XGXS0_LINK_STATUS \
70 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
71 #define NIG_MASK_SERDES0_LINK_STATUS \
72 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
73
74 #define MDIO_AN_CL73_OR_37_COMPLETE \
75 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
76 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
77
78 #define XGXS_RESET_BITS \
79 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
80 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
81 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
82 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
83 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
84
85 #define SERDES_RESET_BITS \
86 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
87 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
88 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
89 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
90
91 #define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
92 #define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
93 #define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
94 #define AUTONEG_PARALLEL \
95 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
96 #define AUTONEG_SGMII_FIBER_AUTODET \
97 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
98 #define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
99
100 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
101 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
102 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
103 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
104 #define GP_STATUS_SPEED_MASK \
105 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
106 #define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
107 #define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
108 #define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
109 #define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
110 #define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
111 #define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
112 #define GP_STATUS_10G_HIG \
113 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
114 #define GP_STATUS_10G_CX4 \
115 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
116 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
117 #define GP_STATUS_10G_KX4 \
118 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
119 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
120 #define GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
121 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
122 #define GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
123 #define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
124 #define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
125 #define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
126 #define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
127 #define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
128 #define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
129 #define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
130 #define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
131 #define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
132 #define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
133 #define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
134 #define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
135 #define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
136 #define LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
137 #define LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
138
139
140
141 /* */
142 #define SFP_EEPROM_CON_TYPE_ADDR 0x2
143 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7
144 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
145
146
147 #define SFP_EEPROM_COMP_CODE_ADDR 0x3
148 #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4)
149 #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5)
150 #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6)
151
152 #define SFP_EEPROM_FC_TX_TECH_ADDR 0x8
153 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
154 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
155
156 #define SFP_EEPROM_OPTIONS_ADDR 0x40
157 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
158 #define SFP_EEPROM_OPTIONS_SIZE 2
159
160 #define EDC_MODE_LINEAR 0x0022
161 #define EDC_MODE_LIMITING 0x0044
162 #define EDC_MODE_PASSIVE_DAC 0x0055
163
164 /* BRB default for class 0 E2 */
165 #define DEFAULT0_E2_BRB_MAC_PAUSE_XOFF_THR 170
166 #define DEFAULT0_E2_BRB_MAC_PAUSE_XON_THR 250
167 #define DEFAULT0_E2_BRB_MAC_FULL_XOFF_THR 10
168 #define DEFAULT0_E2_BRB_MAC_FULL_XON_THR 50
169
170 /* BRB thresholds for E2*/
171 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE 170
172 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
173
174 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE 250
175 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
176
177 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE 10
178 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 90
179
180 #define PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE 50
181 #define PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE 250
182
183 /* BRB default for class 0 E3A0 */
184 #define DEFAULT0_E3A0_BRB_MAC_PAUSE_XOFF_THR 290
185 #define DEFAULT0_E3A0_BRB_MAC_PAUSE_XON_THR 410
186 #define DEFAULT0_E3A0_BRB_MAC_FULL_XOFF_THR 10
187 #define DEFAULT0_E3A0_BRB_MAC_FULL_XON_THR 50
188
189 /* BRB thresholds for E3A0 */
190 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE 290
191 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
192
193 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE 410
194 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
195
196 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE 10
197 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 170
198
199 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE 50
200 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE 410
201
202 /* BRB default for E3B0 */
203 #define DEFAULT0_E3B0_BRB_MAC_PAUSE_XOFF_THR 330
204 #define DEFAULT0_E3B0_BRB_MAC_PAUSE_XON_THR 490
205 #define DEFAULT0_E3B0_BRB_MAC_FULL_XOFF_THR 15
206 #define DEFAULT0_E3B0_BRB_MAC_FULL_XON_THR 55
207
208 /* BRB thresholds for E3B0 2 port mode*/
209 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE 1025
210 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
211
212 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE 1025
213 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
214
215 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE 10
216 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 1025
217
218 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE 50
219 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE 1025
220
221 /* only for E3B0*/
222 #define PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR 1025
223 #define PFC_E3B0_2P_BRB_FULL_LB_XON_THR 1025
224
225 /* Lossy +Lossless GUARANTIED == GUART */
226 #define PFC_E3B0_2P_MIX_PAUSE_LB_GUART 284
227 /* Lossless +Lossless*/
228 #define PFC_E3B0_2P_PAUSE_LB_GUART 236
229 /* Lossy +Lossy*/
230 #define PFC_E3B0_2P_NON_PAUSE_LB_GUART 342
231
232 /* Lossy +Lossless*/
233 #define PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART 284
234 /* Lossless +Lossless*/
235 #define PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART 236
236 /* Lossy +Lossy*/
237 #define PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART 336
238 #define PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST 80
239
240 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART 0
241 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST 0
242
243 /* BRB thresholds for E3B0 4 port mode */
244 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE 304
245 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
246
247 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE 384
248 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
249
250 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE 10
251 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 304
252
253 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE 50
254 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE 384
255
256 /* only for E3B0*/
257 #define PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR 304
258 #define PFC_E3B0_4P_BRB_FULL_LB_XON_THR 384
259 #define PFC_E3B0_4P_LB_GUART 120
260
261 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART 120
262 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST 80
263
264 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART 80
265 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST 120
266
267 /* Pause defines*/
268 #define DEFAULT_E3B0_BRB_FULL_LB_XOFF_THR 330
269 #define DEFAULT_E3B0_BRB_FULL_LB_XON_THR 490
270 #define DEFAULT_E3B0_LB_GUART 40
271
272 #define DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART 40
273 #define DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART_HYST 0
274
275 #define DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART 40
276 #define DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART_HYST 0
277
278 /* ETS defines*/
279 #define DCBX_INVALID_COS (0xFF)
280
281 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000)
282 #define ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000)
283 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360)
284 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720)
285 #define ETS_E3B0_PBF_MIN_W_VAL (10000)
286
287 #define MAX_PACKET_SIZE (9700)
288 #define WC_UC_TIMEOUT 100
289 #define MAX_KR_LINK_RETRY 4
290
291 /**********************************************************/
292 /* INTERFACE */
293 /**********************************************************/
294
295 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
296 bnx2x_cl45_write(_bp, _phy, \
297 (_phy)->def_md_devad, \
298 (_bank + (_addr & 0xf)), \
299 _val)
300
301 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
302 bnx2x_cl45_read(_bp, _phy, \
303 (_phy)->def_md_devad, \
304 (_bank + (_addr & 0xf)), \
305 _val)
306
307 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
308 {
309 u32 val = REG_RD(bp, reg);
310
311 val |= bits;
312 REG_WR(bp, reg, val);
313 return val;
314 }
315
316 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
317 {
318 u32 val = REG_RD(bp, reg);
319
320 val &= ~bits;
321 REG_WR(bp, reg, val);
322 return val;
323 }
324
325 /******************************************************************/
326 /* EPIO/GPIO section */
327 /******************************************************************/
328 static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en)
329 {
330 u32 epio_mask, gp_oenable;
331 *en = 0;
332 /* Sanity check */
333 if (epio_pin > 31) {
334 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin);
335 return;
336 }
337
338 epio_mask = 1 << epio_pin;
339 /* Set this EPIO to output */
340 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
341 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
342
343 *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
344 }
345 static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en)
346 {
347 u32 epio_mask, gp_output, gp_oenable;
348
349 /* Sanity check */
350 if (epio_pin > 31) {
351 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin);
352 return;
353 }
354 DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en);
355 epio_mask = 1 << epio_pin;
356 /* Set this EPIO to output */
357 gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS);
358 if (en)
359 gp_output |= epio_mask;
360 else
361 gp_output &= ~epio_mask;
362
363 REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
364
365 /* Set the value for this EPIO */
366 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
367 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
368 }
369
370 static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val)
371 {
372 if (pin_cfg == PIN_CFG_NA)
373 return;
374 if (pin_cfg >= PIN_CFG_EPIO0) {
375 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
376 } else {
377 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
378 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
379 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port);
380 }
381 }
382
383 static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val)
384 {
385 if (pin_cfg == PIN_CFG_NA)
386 return -EINVAL;
387 if (pin_cfg >= PIN_CFG_EPIO0) {
388 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
389 } else {
390 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
391 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
392 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
393 }
394 return 0;
395
396 }
397 /******************************************************************/
398 /* ETS section */
399 /******************************************************************/
400 static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)
401 {
402 /* ETS disabled configuration*/
403 struct bnx2x *bp = params->bp;
404
405 DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n");
406
407 /*
408 * mapping between entry priority to client number (0,1,2 -debug and
409 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
410 * 3bits client num.
411 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
412 * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000
413 */
414
415 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
416 /*
417 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
418 * as strict. Bits 0,1,2 - debug and management entries, 3 -
419 * COS0 entry, 4 - COS1 entry.
420 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
421 * bit4 bit3 bit2 bit1 bit0
422 * MCP and debug are strict
423 */
424
425 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
426 /* defines which entries (clients) are subjected to WFQ arbitration */
427 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
428 /*
429 * For strict priority entries defines the number of consecutive
430 * slots for the highest priority.
431 */
432 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
433 /*
434 * mapping between the CREDIT_WEIGHT registers and actual client
435 * numbers
436 */
437 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
438 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
439 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
440
441 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
442 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
443 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
444 /* ETS mode disable */
445 REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
446 /*
447 * If ETS mode is enabled (there is no strict priority) defines a WFQ
448 * weight for COS0/COS1.
449 */
450 REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
451 REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
452 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
453 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
454 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
455 /* Defines the number of consecutive slots for the strict priority */
456 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
457 }
458 /******************************************************************************
459 * Description:
460 * Getting min_w_val will be set according to line speed .
461 *.
462 ******************************************************************************/
463 static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars)
464 {
465 u32 min_w_val = 0;
466 /* Calculate min_w_val.*/
467 if (vars->link_up) {
468 if (vars->line_speed == SPEED_20000)
469 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
470 else
471 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
472 } else
473 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
474 /**
475 * If the link isn't up (static configuration for example ) The
476 * link will be according to 20GBPS.
477 */
478 return min_w_val;
479 }
480 /******************************************************************************
481 * Description:
482 * Getting credit upper bound form min_w_val.
483 *.
484 ******************************************************************************/
485 static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val)
486 {
487 const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val),
488 MAX_PACKET_SIZE);
489 return credit_upper_bound;
490 }
491 /******************************************************************************
492 * Description:
493 * Set credit upper bound for NIG.
494 *.
495 ******************************************************************************/
496 static void bnx2x_ets_e3b0_set_credit_upper_bound_nig(
497 const struct link_params *params,
498 const u32 min_w_val)
499 {
500 struct bnx2x *bp = params->bp;
501 const u8 port = params->port;
502 const u32 credit_upper_bound =
503 bnx2x_ets_get_credit_upper_bound(min_w_val);
504
505 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
506 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound);
507 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
508 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound);
509 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
510 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound);
511 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
512 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound);
513 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
514 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound);
515 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
516 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound);
517
518 if (!port) {
519 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
520 credit_upper_bound);
521 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
522 credit_upper_bound);
523 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
524 credit_upper_bound);
525 }
526 }
527 /******************************************************************************
528 * Description:
529 * Will return the NIG ETS registers to init values.Except
530 * credit_upper_bound.
531 * That isn't used in this configuration (No WFQ is enabled) and will be
532 * configured acording to spec
533 *.
534 ******************************************************************************/
535 static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
536 const struct link_vars *vars)
537 {
538 struct bnx2x *bp = params->bp;
539 const u8 port = params->port;
540 const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars);
541 /**
542 * mapping between entry priority to client number (0,1,2 -debug and
543 * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
544 * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
545 * reset value or init tool
546 */
547 if (port) {
548 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
549 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
550 } else {
551 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
552 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
553 }
554 /**
555 * For strict priority entries defines the number of consecutive
556 * slots for the highest priority.
557 */
558 /* TODO_ETS - Should be done by reset value or init tool */
559 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
560 NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
561 /**
562 * mapping between the CREDIT_WEIGHT registers and actual client
563 * numbers
564 */
565 /* TODO_ETS - Should be done by reset value or init tool */
566 if (port) {
567 /*Port 1 has 6 COS*/
568 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
569 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
570 } else {
571 /*Port 0 has 9 COS*/
572 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
573 0x43210876);
574 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
575 }
576
577 /**
578 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
579 * as strict. Bits 0,1,2 - debug and management entries, 3 -
580 * COS0 entry, 4 - COS1 entry.
581 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
582 * bit4 bit3 bit2 bit1 bit0
583 * MCP and debug are strict
584 */
585 if (port)
586 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
587 else
588 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
589 /* defines which entries (clients) are subjected to WFQ arbitration */
590 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
591 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
592
593 /**
594 * Please notice the register address are note continuous and a
595 * for here is note appropriate.In 2 port mode port0 only COS0-5
596 * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
597 * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
598 * are never used for WFQ
599 */
600 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
601 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);
602 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
603 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0);
604 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
605 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0);
606 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
607 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0);
608 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
609 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0);
610 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
611 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0);
612 if (!port) {
613 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
614 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
615 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
616 }
617
618 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);
619 }
620 /******************************************************************************
621 * Description:
622 * Set credit upper bound for PBF.
623 *.
624 ******************************************************************************/
625 static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf(
626 const struct link_params *params,
627 const u32 min_w_val)
628 {
629 struct bnx2x *bp = params->bp;
630 const u32 credit_upper_bound =
631 bnx2x_ets_get_credit_upper_bound(min_w_val);
632 const u8 port = params->port;
633 u32 base_upper_bound = 0;
634 u8 max_cos = 0;
635 u8 i = 0;
636 /**
637 * In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
638 * port mode port1 has COS0-2 that can be used for WFQ.
639 */
640 if (!port) {
641 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
642 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
643 } else {
644 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1;
645 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
646 }
647
648 for (i = 0; i < max_cos; i++)
649 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound);
650 }
651
652 /******************************************************************************
653 * Description:
654 * Will return the PBF ETS registers to init values.Except
655 * credit_upper_bound.
656 * That isn't used in this configuration (No WFQ is enabled) and will be
657 * configured acording to spec
658 *.
659 ******************************************************************************/
660 static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params)
661 {
662 struct bnx2x *bp = params->bp;
663 const u8 port = params->port;
664 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
665 u8 i = 0;
666 u32 base_weight = 0;
667 u8 max_cos = 0;
668
669 /**
670 * mapping between entry priority to client number 0 - COS0
671 * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
672 * TODO_ETS - Should be done by reset value or init tool
673 */
674 if (port)
675 /* 0x688 (|011|0 10|00 1|000) */
676 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);
677 else
678 /* (10 1|100 |011|0 10|00 1|000) */
679 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);
680
681 /* TODO_ETS - Should be done by reset value or init tool */
682 if (port)
683 /* 0x688 (|011|0 10|00 1|000)*/
684 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
685 else
686 /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
687 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
688
689 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
690 PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100);
691
692
693 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
694 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0);
695
696 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
697 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);
698 /**
699 * In 2 port mode port0 has COS0-5 that can be used for WFQ.
700 * In 4 port mode port1 has COS0-2 that can be used for WFQ.
701 */
702 if (!port) {
703 base_weight = PBF_REG_COS0_WEIGHT_P0;
704 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
705 } else {
706 base_weight = PBF_REG_COS0_WEIGHT_P1;
707 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
708 }
709
710 for (i = 0; i < max_cos; i++)
711 REG_WR(bp, base_weight + (0x4 * i), 0);
712
713 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
714 }
715 /******************************************************************************
716 * Description:
717 * E3B0 disable will return basicly the values to init values.
718 *.
719 ******************************************************************************/
720 static int bnx2x_ets_e3b0_disabled(const struct link_params *params,
721 const struct link_vars *vars)
722 {
723 struct bnx2x *bp = params->bp;
724
725 if (!CHIP_IS_E3B0(bp)) {
726 DP(NETIF_MSG_LINK,
727 "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
728 return -EINVAL;
729 }
730
731 bnx2x_ets_e3b0_nig_disabled(params, vars);
732
733 bnx2x_ets_e3b0_pbf_disabled(params);
734
735 return 0;
736 }
737
738 /******************************************************************************
739 * Description:
740 * Disable will return basicly the values to init values.
741 *.
742 ******************************************************************************/
743 int bnx2x_ets_disabled(struct link_params *params,
744 struct link_vars *vars)
745 {
746 struct bnx2x *bp = params->bp;
747 int bnx2x_status = 0;
748
749 if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp)))
750 bnx2x_ets_e2e3a0_disabled(params);
751 else if (CHIP_IS_E3B0(bp))
752 bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars);
753 else {
754 DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n");
755 return -EINVAL;
756 }
757
758 return bnx2x_status;
759 }
760
761 /******************************************************************************
762 * Description
763 * Set the COS mappimg to SP and BW until this point all the COS are not
764 * set as SP or BW.
765 ******************************************************************************/
766 static int bnx2x_ets_e3b0_cli_map(const struct link_params *params,
767 const struct bnx2x_ets_params *ets_params,
768 const u8 cos_sp_bitmap,
769 const u8 cos_bw_bitmap)
770 {
771 struct bnx2x *bp = params->bp;
772 const u8 port = params->port;
773 const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);
774 const u8 pbf_cli_sp_bitmap = cos_sp_bitmap;
775 const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3;
776 const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap;
777
778 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
779 NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap);
780
781 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
782 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap);
783
784 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
785 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
786 nig_cli_subject2wfq_bitmap);
787
788 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
789 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
790 pbf_cli_subject2wfq_bitmap);
791
792 return 0;
793 }
794
795 /******************************************************************************
796 * Description:
797 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
798 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
799 ******************************************************************************/
800 static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp,
801 const u8 cos_entry,
802 const u32 min_w_val_nig,
803 const u32 min_w_val_pbf,
804 const u16 total_bw,
805 const u8 bw,
806 const u8 port)
807 {
808 u32 nig_reg_adress_crd_weight = 0;
809 u32 pbf_reg_adress_crd_weight = 0;
810 /* Calculate and set BW for this COS - use 1 instead of 0 for BW */
811 const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw;
812 const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw;
813
814 switch (cos_entry) {
815 case 0:
816 nig_reg_adress_crd_weight =
817 (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
818 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
819 pbf_reg_adress_crd_weight = (port) ?
820 PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
821 break;
822 case 1:
823 nig_reg_adress_crd_weight = (port) ?
824 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
825 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
826 pbf_reg_adress_crd_weight = (port) ?
827 PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
828 break;
829 case 2:
830 nig_reg_adress_crd_weight = (port) ?
831 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
832 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
833
834 pbf_reg_adress_crd_weight = (port) ?
835 PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
836 break;
837 case 3:
838 if (port)
839 return -EINVAL;
840 nig_reg_adress_crd_weight =
841 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
842 pbf_reg_adress_crd_weight =
843 PBF_REG_COS3_WEIGHT_P0;
844 break;
845 case 4:
846 if (port)
847 return -EINVAL;
848 nig_reg_adress_crd_weight =
849 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
850 pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0;
851 break;
852 case 5:
853 if (port)
854 return -EINVAL;
855 nig_reg_adress_crd_weight =
856 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
857 pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0;
858 break;
859 }
860
861 REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig);
862
863 REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf);
864
865 return 0;
866 }
867 /******************************************************************************
868 * Description:
869 * Calculate the total BW.A value of 0 isn't legal.
870 *.
871 ******************************************************************************/
872 static int bnx2x_ets_e3b0_get_total_bw(
873 const struct link_params *params,
874 struct bnx2x_ets_params *ets_params,
875 u16 *total_bw)
876 {
877 struct bnx2x *bp = params->bp;
878 u8 cos_idx = 0;
879 u8 is_bw_cos_exist = 0;
880
881 *total_bw = 0 ;
882
883 /* Calculate total BW requested */
884 for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
885 if (ets_params->cos[cos_idx].state == bnx2x_cos_state_bw) {
886 is_bw_cos_exist = 1;
887 if (!ets_params->cos[cos_idx].params.bw_params.bw) {
888 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW"
889 "was set to 0\n");
890 /*
891 * This is to prevent a state when ramrods
892 * can't be sent
893 */
894 ets_params->cos[cos_idx].params.bw_params.bw
895 = 1;
896 }
897 *total_bw +=
898 ets_params->cos[cos_idx].params.bw_params.bw;
899 }
900 }
901
902 /* Check total BW is valid */
903 if ((is_bw_cos_exist == 1) && (*total_bw != 100)) {
904 if (*total_bw == 0) {
905 DP(NETIF_MSG_LINK,
906 "bnx2x_ets_E3B0_config total BW shouldn't be 0\n");
907 return -EINVAL;
908 }
909 DP(NETIF_MSG_LINK,
910 "bnx2x_ets_E3B0_config total BW should be 100\n");
911 /*
912 * We can handle a case whre the BW isn't 100 this can happen
913 * if the TC are joined.
914 */
915 }
916 return 0;
917 }
918
919 /******************************************************************************
920 * Description:
921 * Invalidate all the sp_pri_to_cos.
922 *.
923 ******************************************************************************/
924 static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos)
925 {
926 u8 pri = 0;
927 for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++)
928 sp_pri_to_cos[pri] = DCBX_INVALID_COS;
929 }
930 /******************************************************************************
931 * Description:
932 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
933 * according to sp_pri_to_cos.
934 *.
935 ******************************************************************************/
936 static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params,
937 u8 *sp_pri_to_cos, const u8 pri,
938 const u8 cos_entry)
939 {
940 struct bnx2x *bp = params->bp;
941 const u8 port = params->port;
942 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
943 DCBX_E3B0_MAX_NUM_COS_PORT0;
944
945 if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) {
946 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
947 "parameter There can't be two COS's with "
948 "the same strict pri\n");
949 return -EINVAL;
950 }
951
952 if (pri > max_num_of_cos) {
953 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
954 "parameter Illegal strict priority\n");
955 return -EINVAL;
956 }
957
958 sp_pri_to_cos[pri] = cos_entry;
959 return 0;
960
961 }
962
963 /******************************************************************************
964 * Description:
965 * Returns the correct value according to COS and priority in
966 * the sp_pri_cli register.
967 *.
968 ******************************************************************************/
969 static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset,
970 const u8 pri_set,
971 const u8 pri_offset,
972 const u8 entry_size)
973 {
974 u64 pri_cli_nig = 0;
975 pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size *
976 (pri_set + pri_offset));
977
978 return pri_cli_nig;
979 }
980 /******************************************************************************
981 * Description:
982 * Returns the correct value according to COS and priority in the
983 * sp_pri_cli register for NIG.
984 *.
985 ******************************************************************************/
986 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set)
987 {
988 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
989 const u8 nig_cos_offset = 3;
990 const u8 nig_pri_offset = 3;
991
992 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set,
993 nig_pri_offset, 4);
994
995 }
996 /******************************************************************************
997 * Description:
998 * Returns the correct value according to COS and priority in the
999 * sp_pri_cli register for PBF.
1000 *.
1001 ******************************************************************************/
1002 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set)
1003 {
1004 const u8 pbf_cos_offset = 0;
1005 const u8 pbf_pri_offset = 0;
1006
1007 return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set,
1008 pbf_pri_offset, 3);
1009
1010 }
1011
1012 /******************************************************************************
1013 * Description:
1014 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
1015 * according to sp_pri_to_cos.(which COS has higher priority)
1016 *.
1017 ******************************************************************************/
1018 static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params,
1019 u8 *sp_pri_to_cos)
1020 {
1021 struct bnx2x *bp = params->bp;
1022 u8 i = 0;
1023 const u8 port = params->port;
1024 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
1025 u64 pri_cli_nig = 0x210;
1026 u32 pri_cli_pbf = 0x0;
1027 u8 pri_set = 0;
1028 u8 pri_bitmask = 0;
1029 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1030 DCBX_E3B0_MAX_NUM_COS_PORT0;
1031
1032 u8 cos_bit_to_set = (1 << max_num_of_cos) - 1;
1033
1034 /* Set all the strict priority first */
1035 for (i = 0; i < max_num_of_cos; i++) {
1036 if (sp_pri_to_cos[i] != DCBX_INVALID_COS) {
1037 if (sp_pri_to_cos[i] >= DCBX_MAX_NUM_COS) {
1038 DP(NETIF_MSG_LINK,
1039 "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1040 "invalid cos entry\n");
1041 return -EINVAL;
1042 }
1043
1044 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1045 sp_pri_to_cos[i], pri_set);
1046
1047 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1048 sp_pri_to_cos[i], pri_set);
1049 pri_bitmask = 1 << sp_pri_to_cos[i];
1050 /* COS is used remove it from bitmap.*/
1051 if (!(pri_bitmask & cos_bit_to_set)) {
1052 DP(NETIF_MSG_LINK,
1053 "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1054 "invalid There can't be two COS's with"
1055 " the same strict pri\n");
1056 return -EINVAL;
1057 }
1058 cos_bit_to_set &= ~pri_bitmask;
1059 pri_set++;
1060 }
1061 }
1062
1063 /* Set all the Non strict priority i= COS*/
1064 for (i = 0; i < max_num_of_cos; i++) {
1065 pri_bitmask = 1 << i;
1066 /* Check if COS was already used for SP */
1067 if (pri_bitmask & cos_bit_to_set) {
1068 /* COS wasn't used for SP */
1069 pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1070 i, pri_set);
1071
1072 pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1073 i, pri_set);
1074 /* COS is used remove it from bitmap.*/
1075 cos_bit_to_set &= ~pri_bitmask;
1076 pri_set++;
1077 }
1078 }
1079
1080 if (pri_set != max_num_of_cos) {
1081 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all "
1082 "entries were set\n");
1083 return -EINVAL;
1084 }
1085
1086 if (port) {
1087 /* Only 6 usable clients*/
1088 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
1089 (u32)pri_cli_nig);
1090
1091 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf);
1092 } else {
1093 /* Only 9 usable clients*/
1094 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig);
1095 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF);
1096
1097 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
1098 pri_cli_nig_lsb);
1099 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
1100 pri_cli_nig_msb);
1101
1102 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf);
1103 }
1104 return 0;
1105 }
1106
1107 /******************************************************************************
1108 * Description:
1109 * Configure the COS to ETS according to BW and SP settings.
1110 ******************************************************************************/
1111 int bnx2x_ets_e3b0_config(const struct link_params *params,
1112 const struct link_vars *vars,
1113 struct bnx2x_ets_params *ets_params)
1114 {
1115 struct bnx2x *bp = params->bp;
1116 int bnx2x_status = 0;
1117 const u8 port = params->port;
1118 u16 total_bw = 0;
1119 const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars);
1120 const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
1121 u8 cos_bw_bitmap = 0;
1122 u8 cos_sp_bitmap = 0;
1123 u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0};
1124 const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1125 DCBX_E3B0_MAX_NUM_COS_PORT0;
1126 u8 cos_entry = 0;
1127
1128 if (!CHIP_IS_E3B0(bp)) {
1129 DP(NETIF_MSG_LINK,
1130 "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
1131 return -EINVAL;
1132 }
1133
1134 if ((ets_params->num_of_cos > max_num_of_cos)) {
1135 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS "
1136 "isn't supported\n");
1137 return -EINVAL;
1138 }
1139
1140 /* Prepare sp strict priority parameters*/
1141 bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos);
1142
1143 /* Prepare BW parameters*/
1144 bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params,
1145 &total_bw);
1146 if (bnx2x_status) {
1147 DP(NETIF_MSG_LINK,
1148 "bnx2x_ets_E3B0_config get_total_bw failed\n");
1149 return -EINVAL;
1150 }
1151
1152 /*
1153 * Upper bound is set according to current link speed (min_w_val
1154 * should be the same for upper bound and COS credit val).
1155 */
1156 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
1157 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1158
1159
1160 for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
1161 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) {
1162 cos_bw_bitmap |= (1 << cos_entry);
1163 /*
1164 * The function also sets the BW in HW(not the mappin
1165 * yet)
1166 */
1167 bnx2x_status = bnx2x_ets_e3b0_set_cos_bw(
1168 bp, cos_entry, min_w_val_nig, min_w_val_pbf,
1169 total_bw,
1170 ets_params->cos[cos_entry].params.bw_params.bw,
1171 port);
1172 } else if (bnx2x_cos_state_strict ==
1173 ets_params->cos[cos_entry].state){
1174 cos_sp_bitmap |= (1 << cos_entry);
1175
1176 bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set(
1177 params,
1178 sp_pri_to_cos,
1179 ets_params->cos[cos_entry].params.sp_params.pri,
1180 cos_entry);
1181
1182 } else {
1183 DP(NETIF_MSG_LINK,
1184 "bnx2x_ets_e3b0_config cos state not valid\n");
1185 return -EINVAL;
1186 }
1187 if (bnx2x_status) {
1188 DP(NETIF_MSG_LINK,
1189 "bnx2x_ets_e3b0_config set cos bw failed\n");
1190 return bnx2x_status;
1191 }
1192 }
1193
1194 /* Set SP register (which COS has higher priority) */
1195 bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params,
1196 sp_pri_to_cos);
1197
1198 if (bnx2x_status) {
1199 DP(NETIF_MSG_LINK,
1200 "bnx2x_ets_E3B0_config set_pri_cli_reg failed\n");
1201 return bnx2x_status;
1202 }
1203
1204 /* Set client mapping of BW and strict */
1205 bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params,
1206 cos_sp_bitmap,
1207 cos_bw_bitmap);
1208
1209 if (bnx2x_status) {
1210 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n");
1211 return bnx2x_status;
1212 }
1213 return 0;
1214 }
1215 static void bnx2x_ets_bw_limit_common(const struct link_params *params)
1216 {
1217 /* ETS disabled configuration */
1218 struct bnx2x *bp = params->bp;
1219 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1220 /*
1221 * defines which entries (clients) are subjected to WFQ arbitration
1222 * COS0 0x8
1223 * COS1 0x10
1224 */
1225 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
1226 /*
1227 * mapping between the ARB_CREDIT_WEIGHT registers and actual
1228 * client numbers (WEIGHT_0 does not actually have to represent
1229 * client 0)
1230 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1231 * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010
1232 */
1233 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
1234
1235 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
1236 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1237 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
1238 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1239
1240 /* ETS mode enabled*/
1241 REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
1242
1243 /* Defines the number of consecutive slots for the strict priority */
1244 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1245 /*
1246 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
1247 * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0
1248 * entry, 4 - COS1 entry.
1249 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1250 * bit4 bit3 bit2 bit1 bit0
1251 * MCP and debug are strict
1252 */
1253 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1254
1255 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
1256 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
1257 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1258 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
1259 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1260 }
1261
1262 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
1263 const u32 cos1_bw)
1264 {
1265 /* ETS disabled configuration*/
1266 struct bnx2x *bp = params->bp;
1267 const u32 total_bw = cos0_bw + cos1_bw;
1268 u32 cos0_credit_weight = 0;
1269 u32 cos1_credit_weight = 0;
1270
1271 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1272
1273 if ((!total_bw) ||
1274 (!cos0_bw) ||
1275 (!cos1_bw)) {
1276 DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
1277 return;
1278 }
1279
1280 cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1281 total_bw;
1282 cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1283 total_bw;
1284
1285 bnx2x_ets_bw_limit_common(params);
1286
1287 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
1288 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
1289
1290 REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
1291 REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
1292 }
1293
1294 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
1295 {
1296 /* ETS disabled configuration*/
1297 struct bnx2x *bp = params->bp;
1298 u32 val = 0;
1299
1300 DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
1301 /*
1302 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
1303 * as strict. Bits 0,1,2 - debug and management entries,
1304 * 3 - COS0 entry, 4 - COS1 entry.
1305 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1306 * bit4 bit3 bit2 bit1 bit0
1307 * MCP and debug are strict
1308 */
1309 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
1310 /*
1311 * For strict priority entries defines the number of consecutive slots
1312 * for the highest priority.
1313 */
1314 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1315 /* ETS mode disable */
1316 REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
1317 /* Defines the number of consecutive slots for the strict priority */
1318 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
1319
1320 /* Defines the number of consecutive slots for the strict priority */
1321 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
1322
1323 /*
1324 * mapping between entry priority to client number (0,1,2 -debug and
1325 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
1326 * 3bits client num.
1327 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1328 * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000
1329 * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000
1330 */
1331 val = (!strict_cos) ? 0x2318 : 0x22E0;
1332 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
1333
1334 return 0;
1335 }
1336 /******************************************************************/
1337 /* PFC section */
1338 /******************************************************************/
1339 static void bnx2x_update_pfc_xmac(struct link_params *params,
1340 struct link_vars *vars,
1341 u8 is_lb)
1342 {
1343 struct bnx2x *bp = params->bp;
1344 u32 xmac_base;
1345 u32 pause_val, pfc0_val, pfc1_val;
1346
1347 /* XMAC base adrr */
1348 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1349
1350 /* Initialize pause and pfc registers */
1351 pause_val = 0x18000;
1352 pfc0_val = 0xFFFF8000;
1353 pfc1_val = 0x2;
1354
1355 /* No PFC support */
1356 if (!(params->feature_config_flags &
1357 FEATURE_CONFIG_PFC_ENABLED)) {
1358
1359 /*
1360 * RX flow control - Process pause frame in receive direction
1361 */
1362 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1363 pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
1364
1365 /*
1366 * TX flow control - Send pause packet when buffer is full
1367 */
1368 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1369 pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
1370 } else {/* PFC support */
1371 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
1372 XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
1373 XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
1374 XMAC_PFC_CTRL_HI_REG_TX_PFC_EN |
1375 XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1376 /* Write pause and PFC registers */
1377 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1378 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1379 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1380 pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1381
1382 }
1383
1384 /* Write pause and PFC registers */
1385 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1386 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1387 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1388
1389
1390 /* Set MAC address for source TX Pause/PFC frames */
1391 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO,
1392 ((params->mac_addr[2] << 24) |
1393 (params->mac_addr[3] << 16) |
1394 (params->mac_addr[4] << 8) |
1395 (params->mac_addr[5])));
1396 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI,
1397 ((params->mac_addr[0] << 8) |
1398 (params->mac_addr[1])));
1399
1400 udelay(30);
1401 }
1402
1403
1404 static void bnx2x_emac_get_pfc_stat(struct link_params *params,
1405 u32 pfc_frames_sent[2],
1406 u32 pfc_frames_received[2])
1407 {
1408 /* Read pfc statistic */
1409 struct bnx2x *bp = params->bp;
1410 u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1411 u32 val_xon = 0;
1412 u32 val_xoff = 0;
1413
1414 DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n");
1415
1416 /* PFC received frames */
1417 val_xoff = REG_RD(bp, emac_base +
1418 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
1419 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
1420 val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
1421 val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
1422
1423 pfc_frames_received[0] = val_xon + val_xoff;
1424
1425 /* PFC received sent */
1426 val_xoff = REG_RD(bp, emac_base +
1427 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
1428 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
1429 val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
1430 val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
1431
1432 pfc_frames_sent[0] = val_xon + val_xoff;
1433 }
1434
1435 /* Read pfc statistic*/
1436 void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
1437 u32 pfc_frames_sent[2],
1438 u32 pfc_frames_received[2])
1439 {
1440 /* Read pfc statistic */
1441 struct bnx2x *bp = params->bp;
1442
1443 DP(NETIF_MSG_LINK, "pfc statistic\n");
1444
1445 if (!vars->link_up)
1446 return;
1447
1448 if (vars->mac_type == MAC_TYPE_EMAC) {
1449 DP(NETIF_MSG_LINK, "About to read PFC stats from EMAC\n");
1450 bnx2x_emac_get_pfc_stat(params, pfc_frames_sent,
1451 pfc_frames_received);
1452 }
1453 }
1454 /******************************************************************/
1455 /* MAC/PBF section */
1456 /******************************************************************/
1457 static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id, u8 port)
1458 {
1459 u32 mode, emac_base;
1460 /**
1461 * Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1462 * (a value of 49==0x31) and make sure that the AUTO poll is off
1463 */
1464
1465 if (CHIP_IS_E2(bp))
1466 emac_base = GRCBASE_EMAC0;
1467 else
1468 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1469 mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1470 mode &= ~(EMAC_MDIO_MODE_AUTO_POLL |
1471 EMAC_MDIO_MODE_CLOCK_CNT);
1472 if (USES_WARPCORE(bp))
1473 mode |= (74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
1474 else
1475 mode |= (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
1476
1477 mode |= (EMAC_MDIO_MODE_CLAUSE_45);
1478 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, mode);
1479
1480 udelay(40);
1481 }
1482 static u8 bnx2x_is_4_port_mode(struct bnx2x *bp)
1483 {
1484 u32 port4mode_ovwr_val;
1485 /* Check 4-port override enabled */
1486 port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
1487 if (port4mode_ovwr_val & (1<<0)) {
1488 /* Return 4-port mode override value */
1489 return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
1490 }
1491 /* Return 4-port mode from input pin */
1492 return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN);
1493 }
1494
1495 static void bnx2x_emac_init(struct link_params *params,
1496 struct link_vars *vars)
1497 {
1498 /* reset and unreset the emac core */
1499 struct bnx2x *bp = params->bp;
1500 u8 port = params->port;
1501 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1502 u32 val;
1503 u16 timeout;
1504
1505 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1506 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1507 udelay(5);
1508 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1509 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1510
1511 /* init emac - use read-modify-write */
1512 /* self clear reset */
1513 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1514 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
1515
1516 timeout = 200;
1517 do {
1518 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1519 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
1520 if (!timeout) {
1521 DP(NETIF_MSG_LINK, "EMAC timeout!\n");
1522 return;
1523 }
1524 timeout--;
1525 } while (val & EMAC_MODE_RESET);
1526 bnx2x_set_mdio_clk(bp, params->chip_id, port);
1527 /* Set mac address */
1528 val = ((params->mac_addr[0] << 8) |
1529 params->mac_addr[1]);
1530 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
1531
1532 val = ((params->mac_addr[2] << 24) |
1533 (params->mac_addr[3] << 16) |
1534 (params->mac_addr[4] << 8) |
1535 params->mac_addr[5]);
1536 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
1537 }
1538
1539 static void bnx2x_set_xumac_nig(struct link_params *params,
1540 u16 tx_pause_en,
1541 u8 enable)
1542 {
1543 struct bnx2x *bp = params->bp;
1544
1545 REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
1546 enable);
1547 REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
1548 enable);
1549 REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
1550 NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
1551 }
1552
1553 static void bnx2x_umac_disable(struct link_params *params)
1554 {
1555 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1556 struct bnx2x *bp = params->bp;
1557 if (!(REG_RD(bp, MISC_REG_RESET_REG_2) &
1558 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))
1559 return;
1560
1561 /* Disable RX and TX */
1562 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, 0);
1563 }
1564
1565 static void bnx2x_umac_enable(struct link_params *params,
1566 struct link_vars *vars, u8 lb)
1567 {
1568 u32 val;
1569 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1570 struct bnx2x *bp = params->bp;
1571 /* Reset UMAC */
1572 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1573 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1574 usleep_range(1000, 1000);
1575
1576 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1577 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1578
1579 DP(NETIF_MSG_LINK, "enabling UMAC\n");
1580
1581 /**
1582 * This register determines on which events the MAC will assert
1583 * error on the i/f to the NIG along w/ EOP.
1584 */
1585
1586 /**
1587 * BD REG_WR(bp, NIG_REG_P0_MAC_RSV_ERR_MASK +
1588 * params->port*0x14, 0xfffff.
1589 */
1590 /* This register opens the gate for the UMAC despite its name */
1591 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
1592
1593 val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
1594 UMAC_COMMAND_CONFIG_REG_PAD_EN |
1595 UMAC_COMMAND_CONFIG_REG_SW_RESET |
1596 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
1597 switch (vars->line_speed) {
1598 case SPEED_10:
1599 val |= (0<<2);
1600 break;
1601 case SPEED_100:
1602 val |= (1<<2);
1603 break;
1604 case SPEED_1000:
1605 val |= (2<<2);
1606 break;
1607 case SPEED_2500:
1608 val |= (3<<2);
1609 break;
1610 default:
1611 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n",
1612 vars->line_speed);
1613 break;
1614 }
1615 if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1616 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE;
1617
1618 if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1619 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE;
1620
1621 if (vars->duplex == DUPLEX_HALF)
1622 val |= UMAC_COMMAND_CONFIG_REG_HD_ENA;
1623
1624 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1625 udelay(50);
1626
1627 /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
1628 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0,
1629 ((params->mac_addr[2] << 24) |
1630 (params->mac_addr[3] << 16) |
1631 (params->mac_addr[4] << 8) |
1632 (params->mac_addr[5])));
1633 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1,
1634 ((params->mac_addr[0] << 8) |
1635 (params->mac_addr[1])));
1636
1637 /* Enable RX and TX */
1638 val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
1639 val |= UMAC_COMMAND_CONFIG_REG_TX_ENA |
1640 UMAC_COMMAND_CONFIG_REG_RX_ENA;
1641 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1642 udelay(50);
1643
1644 /* Remove SW Reset */
1645 val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
1646
1647 /* Check loopback mode */
1648 if (lb)
1649 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
1650 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1651
1652 /*
1653 * Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1654 * length used by the MAC receive logic to check frames.
1655 */
1656 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
1657 bnx2x_set_xumac_nig(params,
1658 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1659 vars->mac_type = MAC_TYPE_UMAC;
1660
1661 }
1662
1663 /* Define the XMAC mode */
1664 static void bnx2x_xmac_init(struct link_params *params, u32 max_speed)
1665 {
1666 struct bnx2x *bp = params->bp;
1667 u32 is_port4mode = bnx2x_is_4_port_mode(bp);
1668
1669 /*
1670 * In 4-port mode, need to set the mode only once, so if XMAC is
1671 * already out of reset, it means the mode has already been set,
1672 * and it must not* reset the XMAC again, since it controls both
1673 * ports of the path
1674 */
1675
1676 if ((CHIP_NUM(bp) == CHIP_NUM_57840) &&
1677 (REG_RD(bp, MISC_REG_RESET_REG_2) &
1678 MISC_REGISTERS_RESET_REG_2_XMAC)) {
1679 DP(NETIF_MSG_LINK,
1680 "XMAC already out of reset in 4-port mode\n");
1681 return;
1682 }
1683
1684 /* Hard reset */
1685 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1686 MISC_REGISTERS_RESET_REG_2_XMAC);
1687 usleep_range(1000, 1000);
1688
1689 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1690 MISC_REGISTERS_RESET_REG_2_XMAC);
1691 if (is_port4mode) {
1692 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n");
1693
1694 /* Set the number of ports on the system side to up to 2 */
1695 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1696
1697 /* Set the number of ports on the Warp Core to 10G */
1698 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1699 } else {
1700 /* Set the number of ports on the system side to 1 */
1701 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0);
1702 if (max_speed == SPEED_10000) {
1703 DP(NETIF_MSG_LINK,
1704 "Init XMAC to 10G x 1 port per path\n");
1705 /* Set the number of ports on the Warp Core to 10G */
1706 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1707 } else {
1708 DP(NETIF_MSG_LINK,
1709 "Init XMAC to 20G x 2 ports per path\n");
1710 /* Set the number of ports on the Warp Core to 20G */
1711 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1);
1712 }
1713 }
1714 /* Soft reset */
1715 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1716 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1717 usleep_range(1000, 1000);
1718
1719 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1720 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1721
1722 }
1723
1724 static void bnx2x_xmac_disable(struct link_params *params)
1725 {
1726 u8 port = params->port;
1727 struct bnx2x *bp = params->bp;
1728 u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1729
1730 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1731 MISC_REGISTERS_RESET_REG_2_XMAC) {
1732 /*
1733 * Send an indication to change the state in the NIG back to XON
1734 * Clearing this bit enables the next set of this bit to get
1735 * rising edge
1736 */
1737 pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI);
1738 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1739 (pfc_ctrl & ~(1<<1)));
1740 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1741 (pfc_ctrl | (1<<1)));
1742 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port);
1743 REG_WR(bp, xmac_base + XMAC_REG_CTRL, 0);
1744 }
1745 }
1746
1747 static int bnx2x_xmac_enable(struct link_params *params,
1748 struct link_vars *vars, u8 lb)
1749 {
1750 u32 val, xmac_base;
1751 struct bnx2x *bp = params->bp;
1752 DP(NETIF_MSG_LINK, "enabling XMAC\n");
1753
1754 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1755
1756 bnx2x_xmac_init(params, vars->line_speed);
1757
1758 /*
1759 * This register determines on which events the MAC will assert
1760 * error on the i/f to the NIG along w/ EOP.
1761 */
1762
1763 /*
1764 * This register tells the NIG whether to send traffic to UMAC
1765 * or XMAC
1766 */
1767 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
1768
1769 /* Set Max packet size */
1770 REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
1771
1772 /* CRC append for Tx packets */
1773 REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
1774
1775 /* update PFC */
1776 bnx2x_update_pfc_xmac(params, vars, 0);
1777
1778 /* Enable TX and RX */
1779 val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
1780
1781 /* Check loopback mode */
1782 if (lb)
1783 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK;
1784 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1785 bnx2x_set_xumac_nig(params,
1786 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1787
1788 vars->mac_type = MAC_TYPE_XMAC;
1789
1790 return 0;
1791 }
1792
1793 static int bnx2x_emac_enable(struct link_params *params,
1794 struct link_vars *vars, u8 lb)
1795 {
1796 struct bnx2x *bp = params->bp;
1797 u8 port = params->port;
1798 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1799 u32 val;
1800
1801 DP(NETIF_MSG_LINK, "enabling EMAC\n");
1802
1803 /* Disable BMAC */
1804 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1805 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1806
1807 /* enable emac and not bmac */
1808 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
1809
1810 /* ASIC */
1811 if (vars->phy_flags & PHY_XGXS_FLAG) {
1812 u32 ser_lane = ((params->lane_config &
1813 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1814 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1815
1816 DP(NETIF_MSG_LINK, "XGXS\n");
1817 /* select the master lanes (out of 0-3) */
1818 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
1819 /* select XGXS */
1820 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
1821
1822 } else { /* SerDes */
1823 DP(NETIF_MSG_LINK, "SerDes\n");
1824 /* select SerDes */
1825 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
1826 }
1827
1828 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1829 EMAC_RX_MODE_RESET);
1830 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1831 EMAC_TX_MODE_RESET);
1832
1833 if (CHIP_REV_IS_SLOW(bp)) {
1834 /* config GMII mode */
1835 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1836 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII));
1837 } else { /* ASIC */
1838 /* pause enable/disable */
1839 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1840 EMAC_RX_MODE_FLOW_EN);
1841
1842 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1843 (EMAC_TX_MODE_EXT_PAUSE_EN |
1844 EMAC_TX_MODE_FLOW_EN));
1845 if (!(params->feature_config_flags &
1846 FEATURE_CONFIG_PFC_ENABLED)) {
1847 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1848 bnx2x_bits_en(bp, emac_base +
1849 EMAC_REG_EMAC_RX_MODE,
1850 EMAC_RX_MODE_FLOW_EN);
1851
1852 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1853 bnx2x_bits_en(bp, emac_base +
1854 EMAC_REG_EMAC_TX_MODE,
1855 (EMAC_TX_MODE_EXT_PAUSE_EN |
1856 EMAC_TX_MODE_FLOW_EN));
1857 } else
1858 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1859 EMAC_TX_MODE_FLOW_EN);
1860 }
1861
1862 /* KEEP_VLAN_TAG, promiscuous */
1863 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
1864 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
1865
1866 /*
1867 * Setting this bit causes MAC control frames (except for pause
1868 * frames) to be passed on for processing. This setting has no
1869 * affect on the operation of the pause frames. This bit effects
1870 * all packets regardless of RX Parser packet sorting logic.
1871 * Turn the PFC off to make sure we are in Xon state before
1872 * enabling it.
1873 */
1874 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
1875 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1876 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1877 /* Enable PFC again */
1878 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
1879 EMAC_REG_RX_PFC_MODE_RX_EN |
1880 EMAC_REG_RX_PFC_MODE_TX_EN |
1881 EMAC_REG_RX_PFC_MODE_PRIORITIES);
1882
1883 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
1884 ((0x0101 <<
1885 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
1886 (0x00ff <<
1887 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
1888 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
1889 }
1890 EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
1891
1892 /* Set Loopback */
1893 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1894 if (lb)
1895 val |= 0x810;
1896 else
1897 val &= ~0x810;
1898 EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
1899
1900 /* enable emac */
1901 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
1902
1903 /* enable emac for jumbo packets */
1904 EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
1905 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
1906 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
1907
1908 /* strip CRC */
1909 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
1910
1911 /* disable the NIG in/out to the bmac */
1912 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
1913 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
1914 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
1915
1916 /* enable the NIG in/out to the emac */
1917 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
1918 val = 0;
1919 if ((params->feature_config_flags &
1920 FEATURE_CONFIG_PFC_ENABLED) ||
1921 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1922 val = 1;
1923
1924 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
1925 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
1926
1927 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
1928
1929 vars->mac_type = MAC_TYPE_EMAC;
1930 return 0;
1931 }
1932
1933 static void bnx2x_update_pfc_bmac1(struct link_params *params,
1934 struct link_vars *vars)
1935 {
1936 u32 wb_data[2];
1937 struct bnx2x *bp = params->bp;
1938 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1939 NIG_REG_INGRESS_BMAC0_MEM;
1940
1941 u32 val = 0x14;
1942 if ((!(params->feature_config_flags &
1943 FEATURE_CONFIG_PFC_ENABLED)) &&
1944 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1945 /* Enable BigMAC to react on received Pause packets */
1946 val |= (1<<5);
1947 wb_data[0] = val;
1948 wb_data[1] = 0;
1949 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
1950
1951 /* tx control */
1952 val = 0xc0;
1953 if (!(params->feature_config_flags &
1954 FEATURE_CONFIG_PFC_ENABLED) &&
1955 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1956 val |= 0x800000;
1957 wb_data[0] = val;
1958 wb_data[1] = 0;
1959 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
1960 }
1961
1962 static void bnx2x_update_pfc_bmac2(struct link_params *params,
1963 struct link_vars *vars,
1964 u8 is_lb)
1965 {
1966 /*
1967 * Set rx control: Strip CRC and enable BigMAC to relay
1968 * control packets to the system as well
1969 */
1970 u32 wb_data[2];
1971 struct bnx2x *bp = params->bp;
1972 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1973 NIG_REG_INGRESS_BMAC0_MEM;
1974 u32 val = 0x14;
1975
1976 if ((!(params->feature_config_flags &
1977 FEATURE_CONFIG_PFC_ENABLED)) &&
1978 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1979 /* Enable BigMAC to react on received Pause packets */
1980 val |= (1<<5);
1981 wb_data[0] = val;
1982 wb_data[1] = 0;
1983 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
1984 udelay(30);
1985
1986 /* Tx control */
1987 val = 0xc0;
1988 if (!(params->feature_config_flags &
1989 FEATURE_CONFIG_PFC_ENABLED) &&
1990 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1991 val |= 0x800000;
1992 wb_data[0] = val;
1993 wb_data[1] = 0;
1994 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
1995
1996 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1997 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1998 /* Enable PFC RX & TX & STATS and set 8 COS */
1999 wb_data[0] = 0x0;
2000 wb_data[0] |= (1<<0); /* RX */
2001 wb_data[0] |= (1<<1); /* TX */
2002 wb_data[0] |= (1<<2); /* Force initial Xon */
2003 wb_data[0] |= (1<<3); /* 8 cos */
2004 wb_data[0] |= (1<<5); /* STATS */
2005 wb_data[1] = 0;
2006 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
2007 wb_data, 2);
2008 /* Clear the force Xon */
2009 wb_data[0] &= ~(1<<2);
2010 } else {
2011 DP(NETIF_MSG_LINK, "PFC is disabled\n");
2012 /* disable PFC RX & TX & STATS and set 8 COS */
2013 wb_data[0] = 0x8;
2014 wb_data[1] = 0;
2015 }
2016
2017 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
2018
2019 /*
2020 * Set Time (based unit is 512 bit time) between automatic
2021 * re-sending of PP packets amd enable automatic re-send of
2022 * Per-Priroity Packet as long as pp_gen is asserted and
2023 * pp_disable is low.
2024 */
2025 val = 0x8000;
2026 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2027 val |= (1<<16); /* enable automatic re-send */
2028
2029 wb_data[0] = val;
2030 wb_data[1] = 0;
2031 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
2032 wb_data, 2);
2033
2034 /* mac control */
2035 val = 0x3; /* Enable RX and TX */
2036 if (is_lb) {
2037 val |= 0x4; /* Local loopback */
2038 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2039 }
2040 /* When PFC enabled, Pass pause frames towards the NIG. */
2041 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2042 val |= ((1<<6)|(1<<5));
2043
2044 wb_data[0] = val;
2045 wb_data[1] = 0;
2046 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2047 }
2048
2049 /* PFC BRB internal port configuration params */
2050 struct bnx2x_pfc_brb_threshold_val {
2051 u32 pause_xoff;
2052 u32 pause_xon;
2053 u32 full_xoff;
2054 u32 full_xon;
2055 };
2056
2057 struct bnx2x_pfc_brb_e3b0_val {
2058 u32 per_class_guaranty_mode;
2059 u32 lb_guarantied_hyst;
2060 u32 full_lb_xoff_th;
2061 u32 full_lb_xon_threshold;
2062 u32 lb_guarantied;
2063 u32 mac_0_class_t_guarantied;
2064 u32 mac_0_class_t_guarantied_hyst;
2065 u32 mac_1_class_t_guarantied;
2066 u32 mac_1_class_t_guarantied_hyst;
2067 };
2068
2069 struct bnx2x_pfc_brb_th_val {
2070 struct bnx2x_pfc_brb_threshold_val pauseable_th;
2071 struct bnx2x_pfc_brb_threshold_val non_pauseable_th;
2072 struct bnx2x_pfc_brb_threshold_val default_class0;
2073 struct bnx2x_pfc_brb_threshold_val default_class1;
2074
2075 };
2076 static int bnx2x_pfc_brb_get_config_params(
2077 struct link_params *params,
2078 struct bnx2x_pfc_brb_th_val *config_val)
2079 {
2080 struct bnx2x *bp = params->bp;
2081 DP(NETIF_MSG_LINK, "Setting PFC BRB configuration\n");
2082
2083 config_val->default_class1.pause_xoff = 0;
2084 config_val->default_class1.pause_xon = 0;
2085 config_val->default_class1.full_xoff = 0;
2086 config_val->default_class1.full_xon = 0;
2087
2088 if (CHIP_IS_E2(bp)) {
2089 /* class0 defaults */
2090 config_val->default_class0.pause_xoff =
2091 DEFAULT0_E2_BRB_MAC_PAUSE_XOFF_THR;
2092 config_val->default_class0.pause_xon =
2093 DEFAULT0_E2_BRB_MAC_PAUSE_XON_THR;
2094 config_val->default_class0.full_xoff =
2095 DEFAULT0_E2_BRB_MAC_FULL_XOFF_THR;
2096 config_val->default_class0.full_xon =
2097 DEFAULT0_E2_BRB_MAC_FULL_XON_THR;
2098 /* pause able*/
2099 config_val->pauseable_th.pause_xoff =
2100 PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2101 config_val->pauseable_th.pause_xon =
2102 PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE;
2103 config_val->pauseable_th.full_xoff =
2104 PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE;
2105 config_val->pauseable_th.full_xon =
2106 PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE;
2107 /* non pause able*/
2108 config_val->non_pauseable_th.pause_xoff =
2109 PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2110 config_val->non_pauseable_th.pause_xon =
2111 PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2112 config_val->non_pauseable_th.full_xoff =
2113 PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2114 config_val->non_pauseable_th.full_xon =
2115 PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2116 } else if (CHIP_IS_E3A0(bp)) {
2117 /* class0 defaults */
2118 config_val->default_class0.pause_xoff =
2119 DEFAULT0_E3A0_BRB_MAC_PAUSE_XOFF_THR;
2120 config_val->default_class0.pause_xon =
2121 DEFAULT0_E3A0_BRB_MAC_PAUSE_XON_THR;
2122 config_val->default_class0.full_xoff =
2123 DEFAULT0_E3A0_BRB_MAC_FULL_XOFF_THR;
2124 config_val->default_class0.full_xon =
2125 DEFAULT0_E3A0_BRB_MAC_FULL_XON_THR;
2126 /* pause able */
2127 config_val->pauseable_th.pause_xoff =
2128 PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2129 config_val->pauseable_th.pause_xon =
2130 PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE;
2131 config_val->pauseable_th.full_xoff =
2132 PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE;
2133 config_val->pauseable_th.full_xon =
2134 PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE;
2135 /* non pause able*/
2136 config_val->non_pauseable_th.pause_xoff =
2137 PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2138 config_val->non_pauseable_th.pause_xon =
2139 PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2140 config_val->non_pauseable_th.full_xoff =
2141 PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2142 config_val->non_pauseable_th.full_xon =
2143 PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2144 } else if (CHIP_IS_E3B0(bp)) {
2145 /* class0 defaults */
2146 config_val->default_class0.pause_xoff =
2147 DEFAULT0_E3B0_BRB_MAC_PAUSE_XOFF_THR;
2148 config_val->default_class0.pause_xon =
2149 DEFAULT0_E3B0_BRB_MAC_PAUSE_XON_THR;
2150 config_val->default_class0.full_xoff =
2151 DEFAULT0_E3B0_BRB_MAC_FULL_XOFF_THR;
2152 config_val->default_class0.full_xon =
2153 DEFAULT0_E3B0_BRB_MAC_FULL_XON_THR;
2154
2155 if (params->phy[INT_PHY].flags &
2156 FLAGS_4_PORT_MODE) {
2157 config_val->pauseable_th.pause_xoff =
2158 PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2159 config_val->pauseable_th.pause_xon =
2160 PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2161 config_val->pauseable_th.full_xoff =
2162 PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2163 config_val->pauseable_th.full_xon =
2164 PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE;
2165 /* non pause able*/
2166 config_val->non_pauseable_th.pause_xoff =
2167 PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2168 config_val->non_pauseable_th.pause_xon =
2169 PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2170 config_val->non_pauseable_th.full_xoff =
2171 PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2172 config_val->non_pauseable_th.full_xon =
2173 PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2174 } else {
2175 config_val->pauseable_th.pause_xoff =
2176 PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2177 config_val->pauseable_th.pause_xon =
2178 PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2179 config_val->pauseable_th.full_xoff =
2180 PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2181 config_val->pauseable_th.full_xon =
2182 PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE;
2183 /* non pause able*/
2184 config_val->non_pauseable_th.pause_xoff =
2185 PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2186 config_val->non_pauseable_th.pause_xon =
2187 PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2188 config_val->non_pauseable_th.full_xoff =
2189 PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2190 config_val->non_pauseable_th.full_xon =
2191 PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2192 }
2193 } else
2194 return -EINVAL;
2195
2196 return 0;
2197 }
2198
2199 static void bnx2x_pfc_brb_get_e3b0_config_params(
2200 struct link_params *params,
2201 struct bnx2x_pfc_brb_e3b0_val
2202 *e3b0_val,
2203 struct bnx2x_nig_brb_pfc_port_params *pfc_params,
2204 const u8 pfc_enabled)
2205 {
2206 if (pfc_enabled && pfc_params) {
2207 e3b0_val->per_class_guaranty_mode = 1;
2208 e3b0_val->lb_guarantied_hyst = 80;
2209
2210 if (params->phy[INT_PHY].flags &
2211 FLAGS_4_PORT_MODE) {
2212 e3b0_val->full_lb_xoff_th =
2213 PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR;
2214 e3b0_val->full_lb_xon_threshold =
2215 PFC_E3B0_4P_BRB_FULL_LB_XON_THR;
2216 e3b0_val->lb_guarantied =
2217 PFC_E3B0_4P_LB_GUART;
2218 e3b0_val->mac_0_class_t_guarantied =
2219 PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART;
2220 e3b0_val->mac_0_class_t_guarantied_hyst =
2221 PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST;
2222 e3b0_val->mac_1_class_t_guarantied =
2223 PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART;
2224 e3b0_val->mac_1_class_t_guarantied_hyst =
2225 PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST;
2226 } else {
2227 e3b0_val->full_lb_xoff_th =
2228 PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR;
2229 e3b0_val->full_lb_xon_threshold =
2230 PFC_E3B0_2P_BRB_FULL_LB_XON_THR;
2231 e3b0_val->mac_0_class_t_guarantied_hyst =
2232 PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST;
2233 e3b0_val->mac_1_class_t_guarantied =
2234 PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART;
2235 e3b0_val->mac_1_class_t_guarantied_hyst =
2236 PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST;
2237
2238 if (pfc_params->cos0_pauseable !=
2239 pfc_params->cos1_pauseable) {
2240 /* nonpauseable= Lossy + pauseable = Lossless*/
2241 e3b0_val->lb_guarantied =
2242 PFC_E3B0_2P_MIX_PAUSE_LB_GUART;
2243 e3b0_val->mac_0_class_t_guarantied =
2244 PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART;
2245 } else if (pfc_params->cos0_pauseable) {
2246 /* Lossless +Lossless*/
2247 e3b0_val->lb_guarantied =
2248 PFC_E3B0_2P_PAUSE_LB_GUART;
2249 e3b0_val->mac_0_class_t_guarantied =
2250 PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART;
2251 } else {
2252 /* Lossy +Lossy*/
2253 e3b0_val->lb_guarantied =
2254 PFC_E3B0_2P_NON_PAUSE_LB_GUART;
2255 e3b0_val->mac_0_class_t_guarantied =
2256 PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART;
2257 }
2258 }
2259 } else {
2260 e3b0_val->per_class_guaranty_mode = 0;
2261 e3b0_val->lb_guarantied_hyst = 0;
2262 e3b0_val->full_lb_xoff_th =
2263 DEFAULT_E3B0_BRB_FULL_LB_XOFF_THR;
2264 e3b0_val->full_lb_xon_threshold =
2265 DEFAULT_E3B0_BRB_FULL_LB_XON_THR;
2266 e3b0_val->lb_guarantied =
2267 DEFAULT_E3B0_LB_GUART;
2268 e3b0_val->mac_0_class_t_guarantied =
2269 DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART;
2270 e3b0_val->mac_0_class_t_guarantied_hyst =
2271 DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART_HYST;
2272 e3b0_val->mac_1_class_t_guarantied =
2273 DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART;
2274 e3b0_val->mac_1_class_t_guarantied_hyst =
2275 DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART_HYST;
2276 }
2277 }
2278 static int bnx2x_update_pfc_brb(struct link_params *params,
2279 struct link_vars *vars,
2280 struct bnx2x_nig_brb_pfc_port_params
2281 *pfc_params)
2282 {
2283 struct bnx2x *bp = params->bp;
2284 struct bnx2x_pfc_brb_th_val config_val = { {0} };
2285 struct bnx2x_pfc_brb_threshold_val *reg_th_config =
2286 &config_val.pauseable_th;
2287 struct bnx2x_pfc_brb_e3b0_val e3b0_val = {0};
2288 const int set_pfc = params->feature_config_flags &
2289 FEATURE_CONFIG_PFC_ENABLED;
2290 const u8 pfc_enabled = (set_pfc && pfc_params);
2291 int bnx2x_status = 0;
2292 u8 port = params->port;
2293
2294 /* default - pause configuration */
2295 reg_th_config = &config_val.pauseable_th;
2296 bnx2x_status = bnx2x_pfc_brb_get_config_params(params, &config_val);
2297 if (bnx2x_status)
2298 return bnx2x_status;
2299
2300 if (pfc_enabled) {
2301 /* First COS */
2302 if (pfc_params->cos0_pauseable)
2303 reg_th_config = &config_val.pauseable_th;
2304 else
2305 reg_th_config = &config_val.non_pauseable_th;
2306 } else
2307 reg_th_config = &config_val.default_class0;
2308 /*
2309 * The number of free blocks below which the pause signal to class 0
2310 * of MAC #n is asserted. n=0,1
2311 */
2312 REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 :
2313 BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 ,
2314 reg_th_config->pause_xoff);
2315 /*
2316 * The number of free blocks above which the pause signal to class 0
2317 * of MAC #n is de-asserted. n=0,1
2318 */
2319 REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XON_THRESHOLD_1 :
2320 BRB1_REG_PAUSE_0_XON_THRESHOLD_0 , reg_th_config->pause_xon);
2321 /*
2322 * The number of free blocks below which the full signal to class 0
2323 * of MAC #n is asserted. n=0,1
2324 */
2325 REG_WR(bp, (port) ? BRB1_REG_FULL_0_XOFF_THRESHOLD_1 :
2326 BRB1_REG_FULL_0_XOFF_THRESHOLD_0 , reg_th_config->full_xoff);
2327 /*
2328 * The number of free blocks above which the full signal to class 0
2329 * of MAC #n is de-asserted. n=0,1
2330 */
2331 REG_WR(bp, (port) ? BRB1_REG_FULL_0_XON_THRESHOLD_1 :
2332 BRB1_REG_FULL_0_XON_THRESHOLD_0 , reg_th_config->full_xon);
2333
2334 if (pfc_enabled) {
2335 /* Second COS */
2336 if (pfc_params->cos1_pauseable)
2337 reg_th_config = &config_val.pauseable_th;
2338 else
2339 reg_th_config = &config_val.non_pauseable_th;
2340 } else
2341 reg_th_config = &config_val.default_class1;
2342 /*
2343 * The number of free blocks below which the pause signal to
2344 * class 1 of MAC #n is asserted. n=0,1
2345 */
2346 REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 :
2347 BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0,
2348 reg_th_config->pause_xoff);
2349
2350 /*
2351 * The number of free blocks above which the pause signal to
2352 * class 1 of MAC #n is de-asserted. n=0,1
2353 */
2354 REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XON_THRESHOLD_1 :
2355 BRB1_REG_PAUSE_1_XON_THRESHOLD_0,
2356 reg_th_config->pause_xon);
2357 /*
2358 * The number of free blocks below which the full signal to
2359 * class 1 of MAC #n is asserted. n=0,1
2360 */
2361 REG_WR(bp, (port) ? BRB1_REG_FULL_1_XOFF_THRESHOLD_1 :
2362 BRB1_REG_FULL_1_XOFF_THRESHOLD_0,
2363 reg_th_config->full_xoff);
2364 /*
2365 * The number of free blocks above which the full signal to
2366 * class 1 of MAC #n is de-asserted. n=0,1
2367 */
2368 REG_WR(bp, (port) ? BRB1_REG_FULL_1_XON_THRESHOLD_1 :
2369 BRB1_REG_FULL_1_XON_THRESHOLD_0,
2370 reg_th_config->full_xon);
2371
2372 if (CHIP_IS_E3B0(bp)) {
2373 bnx2x_pfc_brb_get_e3b0_config_params(
2374 params,
2375 &e3b0_val,
2376 pfc_params,
2377 pfc_enabled);
2378
2379 REG_WR(bp, BRB1_REG_PER_CLASS_GUARANTY_MODE,
2380 e3b0_val.per_class_guaranty_mode);
2381
2382 /*
2383 * The hysteresis on the guarantied buffer space for the Lb
2384 * port before signaling XON.
2385 */
2386 REG_WR(bp, BRB1_REG_LB_GUARANTIED_HYST,
2387 e3b0_val.lb_guarantied_hyst);
2388
2389 /*
2390 * The number of free blocks below which the full signal to the
2391 * LB port is asserted.
2392 */
2393 REG_WR(bp, BRB1_REG_FULL_LB_XOFF_THRESHOLD,
2394 e3b0_val.full_lb_xoff_th);
2395 /*
2396 * The number of free blocks above which the full signal to the
2397 * LB port is de-asserted.
2398 */
2399 REG_WR(bp, BRB1_REG_FULL_LB_XON_THRESHOLD,
2400 e3b0_val.full_lb_xon_threshold);
2401 /*
2402 * The number of blocks guarantied for the MAC #n port. n=0,1
2403 */
2404
2405 /* The number of blocks guarantied for the LB port.*/
2406 REG_WR(bp, BRB1_REG_LB_GUARANTIED,
2407 e3b0_val.lb_guarantied);
2408
2409 /*
2410 * The number of blocks guarantied for the MAC #n port.
2411 */
2412 REG_WR(bp, BRB1_REG_MAC_GUARANTIED_0,
2413 2 * e3b0_val.mac_0_class_t_guarantied);
2414 REG_WR(bp, BRB1_REG_MAC_GUARANTIED_1,
2415 2 * e3b0_val.mac_1_class_t_guarantied);
2416 /*
2417 * The number of blocks guarantied for class #t in MAC0. t=0,1
2418 */
2419 REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED,
2420 e3b0_val.mac_0_class_t_guarantied);
2421 REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED,
2422 e3b0_val.mac_0_class_t_guarantied);
2423 /*
2424 * The hysteresis on the guarantied buffer space for class in
2425 * MAC0. t=0,1
2426 */
2427 REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST,
2428 e3b0_val.mac_0_class_t_guarantied_hyst);
2429 REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST,
2430 e3b0_val.mac_0_class_t_guarantied_hyst);
2431
2432 /*
2433 * The number of blocks guarantied for class #t in MAC1.t=0,1
2434 */
2435 REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED,
2436 e3b0_val.mac_1_class_t_guarantied);
2437 REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED,
2438 e3b0_val.mac_1_class_t_guarantied);
2439 /*
2440 * The hysteresis on the guarantied buffer space for class #t
2441 * in MAC1. t=0,1
2442 */
2443 REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST,
2444 e3b0_val.mac_1_class_t_guarantied_hyst);
2445 REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST,
2446 e3b0_val.mac_1_class_t_guarantied_hyst);
2447 }
2448
2449 return bnx2x_status;
2450 }
2451
2452 /******************************************************************************
2453 * Description:
2454 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
2455 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
2456 ******************************************************************************/
2457 int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp,
2458 u8 cos_entry,
2459 u32 priority_mask, u8 port)
2460 {
2461 u32 nig_reg_rx_priority_mask_add = 0;
2462
2463 switch (cos_entry) {
2464 case 0:
2465 nig_reg_rx_priority_mask_add = (port) ?
2466 NIG_REG_P1_RX_COS0_PRIORITY_MASK :
2467 NIG_REG_P0_RX_COS0_PRIORITY_MASK;
2468 break;
2469 case 1:
2470 nig_reg_rx_priority_mask_add = (port) ?
2471 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
2472 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
2473 break;
2474 case 2:
2475 nig_reg_rx_priority_mask_add = (port) ?
2476 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
2477 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
2478 break;
2479 case 3:
2480 if (port)
2481 return -EINVAL;
2482 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
2483 break;
2484 case 4:
2485 if (port)
2486 return -EINVAL;
2487 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
2488 break;
2489 case 5:
2490 if (port)
2491 return -EINVAL;
2492 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
2493 break;
2494 }
2495
2496 REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask);
2497
2498 return 0;
2499 }
2500 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
2501 {
2502 struct bnx2x *bp = params->bp;
2503
2504 REG_WR(bp, params->shmem_base +
2505 offsetof(struct shmem_region,
2506 port_mb[params->port].link_status), link_status);
2507 }
2508
2509 static void bnx2x_update_pfc_nig(struct link_params *params,
2510 struct link_vars *vars,
2511 struct bnx2x_nig_brb_pfc_port_params *nig_params)
2512 {
2513 u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
2514 u32 llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0;
2515 u32 pkt_priority_to_cos = 0;
2516 struct bnx2x *bp = params->bp;
2517 u8 port = params->port;
2518
2519 int set_pfc = params->feature_config_flags &
2520 FEATURE_CONFIG_PFC_ENABLED;
2521 DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
2522
2523 /*
2524 * When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
2525 * MAC control frames (that are not pause packets)
2526 * will be forwarded to the XCM.
2527 */
2528 xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK :
2529 NIG_REG_LLH0_XCM_MASK);
2530 /*
2531 * nig params will override non PFC params, since it's possible to
2532 * do transition from PFC to SAFC
2533 */
2534 if (set_pfc) {
2535 pause_enable = 0;
2536 llfc_out_en = 0;
2537 llfc_enable = 0;
2538 if (CHIP_IS_E3(bp))
2539 ppp_enable = 0;
2540 else
2541 ppp_enable = 1;
2542 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2543 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2544 xcm_out_en = 0;
2545 hwpfc_enable = 1;
2546 } else {
2547 if (nig_params) {
2548 llfc_out_en = nig_params->llfc_out_en;
2549 llfc_enable = nig_params->llfc_enable;
2550 pause_enable = nig_params->pause_enable;
2551 } else /*defaul non PFC mode - PAUSE */
2552 pause_enable = 1;
2553
2554 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2555 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2556 xcm_out_en = 1;
2557 }
2558
2559 if (CHIP_IS_E3(bp))
2560 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN :
2561 NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
2562 REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
2563 NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
2564 REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
2565 NIG_REG_LLFC_ENABLE_0, llfc_enable);
2566 REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
2567 NIG_REG_PAUSE_ENABLE_0, pause_enable);
2568
2569 REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
2570 NIG_REG_PPP_ENABLE_0, ppp_enable);
2571
2572 REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
2573 NIG_REG_LLH0_XCM_MASK, xcm_mask);
2574
2575 REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 :
2576 NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
2577
2578 /* output enable for RX_XCM # IF */
2579 REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN :
2580 NIG_REG_XCM0_OUT_EN, xcm_out_en);
2581
2582 /* HW PFC TX enable */
2583 REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE :
2584 NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable);
2585
2586 if (nig_params) {
2587 u8 i = 0;
2588 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
2589
2590 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
2591 bnx2x_pfc_nig_rx_priority_mask(bp, i,
2592 nig_params->rx_cos_priority_mask[i], port);
2593
2594 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
2595 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
2596 nig_params->llfc_high_priority_classes);
2597
2598 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
2599 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
2600 nig_params->llfc_low_priority_classes);
2601 }
2602 REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
2603 NIG_REG_P0_PKT_PRIORITY_TO_COS,
2604 pkt_priority_to_cos);
2605 }
2606
2607 int bnx2x_update_pfc(struct link_params *params,
2608 struct link_vars *vars,
2609 struct bnx2x_nig_brb_pfc_port_params *pfc_params)
2610 {
2611 /*
2612 * The PFC and pause are orthogonal to one another, meaning when
2613 * PFC is enabled, the pause are disabled, and when PFC is
2614 * disabled, pause are set according to the pause result.
2615 */
2616 u32 val;
2617 struct bnx2x *bp = params->bp;
2618 int bnx2x_status = 0;
2619 u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC);
2620
2621 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2622 vars->link_status |= LINK_STATUS_PFC_ENABLED;
2623 else
2624 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
2625
2626 bnx2x_update_mng(params, vars->link_status);
2627
2628 /* update NIG params */
2629 bnx2x_update_pfc_nig(params, vars, pfc_params);
2630
2631 /* update BRB params */
2632 bnx2x_status = bnx2x_update_pfc_brb(params, vars, pfc_params);
2633 if (bnx2x_status)
2634 return bnx2x_status;
2635
2636 if (!vars->link_up)
2637 return bnx2x_status;
2638
2639 DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
2640 if (CHIP_IS_E3(bp))
2641 bnx2x_update_pfc_xmac(params, vars, 0);
2642 else {
2643 val = REG_RD(bp, MISC_REG_RESET_REG_2);
2644 if ((val &
2645 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
2646 == 0) {
2647 DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
2648 bnx2x_emac_enable(params, vars, 0);
2649 return bnx2x_status;
2650 }
2651 if (CHIP_IS_E2(bp))
2652 bnx2x_update_pfc_bmac2(params, vars, bmac_loopback);
2653 else
2654 bnx2x_update_pfc_bmac1(params, vars);
2655
2656 val = 0;
2657 if ((params->feature_config_flags &
2658 FEATURE_CONFIG_PFC_ENABLED) ||
2659 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2660 val = 1;
2661 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
2662 }
2663 return bnx2x_status;
2664 }
2665
2666
2667 static int bnx2x_bmac1_enable(struct link_params *params,
2668 struct link_vars *vars,
2669 u8 is_lb)
2670 {
2671 struct bnx2x *bp = params->bp;
2672 u8 port = params->port;
2673 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2674 NIG_REG_INGRESS_BMAC0_MEM;
2675 u32 wb_data[2];
2676 u32 val;
2677
2678 DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
2679
2680 /* XGXS control */
2681 wb_data[0] = 0x3c;
2682 wb_data[1] = 0;
2683 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2684 wb_data, 2);
2685
2686 /* tx MAC SA */
2687 wb_data[0] = ((params->mac_addr[2] << 24) |
2688 (params->mac_addr[3] << 16) |
2689 (params->mac_addr[4] << 8) |
2690 params->mac_addr[5]);
2691 wb_data[1] = ((params->mac_addr[0] << 8) |
2692 params->mac_addr[1]);
2693 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
2694
2695 /* mac control */
2696 val = 0x3;
2697 if (is_lb) {
2698 val |= 0x4;
2699 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2700 }
2701 wb_data[0] = val;
2702 wb_data[1] = 0;
2703 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
2704
2705 /* set rx mtu */
2706 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2707 wb_data[1] = 0;
2708 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
2709
2710 bnx2x_update_pfc_bmac1(params, vars);
2711
2712 /* set tx mtu */
2713 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2714 wb_data[1] = 0;
2715 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
2716
2717 /* set cnt max size */
2718 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2719 wb_data[1] = 0;
2720 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2721
2722 /* configure safc */
2723 wb_data[0] = 0x1000200;
2724 wb_data[1] = 0;
2725 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
2726 wb_data, 2);
2727
2728 return 0;
2729 }
2730
2731 static int bnx2x_bmac2_enable(struct link_params *params,
2732 struct link_vars *vars,
2733 u8 is_lb)
2734 {
2735 struct bnx2x *bp = params->bp;
2736 u8 port = params->port;
2737 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2738 NIG_REG_INGRESS_BMAC0_MEM;
2739 u32 wb_data[2];
2740
2741 DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
2742
2743 wb_data[0] = 0;
2744 wb_data[1] = 0;
2745 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2746 udelay(30);
2747
2748 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2749 wb_data[0] = 0x3c;
2750 wb_data[1] = 0;
2751 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
2752 wb_data, 2);
2753
2754 udelay(30);
2755
2756 /* tx MAC SA */
2757 wb_data[0] = ((params->mac_addr[2] << 24) |
2758 (params->mac_addr[3] << 16) |
2759 (params->mac_addr[4] << 8) |
2760 params->mac_addr[5]);
2761 wb_data[1] = ((params->mac_addr[0] << 8) |
2762 params->mac_addr[1]);
2763 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
2764 wb_data, 2);
2765
2766 udelay(30);
2767
2768 /* Configure SAFC */
2769 wb_data[0] = 0x1000200;
2770 wb_data[1] = 0;
2771 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
2772 wb_data, 2);
2773 udelay(30);
2774
2775 /* set rx mtu */
2776 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2777 wb_data[1] = 0;
2778 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
2779 udelay(30);
2780
2781 /* set tx mtu */
2782 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2783 wb_data[1] = 0;
2784 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
2785 udelay(30);
2786 /* set cnt max size */
2787 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
2788 wb_data[1] = 0;
2789 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2790 udelay(30);
2791 bnx2x_update_pfc_bmac2(params, vars, is_lb);
2792
2793 return 0;
2794 }
2795
2796 static int bnx2x_bmac_enable(struct link_params *params,
2797 struct link_vars *vars,
2798 u8 is_lb)
2799 {
2800 int rc = 0;
2801 u8 port = params->port;
2802 struct bnx2x *bp = params->bp;
2803 u32 val;
2804 /* reset and unreset the BigMac */
2805 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2806 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2807 msleep(1);
2808
2809 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2810 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2811
2812 /* enable access for bmac registers */
2813 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2814
2815 /* Enable BMAC according to BMAC type*/
2816 if (CHIP_IS_E2(bp))
2817 rc = bnx2x_bmac2_enable(params, vars, is_lb);
2818 else
2819 rc = bnx2x_bmac1_enable(params, vars, is_lb);
2820 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
2821 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
2822 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
2823 val = 0;
2824 if ((params->feature_config_flags &
2825 FEATURE_CONFIG_PFC_ENABLED) ||
2826 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2827 val = 1;
2828 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
2829 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
2830 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
2831 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
2832 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
2833 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
2834
2835 vars->mac_type = MAC_TYPE_BMAC;
2836 return rc;
2837 }
2838
2839 static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
2840 {
2841 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2842 NIG_REG_INGRESS_BMAC0_MEM;
2843 u32 wb_data[2];
2844 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
2845
2846 /* Only if the bmac is out of reset */
2847 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
2848 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
2849 nig_bmac_enable) {
2850
2851 if (CHIP_IS_E2(bp)) {
2852 /* Clear Rx Enable bit in BMAC_CONTROL register */
2853 REG_RD_DMAE(bp, bmac_addr +
2854 BIGMAC2_REGISTER_BMAC_CONTROL,
2855 wb_data, 2);
2856 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2857 REG_WR_DMAE(bp, bmac_addr +
2858 BIGMAC2_REGISTER_BMAC_CONTROL,
2859 wb_data, 2);
2860 } else {
2861 /* Clear Rx Enable bit in BMAC_CONTROL register */
2862 REG_RD_DMAE(bp, bmac_addr +
2863 BIGMAC_REGISTER_BMAC_CONTROL,
2864 wb_data, 2);
2865 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2866 REG_WR_DMAE(bp, bmac_addr +
2867 BIGMAC_REGISTER_BMAC_CONTROL,
2868 wb_data, 2);
2869 }
2870 msleep(1);
2871 }
2872 }
2873
2874 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
2875 u32 line_speed)
2876 {
2877 struct bnx2x *bp = params->bp;
2878 u8 port = params->port;
2879 u32 init_crd, crd;
2880 u32 count = 1000;
2881
2882 /* disable port */
2883 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
2884
2885 /* wait for init credit */
2886 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
2887 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2888 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd);
2889
2890 while ((init_crd != crd) && count) {
2891 msleep(5);
2892
2893 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2894 count--;
2895 }
2896 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2897 if (init_crd != crd) {
2898 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
2899 init_crd, crd);
2900 return -EINVAL;
2901 }
2902
2903 if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
2904 line_speed == SPEED_10 ||
2905 line_speed == SPEED_100 ||
2906 line_speed == SPEED_1000 ||
2907 line_speed == SPEED_2500) {
2908 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
2909 /* update threshold */
2910 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
2911 /* update init credit */
2912 init_crd = 778; /* (800-18-4) */
2913
2914 } else {
2915 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
2916 ETH_OVREHEAD)/16;
2917 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
2918 /* update threshold */
2919 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
2920 /* update init credit */
2921 switch (line_speed) {
2922 case SPEED_10000:
2923 init_crd = thresh + 553 - 22;
2924 break;
2925 default:
2926 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2927 line_speed);
2928 return -EINVAL;
2929 }
2930 }
2931 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
2932 DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
2933 line_speed, init_crd);
2934
2935 /* probe the credit changes */
2936 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
2937 msleep(5);
2938 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
2939
2940 /* enable port */
2941 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
2942 return 0;
2943 }
2944
2945 /**
2946 * bnx2x_get_emac_base - retrive emac base address
2947 *
2948 * @bp: driver handle
2949 * @mdc_mdio_access: access type
2950 * @port: port id
2951 *
2952 * This function selects the MDC/MDIO access (through emac0 or
2953 * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2954 * phy has a default access mode, which could also be overridden
2955 * by nvram configuration. This parameter, whether this is the
2956 * default phy configuration, or the nvram overrun
2957 * configuration, is passed here as mdc_mdio_access and selects
2958 * the emac_base for the CL45 read/writes operations
2959 */
2960 static u32 bnx2x_get_emac_base(struct bnx2x *bp,
2961 u32 mdc_mdio_access, u8 port)
2962 {
2963 u32 emac_base = 0;
2964 switch (mdc_mdio_access) {
2965 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
2966 break;
2967 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
2968 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2969 emac_base = GRCBASE_EMAC1;
2970 else
2971 emac_base = GRCBASE_EMAC0;
2972 break;
2973 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
2974 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2975 emac_base = GRCBASE_EMAC0;
2976 else
2977 emac_base = GRCBASE_EMAC1;
2978 break;
2979 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
2980 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2981 break;
2982 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
2983 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
2984 break;
2985 default:
2986 break;
2987 }
2988 return emac_base;
2989
2990 }
2991
2992 /******************************************************************/
2993 /* CL22 access functions */
2994 /******************************************************************/
2995 static int bnx2x_cl22_write(struct bnx2x *bp,
2996 struct bnx2x_phy *phy,
2997 u16 reg, u16 val)
2998 {
2999 u32 tmp, mode;
3000 u8 i;
3001 int rc = 0;
3002 /* Switch to CL22 */
3003 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
3004 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
3005 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
3006
3007 /* address */
3008 tmp = ((phy->addr << 21) | (reg << 16) | val |
3009 EMAC_MDIO_COMM_COMMAND_WRITE_22 |
3010 EMAC_MDIO_COMM_START_BUSY);
3011 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3012
3013 for (i = 0; i < 50; i++) {
3014 udelay(10);
3015
3016 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3017 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3018 udelay(5);
3019 break;
3020 }
3021 }
3022 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3023 DP(NETIF_MSG_LINK, "write phy register failed\n");
3024 rc = -EFAULT;
3025 }
3026 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
3027 return rc;
3028 }
3029
3030 static int bnx2x_cl22_read(struct bnx2x *bp,
3031 struct bnx2x_phy *phy,
3032 u16 reg, u16 *ret_val)
3033 {
3034 u32 val, mode;
3035 u16 i;
3036 int rc = 0;
3037
3038 /* Switch to CL22 */
3039 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
3040 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
3041 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
3042
3043 /* address */
3044 val = ((phy->addr << 21) | (reg << 16) |
3045 EMAC_MDIO_COMM_COMMAND_READ_22 |
3046 EMAC_MDIO_COMM_START_BUSY);
3047 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
3048
3049 for (i = 0; i < 50; i++) {
3050 udelay(10);
3051
3052 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3053 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
3054 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
3055 udelay(5);
3056 break;
3057 }
3058 }
3059 if (val & EMAC_MDIO_COMM_START_BUSY) {
3060 DP(NETIF_MSG_LINK, "read phy register failed\n");
3061
3062 *ret_val = 0;
3063 rc = -EFAULT;
3064 }
3065 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
3066 return rc;
3067 }
3068
3069 /******************************************************************/
3070 /* CL45 access functions */
3071 /******************************************************************/
3072 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
3073 u8 devad, u16 reg, u16 *ret_val)
3074 {
3075 u32 val;
3076 u16 i;
3077 int rc = 0;
3078 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3079 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3080 EMAC_MDIO_STATUS_10MB);
3081 /* address */
3082 val = ((phy->addr << 21) | (devad << 16) | reg |
3083 EMAC_MDIO_COMM_COMMAND_ADDRESS |
3084 EMAC_MDIO_COMM_START_BUSY);
3085 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
3086
3087 for (i = 0; i < 50; i++) {
3088 udelay(10);
3089
3090 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3091 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
3092 udelay(5);
3093 break;
3094 }
3095 }
3096 if (val & EMAC_MDIO_COMM_START_BUSY) {
3097 DP(NETIF_MSG_LINK, "read phy register failed\n");
3098 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
3099 *ret_val = 0;
3100 rc = -EFAULT;
3101 } else {
3102 /* data */
3103 val = ((phy->addr << 21) | (devad << 16) |
3104 EMAC_MDIO_COMM_COMMAND_READ_45 |
3105 EMAC_MDIO_COMM_START_BUSY);
3106 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
3107
3108 for (i = 0; i < 50; i++) {
3109 udelay(10);
3110
3111 val = REG_RD(bp, phy->mdio_ctrl +
3112 EMAC_REG_EMAC_MDIO_COMM);
3113 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
3114 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
3115 break;
3116 }
3117 }
3118 if (val & EMAC_MDIO_COMM_START_BUSY) {
3119 DP(NETIF_MSG_LINK, "read phy register failed\n");
3120 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
3121 *ret_val = 0;
3122 rc = -EFAULT;
3123 }
3124 }
3125 /* Work around for E3 A0 */
3126 if (phy->flags & FLAGS_MDC_MDIO_WA) {
3127 phy->flags ^= FLAGS_DUMMY_READ;
3128 if (phy->flags & FLAGS_DUMMY_READ) {
3129 u16 temp_val;
3130 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
3131 }
3132 }
3133
3134 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3135 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3136 EMAC_MDIO_STATUS_10MB);
3137 return rc;
3138 }
3139
3140 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3141 u8 devad, u16 reg, u16 val)
3142 {
3143 u32 tmp;
3144 u8 i;
3145 int rc = 0;
3146 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3147 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3148 EMAC_MDIO_STATUS_10MB);
3149
3150 /* address */
3151
3152 tmp = ((phy->addr << 21) | (devad << 16) | reg |
3153 EMAC_MDIO_COMM_COMMAND_ADDRESS |
3154 EMAC_MDIO_COMM_START_BUSY);
3155 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3156
3157 for (i = 0; i < 50; i++) {
3158 udelay(10);
3159
3160 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3161 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3162 udelay(5);
3163 break;
3164 }
3165 }
3166 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3167 DP(NETIF_MSG_LINK, "write phy register failed\n");
3168 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
3169 rc = -EFAULT;
3170 } else {
3171 /* data */
3172 tmp = ((phy->addr << 21) | (devad << 16) | val |
3173 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
3174 EMAC_MDIO_COMM_START_BUSY);
3175 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3176
3177 for (i = 0; i < 50; i++) {
3178 udelay(10);
3179
3180 tmp = REG_RD(bp, phy->mdio_ctrl +
3181 EMAC_REG_EMAC_MDIO_COMM);
3182 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3183 udelay(5);
3184 break;
3185 }
3186 }
3187 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3188 DP(NETIF_MSG_LINK, "write phy register failed\n");
3189 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
3190 rc = -EFAULT;
3191 }
3192 }
3193 /* Work around for E3 A0 */
3194 if (phy->flags & FLAGS_MDC_MDIO_WA) {
3195 phy->flags ^= FLAGS_DUMMY_READ;
3196 if (phy->flags & FLAGS_DUMMY_READ) {
3197 u16 temp_val;
3198 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
3199 }
3200 }
3201 if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3202 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3203 EMAC_MDIO_STATUS_10MB);
3204 return rc;
3205 }
3206 /******************************************************************/
3207 /* BSC access functions from E3 */
3208 /******************************************************************/
3209 static void bnx2x_bsc_module_sel(struct link_params *params)
3210 {
3211 int idx;
3212 u32 board_cfg, sfp_ctrl;
3213 u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
3214 struct bnx2x *bp = params->bp;
3215 u8 port = params->port;
3216 /* Read I2C output PINs */
3217 board_cfg = REG_RD(bp, params->shmem_base +
3218 offsetof(struct shmem_region,
3219 dev_info.shared_hw_config.board));
3220 i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
3221 i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
3222 SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
3223
3224 /* Read I2C output value */
3225 sfp_ctrl = REG_RD(bp, params->shmem_base +
3226 offsetof(struct shmem_region,
3227 dev_info.port_hw_config[port].e3_cmn_pin_cfg));
3228 i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
3229 i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
3230 DP(NETIF_MSG_LINK, "Setting BSC switch\n");
3231 for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
3232 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]);
3233 }
3234
3235 static int bnx2x_bsc_read(struct link_params *params,
3236 struct bnx2x_phy *phy,
3237 u8 sl_devid,
3238 u16 sl_addr,
3239 u8 lc_addr,
3240 u8 xfer_cnt,
3241 u32 *data_array)
3242 {
3243 u32 val, i;
3244 int rc = 0;
3245 struct bnx2x *bp = params->bp;
3246
3247 if ((sl_devid != 0xa0) && (sl_devid != 0xa2)) {
3248 DP(NETIF_MSG_LINK, "invalid sl_devid 0x%x\n", sl_devid);
3249 return -EINVAL;
3250 }
3251
3252 if (xfer_cnt > 16) {
3253 DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n",
3254 xfer_cnt);
3255 return -EINVAL;
3256 }
3257 bnx2x_bsc_module_sel(params);
3258
3259 xfer_cnt = 16 - lc_addr;
3260
3261 /* enable the engine */
3262 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3263 val |= MCPR_IMC_COMMAND_ENABLE;
3264 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3265
3266 /* program slave device ID */
3267 val = (sl_devid << 16) | sl_addr;
3268 REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
3269
3270 /* start xfer with 0 byte to update the address pointer ???*/
3271 val = (MCPR_IMC_COMMAND_ENABLE) |
3272 (MCPR_IMC_COMMAND_WRITE_OP <<
3273 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3274 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
3275 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3276
3277 /* poll for completion */
3278 i = 0;
3279 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3280 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3281 udelay(10);
3282 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3283 if (i++ > 1000) {
3284 DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n",
3285 i);
3286 rc = -EFAULT;
3287 break;
3288 }
3289 }
3290 if (rc == -EFAULT)
3291 return rc;
3292
3293 /* start xfer with read op */
3294 val = (MCPR_IMC_COMMAND_ENABLE) |
3295 (MCPR_IMC_COMMAND_READ_OP <<
3296 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3297 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
3298 (xfer_cnt);
3299 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3300
3301 /* poll for completion */
3302 i = 0;
3303 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3304 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3305 udelay(10);
3306 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3307 if (i++ > 1000) {
3308 DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i);
3309 rc = -EFAULT;
3310 break;
3311 }
3312 }
3313 if (rc == -EFAULT)
3314 return rc;
3315
3316 for (i = (lc_addr >> 2); i < 4; i++) {
3317 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));
3318 #ifdef __BIG_ENDIAN
3319 data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
3320 ((data_array[i] & 0x0000ff00) << 8) |
3321 ((data_array[i] & 0x00ff0000) >> 8) |
3322 ((data_array[i] & 0xff000000) >> 24);
3323 #endif
3324 }
3325 return rc;
3326 }
3327
3328 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3329 u8 devad, u16 reg, u16 or_val)
3330 {
3331 u16 val;
3332 bnx2x_cl45_read(bp, phy, devad, reg, &val);
3333 bnx2x_cl45_write(bp, phy, devad, reg, val | or_val);
3334 }
3335
3336 int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
3337 u8 devad, u16 reg, u16 *ret_val)
3338 {
3339 u8 phy_index;
3340 /*
3341 * Probe for the phy according to the given phy_addr, and execute
3342 * the read request on it
3343 */
3344 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3345 if (params->phy[phy_index].addr == phy_addr) {
3346 return bnx2x_cl45_read(params->bp,
3347 &params->phy[phy_index], devad,
3348 reg, ret_val);
3349 }
3350 }
3351 return -EINVAL;
3352 }
3353
3354 int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
3355 u8 devad, u16 reg, u16 val)
3356 {
3357 u8 phy_index;
3358 /*
3359 * Probe for the phy according to the given phy_addr, and execute
3360 * the write request on it
3361 */
3362 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3363 if (params->phy[phy_index].addr == phy_addr) {
3364 return bnx2x_cl45_write(params->bp,
3365 &params->phy[phy_index], devad,
3366 reg, val);
3367 }
3368 }
3369 return -EINVAL;
3370 }
3371 static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy,
3372 struct link_params *params)
3373 {
3374 u8 lane = 0;
3375 struct bnx2x *bp = params->bp;
3376 u32 path_swap, path_swap_ovr;
3377 u8 path, port;
3378
3379 path = BP_PATH(bp);
3380 port = params->port;
3381
3382 if (bnx2x_is_4_port_mode(bp)) {
3383 u32 port_swap, port_swap_ovr;
3384
3385 /*figure out path swap value */
3386 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
3387 if (path_swap_ovr & 0x1)
3388 path_swap = (path_swap_ovr & 0x2);
3389 else
3390 path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP);
3391
3392 if (path_swap)
3393 path = path ^ 1;
3394
3395 /*figure out port swap value */
3396 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
3397 if (port_swap_ovr & 0x1)
3398 port_swap = (port_swap_ovr & 0x2);
3399 else
3400 port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP);
3401
3402 if (port_swap)
3403 port = port ^ 1;
3404
3405 lane = (port<<1) + path;
3406 } else { /* two port mode - no port swap */
3407
3408 /*figure out path swap value */
3409 path_swap_ovr =
3410 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
3411 if (path_swap_ovr & 0x1) {
3412 path_swap = (path_swap_ovr & 0x2);
3413 } else {
3414 path_swap =
3415 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP);
3416 }
3417 if (path_swap)
3418 path = path ^ 1;
3419
3420 lane = path << 1 ;
3421 }
3422 return lane;
3423 }
3424
3425 static void bnx2x_set_aer_mmd(struct link_params *params,
3426 struct bnx2x_phy *phy)
3427 {
3428 u32 ser_lane;
3429 u16 offset, aer_val;
3430 struct bnx2x *bp = params->bp;
3431 ser_lane = ((params->lane_config &
3432 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3433 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3434
3435 offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
3436 (phy->addr + ser_lane) : 0;
3437
3438 if (USES_WARPCORE(bp)) {
3439 aer_val = bnx2x_get_warpcore_lane(phy, params);
3440 /*
3441 * In Dual-lane mode, two lanes are joined together,
3442 * so in order to configure them, the AER broadcast method is
3443 * used here.
3444 * 0x200 is the broadcast address for lanes 0,1
3445 * 0x201 is the broadcast address for lanes 2,3
3446 */
3447 if (phy->flags & FLAGS_WC_DUAL_MODE)
3448 aer_val = (aer_val >> 1) | 0x200;
3449 } else if (CHIP_IS_E2(bp))
3450 aer_val = 0x3800 + offset - 1;
3451 else
3452 aer_val = 0x3800 + offset;
3453
3454 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3455 MDIO_AER_BLOCK_AER_REG, aer_val);
3456
3457 }
3458
3459 /******************************************************************/
3460 /* Internal phy section */
3461 /******************************************************************/
3462
3463 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
3464 {
3465 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3466
3467 /* Set Clause 22 */
3468 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
3469 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
3470 udelay(500);
3471 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
3472 udelay(500);
3473 /* Set Clause 45 */
3474 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
3475 }
3476
3477 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
3478 {
3479 u32 val;
3480
3481 DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
3482
3483 val = SERDES_RESET_BITS << (port*16);
3484
3485 /* reset and unreset the SerDes/XGXS */
3486 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3487 udelay(500);
3488 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3489
3490 bnx2x_set_serdes_access(bp, port);
3491
3492 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
3493 DEFAULT_PHY_DEV_ADDR);
3494 }
3495
3496 static void bnx2x_xgxs_deassert(struct link_params *params)
3497 {
3498 struct bnx2x *bp = params->bp;
3499 u8 port;
3500 u32 val;
3501 DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
3502 port = params->port;
3503
3504 val = XGXS_RESET_BITS << (port*16);
3505
3506 /* reset and unreset the SerDes/XGXS */
3507 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3508 udelay(500);
3509 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3510
3511 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + port*0x18, 0);
3512 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
3513 params->phy[INT_PHY].def_md_devad);
3514 }
3515
3516 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
3517 struct link_params *params, u16 *ieee_fc)
3518 {
3519 struct bnx2x *bp = params->bp;
3520 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
3521 /**
3522 * resolve pause mode and advertisement Please refer to Table
3523 * 28B-3 of the 802.3ab-1999 spec
3524 */
3525
3526 switch (phy->req_flow_ctrl) {
3527 case BNX2X_FLOW_CTRL_AUTO:
3528 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH)
3529 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3530 else
3531 *ieee_fc |=
3532 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3533 break;
3534
3535 case BNX2X_FLOW_CTRL_TX:
3536 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3537 break;
3538
3539 case BNX2X_FLOW_CTRL_RX:
3540 case BNX2X_FLOW_CTRL_BOTH:
3541 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3542 break;
3543
3544 case BNX2X_FLOW_CTRL_NONE:
3545 default:
3546 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3547 break;
3548 }
3549 DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
3550 }
3551
3552 static void set_phy_vars(struct link_params *params,
3553 struct link_vars *vars)
3554 {
3555 struct bnx2x *bp = params->bp;
3556 u8 actual_phy_idx, phy_index, link_cfg_idx;
3557 u8 phy_config_swapped = params->multi_phy_config &
3558 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
3559 for (phy_index = INT_PHY; phy_index < params->num_phys;
3560 phy_index++) {
3561 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
3562 actual_phy_idx = phy_index;
3563 if (phy_config_swapped) {
3564 if (phy_index == EXT_PHY1)
3565 actual_phy_idx = EXT_PHY2;
3566 else if (phy_index == EXT_PHY2)
3567 actual_phy_idx = EXT_PHY1;
3568 }
3569 params->phy[actual_phy_idx].req_flow_ctrl =
3570 params->req_flow_ctrl[link_cfg_idx];
3571
3572 params->phy[actual_phy_idx].req_line_speed =
3573 params->req_line_speed[link_cfg_idx];
3574
3575 params->phy[actual_phy_idx].speed_cap_mask =
3576 params->speed_cap_mask[link_cfg_idx];
3577
3578 params->phy[actual_phy_idx].req_duplex =
3579 params->req_duplex[link_cfg_idx];
3580
3581 if (params->req_line_speed[link_cfg_idx] ==
3582 SPEED_AUTO_NEG)
3583 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
3584
3585 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
3586 " speed_cap_mask %x\n",
3587 params->phy[actual_phy_idx].req_flow_ctrl,
3588 params->phy[actual_phy_idx].req_line_speed,
3589 params->phy[actual_phy_idx].speed_cap_mask);
3590 }
3591 }
3592
3593 static void bnx2x_ext_phy_set_pause(struct link_params *params,
3594 struct bnx2x_phy *phy,
3595 struct link_vars *vars)
3596 {
3597 u16 val;
3598 struct bnx2x *bp = params->bp;
3599 /* read modify write pause advertizing */
3600 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3601
3602 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3603
3604 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3605 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3606 if ((vars->ieee_fc &
3607 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3608 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3609 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3610 }
3611 if ((vars->ieee_fc &
3612 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3613 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3614 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3615 }
3616 DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3617 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3618 }
3619
3620 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
3621 { /* LD LP */
3622 switch (pause_result) { /* ASYM P ASYM P */
3623 case 0xb: /* 1 0 1 1 */
3624 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
3625 break;
3626
3627 case 0xe: /* 1 1 1 0 */
3628 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
3629 break;
3630
3631 case 0x5: /* 0 1 0 1 */
3632 case 0x7: /* 0 1 1 1 */
3633 case 0xd: /* 1 1 0 1 */
3634 case 0xf: /* 1 1 1 1 */
3635 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
3636 break;
3637
3638 default:
3639 break;
3640 }
3641 if (pause_result & (1<<0))
3642 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
3643 if (pause_result & (1<<1))
3644 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
3645 }
3646
3647 static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy,
3648 struct link_params *params,
3649 struct link_vars *vars)
3650 {
3651 u16 ld_pause; /* local */
3652 u16 lp_pause; /* link partner */
3653 u16 pause_result;
3654 struct bnx2x *bp = params->bp;
3655 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {
3656 bnx2x_cl22_read(bp, phy, 0x4, &ld_pause);
3657 bnx2x_cl22_read(bp, phy, 0x5, &lp_pause);
3658 } else if (CHIP_IS_E3(bp) &&
3659 SINGLE_MEDIA_DIRECT(params)) {
3660 u8 lane = bnx2x_get_warpcore_lane(phy, params);
3661 u16 gp_status, gp_mask;
3662 bnx2x_cl45_read(bp, phy,
3663 MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4,
3664 &gp_status);
3665 gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL |
3666 MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) <<
3667 lane;
3668 if ((gp_status & gp_mask) == gp_mask) {
3669 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3670 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3671 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3672 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3673 } else {
3674 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3675 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
3676 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3677 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
3678 ld_pause = ((ld_pause &
3679 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3680 << 3);
3681 lp_pause = ((lp_pause &
3682 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3683 << 3);
3684 }
3685 } else {
3686 bnx2x_cl45_read(bp, phy,
3687 MDIO_AN_DEVAD,
3688 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3689 bnx2x_cl45_read(bp, phy,
3690 MDIO_AN_DEVAD,
3691 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3692 }
3693 pause_result = (ld_pause &
3694 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3695 pause_result |= (lp_pause &
3696 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3697 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n", pause_result);
3698 bnx2x_pause_resolve(vars, pause_result);
3699
3700 }
3701 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3702 struct link_params *params,
3703 struct link_vars *vars)
3704 {
3705 u8 ret = 0;
3706 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3707 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
3708 /* Update the advertised flow-controled of LD/LP in AN */
3709 if (phy->req_line_speed == SPEED_AUTO_NEG)
3710 bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3711 /* But set the flow-control result as the requested one */
3712 vars->flow_ctrl = phy->req_flow_ctrl;
3713 } else if (phy->req_line_speed != SPEED_AUTO_NEG)
3714 vars->flow_ctrl = params->req_fc_auto_adv;
3715 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3716 ret = 1;
3717 bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3718 }
3719 return ret;
3720 }
3721 /******************************************************************/
3722 /* Warpcore section */
3723 /******************************************************************/
3724 /* The init_internal_warpcore should mirror the xgxs,
3725 * i.e. reset the lane (if needed), set aer for the
3726 * init configuration, and set/clear SGMII flag. Internal
3727 * phy init is done purely in phy_init stage.
3728 */
3729 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
3730 struct link_params *params,
3731 struct link_vars *vars) {
3732 u16 val16 = 0, lane, bam37 = 0;
3733 struct bnx2x *bp = params->bp;
3734 DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n");
3735 /* Set to default registers that may be overriden by 10G force */
3736 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3737 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7);
3738 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3739 MDIO_WC_REG_PAR_DET_10G_CTRL, 0);
3740 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3741 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 0);
3742 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3743 MDIO_WC_REG_XGXSBLK1_LANECTRL0, 0xff);
3744 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3745 MDIO_WC_REG_XGXSBLK1_LANECTRL1, 0x5555);
3746 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3747 MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0);
3748 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3749 MDIO_WC_REG_RX66_CONTROL, 0x7415);
3750 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3751 MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190);
3752 /* Disable Autoneg: re-enable it after adv is done. */
3753 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3754 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0);
3755
3756 /* Check adding advertisement for 1G KX */
3757 if (((vars->line_speed == SPEED_AUTO_NEG) &&
3758 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
3759 (vars->line_speed == SPEED_1000)) {
3760 u16 sd_digital;
3761 val16 |= (1<<5);
3762
3763 /* Enable CL37 1G Parallel Detect */
3764 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3765 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &sd_digital);
3766 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3767 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3768 (sd_digital | 0x1));
3769
3770 DP(NETIF_MSG_LINK, "Advertize 1G\n");
3771 }
3772 if (((vars->line_speed == SPEED_AUTO_NEG) &&
3773 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
3774 (vars->line_speed == SPEED_10000)) {
3775 /* Check adding advertisement for 10G KR */
3776 val16 |= (1<<7);
3777 /* Enable 10G Parallel Detect */
3778 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3779 MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
3780
3781 DP(NETIF_MSG_LINK, "Advertize 10G\n");
3782 }
3783
3784 /* Set Transmit PMD settings */
3785 lane = bnx2x_get_warpcore_lane(phy, params);
3786 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3787 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3788 ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3789 (0x06 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3790 (0x09 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)));
3791 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3792 MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
3793 0x03f0);
3794 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3795 MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
3796 0x03f0);
3797
3798 /* Advertised speeds */
3799 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3800 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, val16);
3801
3802 /* Advertised and set FEC (Forward Error Correction) */
3803 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3804 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2,
3805 (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY |
3806 MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ));
3807
3808 /* Enable CL37 BAM */
3809 if (REG_RD(bp, params->shmem_base +
3810 offsetof(struct shmem_region, dev_info.
3811 port_hw_config[params->port].default_cfg)) &
3812 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
3813 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3814 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, &bam37);
3815 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3816 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, bam37 | 1);
3817 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
3818 }
3819
3820 /* Advertise pause */
3821 bnx2x_ext_phy_set_pause(params, phy, vars);
3822
3823 /*
3824 * Set KR Autoneg Work-Around flag for Warpcore version older than D108
3825 */
3826 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3827 MDIO_WC_REG_UC_INFO_B1_VERSION, &val16);
3828 if (val16 < 0xd108) {
3829 DP(NETIF_MSG_LINK, "Enable AN KR work-around\n");
3830 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
3831 }
3832
3833 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3834 MDIO_WC_REG_DIGITAL5_MISC7, &val16);
3835
3836 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3837 MDIO_WC_REG_DIGITAL5_MISC7, val16 | 0x100);
3838
3839 /* Over 1G - AN local device user page 1 */
3840 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3841 MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
3842
3843 /* Enable Autoneg */
3844 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3845 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
3846
3847 }
3848
3849 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy,
3850 struct link_params *params,
3851 struct link_vars *vars)
3852 {
3853 struct bnx2x *bp = params->bp;
3854 u16 val;
3855
3856 /* Disable Autoneg */
3857 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3858 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7);
3859
3860 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3861 MDIO_WC_REG_PAR_DET_10G_CTRL, 0);
3862
3863 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3864 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 0x3f00);
3865
3866 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3867 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0);
3868
3869 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3870 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3871
3872 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3873 MDIO_WC_REG_DIGITAL3_UP1, 0x1);
3874
3875 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3876 MDIO_WC_REG_DIGITAL5_MISC7, 0xa);
3877
3878 /* Disable CL36 PCS Tx */
3879 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3880 MDIO_WC_REG_XGXSBLK1_LANECTRL0, 0x0);
3881
3882 /* Double Wide Single Data Rate @ pll rate */
3883 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3884 MDIO_WC_REG_XGXSBLK1_LANECTRL1, 0xFFFF);
3885
3886 /* Leave cl72 training enable, needed for KR */
3887 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3888 MDIO_WC_REG_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150,
3889 0x2);
3890
3891 /* Leave CL72 enabled */
3892 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3893 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3894 &val);
3895 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3896 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3897 val | 0x3800);
3898
3899 /* Set speed via PMA/PMD register */
3900 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3901 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
3902
3903 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3904 MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
3905
3906 /*Enable encoded forced speed */
3907 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3908 MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
3909
3910 /* Turn TX scramble payload only the 64/66 scrambler */
3911 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3912 MDIO_WC_REG_TX66_CONTROL, 0x9);
3913
3914 /* Turn RX scramble payload only the 64/66 scrambler */
3915 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3916 MDIO_WC_REG_RX66_CONTROL, 0xF9);
3917
3918 /* set and clear loopback to cause a reset to 64/66 decoder */
3919 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3920 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
3921 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3922 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3923
3924 }
3925
3926 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy,
3927 struct link_params *params,
3928 u8 is_xfi)
3929 {
3930 struct bnx2x *bp = params->bp;
3931 u16 misc1_val, tap_val, tx_driver_val, lane, val;
3932 /* Hold rxSeqStart */
3933 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3934 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, &val);
3935 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3936 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, (val | 0x8000));
3937
3938 /* Hold tx_fifo_reset */
3939 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3940 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, &val);
3941 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3942 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, (val | 0x1));
3943
3944 /* Disable CL73 AN */
3945 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
3946
3947 /* Disable 100FX Enable and Auto-Detect */
3948 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3949 MDIO_WC_REG_FX100_CTRL1, &val);
3950 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3951 MDIO_WC_REG_FX100_CTRL1, (val & 0xFFFA));
3952
3953 /* Disable 100FX Idle detect */
3954 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3955 MDIO_WC_REG_FX100_CTRL3, &val);
3956 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3957 MDIO_WC_REG_FX100_CTRL3, (val | 0x0080));
3958
3959 /* Set Block address to Remote PHY & Clear forced_speed[5] */
3960 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3961 MDIO_WC_REG_DIGITAL4_MISC3, &val);
3962 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3963 MDIO_WC_REG_DIGITAL4_MISC3, (val & 0xFF7F));
3964
3965 /* Turn off auto-detect & fiber mode */
3966 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3967 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &val);
3968 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3969 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3970 (val & 0xFFEE));
3971
3972 /* Set filter_force_link, disable_false_link and parallel_detect */
3973 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3974 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
3975 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3976 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3977 ((val | 0x0006) & 0xFFFE));
3978
3979 /* Set XFI / SFI */
3980 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3981 MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
3982
3983 misc1_val &= ~(0x1f);
3984
3985 if (is_xfi) {
3986 misc1_val |= 0x5;
3987 tap_val = ((0x08 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3988 (0x37 << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3989 (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET));
3990 tx_driver_val =
3991 ((0x00 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3992 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3993 (0x03 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET));
3994
3995 } else {
3996 misc1_val |= 0x9;
3997 tap_val = ((0x0f << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3998 (0x2b << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3999 (0x02 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET));
4000 tx_driver_val =
4001 ((0x03 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
4002 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
4003 (0x06 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET));
4004 }
4005 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4006 MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
4007
4008 /* Set Transmit PMD settings */
4009 lane = bnx2x_get_warpcore_lane(phy, params);
4010 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4011 MDIO_WC_REG_TX_FIR_TAP,
4012 tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
4013 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4014 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4015 tx_driver_val);
4016
4017 /* Enable fiber mode, enable and invert sig_det */
4018 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4019 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &val);
4020 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4021 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, val | 0xd);
4022
4023 /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
4024 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4025 MDIO_WC_REG_DIGITAL4_MISC3, &val);
4026 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4027 MDIO_WC_REG_DIGITAL4_MISC3, val | 0x8080);
4028
4029 /* 10G XFI Full Duplex */
4030 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4031 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);
4032
4033 /* Release tx_fifo_reset */
4034 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4035 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, &val);
4036 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4037 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, val & 0xFFFE);
4038
4039 /* Release rxSeqStart */
4040 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4041 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, &val);
4042 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4043 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, (val & 0x7FFF));
4044 }
4045
4046 static void bnx2x_warpcore_set_20G_KR2(struct bnx2x *bp,
4047 struct bnx2x_phy *phy)
4048 {
4049 DP(NETIF_MSG_LINK, "KR2 still not supported !!!\n");
4050 }
4051
4052 static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp,
4053 struct bnx2x_phy *phy,
4054 u16 lane)
4055 {
4056 /* Rx0 anaRxControl1G */
4057 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4058 MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);
4059
4060 /* Rx2 anaRxControl1G */
4061 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4062 MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
4063
4064 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4065 MDIO_WC_REG_RX66_SCW0, 0xE070);
4066
4067 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4068 MDIO_WC_REG_RX66_SCW1, 0xC0D0);
4069
4070 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4071 MDIO_WC_REG_RX66_SCW2, 0xA0B0);
4072
4073 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4074 MDIO_WC_REG_RX66_SCW3, 0x8090);
4075
4076 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4077 MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
4078
4079 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4080 MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);
4081
4082 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4083 MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);
4084
4085 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4086 MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);
4087
4088 /* Serdes Digital Misc1 */
4089 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4090 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);
4091
4092 /* Serdes Digital4 Misc3 */
4093 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4094 MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);
4095
4096 /* Set Transmit PMD settings */
4097 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4098 MDIO_WC_REG_TX_FIR_TAP,
4099 ((0x12 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
4100 (0x2d << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
4101 (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET) |
4102 MDIO_WC_REG_TX_FIR_TAP_ENABLE));
4103 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4104 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4105 ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
4106 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
4107 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)));
4108 }
4109
4110 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy,
4111 struct link_params *params,
4112 u8 fiber_mode,
4113 u8 always_autoneg)
4114 {
4115 struct bnx2x *bp = params->bp;
4116 u16 val16, digctrl_kx1, digctrl_kx2;
4117
4118 /* Clear XFI clock comp in non-10G single lane mode. */
4119 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4120 MDIO_WC_REG_RX66_CONTROL, &val16);
4121 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4122 MDIO_WC_REG_RX66_CONTROL, val16 & ~(3<<13));
4123
4124 if (always_autoneg || phy->req_line_speed == SPEED_AUTO_NEG) {
4125 /* SGMII Autoneg */
4126 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4127 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4128 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4129 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4130 val16 | 0x1000);
4131 DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n");
4132 } else {
4133 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4134 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4135 val16 &= 0xcebf;
4136 switch (phy->req_line_speed) {
4137 case SPEED_10:
4138 break;
4139 case SPEED_100:
4140 val16 |= 0x2000;
4141 break;
4142 case SPEED_1000:
4143 val16 |= 0x0040;
4144 break;
4145 default:
4146 DP(NETIF_MSG_LINK,
4147 "Speed not supported: 0x%x\n", phy->req_line_speed);
4148 return;
4149 }
4150
4151 if (phy->req_duplex == DUPLEX_FULL)
4152 val16 |= 0x0100;
4153
4154 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4155 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
4156
4157 DP(NETIF_MSG_LINK, "set SGMII force speed %d\n",
4158 phy->req_line_speed);
4159 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4160 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4161 DP(NETIF_MSG_LINK, " (readback) %x\n", val16);
4162 }
4163
4164 /* SGMII Slave mode and disable signal detect */
4165 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4166 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
4167 if (fiber_mode)
4168 digctrl_kx1 = 1;
4169 else
4170 digctrl_kx1 &= 0xff4a;
4171
4172 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4173 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4174 digctrl_kx1);
4175
4176 /* Turn off parallel detect */
4177 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4178 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
4179 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4180 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4181 (digctrl_kx2 & ~(1<<2)));
4182
4183 /* Re-enable parallel detect */
4184 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4185 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4186 (digctrl_kx2 | (1<<2)));
4187
4188 /* Enable autodet */
4189 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4190 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4191 (digctrl_kx1 | 0x10));
4192 }
4193
4194 static void bnx2x_warpcore_reset_lane(struct bnx2x *bp,
4195 struct bnx2x_phy *phy,
4196 u8 reset)
4197 {
4198 u16 val;
4199 /* Take lane out of reset after configuration is finished */
4200 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4201 MDIO_WC_REG_DIGITAL5_MISC6, &val);
4202 if (reset)
4203 val |= 0xC000;
4204 else
4205 val &= 0x3FFF;
4206 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4207 MDIO_WC_REG_DIGITAL5_MISC6, val);
4208 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4209 MDIO_WC_REG_DIGITAL5_MISC6, &val);
4210 }
4211 /* Clear SFI/XFI link settings registers */
4212 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy,
4213 struct link_params *params,
4214 u16 lane)
4215 {
4216 struct bnx2x *bp = params->bp;
4217 u16 val16;
4218
4219 /* Set XFI clock comp as default. */
4220 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4221 MDIO_WC_REG_RX66_CONTROL, &val16);
4222 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4223 MDIO_WC_REG_RX66_CONTROL, val16 | (3<<13));
4224
4225 bnx2x_warpcore_reset_lane(bp, phy, 1);
4226 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
4227 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4228 MDIO_WC_REG_FX100_CTRL1, 0x014a);
4229 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4230 MDIO_WC_REG_FX100_CTRL3, 0x0800);
4231 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4232 MDIO_WC_REG_DIGITAL4_MISC3, 0x8008);
4233 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4234 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x0195);
4235 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4236 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x0007);
4237 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4238 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x0002);
4239 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4240 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000);
4241 lane = bnx2x_get_warpcore_lane(phy, params);
4242 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4243 MDIO_WC_REG_TX_FIR_TAP, 0x0000);
4244 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4245 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);
4246 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4247 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
4248 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4249 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140);
4250 bnx2x_warpcore_reset_lane(bp, phy, 0);
4251 }
4252
4253 static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp,
4254 u32 chip_id,
4255 u32 shmem_base, u8 port,
4256 u8 *gpio_num, u8 *gpio_port)
4257 {
4258 u32 cfg_pin;
4259 *gpio_num = 0;
4260 *gpio_port = 0;
4261 if (CHIP_IS_E3(bp)) {
4262 cfg_pin = (REG_RD(bp, shmem_base +
4263 offsetof(struct shmem_region,
4264 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4265 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
4266 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
4267
4268 /*
4269 * Should not happen. This function called upon interrupt
4270 * triggered by GPIO ( since EPIO can only generate interrupts
4271 * to MCP).
4272 * So if this function was called and none of the GPIOs was set,
4273 * it means the shit hit the fan.
4274 */
4275 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
4276 (cfg_pin > PIN_CFG_GPIO3_P1)) {
4277 DP(NETIF_MSG_LINK,
4278 "ERROR: Invalid cfg pin %x for module detect indication\n",
4279 cfg_pin);
4280 return -EINVAL;
4281 }
4282
4283 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
4284 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
4285 } else {
4286 *gpio_num = MISC_REGISTERS_GPIO_3;
4287 *gpio_port = port;
4288 }
4289 DP(NETIF_MSG_LINK, "MOD_ABS int GPIO%d_P%d\n", *gpio_num, *gpio_port);
4290 return 0;
4291 }
4292
4293 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy,
4294 struct link_params *params)
4295 {
4296 struct bnx2x *bp = params->bp;
4297 u8 gpio_num, gpio_port;
4298 u32 gpio_val;
4299 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id,
4300 params->shmem_base, params->port,
4301 &gpio_num, &gpio_port) != 0)
4302 return 0;
4303 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
4304
4305 /* Call the handling function in case module is detected */
4306 if (gpio_val == 0)
4307 return 1;
4308 else
4309 return 0;
4310 }
4311 static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy,
4312 struct link_params *params)
4313 {
4314 u16 gp2_status_reg0, lane;
4315 struct bnx2x *bp = params->bp;
4316
4317 lane = bnx2x_get_warpcore_lane(phy, params);
4318
4319 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,
4320 &gp2_status_reg0);
4321
4322 return (gp2_status_reg0 >> (8+lane)) & 0x1;
4323 }
4324
4325 static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy,
4326 struct link_params *params,
4327 struct link_vars *vars)
4328 {
4329 struct bnx2x *bp = params->bp;
4330 u32 serdes_net_if;
4331 u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0;
4332 u16 lane = bnx2x_get_warpcore_lane(phy, params);
4333
4334 vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1;
4335
4336 if (!vars->turn_to_run_wc_rt)
4337 return;
4338
4339 /* return if there is no link partner */
4340 if (!(bnx2x_warpcore_get_sigdet(phy, params))) {
4341 DP(NETIF_MSG_LINK, "bnx2x_warpcore_get_sigdet false\n");
4342 return;
4343 }
4344
4345 if (vars->rx_tx_asic_rst) {
4346 serdes_net_if = (REG_RD(bp, params->shmem_base +
4347 offsetof(struct shmem_region, dev_info.
4348 port_hw_config[params->port].default_cfg)) &
4349 PORT_HW_CFG_NET_SERDES_IF_MASK);
4350
4351 switch (serdes_net_if) {
4352 case PORT_HW_CFG_NET_SERDES_IF_KR:
4353 /* Do we get link yet? */
4354 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1,
4355 &gp_status1);
4356 lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */
4357 /*10G KR*/
4358 lnkup_kr = (gp_status1 >> (12+lane)) & 0x1;
4359
4360 DP(NETIF_MSG_LINK,
4361 "gp_status1 0x%x\n", gp_status1);
4362
4363 if (lnkup_kr || lnkup) {
4364 vars->rx_tx_asic_rst = 0;
4365 DP(NETIF_MSG_LINK,
4366 "link up, rx_tx_asic_rst 0x%x\n",
4367 vars->rx_tx_asic_rst);
4368 } else {
4369 /*reset the lane to see if link comes up.*/
4370 bnx2x_warpcore_reset_lane(bp, phy, 1);
4371 bnx2x_warpcore_reset_lane(bp, phy, 0);
4372
4373 /* restart Autoneg */
4374 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4375 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
4376
4377 vars->rx_tx_asic_rst--;
4378 DP(NETIF_MSG_LINK, "0x%x retry left\n",
4379 vars->rx_tx_asic_rst);
4380 }
4381 break;
4382
4383 default:
4384 break;
4385 }
4386
4387 } /*params->rx_tx_asic_rst*/
4388
4389 }
4390
4391 static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy,
4392 struct link_params *params,
4393 struct link_vars *vars)
4394 {
4395 struct bnx2x *bp = params->bp;
4396 u32 serdes_net_if;
4397 u8 fiber_mode;
4398 u16 lane = bnx2x_get_warpcore_lane(phy, params);
4399 serdes_net_if = (REG_RD(bp, params->shmem_base +
4400 offsetof(struct shmem_region, dev_info.
4401 port_hw_config[params->port].default_cfg)) &
4402 PORT_HW_CFG_NET_SERDES_IF_MASK);
4403 DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, "
4404 "serdes_net_if = 0x%x\n",
4405 vars->line_speed, serdes_net_if);
4406 bnx2x_set_aer_mmd(params, phy);
4407
4408 vars->phy_flags |= PHY_XGXS_FLAG;
4409 if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
4410 (phy->req_line_speed &&
4411 ((phy->req_line_speed == SPEED_100) ||
4412 (phy->req_line_speed == SPEED_10)))) {
4413 vars->phy_flags |= PHY_SGMII_FLAG;
4414 DP(NETIF_MSG_LINK, "Setting SGMII mode\n");
4415 bnx2x_warpcore_clear_regs(phy, params, lane);
4416 bnx2x_warpcore_set_sgmii_speed(phy, params, 0, 1);
4417 } else {
4418 switch (serdes_net_if) {
4419 case PORT_HW_CFG_NET_SERDES_IF_KR:
4420 /* Enable KR Auto Neg */
4421 if (params->loopback_mode != LOOPBACK_EXT)
4422 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4423 else {
4424 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n");
4425 bnx2x_warpcore_set_10G_KR(phy, params, vars);
4426 }
4427 break;
4428
4429 case PORT_HW_CFG_NET_SERDES_IF_XFI:
4430 bnx2x_warpcore_clear_regs(phy, params, lane);
4431 if (vars->line_speed == SPEED_10000) {
4432 DP(NETIF_MSG_LINK, "Setting 10G XFI\n");
4433 bnx2x_warpcore_set_10G_XFI(phy, params, 1);
4434 } else {
4435 if (SINGLE_MEDIA_DIRECT(params)) {
4436 DP(NETIF_MSG_LINK, "1G Fiber\n");
4437 fiber_mode = 1;
4438 } else {
4439 DP(NETIF_MSG_LINK, "10/100/1G SGMII\n");
4440 fiber_mode = 0;
4441 }
4442 bnx2x_warpcore_set_sgmii_speed(phy,
4443 params,
4444 fiber_mode,
4445 0);
4446 }
4447
4448 break;
4449
4450 case PORT_HW_CFG_NET_SERDES_IF_SFI:
4451
4452 bnx2x_warpcore_clear_regs(phy, params, lane);
4453 if (vars->line_speed == SPEED_10000) {
4454 DP(NETIF_MSG_LINK, "Setting 10G SFI\n");
4455 bnx2x_warpcore_set_10G_XFI(phy, params, 0);
4456 } else if (vars->line_speed == SPEED_1000) {
4457 DP(NETIF_MSG_LINK, "Setting 1G Fiber\n");
4458 bnx2x_warpcore_set_sgmii_speed(
4459 phy, params, 1, 0);
4460 }
4461 /* Issue Module detection */
4462 if (bnx2x_is_sfp_module_plugged(phy, params))
4463 bnx2x_sfp_module_detection(phy, params);
4464 break;
4465
4466 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
4467 if (vars->line_speed != SPEED_20000) {
4468 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4469 return;
4470 }
4471 DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n");
4472 bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane);
4473 /* Issue Module detection */
4474
4475 bnx2x_sfp_module_detection(phy, params);
4476 break;
4477
4478 case PORT_HW_CFG_NET_SERDES_IF_KR2:
4479 if (vars->line_speed != SPEED_20000) {
4480 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4481 return;
4482 }
4483 DP(NETIF_MSG_LINK, "Setting 20G KR2\n");
4484 bnx2x_warpcore_set_20G_KR2(bp, phy);
4485 break;
4486
4487 default:
4488 DP(NETIF_MSG_LINK,
4489 "Unsupported Serdes Net Interface 0x%x\n",
4490 serdes_net_if);
4491 return;
4492 }
4493 }
4494
4495 /* Take lane out of reset after configuration is finished */
4496 bnx2x_warpcore_reset_lane(bp, phy, 0);
4497 DP(NETIF_MSG_LINK, "Exit config init\n");
4498 }
4499
4500 static void bnx2x_sfp_e3_set_transmitter(struct link_params *params,
4501 struct bnx2x_phy *phy,
4502 u8 tx_en)
4503 {
4504 struct bnx2x *bp = params->bp;
4505 u32 cfg_pin;
4506 u8 port = params->port;
4507
4508 cfg_pin = REG_RD(bp, params->shmem_base +
4509 offsetof(struct shmem_region,
4510 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4511 PORT_HW_CFG_TX_LASER_MASK;
4512 /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4513 DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en);
4514 /* For 20G, the expected pin to be used is 3 pins after the current */
4515
4516 bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1);
4517 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
4518 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1);
4519 }
4520
4521 static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy,
4522 struct link_params *params)
4523 {
4524 struct bnx2x *bp = params->bp;
4525 u16 val16;
4526 bnx2x_sfp_e3_set_transmitter(params, phy, 0);
4527 bnx2x_set_mdio_clk(bp, params->chip_id, params->port);
4528 bnx2x_set_aer_mmd(params, phy);
4529 /* Global register */
4530 bnx2x_warpcore_reset_lane(bp, phy, 1);
4531
4532 /* Clear loopback settings (if any) */
4533 /* 10G & 20G */
4534 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4535 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4536 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4537 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 &
4538 0xBFFF);
4539
4540 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4541 MDIO_WC_REG_IEEE0BLK_MIICNTL, &val16);
4542 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4543 MDIO_WC_REG_IEEE0BLK_MIICNTL, val16 & 0xfffe);
4544
4545 /* Update those 1-copy registers */
4546 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4547 MDIO_AER_BLOCK_AER_REG, 0);
4548 /* Enable 1G MDIO (1-copy) */
4549 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4550 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4551 &val16);
4552 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4553 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4554 val16 & ~0x10);
4555
4556 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4557 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4558 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4559 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4560 val16 & 0xff00);
4561
4562 }
4563
4564 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy,
4565 struct link_params *params)
4566 {
4567 struct bnx2x *bp = params->bp;
4568 u16 val16;
4569 u32 lane;
4570 DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n",
4571 params->loopback_mode, phy->req_line_speed);
4572
4573 if (phy->req_line_speed < SPEED_10000) {
4574 /* 10/100/1000 */
4575
4576 /* Update those 1-copy registers */
4577 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4578 MDIO_AER_BLOCK_AER_REG, 0);
4579 /* Enable 1G MDIO (1-copy) */
4580 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4581 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4582 &val16);
4583 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4584 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4585 val16 | 0x10);
4586 /* Set 1G loopback based on lane (1-copy) */
4587 lane = bnx2x_get_warpcore_lane(phy, params);
4588 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4589 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4590 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4591 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4592 val16 | (1<<lane));
4593
4594 /* Switch back to 4-copy registers */
4595 bnx2x_set_aer_mmd(params, phy);
4596 } else {
4597 /* 10G & 20G */
4598 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4599 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4600 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4601 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 |
4602 0x4000);
4603
4604 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4605 MDIO_WC_REG_IEEE0BLK_MIICNTL, &val16);
4606 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4607 MDIO_WC_REG_IEEE0BLK_MIICNTL, val16 | 0x1);
4608 }
4609 }
4610
4611
4612 void bnx2x_sync_link(struct link_params *params,
4613 struct link_vars *vars)
4614 {
4615 struct bnx2x *bp = params->bp;
4616 u8 link_10g_plus;
4617 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4618 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
4619 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
4620 if (vars->link_up) {
4621 DP(NETIF_MSG_LINK, "phy link up\n");
4622
4623 vars->phy_link_up = 1;
4624 vars->duplex = DUPLEX_FULL;
4625 switch (vars->link_status &
4626 LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
4627 case LINK_10THD:
4628 vars->duplex = DUPLEX_HALF;
4629 /* fall thru */
4630 case LINK_10TFD:
4631 vars->line_speed = SPEED_10;
4632 break;
4633
4634 case LINK_100TXHD:
4635 vars->duplex = DUPLEX_HALF;
4636 /* fall thru */
4637 case LINK_100T4:
4638 case LINK_100TXFD:
4639 vars->line_speed = SPEED_100;
4640 break;
4641
4642 case LINK_1000THD:
4643 vars->duplex = DUPLEX_HALF;
4644 /* fall thru */
4645 case LINK_1000TFD:
4646 vars->line_speed = SPEED_1000;
4647 break;
4648
4649 case LINK_2500THD:
4650 vars->duplex = DUPLEX_HALF;
4651 /* fall thru */
4652 case LINK_2500TFD:
4653 vars->line_speed = SPEED_2500;
4654 break;
4655
4656 case LINK_10GTFD:
4657 vars->line_speed = SPEED_10000;
4658 break;
4659 case LINK_20GTFD:
4660 vars->line_speed = SPEED_20000;
4661 break;
4662 default:
4663 break;
4664 }
4665 vars->flow_ctrl = 0;
4666 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
4667 vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
4668
4669 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
4670 vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
4671
4672 if (!vars->flow_ctrl)
4673 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4674
4675 if (vars->line_speed &&
4676 ((vars->line_speed == SPEED_10) ||
4677 (vars->line_speed == SPEED_100))) {
4678 vars->phy_flags |= PHY_SGMII_FLAG;
4679 } else {
4680 vars->phy_flags &= ~PHY_SGMII_FLAG;
4681 }
4682 if (vars->line_speed &&
4683 USES_WARPCORE(bp) &&
4684 (vars->line_speed == SPEED_1000))
4685 vars->phy_flags |= PHY_SGMII_FLAG;
4686 /* anything 10 and over uses the bmac */
4687 link_10g_plus = (vars->line_speed >= SPEED_10000);
4688
4689 if (link_10g_plus) {
4690 if (USES_WARPCORE(bp))
4691 vars->mac_type = MAC_TYPE_XMAC;
4692 else
4693 vars->mac_type = MAC_TYPE_BMAC;
4694 } else {
4695 if (USES_WARPCORE(bp))
4696 vars->mac_type = MAC_TYPE_UMAC;
4697 else
4698 vars->mac_type = MAC_TYPE_EMAC;
4699 }
4700 } else { /* link down */
4701 DP(NETIF_MSG_LINK, "phy link down\n");
4702
4703 vars->phy_link_up = 0;
4704
4705 vars->line_speed = 0;
4706 vars->duplex = DUPLEX_FULL;
4707 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4708
4709 /* indicate no mac active */
4710 vars->mac_type = MAC_TYPE_NONE;
4711 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4712 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
4713 }
4714 }
4715
4716 void bnx2x_link_status_update(struct link_params *params,
4717 struct link_vars *vars)
4718 {
4719 struct bnx2x *bp = params->bp;
4720 u8 port = params->port;
4721 u32 sync_offset, media_types;
4722 /* Update PHY configuration */
4723 set_phy_vars(params, vars);
4724
4725 vars->link_status = REG_RD(bp, params->shmem_base +
4726 offsetof(struct shmem_region,
4727 port_mb[port].link_status));
4728
4729 vars->phy_flags = PHY_XGXS_FLAG;
4730 bnx2x_sync_link(params, vars);
4731 /* Sync media type */
4732 sync_offset = params->shmem_base +
4733 offsetof(struct shmem_region,
4734 dev_info.port_hw_config[port].media_type);
4735 media_types = REG_RD(bp, sync_offset);
4736
4737 params->phy[INT_PHY].media_type =
4738 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
4739 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
4740 params->phy[EXT_PHY1].media_type =
4741 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
4742 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
4743 params->phy[EXT_PHY2].media_type =
4744 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
4745 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
4746 DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types);
4747
4748 /* Sync AEU offset */
4749 sync_offset = params->shmem_base +
4750 offsetof(struct shmem_region,
4751 dev_info.port_hw_config[port].aeu_int_mask);
4752
4753 vars->aeu_int_mask = REG_RD(bp, sync_offset);
4754
4755 /* Sync PFC status */
4756 if (vars->link_status & LINK_STATUS_PFC_ENABLED)
4757 params->feature_config_flags |=
4758 FEATURE_CONFIG_PFC_ENABLED;
4759 else
4760 params->feature_config_flags &=
4761 ~FEATURE_CONFIG_PFC_ENABLED;
4762
4763 DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x int_mask 0x%x\n",
4764 vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
4765 DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n",
4766 vars->line_speed, vars->duplex, vars->flow_ctrl);
4767 }
4768
4769 static void bnx2x_set_master_ln(struct link_params *params,
4770 struct bnx2x_phy *phy)
4771 {
4772 struct bnx2x *bp = params->bp;
4773 u16 new_master_ln, ser_lane;
4774 ser_lane = ((params->lane_config &
4775 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4776 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4777
4778 /* set the master_ln for AN */
4779 CL22_RD_OVER_CL45(bp, phy,
4780 MDIO_REG_BANK_XGXS_BLOCK2,
4781 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4782 &new_master_ln);
4783
4784 CL22_WR_OVER_CL45(bp, phy,
4785 MDIO_REG_BANK_XGXS_BLOCK2 ,
4786 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4787 (new_master_ln | ser_lane));
4788 }
4789
4790 static int bnx2x_reset_unicore(struct link_params *params,
4791 struct bnx2x_phy *phy,
4792 u8 set_serdes)
4793 {
4794 struct bnx2x *bp = params->bp;
4795 u16 mii_control;
4796 u16 i;
4797 CL22_RD_OVER_CL45(bp, phy,
4798 MDIO_REG_BANK_COMBO_IEEE0,
4799 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4800
4801 /* reset the unicore */
4802 CL22_WR_OVER_CL45(bp, phy,
4803 MDIO_REG_BANK_COMBO_IEEE0,
4804 MDIO_COMBO_IEEE0_MII_CONTROL,
4805 (mii_control |
4806 MDIO_COMBO_IEEO_MII_CONTROL_RESET));
4807 if (set_serdes)
4808 bnx2x_set_serdes_access(bp, params->port);
4809
4810 /* wait for the reset to self clear */
4811 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
4812 udelay(5);
4813
4814 /* the reset erased the previous bank value */
4815 CL22_RD_OVER_CL45(bp, phy,
4816 MDIO_REG_BANK_COMBO_IEEE0,
4817 MDIO_COMBO_IEEE0_MII_CONTROL,
4818 &mii_control);
4819
4820 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
4821 udelay(5);
4822 return 0;
4823 }
4824 }
4825
4826 netdev_err(bp->dev, "Warning: PHY was not initialized,"
4827 " Port %d\n",
4828 params->port);
4829 DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
4830 return -EINVAL;
4831
4832 }
4833
4834 static void bnx2x_set_swap_lanes(struct link_params *params,
4835 struct bnx2x_phy *phy)
4836 {
4837 struct bnx2x *bp = params->bp;
4838 /*
4839 * Each two bits represents a lane number:
4840 * No swap is 0123 => 0x1b no need to enable the swap
4841 */
4842 u16 rx_lane_swap, tx_lane_swap;
4843
4844 rx_lane_swap = ((params->lane_config &
4845 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
4846 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
4847 tx_lane_swap = ((params->lane_config &
4848 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
4849 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
4850
4851 if (rx_lane_swap != 0x1b) {
4852 CL22_WR_OVER_CL45(bp, phy,
4853 MDIO_REG_BANK_XGXS_BLOCK2,
4854 MDIO_XGXS_BLOCK2_RX_LN_SWAP,
4855 (rx_lane_swap |
4856 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
4857 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
4858 } else {
4859 CL22_WR_OVER_CL45(bp, phy,
4860 MDIO_REG_BANK_XGXS_BLOCK2,
4861 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
4862 }
4863
4864 if (tx_lane_swap != 0x1b) {
4865 CL22_WR_OVER_CL45(bp, phy,
4866 MDIO_REG_BANK_XGXS_BLOCK2,
4867 MDIO_XGXS_BLOCK2_TX_LN_SWAP,
4868 (tx_lane_swap |
4869 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
4870 } else {
4871 CL22_WR_OVER_CL45(bp, phy,
4872 MDIO_REG_BANK_XGXS_BLOCK2,
4873 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
4874 }
4875 }
4876
4877 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
4878 struct link_params *params)
4879 {
4880 struct bnx2x *bp = params->bp;
4881 u16 control2;
4882 CL22_RD_OVER_CL45(bp, phy,
4883 MDIO_REG_BANK_SERDES_DIGITAL,
4884 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4885 &control2);
4886 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4887 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4888 else
4889 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4890 DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
4891 phy->speed_cap_mask, control2);
4892 CL22_WR_OVER_CL45(bp, phy,
4893 MDIO_REG_BANK_SERDES_DIGITAL,
4894 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4895 control2);
4896
4897 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
4898 (phy->speed_cap_mask &
4899 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
4900 DP(NETIF_MSG_LINK, "XGXS\n");
4901
4902 CL22_WR_OVER_CL45(bp, phy,
4903 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4904 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
4905 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
4906
4907 CL22_RD_OVER_CL45(bp, phy,
4908 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4909 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4910 &control2);
4911
4912
4913 control2 |=
4914 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
4915
4916 CL22_WR_OVER_CL45(bp, phy,
4917 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4918 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4919 control2);
4920
4921 /* Disable parallel detection of HiG */
4922 CL22_WR_OVER_CL45(bp, phy,
4923 MDIO_REG_BANK_XGXS_BLOCK2,
4924 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
4925 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
4926 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
4927 }
4928 }
4929
4930 static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
4931 struct link_params *params,
4932 struct link_vars *vars,
4933 u8 enable_cl73)
4934 {
4935 struct bnx2x *bp = params->bp;
4936 u16 reg_val;
4937
4938 /* CL37 Autoneg */
4939 CL22_RD_OVER_CL45(bp, phy,
4940 MDIO_REG_BANK_COMBO_IEEE0,
4941 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
4942
4943 /* CL37 Autoneg Enabled */
4944 if (vars->line_speed == SPEED_AUTO_NEG)
4945 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
4946 else /* CL37 Autoneg Disabled */
4947 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4948 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
4949
4950 CL22_WR_OVER_CL45(bp, phy,
4951 MDIO_REG_BANK_COMBO_IEEE0,
4952 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
4953
4954 /* Enable/Disable Autodetection */
4955
4956 CL22_RD_OVER_CL45(bp, phy,
4957 MDIO_REG_BANK_SERDES_DIGITAL,
4958 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
4959 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
4960 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
4961 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
4962 if (vars->line_speed == SPEED_AUTO_NEG)
4963 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
4964 else
4965 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
4966
4967 CL22_WR_OVER_CL45(bp, phy,
4968 MDIO_REG_BANK_SERDES_DIGITAL,
4969 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
4970
4971 /* Enable TetonII and BAM autoneg */
4972 CL22_RD_OVER_CL45(bp, phy,
4973 MDIO_REG_BANK_BAM_NEXT_PAGE,
4974 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
4975 &reg_val);
4976 if (vars->line_speed == SPEED_AUTO_NEG) {
4977 /* Enable BAM aneg Mode and TetonII aneg Mode */
4978 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
4979 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4980 } else {
4981 /* TetonII and BAM Autoneg Disabled */
4982 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
4983 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4984 }
4985 CL22_WR_OVER_CL45(bp, phy,
4986 MDIO_REG_BANK_BAM_NEXT_PAGE,
4987 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
4988 reg_val);
4989
4990 if (enable_cl73) {
4991 /* Enable Cl73 FSM status bits */
4992 CL22_WR_OVER_CL45(bp, phy,
4993 MDIO_REG_BANK_CL73_USERB0,
4994 MDIO_CL73_USERB0_CL73_UCTRL,
4995 0xe);
4996
4997 /* Enable BAM Station Manager*/
4998 CL22_WR_OVER_CL45(bp, phy,
4999 MDIO_REG_BANK_CL73_USERB0,
5000 MDIO_CL73_USERB0_CL73_BAM_CTRL1,
5001 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
5002 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
5003 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
5004
5005 /* Advertise CL73 link speeds */
5006 CL22_RD_OVER_CL45(bp, phy,
5007 MDIO_REG_BANK_CL73_IEEEB1,
5008 MDIO_CL73_IEEEB1_AN_ADV2,
5009 &reg_val);
5010 if (phy->speed_cap_mask &
5011 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5012 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
5013 if (phy->speed_cap_mask &
5014 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
5015 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
5016
5017 CL22_WR_OVER_CL45(bp, phy,
5018 MDIO_REG_BANK_CL73_IEEEB1,
5019 MDIO_CL73_IEEEB1_AN_ADV2,
5020 reg_val);
5021
5022 /* CL73 Autoneg Enabled */
5023 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
5024
5025 } else /* CL73 Autoneg Disabled */
5026 reg_val = 0;
5027
5028 CL22_WR_OVER_CL45(bp, phy,
5029 MDIO_REG_BANK_CL73_IEEEB0,
5030 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
5031 }
5032
5033 /* program SerDes, forced speed */
5034 static void bnx2x_program_serdes(struct bnx2x_phy *phy,
5035 struct link_params *params,
5036 struct link_vars *vars)
5037 {
5038 struct bnx2x *bp = params->bp;
5039 u16 reg_val;
5040
5041 /* program duplex, disable autoneg and sgmii*/
5042 CL22_RD_OVER_CL45(bp, phy,
5043 MDIO_REG_BANK_COMBO_IEEE0,
5044 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
5045 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
5046 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5047 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
5048 if (phy->req_duplex == DUPLEX_FULL)
5049 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5050 CL22_WR_OVER_CL45(bp, phy,
5051 MDIO_REG_BANK_COMBO_IEEE0,
5052 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5053
5054 /*
5055 * program speed
5056 * - needed only if the speed is greater than 1G (2.5G or 10G)
5057 */
5058 CL22_RD_OVER_CL45(bp, phy,
5059 MDIO_REG_BANK_SERDES_DIGITAL,
5060 MDIO_SERDES_DIGITAL_MISC1, &reg_val);
5061 /* clearing the speed value before setting the right speed */
5062 DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
5063
5064 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
5065 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5066
5067 if (!((vars->line_speed == SPEED_1000) ||
5068 (vars->line_speed == SPEED_100) ||
5069 (vars->line_speed == SPEED_10))) {
5070
5071 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
5072 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5073 if (vars->line_speed == SPEED_10000)
5074 reg_val |=
5075 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
5076 }
5077
5078 CL22_WR_OVER_CL45(bp, phy,
5079 MDIO_REG_BANK_SERDES_DIGITAL,
5080 MDIO_SERDES_DIGITAL_MISC1, reg_val);
5081
5082 }
5083
5084 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy,
5085 struct link_params *params)
5086 {
5087 struct bnx2x *bp = params->bp;
5088 u16 val = 0;
5089
5090 /* configure the 48 bits for BAM AN */
5091
5092 /* set extended capabilities */
5093 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
5094 val |= MDIO_OVER_1G_UP1_2_5G;
5095 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5096 val |= MDIO_OVER_1G_UP1_10G;
5097 CL22_WR_OVER_CL45(bp, phy,
5098 MDIO_REG_BANK_OVER_1G,
5099 MDIO_OVER_1G_UP1, val);
5100
5101 CL22_WR_OVER_CL45(bp, phy,
5102 MDIO_REG_BANK_OVER_1G,
5103 MDIO_OVER_1G_UP3, 0x400);
5104 }
5105
5106 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy,
5107 struct link_params *params,
5108 u16 ieee_fc)
5109 {
5110 struct bnx2x *bp = params->bp;
5111 u16 val;
5112 /* for AN, we are always publishing full duplex */
5113
5114 CL22_WR_OVER_CL45(bp, phy,
5115 MDIO_REG_BANK_COMBO_IEEE0,
5116 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
5117 CL22_RD_OVER_CL45(bp, phy,
5118 MDIO_REG_BANK_CL73_IEEEB1,
5119 MDIO_CL73_IEEEB1_AN_ADV1, &val);
5120 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
5121 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
5122 CL22_WR_OVER_CL45(bp, phy,
5123 MDIO_REG_BANK_CL73_IEEEB1,
5124 MDIO_CL73_IEEEB1_AN_ADV1, val);
5125 }
5126
5127 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
5128 struct link_params *params,
5129 u8 enable_cl73)
5130 {
5131 struct bnx2x *bp = params->bp;
5132 u16 mii_control;
5133
5134 DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
5135 /* Enable and restart BAM/CL37 aneg */
5136
5137 if (enable_cl73) {
5138 CL22_RD_OVER_CL45(bp, phy,
5139 MDIO_REG_BANK_CL73_IEEEB0,
5140 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5141 &mii_control);
5142
5143 CL22_WR_OVER_CL45(bp, phy,
5144 MDIO_REG_BANK_CL73_IEEEB0,
5145 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5146 (mii_control |
5147 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
5148 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
5149 } else {
5150
5151 CL22_RD_OVER_CL45(bp, phy,
5152 MDIO_REG_BANK_COMBO_IEEE0,
5153 MDIO_COMBO_IEEE0_MII_CONTROL,
5154 &mii_control);
5155 DP(NETIF_MSG_LINK,
5156 "bnx2x_restart_autoneg mii_control before = 0x%x\n",
5157 mii_control);
5158 CL22_WR_OVER_CL45(bp, phy,
5159 MDIO_REG_BANK_COMBO_IEEE0,
5160 MDIO_COMBO_IEEE0_MII_CONTROL,
5161 (mii_control |
5162 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5163 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
5164 }
5165 }
5166
5167 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
5168 struct link_params *params,
5169 struct link_vars *vars)
5170 {
5171 struct bnx2x *bp = params->bp;
5172 u16 control1;
5173
5174 /* in SGMII mode, the unicore is always slave */
5175
5176 CL22_RD_OVER_CL45(bp, phy,
5177 MDIO_REG_BANK_SERDES_DIGITAL,
5178 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5179 &control1);
5180 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
5181 /* set sgmii mode (and not fiber) */
5182 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
5183 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
5184 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
5185 CL22_WR_OVER_CL45(bp, phy,
5186 MDIO_REG_BANK_SERDES_DIGITAL,
5187 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5188 control1);
5189
5190 /* if forced speed */
5191 if (!(vars->line_speed == SPEED_AUTO_NEG)) {
5192 /* set speed, disable autoneg */
5193 u16 mii_control;
5194
5195 CL22_RD_OVER_CL45(bp, phy,
5196 MDIO_REG_BANK_COMBO_IEEE0,
5197 MDIO_COMBO_IEEE0_MII_CONTROL,
5198 &mii_control);
5199 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5200 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
5201 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
5202
5203 switch (vars->line_speed) {
5204 case SPEED_100:
5205 mii_control |=
5206 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
5207 break;
5208 case SPEED_1000:
5209 mii_control |=
5210 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
5211 break;
5212 case SPEED_10:
5213 /* there is nothing to set for 10M */
5214 break;
5215 default:
5216 /* invalid speed for SGMII */
5217 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5218 vars->line_speed);
5219 break;
5220 }
5221
5222 /* setting the full duplex */
5223 if (phy->req_duplex == DUPLEX_FULL)
5224 mii_control |=
5225 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5226 CL22_WR_OVER_CL45(bp, phy,
5227 MDIO_REG_BANK_COMBO_IEEE0,
5228 MDIO_COMBO_IEEE0_MII_CONTROL,
5229 mii_control);
5230
5231 } else { /* AN mode */
5232 /* enable and restart AN */
5233 bnx2x_restart_autoneg(phy, params, 0);
5234 }
5235 }
5236
5237
5238 /*
5239 * link management
5240 */
5241
5242 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
5243 struct link_params *params)
5244 {
5245 struct bnx2x *bp = params->bp;
5246 u16 pd_10g, status2_1000x;
5247 if (phy->req_line_speed != SPEED_AUTO_NEG)
5248 return 0;
5249 CL22_RD_OVER_CL45(bp, phy,
5250 MDIO_REG_BANK_SERDES_DIGITAL,
5251 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5252 &status2_1000x);
5253 CL22_RD_OVER_CL45(bp, phy,
5254 MDIO_REG_BANK_SERDES_DIGITAL,
5255 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5256 &status2_1000x);
5257 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
5258 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
5259 params->port);
5260 return 1;
5261 }
5262
5263 CL22_RD_OVER_CL45(bp, phy,
5264 MDIO_REG_BANK_10G_PARALLEL_DETECT,
5265 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
5266 &pd_10g);
5267
5268 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
5269 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
5270 params->port);
5271 return 1;
5272 }
5273 return 0;
5274 }
5275
5276 static void bnx2x_update_adv_fc(struct bnx2x_phy *phy,
5277 struct link_params *params,
5278 struct link_vars *vars,
5279 u32 gp_status)
5280 {
5281 u16 ld_pause; /* local driver */
5282 u16 lp_pause; /* link partner */
5283 u16 pause_result;
5284 struct bnx2x *bp = params->bp;
5285 if ((gp_status &
5286 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5287 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
5288 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5289 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
5290
5291 CL22_RD_OVER_CL45(bp, phy,
5292 MDIO_REG_BANK_CL73_IEEEB1,
5293 MDIO_CL73_IEEEB1_AN_ADV1,
5294 &ld_pause);
5295 CL22_RD_OVER_CL45(bp, phy,
5296 MDIO_REG_BANK_CL73_IEEEB1,
5297 MDIO_CL73_IEEEB1_AN_LP_ADV1,
5298 &lp_pause);
5299 pause_result = (ld_pause &
5300 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8;
5301 pause_result |= (lp_pause &
5302 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10;
5303 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n", pause_result);
5304 } else {
5305 CL22_RD_OVER_CL45(bp, phy,
5306 MDIO_REG_BANK_COMBO_IEEE0,
5307 MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
5308 &ld_pause);
5309 CL22_RD_OVER_CL45(bp, phy,
5310 MDIO_REG_BANK_COMBO_IEEE0,
5311 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
5312 &lp_pause);
5313 pause_result = (ld_pause &
5314 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
5315 pause_result |= (lp_pause &
5316 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
5317 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n", pause_result);
5318 }
5319 bnx2x_pause_resolve(vars, pause_result);
5320
5321 }
5322
5323 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
5324 struct link_params *params,
5325 struct link_vars *vars,
5326 u32 gp_status)
5327 {
5328 struct bnx2x *bp = params->bp;
5329 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5330
5331 /* resolve from gp_status in case of AN complete and not sgmii */
5332 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
5333 /* Update the advertised flow-controled of LD/LP in AN */
5334 if (phy->req_line_speed == SPEED_AUTO_NEG)
5335 bnx2x_update_adv_fc(phy, params, vars, gp_status);
5336 /* But set the flow-control result as the requested one */
5337 vars->flow_ctrl = phy->req_flow_ctrl;
5338 } else if (phy->req_line_speed != SPEED_AUTO_NEG)
5339 vars->flow_ctrl = params->req_fc_auto_adv;
5340 else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
5341 (!(vars->phy_flags & PHY_SGMII_FLAG))) {
5342 if (bnx2x_direct_parallel_detect_used(phy, params)) {
5343 vars->flow_ctrl = params->req_fc_auto_adv;
5344 return;
5345 }
5346 bnx2x_update_adv_fc(phy, params, vars, gp_status);
5347 }
5348 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
5349 }
5350
5351 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
5352 struct link_params *params)
5353 {
5354 struct bnx2x *bp = params->bp;
5355 u16 rx_status, ustat_val, cl37_fsm_received;
5356 DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
5357 /* Step 1: Make sure signal is detected */
5358 CL22_RD_OVER_CL45(bp, phy,
5359 MDIO_REG_BANK_RX0,
5360 MDIO_RX0_RX_STATUS,
5361 &rx_status);
5362 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
5363 (MDIO_RX0_RX_STATUS_SIGDET)) {
5364 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
5365 "rx_status(0x80b0) = 0x%x\n", rx_status);
5366 CL22_WR_OVER_CL45(bp, phy,
5367 MDIO_REG_BANK_CL73_IEEEB0,
5368 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5369 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
5370 return;
5371 }
5372 /* Step 2: Check CL73 state machine */
5373 CL22_RD_OVER_CL45(bp, phy,
5374 MDIO_REG_BANK_CL73_USERB0,
5375 MDIO_CL73_USERB0_CL73_USTAT1,
5376 &ustat_val);
5377 if ((ustat_val &
5378 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5379 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
5380 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5381 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
5382 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
5383 "ustat_val(0x8371) = 0x%x\n", ustat_val);
5384 return;
5385 }
5386 /*
5387 * Step 3: Check CL37 Message Pages received to indicate LP
5388 * supports only CL37
5389 */
5390 CL22_RD_OVER_CL45(bp, phy,
5391 MDIO_REG_BANK_REMOTE_PHY,
5392 MDIO_REMOTE_PHY_MISC_RX_STATUS,
5393 &cl37_fsm_received);
5394 if ((cl37_fsm_received &
5395 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5396 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
5397 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5398 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
5399 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
5400 "misc_rx_status(0x8330) = 0x%x\n",
5401 cl37_fsm_received);
5402 return;
5403 }
5404 /*
5405 * The combined cl37/cl73 fsm state information indicating that
5406 * we are connected to a device which does not support cl73, but
5407 * does support cl37 BAM. In this case we disable cl73 and
5408 * restart cl37 auto-neg
5409 */
5410
5411 /* Disable CL73 */
5412 CL22_WR_OVER_CL45(bp, phy,
5413 MDIO_REG_BANK_CL73_IEEEB0,
5414 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5415 0);
5416 /* Restart CL37 autoneg */
5417 bnx2x_restart_autoneg(phy, params, 0);
5418 DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
5419 }
5420
5421 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
5422 struct link_params *params,
5423 struct link_vars *vars,
5424 u32 gp_status)
5425 {
5426 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
5427 vars->link_status |=
5428 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5429
5430 if (bnx2x_direct_parallel_detect_used(phy, params))
5431 vars->link_status |=
5432 LINK_STATUS_PARALLEL_DETECTION_USED;
5433 }
5434 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy,
5435 struct link_params *params,
5436 struct link_vars *vars,
5437 u16 is_link_up,
5438 u16 speed_mask,
5439 u16 is_duplex)
5440 {
5441 struct bnx2x *bp = params->bp;
5442 if (phy->req_line_speed == SPEED_AUTO_NEG)
5443 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
5444 if (is_link_up) {
5445 DP(NETIF_MSG_LINK, "phy link up\n");
5446
5447 vars->phy_link_up = 1;
5448 vars->link_status |= LINK_STATUS_LINK_UP;
5449
5450 switch (speed_mask) {
5451 case GP_STATUS_10M:
5452 vars->line_speed = SPEED_10;
5453 if (vars->duplex == DUPLEX_FULL)
5454 vars->link_status |= LINK_10TFD;
5455 else
5456 vars->link_status |= LINK_10THD;
5457 break;
5458
5459 case GP_STATUS_100M:
5460 vars->line_speed = SPEED_100;
5461 if (vars->duplex == DUPLEX_FULL)
5462 vars->link_status |= LINK_100TXFD;
5463 else
5464 vars->link_status |= LINK_100TXHD;
5465 break;
5466
5467 case GP_STATUS_1G:
5468 case GP_STATUS_1G_KX:
5469 vars->line_speed = SPEED_1000;
5470 if (vars->duplex == DUPLEX_FULL)
5471 vars->link_status |= LINK_1000TFD;
5472 else
5473 vars->link_status |= LINK_1000THD;
5474 break;
5475
5476 case GP_STATUS_2_5G:
5477 vars->line_speed = SPEED_2500;
5478 if (vars->duplex == DUPLEX_FULL)
5479 vars->link_status |= LINK_2500TFD;
5480 else
5481 vars->link_status |= LINK_2500THD;
5482 break;
5483
5484 case GP_STATUS_5G:
5485 case GP_STATUS_6G:
5486 DP(NETIF_MSG_LINK,
5487 "link speed unsupported gp_status 0x%x\n",
5488 speed_mask);
5489 return -EINVAL;
5490
5491 case GP_STATUS_10G_KX4:
5492 case GP_STATUS_10G_HIG:
5493 case GP_STATUS_10G_CX4:
5494 case GP_STATUS_10G_KR:
5495 case GP_STATUS_10G_SFI:
5496 case GP_STATUS_10G_XFI:
5497 vars->line_speed = SPEED_10000;
5498 vars->link_status |= LINK_10GTFD;
5499 break;
5500 case GP_STATUS_20G_DXGXS:
5501 vars->line_speed = SPEED_20000;
5502 vars->link_status |= LINK_20GTFD;
5503 break;
5504 default:
5505 DP(NETIF_MSG_LINK,
5506 "link speed unsupported gp_status 0x%x\n",
5507 speed_mask);
5508 return -EINVAL;
5509 }
5510 } else { /* link_down */
5511 DP(NETIF_MSG_LINK, "phy link down\n");
5512
5513 vars->phy_link_up = 0;
5514
5515 vars->duplex = DUPLEX_FULL;
5516 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5517 vars->mac_type = MAC_TYPE_NONE;
5518 }
5519 DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n",
5520 vars->phy_link_up, vars->line_speed);
5521 return 0;
5522 }
5523
5524 static int bnx2x_link_settings_status(struct bnx2x_phy *phy,
5525 struct link_params *params,
5526 struct link_vars *vars)
5527 {
5528 struct bnx2x *bp = params->bp;
5529
5530 u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
5531 int rc = 0;
5532
5533 /* Read gp_status */
5534 CL22_RD_OVER_CL45(bp, phy,
5535 MDIO_REG_BANK_GP_STATUS,
5536 MDIO_GP_STATUS_TOP_AN_STATUS1,
5537 &gp_status);
5538 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
5539 duplex = DUPLEX_FULL;
5540 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
5541 link_up = 1;
5542 speed_mask = gp_status & GP_STATUS_SPEED_MASK;
5543 DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",
5544 gp_status, link_up, speed_mask);
5545 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
5546 duplex);
5547 if (rc == -EINVAL)
5548 return rc;
5549
5550 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
5551 if (SINGLE_MEDIA_DIRECT(params)) {
5552 bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
5553 if (phy->req_line_speed == SPEED_AUTO_NEG)
5554 bnx2x_xgxs_an_resolve(phy, params, vars,
5555 gp_status);
5556 }
5557 } else { /* link_down */
5558 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5559 SINGLE_MEDIA_DIRECT(params)) {
5560 /* Check signal is detected */
5561 bnx2x_check_fallback_to_cl37(phy, params);
5562 }
5563 }
5564
5565 /* Read LP advertised speeds*/
5566 if (SINGLE_MEDIA_DIRECT(params) &&
5567 (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) {
5568 u16 val;
5569
5570 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_CL73_IEEEB1,
5571 MDIO_CL73_IEEEB1_AN_LP_ADV2, &val);
5572
5573 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5574 vars->link_status |=
5575 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5576 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5577 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5578 vars->link_status |=
5579 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5580
5581 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_OVER_1G,
5582 MDIO_OVER_1G_LP_UP1, &val);
5583
5584 if (val & MDIO_OVER_1G_UP1_2_5G)
5585 vars->link_status |=
5586 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5587 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5588 vars->link_status |=
5589 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5590 }
5591
5592 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
5593 vars->duplex, vars->flow_ctrl, vars->link_status);
5594 return rc;
5595 }
5596
5597 static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy,
5598 struct link_params *params,
5599 struct link_vars *vars)
5600 {
5601 struct bnx2x *bp = params->bp;
5602 u8 lane;
5603 u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
5604 int rc = 0;
5605 lane = bnx2x_get_warpcore_lane(phy, params);
5606 /* Read gp_status */
5607 if (phy->req_line_speed > SPEED_10000) {
5608 u16 temp_link_up;
5609 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5610 1, &temp_link_up);
5611 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5612 1, &link_up);
5613 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n",
5614 temp_link_up, link_up);
5615 link_up &= (1<<2);
5616 if (link_up)
5617 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5618 } else {
5619 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5620 MDIO_WC_REG_GP2_STATUS_GP_2_1, &gp_status1);
5621 DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1);
5622 /* Check for either KR or generic link up. */
5623 gp_status1 = ((gp_status1 >> 8) & 0xf) |
5624 ((gp_status1 >> 12) & 0xf);
5625 link_up = gp_status1 & (1 << lane);
5626 if (link_up && SINGLE_MEDIA_DIRECT(params)) {
5627 u16 pd, gp_status4;
5628 if (phy->req_line_speed == SPEED_AUTO_NEG) {
5629 /* Check Autoneg complete */
5630 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5631 MDIO_WC_REG_GP2_STATUS_GP_2_4,
5632 &gp_status4);
5633 if (gp_status4 & ((1<<12)<<lane))
5634 vars->link_status |=
5635 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5636
5637 /* Check parallel detect used */
5638 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5639 MDIO_WC_REG_PAR_DET_10G_STATUS,
5640 &pd);
5641 if (pd & (1<<15))
5642 vars->link_status |=
5643 LINK_STATUS_PARALLEL_DETECTION_USED;
5644 }
5645 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5646 }
5647 }
5648
5649 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) &&
5650 SINGLE_MEDIA_DIRECT(params)) {
5651 u16 val;
5652
5653 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5654 MDIO_AN_REG_LP_AUTO_NEG2, &val);
5655
5656 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5657 vars->link_status |=
5658 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5659 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5660 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5661 vars->link_status |=
5662 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5663
5664 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5665 MDIO_WC_REG_DIGITAL3_LP_UP1, &val);
5666
5667 if (val & MDIO_OVER_1G_UP1_2_5G)
5668 vars->link_status |=
5669 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5670 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5671 vars->link_status |=
5672 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5673
5674 }
5675
5676
5677 if (lane < 2) {
5678 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5679 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
5680 } else {
5681 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5682 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
5683 }
5684 DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed);
5685
5686 if ((lane & 1) == 0)
5687 gp_speed <<= 8;
5688 gp_speed &= 0x3f00;
5689
5690
5691 rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
5692 duplex);
5693
5694 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
5695 vars->duplex, vars->flow_ctrl, vars->link_status);
5696 return rc;
5697 }
5698 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
5699 {
5700 struct bnx2x *bp = params->bp;
5701 struct bnx2x_phy *phy = &params->phy[INT_PHY];
5702 u16 lp_up2;
5703 u16 tx_driver;
5704 u16 bank;
5705
5706 /* read precomp */
5707 CL22_RD_OVER_CL45(bp, phy,
5708 MDIO_REG_BANK_OVER_1G,
5709 MDIO_OVER_1G_LP_UP2, &lp_up2);
5710
5711 /* bits [10:7] at lp_up2, positioned at [15:12] */
5712 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
5713 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
5714 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
5715
5716 if (lp_up2 == 0)
5717 return;
5718
5719 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
5720 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
5721 CL22_RD_OVER_CL45(bp, phy,
5722 bank,
5723 MDIO_TX0_TX_DRIVER, &tx_driver);
5724
5725 /* replace tx_driver bits [15:12] */
5726 if (lp_up2 !=
5727 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
5728 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
5729 tx_driver |= lp_up2;
5730 CL22_WR_OVER_CL45(bp, phy,
5731 bank,
5732 MDIO_TX0_TX_DRIVER, tx_driver);
5733 }
5734 }
5735 }
5736
5737 static int bnx2x_emac_program(struct link_params *params,
5738 struct link_vars *vars)
5739 {
5740 struct bnx2x *bp = params->bp;
5741 u8 port = params->port;
5742 u16 mode = 0;
5743
5744 DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
5745 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
5746 EMAC_REG_EMAC_MODE,
5747 (EMAC_MODE_25G_MODE |
5748 EMAC_MODE_PORT_MII_10M |
5749 EMAC_MODE_HALF_DUPLEX));
5750 switch (vars->line_speed) {
5751 case SPEED_10:
5752 mode |= EMAC_MODE_PORT_MII_10M;
5753 break;
5754
5755 case SPEED_100:
5756 mode |= EMAC_MODE_PORT_MII;
5757 break;
5758
5759 case SPEED_1000:
5760 mode |= EMAC_MODE_PORT_GMII;
5761 break;
5762
5763 case SPEED_2500:
5764 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
5765 break;
5766
5767 default:
5768 /* 10G not valid for EMAC */
5769 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5770 vars->line_speed);
5771 return -EINVAL;
5772 }
5773
5774 if (vars->duplex == DUPLEX_HALF)
5775 mode |= EMAC_MODE_HALF_DUPLEX;
5776 bnx2x_bits_en(bp,
5777 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
5778 mode);
5779
5780 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
5781 return 0;
5782 }
5783
5784 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
5785 struct link_params *params)
5786 {
5787
5788 u16 bank, i = 0;
5789 struct bnx2x *bp = params->bp;
5790
5791 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
5792 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
5793 CL22_WR_OVER_CL45(bp, phy,
5794 bank,
5795 MDIO_RX0_RX_EQ_BOOST,
5796 phy->rx_preemphasis[i]);
5797 }
5798
5799 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
5800 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
5801 CL22_WR_OVER_CL45(bp, phy,
5802 bank,
5803 MDIO_TX0_TX_DRIVER,
5804 phy->tx_preemphasis[i]);
5805 }
5806 }
5807
5808 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy,
5809 struct link_params *params,
5810 struct link_vars *vars)
5811 {
5812 struct bnx2x *bp = params->bp;
5813 u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
5814 (params->loopback_mode == LOOPBACK_XGXS));
5815 if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
5816 if (SINGLE_MEDIA_DIRECT(params) &&
5817 (params->feature_config_flags &
5818 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
5819 bnx2x_set_preemphasis(phy, params);
5820
5821 /* forced speed requested? */
5822 if (vars->line_speed != SPEED_AUTO_NEG ||
5823 (SINGLE_MEDIA_DIRECT(params) &&
5824 params->loopback_mode == LOOPBACK_EXT)) {
5825 DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
5826
5827 /* disable autoneg */
5828 bnx2x_set_autoneg(phy, params, vars, 0);
5829
5830 /* program speed and duplex */
5831 bnx2x_program_serdes(phy, params, vars);
5832
5833 } else { /* AN_mode */
5834 DP(NETIF_MSG_LINK, "not SGMII, AN\n");
5835
5836 /* AN enabled */
5837 bnx2x_set_brcm_cl37_advertisement(phy, params);
5838
5839 /* program duplex & pause advertisement (for aneg) */
5840 bnx2x_set_ieee_aneg_advertisement(phy, params,
5841 vars->ieee_fc);
5842
5843 /* enable autoneg */
5844 bnx2x_set_autoneg(phy, params, vars, enable_cl73);
5845
5846 /* enable and restart AN */
5847 bnx2x_restart_autoneg(phy, params, enable_cl73);
5848 }
5849
5850 } else { /* SGMII mode */
5851 DP(NETIF_MSG_LINK, "SGMII\n");
5852
5853 bnx2x_initialize_sgmii_process(phy, params, vars);
5854 }
5855 }
5856
5857 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy,
5858 struct link_params *params,
5859 struct link_vars *vars)
5860 {
5861 int rc;
5862 vars->phy_flags |= PHY_XGXS_FLAG;
5863 if ((phy->req_line_speed &&
5864 ((phy->req_line_speed == SPEED_100) ||
5865 (phy->req_line_speed == SPEED_10))) ||
5866 (!phy->req_line_speed &&
5867 (phy->speed_cap_mask >=
5868 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5869 (phy->speed_cap_mask <
5870 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5871 (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
5872 vars->phy_flags |= PHY_SGMII_FLAG;
5873 else
5874 vars->phy_flags &= ~PHY_SGMII_FLAG;
5875
5876 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
5877 bnx2x_set_aer_mmd(params, phy);
5878 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
5879 bnx2x_set_master_ln(params, phy);
5880
5881 rc = bnx2x_reset_unicore(params, phy, 0);
5882 /* reset the SerDes and wait for reset bit return low */
5883 if (rc != 0)
5884 return rc;
5885
5886 bnx2x_set_aer_mmd(params, phy);
5887 /* setting the masterLn_def again after the reset */
5888 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
5889 bnx2x_set_master_ln(params, phy);
5890 bnx2x_set_swap_lanes(params, phy);
5891 }
5892
5893 return rc;
5894 }
5895
5896 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
5897 struct bnx2x_phy *phy,
5898 struct link_params *params)
5899 {
5900 u16 cnt, ctrl;
5901 /* Wait for soft reset to get cleared up to 1 sec */
5902 for (cnt = 0; cnt < 1000; cnt++) {
5903 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
5904 bnx2x_cl22_read(bp, phy,
5905 MDIO_PMA_REG_CTRL, &ctrl);
5906 else
5907 bnx2x_cl45_read(bp, phy,
5908 MDIO_PMA_DEVAD,
5909 MDIO_PMA_REG_CTRL, &ctrl);
5910 if (!(ctrl & (1<<15)))
5911 break;
5912 msleep(1);
5913 }
5914
5915 if (cnt == 1000)
5916 netdev_err(bp->dev, "Warning: PHY was not initialized,"
5917 " Port %d\n",
5918 params->port);
5919 DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
5920 return cnt;
5921 }
5922
5923 static void bnx2x_link_int_enable(struct link_params *params)
5924 {
5925 u8 port = params->port;
5926 u32 mask;
5927 struct bnx2x *bp = params->bp;
5928
5929 /* Setting the status to report on link up for either XGXS or SerDes */
5930 if (CHIP_IS_E3(bp)) {
5931 mask = NIG_MASK_XGXS0_LINK_STATUS;
5932 if (!(SINGLE_MEDIA_DIRECT(params)))
5933 mask |= NIG_MASK_MI_INT;
5934 } else if (params->switch_cfg == SWITCH_CFG_10G) {
5935 mask = (NIG_MASK_XGXS0_LINK10G |
5936 NIG_MASK_XGXS0_LINK_STATUS);
5937 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
5938 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5939 params->phy[INT_PHY].type !=
5940 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
5941 mask |= NIG_MASK_MI_INT;
5942 DP(NETIF_MSG_LINK, "enabled external phy int\n");
5943 }
5944
5945 } else { /* SerDes */
5946 mask = NIG_MASK_SERDES0_LINK_STATUS;
5947 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
5948 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5949 params->phy[INT_PHY].type !=
5950 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
5951 mask |= NIG_MASK_MI_INT;
5952 DP(NETIF_MSG_LINK, "enabled external phy int\n");
5953 }
5954 }
5955 bnx2x_bits_en(bp,
5956 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
5957 mask);
5958
5959 DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
5960 (params->switch_cfg == SWITCH_CFG_10G),
5961 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
5962 DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
5963 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
5964 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
5965 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
5966 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
5967 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
5968 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
5969 }
5970
5971 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
5972 u8 exp_mi_int)
5973 {
5974 u32 latch_status = 0;
5975
5976 /*
5977 * Disable the MI INT ( external phy int ) by writing 1 to the
5978 * status register. Link down indication is high-active-signal,
5979 * so in this case we need to write the status to clear the XOR
5980 */
5981 /* Read Latched signals */
5982 latch_status = REG_RD(bp,
5983 NIG_REG_LATCH_STATUS_0 + port*8);
5984 DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
5985 /* Handle only those with latched-signal=up.*/
5986 if (exp_mi_int)
5987 bnx2x_bits_en(bp,
5988 NIG_REG_STATUS_INTERRUPT_PORT0
5989 + port*4,
5990 NIG_STATUS_EMAC0_MI_INT);
5991 else
5992 bnx2x_bits_dis(bp,
5993 NIG_REG_STATUS_INTERRUPT_PORT0
5994 + port*4,
5995 NIG_STATUS_EMAC0_MI_INT);
5996
5997 if (latch_status & 1) {
5998
5999 /* For all latched-signal=up : Re-Arm Latch signals */
6000 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
6001 (latch_status & 0xfffe) | (latch_status & 1));
6002 }
6003 /* For all latched-signal=up,Write original_signal to status */
6004 }
6005
6006 static void bnx2x_link_int_ack(struct link_params *params,
6007 struct link_vars *vars, u8 is_10g_plus)
6008 {
6009 struct bnx2x *bp = params->bp;
6010 u8 port = params->port;
6011 u32 mask;
6012 /*
6013 * First reset all status we assume only one line will be
6014 * change at a time
6015 */
6016 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6017 (NIG_STATUS_XGXS0_LINK10G |
6018 NIG_STATUS_XGXS0_LINK_STATUS |
6019 NIG_STATUS_SERDES0_LINK_STATUS));
6020 if (vars->phy_link_up) {
6021 if (USES_WARPCORE(bp))
6022 mask = NIG_STATUS_XGXS0_LINK_STATUS;
6023 else {
6024 if (is_10g_plus)
6025 mask = NIG_STATUS_XGXS0_LINK10G;
6026 else if (params->switch_cfg == SWITCH_CFG_10G) {
6027 /*
6028 * Disable the link interrupt by writing 1 to
6029 * the relevant lane in the status register
6030 */
6031 u32 ser_lane =
6032 ((params->lane_config &
6033 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
6034 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
6035 mask = ((1 << ser_lane) <<
6036 NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
6037 } else
6038 mask = NIG_STATUS_SERDES0_LINK_STATUS;
6039 }
6040 DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n",
6041 mask);
6042 bnx2x_bits_en(bp,
6043 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6044 mask);
6045 }
6046 }
6047
6048 static int bnx2x_format_ver(u32 num, u8 *str, u16 *len)
6049 {
6050 u8 *str_ptr = str;
6051 u32 mask = 0xf0000000;
6052 u8 shift = 8*4;
6053 u8 digit;
6054 u8 remove_leading_zeros = 1;
6055 if (*len < 10) {
6056 /* Need more than 10chars for this format */
6057 *str_ptr = '\0';
6058 (*len)--;
6059 return -EINVAL;
6060 }
6061 while (shift > 0) {
6062
6063 shift -= 4;
6064 digit = ((num & mask) >> shift);
6065 if (digit == 0 && remove_leading_zeros) {
6066 mask = mask >> 4;
6067 continue;
6068 } else if (digit < 0xa)
6069 *str_ptr = digit + '0';
6070 else
6071 *str_ptr = digit - 0xa + 'a';
6072 remove_leading_zeros = 0;
6073 str_ptr++;
6074 (*len)--;
6075 mask = mask >> 4;
6076 if (shift == 4*4) {
6077 *str_ptr = '.';
6078 str_ptr++;
6079 (*len)--;
6080 remove_leading_zeros = 1;
6081 }
6082 }
6083 return 0;
6084 }
6085
6086
6087 static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
6088 {
6089 str[0] = '\0';
6090 (*len)--;
6091 return 0;
6092 }
6093
6094 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version,
6095 u16 len)
6096 {
6097 struct bnx2x *bp;
6098 u32 spirom_ver = 0;
6099 int status = 0;
6100 u8 *ver_p = version;
6101 u16 remain_len = len;
6102 if (version == NULL || params == NULL)
6103 return -EINVAL;
6104 bp = params->bp;
6105
6106 /* Extract first external phy*/
6107 version[0] = '\0';
6108 spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
6109
6110 if (params->phy[EXT_PHY1].format_fw_ver) {
6111 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
6112 ver_p,
6113 &remain_len);
6114 ver_p += (len - remain_len);
6115 }
6116 if ((params->num_phys == MAX_PHYS) &&
6117 (params->phy[EXT_PHY2].ver_addr != 0)) {
6118 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
6119 if (params->phy[EXT_PHY2].format_fw_ver) {
6120 *ver_p = '/';
6121 ver_p++;
6122 remain_len--;
6123 status |= params->phy[EXT_PHY2].format_fw_ver(
6124 spirom_ver,
6125 ver_p,
6126 &remain_len);
6127 ver_p = version + (len - remain_len);
6128 }
6129 }
6130 *ver_p = '\0';
6131 return status;
6132 }
6133
6134 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
6135 struct link_params *params)
6136 {
6137 u8 port = params->port;
6138 struct bnx2x *bp = params->bp;
6139
6140 if (phy->req_line_speed != SPEED_1000) {
6141 u32 md_devad = 0;
6142
6143 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
6144
6145 if (!CHIP_IS_E3(bp)) {
6146 /* change the uni_phy_addr in the nig */
6147 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
6148 port*0x18));
6149
6150 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6151 0x5);
6152 }
6153
6154 bnx2x_cl45_write(bp, phy,
6155 5,
6156 (MDIO_REG_BANK_AER_BLOCK +
6157 (MDIO_AER_BLOCK_AER_REG & 0xf)),
6158 0x2800);
6159
6160 bnx2x_cl45_write(bp, phy,
6161 5,
6162 (MDIO_REG_BANK_CL73_IEEEB0 +
6163 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
6164 0x6041);
6165 msleep(200);
6166 /* set aer mmd back */
6167 bnx2x_set_aer_mmd(params, phy);
6168
6169 if (!CHIP_IS_E3(bp)) {
6170 /* and md_devad */
6171 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6172 md_devad);
6173 }
6174 } else {
6175 u16 mii_ctrl;
6176 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
6177 bnx2x_cl45_read(bp, phy, 5,
6178 (MDIO_REG_BANK_COMBO_IEEE0 +
6179 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6180 &mii_ctrl);
6181 bnx2x_cl45_write(bp, phy, 5,
6182 (MDIO_REG_BANK_COMBO_IEEE0 +
6183 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6184 mii_ctrl |
6185 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
6186 }
6187 }
6188
6189 int bnx2x_set_led(struct link_params *params,
6190 struct link_vars *vars, u8 mode, u32 speed)
6191 {
6192 u8 port = params->port;
6193 u16 hw_led_mode = params->hw_led_mode;
6194 int rc = 0;
6195 u8 phy_idx;
6196 u32 tmp;
6197 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
6198 struct bnx2x *bp = params->bp;
6199 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
6200 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
6201 speed, hw_led_mode);
6202 /* In case */
6203 for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
6204 if (params->phy[phy_idx].set_link_led) {
6205 params->phy[phy_idx].set_link_led(
6206 &params->phy[phy_idx], params, mode);
6207 }
6208 }
6209
6210 switch (mode) {
6211 case LED_MODE_FRONT_PANEL_OFF:
6212 case LED_MODE_OFF:
6213 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
6214 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6215 SHARED_HW_CFG_LED_MAC1);
6216
6217 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6218 if (params->phy[EXT_PHY1].type ==
6219 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
6220 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp & 0xfff1);
6221 else {
6222 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6223 (tmp | EMAC_LED_OVERRIDE));
6224 }
6225 break;
6226
6227 case LED_MODE_OPER:
6228 /*
6229 * For all other phys, OPER mode is same as ON, so in case
6230 * link is down, do nothing
6231 */
6232 if (!vars->link_up)
6233 break;
6234 case LED_MODE_ON:
6235 if (((params->phy[EXT_PHY1].type ==
6236 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
6237 (params->phy[EXT_PHY1].type ==
6238 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
6239 CHIP_IS_E2(bp) && params->num_phys == 2) {
6240 /*
6241 * This is a work-around for E2+8727 Configurations
6242 */
6243 if (mode == LED_MODE_ON ||
6244 speed == SPEED_10000){
6245 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6246 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6247
6248 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6249 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6250 (tmp | EMAC_LED_OVERRIDE));
6251 /*
6252 * return here without enabling traffic
6253 * LED blink and setting rate in ON mode.
6254 * In oper mode, enabling LED blink
6255 * and setting rate is needed.
6256 */
6257 if (mode == LED_MODE_ON)
6258 return rc;
6259 }
6260 } else if (SINGLE_MEDIA_DIRECT(params)) {
6261 /*
6262 * This is a work-around for HW issue found when link
6263 * is up in CL73
6264 */
6265 if ((!CHIP_IS_E3(bp)) ||
6266 (CHIP_IS_E3(bp) &&
6267 mode == LED_MODE_ON))
6268 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6269
6270 if (CHIP_IS_E1x(bp) ||
6271 CHIP_IS_E2(bp) ||
6272 (mode == LED_MODE_ON))
6273 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6274 else
6275 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6276 hw_led_mode);
6277 } else if ((params->phy[EXT_PHY1].type ==
6278 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) &&
6279 (mode != LED_MODE_OPER)) {
6280 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6281 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6282 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp | 0x3);
6283 } else
6284 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6285 hw_led_mode);
6286
6287 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
6288 /* Set blinking rate to ~15.9Hz */
6289 if (CHIP_IS_E3(bp))
6290 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6291 LED_BLINK_RATE_VAL_E3);
6292 else
6293 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6294 LED_BLINK_RATE_VAL_E1X_E2);
6295 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
6296 port*4, 1);
6297 if ((params->phy[EXT_PHY1].type !=
6298 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) &&
6299 (mode != LED_MODE_OPER)) {
6300 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6301 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6302 (tmp & (~EMAC_LED_OVERRIDE)));
6303 }
6304
6305 if (CHIP_IS_E1(bp) &&
6306 ((speed == SPEED_2500) ||
6307 (speed == SPEED_1000) ||
6308 (speed == SPEED_100) ||
6309 (speed == SPEED_10))) {
6310 /*
6311 * On Everest 1 Ax chip versions for speeds less than
6312 * 10G LED scheme is different
6313 */
6314 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
6315 + port*4, 1);
6316 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
6317 port*4, 0);
6318 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
6319 port*4, 1);
6320 }
6321 break;
6322
6323 default:
6324 rc = -EINVAL;
6325 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
6326 mode);
6327 break;
6328 }
6329 return rc;
6330
6331 }
6332
6333 /*
6334 * This function comes to reflect the actual link state read DIRECTLY from the
6335 * HW
6336 */
6337 int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
6338 u8 is_serdes)
6339 {
6340 struct bnx2x *bp = params->bp;
6341 u16 gp_status = 0, phy_index = 0;
6342 u8 ext_phy_link_up = 0, serdes_phy_type;
6343 struct link_vars temp_vars;
6344 struct bnx2x_phy *int_phy = &params->phy[INT_PHY];
6345
6346 if (CHIP_IS_E3(bp)) {
6347 u16 link_up;
6348 if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)]
6349 > SPEED_10000) {
6350 /* Check 20G link */
6351 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6352 1, &link_up);
6353 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6354 1, &link_up);
6355 link_up &= (1<<2);
6356 } else {
6357 /* Check 10G link and below*/
6358 u8 lane = bnx2x_get_warpcore_lane(int_phy, params);
6359 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6360 MDIO_WC_REG_GP2_STATUS_GP_2_1,
6361 &gp_status);
6362 gp_status = ((gp_status >> 8) & 0xf) |
6363 ((gp_status >> 12) & 0xf);
6364 link_up = gp_status & (1 << lane);
6365 }
6366 if (!link_up)
6367 return -ESRCH;
6368 } else {
6369 CL22_RD_OVER_CL45(bp, int_phy,
6370 MDIO_REG_BANK_GP_STATUS,
6371 MDIO_GP_STATUS_TOP_AN_STATUS1,
6372 &gp_status);
6373 /* link is up only if both local phy and external phy are up */
6374 if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
6375 return -ESRCH;
6376 }
6377 /* In XGXS loopback mode, do not check external PHY */
6378 if (params->loopback_mode == LOOPBACK_XGXS)
6379 return 0;
6380
6381 switch (params->num_phys) {
6382 case 1:
6383 /* No external PHY */
6384 return 0;
6385 case 2:
6386 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
6387 &params->phy[EXT_PHY1],
6388 params, &temp_vars);
6389 break;
6390 case 3: /* Dual Media */
6391 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6392 phy_index++) {
6393 serdes_phy_type = ((params->phy[phy_index].media_type ==
6394 ETH_PHY_SFP_FIBER) ||
6395 (params->phy[phy_index].media_type ==
6396 ETH_PHY_XFP_FIBER) ||
6397 (params->phy[phy_index].media_type ==
6398 ETH_PHY_DA_TWINAX));
6399
6400 if (is_serdes != serdes_phy_type)
6401 continue;
6402 if (params->phy[phy_index].read_status) {
6403 ext_phy_link_up |=
6404 params->phy[phy_index].read_status(
6405 &params->phy[phy_index],
6406 params, &temp_vars);
6407 }
6408 }
6409 break;
6410 }
6411 if (ext_phy_link_up)
6412 return 0;
6413 return -ESRCH;
6414 }
6415
6416 static int bnx2x_link_initialize(struct link_params *params,
6417 struct link_vars *vars)
6418 {
6419 int rc = 0;
6420 u8 phy_index, non_ext_phy;
6421 struct bnx2x *bp = params->bp;
6422 /*
6423 * In case of external phy existence, the line speed would be the
6424 * line speed linked up by the external phy. In case it is direct
6425 * only, then the line_speed during initialization will be
6426 * equal to the req_line_speed
6427 */
6428 vars->line_speed = params->phy[INT_PHY].req_line_speed;
6429
6430 /*
6431 * Initialize the internal phy in case this is a direct board
6432 * (no external phys), or this board has external phy which requires
6433 * to first.
6434 */
6435 if (!USES_WARPCORE(bp))
6436 bnx2x_prepare_xgxs(&params->phy[INT_PHY], params, vars);
6437 /* init ext phy and enable link state int */
6438 non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
6439 (params->loopback_mode == LOOPBACK_XGXS));
6440
6441 if (non_ext_phy ||
6442 (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
6443 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
6444 struct bnx2x_phy *phy = &params->phy[INT_PHY];
6445 if (vars->line_speed == SPEED_AUTO_NEG &&
6446 (CHIP_IS_E1x(bp) ||
6447 CHIP_IS_E2(bp)))
6448 bnx2x_set_parallel_detection(phy, params);
6449 if (params->phy[INT_PHY].config_init)
6450 params->phy[INT_PHY].config_init(phy,
6451 params,
6452 vars);
6453 }
6454
6455 /* Init external phy*/
6456 if (non_ext_phy) {
6457 if (params->phy[INT_PHY].supported &
6458 SUPPORTED_FIBRE)
6459 vars->link_status |= LINK_STATUS_SERDES_LINK;
6460 } else {
6461 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6462 phy_index++) {
6463 /*
6464 * No need to initialize second phy in case of first
6465 * phy only selection. In case of second phy, we do
6466 * need to initialize the first phy, since they are
6467 * connected.
6468 */
6469 if (params->phy[phy_index].supported &
6470 SUPPORTED_FIBRE)
6471 vars->link_status |= LINK_STATUS_SERDES_LINK;
6472
6473 if (phy_index == EXT_PHY2 &&
6474 (bnx2x_phy_selection(params) ==
6475 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
6476 DP(NETIF_MSG_LINK,
6477 "Not initializing second phy\n");
6478 continue;
6479 }
6480 params->phy[phy_index].config_init(
6481 &params->phy[phy_index],
6482 params, vars);
6483 }
6484 }
6485 /* Reset the interrupt indication after phy was initialized */
6486 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
6487 params->port*4,
6488 (NIG_STATUS_XGXS0_LINK10G |
6489 NIG_STATUS_XGXS0_LINK_STATUS |
6490 NIG_STATUS_SERDES0_LINK_STATUS |
6491 NIG_MASK_MI_INT));
6492 bnx2x_update_mng(params, vars->link_status);
6493 return rc;
6494 }
6495
6496 static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
6497 struct link_params *params)
6498 {
6499 /* reset the SerDes/XGXS */
6500 REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6501 (0x1ff << (params->port*16)));
6502 }
6503
6504 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
6505 struct link_params *params)
6506 {
6507 struct bnx2x *bp = params->bp;
6508 u8 gpio_port;
6509 /* HW reset */
6510 if (CHIP_IS_E2(bp))
6511 gpio_port = BP_PATH(bp);
6512 else
6513 gpio_port = params->port;
6514 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6515 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6516 gpio_port);
6517 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6518 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6519 gpio_port);
6520 DP(NETIF_MSG_LINK, "reset external PHY\n");
6521 }
6522
6523 static int bnx2x_update_link_down(struct link_params *params,
6524 struct link_vars *vars)
6525 {
6526 struct bnx2x *bp = params->bp;
6527 u8 port = params->port;
6528
6529 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
6530 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
6531 vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
6532 /* indicate no mac active */
6533 vars->mac_type = MAC_TYPE_NONE;
6534
6535 /* update shared memory */
6536 vars->link_status &= ~(LINK_STATUS_SPEED_AND_DUPLEX_MASK |
6537 LINK_STATUS_LINK_UP |
6538 LINK_STATUS_PHYSICAL_LINK_FLAG |
6539 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE |
6540 LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK |
6541 LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK |
6542 LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK |
6543 LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE |
6544 LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE);
6545 vars->line_speed = 0;
6546 bnx2x_update_mng(params, vars->link_status);
6547
6548 /* activate nig drain */
6549 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6550
6551 /* disable emac */
6552 if (!CHIP_IS_E3(bp))
6553 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6554
6555 msleep(10);
6556 /* reset BigMac/Xmac */
6557 if (CHIP_IS_E1x(bp) ||
6558 CHIP_IS_E2(bp)) {
6559 bnx2x_bmac_rx_disable(bp, params->port);
6560 REG_WR(bp, GRCBASE_MISC +
6561 MISC_REGISTERS_RESET_REG_2_CLEAR,
6562 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
6563 }
6564 if (CHIP_IS_E3(bp)) {
6565 bnx2x_xmac_disable(params);
6566 bnx2x_umac_disable(params);
6567 }
6568
6569 return 0;
6570 }
6571
6572 static int bnx2x_update_link_up(struct link_params *params,
6573 struct link_vars *vars,
6574 u8 link_10g)
6575 {
6576 struct bnx2x *bp = params->bp;
6577 u8 port = params->port;
6578 int rc = 0;
6579
6580 vars->link_status |= (LINK_STATUS_LINK_UP |
6581 LINK_STATUS_PHYSICAL_LINK_FLAG);
6582 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
6583
6584 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
6585 vars->link_status |=
6586 LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
6587
6588 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
6589 vars->link_status |=
6590 LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
6591 if (USES_WARPCORE(bp)) {
6592 if (link_10g) {
6593 if (bnx2x_xmac_enable(params, vars, 0) ==
6594 -ESRCH) {
6595 DP(NETIF_MSG_LINK, "Found errors on XMAC\n");
6596 vars->link_up = 0;
6597 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6598 vars->link_status &= ~LINK_STATUS_LINK_UP;
6599 }
6600 } else
6601 bnx2x_umac_enable(params, vars, 0);
6602 bnx2x_set_led(params, vars,
6603 LED_MODE_OPER, vars->line_speed);
6604 }
6605 if ((CHIP_IS_E1x(bp) ||
6606 CHIP_IS_E2(bp))) {
6607 if (link_10g) {
6608 if (bnx2x_bmac_enable(params, vars, 0) ==
6609 -ESRCH) {
6610 DP(NETIF_MSG_LINK, "Found errors on BMAC\n");
6611 vars->link_up = 0;
6612 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6613 vars->link_status &= ~LINK_STATUS_LINK_UP;
6614 }
6615
6616 bnx2x_set_led(params, vars,
6617 LED_MODE_OPER, SPEED_10000);
6618 } else {
6619 rc = bnx2x_emac_program(params, vars);
6620 bnx2x_emac_enable(params, vars, 0);
6621
6622 /* AN complete? */
6623 if ((vars->link_status &
6624 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
6625 && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
6626 SINGLE_MEDIA_DIRECT(params))
6627 bnx2x_set_gmii_tx_driver(params);
6628 }
6629 }
6630
6631 /* PBF - link up */
6632 if (CHIP_IS_E1x(bp))
6633 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
6634 vars->line_speed);
6635
6636 /* disable drain */
6637 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
6638
6639 /* update shared memory */
6640 bnx2x_update_mng(params, vars->link_status);
6641 msleep(20);
6642 return rc;
6643 }
6644 /*
6645 * The bnx2x_link_update function should be called upon link
6646 * interrupt.
6647 * Link is considered up as follows:
6648 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6649 * to be up
6650 * - SINGLE_MEDIA - The link between the 577xx and the external
6651 * phy (XGXS) need to up as well as the external link of the
6652 * phy (PHY_EXT1)
6653 * - DUAL_MEDIA - The link between the 577xx and the first
6654 * external phy needs to be up, and at least one of the 2
6655 * external phy link must be up.
6656 */
6657 int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6658 {
6659 struct bnx2x *bp = params->bp;
6660 struct link_vars phy_vars[MAX_PHYS];
6661 u8 port = params->port;
6662 u8 link_10g_plus, phy_index;
6663 u8 ext_phy_link_up = 0, cur_link_up;
6664 int rc = 0;
6665 u8 is_mi_int = 0;
6666 u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
6667 u8 active_external_phy = INT_PHY;
6668 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
6669 for (phy_index = INT_PHY; phy_index < params->num_phys;
6670 phy_index++) {
6671 phy_vars[phy_index].flow_ctrl = 0;
6672 phy_vars[phy_index].link_status = 0;
6673 phy_vars[phy_index].line_speed = 0;
6674 phy_vars[phy_index].duplex = DUPLEX_FULL;
6675 phy_vars[phy_index].phy_link_up = 0;
6676 phy_vars[phy_index].link_up = 0;
6677 phy_vars[phy_index].fault_detected = 0;
6678 }
6679
6680 if (USES_WARPCORE(bp))
6681 bnx2x_set_aer_mmd(params, &params->phy[INT_PHY]);
6682
6683 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
6684 port, (vars->phy_flags & PHY_XGXS_FLAG),
6685 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6686
6687 is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
6688 port*0x18) > 0);
6689 DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
6690 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6691 is_mi_int,
6692 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
6693
6694 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6695 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6696 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6697
6698 /* disable emac */
6699 if (!CHIP_IS_E3(bp))
6700 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6701
6702 /*
6703 * Step 1:
6704 * Check external link change only for external phys, and apply
6705 * priority selection between them in case the link on both phys
6706 * is up. Note that instead of the common vars, a temporary
6707 * vars argument is used since each phy may have different link/
6708 * speed/duplex result
6709 */
6710 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6711 phy_index++) {
6712 struct bnx2x_phy *phy = &params->phy[phy_index];
6713 if (!phy->read_status)
6714 continue;
6715 /* Read link status and params of this ext phy */
6716 cur_link_up = phy->read_status(phy, params,
6717 &phy_vars[phy_index]);
6718 if (cur_link_up) {
6719 DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
6720 phy_index);
6721 } else {
6722 DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
6723 phy_index);
6724 continue;
6725 }
6726
6727 if (!ext_phy_link_up) {
6728 ext_phy_link_up = 1;
6729 active_external_phy = phy_index;
6730 } else {
6731 switch (bnx2x_phy_selection(params)) {
6732 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6733 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6734 /*
6735 * In this option, the first PHY makes sure to pass the
6736 * traffic through itself only.
6737 * Its not clear how to reset the link on the second phy
6738 */
6739 active_external_phy = EXT_PHY1;
6740 break;
6741 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6742 /*
6743 * In this option, the first PHY makes sure to pass the
6744 * traffic through the second PHY.
6745 */
6746 active_external_phy = EXT_PHY2;
6747 break;
6748 default:
6749 /*
6750 * Link indication on both PHYs with the following cases
6751 * is invalid:
6752 * - FIRST_PHY means that second phy wasn't initialized,
6753 * hence its link is expected to be down
6754 * - SECOND_PHY means that first phy should not be able
6755 * to link up by itself (using configuration)
6756 * - DEFAULT should be overriden during initialiazation
6757 */
6758 DP(NETIF_MSG_LINK, "Invalid link indication"
6759 "mpc=0x%x. DISABLING LINK !!!\n",
6760 params->multi_phy_config);
6761 ext_phy_link_up = 0;
6762 break;
6763 }
6764 }
6765 }
6766 prev_line_speed = vars->line_speed;
6767 /*
6768 * Step 2:
6769 * Read the status of the internal phy. In case of
6770 * DIRECT_SINGLE_MEDIA board, this link is the external link,
6771 * otherwise this is the link between the 577xx and the first
6772 * external phy
6773 */
6774 if (params->phy[INT_PHY].read_status)
6775 params->phy[INT_PHY].read_status(
6776 &params->phy[INT_PHY],
6777 params, vars);
6778 /*
6779 * The INT_PHY flow control reside in the vars. This include the
6780 * case where the speed or flow control are not set to AUTO.
6781 * Otherwise, the active external phy flow control result is set
6782 * to the vars. The ext_phy_line_speed is needed to check if the
6783 * speed is different between the internal phy and external phy.
6784 * This case may be result of intermediate link speed change.
6785 */
6786 if (active_external_phy > INT_PHY) {
6787 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
6788 /*
6789 * Link speed is taken from the XGXS. AN and FC result from
6790 * the external phy.
6791 */
6792 vars->link_status |= phy_vars[active_external_phy].link_status;
6793
6794 /*
6795 * if active_external_phy is first PHY and link is up - disable
6796 * disable TX on second external PHY
6797 */
6798 if (active_external_phy == EXT_PHY1) {
6799 if (params->phy[EXT_PHY2].phy_specific_func) {
6800 DP(NETIF_MSG_LINK,
6801 "Disabling TX on EXT_PHY2\n");
6802 params->phy[EXT_PHY2].phy_specific_func(
6803 &params->phy[EXT_PHY2],
6804 params, DISABLE_TX);
6805 }
6806 }
6807
6808 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
6809 vars->duplex = phy_vars[active_external_phy].duplex;
6810 if (params->phy[active_external_phy].supported &
6811 SUPPORTED_FIBRE)
6812 vars->link_status |= LINK_STATUS_SERDES_LINK;
6813 else
6814 vars->link_status &= ~LINK_STATUS_SERDES_LINK;
6815 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
6816 active_external_phy);
6817 }
6818
6819 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6820 phy_index++) {
6821 if (params->phy[phy_index].flags &
6822 FLAGS_REARM_LATCH_SIGNAL) {
6823 bnx2x_rearm_latch_signal(bp, port,
6824 phy_index ==
6825 active_external_phy);
6826 break;
6827 }
6828 }
6829 DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
6830 " ext_phy_line_speed = %d\n", vars->flow_ctrl,
6831 vars->link_status, ext_phy_line_speed);
6832 /*
6833 * Upon link speed change set the NIG into drain mode. Comes to
6834 * deals with possible FIFO glitch due to clk change when speed
6835 * is decreased without link down indicator
6836 */
6837
6838 if (vars->phy_link_up) {
6839 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
6840 (ext_phy_line_speed != vars->line_speed)) {
6841 DP(NETIF_MSG_LINK, "Internal link speed %d is"
6842 " different than the external"
6843 " link speed %d\n", vars->line_speed,
6844 ext_phy_line_speed);
6845 vars->phy_link_up = 0;
6846 } else if (prev_line_speed != vars->line_speed) {
6847 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
6848 0);
6849 msleep(1);
6850 }
6851 }
6852
6853 /* anything 10 and over uses the bmac */
6854 link_10g_plus = (vars->line_speed >= SPEED_10000);
6855
6856 bnx2x_link_int_ack(params, vars, link_10g_plus);
6857
6858 /*
6859 * In case external phy link is up, and internal link is down
6860 * (not initialized yet probably after link initialization, it
6861 * needs to be initialized.
6862 * Note that after link down-up as result of cable plug, the xgxs
6863 * link would probably become up again without the need
6864 * initialize it
6865 */
6866 if (!(SINGLE_MEDIA_DIRECT(params))) {
6867 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
6868 " init_preceding = %d\n", ext_phy_link_up,
6869 vars->phy_link_up,
6870 params->phy[EXT_PHY1].flags &
6871 FLAGS_INIT_XGXS_FIRST);
6872 if (!(params->phy[EXT_PHY1].flags &
6873 FLAGS_INIT_XGXS_FIRST)
6874 && ext_phy_link_up && !vars->phy_link_up) {
6875 vars->line_speed = ext_phy_line_speed;
6876 if (vars->line_speed < SPEED_1000)
6877 vars->phy_flags |= PHY_SGMII_FLAG;
6878 else
6879 vars->phy_flags &= ~PHY_SGMII_FLAG;
6880
6881 if (params->phy[INT_PHY].config_init)
6882 params->phy[INT_PHY].config_init(
6883 &params->phy[INT_PHY], params,
6884 vars);
6885 }
6886 }
6887 /*
6888 * Link is up only if both local phy and external phy (in case of
6889 * non-direct board) are up and no fault detected on active PHY.
6890 */
6891 vars->link_up = (vars->phy_link_up &&
6892 (ext_phy_link_up ||
6893 SINGLE_MEDIA_DIRECT(params)) &&
6894 (phy_vars[active_external_phy].fault_detected == 0));
6895
6896 /* Update the PFC configuration in case it was changed */
6897 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
6898 vars->link_status |= LINK_STATUS_PFC_ENABLED;
6899 else
6900 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
6901
6902 if (vars->link_up)
6903 rc = bnx2x_update_link_up(params, vars, link_10g_plus);
6904 else
6905 rc = bnx2x_update_link_down(params, vars);
6906
6907 return rc;
6908 }
6909
6910 /*****************************************************************************/
6911 /* External Phy section */
6912 /*****************************************************************************/
6913 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
6914 {
6915 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6916 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
6917 msleep(1);
6918 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6919 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
6920 }
6921
6922 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
6923 u32 spirom_ver, u32 ver_addr)
6924 {
6925 DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
6926 (u16)(spirom_ver>>16), (u16)spirom_ver, port);
6927
6928 if (ver_addr)
6929 REG_WR(bp, ver_addr, spirom_ver);
6930 }
6931
6932 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
6933 struct bnx2x_phy *phy,
6934 u8 port)
6935 {
6936 u16 fw_ver1, fw_ver2;
6937
6938 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6939 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6940 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6941 MDIO_PMA_REG_ROM_VER2, &fw_ver2);
6942 bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
6943 phy->ver_addr);
6944 }
6945
6946 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
6947 struct bnx2x_phy *phy,
6948 struct link_vars *vars)
6949 {
6950 u16 val;
6951 bnx2x_cl45_read(bp, phy,
6952 MDIO_AN_DEVAD,
6953 MDIO_AN_REG_STATUS, &val);
6954 bnx2x_cl45_read(bp, phy,
6955 MDIO_AN_DEVAD,
6956 MDIO_AN_REG_STATUS, &val);
6957 if (val & (1<<5))
6958 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
6959 if ((val & (1<<0)) == 0)
6960 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
6961 }
6962
6963 /******************************************************************/
6964 /* common BCM8073/BCM8727 PHY SECTION */
6965 /******************************************************************/
6966 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
6967 struct link_params *params,
6968 struct link_vars *vars)
6969 {
6970 struct bnx2x *bp = params->bp;
6971 if (phy->req_line_speed == SPEED_10 ||
6972 phy->req_line_speed == SPEED_100) {
6973 vars->flow_ctrl = phy->req_flow_ctrl;
6974 return;
6975 }
6976
6977 if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
6978 (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
6979 u16 pause_result;
6980 u16 ld_pause; /* local */
6981 u16 lp_pause; /* link partner */
6982 bnx2x_cl45_read(bp, phy,
6983 MDIO_AN_DEVAD,
6984 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
6985
6986 bnx2x_cl45_read(bp, phy,
6987 MDIO_AN_DEVAD,
6988 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
6989 pause_result = (ld_pause &
6990 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
6991 pause_result |= (lp_pause &
6992 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
6993
6994 bnx2x_pause_resolve(vars, pause_result);
6995 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
6996 pause_result);
6997 }
6998 }
6999 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
7000 struct bnx2x_phy *phy,
7001 u8 port)
7002 {
7003 u32 count = 0;
7004 u16 fw_ver1, fw_msgout;
7005 int rc = 0;
7006
7007 /* Boot port from external ROM */
7008 /* EDC grst */
7009 bnx2x_cl45_write(bp, phy,
7010 MDIO_PMA_DEVAD,
7011 MDIO_PMA_REG_GEN_CTRL,
7012 0x0001);
7013
7014 /* ucode reboot and rst */
7015 bnx2x_cl45_write(bp, phy,
7016 MDIO_PMA_DEVAD,
7017 MDIO_PMA_REG_GEN_CTRL,
7018 0x008c);
7019
7020 bnx2x_cl45_write(bp, phy,
7021 MDIO_PMA_DEVAD,
7022 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
7023
7024 /* Reset internal microprocessor */
7025 bnx2x_cl45_write(bp, phy,
7026 MDIO_PMA_DEVAD,
7027 MDIO_PMA_REG_GEN_CTRL,
7028 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
7029
7030 /* Release srst bit */
7031 bnx2x_cl45_write(bp, phy,
7032 MDIO_PMA_DEVAD,
7033 MDIO_PMA_REG_GEN_CTRL,
7034 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
7035
7036 /* Delay 100ms per the PHY specifications */
7037 msleep(100);
7038
7039 /* 8073 sometimes taking longer to download */
7040 do {
7041 count++;
7042 if (count > 300) {
7043 DP(NETIF_MSG_LINK,
7044 "bnx2x_8073_8727_external_rom_boot port %x:"
7045 "Download failed. fw version = 0x%x\n",
7046 port, fw_ver1);
7047 rc = -EINVAL;
7048 break;
7049 }
7050
7051 bnx2x_cl45_read(bp, phy,
7052 MDIO_PMA_DEVAD,
7053 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7054 bnx2x_cl45_read(bp, phy,
7055 MDIO_PMA_DEVAD,
7056 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
7057
7058 msleep(1);
7059 } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
7060 ((fw_msgout & 0xff) != 0x03 && (phy->type ==
7061 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
7062
7063 /* Clear ser_boot_ctl bit */
7064 bnx2x_cl45_write(bp, phy,
7065 MDIO_PMA_DEVAD,
7066 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
7067 bnx2x_save_bcm_spirom_ver(bp, phy, port);
7068
7069 DP(NETIF_MSG_LINK,
7070 "bnx2x_8073_8727_external_rom_boot port %x:"
7071 "Download complete. fw version = 0x%x\n",
7072 port, fw_ver1);
7073
7074 return rc;
7075 }
7076
7077 /******************************************************************/
7078 /* BCM8073 PHY SECTION */
7079 /******************************************************************/
7080 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
7081 {
7082 /* This is only required for 8073A1, version 102 only */
7083 u16 val;
7084
7085 /* Read 8073 HW revision*/
7086 bnx2x_cl45_read(bp, phy,
7087 MDIO_PMA_DEVAD,
7088 MDIO_PMA_REG_8073_CHIP_REV, &val);
7089
7090 if (val != 1) {
7091 /* No need to workaround in 8073 A1 */
7092 return 0;
7093 }
7094
7095 bnx2x_cl45_read(bp, phy,
7096 MDIO_PMA_DEVAD,
7097 MDIO_PMA_REG_ROM_VER2, &val);
7098
7099 /* SNR should be applied only for version 0x102 */
7100 if (val != 0x102)
7101 return 0;
7102
7103 return 1;
7104 }
7105
7106 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
7107 {
7108 u16 val, cnt, cnt1 ;
7109
7110 bnx2x_cl45_read(bp, phy,
7111 MDIO_PMA_DEVAD,
7112 MDIO_PMA_REG_8073_CHIP_REV, &val);
7113
7114 if (val > 0) {
7115 /* No need to workaround in 8073 A1 */
7116 return 0;
7117 }
7118 /* XAUI workaround in 8073 A0: */
7119
7120 /*
7121 * After loading the boot ROM and restarting Autoneg, poll
7122 * Dev1, Reg $C820:
7123 */
7124
7125 for (cnt = 0; cnt < 1000; cnt++) {
7126 bnx2x_cl45_read(bp, phy,
7127 MDIO_PMA_DEVAD,
7128 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7129 &val);
7130 /*
7131 * If bit [14] = 0 or bit [13] = 0, continue on with
7132 * system initialization (XAUI work-around not required, as
7133 * these bits indicate 2.5G or 1G link up).
7134 */
7135 if (!(val & (1<<14)) || !(val & (1<<13))) {
7136 DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
7137 return 0;
7138 } else if (!(val & (1<<15))) {
7139 DP(NETIF_MSG_LINK, "bit 15 went off\n");
7140 /*
7141 * If bit 15 is 0, then poll Dev1, Reg $C841 until it's
7142 * MSB (bit15) goes to 1 (indicating that the XAUI
7143 * workaround has completed), then continue on with
7144 * system initialization.
7145 */
7146 for (cnt1 = 0; cnt1 < 1000; cnt1++) {
7147 bnx2x_cl45_read(bp, phy,
7148 MDIO_PMA_DEVAD,
7149 MDIO_PMA_REG_8073_XAUI_WA, &val);
7150 if (val & (1<<15)) {
7151 DP(NETIF_MSG_LINK,
7152 "XAUI workaround has completed\n");
7153 return 0;
7154 }
7155 msleep(3);
7156 }
7157 break;
7158 }
7159 msleep(3);
7160 }
7161 DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
7162 return -EINVAL;
7163 }
7164
7165 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
7166 {
7167 /* Force KR or KX */
7168 bnx2x_cl45_write(bp, phy,
7169 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
7170 bnx2x_cl45_write(bp, phy,
7171 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
7172 bnx2x_cl45_write(bp, phy,
7173 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
7174 bnx2x_cl45_write(bp, phy,
7175 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
7176 }
7177
7178 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
7179 struct bnx2x_phy *phy,
7180 struct link_vars *vars)
7181 {
7182 u16 cl37_val;
7183 struct bnx2x *bp = params->bp;
7184 bnx2x_cl45_read(bp, phy,
7185 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
7186
7187 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7188 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
7189 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
7190 if ((vars->ieee_fc &
7191 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
7192 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
7193 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
7194 }
7195 if ((vars->ieee_fc &
7196 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
7197 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
7198 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
7199 }
7200 if ((vars->ieee_fc &
7201 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
7202 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
7203 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7204 }
7205 DP(NETIF_MSG_LINK,
7206 "Ext phy AN advertize cl37 0x%x\n", cl37_val);
7207
7208 bnx2x_cl45_write(bp, phy,
7209 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
7210 msleep(500);
7211 }
7212
7213 static int bnx2x_8073_config_init(struct bnx2x_phy *phy,
7214 struct link_params *params,
7215 struct link_vars *vars)
7216 {
7217 struct bnx2x *bp = params->bp;
7218 u16 val = 0, tmp1;
7219 u8 gpio_port;
7220 DP(NETIF_MSG_LINK, "Init 8073\n");
7221
7222 if (CHIP_IS_E2(bp))
7223 gpio_port = BP_PATH(bp);
7224 else
7225 gpio_port = params->port;
7226 /* Restore normal power mode*/
7227 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7228 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7229
7230 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
7231 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7232
7233 /* enable LASI */
7234 bnx2x_cl45_write(bp, phy,
7235 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2));
7236 bnx2x_cl45_write(bp, phy,
7237 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004);
7238
7239 bnx2x_8073_set_pause_cl37(params, phy, vars);
7240
7241 bnx2x_cl45_read(bp, phy,
7242 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
7243
7244 bnx2x_cl45_read(bp, phy,
7245 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
7246
7247 DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
7248
7249 /* Swap polarity if required - Must be done only in non-1G mode */
7250 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7251 /* Configure the 8073 to swap _P and _N of the KR lines */
7252 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
7253 /* 10G Rx/Tx and 1G Tx signal polarity swap */
7254 bnx2x_cl45_read(bp, phy,
7255 MDIO_PMA_DEVAD,
7256 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
7257 bnx2x_cl45_write(bp, phy,
7258 MDIO_PMA_DEVAD,
7259 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
7260 (val | (3<<9)));
7261 }
7262
7263
7264 /* Enable CL37 BAM */
7265 if (REG_RD(bp, params->shmem_base +
7266 offsetof(struct shmem_region, dev_info.
7267 port_hw_config[params->port].default_cfg)) &
7268 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
7269
7270 bnx2x_cl45_read(bp, phy,
7271 MDIO_AN_DEVAD,
7272 MDIO_AN_REG_8073_BAM, &val);
7273 bnx2x_cl45_write(bp, phy,
7274 MDIO_AN_DEVAD,
7275 MDIO_AN_REG_8073_BAM, val | 1);
7276 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
7277 }
7278 if (params->loopback_mode == LOOPBACK_EXT) {
7279 bnx2x_807x_force_10G(bp, phy);
7280 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
7281 return 0;
7282 } else {
7283 bnx2x_cl45_write(bp, phy,
7284 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
7285 }
7286 if (phy->req_line_speed != SPEED_AUTO_NEG) {
7287 if (phy->req_line_speed == SPEED_10000) {
7288 val = (1<<7);
7289 } else if (phy->req_line_speed == SPEED_2500) {
7290 val = (1<<5);
7291 /*
7292 * Note that 2.5G works only when used with 1G
7293 * advertisement
7294 */
7295 } else
7296 val = (1<<5);
7297 } else {
7298 val = 0;
7299 if (phy->speed_cap_mask &
7300 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
7301 val |= (1<<7);
7302
7303 /* Note that 2.5G works only when used with 1G advertisement */
7304 if (phy->speed_cap_mask &
7305 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
7306 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
7307 val |= (1<<5);
7308 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
7309 }
7310
7311 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
7312 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
7313
7314 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
7315 (phy->req_line_speed == SPEED_AUTO_NEG)) ||
7316 (phy->req_line_speed == SPEED_2500)) {
7317 u16 phy_ver;
7318 /* Allow 2.5G for A1 and above */
7319 bnx2x_cl45_read(bp, phy,
7320 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
7321 &phy_ver);
7322 DP(NETIF_MSG_LINK, "Add 2.5G\n");
7323 if (phy_ver > 0)
7324 tmp1 |= 1;
7325 else
7326 tmp1 &= 0xfffe;
7327 } else {
7328 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
7329 tmp1 &= 0xfffe;
7330 }
7331
7332 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
7333 /* Add support for CL37 (passive mode) II */
7334
7335 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
7336 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
7337 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
7338 0x20 : 0x40)));
7339
7340 /* Add support for CL37 (passive mode) III */
7341 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
7342
7343 /*
7344 * The SNR will improve about 2db by changing BW and FEE main
7345 * tap. Rest commands are executed after link is up
7346 * Change FFE main cursor to 5 in EDC register
7347 */
7348 if (bnx2x_8073_is_snr_needed(bp, phy))
7349 bnx2x_cl45_write(bp, phy,
7350 MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
7351 0xFB0C);
7352
7353 /* Enable FEC (Forware Error Correction) Request in the AN */
7354 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
7355 tmp1 |= (1<<15);
7356 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
7357
7358 bnx2x_ext_phy_set_pause(params, phy, vars);
7359
7360 /* Restart autoneg */
7361 msleep(500);
7362 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
7363 DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
7364 ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
7365 return 0;
7366 }
7367
7368 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
7369 struct link_params *params,
7370 struct link_vars *vars)
7371 {
7372 struct bnx2x *bp = params->bp;
7373 u8 link_up = 0;
7374 u16 val1, val2;
7375 u16 link_status = 0;
7376 u16 an1000_status = 0;
7377
7378 bnx2x_cl45_read(bp, phy,
7379 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
7380
7381 DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
7382
7383 /* clear the interrupt LASI status register */
7384 bnx2x_cl45_read(bp, phy,
7385 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7386 bnx2x_cl45_read(bp, phy,
7387 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
7388 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
7389 /* Clear MSG-OUT */
7390 bnx2x_cl45_read(bp, phy,
7391 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
7392
7393 /* Check the LASI */
7394 bnx2x_cl45_read(bp, phy,
7395 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
7396
7397 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
7398
7399 /* Check the link status */
7400 bnx2x_cl45_read(bp, phy,
7401 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7402 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
7403
7404 bnx2x_cl45_read(bp, phy,
7405 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7406 bnx2x_cl45_read(bp, phy,
7407 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7408 link_up = ((val1 & 4) == 4);
7409 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
7410
7411 if (link_up &&
7412 ((phy->req_line_speed != SPEED_10000))) {
7413 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
7414 return 0;
7415 }
7416 bnx2x_cl45_read(bp, phy,
7417 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7418 bnx2x_cl45_read(bp, phy,
7419 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7420
7421 /* Check the link status on 1.1.2 */
7422 bnx2x_cl45_read(bp, phy,
7423 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7424 bnx2x_cl45_read(bp, phy,
7425 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7426 DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
7427 "an_link_status=0x%x\n", val2, val1, an1000_status);
7428
7429 link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
7430 if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
7431 /*
7432 * The SNR will improve about 2dbby changing the BW and FEE main
7433 * tap. The 1st write to change FFE main tap is set before
7434 * restart AN. Change PLL Bandwidth in EDC register
7435 */
7436 bnx2x_cl45_write(bp, phy,
7437 MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
7438 0x26BC);
7439
7440 /* Change CDR Bandwidth in EDC register */
7441 bnx2x_cl45_write(bp, phy,
7442 MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
7443 0x0333);
7444 }
7445 bnx2x_cl45_read(bp, phy,
7446 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7447 &link_status);
7448
7449 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7450 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
7451 link_up = 1;
7452 vars->line_speed = SPEED_10000;
7453 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
7454 params->port);
7455 } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
7456 link_up = 1;
7457 vars->line_speed = SPEED_2500;
7458 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
7459 params->port);
7460 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
7461 link_up = 1;
7462 vars->line_speed = SPEED_1000;
7463 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
7464 params->port);
7465 } else {
7466 link_up = 0;
7467 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
7468 params->port);
7469 }
7470
7471 if (link_up) {
7472 /* Swap polarity if required */
7473 if (params->lane_config &
7474 PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7475 /* Configure the 8073 to swap P and N of the KR lines */
7476 bnx2x_cl45_read(bp, phy,
7477 MDIO_XS_DEVAD,
7478 MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
7479 /*
7480 * Set bit 3 to invert Rx in 1G mode and clear this bit
7481 * when it`s in 10G mode.
7482 */
7483 if (vars->line_speed == SPEED_1000) {
7484 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
7485 "the 8073\n");
7486 val1 |= (1<<3);
7487 } else
7488 val1 &= ~(1<<3);
7489
7490 bnx2x_cl45_write(bp, phy,
7491 MDIO_XS_DEVAD,
7492 MDIO_XS_REG_8073_RX_CTRL_PCIE,
7493 val1);
7494 }
7495 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
7496 bnx2x_8073_resolve_fc(phy, params, vars);
7497 vars->duplex = DUPLEX_FULL;
7498 }
7499
7500 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
7501 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
7502 MDIO_AN_REG_LP_AUTO_NEG2, &val1);
7503
7504 if (val1 & (1<<5))
7505 vars->link_status |=
7506 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
7507 if (val1 & (1<<7))
7508 vars->link_status |=
7509 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
7510 }
7511
7512 return link_up;
7513 }
7514
7515 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
7516 struct link_params *params)
7517 {
7518 struct bnx2x *bp = params->bp;
7519 u8 gpio_port;
7520 if (CHIP_IS_E2(bp))
7521 gpio_port = BP_PATH(bp);
7522 else
7523 gpio_port = params->port;
7524 DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
7525 gpio_port);
7526 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7527 MISC_REGISTERS_GPIO_OUTPUT_LOW,
7528 gpio_port);
7529 }
7530
7531 /******************************************************************/
7532 /* BCM8705 PHY SECTION */
7533 /******************************************************************/
7534 static int bnx2x_8705_config_init(struct bnx2x_phy *phy,
7535 struct link_params *params,
7536 struct link_vars *vars)
7537 {
7538 struct bnx2x *bp = params->bp;
7539 DP(NETIF_MSG_LINK, "init 8705\n");
7540 /* Restore normal power mode*/
7541 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7542 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
7543 /* HW reset */
7544 bnx2x_ext_phy_hw_reset(bp, params->port);
7545 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
7546 bnx2x_wait_reset_complete(bp, phy, params);
7547
7548 bnx2x_cl45_write(bp, phy,
7549 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
7550 bnx2x_cl45_write(bp, phy,
7551 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
7552 bnx2x_cl45_write(bp, phy,
7553 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
7554 bnx2x_cl45_write(bp, phy,
7555 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
7556 /* BCM8705 doesn't have microcode, hence the 0 */
7557 bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
7558 return 0;
7559 }
7560
7561 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
7562 struct link_params *params,
7563 struct link_vars *vars)
7564 {
7565 u8 link_up = 0;
7566 u16 val1, rx_sd;
7567 struct bnx2x *bp = params->bp;
7568 DP(NETIF_MSG_LINK, "read status 8705\n");
7569 bnx2x_cl45_read(bp, phy,
7570 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7571 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7572
7573 bnx2x_cl45_read(bp, phy,
7574 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7575 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7576
7577 bnx2x_cl45_read(bp, phy,
7578 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
7579
7580 bnx2x_cl45_read(bp, phy,
7581 MDIO_PMA_DEVAD, 0xc809, &val1);
7582 bnx2x_cl45_read(bp, phy,
7583 MDIO_PMA_DEVAD, 0xc809, &val1);
7584
7585 DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
7586 link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
7587 if (link_up) {
7588 vars->line_speed = SPEED_10000;
7589 bnx2x_ext_phy_resolve_fc(phy, params, vars);
7590 }
7591 return link_up;
7592 }
7593
7594 /******************************************************************/
7595 /* SFP+ module Section */
7596 /******************************************************************/
7597 static void bnx2x_set_disable_pmd_transmit(struct link_params *params,
7598 struct bnx2x_phy *phy,
7599 u8 pmd_dis)
7600 {
7601 struct bnx2x *bp = params->bp;
7602 /*
7603 * Disable transmitter only for bootcodes which can enable it afterwards
7604 * (for D3 link)
7605 */
7606 if (pmd_dis) {
7607 if (params->feature_config_flags &
7608 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED)
7609 DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n");
7610 else {
7611 DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n");
7612 return;
7613 }
7614 } else
7615 DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n");
7616 bnx2x_cl45_write(bp, phy,
7617 MDIO_PMA_DEVAD,
7618 MDIO_PMA_REG_TX_DISABLE, pmd_dis);
7619 }
7620
7621 static u8 bnx2x_get_gpio_port(struct link_params *params)
7622 {
7623 u8 gpio_port;
7624 u32 swap_val, swap_override;
7625 struct bnx2x *bp = params->bp;
7626 if (CHIP_IS_E2(bp))
7627 gpio_port = BP_PATH(bp);
7628 else
7629 gpio_port = params->port;
7630 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7631 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7632 return gpio_port ^ (swap_val && swap_override);
7633 }
7634
7635 static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params,
7636 struct bnx2x_phy *phy,
7637 u8 tx_en)
7638 {
7639 u16 val;
7640 u8 port = params->port;
7641 struct bnx2x *bp = params->bp;
7642 u32 tx_en_mode;
7643
7644 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
7645 tx_en_mode = REG_RD(bp, params->shmem_base +
7646 offsetof(struct shmem_region,
7647 dev_info.port_hw_config[port].sfp_ctrl)) &
7648 PORT_HW_CFG_TX_LASER_MASK;
7649 DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "
7650 "mode = %x\n", tx_en, port, tx_en_mode);
7651 switch (tx_en_mode) {
7652 case PORT_HW_CFG_TX_LASER_MDIO:
7653
7654 bnx2x_cl45_read(bp, phy,
7655 MDIO_PMA_DEVAD,
7656 MDIO_PMA_REG_PHY_IDENTIFIER,
7657 &val);
7658
7659 if (tx_en)
7660 val &= ~(1<<15);
7661 else
7662 val |= (1<<15);
7663
7664 bnx2x_cl45_write(bp, phy,
7665 MDIO_PMA_DEVAD,
7666 MDIO_PMA_REG_PHY_IDENTIFIER,
7667 val);
7668 break;
7669 case PORT_HW_CFG_TX_LASER_GPIO0:
7670 case PORT_HW_CFG_TX_LASER_GPIO1:
7671 case PORT_HW_CFG_TX_LASER_GPIO2:
7672 case PORT_HW_CFG_TX_LASER_GPIO3:
7673 {
7674 u16 gpio_pin;
7675 u8 gpio_port, gpio_mode;
7676 if (tx_en)
7677 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
7678 else
7679 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
7680
7681 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
7682 gpio_port = bnx2x_get_gpio_port(params);
7683 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
7684 break;
7685 }
7686 default:
7687 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
7688 break;
7689 }
7690 }
7691
7692 static void bnx2x_sfp_set_transmitter(struct link_params *params,
7693 struct bnx2x_phy *phy,
7694 u8 tx_en)
7695 {
7696 struct bnx2x *bp = params->bp;
7697 DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en);
7698 if (CHIP_IS_E3(bp))
7699 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en);
7700 else
7701 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en);
7702 }
7703
7704 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7705 struct link_params *params,
7706 u16 addr, u8 byte_cnt, u8 *o_buf)
7707 {
7708 struct bnx2x *bp = params->bp;
7709 u16 val = 0;
7710 u16 i;
7711 if (byte_cnt > 16) {
7712 DP(NETIF_MSG_LINK,
7713 "Reading from eeprom is limited to 0xf\n");
7714 return -EINVAL;
7715 }
7716 /* Set the read command byte count */
7717 bnx2x_cl45_write(bp, phy,
7718 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7719 (byte_cnt | 0xa000));
7720
7721 /* Set the read command address */
7722 bnx2x_cl45_write(bp, phy,
7723 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7724 addr);
7725
7726 /* Activate read command */
7727 bnx2x_cl45_write(bp, phy,
7728 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7729 0x2c0f);
7730
7731 /* Wait up to 500us for command complete status */
7732 for (i = 0; i < 100; i++) {
7733 bnx2x_cl45_read(bp, phy,
7734 MDIO_PMA_DEVAD,
7735 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7736 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7737 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7738 break;
7739 udelay(5);
7740 }
7741
7742 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7743 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7744 DP(NETIF_MSG_LINK,
7745 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7746 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7747 return -EINVAL;
7748 }
7749
7750 /* Read the buffer */
7751 for (i = 0; i < byte_cnt; i++) {
7752 bnx2x_cl45_read(bp, phy,
7753 MDIO_PMA_DEVAD,
7754 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
7755 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
7756 }
7757
7758 for (i = 0; i < 100; i++) {
7759 bnx2x_cl45_read(bp, phy,
7760 MDIO_PMA_DEVAD,
7761 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7762 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7763 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7764 return 0;
7765 msleep(1);
7766 }
7767 return -EINVAL;
7768 }
7769
7770 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7771 struct link_params *params,
7772 u16 addr, u8 byte_cnt,
7773 u8 *o_buf)
7774 {
7775 int rc = 0;
7776 u8 i, j = 0, cnt = 0;
7777 u32 data_array[4];
7778 u16 addr32;
7779 struct bnx2x *bp = params->bp;
7780 /*DP(NETIF_MSG_LINK, "bnx2x_direct_read_sfp_module_eeprom:"
7781 " addr %d, cnt %d\n",
7782 addr, byte_cnt);*/
7783 if (byte_cnt > 16) {
7784 DP(NETIF_MSG_LINK,
7785 "Reading from eeprom is limited to 16 bytes\n");
7786 return -EINVAL;
7787 }
7788
7789 /* 4 byte aligned address */
7790 addr32 = addr & (~0x3);
7791 do {
7792 rc = bnx2x_bsc_read(params, phy, 0xa0, addr32, 0, byte_cnt,
7793 data_array);
7794 } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT));
7795
7796 if (rc == 0) {
7797 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
7798 o_buf[j] = *((u8 *)data_array + i);
7799 j++;
7800 }
7801 }
7802
7803 return rc;
7804 }
7805
7806 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7807 struct link_params *params,
7808 u16 addr, u8 byte_cnt, u8 *o_buf)
7809 {
7810 struct bnx2x *bp = params->bp;
7811 u16 val, i;
7812
7813 if (byte_cnt > 16) {
7814 DP(NETIF_MSG_LINK,
7815 "Reading from eeprom is limited to 0xf\n");
7816 return -EINVAL;
7817 }
7818
7819 /* Need to read from 1.8000 to clear it */
7820 bnx2x_cl45_read(bp, phy,
7821 MDIO_PMA_DEVAD,
7822 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7823 &val);
7824
7825 /* Set the read command byte count */
7826 bnx2x_cl45_write(bp, phy,
7827 MDIO_PMA_DEVAD,
7828 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7829 ((byte_cnt < 2) ? 2 : byte_cnt));
7830
7831 /* Set the read command address */
7832 bnx2x_cl45_write(bp, phy,
7833 MDIO_PMA_DEVAD,
7834 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7835 addr);
7836 /* Set the destination address */
7837 bnx2x_cl45_write(bp, phy,
7838 MDIO_PMA_DEVAD,
7839 0x8004,
7840 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
7841
7842 /* Activate read command */
7843 bnx2x_cl45_write(bp, phy,
7844 MDIO_PMA_DEVAD,
7845 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7846 0x8002);
7847 /*
7848 * Wait appropriate time for two-wire command to finish before
7849 * polling the status register
7850 */
7851 msleep(1);
7852
7853 /* Wait up to 500us for command complete status */
7854 for (i = 0; i < 100; i++) {
7855 bnx2x_cl45_read(bp, phy,
7856 MDIO_PMA_DEVAD,
7857 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7858 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7859 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7860 break;
7861 udelay(5);
7862 }
7863
7864 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7865 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7866 DP(NETIF_MSG_LINK,
7867 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7868 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7869 return -EFAULT;
7870 }
7871
7872 /* Read the buffer */
7873 for (i = 0; i < byte_cnt; i++) {
7874 bnx2x_cl45_read(bp, phy,
7875 MDIO_PMA_DEVAD,
7876 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
7877 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
7878 }
7879
7880 for (i = 0; i < 100; i++) {
7881 bnx2x_cl45_read(bp, phy,
7882 MDIO_PMA_DEVAD,
7883 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7884 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7885 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7886 return 0;
7887 msleep(1);
7888 }
7889
7890 return -EINVAL;
7891 }
7892
7893 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7894 struct link_params *params, u16 addr,
7895 u8 byte_cnt, u8 *o_buf)
7896 {
7897 int rc = -EINVAL;
7898 switch (phy->type) {
7899 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
7900 rc = bnx2x_8726_read_sfp_module_eeprom(phy, params, addr,
7901 byte_cnt, o_buf);
7902 break;
7903 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
7904 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
7905 rc = bnx2x_8727_read_sfp_module_eeprom(phy, params, addr,
7906 byte_cnt, o_buf);
7907 break;
7908 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7909 rc = bnx2x_warpcore_read_sfp_module_eeprom(phy, params, addr,
7910 byte_cnt, o_buf);
7911 break;
7912 }
7913 return rc;
7914 }
7915
7916 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy,
7917 struct link_params *params,
7918 u16 *edc_mode)
7919 {
7920 struct bnx2x *bp = params->bp;
7921 u32 sync_offset = 0, phy_idx, media_types;
7922 u8 val, check_limiting_mode = 0;
7923 *edc_mode = EDC_MODE_LIMITING;
7924
7925 phy->media_type = ETH_PHY_UNSPECIFIED;
7926 /* First check for copper cable */
7927 if (bnx2x_read_sfp_module_eeprom(phy,
7928 params,
7929 SFP_EEPROM_CON_TYPE_ADDR,
7930 1,
7931 &val) != 0) {
7932 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
7933 return -EINVAL;
7934 }
7935
7936 switch (val) {
7937 case SFP_EEPROM_CON_TYPE_VAL_COPPER:
7938 {
7939 u8 copper_module_type;
7940 phy->media_type = ETH_PHY_DA_TWINAX;
7941 /*
7942 * Check if its active cable (includes SFP+ module)
7943 * of passive cable
7944 */
7945 if (bnx2x_read_sfp_module_eeprom(phy,
7946 params,
7947 SFP_EEPROM_FC_TX_TECH_ADDR,
7948 1,
7949 &copper_module_type) != 0) {
7950 DP(NETIF_MSG_LINK,
7951 "Failed to read copper-cable-type"
7952 " from SFP+ EEPROM\n");
7953 return -EINVAL;
7954 }
7955
7956 if (copper_module_type &
7957 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
7958 DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
7959 check_limiting_mode = 1;
7960 } else if (copper_module_type &
7961 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
7962 DP(NETIF_MSG_LINK,
7963 "Passive Copper cable detected\n");
7964 *edc_mode =
7965 EDC_MODE_PASSIVE_DAC;
7966 } else {
7967 DP(NETIF_MSG_LINK,
7968 "Unknown copper-cable-type 0x%x !!!\n",
7969 copper_module_type);
7970 return -EINVAL;
7971 }
7972 break;
7973 }
7974 case SFP_EEPROM_CON_TYPE_VAL_LC:
7975 phy->media_type = ETH_PHY_SFP_FIBER;
7976 DP(NETIF_MSG_LINK, "Optic module detected\n");
7977 check_limiting_mode = 1;
7978 break;
7979 default:
7980 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
7981 val);
7982 return -EINVAL;
7983 }
7984 sync_offset = params->shmem_base +
7985 offsetof(struct shmem_region,
7986 dev_info.port_hw_config[params->port].media_type);
7987 media_types = REG_RD(bp, sync_offset);
7988 /* Update media type for non-PMF sync */
7989 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
7990 if (&(params->phy[phy_idx]) == phy) {
7991 media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
7992 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
7993 media_types |= ((phy->media_type &
7994 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
7995 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
7996 break;
7997 }
7998 }
7999 REG_WR(bp, sync_offset, media_types);
8000 if (check_limiting_mode) {
8001 u8 options[SFP_EEPROM_OPTIONS_SIZE];
8002 if (bnx2x_read_sfp_module_eeprom(phy,
8003 params,
8004 SFP_EEPROM_OPTIONS_ADDR,
8005 SFP_EEPROM_OPTIONS_SIZE,
8006 options) != 0) {
8007 DP(NETIF_MSG_LINK,
8008 "Failed to read Option field from module EEPROM\n");
8009 return -EINVAL;
8010 }
8011 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
8012 *edc_mode = EDC_MODE_LINEAR;
8013 else
8014 *edc_mode = EDC_MODE_LIMITING;
8015 }
8016 DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
8017 return 0;
8018 }
8019 /*
8020 * This function read the relevant field from the module (SFP+), and verify it
8021 * is compliant with this board
8022 */
8023 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
8024 struct link_params *params)
8025 {
8026 struct bnx2x *bp = params->bp;
8027 u32 val, cmd;
8028 u32 fw_resp, fw_cmd_param;
8029 char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
8030 char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
8031 phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
8032 val = REG_RD(bp, params->shmem_base +
8033 offsetof(struct shmem_region, dev_info.
8034 port_feature_config[params->port].config));
8035 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8036 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
8037 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
8038 return 0;
8039 }
8040
8041 if (params->feature_config_flags &
8042 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
8043 /* Use specific phy request */
8044 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
8045 } else if (params->feature_config_flags &
8046 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
8047 /* Use first phy request only in case of non-dual media*/
8048 if (DUAL_MEDIA(params)) {
8049 DP(NETIF_MSG_LINK,
8050 "FW does not support OPT MDL verification\n");
8051 return -EINVAL;
8052 }
8053 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
8054 } else {
8055 /* No support in OPT MDL detection */
8056 DP(NETIF_MSG_LINK,
8057 "FW does not support OPT MDL verification\n");
8058 return -EINVAL;
8059 }
8060
8061 fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
8062 fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
8063 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
8064 DP(NETIF_MSG_LINK, "Approved module\n");
8065 return 0;
8066 }
8067
8068 /* format the warning message */
8069 if (bnx2x_read_sfp_module_eeprom(phy,
8070 params,
8071 SFP_EEPROM_VENDOR_NAME_ADDR,
8072 SFP_EEPROM_VENDOR_NAME_SIZE,
8073 (u8 *)vendor_name))
8074 vendor_name[0] = '\0';
8075 else
8076 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
8077 if (bnx2x_read_sfp_module_eeprom(phy,
8078 params,
8079 SFP_EEPROM_PART_NO_ADDR,
8080 SFP_EEPROM_PART_NO_SIZE,
8081 (u8 *)vendor_pn))
8082 vendor_pn[0] = '\0';
8083 else
8084 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
8085
8086 netdev_err(bp->dev, "Warning: Unqualified SFP+ module detected,"
8087 " Port %d from %s part number %s\n",
8088 params->port, vendor_name, vendor_pn);
8089 phy->flags |= FLAGS_SFP_NOT_APPROVED;
8090 return -EINVAL;
8091 }
8092
8093 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
8094 struct link_params *params)
8095
8096 {
8097 u8 val;
8098 struct bnx2x *bp = params->bp;
8099 u16 timeout;
8100 /*
8101 * Initialization time after hot-plug may take up to 300ms for
8102 * some phys type ( e.g. JDSU )
8103 */
8104
8105 for (timeout = 0; timeout < 60; timeout++) {
8106 if (bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val)
8107 == 0) {
8108 DP(NETIF_MSG_LINK,
8109 "SFP+ module initialization took %d ms\n",
8110 timeout * 5);
8111 return 0;
8112 }
8113 msleep(5);
8114 }
8115 return -EINVAL;
8116 }
8117
8118 static void bnx2x_8727_power_module(struct bnx2x *bp,
8119 struct bnx2x_phy *phy,
8120 u8 is_power_up) {
8121 /* Make sure GPIOs are not using for LED mode */
8122 u16 val;
8123 /*
8124 * In the GPIO register, bit 4 is use to determine if the GPIOs are
8125 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
8126 * output
8127 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
8128 * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
8129 * where the 1st bit is the over-current(only input), and 2nd bit is
8130 * for power( only output )
8131 *
8132 * In case of NOC feature is disabled and power is up, set GPIO control
8133 * as input to enable listening of over-current indication
8134 */
8135 if (phy->flags & FLAGS_NOC)
8136 return;
8137 if (is_power_up)
8138 val = (1<<4);
8139 else
8140 /*
8141 * Set GPIO control to OUTPUT, and set the power bit
8142 * to according to the is_power_up
8143 */
8144 val = (1<<1);
8145
8146 bnx2x_cl45_write(bp, phy,
8147 MDIO_PMA_DEVAD,
8148 MDIO_PMA_REG_8727_GPIO_CTRL,
8149 val);
8150 }
8151
8152 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
8153 struct bnx2x_phy *phy,
8154 u16 edc_mode)
8155 {
8156 u16 cur_limiting_mode;
8157
8158 bnx2x_cl45_read(bp, phy,
8159 MDIO_PMA_DEVAD,
8160 MDIO_PMA_REG_ROM_VER2,
8161 &cur_limiting_mode);
8162 DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
8163 cur_limiting_mode);
8164
8165 if (edc_mode == EDC_MODE_LIMITING) {
8166 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
8167 bnx2x_cl45_write(bp, phy,
8168 MDIO_PMA_DEVAD,
8169 MDIO_PMA_REG_ROM_VER2,
8170 EDC_MODE_LIMITING);
8171 } else { /* LRM mode ( default )*/
8172
8173 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
8174
8175 /*
8176 * Changing to LRM mode takes quite few seconds. So do it only
8177 * if current mode is limiting (default is LRM)
8178 */
8179 if (cur_limiting_mode != EDC_MODE_LIMITING)
8180 return 0;
8181
8182 bnx2x_cl45_write(bp, phy,
8183 MDIO_PMA_DEVAD,
8184 MDIO_PMA_REG_LRM_MODE,
8185 0);
8186 bnx2x_cl45_write(bp, phy,
8187 MDIO_PMA_DEVAD,
8188 MDIO_PMA_REG_ROM_VER2,
8189 0x128);
8190 bnx2x_cl45_write(bp, phy,
8191 MDIO_PMA_DEVAD,
8192 MDIO_PMA_REG_MISC_CTRL0,
8193 0x4008);
8194 bnx2x_cl45_write(bp, phy,
8195 MDIO_PMA_DEVAD,
8196 MDIO_PMA_REG_LRM_MODE,
8197 0xaaaa);
8198 }
8199 return 0;
8200 }
8201
8202 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
8203 struct bnx2x_phy *phy,
8204 u16 edc_mode)
8205 {
8206 u16 phy_identifier;
8207 u16 rom_ver2_val;
8208 bnx2x_cl45_read(bp, phy,
8209 MDIO_PMA_DEVAD,
8210 MDIO_PMA_REG_PHY_IDENTIFIER,
8211 &phy_identifier);
8212
8213 bnx2x_cl45_write(bp, phy,
8214 MDIO_PMA_DEVAD,
8215 MDIO_PMA_REG_PHY_IDENTIFIER,
8216 (phy_identifier & ~(1<<9)));
8217
8218 bnx2x_cl45_read(bp, phy,
8219 MDIO_PMA_DEVAD,
8220 MDIO_PMA_REG_ROM_VER2,
8221 &rom_ver2_val);
8222 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
8223 bnx2x_cl45_write(bp, phy,
8224 MDIO_PMA_DEVAD,
8225 MDIO_PMA_REG_ROM_VER2,
8226 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
8227
8228 bnx2x_cl45_write(bp, phy,
8229 MDIO_PMA_DEVAD,
8230 MDIO_PMA_REG_PHY_IDENTIFIER,
8231 (phy_identifier | (1<<9)));
8232
8233 return 0;
8234 }
8235
8236 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
8237 struct link_params *params,
8238 u32 action)
8239 {
8240 struct bnx2x *bp = params->bp;
8241
8242 switch (action) {
8243 case DISABLE_TX:
8244 bnx2x_sfp_set_transmitter(params, phy, 0);
8245 break;
8246 case ENABLE_TX:
8247 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
8248 bnx2x_sfp_set_transmitter(params, phy, 1);
8249 break;
8250 default:
8251 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
8252 action);
8253 return;
8254 }
8255 }
8256
8257 static void bnx2x_set_e1e2_module_fault_led(struct link_params *params,
8258 u8 gpio_mode)
8259 {
8260 struct bnx2x *bp = params->bp;
8261
8262 u32 fault_led_gpio = REG_RD(bp, params->shmem_base +
8263 offsetof(struct shmem_region,
8264 dev_info.port_hw_config[params->port].sfp_ctrl)) &
8265 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
8266 switch (fault_led_gpio) {
8267 case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
8268 return;
8269 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
8270 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
8271 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
8272 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
8273 {
8274 u8 gpio_port = bnx2x_get_gpio_port(params);
8275 u16 gpio_pin = fault_led_gpio -
8276 PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
8277 DP(NETIF_MSG_LINK, "Set fault module-detected led "
8278 "pin %x port %x mode %x\n",
8279 gpio_pin, gpio_port, gpio_mode);
8280 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
8281 }
8282 break;
8283 default:
8284 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n",
8285 fault_led_gpio);
8286 }
8287 }
8288
8289 static void bnx2x_set_e3_module_fault_led(struct link_params *params,
8290 u8 gpio_mode)
8291 {
8292 u32 pin_cfg;
8293 u8 port = params->port;
8294 struct bnx2x *bp = params->bp;
8295 pin_cfg = (REG_RD(bp, params->shmem_base +
8296 offsetof(struct shmem_region,
8297 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
8298 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
8299 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
8300 DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n",
8301 gpio_mode, pin_cfg);
8302 bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode);
8303 }
8304
8305 static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
8306 u8 gpio_mode)
8307 {
8308 struct bnx2x *bp = params->bp;
8309 DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode);
8310 if (CHIP_IS_E3(bp)) {
8311 /*
8312 * Low ==> if SFP+ module is supported otherwise
8313 * High ==> if SFP+ module is not on the approved vendor list
8314 */
8315 bnx2x_set_e3_module_fault_led(params, gpio_mode);
8316 } else
8317 bnx2x_set_e1e2_module_fault_led(params, gpio_mode);
8318 }
8319
8320 static void bnx2x_warpcore_power_module(struct link_params *params,
8321 struct bnx2x_phy *phy,
8322 u8 power)
8323 {
8324 u32 pin_cfg;
8325 struct bnx2x *bp = params->bp;
8326
8327 pin_cfg = (REG_RD(bp, params->shmem_base +
8328 offsetof(struct shmem_region,
8329 dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
8330 PORT_HW_CFG_E3_PWR_DIS_MASK) >>
8331 PORT_HW_CFG_E3_PWR_DIS_SHIFT;
8332
8333 if (pin_cfg == PIN_CFG_NA)
8334 return;
8335 DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n",
8336 power, pin_cfg);
8337 /*
8338 * Low ==> corresponding SFP+ module is powered
8339 * high ==> the SFP+ module is powered down
8340 */
8341 bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1);
8342 }
8343
8344 static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy,
8345 struct link_params *params)
8346 {
8347 struct bnx2x *bp = params->bp;
8348 bnx2x_warpcore_power_module(params, phy, 0);
8349 /* Put Warpcore in low power mode */
8350 REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e);
8351
8352 /* Put LCPLL in low power mode */
8353 REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1);
8354 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0);
8355 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0);
8356 }
8357
8358 static void bnx2x_power_sfp_module(struct link_params *params,
8359 struct bnx2x_phy *phy,
8360 u8 power)
8361 {
8362 struct bnx2x *bp = params->bp;
8363 DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power);
8364
8365 switch (phy->type) {
8366 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8367 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8368 bnx2x_8727_power_module(params->bp, phy, power);
8369 break;
8370 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8371 bnx2x_warpcore_power_module(params, phy, power);
8372 break;
8373 default:
8374 break;
8375 }
8376 }
8377 static void bnx2x_warpcore_set_limiting_mode(struct link_params *params,
8378 struct bnx2x_phy *phy,
8379 u16 edc_mode)
8380 {
8381 u16 val = 0;
8382 u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8383 struct bnx2x *bp = params->bp;
8384
8385 u8 lane = bnx2x_get_warpcore_lane(phy, params);
8386 /* This is a global register which controls all lanes */
8387 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8388 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8389 val &= ~(0xf << (lane << 2));
8390
8391 switch (edc_mode) {
8392 case EDC_MODE_LINEAR:
8393 case EDC_MODE_LIMITING:
8394 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8395 break;
8396 case EDC_MODE_PASSIVE_DAC:
8397 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
8398 break;
8399 default:
8400 break;
8401 }
8402
8403 val |= (mode << (lane << 2));
8404 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
8405 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
8406 /* A must read */
8407 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8408 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8409
8410 /* Restart microcode to re-read the new mode */
8411 bnx2x_warpcore_reset_lane(bp, phy, 1);
8412 bnx2x_warpcore_reset_lane(bp, phy, 0);
8413
8414 }
8415
8416 static void bnx2x_set_limiting_mode(struct link_params *params,
8417 struct bnx2x_phy *phy,
8418 u16 edc_mode)
8419 {
8420 switch (phy->type) {
8421 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8422 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode);
8423 break;
8424 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8425 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8426 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode);
8427 break;
8428 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8429 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode);
8430 break;
8431 }
8432 }
8433
8434 int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
8435 struct link_params *params)
8436 {
8437 struct bnx2x *bp = params->bp;
8438 u16 edc_mode;
8439 int rc = 0;
8440
8441 u32 val = REG_RD(bp, params->shmem_base +
8442 offsetof(struct shmem_region, dev_info.
8443 port_feature_config[params->port].config));
8444
8445 DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
8446 params->port);
8447 /* Power up module */
8448 bnx2x_power_sfp_module(params, phy, 1);
8449 if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
8450 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
8451 return -EINVAL;
8452 } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
8453 /* check SFP+ module compatibility */
8454 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
8455 rc = -EINVAL;
8456 /* Turn on fault module-detected led */
8457 bnx2x_set_sfp_module_fault_led(params,
8458 MISC_REGISTERS_GPIO_HIGH);
8459
8460 /* Check if need to power down the SFP+ module */
8461 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8462 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
8463 DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
8464 bnx2x_power_sfp_module(params, phy, 0);
8465 return rc;
8466 }
8467 } else {
8468 /* Turn off fault module-detected led */
8469 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
8470 }
8471
8472 /*
8473 * Check and set limiting mode / LRM mode on 8726. On 8727 it
8474 * is done automatically
8475 */
8476 bnx2x_set_limiting_mode(params, phy, edc_mode);
8477
8478 /*
8479 * Enable transmit for this module if the module is approved, or
8480 * if unapproved modules should also enable the Tx laser
8481 */
8482 if (rc == 0 ||
8483 (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
8484 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
8485 bnx2x_sfp_set_transmitter(params, phy, 1);
8486 else
8487 bnx2x_sfp_set_transmitter(params, phy, 0);
8488
8489 return rc;
8490 }
8491
8492 void bnx2x_handle_module_detect_int(struct link_params *params)
8493 {
8494 struct bnx2x *bp = params->bp;
8495 struct bnx2x_phy *phy;
8496 u32 gpio_val;
8497 u8 gpio_num, gpio_port;
8498 if (CHIP_IS_E3(bp))
8499 phy = &params->phy[INT_PHY];
8500 else
8501 phy = &params->phy[EXT_PHY1];
8502
8503 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base,
8504 params->port, &gpio_num, &gpio_port) ==
8505 -EINVAL) {
8506 DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n");
8507 return;
8508 }
8509
8510 /* Set valid module led off */
8511 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
8512
8513 /* Get current gpio val reflecting module plugged in / out*/
8514 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
8515
8516 /* Call the handling function in case module is detected */
8517 if (gpio_val == 0) {
8518 bnx2x_power_sfp_module(params, phy, 1);
8519 bnx2x_set_gpio_int(bp, gpio_num,
8520 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
8521 gpio_port);
8522 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
8523 bnx2x_sfp_module_detection(phy, params);
8524 else
8525 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
8526 } else {
8527 u32 val = REG_RD(bp, params->shmem_base +
8528 offsetof(struct shmem_region, dev_info.
8529 port_feature_config[params->port].
8530 config));
8531 bnx2x_set_gpio_int(bp, gpio_num,
8532 MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
8533 gpio_port);
8534 /*
8535 * Module was plugged out.
8536 * Disable transmit for this module
8537 */
8538 phy->media_type = ETH_PHY_NOT_PRESENT;
8539 if (((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8540 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) ||
8541 CHIP_IS_E3(bp))
8542 bnx2x_sfp_set_transmitter(params, phy, 0);
8543 }
8544 }
8545
8546 /******************************************************************/
8547 /* Used by 8706 and 8727 */
8548 /******************************************************************/
8549 static void bnx2x_sfp_mask_fault(struct bnx2x *bp,
8550 struct bnx2x_phy *phy,
8551 u16 alarm_status_offset,
8552 u16 alarm_ctrl_offset)
8553 {
8554 u16 alarm_status, val;
8555 bnx2x_cl45_read(bp, phy,
8556 MDIO_PMA_DEVAD, alarm_status_offset,
8557 &alarm_status);
8558 bnx2x_cl45_read(bp, phy,
8559 MDIO_PMA_DEVAD, alarm_status_offset,
8560 &alarm_status);
8561 /* Mask or enable the fault event. */
8562 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
8563 if (alarm_status & (1<<0))
8564 val &= ~(1<<0);
8565 else
8566 val |= (1<<0);
8567 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
8568 }
8569 /******************************************************************/
8570 /* common BCM8706/BCM8726 PHY SECTION */
8571 /******************************************************************/
8572 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
8573 struct link_params *params,
8574 struct link_vars *vars)
8575 {
8576 u8 link_up = 0;
8577 u16 val1, val2, rx_sd, pcs_status;
8578 struct bnx2x *bp = params->bp;
8579 DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
8580 /* Clear RX Alarm*/
8581 bnx2x_cl45_read(bp, phy,
8582 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
8583
8584 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
8585 MDIO_PMA_LASI_TXCTRL);
8586
8587 /* clear LASI indication*/
8588 bnx2x_cl45_read(bp, phy,
8589 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8590 bnx2x_cl45_read(bp, phy,
8591 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
8592 DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
8593
8594 bnx2x_cl45_read(bp, phy,
8595 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
8596 bnx2x_cl45_read(bp, phy,
8597 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
8598 bnx2x_cl45_read(bp, phy,
8599 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8600 bnx2x_cl45_read(bp, phy,
8601 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8602
8603 DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
8604 " link_status 0x%x\n", rx_sd, pcs_status, val2);
8605 /*
8606 * link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8607 * are set, or if the autoneg bit 1 is set
8608 */
8609 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
8610 if (link_up) {
8611 if (val2 & (1<<1))
8612 vars->line_speed = SPEED_1000;
8613 else
8614 vars->line_speed = SPEED_10000;
8615 bnx2x_ext_phy_resolve_fc(phy, params, vars);
8616 vars->duplex = DUPLEX_FULL;
8617 }
8618
8619 /* Capture 10G link fault. Read twice to clear stale value. */
8620 if (vars->line_speed == SPEED_10000) {
8621 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8622 MDIO_PMA_LASI_TXSTAT, &val1);
8623 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8624 MDIO_PMA_LASI_TXSTAT, &val1);
8625 if (val1 & (1<<0))
8626 vars->fault_detected = 1;
8627 }
8628
8629 return link_up;
8630 }
8631
8632 /******************************************************************/
8633 /* BCM8706 PHY SECTION */
8634 /******************************************************************/
8635 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
8636 struct link_params *params,
8637 struct link_vars *vars)
8638 {
8639 u32 tx_en_mode;
8640 u16 cnt, val, tmp1;
8641 struct bnx2x *bp = params->bp;
8642
8643 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
8644 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8645 /* HW reset */
8646 bnx2x_ext_phy_hw_reset(bp, params->port);
8647 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8648 bnx2x_wait_reset_complete(bp, phy, params);
8649
8650 /* Wait until fw is loaded */
8651 for (cnt = 0; cnt < 100; cnt++) {
8652 bnx2x_cl45_read(bp, phy,
8653 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
8654 if (val)
8655 break;
8656 msleep(10);
8657 }
8658 DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
8659 if ((params->feature_config_flags &
8660 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8661 u8 i;
8662 u16 reg;
8663 for (i = 0; i < 4; i++) {
8664 reg = MDIO_XS_8706_REG_BANK_RX0 +
8665 i*(MDIO_XS_8706_REG_BANK_RX1 -
8666 MDIO_XS_8706_REG_BANK_RX0);
8667 bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
8668 /* Clear first 3 bits of the control */
8669 val &= ~0x7;
8670 /* Set control bits according to configuration */
8671 val |= (phy->rx_preemphasis[i] & 0x7);
8672 DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
8673 " reg 0x%x <-- val 0x%x\n", reg, val);
8674 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
8675 }
8676 }
8677 /* Force speed */
8678 if (phy->req_line_speed == SPEED_10000) {
8679 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
8680
8681 bnx2x_cl45_write(bp, phy,
8682 MDIO_PMA_DEVAD,
8683 MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
8684 bnx2x_cl45_write(bp, phy,
8685 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8686 0);
8687 /* Arm LASI for link and Tx fault. */
8688 bnx2x_cl45_write(bp, phy,
8689 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
8690 } else {
8691 /* Force 1Gbps using autoneg with 1G advertisement */
8692
8693 /* Allow CL37 through CL73 */
8694 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
8695 bnx2x_cl45_write(bp, phy,
8696 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8697
8698 /* Enable Full-Duplex advertisement on CL37 */
8699 bnx2x_cl45_write(bp, phy,
8700 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
8701 /* Enable CL37 AN */
8702 bnx2x_cl45_write(bp, phy,
8703 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8704 /* 1G support */
8705 bnx2x_cl45_write(bp, phy,
8706 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
8707
8708 /* Enable clause 73 AN */
8709 bnx2x_cl45_write(bp, phy,
8710 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8711 bnx2x_cl45_write(bp, phy,
8712 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8713 0x0400);
8714 bnx2x_cl45_write(bp, phy,
8715 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
8716 0x0004);
8717 }
8718 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8719
8720 /*
8721 * If TX Laser is controlled by GPIO_0, do not let PHY go into low
8722 * power mode, if TX Laser is disabled
8723 */
8724
8725 tx_en_mode = REG_RD(bp, params->shmem_base +
8726 offsetof(struct shmem_region,
8727 dev_info.port_hw_config[params->port].sfp_ctrl))
8728 & PORT_HW_CFG_TX_LASER_MASK;
8729
8730 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8731 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
8732 bnx2x_cl45_read(bp, phy,
8733 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
8734 tmp1 |= 0x1;
8735 bnx2x_cl45_write(bp, phy,
8736 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
8737 }
8738
8739 return 0;
8740 }
8741
8742 static int bnx2x_8706_read_status(struct bnx2x_phy *phy,
8743 struct link_params *params,
8744 struct link_vars *vars)
8745 {
8746 return bnx2x_8706_8726_read_status(phy, params, vars);
8747 }
8748
8749 /******************************************************************/
8750 /* BCM8726 PHY SECTION */
8751 /******************************************************************/
8752 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
8753 struct link_params *params)
8754 {
8755 struct bnx2x *bp = params->bp;
8756 DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
8757 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
8758 }
8759
8760 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
8761 struct link_params *params)
8762 {
8763 struct bnx2x *bp = params->bp;
8764 /* Need to wait 100ms after reset */
8765 msleep(100);
8766
8767 /* Micro controller re-boot */
8768 bnx2x_cl45_write(bp, phy,
8769 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
8770
8771 /* Set soft reset */
8772 bnx2x_cl45_write(bp, phy,
8773 MDIO_PMA_DEVAD,
8774 MDIO_PMA_REG_GEN_CTRL,
8775 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
8776
8777 bnx2x_cl45_write(bp, phy,
8778 MDIO_PMA_DEVAD,
8779 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
8780
8781 bnx2x_cl45_write(bp, phy,
8782 MDIO_PMA_DEVAD,
8783 MDIO_PMA_REG_GEN_CTRL,
8784 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
8785
8786 /* wait for 150ms for microcode load */
8787 msleep(150);
8788
8789 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
8790 bnx2x_cl45_write(bp, phy,
8791 MDIO_PMA_DEVAD,
8792 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
8793
8794 msleep(200);
8795 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8796 }
8797
8798 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
8799 struct link_params *params,
8800 struct link_vars *vars)
8801 {
8802 struct bnx2x *bp = params->bp;
8803 u16 val1;
8804 u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
8805 if (link_up) {
8806 bnx2x_cl45_read(bp, phy,
8807 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
8808 &val1);
8809 if (val1 & (1<<15)) {
8810 DP(NETIF_MSG_LINK, "Tx is disabled\n");
8811 link_up = 0;
8812 vars->line_speed = 0;
8813 }
8814 }
8815 return link_up;
8816 }
8817
8818
8819 static int bnx2x_8726_config_init(struct bnx2x_phy *phy,
8820 struct link_params *params,
8821 struct link_vars *vars)
8822 {
8823 struct bnx2x *bp = params->bp;
8824 DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
8825
8826 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
8827 bnx2x_wait_reset_complete(bp, phy, params);
8828
8829 bnx2x_8726_external_rom_boot(phy, params);
8830
8831 /*
8832 * Need to call module detected on initialization since the module
8833 * detection triggered by actual module insertion might occur before
8834 * driver is loaded, and when driver is loaded, it reset all
8835 * registers, including the transmitter
8836 */
8837 bnx2x_sfp_module_detection(phy, params);
8838
8839 if (phy->req_line_speed == SPEED_1000) {
8840 DP(NETIF_MSG_LINK, "Setting 1G force\n");
8841 bnx2x_cl45_write(bp, phy,
8842 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
8843 bnx2x_cl45_write(bp, phy,
8844 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
8845 bnx2x_cl45_write(bp, phy,
8846 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
8847 bnx2x_cl45_write(bp, phy,
8848 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8849 0x400);
8850 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
8851 (phy->speed_cap_mask &
8852 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
8853 ((phy->speed_cap_mask &
8854 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8855 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8856 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
8857 /* Set Flow control */
8858 bnx2x_ext_phy_set_pause(params, phy, vars);
8859 bnx2x_cl45_write(bp, phy,
8860 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
8861 bnx2x_cl45_write(bp, phy,
8862 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8863 bnx2x_cl45_write(bp, phy,
8864 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
8865 bnx2x_cl45_write(bp, phy,
8866 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8867 bnx2x_cl45_write(bp, phy,
8868 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8869 /*
8870 * Enable RX-ALARM control to receive interrupt for 1G speed
8871 * change
8872 */
8873 bnx2x_cl45_write(bp, phy,
8874 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
8875 bnx2x_cl45_write(bp, phy,
8876 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8877 0x400);
8878
8879 } else { /* Default 10G. Set only LASI control */
8880 bnx2x_cl45_write(bp, phy,
8881 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
8882 }
8883
8884 /* Set TX PreEmphasis if needed */
8885 if ((params->feature_config_flags &
8886 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8887 DP(NETIF_MSG_LINK,
8888 "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
8889 phy->tx_preemphasis[0],
8890 phy->tx_preemphasis[1]);
8891 bnx2x_cl45_write(bp, phy,
8892 MDIO_PMA_DEVAD,
8893 MDIO_PMA_REG_8726_TX_CTRL1,
8894 phy->tx_preemphasis[0]);
8895
8896 bnx2x_cl45_write(bp, phy,
8897 MDIO_PMA_DEVAD,
8898 MDIO_PMA_REG_8726_TX_CTRL2,
8899 phy->tx_preemphasis[1]);
8900 }
8901
8902 return 0;
8903
8904 }
8905
8906 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
8907 struct link_params *params)
8908 {
8909 struct bnx2x *bp = params->bp;
8910 DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
8911 /* Set serial boot control for external load */
8912 bnx2x_cl45_write(bp, phy,
8913 MDIO_PMA_DEVAD,
8914 MDIO_PMA_REG_GEN_CTRL, 0x0001);
8915 }
8916
8917 /******************************************************************/
8918 /* BCM8727 PHY SECTION */
8919 /******************************************************************/
8920
8921 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
8922 struct link_params *params, u8 mode)
8923 {
8924 struct bnx2x *bp = params->bp;
8925 u16 led_mode_bitmask = 0;
8926 u16 gpio_pins_bitmask = 0;
8927 u16 val;
8928 /* Only NOC flavor requires to set the LED specifically */
8929 if (!(phy->flags & FLAGS_NOC))
8930 return;
8931 switch (mode) {
8932 case LED_MODE_FRONT_PANEL_OFF:
8933 case LED_MODE_OFF:
8934 led_mode_bitmask = 0;
8935 gpio_pins_bitmask = 0x03;
8936 break;
8937 case LED_MODE_ON:
8938 led_mode_bitmask = 0;
8939 gpio_pins_bitmask = 0x02;
8940 break;
8941 case LED_MODE_OPER:
8942 led_mode_bitmask = 0x60;
8943 gpio_pins_bitmask = 0x11;
8944 break;
8945 }
8946 bnx2x_cl45_read(bp, phy,
8947 MDIO_PMA_DEVAD,
8948 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8949 &val);
8950 val &= 0xff8f;
8951 val |= led_mode_bitmask;
8952 bnx2x_cl45_write(bp, phy,
8953 MDIO_PMA_DEVAD,
8954 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8955 val);
8956 bnx2x_cl45_read(bp, phy,
8957 MDIO_PMA_DEVAD,
8958 MDIO_PMA_REG_8727_GPIO_CTRL,
8959 &val);
8960 val &= 0xffe0;
8961 val |= gpio_pins_bitmask;
8962 bnx2x_cl45_write(bp, phy,
8963 MDIO_PMA_DEVAD,
8964 MDIO_PMA_REG_8727_GPIO_CTRL,
8965 val);
8966 }
8967 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
8968 struct link_params *params) {
8969 u32 swap_val, swap_override;
8970 u8 port;
8971 /*
8972 * The PHY reset is controlled by GPIO 1. Fake the port number
8973 * to cancel the swap done in set_gpio()
8974 */
8975 struct bnx2x *bp = params->bp;
8976 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8977 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
8978 port = (swap_val && swap_override) ^ 1;
8979 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
8980 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
8981 }
8982
8983 static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
8984 struct link_params *params,
8985 struct link_vars *vars)
8986 {
8987 u32 tx_en_mode;
8988 u16 tmp1, val, mod_abs, tmp2;
8989 u16 rx_alarm_ctrl_val;
8990 u16 lasi_ctrl_val;
8991 struct bnx2x *bp = params->bp;
8992 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
8993
8994 bnx2x_wait_reset_complete(bp, phy, params);
8995 rx_alarm_ctrl_val = (1<<2) | (1<<5) ;
8996 /* Should be 0x6 to enable XS on Tx side. */
8997 lasi_ctrl_val = 0x0006;
8998
8999 DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
9000 /* enable LASI */
9001 bnx2x_cl45_write(bp, phy,
9002 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9003 rx_alarm_ctrl_val);
9004 bnx2x_cl45_write(bp, phy,
9005 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
9006 0);
9007 bnx2x_cl45_write(bp, phy,
9008 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, lasi_ctrl_val);
9009
9010 /*
9011 * Initially configure MOD_ABS to interrupt when module is
9012 * presence( bit 8)
9013 */
9014 bnx2x_cl45_read(bp, phy,
9015 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
9016 /*
9017 * Set EDC off by setting OPTXLOS signal input to low (bit 9).
9018 * When the EDC is off it locks onto a reference clock and avoids
9019 * becoming 'lost'
9020 */
9021 mod_abs &= ~(1<<8);
9022 if (!(phy->flags & FLAGS_NOC))
9023 mod_abs &= ~(1<<9);
9024 bnx2x_cl45_write(bp, phy,
9025 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9026
9027
9028 /* Enable/Disable PHY transmitter output */
9029 bnx2x_set_disable_pmd_transmit(params, phy, 0);
9030
9031 /* Make MOD_ABS give interrupt on change */
9032 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9033 &val);
9034 val |= (1<<12);
9035 if (phy->flags & FLAGS_NOC)
9036 val |= (3<<5);
9037
9038 /*
9039 * Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
9040 * status which reflect SFP+ module over-current
9041 */
9042 if (!(phy->flags & FLAGS_NOC))
9043 val &= 0xff8f; /* Reset bits 4-6 */
9044 bnx2x_cl45_write(bp, phy,
9045 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);
9046
9047 bnx2x_8727_power_module(bp, phy, 1);
9048
9049 bnx2x_cl45_read(bp, phy,
9050 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
9051
9052 bnx2x_cl45_read(bp, phy,
9053 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
9054
9055 /* Set option 1G speed */
9056 if (phy->req_line_speed == SPEED_1000) {
9057 DP(NETIF_MSG_LINK, "Setting 1G force\n");
9058 bnx2x_cl45_write(bp, phy,
9059 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
9060 bnx2x_cl45_write(bp, phy,
9061 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
9062 bnx2x_cl45_read(bp, phy,
9063 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
9064 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
9065 /*
9066 * Power down the XAUI until link is up in case of dual-media
9067 * and 1G
9068 */
9069 if (DUAL_MEDIA(params)) {
9070 bnx2x_cl45_read(bp, phy,
9071 MDIO_PMA_DEVAD,
9072 MDIO_PMA_REG_8727_PCS_GP, &val);
9073 val |= (3<<10);
9074 bnx2x_cl45_write(bp, phy,
9075 MDIO_PMA_DEVAD,
9076 MDIO_PMA_REG_8727_PCS_GP, val);
9077 }
9078 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9079 ((phy->speed_cap_mask &
9080 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
9081 ((phy->speed_cap_mask &
9082 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
9083 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
9084
9085 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
9086 bnx2x_cl45_write(bp, phy,
9087 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
9088 bnx2x_cl45_write(bp, phy,
9089 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
9090 } else {
9091 /*
9092 * Since the 8727 has only single reset pin, need to set the 10G
9093 * registers although it is default
9094 */
9095 bnx2x_cl45_write(bp, phy,
9096 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
9097 0x0020);
9098 bnx2x_cl45_write(bp, phy,
9099 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
9100 bnx2x_cl45_write(bp, phy,
9101 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
9102 bnx2x_cl45_write(bp, phy,
9103 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
9104 0x0008);
9105 }
9106
9107 /*
9108 * Set 2-wire transfer rate of SFP+ module EEPROM
9109 * to 100Khz since some DACs(direct attached cables) do
9110 * not work at 400Khz.
9111 */
9112 bnx2x_cl45_write(bp, phy,
9113 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
9114 0xa001);
9115
9116 /* Set TX PreEmphasis if needed */
9117 if ((params->feature_config_flags &
9118 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9119 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
9120 phy->tx_preemphasis[0],
9121 phy->tx_preemphasis[1]);
9122 bnx2x_cl45_write(bp, phy,
9123 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
9124 phy->tx_preemphasis[0]);
9125
9126 bnx2x_cl45_write(bp, phy,
9127 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
9128 phy->tx_preemphasis[1]);
9129 }
9130
9131 /*
9132 * If TX Laser is controlled by GPIO_0, do not let PHY go into low
9133 * power mode, if TX Laser is disabled
9134 */
9135 tx_en_mode = REG_RD(bp, params->shmem_base +
9136 offsetof(struct shmem_region,
9137 dev_info.port_hw_config[params->port].sfp_ctrl))
9138 & PORT_HW_CFG_TX_LASER_MASK;
9139
9140 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
9141
9142 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
9143 bnx2x_cl45_read(bp, phy,
9144 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
9145 tmp2 |= 0x1000;
9146 tmp2 &= 0xFFEF;
9147 bnx2x_cl45_write(bp, phy,
9148 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
9149 }
9150
9151 return 0;
9152 }
9153
9154 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
9155 struct link_params *params)
9156 {
9157 struct bnx2x *bp = params->bp;
9158 u16 mod_abs, rx_alarm_status;
9159 u32 val = REG_RD(bp, params->shmem_base +
9160 offsetof(struct shmem_region, dev_info.
9161 port_feature_config[params->port].
9162 config));
9163 bnx2x_cl45_read(bp, phy,
9164 MDIO_PMA_DEVAD,
9165 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
9166 if (mod_abs & (1<<8)) {
9167
9168 /* Module is absent */
9169 DP(NETIF_MSG_LINK,
9170 "MOD_ABS indication show module is absent\n");
9171 phy->media_type = ETH_PHY_NOT_PRESENT;
9172 /*
9173 * 1. Set mod_abs to detect next module
9174 * presence event
9175 * 2. Set EDC off by setting OPTXLOS signal input to low
9176 * (bit 9).
9177 * When the EDC is off it locks onto a reference clock and
9178 * avoids becoming 'lost'.
9179 */
9180 mod_abs &= ~(1<<8);
9181 if (!(phy->flags & FLAGS_NOC))
9182 mod_abs &= ~(1<<9);
9183 bnx2x_cl45_write(bp, phy,
9184 MDIO_PMA_DEVAD,
9185 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9186
9187 /*
9188 * Clear RX alarm since it stays up as long as
9189 * the mod_abs wasn't changed
9190 */
9191 bnx2x_cl45_read(bp, phy,
9192 MDIO_PMA_DEVAD,
9193 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9194
9195 } else {
9196 /* Module is present */
9197 DP(NETIF_MSG_LINK,
9198 "MOD_ABS indication show module is present\n");
9199 /*
9200 * First disable transmitter, and if the module is ok, the
9201 * module_detection will enable it
9202 * 1. Set mod_abs to detect next module absent event ( bit 8)
9203 * 2. Restore the default polarity of the OPRXLOS signal and
9204 * this signal will then correctly indicate the presence or
9205 * absence of the Rx signal. (bit 9)
9206 */
9207 mod_abs |= (1<<8);
9208 if (!(phy->flags & FLAGS_NOC))
9209 mod_abs |= (1<<9);
9210 bnx2x_cl45_write(bp, phy,
9211 MDIO_PMA_DEVAD,
9212 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9213
9214 /*
9215 * Clear RX alarm since it stays up as long as the mod_abs
9216 * wasn't changed. This is need to be done before calling the
9217 * module detection, otherwise it will clear* the link update
9218 * alarm
9219 */
9220 bnx2x_cl45_read(bp, phy,
9221 MDIO_PMA_DEVAD,
9222 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9223
9224
9225 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
9226 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
9227 bnx2x_sfp_set_transmitter(params, phy, 0);
9228
9229 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
9230 bnx2x_sfp_module_detection(phy, params);
9231 else
9232 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
9233 }
9234
9235 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
9236 rx_alarm_status);
9237 /* No need to check link status in case of module plugged in/out */
9238 }
9239
9240 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
9241 struct link_params *params,
9242 struct link_vars *vars)
9243
9244 {
9245 struct bnx2x *bp = params->bp;
9246 u8 link_up = 0, oc_port = params->port;
9247 u16 link_status = 0;
9248 u16 rx_alarm_status, lasi_ctrl, val1;
9249
9250 /* If PHY is not initialized, do not check link status */
9251 bnx2x_cl45_read(bp, phy,
9252 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
9253 &lasi_ctrl);
9254 if (!lasi_ctrl)
9255 return 0;
9256
9257 /* Check the LASI on Rx */
9258 bnx2x_cl45_read(bp, phy,
9259 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT,
9260 &rx_alarm_status);
9261 vars->line_speed = 0;
9262 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status);
9263
9264 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
9265 MDIO_PMA_LASI_TXCTRL);
9266
9267 bnx2x_cl45_read(bp, phy,
9268 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
9269
9270 DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
9271
9272 /* Clear MSG-OUT */
9273 bnx2x_cl45_read(bp, phy,
9274 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
9275
9276 /*
9277 * If a module is present and there is need to check
9278 * for over current
9279 */
9280 if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
9281 /* Check over-current using 8727 GPIO0 input*/
9282 bnx2x_cl45_read(bp, phy,
9283 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
9284 &val1);
9285
9286 if ((val1 & (1<<8)) == 0) {
9287 if (!CHIP_IS_E1x(bp))
9288 oc_port = BP_PATH(bp) + (params->port << 1);
9289 DP(NETIF_MSG_LINK,
9290 "8727 Power fault has been detected on port %d\n",
9291 oc_port);
9292 netdev_err(bp->dev, "Error: Power fault on Port %d has "
9293 "been detected and the power to "
9294 "that SFP+ module has been removed "
9295 "to prevent failure of the card. "
9296 "Please remove the SFP+ module and "
9297 "restart the system to clear this "
9298 "error.\n",
9299 oc_port);
9300 /* Disable all RX_ALARMs except for mod_abs */
9301 bnx2x_cl45_write(bp, phy,
9302 MDIO_PMA_DEVAD,
9303 MDIO_PMA_LASI_RXCTRL, (1<<5));
9304
9305 bnx2x_cl45_read(bp, phy,
9306 MDIO_PMA_DEVAD,
9307 MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
9308 /* Wait for module_absent_event */
9309 val1 |= (1<<8);
9310 bnx2x_cl45_write(bp, phy,
9311 MDIO_PMA_DEVAD,
9312 MDIO_PMA_REG_PHY_IDENTIFIER, val1);
9313 /* Clear RX alarm */
9314 bnx2x_cl45_read(bp, phy,
9315 MDIO_PMA_DEVAD,
9316 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9317 return 0;
9318 }
9319 } /* Over current check */
9320
9321 /* When module absent bit is set, check module */
9322 if (rx_alarm_status & (1<<5)) {
9323 bnx2x_8727_handle_mod_abs(phy, params);
9324 /* Enable all mod_abs and link detection bits */
9325 bnx2x_cl45_write(bp, phy,
9326 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9327 ((1<<5) | (1<<2)));
9328 }
9329 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser if SFP is approved\n");
9330 bnx2x_8727_specific_func(phy, params, ENABLE_TX);
9331 /* If transmitter is disabled, ignore false link up indication */
9332 bnx2x_cl45_read(bp, phy,
9333 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
9334 if (val1 & (1<<15)) {
9335 DP(NETIF_MSG_LINK, "Tx is disabled\n");
9336 return 0;
9337 }
9338
9339 bnx2x_cl45_read(bp, phy,
9340 MDIO_PMA_DEVAD,
9341 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
9342
9343 /*
9344 * Bits 0..2 --> speed detected,
9345 * Bits 13..15--> link is down
9346 */
9347 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
9348 link_up = 1;
9349 vars->line_speed = SPEED_10000;
9350 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
9351 params->port);
9352 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
9353 link_up = 1;
9354 vars->line_speed = SPEED_1000;
9355 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
9356 params->port);
9357 } else {
9358 link_up = 0;
9359 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
9360 params->port);
9361 }
9362
9363 /* Capture 10G link fault. */
9364 if (vars->line_speed == SPEED_10000) {
9365 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9366 MDIO_PMA_LASI_TXSTAT, &val1);
9367
9368 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9369 MDIO_PMA_LASI_TXSTAT, &val1);
9370
9371 if (val1 & (1<<0)) {
9372 vars->fault_detected = 1;
9373 }
9374 }
9375
9376 if (link_up) {
9377 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9378 vars->duplex = DUPLEX_FULL;
9379 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);
9380 }
9381
9382 if ((DUAL_MEDIA(params)) &&
9383 (phy->req_line_speed == SPEED_1000)) {
9384 bnx2x_cl45_read(bp, phy,
9385 MDIO_PMA_DEVAD,
9386 MDIO_PMA_REG_8727_PCS_GP, &val1);
9387 /*
9388 * In case of dual-media board and 1G, power up the XAUI side,
9389 * otherwise power it down. For 10G it is done automatically
9390 */
9391 if (link_up)
9392 val1 &= ~(3<<10);
9393 else
9394 val1 |= (3<<10);
9395 bnx2x_cl45_write(bp, phy,
9396 MDIO_PMA_DEVAD,
9397 MDIO_PMA_REG_8727_PCS_GP, val1);
9398 }
9399 return link_up;
9400 }
9401
9402 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
9403 struct link_params *params)
9404 {
9405 struct bnx2x *bp = params->bp;
9406
9407 /* Enable/Disable PHY transmitter output */
9408 bnx2x_set_disable_pmd_transmit(params, phy, 1);
9409
9410 /* Disable Transmitter */
9411 bnx2x_sfp_set_transmitter(params, phy, 0);
9412 /* Clear LASI */
9413 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
9414
9415 }
9416
9417 /******************************************************************/
9418 /* BCM8481/BCM84823/BCM84833 PHY SECTION */
9419 /******************************************************************/
9420 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
9421 struct bnx2x *bp,
9422 u8 port)
9423 {
9424 u16 val, fw_ver1, fw_ver2, cnt;
9425
9426 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
9427 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);
9428 bnx2x_save_spirom_version(bp, port,
9429 ((fw_ver1 & 0xf000)>>5) | (fw_ver1 & 0x7f),
9430 phy->ver_addr);
9431 } else {
9432 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */
9433 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
9434 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0014);
9435 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9436 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81B, 0x0000);
9437 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81C, 0x0300);
9438 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x0009);
9439
9440 for (cnt = 0; cnt < 100; cnt++) {
9441 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9442 if (val & 1)
9443 break;
9444 udelay(5);
9445 }
9446 if (cnt == 100) {
9447 DP(NETIF_MSG_LINK, "Unable to read 848xx "
9448 "phy fw version(1)\n");
9449 bnx2x_save_spirom_version(bp, port, 0,
9450 phy->ver_addr);
9451 return;
9452 }
9453
9454
9455 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
9456 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
9457 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9458 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
9459 for (cnt = 0; cnt < 100; cnt++) {
9460 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9461 if (val & 1)
9462 break;
9463 udelay(5);
9464 }
9465 if (cnt == 100) {
9466 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw "
9467 "version(2)\n");
9468 bnx2x_save_spirom_version(bp, port, 0,
9469 phy->ver_addr);
9470 return;
9471 }
9472
9473 /* lower 16 bits of the register SPI_FW_STATUS */
9474 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
9475 /* upper 16 bits of register SPI_FW_STATUS */
9476 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
9477
9478 bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1,
9479 phy->ver_addr);
9480 }
9481
9482 }
9483 static void bnx2x_848xx_set_led(struct bnx2x *bp,
9484 struct bnx2x_phy *phy)
9485 {
9486 u16 val, offset;
9487
9488 /* PHYC_CTL_LED_CTL */
9489 bnx2x_cl45_read(bp, phy,
9490 MDIO_PMA_DEVAD,
9491 MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
9492 val &= 0xFE00;
9493 val |= 0x0092;
9494
9495 bnx2x_cl45_write(bp, phy,
9496 MDIO_PMA_DEVAD,
9497 MDIO_PMA_REG_8481_LINK_SIGNAL, val);
9498
9499 bnx2x_cl45_write(bp, phy,
9500 MDIO_PMA_DEVAD,
9501 MDIO_PMA_REG_8481_LED1_MASK,
9502 0x80);
9503
9504 bnx2x_cl45_write(bp, phy,
9505 MDIO_PMA_DEVAD,
9506 MDIO_PMA_REG_8481_LED2_MASK,
9507 0x18);
9508
9509 /* Select activity source by Tx and Rx, as suggested by PHY AE */
9510 bnx2x_cl45_write(bp, phy,
9511 MDIO_PMA_DEVAD,
9512 MDIO_PMA_REG_8481_LED3_MASK,
9513 0x0006);
9514
9515 /* Select the closest activity blink rate to that in 10/100/1000 */
9516 bnx2x_cl45_write(bp, phy,
9517 MDIO_PMA_DEVAD,
9518 MDIO_PMA_REG_8481_LED3_BLINK,
9519 0);
9520
9521 /* Configure the blink rate to ~15.9 Hz */
9522 bnx2x_cl45_write(bp, phy,
9523 MDIO_PMA_DEVAD,
9524 MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH,
9525 MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ);
9526
9527 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
9528 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1;
9529 else
9530 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1;
9531
9532 bnx2x_cl45_read(bp, phy,
9533 MDIO_PMA_DEVAD, offset, &val);
9534 val |= MDIO_PMA_REG_84823_LED3_STRETCH_EN; /* stretch_en for LED3*/
9535 bnx2x_cl45_write(bp, phy,
9536 MDIO_PMA_DEVAD, offset, val);
9537
9538 /* 'Interrupt Mask' */
9539 bnx2x_cl45_write(bp, phy,
9540 MDIO_AN_DEVAD,
9541 0xFFFB, 0xFFFD);
9542 }
9543
9544 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
9545 struct link_params *params,
9546 struct link_vars *vars)
9547 {
9548 struct bnx2x *bp = params->bp;
9549 u16 autoneg_val, an_1000_val, an_10_100_val, an_10g_val;
9550
9551 if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
9552 /* Save spirom version */
9553 bnx2x_save_848xx_spirom_version(phy, bp, params->port);
9554 }
9555 /*
9556 * This phy uses the NIG latch mechanism since link indication
9557 * arrives through its LED4 and not via its LASI signal, so we
9558 * get steady signal instead of clear on read
9559 */
9560 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
9561 1 << NIG_LATCH_BC_ENABLE_MI_INT);
9562
9563 bnx2x_cl45_write(bp, phy,
9564 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
9565
9566 bnx2x_848xx_set_led(bp, phy);
9567
9568 /* set 1000 speed advertisement */
9569 bnx2x_cl45_read(bp, phy,
9570 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9571 &an_1000_val);
9572
9573 bnx2x_ext_phy_set_pause(params, phy, vars);
9574 bnx2x_cl45_read(bp, phy,
9575 MDIO_AN_DEVAD,
9576 MDIO_AN_REG_8481_LEGACY_AN_ADV,
9577 &an_10_100_val);
9578 bnx2x_cl45_read(bp, phy,
9579 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9580 &autoneg_val);
9581 /* Disable forced speed */
9582 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
9583 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
9584
9585 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9586 (phy->speed_cap_mask &
9587 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9588 (phy->req_line_speed == SPEED_1000)) {
9589 an_1000_val |= (1<<8);
9590 autoneg_val |= (1<<9 | 1<<12);
9591 if (phy->req_duplex == DUPLEX_FULL)
9592 an_1000_val |= (1<<9);
9593 DP(NETIF_MSG_LINK, "Advertising 1G\n");
9594 } else
9595 an_1000_val &= ~((1<<8) | (1<<9));
9596
9597 bnx2x_cl45_write(bp, phy,
9598 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9599 an_1000_val);
9600
9601 /* set 100 speed advertisement */
9602 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9603 (phy->speed_cap_mask &
9604 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
9605 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))) {
9606 an_10_100_val |= (1<<7);
9607 /* Enable autoneg and restart autoneg for legacy speeds */
9608 autoneg_val |= (1<<9 | 1<<12);
9609
9610 if (phy->req_duplex == DUPLEX_FULL)
9611 an_10_100_val |= (1<<8);
9612 DP(NETIF_MSG_LINK, "Advertising 100M\n");
9613 }
9614 /* set 10 speed advertisement */
9615 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9616 (phy->speed_cap_mask &
9617 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
9618 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) &&
9619 (phy->supported &
9620 (SUPPORTED_10baseT_Half |
9621 SUPPORTED_10baseT_Full)))) {
9622 an_10_100_val |= (1<<5);
9623 autoneg_val |= (1<<9 | 1<<12);
9624 if (phy->req_duplex == DUPLEX_FULL)
9625 an_10_100_val |= (1<<6);
9626 DP(NETIF_MSG_LINK, "Advertising 10M\n");
9627 }
9628
9629 /* Only 10/100 are allowed to work in FORCE mode */
9630 if ((phy->req_line_speed == SPEED_100) &&
9631 (phy->supported &
9632 (SUPPORTED_100baseT_Half |
9633 SUPPORTED_100baseT_Full))) {
9634 autoneg_val |= (1<<13);
9635 /* Enabled AUTO-MDIX when autoneg is disabled */
9636 bnx2x_cl45_write(bp, phy,
9637 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9638 (1<<15 | 1<<9 | 7<<0));
9639 /* The PHY needs this set even for forced link. */
9640 an_10_100_val |= (1<<8) | (1<<7);
9641 DP(NETIF_MSG_LINK, "Setting 100M force\n");
9642 }
9643 if ((phy->req_line_speed == SPEED_10) &&
9644 (phy->supported &
9645 (SUPPORTED_10baseT_Half |
9646 SUPPORTED_10baseT_Full))) {
9647 /* Enabled AUTO-MDIX when autoneg is disabled */
9648 bnx2x_cl45_write(bp, phy,
9649 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9650 (1<<15 | 1<<9 | 7<<0));
9651 DP(NETIF_MSG_LINK, "Setting 10M force\n");
9652 }
9653
9654 bnx2x_cl45_write(bp, phy,
9655 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
9656 an_10_100_val);
9657
9658 if (phy->req_duplex == DUPLEX_FULL)
9659 autoneg_val |= (1<<8);
9660
9661 /*
9662 * Always write this if this is not 84833.
9663 * For 84833, write it only when it's a forced speed.
9664 */
9665 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
9666 ((autoneg_val & (1<<12)) == 0))
9667 bnx2x_cl45_write(bp, phy,
9668 MDIO_AN_DEVAD,
9669 MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
9670
9671 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9672 (phy->speed_cap_mask &
9673 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
9674 (phy->req_line_speed == SPEED_10000)) {
9675 DP(NETIF_MSG_LINK, "Advertising 10G\n");
9676 /* Restart autoneg for 10G*/
9677
9678 bnx2x_cl45_read(bp, phy,
9679 MDIO_AN_DEVAD,
9680 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9681 &an_10g_val);
9682 bnx2x_cl45_write(bp, phy,
9683 MDIO_AN_DEVAD,
9684 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9685 an_10g_val | 0x1000);
9686 bnx2x_cl45_write(bp, phy,
9687 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
9688 0x3200);
9689 } else
9690 bnx2x_cl45_write(bp, phy,
9691 MDIO_AN_DEVAD,
9692 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9693 1);
9694
9695 return 0;
9696 }
9697
9698 static int bnx2x_8481_config_init(struct bnx2x_phy *phy,
9699 struct link_params *params,
9700 struct link_vars *vars)
9701 {
9702 struct bnx2x *bp = params->bp;
9703 /* Restore normal power mode*/
9704 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
9705 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
9706
9707 /* HW reset */
9708 bnx2x_ext_phy_hw_reset(bp, params->port);
9709 bnx2x_wait_reset_complete(bp, phy, params);
9710
9711 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9712 return bnx2x_848xx_cmn_config_init(phy, params, vars);
9713 }
9714
9715 #define PHY84833_CMDHDLR_WAIT 300
9716 #define PHY84833_CMDHDLR_MAX_ARGS 5
9717 static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy,
9718 struct link_params *params,
9719 u16 fw_cmd,
9720 u16 cmd_args[])
9721 {
9722 u32 idx;
9723 u16 val;
9724 struct bnx2x *bp = params->bp;
9725 /* Write CMD_OPEN_OVERRIDE to STATUS reg */
9726 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9727 MDIO_84833_CMD_HDLR_STATUS,
9728 PHY84833_STATUS_CMD_OPEN_OVERRIDE);
9729 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9730 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9731 MDIO_84833_CMD_HDLR_STATUS, &val);
9732 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS)
9733 break;
9734 msleep(1);
9735 }
9736 if (idx >= PHY84833_CMDHDLR_WAIT) {
9737 DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n");
9738 return -EINVAL;
9739 }
9740
9741 /* Prepare argument(s) and issue command */
9742 for (idx = 0; idx < PHY84833_CMDHDLR_MAX_ARGS; idx++) {
9743 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9744 MDIO_84833_CMD_HDLR_DATA1 + idx,
9745 cmd_args[idx]);
9746 }
9747 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9748 MDIO_84833_CMD_HDLR_COMMAND, fw_cmd);
9749 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9750 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9751 MDIO_84833_CMD_HDLR_STATUS, &val);
9752 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) ||
9753 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR))
9754 break;
9755 msleep(1);
9756 }
9757 if ((idx >= PHY84833_CMDHDLR_WAIT) ||
9758 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) {
9759 DP(NETIF_MSG_LINK, "FW cmd failed.\n");
9760 return -EINVAL;
9761 }
9762 /* Gather returning data */
9763 for (idx = 0; idx < PHY84833_CMDHDLR_MAX_ARGS; idx++) {
9764 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9765 MDIO_84833_CMD_HDLR_DATA1 + idx,
9766 &cmd_args[idx]);
9767 }
9768 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9769 MDIO_84833_CMD_HDLR_STATUS,
9770 PHY84833_STATUS_CMD_CLEAR_COMPLETE);
9771 return 0;
9772 }
9773
9774
9775 static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy,
9776 struct link_params *params,
9777 struct link_vars *vars)
9778 {
9779 u32 pair_swap;
9780 u16 data[PHY84833_CMDHDLR_MAX_ARGS];
9781 int status;
9782 struct bnx2x *bp = params->bp;
9783
9784 /* Check for configuration. */
9785 pair_swap = REG_RD(bp, params->shmem_base +
9786 offsetof(struct shmem_region,
9787 dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
9788 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
9789
9790 if (pair_swap == 0)
9791 return 0;
9792
9793 /* Only the second argument is used for this command */
9794 data[1] = (u16)pair_swap;
9795
9796 status = bnx2x_84833_cmd_hdlr(phy, params,
9797 PHY84833_CMD_SET_PAIR_SWAP, data);
9798 if (status == 0)
9799 DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data[1]);
9800
9801 return status;
9802 }
9803
9804 static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp,
9805 u32 shmem_base_path[],
9806 u32 chip_id)
9807 {
9808 u32 reset_pin[2];
9809 u32 idx;
9810 u8 reset_gpios;
9811 if (CHIP_IS_E3(bp)) {
9812 /* Assume that these will be GPIOs, not EPIOs. */
9813 for (idx = 0; idx < 2; idx++) {
9814 /* Map config param to register bit. */
9815 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9816 offsetof(struct shmem_region,
9817 dev_info.port_hw_config[0].e3_cmn_pin_cfg));
9818 reset_pin[idx] = (reset_pin[idx] &
9819 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
9820 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
9821 reset_pin[idx] -= PIN_CFG_GPIO0_P0;
9822 reset_pin[idx] = (1 << reset_pin[idx]);
9823 }
9824 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9825 } else {
9826 /* E2, look from diff place of shmem. */
9827 for (idx = 0; idx < 2; idx++) {
9828 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9829 offsetof(struct shmem_region,
9830 dev_info.port_hw_config[0].default_cfg));
9831 reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
9832 reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
9833 reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
9834 reset_pin[idx] = (1 << reset_pin[idx]);
9835 }
9836 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9837 }
9838
9839 return reset_gpios;
9840 }
9841
9842 static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy,
9843 struct link_params *params)
9844 {
9845 struct bnx2x *bp = params->bp;
9846 u8 reset_gpios;
9847 u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base +
9848 offsetof(struct shmem2_region,
9849 other_shmem_base_addr));
9850
9851 u32 shmem_base_path[2];
9852 shmem_base_path[0] = params->shmem_base;
9853 shmem_base_path[1] = other_shmem_base_addr;
9854
9855 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path,
9856 params->chip_id);
9857
9858 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
9859 udelay(10);
9860 DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n",
9861 reset_gpios);
9862
9863 return 0;
9864 }
9865
9866 #define PHY84833_CONSTANT_LATENCY 1193
9867 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
9868 struct link_params *params,
9869 struct link_vars *vars)
9870 {
9871 struct bnx2x *bp = params->bp;
9872 u8 port, initialize = 1;
9873 u16 val;
9874 u32 actual_phy_selection, cms_enable;
9875 u16 cmd_args[PHY84833_CMDHDLR_MAX_ARGS];
9876 int rc = 0;
9877
9878 msleep(1);
9879
9880 if (!(CHIP_IS_E1(bp)))
9881 port = BP_PATH(bp);
9882 else
9883 port = params->port;
9884
9885 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
9886 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
9887 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
9888 port);
9889 } else {
9890 /* MDIO reset */
9891 bnx2x_cl45_write(bp, phy,
9892 MDIO_PMA_DEVAD,
9893 MDIO_PMA_REG_CTRL, 0x8000);
9894 }
9895
9896 bnx2x_wait_reset_complete(bp, phy, params);
9897
9898 /* Wait for GPHY to come out of reset */
9899 msleep(50);
9900 if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
9901 /*
9902 * BCM84823 requires that XGXS links up first @ 10G for normal
9903 * behavior.
9904 */
9905 u16 temp;
9906 temp = vars->line_speed;
9907 vars->line_speed = SPEED_10000;
9908 bnx2x_set_autoneg(&params->phy[INT_PHY], params, vars, 0);
9909 bnx2x_program_serdes(&params->phy[INT_PHY], params, vars);
9910 vars->line_speed = temp;
9911 }
9912
9913 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9914 MDIO_CTL_REG_84823_MEDIA, &val);
9915 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
9916 MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
9917 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
9918 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
9919 MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
9920
9921 if (CHIP_IS_E3(bp)) {
9922 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
9923 MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
9924 } else {
9925 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
9926 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
9927 }
9928
9929 actual_phy_selection = bnx2x_phy_selection(params);
9930
9931 switch (actual_phy_selection) {
9932 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
9933 /* Do nothing. Essentially this is like the priority copper */
9934 break;
9935 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
9936 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
9937 break;
9938 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
9939 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
9940 break;
9941 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
9942 /* Do nothing here. The first PHY won't be initialized at all */
9943 break;
9944 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
9945 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
9946 initialize = 0;
9947 break;
9948 }
9949 if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
9950 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
9951
9952 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9953 MDIO_CTL_REG_84823_MEDIA, val);
9954 DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
9955 params->multi_phy_config, val);
9956
9957 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
9958 bnx2x_84833_pair_swap_cfg(phy, params, vars);
9959
9960 /* Keep AutogrEEEn disabled. */
9961 cmd_args[0] = 0x0;
9962 cmd_args[1] = 0x0;
9963 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1;
9964 cmd_args[3] = PHY84833_CONSTANT_LATENCY;
9965 rc = bnx2x_84833_cmd_hdlr(phy, params,
9966 PHY84833_CMD_SET_EEE_MODE, cmd_args);
9967 if (rc != 0)
9968 DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n");
9969 }
9970 if (initialize)
9971 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
9972 else
9973 bnx2x_save_848xx_spirom_version(phy, bp, params->port);
9974 /* 84833 PHY has a better feature and doesn't need to support this. */
9975 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
9976 cms_enable = REG_RD(bp, params->shmem_base +
9977 offsetof(struct shmem_region,
9978 dev_info.port_hw_config[params->port].default_cfg)) &
9979 PORT_HW_CFG_ENABLE_CMS_MASK;
9980
9981 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9982 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
9983 if (cms_enable)
9984 val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
9985 else
9986 val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
9987 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9988 MDIO_CTL_REG_84823_USER_CTRL_REG, val);
9989 }
9990
9991 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
9992 /* Bring PHY out of super isolate mode as the final step. */
9993 bnx2x_cl45_read(bp, phy,
9994 MDIO_CTL_DEVAD,
9995 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val);
9996 val &= ~MDIO_84833_SUPER_ISOLATE;
9997 bnx2x_cl45_write(bp, phy,
9998 MDIO_CTL_DEVAD,
9999 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val);
10000 }
10001 return rc;
10002 }
10003
10004 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
10005 struct link_params *params,
10006 struct link_vars *vars)
10007 {
10008 struct bnx2x *bp = params->bp;
10009 u16 val, val1, val2;
10010 u8 link_up = 0;
10011
10012
10013 /* Check 10G-BaseT link status */
10014 /* Check PMD signal ok */
10015 bnx2x_cl45_read(bp, phy,
10016 MDIO_AN_DEVAD, 0xFFFA, &val1);
10017 bnx2x_cl45_read(bp, phy,
10018 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
10019 &val2);
10020 DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
10021
10022 /* Check link 10G */
10023 if (val2 & (1<<11)) {
10024 vars->line_speed = SPEED_10000;
10025 vars->duplex = DUPLEX_FULL;
10026 link_up = 1;
10027 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
10028 } else { /* Check Legacy speed link */
10029 u16 legacy_status, legacy_speed;
10030
10031 /* Enable expansion register 0x42 (Operation mode status) */
10032 bnx2x_cl45_write(bp, phy,
10033 MDIO_AN_DEVAD,
10034 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
10035
10036 /* Get legacy speed operation status */
10037 bnx2x_cl45_read(bp, phy,
10038 MDIO_AN_DEVAD,
10039 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
10040 &legacy_status);
10041
10042 DP(NETIF_MSG_LINK, "Legacy speed status = 0x%x\n",
10043 legacy_status);
10044 link_up = ((legacy_status & (1<<11)) == (1<<11));
10045 if (link_up) {
10046 legacy_speed = (legacy_status & (3<<9));
10047 if (legacy_speed == (0<<9))
10048 vars->line_speed = SPEED_10;
10049 else if (legacy_speed == (1<<9))
10050 vars->line_speed = SPEED_100;
10051 else if (legacy_speed == (2<<9))
10052 vars->line_speed = SPEED_1000;
10053 else /* Should not happen */
10054 vars->line_speed = 0;
10055
10056 if (legacy_status & (1<<8))
10057 vars->duplex = DUPLEX_FULL;
10058 else
10059 vars->duplex = DUPLEX_HALF;
10060
10061 DP(NETIF_MSG_LINK,
10062 "Link is up in %dMbps, is_duplex_full= %d\n",
10063 vars->line_speed,
10064 (vars->duplex == DUPLEX_FULL));
10065 /* Check legacy speed AN resolution */
10066 bnx2x_cl45_read(bp, phy,
10067 MDIO_AN_DEVAD,
10068 MDIO_AN_REG_8481_LEGACY_MII_STATUS,
10069 &val);
10070 if (val & (1<<5))
10071 vars->link_status |=
10072 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10073 bnx2x_cl45_read(bp, phy,
10074 MDIO_AN_DEVAD,
10075 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
10076 &val);
10077 if ((val & (1<<0)) == 0)
10078 vars->link_status |=
10079 LINK_STATUS_PARALLEL_DETECTION_USED;
10080 }
10081 }
10082 if (link_up) {
10083 DP(NETIF_MSG_LINK, "BCM84823: link speed is %d\n",
10084 vars->line_speed);
10085 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10086
10087 /* Read LP advertised speeds */
10088 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10089 MDIO_AN_REG_CL37_FC_LP, &val);
10090 if (val & (1<<5))
10091 vars->link_status |=
10092 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
10093 if (val & (1<<6))
10094 vars->link_status |=
10095 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
10096 if (val & (1<<7))
10097 vars->link_status |=
10098 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
10099 if (val & (1<<8))
10100 vars->link_status |=
10101 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
10102 if (val & (1<<9))
10103 vars->link_status |=
10104 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
10105
10106 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10107 MDIO_AN_REG_1000T_STATUS, &val);
10108
10109 if (val & (1<<10))
10110 vars->link_status |=
10111 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
10112 if (val & (1<<11))
10113 vars->link_status |=
10114 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
10115
10116 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10117 MDIO_AN_REG_MASTER_STATUS, &val);
10118
10119 if (val & (1<<11))
10120 vars->link_status |=
10121 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
10122 }
10123
10124 return link_up;
10125 }
10126
10127
10128 static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
10129 {
10130 int status = 0;
10131 u32 spirom_ver;
10132 spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
10133 status = bnx2x_format_ver(spirom_ver, str, len);
10134 return status;
10135 }
10136
10137 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
10138 struct link_params *params)
10139 {
10140 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10141 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
10142 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10143 MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
10144 }
10145
10146 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
10147 struct link_params *params)
10148 {
10149 bnx2x_cl45_write(params->bp, phy,
10150 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
10151 bnx2x_cl45_write(params->bp, phy,
10152 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
10153 }
10154
10155 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
10156 struct link_params *params)
10157 {
10158 struct bnx2x *bp = params->bp;
10159 u8 port;
10160 u16 val16;
10161
10162 if (!(CHIP_IS_E1(bp)))
10163 port = BP_PATH(bp);
10164 else
10165 port = params->port;
10166
10167 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10168 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
10169 MISC_REGISTERS_GPIO_OUTPUT_LOW,
10170 port);
10171 } else {
10172 bnx2x_cl45_read(bp, phy,
10173 MDIO_CTL_DEVAD,
10174 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16);
10175 val16 |= MDIO_84833_SUPER_ISOLATE;
10176 bnx2x_cl45_write(bp, phy,
10177 MDIO_CTL_DEVAD,
10178 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16);
10179 }
10180 }
10181
10182 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
10183 struct link_params *params, u8 mode)
10184 {
10185 struct bnx2x *bp = params->bp;
10186 u16 val;
10187 u8 port;
10188
10189 if (!(CHIP_IS_E1(bp)))
10190 port = BP_PATH(bp);
10191 else
10192 port = params->port;
10193
10194 switch (mode) {
10195 case LED_MODE_OFF:
10196
10197 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port);
10198
10199 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10200 SHARED_HW_CFG_LED_EXTPHY1) {
10201
10202 /* Set LED masks */
10203 bnx2x_cl45_write(bp, phy,
10204 MDIO_PMA_DEVAD,
10205 MDIO_PMA_REG_8481_LED1_MASK,
10206 0x0);
10207
10208 bnx2x_cl45_write(bp, phy,
10209 MDIO_PMA_DEVAD,
10210 MDIO_PMA_REG_8481_LED2_MASK,
10211 0x0);
10212
10213 bnx2x_cl45_write(bp, phy,
10214 MDIO_PMA_DEVAD,
10215 MDIO_PMA_REG_8481_LED3_MASK,
10216 0x0);
10217
10218 bnx2x_cl45_write(bp, phy,
10219 MDIO_PMA_DEVAD,
10220 MDIO_PMA_REG_8481_LED5_MASK,
10221 0x0);
10222
10223 } else {
10224 bnx2x_cl45_write(bp, phy,
10225 MDIO_PMA_DEVAD,
10226 MDIO_PMA_REG_8481_LED1_MASK,
10227 0x0);
10228 }
10229 break;
10230 case LED_MODE_FRONT_PANEL_OFF:
10231
10232 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
10233 port);
10234
10235 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10236 SHARED_HW_CFG_LED_EXTPHY1) {
10237
10238 /* Set LED masks */
10239 bnx2x_cl45_write(bp, phy,
10240 MDIO_PMA_DEVAD,
10241 MDIO_PMA_REG_8481_LED1_MASK,
10242 0x0);
10243
10244 bnx2x_cl45_write(bp, phy,
10245 MDIO_PMA_DEVAD,
10246 MDIO_PMA_REG_8481_LED2_MASK,
10247 0x0);
10248
10249 bnx2x_cl45_write(bp, phy,
10250 MDIO_PMA_DEVAD,
10251 MDIO_PMA_REG_8481_LED3_MASK,
10252 0x0);
10253
10254 bnx2x_cl45_write(bp, phy,
10255 MDIO_PMA_DEVAD,
10256 MDIO_PMA_REG_8481_LED5_MASK,
10257 0x20);
10258
10259 } else {
10260 bnx2x_cl45_write(bp, phy,
10261 MDIO_PMA_DEVAD,
10262 MDIO_PMA_REG_8481_LED1_MASK,
10263 0x0);
10264 }
10265 break;
10266 case LED_MODE_ON:
10267
10268 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port);
10269
10270 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10271 SHARED_HW_CFG_LED_EXTPHY1) {
10272 /* Set control reg */
10273 bnx2x_cl45_read(bp, phy,
10274 MDIO_PMA_DEVAD,
10275 MDIO_PMA_REG_8481_LINK_SIGNAL,
10276 &val);
10277 val &= 0x8000;
10278 val |= 0x2492;
10279
10280 bnx2x_cl45_write(bp, phy,
10281 MDIO_PMA_DEVAD,
10282 MDIO_PMA_REG_8481_LINK_SIGNAL,
10283 val);
10284
10285 /* Set LED masks */
10286 bnx2x_cl45_write(bp, phy,
10287 MDIO_PMA_DEVAD,
10288 MDIO_PMA_REG_8481_LED1_MASK,
10289 0x0);
10290
10291 bnx2x_cl45_write(bp, phy,
10292 MDIO_PMA_DEVAD,
10293 MDIO_PMA_REG_8481_LED2_MASK,
10294 0x20);
10295
10296 bnx2x_cl45_write(bp, phy,
10297 MDIO_PMA_DEVAD,
10298 MDIO_PMA_REG_8481_LED3_MASK,
10299 0x20);
10300
10301 bnx2x_cl45_write(bp, phy,
10302 MDIO_PMA_DEVAD,
10303 MDIO_PMA_REG_8481_LED5_MASK,
10304 0x0);
10305 } else {
10306 bnx2x_cl45_write(bp, phy,
10307 MDIO_PMA_DEVAD,
10308 MDIO_PMA_REG_8481_LED1_MASK,
10309 0x20);
10310 }
10311 break;
10312
10313 case LED_MODE_OPER:
10314
10315 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port);
10316
10317 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10318 SHARED_HW_CFG_LED_EXTPHY1) {
10319
10320 /* Set control reg */
10321 bnx2x_cl45_read(bp, phy,
10322 MDIO_PMA_DEVAD,
10323 MDIO_PMA_REG_8481_LINK_SIGNAL,
10324 &val);
10325
10326 if (!((val &
10327 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
10328 >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
10329 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n");
10330 bnx2x_cl45_write(bp, phy,
10331 MDIO_PMA_DEVAD,
10332 MDIO_PMA_REG_8481_LINK_SIGNAL,
10333 0xa492);
10334 }
10335
10336 /* Set LED masks */
10337 bnx2x_cl45_write(bp, phy,
10338 MDIO_PMA_DEVAD,
10339 MDIO_PMA_REG_8481_LED1_MASK,
10340 0x10);
10341
10342 bnx2x_cl45_write(bp, phy,
10343 MDIO_PMA_DEVAD,
10344 MDIO_PMA_REG_8481_LED2_MASK,
10345 0x80);
10346
10347 bnx2x_cl45_write(bp, phy,
10348 MDIO_PMA_DEVAD,
10349 MDIO_PMA_REG_8481_LED3_MASK,
10350 0x98);
10351
10352 bnx2x_cl45_write(bp, phy,
10353 MDIO_PMA_DEVAD,
10354 MDIO_PMA_REG_8481_LED5_MASK,
10355 0x40);
10356
10357 } else {
10358 bnx2x_cl45_write(bp, phy,
10359 MDIO_PMA_DEVAD,
10360 MDIO_PMA_REG_8481_LED1_MASK,
10361 0x80);
10362
10363 /* Tell LED3 to blink on source */
10364 bnx2x_cl45_read(bp, phy,
10365 MDIO_PMA_DEVAD,
10366 MDIO_PMA_REG_8481_LINK_SIGNAL,
10367 &val);
10368 val &= ~(7<<6);
10369 val |= (1<<6); /* A83B[8:6]= 1 */
10370 bnx2x_cl45_write(bp, phy,
10371 MDIO_PMA_DEVAD,
10372 MDIO_PMA_REG_8481_LINK_SIGNAL,
10373 val);
10374 }
10375 break;
10376 }
10377
10378 /*
10379 * This is a workaround for E3+84833 until autoneg
10380 * restart is fixed in f/w
10381 */
10382 if (CHIP_IS_E3(bp)) {
10383 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
10384 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
10385 }
10386 }
10387
10388 /******************************************************************/
10389 /* 54618SE PHY SECTION */
10390 /******************************************************************/
10391 static int bnx2x_54618se_config_init(struct bnx2x_phy *phy,
10392 struct link_params *params,
10393 struct link_vars *vars)
10394 {
10395 struct bnx2x *bp = params->bp;
10396 u8 port;
10397 u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
10398 u32 cfg_pin;
10399
10400 DP(NETIF_MSG_LINK, "54618SE cfg init\n");
10401 usleep_range(1000, 1000);
10402
10403 /*
10404 * This works with E3 only, no need to check the chip
10405 * before determining the port.
10406 */
10407 port = params->port;
10408
10409 cfg_pin = (REG_RD(bp, params->shmem_base +
10410 offsetof(struct shmem_region,
10411 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10412 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10413 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10414
10415 /* Drive pin high to bring the GPHY out of reset. */
10416 bnx2x_set_cfg_pin(bp, cfg_pin, 1);
10417
10418 /* wait for GPHY to reset */
10419 msleep(50);
10420
10421 /* reset phy */
10422 bnx2x_cl22_write(bp, phy,
10423 MDIO_PMA_REG_CTRL, 0x8000);
10424 bnx2x_wait_reset_complete(bp, phy, params);
10425
10426 /*wait for GPHY to reset */
10427 msleep(50);
10428
10429 /* Configure LED4: set to INTR (0x6). */
10430 /* Accessing shadow register 0xe. */
10431 bnx2x_cl22_write(bp, phy,
10432 MDIO_REG_GPHY_SHADOW,
10433 MDIO_REG_GPHY_SHADOW_LED_SEL2);
10434 bnx2x_cl22_read(bp, phy,
10435 MDIO_REG_GPHY_SHADOW,
10436 &temp);
10437 temp &= ~(0xf << 4);
10438 temp |= (0x6 << 4);
10439 bnx2x_cl22_write(bp, phy,
10440 MDIO_REG_GPHY_SHADOW,
10441 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10442 /* Configure INTR based on link status change. */
10443 bnx2x_cl22_write(bp, phy,
10444 MDIO_REG_INTR_MASK,
10445 ~MDIO_REG_INTR_MASK_LINK_STATUS);
10446
10447 /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
10448 bnx2x_cl22_write(bp, phy,
10449 MDIO_REG_GPHY_SHADOW,
10450 MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
10451 bnx2x_cl22_read(bp, phy,
10452 MDIO_REG_GPHY_SHADOW,
10453 &temp);
10454 temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
10455 bnx2x_cl22_write(bp, phy,
10456 MDIO_REG_GPHY_SHADOW,
10457 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10458
10459 /* Set up fc */
10460 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
10461 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
10462 fc_val = 0;
10463 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
10464 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
10465 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
10466
10467 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
10468 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
10469 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
10470
10471 /* read all advertisement */
10472 bnx2x_cl22_read(bp, phy,
10473 0x09,
10474 &an_1000_val);
10475
10476 bnx2x_cl22_read(bp, phy,
10477 0x04,
10478 &an_10_100_val);
10479
10480 bnx2x_cl22_read(bp, phy,
10481 MDIO_PMA_REG_CTRL,
10482 &autoneg_val);
10483
10484 /* Disable forced speed */
10485 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
10486 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) |
10487 (1<<11));
10488
10489 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10490 (phy->speed_cap_mask &
10491 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
10492 (phy->req_line_speed == SPEED_1000)) {
10493 an_1000_val |= (1<<8);
10494 autoneg_val |= (1<<9 | 1<<12);
10495 if (phy->req_duplex == DUPLEX_FULL)
10496 an_1000_val |= (1<<9);
10497 DP(NETIF_MSG_LINK, "Advertising 1G\n");
10498 } else
10499 an_1000_val &= ~((1<<8) | (1<<9));
10500
10501 bnx2x_cl22_write(bp, phy,
10502 0x09,
10503 an_1000_val);
10504 bnx2x_cl22_read(bp, phy,
10505 0x09,
10506 &an_1000_val);
10507
10508 /* set 100 speed advertisement */
10509 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10510 (phy->speed_cap_mask &
10511 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
10512 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
10513 an_10_100_val |= (1<<7);
10514 /* Enable autoneg and restart autoneg for legacy speeds */
10515 autoneg_val |= (1<<9 | 1<<12);
10516
10517 if (phy->req_duplex == DUPLEX_FULL)
10518 an_10_100_val |= (1<<8);
10519 DP(NETIF_MSG_LINK, "Advertising 100M\n");
10520 }
10521
10522 /* set 10 speed advertisement */
10523 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10524 (phy->speed_cap_mask &
10525 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
10526 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
10527 an_10_100_val |= (1<<5);
10528 autoneg_val |= (1<<9 | 1<<12);
10529 if (phy->req_duplex == DUPLEX_FULL)
10530 an_10_100_val |= (1<<6);
10531 DP(NETIF_MSG_LINK, "Advertising 10M\n");
10532 }
10533
10534 /* Only 10/100 are allowed to work in FORCE mode */
10535 if (phy->req_line_speed == SPEED_100) {
10536 autoneg_val |= (1<<13);
10537 /* Enabled AUTO-MDIX when autoneg is disabled */
10538 bnx2x_cl22_write(bp, phy,
10539 0x18,
10540 (1<<15 | 1<<9 | 7<<0));
10541 DP(NETIF_MSG_LINK, "Setting 100M force\n");
10542 }
10543 if (phy->req_line_speed == SPEED_10) {
10544 /* Enabled AUTO-MDIX when autoneg is disabled */
10545 bnx2x_cl22_write(bp, phy,
10546 0x18,
10547 (1<<15 | 1<<9 | 7<<0));
10548 DP(NETIF_MSG_LINK, "Setting 10M force\n");
10549 }
10550
10551 /* Check if we should turn on Auto-GrEEEn */
10552 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_PHYID_LSB, &temp);
10553 if (temp == MDIO_REG_GPHY_ID_54618SE) {
10554 if (params->feature_config_flags &
10555 FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
10556 temp = 6;
10557 DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n");
10558 } else {
10559 temp = 0;
10560 DP(NETIF_MSG_LINK, "Disabling Auto-GrEEEn\n");
10561 }
10562 bnx2x_cl22_write(bp, phy,
10563 MDIO_REG_GPHY_CL45_ADDR_REG, MDIO_AN_DEVAD);
10564 bnx2x_cl22_write(bp, phy,
10565 MDIO_REG_GPHY_CL45_DATA_REG,
10566 MDIO_REG_GPHY_EEE_ADV);
10567 bnx2x_cl22_write(bp, phy,
10568 MDIO_REG_GPHY_CL45_ADDR_REG,
10569 (0x1 << 14) | MDIO_AN_DEVAD);
10570 bnx2x_cl22_write(bp, phy,
10571 MDIO_REG_GPHY_CL45_DATA_REG,
10572 temp);
10573 }
10574
10575 bnx2x_cl22_write(bp, phy,
10576 0x04,
10577 an_10_100_val | fc_val);
10578
10579 if (phy->req_duplex == DUPLEX_FULL)
10580 autoneg_val |= (1<<8);
10581
10582 bnx2x_cl22_write(bp, phy,
10583 MDIO_PMA_REG_CTRL, autoneg_val);
10584
10585 return 0;
10586 }
10587
10588
10589 static void bnx2x_5461x_set_link_led(struct bnx2x_phy *phy,
10590 struct link_params *params, u8 mode)
10591 {
10592 struct bnx2x *bp = params->bp;
10593 u16 temp;
10594
10595 bnx2x_cl22_write(bp, phy,
10596 MDIO_REG_GPHY_SHADOW,
10597 MDIO_REG_GPHY_SHADOW_LED_SEL1);
10598 bnx2x_cl22_read(bp, phy,
10599 MDIO_REG_GPHY_SHADOW,
10600 &temp);
10601 temp &= 0xff00;
10602
10603 DP(NETIF_MSG_LINK, "54618x set link led (mode=%x)\n", mode);
10604 switch (mode) {
10605 case LED_MODE_FRONT_PANEL_OFF:
10606 case LED_MODE_OFF:
10607 temp |= 0x00ee;
10608 break;
10609 case LED_MODE_OPER:
10610 temp |= 0x0001;
10611 break;
10612 case LED_MODE_ON:
10613 temp |= 0x00ff;
10614 break;
10615 default:
10616 break;
10617 }
10618 bnx2x_cl22_write(bp, phy,
10619 MDIO_REG_GPHY_SHADOW,
10620 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10621 return;
10622 }
10623
10624
10625 static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy,
10626 struct link_params *params)
10627 {
10628 struct bnx2x *bp = params->bp;
10629 u32 cfg_pin;
10630 u8 port;
10631
10632 /*
10633 * In case of no EPIO routed to reset the GPHY, put it
10634 * in low power mode.
10635 */
10636 bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800);
10637 /*
10638 * This works with E3 only, no need to check the chip
10639 * before determining the port.
10640 */
10641 port = params->port;
10642 cfg_pin = (REG_RD(bp, params->shmem_base +
10643 offsetof(struct shmem_region,
10644 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10645 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10646 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10647
10648 /* Drive pin low to put GPHY in reset. */
10649 bnx2x_set_cfg_pin(bp, cfg_pin, 0);
10650 }
10651
10652 static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy,
10653 struct link_params *params,
10654 struct link_vars *vars)
10655 {
10656 struct bnx2x *bp = params->bp;
10657 u16 val;
10658 u8 link_up = 0;
10659 u16 legacy_status, legacy_speed;
10660
10661 /* Get speed operation status */
10662 bnx2x_cl22_read(bp, phy,
10663 0x19,
10664 &legacy_status);
10665 DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status);
10666
10667 /* Read status to clear the PHY interrupt. */
10668 bnx2x_cl22_read(bp, phy,
10669 MDIO_REG_INTR_STATUS,
10670 &val);
10671
10672 link_up = ((legacy_status & (1<<2)) == (1<<2));
10673
10674 if (link_up) {
10675 legacy_speed = (legacy_status & (7<<8));
10676 if (legacy_speed == (7<<8)) {
10677 vars->line_speed = SPEED_1000;
10678 vars->duplex = DUPLEX_FULL;
10679 } else if (legacy_speed == (6<<8)) {
10680 vars->line_speed = SPEED_1000;
10681 vars->duplex = DUPLEX_HALF;
10682 } else if (legacy_speed == (5<<8)) {
10683 vars->line_speed = SPEED_100;
10684 vars->duplex = DUPLEX_FULL;
10685 }
10686 /* Omitting 100Base-T4 for now */
10687 else if (legacy_speed == (3<<8)) {
10688 vars->line_speed = SPEED_100;
10689 vars->duplex = DUPLEX_HALF;
10690 } else if (legacy_speed == (2<<8)) {
10691 vars->line_speed = SPEED_10;
10692 vars->duplex = DUPLEX_FULL;
10693 } else if (legacy_speed == (1<<8)) {
10694 vars->line_speed = SPEED_10;
10695 vars->duplex = DUPLEX_HALF;
10696 } else /* Should not happen */
10697 vars->line_speed = 0;
10698
10699 DP(NETIF_MSG_LINK,
10700 "Link is up in %dMbps, is_duplex_full= %d\n",
10701 vars->line_speed,
10702 (vars->duplex == DUPLEX_FULL));
10703
10704 /* Check legacy speed AN resolution */
10705 bnx2x_cl22_read(bp, phy,
10706 0x01,
10707 &val);
10708 if (val & (1<<5))
10709 vars->link_status |=
10710 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10711 bnx2x_cl22_read(bp, phy,
10712 0x06,
10713 &val);
10714 if ((val & (1<<0)) == 0)
10715 vars->link_status |=
10716 LINK_STATUS_PARALLEL_DETECTION_USED;
10717
10718 DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n",
10719 vars->line_speed);
10720
10721 /* Report whether EEE is resolved. */
10722 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_PHYID_LSB, &val);
10723 if (val == MDIO_REG_GPHY_ID_54618SE) {
10724 if (vars->link_status &
10725 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
10726 val = 0;
10727 else {
10728 bnx2x_cl22_write(bp, phy,
10729 MDIO_REG_GPHY_CL45_ADDR_REG,
10730 MDIO_AN_DEVAD);
10731 bnx2x_cl22_write(bp, phy,
10732 MDIO_REG_GPHY_CL45_DATA_REG,
10733 MDIO_REG_GPHY_EEE_RESOLVED);
10734 bnx2x_cl22_write(bp, phy,
10735 MDIO_REG_GPHY_CL45_ADDR_REG,
10736 (0x1 << 14) | MDIO_AN_DEVAD);
10737 bnx2x_cl22_read(bp, phy,
10738 MDIO_REG_GPHY_CL45_DATA_REG,
10739 &val);
10740 }
10741 DP(NETIF_MSG_LINK, "EEE resolution: 0x%x\n", val);
10742 }
10743
10744 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10745
10746 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
10747 /* report LP advertised speeds */
10748 bnx2x_cl22_read(bp, phy, 0x5, &val);
10749
10750 if (val & (1<<5))
10751 vars->link_status |=
10752 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
10753 if (val & (1<<6))
10754 vars->link_status |=
10755 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
10756 if (val & (1<<7))
10757 vars->link_status |=
10758 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
10759 if (val & (1<<8))
10760 vars->link_status |=
10761 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
10762 if (val & (1<<9))
10763 vars->link_status |=
10764 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
10765
10766 bnx2x_cl22_read(bp, phy, 0xa, &val);
10767 if (val & (1<<10))
10768 vars->link_status |=
10769 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
10770 if (val & (1<<11))
10771 vars->link_status |=
10772 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
10773 }
10774 }
10775 return link_up;
10776 }
10777
10778 static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy,
10779 struct link_params *params)
10780 {
10781 struct bnx2x *bp = params->bp;
10782 u16 val;
10783 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10784
10785 DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n");
10786
10787 /* Enable master/slave manual mmode and set to master */
10788 /* mii write 9 [bits set 11 12] */
10789 bnx2x_cl22_write(bp, phy, 0x09, 3<<11);
10790
10791 /* forced 1G and disable autoneg */
10792 /* set val [mii read 0] */
10793 /* set val [expr $val & [bits clear 6 12 13]] */
10794 /* set val [expr $val | [bits set 6 8]] */
10795 /* mii write 0 $val */
10796 bnx2x_cl22_read(bp, phy, 0x00, &val);
10797 val &= ~((1<<6) | (1<<12) | (1<<13));
10798 val |= (1<<6) | (1<<8);
10799 bnx2x_cl22_write(bp, phy, 0x00, val);
10800
10801 /* Set external loopback and Tx using 6dB coding */
10802 /* mii write 0x18 7 */
10803 /* set val [mii read 0x18] */
10804 /* mii write 0x18 [expr $val | [bits set 10 15]] */
10805 bnx2x_cl22_write(bp, phy, 0x18, 7);
10806 bnx2x_cl22_read(bp, phy, 0x18, &val);
10807 bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15));
10808
10809 /* This register opens the gate for the UMAC despite its name */
10810 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
10811
10812 /*
10813 * Maximum Frame Length (RW). Defines a 14-Bit maximum frame
10814 * length used by the MAC receive logic to check frames.
10815 */
10816 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
10817 }
10818
10819 /******************************************************************/
10820 /* SFX7101 PHY SECTION */
10821 /******************************************************************/
10822 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
10823 struct link_params *params)
10824 {
10825 struct bnx2x *bp = params->bp;
10826 /* SFX7101_XGXS_TEST1 */
10827 bnx2x_cl45_write(bp, phy,
10828 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
10829 }
10830
10831 static int bnx2x_7101_config_init(struct bnx2x_phy *phy,
10832 struct link_params *params,
10833 struct link_vars *vars)
10834 {
10835 u16 fw_ver1, fw_ver2, val;
10836 struct bnx2x *bp = params->bp;
10837 DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
10838
10839 /* Restore normal power mode*/
10840 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
10841 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
10842 /* HW reset */
10843 bnx2x_ext_phy_hw_reset(bp, params->port);
10844 bnx2x_wait_reset_complete(bp, phy, params);
10845
10846 bnx2x_cl45_write(bp, phy,
10847 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
10848 DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
10849 bnx2x_cl45_write(bp, phy,
10850 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
10851
10852 bnx2x_ext_phy_set_pause(params, phy, vars);
10853 /* Restart autoneg */
10854 bnx2x_cl45_read(bp, phy,
10855 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
10856 val |= 0x200;
10857 bnx2x_cl45_write(bp, phy,
10858 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
10859
10860 /* Save spirom version */
10861 bnx2x_cl45_read(bp, phy,
10862 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
10863
10864 bnx2x_cl45_read(bp, phy,
10865 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
10866 bnx2x_save_spirom_version(bp, params->port,
10867 (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
10868 return 0;
10869 }
10870
10871 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
10872 struct link_params *params,
10873 struct link_vars *vars)
10874 {
10875 struct bnx2x *bp = params->bp;
10876 u8 link_up;
10877 u16 val1, val2;
10878 bnx2x_cl45_read(bp, phy,
10879 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
10880 bnx2x_cl45_read(bp, phy,
10881 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
10882 DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
10883 val2, val1);
10884 bnx2x_cl45_read(bp, phy,
10885 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
10886 bnx2x_cl45_read(bp, phy,
10887 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
10888 DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
10889 val2, val1);
10890 link_up = ((val1 & 4) == 4);
10891 /* if link is up print the AN outcome of the SFX7101 PHY */
10892 if (link_up) {
10893 bnx2x_cl45_read(bp, phy,
10894 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
10895 &val2);
10896 vars->line_speed = SPEED_10000;
10897 vars->duplex = DUPLEX_FULL;
10898 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
10899 val2, (val2 & (1<<14)));
10900 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
10901 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10902
10903 /* read LP advertised speeds */
10904 if (val2 & (1<<11))
10905 vars->link_status |=
10906 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
10907 }
10908 return link_up;
10909 }
10910
10911 static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
10912 {
10913 if (*len < 5)
10914 return -EINVAL;
10915 str[0] = (spirom_ver & 0xFF);
10916 str[1] = (spirom_ver & 0xFF00) >> 8;
10917 str[2] = (spirom_ver & 0xFF0000) >> 16;
10918 str[3] = (spirom_ver & 0xFF000000) >> 24;
10919 str[4] = '\0';
10920 *len -= 5;
10921 return 0;
10922 }
10923
10924 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
10925 {
10926 u16 val, cnt;
10927
10928 bnx2x_cl45_read(bp, phy,
10929 MDIO_PMA_DEVAD,
10930 MDIO_PMA_REG_7101_RESET, &val);
10931
10932 for (cnt = 0; cnt < 10; cnt++) {
10933 msleep(50);
10934 /* Writes a self-clearing reset */
10935 bnx2x_cl45_write(bp, phy,
10936 MDIO_PMA_DEVAD,
10937 MDIO_PMA_REG_7101_RESET,
10938 (val | (1<<15)));
10939 /* Wait for clear */
10940 bnx2x_cl45_read(bp, phy,
10941 MDIO_PMA_DEVAD,
10942 MDIO_PMA_REG_7101_RESET, &val);
10943
10944 if ((val & (1<<15)) == 0)
10945 break;
10946 }
10947 }
10948
10949 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
10950 struct link_params *params) {
10951 /* Low power mode is controlled by GPIO 2 */
10952 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
10953 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
10954 /* The PHY reset is controlled by GPIO 1 */
10955 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10956 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
10957 }
10958
10959 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
10960 struct link_params *params, u8 mode)
10961 {
10962 u16 val = 0;
10963 struct bnx2x *bp = params->bp;
10964 switch (mode) {
10965 case LED_MODE_FRONT_PANEL_OFF:
10966 case LED_MODE_OFF:
10967 val = 2;
10968 break;
10969 case LED_MODE_ON:
10970 val = 1;
10971 break;
10972 case LED_MODE_OPER:
10973 val = 0;
10974 break;
10975 }
10976 bnx2x_cl45_write(bp, phy,
10977 MDIO_PMA_DEVAD,
10978 MDIO_PMA_REG_7107_LINK_LED_CNTL,
10979 val);
10980 }
10981
10982 /******************************************************************/
10983 /* STATIC PHY DECLARATION */
10984 /******************************************************************/
10985
10986 static struct bnx2x_phy phy_null = {
10987 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
10988 .addr = 0,
10989 .def_md_devad = 0,
10990 .flags = FLAGS_INIT_XGXS_FIRST,
10991 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10992 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10993 .mdio_ctrl = 0,
10994 .supported = 0,
10995 .media_type = ETH_PHY_NOT_PRESENT,
10996 .ver_addr = 0,
10997 .req_flow_ctrl = 0,
10998 .req_line_speed = 0,
10999 .speed_cap_mask = 0,
11000 .req_duplex = 0,
11001 .rsrv = 0,
11002 .config_init = (config_init_t)NULL,
11003 .read_status = (read_status_t)NULL,
11004 .link_reset = (link_reset_t)NULL,
11005 .config_loopback = (config_loopback_t)NULL,
11006 .format_fw_ver = (format_fw_ver_t)NULL,
11007 .hw_reset = (hw_reset_t)NULL,
11008 .set_link_led = (set_link_led_t)NULL,
11009 .phy_specific_func = (phy_specific_func_t)NULL
11010 };
11011
11012 static struct bnx2x_phy phy_serdes = {
11013 .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
11014 .addr = 0xff,
11015 .def_md_devad = 0,
11016 .flags = 0,
11017 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11018 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11019 .mdio_ctrl = 0,
11020 .supported = (SUPPORTED_10baseT_Half |
11021 SUPPORTED_10baseT_Full |
11022 SUPPORTED_100baseT_Half |
11023 SUPPORTED_100baseT_Full |
11024 SUPPORTED_1000baseT_Full |
11025 SUPPORTED_2500baseX_Full |
11026 SUPPORTED_TP |
11027 SUPPORTED_Autoneg |
11028 SUPPORTED_Pause |
11029 SUPPORTED_Asym_Pause),
11030 .media_type = ETH_PHY_BASE_T,
11031 .ver_addr = 0,
11032 .req_flow_ctrl = 0,
11033 .req_line_speed = 0,
11034 .speed_cap_mask = 0,
11035 .req_duplex = 0,
11036 .rsrv = 0,
11037 .config_init = (config_init_t)bnx2x_xgxs_config_init,
11038 .read_status = (read_status_t)bnx2x_link_settings_status,
11039 .link_reset = (link_reset_t)bnx2x_int_link_reset,
11040 .config_loopback = (config_loopback_t)NULL,
11041 .format_fw_ver = (format_fw_ver_t)NULL,
11042 .hw_reset = (hw_reset_t)NULL,
11043 .set_link_led = (set_link_led_t)NULL,
11044 .phy_specific_func = (phy_specific_func_t)NULL
11045 };
11046
11047 static struct bnx2x_phy phy_xgxs = {
11048 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
11049 .addr = 0xff,
11050 .def_md_devad = 0,
11051 .flags = 0,
11052 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11053 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11054 .mdio_ctrl = 0,
11055 .supported = (SUPPORTED_10baseT_Half |
11056 SUPPORTED_10baseT_Full |
11057 SUPPORTED_100baseT_Half |
11058 SUPPORTED_100baseT_Full |
11059 SUPPORTED_1000baseT_Full |
11060 SUPPORTED_2500baseX_Full |
11061 SUPPORTED_10000baseT_Full |
11062 SUPPORTED_FIBRE |
11063 SUPPORTED_Autoneg |
11064 SUPPORTED_Pause |
11065 SUPPORTED_Asym_Pause),
11066 .media_type = ETH_PHY_CX4,
11067 .ver_addr = 0,
11068 .req_flow_ctrl = 0,
11069 .req_line_speed = 0,
11070 .speed_cap_mask = 0,
11071 .req_duplex = 0,
11072 .rsrv = 0,
11073 .config_init = (config_init_t)bnx2x_xgxs_config_init,
11074 .read_status = (read_status_t)bnx2x_link_settings_status,
11075 .link_reset = (link_reset_t)bnx2x_int_link_reset,
11076 .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
11077 .format_fw_ver = (format_fw_ver_t)NULL,
11078 .hw_reset = (hw_reset_t)NULL,
11079 .set_link_led = (set_link_led_t)NULL,
11080 .phy_specific_func = (phy_specific_func_t)NULL
11081 };
11082 static struct bnx2x_phy phy_warpcore = {
11083 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
11084 .addr = 0xff,
11085 .def_md_devad = 0,
11086 .flags = FLAGS_HW_LOCK_REQUIRED,
11087 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11088 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11089 .mdio_ctrl = 0,
11090 .supported = (SUPPORTED_10baseT_Half |
11091 SUPPORTED_10baseT_Full |
11092 SUPPORTED_100baseT_Half |
11093 SUPPORTED_100baseT_Full |
11094 SUPPORTED_1000baseT_Full |
11095 SUPPORTED_10000baseT_Full |
11096 SUPPORTED_20000baseKR2_Full |
11097 SUPPORTED_20000baseMLD2_Full |
11098 SUPPORTED_FIBRE |
11099 SUPPORTED_Autoneg |
11100 SUPPORTED_Pause |
11101 SUPPORTED_Asym_Pause),
11102 .media_type = ETH_PHY_UNSPECIFIED,
11103 .ver_addr = 0,
11104 .req_flow_ctrl = 0,
11105 .req_line_speed = 0,
11106 .speed_cap_mask = 0,
11107 /* req_duplex = */0,
11108 /* rsrv = */0,
11109 .config_init = (config_init_t)bnx2x_warpcore_config_init,
11110 .read_status = (read_status_t)bnx2x_warpcore_read_status,
11111 .link_reset = (link_reset_t)bnx2x_warpcore_link_reset,
11112 .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback,
11113 .format_fw_ver = (format_fw_ver_t)NULL,
11114 .hw_reset = (hw_reset_t)bnx2x_warpcore_hw_reset,
11115 .set_link_led = (set_link_led_t)NULL,
11116 .phy_specific_func = (phy_specific_func_t)NULL
11117 };
11118
11119
11120 static struct bnx2x_phy phy_7101 = {
11121 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
11122 .addr = 0xff,
11123 .def_md_devad = 0,
11124 .flags = FLAGS_FAN_FAILURE_DET_REQ,
11125 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11126 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11127 .mdio_ctrl = 0,
11128 .supported = (SUPPORTED_10000baseT_Full |
11129 SUPPORTED_TP |
11130 SUPPORTED_Autoneg |
11131 SUPPORTED_Pause |
11132 SUPPORTED_Asym_Pause),
11133 .media_type = ETH_PHY_BASE_T,
11134 .ver_addr = 0,
11135 .req_flow_ctrl = 0,
11136 .req_line_speed = 0,
11137 .speed_cap_mask = 0,
11138 .req_duplex = 0,
11139 .rsrv = 0,
11140 .config_init = (config_init_t)bnx2x_7101_config_init,
11141 .read_status = (read_status_t)bnx2x_7101_read_status,
11142 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
11143 .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
11144 .format_fw_ver = (format_fw_ver_t)bnx2x_7101_format_ver,
11145 .hw_reset = (hw_reset_t)bnx2x_7101_hw_reset,
11146 .set_link_led = (set_link_led_t)bnx2x_7101_set_link_led,
11147 .phy_specific_func = (phy_specific_func_t)NULL
11148 };
11149 static struct bnx2x_phy phy_8073 = {
11150 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
11151 .addr = 0xff,
11152 .def_md_devad = 0,
11153 .flags = FLAGS_HW_LOCK_REQUIRED,
11154 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11155 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11156 .mdio_ctrl = 0,
11157 .supported = (SUPPORTED_10000baseT_Full |
11158 SUPPORTED_2500baseX_Full |
11159 SUPPORTED_1000baseT_Full |
11160 SUPPORTED_FIBRE |
11161 SUPPORTED_Autoneg |
11162 SUPPORTED_Pause |
11163 SUPPORTED_Asym_Pause),
11164 .media_type = ETH_PHY_KR,
11165 .ver_addr = 0,
11166 .req_flow_ctrl = 0,
11167 .req_line_speed = 0,
11168 .speed_cap_mask = 0,
11169 .req_duplex = 0,
11170 .rsrv = 0,
11171 .config_init = (config_init_t)bnx2x_8073_config_init,
11172 .read_status = (read_status_t)bnx2x_8073_read_status,
11173 .link_reset = (link_reset_t)bnx2x_8073_link_reset,
11174 .config_loopback = (config_loopback_t)NULL,
11175 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
11176 .hw_reset = (hw_reset_t)NULL,
11177 .set_link_led = (set_link_led_t)NULL,
11178 .phy_specific_func = (phy_specific_func_t)NULL
11179 };
11180 static struct bnx2x_phy phy_8705 = {
11181 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
11182 .addr = 0xff,
11183 .def_md_devad = 0,
11184 .flags = FLAGS_INIT_XGXS_FIRST,
11185 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11186 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11187 .mdio_ctrl = 0,
11188 .supported = (SUPPORTED_10000baseT_Full |
11189 SUPPORTED_FIBRE |
11190 SUPPORTED_Pause |
11191 SUPPORTED_Asym_Pause),
11192 .media_type = ETH_PHY_XFP_FIBER,
11193 .ver_addr = 0,
11194 .req_flow_ctrl = 0,
11195 .req_line_speed = 0,
11196 .speed_cap_mask = 0,
11197 .req_duplex = 0,
11198 .rsrv = 0,
11199 .config_init = (config_init_t)bnx2x_8705_config_init,
11200 .read_status = (read_status_t)bnx2x_8705_read_status,
11201 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
11202 .config_loopback = (config_loopback_t)NULL,
11203 .format_fw_ver = (format_fw_ver_t)bnx2x_null_format_ver,
11204 .hw_reset = (hw_reset_t)NULL,
11205 .set_link_led = (set_link_led_t)NULL,
11206 .phy_specific_func = (phy_specific_func_t)NULL
11207 };
11208 static struct bnx2x_phy phy_8706 = {
11209 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
11210 .addr = 0xff,
11211 .def_md_devad = 0,
11212 .flags = FLAGS_INIT_XGXS_FIRST,
11213 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11214 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11215 .mdio_ctrl = 0,
11216 .supported = (SUPPORTED_10000baseT_Full |
11217 SUPPORTED_1000baseT_Full |
11218 SUPPORTED_FIBRE |
11219 SUPPORTED_Pause |
11220 SUPPORTED_Asym_Pause),
11221 .media_type = ETH_PHY_SFP_FIBER,
11222 .ver_addr = 0,
11223 .req_flow_ctrl = 0,
11224 .req_line_speed = 0,
11225 .speed_cap_mask = 0,
11226 .req_duplex = 0,
11227 .rsrv = 0,
11228 .config_init = (config_init_t)bnx2x_8706_config_init,
11229 .read_status = (read_status_t)bnx2x_8706_read_status,
11230 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
11231 .config_loopback = (config_loopback_t)NULL,
11232 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
11233 .hw_reset = (hw_reset_t)NULL,
11234 .set_link_led = (set_link_led_t)NULL,
11235 .phy_specific_func = (phy_specific_func_t)NULL
11236 };
11237
11238 static struct bnx2x_phy phy_8726 = {
11239 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
11240 .addr = 0xff,
11241 .def_md_devad = 0,
11242 .flags = (FLAGS_HW_LOCK_REQUIRED |
11243 FLAGS_INIT_XGXS_FIRST),
11244 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11245 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11246 .mdio_ctrl = 0,
11247 .supported = (SUPPORTED_10000baseT_Full |
11248 SUPPORTED_1000baseT_Full |
11249 SUPPORTED_Autoneg |
11250 SUPPORTED_FIBRE |
11251 SUPPORTED_Pause |
11252 SUPPORTED_Asym_Pause),
11253 .media_type = ETH_PHY_NOT_PRESENT,
11254 .ver_addr = 0,
11255 .req_flow_ctrl = 0,
11256 .req_line_speed = 0,
11257 .speed_cap_mask = 0,
11258 .req_duplex = 0,
11259 .rsrv = 0,
11260 .config_init = (config_init_t)bnx2x_8726_config_init,
11261 .read_status = (read_status_t)bnx2x_8726_read_status,
11262 .link_reset = (link_reset_t)bnx2x_8726_link_reset,
11263 .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
11264 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
11265 .hw_reset = (hw_reset_t)NULL,
11266 .set_link_led = (set_link_led_t)NULL,
11267 .phy_specific_func = (phy_specific_func_t)NULL
11268 };
11269
11270 static struct bnx2x_phy phy_8727 = {
11271 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
11272 .addr = 0xff,
11273 .def_md_devad = 0,
11274 .flags = FLAGS_FAN_FAILURE_DET_REQ,
11275 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11276 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11277 .mdio_ctrl = 0,
11278 .supported = (SUPPORTED_10000baseT_Full |
11279 SUPPORTED_1000baseT_Full |
11280 SUPPORTED_FIBRE |
11281 SUPPORTED_Pause |
11282 SUPPORTED_Asym_Pause),
11283 .media_type = ETH_PHY_NOT_PRESENT,
11284 .ver_addr = 0,
11285 .req_flow_ctrl = 0,
11286 .req_line_speed = 0,
11287 .speed_cap_mask = 0,
11288 .req_duplex = 0,
11289 .rsrv = 0,
11290 .config_init = (config_init_t)bnx2x_8727_config_init,
11291 .read_status = (read_status_t)bnx2x_8727_read_status,
11292 .link_reset = (link_reset_t)bnx2x_8727_link_reset,
11293 .config_loopback = (config_loopback_t)NULL,
11294 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
11295 .hw_reset = (hw_reset_t)bnx2x_8727_hw_reset,
11296 .set_link_led = (set_link_led_t)bnx2x_8727_set_link_led,
11297 .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
11298 };
11299 static struct bnx2x_phy phy_8481 = {
11300 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
11301 .addr = 0xff,
11302 .def_md_devad = 0,
11303 .flags = FLAGS_FAN_FAILURE_DET_REQ |
11304 FLAGS_REARM_LATCH_SIGNAL,
11305 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11306 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11307 .mdio_ctrl = 0,
11308 .supported = (SUPPORTED_10baseT_Half |
11309 SUPPORTED_10baseT_Full |
11310 SUPPORTED_100baseT_Half |
11311 SUPPORTED_100baseT_Full |
11312 SUPPORTED_1000baseT_Full |
11313 SUPPORTED_10000baseT_Full |
11314 SUPPORTED_TP |
11315 SUPPORTED_Autoneg |
11316 SUPPORTED_Pause |
11317 SUPPORTED_Asym_Pause),
11318 .media_type = ETH_PHY_BASE_T,
11319 .ver_addr = 0,
11320 .req_flow_ctrl = 0,
11321 .req_line_speed = 0,
11322 .speed_cap_mask = 0,
11323 .req_duplex = 0,
11324 .rsrv = 0,
11325 .config_init = (config_init_t)bnx2x_8481_config_init,
11326 .read_status = (read_status_t)bnx2x_848xx_read_status,
11327 .link_reset = (link_reset_t)bnx2x_8481_link_reset,
11328 .config_loopback = (config_loopback_t)NULL,
11329 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
11330 .hw_reset = (hw_reset_t)bnx2x_8481_hw_reset,
11331 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
11332 .phy_specific_func = (phy_specific_func_t)NULL
11333 };
11334
11335 static struct bnx2x_phy phy_84823 = {
11336 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
11337 .addr = 0xff,
11338 .def_md_devad = 0,
11339 .flags = FLAGS_FAN_FAILURE_DET_REQ |
11340 FLAGS_REARM_LATCH_SIGNAL,
11341 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11342 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11343 .mdio_ctrl = 0,
11344 .supported = (SUPPORTED_10baseT_Half |
11345 SUPPORTED_10baseT_Full |
11346 SUPPORTED_100baseT_Half |
11347 SUPPORTED_100baseT_Full |
11348 SUPPORTED_1000baseT_Full |
11349 SUPPORTED_10000baseT_Full |
11350 SUPPORTED_TP |
11351 SUPPORTED_Autoneg |
11352 SUPPORTED_Pause |
11353 SUPPORTED_Asym_Pause),
11354 .media_type = ETH_PHY_BASE_T,
11355 .ver_addr = 0,
11356 .req_flow_ctrl = 0,
11357 .req_line_speed = 0,
11358 .speed_cap_mask = 0,
11359 .req_duplex = 0,
11360 .rsrv = 0,
11361 .config_init = (config_init_t)bnx2x_848x3_config_init,
11362 .read_status = (read_status_t)bnx2x_848xx_read_status,
11363 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
11364 .config_loopback = (config_loopback_t)NULL,
11365 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
11366 .hw_reset = (hw_reset_t)NULL,
11367 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
11368 .phy_specific_func = (phy_specific_func_t)NULL
11369 };
11370
11371 static struct bnx2x_phy phy_84833 = {
11372 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
11373 .addr = 0xff,
11374 .def_md_devad = 0,
11375 .flags = FLAGS_FAN_FAILURE_DET_REQ |
11376 FLAGS_REARM_LATCH_SIGNAL,
11377 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11378 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11379 .mdio_ctrl = 0,
11380 .supported = (SUPPORTED_100baseT_Half |
11381 SUPPORTED_100baseT_Full |
11382 SUPPORTED_1000baseT_Full |
11383 SUPPORTED_10000baseT_Full |
11384 SUPPORTED_TP |
11385 SUPPORTED_Autoneg |
11386 SUPPORTED_Pause |
11387 SUPPORTED_Asym_Pause),
11388 .media_type = ETH_PHY_BASE_T,
11389 .ver_addr = 0,
11390 .req_flow_ctrl = 0,
11391 .req_line_speed = 0,
11392 .speed_cap_mask = 0,
11393 .req_duplex = 0,
11394 .rsrv = 0,
11395 .config_init = (config_init_t)bnx2x_848x3_config_init,
11396 .read_status = (read_status_t)bnx2x_848xx_read_status,
11397 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
11398 .config_loopback = (config_loopback_t)NULL,
11399 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
11400 .hw_reset = (hw_reset_t)bnx2x_84833_hw_reset_phy,
11401 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
11402 .phy_specific_func = (phy_specific_func_t)NULL
11403 };
11404
11405 static struct bnx2x_phy phy_54618se = {
11406 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE,
11407 .addr = 0xff,
11408 .def_md_devad = 0,
11409 .flags = FLAGS_INIT_XGXS_FIRST,
11410 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11411 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11412 .mdio_ctrl = 0,
11413 .supported = (SUPPORTED_10baseT_Half |
11414 SUPPORTED_10baseT_Full |
11415 SUPPORTED_100baseT_Half |
11416 SUPPORTED_100baseT_Full |
11417 SUPPORTED_1000baseT_Full |
11418 SUPPORTED_TP |
11419 SUPPORTED_Autoneg |
11420 SUPPORTED_Pause |
11421 SUPPORTED_Asym_Pause),
11422 .media_type = ETH_PHY_BASE_T,
11423 .ver_addr = 0,
11424 .req_flow_ctrl = 0,
11425 .req_line_speed = 0,
11426 .speed_cap_mask = 0,
11427 /* req_duplex = */0,
11428 /* rsrv = */0,
11429 .config_init = (config_init_t)bnx2x_54618se_config_init,
11430 .read_status = (read_status_t)bnx2x_54618se_read_status,
11431 .link_reset = (link_reset_t)bnx2x_54618se_link_reset,
11432 .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback,
11433 .format_fw_ver = (format_fw_ver_t)NULL,
11434 .hw_reset = (hw_reset_t)NULL,
11435 .set_link_led = (set_link_led_t)bnx2x_5461x_set_link_led,
11436 .phy_specific_func = (phy_specific_func_t)NULL
11437 };
11438 /*****************************************************************/
11439 /* */
11440 /* Populate the phy according. Main function: bnx2x_populate_phy */
11441 /* */
11442 /*****************************************************************/
11443
11444 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
11445 struct bnx2x_phy *phy, u8 port,
11446 u8 phy_index)
11447 {
11448 /* Get the 4 lanes xgxs config rx and tx */
11449 u32 rx = 0, tx = 0, i;
11450 for (i = 0; i < 2; i++) {
11451 /*
11452 * INT_PHY and EXT_PHY1 share the same value location in the
11453 * shmem. When num_phys is greater than 1, than this value
11454 * applies only to EXT_PHY1
11455 */
11456 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
11457 rx = REG_RD(bp, shmem_base +
11458 offsetof(struct shmem_region,
11459 dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
11460
11461 tx = REG_RD(bp, shmem_base +
11462 offsetof(struct shmem_region,
11463 dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
11464 } else {
11465 rx = REG_RD(bp, shmem_base +
11466 offsetof(struct shmem_region,
11467 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11468
11469 tx = REG_RD(bp, shmem_base +
11470 offsetof(struct shmem_region,
11471 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11472 }
11473
11474 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
11475 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
11476
11477 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
11478 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
11479 }
11480 }
11481
11482 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
11483 u8 phy_index, u8 port)
11484 {
11485 u32 ext_phy_config = 0;
11486 switch (phy_index) {
11487 case EXT_PHY1:
11488 ext_phy_config = REG_RD(bp, shmem_base +
11489 offsetof(struct shmem_region,
11490 dev_info.port_hw_config[port].external_phy_config));
11491 break;
11492 case EXT_PHY2:
11493 ext_phy_config = REG_RD(bp, shmem_base +
11494 offsetof(struct shmem_region,
11495 dev_info.port_hw_config[port].external_phy_config2));
11496 break;
11497 default:
11498 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
11499 return -EINVAL;
11500 }
11501
11502 return ext_phy_config;
11503 }
11504 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
11505 struct bnx2x_phy *phy)
11506 {
11507 u32 phy_addr;
11508 u32 chip_id;
11509 u32 switch_cfg = (REG_RD(bp, shmem_base +
11510 offsetof(struct shmem_region,
11511 dev_info.port_feature_config[port].link_config)) &
11512 PORT_FEATURE_CONNECTED_SWITCH_MASK);
11513 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
11514 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
11515
11516 DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id);
11517 if (USES_WARPCORE(bp)) {
11518 u32 serdes_net_if;
11519 phy_addr = REG_RD(bp,
11520 MISC_REG_WC0_CTRL_PHY_ADDR);
11521 *phy = phy_warpcore;
11522 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
11523 phy->flags |= FLAGS_4_PORT_MODE;
11524 else
11525 phy->flags &= ~FLAGS_4_PORT_MODE;
11526 /* Check Dual mode */
11527 serdes_net_if = (REG_RD(bp, shmem_base +
11528 offsetof(struct shmem_region, dev_info.
11529 port_hw_config[port].default_cfg)) &
11530 PORT_HW_CFG_NET_SERDES_IF_MASK);
11531 /*
11532 * Set the appropriate supported and flags indications per
11533 * interface type of the chip
11534 */
11535 switch (serdes_net_if) {
11536 case PORT_HW_CFG_NET_SERDES_IF_SGMII:
11537 phy->supported &= (SUPPORTED_10baseT_Half |
11538 SUPPORTED_10baseT_Full |
11539 SUPPORTED_100baseT_Half |
11540 SUPPORTED_100baseT_Full |
11541 SUPPORTED_1000baseT_Full |
11542 SUPPORTED_FIBRE |
11543 SUPPORTED_Autoneg |
11544 SUPPORTED_Pause |
11545 SUPPORTED_Asym_Pause);
11546 phy->media_type = ETH_PHY_BASE_T;
11547 break;
11548 case PORT_HW_CFG_NET_SERDES_IF_XFI:
11549 phy->media_type = ETH_PHY_XFP_FIBER;
11550 break;
11551 case PORT_HW_CFG_NET_SERDES_IF_SFI:
11552 phy->supported &= (SUPPORTED_1000baseT_Full |
11553 SUPPORTED_10000baseT_Full |
11554 SUPPORTED_FIBRE |
11555 SUPPORTED_Pause |
11556 SUPPORTED_Asym_Pause);
11557 phy->media_type = ETH_PHY_SFP_FIBER;
11558 break;
11559 case PORT_HW_CFG_NET_SERDES_IF_KR:
11560 phy->media_type = ETH_PHY_KR;
11561 phy->supported &= (SUPPORTED_1000baseT_Full |
11562 SUPPORTED_10000baseT_Full |
11563 SUPPORTED_FIBRE |
11564 SUPPORTED_Autoneg |
11565 SUPPORTED_Pause |
11566 SUPPORTED_Asym_Pause);
11567 break;
11568 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
11569 phy->media_type = ETH_PHY_KR;
11570 phy->flags |= FLAGS_WC_DUAL_MODE;
11571 phy->supported &= (SUPPORTED_20000baseMLD2_Full |
11572 SUPPORTED_FIBRE |
11573 SUPPORTED_Pause |
11574 SUPPORTED_Asym_Pause);
11575 break;
11576 case PORT_HW_CFG_NET_SERDES_IF_KR2:
11577 phy->media_type = ETH_PHY_KR;
11578 phy->flags |= FLAGS_WC_DUAL_MODE;
11579 phy->supported &= (SUPPORTED_20000baseKR2_Full |
11580 SUPPORTED_FIBRE |
11581 SUPPORTED_Pause |
11582 SUPPORTED_Asym_Pause);
11583 break;
11584 default:
11585 DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n",
11586 serdes_net_if);
11587 break;
11588 }
11589
11590 /*
11591 * Enable MDC/MDIO work-around for E3 A0 since free running MDC
11592 * was not set as expected. For B0, ECO will be enabled so there
11593 * won't be an issue there
11594 */
11595 if (CHIP_REV(bp) == CHIP_REV_Ax)
11596 phy->flags |= FLAGS_MDC_MDIO_WA;
11597 else
11598 phy->flags |= FLAGS_MDC_MDIO_WA_B0;
11599 } else {
11600 switch (switch_cfg) {
11601 case SWITCH_CFG_1G:
11602 phy_addr = REG_RD(bp,
11603 NIG_REG_SERDES0_CTRL_PHY_ADDR +
11604 port * 0x10);
11605 *phy = phy_serdes;
11606 break;
11607 case SWITCH_CFG_10G:
11608 phy_addr = REG_RD(bp,
11609 NIG_REG_XGXS0_CTRL_PHY_ADDR +
11610 port * 0x18);
11611 *phy = phy_xgxs;
11612 break;
11613 default:
11614 DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
11615 return -EINVAL;
11616 }
11617 }
11618 phy->addr = (u8)phy_addr;
11619 phy->mdio_ctrl = bnx2x_get_emac_base(bp,
11620 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
11621 port);
11622 if (CHIP_IS_E2(bp))
11623 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
11624 else
11625 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
11626
11627 DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
11628 port, phy->addr, phy->mdio_ctrl);
11629
11630 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
11631 return 0;
11632 }
11633
11634 static int bnx2x_populate_ext_phy(struct bnx2x *bp,
11635 u8 phy_index,
11636 u32 shmem_base,
11637 u32 shmem2_base,
11638 u8 port,
11639 struct bnx2x_phy *phy)
11640 {
11641 u32 ext_phy_config, phy_type, config2;
11642 u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
11643 ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
11644 phy_index, port);
11645 phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11646 /* Select the phy type */
11647 switch (phy_type) {
11648 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
11649 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
11650 *phy = phy_8073;
11651 break;
11652 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
11653 *phy = phy_8705;
11654 break;
11655 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
11656 *phy = phy_8706;
11657 break;
11658 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
11659 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11660 *phy = phy_8726;
11661 break;
11662 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
11663 /* BCM8727_NOC => BCM8727 no over current */
11664 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11665 *phy = phy_8727;
11666 phy->flags |= FLAGS_NOC;
11667 break;
11668 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
11669 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
11670 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11671 *phy = phy_8727;
11672 break;
11673 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
11674 *phy = phy_8481;
11675 break;
11676 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
11677 *phy = phy_84823;
11678 break;
11679 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
11680 *phy = phy_84833;
11681 break;
11682 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616:
11683 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE:
11684 *phy = phy_54618se;
11685 break;
11686 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
11687 *phy = phy_7101;
11688 break;
11689 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
11690 *phy = phy_null;
11691 return -EINVAL;
11692 default:
11693 *phy = phy_null;
11694 /* In case external PHY wasn't found */
11695 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
11696 (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11697 return -EINVAL;
11698 return 0;
11699 }
11700
11701 phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
11702 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
11703
11704 /*
11705 * The shmem address of the phy version is located on different
11706 * structures. In case this structure is too old, do not set
11707 * the address
11708 */
11709 config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
11710 dev_info.shared_hw_config.config2));
11711 if (phy_index == EXT_PHY1) {
11712 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
11713 port_mb[port].ext_phy_fw_version);
11714
11715 /* Check specific mdc mdio settings */
11716 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
11717 mdc_mdio_access = config2 &
11718 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
11719 } else {
11720 u32 size = REG_RD(bp, shmem2_base);
11721
11722 if (size >
11723 offsetof(struct shmem2_region, ext_phy_fw_version2)) {
11724 phy->ver_addr = shmem2_base +
11725 offsetof(struct shmem2_region,
11726 ext_phy_fw_version2[port]);
11727 }
11728 /* Check specific mdc mdio settings */
11729 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
11730 mdc_mdio_access = (config2 &
11731 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
11732 (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
11733 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
11734 }
11735 phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
11736
11737 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
11738 (phy->ver_addr)) {
11739 /*
11740 * Remove 100Mb link supported for BCM84833 when phy fw
11741 * version lower than or equal to 1.39
11742 */
11743 u32 raw_ver = REG_RD(bp, phy->ver_addr);
11744 if (((raw_ver & 0x7F) <= 39) &&
11745 (((raw_ver & 0xF80) >> 7) <= 1))
11746 phy->supported &= ~(SUPPORTED_100baseT_Half |
11747 SUPPORTED_100baseT_Full);
11748 }
11749
11750 /*
11751 * In case mdc/mdio_access of the external phy is different than the
11752 * mdc/mdio access of the XGXS, a HW lock must be taken in each access
11753 * to prevent one port interfere with another port's CL45 operations.
11754 */
11755 if (mdc_mdio_access != SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH)
11756 phy->flags |= FLAGS_HW_LOCK_REQUIRED;
11757 DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
11758 phy_type, port, phy_index);
11759 DP(NETIF_MSG_LINK, " addr=0x%x, mdio_ctl=0x%x\n",
11760 phy->addr, phy->mdio_ctrl);
11761 return 0;
11762 }
11763
11764 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
11765 u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
11766 {
11767 int status = 0;
11768 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
11769 if (phy_index == INT_PHY)
11770 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
11771 status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
11772 port, phy);
11773 return status;
11774 }
11775
11776 static void bnx2x_phy_def_cfg(struct link_params *params,
11777 struct bnx2x_phy *phy,
11778 u8 phy_index)
11779 {
11780 struct bnx2x *bp = params->bp;
11781 u32 link_config;
11782 /* Populate the default phy configuration for MF mode */
11783 if (phy_index == EXT_PHY2) {
11784 link_config = REG_RD(bp, params->shmem_base +
11785 offsetof(struct shmem_region, dev_info.
11786 port_feature_config[params->port].link_config2));
11787 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
11788 offsetof(struct shmem_region,
11789 dev_info.
11790 port_hw_config[params->port].speed_capability_mask2));
11791 } else {
11792 link_config = REG_RD(bp, params->shmem_base +
11793 offsetof(struct shmem_region, dev_info.
11794 port_feature_config[params->port].link_config));
11795 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
11796 offsetof(struct shmem_region,
11797 dev_info.
11798 port_hw_config[params->port].speed_capability_mask));
11799 }
11800 DP(NETIF_MSG_LINK,
11801 "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n",
11802 phy_index, link_config, phy->speed_cap_mask);
11803
11804 phy->req_duplex = DUPLEX_FULL;
11805 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
11806 case PORT_FEATURE_LINK_SPEED_10M_HALF:
11807 phy->req_duplex = DUPLEX_HALF;
11808 case PORT_FEATURE_LINK_SPEED_10M_FULL:
11809 phy->req_line_speed = SPEED_10;
11810 break;
11811 case PORT_FEATURE_LINK_SPEED_100M_HALF:
11812 phy->req_duplex = DUPLEX_HALF;
11813 case PORT_FEATURE_LINK_SPEED_100M_FULL:
11814 phy->req_line_speed = SPEED_100;
11815 break;
11816 case PORT_FEATURE_LINK_SPEED_1G:
11817 phy->req_line_speed = SPEED_1000;
11818 break;
11819 case PORT_FEATURE_LINK_SPEED_2_5G:
11820 phy->req_line_speed = SPEED_2500;
11821 break;
11822 case PORT_FEATURE_LINK_SPEED_10G_CX4:
11823 phy->req_line_speed = SPEED_10000;
11824 break;
11825 default:
11826 phy->req_line_speed = SPEED_AUTO_NEG;
11827 break;
11828 }
11829
11830 switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) {
11831 case PORT_FEATURE_FLOW_CONTROL_AUTO:
11832 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
11833 break;
11834 case PORT_FEATURE_FLOW_CONTROL_TX:
11835 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
11836 break;
11837 case PORT_FEATURE_FLOW_CONTROL_RX:
11838 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
11839 break;
11840 case PORT_FEATURE_FLOW_CONTROL_BOTH:
11841 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
11842 break;
11843 default:
11844 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11845 break;
11846 }
11847 }
11848
11849 u32 bnx2x_phy_selection(struct link_params *params)
11850 {
11851 u32 phy_config_swapped, prio_cfg;
11852 u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
11853
11854 phy_config_swapped = params->multi_phy_config &
11855 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
11856
11857 prio_cfg = params->multi_phy_config &
11858 PORT_HW_CFG_PHY_SELECTION_MASK;
11859
11860 if (phy_config_swapped) {
11861 switch (prio_cfg) {
11862 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
11863 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
11864 break;
11865 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
11866 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
11867 break;
11868 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
11869 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
11870 break;
11871 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
11872 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
11873 break;
11874 }
11875 } else
11876 return_cfg = prio_cfg;
11877
11878 return return_cfg;
11879 }
11880
11881
11882 int bnx2x_phy_probe(struct link_params *params)
11883 {
11884 u8 phy_index, actual_phy_idx;
11885 u32 phy_config_swapped, sync_offset, media_types;
11886 struct bnx2x *bp = params->bp;
11887 struct bnx2x_phy *phy;
11888 params->num_phys = 0;
11889 DP(NETIF_MSG_LINK, "Begin phy probe\n");
11890 phy_config_swapped = params->multi_phy_config &
11891 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
11892
11893 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
11894 phy_index++) {
11895 actual_phy_idx = phy_index;
11896 if (phy_config_swapped) {
11897 if (phy_index == EXT_PHY1)
11898 actual_phy_idx = EXT_PHY2;
11899 else if (phy_index == EXT_PHY2)
11900 actual_phy_idx = EXT_PHY1;
11901 }
11902 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
11903 " actual_phy_idx %x\n", phy_config_swapped,
11904 phy_index, actual_phy_idx);
11905 phy = &params->phy[actual_phy_idx];
11906 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
11907 params->shmem2_base, params->port,
11908 phy) != 0) {
11909 params->num_phys = 0;
11910 DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
11911 phy_index);
11912 for (phy_index = INT_PHY;
11913 phy_index < MAX_PHYS;
11914 phy_index++)
11915 *phy = phy_null;
11916 return -EINVAL;
11917 }
11918 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
11919 break;
11920
11921 sync_offset = params->shmem_base +
11922 offsetof(struct shmem_region,
11923 dev_info.port_hw_config[params->port].media_type);
11924 media_types = REG_RD(bp, sync_offset);
11925
11926 /*
11927 * Update media type for non-PMF sync only for the first time
11928 * In case the media type changes afterwards, it will be updated
11929 * using the update_status function
11930 */
11931 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
11932 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
11933 actual_phy_idx))) == 0) {
11934 media_types |= ((phy->media_type &
11935 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
11936 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
11937 actual_phy_idx));
11938 }
11939 REG_WR(bp, sync_offset, media_types);
11940
11941 bnx2x_phy_def_cfg(params, phy, phy_index);
11942 params->num_phys++;
11943 }
11944
11945 DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
11946 return 0;
11947 }
11948
11949 void bnx2x_init_bmac_loopback(struct link_params *params,
11950 struct link_vars *vars)
11951 {
11952 struct bnx2x *bp = params->bp;
11953 vars->link_up = 1;
11954 vars->line_speed = SPEED_10000;
11955 vars->duplex = DUPLEX_FULL;
11956 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11957 vars->mac_type = MAC_TYPE_BMAC;
11958
11959 vars->phy_flags = PHY_XGXS_FLAG;
11960
11961 bnx2x_xgxs_deassert(params);
11962
11963 /* set bmac loopback */
11964 bnx2x_bmac_enable(params, vars, 1);
11965
11966 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11967 }
11968
11969 void bnx2x_init_emac_loopback(struct link_params *params,
11970 struct link_vars *vars)
11971 {
11972 struct bnx2x *bp = params->bp;
11973 vars->link_up = 1;
11974 vars->line_speed = SPEED_1000;
11975 vars->duplex = DUPLEX_FULL;
11976 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11977 vars->mac_type = MAC_TYPE_EMAC;
11978
11979 vars->phy_flags = PHY_XGXS_FLAG;
11980
11981 bnx2x_xgxs_deassert(params);
11982 /* set bmac loopback */
11983 bnx2x_emac_enable(params, vars, 1);
11984 bnx2x_emac_program(params, vars);
11985 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11986 }
11987
11988 void bnx2x_init_xmac_loopback(struct link_params *params,
11989 struct link_vars *vars)
11990 {
11991 struct bnx2x *bp = params->bp;
11992 vars->link_up = 1;
11993 if (!params->req_line_speed[0])
11994 vars->line_speed = SPEED_10000;
11995 else
11996 vars->line_speed = params->req_line_speed[0];
11997 vars->duplex = DUPLEX_FULL;
11998 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11999 vars->mac_type = MAC_TYPE_XMAC;
12000 vars->phy_flags = PHY_XGXS_FLAG;
12001 /*
12002 * Set WC to loopback mode since link is required to provide clock
12003 * to the XMAC in 20G mode
12004 */
12005 bnx2x_set_aer_mmd(params, &params->phy[0]);
12006 bnx2x_warpcore_reset_lane(bp, &params->phy[0], 0);
12007 params->phy[INT_PHY].config_loopback(
12008 &params->phy[INT_PHY],
12009 params);
12010
12011 bnx2x_xmac_enable(params, vars, 1);
12012 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12013 }
12014
12015 void bnx2x_init_umac_loopback(struct link_params *params,
12016 struct link_vars *vars)
12017 {
12018 struct bnx2x *bp = params->bp;
12019 vars->link_up = 1;
12020 vars->line_speed = SPEED_1000;
12021 vars->duplex = DUPLEX_FULL;
12022 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12023 vars->mac_type = MAC_TYPE_UMAC;
12024 vars->phy_flags = PHY_XGXS_FLAG;
12025 bnx2x_umac_enable(params, vars, 1);
12026
12027 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12028 }
12029
12030 void bnx2x_init_xgxs_loopback(struct link_params *params,
12031 struct link_vars *vars)
12032 {
12033 struct bnx2x *bp = params->bp;
12034 vars->link_up = 1;
12035 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12036 vars->duplex = DUPLEX_FULL;
12037 if (params->req_line_speed[0] == SPEED_1000)
12038 vars->line_speed = SPEED_1000;
12039 else
12040 vars->line_speed = SPEED_10000;
12041
12042 if (!USES_WARPCORE(bp))
12043 bnx2x_xgxs_deassert(params);
12044 bnx2x_link_initialize(params, vars);
12045
12046 if (params->req_line_speed[0] == SPEED_1000) {
12047 if (USES_WARPCORE(bp))
12048 bnx2x_umac_enable(params, vars, 0);
12049 else {
12050 bnx2x_emac_program(params, vars);
12051 bnx2x_emac_enable(params, vars, 0);
12052 }
12053 } else {
12054 if (USES_WARPCORE(bp))
12055 bnx2x_xmac_enable(params, vars, 0);
12056 else
12057 bnx2x_bmac_enable(params, vars, 0);
12058 }
12059
12060 if (params->loopback_mode == LOOPBACK_XGXS) {
12061 /* set 10G XGXS loopback */
12062 params->phy[INT_PHY].config_loopback(
12063 &params->phy[INT_PHY],
12064 params);
12065
12066 } else {
12067 /* set external phy loopback */
12068 u8 phy_index;
12069 for (phy_index = EXT_PHY1;
12070 phy_index < params->num_phys; phy_index++) {
12071 if (params->phy[phy_index].config_loopback)
12072 params->phy[phy_index].config_loopback(
12073 &params->phy[phy_index],
12074 params);
12075 }
12076 }
12077 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12078
12079 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
12080 }
12081
12082 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
12083 {
12084 struct bnx2x *bp = params->bp;
12085 DP(NETIF_MSG_LINK, "Phy Initialization started\n");
12086 DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
12087 params->req_line_speed[0], params->req_flow_ctrl[0]);
12088 DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
12089 params->req_line_speed[1], params->req_flow_ctrl[1]);
12090 vars->link_status = 0;
12091 vars->phy_link_up = 0;
12092 vars->link_up = 0;
12093 vars->line_speed = 0;
12094 vars->duplex = DUPLEX_FULL;
12095 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12096 vars->mac_type = MAC_TYPE_NONE;
12097 vars->phy_flags = 0;
12098
12099 /* disable attentions */
12100 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
12101 (NIG_MASK_XGXS0_LINK_STATUS |
12102 NIG_MASK_XGXS0_LINK10G |
12103 NIG_MASK_SERDES0_LINK_STATUS |
12104 NIG_MASK_MI_INT));
12105
12106 bnx2x_emac_init(params, vars);
12107
12108 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
12109 vars->link_status |= LINK_STATUS_PFC_ENABLED;
12110
12111 if (params->num_phys == 0) {
12112 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
12113 return -EINVAL;
12114 }
12115 set_phy_vars(params, vars);
12116
12117 DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
12118 switch (params->loopback_mode) {
12119 case LOOPBACK_BMAC:
12120 bnx2x_init_bmac_loopback(params, vars);
12121 break;
12122 case LOOPBACK_EMAC:
12123 bnx2x_init_emac_loopback(params, vars);
12124 break;
12125 case LOOPBACK_XMAC:
12126 bnx2x_init_xmac_loopback(params, vars);
12127 break;
12128 case LOOPBACK_UMAC:
12129 bnx2x_init_umac_loopback(params, vars);
12130 break;
12131 case LOOPBACK_XGXS:
12132 case LOOPBACK_EXT_PHY:
12133 bnx2x_init_xgxs_loopback(params, vars);
12134 break;
12135 default:
12136 if (!CHIP_IS_E3(bp)) {
12137 if (params->switch_cfg == SWITCH_CFG_10G)
12138 bnx2x_xgxs_deassert(params);
12139 else
12140 bnx2x_serdes_deassert(bp, params->port);
12141 }
12142 bnx2x_link_initialize(params, vars);
12143 msleep(30);
12144 bnx2x_link_int_enable(params);
12145 break;
12146 }
12147 return 0;
12148 }
12149
12150 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
12151 u8 reset_ext_phy)
12152 {
12153 struct bnx2x *bp = params->bp;
12154 u8 phy_index, port = params->port, clear_latch_ind = 0;
12155 DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
12156 /* disable attentions */
12157 vars->link_status = 0;
12158 bnx2x_update_mng(params, vars->link_status);
12159 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
12160 (NIG_MASK_XGXS0_LINK_STATUS |
12161 NIG_MASK_XGXS0_LINK10G |
12162 NIG_MASK_SERDES0_LINK_STATUS |
12163 NIG_MASK_MI_INT));
12164
12165 /* activate nig drain */
12166 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
12167
12168 /* disable nig egress interface */
12169 if (!CHIP_IS_E3(bp)) {
12170 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
12171 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
12172 }
12173
12174 /* Stop BigMac rx */
12175 if (!CHIP_IS_E3(bp))
12176 bnx2x_bmac_rx_disable(bp, port);
12177 else {
12178 bnx2x_xmac_disable(params);
12179 bnx2x_umac_disable(params);
12180 }
12181 /* disable emac */
12182 if (!CHIP_IS_E3(bp))
12183 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
12184
12185 msleep(10);
12186 /* The PHY reset is controlled by GPIO 1
12187 * Hold it as vars low
12188 */
12189 /* clear link led */
12190 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
12191
12192 if (reset_ext_phy) {
12193 bnx2x_set_mdio_clk(bp, params->chip_id, port);
12194 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
12195 phy_index++) {
12196 if (params->phy[phy_index].link_reset) {
12197 bnx2x_set_aer_mmd(params,
12198 &params->phy[phy_index]);
12199 params->phy[phy_index].link_reset(
12200 &params->phy[phy_index],
12201 params);
12202 }
12203 if (params->phy[phy_index].flags &
12204 FLAGS_REARM_LATCH_SIGNAL)
12205 clear_latch_ind = 1;
12206 }
12207 }
12208
12209 if (clear_latch_ind) {
12210 /* Clear latching indication */
12211 bnx2x_rearm_latch_signal(bp, port, 0);
12212 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
12213 1 << NIG_LATCH_BC_ENABLE_MI_INT);
12214 }
12215 if (params->phy[INT_PHY].link_reset)
12216 params->phy[INT_PHY].link_reset(
12217 &params->phy[INT_PHY], params);
12218
12219 /* disable nig ingress interface */
12220 if (!CHIP_IS_E3(bp)) {
12221 /* reset BigMac */
12222 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
12223 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
12224 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
12225 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
12226 } else {
12227 u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
12228 bnx2x_set_xumac_nig(params, 0, 0);
12229 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
12230 MISC_REGISTERS_RESET_REG_2_XMAC)
12231 REG_WR(bp, xmac_base + XMAC_REG_CTRL,
12232 XMAC_CTRL_REG_SOFT_RESET);
12233 }
12234 vars->link_up = 0;
12235 vars->phy_flags = 0;
12236 return 0;
12237 }
12238
12239 /****************************************************************************/
12240 /* Common function */
12241 /****************************************************************************/
12242 static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
12243 u32 shmem_base_path[],
12244 u32 shmem2_base_path[], u8 phy_index,
12245 u32 chip_id)
12246 {
12247 struct bnx2x_phy phy[PORT_MAX];
12248 struct bnx2x_phy *phy_blk[PORT_MAX];
12249 u16 val;
12250 s8 port = 0;
12251 s8 port_of_path = 0;
12252 u32 swap_val, swap_override;
12253 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
12254 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
12255 port ^= (swap_val && swap_override);
12256 bnx2x_ext_phy_hw_reset(bp, port);
12257 /* PART1 - Reset both phys */
12258 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12259 u32 shmem_base, shmem2_base;
12260 /* In E2, same phy is using for port0 of the two paths */
12261 if (CHIP_IS_E1x(bp)) {
12262 shmem_base = shmem_base_path[0];
12263 shmem2_base = shmem2_base_path[0];
12264 port_of_path = port;
12265 } else {
12266 shmem_base = shmem_base_path[port];
12267 shmem2_base = shmem2_base_path[port];
12268 port_of_path = 0;
12269 }
12270
12271 /* Extract the ext phy address for the port */
12272 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12273 port_of_path, &phy[port]) !=
12274 0) {
12275 DP(NETIF_MSG_LINK, "populate_phy failed\n");
12276 return -EINVAL;
12277 }
12278 /* disable attentions */
12279 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
12280 port_of_path*4,
12281 (NIG_MASK_XGXS0_LINK_STATUS |
12282 NIG_MASK_XGXS0_LINK10G |
12283 NIG_MASK_SERDES0_LINK_STATUS |
12284 NIG_MASK_MI_INT));
12285
12286 /* Need to take the phy out of low power mode in order
12287 to write to access its registers */
12288 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
12289 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
12290 port);
12291
12292 /* Reset the phy */
12293 bnx2x_cl45_write(bp, &phy[port],
12294 MDIO_PMA_DEVAD,
12295 MDIO_PMA_REG_CTRL,
12296 1<<15);
12297 }
12298
12299 /* Add delay of 150ms after reset */
12300 msleep(150);
12301
12302 if (phy[PORT_0].addr & 0x1) {
12303 phy_blk[PORT_0] = &(phy[PORT_1]);
12304 phy_blk[PORT_1] = &(phy[PORT_0]);
12305 } else {
12306 phy_blk[PORT_0] = &(phy[PORT_0]);
12307 phy_blk[PORT_1] = &(phy[PORT_1]);
12308 }
12309
12310 /* PART2 - Download firmware to both phys */
12311 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12312 if (CHIP_IS_E1x(bp))
12313 port_of_path = port;
12314 else
12315 port_of_path = 0;
12316
12317 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
12318 phy_blk[port]->addr);
12319 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
12320 port_of_path))
12321 return -EINVAL;
12322
12323 /* Only set bit 10 = 1 (Tx power down) */
12324 bnx2x_cl45_read(bp, phy_blk[port],
12325 MDIO_PMA_DEVAD,
12326 MDIO_PMA_REG_TX_POWER_DOWN, &val);
12327
12328 /* Phase1 of TX_POWER_DOWN reset */
12329 bnx2x_cl45_write(bp, phy_blk[port],
12330 MDIO_PMA_DEVAD,
12331 MDIO_PMA_REG_TX_POWER_DOWN,
12332 (val | 1<<10));
12333 }
12334
12335 /*
12336 * Toggle Transmitter: Power down and then up with 600ms delay
12337 * between
12338 */
12339 msleep(600);
12340
12341 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
12342 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12343 /* Phase2 of POWER_DOWN_RESET */
12344 /* Release bit 10 (Release Tx power down) */
12345 bnx2x_cl45_read(bp, phy_blk[port],
12346 MDIO_PMA_DEVAD,
12347 MDIO_PMA_REG_TX_POWER_DOWN, &val);
12348
12349 bnx2x_cl45_write(bp, phy_blk[port],
12350 MDIO_PMA_DEVAD,
12351 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
12352 msleep(15);
12353
12354 /* Read modify write the SPI-ROM version select register */
12355 bnx2x_cl45_read(bp, phy_blk[port],
12356 MDIO_PMA_DEVAD,
12357 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
12358 bnx2x_cl45_write(bp, phy_blk[port],
12359 MDIO_PMA_DEVAD,
12360 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
12361
12362 /* set GPIO2 back to LOW */
12363 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
12364 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
12365 }
12366 return 0;
12367 }
12368 static int bnx2x_8726_common_init_phy(struct bnx2x *bp,
12369 u32 shmem_base_path[],
12370 u32 shmem2_base_path[], u8 phy_index,
12371 u32 chip_id)
12372 {
12373 u32 val;
12374 s8 port;
12375 struct bnx2x_phy phy;
12376 /* Use port1 because of the static port-swap */
12377 /* Enable the module detection interrupt */
12378 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
12379 val |= ((1<<MISC_REGISTERS_GPIO_3)|
12380 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
12381 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
12382
12383 bnx2x_ext_phy_hw_reset(bp, 0);
12384 msleep(5);
12385 for (port = 0; port < PORT_MAX; port++) {
12386 u32 shmem_base, shmem2_base;
12387
12388 /* In E2, same phy is using for port0 of the two paths */
12389 if (CHIP_IS_E1x(bp)) {
12390 shmem_base = shmem_base_path[0];
12391 shmem2_base = shmem2_base_path[0];
12392 } else {
12393 shmem_base = shmem_base_path[port];
12394 shmem2_base = shmem2_base_path[port];
12395 }
12396 /* Extract the ext phy address for the port */
12397 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12398 port, &phy) !=
12399 0) {
12400 DP(NETIF_MSG_LINK, "populate phy failed\n");
12401 return -EINVAL;
12402 }
12403
12404 /* Reset phy*/
12405 bnx2x_cl45_write(bp, &phy,
12406 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
12407
12408
12409 /* Set fault module detected LED on */
12410 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
12411 MISC_REGISTERS_GPIO_HIGH,
12412 port);
12413 }
12414
12415 return 0;
12416 }
12417 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base,
12418 u8 *io_gpio, u8 *io_port)
12419 {
12420
12421 u32 phy_gpio_reset = REG_RD(bp, shmem_base +
12422 offsetof(struct shmem_region,
12423 dev_info.port_hw_config[PORT_0].default_cfg));
12424 switch (phy_gpio_reset) {
12425 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
12426 *io_gpio = 0;
12427 *io_port = 0;
12428 break;
12429 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
12430 *io_gpio = 1;
12431 *io_port = 0;
12432 break;
12433 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
12434 *io_gpio = 2;
12435 *io_port = 0;
12436 break;
12437 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
12438 *io_gpio = 3;
12439 *io_port = 0;
12440 break;
12441 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
12442 *io_gpio = 0;
12443 *io_port = 1;
12444 break;
12445 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
12446 *io_gpio = 1;
12447 *io_port = 1;
12448 break;
12449 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
12450 *io_gpio = 2;
12451 *io_port = 1;
12452 break;
12453 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
12454 *io_gpio = 3;
12455 *io_port = 1;
12456 break;
12457 default:
12458 /* Don't override the io_gpio and io_port */
12459 break;
12460 }
12461 }
12462
12463 static int bnx2x_8727_common_init_phy(struct bnx2x *bp,
12464 u32 shmem_base_path[],
12465 u32 shmem2_base_path[], u8 phy_index,
12466 u32 chip_id)
12467 {
12468 s8 port, reset_gpio;
12469 u32 swap_val, swap_override;
12470 struct bnx2x_phy phy[PORT_MAX];
12471 struct bnx2x_phy *phy_blk[PORT_MAX];
12472 s8 port_of_path;
12473 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
12474 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
12475
12476 reset_gpio = MISC_REGISTERS_GPIO_1;
12477 port = 1;
12478
12479 /*
12480 * Retrieve the reset gpio/port which control the reset.
12481 * Default is GPIO1, PORT1
12482 */
12483 bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0],
12484 (u8 *)&reset_gpio, (u8 *)&port);
12485
12486 /* Calculate the port based on port swap */
12487 port ^= (swap_val && swap_override);
12488
12489 /* Initiate PHY reset*/
12490 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
12491 port);
12492 msleep(1);
12493 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
12494 port);
12495
12496 msleep(5);
12497
12498 /* PART1 - Reset both phys */
12499 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12500 u32 shmem_base, shmem2_base;
12501
12502 /* In E2, same phy is using for port0 of the two paths */
12503 if (CHIP_IS_E1x(bp)) {
12504 shmem_base = shmem_base_path[0];
12505 shmem2_base = shmem2_base_path[0];
12506 port_of_path = port;
12507 } else {
12508 shmem_base = shmem_base_path[port];
12509 shmem2_base = shmem2_base_path[port];
12510 port_of_path = 0;
12511 }
12512
12513 /* Extract the ext phy address for the port */
12514 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12515 port_of_path, &phy[port]) !=
12516 0) {
12517 DP(NETIF_MSG_LINK, "populate phy failed\n");
12518 return -EINVAL;
12519 }
12520 /* disable attentions */
12521 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
12522 port_of_path*4,
12523 (NIG_MASK_XGXS0_LINK_STATUS |
12524 NIG_MASK_XGXS0_LINK10G |
12525 NIG_MASK_SERDES0_LINK_STATUS |
12526 NIG_MASK_MI_INT));
12527
12528
12529 /* Reset the phy */
12530 bnx2x_cl45_write(bp, &phy[port],
12531 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
12532 }
12533
12534 /* Add delay of 150ms after reset */
12535 msleep(150);
12536 if (phy[PORT_0].addr & 0x1) {
12537 phy_blk[PORT_0] = &(phy[PORT_1]);
12538 phy_blk[PORT_1] = &(phy[PORT_0]);
12539 } else {
12540 phy_blk[PORT_0] = &(phy[PORT_0]);
12541 phy_blk[PORT_1] = &(phy[PORT_1]);
12542 }
12543 /* PART2 - Download firmware to both phys */
12544 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12545 if (CHIP_IS_E1x(bp))
12546 port_of_path = port;
12547 else
12548 port_of_path = 0;
12549 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
12550 phy_blk[port]->addr);
12551 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
12552 port_of_path))
12553 return -EINVAL;
12554 /* Disable PHY transmitter output */
12555 bnx2x_cl45_write(bp, phy_blk[port],
12556 MDIO_PMA_DEVAD,
12557 MDIO_PMA_REG_TX_DISABLE, 1);
12558
12559 }
12560 return 0;
12561 }
12562
12563 static int bnx2x_84833_common_init_phy(struct bnx2x *bp,
12564 u32 shmem_base_path[],
12565 u32 shmem2_base_path[],
12566 u8 phy_index,
12567 u32 chip_id)
12568 {
12569 u8 reset_gpios;
12570 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id);
12571 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
12572 udelay(10);
12573 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH);
12574 DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n",
12575 reset_gpios);
12576 return 0;
12577 }
12578
12579 static int bnx2x_84833_pre_init_phy(struct bnx2x *bp,
12580 struct bnx2x_phy *phy)
12581 {
12582 u16 val, cnt;
12583 /* Wait for FW completing its initialization. */
12584 for (cnt = 0; cnt < 1500; cnt++) {
12585 bnx2x_cl45_read(bp, phy,
12586 MDIO_PMA_DEVAD,
12587 MDIO_PMA_REG_CTRL, &val);
12588 if (!(val & (1<<15)))
12589 break;
12590 msleep(1);
12591 }
12592 if (cnt >= 1500) {
12593 DP(NETIF_MSG_LINK, "84833 reset timeout\n");
12594 return -EINVAL;
12595 }
12596
12597 /* Put the port in super isolate mode. */
12598 bnx2x_cl45_read(bp, phy,
12599 MDIO_CTL_DEVAD,
12600 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val);
12601 val |= MDIO_84833_SUPER_ISOLATE;
12602 bnx2x_cl45_write(bp, phy,
12603 MDIO_CTL_DEVAD,
12604 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val);
12605
12606 /* Save spirom version */
12607 bnx2x_save_848xx_spirom_version(phy, bp, PORT_0);
12608 return 0;
12609 }
12610
12611 int bnx2x_pre_init_phy(struct bnx2x *bp,
12612 u32 shmem_base,
12613 u32 shmem2_base,
12614 u32 chip_id)
12615 {
12616 int rc = 0;
12617 struct bnx2x_phy phy;
12618 bnx2x_set_mdio_clk(bp, chip_id, PORT_0);
12619 if (bnx2x_populate_phy(bp, EXT_PHY1, shmem_base, shmem2_base,
12620 PORT_0, &phy)) {
12621 DP(NETIF_MSG_LINK, "populate_phy failed\n");
12622 return -EINVAL;
12623 }
12624 switch (phy.type) {
12625 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
12626 rc = bnx2x_84833_pre_init_phy(bp, &phy);
12627 break;
12628 default:
12629 break;
12630 }
12631 return rc;
12632 }
12633
12634 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
12635 u32 shmem2_base_path[], u8 phy_index,
12636 u32 ext_phy_type, u32 chip_id)
12637 {
12638 int rc = 0;
12639
12640 switch (ext_phy_type) {
12641 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
12642 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
12643 shmem2_base_path,
12644 phy_index, chip_id);
12645 break;
12646 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
12647 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
12648 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
12649 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
12650 shmem2_base_path,
12651 phy_index, chip_id);
12652 break;
12653
12654 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
12655 /*
12656 * GPIO1 affects both ports, so there's need to pull
12657 * it for single port alone
12658 */
12659 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
12660 shmem2_base_path,
12661 phy_index, chip_id);
12662 break;
12663 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
12664 /*
12665 * GPIO3's are linked, and so both need to be toggled
12666 * to obtain required 2us pulse.
12667 */
12668 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path,
12669 shmem2_base_path,
12670 phy_index, chip_id);
12671 break;
12672 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
12673 rc = -EINVAL;
12674 break;
12675 default:
12676 DP(NETIF_MSG_LINK,
12677 "ext_phy 0x%x common init not required\n",
12678 ext_phy_type);
12679 break;
12680 }
12681
12682 if (rc != 0)
12683 netdev_err(bp->dev, "Warning: PHY was not initialized,"
12684 " Port %d\n",
12685 0);
12686 return rc;
12687 }
12688
12689 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
12690 u32 shmem2_base_path[], u32 chip_id)
12691 {
12692 int rc = 0;
12693 u32 phy_ver, val;
12694 u8 phy_index = 0;
12695 u32 ext_phy_type, ext_phy_config;
12696 bnx2x_set_mdio_clk(bp, chip_id, PORT_0);
12697 bnx2x_set_mdio_clk(bp, chip_id, PORT_1);
12698 DP(NETIF_MSG_LINK, "Begin common phy init\n");
12699 if (CHIP_IS_E3(bp)) {
12700 /* Enable EPIO */
12701 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG);
12702 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1);
12703 }
12704 /* Check if common init was already done */
12705 phy_ver = REG_RD(bp, shmem_base_path[0] +
12706 offsetof(struct shmem_region,
12707 port_mb[PORT_0].ext_phy_fw_version));
12708 if (phy_ver) {
12709 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
12710 phy_ver);
12711 return 0;
12712 }
12713
12714 /* Read the ext_phy_type for arbitrary port(0) */
12715 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12716 phy_index++) {
12717 ext_phy_config = bnx2x_get_ext_phy_config(bp,
12718 shmem_base_path[0],
12719 phy_index, 0);
12720 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
12721 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
12722 shmem2_base_path,
12723 phy_index, ext_phy_type,
12724 chip_id);
12725 }
12726 return rc;
12727 }
12728
12729 static void bnx2x_check_over_curr(struct link_params *params,
12730 struct link_vars *vars)
12731 {
12732 struct bnx2x *bp = params->bp;
12733 u32 cfg_pin;
12734 u8 port = params->port;
12735 u32 pin_val;
12736
12737 cfg_pin = (REG_RD(bp, params->shmem_base +
12738 offsetof(struct shmem_region,
12739 dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
12740 PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
12741 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
12742
12743 /* Ignore check if no external input PIN available */
12744 if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0)
12745 return;
12746
12747 if (!pin_val) {
12748 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
12749 netdev_err(bp->dev, "Error: Power fault on Port %d has"
12750 " been detected and the power to "
12751 "that SFP+ module has been removed"
12752 " to prevent failure of the card."
12753 " Please remove the SFP+ module and"
12754 " restart the system to clear this"
12755 " error.\n",
12756 params->port);
12757 vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
12758 }
12759 } else
12760 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
12761 }
12762
12763 static void bnx2x_analyze_link_error(struct link_params *params,
12764 struct link_vars *vars, u32 lss_status)
12765 {
12766 struct bnx2x *bp = params->bp;
12767 /* Compare new value with previous value */
12768 u8 led_mode;
12769 u32 half_open_conn = (vars->phy_flags & PHY_HALF_OPEN_CONN_FLAG) > 0;
12770
12771 if ((lss_status ^ half_open_conn) == 0)
12772 return;
12773
12774 /* If values differ */
12775 DP(NETIF_MSG_LINK, "Link changed:%x %x->%x\n", vars->link_up,
12776 half_open_conn, lss_status);
12777
12778 /*
12779 * a. Update shmem->link_status accordingly
12780 * b. Update link_vars->link_up
12781 */
12782 if (lss_status) {
12783 DP(NETIF_MSG_LINK, "Remote Fault detected !!!\n");
12784 vars->link_status &= ~LINK_STATUS_LINK_UP;
12785 vars->link_up = 0;
12786 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
12787 /*
12788 * Set LED mode to off since the PHY doesn't know about these
12789 * errors
12790 */
12791 led_mode = LED_MODE_OFF;
12792 } else {
12793 DP(NETIF_MSG_LINK, "Remote Fault cleared\n");
12794 vars->link_status |= LINK_STATUS_LINK_UP;
12795 vars->link_up = 1;
12796 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
12797 led_mode = LED_MODE_OPER;
12798 }
12799 /* Update the LED according to the link state */
12800 bnx2x_set_led(params, vars, led_mode, SPEED_10000);
12801
12802 /* Update link status in the shared memory */
12803 bnx2x_update_mng(params, vars->link_status);
12804
12805 /* C. Trigger General Attention */
12806 vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT;
12807 bnx2x_notify_link_changed(bp);
12808 }
12809
12810 /******************************************************************************
12811 * Description:
12812 * This function checks for half opened connection change indication.
12813 * When such change occurs, it calls the bnx2x_analyze_link_error
12814 * to check if Remote Fault is set or cleared. Reception of remote fault
12815 * status message in the MAC indicates that the peer's MAC has detected
12816 * a fault, for example, due to break in the TX side of fiber.
12817 *
12818 ******************************************************************************/
12819 static void bnx2x_check_half_open_conn(struct link_params *params,
12820 struct link_vars *vars)
12821 {
12822 struct bnx2x *bp = params->bp;
12823 u32 lss_status = 0;
12824 u32 mac_base;
12825 /* In case link status is physically up @ 10G do */
12826 if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0)
12827 return;
12828
12829 if (CHIP_IS_E3(bp) &&
12830 (REG_RD(bp, MISC_REG_RESET_REG_2) &
12831 (MISC_REGISTERS_RESET_REG_2_XMAC))) {
12832 /* Check E3 XMAC */
12833 /*
12834 * Note that link speed cannot be queried here, since it may be
12835 * zero while link is down. In case UMAC is active, LSS will
12836 * simply not be set
12837 */
12838 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
12839
12840 /* Clear stick bits (Requires rising edge) */
12841 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
12842 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
12843 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
12844 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
12845 if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS))
12846 lss_status = 1;
12847
12848 bnx2x_analyze_link_error(params, vars, lss_status);
12849 } else if (REG_RD(bp, MISC_REG_RESET_REG_2) &
12850 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {
12851 /* Check E1X / E2 BMAC */
12852 u32 lss_status_reg;
12853 u32 wb_data[2];
12854 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
12855 NIG_REG_INGRESS_BMAC0_MEM;
12856 /* Read BIGMAC_REGISTER_RX_LSS_STATUS */
12857 if (CHIP_IS_E2(bp))
12858 lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
12859 else
12860 lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
12861
12862 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2);
12863 lss_status = (wb_data[0] > 0);
12864
12865 bnx2x_analyze_link_error(params, vars, lss_status);
12866 }
12867 }
12868
12869 void bnx2x_period_func(struct link_params *params, struct link_vars *vars)
12870 {
12871 struct bnx2x *bp = params->bp;
12872 u16 phy_idx;
12873 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
12874 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
12875 bnx2x_set_aer_mmd(params, &params->phy[phy_idx]);
12876 bnx2x_check_half_open_conn(params, vars);
12877 break;
12878 }
12879 }
12880
12881 if (CHIP_IS_E3(bp)) {
12882 struct bnx2x_phy *phy = &params->phy[INT_PHY];
12883 bnx2x_set_aer_mmd(params, phy);
12884 bnx2x_check_over_curr(params, vars);
12885 bnx2x_warpcore_config_runtime(phy, params, vars);
12886 }
12887
12888 }
12889
12890 u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base, u32 shmem2_base)
12891 {
12892 u8 phy_index;
12893 struct bnx2x_phy phy;
12894 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12895 phy_index++) {
12896 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12897 0, &phy) != 0) {
12898 DP(NETIF_MSG_LINK, "populate phy failed\n");
12899 return 0;
12900 }
12901
12902 if (phy.flags & FLAGS_HW_LOCK_REQUIRED)
12903 return 1;
12904 }
12905 return 0;
12906 }
12907
12908 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
12909 u32 shmem_base,
12910 u32 shmem2_base,
12911 u8 port)
12912 {
12913 u8 phy_index, fan_failure_det_req = 0;
12914 struct bnx2x_phy phy;
12915 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12916 phy_index++) {
12917 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12918 port, &phy)
12919 != 0) {
12920 DP(NETIF_MSG_LINK, "populate phy failed\n");
12921 return 0;
12922 }
12923 fan_failure_det_req |= (phy.flags &
12924 FLAGS_FAN_FAILURE_DET_REQ);
12925 }
12926 return fan_failure_det_req;
12927 }
12928
12929 void bnx2x_hw_reset_phy(struct link_params *params)
12930 {
12931 u8 phy_index;
12932 struct bnx2x *bp = params->bp;
12933 bnx2x_update_mng(params, 0);
12934 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
12935 (NIG_MASK_XGXS0_LINK_STATUS |
12936 NIG_MASK_XGXS0_LINK10G |
12937 NIG_MASK_SERDES0_LINK_STATUS |
12938 NIG_MASK_MI_INT));
12939
12940 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12941 phy_index++) {
12942 if (params->phy[phy_index].hw_reset) {
12943 params->phy[phy_index].hw_reset(
12944 &params->phy[phy_index],
12945 params);
12946 params->phy[phy_index] = phy_null;
12947 }
12948 }
12949 }
12950
12951 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
12952 u32 chip_id, u32 shmem_base, u32 shmem2_base,
12953 u8 port)
12954 {
12955 u8 gpio_num = 0xff, gpio_port = 0xff, phy_index;
12956 u32 val;
12957 u32 offset, aeu_mask, swap_val, swap_override, sync_offset;
12958 if (CHIP_IS_E3(bp)) {
12959 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id,
12960 shmem_base,
12961 port,
12962 &gpio_num,
12963 &gpio_port) != 0)
12964 return;
12965 } else {
12966 struct bnx2x_phy phy;
12967 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12968 phy_index++) {
12969 if (bnx2x_populate_phy(bp, phy_index, shmem_base,
12970 shmem2_base, port, &phy)
12971 != 0) {
12972 DP(NETIF_MSG_LINK, "populate phy failed\n");
12973 return;
12974 }
12975 if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
12976 gpio_num = MISC_REGISTERS_GPIO_3;
12977 gpio_port = port;
12978 break;
12979 }
12980 }
12981 }
12982
12983 if (gpio_num == 0xff)
12984 return;
12985
12986 /* Set GPIO3 to trigger SFP+ module insertion/removal */
12987 bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);
12988
12989 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
12990 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
12991 gpio_port ^= (swap_val && swap_override);
12992
12993 vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
12994 (gpio_num + (gpio_port << 2));
12995
12996 sync_offset = shmem_base +
12997 offsetof(struct shmem_region,
12998 dev_info.port_hw_config[port].aeu_int_mask);
12999 REG_WR(bp, sync_offset, vars->aeu_int_mask);
13000
13001 DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
13002 gpio_num, gpio_port, vars->aeu_int_mask);
13003
13004 if (port == 0)
13005 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
13006 else
13007 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
13008
13009 /* Open appropriate AEU for interrupts */
13010 aeu_mask = REG_RD(bp, offset);
13011 aeu_mask |= vars->aeu_int_mask;
13012 REG_WR(bp, offset, aeu_mask);
13013
13014 /* Enable the GPIO to trigger interrupt */
13015 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
13016 val |= 1 << (gpio_num + (gpio_port << 2));
13017 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
13018 }
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