drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.h

   1 /* Copyright 2008-2013 Broadcom Corporation
   2  *
   3  * Unless you and Broadcom execute a separate written software license
   4  * agreement governing use of this software, this software is licensed to you
   5  * under the terms of the GNU General Public License version 2, available
   6  * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
   7  *
   8  * Notwithstanding the above, under no circumstances may you combine this
   9  * software in any way with any other Broadcom software provided under a
  10  * license other than the GPL, without Broadcom's express prior written
  11  * consent.
  12  *
  13  * Written by Yaniv Rosner
  14  *
  15  */
  16
  17 #ifndef BNX2X_LINK_H
  18 #define BNX2X_LINK_H
  19
  20
  21
  22 /***********************************************************/
  23 /*                         Defines                         */
  24 /***********************************************************/
  25 #define DEFAULT_PHY_DEV_ADDR    3
  26 #define E2_DEFAULT_PHY_DEV_ADDR 5
  27
  28
  29
  30 #define BNX2X_FLOW_CTRL_AUTO            PORT_FEATURE_FLOW_CONTROL_AUTO
  31 #define BNX2X_FLOW_CTRL_TX              PORT_FEATURE_FLOW_CONTROL_TX
  32 #define BNX2X_FLOW_CTRL_RX              PORT_FEATURE_FLOW_CONTROL_RX
  33 #define BNX2X_FLOW_CTRL_BOTH            PORT_FEATURE_FLOW_CONTROL_BOTH
  34 #define BNX2X_FLOW_CTRL_NONE            PORT_FEATURE_FLOW_CONTROL_NONE
  35
  36 #define NET_SERDES_IF_XFI               1
  37 #define NET_SERDES_IF_SFI               2
  38 #define NET_SERDES_IF_KR                3
  39 #define NET_SERDES_IF_DXGXS     4
  40
  41 #define SPEED_AUTO_NEG          0
  42 #define SPEED_20000             20000
  43
  44 #define I2C_DEV_ADDR_A0                 0xa0
  45 #define I2C_DEV_ADDR_A2                 0xa2
  46
  47 #define SFP_EEPROM_PAGE_SIZE                    16
  48 #define SFP_EEPROM_VENDOR_NAME_ADDR             0x14
  49 #define SFP_EEPROM_VENDOR_NAME_SIZE             16
  50 #define SFP_EEPROM_VENDOR_OUI_ADDR              0x25
  51 #define SFP_EEPROM_VENDOR_OUI_SIZE              3
  52 #define SFP_EEPROM_PART_NO_ADDR                 0x28
  53 #define SFP_EEPROM_PART_NO_SIZE                 16
  54 #define SFP_EEPROM_REVISION_ADDR                0x38
  55 #define SFP_EEPROM_REVISION_SIZE                4
  56 #define SFP_EEPROM_SERIAL_ADDR                  0x44
  57 #define SFP_EEPROM_SERIAL_SIZE                  16
  58 #define SFP_EEPROM_DATE_ADDR                    0x54 /* ASCII YYMMDD */
  59 #define SFP_EEPROM_DATE_SIZE                    6
  60 #define SFP_EEPROM_DIAG_TYPE_ADDR               0x5c
  61 #define SFP_EEPROM_DIAG_TYPE_SIZE               1
  62 #define SFP_EEPROM_DIAG_ADDR_CHANGE_REQ         (1<<2)
  63 #define SFP_EEPROM_SFF_8472_COMP_ADDR           0x5e
  64 #define SFP_EEPROM_SFF_8472_COMP_SIZE           1
  65
  66 #define SFP_EEPROM_A2_CHECKSUM_RANGE            0x5e
  67 #define SFP_EEPROM_A2_CC_DMI_ADDR               0x5f
  68
  69 #define PWR_FLT_ERR_MSG_LEN                     250
  70
  71 #define XGXS_EXT_PHY_TYPE(ext_phy_config) \
  72                 ((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
  73 #define XGXS_EXT_PHY_ADDR(ext_phy_config) \
  74                 (((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \
  75                  PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT)
  76 #define SERDES_EXT_PHY_TYPE(ext_phy_config) \
  77                 ((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)
  78
  79 /* Single Media Direct board is the plain 577xx board with CX4/RJ45 jacks */
  80 #define SINGLE_MEDIA_DIRECT(params)     (params->num_phys == 1)
  81 /* Single Media board contains single external phy */
  82 #define SINGLE_MEDIA(params)            (params->num_phys == 2)
  83 /* Dual Media board contains two external phy with different media */
  84 #define DUAL_MEDIA(params)              (params->num_phys == 3)
  85
  86 #define FW_PARAM_PHY_ADDR_MASK          0x000000FF
  87 #define FW_PARAM_PHY_TYPE_MASK          0x0000FF00
  88 #define FW_PARAM_MDIO_CTRL_MASK         0xFFFF0000
  89 #define FW_PARAM_MDIO_CTRL_OFFSET               16
  90 #define FW_PARAM_PHY_ADDR(fw_param) (fw_param & \
  91                                            FW_PARAM_PHY_ADDR_MASK)
  92 #define FW_PARAM_PHY_TYPE(fw_param) (fw_param & \
  93                                            FW_PARAM_PHY_TYPE_MASK)
  94 #define FW_PARAM_MDIO_CTRL(fw_param) ((fw_param & \
  95                                             FW_PARAM_MDIO_CTRL_MASK) >> \
  96                                             FW_PARAM_MDIO_CTRL_OFFSET)
  97 #define FW_PARAM_SET(phy_addr, phy_type, mdio_access) \
  98         (phy_addr | phy_type | mdio_access << FW_PARAM_MDIO_CTRL_OFFSET)
  99
 100
 101 #define PFC_BRB_FULL_LB_XOFF_THRESHOLD                          170
 102 #define PFC_BRB_FULL_LB_XON_THRESHOLD                           250
 103
 104 #define MAXVAL(a, b) (((a) > (b)) ? (a) : (b))
 105
 106 #define BMAC_CONTROL_RX_ENABLE          2
 107 /***********************************************************/
 108 /*                         Structs                         */
 109 /***********************************************************/
 110 #define INT_PHY         0
 111 #define EXT_PHY1        1
 112 #define EXT_PHY2        2
 113 #define MAX_PHYS        3
 114
 115 /* Same configuration is shared between the XGXS and the first external phy */
 116 #define LINK_CONFIG_SIZE (MAX_PHYS - 1)
 117 #define LINK_CONFIG_IDX(_phy_idx) ((_phy_idx == INT_PHY) ? \
 118                                          0 : (_phy_idx - 1))
 119 /***********************************************************/
 120 /*                      bnx2x_phy struct                     */
 121 /*  Defines the required arguments and function per phy    */
 122 /***********************************************************/
 123 struct link_vars;
 124 struct link_params;
 125 struct bnx2x_phy;
 126
 127 typedef u8 (*config_init_t)(struct bnx2x_phy *phy, struct link_params *params,
 128                             struct link_vars *vars);
 129 typedef u8 (*read_status_t)(struct bnx2x_phy *phy, struct link_params *params,
 130                             struct link_vars *vars);
 131 typedef void (*link_reset_t)(struct bnx2x_phy *phy,
 132                              struct link_params *params);
 133 typedef void (*config_loopback_t)(struct bnx2x_phy *phy,
 134                                   struct link_params *params);
 135 typedef u8 (*format_fw_ver_t)(u32 raw, u8 *str, u16 *len);
 136 typedef void (*hw_reset_t)(struct bnx2x_phy *phy, struct link_params *params);
 137 typedef void (*set_link_led_t)(struct bnx2x_phy *phy,
 138                                struct link_params *params, u8 mode);
 139 typedef void (*phy_specific_func_t)(struct bnx2x_phy *phy,
 140                                     struct link_params *params, u32 action);
 141 struct bnx2x_reg_set {
 142         u8  devad;
 143         u16 reg;
 144         u16 val;
 145 };
 146
 147 struct bnx2x_phy {
 148         u32 type;
 149
 150         /* Loaded during init */
 151         u8 addr;
 152         u8 def_md_devad;
 153         u16 flags;
 154         /* No Over-Current detection */
 155 #define FLAGS_NOC                       (1<<1)
 156         /* Fan failure detection required */
 157 #define FLAGS_FAN_FAILURE_DET_REQ       (1<<2)
 158         /* Initialize first the XGXS and only then the phy itself */
 159 #define FLAGS_INIT_XGXS_FIRST           (1<<3)
 160 #define FLAGS_WC_DUAL_MODE              (1<<4)
 161 #define FLAGS_4_PORT_MODE               (1<<5)
 162 #define FLAGS_REARM_LATCH_SIGNAL        (1<<6)
 163 #define FLAGS_SFP_NOT_APPROVED          (1<<7)
 164 #define FLAGS_MDC_MDIO_WA               (1<<8)
 165 #define FLAGS_DUMMY_READ                (1<<9)
 166 #define FLAGS_MDC_MDIO_WA_B0            (1<<10)
 167 #define FLAGS_TX_ERROR_CHECK            (1<<12)
 168 #define FLAGS_EEE                       (1<<13)
 169 #define FLAGS_MDC_MDIO_WA_G             (1<<15)
 170
 171         /* preemphasis values for the rx side */
 172         u16 rx_preemphasis[4];
 173
 174         /* preemphasis values for the tx side */
 175         u16 tx_preemphasis[4];
 176
 177         /* EMAC address for access MDIO */
 178         u32 mdio_ctrl;
 179
 180         u32 supported;
 181
 182         u32 media_type;
 183 #define ETH_PHY_UNSPECIFIED     0x0
 184 #define ETH_PHY_SFPP_10G_FIBER  0x1
 185 #define ETH_PHY_XFP_FIBER               0x2
 186 #define ETH_PHY_DA_TWINAX               0x3
 187 #define ETH_PHY_BASE_T          0x4
 188 #define ETH_PHY_SFP_1G_FIBER    0x5
 189 #define ETH_PHY_KR              0xf0
 190 #define ETH_PHY_CX4             0xf1
 191 #define ETH_PHY_NOT_PRESENT     0xff
 192
 193         /* The address in which version is located*/
 194         u32 ver_addr;
 195
 196         u16 req_flow_ctrl;
 197
 198         u16 req_line_speed;
 199
 200         u32 speed_cap_mask;
 201
 202         u16 req_duplex;
 203         u16 rsrv;
 204         /* Called per phy/port init, and it configures LASI, speed, autoneg,
 205          duplex, flow control negotiation, etc. */
 206         config_init_t config_init;
 207
 208         /* Called due to interrupt. It determines the link, speed */
 209         read_status_t read_status;
 210
 211         /* Called when driver is unloading. Should reset the phy */
 212         link_reset_t link_reset;
 213
 214         /* Set the loopback configuration for the phy */
 215         config_loopback_t config_loopback;
 216
 217         /* Format the given raw number into str up to len */
 218         format_fw_ver_t format_fw_ver;
 219
 220         /* Reset the phy (both ports) */
 221         hw_reset_t hw_reset;
 222
 223         /* Set link led mode (on/off/oper)*/
 224         set_link_led_t set_link_led;
 225
 226         /* PHY Specific tasks */
 227         phy_specific_func_t phy_specific_func;
 228 #define DISABLE_TX      1
 229 #define ENABLE_TX       2
 230 #define PHY_INIT        3
 231 };
 232
 233 /* Inputs parameters to the CLC */
 234 struct link_params {
 235
 236         u8 port;
 237
 238         /* Default / User Configuration */
 239         u8 loopback_mode;
 240 #define LOOPBACK_NONE           0
 241 #define LOOPBACK_EMAC           1
 242 #define LOOPBACK_BMAC           2
 243 #define LOOPBACK_XGXS           3
 244 #define LOOPBACK_EXT_PHY        4
 245 #define LOOPBACK_EXT            5
 246 #define LOOPBACK_UMAC           6
 247 #define LOOPBACK_XMAC           7
 248
 249         /* Device parameters */
 250         u8 mac_addr[6];
 251
 252         u16 req_duplex[LINK_CONFIG_SIZE];
 253         u16 req_flow_ctrl[LINK_CONFIG_SIZE];
 254
 255         u16 req_line_speed[LINK_CONFIG_SIZE]; /* Also determine AutoNeg */
 256
 257         /* shmem parameters */
 258         u32 shmem_base;
 259         u32 shmem2_base;
 260         u32 speed_cap_mask[LINK_CONFIG_SIZE];
 261         u32 switch_cfg;
 262 #define SWITCH_CFG_1G           PORT_FEATURE_CON_SWITCH_1G_SWITCH
 263 #define SWITCH_CFG_10G          PORT_FEATURE_CON_SWITCH_10G_SWITCH
 264 #define SWITCH_CFG_AUTO_DETECT  PORT_FEATURE_CON_SWITCH_AUTO_DETECT
 265
 266         u32 lane_config;
 267
 268         /* Phy register parameter */
 269         u32 chip_id;
 270
 271         /* features */
 272         u32 feature_config_flags;
 273 #define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED     (1<<0)
 274 #define FEATURE_CONFIG_PFC_ENABLED                      (1<<1)
 275 #define FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY         (1<<2)
 276 #define FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY        (1<<3)
 277 #define FEATURE_CONFIG_BC_SUPPORTS_AFEX                 (1<<8)
 278 #define FEATURE_CONFIG_AUTOGREEEN_ENABLED                       (1<<9)
 279 #define FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED              (1<<10)
 280 #define FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET         (1<<11)
 281 #define FEATURE_CONFIG_MT_SUPPORT                       (1<<13)
 282 #define FEATURE_CONFIG_BOOT_FROM_SAN                    (1<<14)
 283
 284         /* Will be populated during common init */
 285         struct bnx2x_phy phy[MAX_PHYS];
 286
 287         /* Will be populated during common init */
 288         u8 num_phys;
 289
 290         u8 rsrv;
 291
 292         /* Used to configure the EEE Tx LPI timer, has several modes of
 293          * operation, according to bits 29:28 -
 294          * 2'b00: Timer will be configured by nvram, output will be the value
 295          *        from nvram.
 296          * 2'b01: Timer will be configured by nvram, output will be in
 297          *        microseconds.
 298          * 2'b10: bits 1:0 contain an nvram value which will be used instead
 299          *        of the one located in the nvram. Output will be that value.
 300          * 2'b11: bits 19:0 contain the idle timer in microseconds; output
 301          *        will be in microseconds.
 302          * Bits 31:30 should be 2'b11 in order for EEE to be enabled.
 303          */
 304         u32 eee_mode;
 305 #define EEE_MODE_NVRAM_BALANCED_TIME            (0xa00)
 306 #define EEE_MODE_NVRAM_AGGRESSIVE_TIME          (0x100)
 307 #define EEE_MODE_NVRAM_LATENCY_TIME             (0x6000)
 308 #define EEE_MODE_NVRAM_MASK             (0x3)
 309 #define EEE_MODE_TIMER_MASK             (0xfffff)
 310 #define EEE_MODE_OUTPUT_TIME            (1<<28)
 311 #define EEE_MODE_OVERRIDE_NVRAM         (1<<29)
 312 #define EEE_MODE_ENABLE_LPI             (1<<30)
 313 #define EEE_MODE_ADV_LPI                        (1<<31)
 314
 315         u16 hw_led_mode; /* part of the hw_config read from the shmem */
 316         u32 multi_phy_config;
 317
 318         /* Device pointer passed to all callback functions */
 319         struct bnx2x *bp;
 320         u16 req_fc_auto_adv; /* Should be set to TX / BOTH when
 321                                 req_flow_ctrl is set to AUTO */
 322         u16 link_flags;
 323 #define LINK_FLAGS_INT_DISABLED         (1<<0)
 324 #define PHY_INITIALIZED         (1<<1)
 325         u32 lfa_base;
 326 };
 327
 328 /* Output parameters */
 329 struct link_vars {
 330         u8 phy_flags;
 331 #define PHY_XGXS_FLAG                   (1<<0)
 332 #define PHY_SGMII_FLAG                  (1<<1)
 333 #define PHY_PHYSICAL_LINK_FLAG          (1<<2)
 334 #define PHY_HALF_OPEN_CONN_FLAG         (1<<3)
 335 #define PHY_OVER_CURRENT_FLAG           (1<<4)
 336 #define PHY_SFP_TX_FAULT_FLAG           (1<<5)
 337
 338         u8 mac_type;
 339 #define MAC_TYPE_NONE           0
 340 #define MAC_TYPE_EMAC           1
 341 #define MAC_TYPE_BMAC           2
 342 #define MAC_TYPE_UMAC           3
 343 #define MAC_TYPE_XMAC           4
 344
 345         u8 phy_link_up; /* internal phy link indication */
 346         u8 link_up;
 347
 348         u16 line_speed;
 349         u16 duplex;
 350
 351         u16 flow_ctrl;
 352         u16 ieee_fc;
 353
 354         /* The same definitions as the shmem parameter */
 355         u32 link_status;
 356         u32 eee_status;
 357         u8 fault_detected;
 358         u8 check_kr2_recovery_cnt;
 359 #define CHECK_KR2_RECOVERY_CNT  5
 360         u16 periodic_flags;
 361 #define PERIODIC_FLAGS_LINK_EVENT       0x0001
 362
 363         u32 aeu_int_mask;
 364         u8 rx_tx_asic_rst;
 365         u8 turn_to_run_wc_rt;
 366         u16 rsrv2;
 367         /* The same definitions as the shmem2 parameter */
 368         u32 link_attr_sync;
 369 };
 370
 371 /***********************************************************/
 372 /*                         Functions                       */
 373 /***********************************************************/
 374 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars);
 375
 376 /* Reset the link. Should be called when driver or interface goes down
 377    Before calling phy firmware upgrade, the reset_ext_phy should be set
 378    to 0 */
 379 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
 380                      u8 reset_ext_phy);
 381 int bnx2x_lfa_reset(struct link_params *params, struct link_vars *vars);
 382 /* bnx2x_link_update should be called upon link interrupt */
 383 int bnx2x_link_update(struct link_params *params, struct link_vars *vars);
 384
 385 /* use the following phy functions to read/write from external_phy
 386   In order to use it to read/write internal phy registers, use
 387   DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as
 388   the register */
 389 int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
 390                    u8 devad, u16 reg, u16 *ret_val);
 391
 392 int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
 393                     u8 devad, u16 reg, u16 val);
 394
 395 /* Reads the link_status from the shmem,
 396    and update the link vars accordingly */
 397 void bnx2x_link_status_update(struct link_params *input,
 398                             struct link_vars *output);
 399 /* returns string representing the fw_version of the external phy */
 400 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version,
 401                                  u16 len);
 402
 403 /* Set/Unset the led
 404    Basically, the CLC takes care of the led for the link, but in case one needs
 405    to set/unset the led unnaturally, set the "mode" to LED_MODE_OPER to
 406    blink the led, and LED_MODE_OFF to set the led off.*/
 407 int bnx2x_set_led(struct link_params *params,
 408                   struct link_vars *vars, u8 mode, u32 speed);
 409 #define LED_MODE_OFF                    0
 410 #define LED_MODE_ON                     1
 411 #define LED_MODE_OPER                   2
 412 #define LED_MODE_FRONT_PANEL_OFF        3
 413
 414 /* bnx2x_handle_module_detect_int should be called upon module detection
 415    interrupt */
 416 void bnx2x_handle_module_detect_int(struct link_params *params);
 417
 418 /* Get the actual link status. In case it returns 0, link is up,
 419         otherwise link is down*/
 420 int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
 421                     u8 is_serdes);
 422
 423 /* One-time initialization for external phy after power up */
 424 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
 425                           u32 shmem2_base_path[], u32 chip_id);
 426
 427 /* Reset the external PHY using GPIO */
 428 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port);
 429
 430 /* Reset the external of SFX7101 */
 431 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy);
 432
 433 /* Read "byte_cnt" bytes from address "addr" from the SFP+ EEPROM */
 434 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
 435                                  struct link_params *params, u8 dev_addr,
 436                                  u16 addr, u16 byte_cnt, u8 *o_buf);
 437
 438 void bnx2x_hw_reset_phy(struct link_params *params);
 439
 440 /* Check swap bit and adjust PHY order */
 441 u32 bnx2x_phy_selection(struct link_params *params);
 442
 443 /* Probe the phys on board, and populate them in "params" */
 444 int bnx2x_phy_probe(struct link_params *params);
 445
 446 /* Checks if fan failure detection is required on one of the phys on board */
 447 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, u32 shmem_base,
 448                              u32 shmem2_base, u8 port);
 449
 450 /* Open / close the gate between the NIG and the BRB */
 451 void bnx2x_set_rx_filter(struct link_params *params, u8 en);
 452
 453 /* DCBX structs */
 454
 455 /* Number of maximum COS per chip */
 456 #define DCBX_E2E3_MAX_NUM_COS           (2)
 457 #define DCBX_E3B0_MAX_NUM_COS_PORT0     (6)
 458 #define DCBX_E3B0_MAX_NUM_COS_PORT1     (3)
 459 #define DCBX_E3B0_MAX_NUM_COS           ( \
 460                         MAXVAL(DCBX_E3B0_MAX_NUM_COS_PORT0, \
 461                             DCBX_E3B0_MAX_NUM_COS_PORT1))
 462
 463 #define DCBX_MAX_NUM_COS                        ( \
 464                         MAXVAL(DCBX_E3B0_MAX_NUM_COS, \
 465                             DCBX_E2E3_MAX_NUM_COS))
 466
 467 /* PFC port configuration params */
 468 struct bnx2x_nig_brb_pfc_port_params {
 469         /* NIG */
 470         u32 pause_enable;
 471         u32 llfc_out_en;
 472         u32 llfc_enable;
 473         u32 pkt_priority_to_cos;
 474         u8 num_of_rx_cos_priority_mask;
 475         u32 rx_cos_priority_mask[DCBX_MAX_NUM_COS];
 476         u32 llfc_high_priority_classes;
 477         u32 llfc_low_priority_classes;
 478 };
 479
 480
 481 /* ETS port configuration params */
 482 struct bnx2x_ets_bw_params {
 483         u8 bw;
 484 };
 485
 486 struct bnx2x_ets_sp_params {
 487         /**
 488          * valid values are 0 - 5. 0 is highest strict priority.
 489          * There can't be two COS's with the same pri.
 490          */
 491         u8 pri;
 492 };
 493
 494 enum bnx2x_cos_state {
 495         bnx2x_cos_state_strict = 0,
 496         bnx2x_cos_state_bw = 1,
 497 };
 498
 499 struct bnx2x_ets_cos_params {
 500         enum bnx2x_cos_state state ;
 501         union {
 502                 struct bnx2x_ets_bw_params bw_params;
 503                 struct bnx2x_ets_sp_params sp_params;
 504         } params;
 505 };
 506
 507 struct bnx2x_ets_params {
 508         u8 num_of_cos; /* Number of valid COS entries*/
 509         struct bnx2x_ets_cos_params cos[DCBX_MAX_NUM_COS];
 510 };
 511
 512 /* Used to update the PFC attributes in EMAC, BMAC, NIG and BRB
 513  * when link is already up
 514  */
 515 int bnx2x_update_pfc(struct link_params *params,
 516                       struct link_vars *vars,
 517                       struct bnx2x_nig_brb_pfc_port_params *pfc_params);
 518
 519
 520 /* Used to configure the ETS to disable */
 521 int bnx2x_ets_disabled(struct link_params *params,
 522                        struct link_vars *vars);
 523
 524 /* Used to configure the ETS to BW limited */
 525 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
 526                         const u32 cos1_bw);
 527
 528 /* Used to configure the ETS to strict */
 529 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos);
 530
 531
 532 /*  Configure the COS to ETS according to BW and SP settings.*/
 533 int bnx2x_ets_e3b0_config(const struct link_params *params,
 534                          const struct link_vars *vars,
 535                          struct bnx2x_ets_params *ets_params);
 536
 537 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
 538                             u32 chip_id, u32 shmem_base, u32 shmem2_base,
 539                             u8 port);
 540
 541 void bnx2x_period_func(struct link_params *params, struct link_vars *vars);
 542
 543 #endif /* BNX2X_LINK_H */