1 /* bnx2x_main.c: Broadcom Everest network driver.
3 * Copyright (c) 2007-2011 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20 #include <linux/module.h>
21 #include <linux/moduleparam.h>
22 #include <linux/kernel.h>
23 #include <linux/device.h> /* for dev_info() */
24 #include <linux/timer.h>
25 #include <linux/errno.h>
26 #include <linux/ioport.h>
27 #include <linux/slab.h>
28 #include <linux/interrupt.h>
29 #include <linux/pci.h>
30 #include <linux/init.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/bitops.h>
36 #include <linux/irq.h>
37 #include <linux/delay.h>
38 #include <asm/byteorder.h>
39 #include <linux/time.h>
40 #include <linux/ethtool.h>
41 #include <linux/mii.h>
43 #include <linux/if_vlan.h>
47 #include <net/checksum.h>
48 #include <net/ip6_checksum.h>
49 #include <linux/workqueue.h>
50 #include <linux/crc32.h>
51 #include <linux/crc32c.h>
52 #include <linux/prefetch.h>
53 #include <linux/zlib.h>
55 #include <linux/stringify.h>
56 #include <linux/vmalloc.h>
59 #include "bnx2x_init.h"
60 #include "bnx2x_init_ops.h"
61 #include "bnx2x_cmn.h"
62 #include "bnx2x_dcb.h"
65 #include <linux/firmware.h>
66 #include "bnx2x_fw_file_hdr.h"
68 #define FW_FILE_VERSION \
69 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
70 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
71 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
72 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
73 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
74 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
75 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
77 /* Time in jiffies before concluding the transmitter is hung */
78 #define TX_TIMEOUT (5*HZ)
80 static char version
[] __devinitdata
=
81 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
82 DRV_MODULE_NAME
" " DRV_MODULE_VERSION
" (" DRV_MODULE_RELDATE
")\n";
84 MODULE_AUTHOR("Eliezer Tamir");
85 MODULE_DESCRIPTION("Broadcom NetXtreme II "
86 "BCM57710/57711/57711E/"
87 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
88 "57840/57840_MF Driver");
89 MODULE_LICENSE("GPL");
90 MODULE_VERSION(DRV_MODULE_VERSION
);
91 MODULE_FIRMWARE(FW_FILE_NAME_E1
);
92 MODULE_FIRMWARE(FW_FILE_NAME_E1H
);
93 MODULE_FIRMWARE(FW_FILE_NAME_E2
);
95 static int multi_mode
= 1;
96 module_param(multi_mode
, int, 0);
97 MODULE_PARM_DESC(multi_mode
, " Multi queue mode "
98 "(0 Disable; 1 Enable (default))");
101 module_param(num_queues
, int, 0);
102 MODULE_PARM_DESC(num_queues
, " Number of queues for multi_mode=1"
103 " (default is as a number of CPUs)");
105 static int disable_tpa
;
106 module_param(disable_tpa
, int, 0);
107 MODULE_PARM_DESC(disable_tpa
, " Disable the TPA (LRO) feature");
109 #define INT_MODE_INTx 1
110 #define INT_MODE_MSI 2
112 module_param(int_mode
, int, 0);
113 MODULE_PARM_DESC(int_mode
, " Force interrupt mode other than MSI-X "
116 static int dropless_fc
;
117 module_param(dropless_fc
, int, 0);
118 MODULE_PARM_DESC(dropless_fc
, " Pause on exhausted host ring");
121 module_param(poll
, int, 0);
122 MODULE_PARM_DESC(poll
, " Use polling (for debug)");
124 static int mrrs
= -1;
125 module_param(mrrs
, int, 0);
126 MODULE_PARM_DESC(mrrs
, " Force Max Read Req Size (0..3) (for debug)");
129 module_param(debug
, int, 0);
130 MODULE_PARM_DESC(debug
, " Default debug msglevel");
134 struct workqueue_struct
*bnx2x_wq
;
136 enum bnx2x_board_type
{
150 /* indexed by board_type, above */
153 } board_info
[] __devinitdata
= {
154 { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
155 { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
156 { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
157 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
158 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
159 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
160 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
161 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
162 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
163 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
164 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit "
165 "Ethernet Multi Function"}
168 #ifndef PCI_DEVICE_ID_NX2_57710
169 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
171 #ifndef PCI_DEVICE_ID_NX2_57711
172 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
174 #ifndef PCI_DEVICE_ID_NX2_57711E
175 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
177 #ifndef PCI_DEVICE_ID_NX2_57712
178 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
180 #ifndef PCI_DEVICE_ID_NX2_57712_MF
181 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
183 #ifndef PCI_DEVICE_ID_NX2_57800
184 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
186 #ifndef PCI_DEVICE_ID_NX2_57800_MF
187 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
189 #ifndef PCI_DEVICE_ID_NX2_57810
190 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
192 #ifndef PCI_DEVICE_ID_NX2_57810_MF
193 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
195 #ifndef PCI_DEVICE_ID_NX2_57840
196 #define PCI_DEVICE_ID_NX2_57840 CHIP_NUM_57840
198 #ifndef PCI_DEVICE_ID_NX2_57840_MF
199 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
201 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl
) = {
202 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57710
), BCM57710
},
203 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57711
), BCM57711
},
204 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57711E
), BCM57711E
},
205 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57712
), BCM57712
},
206 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57712_MF
), BCM57712_MF
},
207 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57800
), BCM57800
},
208 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57800_MF
), BCM57800_MF
},
209 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57810
), BCM57810
},
210 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57810_MF
), BCM57810_MF
},
211 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57840
), BCM57840
},
212 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57840_MF
), BCM57840_MF
},
216 MODULE_DEVICE_TABLE(pci
, bnx2x_pci_tbl
);
218 /****************************************************************************
219 * General service functions
220 ****************************************************************************/
222 static inline void __storm_memset_dma_mapping(struct bnx2x
*bp
,
223 u32 addr
, dma_addr_t mapping
)
225 REG_WR(bp
, addr
, U64_LO(mapping
));
226 REG_WR(bp
, addr
+ 4, U64_HI(mapping
));
229 static inline void storm_memset_spq_addr(struct bnx2x
*bp
,
230 dma_addr_t mapping
, u16 abs_fid
)
232 u32 addr
= XSEM_REG_FAST_MEMORY
+
233 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid
);
235 __storm_memset_dma_mapping(bp
, addr
, mapping
);
238 static inline void storm_memset_vf_to_pf(struct bnx2x
*bp
, u16 abs_fid
,
241 REG_WR8(bp
, BAR_XSTRORM_INTMEM
+ XSTORM_VF_TO_PF_OFFSET(abs_fid
),
243 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+ CSTORM_VF_TO_PF_OFFSET(abs_fid
),
245 REG_WR8(bp
, BAR_TSTRORM_INTMEM
+ TSTORM_VF_TO_PF_OFFSET(abs_fid
),
247 REG_WR8(bp
, BAR_USTRORM_INTMEM
+ USTORM_VF_TO_PF_OFFSET(abs_fid
),
251 static inline void storm_memset_func_en(struct bnx2x
*bp
, u16 abs_fid
,
254 REG_WR8(bp
, BAR_XSTRORM_INTMEM
+ XSTORM_FUNC_EN_OFFSET(abs_fid
),
256 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+ CSTORM_FUNC_EN_OFFSET(abs_fid
),
258 REG_WR8(bp
, BAR_TSTRORM_INTMEM
+ TSTORM_FUNC_EN_OFFSET(abs_fid
),
260 REG_WR8(bp
, BAR_USTRORM_INTMEM
+ USTORM_FUNC_EN_OFFSET(abs_fid
),
264 static inline void storm_memset_eq_data(struct bnx2x
*bp
,
265 struct event_ring_data
*eq_data
,
268 size_t size
= sizeof(struct event_ring_data
);
270 u32 addr
= BAR_CSTRORM_INTMEM
+ CSTORM_EVENT_RING_DATA_OFFSET(pfid
);
272 __storm_memset_struct(bp
, addr
, size
, (u32
*)eq_data
);
275 static inline void storm_memset_eq_prod(struct bnx2x
*bp
, u16 eq_prod
,
278 u32 addr
= BAR_CSTRORM_INTMEM
+ CSTORM_EVENT_RING_PROD_OFFSET(pfid
);
279 REG_WR16(bp
, addr
, eq_prod
);
283 * locking is done by mcp
285 static void bnx2x_reg_wr_ind(struct bnx2x
*bp
, u32 addr
, u32 val
)
287 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_ADDRESS
, addr
);
288 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_DATA
, val
);
289 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_ADDRESS
,
290 PCICFG_VENDOR_ID_OFFSET
);
293 static u32
bnx2x_reg_rd_ind(struct bnx2x
*bp
, u32 addr
)
297 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_ADDRESS
, addr
);
298 pci_read_config_dword(bp
->pdev
, PCICFG_GRC_DATA
, &val
);
299 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_ADDRESS
,
300 PCICFG_VENDOR_ID_OFFSET
);
305 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
306 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
307 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
308 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
309 #define DMAE_DP_DST_NONE "dst_addr [none]"
311 static void bnx2x_dp_dmae(struct bnx2x
*bp
, struct dmae_command
*dmae
,
314 u32 src_type
= dmae
->opcode
& DMAE_COMMAND_SRC
;
316 switch (dmae
->opcode
& DMAE_COMMAND_DST
) {
317 case DMAE_CMD_DST_PCI
:
318 if (src_type
== DMAE_CMD_SRC_PCI
)
319 DP(msglvl
, "DMAE: opcode 0x%08x\n"
320 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
321 "comp_addr [%x:%08x], comp_val 0x%08x\n",
322 dmae
->opcode
, dmae
->src_addr_hi
, dmae
->src_addr_lo
,
323 dmae
->len
, dmae
->dst_addr_hi
, dmae
->dst_addr_lo
,
324 dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
327 DP(msglvl
, "DMAE: opcode 0x%08x\n"
328 "src [%08x], len [%d*4], dst [%x:%08x]\n"
329 "comp_addr [%x:%08x], comp_val 0x%08x\n",
330 dmae
->opcode
, dmae
->src_addr_lo
>> 2,
331 dmae
->len
, dmae
->dst_addr_hi
, dmae
->dst_addr_lo
,
332 dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
335 case DMAE_CMD_DST_GRC
:
336 if (src_type
== DMAE_CMD_SRC_PCI
)
337 DP(msglvl
, "DMAE: opcode 0x%08x\n"
338 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
339 "comp_addr [%x:%08x], comp_val 0x%08x\n",
340 dmae
->opcode
, dmae
->src_addr_hi
, dmae
->src_addr_lo
,
341 dmae
->len
, dmae
->dst_addr_lo
>> 2,
342 dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
345 DP(msglvl
, "DMAE: opcode 0x%08x\n"
346 "src [%08x], len [%d*4], dst [%08x]\n"
347 "comp_addr [%x:%08x], comp_val 0x%08x\n",
348 dmae
->opcode
, dmae
->src_addr_lo
>> 2,
349 dmae
->len
, dmae
->dst_addr_lo
>> 2,
350 dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
354 if (src_type
== DMAE_CMD_SRC_PCI
)
355 DP(msglvl
, "DMAE: opcode 0x%08x\n"
356 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n"
357 "comp_addr [%x:%08x] comp_val 0x%08x\n",
358 dmae
->opcode
, dmae
->src_addr_hi
, dmae
->src_addr_lo
,
359 dmae
->len
, dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
362 DP(msglvl
, "DMAE: opcode 0x%08x\n"
363 "src_addr [%08x] len [%d * 4] dst_addr [none]\n"
364 "comp_addr [%x:%08x] comp_val 0x%08x\n",
365 dmae
->opcode
, dmae
->src_addr_lo
>> 2,
366 dmae
->len
, dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
373 /* copy command into DMAE command memory and set DMAE command go */
374 void bnx2x_post_dmae(struct bnx2x
*bp
, struct dmae_command
*dmae
, int idx
)
379 cmd_offset
= (DMAE_REG_CMD_MEM
+ sizeof(struct dmae_command
) * idx
);
380 for (i
= 0; i
< (sizeof(struct dmae_command
)/4); i
++) {
381 REG_WR(bp
, cmd_offset
+ i
*4, *(((u32
*)dmae
) + i
));
383 DP(BNX2X_MSG_OFF
, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
384 idx
, i
, cmd_offset
+ i
*4, *(((u32
*)dmae
) + i
));
386 REG_WR(bp
, dmae_reg_go_c
[idx
], 1);
389 u32
bnx2x_dmae_opcode_add_comp(u32 opcode
, u8 comp_type
)
391 return opcode
| ((comp_type
<< DMAE_COMMAND_C_DST_SHIFT
) |
395 u32
bnx2x_dmae_opcode_clr_src_reset(u32 opcode
)
397 return opcode
& ~DMAE_CMD_SRC_RESET
;
400 u32
bnx2x_dmae_opcode(struct bnx2x
*bp
, u8 src_type
, u8 dst_type
,
401 bool with_comp
, u8 comp_type
)
405 opcode
|= ((src_type
<< DMAE_COMMAND_SRC_SHIFT
) |
406 (dst_type
<< DMAE_COMMAND_DST_SHIFT
));
408 opcode
|= (DMAE_CMD_SRC_RESET
| DMAE_CMD_DST_RESET
);
410 opcode
|= (BP_PORT(bp
) ? DMAE_CMD_PORT_1
: DMAE_CMD_PORT_0
);
411 opcode
|= ((BP_VN(bp
) << DMAE_CMD_E1HVN_SHIFT
) |
412 (BP_VN(bp
) << DMAE_COMMAND_DST_VN_SHIFT
));
413 opcode
|= (DMAE_COM_SET_ERR
<< DMAE_COMMAND_ERR_POLICY_SHIFT
);
416 opcode
|= DMAE_CMD_ENDIANITY_B_DW_SWAP
;
418 opcode
|= DMAE_CMD_ENDIANITY_DW_SWAP
;
421 opcode
= bnx2x_dmae_opcode_add_comp(opcode
, comp_type
);
425 static void bnx2x_prep_dmae_with_comp(struct bnx2x
*bp
,
426 struct dmae_command
*dmae
,
427 u8 src_type
, u8 dst_type
)
429 memset(dmae
, 0, sizeof(struct dmae_command
));
432 dmae
->opcode
= bnx2x_dmae_opcode(bp
, src_type
, dst_type
,
433 true, DMAE_COMP_PCI
);
435 /* fill in the completion parameters */
436 dmae
->comp_addr_lo
= U64_LO(bnx2x_sp_mapping(bp
, wb_comp
));
437 dmae
->comp_addr_hi
= U64_HI(bnx2x_sp_mapping(bp
, wb_comp
));
438 dmae
->comp_val
= DMAE_COMP_VAL
;
441 /* issue a dmae command over the init-channel and wailt for completion */
442 static int bnx2x_issue_dmae_with_comp(struct bnx2x
*bp
,
443 struct dmae_command
*dmae
)
445 u32
*wb_comp
= bnx2x_sp(bp
, wb_comp
);
446 int cnt
= CHIP_REV_IS_SLOW(bp
) ? (400000) : 4000;
449 DP(BNX2X_MSG_OFF
, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n",
450 bp
->slowpath
->wb_data
[0], bp
->slowpath
->wb_data
[1],
451 bp
->slowpath
->wb_data
[2], bp
->slowpath
->wb_data
[3]);
454 * Lock the dmae channel. Disable BHs to prevent a dead-lock
455 * as long as this code is called both from syscall context and
456 * from ndo_set_rx_mode() flow that may be called from BH.
458 spin_lock_bh(&bp
->dmae_lock
);
460 /* reset completion */
463 /* post the command on the channel used for initializations */
464 bnx2x_post_dmae(bp
, dmae
, INIT_DMAE_C(bp
));
466 /* wait for completion */
468 while ((*wb_comp
& ~DMAE_PCI_ERR_FLAG
) != DMAE_COMP_VAL
) {
469 DP(BNX2X_MSG_OFF
, "wb_comp 0x%08x\n", *wb_comp
);
472 BNX2X_ERR("DMAE timeout!\n");
479 if (*wb_comp
& DMAE_PCI_ERR_FLAG
) {
480 BNX2X_ERR("DMAE PCI error!\n");
484 DP(BNX2X_MSG_OFF
, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n",
485 bp
->slowpath
->wb_data
[0], bp
->slowpath
->wb_data
[1],
486 bp
->slowpath
->wb_data
[2], bp
->slowpath
->wb_data
[3]);
489 spin_unlock_bh(&bp
->dmae_lock
);
493 void bnx2x_write_dmae(struct bnx2x
*bp
, dma_addr_t dma_addr
, u32 dst_addr
,
496 struct dmae_command dmae
;
498 if (!bp
->dmae_ready
) {
499 u32
*data
= bnx2x_sp(bp
, wb_data
[0]);
501 DP(BNX2X_MSG_OFF
, "DMAE is not ready (dst_addr %08x len32 %d)"
502 " using indirect\n", dst_addr
, len32
);
503 bnx2x_init_ind_wr(bp
, dst_addr
, data
, len32
);
507 /* set opcode and fixed command fields */
508 bnx2x_prep_dmae_with_comp(bp
, &dmae
, DMAE_SRC_PCI
, DMAE_DST_GRC
);
510 /* fill in addresses and len */
511 dmae
.src_addr_lo
= U64_LO(dma_addr
);
512 dmae
.src_addr_hi
= U64_HI(dma_addr
);
513 dmae
.dst_addr_lo
= dst_addr
>> 2;
514 dmae
.dst_addr_hi
= 0;
517 bnx2x_dp_dmae(bp
, &dmae
, BNX2X_MSG_OFF
);
519 /* issue the command and wait for completion */
520 bnx2x_issue_dmae_with_comp(bp
, &dmae
);
523 void bnx2x_read_dmae(struct bnx2x
*bp
, u32 src_addr
, u32 len32
)
525 struct dmae_command dmae
;
527 if (!bp
->dmae_ready
) {
528 u32
*data
= bnx2x_sp(bp
, wb_data
[0]);
531 DP(BNX2X_MSG_OFF
, "DMAE is not ready (src_addr %08x len32 %d)"
532 " using indirect\n", src_addr
, len32
);
533 for (i
= 0; i
< len32
; i
++)
534 data
[i
] = bnx2x_reg_rd_ind(bp
, src_addr
+ i
*4);
538 /* set opcode and fixed command fields */
539 bnx2x_prep_dmae_with_comp(bp
, &dmae
, DMAE_SRC_GRC
, DMAE_DST_PCI
);
541 /* fill in addresses and len */
542 dmae
.src_addr_lo
= src_addr
>> 2;
543 dmae
.src_addr_hi
= 0;
544 dmae
.dst_addr_lo
= U64_LO(bnx2x_sp_mapping(bp
, wb_data
));
545 dmae
.dst_addr_hi
= U64_HI(bnx2x_sp_mapping(bp
, wb_data
));
548 bnx2x_dp_dmae(bp
, &dmae
, BNX2X_MSG_OFF
);
550 /* issue the command and wait for completion */
551 bnx2x_issue_dmae_with_comp(bp
, &dmae
);
554 static void bnx2x_write_dmae_phys_len(struct bnx2x
*bp
, dma_addr_t phys_addr
,
557 int dmae_wr_max
= DMAE_LEN32_WR_MAX(bp
);
560 while (len
> dmae_wr_max
) {
561 bnx2x_write_dmae(bp
, phys_addr
+ offset
,
562 addr
+ offset
, dmae_wr_max
);
563 offset
+= dmae_wr_max
* 4;
567 bnx2x_write_dmae(bp
, phys_addr
+ offset
, addr
+ offset
, len
);
570 /* used only for slowpath so not inlined */
571 static void bnx2x_wb_wr(struct bnx2x
*bp
, int reg
, u32 val_hi
, u32 val_lo
)
575 wb_write
[0] = val_hi
;
576 wb_write
[1] = val_lo
;
577 REG_WR_DMAE(bp
, reg
, wb_write
, 2);
581 static u64
bnx2x_wb_rd(struct bnx2x
*bp
, int reg
)
585 REG_RD_DMAE(bp
, reg
, wb_data
, 2);
587 return HILO_U64(wb_data
[0], wb_data
[1]);
591 static int bnx2x_mc_assert(struct bnx2x
*bp
)
595 u32 row0
, row1
, row2
, row3
;
598 last_idx
= REG_RD8(bp
, BAR_XSTRORM_INTMEM
+
599 XSTORM_ASSERT_LIST_INDEX_OFFSET
);
601 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx
);
603 /* print the asserts */
604 for (i
= 0; i
< STROM_ASSERT_ARRAY_SIZE
; i
++) {
606 row0
= REG_RD(bp
, BAR_XSTRORM_INTMEM
+
607 XSTORM_ASSERT_LIST_OFFSET(i
));
608 row1
= REG_RD(bp
, BAR_XSTRORM_INTMEM
+
609 XSTORM_ASSERT_LIST_OFFSET(i
) + 4);
610 row2
= REG_RD(bp
, BAR_XSTRORM_INTMEM
+
611 XSTORM_ASSERT_LIST_OFFSET(i
) + 8);
612 row3
= REG_RD(bp
, BAR_XSTRORM_INTMEM
+
613 XSTORM_ASSERT_LIST_OFFSET(i
) + 12);
615 if (row0
!= COMMON_ASM_INVALID_ASSERT_OPCODE
) {
616 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
617 " 0x%08x 0x%08x 0x%08x\n",
618 i
, row3
, row2
, row1
, row0
);
626 last_idx
= REG_RD8(bp
, BAR_TSTRORM_INTMEM
+
627 TSTORM_ASSERT_LIST_INDEX_OFFSET
);
629 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx
);
631 /* print the asserts */
632 for (i
= 0; i
< STROM_ASSERT_ARRAY_SIZE
; i
++) {
634 row0
= REG_RD(bp
, BAR_TSTRORM_INTMEM
+
635 TSTORM_ASSERT_LIST_OFFSET(i
));
636 row1
= REG_RD(bp
, BAR_TSTRORM_INTMEM
+
637 TSTORM_ASSERT_LIST_OFFSET(i
) + 4);
638 row2
= REG_RD(bp
, BAR_TSTRORM_INTMEM
+
639 TSTORM_ASSERT_LIST_OFFSET(i
) + 8);
640 row3
= REG_RD(bp
, BAR_TSTRORM_INTMEM
+
641 TSTORM_ASSERT_LIST_OFFSET(i
) + 12);
643 if (row0
!= COMMON_ASM_INVALID_ASSERT_OPCODE
) {
644 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
645 " 0x%08x 0x%08x 0x%08x\n",
646 i
, row3
, row2
, row1
, row0
);
654 last_idx
= REG_RD8(bp
, BAR_CSTRORM_INTMEM
+
655 CSTORM_ASSERT_LIST_INDEX_OFFSET
);
657 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx
);
659 /* print the asserts */
660 for (i
= 0; i
< STROM_ASSERT_ARRAY_SIZE
; i
++) {
662 row0
= REG_RD(bp
, BAR_CSTRORM_INTMEM
+
663 CSTORM_ASSERT_LIST_OFFSET(i
));
664 row1
= REG_RD(bp
, BAR_CSTRORM_INTMEM
+
665 CSTORM_ASSERT_LIST_OFFSET(i
) + 4);
666 row2
= REG_RD(bp
, BAR_CSTRORM_INTMEM
+
667 CSTORM_ASSERT_LIST_OFFSET(i
) + 8);
668 row3
= REG_RD(bp
, BAR_CSTRORM_INTMEM
+
669 CSTORM_ASSERT_LIST_OFFSET(i
) + 12);
671 if (row0
!= COMMON_ASM_INVALID_ASSERT_OPCODE
) {
672 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
673 " 0x%08x 0x%08x 0x%08x\n",
674 i
, row3
, row2
, row1
, row0
);
682 last_idx
= REG_RD8(bp
, BAR_USTRORM_INTMEM
+
683 USTORM_ASSERT_LIST_INDEX_OFFSET
);
685 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx
);
687 /* print the asserts */
688 for (i
= 0; i
< STROM_ASSERT_ARRAY_SIZE
; i
++) {
690 row0
= REG_RD(bp
, BAR_USTRORM_INTMEM
+
691 USTORM_ASSERT_LIST_OFFSET(i
));
692 row1
= REG_RD(bp
, BAR_USTRORM_INTMEM
+
693 USTORM_ASSERT_LIST_OFFSET(i
) + 4);
694 row2
= REG_RD(bp
, BAR_USTRORM_INTMEM
+
695 USTORM_ASSERT_LIST_OFFSET(i
) + 8);
696 row3
= REG_RD(bp
, BAR_USTRORM_INTMEM
+
697 USTORM_ASSERT_LIST_OFFSET(i
) + 12);
699 if (row0
!= COMMON_ASM_INVALID_ASSERT_OPCODE
) {
700 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
701 " 0x%08x 0x%08x 0x%08x\n",
702 i
, row3
, row2
, row1
, row0
);
712 void bnx2x_fw_dump_lvl(struct bnx2x
*bp
, const char *lvl
)
718 u32 trace_shmem_base
;
720 BNX2X_ERR("NO MCP - can not dump\n");
723 netdev_printk(lvl
, bp
->dev
, "bc %d.%d.%d\n",
724 (bp
->common
.bc_ver
& 0xff0000) >> 16,
725 (bp
->common
.bc_ver
& 0xff00) >> 8,
726 (bp
->common
.bc_ver
& 0xff));
728 val
= REG_RD(bp
, MCP_REG_MCPR_CPU_PROGRAM_COUNTER
);
729 if (val
== REG_RD(bp
, MCP_REG_MCPR_CPU_PROGRAM_COUNTER
))
730 printk("%s" "MCP PC at 0x%x\n", lvl
, val
);
732 if (BP_PATH(bp
) == 0)
733 trace_shmem_base
= bp
->common
.shmem_base
;
735 trace_shmem_base
= SHMEM2_RD(bp
, other_shmem_base_addr
);
736 addr
= trace_shmem_base
- 0x0800 + 4;
737 mark
= REG_RD(bp
, addr
);
738 mark
= (CHIP_IS_E1x(bp
) ? MCP_REG_MCPR_SCRATCH
: MCP_A_REG_MCPR_SCRATCH
)
739 + ((mark
+ 0x3) & ~0x3) - 0x08000000;
740 printk("%s" "begin fw dump (mark 0x%x)\n", lvl
, mark
);
743 for (offset
= mark
; offset
<= trace_shmem_base
; offset
+= 0x8*4) {
744 for (word
= 0; word
< 8; word
++)
745 data
[word
] = htonl(REG_RD(bp
, offset
+ 4*word
));
747 pr_cont("%s", (char *)data
);
749 for (offset
= addr
+ 4; offset
<= mark
; offset
+= 0x8*4) {
750 for (word
= 0; word
< 8; word
++)
751 data
[word
] = htonl(REG_RD(bp
, offset
+ 4*word
));
753 pr_cont("%s", (char *)data
);
755 printk("%s" "end of fw dump\n", lvl
);
758 static inline void bnx2x_fw_dump(struct bnx2x
*bp
)
760 bnx2x_fw_dump_lvl(bp
, KERN_ERR
);
763 void bnx2x_panic_dump(struct bnx2x
*bp
)
767 struct hc_sp_status_block_data sp_sb_data
;
768 int func
= BP_FUNC(bp
);
769 #ifdef BNX2X_STOP_ON_ERROR
770 u16 start
= 0, end
= 0;
774 bp
->stats_state
= STATS_STATE_DISABLED
;
775 DP(BNX2X_MSG_STATS
, "stats_state - DISABLED\n");
777 BNX2X_ERR("begin crash dump -----------------\n");
781 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)"
782 " spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
783 bp
->def_idx
, bp
->def_att_idx
, bp
->attn_state
,
784 bp
->spq_prod_idx
, bp
->stats_counter
);
785 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
786 bp
->def_status_blk
->atten_status_block
.attn_bits
,
787 bp
->def_status_blk
->atten_status_block
.attn_bits_ack
,
788 bp
->def_status_blk
->atten_status_block
.status_block_id
,
789 bp
->def_status_blk
->atten_status_block
.attn_bits_index
);
791 for (i
= 0; i
< HC_SP_SB_MAX_INDICES
; i
++)
793 bp
->def_status_blk
->sp_sb
.index_values
[i
],
794 (i
== HC_SP_SB_MAX_INDICES
- 1) ? ") " : " ");
796 for (i
= 0; i
< sizeof(struct hc_sp_status_block_data
)/sizeof(u32
); i
++)
797 *((u32
*)&sp_sb_data
+ i
) = REG_RD(bp
, BAR_CSTRORM_INTMEM
+
798 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func
) +
801 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
802 sp_sb_data
.igu_sb_id
,
803 sp_sb_data
.igu_seg_id
,
804 sp_sb_data
.p_func
.pf_id
,
805 sp_sb_data
.p_func
.vnic_id
,
806 sp_sb_data
.p_func
.vf_id
,
807 sp_sb_data
.p_func
.vf_valid
,
811 for_each_eth_queue(bp
, i
) {
812 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
814 struct hc_status_block_data_e2 sb_data_e2
;
815 struct hc_status_block_data_e1x sb_data_e1x
;
816 struct hc_status_block_sm
*hc_sm_p
=
818 sb_data_e1x
.common
.state_machine
:
819 sb_data_e2
.common
.state_machine
;
820 struct hc_index_data
*hc_index_p
=
822 sb_data_e1x
.index_data
:
823 sb_data_e2
.index_data
;
826 struct bnx2x_fp_txdata txdata
;
829 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)"
830 " rx_comp_prod(0x%x)"
831 " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
832 i
, fp
->rx_bd_prod
, fp
->rx_bd_cons
,
834 fp
->rx_comp_cons
, le16_to_cpu(*fp
->rx_cons_sb
));
835 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)"
836 " fp_hc_idx(0x%x)\n",
837 fp
->rx_sge_prod
, fp
->last_max_sge
,
838 le16_to_cpu(fp
->fp_hc_idx
));
841 for_each_cos_in_tx_queue(fp
, cos
)
843 txdata
= fp
->txdata
[cos
];
844 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)"
845 " tx_bd_prod(0x%x) tx_bd_cons(0x%x)"
846 " *tx_cons_sb(0x%x)\n",
847 i
, txdata
.tx_pkt_prod
,
848 txdata
.tx_pkt_cons
, txdata
.tx_bd_prod
,
850 le16_to_cpu(*txdata
.tx_cons_sb
));
853 loop
= CHIP_IS_E1x(bp
) ?
854 HC_SB_MAX_INDICES_E1X
: HC_SB_MAX_INDICES_E2
;
862 BNX2X_ERR(" run indexes (");
863 for (j
= 0; j
< HC_SB_MAX_SM
; j
++)
865 fp
->sb_running_index
[j
],
866 (j
== HC_SB_MAX_SM
- 1) ? ")" : " ");
868 BNX2X_ERR(" indexes (");
869 for (j
= 0; j
< loop
; j
++)
871 fp
->sb_index_values
[j
],
872 (j
== loop
- 1) ? ")" : " ");
874 data_size
= CHIP_IS_E1x(bp
) ?
875 sizeof(struct hc_status_block_data_e1x
) :
876 sizeof(struct hc_status_block_data_e2
);
877 data_size
/= sizeof(u32
);
878 sb_data_p
= CHIP_IS_E1x(bp
) ?
879 (u32
*)&sb_data_e1x
:
881 /* copy sb data in here */
882 for (j
= 0; j
< data_size
; j
++)
883 *(sb_data_p
+ j
) = REG_RD(bp
, BAR_CSTRORM_INTMEM
+
884 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp
->fw_sb_id
) +
887 if (!CHIP_IS_E1x(bp
)) {
888 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) "
889 "vnic_id(0x%x) same_igu_sb_1b(0x%x) "
891 sb_data_e2
.common
.p_func
.pf_id
,
892 sb_data_e2
.common
.p_func
.vf_id
,
893 sb_data_e2
.common
.p_func
.vf_valid
,
894 sb_data_e2
.common
.p_func
.vnic_id
,
895 sb_data_e2
.common
.same_igu_sb_1b
,
896 sb_data_e2
.common
.state
);
898 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) "
899 "vnic_id(0x%x) same_igu_sb_1b(0x%x) "
901 sb_data_e1x
.common
.p_func
.pf_id
,
902 sb_data_e1x
.common
.p_func
.vf_id
,
903 sb_data_e1x
.common
.p_func
.vf_valid
,
904 sb_data_e1x
.common
.p_func
.vnic_id
,
905 sb_data_e1x
.common
.same_igu_sb_1b
,
906 sb_data_e1x
.common
.state
);
910 for (j
= 0; j
< HC_SB_MAX_SM
; j
++) {
911 pr_cont("SM[%d] __flags (0x%x) "
912 "igu_sb_id (0x%x) igu_seg_id(0x%x) "
913 "time_to_expire (0x%x) "
914 "timer_value(0x%x)\n", j
,
916 hc_sm_p
[j
].igu_sb_id
,
917 hc_sm_p
[j
].igu_seg_id
,
918 hc_sm_p
[j
].time_to_expire
,
919 hc_sm_p
[j
].timer_value
);
923 for (j
= 0; j
< loop
; j
++) {
924 pr_cont("INDEX[%d] flags (0x%x) "
925 "timeout (0x%x)\n", j
,
927 hc_index_p
[j
].timeout
);
931 #ifdef BNX2X_STOP_ON_ERROR
934 for_each_rx_queue(bp
, i
) {
935 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
937 start
= RX_BD(le16_to_cpu(*fp
->rx_cons_sb
) - 10);
938 end
= RX_BD(le16_to_cpu(*fp
->rx_cons_sb
) + 503);
939 for (j
= start
; j
!= end
; j
= RX_BD(j
+ 1)) {
940 u32
*rx_bd
= (u32
*)&fp
->rx_desc_ring
[j
];
941 struct sw_rx_bd
*sw_bd
= &fp
->rx_buf_ring
[j
];
943 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
944 i
, j
, rx_bd
[1], rx_bd
[0], sw_bd
->skb
);
947 start
= RX_SGE(fp
->rx_sge_prod
);
948 end
= RX_SGE(fp
->last_max_sge
);
949 for (j
= start
; j
!= end
; j
= RX_SGE(j
+ 1)) {
950 u32
*rx_sge
= (u32
*)&fp
->rx_sge_ring
[j
];
951 struct sw_rx_page
*sw_page
= &fp
->rx_page_ring
[j
];
953 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
954 i
, j
, rx_sge
[1], rx_sge
[0], sw_page
->page
);
957 start
= RCQ_BD(fp
->rx_comp_cons
- 10);
958 end
= RCQ_BD(fp
->rx_comp_cons
+ 503);
959 for (j
= start
; j
!= end
; j
= RCQ_BD(j
+ 1)) {
960 u32
*cqe
= (u32
*)&fp
->rx_comp_ring
[j
];
962 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
963 i
, j
, cqe
[0], cqe
[1], cqe
[2], cqe
[3]);
968 for_each_tx_queue(bp
, i
) {
969 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
970 for_each_cos_in_tx_queue(fp
, cos
) {
971 struct bnx2x_fp_txdata
*txdata
= &fp
->txdata
[cos
];
973 start
= TX_BD(le16_to_cpu(*txdata
->tx_cons_sb
) - 10);
974 end
= TX_BD(le16_to_cpu(*txdata
->tx_cons_sb
) + 245);
975 for (j
= start
; j
!= end
; j
= TX_BD(j
+ 1)) {
976 struct sw_tx_bd
*sw_bd
=
977 &txdata
->tx_buf_ring
[j
];
979 BNX2X_ERR("fp%d: txdata %d, "
980 "packet[%x]=[%p,%x]\n",
981 i
, cos
, j
, sw_bd
->skb
,
985 start
= TX_BD(txdata
->tx_bd_cons
- 10);
986 end
= TX_BD(txdata
->tx_bd_cons
+ 254);
987 for (j
= start
; j
!= end
; j
= TX_BD(j
+ 1)) {
988 u32
*tx_bd
= (u32
*)&txdata
->tx_desc_ring
[j
];
990 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]="
992 i
, cos
, j
, tx_bd
[0], tx_bd
[1],
1000 BNX2X_ERR("end crash dump -----------------\n");
1004 * FLR Support for E2
1006 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1009 #define FLR_WAIT_USEC 10000 /* 10 miliseconds */
1010 #define FLR_WAIT_INTERAVAL 50 /* usec */
1011 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERAVAL) /* 200 */
1013 struct pbf_pN_buf_regs
{
1020 struct pbf_pN_cmd_regs
{
1026 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x
*bp
,
1027 struct pbf_pN_buf_regs
*regs
,
1030 u32 init_crd
, crd
, crd_start
, crd_freed
, crd_freed_start
;
1031 u32 cur_cnt
= poll_count
;
1033 crd_freed
= crd_freed_start
= REG_RD(bp
, regs
->crd_freed
);
1034 crd
= crd_start
= REG_RD(bp
, regs
->crd
);
1035 init_crd
= REG_RD(bp
, regs
->init_crd
);
1037 DP(BNX2X_MSG_SP
, "INIT CREDIT[%d] : %x\n", regs
->pN
, init_crd
);
1038 DP(BNX2X_MSG_SP
, "CREDIT[%d] : s:%x\n", regs
->pN
, crd
);
1039 DP(BNX2X_MSG_SP
, "CREDIT_FREED[%d]: s:%x\n", regs
->pN
, crd_freed
);
1041 while ((crd
!= init_crd
) && ((u32
)SUB_S32(crd_freed
, crd_freed_start
) <
1042 (init_crd
- crd_start
))) {
1044 udelay(FLR_WAIT_INTERAVAL
);
1045 crd
= REG_RD(bp
, regs
->crd
);
1046 crd_freed
= REG_RD(bp
, regs
->crd_freed
);
1048 DP(BNX2X_MSG_SP
, "PBF tx buffer[%d] timed out\n",
1050 DP(BNX2X_MSG_SP
, "CREDIT[%d] : c:%x\n",
1052 DP(BNX2X_MSG_SP
, "CREDIT_FREED[%d]: c:%x\n",
1053 regs
->pN
, crd_freed
);
1057 DP(BNX2X_MSG_SP
, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1058 poll_count
-cur_cnt
, FLR_WAIT_INTERAVAL
, regs
->pN
);
1061 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x
*bp
,
1062 struct pbf_pN_cmd_regs
*regs
,
1065 u32 occup
, to_free
, freed
, freed_start
;
1066 u32 cur_cnt
= poll_count
;
1068 occup
= to_free
= REG_RD(bp
, regs
->lines_occup
);
1069 freed
= freed_start
= REG_RD(bp
, regs
->lines_freed
);
1071 DP(BNX2X_MSG_SP
, "OCCUPANCY[%d] : s:%x\n", regs
->pN
, occup
);
1072 DP(BNX2X_MSG_SP
, "LINES_FREED[%d] : s:%x\n", regs
->pN
, freed
);
1074 while (occup
&& ((u32
)SUB_S32(freed
, freed_start
) < to_free
)) {
1076 udelay(FLR_WAIT_INTERAVAL
);
1077 occup
= REG_RD(bp
, regs
->lines_occup
);
1078 freed
= REG_RD(bp
, regs
->lines_freed
);
1080 DP(BNX2X_MSG_SP
, "PBF cmd queue[%d] timed out\n",
1082 DP(BNX2X_MSG_SP
, "OCCUPANCY[%d] : s:%x\n",
1084 DP(BNX2X_MSG_SP
, "LINES_FREED[%d] : s:%x\n",
1089 DP(BNX2X_MSG_SP
, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1090 poll_count
-cur_cnt
, FLR_WAIT_INTERAVAL
, regs
->pN
);
1093 static inline u32
bnx2x_flr_clnup_reg_poll(struct bnx2x
*bp
, u32 reg
,
1094 u32 expected
, u32 poll_count
)
1096 u32 cur_cnt
= poll_count
;
1099 while ((val
= REG_RD(bp
, reg
)) != expected
&& cur_cnt
--)
1100 udelay(FLR_WAIT_INTERAVAL
);
1105 static inline int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x
*bp
, u32 reg
,
1106 char *msg
, u32 poll_cnt
)
1108 u32 val
= bnx2x_flr_clnup_reg_poll(bp
, reg
, 0, poll_cnt
);
1110 BNX2X_ERR("%s usage count=%d\n", msg
, val
);
1116 static u32
bnx2x_flr_clnup_poll_count(struct bnx2x
*bp
)
1118 /* adjust polling timeout */
1119 if (CHIP_REV_IS_EMUL(bp
))
1120 return FLR_POLL_CNT
* 2000;
1122 if (CHIP_REV_IS_FPGA(bp
))
1123 return FLR_POLL_CNT
* 120;
1125 return FLR_POLL_CNT
;
1128 static void bnx2x_tx_hw_flushed(struct bnx2x
*bp
, u32 poll_count
)
1130 struct pbf_pN_cmd_regs cmd_regs
[] = {
1131 {0, (CHIP_IS_E3B0(bp
)) ?
1132 PBF_REG_TQ_OCCUPANCY_Q0
:
1133 PBF_REG_P0_TQ_OCCUPANCY
,
1134 (CHIP_IS_E3B0(bp
)) ?
1135 PBF_REG_TQ_LINES_FREED_CNT_Q0
:
1136 PBF_REG_P0_TQ_LINES_FREED_CNT
},
1137 {1, (CHIP_IS_E3B0(bp
)) ?
1138 PBF_REG_TQ_OCCUPANCY_Q1
:
1139 PBF_REG_P1_TQ_OCCUPANCY
,
1140 (CHIP_IS_E3B0(bp
)) ?
1141 PBF_REG_TQ_LINES_FREED_CNT_Q1
:
1142 PBF_REG_P1_TQ_LINES_FREED_CNT
},
1143 {4, (CHIP_IS_E3B0(bp
)) ?
1144 PBF_REG_TQ_OCCUPANCY_LB_Q
:
1145 PBF_REG_P4_TQ_OCCUPANCY
,
1146 (CHIP_IS_E3B0(bp
)) ?
1147 PBF_REG_TQ_LINES_FREED_CNT_LB_Q
:
1148 PBF_REG_P4_TQ_LINES_FREED_CNT
}
1151 struct pbf_pN_buf_regs buf_regs
[] = {
1152 {0, (CHIP_IS_E3B0(bp
)) ?
1153 PBF_REG_INIT_CRD_Q0
:
1154 PBF_REG_P0_INIT_CRD
,
1155 (CHIP_IS_E3B0(bp
)) ?
1158 (CHIP_IS_E3B0(bp
)) ?
1159 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0
:
1160 PBF_REG_P0_INTERNAL_CRD_FREED_CNT
},
1161 {1, (CHIP_IS_E3B0(bp
)) ?
1162 PBF_REG_INIT_CRD_Q1
:
1163 PBF_REG_P1_INIT_CRD
,
1164 (CHIP_IS_E3B0(bp
)) ?
1167 (CHIP_IS_E3B0(bp
)) ?
1168 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1
:
1169 PBF_REG_P1_INTERNAL_CRD_FREED_CNT
},
1170 {4, (CHIP_IS_E3B0(bp
)) ?
1171 PBF_REG_INIT_CRD_LB_Q
:
1172 PBF_REG_P4_INIT_CRD
,
1173 (CHIP_IS_E3B0(bp
)) ?
1174 PBF_REG_CREDIT_LB_Q
:
1176 (CHIP_IS_E3B0(bp
)) ?
1177 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q
:
1178 PBF_REG_P4_INTERNAL_CRD_FREED_CNT
},
1183 /* Verify the command queues are flushed P0, P1, P4 */
1184 for (i
= 0; i
< ARRAY_SIZE(cmd_regs
); i
++)
1185 bnx2x_pbf_pN_cmd_flushed(bp
, &cmd_regs
[i
], poll_count
);
1188 /* Verify the transmission buffers are flushed P0, P1, P4 */
1189 for (i
= 0; i
< ARRAY_SIZE(buf_regs
); i
++)
1190 bnx2x_pbf_pN_buf_flushed(bp
, &buf_regs
[i
], poll_count
);
1193 #define OP_GEN_PARAM(param) \
1194 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1196 #define OP_GEN_TYPE(type) \
1197 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1199 #define OP_GEN_AGG_VECT(index) \
1200 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1203 static inline int bnx2x_send_final_clnup(struct bnx2x
*bp
, u8 clnup_func
,
1206 struct sdm_op_gen op_gen
= {0};
1208 u32 comp_addr
= BAR_CSTRORM_INTMEM
+
1209 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func
);
1212 if (REG_RD(bp
, comp_addr
)) {
1213 BNX2X_ERR("Cleanup complete is not 0\n");
1217 op_gen
.command
|= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX
);
1218 op_gen
.command
|= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE
);
1219 op_gen
.command
|= OP_GEN_AGG_VECT(clnup_func
);
1220 op_gen
.command
|= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT
;
1222 DP(BNX2X_MSG_SP
, "FW Final cleanup\n");
1223 REG_WR(bp
, XSDM_REG_OPERATION_GEN
, op_gen
.command
);
1225 if (bnx2x_flr_clnup_reg_poll(bp
, comp_addr
, 1, poll_cnt
) != 1) {
1226 BNX2X_ERR("FW final cleanup did not succeed\n");
1229 /* Zero completion for nxt FLR */
1230 REG_WR(bp
, comp_addr
, 0);
1235 static inline u8
bnx2x_is_pcie_pending(struct pci_dev
*dev
)
1240 pos
= pci_pcie_cap(dev
);
1244 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVSTA
, &status
);
1245 return status
& PCI_EXP_DEVSTA_TRPND
;
1248 /* PF FLR specific routines
1250 static int bnx2x_poll_hw_usage_counters(struct bnx2x
*bp
, u32 poll_cnt
)
1253 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1254 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1255 CFC_REG_NUM_LCIDS_INSIDE_PF
,
1256 "CFC PF usage counter timed out",
1261 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1262 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1263 DORQ_REG_PF_USAGE_CNT
,
1264 "DQ PF usage counter timed out",
1268 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1269 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1270 QM_REG_PF_USG_CNT_0
+ 4*BP_FUNC(bp
),
1271 "QM PF usage counter timed out",
1275 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1276 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1277 TM_REG_LIN0_VNIC_UC
+ 4*BP_PORT(bp
),
1278 "Timers VNIC usage counter timed out",
1281 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1282 TM_REG_LIN0_NUM_SCANS
+ 4*BP_PORT(bp
),
1283 "Timers NUM_SCANS usage counter timed out",
1287 /* Wait DMAE PF usage counter to zero */
1288 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1289 dmae_reg_go_c
[INIT_DMAE_C(bp
)],
1290 "DMAE dommand register timed out",
1297 static void bnx2x_hw_enable_status(struct bnx2x
*bp
)
1301 val
= REG_RD(bp
, CFC_REG_WEAK_ENABLE_PF
);
1302 DP(BNX2X_MSG_SP
, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val
);
1304 val
= REG_RD(bp
, PBF_REG_DISABLE_PF
);
1305 DP(BNX2X_MSG_SP
, "PBF_REG_DISABLE_PF is 0x%x\n", val
);
1307 val
= REG_RD(bp
, IGU_REG_PCI_PF_MSI_EN
);
1308 DP(BNX2X_MSG_SP
, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val
);
1310 val
= REG_RD(bp
, IGU_REG_PCI_PF_MSIX_EN
);
1311 DP(BNX2X_MSG_SP
, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val
);
1313 val
= REG_RD(bp
, IGU_REG_PCI_PF_MSIX_FUNC_MASK
);
1314 DP(BNX2X_MSG_SP
, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val
);
1316 val
= REG_RD(bp
, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR
);
1317 DP(BNX2X_MSG_SP
, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val
);
1319 val
= REG_RD(bp
, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR
);
1320 DP(BNX2X_MSG_SP
, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val
);
1322 val
= REG_RD(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
);
1323 DP(BNX2X_MSG_SP
, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1327 static int bnx2x_pf_flr_clnup(struct bnx2x
*bp
)
1329 u32 poll_cnt
= bnx2x_flr_clnup_poll_count(bp
);
1331 DP(BNX2X_MSG_SP
, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp
));
1333 /* Re-enable PF target read access */
1334 REG_WR(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ
, 1);
1336 /* Poll HW usage counters */
1337 if (bnx2x_poll_hw_usage_counters(bp
, poll_cnt
))
1340 /* Zero the igu 'trailing edge' and 'leading edge' */
1342 /* Send the FW cleanup command */
1343 if (bnx2x_send_final_clnup(bp
, (u8
)BP_FUNC(bp
), poll_cnt
))
1348 /* Verify TX hw is flushed */
1349 bnx2x_tx_hw_flushed(bp
, poll_cnt
);
1351 /* Wait 100ms (not adjusted according to platform) */
1354 /* Verify no pending pci transactions */
1355 if (bnx2x_is_pcie_pending(bp
->pdev
))
1356 BNX2X_ERR("PCIE Transactions still pending\n");
1359 bnx2x_hw_enable_status(bp
);
1362 * Master enable - Due to WB DMAE writes performed before this
1363 * register is re-initialized as part of the regular function init
1365 REG_WR(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
, 1);
1370 static void bnx2x_hc_int_enable(struct bnx2x
*bp
)
1372 int port
= BP_PORT(bp
);
1373 u32 addr
= port
? HC_REG_CONFIG_1
: HC_REG_CONFIG_0
;
1374 u32 val
= REG_RD(bp
, addr
);
1375 int msix
= (bp
->flags
& USING_MSIX_FLAG
) ? 1 : 0;
1376 int msi
= (bp
->flags
& USING_MSI_FLAG
) ? 1 : 0;
1379 val
&= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0
|
1380 HC_CONFIG_0_REG_INT_LINE_EN_0
);
1381 val
|= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
|
1382 HC_CONFIG_0_REG_ATTN_BIT_EN_0
);
1384 val
&= ~HC_CONFIG_0_REG_INT_LINE_EN_0
;
1385 val
|= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0
|
1386 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
|
1387 HC_CONFIG_0_REG_ATTN_BIT_EN_0
);
1389 val
|= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0
|
1390 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
|
1391 HC_CONFIG_0_REG_INT_LINE_EN_0
|
1392 HC_CONFIG_0_REG_ATTN_BIT_EN_0
);
1394 if (!CHIP_IS_E1(bp
)) {
1395 DP(NETIF_MSG_INTR
, "write %x to HC %d (addr 0x%x)\n",
1398 REG_WR(bp
, addr
, val
);
1400 val
&= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
;
1405 REG_WR(bp
, HC_REG_INT_MASK
+ port
*4, 0x1FFFF);
1407 DP(NETIF_MSG_INTR
, "write %x to HC %d (addr 0x%x) mode %s\n",
1408 val
, port
, addr
, (msix
? "MSI-X" : (msi
? "MSI" : "INTx")));
1410 REG_WR(bp
, addr
, val
);
1412 * Ensure that HC_CONFIG is written before leading/trailing edge config
1417 if (!CHIP_IS_E1(bp
)) {
1418 /* init leading/trailing edge */
1420 val
= (0xee0f | (1 << (BP_VN(bp
) + 4)));
1422 /* enable nig and gpio3 attention */
1427 REG_WR(bp
, HC_REG_TRAILING_EDGE_0
+ port
*8, val
);
1428 REG_WR(bp
, HC_REG_LEADING_EDGE_0
+ port
*8, val
);
1431 /* Make sure that interrupts are indeed enabled from here on */
1435 static void bnx2x_igu_int_enable(struct bnx2x
*bp
)
1438 int msix
= (bp
->flags
& USING_MSIX_FLAG
) ? 1 : 0;
1439 int msi
= (bp
->flags
& USING_MSI_FLAG
) ? 1 : 0;
1441 val
= REG_RD(bp
, IGU_REG_PF_CONFIGURATION
);
1444 val
&= ~(IGU_PF_CONF_INT_LINE_EN
|
1445 IGU_PF_CONF_SINGLE_ISR_EN
);
1446 val
|= (IGU_PF_CONF_FUNC_EN
|
1447 IGU_PF_CONF_MSI_MSIX_EN
|
1448 IGU_PF_CONF_ATTN_BIT_EN
);
1450 val
&= ~IGU_PF_CONF_INT_LINE_EN
;
1451 val
|= (IGU_PF_CONF_FUNC_EN
|
1452 IGU_PF_CONF_MSI_MSIX_EN
|
1453 IGU_PF_CONF_ATTN_BIT_EN
|
1454 IGU_PF_CONF_SINGLE_ISR_EN
);
1456 val
&= ~IGU_PF_CONF_MSI_MSIX_EN
;
1457 val
|= (IGU_PF_CONF_FUNC_EN
|
1458 IGU_PF_CONF_INT_LINE_EN
|
1459 IGU_PF_CONF_ATTN_BIT_EN
|
1460 IGU_PF_CONF_SINGLE_ISR_EN
);
1463 DP(NETIF_MSG_INTR
, "write 0x%x to IGU mode %s\n",
1464 val
, (msix
? "MSI-X" : (msi
? "MSI" : "INTx")));
1466 REG_WR(bp
, IGU_REG_PF_CONFIGURATION
, val
);
1470 /* init leading/trailing edge */
1472 val
= (0xee0f | (1 << (BP_VN(bp
) + 4)));
1474 /* enable nig and gpio3 attention */
1479 REG_WR(bp
, IGU_REG_TRAILING_EDGE_LATCH
, val
);
1480 REG_WR(bp
, IGU_REG_LEADING_EDGE_LATCH
, val
);
1482 /* Make sure that interrupts are indeed enabled from here on */
1486 void bnx2x_int_enable(struct bnx2x
*bp
)
1488 if (bp
->common
.int_block
== INT_BLOCK_HC
)
1489 bnx2x_hc_int_enable(bp
);
1491 bnx2x_igu_int_enable(bp
);
1494 static void bnx2x_hc_int_disable(struct bnx2x
*bp
)
1496 int port
= BP_PORT(bp
);
1497 u32 addr
= port
? HC_REG_CONFIG_1
: HC_REG_CONFIG_0
;
1498 u32 val
= REG_RD(bp
, addr
);
1501 * in E1 we must use only PCI configuration space to disable
1502 * MSI/MSIX capablility
1503 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1505 if (CHIP_IS_E1(bp
)) {
1506 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1507 * Use mask register to prevent from HC sending interrupts
1508 * after we exit the function
1510 REG_WR(bp
, HC_REG_INT_MASK
+ port
*4, 0);
1512 val
&= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0
|
1513 HC_CONFIG_0_REG_INT_LINE_EN_0
|
1514 HC_CONFIG_0_REG_ATTN_BIT_EN_0
);
1516 val
&= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0
|
1517 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
|
1518 HC_CONFIG_0_REG_INT_LINE_EN_0
|
1519 HC_CONFIG_0_REG_ATTN_BIT_EN_0
);
1521 DP(NETIF_MSG_INTR
, "write %x to HC %d (addr 0x%x)\n",
1524 /* flush all outstanding writes */
1527 REG_WR(bp
, addr
, val
);
1528 if (REG_RD(bp
, addr
) != val
)
1529 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1532 static void bnx2x_igu_int_disable(struct bnx2x
*bp
)
1534 u32 val
= REG_RD(bp
, IGU_REG_PF_CONFIGURATION
);
1536 val
&= ~(IGU_PF_CONF_MSI_MSIX_EN
|
1537 IGU_PF_CONF_INT_LINE_EN
|
1538 IGU_PF_CONF_ATTN_BIT_EN
);
1540 DP(NETIF_MSG_INTR
, "write %x to IGU\n", val
);
1542 /* flush all outstanding writes */
1545 REG_WR(bp
, IGU_REG_PF_CONFIGURATION
, val
);
1546 if (REG_RD(bp
, IGU_REG_PF_CONFIGURATION
) != val
)
1547 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1550 void bnx2x_int_disable(struct bnx2x
*bp
)
1552 if (bp
->common
.int_block
== INT_BLOCK_HC
)
1553 bnx2x_hc_int_disable(bp
);
1555 bnx2x_igu_int_disable(bp
);
1558 void bnx2x_int_disable_sync(struct bnx2x
*bp
, int disable_hw
)
1560 int msix
= (bp
->flags
& USING_MSIX_FLAG
) ? 1 : 0;
1564 /* prevent the HW from sending interrupts */
1565 bnx2x_int_disable(bp
);
1567 /* make sure all ISRs are done */
1569 synchronize_irq(bp
->msix_table
[0].vector
);
1574 for_each_eth_queue(bp
, i
)
1575 synchronize_irq(bp
->msix_table
[offset
++].vector
);
1577 synchronize_irq(bp
->pdev
->irq
);
1579 /* make sure sp_task is not running */
1580 cancel_delayed_work(&bp
->sp_task
);
1581 cancel_delayed_work(&bp
->period_task
);
1582 flush_workqueue(bnx2x_wq
);
1588 * General service functions
1591 /* Return true if succeeded to acquire the lock */
1592 static bool bnx2x_trylock_hw_lock(struct bnx2x
*bp
, u32 resource
)
1595 u32 resource_bit
= (1 << resource
);
1596 int func
= BP_FUNC(bp
);
1597 u32 hw_lock_control_reg
;
1599 DP(NETIF_MSG_HW
, "Trying to take a lock on resource %d\n", resource
);
1601 /* Validating that the resource is within range */
1602 if (resource
> HW_LOCK_MAX_RESOURCE_VALUE
) {
1604 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1605 resource
, HW_LOCK_MAX_RESOURCE_VALUE
);
1610 hw_lock_control_reg
= (MISC_REG_DRIVER_CONTROL_1
+ func
*8);
1612 hw_lock_control_reg
=
1613 (MISC_REG_DRIVER_CONTROL_7
+ (func
- 6)*8);
1615 /* Try to acquire the lock */
1616 REG_WR(bp
, hw_lock_control_reg
+ 4, resource_bit
);
1617 lock_status
= REG_RD(bp
, hw_lock_control_reg
);
1618 if (lock_status
& resource_bit
)
1621 DP(NETIF_MSG_HW
, "Failed to get a lock on resource %d\n", resource
);
1626 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1628 * @bp: driver handle
1630 * Returns the recovery leader resource id according to the engine this function
1631 * belongs to. Currently only only 2 engines is supported.
1633 static inline int bnx2x_get_leader_lock_resource(struct bnx2x
*bp
)
1636 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1
;
1638 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0
;
1642 * bnx2x_trylock_leader_lock- try to aquire a leader lock.
1644 * @bp: driver handle
1646 * Tries to aquire a leader lock for cuurent engine.
1648 static inline bool bnx2x_trylock_leader_lock(struct bnx2x
*bp
)
1650 return bnx2x_trylock_hw_lock(bp
, bnx2x_get_leader_lock_resource(bp
));
1654 static void bnx2x_cnic_cfc_comp(struct bnx2x
*bp
, int cid
, u8 err
);
1657 void bnx2x_sp_event(struct bnx2x_fastpath
*fp
, union eth_rx_cqe
*rr_cqe
)
1659 struct bnx2x
*bp
= fp
->bp
;
1660 int cid
= SW_CID(rr_cqe
->ramrod_cqe
.conn_and_cmd_data
);
1661 int command
= CQE_CMD(rr_cqe
->ramrod_cqe
.conn_and_cmd_data
);
1662 enum bnx2x_queue_cmd drv_cmd
= BNX2X_Q_CMD_MAX
;
1663 struct bnx2x_queue_sp_obj
*q_obj
= &fp
->q_obj
;
1666 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1667 fp
->index
, cid
, command
, bp
->state
,
1668 rr_cqe
->ramrod_cqe
.ramrod_type
);
1671 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE
):
1672 DP(BNX2X_MSG_SP
, "got UPDATE ramrod. CID %d\n", cid
);
1673 drv_cmd
= BNX2X_Q_CMD_UPDATE
;
1676 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP
):
1677 DP(BNX2X_MSG_SP
, "got MULTI[%d] setup ramrod\n", cid
);
1678 drv_cmd
= BNX2X_Q_CMD_SETUP
;
1681 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP
):
1682 DP(NETIF_MSG_IFUP
, "got MULTI[%d] tx-only setup ramrod\n", cid
);
1683 drv_cmd
= BNX2X_Q_CMD_SETUP_TX_ONLY
;
1686 case (RAMROD_CMD_ID_ETH_HALT
):
1687 DP(BNX2X_MSG_SP
, "got MULTI[%d] halt ramrod\n", cid
);
1688 drv_cmd
= BNX2X_Q_CMD_HALT
;
1691 case (RAMROD_CMD_ID_ETH_TERMINATE
):
1692 DP(BNX2X_MSG_SP
, "got MULTI[%d] teminate ramrod\n", cid
);
1693 drv_cmd
= BNX2X_Q_CMD_TERMINATE
;
1696 case (RAMROD_CMD_ID_ETH_EMPTY
):
1697 DP(BNX2X_MSG_SP
, "got MULTI[%d] empty ramrod\n", cid
);
1698 drv_cmd
= BNX2X_Q_CMD_EMPTY
;
1702 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1703 command
, fp
->index
);
1707 if ((drv_cmd
!= BNX2X_Q_CMD_MAX
) &&
1708 q_obj
->complete_cmd(bp
, q_obj
, drv_cmd
))
1709 /* q_obj->complete_cmd() failure means that this was
1710 * an unexpected completion.
1712 * In this case we don't want to increase the bp->spq_left
1713 * because apparently we haven't sent this command the first
1716 #ifdef BNX2X_STOP_ON_ERROR
1722 smp_mb__before_atomic_inc();
1723 atomic_inc(&bp
->cq_spq_left
);
1724 /* push the change in bp->spq_left and towards the memory */
1725 smp_mb__after_atomic_inc();
1727 DP(BNX2X_MSG_SP
, "bp->cq_spq_left %x\n", atomic_read(&bp
->cq_spq_left
));
1732 void bnx2x_update_rx_prod(struct bnx2x
*bp
, struct bnx2x_fastpath
*fp
,
1733 u16 bd_prod
, u16 rx_comp_prod
, u16 rx_sge_prod
)
1735 u32 start
= BAR_USTRORM_INTMEM
+ fp
->ustorm_rx_prods_offset
;
1737 bnx2x_update_rx_prod_gen(bp
, fp
, bd_prod
, rx_comp_prod
, rx_sge_prod
,
1741 irqreturn_t
bnx2x_interrupt(int irq
, void *dev_instance
)
1743 struct bnx2x
*bp
= netdev_priv(dev_instance
);
1744 u16 status
= bnx2x_ack_int(bp
);
1749 /* Return here if interrupt is shared and it's not for us */
1750 if (unlikely(status
== 0)) {
1751 DP(NETIF_MSG_INTR
, "not our interrupt!\n");
1754 DP(NETIF_MSG_INTR
, "got an interrupt status 0x%x\n", status
);
1756 #ifdef BNX2X_STOP_ON_ERROR
1757 if (unlikely(bp
->panic
))
1761 for_each_eth_queue(bp
, i
) {
1762 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
1764 mask
= 0x2 << (fp
->index
+ CNIC_PRESENT
);
1765 if (status
& mask
) {
1766 /* Handle Rx or Tx according to SB id */
1767 prefetch(fp
->rx_cons_sb
);
1768 for_each_cos_in_tx_queue(fp
, cos
)
1769 prefetch(fp
->txdata
[cos
].tx_cons_sb
);
1770 prefetch(&fp
->sb_running_index
[SM_RX_ID
]);
1771 napi_schedule(&bnx2x_fp(bp
, fp
->index
, napi
));
1778 if (status
& (mask
| 0x1)) {
1779 struct cnic_ops
*c_ops
= NULL
;
1781 if (likely(bp
->state
== BNX2X_STATE_OPEN
)) {
1783 c_ops
= rcu_dereference(bp
->cnic_ops
);
1785 c_ops
->cnic_handler(bp
->cnic_data
, NULL
);
1793 if (unlikely(status
& 0x1)) {
1794 queue_delayed_work(bnx2x_wq
, &bp
->sp_task
, 0);
1801 if (unlikely(status
))
1802 DP(NETIF_MSG_INTR
, "got an unknown interrupt! (status 0x%x)\n",
1811 * General service functions
1814 int bnx2x_acquire_hw_lock(struct bnx2x
*bp
, u32 resource
)
1817 u32 resource_bit
= (1 << resource
);
1818 int func
= BP_FUNC(bp
);
1819 u32 hw_lock_control_reg
;
1822 /* Validating that the resource is within range */
1823 if (resource
> HW_LOCK_MAX_RESOURCE_VALUE
) {
1825 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1826 resource
, HW_LOCK_MAX_RESOURCE_VALUE
);
1831 hw_lock_control_reg
= (MISC_REG_DRIVER_CONTROL_1
+ func
*8);
1833 hw_lock_control_reg
=
1834 (MISC_REG_DRIVER_CONTROL_7
+ (func
- 6)*8);
1837 /* Validating that the resource is not already taken */
1838 lock_status
= REG_RD(bp
, hw_lock_control_reg
);
1839 if (lock_status
& resource_bit
) {
1840 DP(NETIF_MSG_HW
, "lock_status 0x%x resource_bit 0x%x\n",
1841 lock_status
, resource_bit
);
1845 /* Try for 5 second every 5ms */
1846 for (cnt
= 0; cnt
< 1000; cnt
++) {
1847 /* Try to acquire the lock */
1848 REG_WR(bp
, hw_lock_control_reg
+ 4, resource_bit
);
1849 lock_status
= REG_RD(bp
, hw_lock_control_reg
);
1850 if (lock_status
& resource_bit
)
1855 DP(NETIF_MSG_HW
, "Timeout\n");
1859 int bnx2x_release_leader_lock(struct bnx2x
*bp
)
1861 return bnx2x_release_hw_lock(bp
, bnx2x_get_leader_lock_resource(bp
));
1864 int bnx2x_release_hw_lock(struct bnx2x
*bp
, u32 resource
)
1867 u32 resource_bit
= (1 << resource
);
1868 int func
= BP_FUNC(bp
);
1869 u32 hw_lock_control_reg
;
1871 DP(NETIF_MSG_HW
, "Releasing a lock on resource %d\n", resource
);
1873 /* Validating that the resource is within range */
1874 if (resource
> HW_LOCK_MAX_RESOURCE_VALUE
) {
1876 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1877 resource
, HW_LOCK_MAX_RESOURCE_VALUE
);
1882 hw_lock_control_reg
= (MISC_REG_DRIVER_CONTROL_1
+ func
*8);
1884 hw_lock_control_reg
=
1885 (MISC_REG_DRIVER_CONTROL_7
+ (func
- 6)*8);
1888 /* Validating that the resource is currently taken */
1889 lock_status
= REG_RD(bp
, hw_lock_control_reg
);
1890 if (!(lock_status
& resource_bit
)) {
1891 DP(NETIF_MSG_HW
, "lock_status 0x%x resource_bit 0x%x\n",
1892 lock_status
, resource_bit
);
1896 REG_WR(bp
, hw_lock_control_reg
, resource_bit
);
1901 int bnx2x_get_gpio(struct bnx2x
*bp
, int gpio_num
, u8 port
)
1903 /* The GPIO should be swapped if swap register is set and active */
1904 int gpio_port
= (REG_RD(bp
, NIG_REG_PORT_SWAP
) &&
1905 REG_RD(bp
, NIG_REG_STRAP_OVERRIDE
)) ^ port
;
1906 int gpio_shift
= gpio_num
+
1907 (gpio_port
? MISC_REGISTERS_GPIO_PORT_SHIFT
: 0);
1908 u32 gpio_mask
= (1 << gpio_shift
);
1912 if (gpio_num
> MISC_REGISTERS_GPIO_3
) {
1913 BNX2X_ERR("Invalid GPIO %d\n", gpio_num
);
1917 /* read GPIO value */
1918 gpio_reg
= REG_RD(bp
, MISC_REG_GPIO
);
1920 /* get the requested pin value */
1921 if ((gpio_reg
& gpio_mask
) == gpio_mask
)
1926 DP(NETIF_MSG_LINK
, "pin %d value 0x%x\n", gpio_num
, value
);
1931 int bnx2x_set_gpio(struct bnx2x
*bp
, int gpio_num
, u32 mode
, u8 port
)
1933 /* The GPIO should be swapped if swap register is set and active */
1934 int gpio_port
= (REG_RD(bp
, NIG_REG_PORT_SWAP
) &&
1935 REG_RD(bp
, NIG_REG_STRAP_OVERRIDE
)) ^ port
;
1936 int gpio_shift
= gpio_num
+
1937 (gpio_port
? MISC_REGISTERS_GPIO_PORT_SHIFT
: 0);
1938 u32 gpio_mask
= (1 << gpio_shift
);
1941 if (gpio_num
> MISC_REGISTERS_GPIO_3
) {
1942 BNX2X_ERR("Invalid GPIO %d\n", gpio_num
);
1946 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
1947 /* read GPIO and mask except the float bits */
1948 gpio_reg
= (REG_RD(bp
, MISC_REG_GPIO
) & MISC_REGISTERS_GPIO_FLOAT
);
1951 case MISC_REGISTERS_GPIO_OUTPUT_LOW
:
1952 DP(NETIF_MSG_LINK
, "Set GPIO %d (shift %d) -> output low\n",
1953 gpio_num
, gpio_shift
);
1954 /* clear FLOAT and set CLR */
1955 gpio_reg
&= ~(gpio_mask
<< MISC_REGISTERS_GPIO_FLOAT_POS
);
1956 gpio_reg
|= (gpio_mask
<< MISC_REGISTERS_GPIO_CLR_POS
);
1959 case MISC_REGISTERS_GPIO_OUTPUT_HIGH
:
1960 DP(NETIF_MSG_LINK
, "Set GPIO %d (shift %d) -> output high\n",
1961 gpio_num
, gpio_shift
);
1962 /* clear FLOAT and set SET */
1963 gpio_reg
&= ~(gpio_mask
<< MISC_REGISTERS_GPIO_FLOAT_POS
);
1964 gpio_reg
|= (gpio_mask
<< MISC_REGISTERS_GPIO_SET_POS
);
1967 case MISC_REGISTERS_GPIO_INPUT_HI_Z
:
1968 DP(NETIF_MSG_LINK
, "Set GPIO %d (shift %d) -> input\n",
1969 gpio_num
, gpio_shift
);
1971 gpio_reg
|= (gpio_mask
<< MISC_REGISTERS_GPIO_FLOAT_POS
);
1978 REG_WR(bp
, MISC_REG_GPIO
, gpio_reg
);
1979 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
1984 int bnx2x_set_mult_gpio(struct bnx2x
*bp
, u8 pins
, u32 mode
)
1989 /* Any port swapping should be handled by caller. */
1991 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
1992 /* read GPIO and mask except the float bits */
1993 gpio_reg
= REG_RD(bp
, MISC_REG_GPIO
);
1994 gpio_reg
&= ~(pins
<< MISC_REGISTERS_GPIO_FLOAT_POS
);
1995 gpio_reg
&= ~(pins
<< MISC_REGISTERS_GPIO_CLR_POS
);
1996 gpio_reg
&= ~(pins
<< MISC_REGISTERS_GPIO_SET_POS
);
1999 case MISC_REGISTERS_GPIO_OUTPUT_LOW
:
2000 DP(NETIF_MSG_LINK
, "Set GPIO 0x%x -> output low\n", pins
);
2002 gpio_reg
|= (pins
<< MISC_REGISTERS_GPIO_CLR_POS
);
2005 case MISC_REGISTERS_GPIO_OUTPUT_HIGH
:
2006 DP(NETIF_MSG_LINK
, "Set GPIO 0x%x -> output high\n", pins
);
2008 gpio_reg
|= (pins
<< MISC_REGISTERS_GPIO_SET_POS
);
2011 case MISC_REGISTERS_GPIO_INPUT_HI_Z
:
2012 DP(NETIF_MSG_LINK
, "Set GPIO 0x%x -> input\n", pins
);
2014 gpio_reg
|= (pins
<< MISC_REGISTERS_GPIO_FLOAT_POS
);
2018 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode
);
2024 REG_WR(bp
, MISC_REG_GPIO
, gpio_reg
);
2026 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
2031 int bnx2x_set_gpio_int(struct bnx2x
*bp
, int gpio_num
, u32 mode
, u8 port
)
2033 /* The GPIO should be swapped if swap register is set and active */
2034 int gpio_port
= (REG_RD(bp
, NIG_REG_PORT_SWAP
) &&
2035 REG_RD(bp
, NIG_REG_STRAP_OVERRIDE
)) ^ port
;
2036 int gpio_shift
= gpio_num
+
2037 (gpio_port
? MISC_REGISTERS_GPIO_PORT_SHIFT
: 0);
2038 u32 gpio_mask
= (1 << gpio_shift
);
2041 if (gpio_num
> MISC_REGISTERS_GPIO_3
) {
2042 BNX2X_ERR("Invalid GPIO %d\n", gpio_num
);
2046 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
2048 gpio_reg
= REG_RD(bp
, MISC_REG_GPIO_INT
);
2051 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR
:
2052 DP(NETIF_MSG_LINK
, "Clear GPIO INT %d (shift %d) -> "
2053 "output low\n", gpio_num
, gpio_shift
);
2054 /* clear SET and set CLR */
2055 gpio_reg
&= ~(gpio_mask
<< MISC_REGISTERS_GPIO_INT_SET_POS
);
2056 gpio_reg
|= (gpio_mask
<< MISC_REGISTERS_GPIO_INT_CLR_POS
);
2059 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET
:
2060 DP(NETIF_MSG_LINK
, "Set GPIO INT %d (shift %d) -> "
2061 "output high\n", gpio_num
, gpio_shift
);
2062 /* clear CLR and set SET */
2063 gpio_reg
&= ~(gpio_mask
<< MISC_REGISTERS_GPIO_INT_CLR_POS
);
2064 gpio_reg
|= (gpio_mask
<< MISC_REGISTERS_GPIO_INT_SET_POS
);
2071 REG_WR(bp
, MISC_REG_GPIO_INT
, gpio_reg
);
2072 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
2077 static int bnx2x_set_spio(struct bnx2x
*bp
, int spio_num
, u32 mode
)
2079 u32 spio_mask
= (1 << spio_num
);
2082 if ((spio_num
< MISC_REGISTERS_SPIO_4
) ||
2083 (spio_num
> MISC_REGISTERS_SPIO_7
)) {
2084 BNX2X_ERR("Invalid SPIO %d\n", spio_num
);
2088 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_SPIO
);
2089 /* read SPIO and mask except the float bits */
2090 spio_reg
= (REG_RD(bp
, MISC_REG_SPIO
) & MISC_REGISTERS_SPIO_FLOAT
);
2093 case MISC_REGISTERS_SPIO_OUTPUT_LOW
:
2094 DP(NETIF_MSG_LINK
, "Set SPIO %d -> output low\n", spio_num
);
2095 /* clear FLOAT and set CLR */
2096 spio_reg
&= ~(spio_mask
<< MISC_REGISTERS_SPIO_FLOAT_POS
);
2097 spio_reg
|= (spio_mask
<< MISC_REGISTERS_SPIO_CLR_POS
);
2100 case MISC_REGISTERS_SPIO_OUTPUT_HIGH
:
2101 DP(NETIF_MSG_LINK
, "Set SPIO %d -> output high\n", spio_num
);
2102 /* clear FLOAT and set SET */
2103 spio_reg
&= ~(spio_mask
<< MISC_REGISTERS_SPIO_FLOAT_POS
);
2104 spio_reg
|= (spio_mask
<< MISC_REGISTERS_SPIO_SET_POS
);
2107 case MISC_REGISTERS_SPIO_INPUT_HI_Z
:
2108 DP(NETIF_MSG_LINK
, "Set SPIO %d -> input\n", spio_num
);
2110 spio_reg
|= (spio_mask
<< MISC_REGISTERS_SPIO_FLOAT_POS
);
2117 REG_WR(bp
, MISC_REG_SPIO
, spio_reg
);
2118 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_SPIO
);
2123 void bnx2x_calc_fc_adv(struct bnx2x
*bp
)
2125 u8 cfg_idx
= bnx2x_get_link_cfg_idx(bp
);
2126 switch (bp
->link_vars
.ieee_fc
&
2127 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK
) {
2128 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE
:
2129 bp
->port
.advertising
[cfg_idx
] &= ~(ADVERTISED_Asym_Pause
|
2133 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
:
2134 bp
->port
.advertising
[cfg_idx
] |= (ADVERTISED_Asym_Pause
|
2138 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
:
2139 bp
->port
.advertising
[cfg_idx
] |= ADVERTISED_Asym_Pause
;
2143 bp
->port
.advertising
[cfg_idx
] &= ~(ADVERTISED_Asym_Pause
|
2149 u8
bnx2x_initial_phy_init(struct bnx2x
*bp
, int load_mode
)
2151 if (!BP_NOMCP(bp
)) {
2153 int cfx_idx
= bnx2x_get_link_cfg_idx(bp
);
2154 u16 req_line_speed
= bp
->link_params
.req_line_speed
[cfx_idx
];
2156 * Initialize link parameters structure variables
2157 * It is recommended to turn off RX FC for jumbo frames
2158 * for better performance
2160 if (CHIP_IS_E1x(bp
) && (bp
->dev
->mtu
> 5000))
2161 bp
->link_params
.req_fc_auto_adv
= BNX2X_FLOW_CTRL_TX
;
2163 bp
->link_params
.req_fc_auto_adv
= BNX2X_FLOW_CTRL_BOTH
;
2165 bnx2x_acquire_phy_lock(bp
);
2167 if (load_mode
== LOAD_DIAG
) {
2168 struct link_params
*lp
= &bp
->link_params
;
2169 lp
->loopback_mode
= LOOPBACK_XGXS
;
2170 /* do PHY loopback at 10G speed, if possible */
2171 if (lp
->req_line_speed
[cfx_idx
] < SPEED_10000
) {
2172 if (lp
->speed_cap_mask
[cfx_idx
] &
2173 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
)
2174 lp
->req_line_speed
[cfx_idx
] =
2177 lp
->req_line_speed
[cfx_idx
] =
2182 rc
= bnx2x_phy_init(&bp
->link_params
, &bp
->link_vars
);
2184 bnx2x_release_phy_lock(bp
);
2186 bnx2x_calc_fc_adv(bp
);
2188 if (CHIP_REV_IS_SLOW(bp
) && bp
->link_vars
.link_up
) {
2189 bnx2x_stats_handle(bp
, STATS_EVENT_LINK_UP
);
2190 bnx2x_link_report(bp
);
2192 queue_delayed_work(bnx2x_wq
, &bp
->period_task
, 0);
2193 bp
->link_params
.req_line_speed
[cfx_idx
] = req_line_speed
;
2196 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2200 void bnx2x_link_set(struct bnx2x
*bp
)
2202 if (!BP_NOMCP(bp
)) {
2203 bnx2x_acquire_phy_lock(bp
);
2204 bnx2x_link_reset(&bp
->link_params
, &bp
->link_vars
, 1);
2205 bnx2x_phy_init(&bp
->link_params
, &bp
->link_vars
);
2206 bnx2x_release_phy_lock(bp
);
2208 bnx2x_calc_fc_adv(bp
);
2210 BNX2X_ERR("Bootcode is missing - can not set link\n");
2213 static void bnx2x__link_reset(struct bnx2x
*bp
)
2215 if (!BP_NOMCP(bp
)) {
2216 bnx2x_acquire_phy_lock(bp
);
2217 bnx2x_link_reset(&bp
->link_params
, &bp
->link_vars
, 1);
2218 bnx2x_release_phy_lock(bp
);
2220 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2223 u8
bnx2x_link_test(struct bnx2x
*bp
, u8 is_serdes
)
2227 if (!BP_NOMCP(bp
)) {
2228 bnx2x_acquire_phy_lock(bp
);
2229 rc
= bnx2x_test_link(&bp
->link_params
, &bp
->link_vars
,
2231 bnx2x_release_phy_lock(bp
);
2233 BNX2X_ERR("Bootcode is missing - can not test link\n");
2238 static void bnx2x_init_port_minmax(struct bnx2x
*bp
)
2240 u32 r_param
= bp
->link_vars
.line_speed
/ 8;
2241 u32 fair_periodic_timeout_usec
;
2244 memset(&(bp
->cmng
.rs_vars
), 0,
2245 sizeof(struct rate_shaping_vars_per_port
));
2246 memset(&(bp
->cmng
.fair_vars
), 0, sizeof(struct fairness_vars_per_port
));
2248 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
2249 bp
->cmng
.rs_vars
.rs_periodic_timeout
= RS_PERIODIC_TIMEOUT_USEC
/ 4;
2251 /* this is the threshold below which no timer arming will occur
2252 1.25 coefficient is for the threshold to be a little bigger
2253 than the real time, to compensate for timer in-accuracy */
2254 bp
->cmng
.rs_vars
.rs_threshold
=
2255 (RS_PERIODIC_TIMEOUT_USEC
* r_param
* 5) / 4;
2257 /* resolution of fairness timer */
2258 fair_periodic_timeout_usec
= QM_ARB_BYTES
/ r_param
;
2259 /* for 10G it is 1000usec. for 1G it is 10000usec. */
2260 t_fair
= T_FAIR_COEF
/ bp
->link_vars
.line_speed
;
2262 /* this is the threshold below which we won't arm the timer anymore */
2263 bp
->cmng
.fair_vars
.fair_threshold
= QM_ARB_BYTES
;
2265 /* we multiply by 1e3/8 to get bytes/msec.
2266 We don't want the credits to pass a credit
2267 of the t_fair*FAIR_MEM (algorithm resolution) */
2268 bp
->cmng
.fair_vars
.upper_bound
= r_param
* t_fair
* FAIR_MEM
;
2269 /* since each tick is 4 usec */
2270 bp
->cmng
.fair_vars
.fairness_timeout
= fair_periodic_timeout_usec
/ 4;
2273 /* Calculates the sum of vn_min_rates.
2274 It's needed for further normalizing of the min_rates.
2276 sum of vn_min_rates.
2278 0 - if all the min_rates are 0.
2279 In the later case fainess algorithm should be deactivated.
2280 If not all min_rates are zero then those that are zeroes will be set to 1.
2282 static void bnx2x_calc_vn_weight_sum(struct bnx2x
*bp
)
2287 bp
->vn_weight_sum
= 0;
2288 for (vn
= VN_0
; vn
< BP_MAX_VN_NUM(bp
); vn
++) {
2289 u32 vn_cfg
= bp
->mf_config
[vn
];
2290 u32 vn_min_rate
= ((vn_cfg
& FUNC_MF_CFG_MIN_BW_MASK
) >>
2291 FUNC_MF_CFG_MIN_BW_SHIFT
) * 100;
2293 /* Skip hidden vns */
2294 if (vn_cfg
& FUNC_MF_CFG_FUNC_HIDE
)
2297 /* If min rate is zero - set it to 1 */
2299 vn_min_rate
= DEF_MIN_RATE
;
2303 bp
->vn_weight_sum
+= vn_min_rate
;
2306 /* if ETS or all min rates are zeros - disable fairness */
2307 if (BNX2X_IS_ETS_ENABLED(bp
)) {
2308 bp
->cmng
.flags
.cmng_enables
&=
2309 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN
;
2310 DP(NETIF_MSG_IFUP
, "Fairness will be disabled due to ETS\n");
2311 } else if (all_zero
) {
2312 bp
->cmng
.flags
.cmng_enables
&=
2313 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN
;
2314 DP(NETIF_MSG_IFUP
, "All MIN values are zeroes"
2315 " fairness will be disabled\n");
2317 bp
->cmng
.flags
.cmng_enables
|=
2318 CMNG_FLAGS_PER_PORT_FAIRNESS_VN
;
2321 static void bnx2x_init_vn_minmax(struct bnx2x
*bp
, int vn
)
2323 struct rate_shaping_vars_per_vn m_rs_vn
;
2324 struct fairness_vars_per_vn m_fair_vn
;
2325 u32 vn_cfg
= bp
->mf_config
[vn
];
2326 int func
= func_by_vn(bp
, vn
);
2327 u16 vn_min_rate
, vn_max_rate
;
2330 /* If function is hidden - set min and max to zeroes */
2331 if (vn_cfg
& FUNC_MF_CFG_FUNC_HIDE
) {
2336 u32 maxCfg
= bnx2x_extract_max_cfg(bp
, vn_cfg
);
2338 vn_min_rate
= ((vn_cfg
& FUNC_MF_CFG_MIN_BW_MASK
) >>
2339 FUNC_MF_CFG_MIN_BW_SHIFT
) * 100;
2340 /* If fairness is enabled (not all min rates are zeroes) and
2341 if current min rate is zero - set it to 1.
2342 This is a requirement of the algorithm. */
2343 if (bp
->vn_weight_sum
&& (vn_min_rate
== 0))
2344 vn_min_rate
= DEF_MIN_RATE
;
2347 /* maxCfg in percents of linkspeed */
2348 vn_max_rate
= (bp
->link_vars
.line_speed
* maxCfg
) / 100;
2350 /* maxCfg is absolute in 100Mb units */
2351 vn_max_rate
= maxCfg
* 100;
2355 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n",
2356 func
, vn_min_rate
, vn_max_rate
, bp
->vn_weight_sum
);
2358 memset(&m_rs_vn
, 0, sizeof(struct rate_shaping_vars_per_vn
));
2359 memset(&m_fair_vn
, 0, sizeof(struct fairness_vars_per_vn
));
2361 /* global vn counter - maximal Mbps for this vn */
2362 m_rs_vn
.vn_counter
.rate
= vn_max_rate
;
2364 /* quota - number of bytes transmitted in this period */
2365 m_rs_vn
.vn_counter
.quota
=
2366 (vn_max_rate
* RS_PERIODIC_TIMEOUT_USEC
) / 8;
2368 if (bp
->vn_weight_sum
) {
2369 /* credit for each period of the fairness algorithm:
2370 number of bytes in T_FAIR (the vn share the port rate).
2371 vn_weight_sum should not be larger than 10000, thus
2372 T_FAIR_COEF / (8 * vn_weight_sum) will always be greater
2374 m_fair_vn
.vn_credit_delta
=
2375 max_t(u32
, (vn_min_rate
* (T_FAIR_COEF
/
2376 (8 * bp
->vn_weight_sum
))),
2377 (bp
->cmng
.fair_vars
.fair_threshold
+
2379 DP(NETIF_MSG_IFUP
, "m_fair_vn.vn_credit_delta %d\n",
2380 m_fair_vn
.vn_credit_delta
);
2383 /* Store it to internal memory */
2384 for (i
= 0; i
< sizeof(struct rate_shaping_vars_per_vn
)/4; i
++)
2385 REG_WR(bp
, BAR_XSTRORM_INTMEM
+
2386 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func
) + i
* 4,
2387 ((u32
*)(&m_rs_vn
))[i
]);
2389 for (i
= 0; i
< sizeof(struct fairness_vars_per_vn
)/4; i
++)
2390 REG_WR(bp
, BAR_XSTRORM_INTMEM
+
2391 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func
) + i
* 4,
2392 ((u32
*)(&m_fair_vn
))[i
]);
2395 static int bnx2x_get_cmng_fns_mode(struct bnx2x
*bp
)
2397 if (CHIP_REV_IS_SLOW(bp
))
2398 return CMNG_FNS_NONE
;
2400 return CMNG_FNS_MINMAX
;
2402 return CMNG_FNS_NONE
;
2405 void bnx2x_read_mf_cfg(struct bnx2x
*bp
)
2407 int vn
, n
= (CHIP_MODE_IS_4_PORT(bp
) ? 2 : 1);
2410 return; /* what should be the default bvalue in this case */
2412 /* For 2 port configuration the absolute function number formula
2414 * abs_func = 2 * vn + BP_PORT + BP_PATH
2416 * and there are 4 functions per port
2418 * For 4 port configuration it is
2419 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2421 * and there are 2 functions per port
2423 for (vn
= VN_0
; vn
< BP_MAX_VN_NUM(bp
); vn
++) {
2424 int /*abs*/func
= n
* (2 * vn
+ BP_PORT(bp
)) + BP_PATH(bp
);
2426 if (func
>= E1H_FUNC_MAX
)
2430 MF_CFG_RD(bp
, func_mf_config
[func
].config
);
2434 static void bnx2x_cmng_fns_init(struct bnx2x
*bp
, u8 read_cfg
, u8 cmng_type
)
2437 if (cmng_type
== CMNG_FNS_MINMAX
) {
2440 /* clear cmng_enables */
2441 bp
->cmng
.flags
.cmng_enables
= 0;
2443 /* read mf conf from shmem */
2445 bnx2x_read_mf_cfg(bp
);
2447 /* Init rate shaping and fairness contexts */
2448 bnx2x_init_port_minmax(bp
);
2450 /* vn_weight_sum and enable fairness if not 0 */
2451 bnx2x_calc_vn_weight_sum(bp
);
2453 /* calculate and set min-max rate for each vn */
2455 for (vn
= VN_0
; vn
< BP_MAX_VN_NUM(bp
); vn
++)
2456 bnx2x_init_vn_minmax(bp
, vn
);
2458 /* always enable rate shaping and fairness */
2459 bp
->cmng
.flags
.cmng_enables
|=
2460 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN
;
2461 if (!bp
->vn_weight_sum
)
2462 DP(NETIF_MSG_IFUP
, "All MIN values are zeroes"
2463 " fairness will be disabled\n");
2467 /* rate shaping and fairness are disabled */
2469 "rate shaping and fairness are disabled\n");
2472 /* This function is called upon link interrupt */
2473 static void bnx2x_link_attn(struct bnx2x
*bp
)
2475 /* Make sure that we are synced with the current statistics */
2476 bnx2x_stats_handle(bp
, STATS_EVENT_STOP
);
2478 bnx2x_link_update(&bp
->link_params
, &bp
->link_vars
);
2480 if (bp
->link_vars
.link_up
) {
2482 /* dropless flow control */
2483 if (!CHIP_IS_E1(bp
) && bp
->dropless_fc
) {
2484 int port
= BP_PORT(bp
);
2485 u32 pause_enabled
= 0;
2487 if (bp
->link_vars
.flow_ctrl
& BNX2X_FLOW_CTRL_TX
)
2490 REG_WR(bp
, BAR_USTRORM_INTMEM
+
2491 USTORM_ETH_PAUSE_ENABLED_OFFSET(port
),
2495 if (bp
->link_vars
.mac_type
!= MAC_TYPE_EMAC
) {
2496 struct host_port_stats
*pstats
;
2498 pstats
= bnx2x_sp(bp
, port_stats
);
2499 /* reset old mac stats */
2500 memset(&(pstats
->mac_stx
[0]), 0,
2501 sizeof(struct mac_stx
));
2503 if (bp
->state
== BNX2X_STATE_OPEN
)
2504 bnx2x_stats_handle(bp
, STATS_EVENT_LINK_UP
);
2507 if (bp
->link_vars
.link_up
&& bp
->link_vars
.line_speed
) {
2508 int cmng_fns
= bnx2x_get_cmng_fns_mode(bp
);
2510 if (cmng_fns
!= CMNG_FNS_NONE
) {
2511 bnx2x_cmng_fns_init(bp
, false, cmng_fns
);
2512 storm_memset_cmng(bp
, &bp
->cmng
, BP_PORT(bp
));
2514 /* rate shaping and fairness are disabled */
2516 "single function mode without fairness\n");
2519 __bnx2x_link_report(bp
);
2522 bnx2x_link_sync_notify(bp
);
2525 void bnx2x__link_status_update(struct bnx2x
*bp
)
2527 if (bp
->state
!= BNX2X_STATE_OPEN
)
2530 /* read updated dcb configuration */
2531 bnx2x_dcbx_pmf_update(bp
);
2533 bnx2x_link_status_update(&bp
->link_params
, &bp
->link_vars
);
2535 if (bp
->link_vars
.link_up
)
2536 bnx2x_stats_handle(bp
, STATS_EVENT_LINK_UP
);
2538 bnx2x_stats_handle(bp
, STATS_EVENT_STOP
);
2540 /* indicate link status */
2541 bnx2x_link_report(bp
);
2544 static void bnx2x_pmf_update(struct bnx2x
*bp
)
2546 int port
= BP_PORT(bp
);
2550 DP(NETIF_MSG_LINK
, "pmf %d\n", bp
->port
.pmf
);
2553 * We need the mb() to ensure the ordering between the writing to
2554 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2558 /* queue a periodic task */
2559 queue_delayed_work(bnx2x_wq
, &bp
->period_task
, 0);
2561 bnx2x_dcbx_pmf_update(bp
);
2563 /* enable nig attention */
2564 val
= (0xff0f | (1 << (BP_VN(bp
) + 4)));
2565 if (bp
->common
.int_block
== INT_BLOCK_HC
) {
2566 REG_WR(bp
, HC_REG_TRAILING_EDGE_0
+ port
*8, val
);
2567 REG_WR(bp
, HC_REG_LEADING_EDGE_0
+ port
*8, val
);
2568 } else if (!CHIP_IS_E1x(bp
)) {
2569 REG_WR(bp
, IGU_REG_TRAILING_EDGE_LATCH
, val
);
2570 REG_WR(bp
, IGU_REG_LEADING_EDGE_LATCH
, val
);
2573 bnx2x_stats_handle(bp
, STATS_EVENT_PMF
);
2581 * General service functions
2584 /* send the MCP a request, block until there is a reply */
2585 u32
bnx2x_fw_command(struct bnx2x
*bp
, u32 command
, u32 param
)
2587 int mb_idx
= BP_FW_MB_IDX(bp
);
2591 u8 delay
= CHIP_REV_IS_SLOW(bp
) ? 100 : 10;
2593 mutex_lock(&bp
->fw_mb_mutex
);
2595 SHMEM_WR(bp
, func_mb
[mb_idx
].drv_mb_param
, param
);
2596 SHMEM_WR(bp
, func_mb
[mb_idx
].drv_mb_header
, (command
| seq
));
2598 DP(BNX2X_MSG_MCP
, "wrote command (%x) to FW MB param 0x%08x\n",
2599 (command
| seq
), param
);
2602 /* let the FW do it's magic ... */
2605 rc
= SHMEM_RD(bp
, func_mb
[mb_idx
].fw_mb_header
);
2607 /* Give the FW up to 5 second (500*10ms) */
2608 } while ((seq
!= (rc
& FW_MSG_SEQ_NUMBER_MASK
)) && (cnt
++ < 500));
2610 DP(BNX2X_MSG_MCP
, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2611 cnt
*delay
, rc
, seq
);
2613 /* is this a reply to our command? */
2614 if (seq
== (rc
& FW_MSG_SEQ_NUMBER_MASK
))
2615 rc
&= FW_MSG_CODE_MASK
;
2618 BNX2X_ERR("FW failed to respond!\n");
2622 mutex_unlock(&bp
->fw_mb_mutex
);
2627 static u8
stat_counter_valid(struct bnx2x
*bp
, struct bnx2x_fastpath
*fp
)
2630 /* Statistics are not supported for CNIC Clients at the moment */
2637 void bnx2x_func_init(struct bnx2x
*bp
, struct bnx2x_func_init_params
*p
)
2639 if (CHIP_IS_E1x(bp
)) {
2640 struct tstorm_eth_function_common_config tcfg
= {0};
2642 storm_memset_func_cfg(bp
, &tcfg
, p
->func_id
);
2645 /* Enable the function in the FW */
2646 storm_memset_vf_to_pf(bp
, p
->func_id
, p
->pf_id
);
2647 storm_memset_func_en(bp
, p
->func_id
, 1);
2650 if (p
->func_flgs
& FUNC_FLG_SPQ
) {
2651 storm_memset_spq_addr(bp
, p
->spq_map
, p
->func_id
);
2652 REG_WR(bp
, XSEM_REG_FAST_MEMORY
+
2653 XSTORM_SPQ_PROD_OFFSET(p
->func_id
), p
->spq_prod
);
2658 * bnx2x_get_tx_only_flags - Return common flags
2662 * @zero_stats TRUE if statistics zeroing is needed
2664 * Return the flags that are common for the Tx-only and not normal connections.
2666 static inline unsigned long bnx2x_get_common_flags(struct bnx2x
*bp
,
2667 struct bnx2x_fastpath
*fp
,
2670 unsigned long flags
= 0;
2672 /* PF driver will always initialize the Queue to an ACTIVE state */
2673 __set_bit(BNX2X_Q_FLG_ACTIVE
, &flags
);
2675 /* tx only connections collect statistics (on the same index as the
2676 * parent connection). The statistics are zeroed when the parent
2677 * connection is initialized.
2679 if (stat_counter_valid(bp
, fp
)) {
2680 __set_bit(BNX2X_Q_FLG_STATS
, &flags
);
2682 __set_bit(BNX2X_Q_FLG_ZERO_STATS
, &flags
);
2688 static inline unsigned long bnx2x_get_q_flags(struct bnx2x
*bp
,
2689 struct bnx2x_fastpath
*fp
,
2692 unsigned long flags
= 0;
2694 /* calculate other queue flags */
2696 __set_bit(BNX2X_Q_FLG_OV
, &flags
);
2699 __set_bit(BNX2X_Q_FLG_FCOE
, &flags
);
2701 if (!fp
->disable_tpa
) {
2702 __set_bit(BNX2X_Q_FLG_TPA
, &flags
);
2703 __set_bit(BNX2X_Q_FLG_TPA_IPV6
, &flags
);
2707 __set_bit(BNX2X_Q_FLG_LEADING_RSS
, &flags
);
2708 __set_bit(BNX2X_Q_FLG_MCAST
, &flags
);
2711 /* Always set HW VLAN stripping */
2712 __set_bit(BNX2X_Q_FLG_VLAN
, &flags
);
2715 return flags
| bnx2x_get_common_flags(bp
, fp
, true);
2718 static void bnx2x_pf_q_prep_general(struct bnx2x
*bp
,
2719 struct bnx2x_fastpath
*fp
, struct bnx2x_general_setup_params
*gen_init
,
2722 gen_init
->stat_id
= bnx2x_stats_id(fp
);
2723 gen_init
->spcl_id
= fp
->cl_id
;
2725 /* Always use mini-jumbo MTU for FCoE L2 ring */
2727 gen_init
->mtu
= BNX2X_FCOE_MINI_JUMBO_MTU
;
2729 gen_init
->mtu
= bp
->dev
->mtu
;
2731 gen_init
->cos
= cos
;
2734 static void bnx2x_pf_rx_q_prep(struct bnx2x
*bp
,
2735 struct bnx2x_fastpath
*fp
, struct rxq_pause_params
*pause
,
2736 struct bnx2x_rxq_setup_params
*rxq_init
)
2740 u16 tpa_agg_size
= 0;
2742 if (!fp
->disable_tpa
) {
2743 pause
->sge_th_lo
= SGE_TH_LO(bp
);
2744 pause
->sge_th_hi
= SGE_TH_HI(bp
);
2746 /* validate SGE ring has enough to cross high threshold */
2747 WARN_ON(bp
->dropless_fc
&&
2748 pause
->sge_th_hi
+ FW_PREFETCH_CNT
>
2749 MAX_RX_SGE_CNT
* NUM_RX_SGE_PAGES
);
2751 tpa_agg_size
= min_t(u32
,
2752 (min_t(u32
, 8, MAX_SKB_FRAGS
) *
2753 SGE_PAGE_SIZE
* PAGES_PER_SGE
), 0xffff);
2754 max_sge
= SGE_PAGE_ALIGN(bp
->dev
->mtu
) >>
2756 max_sge
= ((max_sge
+ PAGES_PER_SGE
- 1) &
2757 (~(PAGES_PER_SGE
-1))) >> PAGES_PER_SGE_SHIFT
;
2758 sge_sz
= (u16
)min_t(u32
, SGE_PAGE_SIZE
* PAGES_PER_SGE
,
2762 /* pause - not for e1 */
2763 if (!CHIP_IS_E1(bp
)) {
2764 pause
->bd_th_lo
= BD_TH_LO(bp
);
2765 pause
->bd_th_hi
= BD_TH_HI(bp
);
2767 pause
->rcq_th_lo
= RCQ_TH_LO(bp
);
2768 pause
->rcq_th_hi
= RCQ_TH_HI(bp
);
2770 * validate that rings have enough entries to cross
2773 WARN_ON(bp
->dropless_fc
&&
2774 pause
->bd_th_hi
+ FW_PREFETCH_CNT
>
2776 WARN_ON(bp
->dropless_fc
&&
2777 pause
->rcq_th_hi
+ FW_PREFETCH_CNT
>
2778 NUM_RCQ_RINGS
* MAX_RCQ_DESC_CNT
);
2784 rxq_init
->dscr_map
= fp
->rx_desc_mapping
;
2785 rxq_init
->sge_map
= fp
->rx_sge_mapping
;
2786 rxq_init
->rcq_map
= fp
->rx_comp_mapping
;
2787 rxq_init
->rcq_np_map
= fp
->rx_comp_mapping
+ BCM_PAGE_SIZE
;
2789 /* This should be a maximum number of data bytes that may be
2790 * placed on the BD (not including paddings).
2792 rxq_init
->buf_sz
= fp
->rx_buf_size
- BNX2X_FW_RX_ALIGN_START
-
2793 BNX2X_FW_RX_ALIGN_END
- IP_HEADER_ALIGNMENT_PADDING
;
2795 rxq_init
->cl_qzone_id
= fp
->cl_qzone_id
;
2796 rxq_init
->tpa_agg_sz
= tpa_agg_size
;
2797 rxq_init
->sge_buf_sz
= sge_sz
;
2798 rxq_init
->max_sges_pkt
= max_sge
;
2799 rxq_init
->rss_engine_id
= BP_FUNC(bp
);
2801 /* Maximum number or simultaneous TPA aggregation for this Queue.
2803 * For PF Clients it should be the maximum avaliable number.
2804 * VF driver(s) may want to define it to a smaller value.
2806 rxq_init
->max_tpa_queues
= MAX_AGG_QS(bp
);
2808 rxq_init
->cache_line_log
= BNX2X_RX_ALIGN_SHIFT
;
2809 rxq_init
->fw_sb_id
= fp
->fw_sb_id
;
2812 rxq_init
->sb_cq_index
= HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS
;
2814 rxq_init
->sb_cq_index
= HC_INDEX_ETH_RX_CQ_CONS
;
2817 static void bnx2x_pf_tx_q_prep(struct bnx2x
*bp
,
2818 struct bnx2x_fastpath
*fp
, struct bnx2x_txq_setup_params
*txq_init
,
2821 txq_init
->dscr_map
= fp
->txdata
[cos
].tx_desc_mapping
;
2822 txq_init
->sb_cq_index
= HC_INDEX_ETH_FIRST_TX_CQ_CONS
+ cos
;
2823 txq_init
->traffic_type
= LLFC_TRAFFIC_TYPE_NW
;
2824 txq_init
->fw_sb_id
= fp
->fw_sb_id
;
2827 * set the tss leading client id for TX classfication ==
2828 * leading RSS client id
2830 txq_init
->tss_leading_cl_id
= bnx2x_fp(bp
, 0, cl_id
);
2832 if (IS_FCOE_FP(fp
)) {
2833 txq_init
->sb_cq_index
= HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS
;
2834 txq_init
->traffic_type
= LLFC_TRAFFIC_TYPE_FCOE
;
2838 static void bnx2x_pf_init(struct bnx2x
*bp
)
2840 struct bnx2x_func_init_params func_init
= {0};
2841 struct event_ring_data eq_data
= { {0} };
2844 if (!CHIP_IS_E1x(bp
)) {
2845 /* reset IGU PF statistics: MSIX + ATTN */
2847 REG_WR(bp
, IGU_REG_STATISTIC_NUM_MESSAGE_SENT
+
2848 BNX2X_IGU_STAS_MSG_VF_CNT
*4 +
2849 (CHIP_MODE_IS_4_PORT(bp
) ?
2850 BP_FUNC(bp
) : BP_VN(bp
))*4, 0);
2852 REG_WR(bp
, IGU_REG_STATISTIC_NUM_MESSAGE_SENT
+
2853 BNX2X_IGU_STAS_MSG_VF_CNT
*4 +
2854 BNX2X_IGU_STAS_MSG_PF_CNT
*4 +
2855 (CHIP_MODE_IS_4_PORT(bp
) ?
2856 BP_FUNC(bp
) : BP_VN(bp
))*4, 0);
2859 /* function setup flags */
2860 flags
= (FUNC_FLG_STATS
| FUNC_FLG_LEADING
| FUNC_FLG_SPQ
);
2862 /* This flag is relevant for E1x only.
2863 * E2 doesn't have a TPA configuration in a function level.
2865 flags
|= (bp
->flags
& TPA_ENABLE_FLAG
) ? FUNC_FLG_TPA
: 0;
2867 func_init
.func_flgs
= flags
;
2868 func_init
.pf_id
= BP_FUNC(bp
);
2869 func_init
.func_id
= BP_FUNC(bp
);
2870 func_init
.spq_map
= bp
->spq_mapping
;
2871 func_init
.spq_prod
= bp
->spq_prod_idx
;
2873 bnx2x_func_init(bp
, &func_init
);
2875 memset(&(bp
->cmng
), 0, sizeof(struct cmng_struct_per_port
));
2878 * Congestion management values depend on the link rate
2879 * There is no active link so initial link rate is set to 10 Gbps.
2880 * When the link comes up The congestion management values are
2881 * re-calculated according to the actual link rate.
2883 bp
->link_vars
.line_speed
= SPEED_10000
;
2884 bnx2x_cmng_fns_init(bp
, true, bnx2x_get_cmng_fns_mode(bp
));
2886 /* Only the PMF sets the HW */
2888 storm_memset_cmng(bp
, &bp
->cmng
, BP_PORT(bp
));
2890 /* init Event Queue */
2891 eq_data
.base_addr
.hi
= U64_HI(bp
->eq_mapping
);
2892 eq_data
.base_addr
.lo
= U64_LO(bp
->eq_mapping
);
2893 eq_data
.producer
= bp
->eq_prod
;
2894 eq_data
.index_id
= HC_SP_INDEX_EQ_CONS
;
2895 eq_data
.sb_id
= DEF_SB_ID
;
2896 storm_memset_eq_data(bp
, &eq_data
, BP_FUNC(bp
));
2900 static void bnx2x_e1h_disable(struct bnx2x
*bp
)
2902 int port
= BP_PORT(bp
);
2904 bnx2x_tx_disable(bp
);
2906 REG_WR(bp
, NIG_REG_LLH0_FUNC_EN
+ port
*8, 0);
2909 static void bnx2x_e1h_enable(struct bnx2x
*bp
)
2911 int port
= BP_PORT(bp
);
2913 REG_WR(bp
, NIG_REG_LLH0_FUNC_EN
+ port
*8, 1);
2915 /* Tx queue should be only reenabled */
2916 netif_tx_wake_all_queues(bp
->dev
);
2919 * Should not call netif_carrier_on since it will be called if the link
2920 * is up when checking for link state
2924 /* called due to MCP event (on pmf):
2925 * reread new bandwidth configuration
2927 * notify others function about the change
2929 static inline void bnx2x_config_mf_bw(struct bnx2x
*bp
)
2931 if (bp
->link_vars
.link_up
) {
2932 bnx2x_cmng_fns_init(bp
, true, CMNG_FNS_MINMAX
);
2933 bnx2x_link_sync_notify(bp
);
2935 storm_memset_cmng(bp
, &bp
->cmng
, BP_PORT(bp
));
2938 static inline void bnx2x_set_mf_bw(struct bnx2x
*bp
)
2940 bnx2x_config_mf_bw(bp
);
2941 bnx2x_fw_command(bp
, DRV_MSG_CODE_SET_MF_BW_ACK
, 0);
2944 static void bnx2x_dcc_event(struct bnx2x
*bp
, u32 dcc_event
)
2946 DP(BNX2X_MSG_MCP
, "dcc_event 0x%x\n", dcc_event
);
2948 if (dcc_event
& DRV_STATUS_DCC_DISABLE_ENABLE_PF
) {
2951 * This is the only place besides the function initialization
2952 * where the bp->flags can change so it is done without any
2955 if (bp
->mf_config
[BP_VN(bp
)] & FUNC_MF_CFG_FUNC_DISABLED
) {
2956 DP(NETIF_MSG_IFDOWN
, "mf_cfg function disabled\n");
2957 bp
->flags
|= MF_FUNC_DIS
;
2959 bnx2x_e1h_disable(bp
);
2961 DP(NETIF_MSG_IFUP
, "mf_cfg function enabled\n");
2962 bp
->flags
&= ~MF_FUNC_DIS
;
2964 bnx2x_e1h_enable(bp
);
2966 dcc_event
&= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF
;
2968 if (dcc_event
& DRV_STATUS_DCC_BANDWIDTH_ALLOCATION
) {
2969 bnx2x_config_mf_bw(bp
);
2970 dcc_event
&= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION
;
2973 /* Report results to MCP */
2975 bnx2x_fw_command(bp
, DRV_MSG_CODE_DCC_FAILURE
, 0);
2977 bnx2x_fw_command(bp
, DRV_MSG_CODE_DCC_OK
, 0);
2980 /* must be called under the spq lock */
2981 static inline struct eth_spe
*bnx2x_sp_get_next(struct bnx2x
*bp
)
2983 struct eth_spe
*next_spe
= bp
->spq_prod_bd
;
2985 if (bp
->spq_prod_bd
== bp
->spq_last_bd
) {
2986 bp
->spq_prod_bd
= bp
->spq
;
2987 bp
->spq_prod_idx
= 0;
2988 DP(NETIF_MSG_TIMER
, "end of spq\n");
2996 /* must be called under the spq lock */
2997 static inline void bnx2x_sp_prod_update(struct bnx2x
*bp
)
2999 int func
= BP_FUNC(bp
);
3002 * Make sure that BD data is updated before writing the producer:
3003 * BD data is written to the memory, the producer is read from the
3004 * memory, thus we need a full memory barrier to ensure the ordering.
3008 REG_WR16(bp
, BAR_XSTRORM_INTMEM
+ XSTORM_SPQ_PROD_OFFSET(func
),
3014 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3016 * @cmd: command to check
3017 * @cmd_type: command type
3019 static inline bool bnx2x_is_contextless_ramrod(int cmd
, int cmd_type
)
3021 if ((cmd_type
== NONE_CONNECTION_TYPE
) ||
3022 (cmd
== RAMROD_CMD_ID_ETH_FORWARD_SETUP
) ||
3023 (cmd
== RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES
) ||
3024 (cmd
== RAMROD_CMD_ID_ETH_FILTER_RULES
) ||
3025 (cmd
== RAMROD_CMD_ID_ETH_MULTICAST_RULES
) ||
3026 (cmd
== RAMROD_CMD_ID_ETH_SET_MAC
) ||
3027 (cmd
== RAMROD_CMD_ID_ETH_RSS_UPDATE
))
3036 * bnx2x_sp_post - place a single command on an SP ring
3038 * @bp: driver handle
3039 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3040 * @cid: SW CID the command is related to
3041 * @data_hi: command private data address (high 32 bits)
3042 * @data_lo: command private data address (low 32 bits)
3043 * @cmd_type: command type (e.g. NONE, ETH)
3045 * SP data is handled as if it's always an address pair, thus data fields are
3046 * not swapped to little endian in upper functions. Instead this function swaps
3047 * data as if it's two u32 fields.
3049 int bnx2x_sp_post(struct bnx2x
*bp
, int command
, int cid
,
3050 u32 data_hi
, u32 data_lo
, int cmd_type
)
3052 struct eth_spe
*spe
;
3054 bool common
= bnx2x_is_contextless_ramrod(command
, cmd_type
);
3056 #ifdef BNX2X_STOP_ON_ERROR
3057 if (unlikely(bp
->panic
))
3061 spin_lock_bh(&bp
->spq_lock
);
3064 if (!atomic_read(&bp
->eq_spq_left
)) {
3065 BNX2X_ERR("BUG! EQ ring full!\n");
3066 spin_unlock_bh(&bp
->spq_lock
);
3070 } else if (!atomic_read(&bp
->cq_spq_left
)) {
3071 BNX2X_ERR("BUG! SPQ ring full!\n");
3072 spin_unlock_bh(&bp
->spq_lock
);
3077 spe
= bnx2x_sp_get_next(bp
);
3079 /* CID needs port number to be encoded int it */
3080 spe
->hdr
.conn_and_cmd_data
=
3081 cpu_to_le32((command
<< SPE_HDR_CMD_ID_SHIFT
) |
3084 type
= (cmd_type
<< SPE_HDR_CONN_TYPE_SHIFT
) & SPE_HDR_CONN_TYPE
;
3086 type
|= ((BP_FUNC(bp
) << SPE_HDR_FUNCTION_ID_SHIFT
) &
3087 SPE_HDR_FUNCTION_ID
);
3089 spe
->hdr
.type
= cpu_to_le16(type
);
3091 spe
->data
.update_data_addr
.hi
= cpu_to_le32(data_hi
);
3092 spe
->data
.update_data_addr
.lo
= cpu_to_le32(data_lo
);
3095 * It's ok if the actual decrement is issued towards the memory
3096 * somewhere between the spin_lock and spin_unlock. Thus no
3097 * more explict memory barrier is needed.
3100 atomic_dec(&bp
->eq_spq_left
);
3102 atomic_dec(&bp
->cq_spq_left
);
3105 DP(BNX2X_MSG_SP
/*NETIF_MSG_TIMER*/,
3106 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) "
3107 "type(0x%x) left (CQ, EQ) (%x,%x)\n",
3108 bp
->spq_prod_idx
, (u32
)U64_HI(bp
->spq_mapping
),
3109 (u32
)(U64_LO(bp
->spq_mapping
) +
3110 (void *)bp
->spq_prod_bd
- (void *)bp
->spq
), command
, common
,
3111 HW_CID(bp
, cid
), data_hi
, data_lo
, type
,
3112 atomic_read(&bp
->cq_spq_left
), atomic_read(&bp
->eq_spq_left
));
3114 bnx2x_sp_prod_update(bp
);
3115 spin_unlock_bh(&bp
->spq_lock
);
3119 /* acquire split MCP access lock register */
3120 static int bnx2x_acquire_alr(struct bnx2x
*bp
)
3126 for (j
= 0; j
< 1000; j
++) {
3128 REG_WR(bp
, GRCBASE_MCP
+ 0x9c, val
);
3129 val
= REG_RD(bp
, GRCBASE_MCP
+ 0x9c);
3130 if (val
& (1L << 31))
3135 if (!(val
& (1L << 31))) {
3136 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3143 /* release split MCP access lock register */
3144 static void bnx2x_release_alr(struct bnx2x
*bp
)
3146 REG_WR(bp
, GRCBASE_MCP
+ 0x9c, 0);
3149 #define BNX2X_DEF_SB_ATT_IDX 0x0001
3150 #define BNX2X_DEF_SB_IDX 0x0002
3152 static inline u16
bnx2x_update_dsb_idx(struct bnx2x
*bp
)
3154 struct host_sp_status_block
*def_sb
= bp
->def_status_blk
;
3157 barrier(); /* status block is written to by the chip */
3158 if (bp
->def_att_idx
!= def_sb
->atten_status_block
.attn_bits_index
) {
3159 bp
->def_att_idx
= def_sb
->atten_status_block
.attn_bits_index
;
3160 rc
|= BNX2X_DEF_SB_ATT_IDX
;
3163 if (bp
->def_idx
!= def_sb
->sp_sb
.running_index
) {
3164 bp
->def_idx
= def_sb
->sp_sb
.running_index
;
3165 rc
|= BNX2X_DEF_SB_IDX
;
3168 /* Do not reorder: indecies reading should complete before handling */
3174 * slow path service functions
3177 static void bnx2x_attn_int_asserted(struct bnx2x
*bp
, u32 asserted
)
3179 int port
= BP_PORT(bp
);
3180 u32 aeu_addr
= port
? MISC_REG_AEU_MASK_ATTN_FUNC_1
:
3181 MISC_REG_AEU_MASK_ATTN_FUNC_0
;
3182 u32 nig_int_mask_addr
= port
? NIG_REG_MASK_INTERRUPT_PORT1
:
3183 NIG_REG_MASK_INTERRUPT_PORT0
;
3188 if (bp
->attn_state
& asserted
)
3189 BNX2X_ERR("IGU ERROR\n");
3191 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_PORT0_ATT_MASK
+ port
);
3192 aeu_mask
= REG_RD(bp
, aeu_addr
);
3194 DP(NETIF_MSG_HW
, "aeu_mask %x newly asserted %x\n",
3195 aeu_mask
, asserted
);
3196 aeu_mask
&= ~(asserted
& 0x3ff);
3197 DP(NETIF_MSG_HW
, "new mask %x\n", aeu_mask
);
3199 REG_WR(bp
, aeu_addr
, aeu_mask
);
3200 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_PORT0_ATT_MASK
+ port
);
3202 DP(NETIF_MSG_HW
, "attn_state %x\n", bp
->attn_state
);
3203 bp
->attn_state
|= asserted
;
3204 DP(NETIF_MSG_HW
, "new state %x\n", bp
->attn_state
);
3206 if (asserted
& ATTN_HARD_WIRED_MASK
) {
3207 if (asserted
& ATTN_NIG_FOR_FUNC
) {
3209 bnx2x_acquire_phy_lock(bp
);
3211 /* save nig interrupt mask */
3212 nig_mask
= REG_RD(bp
, nig_int_mask_addr
);
3214 /* If nig_mask is not set, no need to call the update
3218 REG_WR(bp
, nig_int_mask_addr
, 0);
3220 bnx2x_link_attn(bp
);
3223 /* handle unicore attn? */
3225 if (asserted
& ATTN_SW_TIMER_4_FUNC
)
3226 DP(NETIF_MSG_HW
, "ATTN_SW_TIMER_4_FUNC!\n");
3228 if (asserted
& GPIO_2_FUNC
)
3229 DP(NETIF_MSG_HW
, "GPIO_2_FUNC!\n");
3231 if (asserted
& GPIO_3_FUNC
)
3232 DP(NETIF_MSG_HW
, "GPIO_3_FUNC!\n");
3234 if (asserted
& GPIO_4_FUNC
)
3235 DP(NETIF_MSG_HW
, "GPIO_4_FUNC!\n");
3238 if (asserted
& ATTN_GENERAL_ATTN_1
) {
3239 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_1!\n");
3240 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_1
, 0x0);
3242 if (asserted
& ATTN_GENERAL_ATTN_2
) {
3243 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_2!\n");
3244 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_2
, 0x0);
3246 if (asserted
& ATTN_GENERAL_ATTN_3
) {
3247 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_3!\n");
3248 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_3
, 0x0);
3251 if (asserted
& ATTN_GENERAL_ATTN_4
) {
3252 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_4!\n");
3253 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_4
, 0x0);
3255 if (asserted
& ATTN_GENERAL_ATTN_5
) {
3256 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_5!\n");
3257 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_5
, 0x0);
3259 if (asserted
& ATTN_GENERAL_ATTN_6
) {
3260 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_6!\n");
3261 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_6
, 0x0);
3265 } /* if hardwired */
3267 if (bp
->common
.int_block
== INT_BLOCK_HC
)
3268 reg_addr
= (HC_REG_COMMAND_REG
+ port
*32 +
3269 COMMAND_REG_ATTN_BITS_SET
);
3271 reg_addr
= (BAR_IGU_INTMEM
+ IGU_CMD_ATTN_BIT_SET_UPPER
*8);
3273 DP(NETIF_MSG_HW
, "about to mask 0x%08x at %s addr 0x%x\n", asserted
,
3274 (bp
->common
.int_block
== INT_BLOCK_HC
) ? "HC" : "IGU", reg_addr
);
3275 REG_WR(bp
, reg_addr
, asserted
);
3277 /* now set back the mask */
3278 if (asserted
& ATTN_NIG_FOR_FUNC
) {
3279 REG_WR(bp
, nig_int_mask_addr
, nig_mask
);
3280 bnx2x_release_phy_lock(bp
);
3284 static inline void bnx2x_fan_failure(struct bnx2x
*bp
)
3286 int port
= BP_PORT(bp
);
3288 /* mark the failure */
3291 dev_info
.port_hw_config
[port
].external_phy_config
);
3293 ext_phy_config
&= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK
;
3294 ext_phy_config
|= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE
;
3295 SHMEM_WR(bp
, dev_info
.port_hw_config
[port
].external_phy_config
,
3298 /* log the failure */
3299 netdev_err(bp
->dev
, "Fan Failure on Network Controller has caused"
3300 " the driver to shutdown the card to prevent permanent"
3301 " damage. Please contact OEM Support for assistance\n");
3304 * Scheudle device reset (unload)
3305 * This is due to some boards consuming sufficient power when driver is
3306 * up to overheat if fan fails.
3308 smp_mb__before_clear_bit();
3309 set_bit(BNX2X_SP_RTNL_FAN_FAILURE
, &bp
->sp_rtnl_state
);
3310 smp_mb__after_clear_bit();
3311 schedule_delayed_work(&bp
->sp_rtnl_task
, 0);
3315 static inline void bnx2x_attn_int_deasserted0(struct bnx2x
*bp
, u32 attn
)
3317 int port
= BP_PORT(bp
);
3321 reg_offset
= (port
? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0
:
3322 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0
);
3324 if (attn
& AEU_INPUTS_ATTN_BITS_SPIO5
) {
3326 val
= REG_RD(bp
, reg_offset
);
3327 val
&= ~AEU_INPUTS_ATTN_BITS_SPIO5
;
3328 REG_WR(bp
, reg_offset
, val
);
3330 BNX2X_ERR("SPIO5 hw attention\n");
3332 /* Fan failure attention */
3333 bnx2x_hw_reset_phy(&bp
->link_params
);
3334 bnx2x_fan_failure(bp
);
3337 if ((attn
& bp
->link_vars
.aeu_int_mask
) && bp
->port
.pmf
) {
3338 bnx2x_acquire_phy_lock(bp
);
3339 bnx2x_handle_module_detect_int(&bp
->link_params
);
3340 bnx2x_release_phy_lock(bp
);
3343 if (attn
& HW_INTERRUT_ASSERT_SET_0
) {
3345 val
= REG_RD(bp
, reg_offset
);
3346 val
&= ~(attn
& HW_INTERRUT_ASSERT_SET_0
);
3347 REG_WR(bp
, reg_offset
, val
);
3349 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3350 (u32
)(attn
& HW_INTERRUT_ASSERT_SET_0
));
3355 static inline void bnx2x_attn_int_deasserted1(struct bnx2x
*bp
, u32 attn
)
3359 if (attn
& AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT
) {
3361 val
= REG_RD(bp
, DORQ_REG_DORQ_INT_STS_CLR
);
3362 BNX2X_ERR("DB hw attention 0x%x\n", val
);
3363 /* DORQ discard attention */
3365 BNX2X_ERR("FATAL error from DORQ\n");
3368 if (attn
& HW_INTERRUT_ASSERT_SET_1
) {
3370 int port
= BP_PORT(bp
);
3373 reg_offset
= (port
? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1
:
3374 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1
);
3376 val
= REG_RD(bp
, reg_offset
);
3377 val
&= ~(attn
& HW_INTERRUT_ASSERT_SET_1
);
3378 REG_WR(bp
, reg_offset
, val
);
3380 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3381 (u32
)(attn
& HW_INTERRUT_ASSERT_SET_1
));
3386 static inline void bnx2x_attn_int_deasserted2(struct bnx2x
*bp
, u32 attn
)
3390 if (attn
& AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT
) {
3392 val
= REG_RD(bp
, CFC_REG_CFC_INT_STS_CLR
);
3393 BNX2X_ERR("CFC hw attention 0x%x\n", val
);
3394 /* CFC error attention */
3396 BNX2X_ERR("FATAL error from CFC\n");
3399 if (attn
& AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT
) {
3400 val
= REG_RD(bp
, PXP_REG_PXP_INT_STS_CLR_0
);
3401 BNX2X_ERR("PXP hw attention-0 0x%x\n", val
);
3402 /* RQ_USDMDP_FIFO_OVERFLOW */
3404 BNX2X_ERR("FATAL error from PXP\n");
3406 if (!CHIP_IS_E1x(bp
)) {
3407 val
= REG_RD(bp
, PXP_REG_PXP_INT_STS_CLR_1
);
3408 BNX2X_ERR("PXP hw attention-1 0x%x\n", val
);
3412 if (attn
& HW_INTERRUT_ASSERT_SET_2
) {
3414 int port
= BP_PORT(bp
);
3417 reg_offset
= (port
? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2
:
3418 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2
);
3420 val
= REG_RD(bp
, reg_offset
);
3421 val
&= ~(attn
& HW_INTERRUT_ASSERT_SET_2
);
3422 REG_WR(bp
, reg_offset
, val
);
3424 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3425 (u32
)(attn
& HW_INTERRUT_ASSERT_SET_2
));
3430 static inline void bnx2x_attn_int_deasserted3(struct bnx2x
*bp
, u32 attn
)
3434 if (attn
& EVEREST_GEN_ATTN_IN_USE_MASK
) {
3436 if (attn
& BNX2X_PMF_LINK_ASSERT
) {
3437 int func
= BP_FUNC(bp
);
3439 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_12
+ func
*4, 0);
3440 bp
->mf_config
[BP_VN(bp
)] = MF_CFG_RD(bp
,
3441 func_mf_config
[BP_ABS_FUNC(bp
)].config
);
3443 func_mb
[BP_FW_MB_IDX(bp
)].drv_status
);
3444 if (val
& DRV_STATUS_DCC_EVENT_MASK
)
3446 (val
& DRV_STATUS_DCC_EVENT_MASK
));
3448 if (val
& DRV_STATUS_SET_MF_BW
)
3449 bnx2x_set_mf_bw(bp
);
3451 if ((bp
->port
.pmf
== 0) && (val
& DRV_STATUS_PMF
))
3452 bnx2x_pmf_update(bp
);
3455 (val
& DRV_STATUS_DCBX_NEGOTIATION_RESULTS
) &&
3456 bp
->dcbx_enabled
> 0)
3457 /* start dcbx state machine */
3458 bnx2x_dcbx_set_params(bp
,
3459 BNX2X_DCBX_STATE_NEG_RECEIVED
);
3460 if (bp
->link_vars
.periodic_flags
&
3461 PERIODIC_FLAGS_LINK_EVENT
) {
3462 /* sync with link */
3463 bnx2x_acquire_phy_lock(bp
);
3464 bp
->link_vars
.periodic_flags
&=
3465 ~PERIODIC_FLAGS_LINK_EVENT
;
3466 bnx2x_release_phy_lock(bp
);
3468 bnx2x_link_sync_notify(bp
);
3469 bnx2x_link_report(bp
);
3471 /* Always call it here: bnx2x_link_report() will
3472 * prevent the link indication duplication.
3474 bnx2x__link_status_update(bp
);
3475 } else if (attn
& BNX2X_MC_ASSERT_BITS
) {
3477 BNX2X_ERR("MC assert!\n");
3478 bnx2x_mc_assert(bp
);
3479 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_10
, 0);
3480 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_9
, 0);
3481 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_8
, 0);
3482 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_7
, 0);
3485 } else if (attn
& BNX2X_MCP_ASSERT
) {
3487 BNX2X_ERR("MCP assert!\n");
3488 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_11
, 0);
3492 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn
);
3495 if (attn
& EVEREST_LATCHED_ATTN_IN_USE_MASK
) {
3496 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn
);
3497 if (attn
& BNX2X_GRC_TIMEOUT
) {
3498 val
= CHIP_IS_E1(bp
) ? 0 :
3499 REG_RD(bp
, MISC_REG_GRC_TIMEOUT_ATTN
);
3500 BNX2X_ERR("GRC time-out 0x%08x\n", val
);
3502 if (attn
& BNX2X_GRC_RSV
) {
3503 val
= CHIP_IS_E1(bp
) ? 0 :
3504 REG_RD(bp
, MISC_REG_GRC_RSV_ATTN
);
3505 BNX2X_ERR("GRC reserved 0x%08x\n", val
);
3507 REG_WR(bp
, MISC_REG_AEU_CLR_LATCH_SIGNAL
, 0x7ff);
3513 * 0-7 - Engine0 load counter.
3514 * 8-15 - Engine1 load counter.
3515 * 16 - Engine0 RESET_IN_PROGRESS bit.
3516 * 17 - Engine1 RESET_IN_PROGRESS bit.
3517 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
3519 * 19 - Engine1 ONE_IS_LOADED.
3520 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
3521 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
3522 * just the one belonging to its engine).
3525 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
3527 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
3528 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
3529 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
3530 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
3531 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
3532 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
3533 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
3536 * Set the GLOBAL_RESET bit.
3538 * Should be run under rtnl lock
3540 void bnx2x_set_reset_global(struct bnx2x
*bp
)
3542 u32 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
3544 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
| BNX2X_GLOBAL_RESET_BIT
);
3550 * Clear the GLOBAL_RESET bit.
3552 * Should be run under rtnl lock
3554 static inline void bnx2x_clear_reset_global(struct bnx2x
*bp
)
3556 u32 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
3558 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
& (~BNX2X_GLOBAL_RESET_BIT
));
3564 * Checks the GLOBAL_RESET bit.
3566 * should be run under rtnl lock
3568 static inline bool bnx2x_reset_is_global(struct bnx2x
*bp
)
3570 u32 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
3572 DP(NETIF_MSG_HW
, "GEN_REG_VAL=0x%08x\n", val
);
3573 return (val
& BNX2X_GLOBAL_RESET_BIT
) ? true : false;
3577 * Clear RESET_IN_PROGRESS bit for the current engine.
3579 * Should be run under rtnl lock
3581 static inline void bnx2x_set_reset_done(struct bnx2x
*bp
)
3583 u32 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
3584 u32 bit
= BP_PATH(bp
) ?
3585 BNX2X_PATH1_RST_IN_PROG_BIT
: BNX2X_PATH0_RST_IN_PROG_BIT
;
3589 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
);
3595 * Set RESET_IN_PROGRESS for the current engine.
3597 * should be run under rtnl lock
3599 void bnx2x_set_reset_in_progress(struct bnx2x
*bp
)
3601 u32 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
3602 u32 bit
= BP_PATH(bp
) ?
3603 BNX2X_PATH1_RST_IN_PROG_BIT
: BNX2X_PATH0_RST_IN_PROG_BIT
;
3607 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
);
3613 * Checks the RESET_IN_PROGRESS bit for the given engine.
3614 * should be run under rtnl lock
3616 bool bnx2x_reset_is_done(struct bnx2x
*bp
, int engine
)
3618 u32 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
3620 BNX2X_PATH1_RST_IN_PROG_BIT
: BNX2X_PATH0_RST_IN_PROG_BIT
;
3622 /* return false if bit is set */
3623 return (val
& bit
) ? false : true;
3627 * Increment the load counter for the current engine.
3629 * should be run under rtnl lock
3631 void bnx2x_inc_load_cnt(struct bnx2x
*bp
)
3633 u32 val1
, val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
3634 u32 mask
= BP_PATH(bp
) ? BNX2X_PATH1_LOAD_CNT_MASK
:
3635 BNX2X_PATH0_LOAD_CNT_MASK
;
3636 u32 shift
= BP_PATH(bp
) ? BNX2X_PATH1_LOAD_CNT_SHIFT
:
3637 BNX2X_PATH0_LOAD_CNT_SHIFT
;
3639 DP(NETIF_MSG_HW
, "Old GEN_REG_VAL=0x%08x\n", val
);
3641 /* get the current counter value */
3642 val1
= (val
& mask
) >> shift
;
3647 /* clear the old value */
3650 /* set the new one */
3651 val
|= ((val1
<< shift
) & mask
);
3653 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
);
3659 * bnx2x_dec_load_cnt - decrement the load counter
3661 * @bp: driver handle
3663 * Should be run under rtnl lock.
3664 * Decrements the load counter for the current engine. Returns
3665 * the new counter value.
3667 u32
bnx2x_dec_load_cnt(struct bnx2x
*bp
)
3669 u32 val1
, val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
3670 u32 mask
= BP_PATH(bp
) ? BNX2X_PATH1_LOAD_CNT_MASK
:
3671 BNX2X_PATH0_LOAD_CNT_MASK
;
3672 u32 shift
= BP_PATH(bp
) ? BNX2X_PATH1_LOAD_CNT_SHIFT
:
3673 BNX2X_PATH0_LOAD_CNT_SHIFT
;
3675 DP(NETIF_MSG_HW
, "Old GEN_REG_VAL=0x%08x\n", val
);
3677 /* get the current counter value */
3678 val1
= (val
& mask
) >> shift
;
3683 /* clear the old value */
3686 /* set the new one */
3687 val
|= ((val1
<< shift
) & mask
);
3689 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
);
3697 * Read the load counter for the current engine.
3699 * should be run under rtnl lock
3701 static inline u32
bnx2x_get_load_cnt(struct bnx2x
*bp
, int engine
)
3703 u32 mask
= (engine
? BNX2X_PATH1_LOAD_CNT_MASK
:
3704 BNX2X_PATH0_LOAD_CNT_MASK
);
3705 u32 shift
= (engine
? BNX2X_PATH1_LOAD_CNT_SHIFT
:
3706 BNX2X_PATH0_LOAD_CNT_SHIFT
);
3707 u32 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
3709 DP(NETIF_MSG_HW
, "GLOB_REG=0x%08x\n", val
);
3711 val
= (val
& mask
) >> shift
;
3713 DP(NETIF_MSG_HW
, "load_cnt for engine %d = %d\n", engine
, val
);
3719 * Reset the load counter for the current engine.
3721 * should be run under rtnl lock
3723 static inline void bnx2x_clear_load_cnt(struct bnx2x
*bp
)
3725 u32 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
3726 u32 mask
= (BP_PATH(bp
) ? BNX2X_PATH1_LOAD_CNT_MASK
:
3727 BNX2X_PATH0_LOAD_CNT_MASK
);
3729 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
& (~mask
));
3732 static inline void _print_next_block(int idx
, const char *blk
)
3734 pr_cont("%s%s", idx
? ", " : "", blk
);
3737 static inline int bnx2x_check_blocks_with_parity0(u32 sig
, int par_num
,
3742 for (i
= 0; sig
; i
++) {
3743 cur_bit
= ((u32
)0x1 << i
);
3744 if (sig
& cur_bit
) {
3746 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR
:
3748 _print_next_block(par_num
++, "BRB");
3750 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR
:
3752 _print_next_block(par_num
++, "PARSER");
3754 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR
:
3756 _print_next_block(par_num
++, "TSDM");
3758 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR
:
3760 _print_next_block(par_num
++,
3763 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR
:
3765 _print_next_block(par_num
++, "TCM");
3767 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR
:
3769 _print_next_block(par_num
++, "TSEMI");
3771 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR
:
3773 _print_next_block(par_num
++, "XPB");
3785 static inline int bnx2x_check_blocks_with_parity1(u32 sig
, int par_num
,
3786 bool *global
, bool print
)
3790 for (i
= 0; sig
; i
++) {
3791 cur_bit
= ((u32
)0x1 << i
);
3792 if (sig
& cur_bit
) {
3794 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR
:
3796 _print_next_block(par_num
++, "PBF");
3798 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR
:
3800 _print_next_block(par_num
++, "QM");
3802 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR
:
3804 _print_next_block(par_num
++, "TM");
3806 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR
:
3808 _print_next_block(par_num
++, "XSDM");
3810 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR
:
3812 _print_next_block(par_num
++, "XCM");
3814 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR
:
3816 _print_next_block(par_num
++, "XSEMI");
3818 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR
:
3820 _print_next_block(par_num
++,
3823 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR
:
3825 _print_next_block(par_num
++, "NIG");
3827 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR
:
3829 _print_next_block(par_num
++,
3833 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR
:
3835 _print_next_block(par_num
++, "DEBUG");
3837 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR
:
3839 _print_next_block(par_num
++, "USDM");
3841 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR
:
3843 _print_next_block(par_num
++, "UCM");
3845 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR
:
3847 _print_next_block(par_num
++, "USEMI");
3849 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR
:
3851 _print_next_block(par_num
++, "UPB");
3853 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR
:
3855 _print_next_block(par_num
++, "CSDM");
3857 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR
:
3859 _print_next_block(par_num
++, "CCM");
3871 static inline int bnx2x_check_blocks_with_parity2(u32 sig
, int par_num
,
3876 for (i
= 0; sig
; i
++) {
3877 cur_bit
= ((u32
)0x1 << i
);
3878 if (sig
& cur_bit
) {
3880 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR
:
3882 _print_next_block(par_num
++, "CSEMI");
3884 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR
:
3886 _print_next_block(par_num
++, "PXP");
3888 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
:
3890 _print_next_block(par_num
++,
3891 "PXPPCICLOCKCLIENT");
3893 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR
:
3895 _print_next_block(par_num
++, "CFC");
3897 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR
:
3899 _print_next_block(par_num
++, "CDU");
3901 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR
:
3903 _print_next_block(par_num
++, "DMAE");
3905 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR
:
3907 _print_next_block(par_num
++, "IGU");
3909 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR
:
3911 _print_next_block(par_num
++, "MISC");
3923 static inline int bnx2x_check_blocks_with_parity3(u32 sig
, int par_num
,
3924 bool *global
, bool print
)
3928 for (i
= 0; sig
; i
++) {
3929 cur_bit
= ((u32
)0x1 << i
);
3930 if (sig
& cur_bit
) {
3932 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY
:
3934 _print_next_block(par_num
++, "MCP ROM");
3937 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY
:
3939 _print_next_block(par_num
++,
3943 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY
:
3945 _print_next_block(par_num
++,
3949 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY
:
3951 _print_next_block(par_num
++,
3965 static inline int bnx2x_check_blocks_with_parity4(u32 sig
, int par_num
,
3970 for (i
= 0; sig
; i
++) {
3971 cur_bit
= ((u32
)0x1 << i
);
3972 if (sig
& cur_bit
) {
3974 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
:
3976 _print_next_block(par_num
++, "PGLUE_B");
3978 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR
:
3980 _print_next_block(par_num
++, "ATC");
3992 static inline bool bnx2x_parity_attn(struct bnx2x
*bp
, bool *global
, bool print
,
3995 if ((sig
[0] & HW_PRTY_ASSERT_SET_0
) ||
3996 (sig
[1] & HW_PRTY_ASSERT_SET_1
) ||
3997 (sig
[2] & HW_PRTY_ASSERT_SET_2
) ||
3998 (sig
[3] & HW_PRTY_ASSERT_SET_3
) ||
3999 (sig
[4] & HW_PRTY_ASSERT_SET_4
)) {
4001 DP(NETIF_MSG_HW
, "Was parity error: HW block parity attention: "
4002 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x "
4004 sig
[0] & HW_PRTY_ASSERT_SET_0
,
4005 sig
[1] & HW_PRTY_ASSERT_SET_1
,
4006 sig
[2] & HW_PRTY_ASSERT_SET_2
,
4007 sig
[3] & HW_PRTY_ASSERT_SET_3
,
4008 sig
[4] & HW_PRTY_ASSERT_SET_4
);
4011 "Parity errors detected in blocks: ");
4012 par_num
= bnx2x_check_blocks_with_parity0(
4013 sig
[0] & HW_PRTY_ASSERT_SET_0
, par_num
, print
);
4014 par_num
= bnx2x_check_blocks_with_parity1(
4015 sig
[1] & HW_PRTY_ASSERT_SET_1
, par_num
, global
, print
);
4016 par_num
= bnx2x_check_blocks_with_parity2(
4017 sig
[2] & HW_PRTY_ASSERT_SET_2
, par_num
, print
);
4018 par_num
= bnx2x_check_blocks_with_parity3(
4019 sig
[3] & HW_PRTY_ASSERT_SET_3
, par_num
, global
, print
);
4020 par_num
= bnx2x_check_blocks_with_parity4(
4021 sig
[4] & HW_PRTY_ASSERT_SET_4
, par_num
, print
);
4032 * bnx2x_chk_parity_attn - checks for parity attentions.
4034 * @bp: driver handle
4035 * @global: true if there was a global attention
4036 * @print: show parity attention in syslog
4038 bool bnx2x_chk_parity_attn(struct bnx2x
*bp
, bool *global
, bool print
)
4040 struct attn_route attn
= { {0} };
4041 int port
= BP_PORT(bp
);
4043 attn
.sig
[0] = REG_RD(bp
,
4044 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0
+
4046 attn
.sig
[1] = REG_RD(bp
,
4047 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0
+
4049 attn
.sig
[2] = REG_RD(bp
,
4050 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0
+
4052 attn
.sig
[3] = REG_RD(bp
,
4053 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0
+
4056 if (!CHIP_IS_E1x(bp
))
4057 attn
.sig
[4] = REG_RD(bp
,
4058 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0
+
4061 return bnx2x_parity_attn(bp
, global
, print
, attn
.sig
);
4065 static inline void bnx2x_attn_int_deasserted4(struct bnx2x
*bp
, u32 attn
)
4068 if (attn
& AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT
) {
4070 val
= REG_RD(bp
, PGLUE_B_REG_PGLUE_B_INT_STS_CLR
);
4071 BNX2X_ERR("PGLUE hw attention 0x%x\n", val
);
4072 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR
)
4073 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4075 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR
)
4076 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4077 "INCORRECT_RCV_BEHAVIOR\n");
4078 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN
)
4079 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4080 "WAS_ERROR_ATTN\n");
4081 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN
)
4082 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4083 "VF_LENGTH_VIOLATION_ATTN\n");
4085 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN
)
4086 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4087 "VF_GRC_SPACE_VIOLATION_ATTN\n");
4089 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN
)
4090 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4091 "VF_MSIX_BAR_VIOLATION_ATTN\n");
4092 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN
)
4093 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4094 "TCPL_ERROR_ATTN\n");
4095 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN
)
4096 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4097 "TCPL_IN_TWO_RCBS_ATTN\n");
4098 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW
)
4099 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4100 "CSSNOOP_FIFO_OVERFLOW\n");
4102 if (attn
& AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT
) {
4103 val
= REG_RD(bp
, ATC_REG_ATC_INT_STS_CLR
);
4104 BNX2X_ERR("ATC hw attention 0x%x\n", val
);
4105 if (val
& ATC_ATC_INT_STS_REG_ADDRESS_ERROR
)
4106 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4107 if (val
& ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND
)
4108 BNX2X_ERR("ATC_ATC_INT_STS_REG"
4109 "_ATC_TCPL_TO_NOT_PEND\n");
4110 if (val
& ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS
)
4111 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4112 "ATC_GPA_MULTIPLE_HITS\n");
4113 if (val
& ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT
)
4114 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4115 "ATC_RCPL_TO_EMPTY_CNT\n");
4116 if (val
& ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR
)
4117 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4118 if (val
& ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU
)
4119 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4120 "ATC_IREQ_LESS_THAN_STU\n");
4123 if (attn
& (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
|
4124 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR
)) {
4125 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4126 (u32
)(attn
& (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
|
4127 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR
)));
4132 static void bnx2x_attn_int_deasserted(struct bnx2x
*bp
, u32 deasserted
)
4134 struct attn_route attn
, *group_mask
;
4135 int port
= BP_PORT(bp
);
4140 bool global
= false;
4142 /* need to take HW lock because MCP or other port might also
4143 try to handle this event */
4144 bnx2x_acquire_alr(bp
);
4146 if (bnx2x_chk_parity_attn(bp
, &global
, true)) {
4147 #ifndef BNX2X_STOP_ON_ERROR
4148 bp
->recovery_state
= BNX2X_RECOVERY_INIT
;
4149 schedule_delayed_work(&bp
->sp_rtnl_task
, 0);
4150 /* Disable HW interrupts */
4151 bnx2x_int_disable(bp
);
4152 /* In case of parity errors don't handle attentions so that
4153 * other function would "see" parity errors.
4158 bnx2x_release_alr(bp
);
4162 attn
.sig
[0] = REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0
+ port
*4);
4163 attn
.sig
[1] = REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0
+ port
*4);
4164 attn
.sig
[2] = REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0
+ port
*4);
4165 attn
.sig
[3] = REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0
+ port
*4);
4166 if (!CHIP_IS_E1x(bp
))
4168 REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0
+ port
*4);
4172 DP(NETIF_MSG_HW
, "attn: %08x %08x %08x %08x %08x\n",
4173 attn
.sig
[0], attn
.sig
[1], attn
.sig
[2], attn
.sig
[3], attn
.sig
[4]);
4175 for (index
= 0; index
< MAX_DYNAMIC_ATTN_GRPS
; index
++) {
4176 if (deasserted
& (1 << index
)) {
4177 group_mask
= &bp
->attn_group
[index
];
4179 DP(NETIF_MSG_HW
, "group[%d]: %08x %08x "
4182 group_mask
->sig
[0], group_mask
->sig
[1],
4183 group_mask
->sig
[2], group_mask
->sig
[3],
4184 group_mask
->sig
[4]);
4186 bnx2x_attn_int_deasserted4(bp
,
4187 attn
.sig
[4] & group_mask
->sig
[4]);
4188 bnx2x_attn_int_deasserted3(bp
,
4189 attn
.sig
[3] & group_mask
->sig
[3]);
4190 bnx2x_attn_int_deasserted1(bp
,
4191 attn
.sig
[1] & group_mask
->sig
[1]);
4192 bnx2x_attn_int_deasserted2(bp
,
4193 attn
.sig
[2] & group_mask
->sig
[2]);
4194 bnx2x_attn_int_deasserted0(bp
,
4195 attn
.sig
[0] & group_mask
->sig
[0]);
4199 bnx2x_release_alr(bp
);
4201 if (bp
->common
.int_block
== INT_BLOCK_HC
)
4202 reg_addr
= (HC_REG_COMMAND_REG
+ port
*32 +
4203 COMMAND_REG_ATTN_BITS_CLR
);
4205 reg_addr
= (BAR_IGU_INTMEM
+ IGU_CMD_ATTN_BIT_CLR_UPPER
*8);
4208 DP(NETIF_MSG_HW
, "about to mask 0x%08x at %s addr 0x%x\n", val
,
4209 (bp
->common
.int_block
== INT_BLOCK_HC
) ? "HC" : "IGU", reg_addr
);
4210 REG_WR(bp
, reg_addr
, val
);
4212 if (~bp
->attn_state
& deasserted
)
4213 BNX2X_ERR("IGU ERROR\n");
4215 reg_addr
= port
? MISC_REG_AEU_MASK_ATTN_FUNC_1
:
4216 MISC_REG_AEU_MASK_ATTN_FUNC_0
;
4218 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_PORT0_ATT_MASK
+ port
);
4219 aeu_mask
= REG_RD(bp
, reg_addr
);
4221 DP(NETIF_MSG_HW
, "aeu_mask %x newly deasserted %x\n",
4222 aeu_mask
, deasserted
);
4223 aeu_mask
|= (deasserted
& 0x3ff);
4224 DP(NETIF_MSG_HW
, "new mask %x\n", aeu_mask
);
4226 REG_WR(bp
, reg_addr
, aeu_mask
);
4227 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_PORT0_ATT_MASK
+ port
);
4229 DP(NETIF_MSG_HW
, "attn_state %x\n", bp
->attn_state
);
4230 bp
->attn_state
&= ~deasserted
;
4231 DP(NETIF_MSG_HW
, "new state %x\n", bp
->attn_state
);
4234 static void bnx2x_attn_int(struct bnx2x
*bp
)
4236 /* read local copy of bits */
4237 u32 attn_bits
= le32_to_cpu(bp
->def_status_blk
->atten_status_block
.
4239 u32 attn_ack
= le32_to_cpu(bp
->def_status_blk
->atten_status_block
.
4241 u32 attn_state
= bp
->attn_state
;
4243 /* look for changed bits */
4244 u32 asserted
= attn_bits
& ~attn_ack
& ~attn_state
;
4245 u32 deasserted
= ~attn_bits
& attn_ack
& attn_state
;
4248 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
4249 attn_bits
, attn_ack
, asserted
, deasserted
);
4251 if (~(attn_bits
^ attn_ack
) & (attn_bits
^ attn_state
))
4252 BNX2X_ERR("BAD attention state\n");
4254 /* handle bits that were raised */
4256 bnx2x_attn_int_asserted(bp
, asserted
);
4259 bnx2x_attn_int_deasserted(bp
, deasserted
);
4262 void bnx2x_igu_ack_sb(struct bnx2x
*bp
, u8 igu_sb_id
, u8 segment
,
4263 u16 index
, u8 op
, u8 update
)
4265 u32 igu_addr
= BAR_IGU_INTMEM
+ (IGU_CMD_INT_ACK_BASE
+ igu_sb_id
)*8;
4267 bnx2x_igu_ack_sb_gen(bp
, igu_sb_id
, segment
, index
, op
, update
,
4271 static inline void bnx2x_update_eq_prod(struct bnx2x
*bp
, u16 prod
)
4273 /* No memory barriers */
4274 storm_memset_eq_prod(bp
, prod
, BP_FUNC(bp
));
4275 mmiowb(); /* keep prod updates ordered */
4279 static int bnx2x_cnic_handle_cfc_del(struct bnx2x
*bp
, u32 cid
,
4280 union event_ring_elem
*elem
)
4282 u8 err
= elem
->message
.error
;
4284 if (!bp
->cnic_eth_dev
.starting_cid
||
4285 (cid
< bp
->cnic_eth_dev
.starting_cid
&&
4286 cid
!= bp
->cnic_eth_dev
.iscsi_l2_cid
))
4289 DP(BNX2X_MSG_SP
, "got delete ramrod for CNIC CID %d\n", cid
);
4291 if (unlikely(err
)) {
4293 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4295 bnx2x_panic_dump(bp
);
4297 bnx2x_cnic_cfc_comp(bp
, cid
, err
);
4302 static inline void bnx2x_handle_mcast_eqe(struct bnx2x
*bp
)
4304 struct bnx2x_mcast_ramrod_params rparam
;
4307 memset(&rparam
, 0, sizeof(rparam
));
4309 rparam
.mcast_obj
= &bp
->mcast_obj
;
4311 netif_addr_lock_bh(bp
->dev
);
4313 /* Clear pending state for the last command */
4314 bp
->mcast_obj
.raw
.clear_pending(&bp
->mcast_obj
.raw
);
4316 /* If there are pending mcast commands - send them */
4317 if (bp
->mcast_obj
.check_pending(&bp
->mcast_obj
)) {
4318 rc
= bnx2x_config_mcast(bp
, &rparam
, BNX2X_MCAST_CMD_CONT
);
4320 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4324 netif_addr_unlock_bh(bp
->dev
);
4327 static inline void bnx2x_handle_classification_eqe(struct bnx2x
*bp
,
4328 union event_ring_elem
*elem
)
4330 unsigned long ramrod_flags
= 0;
4332 u32 cid
= elem
->message
.data
.eth_event
.echo
& BNX2X_SWCID_MASK
;
4333 struct bnx2x_vlan_mac_obj
*vlan_mac_obj
;
4335 /* Always push next commands out, don't wait here */
4336 __set_bit(RAMROD_CONT
, &ramrod_flags
);
4338 switch (elem
->message
.data
.eth_event
.echo
>> BNX2X_SWCID_SHIFT
) {
4339 case BNX2X_FILTER_MAC_PENDING
:
4341 if (cid
== BNX2X_ISCSI_ETH_CID
)
4342 vlan_mac_obj
= &bp
->iscsi_l2_mac_obj
;
4345 vlan_mac_obj
= &bp
->fp
[cid
].mac_obj
;
4348 case BNX2X_FILTER_MCAST_PENDING
:
4349 /* This is only relevant for 57710 where multicast MACs are
4350 * configured as unicast MACs using the same ramrod.
4352 bnx2x_handle_mcast_eqe(bp
);
4355 BNX2X_ERR("Unsupported classification command: %d\n",
4356 elem
->message
.data
.eth_event
.echo
);
4360 rc
= vlan_mac_obj
->complete(bp
, vlan_mac_obj
, elem
, &ramrod_flags
);
4363 BNX2X_ERR("Failed to schedule new commands: %d\n", rc
);
4365 DP(BNX2X_MSG_SP
, "Scheduled next pending commands...\n");
4370 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x
*bp
, bool start
);
4373 static inline void bnx2x_handle_rx_mode_eqe(struct bnx2x
*bp
)
4375 netif_addr_lock_bh(bp
->dev
);
4377 clear_bit(BNX2X_FILTER_RX_MODE_PENDING
, &bp
->sp_state
);
4379 /* Send rx_mode command again if was requested */
4380 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED
, &bp
->sp_state
))
4381 bnx2x_set_storm_rx_mode(bp
);
4383 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED
,
4385 bnx2x_set_iscsi_eth_rx_mode(bp
, true);
4386 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED
,
4388 bnx2x_set_iscsi_eth_rx_mode(bp
, false);
4391 netif_addr_unlock_bh(bp
->dev
);
4394 static inline struct bnx2x_queue_sp_obj
*bnx2x_cid_to_q_obj(
4395 struct bnx2x
*bp
, u32 cid
)
4397 DP(BNX2X_MSG_SP
, "retrieving fp from cid %d\n", cid
);
4399 if (cid
== BNX2X_FCOE_ETH_CID
)
4400 return &bnx2x_fcoe(bp
, q_obj
);
4403 return &bnx2x_fp(bp
, CID_TO_FP(cid
), q_obj
);
4406 static void bnx2x_eq_int(struct bnx2x
*bp
)
4408 u16 hw_cons
, sw_cons
, sw_prod
;
4409 union event_ring_elem
*elem
;
4413 struct bnx2x_queue_sp_obj
*q_obj
;
4414 struct bnx2x_func_sp_obj
*f_obj
= &bp
->func_obj
;
4415 struct bnx2x_raw_obj
*rss_raw
= &bp
->rss_conf_obj
.raw
;
4417 hw_cons
= le16_to_cpu(*bp
->eq_cons_sb
);
4419 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
4420 * when we get the the next-page we nned to adjust so the loop
4421 * condition below will be met. The next element is the size of a
4422 * regular element and hence incrementing by 1
4424 if ((hw_cons
& EQ_DESC_MAX_PAGE
) == EQ_DESC_MAX_PAGE
)
4427 /* This function may never run in parallel with itself for a
4428 * specific bp, thus there is no need in "paired" read memory
4431 sw_cons
= bp
->eq_cons
;
4432 sw_prod
= bp
->eq_prod
;
4434 DP(BNX2X_MSG_SP
, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
4435 hw_cons
, sw_cons
, atomic_read(&bp
->eq_spq_left
));
4437 for (; sw_cons
!= hw_cons
;
4438 sw_prod
= NEXT_EQ_IDX(sw_prod
), sw_cons
= NEXT_EQ_IDX(sw_cons
)) {
4441 elem
= &bp
->eq_ring
[EQ_DESC(sw_cons
)];
4443 cid
= SW_CID(elem
->message
.data
.cfc_del_event
.cid
);
4444 opcode
= elem
->message
.opcode
;
4447 /* handle eq element */
4449 case EVENT_RING_OPCODE_STAT_QUERY
:
4450 DP(NETIF_MSG_TIMER
, "got statistics comp event %d\n",
4452 /* nothing to do with stats comp */
4455 case EVENT_RING_OPCODE_CFC_DEL
:
4456 /* handle according to cid range */
4458 * we may want to verify here that the bp state is
4462 "got delete ramrod for MULTI[%d]\n", cid
);
4464 if (!bnx2x_cnic_handle_cfc_del(bp
, cid
, elem
))
4467 q_obj
= bnx2x_cid_to_q_obj(bp
, cid
);
4469 if (q_obj
->complete_cmd(bp
, q_obj
, BNX2X_Q_CMD_CFC_DEL
))
4476 case EVENT_RING_OPCODE_STOP_TRAFFIC
:
4477 DP(BNX2X_MSG_SP
, "got STOP TRAFFIC\n");
4478 if (f_obj
->complete_cmd(bp
, f_obj
,
4479 BNX2X_F_CMD_TX_STOP
))
4481 bnx2x_dcbx_set_params(bp
, BNX2X_DCBX_STATE_TX_PAUSED
);
4484 case EVENT_RING_OPCODE_START_TRAFFIC
:
4485 DP(BNX2X_MSG_SP
, "got START TRAFFIC\n");
4486 if (f_obj
->complete_cmd(bp
, f_obj
,
4487 BNX2X_F_CMD_TX_START
))
4489 bnx2x_dcbx_set_params(bp
, BNX2X_DCBX_STATE_TX_RELEASED
);
4491 case EVENT_RING_OPCODE_FUNCTION_START
:
4492 DP(BNX2X_MSG_SP
, "got FUNC_START ramrod\n");
4493 if (f_obj
->complete_cmd(bp
, f_obj
, BNX2X_F_CMD_START
))
4498 case EVENT_RING_OPCODE_FUNCTION_STOP
:
4499 DP(BNX2X_MSG_SP
, "got FUNC_STOP ramrod\n");
4500 if (f_obj
->complete_cmd(bp
, f_obj
, BNX2X_F_CMD_STOP
))
4506 switch (opcode
| bp
->state
) {
4507 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES
|
4509 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES
|
4510 BNX2X_STATE_OPENING_WAIT4_PORT
):
4511 cid
= elem
->message
.data
.eth_event
.echo
&
4513 DP(BNX2X_MSG_SP
, "got RSS_UPDATE ramrod. CID %d\n",
4515 rss_raw
->clear_pending(rss_raw
);
4518 case (EVENT_RING_OPCODE_SET_MAC
| BNX2X_STATE_OPEN
):
4519 case (EVENT_RING_OPCODE_SET_MAC
| BNX2X_STATE_DIAG
):
4520 case (EVENT_RING_OPCODE_SET_MAC
|
4521 BNX2X_STATE_CLOSING_WAIT4_HALT
):
4522 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES
|
4524 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES
|
4526 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES
|
4527 BNX2X_STATE_CLOSING_WAIT4_HALT
):
4528 DP(BNX2X_MSG_SP
, "got (un)set mac ramrod\n");
4529 bnx2x_handle_classification_eqe(bp
, elem
);
4532 case (EVENT_RING_OPCODE_MULTICAST_RULES
|
4534 case (EVENT_RING_OPCODE_MULTICAST_RULES
|
4536 case (EVENT_RING_OPCODE_MULTICAST_RULES
|
4537 BNX2X_STATE_CLOSING_WAIT4_HALT
):
4538 DP(BNX2X_MSG_SP
, "got mcast ramrod\n");
4539 bnx2x_handle_mcast_eqe(bp
);
4542 case (EVENT_RING_OPCODE_FILTERS_RULES
|
4544 case (EVENT_RING_OPCODE_FILTERS_RULES
|
4546 case (EVENT_RING_OPCODE_FILTERS_RULES
|
4547 BNX2X_STATE_CLOSING_WAIT4_HALT
):
4548 DP(BNX2X_MSG_SP
, "got rx_mode ramrod\n");
4549 bnx2x_handle_rx_mode_eqe(bp
);
4552 /* unknown event log error and continue */
4553 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
4554 elem
->message
.opcode
, bp
->state
);
4560 smp_mb__before_atomic_inc();
4561 atomic_add(spqe_cnt
, &bp
->eq_spq_left
);
4563 bp
->eq_cons
= sw_cons
;
4564 bp
->eq_prod
= sw_prod
;
4565 /* Make sure that above mem writes were issued towards the memory */
4568 /* update producer */
4569 bnx2x_update_eq_prod(bp
, bp
->eq_prod
);
4572 static void bnx2x_sp_task(struct work_struct
*work
)
4574 struct bnx2x
*bp
= container_of(work
, struct bnx2x
, sp_task
.work
);
4577 status
= bnx2x_update_dsb_idx(bp
);
4578 /* if (status == 0) */
4579 /* BNX2X_ERR("spurious slowpath interrupt!\n"); */
4581 DP(NETIF_MSG_INTR
, "got a slowpath interrupt (status 0x%x)\n", status
);
4584 if (status
& BNX2X_DEF_SB_ATT_IDX
) {
4586 status
&= ~BNX2X_DEF_SB_ATT_IDX
;
4589 /* SP events: STAT_QUERY and others */
4590 if (status
& BNX2X_DEF_SB_IDX
) {
4592 struct bnx2x_fastpath
*fp
= bnx2x_fcoe_fp(bp
);
4594 if ((!NO_FCOE(bp
)) &&
4595 (bnx2x_has_rx_work(fp
) || bnx2x_has_tx_work(fp
))) {
4597 * Prevent local bottom-halves from running as
4598 * we are going to change the local NAPI list.
4601 napi_schedule(&bnx2x_fcoe(bp
, napi
));
4605 /* Handle EQ completions */
4608 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
, USTORM_ID
,
4609 le16_to_cpu(bp
->def_idx
), IGU_INT_NOP
, 1);
4611 status
&= ~BNX2X_DEF_SB_IDX
;
4614 if (unlikely(status
))
4615 DP(NETIF_MSG_INTR
, "got an unknown interrupt! (status 0x%x)\n",
4618 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
, ATTENTION_ID
,
4619 le16_to_cpu(bp
->def_att_idx
), IGU_INT_ENABLE
, 1);
4622 irqreturn_t
bnx2x_msix_sp_int(int irq
, void *dev_instance
)
4624 struct net_device
*dev
= dev_instance
;
4625 struct bnx2x
*bp
= netdev_priv(dev
);
4627 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
, USTORM_ID
, 0,
4628 IGU_INT_DISABLE
, 0);
4630 #ifdef BNX2X_STOP_ON_ERROR
4631 if (unlikely(bp
->panic
))
4637 struct cnic_ops
*c_ops
;
4640 c_ops
= rcu_dereference(bp
->cnic_ops
);
4642 c_ops
->cnic_handler(bp
->cnic_data
, NULL
);
4646 queue_delayed_work(bnx2x_wq
, &bp
->sp_task
, 0);
4651 /* end of slow path */
4654 void bnx2x_drv_pulse(struct bnx2x
*bp
)
4656 SHMEM_WR(bp
, func_mb
[BP_FW_MB_IDX(bp
)].drv_pulse_mb
,
4657 bp
->fw_drv_pulse_wr_seq
);
4661 static void bnx2x_timer(unsigned long data
)
4664 struct bnx2x
*bp
= (struct bnx2x
*) data
;
4666 if (!netif_running(bp
->dev
))
4670 struct bnx2x_fastpath
*fp
= &bp
->fp
[0];
4672 for_each_cos_in_tx_queue(fp
, cos
)
4673 bnx2x_tx_int(bp
, &fp
->txdata
[cos
]);
4674 bnx2x_rx_int(fp
, 1000);
4677 if (!BP_NOMCP(bp
)) {
4678 int mb_idx
= BP_FW_MB_IDX(bp
);
4682 ++bp
->fw_drv_pulse_wr_seq
;
4683 bp
->fw_drv_pulse_wr_seq
&= DRV_PULSE_SEQ_MASK
;
4684 /* TBD - add SYSTEM_TIME */
4685 drv_pulse
= bp
->fw_drv_pulse_wr_seq
;
4686 bnx2x_drv_pulse(bp
);
4688 mcp_pulse
= (SHMEM_RD(bp
, func_mb
[mb_idx
].mcp_pulse_mb
) &
4689 MCP_PULSE_SEQ_MASK
);
4690 /* The delta between driver pulse and mcp response
4691 * should be 1 (before mcp response) or 0 (after mcp response)
4693 if ((drv_pulse
!= mcp_pulse
) &&
4694 (drv_pulse
!= ((mcp_pulse
+ 1) & MCP_PULSE_SEQ_MASK
))) {
4695 /* someone lost a heartbeat... */
4696 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
4697 drv_pulse
, mcp_pulse
);
4701 if (bp
->state
== BNX2X_STATE_OPEN
)
4702 bnx2x_stats_handle(bp
, STATS_EVENT_UPDATE
);
4704 mod_timer(&bp
->timer
, jiffies
+ bp
->current_interval
);
4707 /* end of Statistics */
4712 * nic init service functions
4715 static inline void bnx2x_fill(struct bnx2x
*bp
, u32 addr
, int fill
, u32 len
)
4718 if (!(len
%4) && !(addr
%4))
4719 for (i
= 0; i
< len
; i
+= 4)
4720 REG_WR(bp
, addr
+ i
, fill
);
4722 for (i
= 0; i
< len
; i
++)
4723 REG_WR8(bp
, addr
+ i
, fill
);
4727 /* helper: writes FP SP data to FW - data_size in dwords */
4728 static inline void bnx2x_wr_fp_sb_data(struct bnx2x
*bp
,
4734 for (index
= 0; index
< data_size
; index
++)
4735 REG_WR(bp
, BAR_CSTRORM_INTMEM
+
4736 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id
) +
4738 *(sb_data_p
+ index
));
4741 static inline void bnx2x_zero_fp_sb(struct bnx2x
*bp
, int fw_sb_id
)
4745 struct hc_status_block_data_e2 sb_data_e2
;
4746 struct hc_status_block_data_e1x sb_data_e1x
;
4748 /* disable the function first */
4749 if (!CHIP_IS_E1x(bp
)) {
4750 memset(&sb_data_e2
, 0, sizeof(struct hc_status_block_data_e2
));
4751 sb_data_e2
.common
.state
= SB_DISABLED
;
4752 sb_data_e2
.common
.p_func
.vf_valid
= false;
4753 sb_data_p
= (u32
*)&sb_data_e2
;
4754 data_size
= sizeof(struct hc_status_block_data_e2
)/sizeof(u32
);
4756 memset(&sb_data_e1x
, 0,
4757 sizeof(struct hc_status_block_data_e1x
));
4758 sb_data_e1x
.common
.state
= SB_DISABLED
;
4759 sb_data_e1x
.common
.p_func
.vf_valid
= false;
4760 sb_data_p
= (u32
*)&sb_data_e1x
;
4761 data_size
= sizeof(struct hc_status_block_data_e1x
)/sizeof(u32
);
4763 bnx2x_wr_fp_sb_data(bp
, fw_sb_id
, sb_data_p
, data_size
);
4765 bnx2x_fill(bp
, BAR_CSTRORM_INTMEM
+
4766 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id
), 0,
4767 CSTORM_STATUS_BLOCK_SIZE
);
4768 bnx2x_fill(bp
, BAR_CSTRORM_INTMEM
+
4769 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id
), 0,
4770 CSTORM_SYNC_BLOCK_SIZE
);
4773 /* helper: writes SP SB data to FW */
4774 static inline void bnx2x_wr_sp_sb_data(struct bnx2x
*bp
,
4775 struct hc_sp_status_block_data
*sp_sb_data
)
4777 int func
= BP_FUNC(bp
);
4779 for (i
= 0; i
< sizeof(struct hc_sp_status_block_data
)/sizeof(u32
); i
++)
4780 REG_WR(bp
, BAR_CSTRORM_INTMEM
+
4781 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func
) +
4783 *((u32
*)sp_sb_data
+ i
));
4786 static inline void bnx2x_zero_sp_sb(struct bnx2x
*bp
)
4788 int func
= BP_FUNC(bp
);
4789 struct hc_sp_status_block_data sp_sb_data
;
4790 memset(&sp_sb_data
, 0, sizeof(struct hc_sp_status_block_data
));
4792 sp_sb_data
.state
= SB_DISABLED
;
4793 sp_sb_data
.p_func
.vf_valid
= false;
4795 bnx2x_wr_sp_sb_data(bp
, &sp_sb_data
);
4797 bnx2x_fill(bp
, BAR_CSTRORM_INTMEM
+
4798 CSTORM_SP_STATUS_BLOCK_OFFSET(func
), 0,
4799 CSTORM_SP_STATUS_BLOCK_SIZE
);
4800 bnx2x_fill(bp
, BAR_CSTRORM_INTMEM
+
4801 CSTORM_SP_SYNC_BLOCK_OFFSET(func
), 0,
4802 CSTORM_SP_SYNC_BLOCK_SIZE
);
4808 void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm
*hc_sm
,
4809 int igu_sb_id
, int igu_seg_id
)
4811 hc_sm
->igu_sb_id
= igu_sb_id
;
4812 hc_sm
->igu_seg_id
= igu_seg_id
;
4813 hc_sm
->timer_value
= 0xFF;
4814 hc_sm
->time_to_expire
= 0xFFFFFFFF;
4818 /* allocates state machine ids. */
4820 void bnx2x_map_sb_state_machines(struct hc_index_data
*index_data
)
4822 /* zero out state machine indices */
4824 index_data
[HC_INDEX_ETH_RX_CQ_CONS
].flags
&= ~HC_INDEX_DATA_SM_ID
;
4827 index_data
[HC_INDEX_OOO_TX_CQ_CONS
].flags
&= ~HC_INDEX_DATA_SM_ID
;
4828 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS0
].flags
&= ~HC_INDEX_DATA_SM_ID
;
4829 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS1
].flags
&= ~HC_INDEX_DATA_SM_ID
;
4830 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS2
].flags
&= ~HC_INDEX_DATA_SM_ID
;
4834 index_data
[HC_INDEX_ETH_RX_CQ_CONS
].flags
|=
4835 SM_RX_ID
<< HC_INDEX_DATA_SM_ID_SHIFT
;
4838 index_data
[HC_INDEX_OOO_TX_CQ_CONS
].flags
|=
4839 SM_TX_ID
<< HC_INDEX_DATA_SM_ID_SHIFT
;
4840 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS0
].flags
|=
4841 SM_TX_ID
<< HC_INDEX_DATA_SM_ID_SHIFT
;
4842 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS1
].flags
|=
4843 SM_TX_ID
<< HC_INDEX_DATA_SM_ID_SHIFT
;
4844 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS2
].flags
|=
4845 SM_TX_ID
<< HC_INDEX_DATA_SM_ID_SHIFT
;
4848 static void bnx2x_init_sb(struct bnx2x
*bp
, dma_addr_t mapping
, int vfid
,
4849 u8 vf_valid
, int fw_sb_id
, int igu_sb_id
)
4853 struct hc_status_block_data_e2 sb_data_e2
;
4854 struct hc_status_block_data_e1x sb_data_e1x
;
4855 struct hc_status_block_sm
*hc_sm_p
;
4859 if (CHIP_INT_MODE_IS_BC(bp
))
4860 igu_seg_id
= HC_SEG_ACCESS_NORM
;
4862 igu_seg_id
= IGU_SEG_ACCESS_NORM
;
4864 bnx2x_zero_fp_sb(bp
, fw_sb_id
);
4866 if (!CHIP_IS_E1x(bp
)) {
4867 memset(&sb_data_e2
, 0, sizeof(struct hc_status_block_data_e2
));
4868 sb_data_e2
.common
.state
= SB_ENABLED
;
4869 sb_data_e2
.common
.p_func
.pf_id
= BP_FUNC(bp
);
4870 sb_data_e2
.common
.p_func
.vf_id
= vfid
;
4871 sb_data_e2
.common
.p_func
.vf_valid
= vf_valid
;
4872 sb_data_e2
.common
.p_func
.vnic_id
= BP_VN(bp
);
4873 sb_data_e2
.common
.same_igu_sb_1b
= true;
4874 sb_data_e2
.common
.host_sb_addr
.hi
= U64_HI(mapping
);
4875 sb_data_e2
.common
.host_sb_addr
.lo
= U64_LO(mapping
);
4876 hc_sm_p
= sb_data_e2
.common
.state_machine
;
4877 sb_data_p
= (u32
*)&sb_data_e2
;
4878 data_size
= sizeof(struct hc_status_block_data_e2
)/sizeof(u32
);
4879 bnx2x_map_sb_state_machines(sb_data_e2
.index_data
);
4881 memset(&sb_data_e1x
, 0,
4882 sizeof(struct hc_status_block_data_e1x
));
4883 sb_data_e1x
.common
.state
= SB_ENABLED
;
4884 sb_data_e1x
.common
.p_func
.pf_id
= BP_FUNC(bp
);
4885 sb_data_e1x
.common
.p_func
.vf_id
= 0xff;
4886 sb_data_e1x
.common
.p_func
.vf_valid
= false;
4887 sb_data_e1x
.common
.p_func
.vnic_id
= BP_VN(bp
);
4888 sb_data_e1x
.common
.same_igu_sb_1b
= true;
4889 sb_data_e1x
.common
.host_sb_addr
.hi
= U64_HI(mapping
);
4890 sb_data_e1x
.common
.host_sb_addr
.lo
= U64_LO(mapping
);
4891 hc_sm_p
= sb_data_e1x
.common
.state_machine
;
4892 sb_data_p
= (u32
*)&sb_data_e1x
;
4893 data_size
= sizeof(struct hc_status_block_data_e1x
)/sizeof(u32
);
4894 bnx2x_map_sb_state_machines(sb_data_e1x
.index_data
);
4897 bnx2x_setup_ndsb_state_machine(&hc_sm_p
[SM_RX_ID
],
4898 igu_sb_id
, igu_seg_id
);
4899 bnx2x_setup_ndsb_state_machine(&hc_sm_p
[SM_TX_ID
],
4900 igu_sb_id
, igu_seg_id
);
4902 DP(NETIF_MSG_HW
, "Init FW SB %d\n", fw_sb_id
);
4904 /* write indecies to HW */
4905 bnx2x_wr_fp_sb_data(bp
, fw_sb_id
, sb_data_p
, data_size
);
4908 static void bnx2x_update_coalesce_sb(struct bnx2x
*bp
, u8 fw_sb_id
,
4909 u16 tx_usec
, u16 rx_usec
)
4911 bnx2x_update_coalesce_sb_index(bp
, fw_sb_id
, HC_INDEX_ETH_RX_CQ_CONS
,
4913 bnx2x_update_coalesce_sb_index(bp
, fw_sb_id
,
4914 HC_INDEX_ETH_TX_CQ_CONS_COS0
, false,
4916 bnx2x_update_coalesce_sb_index(bp
, fw_sb_id
,
4917 HC_INDEX_ETH_TX_CQ_CONS_COS1
, false,
4919 bnx2x_update_coalesce_sb_index(bp
, fw_sb_id
,
4920 HC_INDEX_ETH_TX_CQ_CONS_COS2
, false,
4924 static void bnx2x_init_def_sb(struct bnx2x
*bp
)
4926 struct host_sp_status_block
*def_sb
= bp
->def_status_blk
;
4927 dma_addr_t mapping
= bp
->def_status_blk_mapping
;
4928 int igu_sp_sb_index
;
4930 int port
= BP_PORT(bp
);
4931 int func
= BP_FUNC(bp
);
4932 int reg_offset
, reg_offset_en5
;
4935 struct hc_sp_status_block_data sp_sb_data
;
4936 memset(&sp_sb_data
, 0, sizeof(struct hc_sp_status_block_data
));
4938 if (CHIP_INT_MODE_IS_BC(bp
)) {
4939 igu_sp_sb_index
= DEF_SB_IGU_ID
;
4940 igu_seg_id
= HC_SEG_ACCESS_DEF
;
4942 igu_sp_sb_index
= bp
->igu_dsb_id
;
4943 igu_seg_id
= IGU_SEG_ACCESS_DEF
;
4947 section
= ((u64
)mapping
) + offsetof(struct host_sp_status_block
,
4948 atten_status_block
);
4949 def_sb
->atten_status_block
.status_block_id
= igu_sp_sb_index
;
4953 reg_offset
= (port
? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0
:
4954 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0
);
4955 reg_offset_en5
= (port
? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0
:
4956 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0
);
4957 for (index
= 0; index
< MAX_DYNAMIC_ATTN_GRPS
; index
++) {
4959 /* take care of sig[0]..sig[4] */
4960 for (sindex
= 0; sindex
< 4; sindex
++)
4961 bp
->attn_group
[index
].sig
[sindex
] =
4962 REG_RD(bp
, reg_offset
+ sindex
*0x4 + 0x10*index
);
4964 if (!CHIP_IS_E1x(bp
))
4966 * enable5 is separate from the rest of the registers,
4967 * and therefore the address skip is 4
4968 * and not 16 between the different groups
4970 bp
->attn_group
[index
].sig
[4] = REG_RD(bp
,
4971 reg_offset_en5
+ 0x4*index
);
4973 bp
->attn_group
[index
].sig
[4] = 0;
4976 if (bp
->common
.int_block
== INT_BLOCK_HC
) {
4977 reg_offset
= (port
? HC_REG_ATTN_MSG1_ADDR_L
:
4978 HC_REG_ATTN_MSG0_ADDR_L
);
4980 REG_WR(bp
, reg_offset
, U64_LO(section
));
4981 REG_WR(bp
, reg_offset
+ 4, U64_HI(section
));
4982 } else if (!CHIP_IS_E1x(bp
)) {
4983 REG_WR(bp
, IGU_REG_ATTN_MSG_ADDR_L
, U64_LO(section
));
4984 REG_WR(bp
, IGU_REG_ATTN_MSG_ADDR_H
, U64_HI(section
));
4987 section
= ((u64
)mapping
) + offsetof(struct host_sp_status_block
,
4990 bnx2x_zero_sp_sb(bp
);
4992 sp_sb_data
.state
= SB_ENABLED
;
4993 sp_sb_data
.host_sb_addr
.lo
= U64_LO(section
);
4994 sp_sb_data
.host_sb_addr
.hi
= U64_HI(section
);
4995 sp_sb_data
.igu_sb_id
= igu_sp_sb_index
;
4996 sp_sb_data
.igu_seg_id
= igu_seg_id
;
4997 sp_sb_data
.p_func
.pf_id
= func
;
4998 sp_sb_data
.p_func
.vnic_id
= BP_VN(bp
);
4999 sp_sb_data
.p_func
.vf_id
= 0xff;
5001 bnx2x_wr_sp_sb_data(bp
, &sp_sb_data
);
5003 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
, USTORM_ID
, 0, IGU_INT_ENABLE
, 0);
5006 void bnx2x_update_coalesce(struct bnx2x
*bp
)
5010 for_each_eth_queue(bp
, i
)
5011 bnx2x_update_coalesce_sb(bp
, bp
->fp
[i
].fw_sb_id
,
5012 bp
->tx_ticks
, bp
->rx_ticks
);
5015 static void bnx2x_init_sp_ring(struct bnx2x
*bp
)
5017 spin_lock_init(&bp
->spq_lock
);
5018 atomic_set(&bp
->cq_spq_left
, MAX_SPQ_PENDING
);
5020 bp
->spq_prod_idx
= 0;
5021 bp
->dsb_sp_prod
= BNX2X_SP_DSB_INDEX
;
5022 bp
->spq_prod_bd
= bp
->spq
;
5023 bp
->spq_last_bd
= bp
->spq_prod_bd
+ MAX_SP_DESC_CNT
;
5026 static void bnx2x_init_eq_ring(struct bnx2x
*bp
)
5029 for (i
= 1; i
<= NUM_EQ_PAGES
; i
++) {
5030 union event_ring_elem
*elem
=
5031 &bp
->eq_ring
[EQ_DESC_CNT_PAGE
* i
- 1];
5033 elem
->next_page
.addr
.hi
=
5034 cpu_to_le32(U64_HI(bp
->eq_mapping
+
5035 BCM_PAGE_SIZE
* (i
% NUM_EQ_PAGES
)));
5036 elem
->next_page
.addr
.lo
=
5037 cpu_to_le32(U64_LO(bp
->eq_mapping
+
5038 BCM_PAGE_SIZE
*(i
% NUM_EQ_PAGES
)));
5041 bp
->eq_prod
= NUM_EQ_DESC
;
5042 bp
->eq_cons_sb
= BNX2X_EQ_INDEX
;
5043 /* we want a warning message before it gets rought... */
5044 atomic_set(&bp
->eq_spq_left
,
5045 min_t(int, MAX_SP_DESC_CNT
- MAX_SPQ_PENDING
, NUM_EQ_DESC
) - 1);
5049 /* called with netif_addr_lock_bh() */
5050 void bnx2x_set_q_rx_mode(struct bnx2x
*bp
, u8 cl_id
,
5051 unsigned long rx_mode_flags
,
5052 unsigned long rx_accept_flags
,
5053 unsigned long tx_accept_flags
,
5054 unsigned long ramrod_flags
)
5056 struct bnx2x_rx_mode_ramrod_params ramrod_param
;
5059 memset(&ramrod_param
, 0, sizeof(ramrod_param
));
5061 /* Prepare ramrod parameters */
5062 ramrod_param
.cid
= 0;
5063 ramrod_param
.cl_id
= cl_id
;
5064 ramrod_param
.rx_mode_obj
= &bp
->rx_mode_obj
;
5065 ramrod_param
.func_id
= BP_FUNC(bp
);
5067 ramrod_param
.pstate
= &bp
->sp_state
;
5068 ramrod_param
.state
= BNX2X_FILTER_RX_MODE_PENDING
;
5070 ramrod_param
.rdata
= bnx2x_sp(bp
, rx_mode_rdata
);
5071 ramrod_param
.rdata_mapping
= bnx2x_sp_mapping(bp
, rx_mode_rdata
);
5073 set_bit(BNX2X_FILTER_RX_MODE_PENDING
, &bp
->sp_state
);
5075 ramrod_param
.ramrod_flags
= ramrod_flags
;
5076 ramrod_param
.rx_mode_flags
= rx_mode_flags
;
5078 ramrod_param
.rx_accept_flags
= rx_accept_flags
;
5079 ramrod_param
.tx_accept_flags
= tx_accept_flags
;
5081 rc
= bnx2x_config_rx_mode(bp
, &ramrod_param
);
5083 BNX2X_ERR("Set rx_mode %d failed\n", bp
->rx_mode
);
5088 /* called with netif_addr_lock_bh() */
5089 void bnx2x_set_storm_rx_mode(struct bnx2x
*bp
)
5091 unsigned long rx_mode_flags
= 0, ramrod_flags
= 0;
5092 unsigned long rx_accept_flags
= 0, tx_accept_flags
= 0;
5097 /* Configure rx_mode of FCoE Queue */
5098 __set_bit(BNX2X_RX_MODE_FCOE_ETH
, &rx_mode_flags
);
5101 switch (bp
->rx_mode
) {
5102 case BNX2X_RX_MODE_NONE
:
5104 * 'drop all' supersedes any accept flags that may have been
5105 * passed to the function.
5108 case BNX2X_RX_MODE_NORMAL
:
5109 __set_bit(BNX2X_ACCEPT_UNICAST
, &rx_accept_flags
);
5110 __set_bit(BNX2X_ACCEPT_MULTICAST
, &rx_accept_flags
);
5111 __set_bit(BNX2X_ACCEPT_BROADCAST
, &rx_accept_flags
);
5113 /* internal switching mode */
5114 __set_bit(BNX2X_ACCEPT_UNICAST
, &tx_accept_flags
);
5115 __set_bit(BNX2X_ACCEPT_MULTICAST
, &tx_accept_flags
);
5116 __set_bit(BNX2X_ACCEPT_BROADCAST
, &tx_accept_flags
);
5119 case BNX2X_RX_MODE_ALLMULTI
:
5120 __set_bit(BNX2X_ACCEPT_UNICAST
, &rx_accept_flags
);
5121 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST
, &rx_accept_flags
);
5122 __set_bit(BNX2X_ACCEPT_BROADCAST
, &rx_accept_flags
);
5124 /* internal switching mode */
5125 __set_bit(BNX2X_ACCEPT_UNICAST
, &tx_accept_flags
);
5126 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST
, &tx_accept_flags
);
5127 __set_bit(BNX2X_ACCEPT_BROADCAST
, &tx_accept_flags
);
5130 case BNX2X_RX_MODE_PROMISC
:
5131 /* According to deffinition of SI mode, iface in promisc mode
5132 * should receive matched and unmatched (in resolution of port)
5135 __set_bit(BNX2X_ACCEPT_UNMATCHED
, &rx_accept_flags
);
5136 __set_bit(BNX2X_ACCEPT_UNICAST
, &rx_accept_flags
);
5137 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST
, &rx_accept_flags
);
5138 __set_bit(BNX2X_ACCEPT_BROADCAST
, &rx_accept_flags
);
5140 /* internal switching mode */
5141 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST
, &tx_accept_flags
);
5142 __set_bit(BNX2X_ACCEPT_BROADCAST
, &tx_accept_flags
);
5145 __set_bit(BNX2X_ACCEPT_ALL_UNICAST
, &tx_accept_flags
);
5147 __set_bit(BNX2X_ACCEPT_UNICAST
, &tx_accept_flags
);
5151 BNX2X_ERR("Unknown rx_mode: %d\n", bp
->rx_mode
);
5155 if (bp
->rx_mode
!= BNX2X_RX_MODE_NONE
) {
5156 __set_bit(BNX2X_ACCEPT_ANY_VLAN
, &rx_accept_flags
);
5157 __set_bit(BNX2X_ACCEPT_ANY_VLAN
, &tx_accept_flags
);
5160 __set_bit(RAMROD_RX
, &ramrod_flags
);
5161 __set_bit(RAMROD_TX
, &ramrod_flags
);
5163 bnx2x_set_q_rx_mode(bp
, bp
->fp
->cl_id
, rx_mode_flags
, rx_accept_flags
,
5164 tx_accept_flags
, ramrod_flags
);
5167 static void bnx2x_init_internal_common(struct bnx2x
*bp
)
5173 * In switch independent mode, the TSTORM needs to accept
5174 * packets that failed classification, since approximate match
5175 * mac addresses aren't written to NIG LLH
5177 REG_WR8(bp
, BAR_TSTRORM_INTMEM
+
5178 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET
, 2);
5179 else if (!CHIP_IS_E1(bp
)) /* 57710 doesn't support MF */
5180 REG_WR8(bp
, BAR_TSTRORM_INTMEM
+
5181 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET
, 0);
5183 /* Zero this manually as its initialization is
5184 currently missing in the initTool */
5185 for (i
= 0; i
< (USTORM_AGG_DATA_SIZE
>> 2); i
++)
5186 REG_WR(bp
, BAR_USTRORM_INTMEM
+
5187 USTORM_AGG_DATA_OFFSET
+ i
* 4, 0);
5188 if (!CHIP_IS_E1x(bp
)) {
5189 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+ CSTORM_IGU_MODE_OFFSET
,
5190 CHIP_INT_MODE_IS_BC(bp
) ?
5191 HC_IGU_BC_MODE
: HC_IGU_NBC_MODE
);
5195 static void bnx2x_init_internal(struct bnx2x
*bp
, u32 load_code
)
5197 switch (load_code
) {
5198 case FW_MSG_CODE_DRV_LOAD_COMMON
:
5199 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP
:
5200 bnx2x_init_internal_common(bp
);
5203 case FW_MSG_CODE_DRV_LOAD_PORT
:
5207 case FW_MSG_CODE_DRV_LOAD_FUNCTION
:
5208 /* internal memory per function is
5209 initialized inside bnx2x_pf_init */
5213 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code
);
5218 static inline u8
bnx2x_fp_igu_sb_id(struct bnx2x_fastpath
*fp
)
5220 return fp
->bp
->igu_base_sb
+ fp
->index
+ CNIC_PRESENT
;
5223 static inline u8
bnx2x_fp_fw_sb_id(struct bnx2x_fastpath
*fp
)
5225 return fp
->bp
->base_fw_ndsb
+ fp
->index
+ CNIC_PRESENT
;
5228 static inline u8
bnx2x_fp_cl_id(struct bnx2x_fastpath
*fp
)
5230 if (CHIP_IS_E1x(fp
->bp
))
5231 return BP_L_ID(fp
->bp
) + fp
->index
;
5232 else /* We want Client ID to be the same as IGU SB ID for 57712 */
5233 return bnx2x_fp_igu_sb_id(fp
);
5236 static void bnx2x_init_eth_fp(struct bnx2x
*bp
, int fp_idx
)
5238 struct bnx2x_fastpath
*fp
= &bp
->fp
[fp_idx
];
5240 unsigned long q_type
= 0;
5241 u32 cids
[BNX2X_MULTI_TX_COS
] = { 0 };
5242 fp
->rx_queue
= fp_idx
;
5244 fp
->cl_id
= bnx2x_fp_cl_id(fp
);
5245 fp
->fw_sb_id
= bnx2x_fp_fw_sb_id(fp
);
5246 fp
->igu_sb_id
= bnx2x_fp_igu_sb_id(fp
);
5247 /* qZone id equals to FW (per path) client id */
5248 fp
->cl_qzone_id
= bnx2x_fp_qzone_id(fp
);
5251 fp
->ustorm_rx_prods_offset
= bnx2x_rx_ustorm_prods_offset(fp
);
5252 /* Setup SB indicies */
5253 fp
->rx_cons_sb
= BNX2X_RX_SB_INDEX
;
5255 /* Configure Queue State object */
5256 __set_bit(BNX2X_Q_TYPE_HAS_RX
, &q_type
);
5257 __set_bit(BNX2X_Q_TYPE_HAS_TX
, &q_type
);
5259 BUG_ON(fp
->max_cos
> BNX2X_MULTI_TX_COS
);
5262 for_each_cos_in_tx_queue(fp
, cos
) {
5263 bnx2x_init_txdata(bp
, &fp
->txdata
[cos
],
5264 CID_COS_TO_TX_ONLY_CID(fp
->cid
, cos
),
5265 FP_COS_TO_TXQ(fp
, cos
),
5266 BNX2X_TX_SB_INDEX_BASE
+ cos
);
5267 cids
[cos
] = fp
->txdata
[cos
].cid
;
5270 bnx2x_init_queue_obj(bp
, &fp
->q_obj
, fp
->cl_id
, cids
, fp
->max_cos
,
5271 BP_FUNC(bp
), bnx2x_sp(bp
, q_rdata
),
5272 bnx2x_sp_mapping(bp
, q_rdata
), q_type
);
5275 * Configure classification DBs: Always enable Tx switching
5277 bnx2x_init_vlan_mac_fp_objs(fp
, BNX2X_OBJ_TYPE_RX_TX
);
5279 DP(NETIF_MSG_IFUP
, "queue[%d]: bnx2x_init_sb(%p,%p) "
5280 "cl_id %d fw_sb %d igu_sb %d\n",
5281 fp_idx
, bp
, fp
->status_blk
.e2_sb
, fp
->cl_id
, fp
->fw_sb_id
,
5283 bnx2x_init_sb(bp
, fp
->status_blk_mapping
, BNX2X_VF_ID_INVALID
, false,
5284 fp
->fw_sb_id
, fp
->igu_sb_id
);
5286 bnx2x_update_fpsb_idx(fp
);
5289 void bnx2x_nic_init(struct bnx2x
*bp
, u32 load_code
)
5293 for_each_eth_queue(bp
, i
)
5294 bnx2x_init_eth_fp(bp
, i
);
5297 bnx2x_init_fcoe_fp(bp
);
5299 bnx2x_init_sb(bp
, bp
->cnic_sb_mapping
,
5300 BNX2X_VF_ID_INVALID
, false,
5301 bnx2x_cnic_fw_sb_id(bp
), bnx2x_cnic_igu_sb_id(bp
));
5305 /* Initialize MOD_ABS interrupts */
5306 bnx2x_init_mod_abs_int(bp
, &bp
->link_vars
, bp
->common
.chip_id
,
5307 bp
->common
.shmem_base
, bp
->common
.shmem2_base
,
5309 /* ensure status block indices were read */
5312 bnx2x_init_def_sb(bp
);
5313 bnx2x_update_dsb_idx(bp
);
5314 bnx2x_init_rx_rings(bp
);
5315 bnx2x_init_tx_rings(bp
);
5316 bnx2x_init_sp_ring(bp
);
5317 bnx2x_init_eq_ring(bp
);
5318 bnx2x_init_internal(bp
, load_code
);
5320 bnx2x_stats_init(bp
);
5322 /* flush all before enabling interrupts */
5326 bnx2x_int_enable(bp
);
5328 /* Check for SPIO5 */
5329 bnx2x_attn_int_deasserted0(bp
,
5330 REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0
+ BP_PORT(bp
)*4) &
5331 AEU_INPUTS_ATTN_BITS_SPIO5
);
5334 /* end of nic init */
5337 * gzip service functions
5340 static int bnx2x_gunzip_init(struct bnx2x
*bp
)
5342 bp
->gunzip_buf
= dma_alloc_coherent(&bp
->pdev
->dev
, FW_BUF_SIZE
,
5343 &bp
->gunzip_mapping
, GFP_KERNEL
);
5344 if (bp
->gunzip_buf
== NULL
)
5347 bp
->strm
= kmalloc(sizeof(*bp
->strm
), GFP_KERNEL
);
5348 if (bp
->strm
== NULL
)
5351 bp
->strm
->workspace
= vmalloc(zlib_inflate_workspacesize());
5352 if (bp
->strm
->workspace
== NULL
)
5362 dma_free_coherent(&bp
->pdev
->dev
, FW_BUF_SIZE
, bp
->gunzip_buf
,
5363 bp
->gunzip_mapping
);
5364 bp
->gunzip_buf
= NULL
;
5367 netdev_err(bp
->dev
, "Cannot allocate firmware buffer for"
5368 " un-compression\n");
5372 static void bnx2x_gunzip_end(struct bnx2x
*bp
)
5375 vfree(bp
->strm
->workspace
);
5380 if (bp
->gunzip_buf
) {
5381 dma_free_coherent(&bp
->pdev
->dev
, FW_BUF_SIZE
, bp
->gunzip_buf
,
5382 bp
->gunzip_mapping
);
5383 bp
->gunzip_buf
= NULL
;
5387 static int bnx2x_gunzip(struct bnx2x
*bp
, const u8
*zbuf
, int len
)
5391 /* check gzip header */
5392 if ((zbuf
[0] != 0x1f) || (zbuf
[1] != 0x8b) || (zbuf
[2] != Z_DEFLATED
)) {
5393 BNX2X_ERR("Bad gzip header\n");
5401 if (zbuf
[3] & FNAME
)
5402 while ((zbuf
[n
++] != 0) && (n
< len
));
5404 bp
->strm
->next_in
= (typeof(bp
->strm
->next_in
))zbuf
+ n
;
5405 bp
->strm
->avail_in
= len
- n
;
5406 bp
->strm
->next_out
= bp
->gunzip_buf
;
5407 bp
->strm
->avail_out
= FW_BUF_SIZE
;
5409 rc
= zlib_inflateInit2(bp
->strm
, -MAX_WBITS
);
5413 rc
= zlib_inflate(bp
->strm
, Z_FINISH
);
5414 if ((rc
!= Z_OK
) && (rc
!= Z_STREAM_END
))
5415 netdev_err(bp
->dev
, "Firmware decompression error: %s\n",
5418 bp
->gunzip_outlen
= (FW_BUF_SIZE
- bp
->strm
->avail_out
);
5419 if (bp
->gunzip_outlen
& 0x3)
5420 netdev_err(bp
->dev
, "Firmware decompression error:"
5421 " gunzip_outlen (%d) not aligned\n",
5423 bp
->gunzip_outlen
>>= 2;
5425 zlib_inflateEnd(bp
->strm
);
5427 if (rc
== Z_STREAM_END
)
5433 /* nic load/unload */
5436 * General service functions
5439 /* send a NIG loopback debug packet */
5440 static void bnx2x_lb_pckt(struct bnx2x
*bp
)
5444 /* Ethernet source and destination addresses */
5445 wb_write
[0] = 0x55555555;
5446 wb_write
[1] = 0x55555555;
5447 wb_write
[2] = 0x20; /* SOP */
5448 REG_WR_DMAE(bp
, NIG_REG_DEBUG_PACKET_LB
, wb_write
, 3);
5450 /* NON-IP protocol */
5451 wb_write
[0] = 0x09000000;
5452 wb_write
[1] = 0x55555555;
5453 wb_write
[2] = 0x10; /* EOP, eop_bvalid = 0 */
5454 REG_WR_DMAE(bp
, NIG_REG_DEBUG_PACKET_LB
, wb_write
, 3);
5457 /* some of the internal memories
5458 * are not directly readable from the driver
5459 * to test them we send debug packets
5461 static int bnx2x_int_mem_test(struct bnx2x
*bp
)
5467 if (CHIP_REV_IS_FPGA(bp
))
5469 else if (CHIP_REV_IS_EMUL(bp
))
5474 /* Disable inputs of parser neighbor blocks */
5475 REG_WR(bp
, TSDM_REG_ENABLE_IN1
, 0x0);
5476 REG_WR(bp
, TCM_REG_PRS_IFEN
, 0x0);
5477 REG_WR(bp
, CFC_REG_DEBUG0
, 0x1);
5478 REG_WR(bp
, NIG_REG_PRS_REQ_IN_EN
, 0x0);
5480 /* Write 0 to parser credits for CFC search request */
5481 REG_WR(bp
, PRS_REG_CFC_SEARCH_INITIAL_CREDIT
, 0x0);
5483 /* send Ethernet packet */
5486 /* TODO do i reset NIG statistic? */
5487 /* Wait until NIG register shows 1 packet of size 0x10 */
5488 count
= 1000 * factor
;
5491 bnx2x_read_dmae(bp
, NIG_REG_STAT2_BRB_OCTET
, 2);
5492 val
= *bnx2x_sp(bp
, wb_data
[0]);
5500 BNX2X_ERR("NIG timeout val = 0x%x\n", val
);
5504 /* Wait until PRS register shows 1 packet */
5505 count
= 1000 * factor
;
5507 val
= REG_RD(bp
, PRS_REG_NUM_OF_PACKETS
);
5515 BNX2X_ERR("PRS timeout val = 0x%x\n", val
);
5519 /* Reset and init BRB, PRS */
5520 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
, 0x03);
5522 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
, 0x03);
5524 bnx2x_init_block(bp
, BLOCK_BRB1
, PHASE_COMMON
);
5525 bnx2x_init_block(bp
, BLOCK_PRS
, PHASE_COMMON
);
5527 DP(NETIF_MSG_HW
, "part2\n");
5529 /* Disable inputs of parser neighbor blocks */
5530 REG_WR(bp
, TSDM_REG_ENABLE_IN1
, 0x0);
5531 REG_WR(bp
, TCM_REG_PRS_IFEN
, 0x0);
5532 REG_WR(bp
, CFC_REG_DEBUG0
, 0x1);
5533 REG_WR(bp
, NIG_REG_PRS_REQ_IN_EN
, 0x0);
5535 /* Write 0 to parser credits for CFC search request */
5536 REG_WR(bp
, PRS_REG_CFC_SEARCH_INITIAL_CREDIT
, 0x0);
5538 /* send 10 Ethernet packets */
5539 for (i
= 0; i
< 10; i
++)
5542 /* Wait until NIG register shows 10 + 1
5543 packets of size 11*0x10 = 0xb0 */
5544 count
= 1000 * factor
;
5547 bnx2x_read_dmae(bp
, NIG_REG_STAT2_BRB_OCTET
, 2);
5548 val
= *bnx2x_sp(bp
, wb_data
[0]);
5556 BNX2X_ERR("NIG timeout val = 0x%x\n", val
);
5560 /* Wait until PRS register shows 2 packets */
5561 val
= REG_RD(bp
, PRS_REG_NUM_OF_PACKETS
);
5563 BNX2X_ERR("PRS timeout val = 0x%x\n", val
);
5565 /* Write 1 to parser credits for CFC search request */
5566 REG_WR(bp
, PRS_REG_CFC_SEARCH_INITIAL_CREDIT
, 0x1);
5568 /* Wait until PRS register shows 3 packets */
5569 msleep(10 * factor
);
5570 /* Wait until NIG register shows 1 packet of size 0x10 */
5571 val
= REG_RD(bp
, PRS_REG_NUM_OF_PACKETS
);
5573 BNX2X_ERR("PRS timeout val = 0x%x\n", val
);
5575 /* clear NIG EOP FIFO */
5576 for (i
= 0; i
< 11; i
++)
5577 REG_RD(bp
, NIG_REG_INGRESS_EOP_LB_FIFO
);
5578 val
= REG_RD(bp
, NIG_REG_INGRESS_EOP_LB_EMPTY
);
5580 BNX2X_ERR("clear of NIG failed\n");
5584 /* Reset and init BRB, PRS, NIG */
5585 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
, 0x03);
5587 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
, 0x03);
5589 bnx2x_init_block(bp
, BLOCK_BRB1
, PHASE_COMMON
);
5590 bnx2x_init_block(bp
, BLOCK_PRS
, PHASE_COMMON
);
5593 REG_WR(bp
, PRS_REG_NIC_MODE
, 1);
5596 /* Enable inputs of parser neighbor blocks */
5597 REG_WR(bp
, TSDM_REG_ENABLE_IN1
, 0x7fffffff);
5598 REG_WR(bp
, TCM_REG_PRS_IFEN
, 0x1);
5599 REG_WR(bp
, CFC_REG_DEBUG0
, 0x0);
5600 REG_WR(bp
, NIG_REG_PRS_REQ_IN_EN
, 0x1);
5602 DP(NETIF_MSG_HW
, "done\n");
5607 static void bnx2x_enable_blocks_attention(struct bnx2x
*bp
)
5609 REG_WR(bp
, PXP_REG_PXP_INT_MASK_0
, 0);
5610 if (!CHIP_IS_E1x(bp
))
5611 REG_WR(bp
, PXP_REG_PXP_INT_MASK_1
, 0x40);
5613 REG_WR(bp
, PXP_REG_PXP_INT_MASK_1
, 0);
5614 REG_WR(bp
, DORQ_REG_DORQ_INT_MASK
, 0);
5615 REG_WR(bp
, CFC_REG_CFC_INT_MASK
, 0);
5617 * mask read length error interrupts in brb for parser
5618 * (parsing unit and 'checksum and crc' unit)
5619 * these errors are legal (PU reads fixed length and CAC can cause
5620 * read length error on truncated packets)
5622 REG_WR(bp
, BRB1_REG_BRB1_INT_MASK
, 0xFC00);
5623 REG_WR(bp
, QM_REG_QM_INT_MASK
, 0);
5624 REG_WR(bp
, TM_REG_TM_INT_MASK
, 0);
5625 REG_WR(bp
, XSDM_REG_XSDM_INT_MASK_0
, 0);
5626 REG_WR(bp
, XSDM_REG_XSDM_INT_MASK_1
, 0);
5627 REG_WR(bp
, XCM_REG_XCM_INT_MASK
, 0);
5628 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
5629 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
5630 REG_WR(bp
, USDM_REG_USDM_INT_MASK_0
, 0);
5631 REG_WR(bp
, USDM_REG_USDM_INT_MASK_1
, 0);
5632 REG_WR(bp
, UCM_REG_UCM_INT_MASK
, 0);
5633 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
5634 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
5635 REG_WR(bp
, GRCBASE_UPB
+ PB_REG_PB_INT_MASK
, 0);
5636 REG_WR(bp
, CSDM_REG_CSDM_INT_MASK_0
, 0);
5637 REG_WR(bp
, CSDM_REG_CSDM_INT_MASK_1
, 0);
5638 REG_WR(bp
, CCM_REG_CCM_INT_MASK
, 0);
5639 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
5640 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
5642 if (CHIP_REV_IS_FPGA(bp
))
5643 REG_WR(bp
, PXP2_REG_PXP2_INT_MASK_0
, 0x580000);
5644 else if (!CHIP_IS_E1x(bp
))
5645 REG_WR(bp
, PXP2_REG_PXP2_INT_MASK_0
,
5646 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
5647 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
5648 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
5649 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
5650 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED
));
5652 REG_WR(bp
, PXP2_REG_PXP2_INT_MASK_0
, 0x480000);
5653 REG_WR(bp
, TSDM_REG_TSDM_INT_MASK_0
, 0);
5654 REG_WR(bp
, TSDM_REG_TSDM_INT_MASK_1
, 0);
5655 REG_WR(bp
, TCM_REG_TCM_INT_MASK
, 0);
5656 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
5658 if (!CHIP_IS_E1x(bp
))
5659 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
5660 REG_WR(bp
, TSEM_REG_TSEM_INT_MASK_1
, 0x07ff);
5662 REG_WR(bp
, CDU_REG_CDU_INT_MASK
, 0);
5663 REG_WR(bp
, DMAE_REG_DMAE_INT_MASK
, 0);
5664 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
5665 REG_WR(bp
, PBF_REG_PBF_INT_MASK
, 0x18); /* bit 3,4 masked */
5668 static void bnx2x_reset_common(struct bnx2x
*bp
)
5673 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
,
5676 if (CHIP_IS_E3(bp
)) {
5677 val
|= MISC_REGISTERS_RESET_REG_2_MSTAT0
;
5678 val
|= MISC_REGISTERS_RESET_REG_2_MSTAT1
;
5681 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
, val
);
5684 static void bnx2x_setup_dmae(struct bnx2x
*bp
)
5687 spin_lock_init(&bp
->dmae_lock
);
5690 static void bnx2x_init_pxp(struct bnx2x
*bp
)
5693 int r_order
, w_order
;
5695 pci_read_config_word(bp
->pdev
,
5696 pci_pcie_cap(bp
->pdev
) + PCI_EXP_DEVCTL
, &devctl
);
5697 DP(NETIF_MSG_HW
, "read 0x%x from devctl\n", devctl
);
5698 w_order
= ((devctl
& PCI_EXP_DEVCTL_PAYLOAD
) >> 5);
5700 r_order
= ((devctl
& PCI_EXP_DEVCTL_READRQ
) >> 12);
5702 DP(NETIF_MSG_HW
, "force read order to %d\n", bp
->mrrs
);
5706 bnx2x_init_pxp_arb(bp
, r_order
, w_order
);
5709 static void bnx2x_setup_fan_failure_detection(struct bnx2x
*bp
)
5719 val
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.config2
) &
5720 SHARED_HW_CFG_FAN_FAILURE_MASK
;
5722 if (val
== SHARED_HW_CFG_FAN_FAILURE_ENABLED
)
5726 * The fan failure mechanism is usually related to the PHY type since
5727 * the power consumption of the board is affected by the PHY. Currently,
5728 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
5730 else if (val
== SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE
)
5731 for (port
= PORT_0
; port
< PORT_MAX
; port
++) {
5733 bnx2x_fan_failure_det_req(
5735 bp
->common
.shmem_base
,
5736 bp
->common
.shmem2_base
,
5740 DP(NETIF_MSG_HW
, "fan detection setting: %d\n", is_required
);
5742 if (is_required
== 0)
5745 /* Fan failure is indicated by SPIO 5 */
5746 bnx2x_set_spio(bp
, MISC_REGISTERS_SPIO_5
,
5747 MISC_REGISTERS_SPIO_INPUT_HI_Z
);
5749 /* set to active low mode */
5750 val
= REG_RD(bp
, MISC_REG_SPIO_INT
);
5751 val
|= ((1 << MISC_REGISTERS_SPIO_5
) <<
5752 MISC_REGISTERS_SPIO_INT_OLD_SET_POS
);
5753 REG_WR(bp
, MISC_REG_SPIO_INT
, val
);
5755 /* enable interrupt to signal the IGU */
5756 val
= REG_RD(bp
, MISC_REG_SPIO_EVENT_EN
);
5757 val
|= (1 << MISC_REGISTERS_SPIO_5
);
5758 REG_WR(bp
, MISC_REG_SPIO_EVENT_EN
, val
);
5761 static void bnx2x_pretend_func(struct bnx2x
*bp
, u8 pretend_func_num
)
5767 if (CHIP_IS_E1H(bp
) && (pretend_func_num
>= E1H_FUNC_MAX
))
5770 switch (BP_ABS_FUNC(bp
)) {
5772 offset
= PXP2_REG_PGL_PRETEND_FUNC_F0
;
5775 offset
= PXP2_REG_PGL_PRETEND_FUNC_F1
;
5778 offset
= PXP2_REG_PGL_PRETEND_FUNC_F2
;
5781 offset
= PXP2_REG_PGL_PRETEND_FUNC_F3
;
5784 offset
= PXP2_REG_PGL_PRETEND_FUNC_F4
;
5787 offset
= PXP2_REG_PGL_PRETEND_FUNC_F5
;
5790 offset
= PXP2_REG_PGL_PRETEND_FUNC_F6
;
5793 offset
= PXP2_REG_PGL_PRETEND_FUNC_F7
;
5799 REG_WR(bp
, offset
, pretend_func_num
);
5801 DP(NETIF_MSG_HW
, "Pretending to func %d\n", pretend_func_num
);
5804 void bnx2x_pf_disable(struct bnx2x
*bp
)
5806 u32 val
= REG_RD(bp
, IGU_REG_PF_CONFIGURATION
);
5807 val
&= ~IGU_PF_CONF_FUNC_EN
;
5809 REG_WR(bp
, IGU_REG_PF_CONFIGURATION
, val
);
5810 REG_WR(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
, 0);
5811 REG_WR(bp
, CFC_REG_WEAK_ENABLE_PF
, 0);
5814 static inline void bnx2x__common_init_phy(struct bnx2x
*bp
)
5816 u32 shmem_base
[2], shmem2_base
[2];
5817 shmem_base
[0] = bp
->common
.shmem_base
;
5818 shmem2_base
[0] = bp
->common
.shmem2_base
;
5819 if (!CHIP_IS_E1x(bp
)) {
5821 SHMEM2_RD(bp
, other_shmem_base_addr
);
5823 SHMEM2_RD(bp
, other_shmem2_base_addr
);
5825 bnx2x_acquire_phy_lock(bp
);
5826 bnx2x_common_init_phy(bp
, shmem_base
, shmem2_base
,
5827 bp
->common
.chip_id
);
5828 bnx2x_release_phy_lock(bp
);
5832 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
5834 * @bp: driver handle
5836 static int bnx2x_init_hw_common(struct bnx2x
*bp
)
5840 DP(BNX2X_MSG_MCP
, "starting common init func %d\n", BP_ABS_FUNC(bp
));
5843 * take the UNDI lock to protect undi_unload flow from accessing
5844 * registers while we're resetting the chip
5846 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RESET
);
5848 bnx2x_reset_common(bp
);
5849 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
, 0xffffffff);
5852 if (CHIP_IS_E3(bp
)) {
5853 val
|= MISC_REGISTERS_RESET_REG_2_MSTAT0
;
5854 val
|= MISC_REGISTERS_RESET_REG_2_MSTAT1
;
5856 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_SET
, val
);
5858 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RESET
);
5860 bnx2x_init_block(bp
, BLOCK_MISC
, PHASE_COMMON
);
5862 if (!CHIP_IS_E1x(bp
)) {
5866 * 4-port mode or 2-port mode we need to turn of master-enable
5867 * for everyone, after that, turn it back on for self.
5868 * so, we disregard multi-function or not, and always disable
5869 * for all functions on the given path, this means 0,2,4,6 for
5870 * path 0 and 1,3,5,7 for path 1
5872 for (abs_func_id
= BP_PATH(bp
);
5873 abs_func_id
< E2_FUNC_MAX
*2; abs_func_id
+= 2) {
5874 if (abs_func_id
== BP_ABS_FUNC(bp
)) {
5876 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
,
5881 bnx2x_pretend_func(bp
, abs_func_id
);
5882 /* clear pf enable */
5883 bnx2x_pf_disable(bp
);
5884 bnx2x_pretend_func(bp
, BP_ABS_FUNC(bp
));
5888 bnx2x_init_block(bp
, BLOCK_PXP
, PHASE_COMMON
);
5889 if (CHIP_IS_E1(bp
)) {
5890 /* enable HW interrupt from PXP on USDM overflow
5891 bit 16 on INT_MASK_0 */
5892 REG_WR(bp
, PXP_REG_PXP_INT_MASK_0
, 0);
5895 bnx2x_init_block(bp
, BLOCK_PXP2
, PHASE_COMMON
);
5899 REG_WR(bp
, PXP2_REG_RQ_QM_ENDIAN_M
, 1);
5900 REG_WR(bp
, PXP2_REG_RQ_TM_ENDIAN_M
, 1);
5901 REG_WR(bp
, PXP2_REG_RQ_SRC_ENDIAN_M
, 1);
5902 REG_WR(bp
, PXP2_REG_RQ_CDU_ENDIAN_M
, 1);
5903 REG_WR(bp
, PXP2_REG_RQ_DBG_ENDIAN_M
, 1);
5904 /* make sure this value is 0 */
5905 REG_WR(bp
, PXP2_REG_RQ_HC_ENDIAN_M
, 0);
5907 /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
5908 REG_WR(bp
, PXP2_REG_RD_QM_SWAP_MODE
, 1);
5909 REG_WR(bp
, PXP2_REG_RD_TM_SWAP_MODE
, 1);
5910 REG_WR(bp
, PXP2_REG_RD_SRC_SWAP_MODE
, 1);
5911 REG_WR(bp
, PXP2_REG_RD_CDURD_SWAP_MODE
, 1);
5914 bnx2x_ilt_init_page_size(bp
, INITOP_SET
);
5916 if (CHIP_REV_IS_FPGA(bp
) && CHIP_IS_E1H(bp
))
5917 REG_WR(bp
, PXP2_REG_PGL_TAGS_LIMIT
, 0x1);
5919 /* let the HW do it's magic ... */
5921 /* finish PXP init */
5922 val
= REG_RD(bp
, PXP2_REG_RQ_CFG_DONE
);
5924 BNX2X_ERR("PXP2 CFG failed\n");
5927 val
= REG_RD(bp
, PXP2_REG_RD_INIT_DONE
);
5929 BNX2X_ERR("PXP2 RD_INIT failed\n");
5933 /* Timers bug workaround E2 only. We need to set the entire ILT to
5934 * have entries with value "0" and valid bit on.
5935 * This needs to be done by the first PF that is loaded in a path
5936 * (i.e. common phase)
5938 if (!CHIP_IS_E1x(bp
)) {
5939 /* In E2 there is a bug in the timers block that can cause function 6 / 7
5940 * (i.e. vnic3) to start even if it is marked as "scan-off".
5941 * This occurs when a different function (func2,3) is being marked
5942 * as "scan-off". Real-life scenario for example: if a driver is being
5943 * load-unloaded while func6,7 are down. This will cause the timer to access
5944 * the ilt, translate to a logical address and send a request to read/write.
5945 * Since the ilt for the function that is down is not valid, this will cause
5946 * a translation error which is unrecoverable.
5947 * The Workaround is intended to make sure that when this happens nothing fatal
5948 * will occur. The workaround:
5949 * 1. First PF driver which loads on a path will:
5950 * a. After taking the chip out of reset, by using pretend,
5951 * it will write "0" to the following registers of
5953 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
5954 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
5955 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
5956 * And for itself it will write '1' to
5957 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
5958 * dmae-operations (writing to pram for example.)
5959 * note: can be done for only function 6,7 but cleaner this
5961 * b. Write zero+valid to the entire ILT.
5962 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
5963 * VNIC3 (of that port). The range allocated will be the
5964 * entire ILT. This is needed to prevent ILT range error.
5965 * 2. Any PF driver load flow:
5966 * a. ILT update with the physical addresses of the allocated
5968 * b. Wait 20msec. - note that this timeout is needed to make
5969 * sure there are no requests in one of the PXP internal
5970 * queues with "old" ILT addresses.
5971 * c. PF enable in the PGLC.
5972 * d. Clear the was_error of the PF in the PGLC. (could have
5973 * occured while driver was down)
5974 * e. PF enable in the CFC (WEAK + STRONG)
5975 * f. Timers scan enable
5976 * 3. PF driver unload flow:
5977 * a. Clear the Timers scan_en.
5978 * b. Polling for scan_on=0 for that PF.
5979 * c. Clear the PF enable bit in the PXP.
5980 * d. Clear the PF enable in the CFC (WEAK + STRONG)
5981 * e. Write zero+valid to all ILT entries (The valid bit must
5983 * f. If this is VNIC 3 of a port then also init
5984 * first_timers_ilt_entry to zero and last_timers_ilt_entry
5985 * to the last enrty in the ILT.
5988 * Currently the PF error in the PGLC is non recoverable.
5989 * In the future the there will be a recovery routine for this error.
5990 * Currently attention is masked.
5991 * Having an MCP lock on the load/unload process does not guarantee that
5992 * there is no Timer disable during Func6/7 enable. This is because the
5993 * Timers scan is currently being cleared by the MCP on FLR.
5994 * Step 2.d can be done only for PF6/7 and the driver can also check if
5995 * there is error before clearing it. But the flow above is simpler and
5997 * All ILT entries are written by zero+valid and not just PF6/7
5998 * ILT entries since in the future the ILT entries allocation for
5999 * PF-s might be dynamic.
6001 struct ilt_client_info ilt_cli
;
6002 struct bnx2x_ilt ilt
;
6003 memset(&ilt_cli
, 0, sizeof(struct ilt_client_info
));
6004 memset(&ilt
, 0, sizeof(struct bnx2x_ilt
));
6006 /* initialize dummy TM client */
6008 ilt_cli
.end
= ILT_NUM_PAGE_ENTRIES
- 1;
6009 ilt_cli
.client_num
= ILT_CLIENT_TM
;
6011 /* Step 1: set zeroes to all ilt page entries with valid bit on
6012 * Step 2: set the timers first/last ilt entry to point
6013 * to the entire range to prevent ILT range error for 3rd/4th
6014 * vnic (this code assumes existance of the vnic)
6016 * both steps performed by call to bnx2x_ilt_client_init_op()
6017 * with dummy TM client
6019 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
6020 * and his brother are split registers
6022 bnx2x_pretend_func(bp
, (BP_PATH(bp
) + 6));
6023 bnx2x_ilt_client_init_op_ilt(bp
, &ilt
, &ilt_cli
, INITOP_CLEAR
);
6024 bnx2x_pretend_func(bp
, BP_ABS_FUNC(bp
));
6026 REG_WR(bp
, PXP2_REG_RQ_DRAM_ALIGN
, BNX2X_PXP_DRAM_ALIGN
);
6027 REG_WR(bp
, PXP2_REG_RQ_DRAM_ALIGN_RD
, BNX2X_PXP_DRAM_ALIGN
);
6028 REG_WR(bp
, PXP2_REG_RQ_DRAM_ALIGN_SEL
, 1);
6032 REG_WR(bp
, PXP2_REG_RQ_DISABLE_INPUTS
, 0);
6033 REG_WR(bp
, PXP2_REG_RD_DISABLE_INPUTS
, 0);
6035 if (!CHIP_IS_E1x(bp
)) {
6036 int factor
= CHIP_REV_IS_EMUL(bp
) ? 1000 :
6037 (CHIP_REV_IS_FPGA(bp
) ? 400 : 0);
6038 bnx2x_init_block(bp
, BLOCK_PGLUE_B
, PHASE_COMMON
);
6040 bnx2x_init_block(bp
, BLOCK_ATC
, PHASE_COMMON
);
6042 /* let the HW do it's magic ... */
6045 val
= REG_RD(bp
, ATC_REG_ATC_INIT_DONE
);
6046 } while (factor
-- && (val
!= 1));
6049 BNX2X_ERR("ATC_INIT failed\n");
6054 bnx2x_init_block(bp
, BLOCK_DMAE
, PHASE_COMMON
);
6056 /* clean the DMAE memory */
6058 bnx2x_init_fill(bp
, TSEM_REG_PRAM
, 0, 8, 1);
6060 bnx2x_init_block(bp
, BLOCK_TCM
, PHASE_COMMON
);
6062 bnx2x_init_block(bp
, BLOCK_UCM
, PHASE_COMMON
);
6064 bnx2x_init_block(bp
, BLOCK_CCM
, PHASE_COMMON
);
6066 bnx2x_init_block(bp
, BLOCK_XCM
, PHASE_COMMON
);
6068 bnx2x_read_dmae(bp
, XSEM_REG_PASSIVE_BUFFER
, 3);
6069 bnx2x_read_dmae(bp
, CSEM_REG_PASSIVE_BUFFER
, 3);
6070 bnx2x_read_dmae(bp
, TSEM_REG_PASSIVE_BUFFER
, 3);
6071 bnx2x_read_dmae(bp
, USEM_REG_PASSIVE_BUFFER
, 3);
6073 bnx2x_init_block(bp
, BLOCK_QM
, PHASE_COMMON
);
6076 /* QM queues pointers table */
6077 bnx2x_qm_init_ptr_table(bp
, bp
->qm_cid_count
, INITOP_SET
);
6079 /* soft reset pulse */
6080 REG_WR(bp
, QM_REG_SOFT_RESET
, 1);
6081 REG_WR(bp
, QM_REG_SOFT_RESET
, 0);
6084 bnx2x_init_block(bp
, BLOCK_TM
, PHASE_COMMON
);
6087 bnx2x_init_block(bp
, BLOCK_DORQ
, PHASE_COMMON
);
6088 REG_WR(bp
, DORQ_REG_DPM_CID_OFST
, BNX2X_DB_SHIFT
);
6089 if (!CHIP_REV_IS_SLOW(bp
))
6090 /* enable hw interrupt from doorbell Q */
6091 REG_WR(bp
, DORQ_REG_DORQ_INT_MASK
, 0);
6093 bnx2x_init_block(bp
, BLOCK_BRB1
, PHASE_COMMON
);
6095 bnx2x_init_block(bp
, BLOCK_PRS
, PHASE_COMMON
);
6096 REG_WR(bp
, PRS_REG_A_PRSU_20
, 0xf);
6098 if (!CHIP_IS_E1(bp
))
6099 REG_WR(bp
, PRS_REG_E1HOV_MODE
, bp
->path_has_ovlan
);
6101 if (!CHIP_IS_E1x(bp
) && !CHIP_IS_E3B0(bp
))
6102 /* Bit-map indicating which L2 hdrs may appear
6103 * after the basic Ethernet header
6105 REG_WR(bp
, PRS_REG_HDRS_AFTER_BASIC
,
6106 bp
->path_has_ovlan
? 7 : 6);
6108 bnx2x_init_block(bp
, BLOCK_TSDM
, PHASE_COMMON
);
6109 bnx2x_init_block(bp
, BLOCK_CSDM
, PHASE_COMMON
);
6110 bnx2x_init_block(bp
, BLOCK_USDM
, PHASE_COMMON
);
6111 bnx2x_init_block(bp
, BLOCK_XSDM
, PHASE_COMMON
);
6113 if (!CHIP_IS_E1x(bp
)) {
6114 /* reset VFC memories */
6115 REG_WR(bp
, TSEM_REG_FAST_MEMORY
+ VFC_REG_MEMORIES_RST
,
6116 VFC_MEMORIES_RST_REG_CAM_RST
|
6117 VFC_MEMORIES_RST_REG_RAM_RST
);
6118 REG_WR(bp
, XSEM_REG_FAST_MEMORY
+ VFC_REG_MEMORIES_RST
,
6119 VFC_MEMORIES_RST_REG_CAM_RST
|
6120 VFC_MEMORIES_RST_REG_RAM_RST
);
6125 bnx2x_init_block(bp
, BLOCK_TSEM
, PHASE_COMMON
);
6126 bnx2x_init_block(bp
, BLOCK_USEM
, PHASE_COMMON
);
6127 bnx2x_init_block(bp
, BLOCK_CSEM
, PHASE_COMMON
);
6128 bnx2x_init_block(bp
, BLOCK_XSEM
, PHASE_COMMON
);
6131 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
,
6133 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
,
6136 bnx2x_init_block(bp
, BLOCK_UPB
, PHASE_COMMON
);
6137 bnx2x_init_block(bp
, BLOCK_XPB
, PHASE_COMMON
);
6138 bnx2x_init_block(bp
, BLOCK_PBF
, PHASE_COMMON
);
6140 if (!CHIP_IS_E1x(bp
))
6141 REG_WR(bp
, PBF_REG_HDRS_AFTER_BASIC
,
6142 bp
->path_has_ovlan
? 7 : 6);
6144 REG_WR(bp
, SRC_REG_SOFT_RST
, 1);
6146 bnx2x_init_block(bp
, BLOCK_SRC
, PHASE_COMMON
);
6149 REG_WR(bp
, SRC_REG_KEYSEARCH_0
, 0x63285672);
6150 REG_WR(bp
, SRC_REG_KEYSEARCH_1
, 0x24b8f2cc);
6151 REG_WR(bp
, SRC_REG_KEYSEARCH_2
, 0x223aef9b);
6152 REG_WR(bp
, SRC_REG_KEYSEARCH_3
, 0x26001e3a);
6153 REG_WR(bp
, SRC_REG_KEYSEARCH_4
, 0x7ae91116);
6154 REG_WR(bp
, SRC_REG_KEYSEARCH_5
, 0x5ce5230b);
6155 REG_WR(bp
, SRC_REG_KEYSEARCH_6
, 0x298d8adf);
6156 REG_WR(bp
, SRC_REG_KEYSEARCH_7
, 0x6eb0ff09);
6157 REG_WR(bp
, SRC_REG_KEYSEARCH_8
, 0x1830f82f);
6158 REG_WR(bp
, SRC_REG_KEYSEARCH_9
, 0x01e46be7);
6160 REG_WR(bp
, SRC_REG_SOFT_RST
, 0);
6162 if (sizeof(union cdu_context
) != 1024)
6163 /* we currently assume that a context is 1024 bytes */
6164 dev_alert(&bp
->pdev
->dev
, "please adjust the size "
6165 "of cdu_context(%ld)\n",
6166 (long)sizeof(union cdu_context
));
6168 bnx2x_init_block(bp
, BLOCK_CDU
, PHASE_COMMON
);
6169 val
= (4 << 24) + (0 << 12) + 1024;
6170 REG_WR(bp
, CDU_REG_CDU_GLOBAL_PARAMS
, val
);
6172 bnx2x_init_block(bp
, BLOCK_CFC
, PHASE_COMMON
);
6173 REG_WR(bp
, CFC_REG_INIT_REG
, 0x7FF);
6174 /* enable context validation interrupt from CFC */
6175 REG_WR(bp
, CFC_REG_CFC_INT_MASK
, 0);
6177 /* set the thresholds to prevent CFC/CDU race */
6178 REG_WR(bp
, CFC_REG_DEBUG0
, 0x20020000);
6180 bnx2x_init_block(bp
, BLOCK_HC
, PHASE_COMMON
);
6182 if (!CHIP_IS_E1x(bp
) && BP_NOMCP(bp
))
6183 REG_WR(bp
, IGU_REG_RESET_MEMORIES
, 0x36);
6185 bnx2x_init_block(bp
, BLOCK_IGU
, PHASE_COMMON
);
6186 bnx2x_init_block(bp
, BLOCK_MISC_AEU
, PHASE_COMMON
);
6188 /* Reset PCIE errors for debug */
6189 REG_WR(bp
, 0x2814, 0xffffffff);
6190 REG_WR(bp
, 0x3820, 0xffffffff);
6192 if (!CHIP_IS_E1x(bp
)) {
6193 REG_WR(bp
, PCICFG_OFFSET
+ PXPCS_TL_CONTROL_5
,
6194 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1
|
6195 PXPCS_TL_CONTROL_5_ERR_UNSPPORT
));
6196 REG_WR(bp
, PCICFG_OFFSET
+ PXPCS_TL_FUNC345_STAT
,
6197 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4
|
6198 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3
|
6199 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2
));
6200 REG_WR(bp
, PCICFG_OFFSET
+ PXPCS_TL_FUNC678_STAT
,
6201 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7
|
6202 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6
|
6203 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5
));
6206 bnx2x_init_block(bp
, BLOCK_NIG
, PHASE_COMMON
);
6207 if (!CHIP_IS_E1(bp
)) {
6208 /* in E3 this done in per-port section */
6209 if (!CHIP_IS_E3(bp
))
6210 REG_WR(bp
, NIG_REG_LLH_MF_MODE
, IS_MF(bp
));
6212 if (CHIP_IS_E1H(bp
))
6213 /* not applicable for E2 (and above ...) */
6214 REG_WR(bp
, NIG_REG_LLH_E1HOV_MODE
, IS_MF_SD(bp
));
6216 if (CHIP_REV_IS_SLOW(bp
))
6219 /* finish CFC init */
6220 val
= reg_poll(bp
, CFC_REG_LL_INIT_DONE
, 1, 100, 10);
6222 BNX2X_ERR("CFC LL_INIT failed\n");
6225 val
= reg_poll(bp
, CFC_REG_AC_INIT_DONE
, 1, 100, 10);
6227 BNX2X_ERR("CFC AC_INIT failed\n");
6230 val
= reg_poll(bp
, CFC_REG_CAM_INIT_DONE
, 1, 100, 10);
6232 BNX2X_ERR("CFC CAM_INIT failed\n");
6235 REG_WR(bp
, CFC_REG_DEBUG0
, 0);
6237 if (CHIP_IS_E1(bp
)) {
6238 /* read NIG statistic
6239 to see if this is our first up since powerup */
6240 bnx2x_read_dmae(bp
, NIG_REG_STAT2_BRB_OCTET
, 2);
6241 val
= *bnx2x_sp(bp
, wb_data
[0]);
6243 /* do internal memory self test */
6244 if ((val
== 0) && bnx2x_int_mem_test(bp
)) {
6245 BNX2X_ERR("internal mem self test failed\n");
6250 bnx2x_setup_fan_failure_detection(bp
);
6252 /* clear PXP2 attentions */
6253 REG_RD(bp
, PXP2_REG_PXP2_INT_STS_CLR_0
);
6255 bnx2x_enable_blocks_attention(bp
);
6256 bnx2x_enable_blocks_parity(bp
);
6258 if (!BP_NOMCP(bp
)) {
6259 if (CHIP_IS_E1x(bp
))
6260 bnx2x__common_init_phy(bp
);
6262 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
6268 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
6270 * @bp: driver handle
6272 static int bnx2x_init_hw_common_chip(struct bnx2x
*bp
)
6274 int rc
= bnx2x_init_hw_common(bp
);
6279 /* In E2 2-PORT mode, same ext phy is used for the two paths */
6281 bnx2x__common_init_phy(bp
);
6286 static int bnx2x_init_hw_port(struct bnx2x
*bp
)
6288 int port
= BP_PORT(bp
);
6289 int init_phase
= port
? PHASE_PORT1
: PHASE_PORT0
;
6293 bnx2x__link_reset(bp
);
6295 DP(BNX2X_MSG_MCP
, "starting port init port %d\n", port
);
6297 REG_WR(bp
, NIG_REG_MASK_INTERRUPT_PORT0
+ port
*4, 0);
6299 bnx2x_init_block(bp
, BLOCK_MISC
, init_phase
);
6300 bnx2x_init_block(bp
, BLOCK_PXP
, init_phase
);
6301 bnx2x_init_block(bp
, BLOCK_PXP2
, init_phase
);
6303 /* Timers bug workaround: disables the pf_master bit in pglue at
6304 * common phase, we need to enable it here before any dmae access are
6305 * attempted. Therefore we manually added the enable-master to the
6306 * port phase (it also happens in the function phase)
6308 if (!CHIP_IS_E1x(bp
))
6309 REG_WR(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
, 1);
6311 bnx2x_init_block(bp
, BLOCK_ATC
, init_phase
);
6312 bnx2x_init_block(bp
, BLOCK_DMAE
, init_phase
);
6313 bnx2x_init_block(bp
, BLOCK_PGLUE_B
, init_phase
);
6314 bnx2x_init_block(bp
, BLOCK_QM
, init_phase
);
6316 bnx2x_init_block(bp
, BLOCK_TCM
, init_phase
);
6317 bnx2x_init_block(bp
, BLOCK_UCM
, init_phase
);
6318 bnx2x_init_block(bp
, BLOCK_CCM
, init_phase
);
6319 bnx2x_init_block(bp
, BLOCK_XCM
, init_phase
);
6321 /* QM cid (connection) count */
6322 bnx2x_qm_init_cid_count(bp
, bp
->qm_cid_count
, INITOP_SET
);
6325 bnx2x_init_block(bp
, BLOCK_TM
, init_phase
);
6326 REG_WR(bp
, TM_REG_LIN0_SCAN_TIME
+ port
*4, 20);
6327 REG_WR(bp
, TM_REG_LIN0_MAX_ACTIVE_CID
+ port
*4, 31);
6330 bnx2x_init_block(bp
, BLOCK_DORQ
, init_phase
);
6332 if (CHIP_IS_E1(bp
) || CHIP_IS_E1H(bp
)) {
6333 bnx2x_init_block(bp
, BLOCK_BRB1
, init_phase
);
6336 low
= ((bp
->flags
& ONE_PORT_FLAG
) ? 160 : 246);
6337 else if (bp
->dev
->mtu
> 4096) {
6338 if (bp
->flags
& ONE_PORT_FLAG
)
6342 /* (24*1024 + val*4)/256 */
6343 low
= 96 + (val
/64) +
6344 ((val
% 64) ? 1 : 0);
6347 low
= ((bp
->flags
& ONE_PORT_FLAG
) ? 80 : 160);
6348 high
= low
+ 56; /* 14*1024/256 */
6349 REG_WR(bp
, BRB1_REG_PAUSE_LOW_THRESHOLD_0
+ port
*4, low
);
6350 REG_WR(bp
, BRB1_REG_PAUSE_HIGH_THRESHOLD_0
+ port
*4, high
);
6353 if (CHIP_MODE_IS_4_PORT(bp
))
6354 REG_WR(bp
, (BP_PORT(bp
) ?
6355 BRB1_REG_MAC_GUARANTIED_1
:
6356 BRB1_REG_MAC_GUARANTIED_0
), 40);
6359 bnx2x_init_block(bp
, BLOCK_PRS
, init_phase
);
6360 if (CHIP_IS_E3B0(bp
))
6361 /* Ovlan exists only if we are in multi-function +
6362 * switch-dependent mode, in switch-independent there
6363 * is no ovlan headers
6365 REG_WR(bp
, BP_PORT(bp
) ?
6366 PRS_REG_HDRS_AFTER_BASIC_PORT_1
:
6367 PRS_REG_HDRS_AFTER_BASIC_PORT_0
,
6368 (bp
->path_has_ovlan
? 7 : 6));
6370 bnx2x_init_block(bp
, BLOCK_TSDM
, init_phase
);
6371 bnx2x_init_block(bp
, BLOCK_CSDM
, init_phase
);
6372 bnx2x_init_block(bp
, BLOCK_USDM
, init_phase
);
6373 bnx2x_init_block(bp
, BLOCK_XSDM
, init_phase
);
6375 bnx2x_init_block(bp
, BLOCK_TSEM
, init_phase
);
6376 bnx2x_init_block(bp
, BLOCK_USEM
, init_phase
);
6377 bnx2x_init_block(bp
, BLOCK_CSEM
, init_phase
);
6378 bnx2x_init_block(bp
, BLOCK_XSEM
, init_phase
);
6380 bnx2x_init_block(bp
, BLOCK_UPB
, init_phase
);
6381 bnx2x_init_block(bp
, BLOCK_XPB
, init_phase
);
6383 bnx2x_init_block(bp
, BLOCK_PBF
, init_phase
);
6385 if (CHIP_IS_E1x(bp
)) {
6386 /* configure PBF to work without PAUSE mtu 9000 */
6387 REG_WR(bp
, PBF_REG_P0_PAUSE_ENABLE
+ port
*4, 0);
6389 /* update threshold */
6390 REG_WR(bp
, PBF_REG_P0_ARB_THRSH
+ port
*4, (9040/16));
6391 /* update init credit */
6392 REG_WR(bp
, PBF_REG_P0_INIT_CRD
+ port
*4, (9040/16) + 553 - 22);
6395 REG_WR(bp
, PBF_REG_INIT_P0
+ port
*4, 1);
6397 REG_WR(bp
, PBF_REG_INIT_P0
+ port
*4, 0);
6401 bnx2x_init_block(bp
, BLOCK_SRC
, init_phase
);
6403 bnx2x_init_block(bp
, BLOCK_CDU
, init_phase
);
6404 bnx2x_init_block(bp
, BLOCK_CFC
, init_phase
);
6406 if (CHIP_IS_E1(bp
)) {
6407 REG_WR(bp
, HC_REG_LEADING_EDGE_0
+ port
*8, 0);
6408 REG_WR(bp
, HC_REG_TRAILING_EDGE_0
+ port
*8, 0);
6410 bnx2x_init_block(bp
, BLOCK_HC
, init_phase
);
6412 bnx2x_init_block(bp
, BLOCK_IGU
, init_phase
);
6414 bnx2x_init_block(bp
, BLOCK_MISC_AEU
, init_phase
);
6415 /* init aeu_mask_attn_func_0/1:
6416 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
6417 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
6418 * bits 4-7 are used for "per vn group attention" */
6419 val
= IS_MF(bp
) ? 0xF7 : 0x7;
6420 /* Enable DCBX attention for all but E1 */
6421 val
|= CHIP_IS_E1(bp
) ? 0 : 0x10;
6422 REG_WR(bp
, MISC_REG_AEU_MASK_ATTN_FUNC_0
+ port
*4, val
);
6424 bnx2x_init_block(bp
, BLOCK_NIG
, init_phase
);
6426 if (!CHIP_IS_E1x(bp
)) {
6427 /* Bit-map indicating which L2 hdrs may appear after the
6428 * basic Ethernet header
6430 REG_WR(bp
, BP_PORT(bp
) ?
6431 NIG_REG_P1_HDRS_AFTER_BASIC
:
6432 NIG_REG_P0_HDRS_AFTER_BASIC
,
6433 IS_MF_SD(bp
) ? 7 : 6);
6436 REG_WR(bp
, BP_PORT(bp
) ?
6437 NIG_REG_LLH1_MF_MODE
:
6438 NIG_REG_LLH_MF_MODE
, IS_MF(bp
));
6440 if (!CHIP_IS_E3(bp
))
6441 REG_WR(bp
, NIG_REG_XGXS_SERDES0_MODE_SEL
+ port
*4, 1);
6443 if (!CHIP_IS_E1(bp
)) {
6444 /* 0x2 disable mf_ov, 0x1 enable */
6445 REG_WR(bp
, NIG_REG_LLH0_BRB1_DRV_MASK_MF
+ port
*4,
6446 (IS_MF_SD(bp
) ? 0x1 : 0x2));
6448 if (!CHIP_IS_E1x(bp
)) {
6450 switch (bp
->mf_mode
) {
6451 case MULTI_FUNCTION_SD
:
6454 case MULTI_FUNCTION_SI
:
6459 REG_WR(bp
, (BP_PORT(bp
) ? NIG_REG_LLH1_CLS_TYPE
:
6460 NIG_REG_LLH0_CLS_TYPE
), val
);
6463 REG_WR(bp
, NIG_REG_LLFC_ENABLE_0
+ port
*4, 0);
6464 REG_WR(bp
, NIG_REG_LLFC_OUT_EN_0
+ port
*4, 0);
6465 REG_WR(bp
, NIG_REG_PAUSE_ENABLE_0
+ port
*4, 1);
6470 /* If SPIO5 is set to generate interrupts, enable it for this port */
6471 val
= REG_RD(bp
, MISC_REG_SPIO_EVENT_EN
);
6472 if (val
& (1 << MISC_REGISTERS_SPIO_5
)) {
6473 u32 reg_addr
= (port
? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0
:
6474 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0
);
6475 val
= REG_RD(bp
, reg_addr
);
6476 val
|= AEU_INPUTS_ATTN_BITS_SPIO5
;
6477 REG_WR(bp
, reg_addr
, val
);
6483 static void bnx2x_ilt_wr(struct bnx2x
*bp
, u32 index
, dma_addr_t addr
)
6488 reg
= PXP2_REG_RQ_ONCHIP_AT
+ index
*8;
6490 reg
= PXP2_REG_RQ_ONCHIP_AT_B0
+ index
*8;
6492 bnx2x_wb_wr(bp
, reg
, ONCHIP_ADDR1(addr
), ONCHIP_ADDR2(addr
));
6495 static inline void bnx2x_igu_clear_sb(struct bnx2x
*bp
, u8 idu_sb_id
)
6497 bnx2x_igu_clear_sb_gen(bp
, BP_FUNC(bp
), idu_sb_id
, true /*PF*/);
6500 static inline void bnx2x_clear_func_ilt(struct bnx2x
*bp
, u32 func
)
6502 u32 i
, base
= FUNC_ILT_BASE(func
);
6503 for (i
= base
; i
< base
+ ILT_PER_FUNC
; i
++)
6504 bnx2x_ilt_wr(bp
, i
, 0);
6507 static int bnx2x_init_hw_func(struct bnx2x
*bp
)
6509 int port
= BP_PORT(bp
);
6510 int func
= BP_FUNC(bp
);
6511 int init_phase
= PHASE_PF0
+ func
;
6512 struct bnx2x_ilt
*ilt
= BP_ILT(bp
);
6515 u32 main_mem_base
, main_mem_size
, main_mem_prty_clr
;
6516 int i
, main_mem_width
;
6518 DP(BNX2X_MSG_MCP
, "starting func init func %d\n", func
);
6520 /* FLR cleanup - hmmm */
6521 if (!CHIP_IS_E1x(bp
))
6522 bnx2x_pf_flr_clnup(bp
);
6524 /* set MSI reconfigure capability */
6525 if (bp
->common
.int_block
== INT_BLOCK_HC
) {
6526 addr
= (port
? HC_REG_CONFIG_1
: HC_REG_CONFIG_0
);
6527 val
= REG_RD(bp
, addr
);
6528 val
|= HC_CONFIG_0_REG_MSI_ATTN_EN_0
;
6529 REG_WR(bp
, addr
, val
);
6532 bnx2x_init_block(bp
, BLOCK_PXP
, init_phase
);
6533 bnx2x_init_block(bp
, BLOCK_PXP2
, init_phase
);
6536 cdu_ilt_start
= ilt
->clients
[ILT_CLIENT_CDU
].start
;
6538 for (i
= 0; i
< L2_ILT_LINES(bp
); i
++) {
6539 ilt
->lines
[cdu_ilt_start
+ i
].page
=
6540 bp
->context
.vcxt
+ (ILT_PAGE_CIDS
* i
);
6541 ilt
->lines
[cdu_ilt_start
+ i
].page_mapping
=
6542 bp
->context
.cxt_mapping
+ (CDU_ILT_PAGE_SZ
* i
);
6543 /* cdu ilt pages are allocated manually so there's no need to
6546 bnx2x_ilt_init_op(bp
, INITOP_SET
);
6549 bnx2x_src_init_t2(bp
, bp
->t2
, bp
->t2_mapping
, SRC_CONN_NUM
);
6551 /* T1 hash bits value determines the T1 number of entries */
6552 REG_WR(bp
, SRC_REG_NUMBER_HASH_BITS0
+ port
*4, SRC_HASH_BITS
);
6557 REG_WR(bp
, PRS_REG_NIC_MODE
, 1);
6558 #endif /* BCM_CNIC */
6560 if (!CHIP_IS_E1x(bp
)) {
6561 u32 pf_conf
= IGU_PF_CONF_FUNC_EN
;
6563 /* Turn on a single ISR mode in IGU if driver is going to use
6566 if (!(bp
->flags
& USING_MSIX_FLAG
))
6567 pf_conf
|= IGU_PF_CONF_SINGLE_ISR_EN
;
6569 * Timers workaround bug: function init part.
6570 * Need to wait 20msec after initializing ILT,
6571 * needed to make sure there are no requests in
6572 * one of the PXP internal queues with "old" ILT addresses
6576 * Master enable - Due to WB DMAE writes performed before this
6577 * register is re-initialized as part of the regular function
6580 REG_WR(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
, 1);
6581 /* Enable the function in IGU */
6582 REG_WR(bp
, IGU_REG_PF_CONFIGURATION
, pf_conf
);
6587 bnx2x_init_block(bp
, BLOCK_PGLUE_B
, init_phase
);
6589 if (!CHIP_IS_E1x(bp
))
6590 REG_WR(bp
, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR
, func
);
6592 bnx2x_init_block(bp
, BLOCK_ATC
, init_phase
);
6593 bnx2x_init_block(bp
, BLOCK_DMAE
, init_phase
);
6594 bnx2x_init_block(bp
, BLOCK_NIG
, init_phase
);
6595 bnx2x_init_block(bp
, BLOCK_SRC
, init_phase
);
6596 bnx2x_init_block(bp
, BLOCK_MISC
, init_phase
);
6597 bnx2x_init_block(bp
, BLOCK_TCM
, init_phase
);
6598 bnx2x_init_block(bp
, BLOCK_UCM
, init_phase
);
6599 bnx2x_init_block(bp
, BLOCK_CCM
, init_phase
);
6600 bnx2x_init_block(bp
, BLOCK_XCM
, init_phase
);
6601 bnx2x_init_block(bp
, BLOCK_TSEM
, init_phase
);
6602 bnx2x_init_block(bp
, BLOCK_USEM
, init_phase
);
6603 bnx2x_init_block(bp
, BLOCK_CSEM
, init_phase
);
6604 bnx2x_init_block(bp
, BLOCK_XSEM
, init_phase
);
6606 if (!CHIP_IS_E1x(bp
))
6607 REG_WR(bp
, QM_REG_PF_EN
, 1);
6609 if (!CHIP_IS_E1x(bp
)) {
6610 REG_WR(bp
, TSEM_REG_VFPF_ERR_NUM
, BNX2X_MAX_NUM_OF_VFS
+ func
);
6611 REG_WR(bp
, USEM_REG_VFPF_ERR_NUM
, BNX2X_MAX_NUM_OF_VFS
+ func
);
6612 REG_WR(bp
, CSEM_REG_VFPF_ERR_NUM
, BNX2X_MAX_NUM_OF_VFS
+ func
);
6613 REG_WR(bp
, XSEM_REG_VFPF_ERR_NUM
, BNX2X_MAX_NUM_OF_VFS
+ func
);
6615 bnx2x_init_block(bp
, BLOCK_QM
, init_phase
);
6617 bnx2x_init_block(bp
, BLOCK_TM
, init_phase
);
6618 bnx2x_init_block(bp
, BLOCK_DORQ
, init_phase
);
6619 bnx2x_init_block(bp
, BLOCK_BRB1
, init_phase
);
6620 bnx2x_init_block(bp
, BLOCK_PRS
, init_phase
);
6621 bnx2x_init_block(bp
, BLOCK_TSDM
, init_phase
);
6622 bnx2x_init_block(bp
, BLOCK_CSDM
, init_phase
);
6623 bnx2x_init_block(bp
, BLOCK_USDM
, init_phase
);
6624 bnx2x_init_block(bp
, BLOCK_XSDM
, init_phase
);
6625 bnx2x_init_block(bp
, BLOCK_UPB
, init_phase
);
6626 bnx2x_init_block(bp
, BLOCK_XPB
, init_phase
);
6627 bnx2x_init_block(bp
, BLOCK_PBF
, init_phase
);
6628 if (!CHIP_IS_E1x(bp
))
6629 REG_WR(bp
, PBF_REG_DISABLE_PF
, 0);
6631 bnx2x_init_block(bp
, BLOCK_CDU
, init_phase
);
6633 bnx2x_init_block(bp
, BLOCK_CFC
, init_phase
);
6635 if (!CHIP_IS_E1x(bp
))
6636 REG_WR(bp
, CFC_REG_WEAK_ENABLE_PF
, 1);
6639 REG_WR(bp
, NIG_REG_LLH0_FUNC_EN
+ port
*8, 1);
6640 REG_WR(bp
, NIG_REG_LLH0_FUNC_VLAN_ID
+ port
*8, bp
->mf_ov
);
6643 bnx2x_init_block(bp
, BLOCK_MISC_AEU
, init_phase
);
6645 /* HC init per function */
6646 if (bp
->common
.int_block
== INT_BLOCK_HC
) {
6647 if (CHIP_IS_E1H(bp
)) {
6648 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_12
+ func
*4, 0);
6650 REG_WR(bp
, HC_REG_LEADING_EDGE_0
+ port
*8, 0);
6651 REG_WR(bp
, HC_REG_TRAILING_EDGE_0
+ port
*8, 0);
6653 bnx2x_init_block(bp
, BLOCK_HC
, init_phase
);
6656 int num_segs
, sb_idx
, prod_offset
;
6658 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_12
+ func
*4, 0);
6660 if (!CHIP_IS_E1x(bp
)) {
6661 REG_WR(bp
, IGU_REG_LEADING_EDGE_LATCH
, 0);
6662 REG_WR(bp
, IGU_REG_TRAILING_EDGE_LATCH
, 0);
6665 bnx2x_init_block(bp
, BLOCK_IGU
, init_phase
);
6667 if (!CHIP_IS_E1x(bp
)) {
6671 * E2 mode: address 0-135 match to the mapping memory;
6672 * 136 - PF0 default prod; 137 - PF1 default prod;
6673 * 138 - PF2 default prod; 139 - PF3 default prod;
6674 * 140 - PF0 attn prod; 141 - PF1 attn prod;
6675 * 142 - PF2 attn prod; 143 - PF3 attn prod;
6678 * E1.5 mode - In backward compatible mode;
6679 * for non default SB; each even line in the memory
6680 * holds the U producer and each odd line hold
6681 * the C producer. The first 128 producers are for
6682 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
6683 * producers are for the DSB for each PF.
6684 * Each PF has five segments: (the order inside each
6685 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
6686 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
6687 * 144-147 attn prods;
6689 /* non-default-status-blocks */
6690 num_segs
= CHIP_INT_MODE_IS_BC(bp
) ?
6691 IGU_BC_NDSB_NUM_SEGS
: IGU_NORM_NDSB_NUM_SEGS
;
6692 for (sb_idx
= 0; sb_idx
< bp
->igu_sb_cnt
; sb_idx
++) {
6693 prod_offset
= (bp
->igu_base_sb
+ sb_idx
) *
6696 for (i
= 0; i
< num_segs
; i
++) {
6697 addr
= IGU_REG_PROD_CONS_MEMORY
+
6698 (prod_offset
+ i
) * 4;
6699 REG_WR(bp
, addr
, 0);
6701 /* send consumer update with value 0 */
6702 bnx2x_ack_sb(bp
, bp
->igu_base_sb
+ sb_idx
,
6703 USTORM_ID
, 0, IGU_INT_NOP
, 1);
6704 bnx2x_igu_clear_sb(bp
,
6705 bp
->igu_base_sb
+ sb_idx
);
6708 /* default-status-blocks */
6709 num_segs
= CHIP_INT_MODE_IS_BC(bp
) ?
6710 IGU_BC_DSB_NUM_SEGS
: IGU_NORM_DSB_NUM_SEGS
;
6712 if (CHIP_MODE_IS_4_PORT(bp
))
6713 dsb_idx
= BP_FUNC(bp
);
6715 dsb_idx
= BP_VN(bp
);
6717 prod_offset
= (CHIP_INT_MODE_IS_BC(bp
) ?
6718 IGU_BC_BASE_DSB_PROD
+ dsb_idx
:
6719 IGU_NORM_BASE_DSB_PROD
+ dsb_idx
);
6722 * igu prods come in chunks of E1HVN_MAX (4) -
6723 * does not matters what is the current chip mode
6725 for (i
= 0; i
< (num_segs
* E1HVN_MAX
);
6727 addr
= IGU_REG_PROD_CONS_MEMORY
+
6728 (prod_offset
+ i
)*4;
6729 REG_WR(bp
, addr
, 0);
6731 /* send consumer update with 0 */
6732 if (CHIP_INT_MODE_IS_BC(bp
)) {
6733 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
6734 USTORM_ID
, 0, IGU_INT_NOP
, 1);
6735 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
6736 CSTORM_ID
, 0, IGU_INT_NOP
, 1);
6737 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
6738 XSTORM_ID
, 0, IGU_INT_NOP
, 1);
6739 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
6740 TSTORM_ID
, 0, IGU_INT_NOP
, 1);
6741 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
6742 ATTENTION_ID
, 0, IGU_INT_NOP
, 1);
6744 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
6745 USTORM_ID
, 0, IGU_INT_NOP
, 1);
6746 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
6747 ATTENTION_ID
, 0, IGU_INT_NOP
, 1);
6749 bnx2x_igu_clear_sb(bp
, bp
->igu_dsb_id
);
6751 /* !!! these should become driver const once
6752 rf-tool supports split-68 const */
6753 REG_WR(bp
, IGU_REG_SB_INT_BEFORE_MASK_LSB
, 0);
6754 REG_WR(bp
, IGU_REG_SB_INT_BEFORE_MASK_MSB
, 0);
6755 REG_WR(bp
, IGU_REG_SB_MASK_LSB
, 0);
6756 REG_WR(bp
, IGU_REG_SB_MASK_MSB
, 0);
6757 REG_WR(bp
, IGU_REG_PBA_STATUS_LSB
, 0);
6758 REG_WR(bp
, IGU_REG_PBA_STATUS_MSB
, 0);
6762 /* Reset PCIE errors for debug */
6763 REG_WR(bp
, 0x2114, 0xffffffff);
6764 REG_WR(bp
, 0x2120, 0xffffffff);
6766 if (CHIP_IS_E1x(bp
)) {
6767 main_mem_size
= HC_REG_MAIN_MEMORY_SIZE
/ 2; /*dwords*/
6768 main_mem_base
= HC_REG_MAIN_MEMORY
+
6769 BP_PORT(bp
) * (main_mem_size
* 4);
6770 main_mem_prty_clr
= HC_REG_HC_PRTY_STS_CLR
;
6773 val
= REG_RD(bp
, main_mem_prty_clr
);
6775 DP(BNX2X_MSG_MCP
, "Hmmm... Parity errors in HC "
6777 "function init (0x%x)!\n", val
);
6779 /* Clear "false" parity errors in MSI-X table */
6780 for (i
= main_mem_base
;
6781 i
< main_mem_base
+ main_mem_size
* 4;
6782 i
+= main_mem_width
) {
6783 bnx2x_read_dmae(bp
, i
, main_mem_width
/ 4);
6784 bnx2x_write_dmae(bp
, bnx2x_sp_mapping(bp
, wb_data
),
6785 i
, main_mem_width
/ 4);
6787 /* Clear HC parity attention */
6788 REG_RD(bp
, main_mem_prty_clr
);
6791 #ifdef BNX2X_STOP_ON_ERROR
6792 /* Enable STORMs SP logging */
6793 REG_WR8(bp
, BAR_USTRORM_INTMEM
+
6794 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp
)), 1);
6795 REG_WR8(bp
, BAR_TSTRORM_INTMEM
+
6796 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp
)), 1);
6797 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+
6798 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp
)), 1);
6799 REG_WR8(bp
, BAR_XSTRORM_INTMEM
+
6800 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp
)), 1);
6803 bnx2x_phy_probe(&bp
->link_params
);
6809 void bnx2x_free_mem(struct bnx2x
*bp
)
6812 bnx2x_free_fp_mem(bp
);
6813 /* end of fastpath */
6815 BNX2X_PCI_FREE(bp
->def_status_blk
, bp
->def_status_blk_mapping
,
6816 sizeof(struct host_sp_status_block
));
6818 BNX2X_PCI_FREE(bp
->fw_stats
, bp
->fw_stats_mapping
,
6819 bp
->fw_stats_data_sz
+ bp
->fw_stats_req_sz
);
6821 BNX2X_PCI_FREE(bp
->slowpath
, bp
->slowpath_mapping
,
6822 sizeof(struct bnx2x_slowpath
));
6824 BNX2X_PCI_FREE(bp
->context
.vcxt
, bp
->context
.cxt_mapping
,
6827 bnx2x_ilt_mem_op(bp
, ILT_MEMOP_FREE
);
6829 BNX2X_FREE(bp
->ilt
->lines
);
6832 if (!CHIP_IS_E1x(bp
))
6833 BNX2X_PCI_FREE(bp
->cnic_sb
.e2_sb
, bp
->cnic_sb_mapping
,
6834 sizeof(struct host_hc_status_block_e2
));
6836 BNX2X_PCI_FREE(bp
->cnic_sb
.e1x_sb
, bp
->cnic_sb_mapping
,
6837 sizeof(struct host_hc_status_block_e1x
));
6839 BNX2X_PCI_FREE(bp
->t2
, bp
->t2_mapping
, SRC_T2_SZ
);
6842 BNX2X_PCI_FREE(bp
->spq
, bp
->spq_mapping
, BCM_PAGE_SIZE
);
6844 BNX2X_PCI_FREE(bp
->eq_ring
, bp
->eq_mapping
,
6845 BCM_PAGE_SIZE
* NUM_EQ_PAGES
);
6848 static inline int bnx2x_alloc_fw_stats_mem(struct bnx2x
*bp
)
6852 /* number of eth_queues */
6853 u8 num_queue_stats
= BNX2X_NUM_ETH_QUEUES(bp
);
6855 /* Total number of FW statistics requests =
6856 * 1 for port stats + 1 for PF stats + num_eth_queues */
6857 bp
->fw_stats_num
= 2 + num_queue_stats
;
6860 /* Request is built from stats_query_header and an array of
6861 * stats_query_cmd_group each of which contains
6862 * STATS_QUERY_CMD_COUNT rules. The real number or requests is
6863 * configured in the stats_query_header.
6865 num_groups
= (2 + num_queue_stats
) / STATS_QUERY_CMD_COUNT
+
6866 (((2 + num_queue_stats
) % STATS_QUERY_CMD_COUNT
) ? 1 : 0);
6868 bp
->fw_stats_req_sz
= sizeof(struct stats_query_header
) +
6869 num_groups
* sizeof(struct stats_query_cmd_group
);
6871 /* Data for statistics requests + stats_conter
6873 * stats_counter holds per-STORM counters that are incremented
6874 * when STORM has finished with the current request.
6876 bp
->fw_stats_data_sz
= sizeof(struct per_port_stats
) +
6877 sizeof(struct per_pf_stats
) +
6878 sizeof(struct per_queue_stats
) * num_queue_stats
+
6879 sizeof(struct stats_counter
);
6881 BNX2X_PCI_ALLOC(bp
->fw_stats
, &bp
->fw_stats_mapping
,
6882 bp
->fw_stats_data_sz
+ bp
->fw_stats_req_sz
);
6885 bp
->fw_stats_req
= (struct bnx2x_fw_stats_req
*)bp
->fw_stats
;
6886 bp
->fw_stats_req_mapping
= bp
->fw_stats_mapping
;
6888 bp
->fw_stats_data
= (struct bnx2x_fw_stats_data
*)
6889 ((u8
*)bp
->fw_stats
+ bp
->fw_stats_req_sz
);
6891 bp
->fw_stats_data_mapping
= bp
->fw_stats_mapping
+
6892 bp
->fw_stats_req_sz
;
6896 BNX2X_PCI_FREE(bp
->fw_stats
, bp
->fw_stats_mapping
,
6897 bp
->fw_stats_data_sz
+ bp
->fw_stats_req_sz
);
6902 int bnx2x_alloc_mem(struct bnx2x
*bp
)
6905 if (!CHIP_IS_E1x(bp
))
6906 /* size = the status block + ramrod buffers */
6907 BNX2X_PCI_ALLOC(bp
->cnic_sb
.e2_sb
, &bp
->cnic_sb_mapping
,
6908 sizeof(struct host_hc_status_block_e2
));
6910 BNX2X_PCI_ALLOC(bp
->cnic_sb
.e1x_sb
, &bp
->cnic_sb_mapping
,
6911 sizeof(struct host_hc_status_block_e1x
));
6913 /* allocate searcher T2 table */
6914 BNX2X_PCI_ALLOC(bp
->t2
, &bp
->t2_mapping
, SRC_T2_SZ
);
6918 BNX2X_PCI_ALLOC(bp
->def_status_blk
, &bp
->def_status_blk_mapping
,
6919 sizeof(struct host_sp_status_block
));
6921 BNX2X_PCI_ALLOC(bp
->slowpath
, &bp
->slowpath_mapping
,
6922 sizeof(struct bnx2x_slowpath
));
6924 /* Allocated memory for FW statistics */
6925 if (bnx2x_alloc_fw_stats_mem(bp
))
6928 bp
->context
.size
= sizeof(union cdu_context
) * BNX2X_L2_CID_COUNT(bp
);
6930 BNX2X_PCI_ALLOC(bp
->context
.vcxt
, &bp
->context
.cxt_mapping
,
6933 BNX2X_ALLOC(bp
->ilt
->lines
, sizeof(struct ilt_line
) * ILT_MAX_LINES
);
6935 if (bnx2x_ilt_mem_op(bp
, ILT_MEMOP_ALLOC
))
6938 /* Slow path ring */
6939 BNX2X_PCI_ALLOC(bp
->spq
, &bp
->spq_mapping
, BCM_PAGE_SIZE
);
6942 BNX2X_PCI_ALLOC(bp
->eq_ring
, &bp
->eq_mapping
,
6943 BCM_PAGE_SIZE
* NUM_EQ_PAGES
);
6947 /* need to be done at the end, since it's self adjusting to amount
6948 * of memory available for RSS queues
6950 if (bnx2x_alloc_fp_mem(bp
))
6960 * Init service functions
6963 int bnx2x_set_mac_one(struct bnx2x
*bp
, u8
*mac
,
6964 struct bnx2x_vlan_mac_obj
*obj
, bool set
,
6965 int mac_type
, unsigned long *ramrod_flags
)
6968 struct bnx2x_vlan_mac_ramrod_params ramrod_param
;
6970 memset(&ramrod_param
, 0, sizeof(ramrod_param
));
6972 /* Fill general parameters */
6973 ramrod_param
.vlan_mac_obj
= obj
;
6974 ramrod_param
.ramrod_flags
= *ramrod_flags
;
6976 /* Fill a user request section if needed */
6977 if (!test_bit(RAMROD_CONT
, ramrod_flags
)) {
6978 memcpy(ramrod_param
.user_req
.u
.mac
.mac
, mac
, ETH_ALEN
);
6980 __set_bit(mac_type
, &ramrod_param
.user_req
.vlan_mac_flags
);
6982 /* Set the command: ADD or DEL */
6984 ramrod_param
.user_req
.cmd
= BNX2X_VLAN_MAC_ADD
;
6986 ramrod_param
.user_req
.cmd
= BNX2X_VLAN_MAC_DEL
;
6989 rc
= bnx2x_config_vlan_mac(bp
, &ramrod_param
);
6991 BNX2X_ERR("%s MAC failed\n", (set
? "Set" : "Del"));
6995 int bnx2x_del_all_macs(struct bnx2x
*bp
,
6996 struct bnx2x_vlan_mac_obj
*mac_obj
,
6997 int mac_type
, bool wait_for_comp
)
7000 unsigned long ramrod_flags
= 0, vlan_mac_flags
= 0;
7002 /* Wait for completion of requested */
7004 __set_bit(RAMROD_COMP_WAIT
, &ramrod_flags
);
7006 /* Set the mac type of addresses we want to clear */
7007 __set_bit(mac_type
, &vlan_mac_flags
);
7009 rc
= mac_obj
->delete_all(bp
, mac_obj
, &vlan_mac_flags
, &ramrod_flags
);
7011 BNX2X_ERR("Failed to delete MACs: %d\n", rc
);
7016 int bnx2x_set_eth_mac(struct bnx2x
*bp
, bool set
)
7018 unsigned long ramrod_flags
= 0;
7021 if (is_zero_ether_addr(bp
->dev
->dev_addr
) && IS_MF_ISCSI_SD(bp
)) {
7022 DP(NETIF_MSG_IFUP
, "Ignoring Zero MAC for iSCSI SD mode\n");
7027 DP(NETIF_MSG_IFUP
, "Adding Eth MAC\n");
7029 __set_bit(RAMROD_COMP_WAIT
, &ramrod_flags
);
7030 /* Eth MAC is set on RSS leading client (fp[0]) */
7031 return bnx2x_set_mac_one(bp
, bp
->dev
->dev_addr
, &bp
->fp
->mac_obj
, set
,
7032 BNX2X_ETH_MAC
, &ramrod_flags
);
7035 int bnx2x_setup_leading(struct bnx2x
*bp
)
7037 return bnx2x_setup_queue(bp
, &bp
->fp
[0], 1);
7041 * bnx2x_set_int_mode - configure interrupt mode
7043 * @bp: driver handle
7045 * In case of MSI-X it will also try to enable MSI-X.
7047 static void __devinit
bnx2x_set_int_mode(struct bnx2x
*bp
)
7051 bnx2x_enable_msi(bp
);
7052 /* falling through... */
7054 bp
->num_queues
= 1 + NON_ETH_CONTEXT_USE
;
7055 DP(NETIF_MSG_IFUP
, "set number of queues to 1\n");
7058 /* Set number of queues according to bp->multi_mode value */
7059 bnx2x_set_num_queues(bp
);
7061 DP(NETIF_MSG_IFUP
, "set number of queues to %d\n",
7064 /* if we can't use MSI-X we only need one fp,
7065 * so try to enable MSI-X with the requested number of fp's
7066 * and fallback to MSI or legacy INTx with one fp
7068 if (bnx2x_enable_msix(bp
)) {
7069 /* failed to enable MSI-X */
7072 "Multi requested but failed to "
7073 "enable MSI-X (%d), "
7074 "set number of queues to %d\n",
7076 1 + NON_ETH_CONTEXT_USE
);
7077 bp
->num_queues
= 1 + NON_ETH_CONTEXT_USE
;
7079 /* Try to enable MSI */
7080 if (!(bp
->flags
& DISABLE_MSI_FLAG
))
7081 bnx2x_enable_msi(bp
);
7087 /* must be called prioir to any HW initializations */
7088 static inline u16
bnx2x_cid_ilt_lines(struct bnx2x
*bp
)
7090 return L2_ILT_LINES(bp
);
7093 void bnx2x_ilt_set_info(struct bnx2x
*bp
)
7095 struct ilt_client_info
*ilt_client
;
7096 struct bnx2x_ilt
*ilt
= BP_ILT(bp
);
7099 ilt
->start_line
= FUNC_ILT_BASE(BP_FUNC(bp
));
7100 DP(BNX2X_MSG_SP
, "ilt starts at line %d\n", ilt
->start_line
);
7103 ilt_client
= &ilt
->clients
[ILT_CLIENT_CDU
];
7104 ilt_client
->client_num
= ILT_CLIENT_CDU
;
7105 ilt_client
->page_size
= CDU_ILT_PAGE_SZ
;
7106 ilt_client
->flags
= ILT_CLIENT_SKIP_MEM
;
7107 ilt_client
->start
= line
;
7108 line
+= bnx2x_cid_ilt_lines(bp
);
7110 line
+= CNIC_ILT_LINES
;
7112 ilt_client
->end
= line
- 1;
7114 DP(BNX2X_MSG_SP
, "ilt client[CDU]: start %d, end %d, psz 0x%x, "
7115 "flags 0x%x, hw psz %d\n",
7118 ilt_client
->page_size
,
7120 ilog2(ilt_client
->page_size
>> 12));
7123 if (QM_INIT(bp
->qm_cid_count
)) {
7124 ilt_client
= &ilt
->clients
[ILT_CLIENT_QM
];
7125 ilt_client
->client_num
= ILT_CLIENT_QM
;
7126 ilt_client
->page_size
= QM_ILT_PAGE_SZ
;
7127 ilt_client
->flags
= 0;
7128 ilt_client
->start
= line
;
7130 /* 4 bytes for each cid */
7131 line
+= DIV_ROUND_UP(bp
->qm_cid_count
* QM_QUEUES_PER_FUNC
* 4,
7134 ilt_client
->end
= line
- 1;
7136 DP(BNX2X_MSG_SP
, "ilt client[QM]: start %d, end %d, psz 0x%x, "
7137 "flags 0x%x, hw psz %d\n",
7140 ilt_client
->page_size
,
7142 ilog2(ilt_client
->page_size
>> 12));
7146 ilt_client
= &ilt
->clients
[ILT_CLIENT_SRC
];
7148 ilt_client
->client_num
= ILT_CLIENT_SRC
;
7149 ilt_client
->page_size
= SRC_ILT_PAGE_SZ
;
7150 ilt_client
->flags
= 0;
7151 ilt_client
->start
= line
;
7152 line
+= SRC_ILT_LINES
;
7153 ilt_client
->end
= line
- 1;
7155 DP(BNX2X_MSG_SP
, "ilt client[SRC]: start %d, end %d, psz 0x%x, "
7156 "flags 0x%x, hw psz %d\n",
7159 ilt_client
->page_size
,
7161 ilog2(ilt_client
->page_size
>> 12));
7164 ilt_client
->flags
= (ILT_CLIENT_SKIP_INIT
| ILT_CLIENT_SKIP_MEM
);
7168 ilt_client
= &ilt
->clients
[ILT_CLIENT_TM
];
7170 ilt_client
->client_num
= ILT_CLIENT_TM
;
7171 ilt_client
->page_size
= TM_ILT_PAGE_SZ
;
7172 ilt_client
->flags
= 0;
7173 ilt_client
->start
= line
;
7174 line
+= TM_ILT_LINES
;
7175 ilt_client
->end
= line
- 1;
7177 DP(BNX2X_MSG_SP
, "ilt client[TM]: start %d, end %d, psz 0x%x, "
7178 "flags 0x%x, hw psz %d\n",
7181 ilt_client
->page_size
,
7183 ilog2(ilt_client
->page_size
>> 12));
7186 ilt_client
->flags
= (ILT_CLIENT_SKIP_INIT
| ILT_CLIENT_SKIP_MEM
);
7188 BUG_ON(line
> ILT_MAX_LINES
);
7192 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
7194 * @bp: driver handle
7195 * @fp: pointer to fastpath
7196 * @init_params: pointer to parameters structure
7198 * parameters configured:
7199 * - HC configuration
7200 * - Queue's CDU context
7202 static inline void bnx2x_pf_q_prep_init(struct bnx2x
*bp
,
7203 struct bnx2x_fastpath
*fp
, struct bnx2x_queue_init_params
*init_params
)
7207 /* FCoE Queue uses Default SB, thus has no HC capabilities */
7208 if (!IS_FCOE_FP(fp
)) {
7209 __set_bit(BNX2X_Q_FLG_HC
, &init_params
->rx
.flags
);
7210 __set_bit(BNX2X_Q_FLG_HC
, &init_params
->tx
.flags
);
7212 /* If HC is supporterd, enable host coalescing in the transition
7215 __set_bit(BNX2X_Q_FLG_HC_EN
, &init_params
->rx
.flags
);
7216 __set_bit(BNX2X_Q_FLG_HC_EN
, &init_params
->tx
.flags
);
7219 init_params
->rx
.hc_rate
= bp
->rx_ticks
?
7220 (1000000 / bp
->rx_ticks
) : 0;
7221 init_params
->tx
.hc_rate
= bp
->tx_ticks
?
7222 (1000000 / bp
->tx_ticks
) : 0;
7225 init_params
->rx
.fw_sb_id
= init_params
->tx
.fw_sb_id
=
7229 * CQ index among the SB indices: FCoE clients uses the default
7230 * SB, therefore it's different.
7232 init_params
->rx
.sb_cq_index
= HC_INDEX_ETH_RX_CQ_CONS
;
7233 init_params
->tx
.sb_cq_index
= HC_INDEX_ETH_FIRST_TX_CQ_CONS
;
7236 /* set maximum number of COSs supported by this queue */
7237 init_params
->max_cos
= fp
->max_cos
;
7239 DP(BNX2X_MSG_SP
, "fp: %d setting queue params max cos to: %d\n",
7240 fp
->index
, init_params
->max_cos
);
7242 /* set the context pointers queue object */
7243 for (cos
= FIRST_TX_COS_INDEX
; cos
< init_params
->max_cos
; cos
++)
7244 init_params
->cxts
[cos
] =
7245 &bp
->context
.vcxt
[fp
->txdata
[cos
].cid
].eth
;
7248 int bnx2x_setup_tx_only(struct bnx2x
*bp
, struct bnx2x_fastpath
*fp
,
7249 struct bnx2x_queue_state_params
*q_params
,
7250 struct bnx2x_queue_setup_tx_only_params
*tx_only_params
,
7251 int tx_index
, bool leading
)
7253 memset(tx_only_params
, 0, sizeof(*tx_only_params
));
7255 /* Set the command */
7256 q_params
->cmd
= BNX2X_Q_CMD_SETUP_TX_ONLY
;
7258 /* Set tx-only QUEUE flags: don't zero statistics */
7259 tx_only_params
->flags
= bnx2x_get_common_flags(bp
, fp
, false);
7261 /* choose the index of the cid to send the slow path on */
7262 tx_only_params
->cid_index
= tx_index
;
7264 /* Set general TX_ONLY_SETUP parameters */
7265 bnx2x_pf_q_prep_general(bp
, fp
, &tx_only_params
->gen_params
, tx_index
);
7267 /* Set Tx TX_ONLY_SETUP parameters */
7268 bnx2x_pf_tx_q_prep(bp
, fp
, &tx_only_params
->txq_params
, tx_index
);
7270 DP(BNX2X_MSG_SP
, "preparing to send tx-only ramrod for connection:"
7271 "cos %d, primary cid %d, cid %d, "
7272 "client id %d, sp-client id %d, flags %lx\n",
7273 tx_index
, q_params
->q_obj
->cids
[FIRST_TX_COS_INDEX
],
7274 q_params
->q_obj
->cids
[tx_index
], q_params
->q_obj
->cl_id
,
7275 tx_only_params
->gen_params
.spcl_id
, tx_only_params
->flags
);
7277 /* send the ramrod */
7278 return bnx2x_queue_state_change(bp
, q_params
);
7283 * bnx2x_setup_queue - setup queue
7285 * @bp: driver handle
7286 * @fp: pointer to fastpath
7287 * @leading: is leading
7289 * This function performs 2 steps in a Queue state machine
7290 * actually: 1) RESET->INIT 2) INIT->SETUP
7293 int bnx2x_setup_queue(struct bnx2x
*bp
, struct bnx2x_fastpath
*fp
,
7296 struct bnx2x_queue_state_params q_params
= {0};
7297 struct bnx2x_queue_setup_params
*setup_params
=
7298 &q_params
.params
.setup
;
7299 struct bnx2x_queue_setup_tx_only_params
*tx_only_params
=
7300 &q_params
.params
.tx_only
;
7304 DP(BNX2X_MSG_SP
, "setting up queue %d\n", fp
->index
);
7306 /* reset IGU state skip FCoE L2 queue */
7307 if (!IS_FCOE_FP(fp
))
7308 bnx2x_ack_sb(bp
, fp
->igu_sb_id
, USTORM_ID
, 0,
7311 q_params
.q_obj
= &fp
->q_obj
;
7312 /* We want to wait for completion in this context */
7313 __set_bit(RAMROD_COMP_WAIT
, &q_params
.ramrod_flags
);
7315 /* Prepare the INIT parameters */
7316 bnx2x_pf_q_prep_init(bp
, fp
, &q_params
.params
.init
);
7318 /* Set the command */
7319 q_params
.cmd
= BNX2X_Q_CMD_INIT
;
7321 /* Change the state to INIT */
7322 rc
= bnx2x_queue_state_change(bp
, &q_params
);
7324 BNX2X_ERR("Queue(%d) INIT failed\n", fp
->index
);
7328 DP(BNX2X_MSG_SP
, "init complete\n");
7331 /* Now move the Queue to the SETUP state... */
7332 memset(setup_params
, 0, sizeof(*setup_params
));
7334 /* Set QUEUE flags */
7335 setup_params
->flags
= bnx2x_get_q_flags(bp
, fp
, leading
);
7337 /* Set general SETUP parameters */
7338 bnx2x_pf_q_prep_general(bp
, fp
, &setup_params
->gen_params
,
7339 FIRST_TX_COS_INDEX
);
7341 bnx2x_pf_rx_q_prep(bp
, fp
, &setup_params
->pause_params
,
7342 &setup_params
->rxq_params
);
7344 bnx2x_pf_tx_q_prep(bp
, fp
, &setup_params
->txq_params
,
7345 FIRST_TX_COS_INDEX
);
7347 /* Set the command */
7348 q_params
.cmd
= BNX2X_Q_CMD_SETUP
;
7350 /* Change the state to SETUP */
7351 rc
= bnx2x_queue_state_change(bp
, &q_params
);
7353 BNX2X_ERR("Queue(%d) SETUP failed\n", fp
->index
);
7357 /* loop through the relevant tx-only indices */
7358 for (tx_index
= FIRST_TX_ONLY_COS_INDEX
;
7359 tx_index
< fp
->max_cos
;
7362 /* prepare and send tx-only ramrod*/
7363 rc
= bnx2x_setup_tx_only(bp
, fp
, &q_params
,
7364 tx_only_params
, tx_index
, leading
);
7366 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
7367 fp
->index
, tx_index
);
7375 static int bnx2x_stop_queue(struct bnx2x
*bp
, int index
)
7377 struct bnx2x_fastpath
*fp
= &bp
->fp
[index
];
7378 struct bnx2x_fp_txdata
*txdata
;
7379 struct bnx2x_queue_state_params q_params
= {0};
7382 DP(BNX2X_MSG_SP
, "stopping queue %d cid %d\n", index
, fp
->cid
);
7384 q_params
.q_obj
= &fp
->q_obj
;
7385 /* We want to wait for completion in this context */
7386 __set_bit(RAMROD_COMP_WAIT
, &q_params
.ramrod_flags
);
7389 /* close tx-only connections */
7390 for (tx_index
= FIRST_TX_ONLY_COS_INDEX
;
7391 tx_index
< fp
->max_cos
;
7394 /* ascertain this is a normal queue*/
7395 txdata
= &fp
->txdata
[tx_index
];
7397 DP(BNX2X_MSG_SP
, "stopping tx-only queue %d\n",
7400 /* send halt terminate on tx-only connection */
7401 q_params
.cmd
= BNX2X_Q_CMD_TERMINATE
;
7402 memset(&q_params
.params
.terminate
, 0,
7403 sizeof(q_params
.params
.terminate
));
7404 q_params
.params
.terminate
.cid_index
= tx_index
;
7406 rc
= bnx2x_queue_state_change(bp
, &q_params
);
7410 /* send halt terminate on tx-only connection */
7411 q_params
.cmd
= BNX2X_Q_CMD_CFC_DEL
;
7412 memset(&q_params
.params
.cfc_del
, 0,
7413 sizeof(q_params
.params
.cfc_del
));
7414 q_params
.params
.cfc_del
.cid_index
= tx_index
;
7415 rc
= bnx2x_queue_state_change(bp
, &q_params
);
7419 /* Stop the primary connection: */
7420 /* ...halt the connection */
7421 q_params
.cmd
= BNX2X_Q_CMD_HALT
;
7422 rc
= bnx2x_queue_state_change(bp
, &q_params
);
7426 /* ...terminate the connection */
7427 q_params
.cmd
= BNX2X_Q_CMD_TERMINATE
;
7428 memset(&q_params
.params
.terminate
, 0,
7429 sizeof(q_params
.params
.terminate
));
7430 q_params
.params
.terminate
.cid_index
= FIRST_TX_COS_INDEX
;
7431 rc
= bnx2x_queue_state_change(bp
, &q_params
);
7434 /* ...delete cfc entry */
7435 q_params
.cmd
= BNX2X_Q_CMD_CFC_DEL
;
7436 memset(&q_params
.params
.cfc_del
, 0,
7437 sizeof(q_params
.params
.cfc_del
));
7438 q_params
.params
.cfc_del
.cid_index
= FIRST_TX_COS_INDEX
;
7439 return bnx2x_queue_state_change(bp
, &q_params
);
7443 static void bnx2x_reset_func(struct bnx2x
*bp
)
7445 int port
= BP_PORT(bp
);
7446 int func
= BP_FUNC(bp
);
7449 /* Disable the function in the FW */
7450 REG_WR8(bp
, BAR_XSTRORM_INTMEM
+ XSTORM_FUNC_EN_OFFSET(func
), 0);
7451 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+ CSTORM_FUNC_EN_OFFSET(func
), 0);
7452 REG_WR8(bp
, BAR_TSTRORM_INTMEM
+ TSTORM_FUNC_EN_OFFSET(func
), 0);
7453 REG_WR8(bp
, BAR_USTRORM_INTMEM
+ USTORM_FUNC_EN_OFFSET(func
), 0);
7456 for_each_eth_queue(bp
, i
) {
7457 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
7458 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+
7459 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp
->fw_sb_id
),
7465 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+
7466 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp
)),
7470 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+
7471 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func
),
7474 for (i
= 0; i
< XSTORM_SPQ_DATA_SIZE
/ 4; i
++)
7475 REG_WR(bp
, BAR_XSTRORM_INTMEM
+ XSTORM_SPQ_DATA_OFFSET(func
),
7479 if (bp
->common
.int_block
== INT_BLOCK_HC
) {
7480 REG_WR(bp
, HC_REG_LEADING_EDGE_0
+ port
*8, 0);
7481 REG_WR(bp
, HC_REG_TRAILING_EDGE_0
+ port
*8, 0);
7483 REG_WR(bp
, IGU_REG_LEADING_EDGE_LATCH
, 0);
7484 REG_WR(bp
, IGU_REG_TRAILING_EDGE_LATCH
, 0);
7488 /* Disable Timer scan */
7489 REG_WR(bp
, TM_REG_EN_LINEAR0_TIMER
+ port
*4, 0);
7491 * Wait for at least 10ms and up to 2 second for the timers scan to
7494 for (i
= 0; i
< 200; i
++) {
7496 if (!REG_RD(bp
, TM_REG_LIN0_SCAN_ON
+ port
*4))
7501 bnx2x_clear_func_ilt(bp
, func
);
7503 /* Timers workaround bug for E2: if this is vnic-3,
7504 * we need to set the entire ilt range for this timers.
7506 if (!CHIP_IS_E1x(bp
) && BP_VN(bp
) == 3) {
7507 struct ilt_client_info ilt_cli
;
7508 /* use dummy TM client */
7509 memset(&ilt_cli
, 0, sizeof(struct ilt_client_info
));
7511 ilt_cli
.end
= ILT_NUM_PAGE_ENTRIES
- 1;
7512 ilt_cli
.client_num
= ILT_CLIENT_TM
;
7514 bnx2x_ilt_boundry_init_op(bp
, &ilt_cli
, 0, INITOP_CLEAR
);
7517 /* this assumes that reset_port() called before reset_func()*/
7518 if (!CHIP_IS_E1x(bp
))
7519 bnx2x_pf_disable(bp
);
7524 static void bnx2x_reset_port(struct bnx2x
*bp
)
7526 int port
= BP_PORT(bp
);
7529 /* Reset physical Link */
7530 bnx2x__link_reset(bp
);
7532 REG_WR(bp
, NIG_REG_MASK_INTERRUPT_PORT0
+ port
*4, 0);
7534 /* Do not rcv packets to BRB */
7535 REG_WR(bp
, NIG_REG_LLH0_BRB1_DRV_MASK
+ port
*4, 0x0);
7536 /* Do not direct rcv packets that are not for MCP to the BRB */
7537 REG_WR(bp
, (port
? NIG_REG_LLH1_BRB1_NOT_MCP
:
7538 NIG_REG_LLH0_BRB1_NOT_MCP
), 0x0);
7541 REG_WR(bp
, MISC_REG_AEU_MASK_ATTN_FUNC_0
+ port
*4, 0);
7544 /* Check for BRB port occupancy */
7545 val
= REG_RD(bp
, BRB1_REG_PORT_NUM_OCC_BLOCKS_0
+ port
*4);
7547 DP(NETIF_MSG_IFDOWN
,
7548 "BRB1 is not empty %d blocks are occupied\n", val
);
7550 /* TODO: Close Doorbell port? */
7553 static inline int bnx2x_reset_hw(struct bnx2x
*bp
, u32 load_code
)
7555 struct bnx2x_func_state_params func_params
= {0};
7557 /* Prepare parameters for function state transitions */
7558 __set_bit(RAMROD_COMP_WAIT
, &func_params
.ramrod_flags
);
7560 func_params
.f_obj
= &bp
->func_obj
;
7561 func_params
.cmd
= BNX2X_F_CMD_HW_RESET
;
7563 func_params
.params
.hw_init
.load_phase
= load_code
;
7565 return bnx2x_func_state_change(bp
, &func_params
);
7568 static inline int bnx2x_func_stop(struct bnx2x
*bp
)
7570 struct bnx2x_func_state_params func_params
= {0};
7573 /* Prepare parameters for function state transitions */
7574 __set_bit(RAMROD_COMP_WAIT
, &func_params
.ramrod_flags
);
7575 func_params
.f_obj
= &bp
->func_obj
;
7576 func_params
.cmd
= BNX2X_F_CMD_STOP
;
7579 * Try to stop the function the 'good way'. If fails (in case
7580 * of a parity error during bnx2x_chip_cleanup()) and we are
7581 * not in a debug mode, perform a state transaction in order to
7582 * enable further HW_RESET transaction.
7584 rc
= bnx2x_func_state_change(bp
, &func_params
);
7586 #ifdef BNX2X_STOP_ON_ERROR
7589 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry "
7591 __set_bit(RAMROD_DRV_CLR_ONLY
, &func_params
.ramrod_flags
);
7592 return bnx2x_func_state_change(bp
, &func_params
);
7600 * bnx2x_send_unload_req - request unload mode from the MCP.
7602 * @bp: driver handle
7603 * @unload_mode: requested function's unload mode
7605 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
7607 u32
bnx2x_send_unload_req(struct bnx2x
*bp
, int unload_mode
)
7610 int port
= BP_PORT(bp
);
7612 /* Select the UNLOAD request mode */
7613 if (unload_mode
== UNLOAD_NORMAL
)
7614 reset_code
= DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS
;
7616 else if (bp
->flags
& NO_WOL_FLAG
)
7617 reset_code
= DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP
;
7620 u32 emac_base
= port
? GRCBASE_EMAC1
: GRCBASE_EMAC0
;
7621 u8
*mac_addr
= bp
->dev
->dev_addr
;
7625 /* The mac address is written to entries 1-4 to
7626 * preserve entry 0 which is used by the PMF
7628 u8 entry
= (BP_VN(bp
) + 1)*8;
7630 val
= (mac_addr
[0] << 8) | mac_addr
[1];
7631 EMAC_WR(bp
, EMAC_REG_EMAC_MAC_MATCH
+ entry
, val
);
7633 val
= (mac_addr
[2] << 24) | (mac_addr
[3] << 16) |
7634 (mac_addr
[4] << 8) | mac_addr
[5];
7635 EMAC_WR(bp
, EMAC_REG_EMAC_MAC_MATCH
+ entry
+ 4, val
);
7637 /* Enable the PME and clear the status */
7638 pci_read_config_word(bp
->pdev
, bp
->pm_cap
+ PCI_PM_CTRL
, &pmc
);
7639 pmc
|= PCI_PM_CTRL_PME_ENABLE
| PCI_PM_CTRL_PME_STATUS
;
7640 pci_write_config_word(bp
->pdev
, bp
->pm_cap
+ PCI_PM_CTRL
, pmc
);
7642 reset_code
= DRV_MSG_CODE_UNLOAD_REQ_WOL_EN
;
7645 reset_code
= DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS
;
7647 /* Send the request to the MCP */
7649 reset_code
= bnx2x_fw_command(bp
, reset_code
, 0);
7651 int path
= BP_PATH(bp
);
7653 DP(NETIF_MSG_IFDOWN
, "NO MCP - load counts[%d] "
7655 path
, load_count
[path
][0], load_count
[path
][1],
7656 load_count
[path
][2]);
7657 load_count
[path
][0]--;
7658 load_count
[path
][1 + port
]--;
7659 DP(NETIF_MSG_IFDOWN
, "NO MCP - new load counts[%d] "
7661 path
, load_count
[path
][0], load_count
[path
][1],
7662 load_count
[path
][2]);
7663 if (load_count
[path
][0] == 0)
7664 reset_code
= FW_MSG_CODE_DRV_UNLOAD_COMMON
;
7665 else if (load_count
[path
][1 + port
] == 0)
7666 reset_code
= FW_MSG_CODE_DRV_UNLOAD_PORT
;
7668 reset_code
= FW_MSG_CODE_DRV_UNLOAD_FUNCTION
;
7675 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
7677 * @bp: driver handle
7679 void bnx2x_send_unload_done(struct bnx2x
*bp
)
7681 /* Report UNLOAD_DONE to MCP */
7683 bnx2x_fw_command(bp
, DRV_MSG_CODE_UNLOAD_DONE
, 0);
7686 static inline int bnx2x_func_wait_started(struct bnx2x
*bp
)
7689 int msix
= (bp
->flags
& USING_MSIX_FLAG
) ? 1 : 0;
7695 * (assumption: No Attention from MCP at this stage)
7696 * PMF probably in the middle of TXdisable/enable transaction
7697 * 1. Sync IRS for default SB
7698 * 2. Sync SP queue - this guarantes us that attention handling started
7699 * 3. Wait, that TXdisable/enable transaction completes
7701 * 1+2 guranty that if DCBx attention was scheduled it already changed
7702 * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy
7703 * received complettion for the transaction the state is TX_STOPPED.
7704 * State will return to STARTED after completion of TX_STOPPED-->STARTED
7708 /* make sure default SB ISR is done */
7710 synchronize_irq(bp
->msix_table
[0].vector
);
7712 synchronize_irq(bp
->pdev
->irq
);
7714 flush_workqueue(bnx2x_wq
);
7716 while (bnx2x_func_get_state(bp
, &bp
->func_obj
) !=
7717 BNX2X_F_STATE_STARTED
&& tout
--)
7720 if (bnx2x_func_get_state(bp
, &bp
->func_obj
) !=
7721 BNX2X_F_STATE_STARTED
) {
7722 #ifdef BNX2X_STOP_ON_ERROR
7726 * Failed to complete the transaction in a "good way"
7727 * Force both transactions with CLR bit
7729 struct bnx2x_func_state_params func_params
= {0};
7731 DP(BNX2X_MSG_SP
, "Hmmm... unexpected function state! "
7732 "Forcing STARTED-->TX_ST0PPED-->STARTED\n");
7734 func_params
.f_obj
= &bp
->func_obj
;
7735 __set_bit(RAMROD_DRV_CLR_ONLY
,
7736 &func_params
.ramrod_flags
);
7738 /* STARTED-->TX_ST0PPED */
7739 func_params
.cmd
= BNX2X_F_CMD_TX_STOP
;
7740 bnx2x_func_state_change(bp
, &func_params
);
7742 /* TX_ST0PPED-->STARTED */
7743 func_params
.cmd
= BNX2X_F_CMD_TX_START
;
7744 return bnx2x_func_state_change(bp
, &func_params
);
7751 void bnx2x_chip_cleanup(struct bnx2x
*bp
, int unload_mode
)
7753 int port
= BP_PORT(bp
);
7756 struct bnx2x_mcast_ramrod_params rparam
= {0};
7759 /* Wait until tx fastpath tasks complete */
7760 for_each_tx_queue(bp
, i
) {
7761 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
7763 for_each_cos_in_tx_queue(fp
, cos
)
7764 rc
= bnx2x_clean_tx_queue(bp
, &fp
->txdata
[cos
]);
7765 #ifdef BNX2X_STOP_ON_ERROR
7771 /* Give HW time to discard old tx messages */
7772 usleep_range(1000, 1000);
7774 /* Clean all ETH MACs */
7775 rc
= bnx2x_del_all_macs(bp
, &bp
->fp
[0].mac_obj
, BNX2X_ETH_MAC
, false);
7777 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc
);
7779 /* Clean up UC list */
7780 rc
= bnx2x_del_all_macs(bp
, &bp
->fp
[0].mac_obj
, BNX2X_UC_LIST_MAC
,
7783 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: "
7787 if (!CHIP_IS_E1(bp
))
7788 REG_WR(bp
, NIG_REG_LLH0_FUNC_EN
+ port
*8, 0);
7790 /* Set "drop all" (stop Rx).
7791 * We need to take a netif_addr_lock() here in order to prevent
7792 * a race between the completion code and this code.
7794 netif_addr_lock_bh(bp
->dev
);
7795 /* Schedule the rx_mode command */
7796 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING
, &bp
->sp_state
))
7797 set_bit(BNX2X_FILTER_RX_MODE_SCHED
, &bp
->sp_state
);
7799 bnx2x_set_storm_rx_mode(bp
);
7801 /* Cleanup multicast configuration */
7802 rparam
.mcast_obj
= &bp
->mcast_obj
;
7803 rc
= bnx2x_config_mcast(bp
, &rparam
, BNX2X_MCAST_CMD_DEL
);
7805 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc
);
7807 netif_addr_unlock_bh(bp
->dev
);
7812 * Send the UNLOAD_REQUEST to the MCP. This will return if
7813 * this function should perform FUNC, PORT or COMMON HW
7816 reset_code
= bnx2x_send_unload_req(bp
, unload_mode
);
7819 * (assumption: No Attention from MCP at this stage)
7820 * PMF probably in the middle of TXdisable/enable transaction
7822 rc
= bnx2x_func_wait_started(bp
);
7824 BNX2X_ERR("bnx2x_func_wait_started failed\n");
7825 #ifdef BNX2X_STOP_ON_ERROR
7830 /* Close multi and leading connections
7831 * Completions for ramrods are collected in a synchronous way
7833 for_each_queue(bp
, i
)
7834 if (bnx2x_stop_queue(bp
, i
))
7835 #ifdef BNX2X_STOP_ON_ERROR
7840 /* If SP settings didn't get completed so far - something
7841 * very wrong has happen.
7843 if (!bnx2x_wait_sp_comp(bp
, ~0x0UL
))
7844 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
7846 #ifndef BNX2X_STOP_ON_ERROR
7849 rc
= bnx2x_func_stop(bp
);
7851 BNX2X_ERR("Function stop failed!\n");
7852 #ifdef BNX2X_STOP_ON_ERROR
7857 /* Disable HW interrupts, NAPI */
7858 bnx2x_netif_stop(bp
, 1);
7863 /* Reset the chip */
7864 rc
= bnx2x_reset_hw(bp
, reset_code
);
7866 BNX2X_ERR("HW_RESET failed\n");
7869 /* Report UNLOAD_DONE to MCP */
7870 bnx2x_send_unload_done(bp
);
7873 void bnx2x_disable_close_the_gate(struct bnx2x
*bp
)
7877 DP(NETIF_MSG_HW
, "Disabling \"close the gates\"\n");
7879 if (CHIP_IS_E1(bp
)) {
7880 int port
= BP_PORT(bp
);
7881 u32 addr
= port
? MISC_REG_AEU_MASK_ATTN_FUNC_1
:
7882 MISC_REG_AEU_MASK_ATTN_FUNC_0
;
7884 val
= REG_RD(bp
, addr
);
7886 REG_WR(bp
, addr
, val
);
7888 val
= REG_RD(bp
, MISC_REG_AEU_GENERAL_MASK
);
7889 val
&= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK
|
7890 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK
);
7891 REG_WR(bp
, MISC_REG_AEU_GENERAL_MASK
, val
);
7895 /* Close gates #2, #3 and #4: */
7896 static void bnx2x_set_234_gates(struct bnx2x
*bp
, bool close
)
7900 /* Gates #2 and #4a are closed/opened for "not E1" only */
7901 if (!CHIP_IS_E1(bp
)) {
7903 REG_WR(bp
, PXP_REG_HST_DISCARD_DOORBELLS
, !!close
);
7905 REG_WR(bp
, PXP_REG_HST_DISCARD_INTERNAL_WRITES
, !!close
);
7909 if (CHIP_IS_E1x(bp
)) {
7910 /* Prevent interrupts from HC on both ports */
7911 val
= REG_RD(bp
, HC_REG_CONFIG_1
);
7912 REG_WR(bp
, HC_REG_CONFIG_1
,
7913 (!close
) ? (val
| HC_CONFIG_1_REG_BLOCK_DISABLE_1
) :
7914 (val
& ~(u32
)HC_CONFIG_1_REG_BLOCK_DISABLE_1
));
7916 val
= REG_RD(bp
, HC_REG_CONFIG_0
);
7917 REG_WR(bp
, HC_REG_CONFIG_0
,
7918 (!close
) ? (val
| HC_CONFIG_0_REG_BLOCK_DISABLE_0
) :
7919 (val
& ~(u32
)HC_CONFIG_0_REG_BLOCK_DISABLE_0
));
7921 /* Prevent incomming interrupts in IGU */
7922 val
= REG_RD(bp
, IGU_REG_BLOCK_CONFIGURATION
);
7924 REG_WR(bp
, IGU_REG_BLOCK_CONFIGURATION
,
7926 (val
| IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE
) :
7927 (val
& ~(u32
)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE
));
7930 DP(NETIF_MSG_HW
, "%s gates #2, #3 and #4\n",
7931 close
? "closing" : "opening");
7935 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
7937 static void bnx2x_clp_reset_prep(struct bnx2x
*bp
, u32
*magic_val
)
7939 /* Do some magic... */
7940 u32 val
= MF_CFG_RD(bp
, shared_mf_config
.clp_mb
);
7941 *magic_val
= val
& SHARED_MF_CLP_MAGIC
;
7942 MF_CFG_WR(bp
, shared_mf_config
.clp_mb
, val
| SHARED_MF_CLP_MAGIC
);
7946 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
7948 * @bp: driver handle
7949 * @magic_val: old value of the `magic' bit.
7951 static void bnx2x_clp_reset_done(struct bnx2x
*bp
, u32 magic_val
)
7953 /* Restore the `magic' bit value... */
7954 u32 val
= MF_CFG_RD(bp
, shared_mf_config
.clp_mb
);
7955 MF_CFG_WR(bp
, shared_mf_config
.clp_mb
,
7956 (val
& (~SHARED_MF_CLP_MAGIC
)) | magic_val
);
7960 * bnx2x_reset_mcp_prep - prepare for MCP reset.
7962 * @bp: driver handle
7963 * @magic_val: old value of 'magic' bit.
7965 * Takes care of CLP configurations.
7967 static void bnx2x_reset_mcp_prep(struct bnx2x
*bp
, u32
*magic_val
)
7970 u32 validity_offset
;
7972 DP(NETIF_MSG_HW
, "Starting\n");
7974 /* Set `magic' bit in order to save MF config */
7975 if (!CHIP_IS_E1(bp
))
7976 bnx2x_clp_reset_prep(bp
, magic_val
);
7978 /* Get shmem offset */
7979 shmem
= REG_RD(bp
, MISC_REG_SHARED_MEM_ADDR
);
7980 validity_offset
= offsetof(struct shmem_region
, validity_map
[0]);
7982 /* Clear validity map flags */
7984 REG_WR(bp
, shmem
+ validity_offset
, 0);
7987 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
7988 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
7991 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
7993 * @bp: driver handle
7995 static inline void bnx2x_mcp_wait_one(struct bnx2x
*bp
)
7997 /* special handling for emulation and FPGA,
7998 wait 10 times longer */
7999 if (CHIP_REV_IS_SLOW(bp
))
8000 msleep(MCP_ONE_TIMEOUT
*10);
8002 msleep(MCP_ONE_TIMEOUT
);
8006 * initializes bp->common.shmem_base and waits for validity signature to appear
8008 static int bnx2x_init_shmem(struct bnx2x
*bp
)
8014 bp
->common
.shmem_base
= REG_RD(bp
, MISC_REG_SHARED_MEM_ADDR
);
8015 if (bp
->common
.shmem_base
) {
8016 val
= SHMEM_RD(bp
, validity_map
[BP_PORT(bp
)]);
8017 if (val
& SHR_MEM_VALIDITY_MB
)
8021 bnx2x_mcp_wait_one(bp
);
8023 } while (cnt
++ < (MCP_TIMEOUT
/ MCP_ONE_TIMEOUT
));
8025 BNX2X_ERR("BAD MCP validity signature\n");
8030 static int bnx2x_reset_mcp_comp(struct bnx2x
*bp
, u32 magic_val
)
8032 int rc
= bnx2x_init_shmem(bp
);
8034 /* Restore the `magic' bit value */
8035 if (!CHIP_IS_E1(bp
))
8036 bnx2x_clp_reset_done(bp
, magic_val
);
8041 static void bnx2x_pxp_prep(struct bnx2x
*bp
)
8043 if (!CHIP_IS_E1(bp
)) {
8044 REG_WR(bp
, PXP2_REG_RD_START_INIT
, 0);
8045 REG_WR(bp
, PXP2_REG_RQ_RBC_DONE
, 0);
8051 * Reset the whole chip except for:
8053 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
8056 * - MISC (including AEU)
8060 static void bnx2x_process_kill_chip_reset(struct bnx2x
*bp
, bool global
)
8062 u32 not_reset_mask1
, reset_mask1
, not_reset_mask2
, reset_mask2
;
8063 u32 global_bits2
, stay_reset2
;
8066 * Bits that have to be set in reset_mask2 if we want to reset 'global'
8067 * (per chip) blocks.
8070 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU
|
8071 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE
;
8073 /* Don't reset the following blocks */
8075 MISC_REGISTERS_RESET_REG_1_RST_HC
|
8076 MISC_REGISTERS_RESET_REG_1_RST_PXPV
|
8077 MISC_REGISTERS_RESET_REG_1_RST_PXP
;
8080 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO
|
8081 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE
|
8082 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE
|
8083 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE
|
8084 MISC_REGISTERS_RESET_REG_2_RST_RBCN
|
8085 MISC_REGISTERS_RESET_REG_2_RST_GRC
|
8086 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE
|
8087 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B
|
8088 MISC_REGISTERS_RESET_REG_2_RST_ATC
|
8089 MISC_REGISTERS_RESET_REG_2_PGLC
;
8092 * Keep the following blocks in reset:
8093 * - all xxMACs are handled by the bnx2x_link code.
8096 MISC_REGISTERS_RESET_REG_2_RST_BMAC0
|
8097 MISC_REGISTERS_RESET_REG_2_RST_BMAC1
|
8098 MISC_REGISTERS_RESET_REG_2_RST_EMAC0
|
8099 MISC_REGISTERS_RESET_REG_2_RST_EMAC1
|
8100 MISC_REGISTERS_RESET_REG_2_UMAC0
|
8101 MISC_REGISTERS_RESET_REG_2_UMAC1
|
8102 MISC_REGISTERS_RESET_REG_2_XMAC
|
8103 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT
;
8105 /* Full reset masks according to the chip */
8106 reset_mask1
= 0xffffffff;
8109 reset_mask2
= 0xffff;
8110 else if (CHIP_IS_E1H(bp
))
8111 reset_mask2
= 0x1ffff;
8112 else if (CHIP_IS_E2(bp
))
8113 reset_mask2
= 0xfffff;
8114 else /* CHIP_IS_E3 */
8115 reset_mask2
= 0x3ffffff;
8117 /* Don't reset global blocks unless we need to */
8119 reset_mask2
&= ~global_bits2
;
8122 * In case of attention in the QM, we need to reset PXP
8123 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
8124 * because otherwise QM reset would release 'close the gates' shortly
8125 * before resetting the PXP, then the PSWRQ would send a write
8126 * request to PGLUE. Then when PXP is reset, PGLUE would try to
8127 * read the payload data from PSWWR, but PSWWR would not
8128 * respond. The write queue in PGLUE would stuck, dmae commands
8129 * would not return. Therefore it's important to reset the second
8130 * reset register (containing the
8131 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
8132 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
8135 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
,
8136 reset_mask2
& (~not_reset_mask2
));
8138 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
,
8139 reset_mask1
& (~not_reset_mask1
));
8144 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_SET
,
8145 reset_mask2
& (~stay_reset2
));
8150 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
, reset_mask1
);
8155 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
8156 * It should get cleared in no more than 1s.
8158 * @bp: driver handle
8160 * It should get cleared in no more than 1s. Returns 0 if
8161 * pending writes bit gets cleared.
8163 static int bnx2x_er_poll_igu_vq(struct bnx2x
*bp
)
8169 pend_bits
= REG_RD(bp
, IGU_REG_PENDING_BITS_STATUS
);
8174 usleep_range(1000, 1000);
8175 } while (cnt
-- > 0);
8178 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
8186 static int bnx2x_process_kill(struct bnx2x
*bp
, bool global
)
8190 u32 sr_cnt
, blk_cnt
, port_is_idle_0
, port_is_idle_1
, pgl_exp_rom2
;
8193 /* Empty the Tetris buffer, wait for 1s */
8195 sr_cnt
= REG_RD(bp
, PXP2_REG_RD_SR_CNT
);
8196 blk_cnt
= REG_RD(bp
, PXP2_REG_RD_BLK_CNT
);
8197 port_is_idle_0
= REG_RD(bp
, PXP2_REG_RD_PORT_IS_IDLE_0
);
8198 port_is_idle_1
= REG_RD(bp
, PXP2_REG_RD_PORT_IS_IDLE_1
);
8199 pgl_exp_rom2
= REG_RD(bp
, PXP2_REG_PGL_EXP_ROM2
);
8200 if ((sr_cnt
== 0x7e) && (blk_cnt
== 0xa0) &&
8201 ((port_is_idle_0
& 0x1) == 0x1) &&
8202 ((port_is_idle_1
& 0x1) == 0x1) &&
8203 (pgl_exp_rom2
== 0xffffffff))
8205 usleep_range(1000, 1000);
8206 } while (cnt
-- > 0);
8209 DP(NETIF_MSG_HW
, "Tetris buffer didn't get empty or there"
8211 " outstanding read requests after 1s!\n");
8212 DP(NETIF_MSG_HW
, "sr_cnt=0x%08x, blk_cnt=0x%08x,"
8213 " port_is_idle_0=0x%08x,"
8214 " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
8215 sr_cnt
, blk_cnt
, port_is_idle_0
, port_is_idle_1
,
8222 /* Close gates #2, #3 and #4 */
8223 bnx2x_set_234_gates(bp
, true);
8225 /* Poll for IGU VQs for 57712 and newer chips */
8226 if (!CHIP_IS_E1x(bp
) && bnx2x_er_poll_igu_vq(bp
))
8230 /* TBD: Indicate that "process kill" is in progress to MCP */
8232 /* Clear "unprepared" bit */
8233 REG_WR(bp
, MISC_REG_UNPREPARED
, 0);
8236 /* Make sure all is written to the chip before the reset */
8239 /* Wait for 1ms to empty GLUE and PCI-E core queues,
8240 * PSWHST, GRC and PSWRD Tetris buffer.
8242 usleep_range(1000, 1000);
8244 /* Prepare to chip reset: */
8247 bnx2x_reset_mcp_prep(bp
, &val
);
8253 /* reset the chip */
8254 bnx2x_process_kill_chip_reset(bp
, global
);
8257 /* Recover after reset: */
8259 if (global
&& bnx2x_reset_mcp_comp(bp
, val
))
8262 /* TBD: Add resetting the NO_MCP mode DB here */
8267 /* Open the gates #2, #3 and #4 */
8268 bnx2x_set_234_gates(bp
, false);
8270 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
8271 * reset state, re-enable attentions. */
8276 int bnx2x_leader_reset(struct bnx2x
*bp
)
8279 bool global
= bnx2x_reset_is_global(bp
);
8281 /* Try to recover after the failure */
8282 if (bnx2x_process_kill(bp
, global
)) {
8283 netdev_err(bp
->dev
, "Something bad had happen on engine %d! "
8284 "Aii!\n", BP_PATH(bp
));
8286 goto exit_leader_reset
;
8290 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
8293 bnx2x_set_reset_done(bp
);
8295 bnx2x_clear_reset_global(bp
);
8299 bnx2x_release_leader_lock(bp
);
8304 static inline void bnx2x_recovery_failed(struct bnx2x
*bp
)
8306 netdev_err(bp
->dev
, "Recovery has failed. Power cycle is needed.\n");
8308 /* Disconnect this device */
8309 netif_device_detach(bp
->dev
);
8312 * Block ifup for all function on this engine until "process kill"
8315 bnx2x_set_reset_in_progress(bp
);
8317 /* Shut down the power */
8318 bnx2x_set_power_state(bp
, PCI_D3hot
);
8320 bp
->recovery_state
= BNX2X_RECOVERY_FAILED
;
8326 * Assumption: runs under rtnl lock. This together with the fact
8327 * that it's called only from bnx2x_sp_rtnl() ensure that it
8328 * will never be called when netif_running(bp->dev) is false.
8330 static void bnx2x_parity_recover(struct bnx2x
*bp
)
8332 bool global
= false;
8334 DP(NETIF_MSG_HW
, "Handling parity\n");
8336 switch (bp
->recovery_state
) {
8337 case BNX2X_RECOVERY_INIT
:
8338 DP(NETIF_MSG_HW
, "State is BNX2X_RECOVERY_INIT\n");
8339 bnx2x_chk_parity_attn(bp
, &global
, false);
8341 /* Try to get a LEADER_LOCK HW lock */
8342 if (bnx2x_trylock_leader_lock(bp
)) {
8343 bnx2x_set_reset_in_progress(bp
);
8345 * Check if there is a global attention and if
8346 * there was a global attention, set the global
8351 bnx2x_set_reset_global(bp
);
8356 /* Stop the driver */
8357 /* If interface has been removed - break */
8358 if (bnx2x_nic_unload(bp
, UNLOAD_RECOVERY
))
8361 bp
->recovery_state
= BNX2X_RECOVERY_WAIT
;
8364 * Reset MCP command sequence number and MCP mail box
8365 * sequence as we are going to reset the MCP.
8369 bp
->fw_drv_pulse_wr_seq
= 0;
8372 /* Ensure "is_leader", MCP command sequence and
8373 * "recovery_state" update values are seen on other
8379 case BNX2X_RECOVERY_WAIT
:
8380 DP(NETIF_MSG_HW
, "State is BNX2X_RECOVERY_WAIT\n");
8381 if (bp
->is_leader
) {
8382 int other_engine
= BP_PATH(bp
) ? 0 : 1;
8383 u32 other_load_counter
=
8384 bnx2x_get_load_cnt(bp
, other_engine
);
8386 bnx2x_get_load_cnt(bp
, BP_PATH(bp
));
8387 global
= bnx2x_reset_is_global(bp
);
8390 * In case of a parity in a global block, let
8391 * the first leader that performs a
8392 * leader_reset() reset the global blocks in
8393 * order to clear global attentions. Otherwise
8394 * the the gates will remain closed for that
8398 (global
&& other_load_counter
)) {
8399 /* Wait until all other functions get
8402 schedule_delayed_work(&bp
->sp_rtnl_task
,
8406 /* If all other functions got down -
8407 * try to bring the chip back to
8408 * normal. In any case it's an exit
8409 * point for a leader.
8411 if (bnx2x_leader_reset(bp
)) {
8412 bnx2x_recovery_failed(bp
);
8416 /* If we are here, means that the
8417 * leader has succeeded and doesn't
8418 * want to be a leader any more. Try
8419 * to continue as a none-leader.
8423 } else { /* non-leader */
8424 if (!bnx2x_reset_is_done(bp
, BP_PATH(bp
))) {
8425 /* Try to get a LEADER_LOCK HW lock as
8426 * long as a former leader may have
8427 * been unloaded by the user or
8428 * released a leadership by another
8431 if (bnx2x_trylock_leader_lock(bp
)) {
8432 /* I'm a leader now! Restart a
8439 schedule_delayed_work(&bp
->sp_rtnl_task
,
8445 * If there was a global attention, wait
8446 * for it to be cleared.
8448 if (bnx2x_reset_is_global(bp
)) {
8449 schedule_delayed_work(
8455 if (bnx2x_nic_load(bp
, LOAD_NORMAL
))
8456 bnx2x_recovery_failed(bp
);
8458 bp
->recovery_state
=
8459 BNX2X_RECOVERY_DONE
;
8472 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
8473 * scheduled on a general queue in order to prevent a dead lock.
8475 static void bnx2x_sp_rtnl_task(struct work_struct
*work
)
8477 struct bnx2x
*bp
= container_of(work
, struct bnx2x
, sp_rtnl_task
.work
);
8481 if (!netif_running(bp
->dev
))
8484 /* if stop on error is defined no recovery flows should be executed */
8485 #ifdef BNX2X_STOP_ON_ERROR
8486 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined "
8487 "so reset not done to allow debug dump,\n"
8488 "you will need to reboot when done\n");
8489 goto sp_rtnl_not_reset
;
8492 if (unlikely(bp
->recovery_state
!= BNX2X_RECOVERY_DONE
)) {
8494 * Clear all pending SP commands as we are going to reset the
8497 bp
->sp_rtnl_state
= 0;
8500 bnx2x_parity_recover(bp
);
8505 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT
, &bp
->sp_rtnl_state
)) {
8507 * Clear all pending SP commands as we are going to reset the
8510 bp
->sp_rtnl_state
= 0;
8513 bnx2x_nic_unload(bp
, UNLOAD_NORMAL
);
8514 bnx2x_nic_load(bp
, LOAD_NORMAL
);
8518 #ifdef BNX2X_STOP_ON_ERROR
8521 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC
, &bp
->sp_rtnl_state
))
8522 bnx2x_setup_tc(bp
->dev
, bp
->dcbx_port_params
.ets
.num_of_cos
);
8525 * in case of fan failure we need to reset id if the "stop on error"
8526 * debug flag is set, since we trying to prevent permanent overheating
8529 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE
, &bp
->sp_rtnl_state
)) {
8530 DP(BNX2X_MSG_SP
, "fan failure detected. Unloading driver\n");
8531 netif_device_detach(bp
->dev
);
8532 bnx2x_close(bp
->dev
);
8539 /* end of nic load/unload */
8541 static void bnx2x_period_task(struct work_struct
*work
)
8543 struct bnx2x
*bp
= container_of(work
, struct bnx2x
, period_task
.work
);
8545 if (!netif_running(bp
->dev
))
8546 goto period_task_exit
;
8548 if (CHIP_REV_IS_SLOW(bp
)) {
8549 BNX2X_ERR("period task called on emulation, ignoring\n");
8550 goto period_task_exit
;
8553 bnx2x_acquire_phy_lock(bp
);
8555 * The barrier is needed to ensure the ordering between the writing to
8556 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
8561 bnx2x_period_func(&bp
->link_params
, &bp
->link_vars
);
8563 /* Re-queue task in 1 sec */
8564 queue_delayed_work(bnx2x_wq
, &bp
->period_task
, 1*HZ
);
8567 bnx2x_release_phy_lock(bp
);
8573 * Init service functions
8576 static u32
bnx2x_get_pretend_reg(struct bnx2x
*bp
)
8578 u32 base
= PXP2_REG_PGL_PRETEND_FUNC_F0
;
8579 u32 stride
= PXP2_REG_PGL_PRETEND_FUNC_F1
- base
;
8580 return base
+ (BP_ABS_FUNC(bp
)) * stride
;
8583 static void bnx2x_undi_int_disable_e1h(struct bnx2x
*bp
)
8585 u32 reg
= bnx2x_get_pretend_reg(bp
);
8587 /* Flush all outstanding writes */
8590 /* Pretend to be function 0 */
8592 REG_RD(bp
, reg
); /* Flush the GRC transaction (in the chip) */
8594 /* From now we are in the "like-E1" mode */
8595 bnx2x_int_disable(bp
);
8597 /* Flush all outstanding writes */
8600 /* Restore the original function */
8601 REG_WR(bp
, reg
, BP_ABS_FUNC(bp
));
8605 static inline void bnx2x_undi_int_disable(struct bnx2x
*bp
)
8608 bnx2x_int_disable(bp
);
8610 bnx2x_undi_int_disable_e1h(bp
);
8613 static void __devinit
bnx2x_undi_unload(struct bnx2x
*bp
)
8617 /* Check if there is any driver already loaded */
8618 val
= REG_RD(bp
, MISC_REG_UNPREPARED
);
8621 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RESET
);
8623 * Check if it is the UNDI driver
8624 * UNDI driver initializes CID offset for normal bell to 0x7
8626 val
= REG_RD(bp
, DORQ_REG_NORM_CID_OFST
);
8628 u32 reset_code
= DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS
;
8629 /* save our pf_num */
8630 int orig_pf_num
= bp
->pf_num
;
8632 u32 swap_en
, swap_val
, value
;
8634 /* clear the UNDI indication */
8635 REG_WR(bp
, DORQ_REG_NORM_CID_OFST
, 0);
8637 BNX2X_DEV_INFO("UNDI is active! reset device\n");
8639 /* try unload UNDI on port 0 */
8642 (SHMEM_RD(bp
, func_mb
[bp
->pf_num
].drv_mb_header
) &
8643 DRV_MSG_SEQ_NUMBER_MASK
);
8644 reset_code
= bnx2x_fw_command(bp
, reset_code
, 0);
8646 /* if UNDI is loaded on the other port */
8647 if (reset_code
!= FW_MSG_CODE_DRV_UNLOAD_COMMON
) {
8649 /* send "DONE" for previous unload */
8650 bnx2x_fw_command(bp
,
8651 DRV_MSG_CODE_UNLOAD_DONE
, 0);
8653 /* unload UNDI on port 1 */
8656 (SHMEM_RD(bp
, func_mb
[bp
->pf_num
].drv_mb_header
) &
8657 DRV_MSG_SEQ_NUMBER_MASK
);
8658 reset_code
= DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS
;
8660 bnx2x_fw_command(bp
, reset_code
, 0);
8663 bnx2x_undi_int_disable(bp
);
8666 /* close input traffic and wait for it */
8667 /* Do not rcv packets to BRB */
8668 REG_WR(bp
, (port
? NIG_REG_LLH1_BRB1_DRV_MASK
:
8669 NIG_REG_LLH0_BRB1_DRV_MASK
), 0x0);
8670 /* Do not direct rcv packets that are not for MCP to
8672 REG_WR(bp
, (port
? NIG_REG_LLH1_BRB1_NOT_MCP
:
8673 NIG_REG_LLH0_BRB1_NOT_MCP
), 0x0);
8675 REG_WR(bp
, (port
? MISC_REG_AEU_MASK_ATTN_FUNC_1
:
8676 MISC_REG_AEU_MASK_ATTN_FUNC_0
), 0);
8679 /* save NIG port swap info */
8680 swap_val
= REG_RD(bp
, NIG_REG_PORT_SWAP
);
8681 swap_en
= REG_RD(bp
, NIG_REG_STRAP_OVERRIDE
);
8684 GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
,
8688 if (CHIP_IS_E3(bp
)) {
8689 value
|= MISC_REGISTERS_RESET_REG_2_MSTAT0
;
8690 value
|= MISC_REGISTERS_RESET_REG_2_MSTAT1
;
8694 GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
,
8697 /* take the NIG out of reset and restore swap values */
8699 GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
,
8700 MISC_REGISTERS_RESET_REG_1_RST_NIG
);
8701 REG_WR(bp
, NIG_REG_PORT_SWAP
, swap_val
);
8702 REG_WR(bp
, NIG_REG_STRAP_OVERRIDE
, swap_en
);
8704 /* send unload done to the MCP */
8705 bnx2x_fw_command(bp
, DRV_MSG_CODE_UNLOAD_DONE
, 0);
8707 /* restore our func and fw_seq */
8708 bp
->pf_num
= orig_pf_num
;
8710 (SHMEM_RD(bp
, func_mb
[bp
->pf_num
].drv_mb_header
) &
8711 DRV_MSG_SEQ_NUMBER_MASK
);
8714 /* now it's safe to release the lock */
8715 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RESET
);
8719 static void __devinit
bnx2x_get_common_hwinfo(struct bnx2x
*bp
)
8721 u32 val
, val2
, val3
, val4
, id
;
8724 /* Get the chip revision id and number. */
8725 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
8726 val
= REG_RD(bp
, MISC_REG_CHIP_NUM
);
8727 id
= ((val
& 0xffff) << 16);
8728 val
= REG_RD(bp
, MISC_REG_CHIP_REV
);
8729 id
|= ((val
& 0xf) << 12);
8730 val
= REG_RD(bp
, MISC_REG_CHIP_METAL
);
8731 id
|= ((val
& 0xff) << 4);
8732 val
= REG_RD(bp
, MISC_REG_BOND_ID
);
8734 bp
->common
.chip_id
= id
;
8736 /* Set doorbell size */
8737 bp
->db_size
= (1 << BNX2X_DB_SHIFT
);
8739 if (!CHIP_IS_E1x(bp
)) {
8740 val
= REG_RD(bp
, MISC_REG_PORT4MODE_EN_OVWR
);
8742 val
= REG_RD(bp
, MISC_REG_PORT4MODE_EN
);
8744 val
= (val
>> 1) & 1;
8745 BNX2X_DEV_INFO("chip is in %s\n", val
? "4_PORT_MODE" :
8747 bp
->common
.chip_port_mode
= val
? CHIP_4_PORT_MODE
:
8750 if (CHIP_MODE_IS_4_PORT(bp
))
8751 bp
->pfid
= (bp
->pf_num
>> 1); /* 0..3 */
8753 bp
->pfid
= (bp
->pf_num
& 0x6); /* 0, 2, 4, 6 */
8755 bp
->common
.chip_port_mode
= CHIP_PORT_MODE_NONE
; /* N/A */
8756 bp
->pfid
= bp
->pf_num
; /* 0..7 */
8759 bp
->link_params
.chip_id
= bp
->common
.chip_id
;
8760 BNX2X_DEV_INFO("chip ID is 0x%x\n", id
);
8762 val
= (REG_RD(bp
, 0x2874) & 0x55);
8763 if ((bp
->common
.chip_id
& 0x1) ||
8764 (CHIP_IS_E1(bp
) && val
) || (CHIP_IS_E1H(bp
) && (val
== 0x55))) {
8765 bp
->flags
|= ONE_PORT_FLAG
;
8766 BNX2X_DEV_INFO("single port device\n");
8769 val
= REG_RD(bp
, MCP_REG_MCPR_NVM_CFG4
);
8770 bp
->common
.flash_size
= (BNX2X_NVRAM_1MB_SIZE
<<
8771 (val
& MCPR_NVM_CFG4_FLASH_SIZE
));
8772 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
8773 bp
->common
.flash_size
, bp
->common
.flash_size
);
8775 bnx2x_init_shmem(bp
);
8779 bp
->common
.shmem2_base
= REG_RD(bp
, (BP_PATH(bp
) ?
8780 MISC_REG_GENERIC_CR_1
:
8781 MISC_REG_GENERIC_CR_0
));
8783 bp
->link_params
.shmem_base
= bp
->common
.shmem_base
;
8784 bp
->link_params
.shmem2_base
= bp
->common
.shmem2_base
;
8785 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
8786 bp
->common
.shmem_base
, bp
->common
.shmem2_base
);
8788 if (!bp
->common
.shmem_base
) {
8789 BNX2X_DEV_INFO("MCP not active\n");
8790 bp
->flags
|= NO_MCP_FLAG
;
8794 bp
->common
.hw_config
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.config
);
8795 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp
->common
.hw_config
);
8797 bp
->link_params
.hw_led_mode
= ((bp
->common
.hw_config
&
8798 SHARED_HW_CFG_LED_MODE_MASK
) >>
8799 SHARED_HW_CFG_LED_MODE_SHIFT
);
8801 bp
->link_params
.feature_config_flags
= 0;
8802 val
= SHMEM_RD(bp
, dev_info
.shared_feature_config
.config
);
8803 if (val
& SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED
)
8804 bp
->link_params
.feature_config_flags
|=
8805 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED
;
8807 bp
->link_params
.feature_config_flags
&=
8808 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED
;
8810 val
= SHMEM_RD(bp
, dev_info
.bc_rev
) >> 8;
8811 bp
->common
.bc_ver
= val
;
8812 BNX2X_DEV_INFO("bc_ver %X\n", val
);
8813 if (val
< BNX2X_BC_VER
) {
8814 /* for now only warn
8815 * later we might need to enforce this */
8816 BNX2X_ERR("This driver needs bc_ver %X but found %X, "
8817 "please upgrade BC\n", BNX2X_BC_VER
, val
);
8819 bp
->link_params
.feature_config_flags
|=
8820 (val
>= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL
) ?
8821 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY
: 0;
8823 bp
->link_params
.feature_config_flags
|=
8824 (val
>= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL
) ?
8825 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY
: 0;
8827 bp
->link_params
.feature_config_flags
|=
8828 (val
>= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED
) ?
8829 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED
: 0;
8830 bp
->flags
|= (val
>= REQ_BC_VER_4_PFC_STATS_SUPPORTED
) ?
8831 BC_SUPPORTS_PFC_STATS
: 0;
8833 pci_read_config_word(bp
->pdev
, bp
->pm_cap
+ PCI_PM_PMC
, &pmc
);
8834 bp
->flags
|= (pmc
& PCI_PM_CAP_PME_D3cold
) ? 0 : NO_WOL_FLAG
;
8836 BNX2X_DEV_INFO("%sWoL capable\n",
8837 (bp
->flags
& NO_WOL_FLAG
) ? "not " : "");
8839 val
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.part_num
);
8840 val2
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.part_num
[4]);
8841 val3
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.part_num
[8]);
8842 val4
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.part_num
[12]);
8844 dev_info(&bp
->pdev
->dev
, "part number %X-%X-%X-%X\n",
8845 val
, val2
, val3
, val4
);
8848 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8849 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8851 static void __devinit
bnx2x_get_igu_cam_info(struct bnx2x
*bp
)
8853 int pfid
= BP_FUNC(bp
);
8856 u8 fid
, igu_sb_cnt
= 0;
8858 bp
->igu_base_sb
= 0xff;
8859 if (CHIP_INT_MODE_IS_BC(bp
)) {
8861 igu_sb_cnt
= bp
->igu_sb_cnt
;
8862 bp
->igu_base_sb
= (CHIP_MODE_IS_4_PORT(bp
) ? pfid
: vn
) *
8865 bp
->igu_dsb_id
= E1HVN_MAX
* FP_SB_MAX_E1x
+
8866 (CHIP_MODE_IS_4_PORT(bp
) ? pfid
: vn
);
8871 /* IGU in normal mode - read CAM */
8872 for (igu_sb_id
= 0; igu_sb_id
< IGU_REG_MAPPING_MEMORY_SIZE
;
8874 val
= REG_RD(bp
, IGU_REG_MAPPING_MEMORY
+ igu_sb_id
* 4);
8875 if (!(val
& IGU_REG_MAPPING_MEMORY_VALID
))
8878 if ((fid
& IGU_FID_ENCODE_IS_PF
)) {
8879 if ((fid
& IGU_FID_PF_NUM_MASK
) != pfid
)
8881 if (IGU_VEC(val
) == 0)
8882 /* default status block */
8883 bp
->igu_dsb_id
= igu_sb_id
;
8885 if (bp
->igu_base_sb
== 0xff)
8886 bp
->igu_base_sb
= igu_sb_id
;
8892 #ifdef CONFIG_PCI_MSI
8894 * It's expected that number of CAM entries for this functions is equal
8895 * to the number evaluated based on the MSI-X table size. We want a
8896 * harsh warning if these values are different!
8898 WARN_ON(bp
->igu_sb_cnt
!= igu_sb_cnt
);
8901 if (igu_sb_cnt
== 0)
8902 BNX2X_ERR("CAM configuration error\n");
8905 static void __devinit
bnx2x_link_settings_supported(struct bnx2x
*bp
,
8908 int cfg_size
= 0, idx
, port
= BP_PORT(bp
);
8910 /* Aggregation of supported attributes of all external phys */
8911 bp
->port
.supported
[0] = 0;
8912 bp
->port
.supported
[1] = 0;
8913 switch (bp
->link_params
.num_phys
) {
8915 bp
->port
.supported
[0] = bp
->link_params
.phy
[INT_PHY
].supported
;
8919 bp
->port
.supported
[0] = bp
->link_params
.phy
[EXT_PHY1
].supported
;
8923 if (bp
->link_params
.multi_phy_config
&
8924 PORT_HW_CFG_PHY_SWAPPED_ENABLED
) {
8925 bp
->port
.supported
[1] =
8926 bp
->link_params
.phy
[EXT_PHY1
].supported
;
8927 bp
->port
.supported
[0] =
8928 bp
->link_params
.phy
[EXT_PHY2
].supported
;
8930 bp
->port
.supported
[0] =
8931 bp
->link_params
.phy
[EXT_PHY1
].supported
;
8932 bp
->port
.supported
[1] =
8933 bp
->link_params
.phy
[EXT_PHY2
].supported
;
8939 if (!(bp
->port
.supported
[0] || bp
->port
.supported
[1])) {
8940 BNX2X_ERR("NVRAM config error. BAD phy config."
8941 "PHY1 config 0x%x, PHY2 config 0x%x\n",
8943 dev_info
.port_hw_config
[port
].external_phy_config
),
8945 dev_info
.port_hw_config
[port
].external_phy_config2
));
8950 bp
->port
.phy_addr
= REG_RD(bp
, MISC_REG_WC0_CTRL_PHY_ADDR
);
8952 switch (switch_cfg
) {
8954 bp
->port
.phy_addr
= REG_RD(
8955 bp
, NIG_REG_SERDES0_CTRL_PHY_ADDR
+ port
*0x10);
8957 case SWITCH_CFG_10G
:
8958 bp
->port
.phy_addr
= REG_RD(
8959 bp
, NIG_REG_XGXS0_CTRL_PHY_ADDR
+ port
*0x18);
8962 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
8963 bp
->port
.link_config
[0]);
8967 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp
->port
.phy_addr
);
8968 /* mask what we support according to speed_cap_mask per configuration */
8969 for (idx
= 0; idx
< cfg_size
; idx
++) {
8970 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
8971 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF
))
8972 bp
->port
.supported
[idx
] &= ~SUPPORTED_10baseT_Half
;
8974 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
8975 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL
))
8976 bp
->port
.supported
[idx
] &= ~SUPPORTED_10baseT_Full
;
8978 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
8979 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF
))
8980 bp
->port
.supported
[idx
] &= ~SUPPORTED_100baseT_Half
;
8982 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
8983 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL
))
8984 bp
->port
.supported
[idx
] &= ~SUPPORTED_100baseT_Full
;
8986 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
8987 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
))
8988 bp
->port
.supported
[idx
] &= ~(SUPPORTED_1000baseT_Half
|
8989 SUPPORTED_1000baseT_Full
);
8991 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
8992 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G
))
8993 bp
->port
.supported
[idx
] &= ~SUPPORTED_2500baseX_Full
;
8995 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
8996 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
))
8997 bp
->port
.supported
[idx
] &= ~SUPPORTED_10000baseT_Full
;
9001 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp
->port
.supported
[0],
9002 bp
->port
.supported
[1]);
9005 static void __devinit
bnx2x_link_settings_requested(struct bnx2x
*bp
)
9007 u32 link_config
, idx
, cfg_size
= 0;
9008 bp
->port
.advertising
[0] = 0;
9009 bp
->port
.advertising
[1] = 0;
9010 switch (bp
->link_params
.num_phys
) {
9019 for (idx
= 0; idx
< cfg_size
; idx
++) {
9020 bp
->link_params
.req_duplex
[idx
] = DUPLEX_FULL
;
9021 link_config
= bp
->port
.link_config
[idx
];
9022 switch (link_config
& PORT_FEATURE_LINK_SPEED_MASK
) {
9023 case PORT_FEATURE_LINK_SPEED_AUTO
:
9024 if (bp
->port
.supported
[idx
] & SUPPORTED_Autoneg
) {
9025 bp
->link_params
.req_line_speed
[idx
] =
9027 bp
->port
.advertising
[idx
] |=
9028 bp
->port
.supported
[idx
];
9030 /* force 10G, no AN */
9031 bp
->link_params
.req_line_speed
[idx
] =
9033 bp
->port
.advertising
[idx
] |=
9034 (ADVERTISED_10000baseT_Full
|
9040 case PORT_FEATURE_LINK_SPEED_10M_FULL
:
9041 if (bp
->port
.supported
[idx
] & SUPPORTED_10baseT_Full
) {
9042 bp
->link_params
.req_line_speed
[idx
] =
9044 bp
->port
.advertising
[idx
] |=
9045 (ADVERTISED_10baseT_Full
|
9048 BNX2X_ERR("NVRAM config error. "
9049 "Invalid link_config 0x%x"
9050 " speed_cap_mask 0x%x\n",
9052 bp
->link_params
.speed_cap_mask
[idx
]);
9057 case PORT_FEATURE_LINK_SPEED_10M_HALF
:
9058 if (bp
->port
.supported
[idx
] & SUPPORTED_10baseT_Half
) {
9059 bp
->link_params
.req_line_speed
[idx
] =
9061 bp
->link_params
.req_duplex
[idx
] =
9063 bp
->port
.advertising
[idx
] |=
9064 (ADVERTISED_10baseT_Half
|
9067 BNX2X_ERR("NVRAM config error. "
9068 "Invalid link_config 0x%x"
9069 " speed_cap_mask 0x%x\n",
9071 bp
->link_params
.speed_cap_mask
[idx
]);
9076 case PORT_FEATURE_LINK_SPEED_100M_FULL
:
9077 if (bp
->port
.supported
[idx
] &
9078 SUPPORTED_100baseT_Full
) {
9079 bp
->link_params
.req_line_speed
[idx
] =
9081 bp
->port
.advertising
[idx
] |=
9082 (ADVERTISED_100baseT_Full
|
9085 BNX2X_ERR("NVRAM config error. "
9086 "Invalid link_config 0x%x"
9087 " speed_cap_mask 0x%x\n",
9089 bp
->link_params
.speed_cap_mask
[idx
]);
9094 case PORT_FEATURE_LINK_SPEED_100M_HALF
:
9095 if (bp
->port
.supported
[idx
] &
9096 SUPPORTED_100baseT_Half
) {
9097 bp
->link_params
.req_line_speed
[idx
] =
9099 bp
->link_params
.req_duplex
[idx
] =
9101 bp
->port
.advertising
[idx
] |=
9102 (ADVERTISED_100baseT_Half
|
9105 BNX2X_ERR("NVRAM config error. "
9106 "Invalid link_config 0x%x"
9107 " speed_cap_mask 0x%x\n",
9109 bp
->link_params
.speed_cap_mask
[idx
]);
9114 case PORT_FEATURE_LINK_SPEED_1G
:
9115 if (bp
->port
.supported
[idx
] &
9116 SUPPORTED_1000baseT_Full
) {
9117 bp
->link_params
.req_line_speed
[idx
] =
9119 bp
->port
.advertising
[idx
] |=
9120 (ADVERTISED_1000baseT_Full
|
9123 BNX2X_ERR("NVRAM config error. "
9124 "Invalid link_config 0x%x"
9125 " speed_cap_mask 0x%x\n",
9127 bp
->link_params
.speed_cap_mask
[idx
]);
9132 case PORT_FEATURE_LINK_SPEED_2_5G
:
9133 if (bp
->port
.supported
[idx
] &
9134 SUPPORTED_2500baseX_Full
) {
9135 bp
->link_params
.req_line_speed
[idx
] =
9137 bp
->port
.advertising
[idx
] |=
9138 (ADVERTISED_2500baseX_Full
|
9141 BNX2X_ERR("NVRAM config error. "
9142 "Invalid link_config 0x%x"
9143 " speed_cap_mask 0x%x\n",
9145 bp
->link_params
.speed_cap_mask
[idx
]);
9150 case PORT_FEATURE_LINK_SPEED_10G_CX4
:
9151 if (bp
->port
.supported
[idx
] &
9152 SUPPORTED_10000baseT_Full
) {
9153 bp
->link_params
.req_line_speed
[idx
] =
9155 bp
->port
.advertising
[idx
] |=
9156 (ADVERTISED_10000baseT_Full
|
9159 BNX2X_ERR("NVRAM config error. "
9160 "Invalid link_config 0x%x"
9161 " speed_cap_mask 0x%x\n",
9163 bp
->link_params
.speed_cap_mask
[idx
]);
9167 case PORT_FEATURE_LINK_SPEED_20G
:
9168 bp
->link_params
.req_line_speed
[idx
] = SPEED_20000
;
9172 BNX2X_ERR("NVRAM config error. "
9173 "BAD link speed link_config 0x%x\n",
9175 bp
->link_params
.req_line_speed
[idx
] =
9177 bp
->port
.advertising
[idx
] =
9178 bp
->port
.supported
[idx
];
9182 bp
->link_params
.req_flow_ctrl
[idx
] = (link_config
&
9183 PORT_FEATURE_FLOW_CONTROL_MASK
);
9184 if ((bp
->link_params
.req_flow_ctrl
[idx
] ==
9185 BNX2X_FLOW_CTRL_AUTO
) &&
9186 !(bp
->port
.supported
[idx
] & SUPPORTED_Autoneg
)) {
9187 bp
->link_params
.req_flow_ctrl
[idx
] =
9188 BNX2X_FLOW_CTRL_NONE
;
9191 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl"
9192 " 0x%x advertising 0x%x\n",
9193 bp
->link_params
.req_line_speed
[idx
],
9194 bp
->link_params
.req_duplex
[idx
],
9195 bp
->link_params
.req_flow_ctrl
[idx
],
9196 bp
->port
.advertising
[idx
]);
9200 static void __devinit
bnx2x_set_mac_buf(u8
*mac_buf
, u32 mac_lo
, u16 mac_hi
)
9202 mac_hi
= cpu_to_be16(mac_hi
);
9203 mac_lo
= cpu_to_be32(mac_lo
);
9204 memcpy(mac_buf
, &mac_hi
, sizeof(mac_hi
));
9205 memcpy(mac_buf
+ sizeof(mac_hi
), &mac_lo
, sizeof(mac_lo
));
9208 static void __devinit
bnx2x_get_port_hwinfo(struct bnx2x
*bp
)
9210 int port
= BP_PORT(bp
);
9212 u32 ext_phy_type
, ext_phy_config
;
9214 bp
->link_params
.bp
= bp
;
9215 bp
->link_params
.port
= port
;
9217 bp
->link_params
.lane_config
=
9218 SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].lane_config
);
9220 bp
->link_params
.speed_cap_mask
[0] =
9222 dev_info
.port_hw_config
[port
].speed_capability_mask
);
9223 bp
->link_params
.speed_cap_mask
[1] =
9225 dev_info
.port_hw_config
[port
].speed_capability_mask2
);
9226 bp
->port
.link_config
[0] =
9227 SHMEM_RD(bp
, dev_info
.port_feature_config
[port
].link_config
);
9229 bp
->port
.link_config
[1] =
9230 SHMEM_RD(bp
, dev_info
.port_feature_config
[port
].link_config2
);
9232 bp
->link_params
.multi_phy_config
=
9233 SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].multi_phy_config
);
9234 /* If the device is capable of WoL, set the default state according
9237 config
= SHMEM_RD(bp
, dev_info
.port_feature_config
[port
].config
);
9238 bp
->wol
= (!(bp
->flags
& NO_WOL_FLAG
) &&
9239 (config
& PORT_FEATURE_WOL_ENABLED
));
9241 BNX2X_DEV_INFO("lane_config 0x%08x "
9242 "speed_cap_mask0 0x%08x link_config0 0x%08x\n",
9243 bp
->link_params
.lane_config
,
9244 bp
->link_params
.speed_cap_mask
[0],
9245 bp
->port
.link_config
[0]);
9247 bp
->link_params
.switch_cfg
= (bp
->port
.link_config
[0] &
9248 PORT_FEATURE_CONNECTED_SWITCH_MASK
);
9249 bnx2x_phy_probe(&bp
->link_params
);
9250 bnx2x_link_settings_supported(bp
, bp
->link_params
.switch_cfg
);
9252 bnx2x_link_settings_requested(bp
);
9255 * If connected directly, work with the internal PHY, otherwise, work
9256 * with the external PHY
9260 dev_info
.port_hw_config
[port
].external_phy_config
);
9261 ext_phy_type
= XGXS_EXT_PHY_TYPE(ext_phy_config
);
9262 if (ext_phy_type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
)
9263 bp
->mdio
.prtad
= bp
->port
.phy_addr
;
9265 else if ((ext_phy_type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE
) &&
9266 (ext_phy_type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN
))
9268 XGXS_EXT_PHY_ADDR(ext_phy_config
);
9271 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s)
9272 * In MF mode, it is set to cover self test cases
9275 bp
->port
.need_hw_lock
= 1;
9277 bp
->port
.need_hw_lock
= bnx2x_hw_lock_required(bp
,
9278 bp
->common
.shmem_base
,
9279 bp
->common
.shmem2_base
);
9283 void bnx2x_get_iscsi_info(struct bnx2x
*bp
)
9285 int port
= BP_PORT(bp
);
9287 u32 max_iscsi_conn
= FW_ENCODE_32BIT_PATTERN
^ SHMEM_RD(bp
,
9288 drv_lic_key
[port
].max_iscsi_conn
);
9290 /* Get the number of maximum allowed iSCSI connections */
9291 bp
->cnic_eth_dev
.max_iscsi_conn
=
9292 (max_iscsi_conn
& BNX2X_MAX_ISCSI_INIT_CONN_MASK
) >>
9293 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT
;
9295 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
9296 bp
->cnic_eth_dev
.max_iscsi_conn
);
9299 * If maximum allowed number of connections is zero -
9300 * disable the feature.
9302 if (!bp
->cnic_eth_dev
.max_iscsi_conn
)
9303 bp
->flags
|= NO_ISCSI_FLAG
;
9306 static void __devinit
bnx2x_get_fcoe_info(struct bnx2x
*bp
)
9308 int port
= BP_PORT(bp
);
9309 int func
= BP_ABS_FUNC(bp
);
9311 u32 max_fcoe_conn
= FW_ENCODE_32BIT_PATTERN
^ SHMEM_RD(bp
,
9312 drv_lic_key
[port
].max_fcoe_conn
);
9314 /* Get the number of maximum allowed FCoE connections */
9315 bp
->cnic_eth_dev
.max_fcoe_conn
=
9316 (max_fcoe_conn
& BNX2X_MAX_FCOE_INIT_CONN_MASK
) >>
9317 BNX2X_MAX_FCOE_INIT_CONN_SHIFT
;
9322 bp
->cnic_eth_dev
.fcoe_wwn_port_name_hi
=
9324 dev_info
.port_hw_config
[port
].
9325 fcoe_wwn_port_name_upper
);
9326 bp
->cnic_eth_dev
.fcoe_wwn_port_name_lo
=
9328 dev_info
.port_hw_config
[port
].
9329 fcoe_wwn_port_name_lower
);
9332 bp
->cnic_eth_dev
.fcoe_wwn_node_name_hi
=
9334 dev_info
.port_hw_config
[port
].
9335 fcoe_wwn_node_name_upper
);
9336 bp
->cnic_eth_dev
.fcoe_wwn_node_name_lo
=
9338 dev_info
.port_hw_config
[port
].
9339 fcoe_wwn_node_name_lower
);
9340 } else if (!IS_MF_SD(bp
)) {
9341 u32 cfg
= MF_CFG_RD(bp
, func_ext_config
[func
].func_cfg
);
9344 * Read the WWN info only if the FCoE feature is enabled for
9347 if (cfg
& MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD
) {
9349 bp
->cnic_eth_dev
.fcoe_wwn_port_name_hi
=
9350 MF_CFG_RD(bp
, func_ext_config
[func
].
9351 fcoe_wwn_port_name_upper
);
9352 bp
->cnic_eth_dev
.fcoe_wwn_port_name_lo
=
9353 MF_CFG_RD(bp
, func_ext_config
[func
].
9354 fcoe_wwn_port_name_lower
);
9357 bp
->cnic_eth_dev
.fcoe_wwn_node_name_hi
=
9358 MF_CFG_RD(bp
, func_ext_config
[func
].
9359 fcoe_wwn_node_name_upper
);
9360 bp
->cnic_eth_dev
.fcoe_wwn_node_name_lo
=
9361 MF_CFG_RD(bp
, func_ext_config
[func
].
9362 fcoe_wwn_node_name_lower
);
9366 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp
->cnic_eth_dev
.max_fcoe_conn
);
9369 * If maximum allowed number of connections is zero -
9370 * disable the feature.
9372 if (!bp
->cnic_eth_dev
.max_fcoe_conn
)
9373 bp
->flags
|= NO_FCOE_FLAG
;
9376 static void __devinit
bnx2x_get_cnic_info(struct bnx2x
*bp
)
9379 * iSCSI may be dynamically disabled but reading
9380 * info here we will decrease memory usage by driver
9381 * if the feature is disabled for good
9383 bnx2x_get_iscsi_info(bp
);
9384 bnx2x_get_fcoe_info(bp
);
9388 static void __devinit
bnx2x_get_mac_hwinfo(struct bnx2x
*bp
)
9391 int func
= BP_ABS_FUNC(bp
);
9392 int port
= BP_PORT(bp
);
9394 u8
*iscsi_mac
= bp
->cnic_eth_dev
.iscsi_mac
;
9395 u8
*fip_mac
= bp
->fip_mac
;
9398 /* Zero primary MAC configuration */
9399 memset(bp
->dev
->dev_addr
, 0, ETH_ALEN
);
9402 BNX2X_ERROR("warning: random MAC workaround active\n");
9403 random_ether_addr(bp
->dev
->dev_addr
);
9404 } else if (IS_MF(bp
)) {
9405 val2
= MF_CFG_RD(bp
, func_mf_config
[func
].mac_upper
);
9406 val
= MF_CFG_RD(bp
, func_mf_config
[func
].mac_lower
);
9407 if ((val2
!= FUNC_MF_CFG_UPPERMAC_DEFAULT
) &&
9408 (val
!= FUNC_MF_CFG_LOWERMAC_DEFAULT
))
9409 bnx2x_set_mac_buf(bp
->dev
->dev_addr
, val
, val2
);
9413 * iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
9414 * FCoE MAC then the appropriate feature should be disabled.
9417 u32 cfg
= MF_CFG_RD(bp
, func_ext_config
[func
].func_cfg
);
9418 if (cfg
& MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD
) {
9419 val2
= MF_CFG_RD(bp
, func_ext_config
[func
].
9420 iscsi_mac_addr_upper
);
9421 val
= MF_CFG_RD(bp
, func_ext_config
[func
].
9422 iscsi_mac_addr_lower
);
9423 bnx2x_set_mac_buf(iscsi_mac
, val
, val2
);
9424 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n",
9427 bp
->flags
|= NO_ISCSI_OOO_FLAG
| NO_ISCSI_FLAG
;
9429 if (cfg
& MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD
) {
9430 val2
= MF_CFG_RD(bp
, func_ext_config
[func
].
9431 fcoe_mac_addr_upper
);
9432 val
= MF_CFG_RD(bp
, func_ext_config
[func
].
9433 fcoe_mac_addr_lower
);
9434 bnx2x_set_mac_buf(fip_mac
, val
, val2
);
9435 BNX2X_DEV_INFO("Read FCoE L2 MAC: %pM\n",
9439 bp
->flags
|= NO_FCOE_FLAG
;
9440 } else { /* SD mode */
9441 if (BNX2X_IS_MF_PROTOCOL_ISCSI(bp
)) {
9442 /* use primary mac as iscsi mac */
9443 memcpy(iscsi_mac
, bp
->dev
->dev_addr
, ETH_ALEN
);
9444 /* Zero primary MAC configuration */
9445 memset(bp
->dev
->dev_addr
, 0, ETH_ALEN
);
9447 BNX2X_DEV_INFO("SD ISCSI MODE\n");
9448 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n",
9454 /* in SF read MACs from port configuration */
9455 val2
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].mac_upper
);
9456 val
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].mac_lower
);
9457 bnx2x_set_mac_buf(bp
->dev
->dev_addr
, val
, val2
);
9460 val2
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].
9462 val
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].
9464 bnx2x_set_mac_buf(iscsi_mac
, val
, val2
);
9466 val2
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].
9467 fcoe_fip_mac_upper
);
9468 val
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].
9469 fcoe_fip_mac_lower
);
9470 bnx2x_set_mac_buf(fip_mac
, val
, val2
);
9474 memcpy(bp
->link_params
.mac_addr
, bp
->dev
->dev_addr
, ETH_ALEN
);
9475 memcpy(bp
->dev
->perm_addr
, bp
->dev
->dev_addr
, ETH_ALEN
);
9478 /* Set the FCoE MAC in MF_SD mode */
9479 if (!CHIP_IS_E1x(bp
) && IS_MF_SD(bp
))
9480 memcpy(fip_mac
, bp
->dev
->dev_addr
, ETH_ALEN
);
9482 /* Disable iSCSI if MAC configuration is
9485 if (!is_valid_ether_addr(iscsi_mac
)) {
9486 bp
->flags
|= NO_ISCSI_FLAG
;
9487 memset(iscsi_mac
, 0, ETH_ALEN
);
9490 /* Disable FCoE if MAC configuration is
9493 if (!is_valid_ether_addr(fip_mac
)) {
9494 bp
->flags
|= NO_FCOE_FLAG
;
9495 memset(bp
->fip_mac
, 0, ETH_ALEN
);
9499 if (!bnx2x_is_valid_ether_addr(bp
, bp
->dev
->dev_addr
))
9500 dev_err(&bp
->pdev
->dev
,
9501 "bad Ethernet MAC address configuration: "
9502 "%pM, change it manually before bringing up "
9503 "the appropriate network interface\n",
9507 static int __devinit
bnx2x_get_hwinfo(struct bnx2x
*bp
)
9509 int /*abs*/func
= BP_ABS_FUNC(bp
);
9514 bnx2x_get_common_hwinfo(bp
);
9517 * initialize IGU parameters
9519 if (CHIP_IS_E1x(bp
)) {
9520 bp
->common
.int_block
= INT_BLOCK_HC
;
9522 bp
->igu_dsb_id
= DEF_SB_IGU_ID
;
9523 bp
->igu_base_sb
= 0;
9525 bp
->common
.int_block
= INT_BLOCK_IGU
;
9527 /* do not allow device reset during IGU info preocessing */
9528 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RESET
);
9530 val
= REG_RD(bp
, IGU_REG_BLOCK_CONFIGURATION
);
9532 if (val
& IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN
) {
9535 BNX2X_DEV_INFO("FORCING Normal Mode\n");
9537 val
&= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN
);
9538 REG_WR(bp
, IGU_REG_BLOCK_CONFIGURATION
, val
);
9539 REG_WR(bp
, IGU_REG_RESET_MEMORIES
, 0x7f);
9541 while (tout
&& REG_RD(bp
, IGU_REG_RESET_MEMORIES
)) {
9543 usleep_range(1000, 1000);
9546 if (REG_RD(bp
, IGU_REG_RESET_MEMORIES
)) {
9547 dev_err(&bp
->pdev
->dev
,
9548 "FORCING Normal Mode failed!!!\n");
9553 if (val
& IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN
) {
9554 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
9555 bp
->common
.int_block
|= INT_BLOCK_MODE_BW_COMP
;
9557 BNX2X_DEV_INFO("IGU Normal Mode\n");
9559 bnx2x_get_igu_cam_info(bp
);
9561 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RESET
);
9565 * set base FW non-default (fast path) status block id, this value is
9566 * used to initialize the fw_sb_id saved on the fp/queue structure to
9567 * determine the id used by the FW.
9569 if (CHIP_IS_E1x(bp
))
9570 bp
->base_fw_ndsb
= BP_PORT(bp
) * FP_SB_MAX_E1x
+ BP_L_ID(bp
);
9572 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
9573 * the same queue are indicated on the same IGU SB). So we prefer
9574 * FW and IGU SBs to be the same value.
9576 bp
->base_fw_ndsb
= bp
->igu_base_sb
;
9578 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
9579 "base_fw_ndsb %d\n", bp
->igu_dsb_id
, bp
->igu_base_sb
,
9580 bp
->igu_sb_cnt
, bp
->base_fw_ndsb
);
9583 * Initialize MF configuration
9590 if (!CHIP_IS_E1(bp
) && !BP_NOMCP(bp
)) {
9591 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
9592 bp
->common
.shmem2_base
, SHMEM2_RD(bp
, size
),
9593 (u32
)offsetof(struct shmem2_region
, mf_cfg_addr
));
9595 if (SHMEM2_HAS(bp
, mf_cfg_addr
))
9596 bp
->common
.mf_cfg_base
= SHMEM2_RD(bp
, mf_cfg_addr
);
9598 bp
->common
.mf_cfg_base
= bp
->common
.shmem_base
+
9599 offsetof(struct shmem_region
, func_mb
) +
9600 E1H_FUNC_MAX
* sizeof(struct drv_func_mb
);
9602 * get mf configuration:
9603 * 1. existence of MF configuration
9604 * 2. MAC address must be legal (check only upper bytes)
9605 * for Switch-Independent mode;
9606 * OVLAN must be legal for Switch-Dependent mode
9607 * 3. SF_MODE configures specific MF mode
9609 if (bp
->common
.mf_cfg_base
!= SHMEM_MF_CFG_ADDR_NONE
) {
9610 /* get mf configuration */
9612 dev_info
.shared_feature_config
.config
);
9613 val
&= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK
;
9616 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT
:
9617 val
= MF_CFG_RD(bp
, func_mf_config
[func
].
9619 /* check for legal mac (upper bytes)*/
9620 if (val
!= 0xffff) {
9621 bp
->mf_mode
= MULTI_FUNCTION_SI
;
9622 bp
->mf_config
[vn
] = MF_CFG_RD(bp
,
9623 func_mf_config
[func
].config
);
9625 BNX2X_DEV_INFO("illegal MAC address "
9628 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED
:
9629 /* get OV configuration */
9631 func_mf_config
[FUNC_0
].e1hov_tag
);
9632 val
&= FUNC_MF_CFG_E1HOV_TAG_MASK
;
9634 if (val
!= FUNC_MF_CFG_E1HOV_TAG_DEFAULT
) {
9635 bp
->mf_mode
= MULTI_FUNCTION_SD
;
9636 bp
->mf_config
[vn
] = MF_CFG_RD(bp
,
9637 func_mf_config
[func
].config
);
9639 BNX2X_DEV_INFO("illegal OV for SD\n");
9642 /* Unknown configuration: reset mf_config */
9643 bp
->mf_config
[vn
] = 0;
9644 BNX2X_DEV_INFO("unkown MF mode 0x%x\n", val
);
9648 BNX2X_DEV_INFO("%s function mode\n",
9649 IS_MF(bp
) ? "multi" : "single");
9651 switch (bp
->mf_mode
) {
9652 case MULTI_FUNCTION_SD
:
9653 val
= MF_CFG_RD(bp
, func_mf_config
[func
].e1hov_tag
) &
9654 FUNC_MF_CFG_E1HOV_TAG_MASK
;
9655 if (val
!= FUNC_MF_CFG_E1HOV_TAG_DEFAULT
) {
9657 bp
->path_has_ovlan
= true;
9659 BNX2X_DEV_INFO("MF OV for func %d is %d "
9660 "(0x%04x)\n", func
, bp
->mf_ov
,
9663 dev_err(&bp
->pdev
->dev
,
9664 "No valid MF OV for func %d, "
9665 "aborting\n", func
);
9669 case MULTI_FUNCTION_SI
:
9670 BNX2X_DEV_INFO("func %d is in MF "
9671 "switch-independent mode\n", func
);
9675 dev_err(&bp
->pdev
->dev
,
9676 "VN %d is in a single function mode, "
9683 /* check if other port on the path needs ovlan:
9684 * Since MF configuration is shared between ports
9685 * Possible mixed modes are only
9686 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
9688 if (CHIP_MODE_IS_4_PORT(bp
) &&
9689 !bp
->path_has_ovlan
&&
9691 bp
->common
.mf_cfg_base
!= SHMEM_MF_CFG_ADDR_NONE
) {
9692 u8 other_port
= !BP_PORT(bp
);
9693 u8 other_func
= BP_PATH(bp
) + 2*other_port
;
9695 func_mf_config
[other_func
].e1hov_tag
);
9696 if (val
!= FUNC_MF_CFG_E1HOV_TAG_DEFAULT
)
9697 bp
->path_has_ovlan
= true;
9701 /* adjust igu_sb_cnt to MF for E1x */
9702 if (CHIP_IS_E1x(bp
) && IS_MF(bp
))
9703 bp
->igu_sb_cnt
/= E1HVN_MAX
;
9706 bnx2x_get_port_hwinfo(bp
);
9708 /* Get MAC addresses */
9709 bnx2x_get_mac_hwinfo(bp
);
9712 bnx2x_get_cnic_info(bp
);
9715 /* Get current FW pulse sequence */
9716 if (!BP_NOMCP(bp
)) {
9717 int mb_idx
= BP_FW_MB_IDX(bp
);
9719 bp
->fw_drv_pulse_wr_seq
=
9720 (SHMEM_RD(bp
, func_mb
[mb_idx
].drv_pulse_mb
) &
9721 DRV_PULSE_SEQ_MASK
);
9722 BNX2X_DEV_INFO("drv_pulse 0x%x\n", bp
->fw_drv_pulse_wr_seq
);
9728 static void __devinit
bnx2x_read_fwinfo(struct bnx2x
*bp
)
9730 int cnt
, i
, block_end
, rodi
;
9731 char vpd_data
[BNX2X_VPD_LEN
+1];
9732 char str_id_reg
[VENDOR_ID_LEN
+1];
9733 char str_id_cap
[VENDOR_ID_LEN
+1];
9736 cnt
= pci_read_vpd(bp
->pdev
, 0, BNX2X_VPD_LEN
, vpd_data
);
9737 memset(bp
->fw_ver
, 0, sizeof(bp
->fw_ver
));
9739 if (cnt
< BNX2X_VPD_LEN
)
9742 i
= pci_vpd_find_tag(vpd_data
, 0, BNX2X_VPD_LEN
,
9743 PCI_VPD_LRDT_RO_DATA
);
9748 block_end
= i
+ PCI_VPD_LRDT_TAG_SIZE
+
9749 pci_vpd_lrdt_size(&vpd_data
[i
]);
9751 i
+= PCI_VPD_LRDT_TAG_SIZE
;
9753 if (block_end
> BNX2X_VPD_LEN
)
9756 rodi
= pci_vpd_find_info_keyword(vpd_data
, i
, block_end
,
9757 PCI_VPD_RO_KEYWORD_MFR_ID
);
9761 len
= pci_vpd_info_field_size(&vpd_data
[rodi
]);
9763 if (len
!= VENDOR_ID_LEN
)
9766 rodi
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
9768 /* vendor specific info */
9769 snprintf(str_id_reg
, VENDOR_ID_LEN
+ 1, "%04x", PCI_VENDOR_ID_DELL
);
9770 snprintf(str_id_cap
, VENDOR_ID_LEN
+ 1, "%04X", PCI_VENDOR_ID_DELL
);
9771 if (!strncmp(str_id_reg
, &vpd_data
[rodi
], VENDOR_ID_LEN
) ||
9772 !strncmp(str_id_cap
, &vpd_data
[rodi
], VENDOR_ID_LEN
)) {
9774 rodi
= pci_vpd_find_info_keyword(vpd_data
, i
, block_end
,
9775 PCI_VPD_RO_KEYWORD_VENDOR0
);
9777 len
= pci_vpd_info_field_size(&vpd_data
[rodi
]);
9779 rodi
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
9781 if (len
< 32 && (len
+ rodi
) <= BNX2X_VPD_LEN
) {
9782 memcpy(bp
->fw_ver
, &vpd_data
[rodi
], len
);
9783 bp
->fw_ver
[len
] = ' ';
9792 static void __devinit
bnx2x_set_modes_bitmap(struct bnx2x
*bp
)
9796 if (CHIP_REV_IS_FPGA(bp
))
9797 SET_FLAGS(flags
, MODE_FPGA
);
9798 else if (CHIP_REV_IS_EMUL(bp
))
9799 SET_FLAGS(flags
, MODE_EMUL
);
9801 SET_FLAGS(flags
, MODE_ASIC
);
9803 if (CHIP_MODE_IS_4_PORT(bp
))
9804 SET_FLAGS(flags
, MODE_PORT4
);
9806 SET_FLAGS(flags
, MODE_PORT2
);
9809 SET_FLAGS(flags
, MODE_E2
);
9810 else if (CHIP_IS_E3(bp
)) {
9811 SET_FLAGS(flags
, MODE_E3
);
9812 if (CHIP_REV(bp
) == CHIP_REV_Ax
)
9813 SET_FLAGS(flags
, MODE_E3_A0
);
9814 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
9815 SET_FLAGS(flags
, MODE_E3_B0
| MODE_COS3
);
9819 SET_FLAGS(flags
, MODE_MF
);
9820 switch (bp
->mf_mode
) {
9821 case MULTI_FUNCTION_SD
:
9822 SET_FLAGS(flags
, MODE_MF_SD
);
9824 case MULTI_FUNCTION_SI
:
9825 SET_FLAGS(flags
, MODE_MF_SI
);
9829 SET_FLAGS(flags
, MODE_SF
);
9831 #if defined(__LITTLE_ENDIAN)
9832 SET_FLAGS(flags
, MODE_LITTLE_ENDIAN
);
9833 #else /*(__BIG_ENDIAN)*/
9834 SET_FLAGS(flags
, MODE_BIG_ENDIAN
);
9836 INIT_MODE_FLAGS(bp
) = flags
;
9839 static int __devinit
bnx2x_init_bp(struct bnx2x
*bp
)
9845 mutex_init(&bp
->port
.phy_mutex
);
9846 mutex_init(&bp
->fw_mb_mutex
);
9847 spin_lock_init(&bp
->stats_lock
);
9849 mutex_init(&bp
->cnic_mutex
);
9852 INIT_DELAYED_WORK(&bp
->sp_task
, bnx2x_sp_task
);
9853 INIT_DELAYED_WORK(&bp
->sp_rtnl_task
, bnx2x_sp_rtnl_task
);
9854 INIT_DELAYED_WORK(&bp
->period_task
, bnx2x_period_task
);
9855 rc
= bnx2x_get_hwinfo(bp
);
9859 bnx2x_set_modes_bitmap(bp
);
9861 rc
= bnx2x_alloc_mem_bp(bp
);
9865 bnx2x_read_fwinfo(bp
);
9869 /* need to reset chip if undi was active */
9871 bnx2x_undi_unload(bp
);
9873 /* init fw_seq after undi_unload! */
9874 if (!BP_NOMCP(bp
)) {
9876 (SHMEM_RD(bp
, func_mb
[BP_FW_MB_IDX(bp
)].drv_mb_header
) &
9877 DRV_MSG_SEQ_NUMBER_MASK
);
9878 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp
->fw_seq
);
9881 if (CHIP_REV_IS_FPGA(bp
))
9882 dev_err(&bp
->pdev
->dev
, "FPGA detected\n");
9884 if (BP_NOMCP(bp
) && (func
== 0))
9885 dev_err(&bp
->pdev
->dev
, "MCP disabled, "
9886 "must load devices in order!\n");
9888 bp
->multi_mode
= multi_mode
;
9890 bp
->disable_tpa
= disable_tpa
;
9893 bp
->disable_tpa
|= IS_MF_ISCSI_SD(bp
);
9897 if (bp
->disable_tpa
) {
9898 bp
->flags
&= ~TPA_ENABLE_FLAG
;
9899 bp
->dev
->features
&= ~NETIF_F_LRO
;
9901 bp
->flags
|= TPA_ENABLE_FLAG
;
9902 bp
->dev
->features
|= NETIF_F_LRO
;
9906 bp
->dropless_fc
= 0;
9908 bp
->dropless_fc
= dropless_fc
;
9912 bp
->tx_ring_size
= MAX_TX_AVAIL
;
9914 /* make sure that the numbers are in the right granularity */
9915 bp
->tx_ticks
= (50 / BNX2X_BTR
) * BNX2X_BTR
;
9916 bp
->rx_ticks
= (25 / BNX2X_BTR
) * BNX2X_BTR
;
9918 timer_interval
= (CHIP_REV_IS_SLOW(bp
) ? 5*HZ
: HZ
);
9919 bp
->current_interval
= (poll
? poll
: timer_interval
);
9921 init_timer(&bp
->timer
);
9922 bp
->timer
.expires
= jiffies
+ bp
->current_interval
;
9923 bp
->timer
.data
= (unsigned long) bp
;
9924 bp
->timer
.function
= bnx2x_timer
;
9926 bnx2x_dcbx_set_state(bp
, true, BNX2X_DCBX_ENABLED_ON_NEG_ON
);
9927 bnx2x_dcbx_init_params(bp
);
9930 if (CHIP_IS_E1x(bp
))
9931 bp
->cnic_base_cl_id
= FP_SB_MAX_E1x
;
9933 bp
->cnic_base_cl_id
= FP_SB_MAX_E2
;
9936 /* multiple tx priority */
9937 if (CHIP_IS_E1x(bp
))
9938 bp
->max_cos
= BNX2X_MULTI_TX_COS_E1X
;
9939 if (CHIP_IS_E2(bp
) || CHIP_IS_E3A0(bp
))
9940 bp
->max_cos
= BNX2X_MULTI_TX_COS_E2_E3A0
;
9941 if (CHIP_IS_E3B0(bp
))
9942 bp
->max_cos
= BNX2X_MULTI_TX_COS_E3B0
;
9948 /****************************************************************************
9949 * General service functions
9950 ****************************************************************************/
9953 * net_device service functions
9956 /* called with rtnl_lock */
9957 static int bnx2x_open(struct net_device
*dev
)
9959 struct bnx2x
*bp
= netdev_priv(dev
);
9960 bool global
= false;
9961 int other_engine
= BP_PATH(bp
) ? 0 : 1;
9962 u32 other_load_counter
, load_counter
;
9964 netif_carrier_off(dev
);
9966 bnx2x_set_power_state(bp
, PCI_D0
);
9968 other_load_counter
= bnx2x_get_load_cnt(bp
, other_engine
);
9969 load_counter
= bnx2x_get_load_cnt(bp
, BP_PATH(bp
));
9972 * If parity had happen during the unload, then attentions
9973 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
9974 * want the first function loaded on the current engine to
9975 * complete the recovery.
9977 if (!bnx2x_reset_is_done(bp
, BP_PATH(bp
)) ||
9978 bnx2x_chk_parity_attn(bp
, &global
, true))
9981 * If there are attentions and they are in a global
9982 * blocks, set the GLOBAL_RESET bit regardless whether
9983 * it will be this function that will complete the
9987 bnx2x_set_reset_global(bp
);
9990 * Only the first function on the current engine should
9991 * try to recover in open. In case of attentions in
9992 * global blocks only the first in the chip should try
9995 if ((!load_counter
&&
9996 (!global
|| !other_load_counter
)) &&
9997 bnx2x_trylock_leader_lock(bp
) &&
9998 !bnx2x_leader_reset(bp
)) {
9999 netdev_info(bp
->dev
, "Recovered in open\n");
10003 /* recovery has failed... */
10004 bnx2x_set_power_state(bp
, PCI_D3hot
);
10005 bp
->recovery_state
= BNX2X_RECOVERY_FAILED
;
10007 netdev_err(bp
->dev
, "Recovery flow hasn't been properly"
10008 " completed yet. Try again later. If u still see this"
10009 " message after a few retries then power cycle is"
10015 bp
->recovery_state
= BNX2X_RECOVERY_DONE
;
10016 return bnx2x_nic_load(bp
, LOAD_OPEN
);
10019 /* called with rtnl_lock */
10020 int bnx2x_close(struct net_device
*dev
)
10022 struct bnx2x
*bp
= netdev_priv(dev
);
10024 /* Unload the driver, release IRQs */
10025 bnx2x_nic_unload(bp
, UNLOAD_CLOSE
);
10028 bnx2x_set_power_state(bp
, PCI_D3hot
);
10033 static inline int bnx2x_init_mcast_macs_list(struct bnx2x
*bp
,
10034 struct bnx2x_mcast_ramrod_params
*p
)
10036 int mc_count
= netdev_mc_count(bp
->dev
);
10037 struct bnx2x_mcast_list_elem
*mc_mac
=
10038 kzalloc(sizeof(*mc_mac
) * mc_count
, GFP_ATOMIC
);
10039 struct netdev_hw_addr
*ha
;
10044 INIT_LIST_HEAD(&p
->mcast_list
);
10046 netdev_for_each_mc_addr(ha
, bp
->dev
) {
10047 mc_mac
->mac
= bnx2x_mc_addr(ha
);
10048 list_add_tail(&mc_mac
->link
, &p
->mcast_list
);
10052 p
->mcast_list_len
= mc_count
;
10057 static inline void bnx2x_free_mcast_macs_list(
10058 struct bnx2x_mcast_ramrod_params
*p
)
10060 struct bnx2x_mcast_list_elem
*mc_mac
=
10061 list_first_entry(&p
->mcast_list
, struct bnx2x_mcast_list_elem
,
10069 * bnx2x_set_uc_list - configure a new unicast MACs list.
10071 * @bp: driver handle
10073 * We will use zero (0) as a MAC type for these MACs.
10075 static inline int bnx2x_set_uc_list(struct bnx2x
*bp
)
10078 struct net_device
*dev
= bp
->dev
;
10079 struct netdev_hw_addr
*ha
;
10080 struct bnx2x_vlan_mac_obj
*mac_obj
= &bp
->fp
->mac_obj
;
10081 unsigned long ramrod_flags
= 0;
10083 /* First schedule a cleanup up of old configuration */
10084 rc
= bnx2x_del_all_macs(bp
, mac_obj
, BNX2X_UC_LIST_MAC
, false);
10086 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc
);
10090 netdev_for_each_uc_addr(ha
, dev
) {
10091 rc
= bnx2x_set_mac_one(bp
, bnx2x_uc_addr(ha
), mac_obj
, true,
10092 BNX2X_UC_LIST_MAC
, &ramrod_flags
);
10094 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
10100 /* Execute the pending commands */
10101 __set_bit(RAMROD_CONT
, &ramrod_flags
);
10102 return bnx2x_set_mac_one(bp
, NULL
, mac_obj
, false /* don't care */,
10103 BNX2X_UC_LIST_MAC
, &ramrod_flags
);
10106 static inline int bnx2x_set_mc_list(struct bnx2x
*bp
)
10108 struct net_device
*dev
= bp
->dev
;
10109 struct bnx2x_mcast_ramrod_params rparam
= {0};
10112 rparam
.mcast_obj
= &bp
->mcast_obj
;
10114 /* first, clear all configured multicast MACs */
10115 rc
= bnx2x_config_mcast(bp
, &rparam
, BNX2X_MCAST_CMD_DEL
);
10117 BNX2X_ERR("Failed to clear multicast "
10118 "configuration: %d\n", rc
);
10122 /* then, configure a new MACs list */
10123 if (netdev_mc_count(dev
)) {
10124 rc
= bnx2x_init_mcast_macs_list(bp
, &rparam
);
10126 BNX2X_ERR("Failed to create multicast MACs "
10131 /* Now add the new MACs */
10132 rc
= bnx2x_config_mcast(bp
, &rparam
,
10133 BNX2X_MCAST_CMD_ADD
);
10135 BNX2X_ERR("Failed to set a new multicast "
10136 "configuration: %d\n", rc
);
10138 bnx2x_free_mcast_macs_list(&rparam
);
10145 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
10146 void bnx2x_set_rx_mode(struct net_device
*dev
)
10148 struct bnx2x
*bp
= netdev_priv(dev
);
10149 u32 rx_mode
= BNX2X_RX_MODE_NORMAL
;
10151 if (bp
->state
!= BNX2X_STATE_OPEN
) {
10152 DP(NETIF_MSG_IFUP
, "state is %x, returning\n", bp
->state
);
10156 DP(NETIF_MSG_IFUP
, "dev->flags = %x\n", bp
->dev
->flags
);
10158 if (dev
->flags
& IFF_PROMISC
)
10159 rx_mode
= BNX2X_RX_MODE_PROMISC
;
10160 else if ((dev
->flags
& IFF_ALLMULTI
) ||
10161 ((netdev_mc_count(dev
) > BNX2X_MAX_MULTICAST
) &&
10163 rx_mode
= BNX2X_RX_MODE_ALLMULTI
;
10165 /* some multicasts */
10166 if (bnx2x_set_mc_list(bp
) < 0)
10167 rx_mode
= BNX2X_RX_MODE_ALLMULTI
;
10169 if (bnx2x_set_uc_list(bp
) < 0)
10170 rx_mode
= BNX2X_RX_MODE_PROMISC
;
10173 bp
->rx_mode
= rx_mode
;
10175 /* handle ISCSI SD mode */
10176 if (IS_MF_ISCSI_SD(bp
))
10177 bp
->rx_mode
= BNX2X_RX_MODE_NONE
;
10180 /* Schedule the rx_mode command */
10181 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING
, &bp
->sp_state
)) {
10182 set_bit(BNX2X_FILTER_RX_MODE_SCHED
, &bp
->sp_state
);
10186 bnx2x_set_storm_rx_mode(bp
);
10189 /* called with rtnl_lock */
10190 static int bnx2x_mdio_read(struct net_device
*netdev
, int prtad
,
10191 int devad
, u16 addr
)
10193 struct bnx2x
*bp
= netdev_priv(netdev
);
10197 DP(NETIF_MSG_LINK
, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
10198 prtad
, devad
, addr
);
10200 /* The HW expects different devad if CL22 is used */
10201 devad
= (devad
== MDIO_DEVAD_NONE
) ? DEFAULT_PHY_DEV_ADDR
: devad
;
10203 bnx2x_acquire_phy_lock(bp
);
10204 rc
= bnx2x_phy_read(&bp
->link_params
, prtad
, devad
, addr
, &value
);
10205 bnx2x_release_phy_lock(bp
);
10206 DP(NETIF_MSG_LINK
, "mdio_read_val 0x%x rc = 0x%x\n", value
, rc
);
10213 /* called with rtnl_lock */
10214 static int bnx2x_mdio_write(struct net_device
*netdev
, int prtad
, int devad
,
10215 u16 addr
, u16 value
)
10217 struct bnx2x
*bp
= netdev_priv(netdev
);
10220 DP(NETIF_MSG_LINK
, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x,"
10221 " value 0x%x\n", prtad
, devad
, addr
, value
);
10223 /* The HW expects different devad if CL22 is used */
10224 devad
= (devad
== MDIO_DEVAD_NONE
) ? DEFAULT_PHY_DEV_ADDR
: devad
;
10226 bnx2x_acquire_phy_lock(bp
);
10227 rc
= bnx2x_phy_write(&bp
->link_params
, prtad
, devad
, addr
, value
);
10228 bnx2x_release_phy_lock(bp
);
10232 /* called with rtnl_lock */
10233 static int bnx2x_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
10235 struct bnx2x
*bp
= netdev_priv(dev
);
10236 struct mii_ioctl_data
*mdio
= if_mii(ifr
);
10238 DP(NETIF_MSG_LINK
, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
10239 mdio
->phy_id
, mdio
->reg_num
, mdio
->val_in
);
10241 if (!netif_running(dev
))
10244 return mdio_mii_ioctl(&bp
->mdio
, mdio
, cmd
);
10247 #ifdef CONFIG_NET_POLL_CONTROLLER
10248 static void poll_bnx2x(struct net_device
*dev
)
10250 struct bnx2x
*bp
= netdev_priv(dev
);
10252 disable_irq(bp
->pdev
->irq
);
10253 bnx2x_interrupt(bp
->pdev
->irq
, dev
);
10254 enable_irq(bp
->pdev
->irq
);
10258 static int bnx2x_validate_addr(struct net_device
*dev
)
10260 struct bnx2x
*bp
= netdev_priv(dev
);
10262 if (!bnx2x_is_valid_ether_addr(bp
, dev
->dev_addr
))
10263 return -EADDRNOTAVAIL
;
10267 static const struct net_device_ops bnx2x_netdev_ops
= {
10268 .ndo_open
= bnx2x_open
,
10269 .ndo_stop
= bnx2x_close
,
10270 .ndo_start_xmit
= bnx2x_start_xmit
,
10271 .ndo_select_queue
= bnx2x_select_queue
,
10272 .ndo_set_rx_mode
= bnx2x_set_rx_mode
,
10273 .ndo_set_mac_address
= bnx2x_change_mac_addr
,
10274 .ndo_validate_addr
= bnx2x_validate_addr
,
10275 .ndo_do_ioctl
= bnx2x_ioctl
,
10276 .ndo_change_mtu
= bnx2x_change_mtu
,
10277 .ndo_fix_features
= bnx2x_fix_features
,
10278 .ndo_set_features
= bnx2x_set_features
,
10279 .ndo_tx_timeout
= bnx2x_tx_timeout
,
10280 #ifdef CONFIG_NET_POLL_CONTROLLER
10281 .ndo_poll_controller
= poll_bnx2x
,
10283 .ndo_setup_tc
= bnx2x_setup_tc
,
10285 #if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC)
10286 .ndo_fcoe_get_wwn
= bnx2x_fcoe_get_wwn
,
10290 static inline int bnx2x_set_coherency_mask(struct bnx2x
*bp
)
10292 struct device
*dev
= &bp
->pdev
->dev
;
10294 if (dma_set_mask(dev
, DMA_BIT_MASK(64)) == 0) {
10295 bp
->flags
|= USING_DAC_FLAG
;
10296 if (dma_set_coherent_mask(dev
, DMA_BIT_MASK(64)) != 0) {
10297 dev_err(dev
, "dma_set_coherent_mask failed, "
10301 } else if (dma_set_mask(dev
, DMA_BIT_MASK(32)) != 0) {
10302 dev_err(dev
, "System does not support DMA, aborting\n");
10309 static int __devinit
bnx2x_init_dev(struct pci_dev
*pdev
,
10310 struct net_device
*dev
,
10311 unsigned long board_type
)
10316 SET_NETDEV_DEV(dev
, &pdev
->dev
);
10317 bp
= netdev_priv(dev
);
10322 bp
->pf_num
= PCI_FUNC(pdev
->devfn
);
10324 rc
= pci_enable_device(pdev
);
10326 dev_err(&bp
->pdev
->dev
,
10327 "Cannot enable PCI device, aborting\n");
10331 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
10332 dev_err(&bp
->pdev
->dev
,
10333 "Cannot find PCI device base address, aborting\n");
10335 goto err_out_disable
;
10338 if (!(pci_resource_flags(pdev
, 2) & IORESOURCE_MEM
)) {
10339 dev_err(&bp
->pdev
->dev
, "Cannot find second PCI device"
10340 " base address, aborting\n");
10342 goto err_out_disable
;
10345 if (atomic_read(&pdev
->enable_cnt
) == 1) {
10346 rc
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
10348 dev_err(&bp
->pdev
->dev
,
10349 "Cannot obtain PCI resources, aborting\n");
10350 goto err_out_disable
;
10353 pci_set_master(pdev
);
10354 pci_save_state(pdev
);
10357 bp
->pm_cap
= pci_find_capability(pdev
, PCI_CAP_ID_PM
);
10358 if (bp
->pm_cap
== 0) {
10359 dev_err(&bp
->pdev
->dev
,
10360 "Cannot find power management capability, aborting\n");
10362 goto err_out_release
;
10365 if (!pci_is_pcie(pdev
)) {
10366 dev_err(&bp
->pdev
->dev
, "Not PCI Express, aborting\n");
10368 goto err_out_release
;
10371 rc
= bnx2x_set_coherency_mask(bp
);
10373 goto err_out_release
;
10375 dev
->mem_start
= pci_resource_start(pdev
, 0);
10376 dev
->base_addr
= dev
->mem_start
;
10377 dev
->mem_end
= pci_resource_end(pdev
, 0);
10379 dev
->irq
= pdev
->irq
;
10381 bp
->regview
= pci_ioremap_bar(pdev
, 0);
10382 if (!bp
->regview
) {
10383 dev_err(&bp
->pdev
->dev
,
10384 "Cannot map register space, aborting\n");
10386 goto err_out_release
;
10389 bnx2x_set_power_state(bp
, PCI_D0
);
10391 /* clean indirect addresses */
10392 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_ADDRESS
,
10393 PCICFG_VENDOR_ID_OFFSET
);
10395 * Clean the following indirect addresses for all functions since it
10396 * is not used by the driver.
10398 REG_WR(bp
, PXP2_REG_PGL_ADDR_88_F0
, 0);
10399 REG_WR(bp
, PXP2_REG_PGL_ADDR_8C_F0
, 0);
10400 REG_WR(bp
, PXP2_REG_PGL_ADDR_90_F0
, 0);
10401 REG_WR(bp
, PXP2_REG_PGL_ADDR_94_F0
, 0);
10403 if (CHIP_IS_E1x(bp
)) {
10404 REG_WR(bp
, PXP2_REG_PGL_ADDR_88_F1
, 0);
10405 REG_WR(bp
, PXP2_REG_PGL_ADDR_8C_F1
, 0);
10406 REG_WR(bp
, PXP2_REG_PGL_ADDR_90_F1
, 0);
10407 REG_WR(bp
, PXP2_REG_PGL_ADDR_94_F1
, 0);
10411 * Enable internal target-read (in case we are probed after PF FLR).
10412 * Must be done prior to any BAR read access. Only for 57712 and up
10414 if (board_type
!= BCM57710
&&
10415 board_type
!= BCM57711
&&
10416 board_type
!= BCM57711E
)
10417 REG_WR(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ
, 1);
10419 /* Reset the load counter */
10420 bnx2x_clear_load_cnt(bp
);
10422 dev
->watchdog_timeo
= TX_TIMEOUT
;
10424 dev
->netdev_ops
= &bnx2x_netdev_ops
;
10425 bnx2x_set_ethtool_ops(dev
);
10427 dev
->priv_flags
|= IFF_UNICAST_FLT
;
10429 dev
->hw_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
|
10430 NETIF_F_TSO
| NETIF_F_TSO_ECN
| NETIF_F_TSO6
| NETIF_F_LRO
|
10431 NETIF_F_RXCSUM
| NETIF_F_RXHASH
| NETIF_F_HW_VLAN_TX
;
10433 dev
->vlan_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
|
10434 NETIF_F_TSO
| NETIF_F_TSO_ECN
| NETIF_F_TSO6
| NETIF_F_HIGHDMA
;
10436 dev
->features
|= dev
->hw_features
| NETIF_F_HW_VLAN_RX
;
10437 if (bp
->flags
& USING_DAC_FLAG
)
10438 dev
->features
|= NETIF_F_HIGHDMA
;
10440 /* Add Loopback capability to the device */
10441 dev
->hw_features
|= NETIF_F_LOOPBACK
;
10444 dev
->dcbnl_ops
= &bnx2x_dcbnl_ops
;
10447 /* get_port_hwinfo() will set prtad and mmds properly */
10448 bp
->mdio
.prtad
= MDIO_PRTAD_NONE
;
10450 bp
->mdio
.mode_support
= MDIO_SUPPORTS_C45
| MDIO_EMULATE_C22
;
10451 bp
->mdio
.dev
= dev
;
10452 bp
->mdio
.mdio_read
= bnx2x_mdio_read
;
10453 bp
->mdio
.mdio_write
= bnx2x_mdio_write
;
10458 if (atomic_read(&pdev
->enable_cnt
) == 1)
10459 pci_release_regions(pdev
);
10462 pci_disable_device(pdev
);
10463 pci_set_drvdata(pdev
, NULL
);
10469 static void __devinit
bnx2x_get_pcie_width_speed(struct bnx2x
*bp
,
10470 int *width
, int *speed
)
10472 u32 val
= REG_RD(bp
, PCICFG_OFFSET
+ PCICFG_LINK_CONTROL
);
10474 *width
= (val
& PCICFG_LINK_WIDTH
) >> PCICFG_LINK_WIDTH_SHIFT
;
10476 /* return value of 1=2.5GHz 2=5GHz */
10477 *speed
= (val
& PCICFG_LINK_SPEED
) >> PCICFG_LINK_SPEED_SHIFT
;
10480 static int bnx2x_check_firmware(struct bnx2x
*bp
)
10482 const struct firmware
*firmware
= bp
->firmware
;
10483 struct bnx2x_fw_file_hdr
*fw_hdr
;
10484 struct bnx2x_fw_file_section
*sections
;
10485 u32 offset
, len
, num_ops
;
10490 if (firmware
->size
< sizeof(struct bnx2x_fw_file_hdr
))
10493 fw_hdr
= (struct bnx2x_fw_file_hdr
*)firmware
->data
;
10494 sections
= (struct bnx2x_fw_file_section
*)fw_hdr
;
10496 /* Make sure none of the offsets and sizes make us read beyond
10497 * the end of the firmware data */
10498 for (i
= 0; i
< sizeof(*fw_hdr
) / sizeof(*sections
); i
++) {
10499 offset
= be32_to_cpu(sections
[i
].offset
);
10500 len
= be32_to_cpu(sections
[i
].len
);
10501 if (offset
+ len
> firmware
->size
) {
10502 dev_err(&bp
->pdev
->dev
,
10503 "Section %d length is out of bounds\n", i
);
10508 /* Likewise for the init_ops offsets */
10509 offset
= be32_to_cpu(fw_hdr
->init_ops_offsets
.offset
);
10510 ops_offsets
= (u16
*)(firmware
->data
+ offset
);
10511 num_ops
= be32_to_cpu(fw_hdr
->init_ops
.len
) / sizeof(struct raw_op
);
10513 for (i
= 0; i
< be32_to_cpu(fw_hdr
->init_ops_offsets
.len
) / 2; i
++) {
10514 if (be16_to_cpu(ops_offsets
[i
]) > num_ops
) {
10515 dev_err(&bp
->pdev
->dev
,
10516 "Section offset %d is out of bounds\n", i
);
10521 /* Check FW version */
10522 offset
= be32_to_cpu(fw_hdr
->fw_version
.offset
);
10523 fw_ver
= firmware
->data
+ offset
;
10524 if ((fw_ver
[0] != BCM_5710_FW_MAJOR_VERSION
) ||
10525 (fw_ver
[1] != BCM_5710_FW_MINOR_VERSION
) ||
10526 (fw_ver
[2] != BCM_5710_FW_REVISION_VERSION
) ||
10527 (fw_ver
[3] != BCM_5710_FW_ENGINEERING_VERSION
)) {
10528 dev_err(&bp
->pdev
->dev
,
10529 "Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
10530 fw_ver
[0], fw_ver
[1], fw_ver
[2],
10531 fw_ver
[3], BCM_5710_FW_MAJOR_VERSION
,
10532 BCM_5710_FW_MINOR_VERSION
,
10533 BCM_5710_FW_REVISION_VERSION
,
10534 BCM_5710_FW_ENGINEERING_VERSION
);
10541 static inline void be32_to_cpu_n(const u8
*_source
, u8
*_target
, u32 n
)
10543 const __be32
*source
= (const __be32
*)_source
;
10544 u32
*target
= (u32
*)_target
;
10547 for (i
= 0; i
< n
/4; i
++)
10548 target
[i
] = be32_to_cpu(source
[i
]);
10552 Ops array is stored in the following format:
10553 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
10555 static inline void bnx2x_prep_ops(const u8
*_source
, u8
*_target
, u32 n
)
10557 const __be32
*source
= (const __be32
*)_source
;
10558 struct raw_op
*target
= (struct raw_op
*)_target
;
10561 for (i
= 0, j
= 0; i
< n
/8; i
++, j
+= 2) {
10562 tmp
= be32_to_cpu(source
[j
]);
10563 target
[i
].op
= (tmp
>> 24) & 0xff;
10564 target
[i
].offset
= tmp
& 0xffffff;
10565 target
[i
].raw_data
= be32_to_cpu(source
[j
+ 1]);
10570 * IRO array is stored in the following format:
10571 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
10573 static inline void bnx2x_prep_iro(const u8
*_source
, u8
*_target
, u32 n
)
10575 const __be32
*source
= (const __be32
*)_source
;
10576 struct iro
*target
= (struct iro
*)_target
;
10579 for (i
= 0, j
= 0; i
< n
/sizeof(struct iro
); i
++) {
10580 target
[i
].base
= be32_to_cpu(source
[j
]);
10582 tmp
= be32_to_cpu(source
[j
]);
10583 target
[i
].m1
= (tmp
>> 16) & 0xffff;
10584 target
[i
].m2
= tmp
& 0xffff;
10586 tmp
= be32_to_cpu(source
[j
]);
10587 target
[i
].m3
= (tmp
>> 16) & 0xffff;
10588 target
[i
].size
= tmp
& 0xffff;
10593 static inline void be16_to_cpu_n(const u8
*_source
, u8
*_target
, u32 n
)
10595 const __be16
*source
= (const __be16
*)_source
;
10596 u16
*target
= (u16
*)_target
;
10599 for (i
= 0; i
< n
/2; i
++)
10600 target
[i
] = be16_to_cpu(source
[i
]);
10603 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
10605 u32 len = be32_to_cpu(fw_hdr->arr.len); \
10606 bp->arr = kmalloc(len, GFP_KERNEL); \
10608 pr_err("Failed to allocate %d bytes for "#arr"\n", len); \
10611 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
10612 (u8 *)bp->arr, len); \
10615 int bnx2x_init_firmware(struct bnx2x
*bp
)
10617 struct bnx2x_fw_file_hdr
*fw_hdr
;
10621 if (!bp
->firmware
) {
10622 const char *fw_file_name
;
10624 if (CHIP_IS_E1(bp
))
10625 fw_file_name
= FW_FILE_NAME_E1
;
10626 else if (CHIP_IS_E1H(bp
))
10627 fw_file_name
= FW_FILE_NAME_E1H
;
10628 else if (!CHIP_IS_E1x(bp
))
10629 fw_file_name
= FW_FILE_NAME_E2
;
10631 BNX2X_ERR("Unsupported chip revision\n");
10634 BNX2X_DEV_INFO("Loading %s\n", fw_file_name
);
10636 rc
= request_firmware(&bp
->firmware
, fw_file_name
,
10639 BNX2X_ERR("Can't load firmware file %s\n",
10641 goto request_firmware_exit
;
10644 rc
= bnx2x_check_firmware(bp
);
10646 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name
);
10647 goto request_firmware_exit
;
10651 fw_hdr
= (struct bnx2x_fw_file_hdr
*)bp
->firmware
->data
;
10653 /* Initialize the pointers to the init arrays */
10655 BNX2X_ALLOC_AND_SET(init_data
, request_firmware_exit
, be32_to_cpu_n
);
10658 BNX2X_ALLOC_AND_SET(init_ops
, init_ops_alloc_err
, bnx2x_prep_ops
);
10661 BNX2X_ALLOC_AND_SET(init_ops_offsets
, init_offsets_alloc_err
,
10664 /* STORMs firmware */
10665 INIT_TSEM_INT_TABLE_DATA(bp
) = bp
->firmware
->data
+
10666 be32_to_cpu(fw_hdr
->tsem_int_table_data
.offset
);
10667 INIT_TSEM_PRAM_DATA(bp
) = bp
->firmware
->data
+
10668 be32_to_cpu(fw_hdr
->tsem_pram_data
.offset
);
10669 INIT_USEM_INT_TABLE_DATA(bp
) = bp
->firmware
->data
+
10670 be32_to_cpu(fw_hdr
->usem_int_table_data
.offset
);
10671 INIT_USEM_PRAM_DATA(bp
) = bp
->firmware
->data
+
10672 be32_to_cpu(fw_hdr
->usem_pram_data
.offset
);
10673 INIT_XSEM_INT_TABLE_DATA(bp
) = bp
->firmware
->data
+
10674 be32_to_cpu(fw_hdr
->xsem_int_table_data
.offset
);
10675 INIT_XSEM_PRAM_DATA(bp
) = bp
->firmware
->data
+
10676 be32_to_cpu(fw_hdr
->xsem_pram_data
.offset
);
10677 INIT_CSEM_INT_TABLE_DATA(bp
) = bp
->firmware
->data
+
10678 be32_to_cpu(fw_hdr
->csem_int_table_data
.offset
);
10679 INIT_CSEM_PRAM_DATA(bp
) = bp
->firmware
->data
+
10680 be32_to_cpu(fw_hdr
->csem_pram_data
.offset
);
10682 BNX2X_ALLOC_AND_SET(iro_arr
, iro_alloc_err
, bnx2x_prep_iro
);
10687 kfree(bp
->init_ops_offsets
);
10688 init_offsets_alloc_err
:
10689 kfree(bp
->init_ops
);
10690 init_ops_alloc_err
:
10691 kfree(bp
->init_data
);
10692 request_firmware_exit
:
10693 release_firmware(bp
->firmware
);
10698 static void bnx2x_release_firmware(struct bnx2x
*bp
)
10700 kfree(bp
->init_ops_offsets
);
10701 kfree(bp
->init_ops
);
10702 kfree(bp
->init_data
);
10703 release_firmware(bp
->firmware
);
10704 bp
->firmware
= NULL
;
10708 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv
= {
10709 .init_hw_cmn_chip
= bnx2x_init_hw_common_chip
,
10710 .init_hw_cmn
= bnx2x_init_hw_common
,
10711 .init_hw_port
= bnx2x_init_hw_port
,
10712 .init_hw_func
= bnx2x_init_hw_func
,
10714 .reset_hw_cmn
= bnx2x_reset_common
,
10715 .reset_hw_port
= bnx2x_reset_port
,
10716 .reset_hw_func
= bnx2x_reset_func
,
10718 .gunzip_init
= bnx2x_gunzip_init
,
10719 .gunzip_end
= bnx2x_gunzip_end
,
10721 .init_fw
= bnx2x_init_firmware
,
10722 .release_fw
= bnx2x_release_firmware
,
10725 void bnx2x__init_func_obj(struct bnx2x
*bp
)
10727 /* Prepare DMAE related driver resources */
10728 bnx2x_setup_dmae(bp
);
10730 bnx2x_init_func_obj(bp
, &bp
->func_obj
,
10731 bnx2x_sp(bp
, func_rdata
),
10732 bnx2x_sp_mapping(bp
, func_rdata
),
10733 &bnx2x_func_sp_drv
);
10736 /* must be called after sriov-enable */
10737 static inline int bnx2x_set_qm_cid_count(struct bnx2x
*bp
)
10739 int cid_count
= BNX2X_L2_CID_COUNT(bp
);
10742 cid_count
+= CNIC_CID_MAX
;
10744 return roundup(cid_count
, QM_CID_ROUND
);
10748 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
10753 static inline int bnx2x_get_num_non_def_sbs(struct pci_dev
*pdev
)
10758 pos
= pci_find_capability(pdev
, PCI_CAP_ID_MSIX
);
10761 * If MSI-X is not supported - return number of SBs needed to support
10762 * one fast path queue: one FP queue + SB for CNIC
10765 return 1 + CNIC_PRESENT
;
10768 * The value in the PCI configuration space is the index of the last
10769 * entry, namely one less than the actual size of the table, which is
10770 * exactly what we want to return from this function: number of all SBs
10771 * without the default SB.
10773 pci_read_config_word(pdev
, pos
+ PCI_MSI_FLAGS
, &control
);
10774 return control
& PCI_MSIX_FLAGS_QSIZE
;
10777 static int __devinit
bnx2x_init_one(struct pci_dev
*pdev
,
10778 const struct pci_device_id
*ent
)
10780 struct net_device
*dev
= NULL
;
10782 int pcie_width
, pcie_speed
;
10783 int rc
, max_non_def_sbs
;
10784 int rx_count
, tx_count
, rss_count
;
10786 * An estimated maximum supported CoS number according to the chip
10788 * We will try to roughly estimate the maximum number of CoSes this chip
10789 * may support in order to minimize the memory allocated for Tx
10790 * netdev_queue's. This number will be accurately calculated during the
10791 * initialization of bp->max_cos based on the chip versions AND chip
10792 * revision in the bnx2x_init_bp().
10794 u8 max_cos_est
= 0;
10796 switch (ent
->driver_data
) {
10800 max_cos_est
= BNX2X_MULTI_TX_COS_E1X
;
10805 max_cos_est
= BNX2X_MULTI_TX_COS_E2_E3A0
;
10814 max_cos_est
= BNX2X_MULTI_TX_COS_E3B0
;
10818 pr_err("Unknown board_type (%ld), aborting\n",
10823 max_non_def_sbs
= bnx2x_get_num_non_def_sbs(pdev
);
10826 * Do not allow the maximum SB count to grow above 16
10827 * since Special CIDs starts from 16*BNX2X_MULTI_TX_COS=48.
10828 * We will use the FP_SB_MAX_E1x macro for this matter.
10830 max_non_def_sbs
= min_t(int, FP_SB_MAX_E1x
, max_non_def_sbs
);
10832 WARN_ON(!max_non_def_sbs
);
10834 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
10835 rss_count
= max_non_def_sbs
- CNIC_PRESENT
;
10837 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
10838 rx_count
= rss_count
+ FCOE_PRESENT
;
10841 * Maximum number of netdev Tx queues:
10842 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
10844 tx_count
= MAX_TXQS_PER_COS
* max_cos_est
+ FCOE_PRESENT
;
10846 /* dev zeroed in init_etherdev */
10847 dev
= alloc_etherdev_mqs(sizeof(*bp
), tx_count
, rx_count
);
10849 dev_err(&pdev
->dev
, "Cannot allocate net device\n");
10853 bp
= netdev_priv(dev
);
10855 DP(NETIF_MSG_DRV
, "Allocated netdev with %d tx and %d rx queues\n",
10856 tx_count
, rx_count
);
10858 bp
->igu_sb_cnt
= max_non_def_sbs
;
10859 bp
->msg_enable
= debug
;
10860 pci_set_drvdata(pdev
, dev
);
10862 rc
= bnx2x_init_dev(pdev
, dev
, ent
->driver_data
);
10868 DP(NETIF_MSG_DRV
, "max_non_def_sbs %d\n", max_non_def_sbs
);
10870 rc
= bnx2x_init_bp(bp
);
10872 goto init_one_exit
;
10875 * Map doorbels here as we need the real value of bp->max_cos which
10876 * is initialized in bnx2x_init_bp().
10878 bp
->doorbells
= ioremap_nocache(pci_resource_start(pdev
, 2),
10879 min_t(u64
, BNX2X_DB_SIZE(bp
),
10880 pci_resource_len(pdev
, 2)));
10881 if (!bp
->doorbells
) {
10882 dev_err(&bp
->pdev
->dev
,
10883 "Cannot map doorbell space, aborting\n");
10885 goto init_one_exit
;
10888 /* calc qm_cid_count */
10889 bp
->qm_cid_count
= bnx2x_set_qm_cid_count(bp
);
10892 /* disable FCOE L2 queue for E1x */
10893 if (CHIP_IS_E1x(bp
))
10894 bp
->flags
|= NO_FCOE_FLAG
;
10898 /* Configure interrupt mode: try to enable MSI-X/MSI if
10899 * needed, set bp->num_queues appropriately.
10901 bnx2x_set_int_mode(bp
);
10903 /* Add all NAPI objects */
10904 bnx2x_add_all_napi(bp
);
10906 rc
= register_netdev(dev
);
10908 dev_err(&pdev
->dev
, "Cannot register net device\n");
10909 goto init_one_exit
;
10913 if (!NO_FCOE(bp
)) {
10914 /* Add storage MAC address */
10916 dev_addr_add(bp
->dev
, bp
->fip_mac
, NETDEV_HW_ADDR_T_SAN
);
10921 bnx2x_get_pcie_width_speed(bp
, &pcie_width
, &pcie_speed
);
10923 netdev_info(dev
, "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
10924 board_info
[ent
->driver_data
].name
,
10925 (CHIP_REV(bp
) >> 12) + 'A', (CHIP_METAL(bp
) >> 4),
10927 ((!CHIP_IS_E2(bp
) && pcie_speed
== 2) ||
10928 (CHIP_IS_E2(bp
) && pcie_speed
== 1)) ?
10929 "5GHz (Gen2)" : "2.5GHz",
10930 dev
->base_addr
, bp
->pdev
->irq
, dev
->dev_addr
);
10936 iounmap(bp
->regview
);
10939 iounmap(bp
->doorbells
);
10943 if (atomic_read(&pdev
->enable_cnt
) == 1)
10944 pci_release_regions(pdev
);
10946 pci_disable_device(pdev
);
10947 pci_set_drvdata(pdev
, NULL
);
10952 static void __devexit
bnx2x_remove_one(struct pci_dev
*pdev
)
10954 struct net_device
*dev
= pci_get_drvdata(pdev
);
10958 dev_err(&pdev
->dev
, "BAD net device from bnx2x_init_one\n");
10961 bp
= netdev_priv(dev
);
10964 /* Delete storage MAC address */
10965 if (!NO_FCOE(bp
)) {
10967 dev_addr_del(bp
->dev
, bp
->fip_mac
, NETDEV_HW_ADDR_T_SAN
);
10973 /* Delete app tlvs from dcbnl */
10974 bnx2x_dcbnl_update_applist(bp
, true);
10977 unregister_netdev(dev
);
10979 /* Delete all NAPI objects */
10980 bnx2x_del_all_napi(bp
);
10982 /* Power on: we can't let PCI layer write to us while we are in D3 */
10983 bnx2x_set_power_state(bp
, PCI_D0
);
10985 /* Disable MSI/MSI-X */
10986 bnx2x_disable_msi(bp
);
10989 bnx2x_set_power_state(bp
, PCI_D3hot
);
10991 /* Make sure RESET task is not scheduled before continuing */
10992 cancel_delayed_work_sync(&bp
->sp_rtnl_task
);
10995 iounmap(bp
->regview
);
10998 iounmap(bp
->doorbells
);
11000 bnx2x_release_firmware(bp
);
11002 bnx2x_free_mem_bp(bp
);
11006 if (atomic_read(&pdev
->enable_cnt
) == 1)
11007 pci_release_regions(pdev
);
11009 pci_disable_device(pdev
);
11010 pci_set_drvdata(pdev
, NULL
);
11013 static int bnx2x_eeh_nic_unload(struct bnx2x
*bp
)
11017 bp
->state
= BNX2X_STATE_ERROR
;
11019 bp
->rx_mode
= BNX2X_RX_MODE_NONE
;
11022 bnx2x_cnic_notify(bp
, CNIC_CTL_STOP_CMD
);
11025 bnx2x_tx_disable(bp
);
11027 bnx2x_netif_stop(bp
, 0);
11029 del_timer_sync(&bp
->timer
);
11031 bnx2x_stats_handle(bp
, STATS_EVENT_STOP
);
11034 bnx2x_free_irq(bp
);
11036 /* Free SKBs, SGEs, TPA pool and driver internals */
11037 bnx2x_free_skbs(bp
);
11039 for_each_rx_queue(bp
, i
)
11040 bnx2x_free_rx_sge_range(bp
, bp
->fp
+ i
, NUM_RX_SGE
);
11042 bnx2x_free_mem(bp
);
11044 bp
->state
= BNX2X_STATE_CLOSED
;
11046 netif_carrier_off(bp
->dev
);
11051 static void bnx2x_eeh_recover(struct bnx2x
*bp
)
11055 mutex_init(&bp
->port
.phy_mutex
);
11057 bp
->common
.shmem_base
= REG_RD(bp
, MISC_REG_SHARED_MEM_ADDR
);
11058 bp
->link_params
.shmem_base
= bp
->common
.shmem_base
;
11059 BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp
->common
.shmem_base
);
11061 if (!bp
->common
.shmem_base
||
11062 (bp
->common
.shmem_base
< 0xA0000) ||
11063 (bp
->common
.shmem_base
>= 0xC0000)) {
11064 BNX2X_DEV_INFO("MCP not active\n");
11065 bp
->flags
|= NO_MCP_FLAG
;
11069 val
= SHMEM_RD(bp
, validity_map
[BP_PORT(bp
)]);
11070 if ((val
& (SHR_MEM_VALIDITY_DEV_INFO
| SHR_MEM_VALIDITY_MB
))
11071 != (SHR_MEM_VALIDITY_DEV_INFO
| SHR_MEM_VALIDITY_MB
))
11072 BNX2X_ERR("BAD MCP validity signature\n");
11074 if (!BP_NOMCP(bp
)) {
11076 (SHMEM_RD(bp
, func_mb
[BP_FW_MB_IDX(bp
)].drv_mb_header
) &
11077 DRV_MSG_SEQ_NUMBER_MASK
);
11078 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp
->fw_seq
);
11083 * bnx2x_io_error_detected - called when PCI error is detected
11084 * @pdev: Pointer to PCI device
11085 * @state: The current pci connection state
11087 * This function is called after a PCI bus error affecting
11088 * this device has been detected.
11090 static pci_ers_result_t
bnx2x_io_error_detected(struct pci_dev
*pdev
,
11091 pci_channel_state_t state
)
11093 struct net_device
*dev
= pci_get_drvdata(pdev
);
11094 struct bnx2x
*bp
= netdev_priv(dev
);
11098 netif_device_detach(dev
);
11100 if (state
== pci_channel_io_perm_failure
) {
11102 return PCI_ERS_RESULT_DISCONNECT
;
11105 if (netif_running(dev
))
11106 bnx2x_eeh_nic_unload(bp
);
11108 pci_disable_device(pdev
);
11112 /* Request a slot reset */
11113 return PCI_ERS_RESULT_NEED_RESET
;
11117 * bnx2x_io_slot_reset - called after the PCI bus has been reset
11118 * @pdev: Pointer to PCI device
11120 * Restart the card from scratch, as if from a cold-boot.
11122 static pci_ers_result_t
bnx2x_io_slot_reset(struct pci_dev
*pdev
)
11124 struct net_device
*dev
= pci_get_drvdata(pdev
);
11125 struct bnx2x
*bp
= netdev_priv(dev
);
11129 if (pci_enable_device(pdev
)) {
11130 dev_err(&pdev
->dev
,
11131 "Cannot re-enable PCI device after reset\n");
11133 return PCI_ERS_RESULT_DISCONNECT
;
11136 pci_set_master(pdev
);
11137 pci_restore_state(pdev
);
11139 if (netif_running(dev
))
11140 bnx2x_set_power_state(bp
, PCI_D0
);
11144 return PCI_ERS_RESULT_RECOVERED
;
11148 * bnx2x_io_resume - called when traffic can start flowing again
11149 * @pdev: Pointer to PCI device
11151 * This callback is called when the error recovery driver tells us that
11152 * its OK to resume normal operation.
11154 static void bnx2x_io_resume(struct pci_dev
*pdev
)
11156 struct net_device
*dev
= pci_get_drvdata(pdev
);
11157 struct bnx2x
*bp
= netdev_priv(dev
);
11159 if (bp
->recovery_state
!= BNX2X_RECOVERY_DONE
) {
11160 netdev_err(bp
->dev
, "Handling parity error recovery. "
11161 "Try again later\n");
11167 bnx2x_eeh_recover(bp
);
11169 if (netif_running(dev
))
11170 bnx2x_nic_load(bp
, LOAD_NORMAL
);
11172 netif_device_attach(dev
);
11177 static struct pci_error_handlers bnx2x_err_handler
= {
11178 .error_detected
= bnx2x_io_error_detected
,
11179 .slot_reset
= bnx2x_io_slot_reset
,
11180 .resume
= bnx2x_io_resume
,
11183 static struct pci_driver bnx2x_pci_driver
= {
11184 .name
= DRV_MODULE_NAME
,
11185 .id_table
= bnx2x_pci_tbl
,
11186 .probe
= bnx2x_init_one
,
11187 .remove
= __devexit_p(bnx2x_remove_one
),
11188 .suspend
= bnx2x_suspend
,
11189 .resume
= bnx2x_resume
,
11190 .err_handler
= &bnx2x_err_handler
,
11193 static int __init
bnx2x_init(void)
11197 pr_info("%s", version
);
11199 bnx2x_wq
= create_singlethread_workqueue("bnx2x");
11200 if (bnx2x_wq
== NULL
) {
11201 pr_err("Cannot create workqueue\n");
11205 ret
= pci_register_driver(&bnx2x_pci_driver
);
11207 pr_err("Cannot register driver\n");
11208 destroy_workqueue(bnx2x_wq
);
11213 static void __exit
bnx2x_cleanup(void)
11215 pci_unregister_driver(&bnx2x_pci_driver
);
11217 destroy_workqueue(bnx2x_wq
);
11220 void bnx2x_notify_link_changed(struct bnx2x
*bp
)
11222 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_12
+ BP_FUNC(bp
)*sizeof(u32
), 1);
11225 module_init(bnx2x_init
);
11226 module_exit(bnx2x_cleanup
);
11230 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
11232 * @bp: driver handle
11233 * @set: set or clear the CAM entry
11235 * This function will wait until the ramdord completion returns.
11236 * Return 0 if success, -ENODEV if ramrod doesn't return.
11238 static inline int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x
*bp
)
11240 unsigned long ramrod_flags
= 0;
11242 __set_bit(RAMROD_COMP_WAIT
, &ramrod_flags
);
11243 return bnx2x_set_mac_one(bp
, bp
->cnic_eth_dev
.iscsi_mac
,
11244 &bp
->iscsi_l2_mac_obj
, true,
11245 BNX2X_ISCSI_ETH_MAC
, &ramrod_flags
);
11248 /* count denotes the number of new completions we have seen */
11249 static void bnx2x_cnic_sp_post(struct bnx2x
*bp
, int count
)
11251 struct eth_spe
*spe
;
11253 #ifdef BNX2X_STOP_ON_ERROR
11254 if (unlikely(bp
->panic
))
11258 spin_lock_bh(&bp
->spq_lock
);
11259 BUG_ON(bp
->cnic_spq_pending
< count
);
11260 bp
->cnic_spq_pending
-= count
;
11263 for (; bp
->cnic_kwq_pending
; bp
->cnic_kwq_pending
--) {
11264 u16 type
= (le16_to_cpu(bp
->cnic_kwq_cons
->hdr
.type
)
11265 & SPE_HDR_CONN_TYPE
) >>
11266 SPE_HDR_CONN_TYPE_SHIFT
;
11267 u8 cmd
= (le32_to_cpu(bp
->cnic_kwq_cons
->hdr
.conn_and_cmd_data
)
11268 >> SPE_HDR_CMD_ID_SHIFT
) & 0xff;
11270 /* Set validation for iSCSI L2 client before sending SETUP
11273 if (type
== ETH_CONNECTION_TYPE
) {
11274 if (cmd
== RAMROD_CMD_ID_ETH_CLIENT_SETUP
)
11275 bnx2x_set_ctx_validation(bp
, &bp
->context
.
11276 vcxt
[BNX2X_ISCSI_ETH_CID
].eth
,
11277 BNX2X_ISCSI_ETH_CID
);
11281 * There may be not more than 8 L2, not more than 8 L5 SPEs
11282 * and in the air. We also check that number of outstanding
11283 * COMMON ramrods is not more than the EQ and SPQ can
11286 if (type
== ETH_CONNECTION_TYPE
) {
11287 if (!atomic_read(&bp
->cq_spq_left
))
11290 atomic_dec(&bp
->cq_spq_left
);
11291 } else if (type
== NONE_CONNECTION_TYPE
) {
11292 if (!atomic_read(&bp
->eq_spq_left
))
11295 atomic_dec(&bp
->eq_spq_left
);
11296 } else if ((type
== ISCSI_CONNECTION_TYPE
) ||
11297 (type
== FCOE_CONNECTION_TYPE
)) {
11298 if (bp
->cnic_spq_pending
>=
11299 bp
->cnic_eth_dev
.max_kwqe_pending
)
11302 bp
->cnic_spq_pending
++;
11304 BNX2X_ERR("Unknown SPE type: %d\n", type
);
11309 spe
= bnx2x_sp_get_next(bp
);
11310 *spe
= *bp
->cnic_kwq_cons
;
11312 DP(NETIF_MSG_TIMER
, "pending on SPQ %d, on KWQ %d count %d\n",
11313 bp
->cnic_spq_pending
, bp
->cnic_kwq_pending
, count
);
11315 if (bp
->cnic_kwq_cons
== bp
->cnic_kwq_last
)
11316 bp
->cnic_kwq_cons
= bp
->cnic_kwq
;
11318 bp
->cnic_kwq_cons
++;
11320 bnx2x_sp_prod_update(bp
);
11321 spin_unlock_bh(&bp
->spq_lock
);
11324 static int bnx2x_cnic_sp_queue(struct net_device
*dev
,
11325 struct kwqe_16
*kwqes
[], u32 count
)
11327 struct bnx2x
*bp
= netdev_priv(dev
);
11330 #ifdef BNX2X_STOP_ON_ERROR
11331 if (unlikely(bp
->panic
))
11335 spin_lock_bh(&bp
->spq_lock
);
11337 for (i
= 0; i
< count
; i
++) {
11338 struct eth_spe
*spe
= (struct eth_spe
*)kwqes
[i
];
11340 if (bp
->cnic_kwq_pending
== MAX_SP_DESC_CNT
)
11343 *bp
->cnic_kwq_prod
= *spe
;
11345 bp
->cnic_kwq_pending
++;
11347 DP(NETIF_MSG_TIMER
, "L5 SPQE %x %x %x:%x pos %d\n",
11348 spe
->hdr
.conn_and_cmd_data
, spe
->hdr
.type
,
11349 spe
->data
.update_data_addr
.hi
,
11350 spe
->data
.update_data_addr
.lo
,
11351 bp
->cnic_kwq_pending
);
11353 if (bp
->cnic_kwq_prod
== bp
->cnic_kwq_last
)
11354 bp
->cnic_kwq_prod
= bp
->cnic_kwq
;
11356 bp
->cnic_kwq_prod
++;
11359 spin_unlock_bh(&bp
->spq_lock
);
11361 if (bp
->cnic_spq_pending
< bp
->cnic_eth_dev
.max_kwqe_pending
)
11362 bnx2x_cnic_sp_post(bp
, 0);
11367 static int bnx2x_cnic_ctl_send(struct bnx2x
*bp
, struct cnic_ctl_info
*ctl
)
11369 struct cnic_ops
*c_ops
;
11372 mutex_lock(&bp
->cnic_mutex
);
11373 c_ops
= rcu_dereference_protected(bp
->cnic_ops
,
11374 lockdep_is_held(&bp
->cnic_mutex
));
11376 rc
= c_ops
->cnic_ctl(bp
->cnic_data
, ctl
);
11377 mutex_unlock(&bp
->cnic_mutex
);
11382 static int bnx2x_cnic_ctl_send_bh(struct bnx2x
*bp
, struct cnic_ctl_info
*ctl
)
11384 struct cnic_ops
*c_ops
;
11388 c_ops
= rcu_dereference(bp
->cnic_ops
);
11390 rc
= c_ops
->cnic_ctl(bp
->cnic_data
, ctl
);
11397 * for commands that have no data
11399 int bnx2x_cnic_notify(struct bnx2x
*bp
, int cmd
)
11401 struct cnic_ctl_info ctl
= {0};
11405 return bnx2x_cnic_ctl_send(bp
, &ctl
);
11408 static void bnx2x_cnic_cfc_comp(struct bnx2x
*bp
, int cid
, u8 err
)
11410 struct cnic_ctl_info ctl
= {0};
11412 /* first we tell CNIC and only then we count this as a completion */
11413 ctl
.cmd
= CNIC_CTL_COMPLETION_CMD
;
11414 ctl
.data
.comp
.cid
= cid
;
11415 ctl
.data
.comp
.error
= err
;
11417 bnx2x_cnic_ctl_send_bh(bp
, &ctl
);
11418 bnx2x_cnic_sp_post(bp
, 0);
11422 /* Called with netif_addr_lock_bh() taken.
11423 * Sets an rx_mode config for an iSCSI ETH client.
11425 * Completion should be checked outside.
11427 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x
*bp
, bool start
)
11429 unsigned long accept_flags
= 0, ramrod_flags
= 0;
11430 u8 cl_id
= bnx2x_cnic_eth_cl_id(bp
, BNX2X_ISCSI_ETH_CL_ID_IDX
);
11431 int sched_state
= BNX2X_FILTER_ISCSI_ETH_STOP_SCHED
;
11434 /* Start accepting on iSCSI L2 ring. Accept all multicasts
11435 * because it's the only way for UIO Queue to accept
11436 * multicasts (in non-promiscuous mode only one Queue per
11437 * function will receive multicast packets (leading in our
11440 __set_bit(BNX2X_ACCEPT_UNICAST
, &accept_flags
);
11441 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST
, &accept_flags
);
11442 __set_bit(BNX2X_ACCEPT_BROADCAST
, &accept_flags
);
11443 __set_bit(BNX2X_ACCEPT_ANY_VLAN
, &accept_flags
);
11445 /* Clear STOP_PENDING bit if START is requested */
11446 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED
, &bp
->sp_state
);
11448 sched_state
= BNX2X_FILTER_ISCSI_ETH_START_SCHED
;
11450 /* Clear START_PENDING bit if STOP is requested */
11451 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED
, &bp
->sp_state
);
11453 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING
, &bp
->sp_state
))
11454 set_bit(sched_state
, &bp
->sp_state
);
11456 __set_bit(RAMROD_RX
, &ramrod_flags
);
11457 bnx2x_set_q_rx_mode(bp
, cl_id
, 0, accept_flags
, 0,
11463 static int bnx2x_drv_ctl(struct net_device
*dev
, struct drv_ctl_info
*ctl
)
11465 struct bnx2x
*bp
= netdev_priv(dev
);
11468 switch (ctl
->cmd
) {
11469 case DRV_CTL_CTXTBL_WR_CMD
: {
11470 u32 index
= ctl
->data
.io
.offset
;
11471 dma_addr_t addr
= ctl
->data
.io
.dma_addr
;
11473 bnx2x_ilt_wr(bp
, index
, addr
);
11477 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD
: {
11478 int count
= ctl
->data
.credit
.credit_count
;
11480 bnx2x_cnic_sp_post(bp
, count
);
11484 /* rtnl_lock is held. */
11485 case DRV_CTL_START_L2_CMD
: {
11486 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
11487 unsigned long sp_bits
= 0;
11489 /* Configure the iSCSI classification object */
11490 bnx2x_init_mac_obj(bp
, &bp
->iscsi_l2_mac_obj
,
11491 cp
->iscsi_l2_client_id
,
11492 cp
->iscsi_l2_cid
, BP_FUNC(bp
),
11493 bnx2x_sp(bp
, mac_rdata
),
11494 bnx2x_sp_mapping(bp
, mac_rdata
),
11495 BNX2X_FILTER_MAC_PENDING
,
11496 &bp
->sp_state
, BNX2X_OBJ_TYPE_RX
,
11499 /* Set iSCSI MAC address */
11500 rc
= bnx2x_set_iscsi_eth_mac_addr(bp
);
11507 /* Start accepting on iSCSI L2 ring */
11509 netif_addr_lock_bh(dev
);
11510 bnx2x_set_iscsi_eth_rx_mode(bp
, true);
11511 netif_addr_unlock_bh(dev
);
11513 /* bits to wait on */
11514 __set_bit(BNX2X_FILTER_RX_MODE_PENDING
, &sp_bits
);
11515 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED
, &sp_bits
);
11517 if (!bnx2x_wait_sp_comp(bp
, sp_bits
))
11518 BNX2X_ERR("rx_mode completion timed out!\n");
11523 /* rtnl_lock is held. */
11524 case DRV_CTL_STOP_L2_CMD
: {
11525 unsigned long sp_bits
= 0;
11527 /* Stop accepting on iSCSI L2 ring */
11528 netif_addr_lock_bh(dev
);
11529 bnx2x_set_iscsi_eth_rx_mode(bp
, false);
11530 netif_addr_unlock_bh(dev
);
11532 /* bits to wait on */
11533 __set_bit(BNX2X_FILTER_RX_MODE_PENDING
, &sp_bits
);
11534 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED
, &sp_bits
);
11536 if (!bnx2x_wait_sp_comp(bp
, sp_bits
))
11537 BNX2X_ERR("rx_mode completion timed out!\n");
11542 /* Unset iSCSI L2 MAC */
11543 rc
= bnx2x_del_all_macs(bp
, &bp
->iscsi_l2_mac_obj
,
11544 BNX2X_ISCSI_ETH_MAC
, true);
11547 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD
: {
11548 int count
= ctl
->data
.credit
.credit_count
;
11550 smp_mb__before_atomic_inc();
11551 atomic_add(count
, &bp
->cq_spq_left
);
11552 smp_mb__after_atomic_inc();
11557 BNX2X_ERR("unknown command %x\n", ctl
->cmd
);
11564 void bnx2x_setup_cnic_irq_info(struct bnx2x
*bp
)
11566 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
11568 if (bp
->flags
& USING_MSIX_FLAG
) {
11569 cp
->drv_state
|= CNIC_DRV_STATE_USING_MSIX
;
11570 cp
->irq_arr
[0].irq_flags
|= CNIC_IRQ_FL_MSIX
;
11571 cp
->irq_arr
[0].vector
= bp
->msix_table
[1].vector
;
11573 cp
->drv_state
&= ~CNIC_DRV_STATE_USING_MSIX
;
11574 cp
->irq_arr
[0].irq_flags
&= ~CNIC_IRQ_FL_MSIX
;
11576 if (!CHIP_IS_E1x(bp
))
11577 cp
->irq_arr
[0].status_blk
= (void *)bp
->cnic_sb
.e2_sb
;
11579 cp
->irq_arr
[0].status_blk
= (void *)bp
->cnic_sb
.e1x_sb
;
11581 cp
->irq_arr
[0].status_blk_num
= bnx2x_cnic_fw_sb_id(bp
);
11582 cp
->irq_arr
[0].status_blk_num2
= bnx2x_cnic_igu_sb_id(bp
);
11583 cp
->irq_arr
[1].status_blk
= bp
->def_status_blk
;
11584 cp
->irq_arr
[1].status_blk_num
= DEF_SB_ID
;
11585 cp
->irq_arr
[1].status_blk_num2
= DEF_SB_IGU_ID
;
11590 static int bnx2x_register_cnic(struct net_device
*dev
, struct cnic_ops
*ops
,
11593 struct bnx2x
*bp
= netdev_priv(dev
);
11594 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
11599 bp
->cnic_kwq
= kzalloc(PAGE_SIZE
, GFP_KERNEL
);
11603 bp
->cnic_kwq_cons
= bp
->cnic_kwq
;
11604 bp
->cnic_kwq_prod
= bp
->cnic_kwq
;
11605 bp
->cnic_kwq_last
= bp
->cnic_kwq
+ MAX_SP_DESC_CNT
;
11607 bp
->cnic_spq_pending
= 0;
11608 bp
->cnic_kwq_pending
= 0;
11610 bp
->cnic_data
= data
;
11613 cp
->drv_state
|= CNIC_DRV_STATE_REGD
;
11614 cp
->iro_arr
= bp
->iro_arr
;
11616 bnx2x_setup_cnic_irq_info(bp
);
11618 rcu_assign_pointer(bp
->cnic_ops
, ops
);
11623 static int bnx2x_unregister_cnic(struct net_device
*dev
)
11625 struct bnx2x
*bp
= netdev_priv(dev
);
11626 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
11628 mutex_lock(&bp
->cnic_mutex
);
11630 RCU_INIT_POINTER(bp
->cnic_ops
, NULL
);
11631 mutex_unlock(&bp
->cnic_mutex
);
11633 kfree(bp
->cnic_kwq
);
11634 bp
->cnic_kwq
= NULL
;
11639 struct cnic_eth_dev
*bnx2x_cnic_probe(struct net_device
*dev
)
11641 struct bnx2x
*bp
= netdev_priv(dev
);
11642 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
11644 /* If both iSCSI and FCoE are disabled - return NULL in
11645 * order to indicate CNIC that it should not try to work
11646 * with this device.
11648 if (NO_ISCSI(bp
) && NO_FCOE(bp
))
11651 cp
->drv_owner
= THIS_MODULE
;
11652 cp
->chip_id
= CHIP_ID(bp
);
11653 cp
->pdev
= bp
->pdev
;
11654 cp
->io_base
= bp
->regview
;
11655 cp
->io_base2
= bp
->doorbells
;
11656 cp
->max_kwqe_pending
= 8;
11657 cp
->ctx_blk_size
= CDU_ILT_PAGE_SZ
;
11658 cp
->ctx_tbl_offset
= FUNC_ILT_BASE(BP_FUNC(bp
)) +
11659 bnx2x_cid_ilt_lines(bp
);
11660 cp
->ctx_tbl_len
= CNIC_ILT_LINES
;
11661 cp
->starting_cid
= bnx2x_cid_ilt_lines(bp
) * ILT_PAGE_CIDS
;
11662 cp
->drv_submit_kwqes_16
= bnx2x_cnic_sp_queue
;
11663 cp
->drv_ctl
= bnx2x_drv_ctl
;
11664 cp
->drv_register_cnic
= bnx2x_register_cnic
;
11665 cp
->drv_unregister_cnic
= bnx2x_unregister_cnic
;
11666 cp
->fcoe_init_cid
= BNX2X_FCOE_ETH_CID
;
11667 cp
->iscsi_l2_client_id
=
11668 bnx2x_cnic_eth_cl_id(bp
, BNX2X_ISCSI_ETH_CL_ID_IDX
);
11669 cp
->iscsi_l2_cid
= BNX2X_ISCSI_ETH_CID
;
11671 if (NO_ISCSI_OOO(bp
))
11672 cp
->drv_state
|= CNIC_DRV_STATE_NO_ISCSI_OOO
;
11675 cp
->drv_state
|= CNIC_DRV_STATE_NO_ISCSI
;
11678 cp
->drv_state
|= CNIC_DRV_STATE_NO_FCOE
;
11680 DP(BNX2X_MSG_SP
, "page_size %d, tbl_offset %d, tbl_lines %d, "
11681 "starting cid %d\n",
11683 cp
->ctx_tbl_offset
,
11688 EXPORT_SYMBOL(bnx2x_cnic_probe
);
11690 #endif /* BCM_CNIC */