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[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_main.c
1 /* bnx2x_main.c: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2013 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
20 #include <linux/module.h>
21 #include <linux/moduleparam.h>
22 #include <linux/kernel.h>
23 #include <linux/device.h> /* for dev_info() */
24 #include <linux/timer.h>
25 #include <linux/errno.h>
26 #include <linux/ioport.h>
27 #include <linux/slab.h>
28 #include <linux/interrupt.h>
29 #include <linux/pci.h>
30 #include <linux/aer.h>
31 #include <linux/init.h>
32 #include <linux/netdevice.h>
33 #include <linux/etherdevice.h>
34 #include <linux/skbuff.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/bitops.h>
37 #include <linux/irq.h>
38 #include <linux/delay.h>
39 #include <asm/byteorder.h>
40 #include <linux/time.h>
41 #include <linux/ethtool.h>
42 #include <linux/mii.h>
43 #include <linux/if_vlan.h>
44 #include <linux/crash_dump.h>
45 #include <net/ip.h>
46 #include <net/ipv6.h>
47 #include <net/tcp.h>
48 #include <net/checksum.h>
49 #include <net/ip6_checksum.h>
50 #include <linux/workqueue.h>
51 #include <linux/crc32.h>
52 #include <linux/crc32c.h>
53 #include <linux/prefetch.h>
54 #include <linux/zlib.h>
55 #include <linux/io.h>
56 #include <linux/semaphore.h>
57 #include <linux/stringify.h>
58 #include <linux/vmalloc.h>
59
60 #include "bnx2x.h"
61 #include "bnx2x_init.h"
62 #include "bnx2x_init_ops.h"
63 #include "bnx2x_cmn.h"
64 #include "bnx2x_vfpf.h"
65 #include "bnx2x_dcb.h"
66 #include "bnx2x_sp.h"
67 #include <linux/firmware.h>
68 #include "bnx2x_fw_file_hdr.h"
69 /* FW files */
70 #define FW_FILE_VERSION \
71 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
72 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
73 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
74 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
75 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
76 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
77 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
78
79 /* Time in jiffies before concluding the transmitter is hung */
80 #define TX_TIMEOUT (5*HZ)
81
82 static char version[] =
83 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
84 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
85
86 MODULE_AUTHOR("Eliezer Tamir");
87 MODULE_DESCRIPTION("Broadcom NetXtreme II "
88 "BCM57710/57711/57711E/"
89 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
90 "57840/57840_MF Driver");
91 MODULE_LICENSE("GPL");
92 MODULE_VERSION(DRV_MODULE_VERSION);
93 MODULE_FIRMWARE(FW_FILE_NAME_E1);
94 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
95 MODULE_FIRMWARE(FW_FILE_NAME_E2);
96
97 int bnx2x_num_queues;
98 module_param_named(num_queues, bnx2x_num_queues, int, S_IRUGO);
99 MODULE_PARM_DESC(num_queues,
100 " Set number of queues (default is as a number of CPUs)");
101
102 static int disable_tpa;
103 module_param(disable_tpa, int, S_IRUGO);
104 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
105
106 static int int_mode;
107 module_param(int_mode, int, S_IRUGO);
108 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
109 "(1 INT#x; 2 MSI)");
110
111 static int dropless_fc;
112 module_param(dropless_fc, int, S_IRUGO);
113 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
114
115 static int mrrs = -1;
116 module_param(mrrs, int, S_IRUGO);
117 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
118
119 static int debug;
120 module_param(debug, int, S_IRUGO);
121 MODULE_PARM_DESC(debug, " Default debug msglevel");
122
123 static struct workqueue_struct *bnx2x_wq;
124 struct workqueue_struct *bnx2x_iov_wq;
125
126 struct bnx2x_mac_vals {
127 u32 xmac_addr;
128 u32 xmac_val;
129 u32 emac_addr;
130 u32 emac_val;
131 u32 umac_addr;
132 u32 umac_val;
133 u32 bmac_addr;
134 u32 bmac_val[2];
135 };
136
137 enum bnx2x_board_type {
138 BCM57710 = 0,
139 BCM57711,
140 BCM57711E,
141 BCM57712,
142 BCM57712_MF,
143 BCM57712_VF,
144 BCM57800,
145 BCM57800_MF,
146 BCM57800_VF,
147 BCM57810,
148 BCM57810_MF,
149 BCM57810_VF,
150 BCM57840_4_10,
151 BCM57840_2_20,
152 BCM57840_MF,
153 BCM57840_VF,
154 BCM57811,
155 BCM57811_MF,
156 BCM57840_O,
157 BCM57840_MFO,
158 BCM57811_VF
159 };
160
161 /* indexed by board_type, above */
162 static struct {
163 char *name;
164 } board_info[] = {
165 [BCM57710] = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
166 [BCM57711] = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
167 [BCM57711E] = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
168 [BCM57712] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
169 [BCM57712_MF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
170 [BCM57712_VF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" },
171 [BCM57800] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
172 [BCM57800_MF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
173 [BCM57800_VF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" },
174 [BCM57810] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
175 [BCM57810_MF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
176 [BCM57810_VF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" },
177 [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
178 [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
179 [BCM57840_MF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
180 [BCM57840_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" },
181 [BCM57811] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" },
182 [BCM57811_MF] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" },
183 [BCM57840_O] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
184 [BCM57840_MFO] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
185 [BCM57811_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }
186 };
187
188 #ifndef PCI_DEVICE_ID_NX2_57710
189 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
190 #endif
191 #ifndef PCI_DEVICE_ID_NX2_57711
192 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
193 #endif
194 #ifndef PCI_DEVICE_ID_NX2_57711E
195 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
196 #endif
197 #ifndef PCI_DEVICE_ID_NX2_57712
198 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
199 #endif
200 #ifndef PCI_DEVICE_ID_NX2_57712_MF
201 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
202 #endif
203 #ifndef PCI_DEVICE_ID_NX2_57712_VF
204 #define PCI_DEVICE_ID_NX2_57712_VF CHIP_NUM_57712_VF
205 #endif
206 #ifndef PCI_DEVICE_ID_NX2_57800
207 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
208 #endif
209 #ifndef PCI_DEVICE_ID_NX2_57800_MF
210 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
211 #endif
212 #ifndef PCI_DEVICE_ID_NX2_57800_VF
213 #define PCI_DEVICE_ID_NX2_57800_VF CHIP_NUM_57800_VF
214 #endif
215 #ifndef PCI_DEVICE_ID_NX2_57810
216 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
217 #endif
218 #ifndef PCI_DEVICE_ID_NX2_57810_MF
219 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
220 #endif
221 #ifndef PCI_DEVICE_ID_NX2_57840_O
222 #define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE
223 #endif
224 #ifndef PCI_DEVICE_ID_NX2_57810_VF
225 #define PCI_DEVICE_ID_NX2_57810_VF CHIP_NUM_57810_VF
226 #endif
227 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
228 #define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10
229 #endif
230 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
231 #define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20
232 #endif
233 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
234 #define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE
235 #endif
236 #ifndef PCI_DEVICE_ID_NX2_57840_MF
237 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
238 #endif
239 #ifndef PCI_DEVICE_ID_NX2_57840_VF
240 #define PCI_DEVICE_ID_NX2_57840_VF CHIP_NUM_57840_VF
241 #endif
242 #ifndef PCI_DEVICE_ID_NX2_57811
243 #define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811
244 #endif
245 #ifndef PCI_DEVICE_ID_NX2_57811_MF
246 #define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF
247 #endif
248 #ifndef PCI_DEVICE_ID_NX2_57811_VF
249 #define PCI_DEVICE_ID_NX2_57811_VF CHIP_NUM_57811_VF
250 #endif
251
252 static const struct pci_device_id bnx2x_pci_tbl[] = {
253 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
254 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
255 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
256 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
257 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
258 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
259 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
260 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
261 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
262 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
263 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
264 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
265 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
266 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
267 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
268 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
269 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
270 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
271 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
272 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
273 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
274 { 0 }
275 };
276
277 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
278
279 /* Global resources for unloading a previously loaded device */
280 #define BNX2X_PREV_WAIT_NEEDED 1
281 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
282 static LIST_HEAD(bnx2x_prev_list);
283
284 /* Forward declaration */
285 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
286 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp);
287 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
288
289 /****************************************************************************
290 * General service functions
291 ****************************************************************************/
292
293 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr);
294
295 static void __storm_memset_dma_mapping(struct bnx2x *bp,
296 u32 addr, dma_addr_t mapping)
297 {
298 REG_WR(bp, addr, U64_LO(mapping));
299 REG_WR(bp, addr + 4, U64_HI(mapping));
300 }
301
302 static void storm_memset_spq_addr(struct bnx2x *bp,
303 dma_addr_t mapping, u16 abs_fid)
304 {
305 u32 addr = XSEM_REG_FAST_MEMORY +
306 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
307
308 __storm_memset_dma_mapping(bp, addr, mapping);
309 }
310
311 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
312 u16 pf_id)
313 {
314 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
315 pf_id);
316 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
317 pf_id);
318 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
319 pf_id);
320 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
321 pf_id);
322 }
323
324 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
325 u8 enable)
326 {
327 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
328 enable);
329 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
330 enable);
331 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
332 enable);
333 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
334 enable);
335 }
336
337 static void storm_memset_eq_data(struct bnx2x *bp,
338 struct event_ring_data *eq_data,
339 u16 pfid)
340 {
341 size_t size = sizeof(struct event_ring_data);
342
343 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
344
345 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
346 }
347
348 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
349 u16 pfid)
350 {
351 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
352 REG_WR16(bp, addr, eq_prod);
353 }
354
355 /* used only at init
356 * locking is done by mcp
357 */
358 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
359 {
360 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
361 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
362 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
363 PCICFG_VENDOR_ID_OFFSET);
364 }
365
366 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
367 {
368 u32 val;
369
370 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
371 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
372 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
373 PCICFG_VENDOR_ID_OFFSET);
374
375 return val;
376 }
377
378 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
379 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
380 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
381 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
382 #define DMAE_DP_DST_NONE "dst_addr [none]"
383
384 static void bnx2x_dp_dmae(struct bnx2x *bp,
385 struct dmae_command *dmae, int msglvl)
386 {
387 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
388 int i;
389
390 switch (dmae->opcode & DMAE_COMMAND_DST) {
391 case DMAE_CMD_DST_PCI:
392 if (src_type == DMAE_CMD_SRC_PCI)
393 DP(msglvl, "DMAE: opcode 0x%08x\n"
394 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
395 "comp_addr [%x:%08x], comp_val 0x%08x\n",
396 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
397 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
398 dmae->comp_addr_hi, dmae->comp_addr_lo,
399 dmae->comp_val);
400 else
401 DP(msglvl, "DMAE: opcode 0x%08x\n"
402 "src [%08x], len [%d*4], dst [%x:%08x]\n"
403 "comp_addr [%x:%08x], comp_val 0x%08x\n",
404 dmae->opcode, dmae->src_addr_lo >> 2,
405 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
406 dmae->comp_addr_hi, dmae->comp_addr_lo,
407 dmae->comp_val);
408 break;
409 case DMAE_CMD_DST_GRC:
410 if (src_type == DMAE_CMD_SRC_PCI)
411 DP(msglvl, "DMAE: opcode 0x%08x\n"
412 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
413 "comp_addr [%x:%08x], comp_val 0x%08x\n",
414 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
415 dmae->len, dmae->dst_addr_lo >> 2,
416 dmae->comp_addr_hi, dmae->comp_addr_lo,
417 dmae->comp_val);
418 else
419 DP(msglvl, "DMAE: opcode 0x%08x\n"
420 "src [%08x], len [%d*4], dst [%08x]\n"
421 "comp_addr [%x:%08x], comp_val 0x%08x\n",
422 dmae->opcode, dmae->src_addr_lo >> 2,
423 dmae->len, dmae->dst_addr_lo >> 2,
424 dmae->comp_addr_hi, dmae->comp_addr_lo,
425 dmae->comp_val);
426 break;
427 default:
428 if (src_type == DMAE_CMD_SRC_PCI)
429 DP(msglvl, "DMAE: opcode 0x%08x\n"
430 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n"
431 "comp_addr [%x:%08x] comp_val 0x%08x\n",
432 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
433 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
434 dmae->comp_val);
435 else
436 DP(msglvl, "DMAE: opcode 0x%08x\n"
437 "src_addr [%08x] len [%d * 4] dst_addr [none]\n"
438 "comp_addr [%x:%08x] comp_val 0x%08x\n",
439 dmae->opcode, dmae->src_addr_lo >> 2,
440 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
441 dmae->comp_val);
442 break;
443 }
444
445 for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
446 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
447 i, *(((u32 *)dmae) + i));
448 }
449
450 /* copy command into DMAE command memory and set DMAE command go */
451 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
452 {
453 u32 cmd_offset;
454 int i;
455
456 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
457 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
458 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
459 }
460 REG_WR(bp, dmae_reg_go_c[idx], 1);
461 }
462
463 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
464 {
465 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
466 DMAE_CMD_C_ENABLE);
467 }
468
469 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
470 {
471 return opcode & ~DMAE_CMD_SRC_RESET;
472 }
473
474 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
475 bool with_comp, u8 comp_type)
476 {
477 u32 opcode = 0;
478
479 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
480 (dst_type << DMAE_COMMAND_DST_SHIFT));
481
482 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
483
484 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
485 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
486 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
487 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
488
489 #ifdef __BIG_ENDIAN
490 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
491 #else
492 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
493 #endif
494 if (with_comp)
495 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
496 return opcode;
497 }
498
499 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
500 struct dmae_command *dmae,
501 u8 src_type, u8 dst_type)
502 {
503 memset(dmae, 0, sizeof(struct dmae_command));
504
505 /* set the opcode */
506 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
507 true, DMAE_COMP_PCI);
508
509 /* fill in the completion parameters */
510 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
511 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
512 dmae->comp_val = DMAE_COMP_VAL;
513 }
514
515 /* issue a dmae command over the init-channel and wait for completion */
516 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
517 u32 *comp)
518 {
519 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
520 int rc = 0;
521
522 bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
523
524 /* Lock the dmae channel. Disable BHs to prevent a dead-lock
525 * as long as this code is called both from syscall context and
526 * from ndo_set_rx_mode() flow that may be called from BH.
527 */
528
529 spin_lock_bh(&bp->dmae_lock);
530
531 /* reset completion */
532 *comp = 0;
533
534 /* post the command on the channel used for initializations */
535 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
536
537 /* wait for completion */
538 udelay(5);
539 while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
540
541 if (!cnt ||
542 (bp->recovery_state != BNX2X_RECOVERY_DONE &&
543 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
544 BNX2X_ERR("DMAE timeout!\n");
545 rc = DMAE_TIMEOUT;
546 goto unlock;
547 }
548 cnt--;
549 udelay(50);
550 }
551 if (*comp & DMAE_PCI_ERR_FLAG) {
552 BNX2X_ERR("DMAE PCI error!\n");
553 rc = DMAE_PCI_ERROR;
554 }
555
556 unlock:
557
558 spin_unlock_bh(&bp->dmae_lock);
559
560 return rc;
561 }
562
563 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
564 u32 len32)
565 {
566 int rc;
567 struct dmae_command dmae;
568
569 if (!bp->dmae_ready) {
570 u32 *data = bnx2x_sp(bp, wb_data[0]);
571
572 if (CHIP_IS_E1(bp))
573 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
574 else
575 bnx2x_init_str_wr(bp, dst_addr, data, len32);
576 return;
577 }
578
579 /* set opcode and fixed command fields */
580 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
581
582 /* fill in addresses and len */
583 dmae.src_addr_lo = U64_LO(dma_addr);
584 dmae.src_addr_hi = U64_HI(dma_addr);
585 dmae.dst_addr_lo = dst_addr >> 2;
586 dmae.dst_addr_hi = 0;
587 dmae.len = len32;
588
589 /* issue the command and wait for completion */
590 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
591 if (rc) {
592 BNX2X_ERR("DMAE returned failure %d\n", rc);
593 #ifdef BNX2X_STOP_ON_ERROR
594 bnx2x_panic();
595 #endif
596 }
597 }
598
599 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
600 {
601 int rc;
602 struct dmae_command dmae;
603
604 if (!bp->dmae_ready) {
605 u32 *data = bnx2x_sp(bp, wb_data[0]);
606 int i;
607
608 if (CHIP_IS_E1(bp))
609 for (i = 0; i < len32; i++)
610 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
611 else
612 for (i = 0; i < len32; i++)
613 data[i] = REG_RD(bp, src_addr + i*4);
614
615 return;
616 }
617
618 /* set opcode and fixed command fields */
619 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
620
621 /* fill in addresses and len */
622 dmae.src_addr_lo = src_addr >> 2;
623 dmae.src_addr_hi = 0;
624 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
625 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
626 dmae.len = len32;
627
628 /* issue the command and wait for completion */
629 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
630 if (rc) {
631 BNX2X_ERR("DMAE returned failure %d\n", rc);
632 #ifdef BNX2X_STOP_ON_ERROR
633 bnx2x_panic();
634 #endif
635 }
636 }
637
638 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
639 u32 addr, u32 len)
640 {
641 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
642 int offset = 0;
643
644 while (len > dmae_wr_max) {
645 bnx2x_write_dmae(bp, phys_addr + offset,
646 addr + offset, dmae_wr_max);
647 offset += dmae_wr_max * 4;
648 len -= dmae_wr_max;
649 }
650
651 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
652 }
653
654 enum storms {
655 XSTORM,
656 TSTORM,
657 CSTORM,
658 USTORM,
659 MAX_STORMS
660 };
661
662 #define STORMS_NUM 4
663 #define REGS_IN_ENTRY 4
664
665 static inline int bnx2x_get_assert_list_entry(struct bnx2x *bp,
666 enum storms storm,
667 int entry)
668 {
669 switch (storm) {
670 case XSTORM:
671 return XSTORM_ASSERT_LIST_OFFSET(entry);
672 case TSTORM:
673 return TSTORM_ASSERT_LIST_OFFSET(entry);
674 case CSTORM:
675 return CSTORM_ASSERT_LIST_OFFSET(entry);
676 case USTORM:
677 return USTORM_ASSERT_LIST_OFFSET(entry);
678 case MAX_STORMS:
679 default:
680 BNX2X_ERR("unknown storm\n");
681 }
682 return -EINVAL;
683 }
684
685 static int bnx2x_mc_assert(struct bnx2x *bp)
686 {
687 char last_idx;
688 int i, j, rc = 0;
689 enum storms storm;
690 u32 regs[REGS_IN_ENTRY];
691 u32 bar_storm_intmem[STORMS_NUM] = {
692 BAR_XSTRORM_INTMEM,
693 BAR_TSTRORM_INTMEM,
694 BAR_CSTRORM_INTMEM,
695 BAR_USTRORM_INTMEM
696 };
697 u32 storm_assert_list_index[STORMS_NUM] = {
698 XSTORM_ASSERT_LIST_INDEX_OFFSET,
699 TSTORM_ASSERT_LIST_INDEX_OFFSET,
700 CSTORM_ASSERT_LIST_INDEX_OFFSET,
701 USTORM_ASSERT_LIST_INDEX_OFFSET
702 };
703 char *storms_string[STORMS_NUM] = {
704 "XSTORM",
705 "TSTORM",
706 "CSTORM",
707 "USTORM"
708 };
709
710 for (storm = XSTORM; storm < MAX_STORMS; storm++) {
711 last_idx = REG_RD8(bp, bar_storm_intmem[storm] +
712 storm_assert_list_index[storm]);
713 if (last_idx)
714 BNX2X_ERR("%s_ASSERT_LIST_INDEX 0x%x\n",
715 storms_string[storm], last_idx);
716
717 /* print the asserts */
718 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
719 /* read a single assert entry */
720 for (j = 0; j < REGS_IN_ENTRY; j++)
721 regs[j] = REG_RD(bp, bar_storm_intmem[storm] +
722 bnx2x_get_assert_list_entry(bp,
723 storm,
724 i) +
725 sizeof(u32) * j);
726
727 /* log entry if it contains a valid assert */
728 if (regs[0] != COMMON_ASM_INVALID_ASSERT_OPCODE) {
729 BNX2X_ERR("%s_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
730 storms_string[storm], i, regs[3],
731 regs[2], regs[1], regs[0]);
732 rc++;
733 } else {
734 break;
735 }
736 }
737 }
738
739 BNX2X_ERR("Chip Revision: %s, FW Version: %d_%d_%d\n",
740 CHIP_IS_E1(bp) ? "everest1" :
741 CHIP_IS_E1H(bp) ? "everest1h" :
742 CHIP_IS_E2(bp) ? "everest2" : "everest3",
743 BCM_5710_FW_MAJOR_VERSION,
744 BCM_5710_FW_MINOR_VERSION,
745 BCM_5710_FW_REVISION_VERSION);
746
747 return rc;
748 }
749
750 #define MCPR_TRACE_BUFFER_SIZE (0x800)
751 #define SCRATCH_BUFFER_SIZE(bp) \
752 (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
753
754 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
755 {
756 u32 addr, val;
757 u32 mark, offset;
758 __be32 data[9];
759 int word;
760 u32 trace_shmem_base;
761 if (BP_NOMCP(bp)) {
762 BNX2X_ERR("NO MCP - can not dump\n");
763 return;
764 }
765 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
766 (bp->common.bc_ver & 0xff0000) >> 16,
767 (bp->common.bc_ver & 0xff00) >> 8,
768 (bp->common.bc_ver & 0xff));
769
770 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
771 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
772 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
773
774 if (BP_PATH(bp) == 0)
775 trace_shmem_base = bp->common.shmem_base;
776 else
777 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
778
779 /* sanity */
780 if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
781 trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
782 SCRATCH_BUFFER_SIZE(bp)) {
783 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
784 trace_shmem_base);
785 return;
786 }
787
788 addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
789
790 /* validate TRCB signature */
791 mark = REG_RD(bp, addr);
792 if (mark != MFW_TRACE_SIGNATURE) {
793 BNX2X_ERR("Trace buffer signature is missing.");
794 return ;
795 }
796
797 /* read cyclic buffer pointer */
798 addr += 4;
799 mark = REG_RD(bp, addr);
800 mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
801 if (mark >= trace_shmem_base || mark < addr + 4) {
802 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
803 return;
804 }
805 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
806
807 printk("%s", lvl);
808
809 /* dump buffer after the mark */
810 for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
811 for (word = 0; word < 8; word++)
812 data[word] = htonl(REG_RD(bp, offset + 4*word));
813 data[8] = 0x0;
814 pr_cont("%s", (char *)data);
815 }
816
817 /* dump buffer before the mark */
818 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
819 for (word = 0; word < 8; word++)
820 data[word] = htonl(REG_RD(bp, offset + 4*word));
821 data[8] = 0x0;
822 pr_cont("%s", (char *)data);
823 }
824 printk("%s" "end of fw dump\n", lvl);
825 }
826
827 static void bnx2x_fw_dump(struct bnx2x *bp)
828 {
829 bnx2x_fw_dump_lvl(bp, KERN_ERR);
830 }
831
832 static void bnx2x_hc_int_disable(struct bnx2x *bp)
833 {
834 int port = BP_PORT(bp);
835 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
836 u32 val = REG_RD(bp, addr);
837
838 /* in E1 we must use only PCI configuration space to disable
839 * MSI/MSIX capability
840 * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
841 */
842 if (CHIP_IS_E1(bp)) {
843 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
844 * Use mask register to prevent from HC sending interrupts
845 * after we exit the function
846 */
847 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
848
849 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
850 HC_CONFIG_0_REG_INT_LINE_EN_0 |
851 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
852 } else
853 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
854 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
855 HC_CONFIG_0_REG_INT_LINE_EN_0 |
856 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
857
858 DP(NETIF_MSG_IFDOWN,
859 "write %x to HC %d (addr 0x%x)\n",
860 val, port, addr);
861
862 /* flush all outstanding writes */
863 mmiowb();
864
865 REG_WR(bp, addr, val);
866 if (REG_RD(bp, addr) != val)
867 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
868 }
869
870 static void bnx2x_igu_int_disable(struct bnx2x *bp)
871 {
872 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
873
874 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
875 IGU_PF_CONF_INT_LINE_EN |
876 IGU_PF_CONF_ATTN_BIT_EN);
877
878 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
879
880 /* flush all outstanding writes */
881 mmiowb();
882
883 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
884 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
885 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
886 }
887
888 static void bnx2x_int_disable(struct bnx2x *bp)
889 {
890 if (bp->common.int_block == INT_BLOCK_HC)
891 bnx2x_hc_int_disable(bp);
892 else
893 bnx2x_igu_int_disable(bp);
894 }
895
896 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
897 {
898 int i;
899 u16 j;
900 struct hc_sp_status_block_data sp_sb_data;
901 int func = BP_FUNC(bp);
902 #ifdef BNX2X_STOP_ON_ERROR
903 u16 start = 0, end = 0;
904 u8 cos;
905 #endif
906 if (IS_PF(bp) && disable_int)
907 bnx2x_int_disable(bp);
908
909 bp->stats_state = STATS_STATE_DISABLED;
910 bp->eth_stats.unrecoverable_error++;
911 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
912
913 BNX2X_ERR("begin crash dump -----------------\n");
914
915 /* Indices */
916 /* Common */
917 if (IS_PF(bp)) {
918 struct host_sp_status_block *def_sb = bp->def_status_blk;
919 int data_size, cstorm_offset;
920
921 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
922 bp->def_idx, bp->def_att_idx, bp->attn_state,
923 bp->spq_prod_idx, bp->stats_counter);
924 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
925 def_sb->atten_status_block.attn_bits,
926 def_sb->atten_status_block.attn_bits_ack,
927 def_sb->atten_status_block.status_block_id,
928 def_sb->atten_status_block.attn_bits_index);
929 BNX2X_ERR(" def (");
930 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
931 pr_cont("0x%x%s",
932 def_sb->sp_sb.index_values[i],
933 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
934
935 data_size = sizeof(struct hc_sp_status_block_data) /
936 sizeof(u32);
937 cstorm_offset = CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func);
938 for (i = 0; i < data_size; i++)
939 *((u32 *)&sp_sb_data + i) =
940 REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset +
941 i * sizeof(u32));
942
943 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
944 sp_sb_data.igu_sb_id,
945 sp_sb_data.igu_seg_id,
946 sp_sb_data.p_func.pf_id,
947 sp_sb_data.p_func.vnic_id,
948 sp_sb_data.p_func.vf_id,
949 sp_sb_data.p_func.vf_valid,
950 sp_sb_data.state);
951 }
952
953 for_each_eth_queue(bp, i) {
954 struct bnx2x_fastpath *fp = &bp->fp[i];
955 int loop;
956 struct hc_status_block_data_e2 sb_data_e2;
957 struct hc_status_block_data_e1x sb_data_e1x;
958 struct hc_status_block_sm *hc_sm_p =
959 CHIP_IS_E1x(bp) ?
960 sb_data_e1x.common.state_machine :
961 sb_data_e2.common.state_machine;
962 struct hc_index_data *hc_index_p =
963 CHIP_IS_E1x(bp) ?
964 sb_data_e1x.index_data :
965 sb_data_e2.index_data;
966 u8 data_size, cos;
967 u32 *sb_data_p;
968 struct bnx2x_fp_txdata txdata;
969
970 if (!bp->fp)
971 break;
972
973 if (!fp->rx_cons_sb)
974 continue;
975
976 /* Rx */
977 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
978 i, fp->rx_bd_prod, fp->rx_bd_cons,
979 fp->rx_comp_prod,
980 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
981 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n",
982 fp->rx_sge_prod, fp->last_max_sge,
983 le16_to_cpu(fp->fp_hc_idx));
984
985 /* Tx */
986 for_each_cos_in_tx_queue(fp, cos)
987 {
988 if (!fp->txdata_ptr[cos])
989 break;
990
991 txdata = *fp->txdata_ptr[cos];
992
993 if (!txdata.tx_cons_sb)
994 continue;
995
996 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n",
997 i, txdata.tx_pkt_prod,
998 txdata.tx_pkt_cons, txdata.tx_bd_prod,
999 txdata.tx_bd_cons,
1000 le16_to_cpu(*txdata.tx_cons_sb));
1001 }
1002
1003 loop = CHIP_IS_E1x(bp) ?
1004 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
1005
1006 /* host sb data */
1007
1008 if (IS_FCOE_FP(fp))
1009 continue;
1010
1011 BNX2X_ERR(" run indexes (");
1012 for (j = 0; j < HC_SB_MAX_SM; j++)
1013 pr_cont("0x%x%s",
1014 fp->sb_running_index[j],
1015 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
1016
1017 BNX2X_ERR(" indexes (");
1018 for (j = 0; j < loop; j++)
1019 pr_cont("0x%x%s",
1020 fp->sb_index_values[j],
1021 (j == loop - 1) ? ")" : " ");
1022
1023 /* VF cannot access FW refelection for status block */
1024 if (IS_VF(bp))
1025 continue;
1026
1027 /* fw sb data */
1028 data_size = CHIP_IS_E1x(bp) ?
1029 sizeof(struct hc_status_block_data_e1x) :
1030 sizeof(struct hc_status_block_data_e2);
1031 data_size /= sizeof(u32);
1032 sb_data_p = CHIP_IS_E1x(bp) ?
1033 (u32 *)&sb_data_e1x :
1034 (u32 *)&sb_data_e2;
1035 /* copy sb data in here */
1036 for (j = 0; j < data_size; j++)
1037 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
1038 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1039 j * sizeof(u32));
1040
1041 if (!CHIP_IS_E1x(bp)) {
1042 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
1043 sb_data_e2.common.p_func.pf_id,
1044 sb_data_e2.common.p_func.vf_id,
1045 sb_data_e2.common.p_func.vf_valid,
1046 sb_data_e2.common.p_func.vnic_id,
1047 sb_data_e2.common.same_igu_sb_1b,
1048 sb_data_e2.common.state);
1049 } else {
1050 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
1051 sb_data_e1x.common.p_func.pf_id,
1052 sb_data_e1x.common.p_func.vf_id,
1053 sb_data_e1x.common.p_func.vf_valid,
1054 sb_data_e1x.common.p_func.vnic_id,
1055 sb_data_e1x.common.same_igu_sb_1b,
1056 sb_data_e1x.common.state);
1057 }
1058
1059 /* SB_SMs data */
1060 for (j = 0; j < HC_SB_MAX_SM; j++) {
1061 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1062 j, hc_sm_p[j].__flags,
1063 hc_sm_p[j].igu_sb_id,
1064 hc_sm_p[j].igu_seg_id,
1065 hc_sm_p[j].time_to_expire,
1066 hc_sm_p[j].timer_value);
1067 }
1068
1069 /* Indices data */
1070 for (j = 0; j < loop; j++) {
1071 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
1072 hc_index_p[j].flags,
1073 hc_index_p[j].timeout);
1074 }
1075 }
1076
1077 #ifdef BNX2X_STOP_ON_ERROR
1078 if (IS_PF(bp)) {
1079 /* event queue */
1080 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1081 for (i = 0; i < NUM_EQ_DESC; i++) {
1082 u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1083
1084 BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1085 i, bp->eq_ring[i].message.opcode,
1086 bp->eq_ring[i].message.error);
1087 BNX2X_ERR("data: %x %x %x\n",
1088 data[0], data[1], data[2]);
1089 }
1090 }
1091
1092 /* Rings */
1093 /* Rx */
1094 for_each_valid_rx_queue(bp, i) {
1095 struct bnx2x_fastpath *fp = &bp->fp[i];
1096
1097 if (!bp->fp)
1098 break;
1099
1100 if (!fp->rx_cons_sb)
1101 continue;
1102
1103 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1104 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1105 for (j = start; j != end; j = RX_BD(j + 1)) {
1106 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1107 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1108
1109 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
1110 i, j, rx_bd[1], rx_bd[0], sw_bd->data);
1111 }
1112
1113 start = RX_SGE(fp->rx_sge_prod);
1114 end = RX_SGE(fp->last_max_sge);
1115 for (j = start; j != end; j = RX_SGE(j + 1)) {
1116 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1117 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1118
1119 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
1120 i, j, rx_sge[1], rx_sge[0], sw_page->page);
1121 }
1122
1123 start = RCQ_BD(fp->rx_comp_cons - 10);
1124 end = RCQ_BD(fp->rx_comp_cons + 503);
1125 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1126 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1127
1128 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1129 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1130 }
1131 }
1132
1133 /* Tx */
1134 for_each_valid_tx_queue(bp, i) {
1135 struct bnx2x_fastpath *fp = &bp->fp[i];
1136
1137 if (!bp->fp)
1138 break;
1139
1140 for_each_cos_in_tx_queue(fp, cos) {
1141 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1142
1143 if (!fp->txdata_ptr[cos])
1144 break;
1145
1146 if (!txdata->tx_cons_sb)
1147 continue;
1148
1149 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1150 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1151 for (j = start; j != end; j = TX_BD(j + 1)) {
1152 struct sw_tx_bd *sw_bd =
1153 &txdata->tx_buf_ring[j];
1154
1155 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1156 i, cos, j, sw_bd->skb,
1157 sw_bd->first_bd);
1158 }
1159
1160 start = TX_BD(txdata->tx_bd_cons - 10);
1161 end = TX_BD(txdata->tx_bd_cons + 254);
1162 for (j = start; j != end; j = TX_BD(j + 1)) {
1163 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
1164
1165 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1166 i, cos, j, tx_bd[0], tx_bd[1],
1167 tx_bd[2], tx_bd[3]);
1168 }
1169 }
1170 }
1171 #endif
1172 if (IS_PF(bp)) {
1173 bnx2x_fw_dump(bp);
1174 bnx2x_mc_assert(bp);
1175 }
1176 BNX2X_ERR("end crash dump -----------------\n");
1177 }
1178
1179 /*
1180 * FLR Support for E2
1181 *
1182 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1183 * initialization.
1184 */
1185 #define FLR_WAIT_USEC 10000 /* 10 milliseconds */
1186 #define FLR_WAIT_INTERVAL 50 /* usec */
1187 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1188
1189 struct pbf_pN_buf_regs {
1190 int pN;
1191 u32 init_crd;
1192 u32 crd;
1193 u32 crd_freed;
1194 };
1195
1196 struct pbf_pN_cmd_regs {
1197 int pN;
1198 u32 lines_occup;
1199 u32 lines_freed;
1200 };
1201
1202 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1203 struct pbf_pN_buf_regs *regs,
1204 u32 poll_count)
1205 {
1206 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1207 u32 cur_cnt = poll_count;
1208
1209 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1210 crd = crd_start = REG_RD(bp, regs->crd);
1211 init_crd = REG_RD(bp, regs->init_crd);
1212
1213 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1214 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1215 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1216
1217 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1218 (init_crd - crd_start))) {
1219 if (cur_cnt--) {
1220 udelay(FLR_WAIT_INTERVAL);
1221 crd = REG_RD(bp, regs->crd);
1222 crd_freed = REG_RD(bp, regs->crd_freed);
1223 } else {
1224 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1225 regs->pN);
1226 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1227 regs->pN, crd);
1228 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1229 regs->pN, crd_freed);
1230 break;
1231 }
1232 }
1233 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1234 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1235 }
1236
1237 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1238 struct pbf_pN_cmd_regs *regs,
1239 u32 poll_count)
1240 {
1241 u32 occup, to_free, freed, freed_start;
1242 u32 cur_cnt = poll_count;
1243
1244 occup = to_free = REG_RD(bp, regs->lines_occup);
1245 freed = freed_start = REG_RD(bp, regs->lines_freed);
1246
1247 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1248 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1249
1250 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1251 if (cur_cnt--) {
1252 udelay(FLR_WAIT_INTERVAL);
1253 occup = REG_RD(bp, regs->lines_occup);
1254 freed = REG_RD(bp, regs->lines_freed);
1255 } else {
1256 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1257 regs->pN);
1258 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1259 regs->pN, occup);
1260 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1261 regs->pN, freed);
1262 break;
1263 }
1264 }
1265 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1266 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1267 }
1268
1269 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1270 u32 expected, u32 poll_count)
1271 {
1272 u32 cur_cnt = poll_count;
1273 u32 val;
1274
1275 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1276 udelay(FLR_WAIT_INTERVAL);
1277
1278 return val;
1279 }
1280
1281 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1282 char *msg, u32 poll_cnt)
1283 {
1284 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1285 if (val != 0) {
1286 BNX2X_ERR("%s usage count=%d\n", msg, val);
1287 return 1;
1288 }
1289 return 0;
1290 }
1291
1292 /* Common routines with VF FLR cleanup */
1293 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1294 {
1295 /* adjust polling timeout */
1296 if (CHIP_REV_IS_EMUL(bp))
1297 return FLR_POLL_CNT * 2000;
1298
1299 if (CHIP_REV_IS_FPGA(bp))
1300 return FLR_POLL_CNT * 120;
1301
1302 return FLR_POLL_CNT;
1303 }
1304
1305 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1306 {
1307 struct pbf_pN_cmd_regs cmd_regs[] = {
1308 {0, (CHIP_IS_E3B0(bp)) ?
1309 PBF_REG_TQ_OCCUPANCY_Q0 :
1310 PBF_REG_P0_TQ_OCCUPANCY,
1311 (CHIP_IS_E3B0(bp)) ?
1312 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1313 PBF_REG_P0_TQ_LINES_FREED_CNT},
1314 {1, (CHIP_IS_E3B0(bp)) ?
1315 PBF_REG_TQ_OCCUPANCY_Q1 :
1316 PBF_REG_P1_TQ_OCCUPANCY,
1317 (CHIP_IS_E3B0(bp)) ?
1318 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1319 PBF_REG_P1_TQ_LINES_FREED_CNT},
1320 {4, (CHIP_IS_E3B0(bp)) ?
1321 PBF_REG_TQ_OCCUPANCY_LB_Q :
1322 PBF_REG_P4_TQ_OCCUPANCY,
1323 (CHIP_IS_E3B0(bp)) ?
1324 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1325 PBF_REG_P4_TQ_LINES_FREED_CNT}
1326 };
1327
1328 struct pbf_pN_buf_regs buf_regs[] = {
1329 {0, (CHIP_IS_E3B0(bp)) ?
1330 PBF_REG_INIT_CRD_Q0 :
1331 PBF_REG_P0_INIT_CRD ,
1332 (CHIP_IS_E3B0(bp)) ?
1333 PBF_REG_CREDIT_Q0 :
1334 PBF_REG_P0_CREDIT,
1335 (CHIP_IS_E3B0(bp)) ?
1336 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1337 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1338 {1, (CHIP_IS_E3B0(bp)) ?
1339 PBF_REG_INIT_CRD_Q1 :
1340 PBF_REG_P1_INIT_CRD,
1341 (CHIP_IS_E3B0(bp)) ?
1342 PBF_REG_CREDIT_Q1 :
1343 PBF_REG_P1_CREDIT,
1344 (CHIP_IS_E3B0(bp)) ?
1345 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1346 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1347 {4, (CHIP_IS_E3B0(bp)) ?
1348 PBF_REG_INIT_CRD_LB_Q :
1349 PBF_REG_P4_INIT_CRD,
1350 (CHIP_IS_E3B0(bp)) ?
1351 PBF_REG_CREDIT_LB_Q :
1352 PBF_REG_P4_CREDIT,
1353 (CHIP_IS_E3B0(bp)) ?
1354 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1355 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1356 };
1357
1358 int i;
1359
1360 /* Verify the command queues are flushed P0, P1, P4 */
1361 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1362 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1363
1364 /* Verify the transmission buffers are flushed P0, P1, P4 */
1365 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1366 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1367 }
1368
1369 #define OP_GEN_PARAM(param) \
1370 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1371
1372 #define OP_GEN_TYPE(type) \
1373 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1374
1375 #define OP_GEN_AGG_VECT(index) \
1376 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1377
1378 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
1379 {
1380 u32 op_gen_command = 0;
1381 u32 comp_addr = BAR_CSTRORM_INTMEM +
1382 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1383 int ret = 0;
1384
1385 if (REG_RD(bp, comp_addr)) {
1386 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1387 return 1;
1388 }
1389
1390 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1391 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1392 op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1393 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1394
1395 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1396 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
1397
1398 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1399 BNX2X_ERR("FW final cleanup did not succeed\n");
1400 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1401 (REG_RD(bp, comp_addr)));
1402 bnx2x_panic();
1403 return 1;
1404 }
1405 /* Zero completion for next FLR */
1406 REG_WR(bp, comp_addr, 0);
1407
1408 return ret;
1409 }
1410
1411 u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1412 {
1413 u16 status;
1414
1415 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1416 return status & PCI_EXP_DEVSTA_TRPND;
1417 }
1418
1419 /* PF FLR specific routines
1420 */
1421 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1422 {
1423 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1424 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1425 CFC_REG_NUM_LCIDS_INSIDE_PF,
1426 "CFC PF usage counter timed out",
1427 poll_cnt))
1428 return 1;
1429
1430 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1431 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1432 DORQ_REG_PF_USAGE_CNT,
1433 "DQ PF usage counter timed out",
1434 poll_cnt))
1435 return 1;
1436
1437 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1438 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1439 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1440 "QM PF usage counter timed out",
1441 poll_cnt))
1442 return 1;
1443
1444 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1445 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1446 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1447 "Timers VNIC usage counter timed out",
1448 poll_cnt))
1449 return 1;
1450 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1451 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1452 "Timers NUM_SCANS usage counter timed out",
1453 poll_cnt))
1454 return 1;
1455
1456 /* Wait DMAE PF usage counter to zero */
1457 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1458 dmae_reg_go_c[INIT_DMAE_C(bp)],
1459 "DMAE command register timed out",
1460 poll_cnt))
1461 return 1;
1462
1463 return 0;
1464 }
1465
1466 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1467 {
1468 u32 val;
1469
1470 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1471 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1472
1473 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1474 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1475
1476 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1477 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1478
1479 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1480 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1481
1482 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1483 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1484
1485 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1486 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1487
1488 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1489 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1490
1491 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1492 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1493 val);
1494 }
1495
1496 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1497 {
1498 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1499
1500 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1501
1502 /* Re-enable PF target read access */
1503 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1504
1505 /* Poll HW usage counters */
1506 DP(BNX2X_MSG_SP, "Polling usage counters\n");
1507 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1508 return -EBUSY;
1509
1510 /* Zero the igu 'trailing edge' and 'leading edge' */
1511
1512 /* Send the FW cleanup command */
1513 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1514 return -EBUSY;
1515
1516 /* ATC cleanup */
1517
1518 /* Verify TX hw is flushed */
1519 bnx2x_tx_hw_flushed(bp, poll_cnt);
1520
1521 /* Wait 100ms (not adjusted according to platform) */
1522 msleep(100);
1523
1524 /* Verify no pending pci transactions */
1525 if (bnx2x_is_pcie_pending(bp->pdev))
1526 BNX2X_ERR("PCIE Transactions still pending\n");
1527
1528 /* Debug */
1529 bnx2x_hw_enable_status(bp);
1530
1531 /*
1532 * Master enable - Due to WB DMAE writes performed before this
1533 * register is re-initialized as part of the regular function init
1534 */
1535 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1536
1537 return 0;
1538 }
1539
1540 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1541 {
1542 int port = BP_PORT(bp);
1543 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1544 u32 val = REG_RD(bp, addr);
1545 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1546 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1547 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1548
1549 if (msix) {
1550 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1551 HC_CONFIG_0_REG_INT_LINE_EN_0);
1552 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1553 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1554 if (single_msix)
1555 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1556 } else if (msi) {
1557 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1558 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1559 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1560 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1561 } else {
1562 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1563 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1564 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1565 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1566
1567 if (!CHIP_IS_E1(bp)) {
1568 DP(NETIF_MSG_IFUP,
1569 "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1570
1571 REG_WR(bp, addr, val);
1572
1573 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1574 }
1575 }
1576
1577 if (CHIP_IS_E1(bp))
1578 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1579
1580 DP(NETIF_MSG_IFUP,
1581 "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1582 (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1583
1584 REG_WR(bp, addr, val);
1585 /*
1586 * Ensure that HC_CONFIG is written before leading/trailing edge config
1587 */
1588 mmiowb();
1589 barrier();
1590
1591 if (!CHIP_IS_E1(bp)) {
1592 /* init leading/trailing edge */
1593 if (IS_MF(bp)) {
1594 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1595 if (bp->port.pmf)
1596 /* enable nig and gpio3 attention */
1597 val |= 0x1100;
1598 } else
1599 val = 0xffff;
1600
1601 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1602 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1603 }
1604
1605 /* Make sure that interrupts are indeed enabled from here on */
1606 mmiowb();
1607 }
1608
1609 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1610 {
1611 u32 val;
1612 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1613 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1614 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1615
1616 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1617
1618 if (msix) {
1619 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1620 IGU_PF_CONF_SINGLE_ISR_EN);
1621 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1622 IGU_PF_CONF_ATTN_BIT_EN);
1623
1624 if (single_msix)
1625 val |= IGU_PF_CONF_SINGLE_ISR_EN;
1626 } else if (msi) {
1627 val &= ~IGU_PF_CONF_INT_LINE_EN;
1628 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1629 IGU_PF_CONF_ATTN_BIT_EN |
1630 IGU_PF_CONF_SINGLE_ISR_EN);
1631 } else {
1632 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1633 val |= (IGU_PF_CONF_INT_LINE_EN |
1634 IGU_PF_CONF_ATTN_BIT_EN |
1635 IGU_PF_CONF_SINGLE_ISR_EN);
1636 }
1637
1638 /* Clean previous status - need to configure igu prior to ack*/
1639 if ((!msix) || single_msix) {
1640 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1641 bnx2x_ack_int(bp);
1642 }
1643
1644 val |= IGU_PF_CONF_FUNC_EN;
1645
1646 DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n",
1647 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1648
1649 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1650
1651 if (val & IGU_PF_CONF_INT_LINE_EN)
1652 pci_intx(bp->pdev, true);
1653
1654 barrier();
1655
1656 /* init leading/trailing edge */
1657 if (IS_MF(bp)) {
1658 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1659 if (bp->port.pmf)
1660 /* enable nig and gpio3 attention */
1661 val |= 0x1100;
1662 } else
1663 val = 0xffff;
1664
1665 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1666 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1667
1668 /* Make sure that interrupts are indeed enabled from here on */
1669 mmiowb();
1670 }
1671
1672 void bnx2x_int_enable(struct bnx2x *bp)
1673 {
1674 if (bp->common.int_block == INT_BLOCK_HC)
1675 bnx2x_hc_int_enable(bp);
1676 else
1677 bnx2x_igu_int_enable(bp);
1678 }
1679
1680 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1681 {
1682 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1683 int i, offset;
1684
1685 if (disable_hw)
1686 /* prevent the HW from sending interrupts */
1687 bnx2x_int_disable(bp);
1688
1689 /* make sure all ISRs are done */
1690 if (msix) {
1691 synchronize_irq(bp->msix_table[0].vector);
1692 offset = 1;
1693 if (CNIC_SUPPORT(bp))
1694 offset++;
1695 for_each_eth_queue(bp, i)
1696 synchronize_irq(bp->msix_table[offset++].vector);
1697 } else
1698 synchronize_irq(bp->pdev->irq);
1699
1700 /* make sure sp_task is not running */
1701 cancel_delayed_work(&bp->sp_task);
1702 cancel_delayed_work(&bp->period_task);
1703 flush_workqueue(bnx2x_wq);
1704 }
1705
1706 /* fast path */
1707
1708 /*
1709 * General service functions
1710 */
1711
1712 /* Return true if succeeded to acquire the lock */
1713 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1714 {
1715 u32 lock_status;
1716 u32 resource_bit = (1 << resource);
1717 int func = BP_FUNC(bp);
1718 u32 hw_lock_control_reg;
1719
1720 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1721 "Trying to take a lock on resource %d\n", resource);
1722
1723 /* Validating that the resource is within range */
1724 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1725 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1726 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1727 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1728 return false;
1729 }
1730
1731 if (func <= 5)
1732 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1733 else
1734 hw_lock_control_reg =
1735 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1736
1737 /* Try to acquire the lock */
1738 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1739 lock_status = REG_RD(bp, hw_lock_control_reg);
1740 if (lock_status & resource_bit)
1741 return true;
1742
1743 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1744 "Failed to get a lock on resource %d\n", resource);
1745 return false;
1746 }
1747
1748 /**
1749 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1750 *
1751 * @bp: driver handle
1752 *
1753 * Returns the recovery leader resource id according to the engine this function
1754 * belongs to. Currently only only 2 engines is supported.
1755 */
1756 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1757 {
1758 if (BP_PATH(bp))
1759 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1760 else
1761 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1762 }
1763
1764 /**
1765 * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1766 *
1767 * @bp: driver handle
1768 *
1769 * Tries to acquire a leader lock for current engine.
1770 */
1771 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1772 {
1773 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1774 }
1775
1776 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1777
1778 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1779 static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1780 {
1781 /* Set the interrupt occurred bit for the sp-task to recognize it
1782 * must ack the interrupt and transition according to the IGU
1783 * state machine.
1784 */
1785 atomic_set(&bp->interrupt_occurred, 1);
1786
1787 /* The sp_task must execute only after this bit
1788 * is set, otherwise we will get out of sync and miss all
1789 * further interrupts. Hence, the barrier.
1790 */
1791 smp_wmb();
1792
1793 /* schedule sp_task to workqueue */
1794 return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1795 }
1796
1797 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1798 {
1799 struct bnx2x *bp = fp->bp;
1800 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1801 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1802 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1803 struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1804
1805 DP(BNX2X_MSG_SP,
1806 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1807 fp->index, cid, command, bp->state,
1808 rr_cqe->ramrod_cqe.ramrod_type);
1809
1810 /* If cid is within VF range, replace the slowpath object with the
1811 * one corresponding to this VF
1812 */
1813 if (cid >= BNX2X_FIRST_VF_CID &&
1814 cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1815 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1816
1817 switch (command) {
1818 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1819 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1820 drv_cmd = BNX2X_Q_CMD_UPDATE;
1821 break;
1822
1823 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1824 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1825 drv_cmd = BNX2X_Q_CMD_SETUP;
1826 break;
1827
1828 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1829 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1830 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1831 break;
1832
1833 case (RAMROD_CMD_ID_ETH_HALT):
1834 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1835 drv_cmd = BNX2X_Q_CMD_HALT;
1836 break;
1837
1838 case (RAMROD_CMD_ID_ETH_TERMINATE):
1839 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
1840 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1841 break;
1842
1843 case (RAMROD_CMD_ID_ETH_EMPTY):
1844 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1845 drv_cmd = BNX2X_Q_CMD_EMPTY;
1846 break;
1847
1848 case (RAMROD_CMD_ID_ETH_TPA_UPDATE):
1849 DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid);
1850 drv_cmd = BNX2X_Q_CMD_UPDATE_TPA;
1851 break;
1852
1853 default:
1854 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1855 command, fp->index);
1856 return;
1857 }
1858
1859 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1860 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1861 /* q_obj->complete_cmd() failure means that this was
1862 * an unexpected completion.
1863 *
1864 * In this case we don't want to increase the bp->spq_left
1865 * because apparently we haven't sent this command the first
1866 * place.
1867 */
1868 #ifdef BNX2X_STOP_ON_ERROR
1869 bnx2x_panic();
1870 #else
1871 return;
1872 #endif
1873
1874 smp_mb__before_atomic();
1875 atomic_inc(&bp->cq_spq_left);
1876 /* push the change in bp->spq_left and towards the memory */
1877 smp_mb__after_atomic();
1878
1879 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1880
1881 if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1882 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1883 /* if Q update ramrod is completed for last Q in AFEX vif set
1884 * flow, then ACK MCP at the end
1885 *
1886 * mark pending ACK to MCP bit.
1887 * prevent case that both bits are cleared.
1888 * At the end of load/unload driver checks that
1889 * sp_state is cleared, and this order prevents
1890 * races
1891 */
1892 smp_mb__before_atomic();
1893 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1894 wmb();
1895 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1896 smp_mb__after_atomic();
1897
1898 /* schedule the sp task as mcp ack is required */
1899 bnx2x_schedule_sp_task(bp);
1900 }
1901
1902 return;
1903 }
1904
1905 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1906 {
1907 struct bnx2x *bp = netdev_priv(dev_instance);
1908 u16 status = bnx2x_ack_int(bp);
1909 u16 mask;
1910 int i;
1911 u8 cos;
1912
1913 /* Return here if interrupt is shared and it's not for us */
1914 if (unlikely(status == 0)) {
1915 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1916 return IRQ_NONE;
1917 }
1918 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
1919
1920 #ifdef BNX2X_STOP_ON_ERROR
1921 if (unlikely(bp->panic))
1922 return IRQ_HANDLED;
1923 #endif
1924
1925 for_each_eth_queue(bp, i) {
1926 struct bnx2x_fastpath *fp = &bp->fp[i];
1927
1928 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1929 if (status & mask) {
1930 /* Handle Rx or Tx according to SB id */
1931 for_each_cos_in_tx_queue(fp, cos)
1932 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1933 prefetch(&fp->sb_running_index[SM_RX_ID]);
1934 napi_schedule_irqoff(&bnx2x_fp(bp, fp->index, napi));
1935 status &= ~mask;
1936 }
1937 }
1938
1939 if (CNIC_SUPPORT(bp)) {
1940 mask = 0x2;
1941 if (status & (mask | 0x1)) {
1942 struct cnic_ops *c_ops = NULL;
1943
1944 rcu_read_lock();
1945 c_ops = rcu_dereference(bp->cnic_ops);
1946 if (c_ops && (bp->cnic_eth_dev.drv_state &
1947 CNIC_DRV_STATE_HANDLES_IRQ))
1948 c_ops->cnic_handler(bp->cnic_data, NULL);
1949 rcu_read_unlock();
1950
1951 status &= ~mask;
1952 }
1953 }
1954
1955 if (unlikely(status & 0x1)) {
1956
1957 /* schedule sp task to perform default status block work, ack
1958 * attentions and enable interrupts.
1959 */
1960 bnx2x_schedule_sp_task(bp);
1961
1962 status &= ~0x1;
1963 if (!status)
1964 return IRQ_HANDLED;
1965 }
1966
1967 if (unlikely(status))
1968 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1969 status);
1970
1971 return IRQ_HANDLED;
1972 }
1973
1974 /* Link */
1975
1976 /*
1977 * General service functions
1978 */
1979
1980 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1981 {
1982 u32 lock_status;
1983 u32 resource_bit = (1 << resource);
1984 int func = BP_FUNC(bp);
1985 u32 hw_lock_control_reg;
1986 int cnt;
1987
1988 /* Validating that the resource is within range */
1989 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1990 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1991 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1992 return -EINVAL;
1993 }
1994
1995 if (func <= 5) {
1996 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1997 } else {
1998 hw_lock_control_reg =
1999 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2000 }
2001
2002 /* Validating that the resource is not already taken */
2003 lock_status = REG_RD(bp, hw_lock_control_reg);
2004 if (lock_status & resource_bit) {
2005 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n",
2006 lock_status, resource_bit);
2007 return -EEXIST;
2008 }
2009
2010 /* Try for 5 second every 5ms */
2011 for (cnt = 0; cnt < 1000; cnt++) {
2012 /* Try to acquire the lock */
2013 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
2014 lock_status = REG_RD(bp, hw_lock_control_reg);
2015 if (lock_status & resource_bit)
2016 return 0;
2017
2018 usleep_range(5000, 10000);
2019 }
2020 BNX2X_ERR("Timeout\n");
2021 return -EAGAIN;
2022 }
2023
2024 int bnx2x_release_leader_lock(struct bnx2x *bp)
2025 {
2026 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
2027 }
2028
2029 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
2030 {
2031 u32 lock_status;
2032 u32 resource_bit = (1 << resource);
2033 int func = BP_FUNC(bp);
2034 u32 hw_lock_control_reg;
2035
2036 /* Validating that the resource is within range */
2037 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
2038 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
2039 resource, HW_LOCK_MAX_RESOURCE_VALUE);
2040 return -EINVAL;
2041 }
2042
2043 if (func <= 5) {
2044 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2045 } else {
2046 hw_lock_control_reg =
2047 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2048 }
2049
2050 /* Validating that the resource is currently taken */
2051 lock_status = REG_RD(bp, hw_lock_control_reg);
2052 if (!(lock_status & resource_bit)) {
2053 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2054 lock_status, resource_bit);
2055 return -EFAULT;
2056 }
2057
2058 REG_WR(bp, hw_lock_control_reg, resource_bit);
2059 return 0;
2060 }
2061
2062 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2063 {
2064 /* The GPIO should be swapped if swap register is set and active */
2065 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2066 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2067 int gpio_shift = gpio_num +
2068 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2069 u32 gpio_mask = (1 << gpio_shift);
2070 u32 gpio_reg;
2071 int value;
2072
2073 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2074 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2075 return -EINVAL;
2076 }
2077
2078 /* read GPIO value */
2079 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2080
2081 /* get the requested pin value */
2082 if ((gpio_reg & gpio_mask) == gpio_mask)
2083 value = 1;
2084 else
2085 value = 0;
2086
2087 return value;
2088 }
2089
2090 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2091 {
2092 /* The GPIO should be swapped if swap register is set and active */
2093 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2094 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2095 int gpio_shift = gpio_num +
2096 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2097 u32 gpio_mask = (1 << gpio_shift);
2098 u32 gpio_reg;
2099
2100 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2101 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2102 return -EINVAL;
2103 }
2104
2105 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2106 /* read GPIO and mask except the float bits */
2107 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2108
2109 switch (mode) {
2110 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2111 DP(NETIF_MSG_LINK,
2112 "Set GPIO %d (shift %d) -> output low\n",
2113 gpio_num, gpio_shift);
2114 /* clear FLOAT and set CLR */
2115 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2116 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2117 break;
2118
2119 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2120 DP(NETIF_MSG_LINK,
2121 "Set GPIO %d (shift %d) -> output high\n",
2122 gpio_num, gpio_shift);
2123 /* clear FLOAT and set SET */
2124 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2125 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2126 break;
2127
2128 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2129 DP(NETIF_MSG_LINK,
2130 "Set GPIO %d (shift %d) -> input\n",
2131 gpio_num, gpio_shift);
2132 /* set FLOAT */
2133 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2134 break;
2135
2136 default:
2137 break;
2138 }
2139
2140 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2141 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2142
2143 return 0;
2144 }
2145
2146 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2147 {
2148 u32 gpio_reg = 0;
2149 int rc = 0;
2150
2151 /* Any port swapping should be handled by caller. */
2152
2153 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2154 /* read GPIO and mask except the float bits */
2155 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2156 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2157 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2158 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2159
2160 switch (mode) {
2161 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2162 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2163 /* set CLR */
2164 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2165 break;
2166
2167 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2168 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2169 /* set SET */
2170 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2171 break;
2172
2173 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2174 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2175 /* set FLOAT */
2176 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2177 break;
2178
2179 default:
2180 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2181 rc = -EINVAL;
2182 break;
2183 }
2184
2185 if (rc == 0)
2186 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2187
2188 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2189
2190 return rc;
2191 }
2192
2193 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2194 {
2195 /* The GPIO should be swapped if swap register is set and active */
2196 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2197 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2198 int gpio_shift = gpio_num +
2199 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2200 u32 gpio_mask = (1 << gpio_shift);
2201 u32 gpio_reg;
2202
2203 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2204 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2205 return -EINVAL;
2206 }
2207
2208 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2209 /* read GPIO int */
2210 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2211
2212 switch (mode) {
2213 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2214 DP(NETIF_MSG_LINK,
2215 "Clear GPIO INT %d (shift %d) -> output low\n",
2216 gpio_num, gpio_shift);
2217 /* clear SET and set CLR */
2218 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2219 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2220 break;
2221
2222 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2223 DP(NETIF_MSG_LINK,
2224 "Set GPIO INT %d (shift %d) -> output high\n",
2225 gpio_num, gpio_shift);
2226 /* clear CLR and set SET */
2227 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2228 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2229 break;
2230
2231 default:
2232 break;
2233 }
2234
2235 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2236 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2237
2238 return 0;
2239 }
2240
2241 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2242 {
2243 u32 spio_reg;
2244
2245 /* Only 2 SPIOs are configurable */
2246 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2247 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2248 return -EINVAL;
2249 }
2250
2251 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2252 /* read SPIO and mask except the float bits */
2253 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2254
2255 switch (mode) {
2256 case MISC_SPIO_OUTPUT_LOW:
2257 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2258 /* clear FLOAT and set CLR */
2259 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2260 spio_reg |= (spio << MISC_SPIO_CLR_POS);
2261 break;
2262
2263 case MISC_SPIO_OUTPUT_HIGH:
2264 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2265 /* clear FLOAT and set SET */
2266 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2267 spio_reg |= (spio << MISC_SPIO_SET_POS);
2268 break;
2269
2270 case MISC_SPIO_INPUT_HI_Z:
2271 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2272 /* set FLOAT */
2273 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2274 break;
2275
2276 default:
2277 break;
2278 }
2279
2280 REG_WR(bp, MISC_REG_SPIO, spio_reg);
2281 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2282
2283 return 0;
2284 }
2285
2286 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2287 {
2288 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2289 switch (bp->link_vars.ieee_fc &
2290 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2291 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2292 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2293 ADVERTISED_Pause);
2294 break;
2295
2296 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2297 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2298 ADVERTISED_Pause);
2299 break;
2300
2301 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2302 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2303 break;
2304
2305 default:
2306 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2307 ADVERTISED_Pause);
2308 break;
2309 }
2310 }
2311
2312 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2313 {
2314 /* Initialize link parameters structure variables
2315 * It is recommended to turn off RX FC for jumbo frames
2316 * for better performance
2317 */
2318 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2319 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2320 else
2321 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2322 }
2323
2324 static void bnx2x_init_dropless_fc(struct bnx2x *bp)
2325 {
2326 u32 pause_enabled = 0;
2327
2328 if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
2329 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2330 pause_enabled = 1;
2331
2332 REG_WR(bp, BAR_USTRORM_INTMEM +
2333 USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2334 pause_enabled);
2335 }
2336
2337 DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
2338 pause_enabled ? "enabled" : "disabled");
2339 }
2340
2341 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2342 {
2343 int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2344 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2345
2346 if (!BP_NOMCP(bp)) {
2347 bnx2x_set_requested_fc(bp);
2348 bnx2x_acquire_phy_lock(bp);
2349
2350 if (load_mode == LOAD_DIAG) {
2351 struct link_params *lp = &bp->link_params;
2352 lp->loopback_mode = LOOPBACK_XGXS;
2353 /* do PHY loopback at 10G speed, if possible */
2354 if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2355 if (lp->speed_cap_mask[cfx_idx] &
2356 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2357 lp->req_line_speed[cfx_idx] =
2358 SPEED_10000;
2359 else
2360 lp->req_line_speed[cfx_idx] =
2361 SPEED_1000;
2362 }
2363 }
2364
2365 if (load_mode == LOAD_LOOPBACK_EXT) {
2366 struct link_params *lp = &bp->link_params;
2367 lp->loopback_mode = LOOPBACK_EXT;
2368 }
2369
2370 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2371
2372 bnx2x_release_phy_lock(bp);
2373
2374 bnx2x_init_dropless_fc(bp);
2375
2376 bnx2x_calc_fc_adv(bp);
2377
2378 if (bp->link_vars.link_up) {
2379 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2380 bnx2x_link_report(bp);
2381 }
2382 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2383 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2384 return rc;
2385 }
2386 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2387 return -EINVAL;
2388 }
2389
2390 void bnx2x_link_set(struct bnx2x *bp)
2391 {
2392 if (!BP_NOMCP(bp)) {
2393 bnx2x_acquire_phy_lock(bp);
2394 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2395 bnx2x_release_phy_lock(bp);
2396
2397 bnx2x_init_dropless_fc(bp);
2398
2399 bnx2x_calc_fc_adv(bp);
2400 } else
2401 BNX2X_ERR("Bootcode is missing - can not set link\n");
2402 }
2403
2404 static void bnx2x__link_reset(struct bnx2x *bp)
2405 {
2406 if (!BP_NOMCP(bp)) {
2407 bnx2x_acquire_phy_lock(bp);
2408 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2409 bnx2x_release_phy_lock(bp);
2410 } else
2411 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2412 }
2413
2414 void bnx2x_force_link_reset(struct bnx2x *bp)
2415 {
2416 bnx2x_acquire_phy_lock(bp);
2417 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2418 bnx2x_release_phy_lock(bp);
2419 }
2420
2421 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2422 {
2423 u8 rc = 0;
2424
2425 if (!BP_NOMCP(bp)) {
2426 bnx2x_acquire_phy_lock(bp);
2427 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2428 is_serdes);
2429 bnx2x_release_phy_lock(bp);
2430 } else
2431 BNX2X_ERR("Bootcode is missing - can not test link\n");
2432
2433 return rc;
2434 }
2435
2436 /* Calculates the sum of vn_min_rates.
2437 It's needed for further normalizing of the min_rates.
2438 Returns:
2439 sum of vn_min_rates.
2440 or
2441 0 - if all the min_rates are 0.
2442 In the later case fairness algorithm should be deactivated.
2443 If not all min_rates are zero then those that are zeroes will be set to 1.
2444 */
2445 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2446 struct cmng_init_input *input)
2447 {
2448 int all_zero = 1;
2449 int vn;
2450
2451 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2452 u32 vn_cfg = bp->mf_config[vn];
2453 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2454 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2455
2456 /* Skip hidden vns */
2457 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2458 vn_min_rate = 0;
2459 /* If min rate is zero - set it to 1 */
2460 else if (!vn_min_rate)
2461 vn_min_rate = DEF_MIN_RATE;
2462 else
2463 all_zero = 0;
2464
2465 input->vnic_min_rate[vn] = vn_min_rate;
2466 }
2467
2468 /* if ETS or all min rates are zeros - disable fairness */
2469 if (BNX2X_IS_ETS_ENABLED(bp)) {
2470 input->flags.cmng_enables &=
2471 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2472 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2473 } else if (all_zero) {
2474 input->flags.cmng_enables &=
2475 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2476 DP(NETIF_MSG_IFUP,
2477 "All MIN values are zeroes fairness will be disabled\n");
2478 } else
2479 input->flags.cmng_enables |=
2480 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2481 }
2482
2483 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2484 struct cmng_init_input *input)
2485 {
2486 u16 vn_max_rate;
2487 u32 vn_cfg = bp->mf_config[vn];
2488
2489 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2490 vn_max_rate = 0;
2491 else {
2492 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2493
2494 if (IS_MF_SI(bp)) {
2495 /* maxCfg in percents of linkspeed */
2496 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2497 } else /* SD modes */
2498 /* maxCfg is absolute in 100Mb units */
2499 vn_max_rate = maxCfg * 100;
2500 }
2501
2502 DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2503
2504 input->vnic_max_rate[vn] = vn_max_rate;
2505 }
2506
2507 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2508 {
2509 if (CHIP_REV_IS_SLOW(bp))
2510 return CMNG_FNS_NONE;
2511 if (IS_MF(bp))
2512 return CMNG_FNS_MINMAX;
2513
2514 return CMNG_FNS_NONE;
2515 }
2516
2517 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2518 {
2519 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2520
2521 if (BP_NOMCP(bp))
2522 return; /* what should be the default value in this case */
2523
2524 /* For 2 port configuration the absolute function number formula
2525 * is:
2526 * abs_func = 2 * vn + BP_PORT + BP_PATH
2527 *
2528 * and there are 4 functions per port
2529 *
2530 * For 4 port configuration it is
2531 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2532 *
2533 * and there are 2 functions per port
2534 */
2535 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2536 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2537
2538 if (func >= E1H_FUNC_MAX)
2539 break;
2540
2541 bp->mf_config[vn] =
2542 MF_CFG_RD(bp, func_mf_config[func].config);
2543 }
2544 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2545 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2546 bp->flags |= MF_FUNC_DIS;
2547 } else {
2548 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2549 bp->flags &= ~MF_FUNC_DIS;
2550 }
2551 }
2552
2553 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2554 {
2555 struct cmng_init_input input;
2556 memset(&input, 0, sizeof(struct cmng_init_input));
2557
2558 input.port_rate = bp->link_vars.line_speed;
2559
2560 if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
2561 int vn;
2562
2563 /* read mf conf from shmem */
2564 if (read_cfg)
2565 bnx2x_read_mf_cfg(bp);
2566
2567 /* vn_weight_sum and enable fairness if not 0 */
2568 bnx2x_calc_vn_min(bp, &input);
2569
2570 /* calculate and set min-max rate for each vn */
2571 if (bp->port.pmf)
2572 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2573 bnx2x_calc_vn_max(bp, vn, &input);
2574
2575 /* always enable rate shaping and fairness */
2576 input.flags.cmng_enables |=
2577 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2578
2579 bnx2x_init_cmng(&input, &bp->cmng);
2580 return;
2581 }
2582
2583 /* rate shaping and fairness are disabled */
2584 DP(NETIF_MSG_IFUP,
2585 "rate shaping and fairness are disabled\n");
2586 }
2587
2588 static void storm_memset_cmng(struct bnx2x *bp,
2589 struct cmng_init *cmng,
2590 u8 port)
2591 {
2592 int vn;
2593 size_t size = sizeof(struct cmng_struct_per_port);
2594
2595 u32 addr = BAR_XSTRORM_INTMEM +
2596 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2597
2598 __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2599
2600 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2601 int func = func_by_vn(bp, vn);
2602
2603 addr = BAR_XSTRORM_INTMEM +
2604 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2605 size = sizeof(struct rate_shaping_vars_per_vn);
2606 __storm_memset_struct(bp, addr, size,
2607 (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2608
2609 addr = BAR_XSTRORM_INTMEM +
2610 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2611 size = sizeof(struct fairness_vars_per_vn);
2612 __storm_memset_struct(bp, addr, size,
2613 (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2614 }
2615 }
2616
2617 /* init cmng mode in HW according to local configuration */
2618 void bnx2x_set_local_cmng(struct bnx2x *bp)
2619 {
2620 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2621
2622 if (cmng_fns != CMNG_FNS_NONE) {
2623 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2624 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2625 } else {
2626 /* rate shaping and fairness are disabled */
2627 DP(NETIF_MSG_IFUP,
2628 "single function mode without fairness\n");
2629 }
2630 }
2631
2632 /* This function is called upon link interrupt */
2633 static void bnx2x_link_attn(struct bnx2x *bp)
2634 {
2635 /* Make sure that we are synced with the current statistics */
2636 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2637
2638 bnx2x_link_update(&bp->link_params, &bp->link_vars);
2639
2640 bnx2x_init_dropless_fc(bp);
2641
2642 if (bp->link_vars.link_up) {
2643
2644 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2645 struct host_port_stats *pstats;
2646
2647 pstats = bnx2x_sp(bp, port_stats);
2648 /* reset old mac stats */
2649 memset(&(pstats->mac_stx[0]), 0,
2650 sizeof(struct mac_stx));
2651 }
2652 if (bp->state == BNX2X_STATE_OPEN)
2653 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2654 }
2655
2656 if (bp->link_vars.link_up && bp->link_vars.line_speed)
2657 bnx2x_set_local_cmng(bp);
2658
2659 __bnx2x_link_report(bp);
2660
2661 if (IS_MF(bp))
2662 bnx2x_link_sync_notify(bp);
2663 }
2664
2665 void bnx2x__link_status_update(struct bnx2x *bp)
2666 {
2667 if (bp->state != BNX2X_STATE_OPEN)
2668 return;
2669
2670 /* read updated dcb configuration */
2671 if (IS_PF(bp)) {
2672 bnx2x_dcbx_pmf_update(bp);
2673 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2674 if (bp->link_vars.link_up)
2675 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2676 else
2677 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2678 /* indicate link status */
2679 bnx2x_link_report(bp);
2680
2681 } else { /* VF */
2682 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2683 SUPPORTED_10baseT_Full |
2684 SUPPORTED_100baseT_Half |
2685 SUPPORTED_100baseT_Full |
2686 SUPPORTED_1000baseT_Full |
2687 SUPPORTED_2500baseX_Full |
2688 SUPPORTED_10000baseT_Full |
2689 SUPPORTED_TP |
2690 SUPPORTED_FIBRE |
2691 SUPPORTED_Autoneg |
2692 SUPPORTED_Pause |
2693 SUPPORTED_Asym_Pause);
2694 bp->port.advertising[0] = bp->port.supported[0];
2695
2696 bp->link_params.bp = bp;
2697 bp->link_params.port = BP_PORT(bp);
2698 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2699 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2700 bp->link_params.req_line_speed[0] = SPEED_10000;
2701 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2702 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2703 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2704 bp->link_vars.line_speed = SPEED_10000;
2705 bp->link_vars.link_status =
2706 (LINK_STATUS_LINK_UP |
2707 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2708 bp->link_vars.link_up = 1;
2709 bp->link_vars.duplex = DUPLEX_FULL;
2710 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2711 __bnx2x_link_report(bp);
2712
2713 bnx2x_sample_bulletin(bp);
2714
2715 /* if bulletin board did not have an update for link status
2716 * __bnx2x_link_report will report current status
2717 * but it will NOT duplicate report in case of already reported
2718 * during sampling bulletin board.
2719 */
2720 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2721 }
2722 }
2723
2724 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2725 u16 vlan_val, u8 allowed_prio)
2726 {
2727 struct bnx2x_func_state_params func_params = {NULL};
2728 struct bnx2x_func_afex_update_params *f_update_params =
2729 &func_params.params.afex_update;
2730
2731 func_params.f_obj = &bp->func_obj;
2732 func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2733
2734 /* no need to wait for RAMROD completion, so don't
2735 * set RAMROD_COMP_WAIT flag
2736 */
2737
2738 f_update_params->vif_id = vifid;
2739 f_update_params->afex_default_vlan = vlan_val;
2740 f_update_params->allowed_priorities = allowed_prio;
2741
2742 /* if ramrod can not be sent, response to MCP immediately */
2743 if (bnx2x_func_state_change(bp, &func_params) < 0)
2744 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2745
2746 return 0;
2747 }
2748
2749 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2750 u16 vif_index, u8 func_bit_map)
2751 {
2752 struct bnx2x_func_state_params func_params = {NULL};
2753 struct bnx2x_func_afex_viflists_params *update_params =
2754 &func_params.params.afex_viflists;
2755 int rc;
2756 u32 drv_msg_code;
2757
2758 /* validate only LIST_SET and LIST_GET are received from switch */
2759 if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2760 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2761 cmd_type);
2762
2763 func_params.f_obj = &bp->func_obj;
2764 func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2765
2766 /* set parameters according to cmd_type */
2767 update_params->afex_vif_list_command = cmd_type;
2768 update_params->vif_list_index = vif_index;
2769 update_params->func_bit_map =
2770 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2771 update_params->func_to_clear = 0;
2772 drv_msg_code =
2773 (cmd_type == VIF_LIST_RULE_GET) ?
2774 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2775 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2776
2777 /* if ramrod can not be sent, respond to MCP immediately for
2778 * SET and GET requests (other are not triggered from MCP)
2779 */
2780 rc = bnx2x_func_state_change(bp, &func_params);
2781 if (rc < 0)
2782 bnx2x_fw_command(bp, drv_msg_code, 0);
2783
2784 return 0;
2785 }
2786
2787 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2788 {
2789 struct afex_stats afex_stats;
2790 u32 func = BP_ABS_FUNC(bp);
2791 u32 mf_config;
2792 u16 vlan_val;
2793 u32 vlan_prio;
2794 u16 vif_id;
2795 u8 allowed_prio;
2796 u8 vlan_mode;
2797 u32 addr_to_write, vifid, addrs, stats_type, i;
2798
2799 if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2800 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2801 DP(BNX2X_MSG_MCP,
2802 "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2803 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2804 }
2805
2806 if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2807 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2808 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2809 DP(BNX2X_MSG_MCP,
2810 "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2811 vifid, addrs);
2812 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2813 addrs);
2814 }
2815
2816 if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2817 addr_to_write = SHMEM2_RD(bp,
2818 afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2819 stats_type = SHMEM2_RD(bp,
2820 afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2821
2822 DP(BNX2X_MSG_MCP,
2823 "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2824 addr_to_write);
2825
2826 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2827
2828 /* write response to scratchpad, for MCP */
2829 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2830 REG_WR(bp, addr_to_write + i*sizeof(u32),
2831 *(((u32 *)(&afex_stats))+i));
2832
2833 /* send ack message to MCP */
2834 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2835 }
2836
2837 if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2838 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2839 bp->mf_config[BP_VN(bp)] = mf_config;
2840 DP(BNX2X_MSG_MCP,
2841 "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2842 mf_config);
2843
2844 /* if VIF_SET is "enabled" */
2845 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2846 /* set rate limit directly to internal RAM */
2847 struct cmng_init_input cmng_input;
2848 struct rate_shaping_vars_per_vn m_rs_vn;
2849 size_t size = sizeof(struct rate_shaping_vars_per_vn);
2850 u32 addr = BAR_XSTRORM_INTMEM +
2851 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2852
2853 bp->mf_config[BP_VN(bp)] = mf_config;
2854
2855 bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2856 m_rs_vn.vn_counter.rate =
2857 cmng_input.vnic_max_rate[BP_VN(bp)];
2858 m_rs_vn.vn_counter.quota =
2859 (m_rs_vn.vn_counter.rate *
2860 RS_PERIODIC_TIMEOUT_USEC) / 8;
2861
2862 __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2863
2864 /* read relevant values from mf_cfg struct in shmem */
2865 vif_id =
2866 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2867 FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2868 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2869 vlan_val =
2870 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2871 FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2872 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2873 vlan_prio = (mf_config &
2874 FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2875 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2876 vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2877 vlan_mode =
2878 (MF_CFG_RD(bp,
2879 func_mf_config[func].afex_config) &
2880 FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2881 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2882 allowed_prio =
2883 (MF_CFG_RD(bp,
2884 func_mf_config[func].afex_config) &
2885 FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2886 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2887
2888 /* send ramrod to FW, return in case of failure */
2889 if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2890 allowed_prio))
2891 return;
2892
2893 bp->afex_def_vlan_tag = vlan_val;
2894 bp->afex_vlan_mode = vlan_mode;
2895 } else {
2896 /* notify link down because BP->flags is disabled */
2897 bnx2x_link_report(bp);
2898
2899 /* send INVALID VIF ramrod to FW */
2900 bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2901
2902 /* Reset the default afex VLAN */
2903 bp->afex_def_vlan_tag = -1;
2904 }
2905 }
2906 }
2907
2908 static void bnx2x_handle_update_svid_cmd(struct bnx2x *bp)
2909 {
2910 struct bnx2x_func_switch_update_params *switch_update_params;
2911 struct bnx2x_func_state_params func_params;
2912
2913 memset(&func_params, 0, sizeof(struct bnx2x_func_state_params));
2914 switch_update_params = &func_params.params.switch_update;
2915 func_params.f_obj = &bp->func_obj;
2916 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
2917
2918 if (IS_MF_UFP(bp)) {
2919 int func = BP_ABS_FUNC(bp);
2920 u32 val;
2921
2922 /* Re-learn the S-tag from shmem */
2923 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2924 FUNC_MF_CFG_E1HOV_TAG_MASK;
2925 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
2926 bp->mf_ov = val;
2927 } else {
2928 BNX2X_ERR("Got an SVID event, but no tag is configured in shmem\n");
2929 goto fail;
2930 }
2931
2932 /* Configure new S-tag in LLH */
2933 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + BP_PORT(bp) * 8,
2934 bp->mf_ov);
2935
2936 /* Send Ramrod to update FW of change */
2937 __set_bit(BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG,
2938 &switch_update_params->changes);
2939 switch_update_params->vlan = bp->mf_ov;
2940
2941 if (bnx2x_func_state_change(bp, &func_params) < 0) {
2942 BNX2X_ERR("Failed to configure FW of S-tag Change to %02x\n",
2943 bp->mf_ov);
2944 goto fail;
2945 }
2946
2947 DP(BNX2X_MSG_MCP, "Configured S-tag %02x\n", bp->mf_ov);
2948
2949 bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_OK, 0);
2950
2951 return;
2952 }
2953
2954 /* not supported by SW yet */
2955 fail:
2956 bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE, 0);
2957 }
2958
2959 static void bnx2x_pmf_update(struct bnx2x *bp)
2960 {
2961 int port = BP_PORT(bp);
2962 u32 val;
2963
2964 bp->port.pmf = 1;
2965 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2966
2967 /*
2968 * We need the mb() to ensure the ordering between the writing to
2969 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2970 */
2971 smp_mb();
2972
2973 /* queue a periodic task */
2974 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2975
2976 bnx2x_dcbx_pmf_update(bp);
2977
2978 /* enable nig attention */
2979 val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2980 if (bp->common.int_block == INT_BLOCK_HC) {
2981 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2982 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2983 } else if (!CHIP_IS_E1x(bp)) {
2984 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2985 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2986 }
2987
2988 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2989 }
2990
2991 /* end of Link */
2992
2993 /* slow path */
2994
2995 /*
2996 * General service functions
2997 */
2998
2999 /* send the MCP a request, block until there is a reply */
3000 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
3001 {
3002 int mb_idx = BP_FW_MB_IDX(bp);
3003 u32 seq;
3004 u32 rc = 0;
3005 u32 cnt = 1;
3006 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
3007
3008 mutex_lock(&bp->fw_mb_mutex);
3009 seq = ++bp->fw_seq;
3010 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
3011 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
3012
3013 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
3014 (command | seq), param);
3015
3016 do {
3017 /* let the FW do it's magic ... */
3018 msleep(delay);
3019
3020 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
3021
3022 /* Give the FW up to 5 second (500*10ms) */
3023 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
3024
3025 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
3026 cnt*delay, rc, seq);
3027
3028 /* is this a reply to our command? */
3029 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
3030 rc &= FW_MSG_CODE_MASK;
3031 else {
3032 /* FW BUG! */
3033 BNX2X_ERR("FW failed to respond!\n");
3034 bnx2x_fw_dump(bp);
3035 rc = 0;
3036 }
3037 mutex_unlock(&bp->fw_mb_mutex);
3038
3039 return rc;
3040 }
3041
3042 static void storm_memset_func_cfg(struct bnx2x *bp,
3043 struct tstorm_eth_function_common_config *tcfg,
3044 u16 abs_fid)
3045 {
3046 size_t size = sizeof(struct tstorm_eth_function_common_config);
3047
3048 u32 addr = BAR_TSTRORM_INTMEM +
3049 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
3050
3051 __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
3052 }
3053
3054 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
3055 {
3056 if (CHIP_IS_E1x(bp)) {
3057 struct tstorm_eth_function_common_config tcfg = {0};
3058
3059 storm_memset_func_cfg(bp, &tcfg, p->func_id);
3060 }
3061
3062 /* Enable the function in the FW */
3063 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
3064 storm_memset_func_en(bp, p->func_id, 1);
3065
3066 /* spq */
3067 if (p->func_flgs & FUNC_FLG_SPQ) {
3068 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
3069 REG_WR(bp, XSEM_REG_FAST_MEMORY +
3070 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
3071 }
3072 }
3073
3074 /**
3075 * bnx2x_get_common_flags - Return common flags
3076 *
3077 * @bp device handle
3078 * @fp queue handle
3079 * @zero_stats TRUE if statistics zeroing is needed
3080 *
3081 * Return the flags that are common for the Tx-only and not normal connections.
3082 */
3083 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
3084 struct bnx2x_fastpath *fp,
3085 bool zero_stats)
3086 {
3087 unsigned long flags = 0;
3088
3089 /* PF driver will always initialize the Queue to an ACTIVE state */
3090 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
3091
3092 /* tx only connections collect statistics (on the same index as the
3093 * parent connection). The statistics are zeroed when the parent
3094 * connection is initialized.
3095 */
3096
3097 __set_bit(BNX2X_Q_FLG_STATS, &flags);
3098 if (zero_stats)
3099 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
3100
3101 if (bp->flags & TX_SWITCHING)
3102 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags);
3103
3104 __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
3105 __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
3106
3107 #ifdef BNX2X_STOP_ON_ERROR
3108 __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
3109 #endif
3110
3111 return flags;
3112 }
3113
3114 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
3115 struct bnx2x_fastpath *fp,
3116 bool leading)
3117 {
3118 unsigned long flags = 0;
3119
3120 /* calculate other queue flags */
3121 if (IS_MF_SD(bp))
3122 __set_bit(BNX2X_Q_FLG_OV, &flags);
3123
3124 if (IS_FCOE_FP(fp)) {
3125 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
3126 /* For FCoE - force usage of default priority (for afex) */
3127 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
3128 }
3129
3130 if (!fp->disable_tpa) {
3131 __set_bit(BNX2X_Q_FLG_TPA, &flags);
3132 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
3133 if (fp->mode == TPA_MODE_GRO)
3134 __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
3135 }
3136
3137 if (leading) {
3138 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3139 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3140 }
3141
3142 /* Always set HW VLAN stripping */
3143 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
3144
3145 /* configure silent vlan removal */
3146 if (IS_MF_AFEX(bp))
3147 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3148
3149 return flags | bnx2x_get_common_flags(bp, fp, true);
3150 }
3151
3152 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
3153 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3154 u8 cos)
3155 {
3156 gen_init->stat_id = bnx2x_stats_id(fp);
3157 gen_init->spcl_id = fp->cl_id;
3158
3159 /* Always use mini-jumbo MTU for FCoE L2 ring */
3160 if (IS_FCOE_FP(fp))
3161 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3162 else
3163 gen_init->mtu = bp->dev->mtu;
3164
3165 gen_init->cos = cos;
3166 }
3167
3168 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
3169 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
3170 struct bnx2x_rxq_setup_params *rxq_init)
3171 {
3172 u8 max_sge = 0;
3173 u16 sge_sz = 0;
3174 u16 tpa_agg_size = 0;
3175
3176 if (!fp->disable_tpa) {
3177 pause->sge_th_lo = SGE_TH_LO(bp);
3178 pause->sge_th_hi = SGE_TH_HI(bp);
3179
3180 /* validate SGE ring has enough to cross high threshold */
3181 WARN_ON(bp->dropless_fc &&
3182 pause->sge_th_hi + FW_PREFETCH_CNT >
3183 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3184
3185 tpa_agg_size = TPA_AGG_SIZE;
3186 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3187 SGE_PAGE_SHIFT;
3188 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3189 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
3190 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
3191 }
3192
3193 /* pause - not for e1 */
3194 if (!CHIP_IS_E1(bp)) {
3195 pause->bd_th_lo = BD_TH_LO(bp);
3196 pause->bd_th_hi = BD_TH_HI(bp);
3197
3198 pause->rcq_th_lo = RCQ_TH_LO(bp);
3199 pause->rcq_th_hi = RCQ_TH_HI(bp);
3200 /*
3201 * validate that rings have enough entries to cross
3202 * high thresholds
3203 */
3204 WARN_ON(bp->dropless_fc &&
3205 pause->bd_th_hi + FW_PREFETCH_CNT >
3206 bp->rx_ring_size);
3207 WARN_ON(bp->dropless_fc &&
3208 pause->rcq_th_hi + FW_PREFETCH_CNT >
3209 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
3210
3211 pause->pri_map = 1;
3212 }
3213
3214 /* rxq setup */
3215 rxq_init->dscr_map = fp->rx_desc_mapping;
3216 rxq_init->sge_map = fp->rx_sge_mapping;
3217 rxq_init->rcq_map = fp->rx_comp_mapping;
3218 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
3219
3220 /* This should be a maximum number of data bytes that may be
3221 * placed on the BD (not including paddings).
3222 */
3223 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3224 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
3225
3226 rxq_init->cl_qzone_id = fp->cl_qzone_id;
3227 rxq_init->tpa_agg_sz = tpa_agg_size;
3228 rxq_init->sge_buf_sz = sge_sz;
3229 rxq_init->max_sges_pkt = max_sge;
3230 rxq_init->rss_engine_id = BP_FUNC(bp);
3231 rxq_init->mcast_engine_id = BP_FUNC(bp);
3232
3233 /* Maximum number or simultaneous TPA aggregation for this Queue.
3234 *
3235 * For PF Clients it should be the maximum available number.
3236 * VF driver(s) may want to define it to a smaller value.
3237 */
3238 rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
3239
3240 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3241 rxq_init->fw_sb_id = fp->fw_sb_id;
3242
3243 if (IS_FCOE_FP(fp))
3244 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3245 else
3246 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
3247 /* configure silent vlan removal
3248 * if multi function mode is afex, then mask default vlan
3249 */
3250 if (IS_MF_AFEX(bp)) {
3251 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3252 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3253 }
3254 }
3255
3256 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
3257 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3258 u8 cos)
3259 {
3260 txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
3261 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
3262 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3263 txq_init->fw_sb_id = fp->fw_sb_id;
3264
3265 /*
3266 * set the tss leading client id for TX classification ==
3267 * leading RSS client id
3268 */
3269 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3270
3271 if (IS_FCOE_FP(fp)) {
3272 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3273 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3274 }
3275 }
3276
3277 static void bnx2x_pf_init(struct bnx2x *bp)
3278 {
3279 struct bnx2x_func_init_params func_init = {0};
3280 struct event_ring_data eq_data = { {0} };
3281 u16 flags;
3282
3283 if (!CHIP_IS_E1x(bp)) {
3284 /* reset IGU PF statistics: MSIX + ATTN */
3285 /* PF */
3286 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3287 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3288 (CHIP_MODE_IS_4_PORT(bp) ?
3289 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3290 /* ATTN */
3291 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3292 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3293 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3294 (CHIP_MODE_IS_4_PORT(bp) ?
3295 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3296 }
3297
3298 /* function setup flags */
3299 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
3300
3301 /* This flag is relevant for E1x only.
3302 * E2 doesn't have a TPA configuration in a function level.
3303 */
3304 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
3305
3306 func_init.func_flgs = flags;
3307 func_init.pf_id = BP_FUNC(bp);
3308 func_init.func_id = BP_FUNC(bp);
3309 func_init.spq_map = bp->spq_mapping;
3310 func_init.spq_prod = bp->spq_prod_idx;
3311
3312 bnx2x_func_init(bp, &func_init);
3313
3314 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3315
3316 /*
3317 * Congestion management values depend on the link rate
3318 * There is no active link so initial link rate is set to 10 Gbps.
3319 * When the link comes up The congestion management values are
3320 * re-calculated according to the actual link rate.
3321 */
3322 bp->link_vars.line_speed = SPEED_10000;
3323 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3324
3325 /* Only the PMF sets the HW */
3326 if (bp->port.pmf)
3327 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3328
3329 /* init Event Queue - PCI bus guarantees correct endianity*/
3330 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3331 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3332 eq_data.producer = bp->eq_prod;
3333 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3334 eq_data.sb_id = DEF_SB_ID;
3335 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3336 }
3337
3338 static void bnx2x_e1h_disable(struct bnx2x *bp)
3339 {
3340 int port = BP_PORT(bp);
3341
3342 bnx2x_tx_disable(bp);
3343
3344 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3345 }
3346
3347 static void bnx2x_e1h_enable(struct bnx2x *bp)
3348 {
3349 int port = BP_PORT(bp);
3350
3351 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
3352 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3353
3354 /* Tx queue should be only re-enabled */
3355 netif_tx_wake_all_queues(bp->dev);
3356
3357 /*
3358 * Should not call netif_carrier_on since it will be called if the link
3359 * is up when checking for link state
3360 */
3361 }
3362
3363 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3364
3365 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3366 {
3367 struct eth_stats_info *ether_stat =
3368 &bp->slowpath->drv_info_to_mcp.ether_stat;
3369 struct bnx2x_vlan_mac_obj *mac_obj =
3370 &bp->sp_objs->mac_obj;
3371 int i;
3372
3373 strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3374 ETH_STAT_INFO_VERSION_LEN);
3375
3376 /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3377 * mac_local field in ether_stat struct. The base address is offset by 2
3378 * bytes to account for the field being 8 bytes but a mac address is
3379 * only 6 bytes. Likewise, the stride for the get_n_elements function is
3380 * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3381 * allocated by the ether_stat struct, so the macs will land in their
3382 * proper positions.
3383 */
3384 for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3385 memset(ether_stat->mac_local + i, 0,
3386 sizeof(ether_stat->mac_local[0]));
3387 mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3388 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3389 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3390 ETH_ALEN);
3391 ether_stat->mtu_size = bp->dev->mtu;
3392 if (bp->dev->features & NETIF_F_RXCSUM)
3393 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3394 if (bp->dev->features & NETIF_F_TSO)
3395 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3396 ether_stat->feature_flags |= bp->common.boot_mode;
3397
3398 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3399
3400 ether_stat->txq_size = bp->tx_ring_size;
3401 ether_stat->rxq_size = bp->rx_ring_size;
3402
3403 #ifdef CONFIG_BNX2X_SRIOV
3404 ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0;
3405 #endif
3406 }
3407
3408 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3409 {
3410 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3411 struct fcoe_stats_info *fcoe_stat =
3412 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3413
3414 if (!CNIC_LOADED(bp))
3415 return;
3416
3417 memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
3418
3419 fcoe_stat->qos_priority =
3420 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3421
3422 /* insert FCoE stats from ramrod response */
3423 if (!NO_FCOE(bp)) {
3424 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3425 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3426 tstorm_queue_statistics;
3427
3428 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3429 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3430 xstorm_queue_statistics;
3431
3432 struct fcoe_statistics_params *fw_fcoe_stat =
3433 &bp->fw_stats_data->fcoe;
3434
3435 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3436 fcoe_stat->rx_bytes_lo,
3437 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3438
3439 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3440 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3441 fcoe_stat->rx_bytes_lo,
3442 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3443
3444 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3445 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3446 fcoe_stat->rx_bytes_lo,
3447 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3448
3449 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3450 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3451 fcoe_stat->rx_bytes_lo,
3452 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3453
3454 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3455 fcoe_stat->rx_frames_lo,
3456 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3457
3458 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3459 fcoe_stat->rx_frames_lo,
3460 fcoe_q_tstorm_stats->rcv_ucast_pkts);
3461
3462 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3463 fcoe_stat->rx_frames_lo,
3464 fcoe_q_tstorm_stats->rcv_bcast_pkts);
3465
3466 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3467 fcoe_stat->rx_frames_lo,
3468 fcoe_q_tstorm_stats->rcv_mcast_pkts);
3469
3470 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3471 fcoe_stat->tx_bytes_lo,
3472 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3473
3474 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3475 fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3476 fcoe_stat->tx_bytes_lo,
3477 fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3478
3479 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3480 fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3481 fcoe_stat->tx_bytes_lo,
3482 fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3483
3484 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3485 fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3486 fcoe_stat->tx_bytes_lo,
3487 fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3488
3489 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3490 fcoe_stat->tx_frames_lo,
3491 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3492
3493 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3494 fcoe_stat->tx_frames_lo,
3495 fcoe_q_xstorm_stats->ucast_pkts_sent);
3496
3497 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3498 fcoe_stat->tx_frames_lo,
3499 fcoe_q_xstorm_stats->bcast_pkts_sent);
3500
3501 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3502 fcoe_stat->tx_frames_lo,
3503 fcoe_q_xstorm_stats->mcast_pkts_sent);
3504 }
3505
3506 /* ask L5 driver to add data to the struct */
3507 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3508 }
3509
3510 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3511 {
3512 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3513 struct iscsi_stats_info *iscsi_stat =
3514 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3515
3516 if (!CNIC_LOADED(bp))
3517 return;
3518
3519 memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3520 ETH_ALEN);
3521
3522 iscsi_stat->qos_priority =
3523 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3524
3525 /* ask L5 driver to add data to the struct */
3526 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3527 }
3528
3529 /* called due to MCP event (on pmf):
3530 * reread new bandwidth configuration
3531 * configure FW
3532 * notify others function about the change
3533 */
3534 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3535 {
3536 if (bp->link_vars.link_up) {
3537 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3538 bnx2x_link_sync_notify(bp);
3539 }
3540 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3541 }
3542
3543 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3544 {
3545 bnx2x_config_mf_bw(bp);
3546 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3547 }
3548
3549 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3550 {
3551 DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3552 bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3553 }
3554
3555 #define BNX2X_UPDATE_DRV_INFO_IND_LENGTH (20)
3556 #define BNX2X_UPDATE_DRV_INFO_IND_COUNT (25)
3557
3558 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3559 {
3560 enum drv_info_opcode op_code;
3561 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3562 bool release = false;
3563 int wait;
3564
3565 /* if drv_info version supported by MFW doesn't match - send NACK */
3566 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3567 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3568 return;
3569 }
3570
3571 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3572 DRV_INFO_CONTROL_OP_CODE_SHIFT;
3573
3574 /* Must prevent other flows from accessing drv_info_to_mcp */
3575 mutex_lock(&bp->drv_info_mutex);
3576
3577 memset(&bp->slowpath->drv_info_to_mcp, 0,
3578 sizeof(union drv_info_to_mcp));
3579
3580 switch (op_code) {
3581 case ETH_STATS_OPCODE:
3582 bnx2x_drv_info_ether_stat(bp);
3583 break;
3584 case FCOE_STATS_OPCODE:
3585 bnx2x_drv_info_fcoe_stat(bp);
3586 break;
3587 case ISCSI_STATS_OPCODE:
3588 bnx2x_drv_info_iscsi_stat(bp);
3589 break;
3590 default:
3591 /* if op code isn't supported - send NACK */
3592 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3593 goto out;
3594 }
3595
3596 /* if we got drv_info attn from MFW then these fields are defined in
3597 * shmem2 for sure
3598 */
3599 SHMEM2_WR(bp, drv_info_host_addr_lo,
3600 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3601 SHMEM2_WR(bp, drv_info_host_addr_hi,
3602 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3603
3604 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3605
3606 /* Since possible management wants both this and get_driver_version
3607 * need to wait until management notifies us it finished utilizing
3608 * the buffer.
3609 */
3610 if (!SHMEM2_HAS(bp, mfw_drv_indication)) {
3611 DP(BNX2X_MSG_MCP, "Management does not support indication\n");
3612 } else if (!bp->drv_info_mng_owner) {
3613 u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1));
3614
3615 for (wait = 0; wait < BNX2X_UPDATE_DRV_INFO_IND_COUNT; wait++) {
3616 u32 indication = SHMEM2_RD(bp, mfw_drv_indication);
3617
3618 /* Management is done; need to clear indication */
3619 if (indication & bit) {
3620 SHMEM2_WR(bp, mfw_drv_indication,
3621 indication & ~bit);
3622 release = true;
3623 break;
3624 }
3625
3626 msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH);
3627 }
3628 }
3629 if (!release) {
3630 DP(BNX2X_MSG_MCP, "Management did not release indication\n");
3631 bp->drv_info_mng_owner = true;
3632 }
3633
3634 out:
3635 mutex_unlock(&bp->drv_info_mutex);
3636 }
3637
3638 static u32 bnx2x_update_mng_version_utility(u8 *version, bool bnx2x_format)
3639 {
3640 u8 vals[4];
3641 int i = 0;
3642
3643 if (bnx2x_format) {
3644 i = sscanf(version, "1.%c%hhd.%hhd.%hhd",
3645 &vals[0], &vals[1], &vals[2], &vals[3]);
3646 if (i > 0)
3647 vals[0] -= '0';
3648 } else {
3649 i = sscanf(version, "%hhd.%hhd.%hhd.%hhd",
3650 &vals[0], &vals[1], &vals[2], &vals[3]);
3651 }
3652
3653 while (i < 4)
3654 vals[i++] = 0;
3655
3656 return (vals[0] << 24) | (vals[1] << 16) | (vals[2] << 8) | vals[3];
3657 }
3658
3659 void bnx2x_update_mng_version(struct bnx2x *bp)
3660 {
3661 u32 iscsiver = DRV_VER_NOT_LOADED;
3662 u32 fcoever = DRV_VER_NOT_LOADED;
3663 u32 ethver = DRV_VER_NOT_LOADED;
3664 int idx = BP_FW_MB_IDX(bp);
3665 u8 *version;
3666
3667 if (!SHMEM2_HAS(bp, func_os_drv_ver))
3668 return;
3669
3670 mutex_lock(&bp->drv_info_mutex);
3671 /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */
3672 if (bp->drv_info_mng_owner)
3673 goto out;
3674
3675 if (bp->state != BNX2X_STATE_OPEN)
3676 goto out;
3677
3678 /* Parse ethernet driver version */
3679 ethver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3680 if (!CNIC_LOADED(bp))
3681 goto out;
3682
3683 /* Try getting storage driver version via cnic */
3684 memset(&bp->slowpath->drv_info_to_mcp, 0,
3685 sizeof(union drv_info_to_mcp));
3686 bnx2x_drv_info_iscsi_stat(bp);
3687 version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version;
3688 iscsiver = bnx2x_update_mng_version_utility(version, false);
3689
3690 memset(&bp->slowpath->drv_info_to_mcp, 0,
3691 sizeof(union drv_info_to_mcp));
3692 bnx2x_drv_info_fcoe_stat(bp);
3693 version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version;
3694 fcoever = bnx2x_update_mng_version_utility(version, false);
3695
3696 out:
3697 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver);
3698 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver);
3699 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever);
3700
3701 mutex_unlock(&bp->drv_info_mutex);
3702
3703 DP(BNX2X_MSG_MCP, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n",
3704 ethver, iscsiver, fcoever);
3705 }
3706
3707 static void bnx2x_oem_event(struct bnx2x *bp, u32 event)
3708 {
3709 u32 cmd_ok, cmd_fail;
3710
3711 /* sanity */
3712 if (event & DRV_STATUS_DCC_EVENT_MASK &&
3713 event & DRV_STATUS_OEM_EVENT_MASK) {
3714 BNX2X_ERR("Received simultaneous events %08x\n", event);
3715 return;
3716 }
3717
3718 if (event & DRV_STATUS_DCC_EVENT_MASK) {
3719 cmd_fail = DRV_MSG_CODE_DCC_FAILURE;
3720 cmd_ok = DRV_MSG_CODE_DCC_OK;
3721 } else /* if (event & DRV_STATUS_OEM_EVENT_MASK) */ {
3722 cmd_fail = DRV_MSG_CODE_OEM_FAILURE;
3723 cmd_ok = DRV_MSG_CODE_OEM_OK;
3724 }
3725
3726 DP(BNX2X_MSG_MCP, "oem_event 0x%x\n", event);
3727
3728 if (event & (DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3729 DRV_STATUS_OEM_DISABLE_ENABLE_PF)) {
3730 /* This is the only place besides the function initialization
3731 * where the bp->flags can change so it is done without any
3732 * locks
3733 */
3734 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3735 DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3736 bp->flags |= MF_FUNC_DIS;
3737
3738 bnx2x_e1h_disable(bp);
3739 } else {
3740 DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3741 bp->flags &= ~MF_FUNC_DIS;
3742
3743 bnx2x_e1h_enable(bp);
3744 }
3745 event &= ~(DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3746 DRV_STATUS_OEM_DISABLE_ENABLE_PF);
3747 }
3748
3749 if (event & (DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3750 DRV_STATUS_OEM_BANDWIDTH_ALLOCATION)) {
3751 bnx2x_config_mf_bw(bp);
3752 event &= ~(DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3753 DRV_STATUS_OEM_BANDWIDTH_ALLOCATION);
3754 }
3755
3756 /* Report results to MCP */
3757 if (event)
3758 bnx2x_fw_command(bp, cmd_fail, 0);
3759 else
3760 bnx2x_fw_command(bp, cmd_ok, 0);
3761 }
3762
3763 /* must be called under the spq lock */
3764 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3765 {
3766 struct eth_spe *next_spe = bp->spq_prod_bd;
3767
3768 if (bp->spq_prod_bd == bp->spq_last_bd) {
3769 bp->spq_prod_bd = bp->spq;
3770 bp->spq_prod_idx = 0;
3771 DP(BNX2X_MSG_SP, "end of spq\n");
3772 } else {
3773 bp->spq_prod_bd++;
3774 bp->spq_prod_idx++;
3775 }
3776 return next_spe;
3777 }
3778
3779 /* must be called under the spq lock */
3780 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3781 {
3782 int func = BP_FUNC(bp);
3783
3784 /*
3785 * Make sure that BD data is updated before writing the producer:
3786 * BD data is written to the memory, the producer is read from the
3787 * memory, thus we need a full memory barrier to ensure the ordering.
3788 */
3789 mb();
3790
3791 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3792 bp->spq_prod_idx);
3793 mmiowb();
3794 }
3795
3796 /**
3797 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3798 *
3799 * @cmd: command to check
3800 * @cmd_type: command type
3801 */
3802 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3803 {
3804 if ((cmd_type == NONE_CONNECTION_TYPE) ||
3805 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3806 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3807 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3808 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3809 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3810 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3811 return true;
3812 else
3813 return false;
3814 }
3815
3816 /**
3817 * bnx2x_sp_post - place a single command on an SP ring
3818 *
3819 * @bp: driver handle
3820 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3821 * @cid: SW CID the command is related to
3822 * @data_hi: command private data address (high 32 bits)
3823 * @data_lo: command private data address (low 32 bits)
3824 * @cmd_type: command type (e.g. NONE, ETH)
3825 *
3826 * SP data is handled as if it's always an address pair, thus data fields are
3827 * not swapped to little endian in upper functions. Instead this function swaps
3828 * data as if it's two u32 fields.
3829 */
3830 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3831 u32 data_hi, u32 data_lo, int cmd_type)
3832 {
3833 struct eth_spe *spe;
3834 u16 type;
3835 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3836
3837 #ifdef BNX2X_STOP_ON_ERROR
3838 if (unlikely(bp->panic)) {
3839 BNX2X_ERR("Can't post SP when there is panic\n");
3840 return -EIO;
3841 }
3842 #endif
3843
3844 spin_lock_bh(&bp->spq_lock);
3845
3846 if (common) {
3847 if (!atomic_read(&bp->eq_spq_left)) {
3848 BNX2X_ERR("BUG! EQ ring full!\n");
3849 spin_unlock_bh(&bp->spq_lock);
3850 bnx2x_panic();
3851 return -EBUSY;
3852 }
3853 } else if (!atomic_read(&bp->cq_spq_left)) {
3854 BNX2X_ERR("BUG! SPQ ring full!\n");
3855 spin_unlock_bh(&bp->spq_lock);
3856 bnx2x_panic();
3857 return -EBUSY;
3858 }
3859
3860 spe = bnx2x_sp_get_next(bp);
3861
3862 /* CID needs port number to be encoded int it */
3863 spe->hdr.conn_and_cmd_data =
3864 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3865 HW_CID(bp, cid));
3866
3867 /* In some cases, type may already contain the func-id
3868 * mainly in SRIOV related use cases, so we add it here only
3869 * if it's not already set.
3870 */
3871 if (!(cmd_type & SPE_HDR_FUNCTION_ID)) {
3872 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) &
3873 SPE_HDR_CONN_TYPE;
3874 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3875 SPE_HDR_FUNCTION_ID);
3876 } else {
3877 type = cmd_type;
3878 }
3879
3880 spe->hdr.type = cpu_to_le16(type);
3881
3882 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3883 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3884
3885 /*
3886 * It's ok if the actual decrement is issued towards the memory
3887 * somewhere between the spin_lock and spin_unlock. Thus no
3888 * more explicit memory barrier is needed.
3889 */
3890 if (common)
3891 atomic_dec(&bp->eq_spq_left);
3892 else
3893 atomic_dec(&bp->cq_spq_left);
3894
3895 DP(BNX2X_MSG_SP,
3896 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3897 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3898 (u32)(U64_LO(bp->spq_mapping) +
3899 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3900 HW_CID(bp, cid), data_hi, data_lo, type,
3901 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3902
3903 bnx2x_sp_prod_update(bp);
3904 spin_unlock_bh(&bp->spq_lock);
3905 return 0;
3906 }
3907
3908 /* acquire split MCP access lock register */
3909 static int bnx2x_acquire_alr(struct bnx2x *bp)
3910 {
3911 u32 j, val;
3912 int rc = 0;
3913
3914 might_sleep();
3915 for (j = 0; j < 1000; j++) {
3916 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3917 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3918 if (val & MCPR_ACCESS_LOCK_LOCK)
3919 break;
3920
3921 usleep_range(5000, 10000);
3922 }
3923 if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
3924 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3925 rc = -EBUSY;
3926 }
3927
3928 return rc;
3929 }
3930
3931 /* release split MCP access lock register */
3932 static void bnx2x_release_alr(struct bnx2x *bp)
3933 {
3934 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
3935 }
3936
3937 #define BNX2X_DEF_SB_ATT_IDX 0x0001
3938 #define BNX2X_DEF_SB_IDX 0x0002
3939
3940 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3941 {
3942 struct host_sp_status_block *def_sb = bp->def_status_blk;
3943 u16 rc = 0;
3944
3945 barrier(); /* status block is written to by the chip */
3946 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3947 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3948 rc |= BNX2X_DEF_SB_ATT_IDX;
3949 }
3950
3951 if (bp->def_idx != def_sb->sp_sb.running_index) {
3952 bp->def_idx = def_sb->sp_sb.running_index;
3953 rc |= BNX2X_DEF_SB_IDX;
3954 }
3955
3956 /* Do not reorder: indices reading should complete before handling */
3957 barrier();
3958 return rc;
3959 }
3960
3961 /*
3962 * slow path service functions
3963 */
3964
3965 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3966 {
3967 int port = BP_PORT(bp);
3968 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3969 MISC_REG_AEU_MASK_ATTN_FUNC_0;
3970 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3971 NIG_REG_MASK_INTERRUPT_PORT0;
3972 u32 aeu_mask;
3973 u32 nig_mask = 0;
3974 u32 reg_addr;
3975
3976 if (bp->attn_state & asserted)
3977 BNX2X_ERR("IGU ERROR\n");
3978
3979 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3980 aeu_mask = REG_RD(bp, aeu_addr);
3981
3982 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3983 aeu_mask, asserted);
3984 aeu_mask &= ~(asserted & 0x3ff);
3985 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3986
3987 REG_WR(bp, aeu_addr, aeu_mask);
3988 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3989
3990 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3991 bp->attn_state |= asserted;
3992 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3993
3994 if (asserted & ATTN_HARD_WIRED_MASK) {
3995 if (asserted & ATTN_NIG_FOR_FUNC) {
3996
3997 bnx2x_acquire_phy_lock(bp);
3998
3999 /* save nig interrupt mask */
4000 nig_mask = REG_RD(bp, nig_int_mask_addr);
4001
4002 /* If nig_mask is not set, no need to call the update
4003 * function.
4004 */
4005 if (nig_mask) {
4006 REG_WR(bp, nig_int_mask_addr, 0);
4007
4008 bnx2x_link_attn(bp);
4009 }
4010
4011 /* handle unicore attn? */
4012 }
4013 if (asserted & ATTN_SW_TIMER_4_FUNC)
4014 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
4015
4016 if (asserted & GPIO_2_FUNC)
4017 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
4018
4019 if (asserted & GPIO_3_FUNC)
4020 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
4021
4022 if (asserted & GPIO_4_FUNC)
4023 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
4024
4025 if (port == 0) {
4026 if (asserted & ATTN_GENERAL_ATTN_1) {
4027 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
4028 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
4029 }
4030 if (asserted & ATTN_GENERAL_ATTN_2) {
4031 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
4032 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
4033 }
4034 if (asserted & ATTN_GENERAL_ATTN_3) {
4035 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
4036 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
4037 }
4038 } else {
4039 if (asserted & ATTN_GENERAL_ATTN_4) {
4040 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
4041 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
4042 }
4043 if (asserted & ATTN_GENERAL_ATTN_5) {
4044 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
4045 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
4046 }
4047 if (asserted & ATTN_GENERAL_ATTN_6) {
4048 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
4049 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
4050 }
4051 }
4052
4053 } /* if hardwired */
4054
4055 if (bp->common.int_block == INT_BLOCK_HC)
4056 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4057 COMMAND_REG_ATTN_BITS_SET);
4058 else
4059 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
4060
4061 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
4062 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4063 REG_WR(bp, reg_addr, asserted);
4064
4065 /* now set back the mask */
4066 if (asserted & ATTN_NIG_FOR_FUNC) {
4067 /* Verify that IGU ack through BAR was written before restoring
4068 * NIG mask. This loop should exit after 2-3 iterations max.
4069 */
4070 if (bp->common.int_block != INT_BLOCK_HC) {
4071 u32 cnt = 0, igu_acked;
4072 do {
4073 igu_acked = REG_RD(bp,
4074 IGU_REG_ATTENTION_ACK_BITS);
4075 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
4076 (++cnt < MAX_IGU_ATTN_ACK_TO));
4077 if (!igu_acked)
4078 DP(NETIF_MSG_HW,
4079 "Failed to verify IGU ack on time\n");
4080 barrier();
4081 }
4082 REG_WR(bp, nig_int_mask_addr, nig_mask);
4083 bnx2x_release_phy_lock(bp);
4084 }
4085 }
4086
4087 static void bnx2x_fan_failure(struct bnx2x *bp)
4088 {
4089 int port = BP_PORT(bp);
4090 u32 ext_phy_config;
4091 /* mark the failure */
4092 ext_phy_config =
4093 SHMEM_RD(bp,
4094 dev_info.port_hw_config[port].external_phy_config);
4095
4096 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
4097 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
4098 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
4099 ext_phy_config);
4100
4101 /* log the failure */
4102 netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
4103 "Please contact OEM Support for assistance\n");
4104
4105 /* Schedule device reset (unload)
4106 * This is due to some boards consuming sufficient power when driver is
4107 * up to overheat if fan fails.
4108 */
4109 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0);
4110 }
4111
4112 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
4113 {
4114 int port = BP_PORT(bp);
4115 int reg_offset;
4116 u32 val;
4117
4118 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4119 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4120
4121 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4122
4123 val = REG_RD(bp, reg_offset);
4124 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4125 REG_WR(bp, reg_offset, val);
4126
4127 BNX2X_ERR("SPIO5 hw attention\n");
4128
4129 /* Fan failure attention */
4130 bnx2x_hw_reset_phy(&bp->link_params);
4131 bnx2x_fan_failure(bp);
4132 }
4133
4134 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
4135 bnx2x_acquire_phy_lock(bp);
4136 bnx2x_handle_module_detect_int(&bp->link_params);
4137 bnx2x_release_phy_lock(bp);
4138 }
4139
4140 if (attn & HW_INTERRUT_ASSERT_SET_0) {
4141
4142 val = REG_RD(bp, reg_offset);
4143 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4144 REG_WR(bp, reg_offset, val);
4145
4146 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
4147 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
4148 bnx2x_panic();
4149 }
4150 }
4151
4152 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
4153 {
4154 u32 val;
4155
4156 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4157
4158 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
4159 BNX2X_ERR("DB hw attention 0x%x\n", val);
4160 /* DORQ discard attention */
4161 if (val & 0x2)
4162 BNX2X_ERR("FATAL error from DORQ\n");
4163 }
4164
4165 if (attn & HW_INTERRUT_ASSERT_SET_1) {
4166
4167 int port = BP_PORT(bp);
4168 int reg_offset;
4169
4170 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4171 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4172
4173 val = REG_RD(bp, reg_offset);
4174 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4175 REG_WR(bp, reg_offset, val);
4176
4177 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
4178 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
4179 bnx2x_panic();
4180 }
4181 }
4182
4183 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
4184 {
4185 u32 val;
4186
4187 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
4188
4189 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
4190 BNX2X_ERR("CFC hw attention 0x%x\n", val);
4191 /* CFC error attention */
4192 if (val & 0x2)
4193 BNX2X_ERR("FATAL error from CFC\n");
4194 }
4195
4196 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
4197 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
4198 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
4199 /* RQ_USDMDP_FIFO_OVERFLOW */
4200 if (val & 0x18000)
4201 BNX2X_ERR("FATAL error from PXP\n");
4202
4203 if (!CHIP_IS_E1x(bp)) {
4204 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
4205 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
4206 }
4207 }
4208
4209 if (attn & HW_INTERRUT_ASSERT_SET_2) {
4210
4211 int port = BP_PORT(bp);
4212 int reg_offset;
4213
4214 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4215 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4216
4217 val = REG_RD(bp, reg_offset);
4218 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4219 REG_WR(bp, reg_offset, val);
4220
4221 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
4222 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
4223 bnx2x_panic();
4224 }
4225 }
4226
4227 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
4228 {
4229 u32 val;
4230
4231 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
4232
4233 if (attn & BNX2X_PMF_LINK_ASSERT) {
4234 int func = BP_FUNC(bp);
4235
4236 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
4237 bnx2x_read_mf_cfg(bp);
4238 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
4239 func_mf_config[BP_ABS_FUNC(bp)].config);
4240 val = SHMEM_RD(bp,
4241 func_mb[BP_FW_MB_IDX(bp)].drv_status);
4242
4243 if (val & (DRV_STATUS_DCC_EVENT_MASK |
4244 DRV_STATUS_OEM_EVENT_MASK))
4245 bnx2x_oem_event(bp,
4246 (val & (DRV_STATUS_DCC_EVENT_MASK |
4247 DRV_STATUS_OEM_EVENT_MASK)));
4248
4249 if (val & DRV_STATUS_SET_MF_BW)
4250 bnx2x_set_mf_bw(bp);
4251
4252 if (val & DRV_STATUS_DRV_INFO_REQ)
4253 bnx2x_handle_drv_info_req(bp);
4254
4255 if (val & DRV_STATUS_VF_DISABLED)
4256 bnx2x_schedule_iov_task(bp,
4257 BNX2X_IOV_HANDLE_FLR);
4258
4259 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
4260 bnx2x_pmf_update(bp);
4261
4262 if (bp->port.pmf &&
4263 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
4264 bp->dcbx_enabled > 0)
4265 /* start dcbx state machine */
4266 bnx2x_dcbx_set_params(bp,
4267 BNX2X_DCBX_STATE_NEG_RECEIVED);
4268 if (val & DRV_STATUS_AFEX_EVENT_MASK)
4269 bnx2x_handle_afex_cmd(bp,
4270 val & DRV_STATUS_AFEX_EVENT_MASK);
4271 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
4272 bnx2x_handle_eee_event(bp);
4273
4274 if (val & DRV_STATUS_OEM_UPDATE_SVID)
4275 bnx2x_handle_update_svid_cmd(bp);
4276
4277 if (bp->link_vars.periodic_flags &
4278 PERIODIC_FLAGS_LINK_EVENT) {
4279 /* sync with link */
4280 bnx2x_acquire_phy_lock(bp);
4281 bp->link_vars.periodic_flags &=
4282 ~PERIODIC_FLAGS_LINK_EVENT;
4283 bnx2x_release_phy_lock(bp);
4284 if (IS_MF(bp))
4285 bnx2x_link_sync_notify(bp);
4286 bnx2x_link_report(bp);
4287 }
4288 /* Always call it here: bnx2x_link_report() will
4289 * prevent the link indication duplication.
4290 */
4291 bnx2x__link_status_update(bp);
4292 } else if (attn & BNX2X_MC_ASSERT_BITS) {
4293
4294 BNX2X_ERR("MC assert!\n");
4295 bnx2x_mc_assert(bp);
4296 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4297 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4298 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4299 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4300 bnx2x_panic();
4301
4302 } else if (attn & BNX2X_MCP_ASSERT) {
4303
4304 BNX2X_ERR("MCP assert!\n");
4305 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
4306 bnx2x_fw_dump(bp);
4307
4308 } else
4309 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4310 }
4311
4312 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4313 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4314 if (attn & BNX2X_GRC_TIMEOUT) {
4315 val = CHIP_IS_E1(bp) ? 0 :
4316 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
4317 BNX2X_ERR("GRC time-out 0x%08x\n", val);
4318 }
4319 if (attn & BNX2X_GRC_RSV) {
4320 val = CHIP_IS_E1(bp) ? 0 :
4321 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
4322 BNX2X_ERR("GRC reserved 0x%08x\n", val);
4323 }
4324 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4325 }
4326 }
4327
4328 /*
4329 * Bits map:
4330 * 0-7 - Engine0 load counter.
4331 * 8-15 - Engine1 load counter.
4332 * 16 - Engine0 RESET_IN_PROGRESS bit.
4333 * 17 - Engine1 RESET_IN_PROGRESS bit.
4334 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4335 * on the engine
4336 * 19 - Engine1 ONE_IS_LOADED.
4337 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
4338 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
4339 * just the one belonging to its engine).
4340 *
4341 */
4342 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
4343
4344 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
4345 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
4346 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
4347 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
4348 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
4349 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
4350 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
4351
4352 /*
4353 * Set the GLOBAL_RESET bit.
4354 *
4355 * Should be run under rtnl lock
4356 */
4357 void bnx2x_set_reset_global(struct bnx2x *bp)
4358 {
4359 u32 val;
4360 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4361 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4362 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
4363 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4364 }
4365
4366 /*
4367 * Clear the GLOBAL_RESET bit.
4368 *
4369 * Should be run under rtnl lock
4370 */
4371 static void bnx2x_clear_reset_global(struct bnx2x *bp)
4372 {
4373 u32 val;
4374 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4375 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4376 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
4377 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4378 }
4379
4380 /*
4381 * Checks the GLOBAL_RESET bit.
4382 *
4383 * should be run under rtnl lock
4384 */
4385 static bool bnx2x_reset_is_global(struct bnx2x *bp)
4386 {
4387 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4388
4389 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4390 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4391 }
4392
4393 /*
4394 * Clear RESET_IN_PROGRESS bit for the current engine.
4395 *
4396 * Should be run under rtnl lock
4397 */
4398 static void bnx2x_set_reset_done(struct bnx2x *bp)
4399 {
4400 u32 val;
4401 u32 bit = BP_PATH(bp) ?
4402 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4403 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4404 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4405
4406 /* Clear the bit */
4407 val &= ~bit;
4408 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4409
4410 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4411 }
4412
4413 /*
4414 * Set RESET_IN_PROGRESS for the current engine.
4415 *
4416 * should be run under rtnl lock
4417 */
4418 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
4419 {
4420 u32 val;
4421 u32 bit = BP_PATH(bp) ?
4422 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4423 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4424 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4425
4426 /* Set the bit */
4427 val |= bit;
4428 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4429 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4430 }
4431
4432 /*
4433 * Checks the RESET_IN_PROGRESS bit for the given engine.
4434 * should be run under rtnl lock
4435 */
4436 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
4437 {
4438 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4439 u32 bit = engine ?
4440 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4441
4442 /* return false if bit is set */
4443 return (val & bit) ? false : true;
4444 }
4445
4446 /*
4447 * set pf load for the current pf.
4448 *
4449 * should be run under rtnl lock
4450 */
4451 void bnx2x_set_pf_load(struct bnx2x *bp)
4452 {
4453 u32 val1, val;
4454 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4455 BNX2X_PATH0_LOAD_CNT_MASK;
4456 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4457 BNX2X_PATH0_LOAD_CNT_SHIFT;
4458
4459 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4460 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4461
4462 DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4463
4464 /* get the current counter value */
4465 val1 = (val & mask) >> shift;
4466
4467 /* set bit of that PF */
4468 val1 |= (1 << bp->pf_num);
4469
4470 /* clear the old value */
4471 val &= ~mask;
4472
4473 /* set the new one */
4474 val |= ((val1 << shift) & mask);
4475
4476 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4477 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4478 }
4479
4480 /**
4481 * bnx2x_clear_pf_load - clear pf load mark
4482 *
4483 * @bp: driver handle
4484 *
4485 * Should be run under rtnl lock.
4486 * Decrements the load counter for the current engine. Returns
4487 * whether other functions are still loaded
4488 */
4489 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4490 {
4491 u32 val1, val;
4492 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4493 BNX2X_PATH0_LOAD_CNT_MASK;
4494 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4495 BNX2X_PATH0_LOAD_CNT_SHIFT;
4496
4497 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4498 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4499 DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4500
4501 /* get the current counter value */
4502 val1 = (val & mask) >> shift;
4503
4504 /* clear bit of that PF */
4505 val1 &= ~(1 << bp->pf_num);
4506
4507 /* clear the old value */
4508 val &= ~mask;
4509
4510 /* set the new one */
4511 val |= ((val1 << shift) & mask);
4512
4513 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4514 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4515 return val1 != 0;
4516 }
4517
4518 /*
4519 * Read the load status for the current engine.
4520 *
4521 * should be run under rtnl lock
4522 */
4523 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4524 {
4525 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4526 BNX2X_PATH0_LOAD_CNT_MASK);
4527 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4528 BNX2X_PATH0_LOAD_CNT_SHIFT);
4529 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4530
4531 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4532
4533 val = (val & mask) >> shift;
4534
4535 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4536 engine, val);
4537
4538 return val != 0;
4539 }
4540
4541 static void _print_parity(struct bnx2x *bp, u32 reg)
4542 {
4543 pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4544 }
4545
4546 static void _print_next_block(int idx, const char *blk)
4547 {
4548 pr_cont("%s%s", idx ? ", " : "", blk);
4549 }
4550
4551 static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4552 int *par_num, bool print)
4553 {
4554 u32 cur_bit;
4555 bool res;
4556 int i;
4557
4558 res = false;
4559
4560 for (i = 0; sig; i++) {
4561 cur_bit = (0x1UL << i);
4562 if (sig & cur_bit) {
4563 res |= true; /* Each bit is real error! */
4564
4565 if (print) {
4566 switch (cur_bit) {
4567 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4568 _print_next_block((*par_num)++, "BRB");
4569 _print_parity(bp,
4570 BRB1_REG_BRB1_PRTY_STS);
4571 break;
4572 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4573 _print_next_block((*par_num)++,
4574 "PARSER");
4575 _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4576 break;
4577 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4578 _print_next_block((*par_num)++, "TSDM");
4579 _print_parity(bp,
4580 TSDM_REG_TSDM_PRTY_STS);
4581 break;
4582 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4583 _print_next_block((*par_num)++,
4584 "SEARCHER");
4585 _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4586 break;
4587 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4588 _print_next_block((*par_num)++, "TCM");
4589 _print_parity(bp, TCM_REG_TCM_PRTY_STS);
4590 break;
4591 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4592 _print_next_block((*par_num)++,
4593 "TSEMI");
4594 _print_parity(bp,
4595 TSEM_REG_TSEM_PRTY_STS_0);
4596 _print_parity(bp,
4597 TSEM_REG_TSEM_PRTY_STS_1);
4598 break;
4599 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4600 _print_next_block((*par_num)++, "XPB");
4601 _print_parity(bp, GRCBASE_XPB +
4602 PB_REG_PB_PRTY_STS);
4603 break;
4604 }
4605 }
4606
4607 /* Clear the bit */
4608 sig &= ~cur_bit;
4609 }
4610 }
4611
4612 return res;
4613 }
4614
4615 static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4616 int *par_num, bool *global,
4617 bool print)
4618 {
4619 u32 cur_bit;
4620 bool res;
4621 int i;
4622
4623 res = false;
4624
4625 for (i = 0; sig; i++) {
4626 cur_bit = (0x1UL << i);
4627 if (sig & cur_bit) {
4628 res |= true; /* Each bit is real error! */
4629 switch (cur_bit) {
4630 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4631 if (print) {
4632 _print_next_block((*par_num)++, "PBF");
4633 _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4634 }
4635 break;
4636 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4637 if (print) {
4638 _print_next_block((*par_num)++, "QM");
4639 _print_parity(bp, QM_REG_QM_PRTY_STS);
4640 }
4641 break;
4642 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4643 if (print) {
4644 _print_next_block((*par_num)++, "TM");
4645 _print_parity(bp, TM_REG_TM_PRTY_STS);
4646 }
4647 break;
4648 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4649 if (print) {
4650 _print_next_block((*par_num)++, "XSDM");
4651 _print_parity(bp,
4652 XSDM_REG_XSDM_PRTY_STS);
4653 }
4654 break;
4655 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4656 if (print) {
4657 _print_next_block((*par_num)++, "XCM");
4658 _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4659 }
4660 break;
4661 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4662 if (print) {
4663 _print_next_block((*par_num)++,
4664 "XSEMI");
4665 _print_parity(bp,
4666 XSEM_REG_XSEM_PRTY_STS_0);
4667 _print_parity(bp,
4668 XSEM_REG_XSEM_PRTY_STS_1);
4669 }
4670 break;
4671 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4672 if (print) {
4673 _print_next_block((*par_num)++,
4674 "DOORBELLQ");
4675 _print_parity(bp,
4676 DORQ_REG_DORQ_PRTY_STS);
4677 }
4678 break;
4679 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4680 if (print) {
4681 _print_next_block((*par_num)++, "NIG");
4682 if (CHIP_IS_E1x(bp)) {
4683 _print_parity(bp,
4684 NIG_REG_NIG_PRTY_STS);
4685 } else {
4686 _print_parity(bp,
4687 NIG_REG_NIG_PRTY_STS_0);
4688 _print_parity(bp,
4689 NIG_REG_NIG_PRTY_STS_1);
4690 }
4691 }
4692 break;
4693 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4694 if (print)
4695 _print_next_block((*par_num)++,
4696 "VAUX PCI CORE");
4697 *global = true;
4698 break;
4699 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4700 if (print) {
4701 _print_next_block((*par_num)++,
4702 "DEBUG");
4703 _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4704 }
4705 break;
4706 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4707 if (print) {
4708 _print_next_block((*par_num)++, "USDM");
4709 _print_parity(bp,
4710 USDM_REG_USDM_PRTY_STS);
4711 }
4712 break;
4713 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4714 if (print) {
4715 _print_next_block((*par_num)++, "UCM");
4716 _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4717 }
4718 break;
4719 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4720 if (print) {
4721 _print_next_block((*par_num)++,
4722 "USEMI");
4723 _print_parity(bp,
4724 USEM_REG_USEM_PRTY_STS_0);
4725 _print_parity(bp,
4726 USEM_REG_USEM_PRTY_STS_1);
4727 }
4728 break;
4729 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4730 if (print) {
4731 _print_next_block((*par_num)++, "UPB");
4732 _print_parity(bp, GRCBASE_UPB +
4733 PB_REG_PB_PRTY_STS);
4734 }
4735 break;
4736 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4737 if (print) {
4738 _print_next_block((*par_num)++, "CSDM");
4739 _print_parity(bp,
4740 CSDM_REG_CSDM_PRTY_STS);
4741 }
4742 break;
4743 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4744 if (print) {
4745 _print_next_block((*par_num)++, "CCM");
4746 _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4747 }
4748 break;
4749 }
4750
4751 /* Clear the bit */
4752 sig &= ~cur_bit;
4753 }
4754 }
4755
4756 return res;
4757 }
4758
4759 static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4760 int *par_num, bool print)
4761 {
4762 u32 cur_bit;
4763 bool res;
4764 int i;
4765
4766 res = false;
4767
4768 for (i = 0; sig; i++) {
4769 cur_bit = (0x1UL << i);
4770 if (sig & cur_bit) {
4771 res = true; /* Each bit is real error! */
4772 if (print) {
4773 switch (cur_bit) {
4774 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4775 _print_next_block((*par_num)++,
4776 "CSEMI");
4777 _print_parity(bp,
4778 CSEM_REG_CSEM_PRTY_STS_0);
4779 _print_parity(bp,
4780 CSEM_REG_CSEM_PRTY_STS_1);
4781 break;
4782 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4783 _print_next_block((*par_num)++, "PXP");
4784 _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4785 _print_parity(bp,
4786 PXP2_REG_PXP2_PRTY_STS_0);
4787 _print_parity(bp,
4788 PXP2_REG_PXP2_PRTY_STS_1);
4789 break;
4790 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4791 _print_next_block((*par_num)++,
4792 "PXPPCICLOCKCLIENT");
4793 break;
4794 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4795 _print_next_block((*par_num)++, "CFC");
4796 _print_parity(bp,
4797 CFC_REG_CFC_PRTY_STS);
4798 break;
4799 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4800 _print_next_block((*par_num)++, "CDU");
4801 _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4802 break;
4803 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4804 _print_next_block((*par_num)++, "DMAE");
4805 _print_parity(bp,
4806 DMAE_REG_DMAE_PRTY_STS);
4807 break;
4808 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4809 _print_next_block((*par_num)++, "IGU");
4810 if (CHIP_IS_E1x(bp))
4811 _print_parity(bp,
4812 HC_REG_HC_PRTY_STS);
4813 else
4814 _print_parity(bp,
4815 IGU_REG_IGU_PRTY_STS);
4816 break;
4817 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4818 _print_next_block((*par_num)++, "MISC");
4819 _print_parity(bp,
4820 MISC_REG_MISC_PRTY_STS);
4821 break;
4822 }
4823 }
4824
4825 /* Clear the bit */
4826 sig &= ~cur_bit;
4827 }
4828 }
4829
4830 return res;
4831 }
4832
4833 static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
4834 int *par_num, bool *global,
4835 bool print)
4836 {
4837 bool res = false;
4838 u32 cur_bit;
4839 int i;
4840
4841 for (i = 0; sig; i++) {
4842 cur_bit = (0x1UL << i);
4843 if (sig & cur_bit) {
4844 switch (cur_bit) {
4845 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4846 if (print)
4847 _print_next_block((*par_num)++,
4848 "MCP ROM");
4849 *global = true;
4850 res = true;
4851 break;
4852 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4853 if (print)
4854 _print_next_block((*par_num)++,
4855 "MCP UMP RX");
4856 *global = true;
4857 res = true;
4858 break;
4859 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4860 if (print)
4861 _print_next_block((*par_num)++,
4862 "MCP UMP TX");
4863 *global = true;
4864 res = true;
4865 break;
4866 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4867 if (print)
4868 _print_next_block((*par_num)++,
4869 "MCP SCPAD");
4870 /* clear latched SCPAD PATIRY from MCP */
4871 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
4872 1UL << 10);
4873 break;
4874 }
4875
4876 /* Clear the bit */
4877 sig &= ~cur_bit;
4878 }
4879 }
4880
4881 return res;
4882 }
4883
4884 static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4885 int *par_num, bool print)
4886 {
4887 u32 cur_bit;
4888 bool res;
4889 int i;
4890
4891 res = false;
4892
4893 for (i = 0; sig; i++) {
4894 cur_bit = (0x1UL << i);
4895 if (sig & cur_bit) {
4896 res = true; /* Each bit is real error! */
4897 if (print) {
4898 switch (cur_bit) {
4899 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4900 _print_next_block((*par_num)++,
4901 "PGLUE_B");
4902 _print_parity(bp,
4903 PGLUE_B_REG_PGLUE_B_PRTY_STS);
4904 break;
4905 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4906 _print_next_block((*par_num)++, "ATC");
4907 _print_parity(bp,
4908 ATC_REG_ATC_PRTY_STS);
4909 break;
4910 }
4911 }
4912 /* Clear the bit */
4913 sig &= ~cur_bit;
4914 }
4915 }
4916
4917 return res;
4918 }
4919
4920 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4921 u32 *sig)
4922 {
4923 bool res = false;
4924
4925 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4926 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4927 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4928 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4929 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4930 int par_num = 0;
4931 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4932 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4933 sig[0] & HW_PRTY_ASSERT_SET_0,
4934 sig[1] & HW_PRTY_ASSERT_SET_1,
4935 sig[2] & HW_PRTY_ASSERT_SET_2,
4936 sig[3] & HW_PRTY_ASSERT_SET_3,
4937 sig[4] & HW_PRTY_ASSERT_SET_4);
4938 if (print)
4939 netdev_err(bp->dev,
4940 "Parity errors detected in blocks: ");
4941 res |= bnx2x_check_blocks_with_parity0(bp,
4942 sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
4943 res |= bnx2x_check_blocks_with_parity1(bp,
4944 sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
4945 res |= bnx2x_check_blocks_with_parity2(bp,
4946 sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
4947 res |= bnx2x_check_blocks_with_parity3(bp,
4948 sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
4949 res |= bnx2x_check_blocks_with_parity4(bp,
4950 sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
4951
4952 if (print)
4953 pr_cont("\n");
4954 }
4955
4956 return res;
4957 }
4958
4959 /**
4960 * bnx2x_chk_parity_attn - checks for parity attentions.
4961 *
4962 * @bp: driver handle
4963 * @global: true if there was a global attention
4964 * @print: show parity attention in syslog
4965 */
4966 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4967 {
4968 struct attn_route attn = { {0} };
4969 int port = BP_PORT(bp);
4970
4971 attn.sig[0] = REG_RD(bp,
4972 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4973 port*4);
4974 attn.sig[1] = REG_RD(bp,
4975 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4976 port*4);
4977 attn.sig[2] = REG_RD(bp,
4978 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4979 port*4);
4980 attn.sig[3] = REG_RD(bp,
4981 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4982 port*4);
4983 /* Since MCP attentions can't be disabled inside the block, we need to
4984 * read AEU registers to see whether they're currently disabled
4985 */
4986 attn.sig[3] &= ((REG_RD(bp,
4987 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
4988 : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
4989 MISC_AEU_ENABLE_MCP_PRTY_BITS) |
4990 ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
4991
4992 if (!CHIP_IS_E1x(bp))
4993 attn.sig[4] = REG_RD(bp,
4994 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4995 port*4);
4996
4997 return bnx2x_parity_attn(bp, global, print, attn.sig);
4998 }
4999
5000 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
5001 {
5002 u32 val;
5003 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
5004
5005 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
5006 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
5007 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
5008 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
5009 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
5010 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
5011 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
5012 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
5013 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
5014 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
5015 if (val &
5016 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
5017 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
5018 if (val &
5019 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
5020 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
5021 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
5022 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
5023 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
5024 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
5025 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
5026 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
5027 }
5028 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
5029 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
5030 BNX2X_ERR("ATC hw attention 0x%x\n", val);
5031 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
5032 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
5033 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
5034 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
5035 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
5036 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
5037 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
5038 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
5039 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
5040 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
5041 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
5042 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
5043 }
5044
5045 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5046 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
5047 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
5048 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5049 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
5050 }
5051 }
5052
5053 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
5054 {
5055 struct attn_route attn, *group_mask;
5056 int port = BP_PORT(bp);
5057 int index;
5058 u32 reg_addr;
5059 u32 val;
5060 u32 aeu_mask;
5061 bool global = false;
5062
5063 /* need to take HW lock because MCP or other port might also
5064 try to handle this event */
5065 bnx2x_acquire_alr(bp);
5066
5067 if (bnx2x_chk_parity_attn(bp, &global, true)) {
5068 #ifndef BNX2X_STOP_ON_ERROR
5069 bp->recovery_state = BNX2X_RECOVERY_INIT;
5070 schedule_delayed_work(&bp->sp_rtnl_task, 0);
5071 /* Disable HW interrupts */
5072 bnx2x_int_disable(bp);
5073 /* In case of parity errors don't handle attentions so that
5074 * other function would "see" parity errors.
5075 */
5076 #else
5077 bnx2x_panic();
5078 #endif
5079 bnx2x_release_alr(bp);
5080 return;
5081 }
5082
5083 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
5084 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
5085 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
5086 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
5087 if (!CHIP_IS_E1x(bp))
5088 attn.sig[4] =
5089 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
5090 else
5091 attn.sig[4] = 0;
5092
5093 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
5094 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
5095
5096 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5097 if (deasserted & (1 << index)) {
5098 group_mask = &bp->attn_group[index];
5099
5100 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
5101 index,
5102 group_mask->sig[0], group_mask->sig[1],
5103 group_mask->sig[2], group_mask->sig[3],
5104 group_mask->sig[4]);
5105
5106 bnx2x_attn_int_deasserted4(bp,
5107 attn.sig[4] & group_mask->sig[4]);
5108 bnx2x_attn_int_deasserted3(bp,
5109 attn.sig[3] & group_mask->sig[3]);
5110 bnx2x_attn_int_deasserted1(bp,
5111 attn.sig[1] & group_mask->sig[1]);
5112 bnx2x_attn_int_deasserted2(bp,
5113 attn.sig[2] & group_mask->sig[2]);
5114 bnx2x_attn_int_deasserted0(bp,
5115 attn.sig[0] & group_mask->sig[0]);
5116 }
5117 }
5118
5119 bnx2x_release_alr(bp);
5120
5121 if (bp->common.int_block == INT_BLOCK_HC)
5122 reg_addr = (HC_REG_COMMAND_REG + port*32 +
5123 COMMAND_REG_ATTN_BITS_CLR);
5124 else
5125 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
5126
5127 val = ~deasserted;
5128 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
5129 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5130 REG_WR(bp, reg_addr, val);
5131
5132 if (~bp->attn_state & deasserted)
5133 BNX2X_ERR("IGU ERROR\n");
5134
5135 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
5136 MISC_REG_AEU_MASK_ATTN_FUNC_0;
5137
5138 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5139 aeu_mask = REG_RD(bp, reg_addr);
5140
5141 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
5142 aeu_mask, deasserted);
5143 aeu_mask |= (deasserted & 0x3ff);
5144 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
5145
5146 REG_WR(bp, reg_addr, aeu_mask);
5147 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5148
5149 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
5150 bp->attn_state &= ~deasserted;
5151 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
5152 }
5153
5154 static void bnx2x_attn_int(struct bnx2x *bp)
5155 {
5156 /* read local copy of bits */
5157 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
5158 attn_bits);
5159 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
5160 attn_bits_ack);
5161 u32 attn_state = bp->attn_state;
5162
5163 /* look for changed bits */
5164 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
5165 u32 deasserted = ~attn_bits & attn_ack & attn_state;
5166
5167 DP(NETIF_MSG_HW,
5168 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
5169 attn_bits, attn_ack, asserted, deasserted);
5170
5171 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
5172 BNX2X_ERR("BAD attention state\n");
5173
5174 /* handle bits that were raised */
5175 if (asserted)
5176 bnx2x_attn_int_asserted(bp, asserted);
5177
5178 if (deasserted)
5179 bnx2x_attn_int_deasserted(bp, deasserted);
5180 }
5181
5182 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
5183 u16 index, u8 op, u8 update)
5184 {
5185 u32 igu_addr = bp->igu_base_addr;
5186 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
5187 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
5188 igu_addr);
5189 }
5190
5191 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
5192 {
5193 /* No memory barriers */
5194 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
5195 mmiowb(); /* keep prod updates ordered */
5196 }
5197
5198 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
5199 union event_ring_elem *elem)
5200 {
5201 u8 err = elem->message.error;
5202
5203 if (!bp->cnic_eth_dev.starting_cid ||
5204 (cid < bp->cnic_eth_dev.starting_cid &&
5205 cid != bp->cnic_eth_dev.iscsi_l2_cid))
5206 return 1;
5207
5208 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
5209
5210 if (unlikely(err)) {
5211
5212 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
5213 cid);
5214 bnx2x_panic_dump(bp, false);
5215 }
5216 bnx2x_cnic_cfc_comp(bp, cid, err);
5217 return 0;
5218 }
5219
5220 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
5221 {
5222 struct bnx2x_mcast_ramrod_params rparam;
5223 int rc;
5224
5225 memset(&rparam, 0, sizeof(rparam));
5226
5227 rparam.mcast_obj = &bp->mcast_obj;
5228
5229 netif_addr_lock_bh(bp->dev);
5230
5231 /* Clear pending state for the last command */
5232 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
5233
5234 /* If there are pending mcast commands - send them */
5235 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
5236 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
5237 if (rc < 0)
5238 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
5239 rc);
5240 }
5241
5242 netif_addr_unlock_bh(bp->dev);
5243 }
5244
5245 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
5246 union event_ring_elem *elem)
5247 {
5248 unsigned long ramrod_flags = 0;
5249 int rc = 0;
5250 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
5251 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
5252
5253 /* Always push next commands out, don't wait here */
5254 __set_bit(RAMROD_CONT, &ramrod_flags);
5255
5256 switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo)
5257 >> BNX2X_SWCID_SHIFT) {
5258 case BNX2X_FILTER_MAC_PENDING:
5259 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
5260 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
5261 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
5262 else
5263 vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
5264
5265 break;
5266 case BNX2X_FILTER_MCAST_PENDING:
5267 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
5268 /* This is only relevant for 57710 where multicast MACs are
5269 * configured as unicast MACs using the same ramrod.
5270 */
5271 bnx2x_handle_mcast_eqe(bp);
5272 return;
5273 default:
5274 BNX2X_ERR("Unsupported classification command: %d\n",
5275 elem->message.data.eth_event.echo);
5276 return;
5277 }
5278
5279 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
5280
5281 if (rc < 0)
5282 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
5283 else if (rc > 0)
5284 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
5285 }
5286
5287 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
5288
5289 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
5290 {
5291 netif_addr_lock_bh(bp->dev);
5292
5293 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5294
5295 /* Send rx_mode command again if was requested */
5296 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5297 bnx2x_set_storm_rx_mode(bp);
5298 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5299 &bp->sp_state))
5300 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5301 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5302 &bp->sp_state))
5303 bnx2x_set_iscsi_eth_rx_mode(bp, false);
5304
5305 netif_addr_unlock_bh(bp->dev);
5306 }
5307
5308 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
5309 union event_ring_elem *elem)
5310 {
5311 if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5312 DP(BNX2X_MSG_SP,
5313 "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5314 elem->message.data.vif_list_event.func_bit_map);
5315 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5316 elem->message.data.vif_list_event.func_bit_map);
5317 } else if (elem->message.data.vif_list_event.echo ==
5318 VIF_LIST_RULE_SET) {
5319 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5320 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5321 }
5322 }
5323
5324 /* called with rtnl_lock */
5325 static void bnx2x_after_function_update(struct bnx2x *bp)
5326 {
5327 int q, rc;
5328 struct bnx2x_fastpath *fp;
5329 struct bnx2x_queue_state_params queue_params = {NULL};
5330 struct bnx2x_queue_update_params *q_update_params =
5331 &queue_params.params.update;
5332
5333 /* Send Q update command with afex vlan removal values for all Qs */
5334 queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5335
5336 /* set silent vlan removal values according to vlan mode */
5337 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5338 &q_update_params->update_flags);
5339 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5340 &q_update_params->update_flags);
5341 __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5342
5343 /* in access mode mark mask and value are 0 to strip all vlans */
5344 if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5345 q_update_params->silent_removal_value = 0;
5346 q_update_params->silent_removal_mask = 0;
5347 } else {
5348 q_update_params->silent_removal_value =
5349 (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5350 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5351 }
5352
5353 for_each_eth_queue(bp, q) {
5354 /* Set the appropriate Queue object */
5355 fp = &bp->fp[q];
5356 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5357
5358 /* send the ramrod */
5359 rc = bnx2x_queue_state_change(bp, &queue_params);
5360 if (rc < 0)
5361 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5362 q);
5363 }
5364
5365 if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
5366 fp = &bp->fp[FCOE_IDX(bp)];
5367 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5368
5369 /* clear pending completion bit */
5370 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5371
5372 /* mark latest Q bit */
5373 smp_mb__before_atomic();
5374 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
5375 smp_mb__after_atomic();
5376
5377 /* send Q update ramrod for FCoE Q */
5378 rc = bnx2x_queue_state_change(bp, &queue_params);
5379 if (rc < 0)
5380 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5381 q);
5382 } else {
5383 /* If no FCoE ring - ACK MCP now */
5384 bnx2x_link_report(bp);
5385 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5386 }
5387 }
5388
5389 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
5390 struct bnx2x *bp, u32 cid)
5391 {
5392 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
5393
5394 if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
5395 return &bnx2x_fcoe_sp_obj(bp, q_obj);
5396 else
5397 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
5398 }
5399
5400 static void bnx2x_eq_int(struct bnx2x *bp)
5401 {
5402 u16 hw_cons, sw_cons, sw_prod;
5403 union event_ring_elem *elem;
5404 u8 echo;
5405 u32 cid;
5406 u8 opcode;
5407 int rc, spqe_cnt = 0;
5408 struct bnx2x_queue_sp_obj *q_obj;
5409 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5410 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
5411
5412 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5413
5414 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5415 * when we get the next-page we need to adjust so the loop
5416 * condition below will be met. The next element is the size of a
5417 * regular element and hence incrementing by 1
5418 */
5419 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5420 hw_cons++;
5421
5422 /* This function may never run in parallel with itself for a
5423 * specific bp, thus there is no need in "paired" read memory
5424 * barrier here.
5425 */
5426 sw_cons = bp->eq_cons;
5427 sw_prod = bp->eq_prod;
5428
5429 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
5430 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
5431
5432 for (; sw_cons != hw_cons;
5433 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5434
5435 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5436
5437 rc = bnx2x_iov_eq_sp_event(bp, elem);
5438 if (!rc) {
5439 DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5440 rc);
5441 goto next_spqe;
5442 }
5443
5444 /* elem CID originates from FW; actually LE */
5445 cid = SW_CID((__force __le32)
5446 elem->message.data.cfc_del_event.cid);
5447 opcode = elem->message.opcode;
5448
5449 /* handle eq element */
5450 switch (opcode) {
5451 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5452 bnx2x_vf_mbx_schedule(bp,
5453 &elem->message.data.vf_pf_event);
5454 continue;
5455
5456 case EVENT_RING_OPCODE_STAT_QUERY:
5457 DP_AND((BNX2X_MSG_SP | BNX2X_MSG_STATS),
5458 "got statistics comp event %d\n",
5459 bp->stats_comp++);
5460 /* nothing to do with stats comp */
5461 goto next_spqe;
5462
5463 case EVENT_RING_OPCODE_CFC_DEL:
5464 /* handle according to cid range */
5465 /*
5466 * we may want to verify here that the bp state is
5467 * HALTING
5468 */
5469 DP(BNX2X_MSG_SP,
5470 "got delete ramrod for MULTI[%d]\n", cid);
5471
5472 if (CNIC_LOADED(bp) &&
5473 !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
5474 goto next_spqe;
5475
5476 q_obj = bnx2x_cid_to_q_obj(bp, cid);
5477
5478 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5479 break;
5480
5481 goto next_spqe;
5482
5483 case EVENT_RING_OPCODE_STOP_TRAFFIC:
5484 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
5485 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5486 if (f_obj->complete_cmd(bp, f_obj,
5487 BNX2X_F_CMD_TX_STOP))
5488 break;
5489 goto next_spqe;
5490
5491 case EVENT_RING_OPCODE_START_TRAFFIC:
5492 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
5493 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5494 if (f_obj->complete_cmd(bp, f_obj,
5495 BNX2X_F_CMD_TX_START))
5496 break;
5497 goto next_spqe;
5498
5499 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
5500 echo = elem->message.data.function_update_event.echo;
5501 if (echo == SWITCH_UPDATE) {
5502 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5503 "got FUNC_SWITCH_UPDATE ramrod\n");
5504 if (f_obj->complete_cmd(
5505 bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5506 break;
5507
5508 } else {
5509 int cmd = BNX2X_SP_RTNL_AFEX_F_UPDATE;
5510
5511 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5512 "AFEX: ramrod completed FUNCTION_UPDATE\n");
5513 f_obj->complete_cmd(bp, f_obj,
5514 BNX2X_F_CMD_AFEX_UPDATE);
5515
5516 /* We will perform the Queues update from
5517 * sp_rtnl task as all Queue SP operations
5518 * should run under rtnl_lock.
5519 */
5520 bnx2x_schedule_sp_rtnl(bp, cmd, 0);
5521 }
5522
5523 goto next_spqe;
5524
5525 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5526 f_obj->complete_cmd(bp, f_obj,
5527 BNX2X_F_CMD_AFEX_VIFLISTS);
5528 bnx2x_after_afex_vif_lists(bp, elem);
5529 goto next_spqe;
5530 case EVENT_RING_OPCODE_FUNCTION_START:
5531 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5532 "got FUNC_START ramrod\n");
5533 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5534 break;
5535
5536 goto next_spqe;
5537
5538 case EVENT_RING_OPCODE_FUNCTION_STOP:
5539 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5540 "got FUNC_STOP ramrod\n");
5541 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5542 break;
5543
5544 goto next_spqe;
5545
5546 case EVENT_RING_OPCODE_SET_TIMESYNC:
5547 DP(BNX2X_MSG_SP | BNX2X_MSG_PTP,
5548 "got set_timesync ramrod completion\n");
5549 if (f_obj->complete_cmd(bp, f_obj,
5550 BNX2X_F_CMD_SET_TIMESYNC))
5551 break;
5552 goto next_spqe;
5553 }
5554
5555 switch (opcode | bp->state) {
5556 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5557 BNX2X_STATE_OPEN):
5558 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5559 BNX2X_STATE_OPENING_WAIT4_PORT):
5560 cid = elem->message.data.eth_event.echo &
5561 BNX2X_SWCID_MASK;
5562 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
5563 cid);
5564 rss_raw->clear_pending(rss_raw);
5565 break;
5566
5567 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5568 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5569 case (EVENT_RING_OPCODE_SET_MAC |
5570 BNX2X_STATE_CLOSING_WAIT4_HALT):
5571 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5572 BNX2X_STATE_OPEN):
5573 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5574 BNX2X_STATE_DIAG):
5575 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5576 BNX2X_STATE_CLOSING_WAIT4_HALT):
5577 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
5578 bnx2x_handle_classification_eqe(bp, elem);
5579 break;
5580
5581 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5582 BNX2X_STATE_OPEN):
5583 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5584 BNX2X_STATE_DIAG):
5585 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5586 BNX2X_STATE_CLOSING_WAIT4_HALT):
5587 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5588 bnx2x_handle_mcast_eqe(bp);
5589 break;
5590
5591 case (EVENT_RING_OPCODE_FILTERS_RULES |
5592 BNX2X_STATE_OPEN):
5593 case (EVENT_RING_OPCODE_FILTERS_RULES |
5594 BNX2X_STATE_DIAG):
5595 case (EVENT_RING_OPCODE_FILTERS_RULES |
5596 BNX2X_STATE_CLOSING_WAIT4_HALT):
5597 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5598 bnx2x_handle_rx_mode_eqe(bp);
5599 break;
5600 default:
5601 /* unknown event log error and continue */
5602 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5603 elem->message.opcode, bp->state);
5604 }
5605 next_spqe:
5606 spqe_cnt++;
5607 } /* for */
5608
5609 smp_mb__before_atomic();
5610 atomic_add(spqe_cnt, &bp->eq_spq_left);
5611
5612 bp->eq_cons = sw_cons;
5613 bp->eq_prod = sw_prod;
5614 /* Make sure that above mem writes were issued towards the memory */
5615 smp_wmb();
5616
5617 /* update producer */
5618 bnx2x_update_eq_prod(bp, bp->eq_prod);
5619 }
5620
5621 static void bnx2x_sp_task(struct work_struct *work)
5622 {
5623 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5624
5625 DP(BNX2X_MSG_SP, "sp task invoked\n");
5626
5627 /* make sure the atomic interrupt_occurred has been written */
5628 smp_rmb();
5629 if (atomic_read(&bp->interrupt_occurred)) {
5630
5631 /* what work needs to be performed? */
5632 u16 status = bnx2x_update_dsb_idx(bp);
5633
5634 DP(BNX2X_MSG_SP, "status %x\n", status);
5635 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5636 atomic_set(&bp->interrupt_occurred, 0);
5637
5638 /* HW attentions */
5639 if (status & BNX2X_DEF_SB_ATT_IDX) {
5640 bnx2x_attn_int(bp);
5641 status &= ~BNX2X_DEF_SB_ATT_IDX;
5642 }
5643
5644 /* SP events: STAT_QUERY and others */
5645 if (status & BNX2X_DEF_SB_IDX) {
5646 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5647
5648 if (FCOE_INIT(bp) &&
5649 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5650 /* Prevent local bottom-halves from running as
5651 * we are going to change the local NAPI list.
5652 */
5653 local_bh_disable();
5654 napi_schedule(&bnx2x_fcoe(bp, napi));
5655 local_bh_enable();
5656 }
5657
5658 /* Handle EQ completions */
5659 bnx2x_eq_int(bp);
5660 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5661 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5662
5663 status &= ~BNX2X_DEF_SB_IDX;
5664 }
5665
5666 /* if status is non zero then perhaps something went wrong */
5667 if (unlikely(status))
5668 DP(BNX2X_MSG_SP,
5669 "got an unknown interrupt! (status 0x%x)\n", status);
5670
5671 /* ack status block only if something was actually handled */
5672 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5673 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5674 }
5675
5676 /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5677 if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5678 &bp->sp_state)) {
5679 bnx2x_link_report(bp);
5680 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5681 }
5682 }
5683
5684 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5685 {
5686 struct net_device *dev = dev_instance;
5687 struct bnx2x *bp = netdev_priv(dev);
5688
5689 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5690 IGU_INT_DISABLE, 0);
5691
5692 #ifdef BNX2X_STOP_ON_ERROR
5693 if (unlikely(bp->panic))
5694 return IRQ_HANDLED;
5695 #endif
5696
5697 if (CNIC_LOADED(bp)) {
5698 struct cnic_ops *c_ops;
5699
5700 rcu_read_lock();
5701 c_ops = rcu_dereference(bp->cnic_ops);
5702 if (c_ops)
5703 c_ops->cnic_handler(bp->cnic_data, NULL);
5704 rcu_read_unlock();
5705 }
5706
5707 /* schedule sp task to perform default status block work, ack
5708 * attentions and enable interrupts.
5709 */
5710 bnx2x_schedule_sp_task(bp);
5711
5712 return IRQ_HANDLED;
5713 }
5714
5715 /* end of slow path */
5716
5717 void bnx2x_drv_pulse(struct bnx2x *bp)
5718 {
5719 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5720 bp->fw_drv_pulse_wr_seq);
5721 }
5722
5723 static void bnx2x_timer(unsigned long data)
5724 {
5725 struct bnx2x *bp = (struct bnx2x *) data;
5726
5727 if (!netif_running(bp->dev))
5728 return;
5729
5730 if (IS_PF(bp) &&
5731 !BP_NOMCP(bp)) {
5732 int mb_idx = BP_FW_MB_IDX(bp);
5733 u16 drv_pulse;
5734 u16 mcp_pulse;
5735
5736 ++bp->fw_drv_pulse_wr_seq;
5737 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5738 drv_pulse = bp->fw_drv_pulse_wr_seq;
5739 bnx2x_drv_pulse(bp);
5740
5741 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5742 MCP_PULSE_SEQ_MASK);
5743 /* The delta between driver pulse and mcp response
5744 * should not get too big. If the MFW is more than 5 pulses
5745 * behind, we should worry about it enough to generate an error
5746 * log.
5747 */
5748 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
5749 BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5750 drv_pulse, mcp_pulse);
5751 }
5752
5753 if (bp->state == BNX2X_STATE_OPEN)
5754 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5755
5756 /* sample pf vf bulletin board for new posts from pf */
5757 if (IS_VF(bp))
5758 bnx2x_timer_sriov(bp);
5759
5760 mod_timer(&bp->timer, jiffies + bp->current_interval);
5761 }
5762
5763 /* end of Statistics */
5764
5765 /* nic init */
5766
5767 /*
5768 * nic init service functions
5769 */
5770
5771 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5772 {
5773 u32 i;
5774 if (!(len%4) && !(addr%4))
5775 for (i = 0; i < len; i += 4)
5776 REG_WR(bp, addr + i, fill);
5777 else
5778 for (i = 0; i < len; i++)
5779 REG_WR8(bp, addr + i, fill);
5780 }
5781
5782 /* helper: writes FP SP data to FW - data_size in dwords */
5783 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5784 int fw_sb_id,
5785 u32 *sb_data_p,
5786 u32 data_size)
5787 {
5788 int index;
5789 for (index = 0; index < data_size; index++)
5790 REG_WR(bp, BAR_CSTRORM_INTMEM +
5791 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5792 sizeof(u32)*index,
5793 *(sb_data_p + index));
5794 }
5795
5796 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5797 {
5798 u32 *sb_data_p;
5799 u32 data_size = 0;
5800 struct hc_status_block_data_e2 sb_data_e2;
5801 struct hc_status_block_data_e1x sb_data_e1x;
5802
5803 /* disable the function first */
5804 if (!CHIP_IS_E1x(bp)) {
5805 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5806 sb_data_e2.common.state = SB_DISABLED;
5807 sb_data_e2.common.p_func.vf_valid = false;
5808 sb_data_p = (u32 *)&sb_data_e2;
5809 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5810 } else {
5811 memset(&sb_data_e1x, 0,
5812 sizeof(struct hc_status_block_data_e1x));
5813 sb_data_e1x.common.state = SB_DISABLED;
5814 sb_data_e1x.common.p_func.vf_valid = false;
5815 sb_data_p = (u32 *)&sb_data_e1x;
5816 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5817 }
5818 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5819
5820 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5821 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5822 CSTORM_STATUS_BLOCK_SIZE);
5823 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5824 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5825 CSTORM_SYNC_BLOCK_SIZE);
5826 }
5827
5828 /* helper: writes SP SB data to FW */
5829 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5830 struct hc_sp_status_block_data *sp_sb_data)
5831 {
5832 int func = BP_FUNC(bp);
5833 int i;
5834 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5835 REG_WR(bp, BAR_CSTRORM_INTMEM +
5836 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5837 i*sizeof(u32),
5838 *((u32 *)sp_sb_data + i));
5839 }
5840
5841 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5842 {
5843 int func = BP_FUNC(bp);
5844 struct hc_sp_status_block_data sp_sb_data;
5845 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5846
5847 sp_sb_data.state = SB_DISABLED;
5848 sp_sb_data.p_func.vf_valid = false;
5849
5850 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5851
5852 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5853 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5854 CSTORM_SP_STATUS_BLOCK_SIZE);
5855 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5856 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5857 CSTORM_SP_SYNC_BLOCK_SIZE);
5858 }
5859
5860 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5861 int igu_sb_id, int igu_seg_id)
5862 {
5863 hc_sm->igu_sb_id = igu_sb_id;
5864 hc_sm->igu_seg_id = igu_seg_id;
5865 hc_sm->timer_value = 0xFF;
5866 hc_sm->time_to_expire = 0xFFFFFFFF;
5867 }
5868
5869 /* allocates state machine ids. */
5870 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5871 {
5872 /* zero out state machine indices */
5873 /* rx indices */
5874 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5875
5876 /* tx indices */
5877 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5878 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5879 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5880 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5881
5882 /* map indices */
5883 /* rx indices */
5884 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5885 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5886
5887 /* tx indices */
5888 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5889 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5890 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5891 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5892 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5893 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5894 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5895 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5896 }
5897
5898 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5899 u8 vf_valid, int fw_sb_id, int igu_sb_id)
5900 {
5901 int igu_seg_id;
5902
5903 struct hc_status_block_data_e2 sb_data_e2;
5904 struct hc_status_block_data_e1x sb_data_e1x;
5905 struct hc_status_block_sm *hc_sm_p;
5906 int data_size;
5907 u32 *sb_data_p;
5908
5909 if (CHIP_INT_MODE_IS_BC(bp))
5910 igu_seg_id = HC_SEG_ACCESS_NORM;
5911 else
5912 igu_seg_id = IGU_SEG_ACCESS_NORM;
5913
5914 bnx2x_zero_fp_sb(bp, fw_sb_id);
5915
5916 if (!CHIP_IS_E1x(bp)) {
5917 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5918 sb_data_e2.common.state = SB_ENABLED;
5919 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5920 sb_data_e2.common.p_func.vf_id = vfid;
5921 sb_data_e2.common.p_func.vf_valid = vf_valid;
5922 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5923 sb_data_e2.common.same_igu_sb_1b = true;
5924 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5925 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5926 hc_sm_p = sb_data_e2.common.state_machine;
5927 sb_data_p = (u32 *)&sb_data_e2;
5928 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5929 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5930 } else {
5931 memset(&sb_data_e1x, 0,
5932 sizeof(struct hc_status_block_data_e1x));
5933 sb_data_e1x.common.state = SB_ENABLED;
5934 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5935 sb_data_e1x.common.p_func.vf_id = 0xff;
5936 sb_data_e1x.common.p_func.vf_valid = false;
5937 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5938 sb_data_e1x.common.same_igu_sb_1b = true;
5939 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5940 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5941 hc_sm_p = sb_data_e1x.common.state_machine;
5942 sb_data_p = (u32 *)&sb_data_e1x;
5943 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5944 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5945 }
5946
5947 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5948 igu_sb_id, igu_seg_id);
5949 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5950 igu_sb_id, igu_seg_id);
5951
5952 DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5953
5954 /* write indices to HW - PCI guarantees endianity of regpairs */
5955 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5956 }
5957
5958 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5959 u16 tx_usec, u16 rx_usec)
5960 {
5961 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
5962 false, rx_usec);
5963 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5964 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5965 tx_usec);
5966 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5967 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5968 tx_usec);
5969 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5970 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5971 tx_usec);
5972 }
5973
5974 static void bnx2x_init_def_sb(struct bnx2x *bp)
5975 {
5976 struct host_sp_status_block *def_sb = bp->def_status_blk;
5977 dma_addr_t mapping = bp->def_status_blk_mapping;
5978 int igu_sp_sb_index;
5979 int igu_seg_id;
5980 int port = BP_PORT(bp);
5981 int func = BP_FUNC(bp);
5982 int reg_offset, reg_offset_en5;
5983 u64 section;
5984 int index;
5985 struct hc_sp_status_block_data sp_sb_data;
5986 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5987
5988 if (CHIP_INT_MODE_IS_BC(bp)) {
5989 igu_sp_sb_index = DEF_SB_IGU_ID;
5990 igu_seg_id = HC_SEG_ACCESS_DEF;
5991 } else {
5992 igu_sp_sb_index = bp->igu_dsb_id;
5993 igu_seg_id = IGU_SEG_ACCESS_DEF;
5994 }
5995
5996 /* ATTN */
5997 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5998 atten_status_block);
5999 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
6000
6001 bp->attn_state = 0;
6002
6003 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6004 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6005 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
6006 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
6007 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
6008 int sindex;
6009 /* take care of sig[0]..sig[4] */
6010 for (sindex = 0; sindex < 4; sindex++)
6011 bp->attn_group[index].sig[sindex] =
6012 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
6013
6014 if (!CHIP_IS_E1x(bp))
6015 /*
6016 * enable5 is separate from the rest of the registers,
6017 * and therefore the address skip is 4
6018 * and not 16 between the different groups
6019 */
6020 bp->attn_group[index].sig[4] = REG_RD(bp,
6021 reg_offset_en5 + 0x4*index);
6022 else
6023 bp->attn_group[index].sig[4] = 0;
6024 }
6025
6026 if (bp->common.int_block == INT_BLOCK_HC) {
6027 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
6028 HC_REG_ATTN_MSG0_ADDR_L);
6029
6030 REG_WR(bp, reg_offset, U64_LO(section));
6031 REG_WR(bp, reg_offset + 4, U64_HI(section));
6032 } else if (!CHIP_IS_E1x(bp)) {
6033 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
6034 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
6035 }
6036
6037 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6038 sp_sb);
6039
6040 bnx2x_zero_sp_sb(bp);
6041
6042 /* PCI guarantees endianity of regpairs */
6043 sp_sb_data.state = SB_ENABLED;
6044 sp_sb_data.host_sb_addr.lo = U64_LO(section);
6045 sp_sb_data.host_sb_addr.hi = U64_HI(section);
6046 sp_sb_data.igu_sb_id = igu_sp_sb_index;
6047 sp_sb_data.igu_seg_id = igu_seg_id;
6048 sp_sb_data.p_func.pf_id = func;
6049 sp_sb_data.p_func.vnic_id = BP_VN(bp);
6050 sp_sb_data.p_func.vf_id = 0xff;
6051
6052 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
6053
6054 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6055 }
6056
6057 void bnx2x_update_coalesce(struct bnx2x *bp)
6058 {
6059 int i;
6060
6061 for_each_eth_queue(bp, i)
6062 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
6063 bp->tx_ticks, bp->rx_ticks);
6064 }
6065
6066 static void bnx2x_init_sp_ring(struct bnx2x *bp)
6067 {
6068 spin_lock_init(&bp->spq_lock);
6069 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
6070
6071 bp->spq_prod_idx = 0;
6072 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
6073 bp->spq_prod_bd = bp->spq;
6074 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
6075 }
6076
6077 static void bnx2x_init_eq_ring(struct bnx2x *bp)
6078 {
6079 int i;
6080 for (i = 1; i <= NUM_EQ_PAGES; i++) {
6081 union event_ring_elem *elem =
6082 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
6083
6084 elem->next_page.addr.hi =
6085 cpu_to_le32(U64_HI(bp->eq_mapping +
6086 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
6087 elem->next_page.addr.lo =
6088 cpu_to_le32(U64_LO(bp->eq_mapping +
6089 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
6090 }
6091 bp->eq_cons = 0;
6092 bp->eq_prod = NUM_EQ_DESC;
6093 bp->eq_cons_sb = BNX2X_EQ_INDEX;
6094 /* we want a warning message before it gets wrought... */
6095 atomic_set(&bp->eq_spq_left,
6096 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
6097 }
6098
6099 /* called with netif_addr_lock_bh() */
6100 static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
6101 unsigned long rx_mode_flags,
6102 unsigned long rx_accept_flags,
6103 unsigned long tx_accept_flags,
6104 unsigned long ramrod_flags)
6105 {
6106 struct bnx2x_rx_mode_ramrod_params ramrod_param;
6107 int rc;
6108
6109 memset(&ramrod_param, 0, sizeof(ramrod_param));
6110
6111 /* Prepare ramrod parameters */
6112 ramrod_param.cid = 0;
6113 ramrod_param.cl_id = cl_id;
6114 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
6115 ramrod_param.func_id = BP_FUNC(bp);
6116
6117 ramrod_param.pstate = &bp->sp_state;
6118 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
6119
6120 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
6121 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
6122
6123 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
6124
6125 ramrod_param.ramrod_flags = ramrod_flags;
6126 ramrod_param.rx_mode_flags = rx_mode_flags;
6127
6128 ramrod_param.rx_accept_flags = rx_accept_flags;
6129 ramrod_param.tx_accept_flags = tx_accept_flags;
6130
6131 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
6132 if (rc < 0) {
6133 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
6134 return rc;
6135 }
6136
6137 return 0;
6138 }
6139
6140 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
6141 unsigned long *rx_accept_flags,
6142 unsigned long *tx_accept_flags)
6143 {
6144 /* Clear the flags first */
6145 *rx_accept_flags = 0;
6146 *tx_accept_flags = 0;
6147
6148 switch (rx_mode) {
6149 case BNX2X_RX_MODE_NONE:
6150 /*
6151 * 'drop all' supersedes any accept flags that may have been
6152 * passed to the function.
6153 */
6154 break;
6155 case BNX2X_RX_MODE_NORMAL:
6156 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6157 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
6158 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6159
6160 /* internal switching mode */
6161 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6162 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
6163 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6164
6165 break;
6166 case BNX2X_RX_MODE_ALLMULTI:
6167 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6168 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6169 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6170
6171 /* internal switching mode */
6172 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6173 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6174 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6175
6176 break;
6177 case BNX2X_RX_MODE_PROMISC:
6178 /* According to definition of SI mode, iface in promisc mode
6179 * should receive matched and unmatched (in resolution of port)
6180 * unicast packets.
6181 */
6182 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
6183 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6184 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6185 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6186
6187 /* internal switching mode */
6188 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6189 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6190
6191 if (IS_MF_SI(bp))
6192 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
6193 else
6194 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6195
6196 break;
6197 default:
6198 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
6199 return -EINVAL;
6200 }
6201
6202 /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
6203 if (rx_mode != BNX2X_RX_MODE_NONE) {
6204 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6205 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6206 }
6207
6208 return 0;
6209 }
6210
6211 /* called with netif_addr_lock_bh() */
6212 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
6213 {
6214 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
6215 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
6216 int rc;
6217
6218 if (!NO_FCOE(bp))
6219 /* Configure rx_mode of FCoE Queue */
6220 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
6221
6222 rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
6223 &tx_accept_flags);
6224 if (rc)
6225 return rc;
6226
6227 __set_bit(RAMROD_RX, &ramrod_flags);
6228 __set_bit(RAMROD_TX, &ramrod_flags);
6229
6230 return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
6231 rx_accept_flags, tx_accept_flags,
6232 ramrod_flags);
6233 }
6234
6235 static void bnx2x_init_internal_common(struct bnx2x *bp)
6236 {
6237 int i;
6238
6239 /* Zero this manually as its initialization is
6240 currently missing in the initTool */
6241 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
6242 REG_WR(bp, BAR_USTRORM_INTMEM +
6243 USTORM_AGG_DATA_OFFSET + i * 4, 0);
6244 if (!CHIP_IS_E1x(bp)) {
6245 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
6246 CHIP_INT_MODE_IS_BC(bp) ?
6247 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
6248 }
6249 }
6250
6251 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
6252 {
6253 switch (load_code) {
6254 case FW_MSG_CODE_DRV_LOAD_COMMON:
6255 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
6256 bnx2x_init_internal_common(bp);
6257 /* no break */
6258
6259 case FW_MSG_CODE_DRV_LOAD_PORT:
6260 /* nothing to do */
6261 /* no break */
6262
6263 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
6264 /* internal memory per function is
6265 initialized inside bnx2x_pf_init */
6266 break;
6267
6268 default:
6269 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6270 break;
6271 }
6272 }
6273
6274 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
6275 {
6276 return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
6277 }
6278
6279 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
6280 {
6281 return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
6282 }
6283
6284 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
6285 {
6286 if (CHIP_IS_E1x(fp->bp))
6287 return BP_L_ID(fp->bp) + fp->index;
6288 else /* We want Client ID to be the same as IGU SB ID for 57712 */
6289 return bnx2x_fp_igu_sb_id(fp);
6290 }
6291
6292 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
6293 {
6294 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6295 u8 cos;
6296 unsigned long q_type = 0;
6297 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
6298 fp->rx_queue = fp_idx;
6299 fp->cid = fp_idx;
6300 fp->cl_id = bnx2x_fp_cl_id(fp);
6301 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6302 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
6303 /* qZone id equals to FW (per path) client id */
6304 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
6305
6306 /* init shortcut */
6307 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
6308
6309 /* Setup SB indices */
6310 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
6311
6312 /* Configure Queue State object */
6313 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6314 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6315
6316 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6317
6318 /* init tx data */
6319 for_each_cos_in_tx_queue(fp, cos) {
6320 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6321 CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6322 FP_COS_TO_TXQ(fp, cos, bp),
6323 BNX2X_TX_SB_INDEX_BASE + cos, fp);
6324 cids[cos] = fp->txdata_ptr[cos]->cid;
6325 }
6326
6327 /* nothing more for vf to do here */
6328 if (IS_VF(bp))
6329 return;
6330
6331 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6332 fp->fw_sb_id, fp->igu_sb_id);
6333 bnx2x_update_fpsb_idx(fp);
6334 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6335 fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6336 bnx2x_sp_mapping(bp, q_rdata), q_type);
6337
6338 /**
6339 * Configure classification DBs: Always enable Tx switching
6340 */
6341 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6342
6343 DP(NETIF_MSG_IFUP,
6344 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6345 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6346 fp->igu_sb_id);
6347 }
6348
6349 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
6350 {
6351 int i;
6352
6353 for (i = 1; i <= NUM_TX_RINGS; i++) {
6354 struct eth_tx_next_bd *tx_next_bd =
6355 &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
6356
6357 tx_next_bd->addr_hi =
6358 cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
6359 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6360 tx_next_bd->addr_lo =
6361 cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
6362 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6363 }
6364
6365 *txdata->tx_cons_sb = cpu_to_le16(0);
6366
6367 SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
6368 txdata->tx_db.data.zero_fill1 = 0;
6369 txdata->tx_db.data.prod = 0;
6370
6371 txdata->tx_pkt_prod = 0;
6372 txdata->tx_pkt_cons = 0;
6373 txdata->tx_bd_prod = 0;
6374 txdata->tx_bd_cons = 0;
6375 txdata->tx_pkt = 0;
6376 }
6377
6378 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
6379 {
6380 int i;
6381
6382 for_each_tx_queue_cnic(bp, i)
6383 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6384 }
6385
6386 static void bnx2x_init_tx_rings(struct bnx2x *bp)
6387 {
6388 int i;
6389 u8 cos;
6390
6391 for_each_eth_queue(bp, i)
6392 for_each_cos_in_tx_queue(&bp->fp[i], cos)
6393 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
6394 }
6395
6396 static void bnx2x_init_fcoe_fp(struct bnx2x *bp)
6397 {
6398 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
6399 unsigned long q_type = 0;
6400
6401 bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp);
6402 bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp,
6403 BNX2X_FCOE_ETH_CL_ID_IDX);
6404 bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp);
6405 bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
6406 bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
6407 bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
6408 bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]),
6409 fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX,
6410 fp);
6411
6412 DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index);
6413
6414 /* qZone id equals to FW (per path) client id */
6415 bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp);
6416 /* init shortcut */
6417 bnx2x_fcoe(bp, ustorm_rx_prods_offset) =
6418 bnx2x_rx_ustorm_prods_offset(fp);
6419
6420 /* Configure Queue State object */
6421 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6422 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6423
6424 /* No multi-CoS for FCoE L2 client */
6425 BUG_ON(fp->max_cos != 1);
6426
6427 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id,
6428 &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6429 bnx2x_sp_mapping(bp, q_rdata), q_type);
6430
6431 DP(NETIF_MSG_IFUP,
6432 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6433 fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6434 fp->igu_sb_id);
6435 }
6436
6437 void bnx2x_nic_init_cnic(struct bnx2x *bp)
6438 {
6439 if (!NO_FCOE(bp))
6440 bnx2x_init_fcoe_fp(bp);
6441
6442 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6443 BNX2X_VF_ID_INVALID, false,
6444 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
6445
6446 /* ensure status block indices were read */
6447 rmb();
6448 bnx2x_init_rx_rings_cnic(bp);
6449 bnx2x_init_tx_rings_cnic(bp);
6450
6451 /* flush all */
6452 mb();
6453 mmiowb();
6454 }
6455
6456 void bnx2x_pre_irq_nic_init(struct bnx2x *bp)
6457 {
6458 int i;
6459
6460 /* Setup NIC internals and enable interrupts */
6461 for_each_eth_queue(bp, i)
6462 bnx2x_init_eth_fp(bp, i);
6463
6464 /* ensure status block indices were read */
6465 rmb();
6466 bnx2x_init_rx_rings(bp);
6467 bnx2x_init_tx_rings(bp);
6468
6469 if (IS_PF(bp)) {
6470 /* Initialize MOD_ABS interrupts */
6471 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6472 bp->common.shmem_base,
6473 bp->common.shmem2_base, BP_PORT(bp));
6474
6475 /* initialize the default status block and sp ring */
6476 bnx2x_init_def_sb(bp);
6477 bnx2x_update_dsb_idx(bp);
6478 bnx2x_init_sp_ring(bp);
6479 } else {
6480 bnx2x_memset_stats(bp);
6481 }
6482 }
6483
6484 void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code)
6485 {
6486 bnx2x_init_eq_ring(bp);
6487 bnx2x_init_internal(bp, load_code);
6488 bnx2x_pf_init(bp);
6489 bnx2x_stats_init(bp);
6490
6491 /* flush all before enabling interrupts */
6492 mb();
6493 mmiowb();
6494
6495 bnx2x_int_enable(bp);
6496
6497 /* Check for SPIO5 */
6498 bnx2x_attn_int_deasserted0(bp,
6499 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6500 AEU_INPUTS_ATTN_BITS_SPIO5);
6501 }
6502
6503 /* gzip service functions */
6504 static int bnx2x_gunzip_init(struct bnx2x *bp)
6505 {
6506 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6507 &bp->gunzip_mapping, GFP_KERNEL);
6508 if (bp->gunzip_buf == NULL)
6509 goto gunzip_nomem1;
6510
6511 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6512 if (bp->strm == NULL)
6513 goto gunzip_nomem2;
6514
6515 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
6516 if (bp->strm->workspace == NULL)
6517 goto gunzip_nomem3;
6518
6519 return 0;
6520
6521 gunzip_nomem3:
6522 kfree(bp->strm);
6523 bp->strm = NULL;
6524
6525 gunzip_nomem2:
6526 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6527 bp->gunzip_mapping);
6528 bp->gunzip_buf = NULL;
6529
6530 gunzip_nomem1:
6531 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
6532 return -ENOMEM;
6533 }
6534
6535 static void bnx2x_gunzip_end(struct bnx2x *bp)
6536 {
6537 if (bp->strm) {
6538 vfree(bp->strm->workspace);
6539 kfree(bp->strm);
6540 bp->strm = NULL;
6541 }
6542
6543 if (bp->gunzip_buf) {
6544 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6545 bp->gunzip_mapping);
6546 bp->gunzip_buf = NULL;
6547 }
6548 }
6549
6550 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
6551 {
6552 int n, rc;
6553
6554 /* check gzip header */
6555 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6556 BNX2X_ERR("Bad gzip header\n");
6557 return -EINVAL;
6558 }
6559
6560 n = 10;
6561
6562 #define FNAME 0x8
6563
6564 if (zbuf[3] & FNAME)
6565 while ((zbuf[n++] != 0) && (n < len));
6566
6567 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
6568 bp->strm->avail_in = len - n;
6569 bp->strm->next_out = bp->gunzip_buf;
6570 bp->strm->avail_out = FW_BUF_SIZE;
6571
6572 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6573 if (rc != Z_OK)
6574 return rc;
6575
6576 rc = zlib_inflate(bp->strm, Z_FINISH);
6577 if ((rc != Z_OK) && (rc != Z_STREAM_END))
6578 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6579 bp->strm->msg);
6580
6581 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6582 if (bp->gunzip_outlen & 0x3)
6583 netdev_err(bp->dev,
6584 "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
6585 bp->gunzip_outlen);
6586 bp->gunzip_outlen >>= 2;
6587
6588 zlib_inflateEnd(bp->strm);
6589
6590 if (rc == Z_STREAM_END)
6591 return 0;
6592
6593 return rc;
6594 }
6595
6596 /* nic load/unload */
6597
6598 /*
6599 * General service functions
6600 */
6601
6602 /* send a NIG loopback debug packet */
6603 static void bnx2x_lb_pckt(struct bnx2x *bp)
6604 {
6605 u32 wb_write[3];
6606
6607 /* Ethernet source and destination addresses */
6608 wb_write[0] = 0x55555555;
6609 wb_write[1] = 0x55555555;
6610 wb_write[2] = 0x20; /* SOP */
6611 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6612
6613 /* NON-IP protocol */
6614 wb_write[0] = 0x09000000;
6615 wb_write[1] = 0x55555555;
6616 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
6617 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6618 }
6619
6620 /* some of the internal memories
6621 * are not directly readable from the driver
6622 * to test them we send debug packets
6623 */
6624 static int bnx2x_int_mem_test(struct bnx2x *bp)
6625 {
6626 int factor;
6627 int count, i;
6628 u32 val = 0;
6629
6630 if (CHIP_REV_IS_FPGA(bp))
6631 factor = 120;
6632 else if (CHIP_REV_IS_EMUL(bp))
6633 factor = 200;
6634 else
6635 factor = 1;
6636
6637 /* Disable inputs of parser neighbor blocks */
6638 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6639 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6640 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6641 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6642
6643 /* Write 0 to parser credits for CFC search request */
6644 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6645
6646 /* send Ethernet packet */
6647 bnx2x_lb_pckt(bp);
6648
6649 /* TODO do i reset NIG statistic? */
6650 /* Wait until NIG register shows 1 packet of size 0x10 */
6651 count = 1000 * factor;
6652 while (count) {
6653
6654 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6655 val = *bnx2x_sp(bp, wb_data[0]);
6656 if (val == 0x10)
6657 break;
6658
6659 usleep_range(10000, 20000);
6660 count--;
6661 }
6662 if (val != 0x10) {
6663 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6664 return -1;
6665 }
6666
6667 /* Wait until PRS register shows 1 packet */
6668 count = 1000 * factor;
6669 while (count) {
6670 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6671 if (val == 1)
6672 break;
6673
6674 usleep_range(10000, 20000);
6675 count--;
6676 }
6677 if (val != 0x1) {
6678 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6679 return -2;
6680 }
6681
6682 /* Reset and init BRB, PRS */
6683 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6684 msleep(50);
6685 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6686 msleep(50);
6687 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6688 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6689
6690 DP(NETIF_MSG_HW, "part2\n");
6691
6692 /* Disable inputs of parser neighbor blocks */
6693 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6694 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6695 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6696 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6697
6698 /* Write 0 to parser credits for CFC search request */
6699 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6700
6701 /* send 10 Ethernet packets */
6702 for (i = 0; i < 10; i++)
6703 bnx2x_lb_pckt(bp);
6704
6705 /* Wait until NIG register shows 10 + 1
6706 packets of size 11*0x10 = 0xb0 */
6707 count = 1000 * factor;
6708 while (count) {
6709
6710 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6711 val = *bnx2x_sp(bp, wb_data[0]);
6712 if (val == 0xb0)
6713 break;
6714
6715 usleep_range(10000, 20000);
6716 count--;
6717 }
6718 if (val != 0xb0) {
6719 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6720 return -3;
6721 }
6722
6723 /* Wait until PRS register shows 2 packets */
6724 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6725 if (val != 2)
6726 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6727
6728 /* Write 1 to parser credits for CFC search request */
6729 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6730
6731 /* Wait until PRS register shows 3 packets */
6732 msleep(10 * factor);
6733 /* Wait until NIG register shows 1 packet of size 0x10 */
6734 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6735 if (val != 3)
6736 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6737
6738 /* clear NIG EOP FIFO */
6739 for (i = 0; i < 11; i++)
6740 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6741 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6742 if (val != 1) {
6743 BNX2X_ERR("clear of NIG failed\n");
6744 return -4;
6745 }
6746
6747 /* Reset and init BRB, PRS, NIG */
6748 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6749 msleep(50);
6750 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6751 msleep(50);
6752 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6753 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6754 if (!CNIC_SUPPORT(bp))
6755 /* set NIC mode */
6756 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6757
6758 /* Enable inputs of parser neighbor blocks */
6759 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6760 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6761 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6762 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6763
6764 DP(NETIF_MSG_HW, "done\n");
6765
6766 return 0; /* OK */
6767 }
6768
6769 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6770 {
6771 u32 val;
6772
6773 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6774 if (!CHIP_IS_E1x(bp))
6775 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6776 else
6777 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6778 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6779 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6780 /*
6781 * mask read length error interrupts in brb for parser
6782 * (parsing unit and 'checksum and crc' unit)
6783 * these errors are legal (PU reads fixed length and CAC can cause
6784 * read length error on truncated packets)
6785 */
6786 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6787 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6788 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6789 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6790 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6791 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6792 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6793 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6794 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6795 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6796 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6797 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6798 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6799 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6800 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6801 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6802 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6803 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6804 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6805
6806 val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
6807 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6808 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6809 if (!CHIP_IS_E1x(bp))
6810 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6811 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6812 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6813
6814 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6815 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6816 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6817 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6818
6819 if (!CHIP_IS_E1x(bp))
6820 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6821 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6822
6823 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6824 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6825 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6826 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
6827 }
6828
6829 static void bnx2x_reset_common(struct bnx2x *bp)
6830 {
6831 u32 val = 0x1400;
6832
6833 /* reset_common */
6834 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6835 0xd3ffff7f);
6836
6837 if (CHIP_IS_E3(bp)) {
6838 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6839 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6840 }
6841
6842 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6843 }
6844
6845 static void bnx2x_setup_dmae(struct bnx2x *bp)
6846 {
6847 bp->dmae_ready = 0;
6848 spin_lock_init(&bp->dmae_lock);
6849 }
6850
6851 static void bnx2x_init_pxp(struct bnx2x *bp)
6852 {
6853 u16 devctl;
6854 int r_order, w_order;
6855
6856 pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
6857 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6858 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6859 if (bp->mrrs == -1)
6860 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6861 else {
6862 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6863 r_order = bp->mrrs;
6864 }
6865
6866 bnx2x_init_pxp_arb(bp, r_order, w_order);
6867 }
6868
6869 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6870 {
6871 int is_required;
6872 u32 val;
6873 int port;
6874
6875 if (BP_NOMCP(bp))
6876 return;
6877
6878 is_required = 0;
6879 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6880 SHARED_HW_CFG_FAN_FAILURE_MASK;
6881
6882 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6883 is_required = 1;
6884
6885 /*
6886 * The fan failure mechanism is usually related to the PHY type since
6887 * the power consumption of the board is affected by the PHY. Currently,
6888 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6889 */
6890 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6891 for (port = PORT_0; port < PORT_MAX; port++) {
6892 is_required |=
6893 bnx2x_fan_failure_det_req(
6894 bp,
6895 bp->common.shmem_base,
6896 bp->common.shmem2_base,
6897 port);
6898 }
6899
6900 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6901
6902 if (is_required == 0)
6903 return;
6904
6905 /* Fan failure is indicated by SPIO 5 */
6906 bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
6907
6908 /* set to active low mode */
6909 val = REG_RD(bp, MISC_REG_SPIO_INT);
6910 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
6911 REG_WR(bp, MISC_REG_SPIO_INT, val);
6912
6913 /* enable interrupt to signal the IGU */
6914 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6915 val |= MISC_SPIO_SPIO5;
6916 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6917 }
6918
6919 void bnx2x_pf_disable(struct bnx2x *bp)
6920 {
6921 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6922 val &= ~IGU_PF_CONF_FUNC_EN;
6923
6924 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6925 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6926 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6927 }
6928
6929 static void bnx2x__common_init_phy(struct bnx2x *bp)
6930 {
6931 u32 shmem_base[2], shmem2_base[2];
6932 /* Avoid common init in case MFW supports LFA */
6933 if (SHMEM2_RD(bp, size) >
6934 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6935 return;
6936 shmem_base[0] = bp->common.shmem_base;
6937 shmem2_base[0] = bp->common.shmem2_base;
6938 if (!CHIP_IS_E1x(bp)) {
6939 shmem_base[1] =
6940 SHMEM2_RD(bp, other_shmem_base_addr);
6941 shmem2_base[1] =
6942 SHMEM2_RD(bp, other_shmem2_base_addr);
6943 }
6944 bnx2x_acquire_phy_lock(bp);
6945 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6946 bp->common.chip_id);
6947 bnx2x_release_phy_lock(bp);
6948 }
6949
6950 static void bnx2x_config_endianity(struct bnx2x *bp, u32 val)
6951 {
6952 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, val);
6953 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, val);
6954 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, val);
6955 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, val);
6956 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, val);
6957
6958 /* make sure this value is 0 */
6959 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
6960
6961 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, val);
6962 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, val);
6963 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, val);
6964 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, val);
6965 }
6966
6967 static void bnx2x_set_endianity(struct bnx2x *bp)
6968 {
6969 #ifdef __BIG_ENDIAN
6970 bnx2x_config_endianity(bp, 1);
6971 #else
6972 bnx2x_config_endianity(bp, 0);
6973 #endif
6974 }
6975
6976 static void bnx2x_reset_endianity(struct bnx2x *bp)
6977 {
6978 bnx2x_config_endianity(bp, 0);
6979 }
6980
6981 /**
6982 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6983 *
6984 * @bp: driver handle
6985 */
6986 static int bnx2x_init_hw_common(struct bnx2x *bp)
6987 {
6988 u32 val;
6989
6990 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp));
6991
6992 /*
6993 * take the RESET lock to protect undi_unload flow from accessing
6994 * registers while we're resetting the chip
6995 */
6996 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6997
6998 bnx2x_reset_common(bp);
6999 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
7000
7001 val = 0xfffc;
7002 if (CHIP_IS_E3(bp)) {
7003 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
7004 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
7005 }
7006 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
7007
7008 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
7009
7010 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
7011
7012 if (!CHIP_IS_E1x(bp)) {
7013 u8 abs_func_id;
7014
7015 /**
7016 * 4-port mode or 2-port mode we need to turn of master-enable
7017 * for everyone, after that, turn it back on for self.
7018 * so, we disregard multi-function or not, and always disable
7019 * for all functions on the given path, this means 0,2,4,6 for
7020 * path 0 and 1,3,5,7 for path 1
7021 */
7022 for (abs_func_id = BP_PATH(bp);
7023 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
7024 if (abs_func_id == BP_ABS_FUNC(bp)) {
7025 REG_WR(bp,
7026 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
7027 1);
7028 continue;
7029 }
7030
7031 bnx2x_pretend_func(bp, abs_func_id);
7032 /* clear pf enable */
7033 bnx2x_pf_disable(bp);
7034 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7035 }
7036 }
7037
7038 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
7039 if (CHIP_IS_E1(bp)) {
7040 /* enable HW interrupt from PXP on USDM overflow
7041 bit 16 on INT_MASK_0 */
7042 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
7043 }
7044
7045 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
7046 bnx2x_init_pxp(bp);
7047 bnx2x_set_endianity(bp);
7048 bnx2x_ilt_init_page_size(bp, INITOP_SET);
7049
7050 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
7051 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
7052
7053 /* let the HW do it's magic ... */
7054 msleep(100);
7055 /* finish PXP init */
7056 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
7057 if (val != 1) {
7058 BNX2X_ERR("PXP2 CFG failed\n");
7059 return -EBUSY;
7060 }
7061 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
7062 if (val != 1) {
7063 BNX2X_ERR("PXP2 RD_INIT failed\n");
7064 return -EBUSY;
7065 }
7066
7067 /* Timers bug workaround E2 only. We need to set the entire ILT to
7068 * have entries with value "0" and valid bit on.
7069 * This needs to be done by the first PF that is loaded in a path
7070 * (i.e. common phase)
7071 */
7072 if (!CHIP_IS_E1x(bp)) {
7073 /* In E2 there is a bug in the timers block that can cause function 6 / 7
7074 * (i.e. vnic3) to start even if it is marked as "scan-off".
7075 * This occurs when a different function (func2,3) is being marked
7076 * as "scan-off". Real-life scenario for example: if a driver is being
7077 * load-unloaded while func6,7 are down. This will cause the timer to access
7078 * the ilt, translate to a logical address and send a request to read/write.
7079 * Since the ilt for the function that is down is not valid, this will cause
7080 * a translation error which is unrecoverable.
7081 * The Workaround is intended to make sure that when this happens nothing fatal
7082 * will occur. The workaround:
7083 * 1. First PF driver which loads on a path will:
7084 * a. After taking the chip out of reset, by using pretend,
7085 * it will write "0" to the following registers of
7086 * the other vnics.
7087 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
7088 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
7089 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
7090 * And for itself it will write '1' to
7091 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
7092 * dmae-operations (writing to pram for example.)
7093 * note: can be done for only function 6,7 but cleaner this
7094 * way.
7095 * b. Write zero+valid to the entire ILT.
7096 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
7097 * VNIC3 (of that port). The range allocated will be the
7098 * entire ILT. This is needed to prevent ILT range error.
7099 * 2. Any PF driver load flow:
7100 * a. ILT update with the physical addresses of the allocated
7101 * logical pages.
7102 * b. Wait 20msec. - note that this timeout is needed to make
7103 * sure there are no requests in one of the PXP internal
7104 * queues with "old" ILT addresses.
7105 * c. PF enable in the PGLC.
7106 * d. Clear the was_error of the PF in the PGLC. (could have
7107 * occurred while driver was down)
7108 * e. PF enable in the CFC (WEAK + STRONG)
7109 * f. Timers scan enable
7110 * 3. PF driver unload flow:
7111 * a. Clear the Timers scan_en.
7112 * b. Polling for scan_on=0 for that PF.
7113 * c. Clear the PF enable bit in the PXP.
7114 * d. Clear the PF enable in the CFC (WEAK + STRONG)
7115 * e. Write zero+valid to all ILT entries (The valid bit must
7116 * stay set)
7117 * f. If this is VNIC 3 of a port then also init
7118 * first_timers_ilt_entry to zero and last_timers_ilt_entry
7119 * to the last entry in the ILT.
7120 *
7121 * Notes:
7122 * Currently the PF error in the PGLC is non recoverable.
7123 * In the future the there will be a recovery routine for this error.
7124 * Currently attention is masked.
7125 * Having an MCP lock on the load/unload process does not guarantee that
7126 * there is no Timer disable during Func6/7 enable. This is because the
7127 * Timers scan is currently being cleared by the MCP on FLR.
7128 * Step 2.d can be done only for PF6/7 and the driver can also check if
7129 * there is error before clearing it. But the flow above is simpler and
7130 * more general.
7131 * All ILT entries are written by zero+valid and not just PF6/7
7132 * ILT entries since in the future the ILT entries allocation for
7133 * PF-s might be dynamic.
7134 */
7135 struct ilt_client_info ilt_cli;
7136 struct bnx2x_ilt ilt;
7137 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7138 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
7139
7140 /* initialize dummy TM client */
7141 ilt_cli.start = 0;
7142 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7143 ilt_cli.client_num = ILT_CLIENT_TM;
7144
7145 /* Step 1: set zeroes to all ilt page entries with valid bit on
7146 * Step 2: set the timers first/last ilt entry to point
7147 * to the entire range to prevent ILT range error for 3rd/4th
7148 * vnic (this code assumes existence of the vnic)
7149 *
7150 * both steps performed by call to bnx2x_ilt_client_init_op()
7151 * with dummy TM client
7152 *
7153 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
7154 * and his brother are split registers
7155 */
7156 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
7157 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
7158 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7159
7160 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
7161 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
7162 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
7163 }
7164
7165 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
7166 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
7167
7168 if (!CHIP_IS_E1x(bp)) {
7169 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
7170 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
7171 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
7172
7173 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
7174
7175 /* let the HW do it's magic ... */
7176 do {
7177 msleep(200);
7178 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
7179 } while (factor-- && (val != 1));
7180
7181 if (val != 1) {
7182 BNX2X_ERR("ATC_INIT failed\n");
7183 return -EBUSY;
7184 }
7185 }
7186
7187 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
7188
7189 bnx2x_iov_init_dmae(bp);
7190
7191 /* clean the DMAE memory */
7192 bp->dmae_ready = 1;
7193 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
7194
7195 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
7196
7197 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
7198
7199 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
7200
7201 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
7202
7203 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
7204 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
7205 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
7206 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
7207
7208 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
7209
7210 /* QM queues pointers table */
7211 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
7212
7213 /* soft reset pulse */
7214 REG_WR(bp, QM_REG_SOFT_RESET, 1);
7215 REG_WR(bp, QM_REG_SOFT_RESET, 0);
7216
7217 if (CNIC_SUPPORT(bp))
7218 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
7219
7220 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
7221
7222 if (!CHIP_REV_IS_SLOW(bp))
7223 /* enable hw interrupt from doorbell Q */
7224 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
7225
7226 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
7227
7228 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
7229 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
7230
7231 if (!CHIP_IS_E1(bp))
7232 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
7233
7234 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
7235 if (IS_MF_AFEX(bp)) {
7236 /* configure that VNTag and VLAN headers must be
7237 * received in afex mode
7238 */
7239 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
7240 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
7241 REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
7242 REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
7243 REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
7244 } else {
7245 /* Bit-map indicating which L2 hdrs may appear
7246 * after the basic Ethernet header
7247 */
7248 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
7249 bp->path_has_ovlan ? 7 : 6);
7250 }
7251 }
7252
7253 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
7254 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
7255 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
7256 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
7257
7258 if (!CHIP_IS_E1x(bp)) {
7259 /* reset VFC memories */
7260 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7261 VFC_MEMORIES_RST_REG_CAM_RST |
7262 VFC_MEMORIES_RST_REG_RAM_RST);
7263 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7264 VFC_MEMORIES_RST_REG_CAM_RST |
7265 VFC_MEMORIES_RST_REG_RAM_RST);
7266
7267 msleep(20);
7268 }
7269
7270 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
7271 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
7272 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
7273 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
7274
7275 /* sync semi rtc */
7276 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7277 0x80000000);
7278 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7279 0x80000000);
7280
7281 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
7282 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
7283 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
7284
7285 if (!CHIP_IS_E1x(bp)) {
7286 if (IS_MF_AFEX(bp)) {
7287 /* configure that VNTag and VLAN headers must be
7288 * sent in afex mode
7289 */
7290 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
7291 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
7292 REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
7293 REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
7294 REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
7295 } else {
7296 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
7297 bp->path_has_ovlan ? 7 : 6);
7298 }
7299 }
7300
7301 REG_WR(bp, SRC_REG_SOFT_RST, 1);
7302
7303 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
7304
7305 if (CNIC_SUPPORT(bp)) {
7306 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
7307 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
7308 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
7309 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
7310 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
7311 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
7312 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
7313 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
7314 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
7315 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
7316 }
7317 REG_WR(bp, SRC_REG_SOFT_RST, 0);
7318
7319 if (sizeof(union cdu_context) != 1024)
7320 /* we currently assume that a context is 1024 bytes */
7321 dev_alert(&bp->pdev->dev,
7322 "please adjust the size of cdu_context(%ld)\n",
7323 (long)sizeof(union cdu_context));
7324
7325 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
7326 val = (4 << 24) + (0 << 12) + 1024;
7327 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
7328
7329 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
7330 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
7331 /* enable context validation interrupt from CFC */
7332 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
7333
7334 /* set the thresholds to prevent CFC/CDU race */
7335 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
7336
7337 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
7338
7339 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
7340 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
7341
7342 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
7343 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
7344
7345 /* Reset PCIE errors for debug */
7346 REG_WR(bp, 0x2814, 0xffffffff);
7347 REG_WR(bp, 0x3820, 0xffffffff);
7348
7349 if (!CHIP_IS_E1x(bp)) {
7350 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
7351 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
7352 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
7353 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
7354 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
7355 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
7356 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
7357 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
7358 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
7359 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
7360 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
7361 }
7362
7363 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
7364 if (!CHIP_IS_E1(bp)) {
7365 /* in E3 this done in per-port section */
7366 if (!CHIP_IS_E3(bp))
7367 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
7368 }
7369 if (CHIP_IS_E1H(bp))
7370 /* not applicable for E2 (and above ...) */
7371 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
7372
7373 if (CHIP_REV_IS_SLOW(bp))
7374 msleep(200);
7375
7376 /* finish CFC init */
7377 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
7378 if (val != 1) {
7379 BNX2X_ERR("CFC LL_INIT failed\n");
7380 return -EBUSY;
7381 }
7382 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
7383 if (val != 1) {
7384 BNX2X_ERR("CFC AC_INIT failed\n");
7385 return -EBUSY;
7386 }
7387 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
7388 if (val != 1) {
7389 BNX2X_ERR("CFC CAM_INIT failed\n");
7390 return -EBUSY;
7391 }
7392 REG_WR(bp, CFC_REG_DEBUG0, 0);
7393
7394 if (CHIP_IS_E1(bp)) {
7395 /* read NIG statistic
7396 to see if this is our first up since powerup */
7397 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
7398 val = *bnx2x_sp(bp, wb_data[0]);
7399
7400 /* do internal memory self test */
7401 if ((val == 0) && bnx2x_int_mem_test(bp)) {
7402 BNX2X_ERR("internal mem self test failed\n");
7403 return -EBUSY;
7404 }
7405 }
7406
7407 bnx2x_setup_fan_failure_detection(bp);
7408
7409 /* clear PXP2 attentions */
7410 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
7411
7412 bnx2x_enable_blocks_attention(bp);
7413 bnx2x_enable_blocks_parity(bp);
7414
7415 if (!BP_NOMCP(bp)) {
7416 if (CHIP_IS_E1x(bp))
7417 bnx2x__common_init_phy(bp);
7418 } else
7419 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
7420
7421 return 0;
7422 }
7423
7424 /**
7425 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7426 *
7427 * @bp: driver handle
7428 */
7429 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
7430 {
7431 int rc = bnx2x_init_hw_common(bp);
7432
7433 if (rc)
7434 return rc;
7435
7436 /* In E2 2-PORT mode, same ext phy is used for the two paths */
7437 if (!BP_NOMCP(bp))
7438 bnx2x__common_init_phy(bp);
7439
7440 return 0;
7441 }
7442
7443 static int bnx2x_init_hw_port(struct bnx2x *bp)
7444 {
7445 int port = BP_PORT(bp);
7446 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
7447 u32 low, high;
7448 u32 val, reg;
7449
7450 DP(NETIF_MSG_HW, "starting port init port %d\n", port);
7451
7452 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7453
7454 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7455 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7456 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7457
7458 /* Timers bug workaround: disables the pf_master bit in pglue at
7459 * common phase, we need to enable it here before any dmae access are
7460 * attempted. Therefore we manually added the enable-master to the
7461 * port phase (it also happens in the function phase)
7462 */
7463 if (!CHIP_IS_E1x(bp))
7464 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7465
7466 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7467 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7468 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7469 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7470
7471 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7472 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7473 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7474 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7475
7476 /* QM cid (connection) count */
7477 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
7478
7479 if (CNIC_SUPPORT(bp)) {
7480 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7481 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7482 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7483 }
7484
7485 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7486
7487 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7488
7489 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
7490
7491 if (IS_MF(bp))
7492 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7493 else if (bp->dev->mtu > 4096) {
7494 if (bp->flags & ONE_PORT_FLAG)
7495 low = 160;
7496 else {
7497 val = bp->dev->mtu;
7498 /* (24*1024 + val*4)/256 */
7499 low = 96 + (val/64) +
7500 ((val % 64) ? 1 : 0);
7501 }
7502 } else
7503 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7504 high = low + 56; /* 14*1024/256 */
7505 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7506 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
7507 }
7508
7509 if (CHIP_MODE_IS_4_PORT(bp))
7510 REG_WR(bp, (BP_PORT(bp) ?
7511 BRB1_REG_MAC_GUARANTIED_1 :
7512 BRB1_REG_MAC_GUARANTIED_0), 40);
7513
7514 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7515 if (CHIP_IS_E3B0(bp)) {
7516 if (IS_MF_AFEX(bp)) {
7517 /* configure headers for AFEX mode */
7518 REG_WR(bp, BP_PORT(bp) ?
7519 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7520 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7521 REG_WR(bp, BP_PORT(bp) ?
7522 PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7523 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7524 REG_WR(bp, BP_PORT(bp) ?
7525 PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7526 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7527 } else {
7528 /* Ovlan exists only if we are in multi-function +
7529 * switch-dependent mode, in switch-independent there
7530 * is no ovlan headers
7531 */
7532 REG_WR(bp, BP_PORT(bp) ?
7533 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7534 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7535 (bp->path_has_ovlan ? 7 : 6));
7536 }
7537 }
7538
7539 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7540 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7541 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7542 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7543
7544 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7545 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7546 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7547 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7548
7549 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7550 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7551
7552 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7553
7554 if (CHIP_IS_E1x(bp)) {
7555 /* configure PBF to work without PAUSE mtu 9000 */
7556 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
7557
7558 /* update threshold */
7559 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7560 /* update init credit */
7561 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
7562
7563 /* probe changes */
7564 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7565 udelay(50);
7566 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7567 }
7568
7569 if (CNIC_SUPPORT(bp))
7570 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7571
7572 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7573 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7574
7575 if (CHIP_IS_E1(bp)) {
7576 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7577 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7578 }
7579 bnx2x_init_block(bp, BLOCK_HC, init_phase);
7580
7581 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7582
7583 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7584 /* init aeu_mask_attn_func_0/1:
7585 * - SF mode: bits 3-7 are masked. Only bits 0-2 are in use
7586 * - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
7587 * bits 4-7 are used for "per vn group attention" */
7588 val = IS_MF(bp) ? 0xF7 : 0x7;
7589 /* Enable DCBX attention for all but E1 */
7590 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7591 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
7592
7593 /* SCPAD_PARITY should NOT trigger close the gates */
7594 reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0;
7595 REG_WR(bp, reg,
7596 REG_RD(bp, reg) &
7597 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7598
7599 reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0;
7600 REG_WR(bp, reg,
7601 REG_RD(bp, reg) &
7602 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7603
7604 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7605
7606 if (!CHIP_IS_E1x(bp)) {
7607 /* Bit-map indicating which L2 hdrs may appear after the
7608 * basic Ethernet header
7609 */
7610 if (IS_MF_AFEX(bp))
7611 REG_WR(bp, BP_PORT(bp) ?
7612 NIG_REG_P1_HDRS_AFTER_BASIC :
7613 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7614 else
7615 REG_WR(bp, BP_PORT(bp) ?
7616 NIG_REG_P1_HDRS_AFTER_BASIC :
7617 NIG_REG_P0_HDRS_AFTER_BASIC,
7618 IS_MF_SD(bp) ? 7 : 6);
7619
7620 if (CHIP_IS_E3(bp))
7621 REG_WR(bp, BP_PORT(bp) ?
7622 NIG_REG_LLH1_MF_MODE :
7623 NIG_REG_LLH_MF_MODE, IS_MF(bp));
7624 }
7625 if (!CHIP_IS_E3(bp))
7626 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
7627
7628 if (!CHIP_IS_E1(bp)) {
7629 /* 0x2 disable mf_ov, 0x1 enable */
7630 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
7631 (IS_MF_SD(bp) ? 0x1 : 0x2));
7632
7633 if (!CHIP_IS_E1x(bp)) {
7634 val = 0;
7635 switch (bp->mf_mode) {
7636 case MULTI_FUNCTION_SD:
7637 val = 1;
7638 break;
7639 case MULTI_FUNCTION_SI:
7640 case MULTI_FUNCTION_AFEX:
7641 val = 2;
7642 break;
7643 }
7644
7645 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7646 NIG_REG_LLH0_CLS_TYPE), val);
7647 }
7648 {
7649 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7650 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7651 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7652 }
7653 }
7654
7655 /* If SPIO5 is set to generate interrupts, enable it for this port */
7656 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
7657 if (val & MISC_SPIO_SPIO5) {
7658 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7659 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7660 val = REG_RD(bp, reg_addr);
7661 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
7662 REG_WR(bp, reg_addr, val);
7663 }
7664
7665 return 0;
7666 }
7667
7668 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7669 {
7670 int reg;
7671 u32 wb_write[2];
7672
7673 if (CHIP_IS_E1(bp))
7674 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
7675 else
7676 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
7677
7678 wb_write[0] = ONCHIP_ADDR1(addr);
7679 wb_write[1] = ONCHIP_ADDR2(addr);
7680 REG_WR_DMAE(bp, reg, wb_write, 2);
7681 }
7682
7683 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
7684 {
7685 u32 data, ctl, cnt = 100;
7686 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7687 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7688 u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7689 u32 sb_bit = 1 << (idu_sb_id%32);
7690 u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
7691 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7692
7693 /* Not supported in BC mode */
7694 if (CHIP_INT_MODE_IS_BC(bp))
7695 return;
7696
7697 data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7698 << IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
7699 IGU_REGULAR_CLEANUP_SET |
7700 IGU_REGULAR_BCLEANUP;
7701
7702 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
7703 func_encode << IGU_CTRL_REG_FID_SHIFT |
7704 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7705
7706 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7707 data, igu_addr_data);
7708 REG_WR(bp, igu_addr_data, data);
7709 mmiowb();
7710 barrier();
7711 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7712 ctl, igu_addr_ctl);
7713 REG_WR(bp, igu_addr_ctl, ctl);
7714 mmiowb();
7715 barrier();
7716
7717 /* wait for clean up to finish */
7718 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7719 msleep(20);
7720
7721 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7722 DP(NETIF_MSG_HW,
7723 "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7724 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7725 }
7726 }
7727
7728 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7729 {
7730 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7731 }
7732
7733 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7734 {
7735 u32 i, base = FUNC_ILT_BASE(func);
7736 for (i = base; i < base + ILT_PER_FUNC; i++)
7737 bnx2x_ilt_wr(bp, i, 0);
7738 }
7739
7740 static void bnx2x_init_searcher(struct bnx2x *bp)
7741 {
7742 int port = BP_PORT(bp);
7743 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7744 /* T1 hash bits value determines the T1 number of entries */
7745 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7746 }
7747
7748 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7749 {
7750 int rc;
7751 struct bnx2x_func_state_params func_params = {NULL};
7752 struct bnx2x_func_switch_update_params *switch_update_params =
7753 &func_params.params.switch_update;
7754
7755 /* Prepare parameters for function state transitions */
7756 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7757 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7758
7759 func_params.f_obj = &bp->func_obj;
7760 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7761
7762 /* Function parameters */
7763 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
7764 &switch_update_params->changes);
7765 if (suspend)
7766 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND,
7767 &switch_update_params->changes);
7768
7769 rc = bnx2x_func_state_change(bp, &func_params);
7770
7771 return rc;
7772 }
7773
7774 static int bnx2x_reset_nic_mode(struct bnx2x *bp)
7775 {
7776 int rc, i, port = BP_PORT(bp);
7777 int vlan_en = 0, mac_en[NUM_MACS];
7778
7779 /* Close input from network */
7780 if (bp->mf_mode == SINGLE_FUNCTION) {
7781 bnx2x_set_rx_filter(&bp->link_params, 0);
7782 } else {
7783 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7784 NIG_REG_LLH0_FUNC_EN);
7785 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7786 NIG_REG_LLH0_FUNC_EN, 0);
7787 for (i = 0; i < NUM_MACS; i++) {
7788 mac_en[i] = REG_RD(bp, port ?
7789 (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7790 4 * i) :
7791 (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7792 4 * i));
7793 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7794 4 * i) :
7795 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7796 }
7797 }
7798
7799 /* Close BMC to host */
7800 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7801 NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7802
7803 /* Suspend Tx switching to the PF. Completion of this ramrod
7804 * further guarantees that all the packets of that PF / child
7805 * VFs in BRB were processed by the Parser, so it is safe to
7806 * change the NIC_MODE register.
7807 */
7808 rc = bnx2x_func_switch_update(bp, 1);
7809 if (rc) {
7810 BNX2X_ERR("Can't suspend tx-switching!\n");
7811 return rc;
7812 }
7813
7814 /* Change NIC_MODE register */
7815 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7816
7817 /* Open input from network */
7818 if (bp->mf_mode == SINGLE_FUNCTION) {
7819 bnx2x_set_rx_filter(&bp->link_params, 1);
7820 } else {
7821 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7822 NIG_REG_LLH0_FUNC_EN, vlan_en);
7823 for (i = 0; i < NUM_MACS; i++) {
7824 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7825 4 * i) :
7826 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7827 mac_en[i]);
7828 }
7829 }
7830
7831 /* Enable BMC to host */
7832 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7833 NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7834
7835 /* Resume Tx switching to the PF */
7836 rc = bnx2x_func_switch_update(bp, 0);
7837 if (rc) {
7838 BNX2X_ERR("Can't resume tx-switching!\n");
7839 return rc;
7840 }
7841
7842 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7843 return 0;
7844 }
7845
7846 int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7847 {
7848 int rc;
7849
7850 bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7851
7852 if (CONFIGURE_NIC_MODE(bp)) {
7853 /* Configure searcher as part of function hw init */
7854 bnx2x_init_searcher(bp);
7855
7856 /* Reset NIC mode */
7857 rc = bnx2x_reset_nic_mode(bp);
7858 if (rc)
7859 BNX2X_ERR("Can't change NIC mode!\n");
7860 return rc;
7861 }
7862
7863 return 0;
7864 }
7865
7866 static int bnx2x_init_hw_func(struct bnx2x *bp)
7867 {
7868 int port = BP_PORT(bp);
7869 int func = BP_FUNC(bp);
7870 int init_phase = PHASE_PF0 + func;
7871 struct bnx2x_ilt *ilt = BP_ILT(bp);
7872 u16 cdu_ilt_start;
7873 u32 addr, val;
7874 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7875 int i, main_mem_width, rc;
7876
7877 DP(NETIF_MSG_HW, "starting func init func %d\n", func);
7878
7879 /* FLR cleanup - hmmm */
7880 if (!CHIP_IS_E1x(bp)) {
7881 rc = bnx2x_pf_flr_clnup(bp);
7882 if (rc) {
7883 bnx2x_fw_dump(bp);
7884 return rc;
7885 }
7886 }
7887
7888 /* set MSI reconfigure capability */
7889 if (bp->common.int_block == INT_BLOCK_HC) {
7890 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7891 val = REG_RD(bp, addr);
7892 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7893 REG_WR(bp, addr, val);
7894 }
7895
7896 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7897 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7898
7899 ilt = BP_ILT(bp);
7900 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7901
7902 if (IS_SRIOV(bp))
7903 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7904 cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7905
7906 /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7907 * those of the VFs, so start line should be reset
7908 */
7909 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7910 for (i = 0; i < L2_ILT_LINES(bp); i++) {
7911 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7912 ilt->lines[cdu_ilt_start + i].page_mapping =
7913 bp->context[i].cxt_mapping;
7914 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7915 }
7916
7917 bnx2x_ilt_init_op(bp, INITOP_SET);
7918
7919 if (!CONFIGURE_NIC_MODE(bp)) {
7920 bnx2x_init_searcher(bp);
7921 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7922 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7923 } else {
7924 /* Set NIC mode */
7925 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7926 DP(NETIF_MSG_IFUP, "NIC MODE configured\n");
7927 }
7928
7929 if (!CHIP_IS_E1x(bp)) {
7930 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7931
7932 /* Turn on a single ISR mode in IGU if driver is going to use
7933 * INT#x or MSI
7934 */
7935 if (!(bp->flags & USING_MSIX_FLAG))
7936 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7937 /*
7938 * Timers workaround bug: function init part.
7939 * Need to wait 20msec after initializing ILT,
7940 * needed to make sure there are no requests in
7941 * one of the PXP internal queues with "old" ILT addresses
7942 */
7943 msleep(20);
7944 /*
7945 * Master enable - Due to WB DMAE writes performed before this
7946 * register is re-initialized as part of the regular function
7947 * init
7948 */
7949 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7950 /* Enable the function in IGU */
7951 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7952 }
7953
7954 bp->dmae_ready = 1;
7955
7956 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7957
7958 if (!CHIP_IS_E1x(bp))
7959 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
7960
7961 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7962 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7963 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7964 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7965 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7966 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7967 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7968 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7969 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7970 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7971 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7972 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7973 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7974
7975 if (!CHIP_IS_E1x(bp))
7976 REG_WR(bp, QM_REG_PF_EN, 1);
7977
7978 if (!CHIP_IS_E1x(bp)) {
7979 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7980 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7981 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7982 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7983 }
7984 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7985
7986 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7987 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7988 REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */
7989
7990 bnx2x_iov_init_dq(bp);
7991
7992 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7993 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7994 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7995 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7996 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7997 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7998 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7999 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
8000 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
8001 if (!CHIP_IS_E1x(bp))
8002 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
8003
8004 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
8005
8006 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
8007
8008 if (!CHIP_IS_E1x(bp))
8009 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
8010
8011 if (IS_MF(bp)) {
8012 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) {
8013 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
8014 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8,
8015 bp->mf_ov);
8016 }
8017 }
8018
8019 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
8020
8021 /* HC init per function */
8022 if (bp->common.int_block == INT_BLOCK_HC) {
8023 if (CHIP_IS_E1H(bp)) {
8024 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8025
8026 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8027 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8028 }
8029 bnx2x_init_block(bp, BLOCK_HC, init_phase);
8030
8031 } else {
8032 int num_segs, sb_idx, prod_offset;
8033
8034 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8035
8036 if (!CHIP_IS_E1x(bp)) {
8037 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8038 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8039 }
8040
8041 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
8042
8043 if (!CHIP_IS_E1x(bp)) {
8044 int dsb_idx = 0;
8045 /**
8046 * Producer memory:
8047 * E2 mode: address 0-135 match to the mapping memory;
8048 * 136 - PF0 default prod; 137 - PF1 default prod;
8049 * 138 - PF2 default prod; 139 - PF3 default prod;
8050 * 140 - PF0 attn prod; 141 - PF1 attn prod;
8051 * 142 - PF2 attn prod; 143 - PF3 attn prod;
8052 * 144-147 reserved.
8053 *
8054 * E1.5 mode - In backward compatible mode;
8055 * for non default SB; each even line in the memory
8056 * holds the U producer and each odd line hold
8057 * the C producer. The first 128 producers are for
8058 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
8059 * producers are for the DSB for each PF.
8060 * Each PF has five segments: (the order inside each
8061 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
8062 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
8063 * 144-147 attn prods;
8064 */
8065 /* non-default-status-blocks */
8066 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8067 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
8068 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
8069 prod_offset = (bp->igu_base_sb + sb_idx) *
8070 num_segs;
8071
8072 for (i = 0; i < num_segs; i++) {
8073 addr = IGU_REG_PROD_CONS_MEMORY +
8074 (prod_offset + i) * 4;
8075 REG_WR(bp, addr, 0);
8076 }
8077 /* send consumer update with value 0 */
8078 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
8079 USTORM_ID, 0, IGU_INT_NOP, 1);
8080 bnx2x_igu_clear_sb(bp,
8081 bp->igu_base_sb + sb_idx);
8082 }
8083
8084 /* default-status-blocks */
8085 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8086 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
8087
8088 if (CHIP_MODE_IS_4_PORT(bp))
8089 dsb_idx = BP_FUNC(bp);
8090 else
8091 dsb_idx = BP_VN(bp);
8092
8093 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
8094 IGU_BC_BASE_DSB_PROD + dsb_idx :
8095 IGU_NORM_BASE_DSB_PROD + dsb_idx);
8096
8097 /*
8098 * igu prods come in chunks of E1HVN_MAX (4) -
8099 * does not matters what is the current chip mode
8100 */
8101 for (i = 0; i < (num_segs * E1HVN_MAX);
8102 i += E1HVN_MAX) {
8103 addr = IGU_REG_PROD_CONS_MEMORY +
8104 (prod_offset + i)*4;
8105 REG_WR(bp, addr, 0);
8106 }
8107 /* send consumer update with 0 */
8108 if (CHIP_INT_MODE_IS_BC(bp)) {
8109 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8110 USTORM_ID, 0, IGU_INT_NOP, 1);
8111 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8112 CSTORM_ID, 0, IGU_INT_NOP, 1);
8113 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8114 XSTORM_ID, 0, IGU_INT_NOP, 1);
8115 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8116 TSTORM_ID, 0, IGU_INT_NOP, 1);
8117 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8118 ATTENTION_ID, 0, IGU_INT_NOP, 1);
8119 } else {
8120 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8121 USTORM_ID, 0, IGU_INT_NOP, 1);
8122 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8123 ATTENTION_ID, 0, IGU_INT_NOP, 1);
8124 }
8125 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
8126
8127 /* !!! These should become driver const once
8128 rf-tool supports split-68 const */
8129 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
8130 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
8131 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
8132 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
8133 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
8134 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
8135 }
8136 }
8137
8138 /* Reset PCIE errors for debug */
8139 REG_WR(bp, 0x2114, 0xffffffff);
8140 REG_WR(bp, 0x2120, 0xffffffff);
8141
8142 if (CHIP_IS_E1x(bp)) {
8143 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
8144 main_mem_base = HC_REG_MAIN_MEMORY +
8145 BP_PORT(bp) * (main_mem_size * 4);
8146 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
8147 main_mem_width = 8;
8148
8149 val = REG_RD(bp, main_mem_prty_clr);
8150 if (val)
8151 DP(NETIF_MSG_HW,
8152 "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
8153 val);
8154
8155 /* Clear "false" parity errors in MSI-X table */
8156 for (i = main_mem_base;
8157 i < main_mem_base + main_mem_size * 4;
8158 i += main_mem_width) {
8159 bnx2x_read_dmae(bp, i, main_mem_width / 4);
8160 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
8161 i, main_mem_width / 4);
8162 }
8163 /* Clear HC parity attention */
8164 REG_RD(bp, main_mem_prty_clr);
8165 }
8166
8167 #ifdef BNX2X_STOP_ON_ERROR
8168 /* Enable STORMs SP logging */
8169 REG_WR8(bp, BAR_USTRORM_INTMEM +
8170 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8171 REG_WR8(bp, BAR_TSTRORM_INTMEM +
8172 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8173 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8174 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8175 REG_WR8(bp, BAR_XSTRORM_INTMEM +
8176 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8177 #endif
8178
8179 bnx2x_phy_probe(&bp->link_params);
8180
8181 return 0;
8182 }
8183
8184 void bnx2x_free_mem_cnic(struct bnx2x *bp)
8185 {
8186 bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
8187
8188 if (!CHIP_IS_E1x(bp))
8189 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
8190 sizeof(struct host_hc_status_block_e2));
8191 else
8192 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
8193 sizeof(struct host_hc_status_block_e1x));
8194
8195 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8196 }
8197
8198 void bnx2x_free_mem(struct bnx2x *bp)
8199 {
8200 int i;
8201
8202 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
8203 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
8204
8205 if (IS_VF(bp))
8206 return;
8207
8208 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
8209 sizeof(struct host_sp_status_block));
8210
8211 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
8212 sizeof(struct bnx2x_slowpath));
8213
8214 for (i = 0; i < L2_ILT_LINES(bp); i++)
8215 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
8216 bp->context[i].size);
8217 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
8218
8219 BNX2X_FREE(bp->ilt->lines);
8220
8221 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
8222
8223 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
8224 BCM_PAGE_SIZE * NUM_EQ_PAGES);
8225
8226 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8227
8228 bnx2x_iov_free_mem(bp);
8229 }
8230
8231 int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
8232 {
8233 if (!CHIP_IS_E1x(bp)) {
8234 /* size = the status block + ramrod buffers */
8235 bp->cnic_sb.e2_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8236 sizeof(struct host_hc_status_block_e2));
8237 if (!bp->cnic_sb.e2_sb)
8238 goto alloc_mem_err;
8239 } else {
8240 bp->cnic_sb.e1x_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8241 sizeof(struct host_hc_status_block_e1x));
8242 if (!bp->cnic_sb.e1x_sb)
8243 goto alloc_mem_err;
8244 }
8245
8246 if (CONFIGURE_NIC_MODE(bp) && !bp->t2) {
8247 /* allocate searcher T2 table, as it wasn't allocated before */
8248 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8249 if (!bp->t2)
8250 goto alloc_mem_err;
8251 }
8252
8253 /* write address to which L5 should insert its values */
8254 bp->cnic_eth_dev.addr_drv_info_to_mcp =
8255 &bp->slowpath->drv_info_to_mcp;
8256
8257 if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
8258 goto alloc_mem_err;
8259
8260 return 0;
8261
8262 alloc_mem_err:
8263 bnx2x_free_mem_cnic(bp);
8264 BNX2X_ERR("Can't allocate memory\n");
8265 return -ENOMEM;
8266 }
8267
8268 int bnx2x_alloc_mem(struct bnx2x *bp)
8269 {
8270 int i, allocated, context_size;
8271
8272 if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) {
8273 /* allocate searcher T2 table */
8274 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8275 if (!bp->t2)
8276 goto alloc_mem_err;
8277 }
8278
8279 bp->def_status_blk = BNX2X_PCI_ALLOC(&bp->def_status_blk_mapping,
8280 sizeof(struct host_sp_status_block));
8281 if (!bp->def_status_blk)
8282 goto alloc_mem_err;
8283
8284 bp->slowpath = BNX2X_PCI_ALLOC(&bp->slowpath_mapping,
8285 sizeof(struct bnx2x_slowpath));
8286 if (!bp->slowpath)
8287 goto alloc_mem_err;
8288
8289 /* Allocate memory for CDU context:
8290 * This memory is allocated separately and not in the generic ILT
8291 * functions because CDU differs in few aspects:
8292 * 1. There are multiple entities allocating memory for context -
8293 * 'regular' driver, CNIC and SRIOV driver. Each separately controls
8294 * its own ILT lines.
8295 * 2. Since CDU page-size is not a single 4KB page (which is the case
8296 * for the other ILT clients), to be efficient we want to support
8297 * allocation of sub-page-size in the last entry.
8298 * 3. Context pointers are used by the driver to pass to FW / update
8299 * the context (for the other ILT clients the pointers are used just to
8300 * free the memory during unload).
8301 */
8302 context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
8303
8304 for (i = 0, allocated = 0; allocated < context_size; i++) {
8305 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
8306 (context_size - allocated));
8307 bp->context[i].vcxt = BNX2X_PCI_ALLOC(&bp->context[i].cxt_mapping,
8308 bp->context[i].size);
8309 if (!bp->context[i].vcxt)
8310 goto alloc_mem_err;
8311 allocated += bp->context[i].size;
8312 }
8313 bp->ilt->lines = kcalloc(ILT_MAX_LINES, sizeof(struct ilt_line),
8314 GFP_KERNEL);
8315 if (!bp->ilt->lines)
8316 goto alloc_mem_err;
8317
8318 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
8319 goto alloc_mem_err;
8320
8321 if (bnx2x_iov_alloc_mem(bp))
8322 goto alloc_mem_err;
8323
8324 /* Slow path ring */
8325 bp->spq = BNX2X_PCI_ALLOC(&bp->spq_mapping, BCM_PAGE_SIZE);
8326 if (!bp->spq)
8327 goto alloc_mem_err;
8328
8329 /* EQ */
8330 bp->eq_ring = BNX2X_PCI_ALLOC(&bp->eq_mapping,
8331 BCM_PAGE_SIZE * NUM_EQ_PAGES);
8332 if (!bp->eq_ring)
8333 goto alloc_mem_err;
8334
8335 return 0;
8336
8337 alloc_mem_err:
8338 bnx2x_free_mem(bp);
8339 BNX2X_ERR("Can't allocate memory\n");
8340 return -ENOMEM;
8341 }
8342
8343 /*
8344 * Init service functions
8345 */
8346
8347 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
8348 struct bnx2x_vlan_mac_obj *obj, bool set,
8349 int mac_type, unsigned long *ramrod_flags)
8350 {
8351 int rc;
8352 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
8353
8354 memset(&ramrod_param, 0, sizeof(ramrod_param));
8355
8356 /* Fill general parameters */
8357 ramrod_param.vlan_mac_obj = obj;
8358 ramrod_param.ramrod_flags = *ramrod_flags;
8359
8360 /* Fill a user request section if needed */
8361 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8362 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
8363
8364 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
8365
8366 /* Set the command: ADD or DEL */
8367 if (set)
8368 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8369 else
8370 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
8371 }
8372
8373 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
8374
8375 if (rc == -EEXIST) {
8376 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8377 /* do not treat adding same MAC as error */
8378 rc = 0;
8379 } else if (rc < 0)
8380 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
8381
8382 return rc;
8383 }
8384
8385 int bnx2x_del_all_macs(struct bnx2x *bp,
8386 struct bnx2x_vlan_mac_obj *mac_obj,
8387 int mac_type, bool wait_for_comp)
8388 {
8389 int rc;
8390 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
8391
8392 /* Wait for completion of requested */
8393 if (wait_for_comp)
8394 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8395
8396 /* Set the mac type of addresses we want to clear */
8397 __set_bit(mac_type, &vlan_mac_flags);
8398
8399 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
8400 if (rc < 0)
8401 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
8402
8403 return rc;
8404 }
8405
8406 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
8407 {
8408 if (IS_PF(bp)) {
8409 unsigned long ramrod_flags = 0;
8410
8411 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
8412 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8413 return bnx2x_set_mac_one(bp, bp->dev->dev_addr,
8414 &bp->sp_objs->mac_obj, set,
8415 BNX2X_ETH_MAC, &ramrod_flags);
8416 } else { /* vf */
8417 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr,
8418 bp->fp->index, true);
8419 }
8420 }
8421
8422 int bnx2x_setup_leading(struct bnx2x *bp)
8423 {
8424 if (IS_PF(bp))
8425 return bnx2x_setup_queue(bp, &bp->fp[0], true);
8426 else /* VF */
8427 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true);
8428 }
8429
8430 /**
8431 * bnx2x_set_int_mode - configure interrupt mode
8432 *
8433 * @bp: driver handle
8434 *
8435 * In case of MSI-X it will also try to enable MSI-X.
8436 */
8437 int bnx2x_set_int_mode(struct bnx2x *bp)
8438 {
8439 int rc = 0;
8440
8441 if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) {
8442 BNX2X_ERR("VF not loaded since interrupt mode not msix\n");
8443 return -EINVAL;
8444 }
8445
8446 switch (int_mode) {
8447 case BNX2X_INT_MODE_MSIX:
8448 /* attempt to enable msix */
8449 rc = bnx2x_enable_msix(bp);
8450
8451 /* msix attained */
8452 if (!rc)
8453 return 0;
8454
8455 /* vfs use only msix */
8456 if (rc && IS_VF(bp))
8457 return rc;
8458
8459 /* failed to enable multiple MSI-X */
8460 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
8461 bp->num_queues,
8462 1 + bp->num_cnic_queues);
8463
8464 /* falling through... */
8465 case BNX2X_INT_MODE_MSI:
8466 bnx2x_enable_msi(bp);
8467
8468 /* falling through... */
8469 case BNX2X_INT_MODE_INTX:
8470 bp->num_ethernet_queues = 1;
8471 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
8472 BNX2X_DEV_INFO("set number of queues to 1\n");
8473 break;
8474 default:
8475 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8476 return -EINVAL;
8477 }
8478 return 0;
8479 }
8480
8481 /* must be called prior to any HW initializations */
8482 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8483 {
8484 if (IS_SRIOV(bp))
8485 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
8486 return L2_ILT_LINES(bp);
8487 }
8488
8489 void bnx2x_ilt_set_info(struct bnx2x *bp)
8490 {
8491 struct ilt_client_info *ilt_client;
8492 struct bnx2x_ilt *ilt = BP_ILT(bp);
8493 u16 line = 0;
8494
8495 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8496 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8497
8498 /* CDU */
8499 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8500 ilt_client->client_num = ILT_CLIENT_CDU;
8501 ilt_client->page_size = CDU_ILT_PAGE_SZ;
8502 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8503 ilt_client->start = line;
8504 line += bnx2x_cid_ilt_lines(bp);
8505
8506 if (CNIC_SUPPORT(bp))
8507 line += CNIC_ILT_LINES;
8508 ilt_client->end = line - 1;
8509
8510 DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8511 ilt_client->start,
8512 ilt_client->end,
8513 ilt_client->page_size,
8514 ilt_client->flags,
8515 ilog2(ilt_client->page_size >> 12));
8516
8517 /* QM */
8518 if (QM_INIT(bp->qm_cid_count)) {
8519 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8520 ilt_client->client_num = ILT_CLIENT_QM;
8521 ilt_client->page_size = QM_ILT_PAGE_SZ;
8522 ilt_client->flags = 0;
8523 ilt_client->start = line;
8524
8525 /* 4 bytes for each cid */
8526 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8527 QM_ILT_PAGE_SZ);
8528
8529 ilt_client->end = line - 1;
8530
8531 DP(NETIF_MSG_IFUP,
8532 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8533 ilt_client->start,
8534 ilt_client->end,
8535 ilt_client->page_size,
8536 ilt_client->flags,
8537 ilog2(ilt_client->page_size >> 12));
8538 }
8539
8540 if (CNIC_SUPPORT(bp)) {
8541 /* SRC */
8542 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8543 ilt_client->client_num = ILT_CLIENT_SRC;
8544 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8545 ilt_client->flags = 0;
8546 ilt_client->start = line;
8547 line += SRC_ILT_LINES;
8548 ilt_client->end = line - 1;
8549
8550 DP(NETIF_MSG_IFUP,
8551 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8552 ilt_client->start,
8553 ilt_client->end,
8554 ilt_client->page_size,
8555 ilt_client->flags,
8556 ilog2(ilt_client->page_size >> 12));
8557
8558 /* TM */
8559 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8560 ilt_client->client_num = ILT_CLIENT_TM;
8561 ilt_client->page_size = TM_ILT_PAGE_SZ;
8562 ilt_client->flags = 0;
8563 ilt_client->start = line;
8564 line += TM_ILT_LINES;
8565 ilt_client->end = line - 1;
8566
8567 DP(NETIF_MSG_IFUP,
8568 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8569 ilt_client->start,
8570 ilt_client->end,
8571 ilt_client->page_size,
8572 ilt_client->flags,
8573 ilog2(ilt_client->page_size >> 12));
8574 }
8575
8576 BUG_ON(line > ILT_MAX_LINES);
8577 }
8578
8579 /**
8580 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8581 *
8582 * @bp: driver handle
8583 * @fp: pointer to fastpath
8584 * @init_params: pointer to parameters structure
8585 *
8586 * parameters configured:
8587 * - HC configuration
8588 * - Queue's CDU context
8589 */
8590 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
8591 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
8592 {
8593 u8 cos;
8594 int cxt_index, cxt_offset;
8595
8596 /* FCoE Queue uses Default SB, thus has no HC capabilities */
8597 if (!IS_FCOE_FP(fp)) {
8598 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8599 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8600
8601 /* If HC is supported, enable host coalescing in the transition
8602 * to INIT state.
8603 */
8604 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8605 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8606
8607 /* HC rate */
8608 init_params->rx.hc_rate = bp->rx_ticks ?
8609 (1000000 / bp->rx_ticks) : 0;
8610 init_params->tx.hc_rate = bp->tx_ticks ?
8611 (1000000 / bp->tx_ticks) : 0;
8612
8613 /* FW SB ID */
8614 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8615 fp->fw_sb_id;
8616
8617 /*
8618 * CQ index among the SB indices: FCoE clients uses the default
8619 * SB, therefore it's different.
8620 */
8621 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8622 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
8623 }
8624
8625 /* set maximum number of COSs supported by this queue */
8626 init_params->max_cos = fp->max_cos;
8627
8628 DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
8629 fp->index, init_params->max_cos);
8630
8631 /* set the context pointers queue object */
8632 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
8633 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8634 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
8635 ILT_PAGE_CIDS);
8636 init_params->cxts[cos] =
8637 &bp->context[cxt_index].vcxt[cxt_offset].eth;
8638 }
8639 }
8640
8641 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8642 struct bnx2x_queue_state_params *q_params,
8643 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8644 int tx_index, bool leading)
8645 {
8646 memset(tx_only_params, 0, sizeof(*tx_only_params));
8647
8648 /* Set the command */
8649 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8650
8651 /* Set tx-only QUEUE flags: don't zero statistics */
8652 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8653
8654 /* choose the index of the cid to send the slow path on */
8655 tx_only_params->cid_index = tx_index;
8656
8657 /* Set general TX_ONLY_SETUP parameters */
8658 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8659
8660 /* Set Tx TX_ONLY_SETUP parameters */
8661 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8662
8663 DP(NETIF_MSG_IFUP,
8664 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8665 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8666 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8667 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8668
8669 /* send the ramrod */
8670 return bnx2x_queue_state_change(bp, q_params);
8671 }
8672
8673 /**
8674 * bnx2x_setup_queue - setup queue
8675 *
8676 * @bp: driver handle
8677 * @fp: pointer to fastpath
8678 * @leading: is leading
8679 *
8680 * This function performs 2 steps in a Queue state machine
8681 * actually: 1) RESET->INIT 2) INIT->SETUP
8682 */
8683
8684 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8685 bool leading)
8686 {
8687 struct bnx2x_queue_state_params q_params = {NULL};
8688 struct bnx2x_queue_setup_params *setup_params =
8689 &q_params.params.setup;
8690 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8691 &q_params.params.tx_only;
8692 int rc;
8693 u8 tx_index;
8694
8695 DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
8696
8697 /* reset IGU state skip FCoE L2 queue */
8698 if (!IS_FCOE_FP(fp))
8699 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
8700 IGU_INT_ENABLE, 0);
8701
8702 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8703 /* We want to wait for completion in this context */
8704 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8705
8706 /* Prepare the INIT parameters */
8707 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
8708
8709 /* Set the command */
8710 q_params.cmd = BNX2X_Q_CMD_INIT;
8711
8712 /* Change the state to INIT */
8713 rc = bnx2x_queue_state_change(bp, &q_params);
8714 if (rc) {
8715 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
8716 return rc;
8717 }
8718
8719 DP(NETIF_MSG_IFUP, "init complete\n");
8720
8721 /* Now move the Queue to the SETUP state... */
8722 memset(setup_params, 0, sizeof(*setup_params));
8723
8724 /* Set QUEUE flags */
8725 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
8726
8727 /* Set general SETUP parameters */
8728 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8729 FIRST_TX_COS_INDEX);
8730
8731 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
8732 &setup_params->rxq_params);
8733
8734 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8735 FIRST_TX_COS_INDEX);
8736
8737 /* Set the command */
8738 q_params.cmd = BNX2X_Q_CMD_SETUP;
8739
8740 if (IS_FCOE_FP(fp))
8741 bp->fcoe_init = true;
8742
8743 /* Change the state to SETUP */
8744 rc = bnx2x_queue_state_change(bp, &q_params);
8745 if (rc) {
8746 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8747 return rc;
8748 }
8749
8750 /* loop through the relevant tx-only indices */
8751 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8752 tx_index < fp->max_cos;
8753 tx_index++) {
8754
8755 /* prepare and send tx-only ramrod*/
8756 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8757 tx_only_params, tx_index, leading);
8758 if (rc) {
8759 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8760 fp->index, tx_index);
8761 return rc;
8762 }
8763 }
8764
8765 return rc;
8766 }
8767
8768 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
8769 {
8770 struct bnx2x_fastpath *fp = &bp->fp[index];
8771 struct bnx2x_fp_txdata *txdata;
8772 struct bnx2x_queue_state_params q_params = {NULL};
8773 int rc, tx_index;
8774
8775 DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
8776
8777 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8778 /* We want to wait for completion in this context */
8779 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8780
8781 /* close tx-only connections */
8782 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8783 tx_index < fp->max_cos;
8784 tx_index++){
8785
8786 /* ascertain this is a normal queue*/
8787 txdata = fp->txdata_ptr[tx_index];
8788
8789 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
8790 txdata->txq_index);
8791
8792 /* send halt terminate on tx-only connection */
8793 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8794 memset(&q_params.params.terminate, 0,
8795 sizeof(q_params.params.terminate));
8796 q_params.params.terminate.cid_index = tx_index;
8797
8798 rc = bnx2x_queue_state_change(bp, &q_params);
8799 if (rc)
8800 return rc;
8801
8802 /* send halt terminate on tx-only connection */
8803 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8804 memset(&q_params.params.cfc_del, 0,
8805 sizeof(q_params.params.cfc_del));
8806 q_params.params.cfc_del.cid_index = tx_index;
8807 rc = bnx2x_queue_state_change(bp, &q_params);
8808 if (rc)
8809 return rc;
8810 }
8811 /* Stop the primary connection: */
8812 /* ...halt the connection */
8813 q_params.cmd = BNX2X_Q_CMD_HALT;
8814 rc = bnx2x_queue_state_change(bp, &q_params);
8815 if (rc)
8816 return rc;
8817
8818 /* ...terminate the connection */
8819 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8820 memset(&q_params.params.terminate, 0,
8821 sizeof(q_params.params.terminate));
8822 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8823 rc = bnx2x_queue_state_change(bp, &q_params);
8824 if (rc)
8825 return rc;
8826 /* ...delete cfc entry */
8827 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8828 memset(&q_params.params.cfc_del, 0,
8829 sizeof(q_params.params.cfc_del));
8830 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8831 return bnx2x_queue_state_change(bp, &q_params);
8832 }
8833
8834 static void bnx2x_reset_func(struct bnx2x *bp)
8835 {
8836 int port = BP_PORT(bp);
8837 int func = BP_FUNC(bp);
8838 int i;
8839
8840 /* Disable the function in the FW */
8841 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8842 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8843 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8844 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8845
8846 /* FP SBs */
8847 for_each_eth_queue(bp, i) {
8848 struct bnx2x_fastpath *fp = &bp->fp[i];
8849 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8850 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8851 SB_DISABLED);
8852 }
8853
8854 if (CNIC_LOADED(bp))
8855 /* CNIC SB */
8856 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8857 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8858 (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8859
8860 /* SP SB */
8861 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8862 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8863 SB_DISABLED);
8864
8865 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8866 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8867 0);
8868
8869 /* Configure IGU */
8870 if (bp->common.int_block == INT_BLOCK_HC) {
8871 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8872 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8873 } else {
8874 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8875 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8876 }
8877
8878 if (CNIC_LOADED(bp)) {
8879 /* Disable Timer scan */
8880 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8881 /*
8882 * Wait for at least 10ms and up to 2 second for the timers
8883 * scan to complete
8884 */
8885 for (i = 0; i < 200; i++) {
8886 usleep_range(10000, 20000);
8887 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8888 break;
8889 }
8890 }
8891 /* Clear ILT */
8892 bnx2x_clear_func_ilt(bp, func);
8893
8894 /* Timers workaround bug for E2: if this is vnic-3,
8895 * we need to set the entire ilt range for this timers.
8896 */
8897 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
8898 struct ilt_client_info ilt_cli;
8899 /* use dummy TM client */
8900 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8901 ilt_cli.start = 0;
8902 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8903 ilt_cli.client_num = ILT_CLIENT_TM;
8904
8905 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8906 }
8907
8908 /* this assumes that reset_port() called before reset_func()*/
8909 if (!CHIP_IS_E1x(bp))
8910 bnx2x_pf_disable(bp);
8911
8912 bp->dmae_ready = 0;
8913 }
8914
8915 static void bnx2x_reset_port(struct bnx2x *bp)
8916 {
8917 int port = BP_PORT(bp);
8918 u32 val;
8919
8920 /* Reset physical Link */
8921 bnx2x__link_reset(bp);
8922
8923 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8924
8925 /* Do not rcv packets to BRB */
8926 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8927 /* Do not direct rcv packets that are not for MCP to the BRB */
8928 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8929 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8930
8931 /* Configure AEU */
8932 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8933
8934 msleep(100);
8935 /* Check for BRB port occupancy */
8936 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8937 if (val)
8938 DP(NETIF_MSG_IFDOWN,
8939 "BRB1 is not empty %d blocks are occupied\n", val);
8940
8941 /* TODO: Close Doorbell port? */
8942 }
8943
8944 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
8945 {
8946 struct bnx2x_func_state_params func_params = {NULL};
8947
8948 /* Prepare parameters for function state transitions */
8949 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8950
8951 func_params.f_obj = &bp->func_obj;
8952 func_params.cmd = BNX2X_F_CMD_HW_RESET;
8953
8954 func_params.params.hw_init.load_phase = load_code;
8955
8956 return bnx2x_func_state_change(bp, &func_params);
8957 }
8958
8959 static int bnx2x_func_stop(struct bnx2x *bp)
8960 {
8961 struct bnx2x_func_state_params func_params = {NULL};
8962 int rc;
8963
8964 /* Prepare parameters for function state transitions */
8965 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8966 func_params.f_obj = &bp->func_obj;
8967 func_params.cmd = BNX2X_F_CMD_STOP;
8968
8969 /*
8970 * Try to stop the function the 'good way'. If fails (in case
8971 * of a parity error during bnx2x_chip_cleanup()) and we are
8972 * not in a debug mode, perform a state transaction in order to
8973 * enable further HW_RESET transaction.
8974 */
8975 rc = bnx2x_func_state_change(bp, &func_params);
8976 if (rc) {
8977 #ifdef BNX2X_STOP_ON_ERROR
8978 return rc;
8979 #else
8980 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
8981 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
8982 return bnx2x_func_state_change(bp, &func_params);
8983 #endif
8984 }
8985
8986 return 0;
8987 }
8988
8989 /**
8990 * bnx2x_send_unload_req - request unload mode from the MCP.
8991 *
8992 * @bp: driver handle
8993 * @unload_mode: requested function's unload mode
8994 *
8995 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
8996 */
8997 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
8998 {
8999 u32 reset_code = 0;
9000 int port = BP_PORT(bp);
9001
9002 /* Select the UNLOAD request mode */
9003 if (unload_mode == UNLOAD_NORMAL)
9004 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
9005
9006 else if (bp->flags & NO_WOL_FLAG)
9007 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
9008
9009 else if (bp->wol) {
9010 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
9011 u8 *mac_addr = bp->dev->dev_addr;
9012 struct pci_dev *pdev = bp->pdev;
9013 u32 val;
9014 u16 pmc;
9015
9016 /* The mac address is written to entries 1-4 to
9017 * preserve entry 0 which is used by the PMF
9018 */
9019 u8 entry = (BP_VN(bp) + 1)*8;
9020
9021 val = (mac_addr[0] << 8) | mac_addr[1];
9022 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
9023
9024 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
9025 (mac_addr[4] << 8) | mac_addr[5];
9026 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
9027
9028 /* Enable the PME and clear the status */
9029 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc);
9030 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
9031 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc);
9032
9033 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
9034
9035 } else
9036 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
9037
9038 /* Send the request to the MCP */
9039 if (!BP_NOMCP(bp))
9040 reset_code = bnx2x_fw_command(bp, reset_code, 0);
9041 else {
9042 int path = BP_PATH(bp);
9043
9044 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n",
9045 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9046 bnx2x_load_count[path][2]);
9047 bnx2x_load_count[path][0]--;
9048 bnx2x_load_count[path][1 + port]--;
9049 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n",
9050 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9051 bnx2x_load_count[path][2]);
9052 if (bnx2x_load_count[path][0] == 0)
9053 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
9054 else if (bnx2x_load_count[path][1 + port] == 0)
9055 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
9056 else
9057 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
9058 }
9059
9060 return reset_code;
9061 }
9062
9063 /**
9064 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
9065 *
9066 * @bp: driver handle
9067 * @keep_link: true iff link should be kept up
9068 */
9069 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
9070 {
9071 u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
9072
9073 /* Report UNLOAD_DONE to MCP */
9074 if (!BP_NOMCP(bp))
9075 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
9076 }
9077
9078 static int bnx2x_func_wait_started(struct bnx2x *bp)
9079 {
9080 int tout = 50;
9081 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
9082
9083 if (!bp->port.pmf)
9084 return 0;
9085
9086 /*
9087 * (assumption: No Attention from MCP at this stage)
9088 * PMF probably in the middle of TX disable/enable transaction
9089 * 1. Sync IRS for default SB
9090 * 2. Sync SP queue - this guarantees us that attention handling started
9091 * 3. Wait, that TX disable/enable transaction completes
9092 *
9093 * 1+2 guarantee that if DCBx attention was scheduled it already changed
9094 * pending bit of transaction from STARTED-->TX_STOPPED, if we already
9095 * received completion for the transaction the state is TX_STOPPED.
9096 * State will return to STARTED after completion of TX_STOPPED-->STARTED
9097 * transaction.
9098 */
9099
9100 /* make sure default SB ISR is done */
9101 if (msix)
9102 synchronize_irq(bp->msix_table[0].vector);
9103 else
9104 synchronize_irq(bp->pdev->irq);
9105
9106 flush_workqueue(bnx2x_wq);
9107 flush_workqueue(bnx2x_iov_wq);
9108
9109 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
9110 BNX2X_F_STATE_STARTED && tout--)
9111 msleep(20);
9112
9113 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
9114 BNX2X_F_STATE_STARTED) {
9115 #ifdef BNX2X_STOP_ON_ERROR
9116 BNX2X_ERR("Wrong function state\n");
9117 return -EBUSY;
9118 #else
9119 /*
9120 * Failed to complete the transaction in a "good way"
9121 * Force both transactions with CLR bit
9122 */
9123 struct bnx2x_func_state_params func_params = {NULL};
9124
9125 DP(NETIF_MSG_IFDOWN,
9126 "Hmmm... Unexpected function state! Forcing STARTED-->TX_STOPPED-->STARTED\n");
9127
9128 func_params.f_obj = &bp->func_obj;
9129 __set_bit(RAMROD_DRV_CLR_ONLY,
9130 &func_params.ramrod_flags);
9131
9132 /* STARTED-->TX_ST0PPED */
9133 func_params.cmd = BNX2X_F_CMD_TX_STOP;
9134 bnx2x_func_state_change(bp, &func_params);
9135
9136 /* TX_ST0PPED-->STARTED */
9137 func_params.cmd = BNX2X_F_CMD_TX_START;
9138 return bnx2x_func_state_change(bp, &func_params);
9139 #endif
9140 }
9141
9142 return 0;
9143 }
9144
9145 static void bnx2x_disable_ptp(struct bnx2x *bp)
9146 {
9147 int port = BP_PORT(bp);
9148
9149 /* Disable sending PTP packets to host */
9150 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
9151 NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
9152
9153 /* Reset PTP event detection rules */
9154 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
9155 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
9156 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
9157 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
9158 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
9159 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
9160 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
9161 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
9162
9163 /* Disable the PTP feature */
9164 REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
9165 NIG_REG_P0_PTP_EN, 0x0);
9166 }
9167
9168 /* Called during unload, to stop PTP-related stuff */
9169 void bnx2x_stop_ptp(struct bnx2x *bp)
9170 {
9171 /* Cancel PTP work queue. Should be done after the Tx queues are
9172 * drained to prevent additional scheduling.
9173 */
9174 cancel_work_sync(&bp->ptp_task);
9175
9176 if (bp->ptp_tx_skb) {
9177 dev_kfree_skb_any(bp->ptp_tx_skb);
9178 bp->ptp_tx_skb = NULL;
9179 }
9180
9181 /* Disable PTP in HW */
9182 bnx2x_disable_ptp(bp);
9183
9184 DP(BNX2X_MSG_PTP, "PTP stop ended successfully\n");
9185 }
9186
9187 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
9188 {
9189 int port = BP_PORT(bp);
9190 int i, rc = 0;
9191 u8 cos;
9192 struct bnx2x_mcast_ramrod_params rparam = {NULL};
9193 u32 reset_code;
9194
9195 /* Wait until tx fastpath tasks complete */
9196 for_each_tx_queue(bp, i) {
9197 struct bnx2x_fastpath *fp = &bp->fp[i];
9198
9199 for_each_cos_in_tx_queue(fp, cos)
9200 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
9201 #ifdef BNX2X_STOP_ON_ERROR
9202 if (rc)
9203 return;
9204 #endif
9205 }
9206
9207 /* Give HW time to discard old tx messages */
9208 usleep_range(1000, 2000);
9209
9210 /* Clean all ETH MACs */
9211 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
9212 false);
9213 if (rc < 0)
9214 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
9215
9216 /* Clean up UC list */
9217 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
9218 true);
9219 if (rc < 0)
9220 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
9221 rc);
9222
9223 /* Disable LLH */
9224 if (!CHIP_IS_E1(bp))
9225 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
9226
9227 /* Set "drop all" (stop Rx).
9228 * We need to take a netif_addr_lock() here in order to prevent
9229 * a race between the completion code and this code.
9230 */
9231 netif_addr_lock_bh(bp->dev);
9232 /* Schedule the rx_mode command */
9233 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
9234 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
9235 else
9236 bnx2x_set_storm_rx_mode(bp);
9237
9238 /* Cleanup multicast configuration */
9239 rparam.mcast_obj = &bp->mcast_obj;
9240 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
9241 if (rc < 0)
9242 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
9243
9244 netif_addr_unlock_bh(bp->dev);
9245
9246 bnx2x_iov_chip_cleanup(bp);
9247
9248 /*
9249 * Send the UNLOAD_REQUEST to the MCP. This will return if
9250 * this function should perform FUNC, PORT or COMMON HW
9251 * reset.
9252 */
9253 reset_code = bnx2x_send_unload_req(bp, unload_mode);
9254
9255 /*
9256 * (assumption: No Attention from MCP at this stage)
9257 * PMF probably in the middle of TX disable/enable transaction
9258 */
9259 rc = bnx2x_func_wait_started(bp);
9260 if (rc) {
9261 BNX2X_ERR("bnx2x_func_wait_started failed\n");
9262 #ifdef BNX2X_STOP_ON_ERROR
9263 return;
9264 #endif
9265 }
9266
9267 /* Close multi and leading connections
9268 * Completions for ramrods are collected in a synchronous way
9269 */
9270 for_each_eth_queue(bp, i)
9271 if (bnx2x_stop_queue(bp, i))
9272 #ifdef BNX2X_STOP_ON_ERROR
9273 return;
9274 #else
9275 goto unload_error;
9276 #endif
9277
9278 if (CNIC_LOADED(bp)) {
9279 for_each_cnic_queue(bp, i)
9280 if (bnx2x_stop_queue(bp, i))
9281 #ifdef BNX2X_STOP_ON_ERROR
9282 return;
9283 #else
9284 goto unload_error;
9285 #endif
9286 }
9287
9288 /* If SP settings didn't get completed so far - something
9289 * very wrong has happen.
9290 */
9291 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
9292 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
9293
9294 #ifndef BNX2X_STOP_ON_ERROR
9295 unload_error:
9296 #endif
9297 rc = bnx2x_func_stop(bp);
9298 if (rc) {
9299 BNX2X_ERR("Function stop failed!\n");
9300 #ifdef BNX2X_STOP_ON_ERROR
9301 return;
9302 #endif
9303 }
9304
9305 /* stop_ptp should be after the Tx queues are drained to prevent
9306 * scheduling to the cancelled PTP work queue. It should also be after
9307 * function stop ramrod is sent, since as part of this ramrod FW access
9308 * PTP registers.
9309 */
9310 bnx2x_stop_ptp(bp);
9311
9312 /* Disable HW interrupts, NAPI */
9313 bnx2x_netif_stop(bp, 1);
9314 /* Delete all NAPI objects */
9315 bnx2x_del_all_napi(bp);
9316 if (CNIC_LOADED(bp))
9317 bnx2x_del_all_napi_cnic(bp);
9318
9319 /* Release IRQs */
9320 bnx2x_free_irq(bp);
9321
9322 /* Reset the chip */
9323 rc = bnx2x_reset_hw(bp, reset_code);
9324 if (rc)
9325 BNX2X_ERR("HW_RESET failed\n");
9326
9327 /* Report UNLOAD_DONE to MCP */
9328 bnx2x_send_unload_done(bp, keep_link);
9329 }
9330
9331 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
9332 {
9333 u32 val;
9334
9335 DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
9336
9337 if (CHIP_IS_E1(bp)) {
9338 int port = BP_PORT(bp);
9339 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
9340 MISC_REG_AEU_MASK_ATTN_FUNC_0;
9341
9342 val = REG_RD(bp, addr);
9343 val &= ~(0x300);
9344 REG_WR(bp, addr, val);
9345 } else {
9346 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
9347 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
9348 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
9349 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
9350 }
9351 }
9352
9353 /* Close gates #2, #3 and #4: */
9354 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
9355 {
9356 u32 val;
9357
9358 /* Gates #2 and #4a are closed/opened for "not E1" only */
9359 if (!CHIP_IS_E1(bp)) {
9360 /* #4 */
9361 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
9362 /* #2 */
9363 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
9364 }
9365
9366 /* #3 */
9367 if (CHIP_IS_E1x(bp)) {
9368 /* Prevent interrupts from HC on both ports */
9369 val = REG_RD(bp, HC_REG_CONFIG_1);
9370 REG_WR(bp, HC_REG_CONFIG_1,
9371 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
9372 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
9373
9374 val = REG_RD(bp, HC_REG_CONFIG_0);
9375 REG_WR(bp, HC_REG_CONFIG_0,
9376 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
9377 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
9378 } else {
9379 /* Prevent incoming interrupts in IGU */
9380 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9381
9382 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
9383 (!close) ?
9384 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
9385 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
9386 }
9387
9388 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
9389 close ? "closing" : "opening");
9390 mmiowb();
9391 }
9392
9393 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
9394
9395 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
9396 {
9397 /* Do some magic... */
9398 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9399 *magic_val = val & SHARED_MF_CLP_MAGIC;
9400 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
9401 }
9402
9403 /**
9404 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
9405 *
9406 * @bp: driver handle
9407 * @magic_val: old value of the `magic' bit.
9408 */
9409 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
9410 {
9411 /* Restore the `magic' bit value... */
9412 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9413 MF_CFG_WR(bp, shared_mf_config.clp_mb,
9414 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
9415 }
9416
9417 /**
9418 * bnx2x_reset_mcp_prep - prepare for MCP reset.
9419 *
9420 * @bp: driver handle
9421 * @magic_val: old value of 'magic' bit.
9422 *
9423 * Takes care of CLP configurations.
9424 */
9425 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
9426 {
9427 u32 shmem;
9428 u32 validity_offset;
9429
9430 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
9431
9432 /* Set `magic' bit in order to save MF config */
9433 if (!CHIP_IS_E1(bp))
9434 bnx2x_clp_reset_prep(bp, magic_val);
9435
9436 /* Get shmem offset */
9437 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9438 validity_offset =
9439 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
9440
9441 /* Clear validity map flags */
9442 if (shmem > 0)
9443 REG_WR(bp, shmem + validity_offset, 0);
9444 }
9445
9446 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
9447 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
9448
9449 /**
9450 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
9451 *
9452 * @bp: driver handle
9453 */
9454 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
9455 {
9456 /* special handling for emulation and FPGA,
9457 wait 10 times longer */
9458 if (CHIP_REV_IS_SLOW(bp))
9459 msleep(MCP_ONE_TIMEOUT*10);
9460 else
9461 msleep(MCP_ONE_TIMEOUT);
9462 }
9463
9464 /*
9465 * initializes bp->common.shmem_base and waits for validity signature to appear
9466 */
9467 static int bnx2x_init_shmem(struct bnx2x *bp)
9468 {
9469 int cnt = 0;
9470 u32 val = 0;
9471
9472 do {
9473 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9474 if (bp->common.shmem_base) {
9475 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9476 if (val & SHR_MEM_VALIDITY_MB)
9477 return 0;
9478 }
9479
9480 bnx2x_mcp_wait_one(bp);
9481
9482 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
9483
9484 BNX2X_ERR("BAD MCP validity signature\n");
9485
9486 return -ENODEV;
9487 }
9488
9489 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
9490 {
9491 int rc = bnx2x_init_shmem(bp);
9492
9493 /* Restore the `magic' bit value */
9494 if (!CHIP_IS_E1(bp))
9495 bnx2x_clp_reset_done(bp, magic_val);
9496
9497 return rc;
9498 }
9499
9500 static void bnx2x_pxp_prep(struct bnx2x *bp)
9501 {
9502 if (!CHIP_IS_E1(bp)) {
9503 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
9504 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
9505 mmiowb();
9506 }
9507 }
9508
9509 /*
9510 * Reset the whole chip except for:
9511 * - PCIE core
9512 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9513 * one reset bit)
9514 * - IGU
9515 * - MISC (including AEU)
9516 * - GRC
9517 * - RBCN, RBCP
9518 */
9519 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
9520 {
9521 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
9522 u32 global_bits2, stay_reset2;
9523
9524 /*
9525 * Bits that have to be set in reset_mask2 if we want to reset 'global'
9526 * (per chip) blocks.
9527 */
9528 global_bits2 =
9529 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9530 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
9531
9532 /* Don't reset the following blocks.
9533 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9534 * reset, as in 4 port device they might still be owned
9535 * by the MCP (there is only one leader per path).
9536 */
9537 not_reset_mask1 =
9538 MISC_REGISTERS_RESET_REG_1_RST_HC |
9539 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9540 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9541
9542 not_reset_mask2 =
9543 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
9544 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9545 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9546 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9547 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9548 MISC_REGISTERS_RESET_REG_2_RST_GRC |
9549 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
9550 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9551 MISC_REGISTERS_RESET_REG_2_RST_ATC |
9552 MISC_REGISTERS_RESET_REG_2_PGLC |
9553 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9554 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9555 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9556 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9557 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9558 MISC_REGISTERS_RESET_REG_2_UMAC1;
9559
9560 /*
9561 * Keep the following blocks in reset:
9562 * - all xxMACs are handled by the bnx2x_link code.
9563 */
9564 stay_reset2 =
9565 MISC_REGISTERS_RESET_REG_2_XMAC |
9566 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9567
9568 /* Full reset masks according to the chip */
9569 reset_mask1 = 0xffffffff;
9570
9571 if (CHIP_IS_E1(bp))
9572 reset_mask2 = 0xffff;
9573 else if (CHIP_IS_E1H(bp))
9574 reset_mask2 = 0x1ffff;
9575 else if (CHIP_IS_E2(bp))
9576 reset_mask2 = 0xfffff;
9577 else /* CHIP_IS_E3 */
9578 reset_mask2 = 0x3ffffff;
9579
9580 /* Don't reset global blocks unless we need to */
9581 if (!global)
9582 reset_mask2 &= ~global_bits2;
9583
9584 /*
9585 * In case of attention in the QM, we need to reset PXP
9586 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9587 * because otherwise QM reset would release 'close the gates' shortly
9588 * before resetting the PXP, then the PSWRQ would send a write
9589 * request to PGLUE. Then when PXP is reset, PGLUE would try to
9590 * read the payload data from PSWWR, but PSWWR would not
9591 * respond. The write queue in PGLUE would stuck, dmae commands
9592 * would not return. Therefore it's important to reset the second
9593 * reset register (containing the
9594 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9595 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9596 * bit).
9597 */
9598 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9599 reset_mask2 & (~not_reset_mask2));
9600
9601 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9602 reset_mask1 & (~not_reset_mask1));
9603
9604 barrier();
9605 mmiowb();
9606
9607 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9608 reset_mask2 & (~stay_reset2));
9609
9610 barrier();
9611 mmiowb();
9612
9613 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
9614 mmiowb();
9615 }
9616
9617 /**
9618 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9619 * It should get cleared in no more than 1s.
9620 *
9621 * @bp: driver handle
9622 *
9623 * It should get cleared in no more than 1s. Returns 0 if
9624 * pending writes bit gets cleared.
9625 */
9626 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9627 {
9628 u32 cnt = 1000;
9629 u32 pend_bits = 0;
9630
9631 do {
9632 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9633
9634 if (pend_bits == 0)
9635 break;
9636
9637 usleep_range(1000, 2000);
9638 } while (cnt-- > 0);
9639
9640 if (cnt <= 0) {
9641 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9642 pend_bits);
9643 return -EBUSY;
9644 }
9645
9646 return 0;
9647 }
9648
9649 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
9650 {
9651 int cnt = 1000;
9652 u32 val = 0;
9653 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
9654 u32 tags_63_32 = 0;
9655
9656 /* Empty the Tetris buffer, wait for 1s */
9657 do {
9658 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9659 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9660 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9661 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9662 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
9663 if (CHIP_IS_E3(bp))
9664 tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9665
9666 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9667 ((port_is_idle_0 & 0x1) == 0x1) &&
9668 ((port_is_idle_1 & 0x1) == 0x1) &&
9669 (pgl_exp_rom2 == 0xffffffff) &&
9670 (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
9671 break;
9672 usleep_range(1000, 2000);
9673 } while (cnt-- > 0);
9674
9675 if (cnt <= 0) {
9676 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9677 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9678 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9679 pgl_exp_rom2);
9680 return -EAGAIN;
9681 }
9682
9683 barrier();
9684
9685 /* Close gates #2, #3 and #4 */
9686 bnx2x_set_234_gates(bp, true);
9687
9688 /* Poll for IGU VQs for 57712 and newer chips */
9689 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9690 return -EAGAIN;
9691
9692 /* TBD: Indicate that "process kill" is in progress to MCP */
9693
9694 /* Clear "unprepared" bit */
9695 REG_WR(bp, MISC_REG_UNPREPARED, 0);
9696 barrier();
9697
9698 /* Make sure all is written to the chip before the reset */
9699 mmiowb();
9700
9701 /* Wait for 1ms to empty GLUE and PCI-E core queues,
9702 * PSWHST, GRC and PSWRD Tetris buffer.
9703 */
9704 usleep_range(1000, 2000);
9705
9706 /* Prepare to chip reset: */
9707 /* MCP */
9708 if (global)
9709 bnx2x_reset_mcp_prep(bp, &val);
9710
9711 /* PXP */
9712 bnx2x_pxp_prep(bp);
9713 barrier();
9714
9715 /* reset the chip */
9716 bnx2x_process_kill_chip_reset(bp, global);
9717 barrier();
9718
9719 /* clear errors in PGB */
9720 if (!CHIP_IS_E1x(bp))
9721 REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f);
9722
9723 /* Recover after reset: */
9724 /* MCP */
9725 if (global && bnx2x_reset_mcp_comp(bp, val))
9726 return -EAGAIN;
9727
9728 /* TBD: Add resetting the NO_MCP mode DB here */
9729
9730 /* Open the gates #2, #3 and #4 */
9731 bnx2x_set_234_gates(bp, false);
9732
9733 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9734 * reset state, re-enable attentions. */
9735
9736 return 0;
9737 }
9738
9739 static int bnx2x_leader_reset(struct bnx2x *bp)
9740 {
9741 int rc = 0;
9742 bool global = bnx2x_reset_is_global(bp);
9743 u32 load_code;
9744
9745 /* if not going to reset MCP - load "fake" driver to reset HW while
9746 * driver is owner of the HW
9747 */
9748 if (!global && !BP_NOMCP(bp)) {
9749 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9750 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
9751 if (!load_code) {
9752 BNX2X_ERR("MCP response failure, aborting\n");
9753 rc = -EAGAIN;
9754 goto exit_leader_reset;
9755 }
9756 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9757 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9758 BNX2X_ERR("MCP unexpected resp, aborting\n");
9759 rc = -EAGAIN;
9760 goto exit_leader_reset2;
9761 }
9762 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9763 if (!load_code) {
9764 BNX2X_ERR("MCP response failure, aborting\n");
9765 rc = -EAGAIN;
9766 goto exit_leader_reset2;
9767 }
9768 }
9769
9770 /* Try to recover after the failure */
9771 if (bnx2x_process_kill(bp, global)) {
9772 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9773 BP_PATH(bp));
9774 rc = -EAGAIN;
9775 goto exit_leader_reset2;
9776 }
9777
9778 /*
9779 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9780 * state.
9781 */
9782 bnx2x_set_reset_done(bp);
9783 if (global)
9784 bnx2x_clear_reset_global(bp);
9785
9786 exit_leader_reset2:
9787 /* unload "fake driver" if it was loaded */
9788 if (!global && !BP_NOMCP(bp)) {
9789 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9790 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9791 }
9792 exit_leader_reset:
9793 bp->is_leader = 0;
9794 bnx2x_release_leader_lock(bp);
9795 smp_mb();
9796 return rc;
9797 }
9798
9799 static void bnx2x_recovery_failed(struct bnx2x *bp)
9800 {
9801 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9802
9803 /* Disconnect this device */
9804 netif_device_detach(bp->dev);
9805
9806 /*
9807 * Block ifup for all function on this engine until "process kill"
9808 * or power cycle.
9809 */
9810 bnx2x_set_reset_in_progress(bp);
9811
9812 /* Shut down the power */
9813 bnx2x_set_power_state(bp, PCI_D3hot);
9814
9815 bp->recovery_state = BNX2X_RECOVERY_FAILED;
9816
9817 smp_mb();
9818 }
9819
9820 /*
9821 * Assumption: runs under rtnl lock. This together with the fact
9822 * that it's called only from bnx2x_sp_rtnl() ensure that it
9823 * will never be called when netif_running(bp->dev) is false.
9824 */
9825 static void bnx2x_parity_recover(struct bnx2x *bp)
9826 {
9827 bool global = false;
9828 u32 error_recovered, error_unrecovered;
9829 bool is_parity;
9830
9831 DP(NETIF_MSG_HW, "Handling parity\n");
9832 while (1) {
9833 switch (bp->recovery_state) {
9834 case BNX2X_RECOVERY_INIT:
9835 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
9836 is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9837 WARN_ON(!is_parity);
9838
9839 /* Try to get a LEADER_LOCK HW lock */
9840 if (bnx2x_trylock_leader_lock(bp)) {
9841 bnx2x_set_reset_in_progress(bp);
9842 /*
9843 * Check if there is a global attention and if
9844 * there was a global attention, set the global
9845 * reset bit.
9846 */
9847
9848 if (global)
9849 bnx2x_set_reset_global(bp);
9850
9851 bp->is_leader = 1;
9852 }
9853
9854 /* Stop the driver */
9855 /* If interface has been removed - break */
9856 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
9857 return;
9858
9859 bp->recovery_state = BNX2X_RECOVERY_WAIT;
9860
9861 /* Ensure "is_leader", MCP command sequence and
9862 * "recovery_state" update values are seen on other
9863 * CPUs.
9864 */
9865 smp_mb();
9866 break;
9867
9868 case BNX2X_RECOVERY_WAIT:
9869 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9870 if (bp->is_leader) {
9871 int other_engine = BP_PATH(bp) ? 0 : 1;
9872 bool other_load_status =
9873 bnx2x_get_load_status(bp, other_engine);
9874 bool load_status =
9875 bnx2x_get_load_status(bp, BP_PATH(bp));
9876 global = bnx2x_reset_is_global(bp);
9877
9878 /*
9879 * In case of a parity in a global block, let
9880 * the first leader that performs a
9881 * leader_reset() reset the global blocks in
9882 * order to clear global attentions. Otherwise
9883 * the gates will remain closed for that
9884 * engine.
9885 */
9886 if (load_status ||
9887 (global && other_load_status)) {
9888 /* Wait until all other functions get
9889 * down.
9890 */
9891 schedule_delayed_work(&bp->sp_rtnl_task,
9892 HZ/10);
9893 return;
9894 } else {
9895 /* If all other functions got down -
9896 * try to bring the chip back to
9897 * normal. In any case it's an exit
9898 * point for a leader.
9899 */
9900 if (bnx2x_leader_reset(bp)) {
9901 bnx2x_recovery_failed(bp);
9902 return;
9903 }
9904
9905 /* If we are here, means that the
9906 * leader has succeeded and doesn't
9907 * want to be a leader any more. Try
9908 * to continue as a none-leader.
9909 */
9910 break;
9911 }
9912 } else { /* non-leader */
9913 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
9914 /* Try to get a LEADER_LOCK HW lock as
9915 * long as a former leader may have
9916 * been unloaded by the user or
9917 * released a leadership by another
9918 * reason.
9919 */
9920 if (bnx2x_trylock_leader_lock(bp)) {
9921 /* I'm a leader now! Restart a
9922 * switch case.
9923 */
9924 bp->is_leader = 1;
9925 break;
9926 }
9927
9928 schedule_delayed_work(&bp->sp_rtnl_task,
9929 HZ/10);
9930 return;
9931
9932 } else {
9933 /*
9934 * If there was a global attention, wait
9935 * for it to be cleared.
9936 */
9937 if (bnx2x_reset_is_global(bp)) {
9938 schedule_delayed_work(
9939 &bp->sp_rtnl_task,
9940 HZ/10);
9941 return;
9942 }
9943
9944 error_recovered =
9945 bp->eth_stats.recoverable_error;
9946 error_unrecovered =
9947 bp->eth_stats.unrecoverable_error;
9948 bp->recovery_state =
9949 BNX2X_RECOVERY_NIC_LOADING;
9950 if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
9951 error_unrecovered++;
9952 netdev_err(bp->dev,
9953 "Recovery failed. Power cycle needed\n");
9954 /* Disconnect this device */
9955 netif_device_detach(bp->dev);
9956 /* Shut down the power */
9957 bnx2x_set_power_state(
9958 bp, PCI_D3hot);
9959 smp_mb();
9960 } else {
9961 bp->recovery_state =
9962 BNX2X_RECOVERY_DONE;
9963 error_recovered++;
9964 smp_mb();
9965 }
9966 bp->eth_stats.recoverable_error =
9967 error_recovered;
9968 bp->eth_stats.unrecoverable_error =
9969 error_unrecovered;
9970
9971 return;
9972 }
9973 }
9974 default:
9975 return;
9976 }
9977 }
9978 }
9979
9980 static int bnx2x_close(struct net_device *dev);
9981
9982 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
9983 * scheduled on a general queue in order to prevent a dead lock.
9984 */
9985 static void bnx2x_sp_rtnl_task(struct work_struct *work)
9986 {
9987 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
9988
9989 rtnl_lock();
9990
9991 if (!netif_running(bp->dev)) {
9992 rtnl_unlock();
9993 return;
9994 }
9995
9996 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
9997 #ifdef BNX2X_STOP_ON_ERROR
9998 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9999 "you will need to reboot when done\n");
10000 goto sp_rtnl_not_reset;
10001 #endif
10002 /*
10003 * Clear all pending SP commands as we are going to reset the
10004 * function anyway.
10005 */
10006 bp->sp_rtnl_state = 0;
10007 smp_mb();
10008
10009 bnx2x_parity_recover(bp);
10010
10011 rtnl_unlock();
10012 return;
10013 }
10014
10015 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
10016 #ifdef BNX2X_STOP_ON_ERROR
10017 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10018 "you will need to reboot when done\n");
10019 goto sp_rtnl_not_reset;
10020 #endif
10021
10022 /*
10023 * Clear all pending SP commands as we are going to reset the
10024 * function anyway.
10025 */
10026 bp->sp_rtnl_state = 0;
10027 smp_mb();
10028
10029 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
10030 bnx2x_nic_load(bp, LOAD_NORMAL);
10031
10032 rtnl_unlock();
10033 return;
10034 }
10035 #ifdef BNX2X_STOP_ON_ERROR
10036 sp_rtnl_not_reset:
10037 #endif
10038 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
10039 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
10040 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
10041 bnx2x_after_function_update(bp);
10042 /*
10043 * in case of fan failure we need to reset id if the "stop on error"
10044 * debug flag is set, since we trying to prevent permanent overheating
10045 * damage
10046 */
10047 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
10048 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
10049 netif_device_detach(bp->dev);
10050 bnx2x_close(bp->dev);
10051 rtnl_unlock();
10052 return;
10053 }
10054
10055 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
10056 DP(BNX2X_MSG_SP,
10057 "sending set mcast vf pf channel message from rtnl sp-task\n");
10058 bnx2x_vfpf_set_mcast(bp->dev);
10059 }
10060 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
10061 &bp->sp_rtnl_state)){
10062 if (!test_bit(__LINK_STATE_NOCARRIER, &bp->dev->state)) {
10063 bnx2x_tx_disable(bp);
10064 BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n");
10065 }
10066 }
10067
10068 if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) {
10069 DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n");
10070 bnx2x_set_rx_mode_inner(bp);
10071 }
10072
10073 if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
10074 &bp->sp_rtnl_state))
10075 bnx2x_pf_set_vfs_vlan(bp);
10076
10077 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) {
10078 bnx2x_dcbx_stop_hw_tx(bp);
10079 bnx2x_dcbx_resume_hw_tx(bp);
10080 }
10081
10082 if (test_and_clear_bit(BNX2X_SP_RTNL_GET_DRV_VERSION,
10083 &bp->sp_rtnl_state))
10084 bnx2x_update_mng_version(bp);
10085
10086 /* work which needs rtnl lock not-taken (as it takes the lock itself and
10087 * can be called from other contexts as well)
10088 */
10089 rtnl_unlock();
10090
10091 /* enable SR-IOV if applicable */
10092 if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
10093 &bp->sp_rtnl_state)) {
10094 bnx2x_disable_sriov(bp);
10095 bnx2x_enable_sriov(bp);
10096 }
10097 }
10098
10099 static void bnx2x_period_task(struct work_struct *work)
10100 {
10101 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
10102
10103 if (!netif_running(bp->dev))
10104 goto period_task_exit;
10105
10106 if (CHIP_REV_IS_SLOW(bp)) {
10107 BNX2X_ERR("period task called on emulation, ignoring\n");
10108 goto period_task_exit;
10109 }
10110
10111 bnx2x_acquire_phy_lock(bp);
10112 /*
10113 * The barrier is needed to ensure the ordering between the writing to
10114 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
10115 * the reading here.
10116 */
10117 smp_mb();
10118 if (bp->port.pmf) {
10119 bnx2x_period_func(&bp->link_params, &bp->link_vars);
10120
10121 /* Re-queue task in 1 sec */
10122 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
10123 }
10124
10125 bnx2x_release_phy_lock(bp);
10126 period_task_exit:
10127 return;
10128 }
10129
10130 /*
10131 * Init service functions
10132 */
10133
10134 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
10135 {
10136 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
10137 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
10138 return base + (BP_ABS_FUNC(bp)) * stride;
10139 }
10140
10141 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
10142 struct bnx2x_mac_vals *vals)
10143 {
10144 u32 val, base_addr, offset, mask, reset_reg;
10145 bool mac_stopped = false;
10146 u8 port = BP_PORT(bp);
10147
10148 /* reset addresses as they also mark which values were changed */
10149 vals->bmac_addr = 0;
10150 vals->umac_addr = 0;
10151 vals->xmac_addr = 0;
10152 vals->emac_addr = 0;
10153
10154 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
10155
10156 if (!CHIP_IS_E3(bp)) {
10157 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
10158 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
10159 if ((mask & reset_reg) && val) {
10160 u32 wb_data[2];
10161 BNX2X_DEV_INFO("Disable bmac Rx\n");
10162 base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
10163 : NIG_REG_INGRESS_BMAC0_MEM;
10164 offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
10165 : BIGMAC_REGISTER_BMAC_CONTROL;
10166
10167 /*
10168 * use rd/wr since we cannot use dmae. This is safe
10169 * since MCP won't access the bus due to the request
10170 * to unload, and no function on the path can be
10171 * loaded at this time.
10172 */
10173 wb_data[0] = REG_RD(bp, base_addr + offset);
10174 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
10175 vals->bmac_addr = base_addr + offset;
10176 vals->bmac_val[0] = wb_data[0];
10177 vals->bmac_val[1] = wb_data[1];
10178 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
10179 REG_WR(bp, vals->bmac_addr, wb_data[0]);
10180 REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
10181 }
10182 BNX2X_DEV_INFO("Disable emac Rx\n");
10183 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
10184 vals->emac_val = REG_RD(bp, vals->emac_addr);
10185 REG_WR(bp, vals->emac_addr, 0);
10186 mac_stopped = true;
10187 } else {
10188 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
10189 BNX2X_DEV_INFO("Disable xmac Rx\n");
10190 base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
10191 val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
10192 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10193 val & ~(1 << 1));
10194 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10195 val | (1 << 1));
10196 vals->xmac_addr = base_addr + XMAC_REG_CTRL;
10197 vals->xmac_val = REG_RD(bp, vals->xmac_addr);
10198 REG_WR(bp, vals->xmac_addr, 0);
10199 mac_stopped = true;
10200 }
10201 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
10202 if (mask & reset_reg) {
10203 BNX2X_DEV_INFO("Disable umac Rx\n");
10204 base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10205 vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
10206 vals->umac_val = REG_RD(bp, vals->umac_addr);
10207 REG_WR(bp, vals->umac_addr, 0);
10208 mac_stopped = true;
10209 }
10210 }
10211
10212 if (mac_stopped)
10213 msleep(20);
10214 }
10215
10216 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
10217 #define BNX2X_PREV_UNDI_PROD_ADDR_H(f) (BAR_TSTRORM_INTMEM + \
10218 0x1848 + ((f) << 4))
10219 #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
10220 #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
10221 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
10222
10223 #define BCM_5710_UNDI_FW_MF_MAJOR (0x07)
10224 #define BCM_5710_UNDI_FW_MF_MINOR (0x08)
10225 #define BCM_5710_UNDI_FW_MF_VERS (0x05)
10226
10227 static bool bnx2x_prev_is_after_undi(struct bnx2x *bp)
10228 {
10229 /* UNDI marks its presence in DORQ -
10230 * it initializes CID offset for normal bell to 0x7
10231 */
10232 if (!(REG_RD(bp, MISC_REG_RESET_REG_1) &
10233 MISC_REGISTERS_RESET_REG_1_RST_DORQ))
10234 return false;
10235
10236 if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) {
10237 BNX2X_DEV_INFO("UNDI previously loaded\n");
10238 return true;
10239 }
10240
10241 return false;
10242 }
10243
10244 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 inc)
10245 {
10246 u16 rcq, bd;
10247 u32 addr, tmp_reg;
10248
10249 if (BP_FUNC(bp) < 2)
10250 addr = BNX2X_PREV_UNDI_PROD_ADDR(BP_PORT(bp));
10251 else
10252 addr = BNX2X_PREV_UNDI_PROD_ADDR_H(BP_FUNC(bp) - 2);
10253
10254 tmp_reg = REG_RD(bp, addr);
10255 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
10256 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
10257
10258 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
10259 REG_WR(bp, addr, tmp_reg);
10260
10261 BNX2X_DEV_INFO("UNDI producer [%d/%d][%08x] rings bd -> 0x%04x, rcq -> 0x%04x\n",
10262 BP_PORT(bp), BP_FUNC(bp), addr, bd, rcq);
10263 }
10264
10265 static int bnx2x_prev_mcp_done(struct bnx2x *bp)
10266 {
10267 u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
10268 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
10269 if (!rc) {
10270 BNX2X_ERR("MCP response failure, aborting\n");
10271 return -EBUSY;
10272 }
10273
10274 return 0;
10275 }
10276
10277 static struct bnx2x_prev_path_list *
10278 bnx2x_prev_path_get_entry(struct bnx2x *bp)
10279 {
10280 struct bnx2x_prev_path_list *tmp_list;
10281
10282 list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
10283 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
10284 bp->pdev->bus->number == tmp_list->bus &&
10285 BP_PATH(bp) == tmp_list->path)
10286 return tmp_list;
10287
10288 return NULL;
10289 }
10290
10291 static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
10292 {
10293 struct bnx2x_prev_path_list *tmp_list;
10294 int rc;
10295
10296 rc = down_interruptible(&bnx2x_prev_sem);
10297 if (rc) {
10298 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10299 return rc;
10300 }
10301
10302 tmp_list = bnx2x_prev_path_get_entry(bp);
10303 if (tmp_list) {
10304 tmp_list->aer = 1;
10305 rc = 0;
10306 } else {
10307 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
10308 BP_PATH(bp));
10309 }
10310
10311 up(&bnx2x_prev_sem);
10312
10313 return rc;
10314 }
10315
10316 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
10317 {
10318 struct bnx2x_prev_path_list *tmp_list;
10319 bool rc = false;
10320
10321 if (down_trylock(&bnx2x_prev_sem))
10322 return false;
10323
10324 tmp_list = bnx2x_prev_path_get_entry(bp);
10325 if (tmp_list) {
10326 if (tmp_list->aer) {
10327 DP(NETIF_MSG_HW, "Path %d was marked by AER\n",
10328 BP_PATH(bp));
10329 } else {
10330 rc = true;
10331 BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
10332 BP_PATH(bp));
10333 }
10334 }
10335
10336 up(&bnx2x_prev_sem);
10337
10338 return rc;
10339 }
10340
10341 bool bnx2x_port_after_undi(struct bnx2x *bp)
10342 {
10343 struct bnx2x_prev_path_list *entry;
10344 bool val;
10345
10346 down(&bnx2x_prev_sem);
10347
10348 entry = bnx2x_prev_path_get_entry(bp);
10349 val = !!(entry && (entry->undi & (1 << BP_PORT(bp))));
10350
10351 up(&bnx2x_prev_sem);
10352
10353 return val;
10354 }
10355
10356 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
10357 {
10358 struct bnx2x_prev_path_list *tmp_list;
10359 int rc;
10360
10361 rc = down_interruptible(&bnx2x_prev_sem);
10362 if (rc) {
10363 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10364 return rc;
10365 }
10366
10367 /* Check whether the entry for this path already exists */
10368 tmp_list = bnx2x_prev_path_get_entry(bp);
10369 if (tmp_list) {
10370 if (!tmp_list->aer) {
10371 BNX2X_ERR("Re-Marking the path.\n");
10372 } else {
10373 DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
10374 BP_PATH(bp));
10375 tmp_list->aer = 0;
10376 }
10377 up(&bnx2x_prev_sem);
10378 return 0;
10379 }
10380 up(&bnx2x_prev_sem);
10381
10382 /* Create an entry for this path and add it */
10383 tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
10384 if (!tmp_list) {
10385 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
10386 return -ENOMEM;
10387 }
10388
10389 tmp_list->bus = bp->pdev->bus->number;
10390 tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
10391 tmp_list->path = BP_PATH(bp);
10392 tmp_list->aer = 0;
10393 tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
10394
10395 rc = down_interruptible(&bnx2x_prev_sem);
10396 if (rc) {
10397 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10398 kfree(tmp_list);
10399 } else {
10400 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n",
10401 BP_PATH(bp));
10402 list_add(&tmp_list->list, &bnx2x_prev_list);
10403 up(&bnx2x_prev_sem);
10404 }
10405
10406 return rc;
10407 }
10408
10409 static int bnx2x_do_flr(struct bnx2x *bp)
10410 {
10411 struct pci_dev *dev = bp->pdev;
10412
10413 if (CHIP_IS_E1x(bp)) {
10414 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
10415 return -EINVAL;
10416 }
10417
10418 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
10419 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
10420 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
10421 bp->common.bc_ver);
10422 return -EINVAL;
10423 }
10424
10425 if (!pci_wait_for_pending_transaction(dev))
10426 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
10427
10428 BNX2X_DEV_INFO("Initiating FLR\n");
10429 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
10430
10431 return 0;
10432 }
10433
10434 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
10435 {
10436 int rc;
10437
10438 BNX2X_DEV_INFO("Uncommon unload Flow\n");
10439
10440 /* Test if previous unload process was already finished for this path */
10441 if (bnx2x_prev_is_path_marked(bp))
10442 return bnx2x_prev_mcp_done(bp);
10443
10444 BNX2X_DEV_INFO("Path is unmarked\n");
10445
10446 /* Cannot proceed with FLR if UNDI is loaded, since FW does not match */
10447 if (bnx2x_prev_is_after_undi(bp))
10448 goto out;
10449
10450 /* If function has FLR capabilities, and existing FW version matches
10451 * the one required, then FLR will be sufficient to clean any residue
10452 * left by previous driver
10453 */
10454 rc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false);
10455
10456 if (!rc) {
10457 /* fw version is good */
10458 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
10459 rc = bnx2x_do_flr(bp);
10460 }
10461
10462 if (!rc) {
10463 /* FLR was performed */
10464 BNX2X_DEV_INFO("FLR successful\n");
10465 return 0;
10466 }
10467
10468 BNX2X_DEV_INFO("Could not FLR\n");
10469
10470 out:
10471 /* Close the MCP request, return failure*/
10472 rc = bnx2x_prev_mcp_done(bp);
10473 if (!rc)
10474 rc = BNX2X_PREV_WAIT_NEEDED;
10475
10476 return rc;
10477 }
10478
10479 static int bnx2x_prev_unload_common(struct bnx2x *bp)
10480 {
10481 u32 reset_reg, tmp_reg = 0, rc;
10482 bool prev_undi = false;
10483 struct bnx2x_mac_vals mac_vals;
10484
10485 /* It is possible a previous function received 'common' answer,
10486 * but hasn't loaded yet, therefore creating a scenario of
10487 * multiple functions receiving 'common' on the same path.
10488 */
10489 BNX2X_DEV_INFO("Common unload Flow\n");
10490
10491 memset(&mac_vals, 0, sizeof(mac_vals));
10492
10493 if (bnx2x_prev_is_path_marked(bp))
10494 return bnx2x_prev_mcp_done(bp);
10495
10496 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
10497
10498 /* Reset should be performed after BRB is emptied */
10499 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
10500 u32 timer_count = 1000;
10501
10502 /* Close the MAC Rx to prevent BRB from filling up */
10503 bnx2x_prev_unload_close_mac(bp, &mac_vals);
10504
10505 /* close LLH filters towards the BRB */
10506 bnx2x_set_rx_filter(&bp->link_params, 0);
10507
10508 /* Check if the UNDI driver was previously loaded */
10509 if (bnx2x_prev_is_after_undi(bp)) {
10510 prev_undi = true;
10511 /* clear the UNDI indication */
10512 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
10513 /* clear possible idle check errors */
10514 REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
10515 }
10516 if (!CHIP_IS_E1x(bp))
10517 /* block FW from writing to host */
10518 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10519
10520 /* wait until BRB is empty */
10521 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10522 while (timer_count) {
10523 u32 prev_brb = tmp_reg;
10524
10525 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10526 if (!tmp_reg)
10527 break;
10528
10529 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
10530
10531 /* reset timer as long as BRB actually gets emptied */
10532 if (prev_brb > tmp_reg)
10533 timer_count = 1000;
10534 else
10535 timer_count--;
10536
10537 /* If UNDI resides in memory, manually increment it */
10538 if (prev_undi)
10539 bnx2x_prev_unload_undi_inc(bp, 1);
10540
10541 udelay(10);
10542 }
10543
10544 if (!timer_count)
10545 BNX2X_ERR("Failed to empty BRB, hope for the best\n");
10546 }
10547
10548 /* No packets are in the pipeline, path is ready for reset */
10549 bnx2x_reset_common(bp);
10550
10551 if (mac_vals.xmac_addr)
10552 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
10553 if (mac_vals.umac_addr)
10554 REG_WR(bp, mac_vals.umac_addr, mac_vals.umac_val);
10555 if (mac_vals.emac_addr)
10556 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
10557 if (mac_vals.bmac_addr) {
10558 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
10559 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
10560 }
10561
10562 rc = bnx2x_prev_mark_path(bp, prev_undi);
10563 if (rc) {
10564 bnx2x_prev_mcp_done(bp);
10565 return rc;
10566 }
10567
10568 return bnx2x_prev_mcp_done(bp);
10569 }
10570
10571 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
10572 * and boot began, or when kdump kernel was loaded. Either case would invalidate
10573 * the addresses of the transaction, resulting in was-error bit set in the pci
10574 * causing all hw-to-host pcie transactions to timeout. If this happened we want
10575 * to clear the interrupt which detected this from the pglueb and the was done
10576 * bit
10577 */
10578 static void bnx2x_prev_interrupted_dmae(struct bnx2x *bp)
10579 {
10580 if (!CHIP_IS_E1x(bp)) {
10581 u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS);
10582 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
10583 DP(BNX2X_MSG_SP,
10584 "'was error' bit was found to be set in pglueb upon startup. Clearing\n");
10585 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
10586 1 << BP_FUNC(bp));
10587 }
10588 }
10589 }
10590
10591 static int bnx2x_prev_unload(struct bnx2x *bp)
10592 {
10593 int time_counter = 10;
10594 u32 rc, fw, hw_lock_reg, hw_lock_val;
10595 BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10596
10597 /* clear hw from errors which may have resulted from an interrupted
10598 * dmae transaction.
10599 */
10600 bnx2x_prev_interrupted_dmae(bp);
10601
10602 /* Release previously held locks */
10603 hw_lock_reg = (BP_FUNC(bp) <= 5) ?
10604 (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
10605 (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
10606
10607 hw_lock_val = REG_RD(bp, hw_lock_reg);
10608 if (hw_lock_val) {
10609 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
10610 BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10611 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10612 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
10613 }
10614
10615 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10616 REG_WR(bp, hw_lock_reg, 0xffffffff);
10617 } else
10618 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10619
10620 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
10621 BNX2X_DEV_INFO("Release previously held alr\n");
10622 bnx2x_release_alr(bp);
10623 }
10624
10625 do {
10626 int aer = 0;
10627 /* Lock MCP using an unload request */
10628 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10629 if (!fw) {
10630 BNX2X_ERR("MCP response failure, aborting\n");
10631 rc = -EBUSY;
10632 break;
10633 }
10634
10635 rc = down_interruptible(&bnx2x_prev_sem);
10636 if (rc) {
10637 BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10638 rc);
10639 } else {
10640 /* If Path is marked by EEH, ignore unload status */
10641 aer = !!(bnx2x_prev_path_get_entry(bp) &&
10642 bnx2x_prev_path_get_entry(bp)->aer);
10643 up(&bnx2x_prev_sem);
10644 }
10645
10646 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) {
10647 rc = bnx2x_prev_unload_common(bp);
10648 break;
10649 }
10650
10651 /* non-common reply from MCP might require looping */
10652 rc = bnx2x_prev_unload_uncommon(bp);
10653 if (rc != BNX2X_PREV_WAIT_NEEDED)
10654 break;
10655
10656 msleep(20);
10657 } while (--time_counter);
10658
10659 if (!time_counter || rc) {
10660 BNX2X_DEV_INFO("Unloading previous driver did not occur, Possibly due to MF UNDI\n");
10661 rc = -EPROBE_DEFER;
10662 }
10663
10664 /* Mark function if its port was used to boot from SAN */
10665 if (bnx2x_port_after_undi(bp))
10666 bp->link_params.feature_config_flags |=
10667 FEATURE_CONFIG_BOOT_FROM_SAN;
10668
10669 BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10670
10671 return rc;
10672 }
10673
10674 static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
10675 {
10676 u32 val, val2, val3, val4, id, boot_mode;
10677 u16 pmc;
10678
10679 /* Get the chip revision id and number. */
10680 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10681 val = REG_RD(bp, MISC_REG_CHIP_NUM);
10682 id = ((val & 0xffff) << 16);
10683 val = REG_RD(bp, MISC_REG_CHIP_REV);
10684 id |= ((val & 0xf) << 12);
10685
10686 /* Metal is read from PCI regs, but we can't access >=0x400 from
10687 * the configuration space (so we need to reg_rd)
10688 */
10689 val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
10690 id |= (((val >> 24) & 0xf) << 4);
10691 val = REG_RD(bp, MISC_REG_BOND_ID);
10692 id |= (val & 0xf);
10693 bp->common.chip_id = id;
10694
10695 /* force 57811 according to MISC register */
10696 if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10697 if (CHIP_IS_57810(bp))
10698 bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10699 (bp->common.chip_id & 0x0000FFFF);
10700 else if (CHIP_IS_57810_MF(bp))
10701 bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10702 (bp->common.chip_id & 0x0000FFFF);
10703 bp->common.chip_id |= 0x1;
10704 }
10705
10706 /* Set doorbell size */
10707 bp->db_size = (1 << BNX2X_DB_SHIFT);
10708
10709 if (!CHIP_IS_E1x(bp)) {
10710 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10711 if ((val & 1) == 0)
10712 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10713 else
10714 val = (val >> 1) & 1;
10715 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10716 "2_PORT_MODE");
10717 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10718 CHIP_2_PORT_MODE;
10719
10720 if (CHIP_MODE_IS_4_PORT(bp))
10721 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
10722 else
10723 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
10724 } else {
10725 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10726 bp->pfid = bp->pf_num; /* 0..7 */
10727 }
10728
10729 BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10730
10731 bp->link_params.chip_id = bp->common.chip_id;
10732 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
10733
10734 val = (REG_RD(bp, 0x2874) & 0x55);
10735 if ((bp->common.chip_id & 0x1) ||
10736 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
10737 bp->flags |= ONE_PORT_FLAG;
10738 BNX2X_DEV_INFO("single port device\n");
10739 }
10740
10741 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
10742 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
10743 (val & MCPR_NVM_CFG4_FLASH_SIZE));
10744 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10745 bp->common.flash_size, bp->common.flash_size);
10746
10747 bnx2x_init_shmem(bp);
10748
10749 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
10750 MISC_REG_GENERIC_CR_1 :
10751 MISC_REG_GENERIC_CR_0));
10752
10753 bp->link_params.shmem_base = bp->common.shmem_base;
10754 bp->link_params.shmem2_base = bp->common.shmem2_base;
10755 if (SHMEM2_RD(bp, size) >
10756 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
10757 bp->link_params.lfa_base =
10758 REG_RD(bp, bp->common.shmem2_base +
10759 (u32)offsetof(struct shmem2_region,
10760 lfa_host_addr[BP_PORT(bp)]));
10761 else
10762 bp->link_params.lfa_base = 0;
10763 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
10764 bp->common.shmem_base, bp->common.shmem2_base);
10765
10766 if (!bp->common.shmem_base) {
10767 BNX2X_DEV_INFO("MCP not active\n");
10768 bp->flags |= NO_MCP_FLAG;
10769 return;
10770 }
10771
10772 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
10773 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
10774
10775 bp->link_params.hw_led_mode = ((bp->common.hw_config &
10776 SHARED_HW_CFG_LED_MODE_MASK) >>
10777 SHARED_HW_CFG_LED_MODE_SHIFT);
10778
10779 bp->link_params.feature_config_flags = 0;
10780 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
10781 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
10782 bp->link_params.feature_config_flags |=
10783 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10784 else
10785 bp->link_params.feature_config_flags &=
10786 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10787
10788 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
10789 bp->common.bc_ver = val;
10790 BNX2X_DEV_INFO("bc_ver %X\n", val);
10791 if (val < BNX2X_BC_VER) {
10792 /* for now only warn
10793 * later we might need to enforce this */
10794 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
10795 BNX2X_BC_VER, val);
10796 }
10797 bp->link_params.feature_config_flags |=
10798 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
10799 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
10800
10801 bp->link_params.feature_config_flags |=
10802 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
10803 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
10804 bp->link_params.feature_config_flags |=
10805 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
10806 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
10807 bp->link_params.feature_config_flags |=
10808 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
10809 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
10810
10811 bp->link_params.feature_config_flags |=
10812 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
10813 FEATURE_CONFIG_MT_SUPPORT : 0;
10814
10815 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
10816 BC_SUPPORTS_PFC_STATS : 0;
10817
10818 bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
10819 BC_SUPPORTS_FCOE_FEATURES : 0;
10820
10821 bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
10822 BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
10823
10824 bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ?
10825 BC_SUPPORTS_RMMOD_CMD : 0;
10826
10827 boot_mode = SHMEM_RD(bp,
10828 dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
10829 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
10830 switch (boot_mode) {
10831 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
10832 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
10833 break;
10834 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
10835 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
10836 break;
10837 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
10838 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
10839 break;
10840 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
10841 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
10842 break;
10843 }
10844
10845 pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc);
10846 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
10847
10848 BNX2X_DEV_INFO("%sWoL capable\n",
10849 (bp->flags & NO_WOL_FLAG) ? "not " : "");
10850
10851 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
10852 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
10853 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
10854 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
10855
10856 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
10857 val, val2, val3, val4);
10858 }
10859
10860 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
10861 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
10862
10863 static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
10864 {
10865 int pfid = BP_FUNC(bp);
10866 int igu_sb_id;
10867 u32 val;
10868 u8 fid, igu_sb_cnt = 0;
10869
10870 bp->igu_base_sb = 0xff;
10871 if (CHIP_INT_MODE_IS_BC(bp)) {
10872 int vn = BP_VN(bp);
10873 igu_sb_cnt = bp->igu_sb_cnt;
10874 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
10875 FP_SB_MAX_E1x;
10876
10877 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
10878 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
10879
10880 return 0;
10881 }
10882
10883 /* IGU in normal mode - read CAM */
10884 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
10885 igu_sb_id++) {
10886 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
10887 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
10888 continue;
10889 fid = IGU_FID(val);
10890 if ((fid & IGU_FID_ENCODE_IS_PF)) {
10891 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
10892 continue;
10893 if (IGU_VEC(val) == 0)
10894 /* default status block */
10895 bp->igu_dsb_id = igu_sb_id;
10896 else {
10897 if (bp->igu_base_sb == 0xff)
10898 bp->igu_base_sb = igu_sb_id;
10899 igu_sb_cnt++;
10900 }
10901 }
10902 }
10903
10904 #ifdef CONFIG_PCI_MSI
10905 /* Due to new PF resource allocation by MFW T7.4 and above, it's
10906 * optional that number of CAM entries will not be equal to the value
10907 * advertised in PCI.
10908 * Driver should use the minimal value of both as the actual status
10909 * block count
10910 */
10911 bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
10912 #endif
10913
10914 if (igu_sb_cnt == 0) {
10915 BNX2X_ERR("CAM configuration error\n");
10916 return -EINVAL;
10917 }
10918
10919 return 0;
10920 }
10921
10922 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
10923 {
10924 int cfg_size = 0, idx, port = BP_PORT(bp);
10925
10926 /* Aggregation of supported attributes of all external phys */
10927 bp->port.supported[0] = 0;
10928 bp->port.supported[1] = 0;
10929 switch (bp->link_params.num_phys) {
10930 case 1:
10931 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
10932 cfg_size = 1;
10933 break;
10934 case 2:
10935 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
10936 cfg_size = 1;
10937 break;
10938 case 3:
10939 if (bp->link_params.multi_phy_config &
10940 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
10941 bp->port.supported[1] =
10942 bp->link_params.phy[EXT_PHY1].supported;
10943 bp->port.supported[0] =
10944 bp->link_params.phy[EXT_PHY2].supported;
10945 } else {
10946 bp->port.supported[0] =
10947 bp->link_params.phy[EXT_PHY1].supported;
10948 bp->port.supported[1] =
10949 bp->link_params.phy[EXT_PHY2].supported;
10950 }
10951 cfg_size = 2;
10952 break;
10953 }
10954
10955 if (!(bp->port.supported[0] || bp->port.supported[1])) {
10956 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
10957 SHMEM_RD(bp,
10958 dev_info.port_hw_config[port].external_phy_config),
10959 SHMEM_RD(bp,
10960 dev_info.port_hw_config[port].external_phy_config2));
10961 return;
10962 }
10963
10964 if (CHIP_IS_E3(bp))
10965 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
10966 else {
10967 switch (switch_cfg) {
10968 case SWITCH_CFG_1G:
10969 bp->port.phy_addr = REG_RD(
10970 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
10971 break;
10972 case SWITCH_CFG_10G:
10973 bp->port.phy_addr = REG_RD(
10974 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
10975 break;
10976 default:
10977 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
10978 bp->port.link_config[0]);
10979 return;
10980 }
10981 }
10982 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
10983 /* mask what we support according to speed_cap_mask per configuration */
10984 for (idx = 0; idx < cfg_size; idx++) {
10985 if (!(bp->link_params.speed_cap_mask[idx] &
10986 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
10987 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
10988
10989 if (!(bp->link_params.speed_cap_mask[idx] &
10990 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
10991 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
10992
10993 if (!(bp->link_params.speed_cap_mask[idx] &
10994 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
10995 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
10996
10997 if (!(bp->link_params.speed_cap_mask[idx] &
10998 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
10999 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
11000
11001 if (!(bp->link_params.speed_cap_mask[idx] &
11002 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
11003 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
11004 SUPPORTED_1000baseT_Full);
11005
11006 if (!(bp->link_params.speed_cap_mask[idx] &
11007 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
11008 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
11009
11010 if (!(bp->link_params.speed_cap_mask[idx] &
11011 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
11012 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
11013
11014 if (!(bp->link_params.speed_cap_mask[idx] &
11015 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
11016 bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full;
11017 }
11018
11019 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
11020 bp->port.supported[1]);
11021 }
11022
11023 static void bnx2x_link_settings_requested(struct bnx2x *bp)
11024 {
11025 u32 link_config, idx, cfg_size = 0;
11026 bp->port.advertising[0] = 0;
11027 bp->port.advertising[1] = 0;
11028 switch (bp->link_params.num_phys) {
11029 case 1:
11030 case 2:
11031 cfg_size = 1;
11032 break;
11033 case 3:
11034 cfg_size = 2;
11035 break;
11036 }
11037 for (idx = 0; idx < cfg_size; idx++) {
11038 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
11039 link_config = bp->port.link_config[idx];
11040 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
11041 case PORT_FEATURE_LINK_SPEED_AUTO:
11042 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
11043 bp->link_params.req_line_speed[idx] =
11044 SPEED_AUTO_NEG;
11045 bp->port.advertising[idx] |=
11046 bp->port.supported[idx];
11047 if (bp->link_params.phy[EXT_PHY1].type ==
11048 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
11049 bp->port.advertising[idx] |=
11050 (SUPPORTED_100baseT_Half |
11051 SUPPORTED_100baseT_Full);
11052 } else {
11053 /* force 10G, no AN */
11054 bp->link_params.req_line_speed[idx] =
11055 SPEED_10000;
11056 bp->port.advertising[idx] |=
11057 (ADVERTISED_10000baseT_Full |
11058 ADVERTISED_FIBRE);
11059 continue;
11060 }
11061 break;
11062
11063 case PORT_FEATURE_LINK_SPEED_10M_FULL:
11064 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
11065 bp->link_params.req_line_speed[idx] =
11066 SPEED_10;
11067 bp->port.advertising[idx] |=
11068 (ADVERTISED_10baseT_Full |
11069 ADVERTISED_TP);
11070 } else {
11071 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11072 link_config,
11073 bp->link_params.speed_cap_mask[idx]);
11074 return;
11075 }
11076 break;
11077
11078 case PORT_FEATURE_LINK_SPEED_10M_HALF:
11079 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
11080 bp->link_params.req_line_speed[idx] =
11081 SPEED_10;
11082 bp->link_params.req_duplex[idx] =
11083 DUPLEX_HALF;
11084 bp->port.advertising[idx] |=
11085 (ADVERTISED_10baseT_Half |
11086 ADVERTISED_TP);
11087 } else {
11088 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11089 link_config,
11090 bp->link_params.speed_cap_mask[idx]);
11091 return;
11092 }
11093 break;
11094
11095 case PORT_FEATURE_LINK_SPEED_100M_FULL:
11096 if (bp->port.supported[idx] &
11097 SUPPORTED_100baseT_Full) {
11098 bp->link_params.req_line_speed[idx] =
11099 SPEED_100;
11100 bp->port.advertising[idx] |=
11101 (ADVERTISED_100baseT_Full |
11102 ADVERTISED_TP);
11103 } else {
11104 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11105 link_config,
11106 bp->link_params.speed_cap_mask[idx]);
11107 return;
11108 }
11109 break;
11110
11111 case PORT_FEATURE_LINK_SPEED_100M_HALF:
11112 if (bp->port.supported[idx] &
11113 SUPPORTED_100baseT_Half) {
11114 bp->link_params.req_line_speed[idx] =
11115 SPEED_100;
11116 bp->link_params.req_duplex[idx] =
11117 DUPLEX_HALF;
11118 bp->port.advertising[idx] |=
11119 (ADVERTISED_100baseT_Half |
11120 ADVERTISED_TP);
11121 } else {
11122 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11123 link_config,
11124 bp->link_params.speed_cap_mask[idx]);
11125 return;
11126 }
11127 break;
11128
11129 case PORT_FEATURE_LINK_SPEED_1G:
11130 if (bp->port.supported[idx] &
11131 SUPPORTED_1000baseT_Full) {
11132 bp->link_params.req_line_speed[idx] =
11133 SPEED_1000;
11134 bp->port.advertising[idx] |=
11135 (ADVERTISED_1000baseT_Full |
11136 ADVERTISED_TP);
11137 } else {
11138 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11139 link_config,
11140 bp->link_params.speed_cap_mask[idx]);
11141 return;
11142 }
11143 break;
11144
11145 case PORT_FEATURE_LINK_SPEED_2_5G:
11146 if (bp->port.supported[idx] &
11147 SUPPORTED_2500baseX_Full) {
11148 bp->link_params.req_line_speed[idx] =
11149 SPEED_2500;
11150 bp->port.advertising[idx] |=
11151 (ADVERTISED_2500baseX_Full |
11152 ADVERTISED_TP);
11153 } else {
11154 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11155 link_config,
11156 bp->link_params.speed_cap_mask[idx]);
11157 return;
11158 }
11159 break;
11160
11161 case PORT_FEATURE_LINK_SPEED_10G_CX4:
11162 if (bp->port.supported[idx] &
11163 SUPPORTED_10000baseT_Full) {
11164 bp->link_params.req_line_speed[idx] =
11165 SPEED_10000;
11166 bp->port.advertising[idx] |=
11167 (ADVERTISED_10000baseT_Full |
11168 ADVERTISED_FIBRE);
11169 } else {
11170 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11171 link_config,
11172 bp->link_params.speed_cap_mask[idx]);
11173 return;
11174 }
11175 break;
11176 case PORT_FEATURE_LINK_SPEED_20G:
11177 bp->link_params.req_line_speed[idx] = SPEED_20000;
11178
11179 break;
11180 default:
11181 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
11182 link_config);
11183 bp->link_params.req_line_speed[idx] =
11184 SPEED_AUTO_NEG;
11185 bp->port.advertising[idx] =
11186 bp->port.supported[idx];
11187 break;
11188 }
11189
11190 bp->link_params.req_flow_ctrl[idx] = (link_config &
11191 PORT_FEATURE_FLOW_CONTROL_MASK);
11192 if (bp->link_params.req_flow_ctrl[idx] ==
11193 BNX2X_FLOW_CTRL_AUTO) {
11194 if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
11195 bp->link_params.req_flow_ctrl[idx] =
11196 BNX2X_FLOW_CTRL_NONE;
11197 else
11198 bnx2x_set_requested_fc(bp);
11199 }
11200
11201 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
11202 bp->link_params.req_line_speed[idx],
11203 bp->link_params.req_duplex[idx],
11204 bp->link_params.req_flow_ctrl[idx],
11205 bp->port.advertising[idx]);
11206 }
11207 }
11208
11209 static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
11210 {
11211 __be16 mac_hi_be = cpu_to_be16(mac_hi);
11212 __be32 mac_lo_be = cpu_to_be32(mac_lo);
11213 memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
11214 memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
11215 }
11216
11217 static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
11218 {
11219 int port = BP_PORT(bp);
11220 u32 config;
11221 u32 ext_phy_type, ext_phy_config, eee_mode;
11222
11223 bp->link_params.bp = bp;
11224 bp->link_params.port = port;
11225
11226 bp->link_params.lane_config =
11227 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
11228
11229 bp->link_params.speed_cap_mask[0] =
11230 SHMEM_RD(bp,
11231 dev_info.port_hw_config[port].speed_capability_mask) &
11232 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
11233 bp->link_params.speed_cap_mask[1] =
11234 SHMEM_RD(bp,
11235 dev_info.port_hw_config[port].speed_capability_mask2) &
11236 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
11237 bp->port.link_config[0] =
11238 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
11239
11240 bp->port.link_config[1] =
11241 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
11242
11243 bp->link_params.multi_phy_config =
11244 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
11245 /* If the device is capable of WoL, set the default state according
11246 * to the HW
11247 */
11248 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
11249 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
11250 (config & PORT_FEATURE_WOL_ENABLED));
11251
11252 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11253 PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
11254 bp->flags |= NO_ISCSI_FLAG;
11255 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11256 PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
11257 bp->flags |= NO_FCOE_FLAG;
11258
11259 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n",
11260 bp->link_params.lane_config,
11261 bp->link_params.speed_cap_mask[0],
11262 bp->port.link_config[0]);
11263
11264 bp->link_params.switch_cfg = (bp->port.link_config[0] &
11265 PORT_FEATURE_CONNECTED_SWITCH_MASK);
11266 bnx2x_phy_probe(&bp->link_params);
11267 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
11268
11269 bnx2x_link_settings_requested(bp);
11270
11271 /*
11272 * If connected directly, work with the internal PHY, otherwise, work
11273 * with the external PHY
11274 */
11275 ext_phy_config =
11276 SHMEM_RD(bp,
11277 dev_info.port_hw_config[port].external_phy_config);
11278 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11279 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
11280 bp->mdio.prtad = bp->port.phy_addr;
11281
11282 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
11283 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11284 bp->mdio.prtad =
11285 XGXS_EXT_PHY_ADDR(ext_phy_config);
11286
11287 /* Configure link feature according to nvram value */
11288 eee_mode = (((SHMEM_RD(bp, dev_info.
11289 port_feature_config[port].eee_power_mode)) &
11290 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
11291 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
11292 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
11293 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
11294 EEE_MODE_ENABLE_LPI |
11295 EEE_MODE_OUTPUT_TIME;
11296 } else {
11297 bp->link_params.eee_mode = 0;
11298 }
11299 }
11300
11301 void bnx2x_get_iscsi_info(struct bnx2x *bp)
11302 {
11303 u32 no_flags = NO_ISCSI_FLAG;
11304 int port = BP_PORT(bp);
11305 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11306 drv_lic_key[port].max_iscsi_conn);
11307
11308 if (!CNIC_SUPPORT(bp)) {
11309 bp->flags |= no_flags;
11310 return;
11311 }
11312
11313 /* Get the number of maximum allowed iSCSI connections */
11314 bp->cnic_eth_dev.max_iscsi_conn =
11315 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
11316 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
11317
11318 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
11319 bp->cnic_eth_dev.max_iscsi_conn);
11320
11321 /*
11322 * If maximum allowed number of connections is zero -
11323 * disable the feature.
11324 */
11325 if (!bp->cnic_eth_dev.max_iscsi_conn)
11326 bp->flags |= no_flags;
11327 }
11328
11329 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
11330 {
11331 /* Port info */
11332 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11333 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
11334 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11335 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
11336
11337 /* Node info */
11338 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11339 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
11340 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11341 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
11342 }
11343
11344 static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp)
11345 {
11346 u8 count = 0;
11347
11348 if (IS_MF(bp)) {
11349 u8 fid;
11350
11351 /* iterate over absolute function ids for this path: */
11352 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) {
11353 if (IS_MF_SD(bp)) {
11354 u32 cfg = MF_CFG_RD(bp,
11355 func_mf_config[fid].config);
11356
11357 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) &&
11358 ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) ==
11359 FUNC_MF_CFG_PROTOCOL_FCOE))
11360 count++;
11361 } else {
11362 u32 cfg = MF_CFG_RD(bp,
11363 func_ext_config[fid].
11364 func_cfg);
11365
11366 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) &&
11367 (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
11368 count++;
11369 }
11370 }
11371 } else { /* SF */
11372 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1;
11373
11374 for (port = 0; port < port_cnt; port++) {
11375 u32 lic = SHMEM_RD(bp,
11376 drv_lic_key[port].max_fcoe_conn) ^
11377 FW_ENCODE_32BIT_PATTERN;
11378 if (lic)
11379 count++;
11380 }
11381 }
11382
11383 return count;
11384 }
11385
11386 static void bnx2x_get_fcoe_info(struct bnx2x *bp)
11387 {
11388 int port = BP_PORT(bp);
11389 int func = BP_ABS_FUNC(bp);
11390 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11391 drv_lic_key[port].max_fcoe_conn);
11392 u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp);
11393
11394 if (!CNIC_SUPPORT(bp)) {
11395 bp->flags |= NO_FCOE_FLAG;
11396 return;
11397 }
11398
11399 /* Get the number of maximum allowed FCoE connections */
11400 bp->cnic_eth_dev.max_fcoe_conn =
11401 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
11402 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
11403
11404 /* Calculate the number of maximum allowed FCoE tasks */
11405 bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE;
11406
11407 /* check if FCoE resources must be shared between different functions */
11408 if (num_fcoe_func)
11409 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func;
11410
11411 /* Read the WWN: */
11412 if (!IS_MF(bp)) {
11413 /* Port info */
11414 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11415 SHMEM_RD(bp,
11416 dev_info.port_hw_config[port].
11417 fcoe_wwn_port_name_upper);
11418 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11419 SHMEM_RD(bp,
11420 dev_info.port_hw_config[port].
11421 fcoe_wwn_port_name_lower);
11422
11423 /* Node info */
11424 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11425 SHMEM_RD(bp,
11426 dev_info.port_hw_config[port].
11427 fcoe_wwn_node_name_upper);
11428 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11429 SHMEM_RD(bp,
11430 dev_info.port_hw_config[port].
11431 fcoe_wwn_node_name_lower);
11432 } else if (!IS_MF_SD(bp)) {
11433 /* Read the WWN info only if the FCoE feature is enabled for
11434 * this function.
11435 */
11436 if (BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp))
11437 bnx2x_get_ext_wwn_info(bp, func);
11438 } else {
11439 if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
11440 bnx2x_get_ext_wwn_info(bp, func);
11441 }
11442
11443 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
11444
11445 /*
11446 * If maximum allowed number of connections is zero -
11447 * disable the feature.
11448 */
11449 if (!bp->cnic_eth_dev.max_fcoe_conn)
11450 bp->flags |= NO_FCOE_FLAG;
11451 }
11452
11453 static void bnx2x_get_cnic_info(struct bnx2x *bp)
11454 {
11455 /*
11456 * iSCSI may be dynamically disabled but reading
11457 * info here we will decrease memory usage by driver
11458 * if the feature is disabled for good
11459 */
11460 bnx2x_get_iscsi_info(bp);
11461 bnx2x_get_fcoe_info(bp);
11462 }
11463
11464 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
11465 {
11466 u32 val, val2;
11467 int func = BP_ABS_FUNC(bp);
11468 int port = BP_PORT(bp);
11469 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
11470 u8 *fip_mac = bp->fip_mac;
11471
11472 if (IS_MF(bp)) {
11473 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
11474 * FCoE MAC then the appropriate feature should be disabled.
11475 * In non SD mode features configuration comes from struct
11476 * func_ext_config.
11477 */
11478 if (!IS_MF_SD(bp)) {
11479 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
11480 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
11481 val2 = MF_CFG_RD(bp, func_ext_config[func].
11482 iscsi_mac_addr_upper);
11483 val = MF_CFG_RD(bp, func_ext_config[func].
11484 iscsi_mac_addr_lower);
11485 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11486 BNX2X_DEV_INFO
11487 ("Read iSCSI MAC: %pM\n", iscsi_mac);
11488 } else {
11489 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11490 }
11491
11492 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
11493 val2 = MF_CFG_RD(bp, func_ext_config[func].
11494 fcoe_mac_addr_upper);
11495 val = MF_CFG_RD(bp, func_ext_config[func].
11496 fcoe_mac_addr_lower);
11497 bnx2x_set_mac_buf(fip_mac, val, val2);
11498 BNX2X_DEV_INFO
11499 ("Read FCoE L2 MAC: %pM\n", fip_mac);
11500 } else {
11501 bp->flags |= NO_FCOE_FLAG;
11502 }
11503
11504 bp->mf_ext_config = cfg;
11505
11506 } else { /* SD MODE */
11507 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
11508 /* use primary mac as iscsi mac */
11509 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
11510
11511 BNX2X_DEV_INFO("SD ISCSI MODE\n");
11512 BNX2X_DEV_INFO
11513 ("Read iSCSI MAC: %pM\n", iscsi_mac);
11514 } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
11515 /* use primary mac as fip mac */
11516 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
11517 BNX2X_DEV_INFO("SD FCoE MODE\n");
11518 BNX2X_DEV_INFO
11519 ("Read FIP MAC: %pM\n", fip_mac);
11520 }
11521 }
11522
11523 /* If this is a storage-only interface, use SAN mac as
11524 * primary MAC. Notice that for SD this is already the case,
11525 * as the SAN mac was copied from the primary MAC.
11526 */
11527 if (IS_MF_FCOE_AFEX(bp))
11528 memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
11529 } else {
11530 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11531 iscsi_mac_upper);
11532 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11533 iscsi_mac_lower);
11534 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11535
11536 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11537 fcoe_fip_mac_upper);
11538 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11539 fcoe_fip_mac_lower);
11540 bnx2x_set_mac_buf(fip_mac, val, val2);
11541 }
11542
11543 /* Disable iSCSI OOO if MAC configuration is invalid. */
11544 if (!is_valid_ether_addr(iscsi_mac)) {
11545 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11546 memset(iscsi_mac, 0, ETH_ALEN);
11547 }
11548
11549 /* Disable FCoE if MAC configuration is invalid. */
11550 if (!is_valid_ether_addr(fip_mac)) {
11551 bp->flags |= NO_FCOE_FLAG;
11552 memset(bp->fip_mac, 0, ETH_ALEN);
11553 }
11554 }
11555
11556 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
11557 {
11558 u32 val, val2;
11559 int func = BP_ABS_FUNC(bp);
11560 int port = BP_PORT(bp);
11561
11562 /* Zero primary MAC configuration */
11563 memset(bp->dev->dev_addr, 0, ETH_ALEN);
11564
11565 if (BP_NOMCP(bp)) {
11566 BNX2X_ERROR("warning: random MAC workaround active\n");
11567 eth_hw_addr_random(bp->dev);
11568 } else if (IS_MF(bp)) {
11569 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11570 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
11571 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
11572 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
11573 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11574
11575 if (CNIC_SUPPORT(bp))
11576 bnx2x_get_cnic_mac_hwinfo(bp);
11577 } else {
11578 /* in SF read MACs from port configuration */
11579 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11580 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11581 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11582
11583 if (CNIC_SUPPORT(bp))
11584 bnx2x_get_cnic_mac_hwinfo(bp);
11585 }
11586
11587 if (!BP_NOMCP(bp)) {
11588 /* Read physical port identifier from shmem */
11589 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11590 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11591 bnx2x_set_mac_buf(bp->phys_port_id, val, val2);
11592 bp->flags |= HAS_PHYS_PORT_ID;
11593 }
11594
11595 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
11596
11597 if (!is_valid_ether_addr(bp->dev->dev_addr))
11598 dev_err(&bp->pdev->dev,
11599 "bad Ethernet MAC address configuration: %pM\n"
11600 "change it manually before bringing up the appropriate network interface\n",
11601 bp->dev->dev_addr);
11602 }
11603
11604 static bool bnx2x_get_dropless_info(struct bnx2x *bp)
11605 {
11606 int tmp;
11607 u32 cfg;
11608
11609 if (IS_VF(bp))
11610 return 0;
11611
11612 if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
11613 /* Take function: tmp = func */
11614 tmp = BP_ABS_FUNC(bp);
11615 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
11616 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
11617 } else {
11618 /* Take port: tmp = port */
11619 tmp = BP_PORT(bp);
11620 cfg = SHMEM_RD(bp,
11621 dev_info.port_hw_config[tmp].generic_features);
11622 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
11623 }
11624 return cfg;
11625 }
11626
11627 static void validate_set_si_mode(struct bnx2x *bp)
11628 {
11629 u8 func = BP_ABS_FUNC(bp);
11630 u32 val;
11631
11632 val = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11633
11634 /* check for legal mac (upper bytes) */
11635 if (val != 0xffff) {
11636 bp->mf_mode = MULTI_FUNCTION_SI;
11637 bp->mf_config[BP_VN(bp)] =
11638 MF_CFG_RD(bp, func_mf_config[func].config);
11639 } else
11640 BNX2X_DEV_INFO("illegal MAC address for SI\n");
11641 }
11642
11643 static int bnx2x_get_hwinfo(struct bnx2x *bp)
11644 {
11645 int /*abs*/func = BP_ABS_FUNC(bp);
11646 int vn;
11647 u32 val = 0, val2 = 0;
11648 int rc = 0;
11649
11650 bnx2x_get_common_hwinfo(bp);
11651
11652 /*
11653 * initialize IGU parameters
11654 */
11655 if (CHIP_IS_E1x(bp)) {
11656 bp->common.int_block = INT_BLOCK_HC;
11657
11658 bp->igu_dsb_id = DEF_SB_IGU_ID;
11659 bp->igu_base_sb = 0;
11660 } else {
11661 bp->common.int_block = INT_BLOCK_IGU;
11662
11663 /* do not allow device reset during IGU info processing */
11664 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11665
11666 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
11667
11668 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11669 int tout = 5000;
11670
11671 BNX2X_DEV_INFO("FORCING Normal Mode\n");
11672
11673 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
11674 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
11675 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
11676
11677 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11678 tout--;
11679 usleep_range(1000, 2000);
11680 }
11681
11682 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11683 dev_err(&bp->pdev->dev,
11684 "FORCING Normal Mode failed!!!\n");
11685 bnx2x_release_hw_lock(bp,
11686 HW_LOCK_RESOURCE_RESET);
11687 return -EPERM;
11688 }
11689 }
11690
11691 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11692 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
11693 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
11694 } else
11695 BNX2X_DEV_INFO("IGU Normal Mode\n");
11696
11697 rc = bnx2x_get_igu_cam_info(bp);
11698 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11699 if (rc)
11700 return rc;
11701 }
11702
11703 /*
11704 * set base FW non-default (fast path) status block id, this value is
11705 * used to initialize the fw_sb_id saved on the fp/queue structure to
11706 * determine the id used by the FW.
11707 */
11708 if (CHIP_IS_E1x(bp))
11709 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
11710 else /*
11711 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
11712 * the same queue are indicated on the same IGU SB). So we prefer
11713 * FW and IGU SBs to be the same value.
11714 */
11715 bp->base_fw_ndsb = bp->igu_base_sb;
11716
11717 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
11718 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
11719 bp->igu_sb_cnt, bp->base_fw_ndsb);
11720
11721 /*
11722 * Initialize MF configuration
11723 */
11724
11725 bp->mf_ov = 0;
11726 bp->mf_mode = 0;
11727 bp->mf_sub_mode = 0;
11728 vn = BP_VN(bp);
11729
11730 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
11731 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
11732 bp->common.shmem2_base, SHMEM2_RD(bp, size),
11733 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
11734
11735 if (SHMEM2_HAS(bp, mf_cfg_addr))
11736 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
11737 else
11738 bp->common.mf_cfg_base = bp->common.shmem_base +
11739 offsetof(struct shmem_region, func_mb) +
11740 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
11741 /*
11742 * get mf configuration:
11743 * 1. Existence of MF configuration
11744 * 2. MAC address must be legal (check only upper bytes)
11745 * for Switch-Independent mode;
11746 * OVLAN must be legal for Switch-Dependent mode
11747 * 3. SF_MODE configures specific MF mode
11748 */
11749 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11750 /* get mf configuration */
11751 val = SHMEM_RD(bp,
11752 dev_info.shared_feature_config.config);
11753 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
11754
11755 switch (val) {
11756 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
11757 validate_set_si_mode(bp);
11758 break;
11759 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
11760 if ((!CHIP_IS_E1x(bp)) &&
11761 (MF_CFG_RD(bp, func_mf_config[func].
11762 mac_upper) != 0xffff) &&
11763 (SHMEM2_HAS(bp,
11764 afex_driver_support))) {
11765 bp->mf_mode = MULTI_FUNCTION_AFEX;
11766 bp->mf_config[vn] = MF_CFG_RD(bp,
11767 func_mf_config[func].config);
11768 } else {
11769 BNX2X_DEV_INFO("can not configure afex mode\n");
11770 }
11771 break;
11772 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
11773 /* get OV configuration */
11774 val = MF_CFG_RD(bp,
11775 func_mf_config[FUNC_0].e1hov_tag);
11776 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
11777
11778 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11779 bp->mf_mode = MULTI_FUNCTION_SD;
11780 bp->mf_config[vn] = MF_CFG_RD(bp,
11781 func_mf_config[func].config);
11782 } else
11783 BNX2X_DEV_INFO("illegal OV for SD\n");
11784 break;
11785 case SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE:
11786 bp->mf_mode = MULTI_FUNCTION_SD;
11787 bp->mf_sub_mode = SUB_MF_MODE_UFP;
11788 bp->mf_config[vn] =
11789 MF_CFG_RD(bp,
11790 func_mf_config[func].config);
11791 break;
11792 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
11793 bp->mf_config[vn] = 0;
11794 break;
11795 case SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE:
11796 val2 = SHMEM_RD(bp,
11797 dev_info.shared_hw_config.config_3);
11798 val2 &= SHARED_HW_CFG_EXTENDED_MF_MODE_MASK;
11799 switch (val2) {
11800 case SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5:
11801 validate_set_si_mode(bp);
11802 bp->mf_sub_mode =
11803 SUB_MF_MODE_NPAR1_DOT_5;
11804 break;
11805 default:
11806 /* Unknown configuration */
11807 bp->mf_config[vn] = 0;
11808 BNX2X_DEV_INFO("unknown extended MF mode 0x%x\n",
11809 val);
11810 }
11811 break;
11812 default:
11813 /* Unknown configuration: reset mf_config */
11814 bp->mf_config[vn] = 0;
11815 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
11816 }
11817 }
11818
11819 BNX2X_DEV_INFO("%s function mode\n",
11820 IS_MF(bp) ? "multi" : "single");
11821
11822 switch (bp->mf_mode) {
11823 case MULTI_FUNCTION_SD:
11824 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
11825 FUNC_MF_CFG_E1HOV_TAG_MASK;
11826 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11827 bp->mf_ov = val;
11828 bp->path_has_ovlan = true;
11829
11830 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
11831 func, bp->mf_ov, bp->mf_ov);
11832 } else if (bp->mf_sub_mode == SUB_MF_MODE_UFP) {
11833 dev_err(&bp->pdev->dev,
11834 "Unexpected - no valid MF OV for func %d in UFP mode\n",
11835 func);
11836 bp->path_has_ovlan = true;
11837 } else {
11838 dev_err(&bp->pdev->dev,
11839 "No valid MF OV for func %d, aborting\n",
11840 func);
11841 return -EPERM;
11842 }
11843 break;
11844 case MULTI_FUNCTION_AFEX:
11845 BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
11846 break;
11847 case MULTI_FUNCTION_SI:
11848 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
11849 func);
11850 break;
11851 default:
11852 if (vn) {
11853 dev_err(&bp->pdev->dev,
11854 "VN %d is in a single function mode, aborting\n",
11855 vn);
11856 return -EPERM;
11857 }
11858 break;
11859 }
11860
11861 /* check if other port on the path needs ovlan:
11862 * Since MF configuration is shared between ports
11863 * Possible mixed modes are only
11864 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
11865 */
11866 if (CHIP_MODE_IS_4_PORT(bp) &&
11867 !bp->path_has_ovlan &&
11868 !IS_MF(bp) &&
11869 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11870 u8 other_port = !BP_PORT(bp);
11871 u8 other_func = BP_PATH(bp) + 2*other_port;
11872 val = MF_CFG_RD(bp,
11873 func_mf_config[other_func].e1hov_tag);
11874 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
11875 bp->path_has_ovlan = true;
11876 }
11877 }
11878
11879 /* adjust igu_sb_cnt to MF for E1H */
11880 if (CHIP_IS_E1H(bp) && IS_MF(bp))
11881 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT);
11882
11883 /* port info */
11884 bnx2x_get_port_hwinfo(bp);
11885
11886 /* Get MAC addresses */
11887 bnx2x_get_mac_hwinfo(bp);
11888
11889 bnx2x_get_cnic_info(bp);
11890
11891 return rc;
11892 }
11893
11894 static void bnx2x_read_fwinfo(struct bnx2x *bp)
11895 {
11896 int cnt, i, block_end, rodi;
11897 char vpd_start[BNX2X_VPD_LEN+1];
11898 char str_id_reg[VENDOR_ID_LEN+1];
11899 char str_id_cap[VENDOR_ID_LEN+1];
11900 char *vpd_data;
11901 char *vpd_extended_data = NULL;
11902 u8 len;
11903
11904 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
11905 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
11906
11907 if (cnt < BNX2X_VPD_LEN)
11908 goto out_not_found;
11909
11910 /* VPD RO tag should be first tag after identifier string, hence
11911 * we should be able to find it in first BNX2X_VPD_LEN chars
11912 */
11913 i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
11914 PCI_VPD_LRDT_RO_DATA);
11915 if (i < 0)
11916 goto out_not_found;
11917
11918 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
11919 pci_vpd_lrdt_size(&vpd_start[i]);
11920
11921 i += PCI_VPD_LRDT_TAG_SIZE;
11922
11923 if (block_end > BNX2X_VPD_LEN) {
11924 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
11925 if (vpd_extended_data == NULL)
11926 goto out_not_found;
11927
11928 /* read rest of vpd image into vpd_extended_data */
11929 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
11930 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
11931 block_end - BNX2X_VPD_LEN,
11932 vpd_extended_data + BNX2X_VPD_LEN);
11933 if (cnt < (block_end - BNX2X_VPD_LEN))
11934 goto out_not_found;
11935 vpd_data = vpd_extended_data;
11936 } else
11937 vpd_data = vpd_start;
11938
11939 /* now vpd_data holds full vpd content in both cases */
11940
11941 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11942 PCI_VPD_RO_KEYWORD_MFR_ID);
11943 if (rodi < 0)
11944 goto out_not_found;
11945
11946 len = pci_vpd_info_field_size(&vpd_data[rodi]);
11947
11948 if (len != VENDOR_ID_LEN)
11949 goto out_not_found;
11950
11951 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11952
11953 /* vendor specific info */
11954 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
11955 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
11956 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
11957 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
11958
11959 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11960 PCI_VPD_RO_KEYWORD_VENDOR0);
11961 if (rodi >= 0) {
11962 len = pci_vpd_info_field_size(&vpd_data[rodi]);
11963
11964 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11965
11966 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
11967 memcpy(bp->fw_ver, &vpd_data[rodi], len);
11968 bp->fw_ver[len] = ' ';
11969 }
11970 }
11971 kfree(vpd_extended_data);
11972 return;
11973 }
11974 out_not_found:
11975 kfree(vpd_extended_data);
11976 return;
11977 }
11978
11979 static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
11980 {
11981 u32 flags = 0;
11982
11983 if (CHIP_REV_IS_FPGA(bp))
11984 SET_FLAGS(flags, MODE_FPGA);
11985 else if (CHIP_REV_IS_EMUL(bp))
11986 SET_FLAGS(flags, MODE_EMUL);
11987 else
11988 SET_FLAGS(flags, MODE_ASIC);
11989
11990 if (CHIP_MODE_IS_4_PORT(bp))
11991 SET_FLAGS(flags, MODE_PORT4);
11992 else
11993 SET_FLAGS(flags, MODE_PORT2);
11994
11995 if (CHIP_IS_E2(bp))
11996 SET_FLAGS(flags, MODE_E2);
11997 else if (CHIP_IS_E3(bp)) {
11998 SET_FLAGS(flags, MODE_E3);
11999 if (CHIP_REV(bp) == CHIP_REV_Ax)
12000 SET_FLAGS(flags, MODE_E3_A0);
12001 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
12002 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
12003 }
12004
12005 if (IS_MF(bp)) {
12006 SET_FLAGS(flags, MODE_MF);
12007 switch (bp->mf_mode) {
12008 case MULTI_FUNCTION_SD:
12009 SET_FLAGS(flags, MODE_MF_SD);
12010 break;
12011 case MULTI_FUNCTION_SI:
12012 SET_FLAGS(flags, MODE_MF_SI);
12013 break;
12014 case MULTI_FUNCTION_AFEX:
12015 SET_FLAGS(flags, MODE_MF_AFEX);
12016 break;
12017 }
12018 } else
12019 SET_FLAGS(flags, MODE_SF);
12020
12021 #if defined(__LITTLE_ENDIAN)
12022 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
12023 #else /*(__BIG_ENDIAN)*/
12024 SET_FLAGS(flags, MODE_BIG_ENDIAN);
12025 #endif
12026 INIT_MODE_FLAGS(bp) = flags;
12027 }
12028
12029 static int bnx2x_init_bp(struct bnx2x *bp)
12030 {
12031 int func;
12032 int rc;
12033
12034 mutex_init(&bp->port.phy_mutex);
12035 mutex_init(&bp->fw_mb_mutex);
12036 mutex_init(&bp->drv_info_mutex);
12037 bp->drv_info_mng_owner = false;
12038 spin_lock_init(&bp->stats_lock);
12039 sema_init(&bp->stats_sema, 1);
12040
12041 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
12042 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
12043 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
12044 INIT_DELAYED_WORK(&bp->iov_task, bnx2x_iov_task);
12045 if (IS_PF(bp)) {
12046 rc = bnx2x_get_hwinfo(bp);
12047 if (rc)
12048 return rc;
12049 } else {
12050 eth_zero_addr(bp->dev->dev_addr);
12051 }
12052
12053 bnx2x_set_modes_bitmap(bp);
12054
12055 rc = bnx2x_alloc_mem_bp(bp);
12056 if (rc)
12057 return rc;
12058
12059 bnx2x_read_fwinfo(bp);
12060
12061 func = BP_FUNC(bp);
12062
12063 /* need to reset chip if undi was active */
12064 if (IS_PF(bp) && !BP_NOMCP(bp)) {
12065 /* init fw_seq */
12066 bp->fw_seq =
12067 SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
12068 DRV_MSG_SEQ_NUMBER_MASK;
12069 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
12070
12071 rc = bnx2x_prev_unload(bp);
12072 if (rc) {
12073 bnx2x_free_mem_bp(bp);
12074 return rc;
12075 }
12076 }
12077
12078 if (CHIP_REV_IS_FPGA(bp))
12079 dev_err(&bp->pdev->dev, "FPGA detected\n");
12080
12081 if (BP_NOMCP(bp) && (func == 0))
12082 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
12083
12084 bp->disable_tpa = disable_tpa;
12085 bp->disable_tpa |= !!IS_MF_STORAGE_ONLY(bp);
12086 /* Reduce memory usage in kdump environment by disabling TPA */
12087 bp->disable_tpa |= is_kdump_kernel();
12088
12089 /* Set TPA flags */
12090 if (bp->disable_tpa) {
12091 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
12092 bp->dev->features &= ~NETIF_F_LRO;
12093 } else {
12094 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
12095 bp->dev->features |= NETIF_F_LRO;
12096 }
12097
12098 if (CHIP_IS_E1(bp))
12099 bp->dropless_fc = 0;
12100 else
12101 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
12102
12103 bp->mrrs = mrrs;
12104
12105 bp->tx_ring_size = IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL;
12106 if (IS_VF(bp))
12107 bp->rx_ring_size = MAX_RX_AVAIL;
12108
12109 /* make sure that the numbers are in the right granularity */
12110 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
12111 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
12112
12113 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
12114
12115 init_timer(&bp->timer);
12116 bp->timer.expires = jiffies + bp->current_interval;
12117 bp->timer.data = (unsigned long) bp;
12118 bp->timer.function = bnx2x_timer;
12119
12120 if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
12121 SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
12122 SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
12123 SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
12124 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
12125 bnx2x_dcbx_init_params(bp);
12126 } else {
12127 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
12128 }
12129
12130 if (CHIP_IS_E1x(bp))
12131 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
12132 else
12133 bp->cnic_base_cl_id = FP_SB_MAX_E2;
12134
12135 /* multiple tx priority */
12136 if (IS_VF(bp))
12137 bp->max_cos = 1;
12138 else if (CHIP_IS_E1x(bp))
12139 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
12140 else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
12141 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
12142 else if (CHIP_IS_E3B0(bp))
12143 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
12144 else
12145 BNX2X_ERR("unknown chip %x revision %x\n",
12146 CHIP_NUM(bp), CHIP_REV(bp));
12147 BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
12148
12149 /* We need at least one default status block for slow-path events,
12150 * second status block for the L2 queue, and a third status block for
12151 * CNIC if supported.
12152 */
12153 if (IS_VF(bp))
12154 bp->min_msix_vec_cnt = 1;
12155 else if (CNIC_SUPPORT(bp))
12156 bp->min_msix_vec_cnt = 3;
12157 else /* PF w/o cnic */
12158 bp->min_msix_vec_cnt = 2;
12159 BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
12160
12161 bp->dump_preset_idx = 1;
12162
12163 if (CHIP_IS_E3B0(bp))
12164 bp->flags |= PTP_SUPPORTED;
12165
12166 return rc;
12167 }
12168
12169 /****************************************************************************
12170 * General service functions
12171 ****************************************************************************/
12172
12173 /*
12174 * net_device service functions
12175 */
12176
12177 /* called with rtnl_lock */
12178 static int bnx2x_open(struct net_device *dev)
12179 {
12180 struct bnx2x *bp = netdev_priv(dev);
12181 int rc;
12182
12183 bp->stats_init = true;
12184
12185 netif_carrier_off(dev);
12186
12187 bnx2x_set_power_state(bp, PCI_D0);
12188
12189 /* If parity had happen during the unload, then attentions
12190 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
12191 * want the first function loaded on the current engine to
12192 * complete the recovery.
12193 * Parity recovery is only relevant for PF driver.
12194 */
12195 if (IS_PF(bp)) {
12196 int other_engine = BP_PATH(bp) ? 0 : 1;
12197 bool other_load_status, load_status;
12198 bool global = false;
12199
12200 other_load_status = bnx2x_get_load_status(bp, other_engine);
12201 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
12202 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
12203 bnx2x_chk_parity_attn(bp, &global, true)) {
12204 do {
12205 /* If there are attentions and they are in a
12206 * global blocks, set the GLOBAL_RESET bit
12207 * regardless whether it will be this function
12208 * that will complete the recovery or not.
12209 */
12210 if (global)
12211 bnx2x_set_reset_global(bp);
12212
12213 /* Only the first function on the current
12214 * engine should try to recover in open. In case
12215 * of attentions in global blocks only the first
12216 * in the chip should try to recover.
12217 */
12218 if ((!load_status &&
12219 (!global || !other_load_status)) &&
12220 bnx2x_trylock_leader_lock(bp) &&
12221 !bnx2x_leader_reset(bp)) {
12222 netdev_info(bp->dev,
12223 "Recovered in open\n");
12224 break;
12225 }
12226
12227 /* recovery has failed... */
12228 bnx2x_set_power_state(bp, PCI_D3hot);
12229 bp->recovery_state = BNX2X_RECOVERY_FAILED;
12230
12231 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
12232 "If you still see this message after a few retries then power cycle is required.\n");
12233
12234 return -EAGAIN;
12235 } while (0);
12236 }
12237 }
12238
12239 bp->recovery_state = BNX2X_RECOVERY_DONE;
12240 rc = bnx2x_nic_load(bp, LOAD_OPEN);
12241 if (rc)
12242 return rc;
12243 return 0;
12244 }
12245
12246 /* called with rtnl_lock */
12247 static int bnx2x_close(struct net_device *dev)
12248 {
12249 struct bnx2x *bp = netdev_priv(dev);
12250
12251 /* Unload the driver, release IRQs */
12252 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
12253
12254 return 0;
12255 }
12256
12257 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
12258 struct bnx2x_mcast_ramrod_params *p)
12259 {
12260 int mc_count = netdev_mc_count(bp->dev);
12261 struct bnx2x_mcast_list_elem *mc_mac =
12262 kcalloc(mc_count, sizeof(*mc_mac), GFP_ATOMIC);
12263 struct netdev_hw_addr *ha;
12264
12265 if (!mc_mac)
12266 return -ENOMEM;
12267
12268 INIT_LIST_HEAD(&p->mcast_list);
12269
12270 netdev_for_each_mc_addr(ha, bp->dev) {
12271 mc_mac->mac = bnx2x_mc_addr(ha);
12272 list_add_tail(&mc_mac->link, &p->mcast_list);
12273 mc_mac++;
12274 }
12275
12276 p->mcast_list_len = mc_count;
12277
12278 return 0;
12279 }
12280
12281 static void bnx2x_free_mcast_macs_list(
12282 struct bnx2x_mcast_ramrod_params *p)
12283 {
12284 struct bnx2x_mcast_list_elem *mc_mac =
12285 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
12286 link);
12287
12288 WARN_ON(!mc_mac);
12289 kfree(mc_mac);
12290 }
12291
12292 /**
12293 * bnx2x_set_uc_list - configure a new unicast MACs list.
12294 *
12295 * @bp: driver handle
12296 *
12297 * We will use zero (0) as a MAC type for these MACs.
12298 */
12299 static int bnx2x_set_uc_list(struct bnx2x *bp)
12300 {
12301 int rc;
12302 struct net_device *dev = bp->dev;
12303 struct netdev_hw_addr *ha;
12304 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
12305 unsigned long ramrod_flags = 0;
12306
12307 /* First schedule a cleanup up of old configuration */
12308 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
12309 if (rc < 0) {
12310 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
12311 return rc;
12312 }
12313
12314 netdev_for_each_uc_addr(ha, dev) {
12315 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
12316 BNX2X_UC_LIST_MAC, &ramrod_flags);
12317 if (rc == -EEXIST) {
12318 DP(BNX2X_MSG_SP,
12319 "Failed to schedule ADD operations: %d\n", rc);
12320 /* do not treat adding same MAC as error */
12321 rc = 0;
12322
12323 } else if (rc < 0) {
12324
12325 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
12326 rc);
12327 return rc;
12328 }
12329 }
12330
12331 /* Execute the pending commands */
12332 __set_bit(RAMROD_CONT, &ramrod_flags);
12333 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
12334 BNX2X_UC_LIST_MAC, &ramrod_flags);
12335 }
12336
12337 static int bnx2x_set_mc_list(struct bnx2x *bp)
12338 {
12339 struct net_device *dev = bp->dev;
12340 struct bnx2x_mcast_ramrod_params rparam = {NULL};
12341 int rc = 0;
12342
12343 rparam.mcast_obj = &bp->mcast_obj;
12344
12345 /* first, clear all configured multicast MACs */
12346 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
12347 if (rc < 0) {
12348 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
12349 return rc;
12350 }
12351
12352 /* then, configure a new MACs list */
12353 if (netdev_mc_count(dev)) {
12354 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
12355 if (rc) {
12356 BNX2X_ERR("Failed to create multicast MACs list: %d\n",
12357 rc);
12358 return rc;
12359 }
12360
12361 /* Now add the new MACs */
12362 rc = bnx2x_config_mcast(bp, &rparam,
12363 BNX2X_MCAST_CMD_ADD);
12364 if (rc < 0)
12365 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
12366 rc);
12367
12368 bnx2x_free_mcast_macs_list(&rparam);
12369 }
12370
12371 return rc;
12372 }
12373
12374 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
12375 static void bnx2x_set_rx_mode(struct net_device *dev)
12376 {
12377 struct bnx2x *bp = netdev_priv(dev);
12378
12379 if (bp->state != BNX2X_STATE_OPEN) {
12380 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
12381 return;
12382 } else {
12383 /* Schedule an SP task to handle rest of change */
12384 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_RX_MODE,
12385 NETIF_MSG_IFUP);
12386 }
12387 }
12388
12389 void bnx2x_set_rx_mode_inner(struct bnx2x *bp)
12390 {
12391 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
12392
12393 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
12394
12395 netif_addr_lock_bh(bp->dev);
12396
12397 if (bp->dev->flags & IFF_PROMISC) {
12398 rx_mode = BNX2X_RX_MODE_PROMISC;
12399 } else if ((bp->dev->flags & IFF_ALLMULTI) ||
12400 ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) &&
12401 CHIP_IS_E1(bp))) {
12402 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12403 } else {
12404 if (IS_PF(bp)) {
12405 /* some multicasts */
12406 if (bnx2x_set_mc_list(bp) < 0)
12407 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12408
12409 /* release bh lock, as bnx2x_set_uc_list might sleep */
12410 netif_addr_unlock_bh(bp->dev);
12411 if (bnx2x_set_uc_list(bp) < 0)
12412 rx_mode = BNX2X_RX_MODE_PROMISC;
12413 netif_addr_lock_bh(bp->dev);
12414 } else {
12415 /* configuring mcast to a vf involves sleeping (when we
12416 * wait for the pf's response).
12417 */
12418 bnx2x_schedule_sp_rtnl(bp,
12419 BNX2X_SP_RTNL_VFPF_MCAST, 0);
12420 }
12421 }
12422
12423 bp->rx_mode = rx_mode;
12424 /* handle ISCSI SD mode */
12425 if (IS_MF_ISCSI_ONLY(bp))
12426 bp->rx_mode = BNX2X_RX_MODE_NONE;
12427
12428 /* Schedule the rx_mode command */
12429 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
12430 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
12431 netif_addr_unlock_bh(bp->dev);
12432 return;
12433 }
12434
12435 if (IS_PF(bp)) {
12436 bnx2x_set_storm_rx_mode(bp);
12437 netif_addr_unlock_bh(bp->dev);
12438 } else {
12439 /* VF will need to request the PF to make this change, and so
12440 * the VF needs to release the bottom-half lock prior to the
12441 * request (as it will likely require sleep on the VF side)
12442 */
12443 netif_addr_unlock_bh(bp->dev);
12444 bnx2x_vfpf_storm_rx_mode(bp);
12445 }
12446 }
12447
12448 /* called with rtnl_lock */
12449 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
12450 int devad, u16 addr)
12451 {
12452 struct bnx2x *bp = netdev_priv(netdev);
12453 u16 value;
12454 int rc;
12455
12456 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
12457 prtad, devad, addr);
12458
12459 /* The HW expects different devad if CL22 is used */
12460 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12461
12462 bnx2x_acquire_phy_lock(bp);
12463 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
12464 bnx2x_release_phy_lock(bp);
12465 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
12466
12467 if (!rc)
12468 rc = value;
12469 return rc;
12470 }
12471
12472 /* called with rtnl_lock */
12473 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
12474 u16 addr, u16 value)
12475 {
12476 struct bnx2x *bp = netdev_priv(netdev);
12477 int rc;
12478
12479 DP(NETIF_MSG_LINK,
12480 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
12481 prtad, devad, addr, value);
12482
12483 /* The HW expects different devad if CL22 is used */
12484 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12485
12486 bnx2x_acquire_phy_lock(bp);
12487 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
12488 bnx2x_release_phy_lock(bp);
12489 return rc;
12490 }
12491
12492 /* called with rtnl_lock */
12493 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12494 {
12495 struct bnx2x *bp = netdev_priv(dev);
12496 struct mii_ioctl_data *mdio = if_mii(ifr);
12497
12498 if (!netif_running(dev))
12499 return -EAGAIN;
12500
12501 switch (cmd) {
12502 case SIOCSHWTSTAMP:
12503 return bnx2x_hwtstamp_ioctl(bp, ifr);
12504 default:
12505 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
12506 mdio->phy_id, mdio->reg_num, mdio->val_in);
12507 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
12508 }
12509 }
12510
12511 #ifdef CONFIG_NET_POLL_CONTROLLER
12512 static void poll_bnx2x(struct net_device *dev)
12513 {
12514 struct bnx2x *bp = netdev_priv(dev);
12515 int i;
12516
12517 for_each_eth_queue(bp, i) {
12518 struct bnx2x_fastpath *fp = &bp->fp[i];
12519 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
12520 }
12521 }
12522 #endif
12523
12524 static int bnx2x_validate_addr(struct net_device *dev)
12525 {
12526 struct bnx2x *bp = netdev_priv(dev);
12527
12528 /* query the bulletin board for mac address configured by the PF */
12529 if (IS_VF(bp))
12530 bnx2x_sample_bulletin(bp);
12531
12532 if (!is_valid_ether_addr(dev->dev_addr)) {
12533 BNX2X_ERR("Non-valid Ethernet address\n");
12534 return -EADDRNOTAVAIL;
12535 }
12536 return 0;
12537 }
12538
12539 static int bnx2x_get_phys_port_id(struct net_device *netdev,
12540 struct netdev_phys_item_id *ppid)
12541 {
12542 struct bnx2x *bp = netdev_priv(netdev);
12543
12544 if (!(bp->flags & HAS_PHYS_PORT_ID))
12545 return -EOPNOTSUPP;
12546
12547 ppid->id_len = sizeof(bp->phys_port_id);
12548 memcpy(ppid->id, bp->phys_port_id, ppid->id_len);
12549
12550 return 0;
12551 }
12552
12553 static const struct net_device_ops bnx2x_netdev_ops = {
12554 .ndo_open = bnx2x_open,
12555 .ndo_stop = bnx2x_close,
12556 .ndo_start_xmit = bnx2x_start_xmit,
12557 .ndo_select_queue = bnx2x_select_queue,
12558 .ndo_set_rx_mode = bnx2x_set_rx_mode,
12559 .ndo_set_mac_address = bnx2x_change_mac_addr,
12560 .ndo_validate_addr = bnx2x_validate_addr,
12561 .ndo_do_ioctl = bnx2x_ioctl,
12562 .ndo_change_mtu = bnx2x_change_mtu,
12563 .ndo_fix_features = bnx2x_fix_features,
12564 .ndo_set_features = bnx2x_set_features,
12565 .ndo_tx_timeout = bnx2x_tx_timeout,
12566 #ifdef CONFIG_NET_POLL_CONTROLLER
12567 .ndo_poll_controller = poll_bnx2x,
12568 #endif
12569 .ndo_setup_tc = bnx2x_setup_tc,
12570 #ifdef CONFIG_BNX2X_SRIOV
12571 .ndo_set_vf_mac = bnx2x_set_vf_mac,
12572 .ndo_set_vf_vlan = bnx2x_set_vf_vlan,
12573 .ndo_get_vf_config = bnx2x_get_vf_config,
12574 #endif
12575 #ifdef NETDEV_FCOE_WWNN
12576 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
12577 #endif
12578
12579 #ifdef CONFIG_NET_RX_BUSY_POLL
12580 .ndo_busy_poll = bnx2x_low_latency_recv,
12581 #endif
12582 .ndo_get_phys_port_id = bnx2x_get_phys_port_id,
12583 .ndo_set_vf_link_state = bnx2x_set_vf_link_state,
12584 };
12585
12586 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
12587 {
12588 struct device *dev = &bp->pdev->dev;
12589
12590 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)) != 0 &&
12591 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)) != 0) {
12592 dev_err(dev, "System does not support DMA, aborting\n");
12593 return -EIO;
12594 }
12595
12596 return 0;
12597 }
12598
12599 static void bnx2x_disable_pcie_error_reporting(struct bnx2x *bp)
12600 {
12601 if (bp->flags & AER_ENABLED) {
12602 pci_disable_pcie_error_reporting(bp->pdev);
12603 bp->flags &= ~AER_ENABLED;
12604 }
12605 }
12606
12607 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
12608 struct net_device *dev, unsigned long board_type)
12609 {
12610 int rc;
12611 u32 pci_cfg_dword;
12612 bool chip_is_e1x = (board_type == BCM57710 ||
12613 board_type == BCM57711 ||
12614 board_type == BCM57711E);
12615
12616 SET_NETDEV_DEV(dev, &pdev->dev);
12617
12618 bp->dev = dev;
12619 bp->pdev = pdev;
12620
12621 rc = pci_enable_device(pdev);
12622 if (rc) {
12623 dev_err(&bp->pdev->dev,
12624 "Cannot enable PCI device, aborting\n");
12625 goto err_out;
12626 }
12627
12628 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
12629 dev_err(&bp->pdev->dev,
12630 "Cannot find PCI device base address, aborting\n");
12631 rc = -ENODEV;
12632 goto err_out_disable;
12633 }
12634
12635 if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
12636 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
12637 rc = -ENODEV;
12638 goto err_out_disable;
12639 }
12640
12641 pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
12642 if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
12643 PCICFG_REVESION_ID_ERROR_VAL) {
12644 pr_err("PCI device error, probably due to fan failure, aborting\n");
12645 rc = -ENODEV;
12646 goto err_out_disable;
12647 }
12648
12649 if (atomic_read(&pdev->enable_cnt) == 1) {
12650 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
12651 if (rc) {
12652 dev_err(&bp->pdev->dev,
12653 "Cannot obtain PCI resources, aborting\n");
12654 goto err_out_disable;
12655 }
12656
12657 pci_set_master(pdev);
12658 pci_save_state(pdev);
12659 }
12660
12661 if (IS_PF(bp)) {
12662 if (!pdev->pm_cap) {
12663 dev_err(&bp->pdev->dev,
12664 "Cannot find power management capability, aborting\n");
12665 rc = -EIO;
12666 goto err_out_release;
12667 }
12668 }
12669
12670 if (!pci_is_pcie(pdev)) {
12671 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
12672 rc = -EIO;
12673 goto err_out_release;
12674 }
12675
12676 rc = bnx2x_set_coherency_mask(bp);
12677 if (rc)
12678 goto err_out_release;
12679
12680 dev->mem_start = pci_resource_start(pdev, 0);
12681 dev->base_addr = dev->mem_start;
12682 dev->mem_end = pci_resource_end(pdev, 0);
12683
12684 dev->irq = pdev->irq;
12685
12686 bp->regview = pci_ioremap_bar(pdev, 0);
12687 if (!bp->regview) {
12688 dev_err(&bp->pdev->dev,
12689 "Cannot map register space, aborting\n");
12690 rc = -ENOMEM;
12691 goto err_out_release;
12692 }
12693
12694 /* In E1/E1H use pci device function given by kernel.
12695 * In E2/E3 read physical function from ME register since these chips
12696 * support Physical Device Assignment where kernel BDF maybe arbitrary
12697 * (depending on hypervisor).
12698 */
12699 if (chip_is_e1x) {
12700 bp->pf_num = PCI_FUNC(pdev->devfn);
12701 } else {
12702 /* chip is E2/3*/
12703 pci_read_config_dword(bp->pdev,
12704 PCICFG_ME_REGISTER, &pci_cfg_dword);
12705 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
12706 ME_REG_ABS_PF_NUM_SHIFT);
12707 }
12708 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
12709
12710 /* clean indirect addresses */
12711 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
12712 PCICFG_VENDOR_ID_OFFSET);
12713
12714 /* AER (Advanced Error reporting) configuration */
12715 rc = pci_enable_pcie_error_reporting(pdev);
12716 if (!rc)
12717 bp->flags |= AER_ENABLED;
12718 else
12719 BNX2X_DEV_INFO("Failed To configure PCIe AER [%d]\n", rc);
12720
12721 /*
12722 * Clean the following indirect addresses for all functions since it
12723 * is not used by the driver.
12724 */
12725 if (IS_PF(bp)) {
12726 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
12727 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
12728 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
12729 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
12730
12731 if (chip_is_e1x) {
12732 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
12733 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
12734 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
12735 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
12736 }
12737
12738 /* Enable internal target-read (in case we are probed after PF
12739 * FLR). Must be done prior to any BAR read access. Only for
12740 * 57712 and up
12741 */
12742 if (!chip_is_e1x)
12743 REG_WR(bp,
12744 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
12745 }
12746
12747 dev->watchdog_timeo = TX_TIMEOUT;
12748
12749 dev->netdev_ops = &bnx2x_netdev_ops;
12750 bnx2x_set_ethtool_ops(bp, dev);
12751
12752 dev->priv_flags |= IFF_UNICAST_FLT;
12753
12754 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12755 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12756 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
12757 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX;
12758 if (!CHIP_IS_E1x(bp)) {
12759 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL |
12760 NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT;
12761 dev->hw_enc_features =
12762 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
12763 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12764 NETIF_F_GSO_IPIP |
12765 NETIF_F_GSO_SIT |
12766 NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL;
12767 }
12768
12769 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12770 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
12771
12772 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
12773 dev->features |= NETIF_F_HIGHDMA;
12774
12775 /* Add Loopback capability to the device */
12776 dev->hw_features |= NETIF_F_LOOPBACK;
12777
12778 #ifdef BCM_DCBNL
12779 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
12780 #endif
12781
12782 /* get_port_hwinfo() will set prtad and mmds properly */
12783 bp->mdio.prtad = MDIO_PRTAD_NONE;
12784 bp->mdio.mmds = 0;
12785 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
12786 bp->mdio.dev = dev;
12787 bp->mdio.mdio_read = bnx2x_mdio_read;
12788 bp->mdio.mdio_write = bnx2x_mdio_write;
12789
12790 return 0;
12791
12792 err_out_release:
12793 if (atomic_read(&pdev->enable_cnt) == 1)
12794 pci_release_regions(pdev);
12795
12796 err_out_disable:
12797 pci_disable_device(pdev);
12798
12799 err_out:
12800 return rc;
12801 }
12802
12803 static int bnx2x_check_firmware(struct bnx2x *bp)
12804 {
12805 const struct firmware *firmware = bp->firmware;
12806 struct bnx2x_fw_file_hdr *fw_hdr;
12807 struct bnx2x_fw_file_section *sections;
12808 u32 offset, len, num_ops;
12809 __be16 *ops_offsets;
12810 int i;
12811 const u8 *fw_ver;
12812
12813 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
12814 BNX2X_ERR("Wrong FW size\n");
12815 return -EINVAL;
12816 }
12817
12818 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
12819 sections = (struct bnx2x_fw_file_section *)fw_hdr;
12820
12821 /* Make sure none of the offsets and sizes make us read beyond
12822 * the end of the firmware data */
12823 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
12824 offset = be32_to_cpu(sections[i].offset);
12825 len = be32_to_cpu(sections[i].len);
12826 if (offset + len > firmware->size) {
12827 BNX2X_ERR("Section %d length is out of bounds\n", i);
12828 return -EINVAL;
12829 }
12830 }
12831
12832 /* Likewise for the init_ops offsets */
12833 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
12834 ops_offsets = (__force __be16 *)(firmware->data + offset);
12835 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
12836
12837 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
12838 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
12839 BNX2X_ERR("Section offset %d is out of bounds\n", i);
12840 return -EINVAL;
12841 }
12842 }
12843
12844 /* Check FW version */
12845 offset = be32_to_cpu(fw_hdr->fw_version.offset);
12846 fw_ver = firmware->data + offset;
12847 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
12848 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
12849 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
12850 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
12851 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
12852 fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
12853 BCM_5710_FW_MAJOR_VERSION,
12854 BCM_5710_FW_MINOR_VERSION,
12855 BCM_5710_FW_REVISION_VERSION,
12856 BCM_5710_FW_ENGINEERING_VERSION);
12857 return -EINVAL;
12858 }
12859
12860 return 0;
12861 }
12862
12863 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12864 {
12865 const __be32 *source = (const __be32 *)_source;
12866 u32 *target = (u32 *)_target;
12867 u32 i;
12868
12869 for (i = 0; i < n/4; i++)
12870 target[i] = be32_to_cpu(source[i]);
12871 }
12872
12873 /*
12874 Ops array is stored in the following format:
12875 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
12876 */
12877 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
12878 {
12879 const __be32 *source = (const __be32 *)_source;
12880 struct raw_op *target = (struct raw_op *)_target;
12881 u32 i, j, tmp;
12882
12883 for (i = 0, j = 0; i < n/8; i++, j += 2) {
12884 tmp = be32_to_cpu(source[j]);
12885 target[i].op = (tmp >> 24) & 0xff;
12886 target[i].offset = tmp & 0xffffff;
12887 target[i].raw_data = be32_to_cpu(source[j + 1]);
12888 }
12889 }
12890
12891 /* IRO array is stored in the following format:
12892 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
12893 */
12894 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
12895 {
12896 const __be32 *source = (const __be32 *)_source;
12897 struct iro *target = (struct iro *)_target;
12898 u32 i, j, tmp;
12899
12900 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
12901 target[i].base = be32_to_cpu(source[j]);
12902 j++;
12903 tmp = be32_to_cpu(source[j]);
12904 target[i].m1 = (tmp >> 16) & 0xffff;
12905 target[i].m2 = tmp & 0xffff;
12906 j++;
12907 tmp = be32_to_cpu(source[j]);
12908 target[i].m3 = (tmp >> 16) & 0xffff;
12909 target[i].size = tmp & 0xffff;
12910 j++;
12911 }
12912 }
12913
12914 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12915 {
12916 const __be16 *source = (const __be16 *)_source;
12917 u16 *target = (u16 *)_target;
12918 u32 i;
12919
12920 for (i = 0; i < n/2; i++)
12921 target[i] = be16_to_cpu(source[i]);
12922 }
12923
12924 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
12925 do { \
12926 u32 len = be32_to_cpu(fw_hdr->arr.len); \
12927 bp->arr = kmalloc(len, GFP_KERNEL); \
12928 if (!bp->arr) \
12929 goto lbl; \
12930 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
12931 (u8 *)bp->arr, len); \
12932 } while (0)
12933
12934 static int bnx2x_init_firmware(struct bnx2x *bp)
12935 {
12936 const char *fw_file_name;
12937 struct bnx2x_fw_file_hdr *fw_hdr;
12938 int rc;
12939
12940 if (bp->firmware)
12941 return 0;
12942
12943 if (CHIP_IS_E1(bp))
12944 fw_file_name = FW_FILE_NAME_E1;
12945 else if (CHIP_IS_E1H(bp))
12946 fw_file_name = FW_FILE_NAME_E1H;
12947 else if (!CHIP_IS_E1x(bp))
12948 fw_file_name = FW_FILE_NAME_E2;
12949 else {
12950 BNX2X_ERR("Unsupported chip revision\n");
12951 return -EINVAL;
12952 }
12953 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
12954
12955 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
12956 if (rc) {
12957 BNX2X_ERR("Can't load firmware file %s\n",
12958 fw_file_name);
12959 goto request_firmware_exit;
12960 }
12961
12962 rc = bnx2x_check_firmware(bp);
12963 if (rc) {
12964 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
12965 goto request_firmware_exit;
12966 }
12967
12968 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
12969
12970 /* Initialize the pointers to the init arrays */
12971 /* Blob */
12972 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
12973
12974 /* Opcodes */
12975 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
12976
12977 /* Offsets */
12978 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
12979 be16_to_cpu_n);
12980
12981 /* STORMs firmware */
12982 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12983 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
12984 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
12985 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
12986 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12987 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
12988 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
12989 be32_to_cpu(fw_hdr->usem_pram_data.offset);
12990 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12991 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
12992 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
12993 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
12994 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12995 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
12996 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
12997 be32_to_cpu(fw_hdr->csem_pram_data.offset);
12998 /* IRO */
12999 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
13000
13001 return 0;
13002
13003 iro_alloc_err:
13004 kfree(bp->init_ops_offsets);
13005 init_offsets_alloc_err:
13006 kfree(bp->init_ops);
13007 init_ops_alloc_err:
13008 kfree(bp->init_data);
13009 request_firmware_exit:
13010 release_firmware(bp->firmware);
13011 bp->firmware = NULL;
13012
13013 return rc;
13014 }
13015
13016 static void bnx2x_release_firmware(struct bnx2x *bp)
13017 {
13018 kfree(bp->init_ops_offsets);
13019 kfree(bp->init_ops);
13020 kfree(bp->init_data);
13021 release_firmware(bp->firmware);
13022 bp->firmware = NULL;
13023 }
13024
13025 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
13026 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
13027 .init_hw_cmn = bnx2x_init_hw_common,
13028 .init_hw_port = bnx2x_init_hw_port,
13029 .init_hw_func = bnx2x_init_hw_func,
13030
13031 .reset_hw_cmn = bnx2x_reset_common,
13032 .reset_hw_port = bnx2x_reset_port,
13033 .reset_hw_func = bnx2x_reset_func,
13034
13035 .gunzip_init = bnx2x_gunzip_init,
13036 .gunzip_end = bnx2x_gunzip_end,
13037
13038 .init_fw = bnx2x_init_firmware,
13039 .release_fw = bnx2x_release_firmware,
13040 };
13041
13042 void bnx2x__init_func_obj(struct bnx2x *bp)
13043 {
13044 /* Prepare DMAE related driver resources */
13045 bnx2x_setup_dmae(bp);
13046
13047 bnx2x_init_func_obj(bp, &bp->func_obj,
13048 bnx2x_sp(bp, func_rdata),
13049 bnx2x_sp_mapping(bp, func_rdata),
13050 bnx2x_sp(bp, func_afex_rdata),
13051 bnx2x_sp_mapping(bp, func_afex_rdata),
13052 &bnx2x_func_sp_drv);
13053 }
13054
13055 /* must be called after sriov-enable */
13056 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
13057 {
13058 int cid_count = BNX2X_L2_MAX_CID(bp);
13059
13060 if (IS_SRIOV(bp))
13061 cid_count += BNX2X_VF_CIDS;
13062
13063 if (CNIC_SUPPORT(bp))
13064 cid_count += CNIC_CID_MAX;
13065
13066 return roundup(cid_count, QM_CID_ROUND);
13067 }
13068
13069 /**
13070 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
13071 *
13072 * @dev: pci device
13073 *
13074 */
13075 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt)
13076 {
13077 int index;
13078 u16 control = 0;
13079
13080 /*
13081 * If MSI-X is not supported - return number of SBs needed to support
13082 * one fast path queue: one FP queue + SB for CNIC
13083 */
13084 if (!pdev->msix_cap) {
13085 dev_info(&pdev->dev, "no msix capability found\n");
13086 return 1 + cnic_cnt;
13087 }
13088 dev_info(&pdev->dev, "msix capability found\n");
13089
13090 /*
13091 * The value in the PCI configuration space is the index of the last
13092 * entry, namely one less than the actual size of the table, which is
13093 * exactly what we want to return from this function: number of all SBs
13094 * without the default SB.
13095 * For VFs there is no default SB, then we return (index+1).
13096 */
13097 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &control);
13098
13099 index = control & PCI_MSIX_FLAGS_QSIZE;
13100
13101 return index;
13102 }
13103
13104 static int set_max_cos_est(int chip_id)
13105 {
13106 switch (chip_id) {
13107 case BCM57710:
13108 case BCM57711:
13109 case BCM57711E:
13110 return BNX2X_MULTI_TX_COS_E1X;
13111 case BCM57712:
13112 case BCM57712_MF:
13113 return BNX2X_MULTI_TX_COS_E2_E3A0;
13114 case BCM57800:
13115 case BCM57800_MF:
13116 case BCM57810:
13117 case BCM57810_MF:
13118 case BCM57840_4_10:
13119 case BCM57840_2_20:
13120 case BCM57840_O:
13121 case BCM57840_MFO:
13122 case BCM57840_MF:
13123 case BCM57811:
13124 case BCM57811_MF:
13125 return BNX2X_MULTI_TX_COS_E3B0;
13126 case BCM57712_VF:
13127 case BCM57800_VF:
13128 case BCM57810_VF:
13129 case BCM57840_VF:
13130 case BCM57811_VF:
13131 return 1;
13132 default:
13133 pr_err("Unknown board_type (%d), aborting\n", chip_id);
13134 return -ENODEV;
13135 }
13136 }
13137
13138 static int set_is_vf(int chip_id)
13139 {
13140 switch (chip_id) {
13141 case BCM57712_VF:
13142 case BCM57800_VF:
13143 case BCM57810_VF:
13144 case BCM57840_VF:
13145 case BCM57811_VF:
13146 return true;
13147 default:
13148 return false;
13149 }
13150 }
13151
13152 /* nig_tsgen registers relative address */
13153 #define tsgen_ctrl 0x0
13154 #define tsgen_freecount 0x10
13155 #define tsgen_synctime_t0 0x20
13156 #define tsgen_offset_t0 0x28
13157 #define tsgen_drift_t0 0x30
13158 #define tsgen_synctime_t1 0x58
13159 #define tsgen_offset_t1 0x60
13160 #define tsgen_drift_t1 0x68
13161
13162 /* FW workaround for setting drift */
13163 static int bnx2x_send_update_drift_ramrod(struct bnx2x *bp, int drift_dir,
13164 int best_val, int best_period)
13165 {
13166 struct bnx2x_func_state_params func_params = {NULL};
13167 struct bnx2x_func_set_timesync_params *set_timesync_params =
13168 &func_params.params.set_timesync;
13169
13170 /* Prepare parameters for function state transitions */
13171 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
13172 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
13173
13174 func_params.f_obj = &bp->func_obj;
13175 func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
13176
13177 /* Function parameters */
13178 set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_SET;
13179 set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
13180 set_timesync_params->add_sub_drift_adjust_value =
13181 drift_dir ? TS_ADD_VALUE : TS_SUB_VALUE;
13182 set_timesync_params->drift_adjust_value = best_val;
13183 set_timesync_params->drift_adjust_period = best_period;
13184
13185 return bnx2x_func_state_change(bp, &func_params);
13186 }
13187
13188 static int bnx2x_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
13189 {
13190 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13191 int rc;
13192 int drift_dir = 1;
13193 int val, period, period1, period2, dif, dif1, dif2;
13194 int best_dif = BNX2X_MAX_PHC_DRIFT, best_period = 0, best_val = 0;
13195
13196 DP(BNX2X_MSG_PTP, "PTP adjfreq called, ppb = %d\n", ppb);
13197
13198 if (!netif_running(bp->dev)) {
13199 DP(BNX2X_MSG_PTP,
13200 "PTP adjfreq called while the interface is down\n");
13201 return -EFAULT;
13202 }
13203
13204 if (ppb < 0) {
13205 ppb = -ppb;
13206 drift_dir = 0;
13207 }
13208
13209 if (ppb == 0) {
13210 best_val = 1;
13211 best_period = 0x1FFFFFF;
13212 } else if (ppb >= BNX2X_MAX_PHC_DRIFT) {
13213 best_val = 31;
13214 best_period = 1;
13215 } else {
13216 /* Changed not to allow val = 8, 16, 24 as these values
13217 * are not supported in workaround.
13218 */
13219 for (val = 0; val <= 31; val++) {
13220 if ((val & 0x7) == 0)
13221 continue;
13222 period1 = val * 1000000 / ppb;
13223 period2 = period1 + 1;
13224 if (period1 != 0)
13225 dif1 = ppb - (val * 1000000 / period1);
13226 else
13227 dif1 = BNX2X_MAX_PHC_DRIFT;
13228 if (dif1 < 0)
13229 dif1 = -dif1;
13230 dif2 = ppb - (val * 1000000 / period2);
13231 if (dif2 < 0)
13232 dif2 = -dif2;
13233 dif = (dif1 < dif2) ? dif1 : dif2;
13234 period = (dif1 < dif2) ? period1 : period2;
13235 if (dif < best_dif) {
13236 best_dif = dif;
13237 best_val = val;
13238 best_period = period;
13239 }
13240 }
13241 }
13242
13243 rc = bnx2x_send_update_drift_ramrod(bp, drift_dir, best_val,
13244 best_period);
13245 if (rc) {
13246 BNX2X_ERR("Failed to set drift\n");
13247 return -EFAULT;
13248 }
13249
13250 DP(BNX2X_MSG_PTP, "Configrued val = %d, period = %d\n", best_val,
13251 best_period);
13252
13253 return 0;
13254 }
13255
13256 static int bnx2x_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
13257 {
13258 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13259 u64 now;
13260
13261 DP(BNX2X_MSG_PTP, "PTP adjtime called, delta = %llx\n", delta);
13262
13263 now = timecounter_read(&bp->timecounter);
13264 now += delta;
13265 /* Re-init the timecounter */
13266 timecounter_init(&bp->timecounter, &bp->cyclecounter, now);
13267
13268 return 0;
13269 }
13270
13271 static int bnx2x_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
13272 {
13273 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13274 u64 ns;
13275 u32 remainder;
13276
13277 ns = timecounter_read(&bp->timecounter);
13278
13279 DP(BNX2X_MSG_PTP, "PTP gettime called, ns = %llu\n", ns);
13280
13281 ts->tv_sec = div_u64_rem(ns, 1000000000ULL, &remainder);
13282 ts->tv_nsec = remainder;
13283
13284 return 0;
13285 }
13286
13287 static int bnx2x_ptp_settime(struct ptp_clock_info *ptp,
13288 const struct timespec *ts)
13289 {
13290 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13291 u64 ns;
13292
13293 ns = ts->tv_sec * 1000000000ULL;
13294 ns += ts->tv_nsec;
13295
13296 DP(BNX2X_MSG_PTP, "PTP settime called, ns = %llu\n", ns);
13297
13298 /* Re-init the timecounter */
13299 timecounter_init(&bp->timecounter, &bp->cyclecounter, ns);
13300
13301 return 0;
13302 }
13303
13304 /* Enable (or disable) ancillary features of the phc subsystem */
13305 static int bnx2x_ptp_enable(struct ptp_clock_info *ptp,
13306 struct ptp_clock_request *rq, int on)
13307 {
13308 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13309
13310 BNX2X_ERR("PHC ancillary features are not supported\n");
13311 return -ENOTSUPP;
13312 }
13313
13314 void bnx2x_register_phc(struct bnx2x *bp)
13315 {
13316 /* Fill the ptp_clock_info struct and register PTP clock*/
13317 bp->ptp_clock_info.owner = THIS_MODULE;
13318 snprintf(bp->ptp_clock_info.name, 16, "%s", bp->dev->name);
13319 bp->ptp_clock_info.max_adj = BNX2X_MAX_PHC_DRIFT; /* In PPB */
13320 bp->ptp_clock_info.n_alarm = 0;
13321 bp->ptp_clock_info.n_ext_ts = 0;
13322 bp->ptp_clock_info.n_per_out = 0;
13323 bp->ptp_clock_info.pps = 0;
13324 bp->ptp_clock_info.adjfreq = bnx2x_ptp_adjfreq;
13325 bp->ptp_clock_info.adjtime = bnx2x_ptp_adjtime;
13326 bp->ptp_clock_info.gettime = bnx2x_ptp_gettime;
13327 bp->ptp_clock_info.settime = bnx2x_ptp_settime;
13328 bp->ptp_clock_info.enable = bnx2x_ptp_enable;
13329
13330 bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &bp->pdev->dev);
13331 if (IS_ERR(bp->ptp_clock)) {
13332 bp->ptp_clock = NULL;
13333 BNX2X_ERR("PTP clock registeration failed\n");
13334 }
13335 }
13336
13337 static int bnx2x_init_one(struct pci_dev *pdev,
13338 const struct pci_device_id *ent)
13339 {
13340 struct net_device *dev = NULL;
13341 struct bnx2x *bp;
13342 enum pcie_link_width pcie_width;
13343 enum pci_bus_speed pcie_speed;
13344 int rc, max_non_def_sbs;
13345 int rx_count, tx_count, rss_count, doorbell_size;
13346 int max_cos_est;
13347 bool is_vf;
13348 int cnic_cnt;
13349
13350 /* An estimated maximum supported CoS number according to the chip
13351 * version.
13352 * We will try to roughly estimate the maximum number of CoSes this chip
13353 * may support in order to minimize the memory allocated for Tx
13354 * netdev_queue's. This number will be accurately calculated during the
13355 * initialization of bp->max_cos based on the chip versions AND chip
13356 * revision in the bnx2x_init_bp().
13357 */
13358 max_cos_est = set_max_cos_est(ent->driver_data);
13359 if (max_cos_est < 0)
13360 return max_cos_est;
13361 is_vf = set_is_vf(ent->driver_data);
13362 cnic_cnt = is_vf ? 0 : 1;
13363
13364 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt);
13365
13366 /* add another SB for VF as it has no default SB */
13367 max_non_def_sbs += is_vf ? 1 : 0;
13368
13369 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
13370 rss_count = max_non_def_sbs - cnic_cnt;
13371
13372 if (rss_count < 1)
13373 return -EINVAL;
13374
13375 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
13376 rx_count = rss_count + cnic_cnt;
13377
13378 /* Maximum number of netdev Tx queues:
13379 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
13380 */
13381 tx_count = rss_count * max_cos_est + cnic_cnt;
13382
13383 /* dev zeroed in init_etherdev */
13384 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
13385 if (!dev)
13386 return -ENOMEM;
13387
13388 bp = netdev_priv(dev);
13389
13390 bp->flags = 0;
13391 if (is_vf)
13392 bp->flags |= IS_VF_FLAG;
13393
13394 bp->igu_sb_cnt = max_non_def_sbs;
13395 bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
13396 bp->msg_enable = debug;
13397 bp->cnic_support = cnic_cnt;
13398 bp->cnic_probe = bnx2x_cnic_probe;
13399
13400 pci_set_drvdata(pdev, dev);
13401
13402 rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
13403 if (rc < 0) {
13404 free_netdev(dev);
13405 return rc;
13406 }
13407
13408 BNX2X_DEV_INFO("This is a %s function\n",
13409 IS_PF(bp) ? "physical" : "virtual");
13410 BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
13411 BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
13412 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
13413 tx_count, rx_count);
13414
13415 rc = bnx2x_init_bp(bp);
13416 if (rc)
13417 goto init_one_exit;
13418
13419 /* Map doorbells here as we need the real value of bp->max_cos which
13420 * is initialized in bnx2x_init_bp() to determine the number of
13421 * l2 connections.
13422 */
13423 if (IS_VF(bp)) {
13424 bp->doorbells = bnx2x_vf_doorbells(bp);
13425 rc = bnx2x_vf_pci_alloc(bp);
13426 if (rc)
13427 goto init_one_exit;
13428 } else {
13429 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
13430 if (doorbell_size > pci_resource_len(pdev, 2)) {
13431 dev_err(&bp->pdev->dev,
13432 "Cannot map doorbells, bar size too small, aborting\n");
13433 rc = -ENOMEM;
13434 goto init_one_exit;
13435 }
13436 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
13437 doorbell_size);
13438 }
13439 if (!bp->doorbells) {
13440 dev_err(&bp->pdev->dev,
13441 "Cannot map doorbell space, aborting\n");
13442 rc = -ENOMEM;
13443 goto init_one_exit;
13444 }
13445
13446 if (IS_VF(bp)) {
13447 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
13448 if (rc)
13449 goto init_one_exit;
13450 }
13451
13452 /* Enable SRIOV if capability found in configuration space */
13453 rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS);
13454 if (rc)
13455 goto init_one_exit;
13456
13457 /* calc qm_cid_count */
13458 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
13459 BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
13460
13461 /* disable FCOE L2 queue for E1x*/
13462 if (CHIP_IS_E1x(bp))
13463 bp->flags |= NO_FCOE_FLAG;
13464
13465 /* Set bp->num_queues for MSI-X mode*/
13466 bnx2x_set_num_queues(bp);
13467
13468 /* Configure interrupt mode: try to enable MSI-X/MSI if
13469 * needed.
13470 */
13471 rc = bnx2x_set_int_mode(bp);
13472 if (rc) {
13473 dev_err(&pdev->dev, "Cannot set interrupts\n");
13474 goto init_one_exit;
13475 }
13476 BNX2X_DEV_INFO("set interrupts successfully\n");
13477
13478 /* register the net device */
13479 rc = register_netdev(dev);
13480 if (rc) {
13481 dev_err(&pdev->dev, "Cannot register net device\n");
13482 goto init_one_exit;
13483 }
13484 BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
13485
13486 if (!NO_FCOE(bp)) {
13487 /* Add storage MAC address */
13488 rtnl_lock();
13489 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13490 rtnl_unlock();
13491 }
13492 if (pcie_get_minimum_link(bp->pdev, &pcie_speed, &pcie_width) ||
13493 pcie_speed == PCI_SPEED_UNKNOWN ||
13494 pcie_width == PCIE_LNK_WIDTH_UNKNOWN)
13495 BNX2X_DEV_INFO("Failed to determine PCI Express Bandwidth\n");
13496 else
13497 BNX2X_DEV_INFO(
13498 "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
13499 board_info[ent->driver_data].name,
13500 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
13501 pcie_width,
13502 pcie_speed == PCIE_SPEED_2_5GT ? "2.5GHz" :
13503 pcie_speed == PCIE_SPEED_5_0GT ? "5.0GHz" :
13504 pcie_speed == PCIE_SPEED_8_0GT ? "8.0GHz" :
13505 "Unknown",
13506 dev->base_addr, bp->pdev->irq, dev->dev_addr);
13507
13508 bnx2x_register_phc(bp);
13509
13510 return 0;
13511
13512 init_one_exit:
13513 bnx2x_disable_pcie_error_reporting(bp);
13514
13515 if (bp->regview)
13516 iounmap(bp->regview);
13517
13518 if (IS_PF(bp) && bp->doorbells)
13519 iounmap(bp->doorbells);
13520
13521 free_netdev(dev);
13522
13523 if (atomic_read(&pdev->enable_cnt) == 1)
13524 pci_release_regions(pdev);
13525
13526 pci_disable_device(pdev);
13527
13528 return rc;
13529 }
13530
13531 static void __bnx2x_remove(struct pci_dev *pdev,
13532 struct net_device *dev,
13533 struct bnx2x *bp,
13534 bool remove_netdev)
13535 {
13536 if (bp->ptp_clock) {
13537 ptp_clock_unregister(bp->ptp_clock);
13538 bp->ptp_clock = NULL;
13539 }
13540
13541 /* Delete storage MAC address */
13542 if (!NO_FCOE(bp)) {
13543 rtnl_lock();
13544 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13545 rtnl_unlock();
13546 }
13547
13548 #ifdef BCM_DCBNL
13549 /* Delete app tlvs from dcbnl */
13550 bnx2x_dcbnl_update_applist(bp, true);
13551 #endif
13552
13553 if (IS_PF(bp) &&
13554 !BP_NOMCP(bp) &&
13555 (bp->flags & BC_SUPPORTS_RMMOD_CMD))
13556 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0);
13557
13558 /* Close the interface - either directly or implicitly */
13559 if (remove_netdev) {
13560 unregister_netdev(dev);
13561 } else {
13562 rtnl_lock();
13563 dev_close(dev);
13564 rtnl_unlock();
13565 }
13566
13567 bnx2x_iov_remove_one(bp);
13568
13569 /* Power on: we can't let PCI layer write to us while we are in D3 */
13570 if (IS_PF(bp)) {
13571 bnx2x_set_power_state(bp, PCI_D0);
13572
13573 /* Set endianity registers to reset values in case next driver
13574 * boots in different endianty environment.
13575 */
13576 bnx2x_reset_endianity(bp);
13577 }
13578
13579 /* Disable MSI/MSI-X */
13580 bnx2x_disable_msi(bp);
13581
13582 /* Power off */
13583 if (IS_PF(bp))
13584 bnx2x_set_power_state(bp, PCI_D3hot);
13585
13586 /* Make sure RESET task is not scheduled before continuing */
13587 cancel_delayed_work_sync(&bp->sp_rtnl_task);
13588
13589 /* send message via vfpf channel to release the resources of this vf */
13590 if (IS_VF(bp))
13591 bnx2x_vfpf_release(bp);
13592
13593 /* Assumes no further PCIe PM changes will occur */
13594 if (system_state == SYSTEM_POWER_OFF) {
13595 pci_wake_from_d3(pdev, bp->wol);
13596 pci_set_power_state(pdev, PCI_D3hot);
13597 }
13598
13599 bnx2x_disable_pcie_error_reporting(bp);
13600 if (remove_netdev) {
13601 if (bp->regview)
13602 iounmap(bp->regview);
13603
13604 /* For vfs, doorbells are part of the regview and were unmapped
13605 * along with it. FW is only loaded by PF.
13606 */
13607 if (IS_PF(bp)) {
13608 if (bp->doorbells)
13609 iounmap(bp->doorbells);
13610
13611 bnx2x_release_firmware(bp);
13612 } else {
13613 bnx2x_vf_pci_dealloc(bp);
13614 }
13615 bnx2x_free_mem_bp(bp);
13616
13617 free_netdev(dev);
13618
13619 if (atomic_read(&pdev->enable_cnt) == 1)
13620 pci_release_regions(pdev);
13621
13622 pci_disable_device(pdev);
13623 }
13624 }
13625
13626 static void bnx2x_remove_one(struct pci_dev *pdev)
13627 {
13628 struct net_device *dev = pci_get_drvdata(pdev);
13629 struct bnx2x *bp;
13630
13631 if (!dev) {
13632 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
13633 return;
13634 }
13635 bp = netdev_priv(dev);
13636
13637 __bnx2x_remove(pdev, dev, bp, true);
13638 }
13639
13640 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
13641 {
13642 bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
13643
13644 bp->rx_mode = BNX2X_RX_MODE_NONE;
13645
13646 if (CNIC_LOADED(bp))
13647 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
13648
13649 /* Stop Tx */
13650 bnx2x_tx_disable(bp);
13651 /* Delete all NAPI objects */
13652 bnx2x_del_all_napi(bp);
13653 if (CNIC_LOADED(bp))
13654 bnx2x_del_all_napi_cnic(bp);
13655 netdev_reset_tc(bp->dev);
13656
13657 del_timer_sync(&bp->timer);
13658 cancel_delayed_work_sync(&bp->sp_task);
13659 cancel_delayed_work_sync(&bp->period_task);
13660
13661 spin_lock_bh(&bp->stats_lock);
13662 bp->stats_state = STATS_STATE_DISABLED;
13663 spin_unlock_bh(&bp->stats_lock);
13664
13665 bnx2x_save_statistics(bp);
13666
13667 netif_carrier_off(bp->dev);
13668
13669 return 0;
13670 }
13671
13672 /**
13673 * bnx2x_io_error_detected - called when PCI error is detected
13674 * @pdev: Pointer to PCI device
13675 * @state: The current pci connection state
13676 *
13677 * This function is called after a PCI bus error affecting
13678 * this device has been detected.
13679 */
13680 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
13681 pci_channel_state_t state)
13682 {
13683 struct net_device *dev = pci_get_drvdata(pdev);
13684 struct bnx2x *bp = netdev_priv(dev);
13685
13686 rtnl_lock();
13687
13688 BNX2X_ERR("IO error detected\n");
13689
13690 netif_device_detach(dev);
13691
13692 if (state == pci_channel_io_perm_failure) {
13693 rtnl_unlock();
13694 return PCI_ERS_RESULT_DISCONNECT;
13695 }
13696
13697 if (netif_running(dev))
13698 bnx2x_eeh_nic_unload(bp);
13699
13700 bnx2x_prev_path_mark_eeh(bp);
13701
13702 pci_disable_device(pdev);
13703
13704 rtnl_unlock();
13705
13706 /* Request a slot reset */
13707 return PCI_ERS_RESULT_NEED_RESET;
13708 }
13709
13710 /**
13711 * bnx2x_io_slot_reset - called after the PCI bus has been reset
13712 * @pdev: Pointer to PCI device
13713 *
13714 * Restart the card from scratch, as if from a cold-boot.
13715 */
13716 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
13717 {
13718 struct net_device *dev = pci_get_drvdata(pdev);
13719 struct bnx2x *bp = netdev_priv(dev);
13720 int i;
13721
13722 rtnl_lock();
13723 BNX2X_ERR("IO slot reset initializing...\n");
13724 if (pci_enable_device(pdev)) {
13725 dev_err(&pdev->dev,
13726 "Cannot re-enable PCI device after reset\n");
13727 rtnl_unlock();
13728 return PCI_ERS_RESULT_DISCONNECT;
13729 }
13730
13731 pci_set_master(pdev);
13732 pci_restore_state(pdev);
13733 pci_save_state(pdev);
13734
13735 if (netif_running(dev))
13736 bnx2x_set_power_state(bp, PCI_D0);
13737
13738 if (netif_running(dev)) {
13739 BNX2X_ERR("IO slot reset --> driver unload\n");
13740
13741 /* MCP should have been reset; Need to wait for validity */
13742 bnx2x_init_shmem(bp);
13743
13744 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
13745 u32 v;
13746
13747 v = SHMEM2_RD(bp,
13748 drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
13749 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
13750 v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
13751 }
13752 bnx2x_drain_tx_queues(bp);
13753 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
13754 bnx2x_netif_stop(bp, 1);
13755 bnx2x_free_irq(bp);
13756
13757 /* Report UNLOAD_DONE to MCP */
13758 bnx2x_send_unload_done(bp, true);
13759
13760 bp->sp_state = 0;
13761 bp->port.pmf = 0;
13762
13763 bnx2x_prev_unload(bp);
13764
13765 /* We should have reseted the engine, so It's fair to
13766 * assume the FW will no longer write to the bnx2x driver.
13767 */
13768 bnx2x_squeeze_objects(bp);
13769 bnx2x_free_skbs(bp);
13770 for_each_rx_queue(bp, i)
13771 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
13772 bnx2x_free_fp_mem(bp);
13773 bnx2x_free_mem(bp);
13774
13775 bp->state = BNX2X_STATE_CLOSED;
13776 }
13777
13778 rtnl_unlock();
13779
13780 /* If AER, perform cleanup of the PCIe registers */
13781 if (bp->flags & AER_ENABLED) {
13782 if (pci_cleanup_aer_uncorrect_error_status(pdev))
13783 BNX2X_ERR("pci_cleanup_aer_uncorrect_error_status failed\n");
13784 else
13785 DP(NETIF_MSG_HW, "pci_cleanup_aer_uncorrect_error_status succeeded\n");
13786 }
13787
13788 return PCI_ERS_RESULT_RECOVERED;
13789 }
13790
13791 /**
13792 * bnx2x_io_resume - called when traffic can start flowing again
13793 * @pdev: Pointer to PCI device
13794 *
13795 * This callback is called when the error recovery driver tells us that
13796 * its OK to resume normal operation.
13797 */
13798 static void bnx2x_io_resume(struct pci_dev *pdev)
13799 {
13800 struct net_device *dev = pci_get_drvdata(pdev);
13801 struct bnx2x *bp = netdev_priv(dev);
13802
13803 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
13804 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
13805 return;
13806 }
13807
13808 rtnl_lock();
13809
13810 bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
13811 DRV_MSG_SEQ_NUMBER_MASK;
13812
13813 if (netif_running(dev))
13814 bnx2x_nic_load(bp, LOAD_NORMAL);
13815
13816 netif_device_attach(dev);
13817
13818 rtnl_unlock();
13819 }
13820
13821 static const struct pci_error_handlers bnx2x_err_handler = {
13822 .error_detected = bnx2x_io_error_detected,
13823 .slot_reset = bnx2x_io_slot_reset,
13824 .resume = bnx2x_io_resume,
13825 };
13826
13827 static void bnx2x_shutdown(struct pci_dev *pdev)
13828 {
13829 struct net_device *dev = pci_get_drvdata(pdev);
13830 struct bnx2x *bp;
13831
13832 if (!dev)
13833 return;
13834
13835 bp = netdev_priv(dev);
13836 if (!bp)
13837 return;
13838
13839 rtnl_lock();
13840 netif_device_detach(dev);
13841 rtnl_unlock();
13842
13843 /* Don't remove the netdevice, as there are scenarios which will cause
13844 * the kernel to hang, e.g., when trying to remove bnx2i while the
13845 * rootfs is mounted from SAN.
13846 */
13847 __bnx2x_remove(pdev, dev, bp, false);
13848 }
13849
13850 static struct pci_driver bnx2x_pci_driver = {
13851 .name = DRV_MODULE_NAME,
13852 .id_table = bnx2x_pci_tbl,
13853 .probe = bnx2x_init_one,
13854 .remove = bnx2x_remove_one,
13855 .suspend = bnx2x_suspend,
13856 .resume = bnx2x_resume,
13857 .err_handler = &bnx2x_err_handler,
13858 #ifdef CONFIG_BNX2X_SRIOV
13859 .sriov_configure = bnx2x_sriov_configure,
13860 #endif
13861 .shutdown = bnx2x_shutdown,
13862 };
13863
13864 static int __init bnx2x_init(void)
13865 {
13866 int ret;
13867
13868 pr_info("%s", version);
13869
13870 bnx2x_wq = create_singlethread_workqueue("bnx2x");
13871 if (bnx2x_wq == NULL) {
13872 pr_err("Cannot create workqueue\n");
13873 return -ENOMEM;
13874 }
13875 bnx2x_iov_wq = create_singlethread_workqueue("bnx2x_iov");
13876 if (!bnx2x_iov_wq) {
13877 pr_err("Cannot create iov workqueue\n");
13878 destroy_workqueue(bnx2x_wq);
13879 return -ENOMEM;
13880 }
13881
13882 ret = pci_register_driver(&bnx2x_pci_driver);
13883 if (ret) {
13884 pr_err("Cannot register driver\n");
13885 destroy_workqueue(bnx2x_wq);
13886 destroy_workqueue(bnx2x_iov_wq);
13887 }
13888 return ret;
13889 }
13890
13891 static void __exit bnx2x_cleanup(void)
13892 {
13893 struct list_head *pos, *q;
13894
13895 pci_unregister_driver(&bnx2x_pci_driver);
13896
13897 destroy_workqueue(bnx2x_wq);
13898 destroy_workqueue(bnx2x_iov_wq);
13899
13900 /* Free globally allocated resources */
13901 list_for_each_safe(pos, q, &bnx2x_prev_list) {
13902 struct bnx2x_prev_path_list *tmp =
13903 list_entry(pos, struct bnx2x_prev_path_list, list);
13904 list_del(pos);
13905 kfree(tmp);
13906 }
13907 }
13908
13909 void bnx2x_notify_link_changed(struct bnx2x *bp)
13910 {
13911 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
13912 }
13913
13914 module_init(bnx2x_init);
13915 module_exit(bnx2x_cleanup);
13916
13917 /**
13918 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
13919 *
13920 * @bp: driver handle
13921 * @set: set or clear the CAM entry
13922 *
13923 * This function will wait until the ramrod completion returns.
13924 * Return 0 if success, -ENODEV if ramrod doesn't return.
13925 */
13926 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
13927 {
13928 unsigned long ramrod_flags = 0;
13929
13930 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
13931 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
13932 &bp->iscsi_l2_mac_obj, true,
13933 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
13934 }
13935
13936 /* count denotes the number of new completions we have seen */
13937 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
13938 {
13939 struct eth_spe *spe;
13940 int cxt_index, cxt_offset;
13941
13942 #ifdef BNX2X_STOP_ON_ERROR
13943 if (unlikely(bp->panic))
13944 return;
13945 #endif
13946
13947 spin_lock_bh(&bp->spq_lock);
13948 BUG_ON(bp->cnic_spq_pending < count);
13949 bp->cnic_spq_pending -= count;
13950
13951 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
13952 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
13953 & SPE_HDR_CONN_TYPE) >>
13954 SPE_HDR_CONN_TYPE_SHIFT;
13955 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
13956 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
13957
13958 /* Set validation for iSCSI L2 client before sending SETUP
13959 * ramrod
13960 */
13961 if (type == ETH_CONNECTION_TYPE) {
13962 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
13963 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
13964 ILT_PAGE_CIDS;
13965 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
13966 (cxt_index * ILT_PAGE_CIDS);
13967 bnx2x_set_ctx_validation(bp,
13968 &bp->context[cxt_index].
13969 vcxt[cxt_offset].eth,
13970 BNX2X_ISCSI_ETH_CID(bp));
13971 }
13972 }
13973
13974 /*
13975 * There may be not more than 8 L2, not more than 8 L5 SPEs
13976 * and in the air. We also check that number of outstanding
13977 * COMMON ramrods is not more than the EQ and SPQ can
13978 * accommodate.
13979 */
13980 if (type == ETH_CONNECTION_TYPE) {
13981 if (!atomic_read(&bp->cq_spq_left))
13982 break;
13983 else
13984 atomic_dec(&bp->cq_spq_left);
13985 } else if (type == NONE_CONNECTION_TYPE) {
13986 if (!atomic_read(&bp->eq_spq_left))
13987 break;
13988 else
13989 atomic_dec(&bp->eq_spq_left);
13990 } else if ((type == ISCSI_CONNECTION_TYPE) ||
13991 (type == FCOE_CONNECTION_TYPE)) {
13992 if (bp->cnic_spq_pending >=
13993 bp->cnic_eth_dev.max_kwqe_pending)
13994 break;
13995 else
13996 bp->cnic_spq_pending++;
13997 } else {
13998 BNX2X_ERR("Unknown SPE type: %d\n", type);
13999 bnx2x_panic();
14000 break;
14001 }
14002
14003 spe = bnx2x_sp_get_next(bp);
14004 *spe = *bp->cnic_kwq_cons;
14005
14006 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
14007 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
14008
14009 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
14010 bp->cnic_kwq_cons = bp->cnic_kwq;
14011 else
14012 bp->cnic_kwq_cons++;
14013 }
14014 bnx2x_sp_prod_update(bp);
14015 spin_unlock_bh(&bp->spq_lock);
14016 }
14017
14018 static int bnx2x_cnic_sp_queue(struct net_device *dev,
14019 struct kwqe_16 *kwqes[], u32 count)
14020 {
14021 struct bnx2x *bp = netdev_priv(dev);
14022 int i;
14023
14024 #ifdef BNX2X_STOP_ON_ERROR
14025 if (unlikely(bp->panic)) {
14026 BNX2X_ERR("Can't post to SP queue while panic\n");
14027 return -EIO;
14028 }
14029 #endif
14030
14031 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
14032 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
14033 BNX2X_ERR("Handling parity error recovery. Try again later\n");
14034 return -EAGAIN;
14035 }
14036
14037 spin_lock_bh(&bp->spq_lock);
14038
14039 for (i = 0; i < count; i++) {
14040 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
14041
14042 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
14043 break;
14044
14045 *bp->cnic_kwq_prod = *spe;
14046
14047 bp->cnic_kwq_pending++;
14048
14049 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
14050 spe->hdr.conn_and_cmd_data, spe->hdr.type,
14051 spe->data.update_data_addr.hi,
14052 spe->data.update_data_addr.lo,
14053 bp->cnic_kwq_pending);
14054
14055 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
14056 bp->cnic_kwq_prod = bp->cnic_kwq;
14057 else
14058 bp->cnic_kwq_prod++;
14059 }
14060
14061 spin_unlock_bh(&bp->spq_lock);
14062
14063 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
14064 bnx2x_cnic_sp_post(bp, 0);
14065
14066 return i;
14067 }
14068
14069 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14070 {
14071 struct cnic_ops *c_ops;
14072 int rc = 0;
14073
14074 mutex_lock(&bp->cnic_mutex);
14075 c_ops = rcu_dereference_protected(bp->cnic_ops,
14076 lockdep_is_held(&bp->cnic_mutex));
14077 if (c_ops)
14078 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14079 mutex_unlock(&bp->cnic_mutex);
14080
14081 return rc;
14082 }
14083
14084 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14085 {
14086 struct cnic_ops *c_ops;
14087 int rc = 0;
14088
14089 rcu_read_lock();
14090 c_ops = rcu_dereference(bp->cnic_ops);
14091 if (c_ops)
14092 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14093 rcu_read_unlock();
14094
14095 return rc;
14096 }
14097
14098 /*
14099 * for commands that have no data
14100 */
14101 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
14102 {
14103 struct cnic_ctl_info ctl = {0};
14104
14105 ctl.cmd = cmd;
14106
14107 return bnx2x_cnic_ctl_send(bp, &ctl);
14108 }
14109
14110 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
14111 {
14112 struct cnic_ctl_info ctl = {0};
14113
14114 /* first we tell CNIC and only then we count this as a completion */
14115 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
14116 ctl.data.comp.cid = cid;
14117 ctl.data.comp.error = err;
14118
14119 bnx2x_cnic_ctl_send_bh(bp, &ctl);
14120 bnx2x_cnic_sp_post(bp, 0);
14121 }
14122
14123 /* Called with netif_addr_lock_bh() taken.
14124 * Sets an rx_mode config for an iSCSI ETH client.
14125 * Doesn't block.
14126 * Completion should be checked outside.
14127 */
14128 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
14129 {
14130 unsigned long accept_flags = 0, ramrod_flags = 0;
14131 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
14132 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
14133
14134 if (start) {
14135 /* Start accepting on iSCSI L2 ring. Accept all multicasts
14136 * because it's the only way for UIO Queue to accept
14137 * multicasts (in non-promiscuous mode only one Queue per
14138 * function will receive multicast packets (leading in our
14139 * case).
14140 */
14141 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
14142 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
14143 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
14144 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
14145
14146 /* Clear STOP_PENDING bit if START is requested */
14147 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
14148
14149 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
14150 } else
14151 /* Clear START_PENDING bit if STOP is requested */
14152 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
14153
14154 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
14155 set_bit(sched_state, &bp->sp_state);
14156 else {
14157 __set_bit(RAMROD_RX, &ramrod_flags);
14158 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
14159 ramrod_flags);
14160 }
14161 }
14162
14163 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
14164 {
14165 struct bnx2x *bp = netdev_priv(dev);
14166 int rc = 0;
14167
14168 switch (ctl->cmd) {
14169 case DRV_CTL_CTXTBL_WR_CMD: {
14170 u32 index = ctl->data.io.offset;
14171 dma_addr_t addr = ctl->data.io.dma_addr;
14172
14173 bnx2x_ilt_wr(bp, index, addr);
14174 break;
14175 }
14176
14177 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
14178 int count = ctl->data.credit.credit_count;
14179
14180 bnx2x_cnic_sp_post(bp, count);
14181 break;
14182 }
14183
14184 /* rtnl_lock is held. */
14185 case DRV_CTL_START_L2_CMD: {
14186 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14187 unsigned long sp_bits = 0;
14188
14189 /* Configure the iSCSI classification object */
14190 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
14191 cp->iscsi_l2_client_id,
14192 cp->iscsi_l2_cid, BP_FUNC(bp),
14193 bnx2x_sp(bp, mac_rdata),
14194 bnx2x_sp_mapping(bp, mac_rdata),
14195 BNX2X_FILTER_MAC_PENDING,
14196 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
14197 &bp->macs_pool);
14198
14199 /* Set iSCSI MAC address */
14200 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
14201 if (rc)
14202 break;
14203
14204 mmiowb();
14205 barrier();
14206
14207 /* Start accepting on iSCSI L2 ring */
14208
14209 netif_addr_lock_bh(dev);
14210 bnx2x_set_iscsi_eth_rx_mode(bp, true);
14211 netif_addr_unlock_bh(dev);
14212
14213 /* bits to wait on */
14214 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14215 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
14216
14217 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14218 BNX2X_ERR("rx_mode completion timed out!\n");
14219
14220 break;
14221 }
14222
14223 /* rtnl_lock is held. */
14224 case DRV_CTL_STOP_L2_CMD: {
14225 unsigned long sp_bits = 0;
14226
14227 /* Stop accepting on iSCSI L2 ring */
14228 netif_addr_lock_bh(dev);
14229 bnx2x_set_iscsi_eth_rx_mode(bp, false);
14230 netif_addr_unlock_bh(dev);
14231
14232 /* bits to wait on */
14233 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14234 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
14235
14236 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14237 BNX2X_ERR("rx_mode completion timed out!\n");
14238
14239 mmiowb();
14240 barrier();
14241
14242 /* Unset iSCSI L2 MAC */
14243 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
14244 BNX2X_ISCSI_ETH_MAC, true);
14245 break;
14246 }
14247 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
14248 int count = ctl->data.credit.credit_count;
14249
14250 smp_mb__before_atomic();
14251 atomic_add(count, &bp->cq_spq_left);
14252 smp_mb__after_atomic();
14253 break;
14254 }
14255 case DRV_CTL_ULP_REGISTER_CMD: {
14256 int ulp_type = ctl->data.register_data.ulp_type;
14257
14258 if (CHIP_IS_E3(bp)) {
14259 int idx = BP_FW_MB_IDX(bp);
14260 u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14261 int path = BP_PATH(bp);
14262 int port = BP_PORT(bp);
14263 int i;
14264 u32 scratch_offset;
14265 u32 *host_addr;
14266
14267 /* first write capability to shmem2 */
14268 if (ulp_type == CNIC_ULP_ISCSI)
14269 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14270 else if (ulp_type == CNIC_ULP_FCOE)
14271 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14272 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14273
14274 if ((ulp_type != CNIC_ULP_FCOE) ||
14275 (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
14276 (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES)))
14277 break;
14278
14279 /* if reached here - should write fcoe capabilities */
14280 scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
14281 if (!scratch_offset)
14282 break;
14283 scratch_offset += offsetof(struct glob_ncsi_oem_data,
14284 fcoe_features[path][port]);
14285 host_addr = (u32 *) &(ctl->data.register_data.
14286 fcoe_features);
14287 for (i = 0; i < sizeof(struct fcoe_capabilities);
14288 i += 4)
14289 REG_WR(bp, scratch_offset + i,
14290 *(host_addr + i/4));
14291 }
14292 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14293 break;
14294 }
14295
14296 case DRV_CTL_ULP_UNREGISTER_CMD: {
14297 int ulp_type = ctl->data.ulp_type;
14298
14299 if (CHIP_IS_E3(bp)) {
14300 int idx = BP_FW_MB_IDX(bp);
14301 u32 cap;
14302
14303 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14304 if (ulp_type == CNIC_ULP_ISCSI)
14305 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14306 else if (ulp_type == CNIC_ULP_FCOE)
14307 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14308 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14309 }
14310 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14311 break;
14312 }
14313
14314 default:
14315 BNX2X_ERR("unknown command %x\n", ctl->cmd);
14316 rc = -EINVAL;
14317 }
14318
14319 return rc;
14320 }
14321
14322 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
14323 {
14324 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14325
14326 if (bp->flags & USING_MSIX_FLAG) {
14327 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
14328 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
14329 cp->irq_arr[0].vector = bp->msix_table[1].vector;
14330 } else {
14331 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
14332 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
14333 }
14334 if (!CHIP_IS_E1x(bp))
14335 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
14336 else
14337 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
14338
14339 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
14340 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
14341 cp->irq_arr[1].status_blk = bp->def_status_blk;
14342 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
14343 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
14344
14345 cp->num_irq = 2;
14346 }
14347
14348 void bnx2x_setup_cnic_info(struct bnx2x *bp)
14349 {
14350 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14351
14352 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
14353 bnx2x_cid_ilt_lines(bp);
14354 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
14355 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
14356 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
14357
14358 DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n",
14359 BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid,
14360 cp->iscsi_l2_cid);
14361
14362 if (NO_ISCSI_OOO(bp))
14363 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
14364 }
14365
14366 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
14367 void *data)
14368 {
14369 struct bnx2x *bp = netdev_priv(dev);
14370 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14371 int rc;
14372
14373 DP(NETIF_MSG_IFUP, "Register_cnic called\n");
14374
14375 if (ops == NULL) {
14376 BNX2X_ERR("NULL ops received\n");
14377 return -EINVAL;
14378 }
14379
14380 if (!CNIC_SUPPORT(bp)) {
14381 BNX2X_ERR("Can't register CNIC when not supported\n");
14382 return -EOPNOTSUPP;
14383 }
14384
14385 if (!CNIC_LOADED(bp)) {
14386 rc = bnx2x_load_cnic(bp);
14387 if (rc) {
14388 BNX2X_ERR("CNIC-related load failed\n");
14389 return rc;
14390 }
14391 }
14392
14393 bp->cnic_enabled = true;
14394
14395 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
14396 if (!bp->cnic_kwq)
14397 return -ENOMEM;
14398
14399 bp->cnic_kwq_cons = bp->cnic_kwq;
14400 bp->cnic_kwq_prod = bp->cnic_kwq;
14401 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
14402
14403 bp->cnic_spq_pending = 0;
14404 bp->cnic_kwq_pending = 0;
14405
14406 bp->cnic_data = data;
14407
14408 cp->num_irq = 0;
14409 cp->drv_state |= CNIC_DRV_STATE_REGD;
14410 cp->iro_arr = bp->iro_arr;
14411
14412 bnx2x_setup_cnic_irq_info(bp);
14413
14414 rcu_assign_pointer(bp->cnic_ops, ops);
14415
14416 /* Schedule driver to read CNIC driver versions */
14417 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14418
14419 return 0;
14420 }
14421
14422 static int bnx2x_unregister_cnic(struct net_device *dev)
14423 {
14424 struct bnx2x *bp = netdev_priv(dev);
14425 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14426
14427 mutex_lock(&bp->cnic_mutex);
14428 cp->drv_state = 0;
14429 RCU_INIT_POINTER(bp->cnic_ops, NULL);
14430 mutex_unlock(&bp->cnic_mutex);
14431 synchronize_rcu();
14432 bp->cnic_enabled = false;
14433 kfree(bp->cnic_kwq);
14434 bp->cnic_kwq = NULL;
14435
14436 return 0;
14437 }
14438
14439 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
14440 {
14441 struct bnx2x *bp = netdev_priv(dev);
14442 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14443
14444 /* If both iSCSI and FCoE are disabled - return NULL in
14445 * order to indicate CNIC that it should not try to work
14446 * with this device.
14447 */
14448 if (NO_ISCSI(bp) && NO_FCOE(bp))
14449 return NULL;
14450
14451 cp->drv_owner = THIS_MODULE;
14452 cp->chip_id = CHIP_ID(bp);
14453 cp->pdev = bp->pdev;
14454 cp->io_base = bp->regview;
14455 cp->io_base2 = bp->doorbells;
14456 cp->max_kwqe_pending = 8;
14457 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
14458 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
14459 bnx2x_cid_ilt_lines(bp);
14460 cp->ctx_tbl_len = CNIC_ILT_LINES;
14461 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
14462 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
14463 cp->drv_ctl = bnx2x_drv_ctl;
14464 cp->drv_register_cnic = bnx2x_register_cnic;
14465 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
14466 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
14467 cp->iscsi_l2_client_id =
14468 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
14469 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
14470
14471 if (NO_ISCSI_OOO(bp))
14472 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
14473
14474 if (NO_ISCSI(bp))
14475 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
14476
14477 if (NO_FCOE(bp))
14478 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
14479
14480 BNX2X_DEV_INFO(
14481 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
14482 cp->ctx_blk_size,
14483 cp->ctx_tbl_offset,
14484 cp->ctx_tbl_len,
14485 cp->starting_cid);
14486 return cp;
14487 }
14488
14489 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
14490 {
14491 struct bnx2x *bp = fp->bp;
14492 u32 offset = BAR_USTRORM_INTMEM;
14493
14494 if (IS_VF(bp))
14495 return bnx2x_vf_ustorm_prods_offset(bp, fp);
14496 else if (!CHIP_IS_E1x(bp))
14497 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
14498 else
14499 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
14500
14501 return offset;
14502 }
14503
14504 /* called only on E1H or E2.
14505 * When pretending to be PF, the pretend value is the function number 0...7
14506 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
14507 * combination
14508 */
14509 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
14510 {
14511 u32 pretend_reg;
14512
14513 if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
14514 return -1;
14515
14516 /* get my own pretend register */
14517 pretend_reg = bnx2x_get_pretend_reg(bp);
14518 REG_WR(bp, pretend_reg, pretend_func_val);
14519 REG_RD(bp, pretend_reg);
14520 return 0;
14521 }
14522
14523 static void bnx2x_ptp_task(struct work_struct *work)
14524 {
14525 struct bnx2x *bp = container_of(work, struct bnx2x, ptp_task);
14526 int port = BP_PORT(bp);
14527 u32 val_seq;
14528 u64 timestamp, ns;
14529 struct skb_shared_hwtstamps shhwtstamps;
14530
14531 /* Read Tx timestamp registers */
14532 val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
14533 NIG_REG_P0_TLLH_PTP_BUF_SEQID);
14534 if (val_seq & 0x10000) {
14535 /* There is a valid timestamp value */
14536 timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB :
14537 NIG_REG_P0_TLLH_PTP_BUF_TS_MSB);
14538 timestamp <<= 32;
14539 timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB :
14540 NIG_REG_P0_TLLH_PTP_BUF_TS_LSB);
14541 /* Reset timestamp register to allow new timestamp */
14542 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
14543 NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
14544 ns = timecounter_cyc2time(&bp->timecounter, timestamp);
14545
14546 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
14547 shhwtstamps.hwtstamp = ns_to_ktime(ns);
14548 skb_tstamp_tx(bp->ptp_tx_skb, &shhwtstamps);
14549 dev_kfree_skb_any(bp->ptp_tx_skb);
14550 bp->ptp_tx_skb = NULL;
14551
14552 DP(BNX2X_MSG_PTP, "Tx timestamp, timestamp cycles = %llu, ns = %llu\n",
14553 timestamp, ns);
14554 } else {
14555 DP(BNX2X_MSG_PTP, "There is no valid Tx timestamp yet\n");
14556 /* Reschedule to keep checking for a valid timestamp value */
14557 schedule_work(&bp->ptp_task);
14558 }
14559 }
14560
14561 void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb)
14562 {
14563 int port = BP_PORT(bp);
14564 u64 timestamp, ns;
14565
14566 timestamp = REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB :
14567 NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB);
14568 timestamp <<= 32;
14569 timestamp |= REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB :
14570 NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB);
14571
14572 /* Reset timestamp register to allow new timestamp */
14573 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
14574 NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
14575
14576 ns = timecounter_cyc2time(&bp->timecounter, timestamp);
14577
14578 skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns);
14579
14580 DP(BNX2X_MSG_PTP, "Rx timestamp, timestamp cycles = %llu, ns = %llu\n",
14581 timestamp, ns);
14582 }
14583
14584 /* Read the PHC */
14585 static cycle_t bnx2x_cyclecounter_read(const struct cyclecounter *cc)
14586 {
14587 struct bnx2x *bp = container_of(cc, struct bnx2x, cyclecounter);
14588 int port = BP_PORT(bp);
14589 u32 wb_data[2];
14590 u64 phc_cycles;
14591
14592 REG_RD_DMAE(bp, port ? NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t1 :
14593 NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t0, wb_data, 2);
14594 phc_cycles = wb_data[1];
14595 phc_cycles = (phc_cycles << 32) + wb_data[0];
14596
14597 DP(BNX2X_MSG_PTP, "PHC read cycles = %llu\n", phc_cycles);
14598
14599 return phc_cycles;
14600 }
14601
14602 static void bnx2x_init_cyclecounter(struct bnx2x *bp)
14603 {
14604 memset(&bp->cyclecounter, 0, sizeof(bp->cyclecounter));
14605 bp->cyclecounter.read = bnx2x_cyclecounter_read;
14606 bp->cyclecounter.mask = CLOCKSOURCE_MASK(64);
14607 bp->cyclecounter.shift = 1;
14608 bp->cyclecounter.mult = 1;
14609 }
14610
14611 static int bnx2x_send_reset_timesync_ramrod(struct bnx2x *bp)
14612 {
14613 struct bnx2x_func_state_params func_params = {NULL};
14614 struct bnx2x_func_set_timesync_params *set_timesync_params =
14615 &func_params.params.set_timesync;
14616
14617 /* Prepare parameters for function state transitions */
14618 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
14619 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
14620
14621 func_params.f_obj = &bp->func_obj;
14622 func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
14623
14624 /* Function parameters */
14625 set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_RESET;
14626 set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
14627
14628 return bnx2x_func_state_change(bp, &func_params);
14629 }
14630
14631 int bnx2x_enable_ptp_packets(struct bnx2x *bp)
14632 {
14633 struct bnx2x_queue_state_params q_params;
14634 int rc, i;
14635
14636 /* send queue update ramrod to enable PTP packets */
14637 memset(&q_params, 0, sizeof(q_params));
14638 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
14639 q_params.cmd = BNX2X_Q_CMD_UPDATE;
14640 __set_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG,
14641 &q_params.params.update.update_flags);
14642 __set_bit(BNX2X_Q_UPDATE_PTP_PKTS,
14643 &q_params.params.update.update_flags);
14644
14645 /* send the ramrod on all the queues of the PF */
14646 for_each_eth_queue(bp, i) {
14647 struct bnx2x_fastpath *fp = &bp->fp[i];
14648
14649 /* Set the appropriate Queue object */
14650 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
14651
14652 /* Update the Queue state */
14653 rc = bnx2x_queue_state_change(bp, &q_params);
14654 if (rc) {
14655 BNX2X_ERR("Failed to enable PTP packets\n");
14656 return rc;
14657 }
14658 }
14659
14660 return 0;
14661 }
14662
14663 int bnx2x_configure_ptp_filters(struct bnx2x *bp)
14664 {
14665 int port = BP_PORT(bp);
14666 int rc;
14667
14668 if (!bp->hwtstamp_ioctl_called)
14669 return 0;
14670
14671 switch (bp->tx_type) {
14672 case HWTSTAMP_TX_ON:
14673 bp->flags |= TX_TIMESTAMPING_EN;
14674 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
14675 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x6AA);
14676 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
14677 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3EEE);
14678 break;
14679 case HWTSTAMP_TX_ONESTEP_SYNC:
14680 BNX2X_ERR("One-step timestamping is not supported\n");
14681 return -ERANGE;
14682 }
14683
14684 switch (bp->rx_filter) {
14685 case HWTSTAMP_FILTER_NONE:
14686 break;
14687 case HWTSTAMP_FILTER_ALL:
14688 case HWTSTAMP_FILTER_SOME:
14689 bp->rx_filter = HWTSTAMP_FILTER_NONE;
14690 break;
14691 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
14692 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
14693 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
14694 bp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
14695 /* Initialize PTP detection for UDP/IPv4 events */
14696 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14697 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EE);
14698 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14699 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFE);
14700 break;
14701 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
14702 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
14703 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
14704 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
14705 /* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */
14706 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14707 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EA);
14708 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14709 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FEE);
14710 break;
14711 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
14712 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
14713 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
14714 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
14715 /* Initialize PTP detection L2 events */
14716 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14717 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6BF);
14718 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14719 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EFF);
14720
14721 break;
14722 case HWTSTAMP_FILTER_PTP_V2_EVENT:
14723 case HWTSTAMP_FILTER_PTP_V2_SYNC:
14724 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
14725 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
14726 /* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */
14727 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14728 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6AA);
14729 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14730 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EEE);
14731 break;
14732 }
14733
14734 /* Indicate to FW that this PF expects recorded PTP packets */
14735 rc = bnx2x_enable_ptp_packets(bp);
14736 if (rc)
14737 return rc;
14738
14739 /* Enable sending PTP packets to host */
14740 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
14741 NIG_REG_P0_LLH_PTP_TO_HOST, 0x1);
14742
14743 return 0;
14744 }
14745
14746 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr)
14747 {
14748 struct hwtstamp_config config;
14749 int rc;
14750
14751 DP(BNX2X_MSG_PTP, "HWTSTAMP IOCTL called\n");
14752
14753 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
14754 return -EFAULT;
14755
14756 DP(BNX2X_MSG_PTP, "Requested tx_type: %d, requested rx_filters = %d\n",
14757 config.tx_type, config.rx_filter);
14758
14759 if (config.flags) {
14760 BNX2X_ERR("config.flags is reserved for future use\n");
14761 return -EINVAL;
14762 }
14763
14764 bp->hwtstamp_ioctl_called = 1;
14765 bp->tx_type = config.tx_type;
14766 bp->rx_filter = config.rx_filter;
14767
14768 rc = bnx2x_configure_ptp_filters(bp);
14769 if (rc)
14770 return rc;
14771
14772 config.rx_filter = bp->rx_filter;
14773
14774 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
14775 -EFAULT : 0;
14776 }
14777
14778 /* Configrues HW for PTP */
14779 static int bnx2x_configure_ptp(struct bnx2x *bp)
14780 {
14781 int rc, port = BP_PORT(bp);
14782 u32 wb_data[2];
14783
14784 /* Reset PTP event detection rules - will be configured in the IOCTL */
14785 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14786 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
14787 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14788 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
14789 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
14790 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
14791 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
14792 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
14793
14794 /* Disable PTP packets to host - will be configured in the IOCTL*/
14795 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
14796 NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
14797
14798 /* Enable the PTP feature */
14799 REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
14800 NIG_REG_P0_PTP_EN, 0x3F);
14801
14802 /* Enable the free-running counter */
14803 wb_data[0] = 0;
14804 wb_data[1] = 0;
14805 REG_WR_DMAE(bp, NIG_REG_TIMESYNC_GEN_REG + tsgen_ctrl, wb_data, 2);
14806
14807 /* Reset drift register (offset register is not reset) */
14808 rc = bnx2x_send_reset_timesync_ramrod(bp);
14809 if (rc) {
14810 BNX2X_ERR("Failed to reset PHC drift register\n");
14811 return -EFAULT;
14812 }
14813
14814 /* Reset possibly old timestamps */
14815 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
14816 NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
14817 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
14818 NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
14819
14820 return 0;
14821 }
14822
14823 /* Called during load, to initialize PTP-related stuff */
14824 void bnx2x_init_ptp(struct bnx2x *bp)
14825 {
14826 int rc;
14827
14828 /* Configure PTP in HW */
14829 rc = bnx2x_configure_ptp(bp);
14830 if (rc) {
14831 BNX2X_ERR("Stopping PTP initialization\n");
14832 return;
14833 }
14834
14835 /* Init work queue for Tx timestamping */
14836 INIT_WORK(&bp->ptp_task, bnx2x_ptp_task);
14837
14838 /* Init cyclecounter and timecounter. This is done only in the first
14839 * load. If done in every load, PTP application will fail when doing
14840 * unload / load (e.g. MTU change) while it is running.
14841 */
14842 if (!bp->timecounter_init_done) {
14843 bnx2x_init_cyclecounter(bp);
14844 timecounter_init(&bp->timecounter, &bp->cyclecounter,
14845 ktime_to_ns(ktime_get_real()));
14846 bp->timecounter_init_done = 1;
14847 }
14848
14849 DP(BNX2X_MSG_PTP, "PTP initialization ended successfully\n");
14850 }
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