1 /* bnx2x_main.c: QLogic Everest network driver.
3 * Copyright (c) 2007-2013 Broadcom Corporation
4 * Copyright (c) 2014 QLogic Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation.
11 * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
12 * Written by: Eliezer Tamir
13 * Based on code from Michael Chan's bnx2 driver
14 * UDP CSUM errata workaround by Arik Gendelman
15 * Slowpath and fastpath rework by Vladislav Zolotarov
16 * Statistics and Link management by Yitchak Gertner
20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/kernel.h>
25 #include <linux/device.h> /* for dev_info() */
26 #include <linux/timer.h>
27 #include <linux/errno.h>
28 #include <linux/ioport.h>
29 #include <linux/slab.h>
30 #include <linux/interrupt.h>
31 #include <linux/pci.h>
32 #include <linux/aer.h>
33 #include <linux/init.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/bitops.h>
39 #include <linux/irq.h>
40 #include <linux/delay.h>
41 #include <asm/byteorder.h>
42 #include <linux/time.h>
43 #include <linux/ethtool.h>
44 #include <linux/mii.h>
45 #include <linux/if_vlan.h>
46 #include <linux/crash_dump.h>
50 #include <net/vxlan.h>
51 #include <net/checksum.h>
52 #include <net/ip6_checksum.h>
53 #include <linux/workqueue.h>
54 #include <linux/crc32.h>
55 #include <linux/crc32c.h>
56 #include <linux/prefetch.h>
57 #include <linux/zlib.h>
59 #include <linux/semaphore.h>
60 #include <linux/stringify.h>
61 #include <linux/vmalloc.h>
63 #include "bnx2x_init.h"
64 #include "bnx2x_init_ops.h"
65 #include "bnx2x_cmn.h"
66 #include "bnx2x_vfpf.h"
67 #include "bnx2x_dcb.h"
69 #include <linux/firmware.h>
70 #include "bnx2x_fw_file_hdr.h"
72 #define FW_FILE_VERSION \
73 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
74 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
75 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
76 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
77 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
78 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
79 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
81 /* Time in jiffies before concluding the transmitter is hung */
82 #define TX_TIMEOUT (5*HZ)
84 static char version
[] =
85 "QLogic 5771x/578xx 10/20-Gigabit Ethernet Driver "
86 DRV_MODULE_NAME
" " DRV_MODULE_VERSION
" (" DRV_MODULE_RELDATE
")\n";
88 MODULE_AUTHOR("Eliezer Tamir");
89 MODULE_DESCRIPTION("QLogic "
90 "BCM57710/57711/57711E/"
91 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
92 "57840/57840_MF Driver");
93 MODULE_LICENSE("GPL");
94 MODULE_VERSION(DRV_MODULE_VERSION
);
95 MODULE_FIRMWARE(FW_FILE_NAME_E1
);
96 MODULE_FIRMWARE(FW_FILE_NAME_E1H
);
97 MODULE_FIRMWARE(FW_FILE_NAME_E2
);
100 module_param_named(num_queues
, bnx2x_num_queues
, int, S_IRUGO
);
101 MODULE_PARM_DESC(num_queues
,
102 " Set number of queues (default is as a number of CPUs)");
104 static int disable_tpa
;
105 module_param(disable_tpa
, int, S_IRUGO
);
106 MODULE_PARM_DESC(disable_tpa
, " Disable the TPA (LRO) feature");
109 module_param(int_mode
, int, S_IRUGO
);
110 MODULE_PARM_DESC(int_mode
, " Force interrupt mode other than MSI-X "
113 static int dropless_fc
;
114 module_param(dropless_fc
, int, S_IRUGO
);
115 MODULE_PARM_DESC(dropless_fc
, " Pause on exhausted host ring");
117 static int mrrs
= -1;
118 module_param(mrrs
, int, S_IRUGO
);
119 MODULE_PARM_DESC(mrrs
, " Force Max Read Req Size (0..3) (for debug)");
122 module_param(debug
, int, S_IRUGO
);
123 MODULE_PARM_DESC(debug
, " Default debug msglevel");
125 static struct workqueue_struct
*bnx2x_wq
;
126 struct workqueue_struct
*bnx2x_iov_wq
;
128 struct bnx2x_mac_vals
{
139 enum bnx2x_board_type
{
163 /* indexed by board_type, above */
167 [BCM57710
] = { "QLogic BCM57710 10 Gigabit PCIe [Everest]" },
168 [BCM57711
] = { "QLogic BCM57711 10 Gigabit PCIe" },
169 [BCM57711E
] = { "QLogic BCM57711E 10 Gigabit PCIe" },
170 [BCM57712
] = { "QLogic BCM57712 10 Gigabit Ethernet" },
171 [BCM57712_MF
] = { "QLogic BCM57712 10 Gigabit Ethernet Multi Function" },
172 [BCM57712_VF
] = { "QLogic BCM57712 10 Gigabit Ethernet Virtual Function" },
173 [BCM57800
] = { "QLogic BCM57800 10 Gigabit Ethernet" },
174 [BCM57800_MF
] = { "QLogic BCM57800 10 Gigabit Ethernet Multi Function" },
175 [BCM57800_VF
] = { "QLogic BCM57800 10 Gigabit Ethernet Virtual Function" },
176 [BCM57810
] = { "QLogic BCM57810 10 Gigabit Ethernet" },
177 [BCM57810_MF
] = { "QLogic BCM57810 10 Gigabit Ethernet Multi Function" },
178 [BCM57810_VF
] = { "QLogic BCM57810 10 Gigabit Ethernet Virtual Function" },
179 [BCM57840_4_10
] = { "QLogic BCM57840 10 Gigabit Ethernet" },
180 [BCM57840_2_20
] = { "QLogic BCM57840 20 Gigabit Ethernet" },
181 [BCM57840_MF
] = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" },
182 [BCM57840_VF
] = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" },
183 [BCM57811
] = { "QLogic BCM57811 10 Gigabit Ethernet" },
184 [BCM57811_MF
] = { "QLogic BCM57811 10 Gigabit Ethernet Multi Function" },
185 [BCM57840_O
] = { "QLogic BCM57840 10/20 Gigabit Ethernet" },
186 [BCM57840_MFO
] = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" },
187 [BCM57811_VF
] = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" }
190 #ifndef PCI_DEVICE_ID_NX2_57710
191 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
193 #ifndef PCI_DEVICE_ID_NX2_57711
194 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
196 #ifndef PCI_DEVICE_ID_NX2_57711E
197 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
199 #ifndef PCI_DEVICE_ID_NX2_57712
200 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
202 #ifndef PCI_DEVICE_ID_NX2_57712_MF
203 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
205 #ifndef PCI_DEVICE_ID_NX2_57712_VF
206 #define PCI_DEVICE_ID_NX2_57712_VF CHIP_NUM_57712_VF
208 #ifndef PCI_DEVICE_ID_NX2_57800
209 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
211 #ifndef PCI_DEVICE_ID_NX2_57800_MF
212 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
214 #ifndef PCI_DEVICE_ID_NX2_57800_VF
215 #define PCI_DEVICE_ID_NX2_57800_VF CHIP_NUM_57800_VF
217 #ifndef PCI_DEVICE_ID_NX2_57810
218 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
220 #ifndef PCI_DEVICE_ID_NX2_57810_MF
221 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
223 #ifndef PCI_DEVICE_ID_NX2_57840_O
224 #define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE
226 #ifndef PCI_DEVICE_ID_NX2_57810_VF
227 #define PCI_DEVICE_ID_NX2_57810_VF CHIP_NUM_57810_VF
229 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
230 #define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10
232 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
233 #define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20
235 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
236 #define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE
238 #ifndef PCI_DEVICE_ID_NX2_57840_MF
239 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
241 #ifndef PCI_DEVICE_ID_NX2_57840_VF
242 #define PCI_DEVICE_ID_NX2_57840_VF CHIP_NUM_57840_VF
244 #ifndef PCI_DEVICE_ID_NX2_57811
245 #define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811
247 #ifndef PCI_DEVICE_ID_NX2_57811_MF
248 #define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF
250 #ifndef PCI_DEVICE_ID_NX2_57811_VF
251 #define PCI_DEVICE_ID_NX2_57811_VF CHIP_NUM_57811_VF
254 static const struct pci_device_id bnx2x_pci_tbl
[] = {
255 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57710
), BCM57710
},
256 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57711
), BCM57711
},
257 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57711E
), BCM57711E
},
258 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57712
), BCM57712
},
259 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57712_MF
), BCM57712_MF
},
260 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57712_VF
), BCM57712_VF
},
261 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57800
), BCM57800
},
262 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57800_MF
), BCM57800_MF
},
263 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57800_VF
), BCM57800_VF
},
264 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57810
), BCM57810
},
265 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57810_MF
), BCM57810_MF
},
266 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57840_O
), BCM57840_O
},
267 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57840_4_10
), BCM57840_4_10
},
268 { PCI_VDEVICE(QLOGIC
, PCI_DEVICE_ID_NX2_57840_4_10
), BCM57840_4_10
},
269 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57840_2_20
), BCM57840_2_20
},
270 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57810_VF
), BCM57810_VF
},
271 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57840_MFO
), BCM57840_MFO
},
272 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57840_MF
), BCM57840_MF
},
273 { PCI_VDEVICE(QLOGIC
, PCI_DEVICE_ID_NX2_57840_MF
), BCM57840_MF
},
274 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57840_VF
), BCM57840_VF
},
275 { PCI_VDEVICE(QLOGIC
, PCI_DEVICE_ID_NX2_57840_VF
), BCM57840_VF
},
276 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57811
), BCM57811
},
277 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57811_MF
), BCM57811_MF
},
278 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57811_VF
), BCM57811_VF
},
282 MODULE_DEVICE_TABLE(pci
, bnx2x_pci_tbl
);
284 /* Global resources for unloading a previously loaded device */
285 #define BNX2X_PREV_WAIT_NEEDED 1
286 static DEFINE_SEMAPHORE(bnx2x_prev_sem
);
287 static LIST_HEAD(bnx2x_prev_list
);
289 /* Forward declaration */
290 static struct cnic_eth_dev
*bnx2x_cnic_probe(struct net_device
*dev
);
291 static u32
bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath
*fp
);
292 static int bnx2x_set_storm_rx_mode(struct bnx2x
*bp
);
294 /****************************************************************************
295 * General service functions
296 ****************************************************************************/
298 static int bnx2x_hwtstamp_ioctl(struct bnx2x
*bp
, struct ifreq
*ifr
);
300 static void __storm_memset_dma_mapping(struct bnx2x
*bp
,
301 u32 addr
, dma_addr_t mapping
)
303 REG_WR(bp
, addr
, U64_LO(mapping
));
304 REG_WR(bp
, addr
+ 4, U64_HI(mapping
));
307 static void storm_memset_spq_addr(struct bnx2x
*bp
,
308 dma_addr_t mapping
, u16 abs_fid
)
310 u32 addr
= XSEM_REG_FAST_MEMORY
+
311 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid
);
313 __storm_memset_dma_mapping(bp
, addr
, mapping
);
316 static void storm_memset_vf_to_pf(struct bnx2x
*bp
, u16 abs_fid
,
319 REG_WR8(bp
, BAR_XSTRORM_INTMEM
+ XSTORM_VF_TO_PF_OFFSET(abs_fid
),
321 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+ CSTORM_VF_TO_PF_OFFSET(abs_fid
),
323 REG_WR8(bp
, BAR_TSTRORM_INTMEM
+ TSTORM_VF_TO_PF_OFFSET(abs_fid
),
325 REG_WR8(bp
, BAR_USTRORM_INTMEM
+ USTORM_VF_TO_PF_OFFSET(abs_fid
),
329 static void storm_memset_func_en(struct bnx2x
*bp
, u16 abs_fid
,
332 REG_WR8(bp
, BAR_XSTRORM_INTMEM
+ XSTORM_FUNC_EN_OFFSET(abs_fid
),
334 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+ CSTORM_FUNC_EN_OFFSET(abs_fid
),
336 REG_WR8(bp
, BAR_TSTRORM_INTMEM
+ TSTORM_FUNC_EN_OFFSET(abs_fid
),
338 REG_WR8(bp
, BAR_USTRORM_INTMEM
+ USTORM_FUNC_EN_OFFSET(abs_fid
),
342 static void storm_memset_eq_data(struct bnx2x
*bp
,
343 struct event_ring_data
*eq_data
,
346 size_t size
= sizeof(struct event_ring_data
);
348 u32 addr
= BAR_CSTRORM_INTMEM
+ CSTORM_EVENT_RING_DATA_OFFSET(pfid
);
350 __storm_memset_struct(bp
, addr
, size
, (u32
*)eq_data
);
353 static void storm_memset_eq_prod(struct bnx2x
*bp
, u16 eq_prod
,
356 u32 addr
= BAR_CSTRORM_INTMEM
+ CSTORM_EVENT_RING_PROD_OFFSET(pfid
);
357 REG_WR16(bp
, addr
, eq_prod
);
361 * locking is done by mcp
363 static void bnx2x_reg_wr_ind(struct bnx2x
*bp
, u32 addr
, u32 val
)
365 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_ADDRESS
, addr
);
366 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_DATA
, val
);
367 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_ADDRESS
,
368 PCICFG_VENDOR_ID_OFFSET
);
371 static u32
bnx2x_reg_rd_ind(struct bnx2x
*bp
, u32 addr
)
375 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_ADDRESS
, addr
);
376 pci_read_config_dword(bp
->pdev
, PCICFG_GRC_DATA
, &val
);
377 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_ADDRESS
,
378 PCICFG_VENDOR_ID_OFFSET
);
383 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
384 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
385 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
386 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
387 #define DMAE_DP_DST_NONE "dst_addr [none]"
389 static void bnx2x_dp_dmae(struct bnx2x
*bp
,
390 struct dmae_command
*dmae
, int msglvl
)
392 u32 src_type
= dmae
->opcode
& DMAE_COMMAND_SRC
;
395 switch (dmae
->opcode
& DMAE_COMMAND_DST
) {
396 case DMAE_CMD_DST_PCI
:
397 if (src_type
== DMAE_CMD_SRC_PCI
)
398 DP(msglvl
, "DMAE: opcode 0x%08x\n"
399 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
400 "comp_addr [%x:%08x], comp_val 0x%08x\n",
401 dmae
->opcode
, dmae
->src_addr_hi
, dmae
->src_addr_lo
,
402 dmae
->len
, dmae
->dst_addr_hi
, dmae
->dst_addr_lo
,
403 dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
406 DP(msglvl
, "DMAE: opcode 0x%08x\n"
407 "src [%08x], len [%d*4], dst [%x:%08x]\n"
408 "comp_addr [%x:%08x], comp_val 0x%08x\n",
409 dmae
->opcode
, dmae
->src_addr_lo
>> 2,
410 dmae
->len
, dmae
->dst_addr_hi
, dmae
->dst_addr_lo
,
411 dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
414 case DMAE_CMD_DST_GRC
:
415 if (src_type
== DMAE_CMD_SRC_PCI
)
416 DP(msglvl
, "DMAE: opcode 0x%08x\n"
417 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
418 "comp_addr [%x:%08x], comp_val 0x%08x\n",
419 dmae
->opcode
, dmae
->src_addr_hi
, dmae
->src_addr_lo
,
420 dmae
->len
, dmae
->dst_addr_lo
>> 2,
421 dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
424 DP(msglvl
, "DMAE: opcode 0x%08x\n"
425 "src [%08x], len [%d*4], dst [%08x]\n"
426 "comp_addr [%x:%08x], comp_val 0x%08x\n",
427 dmae
->opcode
, dmae
->src_addr_lo
>> 2,
428 dmae
->len
, dmae
->dst_addr_lo
>> 2,
429 dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
433 if (src_type
== DMAE_CMD_SRC_PCI
)
434 DP(msglvl
, "DMAE: opcode 0x%08x\n"
435 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n"
436 "comp_addr [%x:%08x] comp_val 0x%08x\n",
437 dmae
->opcode
, dmae
->src_addr_hi
, dmae
->src_addr_lo
,
438 dmae
->len
, dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
441 DP(msglvl
, "DMAE: opcode 0x%08x\n"
442 "src_addr [%08x] len [%d * 4] dst_addr [none]\n"
443 "comp_addr [%x:%08x] comp_val 0x%08x\n",
444 dmae
->opcode
, dmae
->src_addr_lo
>> 2,
445 dmae
->len
, dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
450 for (i
= 0; i
< (sizeof(struct dmae_command
)/4); i
++)
451 DP(msglvl
, "DMAE RAW [%02d]: 0x%08x\n",
452 i
, *(((u32
*)dmae
) + i
));
455 /* copy command into DMAE command memory and set DMAE command go */
456 void bnx2x_post_dmae(struct bnx2x
*bp
, struct dmae_command
*dmae
, int idx
)
461 cmd_offset
= (DMAE_REG_CMD_MEM
+ sizeof(struct dmae_command
) * idx
);
462 for (i
= 0; i
< (sizeof(struct dmae_command
)/4); i
++) {
463 REG_WR(bp
, cmd_offset
+ i
*4, *(((u32
*)dmae
) + i
));
465 REG_WR(bp
, dmae_reg_go_c
[idx
], 1);
468 u32
bnx2x_dmae_opcode_add_comp(u32 opcode
, u8 comp_type
)
470 return opcode
| ((comp_type
<< DMAE_COMMAND_C_DST_SHIFT
) |
474 u32
bnx2x_dmae_opcode_clr_src_reset(u32 opcode
)
476 return opcode
& ~DMAE_CMD_SRC_RESET
;
479 u32
bnx2x_dmae_opcode(struct bnx2x
*bp
, u8 src_type
, u8 dst_type
,
480 bool with_comp
, u8 comp_type
)
484 opcode
|= ((src_type
<< DMAE_COMMAND_SRC_SHIFT
) |
485 (dst_type
<< DMAE_COMMAND_DST_SHIFT
));
487 opcode
|= (DMAE_CMD_SRC_RESET
| DMAE_CMD_DST_RESET
);
489 opcode
|= (BP_PORT(bp
) ? DMAE_CMD_PORT_1
: DMAE_CMD_PORT_0
);
490 opcode
|= ((BP_VN(bp
) << DMAE_CMD_E1HVN_SHIFT
) |
491 (BP_VN(bp
) << DMAE_COMMAND_DST_VN_SHIFT
));
492 opcode
|= (DMAE_COM_SET_ERR
<< DMAE_COMMAND_ERR_POLICY_SHIFT
);
495 opcode
|= DMAE_CMD_ENDIANITY_B_DW_SWAP
;
497 opcode
|= DMAE_CMD_ENDIANITY_DW_SWAP
;
500 opcode
= bnx2x_dmae_opcode_add_comp(opcode
, comp_type
);
504 void bnx2x_prep_dmae_with_comp(struct bnx2x
*bp
,
505 struct dmae_command
*dmae
,
506 u8 src_type
, u8 dst_type
)
508 memset(dmae
, 0, sizeof(struct dmae_command
));
511 dmae
->opcode
= bnx2x_dmae_opcode(bp
, src_type
, dst_type
,
512 true, DMAE_COMP_PCI
);
514 /* fill in the completion parameters */
515 dmae
->comp_addr_lo
= U64_LO(bnx2x_sp_mapping(bp
, wb_comp
));
516 dmae
->comp_addr_hi
= U64_HI(bnx2x_sp_mapping(bp
, wb_comp
));
517 dmae
->comp_val
= DMAE_COMP_VAL
;
520 /* issue a dmae command over the init-channel and wait for completion */
521 int bnx2x_issue_dmae_with_comp(struct bnx2x
*bp
, struct dmae_command
*dmae
,
524 int cnt
= CHIP_REV_IS_SLOW(bp
) ? (400000) : 4000;
527 bnx2x_dp_dmae(bp
, dmae
, BNX2X_MSG_DMAE
);
529 /* Lock the dmae channel. Disable BHs to prevent a dead-lock
530 * as long as this code is called both from syscall context and
531 * from ndo_set_rx_mode() flow that may be called from BH.
534 spin_lock_bh(&bp
->dmae_lock
);
536 /* reset completion */
539 /* post the command on the channel used for initializations */
540 bnx2x_post_dmae(bp
, dmae
, INIT_DMAE_C(bp
));
542 /* wait for completion */
544 while ((*comp
& ~DMAE_PCI_ERR_FLAG
) != DMAE_COMP_VAL
) {
547 (bp
->recovery_state
!= BNX2X_RECOVERY_DONE
&&
548 bp
->recovery_state
!= BNX2X_RECOVERY_NIC_LOADING
)) {
549 BNX2X_ERR("DMAE timeout!\n");
556 if (*comp
& DMAE_PCI_ERR_FLAG
) {
557 BNX2X_ERR("DMAE PCI error!\n");
563 spin_unlock_bh(&bp
->dmae_lock
);
568 void bnx2x_write_dmae(struct bnx2x
*bp
, dma_addr_t dma_addr
, u32 dst_addr
,
572 struct dmae_command dmae
;
574 if (!bp
->dmae_ready
) {
575 u32
*data
= bnx2x_sp(bp
, wb_data
[0]);
578 bnx2x_init_ind_wr(bp
, dst_addr
, data
, len32
);
580 bnx2x_init_str_wr(bp
, dst_addr
, data
, len32
);
584 /* set opcode and fixed command fields */
585 bnx2x_prep_dmae_with_comp(bp
, &dmae
, DMAE_SRC_PCI
, DMAE_DST_GRC
);
587 /* fill in addresses and len */
588 dmae
.src_addr_lo
= U64_LO(dma_addr
);
589 dmae
.src_addr_hi
= U64_HI(dma_addr
);
590 dmae
.dst_addr_lo
= dst_addr
>> 2;
591 dmae
.dst_addr_hi
= 0;
594 /* issue the command and wait for completion */
595 rc
= bnx2x_issue_dmae_with_comp(bp
, &dmae
, bnx2x_sp(bp
, wb_comp
));
597 BNX2X_ERR("DMAE returned failure %d\n", rc
);
598 #ifdef BNX2X_STOP_ON_ERROR
604 void bnx2x_read_dmae(struct bnx2x
*bp
, u32 src_addr
, u32 len32
)
607 struct dmae_command dmae
;
609 if (!bp
->dmae_ready
) {
610 u32
*data
= bnx2x_sp(bp
, wb_data
[0]);
614 for (i
= 0; i
< len32
; i
++)
615 data
[i
] = bnx2x_reg_rd_ind(bp
, src_addr
+ i
*4);
617 for (i
= 0; i
< len32
; i
++)
618 data
[i
] = REG_RD(bp
, src_addr
+ i
*4);
623 /* set opcode and fixed command fields */
624 bnx2x_prep_dmae_with_comp(bp
, &dmae
, DMAE_SRC_GRC
, DMAE_DST_PCI
);
626 /* fill in addresses and len */
627 dmae
.src_addr_lo
= src_addr
>> 2;
628 dmae
.src_addr_hi
= 0;
629 dmae
.dst_addr_lo
= U64_LO(bnx2x_sp_mapping(bp
, wb_data
));
630 dmae
.dst_addr_hi
= U64_HI(bnx2x_sp_mapping(bp
, wb_data
));
633 /* issue the command and wait for completion */
634 rc
= bnx2x_issue_dmae_with_comp(bp
, &dmae
, bnx2x_sp(bp
, wb_comp
));
636 BNX2X_ERR("DMAE returned failure %d\n", rc
);
637 #ifdef BNX2X_STOP_ON_ERROR
643 static void bnx2x_write_dmae_phys_len(struct bnx2x
*bp
, dma_addr_t phys_addr
,
646 int dmae_wr_max
= DMAE_LEN32_WR_MAX(bp
);
649 while (len
> dmae_wr_max
) {
650 bnx2x_write_dmae(bp
, phys_addr
+ offset
,
651 addr
+ offset
, dmae_wr_max
);
652 offset
+= dmae_wr_max
* 4;
656 bnx2x_write_dmae(bp
, phys_addr
+ offset
, addr
+ offset
, len
);
668 #define REGS_IN_ENTRY 4
670 static inline int bnx2x_get_assert_list_entry(struct bnx2x
*bp
,
676 return XSTORM_ASSERT_LIST_OFFSET(entry
);
678 return TSTORM_ASSERT_LIST_OFFSET(entry
);
680 return CSTORM_ASSERT_LIST_OFFSET(entry
);
682 return USTORM_ASSERT_LIST_OFFSET(entry
);
685 BNX2X_ERR("unknown storm\n");
690 static int bnx2x_mc_assert(struct bnx2x
*bp
)
695 u32 regs
[REGS_IN_ENTRY
];
696 u32 bar_storm_intmem
[STORMS_NUM
] = {
702 u32 storm_assert_list_index
[STORMS_NUM
] = {
703 XSTORM_ASSERT_LIST_INDEX_OFFSET
,
704 TSTORM_ASSERT_LIST_INDEX_OFFSET
,
705 CSTORM_ASSERT_LIST_INDEX_OFFSET
,
706 USTORM_ASSERT_LIST_INDEX_OFFSET
708 char *storms_string
[STORMS_NUM
] = {
715 for (storm
= XSTORM
; storm
< MAX_STORMS
; storm
++) {
716 last_idx
= REG_RD8(bp
, bar_storm_intmem
[storm
] +
717 storm_assert_list_index
[storm
]);
719 BNX2X_ERR("%s_ASSERT_LIST_INDEX 0x%x\n",
720 storms_string
[storm
], last_idx
);
722 /* print the asserts */
723 for (i
= 0; i
< STROM_ASSERT_ARRAY_SIZE
; i
++) {
724 /* read a single assert entry */
725 for (j
= 0; j
< REGS_IN_ENTRY
; j
++)
726 regs
[j
] = REG_RD(bp
, bar_storm_intmem
[storm
] +
727 bnx2x_get_assert_list_entry(bp
,
732 /* log entry if it contains a valid assert */
733 if (regs
[0] != COMMON_ASM_INVALID_ASSERT_OPCODE
) {
734 BNX2X_ERR("%s_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
735 storms_string
[storm
], i
, regs
[3],
736 regs
[2], regs
[1], regs
[0]);
744 BNX2X_ERR("Chip Revision: %s, FW Version: %d_%d_%d\n",
745 CHIP_IS_E1(bp
) ? "everest1" :
746 CHIP_IS_E1H(bp
) ? "everest1h" :
747 CHIP_IS_E2(bp
) ? "everest2" : "everest3",
748 BCM_5710_FW_MAJOR_VERSION
,
749 BCM_5710_FW_MINOR_VERSION
,
750 BCM_5710_FW_REVISION_VERSION
);
755 #define MCPR_TRACE_BUFFER_SIZE (0x800)
756 #define SCRATCH_BUFFER_SIZE(bp) \
757 (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
759 void bnx2x_fw_dump_lvl(struct bnx2x
*bp
, const char *lvl
)
765 u32 trace_shmem_base
;
767 BNX2X_ERR("NO MCP - can not dump\n");
770 netdev_printk(lvl
, bp
->dev
, "bc %d.%d.%d\n",
771 (bp
->common
.bc_ver
& 0xff0000) >> 16,
772 (bp
->common
.bc_ver
& 0xff00) >> 8,
773 (bp
->common
.bc_ver
& 0xff));
775 if (pci_channel_offline(bp
->pdev
)) {
776 BNX2X_ERR("Cannot dump MCP info while in PCI error\n");
780 val
= REG_RD(bp
, MCP_REG_MCPR_CPU_PROGRAM_COUNTER
);
781 if (val
== REG_RD(bp
, MCP_REG_MCPR_CPU_PROGRAM_COUNTER
))
782 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl
, val
);
784 if (BP_PATH(bp
) == 0)
785 trace_shmem_base
= bp
->common
.shmem_base
;
787 trace_shmem_base
= SHMEM2_RD(bp
, other_shmem_base_addr
);
790 if (trace_shmem_base
< MCPR_SCRATCH_BASE(bp
) + MCPR_TRACE_BUFFER_SIZE
||
791 trace_shmem_base
>= MCPR_SCRATCH_BASE(bp
) +
792 SCRATCH_BUFFER_SIZE(bp
)) {
793 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
798 addr
= trace_shmem_base
- MCPR_TRACE_BUFFER_SIZE
;
800 /* validate TRCB signature */
801 mark
= REG_RD(bp
, addr
);
802 if (mark
!= MFW_TRACE_SIGNATURE
) {
803 BNX2X_ERR("Trace buffer signature is missing.");
807 /* read cyclic buffer pointer */
809 mark
= REG_RD(bp
, addr
);
810 mark
= MCPR_SCRATCH_BASE(bp
) + ((mark
+ 0x3) & ~0x3) - 0x08000000;
811 if (mark
>= trace_shmem_base
|| mark
< addr
+ 4) {
812 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
815 printk("%s" "begin fw dump (mark 0x%x)\n", lvl
, mark
);
819 /* dump buffer after the mark */
820 for (offset
= mark
; offset
< trace_shmem_base
; offset
+= 0x8*4) {
821 for (word
= 0; word
< 8; word
++)
822 data
[word
] = htonl(REG_RD(bp
, offset
+ 4*word
));
824 pr_cont("%s", (char *)data
);
827 /* dump buffer before the mark */
828 for (offset
= addr
+ 4; offset
<= mark
; offset
+= 0x8*4) {
829 for (word
= 0; word
< 8; word
++)
830 data
[word
] = htonl(REG_RD(bp
, offset
+ 4*word
));
832 pr_cont("%s", (char *)data
);
834 printk("%s" "end of fw dump\n", lvl
);
837 static void bnx2x_fw_dump(struct bnx2x
*bp
)
839 bnx2x_fw_dump_lvl(bp
, KERN_ERR
);
842 static void bnx2x_hc_int_disable(struct bnx2x
*bp
)
844 int port
= BP_PORT(bp
);
845 u32 addr
= port
? HC_REG_CONFIG_1
: HC_REG_CONFIG_0
;
846 u32 val
= REG_RD(bp
, addr
);
848 /* in E1 we must use only PCI configuration space to disable
849 * MSI/MSIX capability
850 * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
852 if (CHIP_IS_E1(bp
)) {
853 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
854 * Use mask register to prevent from HC sending interrupts
855 * after we exit the function
857 REG_WR(bp
, HC_REG_INT_MASK
+ port
*4, 0);
859 val
&= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0
|
860 HC_CONFIG_0_REG_INT_LINE_EN_0
|
861 HC_CONFIG_0_REG_ATTN_BIT_EN_0
);
863 val
&= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0
|
864 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
|
865 HC_CONFIG_0_REG_INT_LINE_EN_0
|
866 HC_CONFIG_0_REG_ATTN_BIT_EN_0
);
869 "write %x to HC %d (addr 0x%x)\n",
872 /* flush all outstanding writes */
875 REG_WR(bp
, addr
, val
);
876 if (REG_RD(bp
, addr
) != val
)
877 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
880 static void bnx2x_igu_int_disable(struct bnx2x
*bp
)
882 u32 val
= REG_RD(bp
, IGU_REG_PF_CONFIGURATION
);
884 val
&= ~(IGU_PF_CONF_MSI_MSIX_EN
|
885 IGU_PF_CONF_INT_LINE_EN
|
886 IGU_PF_CONF_ATTN_BIT_EN
);
888 DP(NETIF_MSG_IFDOWN
, "write %x to IGU\n", val
);
890 /* flush all outstanding writes */
893 REG_WR(bp
, IGU_REG_PF_CONFIGURATION
, val
);
894 if (REG_RD(bp
, IGU_REG_PF_CONFIGURATION
) != val
)
895 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
898 static void bnx2x_int_disable(struct bnx2x
*bp
)
900 if (bp
->common
.int_block
== INT_BLOCK_HC
)
901 bnx2x_hc_int_disable(bp
);
903 bnx2x_igu_int_disable(bp
);
906 void bnx2x_panic_dump(struct bnx2x
*bp
, bool disable_int
)
910 struct hc_sp_status_block_data sp_sb_data
;
911 int func
= BP_FUNC(bp
);
912 #ifdef BNX2X_STOP_ON_ERROR
913 u16 start
= 0, end
= 0;
916 if (IS_PF(bp
) && disable_int
)
917 bnx2x_int_disable(bp
);
919 bp
->stats_state
= STATS_STATE_DISABLED
;
920 bp
->eth_stats
.unrecoverable_error
++;
921 DP(BNX2X_MSG_STATS
, "stats_state - DISABLED\n");
923 BNX2X_ERR("begin crash dump -----------------\n");
928 struct host_sp_status_block
*def_sb
= bp
->def_status_blk
;
929 int data_size
, cstorm_offset
;
931 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
932 bp
->def_idx
, bp
->def_att_idx
, bp
->attn_state
,
933 bp
->spq_prod_idx
, bp
->stats_counter
);
934 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
935 def_sb
->atten_status_block
.attn_bits
,
936 def_sb
->atten_status_block
.attn_bits_ack
,
937 def_sb
->atten_status_block
.status_block_id
,
938 def_sb
->atten_status_block
.attn_bits_index
);
940 for (i
= 0; i
< HC_SP_SB_MAX_INDICES
; i
++)
942 def_sb
->sp_sb
.index_values
[i
],
943 (i
== HC_SP_SB_MAX_INDICES
- 1) ? ") " : " ");
945 data_size
= sizeof(struct hc_sp_status_block_data
) /
947 cstorm_offset
= CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func
);
948 for (i
= 0; i
< data_size
; i
++)
949 *((u32
*)&sp_sb_data
+ i
) =
950 REG_RD(bp
, BAR_CSTRORM_INTMEM
+ cstorm_offset
+
953 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
954 sp_sb_data
.igu_sb_id
,
955 sp_sb_data
.igu_seg_id
,
956 sp_sb_data
.p_func
.pf_id
,
957 sp_sb_data
.p_func
.vnic_id
,
958 sp_sb_data
.p_func
.vf_id
,
959 sp_sb_data
.p_func
.vf_valid
,
963 for_each_eth_queue(bp
, i
) {
964 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
966 struct hc_status_block_data_e2 sb_data_e2
;
967 struct hc_status_block_data_e1x sb_data_e1x
;
968 struct hc_status_block_sm
*hc_sm_p
=
970 sb_data_e1x
.common
.state_machine
:
971 sb_data_e2
.common
.state_machine
;
972 struct hc_index_data
*hc_index_p
=
974 sb_data_e1x
.index_data
:
975 sb_data_e2
.index_data
;
978 struct bnx2x_fp_txdata txdata
;
987 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
988 i
, fp
->rx_bd_prod
, fp
->rx_bd_cons
,
990 fp
->rx_comp_cons
, le16_to_cpu(*fp
->rx_cons_sb
));
991 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n",
992 fp
->rx_sge_prod
, fp
->last_max_sge
,
993 le16_to_cpu(fp
->fp_hc_idx
));
996 for_each_cos_in_tx_queue(fp
, cos
)
998 if (!fp
->txdata_ptr
[cos
])
1001 txdata
= *fp
->txdata_ptr
[cos
];
1003 if (!txdata
.tx_cons_sb
)
1006 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n",
1007 i
, txdata
.tx_pkt_prod
,
1008 txdata
.tx_pkt_cons
, txdata
.tx_bd_prod
,
1010 le16_to_cpu(*txdata
.tx_cons_sb
));
1013 loop
= CHIP_IS_E1x(bp
) ?
1014 HC_SB_MAX_INDICES_E1X
: HC_SB_MAX_INDICES_E2
;
1021 BNX2X_ERR(" run indexes (");
1022 for (j
= 0; j
< HC_SB_MAX_SM
; j
++)
1024 fp
->sb_running_index
[j
],
1025 (j
== HC_SB_MAX_SM
- 1) ? ")" : " ");
1027 BNX2X_ERR(" indexes (");
1028 for (j
= 0; j
< loop
; j
++)
1030 fp
->sb_index_values
[j
],
1031 (j
== loop
- 1) ? ")" : " ");
1033 /* VF cannot access FW refelection for status block */
1038 data_size
= CHIP_IS_E1x(bp
) ?
1039 sizeof(struct hc_status_block_data_e1x
) :
1040 sizeof(struct hc_status_block_data_e2
);
1041 data_size
/= sizeof(u32
);
1042 sb_data_p
= CHIP_IS_E1x(bp
) ?
1043 (u32
*)&sb_data_e1x
:
1045 /* copy sb data in here */
1046 for (j
= 0; j
< data_size
; j
++)
1047 *(sb_data_p
+ j
) = REG_RD(bp
, BAR_CSTRORM_INTMEM
+
1048 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp
->fw_sb_id
) +
1051 if (!CHIP_IS_E1x(bp
)) {
1052 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
1053 sb_data_e2
.common
.p_func
.pf_id
,
1054 sb_data_e2
.common
.p_func
.vf_id
,
1055 sb_data_e2
.common
.p_func
.vf_valid
,
1056 sb_data_e2
.common
.p_func
.vnic_id
,
1057 sb_data_e2
.common
.same_igu_sb_1b
,
1058 sb_data_e2
.common
.state
);
1060 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
1061 sb_data_e1x
.common
.p_func
.pf_id
,
1062 sb_data_e1x
.common
.p_func
.vf_id
,
1063 sb_data_e1x
.common
.p_func
.vf_valid
,
1064 sb_data_e1x
.common
.p_func
.vnic_id
,
1065 sb_data_e1x
.common
.same_igu_sb_1b
,
1066 sb_data_e1x
.common
.state
);
1070 for (j
= 0; j
< HC_SB_MAX_SM
; j
++) {
1071 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1072 j
, hc_sm_p
[j
].__flags
,
1073 hc_sm_p
[j
].igu_sb_id
,
1074 hc_sm_p
[j
].igu_seg_id
,
1075 hc_sm_p
[j
].time_to_expire
,
1076 hc_sm_p
[j
].timer_value
);
1080 for (j
= 0; j
< loop
; j
++) {
1081 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j
,
1082 hc_index_p
[j
].flags
,
1083 hc_index_p
[j
].timeout
);
1087 #ifdef BNX2X_STOP_ON_ERROR
1090 BNX2X_ERR("eq cons %x prod %x\n", bp
->eq_cons
, bp
->eq_prod
);
1091 for (i
= 0; i
< NUM_EQ_DESC
; i
++) {
1092 u32
*data
= (u32
*)&bp
->eq_ring
[i
].message
.data
;
1094 BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1095 i
, bp
->eq_ring
[i
].message
.opcode
,
1096 bp
->eq_ring
[i
].message
.error
);
1097 BNX2X_ERR("data: %x %x %x\n",
1098 data
[0], data
[1], data
[2]);
1104 for_each_valid_rx_queue(bp
, i
) {
1105 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
1110 if (!fp
->rx_cons_sb
)
1113 start
= RX_BD(le16_to_cpu(*fp
->rx_cons_sb
) - 10);
1114 end
= RX_BD(le16_to_cpu(*fp
->rx_cons_sb
) + 503);
1115 for (j
= start
; j
!= end
; j
= RX_BD(j
+ 1)) {
1116 u32
*rx_bd
= (u32
*)&fp
->rx_desc_ring
[j
];
1117 struct sw_rx_bd
*sw_bd
= &fp
->rx_buf_ring
[j
];
1119 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
1120 i
, j
, rx_bd
[1], rx_bd
[0], sw_bd
->data
);
1123 start
= RX_SGE(fp
->rx_sge_prod
);
1124 end
= RX_SGE(fp
->last_max_sge
);
1125 for (j
= start
; j
!= end
; j
= RX_SGE(j
+ 1)) {
1126 u32
*rx_sge
= (u32
*)&fp
->rx_sge_ring
[j
];
1127 struct sw_rx_page
*sw_page
= &fp
->rx_page_ring
[j
];
1129 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
1130 i
, j
, rx_sge
[1], rx_sge
[0], sw_page
->page
);
1133 start
= RCQ_BD(fp
->rx_comp_cons
- 10);
1134 end
= RCQ_BD(fp
->rx_comp_cons
+ 503);
1135 for (j
= start
; j
!= end
; j
= RCQ_BD(j
+ 1)) {
1136 u32
*cqe
= (u32
*)&fp
->rx_comp_ring
[j
];
1138 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1139 i
, j
, cqe
[0], cqe
[1], cqe
[2], cqe
[3]);
1144 for_each_valid_tx_queue(bp
, i
) {
1145 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
1150 for_each_cos_in_tx_queue(fp
, cos
) {
1151 struct bnx2x_fp_txdata
*txdata
= fp
->txdata_ptr
[cos
];
1153 if (!fp
->txdata_ptr
[cos
])
1156 if (!txdata
->tx_cons_sb
)
1159 start
= TX_BD(le16_to_cpu(*txdata
->tx_cons_sb
) - 10);
1160 end
= TX_BD(le16_to_cpu(*txdata
->tx_cons_sb
) + 245);
1161 for (j
= start
; j
!= end
; j
= TX_BD(j
+ 1)) {
1162 struct sw_tx_bd
*sw_bd
=
1163 &txdata
->tx_buf_ring
[j
];
1165 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1166 i
, cos
, j
, sw_bd
->skb
,
1170 start
= TX_BD(txdata
->tx_bd_cons
- 10);
1171 end
= TX_BD(txdata
->tx_bd_cons
+ 254);
1172 for (j
= start
; j
!= end
; j
= TX_BD(j
+ 1)) {
1173 u32
*tx_bd
= (u32
*)&txdata
->tx_desc_ring
[j
];
1175 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1176 i
, cos
, j
, tx_bd
[0], tx_bd
[1],
1177 tx_bd
[2], tx_bd
[3]);
1184 bnx2x_mc_assert(bp
);
1186 BNX2X_ERR("end crash dump -----------------\n");
1190 * FLR Support for E2
1192 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1195 #define FLR_WAIT_USEC 10000 /* 10 milliseconds */
1196 #define FLR_WAIT_INTERVAL 50 /* usec */
1197 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1199 struct pbf_pN_buf_regs
{
1206 struct pbf_pN_cmd_regs
{
1212 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x
*bp
,
1213 struct pbf_pN_buf_regs
*regs
,
1216 u32 init_crd
, crd
, crd_start
, crd_freed
, crd_freed_start
;
1217 u32 cur_cnt
= poll_count
;
1219 crd_freed
= crd_freed_start
= REG_RD(bp
, regs
->crd_freed
);
1220 crd
= crd_start
= REG_RD(bp
, regs
->crd
);
1221 init_crd
= REG_RD(bp
, regs
->init_crd
);
1223 DP(BNX2X_MSG_SP
, "INIT CREDIT[%d] : %x\n", regs
->pN
, init_crd
);
1224 DP(BNX2X_MSG_SP
, "CREDIT[%d] : s:%x\n", regs
->pN
, crd
);
1225 DP(BNX2X_MSG_SP
, "CREDIT_FREED[%d]: s:%x\n", regs
->pN
, crd_freed
);
1227 while ((crd
!= init_crd
) && ((u32
)SUB_S32(crd_freed
, crd_freed_start
) <
1228 (init_crd
- crd_start
))) {
1230 udelay(FLR_WAIT_INTERVAL
);
1231 crd
= REG_RD(bp
, regs
->crd
);
1232 crd_freed
= REG_RD(bp
, regs
->crd_freed
);
1234 DP(BNX2X_MSG_SP
, "PBF tx buffer[%d] timed out\n",
1236 DP(BNX2X_MSG_SP
, "CREDIT[%d] : c:%x\n",
1238 DP(BNX2X_MSG_SP
, "CREDIT_FREED[%d]: c:%x\n",
1239 regs
->pN
, crd_freed
);
1243 DP(BNX2X_MSG_SP
, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1244 poll_count
-cur_cnt
, FLR_WAIT_INTERVAL
, regs
->pN
);
1247 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x
*bp
,
1248 struct pbf_pN_cmd_regs
*regs
,
1251 u32 occup
, to_free
, freed
, freed_start
;
1252 u32 cur_cnt
= poll_count
;
1254 occup
= to_free
= REG_RD(bp
, regs
->lines_occup
);
1255 freed
= freed_start
= REG_RD(bp
, regs
->lines_freed
);
1257 DP(BNX2X_MSG_SP
, "OCCUPANCY[%d] : s:%x\n", regs
->pN
, occup
);
1258 DP(BNX2X_MSG_SP
, "LINES_FREED[%d] : s:%x\n", regs
->pN
, freed
);
1260 while (occup
&& ((u32
)SUB_S32(freed
, freed_start
) < to_free
)) {
1262 udelay(FLR_WAIT_INTERVAL
);
1263 occup
= REG_RD(bp
, regs
->lines_occup
);
1264 freed
= REG_RD(bp
, regs
->lines_freed
);
1266 DP(BNX2X_MSG_SP
, "PBF cmd queue[%d] timed out\n",
1268 DP(BNX2X_MSG_SP
, "OCCUPANCY[%d] : s:%x\n",
1270 DP(BNX2X_MSG_SP
, "LINES_FREED[%d] : s:%x\n",
1275 DP(BNX2X_MSG_SP
, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1276 poll_count
-cur_cnt
, FLR_WAIT_INTERVAL
, regs
->pN
);
1279 static u32
bnx2x_flr_clnup_reg_poll(struct bnx2x
*bp
, u32 reg
,
1280 u32 expected
, u32 poll_count
)
1282 u32 cur_cnt
= poll_count
;
1285 while ((val
= REG_RD(bp
, reg
)) != expected
&& cur_cnt
--)
1286 udelay(FLR_WAIT_INTERVAL
);
1291 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x
*bp
, u32 reg
,
1292 char *msg
, u32 poll_cnt
)
1294 u32 val
= bnx2x_flr_clnup_reg_poll(bp
, reg
, 0, poll_cnt
);
1296 BNX2X_ERR("%s usage count=%d\n", msg
, val
);
1302 /* Common routines with VF FLR cleanup */
1303 u32
bnx2x_flr_clnup_poll_count(struct bnx2x
*bp
)
1305 /* adjust polling timeout */
1306 if (CHIP_REV_IS_EMUL(bp
))
1307 return FLR_POLL_CNT
* 2000;
1309 if (CHIP_REV_IS_FPGA(bp
))
1310 return FLR_POLL_CNT
* 120;
1312 return FLR_POLL_CNT
;
1315 void bnx2x_tx_hw_flushed(struct bnx2x
*bp
, u32 poll_count
)
1317 struct pbf_pN_cmd_regs cmd_regs
[] = {
1318 {0, (CHIP_IS_E3B0(bp
)) ?
1319 PBF_REG_TQ_OCCUPANCY_Q0
:
1320 PBF_REG_P0_TQ_OCCUPANCY
,
1321 (CHIP_IS_E3B0(bp
)) ?
1322 PBF_REG_TQ_LINES_FREED_CNT_Q0
:
1323 PBF_REG_P0_TQ_LINES_FREED_CNT
},
1324 {1, (CHIP_IS_E3B0(bp
)) ?
1325 PBF_REG_TQ_OCCUPANCY_Q1
:
1326 PBF_REG_P1_TQ_OCCUPANCY
,
1327 (CHIP_IS_E3B0(bp
)) ?
1328 PBF_REG_TQ_LINES_FREED_CNT_Q1
:
1329 PBF_REG_P1_TQ_LINES_FREED_CNT
},
1330 {4, (CHIP_IS_E3B0(bp
)) ?
1331 PBF_REG_TQ_OCCUPANCY_LB_Q
:
1332 PBF_REG_P4_TQ_OCCUPANCY
,
1333 (CHIP_IS_E3B0(bp
)) ?
1334 PBF_REG_TQ_LINES_FREED_CNT_LB_Q
:
1335 PBF_REG_P4_TQ_LINES_FREED_CNT
}
1338 struct pbf_pN_buf_regs buf_regs
[] = {
1339 {0, (CHIP_IS_E3B0(bp
)) ?
1340 PBF_REG_INIT_CRD_Q0
:
1341 PBF_REG_P0_INIT_CRD
,
1342 (CHIP_IS_E3B0(bp
)) ?
1345 (CHIP_IS_E3B0(bp
)) ?
1346 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0
:
1347 PBF_REG_P0_INTERNAL_CRD_FREED_CNT
},
1348 {1, (CHIP_IS_E3B0(bp
)) ?
1349 PBF_REG_INIT_CRD_Q1
:
1350 PBF_REG_P1_INIT_CRD
,
1351 (CHIP_IS_E3B0(bp
)) ?
1354 (CHIP_IS_E3B0(bp
)) ?
1355 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1
:
1356 PBF_REG_P1_INTERNAL_CRD_FREED_CNT
},
1357 {4, (CHIP_IS_E3B0(bp
)) ?
1358 PBF_REG_INIT_CRD_LB_Q
:
1359 PBF_REG_P4_INIT_CRD
,
1360 (CHIP_IS_E3B0(bp
)) ?
1361 PBF_REG_CREDIT_LB_Q
:
1363 (CHIP_IS_E3B0(bp
)) ?
1364 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q
:
1365 PBF_REG_P4_INTERNAL_CRD_FREED_CNT
},
1370 /* Verify the command queues are flushed P0, P1, P4 */
1371 for (i
= 0; i
< ARRAY_SIZE(cmd_regs
); i
++)
1372 bnx2x_pbf_pN_cmd_flushed(bp
, &cmd_regs
[i
], poll_count
);
1374 /* Verify the transmission buffers are flushed P0, P1, P4 */
1375 for (i
= 0; i
< ARRAY_SIZE(buf_regs
); i
++)
1376 bnx2x_pbf_pN_buf_flushed(bp
, &buf_regs
[i
], poll_count
);
1379 #define OP_GEN_PARAM(param) \
1380 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1382 #define OP_GEN_TYPE(type) \
1383 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1385 #define OP_GEN_AGG_VECT(index) \
1386 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1388 int bnx2x_send_final_clnup(struct bnx2x
*bp
, u8 clnup_func
, u32 poll_cnt
)
1390 u32 op_gen_command
= 0;
1391 u32 comp_addr
= BAR_CSTRORM_INTMEM
+
1392 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func
);
1395 if (REG_RD(bp
, comp_addr
)) {
1396 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1400 op_gen_command
|= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX
);
1401 op_gen_command
|= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE
);
1402 op_gen_command
|= OP_GEN_AGG_VECT(clnup_func
);
1403 op_gen_command
|= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT
;
1405 DP(BNX2X_MSG_SP
, "sending FW Final cleanup\n");
1406 REG_WR(bp
, XSDM_REG_OPERATION_GEN
, op_gen_command
);
1408 if (bnx2x_flr_clnup_reg_poll(bp
, comp_addr
, 1, poll_cnt
) != 1) {
1409 BNX2X_ERR("FW final cleanup did not succeed\n");
1410 DP(BNX2X_MSG_SP
, "At timeout completion address contained %x\n",
1411 (REG_RD(bp
, comp_addr
)));
1415 /* Zero completion for next FLR */
1416 REG_WR(bp
, comp_addr
, 0);
1421 u8
bnx2x_is_pcie_pending(struct pci_dev
*dev
)
1425 pcie_capability_read_word(dev
, PCI_EXP_DEVSTA
, &status
);
1426 return status
& PCI_EXP_DEVSTA_TRPND
;
1429 /* PF FLR specific routines
1431 static int bnx2x_poll_hw_usage_counters(struct bnx2x
*bp
, u32 poll_cnt
)
1433 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1434 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1435 CFC_REG_NUM_LCIDS_INSIDE_PF
,
1436 "CFC PF usage counter timed out",
1440 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1441 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1442 DORQ_REG_PF_USAGE_CNT
,
1443 "DQ PF usage counter timed out",
1447 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1448 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1449 QM_REG_PF_USG_CNT_0
+ 4*BP_FUNC(bp
),
1450 "QM PF usage counter timed out",
1454 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1455 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1456 TM_REG_LIN0_VNIC_UC
+ 4*BP_PORT(bp
),
1457 "Timers VNIC usage counter timed out",
1460 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1461 TM_REG_LIN0_NUM_SCANS
+ 4*BP_PORT(bp
),
1462 "Timers NUM_SCANS usage counter timed out",
1466 /* Wait DMAE PF usage counter to zero */
1467 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1468 dmae_reg_go_c
[INIT_DMAE_C(bp
)],
1469 "DMAE command register timed out",
1476 static void bnx2x_hw_enable_status(struct bnx2x
*bp
)
1480 val
= REG_RD(bp
, CFC_REG_WEAK_ENABLE_PF
);
1481 DP(BNX2X_MSG_SP
, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val
);
1483 val
= REG_RD(bp
, PBF_REG_DISABLE_PF
);
1484 DP(BNX2X_MSG_SP
, "PBF_REG_DISABLE_PF is 0x%x\n", val
);
1486 val
= REG_RD(bp
, IGU_REG_PCI_PF_MSI_EN
);
1487 DP(BNX2X_MSG_SP
, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val
);
1489 val
= REG_RD(bp
, IGU_REG_PCI_PF_MSIX_EN
);
1490 DP(BNX2X_MSG_SP
, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val
);
1492 val
= REG_RD(bp
, IGU_REG_PCI_PF_MSIX_FUNC_MASK
);
1493 DP(BNX2X_MSG_SP
, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val
);
1495 val
= REG_RD(bp
, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR
);
1496 DP(BNX2X_MSG_SP
, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val
);
1498 val
= REG_RD(bp
, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR
);
1499 DP(BNX2X_MSG_SP
, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val
);
1501 val
= REG_RD(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
);
1502 DP(BNX2X_MSG_SP
, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1506 static int bnx2x_pf_flr_clnup(struct bnx2x
*bp
)
1508 u32 poll_cnt
= bnx2x_flr_clnup_poll_count(bp
);
1510 DP(BNX2X_MSG_SP
, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp
));
1512 /* Re-enable PF target read access */
1513 REG_WR(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ
, 1);
1515 /* Poll HW usage counters */
1516 DP(BNX2X_MSG_SP
, "Polling usage counters\n");
1517 if (bnx2x_poll_hw_usage_counters(bp
, poll_cnt
))
1520 /* Zero the igu 'trailing edge' and 'leading edge' */
1522 /* Send the FW cleanup command */
1523 if (bnx2x_send_final_clnup(bp
, (u8
)BP_FUNC(bp
), poll_cnt
))
1528 /* Verify TX hw is flushed */
1529 bnx2x_tx_hw_flushed(bp
, poll_cnt
);
1531 /* Wait 100ms (not adjusted according to platform) */
1534 /* Verify no pending pci transactions */
1535 if (bnx2x_is_pcie_pending(bp
->pdev
))
1536 BNX2X_ERR("PCIE Transactions still pending\n");
1539 bnx2x_hw_enable_status(bp
);
1542 * Master enable - Due to WB DMAE writes performed before this
1543 * register is re-initialized as part of the regular function init
1545 REG_WR(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
, 1);
1550 static void bnx2x_hc_int_enable(struct bnx2x
*bp
)
1552 int port
= BP_PORT(bp
);
1553 u32 addr
= port
? HC_REG_CONFIG_1
: HC_REG_CONFIG_0
;
1554 u32 val
= REG_RD(bp
, addr
);
1555 bool msix
= (bp
->flags
& USING_MSIX_FLAG
) ? true : false;
1556 bool single_msix
= (bp
->flags
& USING_SINGLE_MSIX_FLAG
) ? true : false;
1557 bool msi
= (bp
->flags
& USING_MSI_FLAG
) ? true : false;
1560 val
&= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0
|
1561 HC_CONFIG_0_REG_INT_LINE_EN_0
);
1562 val
|= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
|
1563 HC_CONFIG_0_REG_ATTN_BIT_EN_0
);
1565 val
|= HC_CONFIG_0_REG_SINGLE_ISR_EN_0
;
1567 val
&= ~HC_CONFIG_0_REG_INT_LINE_EN_0
;
1568 val
|= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0
|
1569 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
|
1570 HC_CONFIG_0_REG_ATTN_BIT_EN_0
);
1572 val
|= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0
|
1573 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
|
1574 HC_CONFIG_0_REG_INT_LINE_EN_0
|
1575 HC_CONFIG_0_REG_ATTN_BIT_EN_0
);
1577 if (!CHIP_IS_E1(bp
)) {
1579 "write %x to HC %d (addr 0x%x)\n", val
, port
, addr
);
1581 REG_WR(bp
, addr
, val
);
1583 val
&= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
;
1588 REG_WR(bp
, HC_REG_INT_MASK
+ port
*4, 0x1FFFF);
1591 "write %x to HC %d (addr 0x%x) mode %s\n", val
, port
, addr
,
1592 (msix
? "MSI-X" : (msi
? "MSI" : "INTx")));
1594 REG_WR(bp
, addr
, val
);
1596 * Ensure that HC_CONFIG is written before leading/trailing edge config
1601 if (!CHIP_IS_E1(bp
)) {
1602 /* init leading/trailing edge */
1604 val
= (0xee0f | (1 << (BP_VN(bp
) + 4)));
1606 /* enable nig and gpio3 attention */
1611 REG_WR(bp
, HC_REG_TRAILING_EDGE_0
+ port
*8, val
);
1612 REG_WR(bp
, HC_REG_LEADING_EDGE_0
+ port
*8, val
);
1615 /* Make sure that interrupts are indeed enabled from here on */
1619 static void bnx2x_igu_int_enable(struct bnx2x
*bp
)
1622 bool msix
= (bp
->flags
& USING_MSIX_FLAG
) ? true : false;
1623 bool single_msix
= (bp
->flags
& USING_SINGLE_MSIX_FLAG
) ? true : false;
1624 bool msi
= (bp
->flags
& USING_MSI_FLAG
) ? true : false;
1626 val
= REG_RD(bp
, IGU_REG_PF_CONFIGURATION
);
1629 val
&= ~(IGU_PF_CONF_INT_LINE_EN
|
1630 IGU_PF_CONF_SINGLE_ISR_EN
);
1631 val
|= (IGU_PF_CONF_MSI_MSIX_EN
|
1632 IGU_PF_CONF_ATTN_BIT_EN
);
1635 val
|= IGU_PF_CONF_SINGLE_ISR_EN
;
1637 val
&= ~IGU_PF_CONF_INT_LINE_EN
;
1638 val
|= (IGU_PF_CONF_MSI_MSIX_EN
|
1639 IGU_PF_CONF_ATTN_BIT_EN
|
1640 IGU_PF_CONF_SINGLE_ISR_EN
);
1642 val
&= ~IGU_PF_CONF_MSI_MSIX_EN
;
1643 val
|= (IGU_PF_CONF_INT_LINE_EN
|
1644 IGU_PF_CONF_ATTN_BIT_EN
|
1645 IGU_PF_CONF_SINGLE_ISR_EN
);
1648 /* Clean previous status - need to configure igu prior to ack*/
1649 if ((!msix
) || single_msix
) {
1650 REG_WR(bp
, IGU_REG_PF_CONFIGURATION
, val
);
1654 val
|= IGU_PF_CONF_FUNC_EN
;
1656 DP(NETIF_MSG_IFUP
, "write 0x%x to IGU mode %s\n",
1657 val
, (msix
? "MSI-X" : (msi
? "MSI" : "INTx")));
1659 REG_WR(bp
, IGU_REG_PF_CONFIGURATION
, val
);
1661 if (val
& IGU_PF_CONF_INT_LINE_EN
)
1662 pci_intx(bp
->pdev
, true);
1666 /* init leading/trailing edge */
1668 val
= (0xee0f | (1 << (BP_VN(bp
) + 4)));
1670 /* enable nig and gpio3 attention */
1675 REG_WR(bp
, IGU_REG_TRAILING_EDGE_LATCH
, val
);
1676 REG_WR(bp
, IGU_REG_LEADING_EDGE_LATCH
, val
);
1678 /* Make sure that interrupts are indeed enabled from here on */
1682 void bnx2x_int_enable(struct bnx2x
*bp
)
1684 if (bp
->common
.int_block
== INT_BLOCK_HC
)
1685 bnx2x_hc_int_enable(bp
);
1687 bnx2x_igu_int_enable(bp
);
1690 void bnx2x_int_disable_sync(struct bnx2x
*bp
, int disable_hw
)
1692 int msix
= (bp
->flags
& USING_MSIX_FLAG
) ? 1 : 0;
1696 /* prevent the HW from sending interrupts */
1697 bnx2x_int_disable(bp
);
1699 /* make sure all ISRs are done */
1701 synchronize_irq(bp
->msix_table
[0].vector
);
1703 if (CNIC_SUPPORT(bp
))
1705 for_each_eth_queue(bp
, i
)
1706 synchronize_irq(bp
->msix_table
[offset
++].vector
);
1708 synchronize_irq(bp
->pdev
->irq
);
1710 /* make sure sp_task is not running */
1711 cancel_delayed_work(&bp
->sp_task
);
1712 cancel_delayed_work(&bp
->period_task
);
1713 flush_workqueue(bnx2x_wq
);
1719 * General service functions
1722 /* Return true if succeeded to acquire the lock */
1723 static bool bnx2x_trylock_hw_lock(struct bnx2x
*bp
, u32 resource
)
1726 u32 resource_bit
= (1 << resource
);
1727 int func
= BP_FUNC(bp
);
1728 u32 hw_lock_control_reg
;
1730 DP(NETIF_MSG_HW
| NETIF_MSG_IFUP
,
1731 "Trying to take a lock on resource %d\n", resource
);
1733 /* Validating that the resource is within range */
1734 if (resource
> HW_LOCK_MAX_RESOURCE_VALUE
) {
1735 DP(NETIF_MSG_HW
| NETIF_MSG_IFUP
,
1736 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1737 resource
, HW_LOCK_MAX_RESOURCE_VALUE
);
1742 hw_lock_control_reg
= (MISC_REG_DRIVER_CONTROL_1
+ func
*8);
1744 hw_lock_control_reg
=
1745 (MISC_REG_DRIVER_CONTROL_7
+ (func
- 6)*8);
1747 /* Try to acquire the lock */
1748 REG_WR(bp
, hw_lock_control_reg
+ 4, resource_bit
);
1749 lock_status
= REG_RD(bp
, hw_lock_control_reg
);
1750 if (lock_status
& resource_bit
)
1753 DP(NETIF_MSG_HW
| NETIF_MSG_IFUP
,
1754 "Failed to get a lock on resource %d\n", resource
);
1759 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1761 * @bp: driver handle
1763 * Returns the recovery leader resource id according to the engine this function
1764 * belongs to. Currently only only 2 engines is supported.
1766 static int bnx2x_get_leader_lock_resource(struct bnx2x
*bp
)
1769 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1
;
1771 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0
;
1775 * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1777 * @bp: driver handle
1779 * Tries to acquire a leader lock for current engine.
1781 static bool bnx2x_trylock_leader_lock(struct bnx2x
*bp
)
1783 return bnx2x_trylock_hw_lock(bp
, bnx2x_get_leader_lock_resource(bp
));
1786 static void bnx2x_cnic_cfc_comp(struct bnx2x
*bp
, int cid
, u8 err
);
1788 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1789 static int bnx2x_schedule_sp_task(struct bnx2x
*bp
)
1791 /* Set the interrupt occurred bit for the sp-task to recognize it
1792 * must ack the interrupt and transition according to the IGU
1795 atomic_set(&bp
->interrupt_occurred
, 1);
1797 /* The sp_task must execute only after this bit
1798 * is set, otherwise we will get out of sync and miss all
1799 * further interrupts. Hence, the barrier.
1803 /* schedule sp_task to workqueue */
1804 return queue_delayed_work(bnx2x_wq
, &bp
->sp_task
, 0);
1807 void bnx2x_sp_event(struct bnx2x_fastpath
*fp
, union eth_rx_cqe
*rr_cqe
)
1809 struct bnx2x
*bp
= fp
->bp
;
1810 int cid
= SW_CID(rr_cqe
->ramrod_cqe
.conn_and_cmd_data
);
1811 int command
= CQE_CMD(rr_cqe
->ramrod_cqe
.conn_and_cmd_data
);
1812 enum bnx2x_queue_cmd drv_cmd
= BNX2X_Q_CMD_MAX
;
1813 struct bnx2x_queue_sp_obj
*q_obj
= &bnx2x_sp_obj(bp
, fp
).q_obj
;
1816 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1817 fp
->index
, cid
, command
, bp
->state
,
1818 rr_cqe
->ramrod_cqe
.ramrod_type
);
1820 /* If cid is within VF range, replace the slowpath object with the
1821 * one corresponding to this VF
1823 if (cid
>= BNX2X_FIRST_VF_CID
&&
1824 cid
< BNX2X_FIRST_VF_CID
+ BNX2X_VF_CIDS
)
1825 bnx2x_iov_set_queue_sp_obj(bp
, cid
, &q_obj
);
1828 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE
):
1829 DP(BNX2X_MSG_SP
, "got UPDATE ramrod. CID %d\n", cid
);
1830 drv_cmd
= BNX2X_Q_CMD_UPDATE
;
1833 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP
):
1834 DP(BNX2X_MSG_SP
, "got MULTI[%d] setup ramrod\n", cid
);
1835 drv_cmd
= BNX2X_Q_CMD_SETUP
;
1838 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP
):
1839 DP(BNX2X_MSG_SP
, "got MULTI[%d] tx-only setup ramrod\n", cid
);
1840 drv_cmd
= BNX2X_Q_CMD_SETUP_TX_ONLY
;
1843 case (RAMROD_CMD_ID_ETH_HALT
):
1844 DP(BNX2X_MSG_SP
, "got MULTI[%d] halt ramrod\n", cid
);
1845 drv_cmd
= BNX2X_Q_CMD_HALT
;
1848 case (RAMROD_CMD_ID_ETH_TERMINATE
):
1849 DP(BNX2X_MSG_SP
, "got MULTI[%d] terminate ramrod\n", cid
);
1850 drv_cmd
= BNX2X_Q_CMD_TERMINATE
;
1853 case (RAMROD_CMD_ID_ETH_EMPTY
):
1854 DP(BNX2X_MSG_SP
, "got MULTI[%d] empty ramrod\n", cid
);
1855 drv_cmd
= BNX2X_Q_CMD_EMPTY
;
1858 case (RAMROD_CMD_ID_ETH_TPA_UPDATE
):
1859 DP(BNX2X_MSG_SP
, "got tpa update ramrod CID=%d\n", cid
);
1860 drv_cmd
= BNX2X_Q_CMD_UPDATE_TPA
;
1864 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1865 command
, fp
->index
);
1869 if ((drv_cmd
!= BNX2X_Q_CMD_MAX
) &&
1870 q_obj
->complete_cmd(bp
, q_obj
, drv_cmd
))
1871 /* q_obj->complete_cmd() failure means that this was
1872 * an unexpected completion.
1874 * In this case we don't want to increase the bp->spq_left
1875 * because apparently we haven't sent this command the first
1878 #ifdef BNX2X_STOP_ON_ERROR
1884 smp_mb__before_atomic();
1885 atomic_inc(&bp
->cq_spq_left
);
1886 /* push the change in bp->spq_left and towards the memory */
1887 smp_mb__after_atomic();
1889 DP(BNX2X_MSG_SP
, "bp->cq_spq_left %x\n", atomic_read(&bp
->cq_spq_left
));
1891 if ((drv_cmd
== BNX2X_Q_CMD_UPDATE
) && (IS_FCOE_FP(fp
)) &&
1892 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING
, &bp
->sp_state
))) {
1893 /* if Q update ramrod is completed for last Q in AFEX vif set
1894 * flow, then ACK MCP at the end
1896 * mark pending ACK to MCP bit.
1897 * prevent case that both bits are cleared.
1898 * At the end of load/unload driver checks that
1899 * sp_state is cleared, and this order prevents
1902 smp_mb__before_atomic();
1903 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK
, &bp
->sp_state
);
1905 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING
, &bp
->sp_state
);
1906 smp_mb__after_atomic();
1908 /* schedule the sp task as mcp ack is required */
1909 bnx2x_schedule_sp_task(bp
);
1915 irqreturn_t
bnx2x_interrupt(int irq
, void *dev_instance
)
1917 struct bnx2x
*bp
= netdev_priv(dev_instance
);
1918 u16 status
= bnx2x_ack_int(bp
);
1923 /* Return here if interrupt is shared and it's not for us */
1924 if (unlikely(status
== 0)) {
1925 DP(NETIF_MSG_INTR
, "not our interrupt!\n");
1928 DP(NETIF_MSG_INTR
, "got an interrupt status 0x%x\n", status
);
1930 #ifdef BNX2X_STOP_ON_ERROR
1931 if (unlikely(bp
->panic
))
1935 for_each_eth_queue(bp
, i
) {
1936 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
1938 mask
= 0x2 << (fp
->index
+ CNIC_SUPPORT(bp
));
1939 if (status
& mask
) {
1940 /* Handle Rx or Tx according to SB id */
1941 for_each_cos_in_tx_queue(fp
, cos
)
1942 prefetch(fp
->txdata_ptr
[cos
]->tx_cons_sb
);
1943 prefetch(&fp
->sb_running_index
[SM_RX_ID
]);
1944 napi_schedule_irqoff(&bnx2x_fp(bp
, fp
->index
, napi
));
1949 if (CNIC_SUPPORT(bp
)) {
1951 if (status
& (mask
| 0x1)) {
1952 struct cnic_ops
*c_ops
= NULL
;
1955 c_ops
= rcu_dereference(bp
->cnic_ops
);
1956 if (c_ops
&& (bp
->cnic_eth_dev
.drv_state
&
1957 CNIC_DRV_STATE_HANDLES_IRQ
))
1958 c_ops
->cnic_handler(bp
->cnic_data
, NULL
);
1965 if (unlikely(status
& 0x1)) {
1967 /* schedule sp task to perform default status block work, ack
1968 * attentions and enable interrupts.
1970 bnx2x_schedule_sp_task(bp
);
1977 if (unlikely(status
))
1978 DP(NETIF_MSG_INTR
, "got an unknown interrupt! (status 0x%x)\n",
1987 * General service functions
1990 int bnx2x_acquire_hw_lock(struct bnx2x
*bp
, u32 resource
)
1993 u32 resource_bit
= (1 << resource
);
1994 int func
= BP_FUNC(bp
);
1995 u32 hw_lock_control_reg
;
1998 /* Validating that the resource is within range */
1999 if (resource
> HW_LOCK_MAX_RESOURCE_VALUE
) {
2000 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
2001 resource
, HW_LOCK_MAX_RESOURCE_VALUE
);
2006 hw_lock_control_reg
= (MISC_REG_DRIVER_CONTROL_1
+ func
*8);
2008 hw_lock_control_reg
=
2009 (MISC_REG_DRIVER_CONTROL_7
+ (func
- 6)*8);
2012 /* Validating that the resource is not already taken */
2013 lock_status
= REG_RD(bp
, hw_lock_control_reg
);
2014 if (lock_status
& resource_bit
) {
2015 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n",
2016 lock_status
, resource_bit
);
2020 /* Try for 5 second every 5ms */
2021 for (cnt
= 0; cnt
< 1000; cnt
++) {
2022 /* Try to acquire the lock */
2023 REG_WR(bp
, hw_lock_control_reg
+ 4, resource_bit
);
2024 lock_status
= REG_RD(bp
, hw_lock_control_reg
);
2025 if (lock_status
& resource_bit
)
2028 usleep_range(5000, 10000);
2030 BNX2X_ERR("Timeout\n");
2034 int bnx2x_release_leader_lock(struct bnx2x
*bp
)
2036 return bnx2x_release_hw_lock(bp
, bnx2x_get_leader_lock_resource(bp
));
2039 int bnx2x_release_hw_lock(struct bnx2x
*bp
, u32 resource
)
2042 u32 resource_bit
= (1 << resource
);
2043 int func
= BP_FUNC(bp
);
2044 u32 hw_lock_control_reg
;
2046 /* Validating that the resource is within range */
2047 if (resource
> HW_LOCK_MAX_RESOURCE_VALUE
) {
2048 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
2049 resource
, HW_LOCK_MAX_RESOURCE_VALUE
);
2054 hw_lock_control_reg
= (MISC_REG_DRIVER_CONTROL_1
+ func
*8);
2056 hw_lock_control_reg
=
2057 (MISC_REG_DRIVER_CONTROL_7
+ (func
- 6)*8);
2060 /* Validating that the resource is currently taken */
2061 lock_status
= REG_RD(bp
, hw_lock_control_reg
);
2062 if (!(lock_status
& resource_bit
)) {
2063 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2064 lock_status
, resource_bit
);
2068 REG_WR(bp
, hw_lock_control_reg
, resource_bit
);
2072 int bnx2x_get_gpio(struct bnx2x
*bp
, int gpio_num
, u8 port
)
2074 /* The GPIO should be swapped if swap register is set and active */
2075 int gpio_port
= (REG_RD(bp
, NIG_REG_PORT_SWAP
) &&
2076 REG_RD(bp
, NIG_REG_STRAP_OVERRIDE
)) ^ port
;
2077 int gpio_shift
= gpio_num
+
2078 (gpio_port
? MISC_REGISTERS_GPIO_PORT_SHIFT
: 0);
2079 u32 gpio_mask
= (1 << gpio_shift
);
2083 if (gpio_num
> MISC_REGISTERS_GPIO_3
) {
2084 BNX2X_ERR("Invalid GPIO %d\n", gpio_num
);
2088 /* read GPIO value */
2089 gpio_reg
= REG_RD(bp
, MISC_REG_GPIO
);
2091 /* get the requested pin value */
2092 if ((gpio_reg
& gpio_mask
) == gpio_mask
)
2100 int bnx2x_set_gpio(struct bnx2x
*bp
, int gpio_num
, u32 mode
, u8 port
)
2102 /* The GPIO should be swapped if swap register is set and active */
2103 int gpio_port
= (REG_RD(bp
, NIG_REG_PORT_SWAP
) &&
2104 REG_RD(bp
, NIG_REG_STRAP_OVERRIDE
)) ^ port
;
2105 int gpio_shift
= gpio_num
+
2106 (gpio_port
? MISC_REGISTERS_GPIO_PORT_SHIFT
: 0);
2107 u32 gpio_mask
= (1 << gpio_shift
);
2110 if (gpio_num
> MISC_REGISTERS_GPIO_3
) {
2111 BNX2X_ERR("Invalid GPIO %d\n", gpio_num
);
2115 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
2116 /* read GPIO and mask except the float bits */
2117 gpio_reg
= (REG_RD(bp
, MISC_REG_GPIO
) & MISC_REGISTERS_GPIO_FLOAT
);
2120 case MISC_REGISTERS_GPIO_OUTPUT_LOW
:
2122 "Set GPIO %d (shift %d) -> output low\n",
2123 gpio_num
, gpio_shift
);
2124 /* clear FLOAT and set CLR */
2125 gpio_reg
&= ~(gpio_mask
<< MISC_REGISTERS_GPIO_FLOAT_POS
);
2126 gpio_reg
|= (gpio_mask
<< MISC_REGISTERS_GPIO_CLR_POS
);
2129 case MISC_REGISTERS_GPIO_OUTPUT_HIGH
:
2131 "Set GPIO %d (shift %d) -> output high\n",
2132 gpio_num
, gpio_shift
);
2133 /* clear FLOAT and set SET */
2134 gpio_reg
&= ~(gpio_mask
<< MISC_REGISTERS_GPIO_FLOAT_POS
);
2135 gpio_reg
|= (gpio_mask
<< MISC_REGISTERS_GPIO_SET_POS
);
2138 case MISC_REGISTERS_GPIO_INPUT_HI_Z
:
2140 "Set GPIO %d (shift %d) -> input\n",
2141 gpio_num
, gpio_shift
);
2143 gpio_reg
|= (gpio_mask
<< MISC_REGISTERS_GPIO_FLOAT_POS
);
2150 REG_WR(bp
, MISC_REG_GPIO
, gpio_reg
);
2151 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
2156 int bnx2x_set_mult_gpio(struct bnx2x
*bp
, u8 pins
, u32 mode
)
2161 /* Any port swapping should be handled by caller. */
2163 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
2164 /* read GPIO and mask except the float bits */
2165 gpio_reg
= REG_RD(bp
, MISC_REG_GPIO
);
2166 gpio_reg
&= ~(pins
<< MISC_REGISTERS_GPIO_FLOAT_POS
);
2167 gpio_reg
&= ~(pins
<< MISC_REGISTERS_GPIO_CLR_POS
);
2168 gpio_reg
&= ~(pins
<< MISC_REGISTERS_GPIO_SET_POS
);
2171 case MISC_REGISTERS_GPIO_OUTPUT_LOW
:
2172 DP(NETIF_MSG_LINK
, "Set GPIO 0x%x -> output low\n", pins
);
2174 gpio_reg
|= (pins
<< MISC_REGISTERS_GPIO_CLR_POS
);
2177 case MISC_REGISTERS_GPIO_OUTPUT_HIGH
:
2178 DP(NETIF_MSG_LINK
, "Set GPIO 0x%x -> output high\n", pins
);
2180 gpio_reg
|= (pins
<< MISC_REGISTERS_GPIO_SET_POS
);
2183 case MISC_REGISTERS_GPIO_INPUT_HI_Z
:
2184 DP(NETIF_MSG_LINK
, "Set GPIO 0x%x -> input\n", pins
);
2186 gpio_reg
|= (pins
<< MISC_REGISTERS_GPIO_FLOAT_POS
);
2190 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode
);
2196 REG_WR(bp
, MISC_REG_GPIO
, gpio_reg
);
2198 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
2203 int bnx2x_set_gpio_int(struct bnx2x
*bp
, int gpio_num
, u32 mode
, u8 port
)
2205 /* The GPIO should be swapped if swap register is set and active */
2206 int gpio_port
= (REG_RD(bp
, NIG_REG_PORT_SWAP
) &&
2207 REG_RD(bp
, NIG_REG_STRAP_OVERRIDE
)) ^ port
;
2208 int gpio_shift
= gpio_num
+
2209 (gpio_port
? MISC_REGISTERS_GPIO_PORT_SHIFT
: 0);
2210 u32 gpio_mask
= (1 << gpio_shift
);
2213 if (gpio_num
> MISC_REGISTERS_GPIO_3
) {
2214 BNX2X_ERR("Invalid GPIO %d\n", gpio_num
);
2218 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
2220 gpio_reg
= REG_RD(bp
, MISC_REG_GPIO_INT
);
2223 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR
:
2225 "Clear GPIO INT %d (shift %d) -> output low\n",
2226 gpio_num
, gpio_shift
);
2227 /* clear SET and set CLR */
2228 gpio_reg
&= ~(gpio_mask
<< MISC_REGISTERS_GPIO_INT_SET_POS
);
2229 gpio_reg
|= (gpio_mask
<< MISC_REGISTERS_GPIO_INT_CLR_POS
);
2232 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET
:
2234 "Set GPIO INT %d (shift %d) -> output high\n",
2235 gpio_num
, gpio_shift
);
2236 /* clear CLR and set SET */
2237 gpio_reg
&= ~(gpio_mask
<< MISC_REGISTERS_GPIO_INT_CLR_POS
);
2238 gpio_reg
|= (gpio_mask
<< MISC_REGISTERS_GPIO_INT_SET_POS
);
2245 REG_WR(bp
, MISC_REG_GPIO_INT
, gpio_reg
);
2246 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
2251 static int bnx2x_set_spio(struct bnx2x
*bp
, int spio
, u32 mode
)
2255 /* Only 2 SPIOs are configurable */
2256 if ((spio
!= MISC_SPIO_SPIO4
) && (spio
!= MISC_SPIO_SPIO5
)) {
2257 BNX2X_ERR("Invalid SPIO 0x%x\n", spio
);
2261 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_SPIO
);
2262 /* read SPIO and mask except the float bits */
2263 spio_reg
= (REG_RD(bp
, MISC_REG_SPIO
) & MISC_SPIO_FLOAT
);
2266 case MISC_SPIO_OUTPUT_LOW
:
2267 DP(NETIF_MSG_HW
, "Set SPIO 0x%x -> output low\n", spio
);
2268 /* clear FLOAT and set CLR */
2269 spio_reg
&= ~(spio
<< MISC_SPIO_FLOAT_POS
);
2270 spio_reg
|= (spio
<< MISC_SPIO_CLR_POS
);
2273 case MISC_SPIO_OUTPUT_HIGH
:
2274 DP(NETIF_MSG_HW
, "Set SPIO 0x%x -> output high\n", spio
);
2275 /* clear FLOAT and set SET */
2276 spio_reg
&= ~(spio
<< MISC_SPIO_FLOAT_POS
);
2277 spio_reg
|= (spio
<< MISC_SPIO_SET_POS
);
2280 case MISC_SPIO_INPUT_HI_Z
:
2281 DP(NETIF_MSG_HW
, "Set SPIO 0x%x -> input\n", spio
);
2283 spio_reg
|= (spio
<< MISC_SPIO_FLOAT_POS
);
2290 REG_WR(bp
, MISC_REG_SPIO
, spio_reg
);
2291 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_SPIO
);
2296 void bnx2x_calc_fc_adv(struct bnx2x
*bp
)
2298 u8 cfg_idx
= bnx2x_get_link_cfg_idx(bp
);
2300 bp
->port
.advertising
[cfg_idx
] &= ~(ADVERTISED_Asym_Pause
|
2302 switch (bp
->link_vars
.ieee_fc
&
2303 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK
) {
2304 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
:
2305 bp
->port
.advertising
[cfg_idx
] |= (ADVERTISED_Asym_Pause
|
2309 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
:
2310 bp
->port
.advertising
[cfg_idx
] |= ADVERTISED_Asym_Pause
;
2318 static void bnx2x_set_requested_fc(struct bnx2x
*bp
)
2320 /* Initialize link parameters structure variables
2321 * It is recommended to turn off RX FC for jumbo frames
2322 * for better performance
2324 if (CHIP_IS_E1x(bp
) && (bp
->dev
->mtu
> 5000))
2325 bp
->link_params
.req_fc_auto_adv
= BNX2X_FLOW_CTRL_TX
;
2327 bp
->link_params
.req_fc_auto_adv
= BNX2X_FLOW_CTRL_BOTH
;
2330 static void bnx2x_init_dropless_fc(struct bnx2x
*bp
)
2332 u32 pause_enabled
= 0;
2334 if (!CHIP_IS_E1(bp
) && bp
->dropless_fc
&& bp
->link_vars
.link_up
) {
2335 if (bp
->link_vars
.flow_ctrl
& BNX2X_FLOW_CTRL_TX
)
2338 REG_WR(bp
, BAR_USTRORM_INTMEM
+
2339 USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp
)),
2343 DP(NETIF_MSG_IFUP
| NETIF_MSG_LINK
, "dropless_fc is %s\n",
2344 pause_enabled
? "enabled" : "disabled");
2347 int bnx2x_initial_phy_init(struct bnx2x
*bp
, int load_mode
)
2349 int rc
, cfx_idx
= bnx2x_get_link_cfg_idx(bp
);
2350 u16 req_line_speed
= bp
->link_params
.req_line_speed
[cfx_idx
];
2352 if (!BP_NOMCP(bp
)) {
2353 bnx2x_set_requested_fc(bp
);
2354 bnx2x_acquire_phy_lock(bp
);
2356 if (load_mode
== LOAD_DIAG
) {
2357 struct link_params
*lp
= &bp
->link_params
;
2358 lp
->loopback_mode
= LOOPBACK_XGXS
;
2359 /* Prefer doing PHY loopback at highest speed */
2360 if (lp
->req_line_speed
[cfx_idx
] < SPEED_20000
) {
2361 if (lp
->speed_cap_mask
[cfx_idx
] &
2362 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G
)
2363 lp
->req_line_speed
[cfx_idx
] =
2365 else if (lp
->speed_cap_mask
[cfx_idx
] &
2366 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
)
2367 lp
->req_line_speed
[cfx_idx
] =
2370 lp
->req_line_speed
[cfx_idx
] =
2375 if (load_mode
== LOAD_LOOPBACK_EXT
) {
2376 struct link_params
*lp
= &bp
->link_params
;
2377 lp
->loopback_mode
= LOOPBACK_EXT
;
2380 rc
= bnx2x_phy_init(&bp
->link_params
, &bp
->link_vars
);
2382 bnx2x_release_phy_lock(bp
);
2384 bnx2x_init_dropless_fc(bp
);
2386 bnx2x_calc_fc_adv(bp
);
2388 if (bp
->link_vars
.link_up
) {
2389 bnx2x_stats_handle(bp
, STATS_EVENT_LINK_UP
);
2390 bnx2x_link_report(bp
);
2392 queue_delayed_work(bnx2x_wq
, &bp
->period_task
, 0);
2393 bp
->link_params
.req_line_speed
[cfx_idx
] = req_line_speed
;
2396 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2400 void bnx2x_link_set(struct bnx2x
*bp
)
2402 if (!BP_NOMCP(bp
)) {
2403 bnx2x_acquire_phy_lock(bp
);
2404 bnx2x_phy_init(&bp
->link_params
, &bp
->link_vars
);
2405 bnx2x_release_phy_lock(bp
);
2407 bnx2x_init_dropless_fc(bp
);
2409 bnx2x_calc_fc_adv(bp
);
2411 BNX2X_ERR("Bootcode is missing - can not set link\n");
2414 static void bnx2x__link_reset(struct bnx2x
*bp
)
2416 if (!BP_NOMCP(bp
)) {
2417 bnx2x_acquire_phy_lock(bp
);
2418 bnx2x_lfa_reset(&bp
->link_params
, &bp
->link_vars
);
2419 bnx2x_release_phy_lock(bp
);
2421 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2424 void bnx2x_force_link_reset(struct bnx2x
*bp
)
2426 bnx2x_acquire_phy_lock(bp
);
2427 bnx2x_link_reset(&bp
->link_params
, &bp
->link_vars
, 1);
2428 bnx2x_release_phy_lock(bp
);
2431 u8
bnx2x_link_test(struct bnx2x
*bp
, u8 is_serdes
)
2435 if (!BP_NOMCP(bp
)) {
2436 bnx2x_acquire_phy_lock(bp
);
2437 rc
= bnx2x_test_link(&bp
->link_params
, &bp
->link_vars
,
2439 bnx2x_release_phy_lock(bp
);
2441 BNX2X_ERR("Bootcode is missing - can not test link\n");
2446 /* Calculates the sum of vn_min_rates.
2447 It's needed for further normalizing of the min_rates.
2449 sum of vn_min_rates.
2451 0 - if all the min_rates are 0.
2452 In the later case fairness algorithm should be deactivated.
2453 If not all min_rates are zero then those that are zeroes will be set to 1.
2455 static void bnx2x_calc_vn_min(struct bnx2x
*bp
,
2456 struct cmng_init_input
*input
)
2461 for (vn
= VN_0
; vn
< BP_MAX_VN_NUM(bp
); vn
++) {
2462 u32 vn_cfg
= bp
->mf_config
[vn
];
2463 u32 vn_min_rate
= ((vn_cfg
& FUNC_MF_CFG_MIN_BW_MASK
) >>
2464 FUNC_MF_CFG_MIN_BW_SHIFT
) * 100;
2466 /* Skip hidden vns */
2467 if (vn_cfg
& FUNC_MF_CFG_FUNC_HIDE
)
2469 /* If min rate is zero - set it to 1 */
2470 else if (!vn_min_rate
)
2471 vn_min_rate
= DEF_MIN_RATE
;
2475 input
->vnic_min_rate
[vn
] = vn_min_rate
;
2478 /* if ETS or all min rates are zeros - disable fairness */
2479 if (BNX2X_IS_ETS_ENABLED(bp
)) {
2480 input
->flags
.cmng_enables
&=
2481 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN
;
2482 DP(NETIF_MSG_IFUP
, "Fairness will be disabled due to ETS\n");
2483 } else if (all_zero
) {
2484 input
->flags
.cmng_enables
&=
2485 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN
;
2487 "All MIN values are zeroes fairness will be disabled\n");
2489 input
->flags
.cmng_enables
|=
2490 CMNG_FLAGS_PER_PORT_FAIRNESS_VN
;
2493 static void bnx2x_calc_vn_max(struct bnx2x
*bp
, int vn
,
2494 struct cmng_init_input
*input
)
2497 u32 vn_cfg
= bp
->mf_config
[vn
];
2499 if (vn_cfg
& FUNC_MF_CFG_FUNC_HIDE
)
2502 u32 maxCfg
= bnx2x_extract_max_cfg(bp
, vn_cfg
);
2504 if (IS_MF_PERCENT_BW(bp
)) {
2505 /* maxCfg in percents of linkspeed */
2506 vn_max_rate
= (bp
->link_vars
.line_speed
* maxCfg
) / 100;
2507 } else /* SD modes */
2508 /* maxCfg is absolute in 100Mb units */
2509 vn_max_rate
= maxCfg
* 100;
2512 DP(NETIF_MSG_IFUP
, "vn %d: vn_max_rate %d\n", vn
, vn_max_rate
);
2514 input
->vnic_max_rate
[vn
] = vn_max_rate
;
2517 static int bnx2x_get_cmng_fns_mode(struct bnx2x
*bp
)
2519 if (CHIP_REV_IS_SLOW(bp
))
2520 return CMNG_FNS_NONE
;
2522 return CMNG_FNS_MINMAX
;
2524 return CMNG_FNS_NONE
;
2527 void bnx2x_read_mf_cfg(struct bnx2x
*bp
)
2529 int vn
, n
= (CHIP_MODE_IS_4_PORT(bp
) ? 2 : 1);
2532 return; /* what should be the default value in this case */
2534 /* For 2 port configuration the absolute function number formula
2536 * abs_func = 2 * vn + BP_PORT + BP_PATH
2538 * and there are 4 functions per port
2540 * For 4 port configuration it is
2541 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2543 * and there are 2 functions per port
2545 for (vn
= VN_0
; vn
< BP_MAX_VN_NUM(bp
); vn
++) {
2546 int /*abs*/func
= n
* (2 * vn
+ BP_PORT(bp
)) + BP_PATH(bp
);
2548 if (func
>= E1H_FUNC_MAX
)
2552 MF_CFG_RD(bp
, func_mf_config
[func
].config
);
2554 if (bp
->mf_config
[BP_VN(bp
)] & FUNC_MF_CFG_FUNC_DISABLED
) {
2555 DP(NETIF_MSG_IFUP
, "mf_cfg function disabled\n");
2556 bp
->flags
|= MF_FUNC_DIS
;
2558 DP(NETIF_MSG_IFUP
, "mf_cfg function enabled\n");
2559 bp
->flags
&= ~MF_FUNC_DIS
;
2563 static void bnx2x_cmng_fns_init(struct bnx2x
*bp
, u8 read_cfg
, u8 cmng_type
)
2565 struct cmng_init_input input
;
2566 memset(&input
, 0, sizeof(struct cmng_init_input
));
2568 input
.port_rate
= bp
->link_vars
.line_speed
;
2570 if (cmng_type
== CMNG_FNS_MINMAX
&& input
.port_rate
) {
2573 /* read mf conf from shmem */
2575 bnx2x_read_mf_cfg(bp
);
2577 /* vn_weight_sum and enable fairness if not 0 */
2578 bnx2x_calc_vn_min(bp
, &input
);
2580 /* calculate and set min-max rate for each vn */
2582 for (vn
= VN_0
; vn
< BP_MAX_VN_NUM(bp
); vn
++)
2583 bnx2x_calc_vn_max(bp
, vn
, &input
);
2585 /* always enable rate shaping and fairness */
2586 input
.flags
.cmng_enables
|=
2587 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN
;
2589 bnx2x_init_cmng(&input
, &bp
->cmng
);
2593 /* rate shaping and fairness are disabled */
2595 "rate shaping and fairness are disabled\n");
2598 static void storm_memset_cmng(struct bnx2x
*bp
,
2599 struct cmng_init
*cmng
,
2603 size_t size
= sizeof(struct cmng_struct_per_port
);
2605 u32 addr
= BAR_XSTRORM_INTMEM
+
2606 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port
);
2608 __storm_memset_struct(bp
, addr
, size
, (u32
*)&cmng
->port
);
2610 for (vn
= VN_0
; vn
< BP_MAX_VN_NUM(bp
); vn
++) {
2611 int func
= func_by_vn(bp
, vn
);
2613 addr
= BAR_XSTRORM_INTMEM
+
2614 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func
);
2615 size
= sizeof(struct rate_shaping_vars_per_vn
);
2616 __storm_memset_struct(bp
, addr
, size
,
2617 (u32
*)&cmng
->vnic
.vnic_max_rate
[vn
]);
2619 addr
= BAR_XSTRORM_INTMEM
+
2620 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func
);
2621 size
= sizeof(struct fairness_vars_per_vn
);
2622 __storm_memset_struct(bp
, addr
, size
,
2623 (u32
*)&cmng
->vnic
.vnic_min_rate
[vn
]);
2627 /* init cmng mode in HW according to local configuration */
2628 void bnx2x_set_local_cmng(struct bnx2x
*bp
)
2630 int cmng_fns
= bnx2x_get_cmng_fns_mode(bp
);
2632 if (cmng_fns
!= CMNG_FNS_NONE
) {
2633 bnx2x_cmng_fns_init(bp
, false, cmng_fns
);
2634 storm_memset_cmng(bp
, &bp
->cmng
, BP_PORT(bp
));
2636 /* rate shaping and fairness are disabled */
2638 "single function mode without fairness\n");
2642 /* This function is called upon link interrupt */
2643 static void bnx2x_link_attn(struct bnx2x
*bp
)
2645 /* Make sure that we are synced with the current statistics */
2646 bnx2x_stats_handle(bp
, STATS_EVENT_STOP
);
2648 bnx2x_link_update(&bp
->link_params
, &bp
->link_vars
);
2650 bnx2x_init_dropless_fc(bp
);
2652 if (bp
->link_vars
.link_up
) {
2654 if (bp
->link_vars
.mac_type
!= MAC_TYPE_EMAC
) {
2655 struct host_port_stats
*pstats
;
2657 pstats
= bnx2x_sp(bp
, port_stats
);
2658 /* reset old mac stats */
2659 memset(&(pstats
->mac_stx
[0]), 0,
2660 sizeof(struct mac_stx
));
2662 if (bp
->state
== BNX2X_STATE_OPEN
)
2663 bnx2x_stats_handle(bp
, STATS_EVENT_LINK_UP
);
2666 if (bp
->link_vars
.link_up
&& bp
->link_vars
.line_speed
)
2667 bnx2x_set_local_cmng(bp
);
2669 __bnx2x_link_report(bp
);
2672 bnx2x_link_sync_notify(bp
);
2675 void bnx2x__link_status_update(struct bnx2x
*bp
)
2677 if (bp
->state
!= BNX2X_STATE_OPEN
)
2680 /* read updated dcb configuration */
2682 bnx2x_dcbx_pmf_update(bp
);
2683 bnx2x_link_status_update(&bp
->link_params
, &bp
->link_vars
);
2684 if (bp
->link_vars
.link_up
)
2685 bnx2x_stats_handle(bp
, STATS_EVENT_LINK_UP
);
2687 bnx2x_stats_handle(bp
, STATS_EVENT_STOP
);
2688 /* indicate link status */
2689 bnx2x_link_report(bp
);
2692 bp
->port
.supported
[0] |= (SUPPORTED_10baseT_Half
|
2693 SUPPORTED_10baseT_Full
|
2694 SUPPORTED_100baseT_Half
|
2695 SUPPORTED_100baseT_Full
|
2696 SUPPORTED_1000baseT_Full
|
2697 SUPPORTED_2500baseX_Full
|
2698 SUPPORTED_10000baseT_Full
|
2703 SUPPORTED_Asym_Pause
);
2704 bp
->port
.advertising
[0] = bp
->port
.supported
[0];
2706 bp
->link_params
.bp
= bp
;
2707 bp
->link_params
.port
= BP_PORT(bp
);
2708 bp
->link_params
.req_duplex
[0] = DUPLEX_FULL
;
2709 bp
->link_params
.req_flow_ctrl
[0] = BNX2X_FLOW_CTRL_NONE
;
2710 bp
->link_params
.req_line_speed
[0] = SPEED_10000
;
2711 bp
->link_params
.speed_cap_mask
[0] = 0x7f0000;
2712 bp
->link_params
.switch_cfg
= SWITCH_CFG_10G
;
2713 bp
->link_vars
.mac_type
= MAC_TYPE_BMAC
;
2714 bp
->link_vars
.line_speed
= SPEED_10000
;
2715 bp
->link_vars
.link_status
=
2716 (LINK_STATUS_LINK_UP
|
2717 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
);
2718 bp
->link_vars
.link_up
= 1;
2719 bp
->link_vars
.duplex
= DUPLEX_FULL
;
2720 bp
->link_vars
.flow_ctrl
= BNX2X_FLOW_CTRL_NONE
;
2721 __bnx2x_link_report(bp
);
2723 bnx2x_sample_bulletin(bp
);
2725 /* if bulletin board did not have an update for link status
2726 * __bnx2x_link_report will report current status
2727 * but it will NOT duplicate report in case of already reported
2728 * during sampling bulletin board.
2730 bnx2x_stats_handle(bp
, STATS_EVENT_LINK_UP
);
2734 static int bnx2x_afex_func_update(struct bnx2x
*bp
, u16 vifid
,
2735 u16 vlan_val
, u8 allowed_prio
)
2737 struct bnx2x_func_state_params func_params
= {NULL
};
2738 struct bnx2x_func_afex_update_params
*f_update_params
=
2739 &func_params
.params
.afex_update
;
2741 func_params
.f_obj
= &bp
->func_obj
;
2742 func_params
.cmd
= BNX2X_F_CMD_AFEX_UPDATE
;
2744 /* no need to wait for RAMROD completion, so don't
2745 * set RAMROD_COMP_WAIT flag
2748 f_update_params
->vif_id
= vifid
;
2749 f_update_params
->afex_default_vlan
= vlan_val
;
2750 f_update_params
->allowed_priorities
= allowed_prio
;
2752 /* if ramrod can not be sent, response to MCP immediately */
2753 if (bnx2x_func_state_change(bp
, &func_params
) < 0)
2754 bnx2x_fw_command(bp
, DRV_MSG_CODE_AFEX_VIFSET_ACK
, 0);
2759 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x
*bp
, u8 cmd_type
,
2760 u16 vif_index
, u8 func_bit_map
)
2762 struct bnx2x_func_state_params func_params
= {NULL
};
2763 struct bnx2x_func_afex_viflists_params
*update_params
=
2764 &func_params
.params
.afex_viflists
;
2768 /* validate only LIST_SET and LIST_GET are received from switch */
2769 if ((cmd_type
!= VIF_LIST_RULE_GET
) && (cmd_type
!= VIF_LIST_RULE_SET
))
2770 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2773 func_params
.f_obj
= &bp
->func_obj
;
2774 func_params
.cmd
= BNX2X_F_CMD_AFEX_VIFLISTS
;
2776 /* set parameters according to cmd_type */
2777 update_params
->afex_vif_list_command
= cmd_type
;
2778 update_params
->vif_list_index
= vif_index
;
2779 update_params
->func_bit_map
=
2780 (cmd_type
== VIF_LIST_RULE_GET
) ? 0 : func_bit_map
;
2781 update_params
->func_to_clear
= 0;
2783 (cmd_type
== VIF_LIST_RULE_GET
) ?
2784 DRV_MSG_CODE_AFEX_LISTGET_ACK
:
2785 DRV_MSG_CODE_AFEX_LISTSET_ACK
;
2787 /* if ramrod can not be sent, respond to MCP immediately for
2788 * SET and GET requests (other are not triggered from MCP)
2790 rc
= bnx2x_func_state_change(bp
, &func_params
);
2792 bnx2x_fw_command(bp
, drv_msg_code
, 0);
2797 static void bnx2x_handle_afex_cmd(struct bnx2x
*bp
, u32 cmd
)
2799 struct afex_stats afex_stats
;
2800 u32 func
= BP_ABS_FUNC(bp
);
2807 u32 addr_to_write
, vifid
, addrs
, stats_type
, i
;
2809 if (cmd
& DRV_STATUS_AFEX_LISTGET_REQ
) {
2810 vifid
= SHMEM2_RD(bp
, afex_param1_to_driver
[BP_FW_MB_IDX(bp
)]);
2812 "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid
);
2813 bnx2x_afex_handle_vif_list_cmd(bp
, VIF_LIST_RULE_GET
, vifid
, 0);
2816 if (cmd
& DRV_STATUS_AFEX_LISTSET_REQ
) {
2817 vifid
= SHMEM2_RD(bp
, afex_param1_to_driver
[BP_FW_MB_IDX(bp
)]);
2818 addrs
= SHMEM2_RD(bp
, afex_param2_to_driver
[BP_FW_MB_IDX(bp
)]);
2820 "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2822 bnx2x_afex_handle_vif_list_cmd(bp
, VIF_LIST_RULE_SET
, vifid
,
2826 if (cmd
& DRV_STATUS_AFEX_STATSGET_REQ
) {
2827 addr_to_write
= SHMEM2_RD(bp
,
2828 afex_scratchpad_addr_to_write
[BP_FW_MB_IDX(bp
)]);
2829 stats_type
= SHMEM2_RD(bp
,
2830 afex_param1_to_driver
[BP_FW_MB_IDX(bp
)]);
2833 "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2836 bnx2x_afex_collect_stats(bp
, (void *)&afex_stats
, stats_type
);
2838 /* write response to scratchpad, for MCP */
2839 for (i
= 0; i
< (sizeof(struct afex_stats
)/sizeof(u32
)); i
++)
2840 REG_WR(bp
, addr_to_write
+ i
*sizeof(u32
),
2841 *(((u32
*)(&afex_stats
))+i
));
2843 /* send ack message to MCP */
2844 bnx2x_fw_command(bp
, DRV_MSG_CODE_AFEX_STATSGET_ACK
, 0);
2847 if (cmd
& DRV_STATUS_AFEX_VIFSET_REQ
) {
2848 mf_config
= MF_CFG_RD(bp
, func_mf_config
[func
].config
);
2849 bp
->mf_config
[BP_VN(bp
)] = mf_config
;
2851 "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2854 /* if VIF_SET is "enabled" */
2855 if (!(mf_config
& FUNC_MF_CFG_FUNC_DISABLED
)) {
2856 /* set rate limit directly to internal RAM */
2857 struct cmng_init_input cmng_input
;
2858 struct rate_shaping_vars_per_vn m_rs_vn
;
2859 size_t size
= sizeof(struct rate_shaping_vars_per_vn
);
2860 u32 addr
= BAR_XSTRORM_INTMEM
+
2861 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp
));
2863 bp
->mf_config
[BP_VN(bp
)] = mf_config
;
2865 bnx2x_calc_vn_max(bp
, BP_VN(bp
), &cmng_input
);
2866 m_rs_vn
.vn_counter
.rate
=
2867 cmng_input
.vnic_max_rate
[BP_VN(bp
)];
2868 m_rs_vn
.vn_counter
.quota
=
2869 (m_rs_vn
.vn_counter
.rate
*
2870 RS_PERIODIC_TIMEOUT_USEC
) / 8;
2872 __storm_memset_struct(bp
, addr
, size
, (u32
*)&m_rs_vn
);
2874 /* read relevant values from mf_cfg struct in shmem */
2876 (MF_CFG_RD(bp
, func_mf_config
[func
].e1hov_tag
) &
2877 FUNC_MF_CFG_E1HOV_TAG_MASK
) >>
2878 FUNC_MF_CFG_E1HOV_TAG_SHIFT
;
2880 (MF_CFG_RD(bp
, func_mf_config
[func
].e1hov_tag
) &
2881 FUNC_MF_CFG_AFEX_VLAN_MASK
) >>
2882 FUNC_MF_CFG_AFEX_VLAN_SHIFT
;
2883 vlan_prio
= (mf_config
&
2884 FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK
) >>
2885 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT
;
2886 vlan_val
|= (vlan_prio
<< VLAN_PRIO_SHIFT
);
2889 func_mf_config
[func
].afex_config
) &
2890 FUNC_MF_CFG_AFEX_VLAN_MODE_MASK
) >>
2891 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT
;
2894 func_mf_config
[func
].afex_config
) &
2895 FUNC_MF_CFG_AFEX_COS_FILTER_MASK
) >>
2896 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT
;
2898 /* send ramrod to FW, return in case of failure */
2899 if (bnx2x_afex_func_update(bp
, vif_id
, vlan_val
,
2903 bp
->afex_def_vlan_tag
= vlan_val
;
2904 bp
->afex_vlan_mode
= vlan_mode
;
2906 /* notify link down because BP->flags is disabled */
2907 bnx2x_link_report(bp
);
2909 /* send INVALID VIF ramrod to FW */
2910 bnx2x_afex_func_update(bp
, 0xFFFF, 0, 0);
2912 /* Reset the default afex VLAN */
2913 bp
->afex_def_vlan_tag
= -1;
2918 static void bnx2x_handle_update_svid_cmd(struct bnx2x
*bp
)
2920 struct bnx2x_func_switch_update_params
*switch_update_params
;
2921 struct bnx2x_func_state_params func_params
;
2923 memset(&func_params
, 0, sizeof(struct bnx2x_func_state_params
));
2924 switch_update_params
= &func_params
.params
.switch_update
;
2925 func_params
.f_obj
= &bp
->func_obj
;
2926 func_params
.cmd
= BNX2X_F_CMD_SWITCH_UPDATE
;
2928 if (IS_MF_UFP(bp
) || IS_MF_BD(bp
)) {
2929 int func
= BP_ABS_FUNC(bp
);
2932 /* Re-learn the S-tag from shmem */
2933 val
= MF_CFG_RD(bp
, func_mf_config
[func
].e1hov_tag
) &
2934 FUNC_MF_CFG_E1HOV_TAG_MASK
;
2935 if (val
!= FUNC_MF_CFG_E1HOV_TAG_DEFAULT
) {
2938 BNX2X_ERR("Got an SVID event, but no tag is configured in shmem\n");
2942 /* Configure new S-tag in LLH */
2943 REG_WR(bp
, NIG_REG_LLH0_FUNC_VLAN_ID
+ BP_PORT(bp
) * 8,
2946 /* Send Ramrod to update FW of change */
2947 __set_bit(BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG
,
2948 &switch_update_params
->changes
);
2949 switch_update_params
->vlan
= bp
->mf_ov
;
2951 if (bnx2x_func_state_change(bp
, &func_params
) < 0) {
2952 BNX2X_ERR("Failed to configure FW of S-tag Change to %02x\n",
2956 DP(BNX2X_MSG_MCP
, "Configured S-tag %02x\n",
2963 bnx2x_fw_command(bp
, DRV_MSG_CODE_OEM_UPDATE_SVID_OK
, 0);
2966 bnx2x_fw_command(bp
, DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE
, 0);
2969 static void bnx2x_pmf_update(struct bnx2x
*bp
)
2971 int port
= BP_PORT(bp
);
2975 DP(BNX2X_MSG_MCP
, "pmf %d\n", bp
->port
.pmf
);
2978 * We need the mb() to ensure the ordering between the writing to
2979 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2983 /* queue a periodic task */
2984 queue_delayed_work(bnx2x_wq
, &bp
->period_task
, 0);
2986 bnx2x_dcbx_pmf_update(bp
);
2988 /* enable nig attention */
2989 val
= (0xff0f | (1 << (BP_VN(bp
) + 4)));
2990 if (bp
->common
.int_block
== INT_BLOCK_HC
) {
2991 REG_WR(bp
, HC_REG_TRAILING_EDGE_0
+ port
*8, val
);
2992 REG_WR(bp
, HC_REG_LEADING_EDGE_0
+ port
*8, val
);
2993 } else if (!CHIP_IS_E1x(bp
)) {
2994 REG_WR(bp
, IGU_REG_TRAILING_EDGE_LATCH
, val
);
2995 REG_WR(bp
, IGU_REG_LEADING_EDGE_LATCH
, val
);
2998 bnx2x_stats_handle(bp
, STATS_EVENT_PMF
);
3006 * General service functions
3009 /* send the MCP a request, block until there is a reply */
3010 u32
bnx2x_fw_command(struct bnx2x
*bp
, u32 command
, u32 param
)
3012 int mb_idx
= BP_FW_MB_IDX(bp
);
3016 u8 delay
= CHIP_REV_IS_SLOW(bp
) ? 100 : 10;
3018 mutex_lock(&bp
->fw_mb_mutex
);
3020 SHMEM_WR(bp
, func_mb
[mb_idx
].drv_mb_param
, param
);
3021 SHMEM_WR(bp
, func_mb
[mb_idx
].drv_mb_header
, (command
| seq
));
3023 DP(BNX2X_MSG_MCP
, "wrote command (%x) to FW MB param 0x%08x\n",
3024 (command
| seq
), param
);
3027 /* let the FW do it's magic ... */
3030 rc
= SHMEM_RD(bp
, func_mb
[mb_idx
].fw_mb_header
);
3032 /* Give the FW up to 5 second (500*10ms) */
3033 } while ((seq
!= (rc
& FW_MSG_SEQ_NUMBER_MASK
)) && (cnt
++ < 500));
3035 DP(BNX2X_MSG_MCP
, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
3036 cnt
*delay
, rc
, seq
);
3038 /* is this a reply to our command? */
3039 if (seq
== (rc
& FW_MSG_SEQ_NUMBER_MASK
))
3040 rc
&= FW_MSG_CODE_MASK
;
3043 BNX2X_ERR("FW failed to respond!\n");
3047 mutex_unlock(&bp
->fw_mb_mutex
);
3052 static void storm_memset_func_cfg(struct bnx2x
*bp
,
3053 struct tstorm_eth_function_common_config
*tcfg
,
3056 size_t size
= sizeof(struct tstorm_eth_function_common_config
);
3058 u32 addr
= BAR_TSTRORM_INTMEM
+
3059 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid
);
3061 __storm_memset_struct(bp
, addr
, size
, (u32
*)tcfg
);
3064 void bnx2x_func_init(struct bnx2x
*bp
, struct bnx2x_func_init_params
*p
)
3066 if (CHIP_IS_E1x(bp
)) {
3067 struct tstorm_eth_function_common_config tcfg
= {0};
3069 storm_memset_func_cfg(bp
, &tcfg
, p
->func_id
);
3072 /* Enable the function in the FW */
3073 storm_memset_vf_to_pf(bp
, p
->func_id
, p
->pf_id
);
3074 storm_memset_func_en(bp
, p
->func_id
, 1);
3077 if (p
->spq_active
) {
3078 storm_memset_spq_addr(bp
, p
->spq_map
, p
->func_id
);
3079 REG_WR(bp
, XSEM_REG_FAST_MEMORY
+
3080 XSTORM_SPQ_PROD_OFFSET(p
->func_id
), p
->spq_prod
);
3085 * bnx2x_get_common_flags - Return common flags
3089 * @zero_stats TRUE if statistics zeroing is needed
3091 * Return the flags that are common for the Tx-only and not normal connections.
3093 static unsigned long bnx2x_get_common_flags(struct bnx2x
*bp
,
3094 struct bnx2x_fastpath
*fp
,
3097 unsigned long flags
= 0;
3099 /* PF driver will always initialize the Queue to an ACTIVE state */
3100 __set_bit(BNX2X_Q_FLG_ACTIVE
, &flags
);
3102 /* tx only connections collect statistics (on the same index as the
3103 * parent connection). The statistics are zeroed when the parent
3104 * connection is initialized.
3107 __set_bit(BNX2X_Q_FLG_STATS
, &flags
);
3109 __set_bit(BNX2X_Q_FLG_ZERO_STATS
, &flags
);
3111 if (bp
->flags
& TX_SWITCHING
)
3112 __set_bit(BNX2X_Q_FLG_TX_SWITCH
, &flags
);
3114 __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT
, &flags
);
3115 __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID
, &flags
);
3117 #ifdef BNX2X_STOP_ON_ERROR
3118 __set_bit(BNX2X_Q_FLG_TX_SEC
, &flags
);
3124 static unsigned long bnx2x_get_q_flags(struct bnx2x
*bp
,
3125 struct bnx2x_fastpath
*fp
,
3128 unsigned long flags
= 0;
3130 /* calculate other queue flags */
3132 __set_bit(BNX2X_Q_FLG_OV
, &flags
);
3134 if (IS_FCOE_FP(fp
)) {
3135 __set_bit(BNX2X_Q_FLG_FCOE
, &flags
);
3136 /* For FCoE - force usage of default priority (for afex) */
3137 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI
, &flags
);
3140 if (fp
->mode
!= TPA_MODE_DISABLED
) {
3141 __set_bit(BNX2X_Q_FLG_TPA
, &flags
);
3142 __set_bit(BNX2X_Q_FLG_TPA_IPV6
, &flags
);
3143 if (fp
->mode
== TPA_MODE_GRO
)
3144 __set_bit(BNX2X_Q_FLG_TPA_GRO
, &flags
);
3148 __set_bit(BNX2X_Q_FLG_LEADING_RSS
, &flags
);
3149 __set_bit(BNX2X_Q_FLG_MCAST
, &flags
);
3152 /* Always set HW VLAN stripping */
3153 __set_bit(BNX2X_Q_FLG_VLAN
, &flags
);
3155 /* configure silent vlan removal */
3157 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM
, &flags
);
3159 return flags
| bnx2x_get_common_flags(bp
, fp
, true);
3162 static void bnx2x_pf_q_prep_general(struct bnx2x
*bp
,
3163 struct bnx2x_fastpath
*fp
, struct bnx2x_general_setup_params
*gen_init
,
3166 gen_init
->stat_id
= bnx2x_stats_id(fp
);
3167 gen_init
->spcl_id
= fp
->cl_id
;
3169 /* Always use mini-jumbo MTU for FCoE L2 ring */
3171 gen_init
->mtu
= BNX2X_FCOE_MINI_JUMBO_MTU
;
3173 gen_init
->mtu
= bp
->dev
->mtu
;
3175 gen_init
->cos
= cos
;
3177 gen_init
->fp_hsi
= ETH_FP_HSI_VERSION
;
3180 static void bnx2x_pf_rx_q_prep(struct bnx2x
*bp
,
3181 struct bnx2x_fastpath
*fp
, struct rxq_pause_params
*pause
,
3182 struct bnx2x_rxq_setup_params
*rxq_init
)
3186 u16 tpa_agg_size
= 0;
3188 if (fp
->mode
!= TPA_MODE_DISABLED
) {
3189 pause
->sge_th_lo
= SGE_TH_LO(bp
);
3190 pause
->sge_th_hi
= SGE_TH_HI(bp
);
3192 /* validate SGE ring has enough to cross high threshold */
3193 WARN_ON(bp
->dropless_fc
&&
3194 pause
->sge_th_hi
+ FW_PREFETCH_CNT
>
3195 MAX_RX_SGE_CNT
* NUM_RX_SGE_PAGES
);
3197 tpa_agg_size
= TPA_AGG_SIZE
;
3198 max_sge
= SGE_PAGE_ALIGN(bp
->dev
->mtu
) >>
3200 max_sge
= ((max_sge
+ PAGES_PER_SGE
- 1) &
3201 (~(PAGES_PER_SGE
-1))) >> PAGES_PER_SGE_SHIFT
;
3202 sge_sz
= (u16
)min_t(u32
, SGE_PAGES
, 0xffff);
3205 /* pause - not for e1 */
3206 if (!CHIP_IS_E1(bp
)) {
3207 pause
->bd_th_lo
= BD_TH_LO(bp
);
3208 pause
->bd_th_hi
= BD_TH_HI(bp
);
3210 pause
->rcq_th_lo
= RCQ_TH_LO(bp
);
3211 pause
->rcq_th_hi
= RCQ_TH_HI(bp
);
3213 * validate that rings have enough entries to cross
3216 WARN_ON(bp
->dropless_fc
&&
3217 pause
->bd_th_hi
+ FW_PREFETCH_CNT
>
3219 WARN_ON(bp
->dropless_fc
&&
3220 pause
->rcq_th_hi
+ FW_PREFETCH_CNT
>
3221 NUM_RCQ_RINGS
* MAX_RCQ_DESC_CNT
);
3227 rxq_init
->dscr_map
= fp
->rx_desc_mapping
;
3228 rxq_init
->sge_map
= fp
->rx_sge_mapping
;
3229 rxq_init
->rcq_map
= fp
->rx_comp_mapping
;
3230 rxq_init
->rcq_np_map
= fp
->rx_comp_mapping
+ BCM_PAGE_SIZE
;
3232 /* This should be a maximum number of data bytes that may be
3233 * placed on the BD (not including paddings).
3235 rxq_init
->buf_sz
= fp
->rx_buf_size
- BNX2X_FW_RX_ALIGN_START
-
3236 BNX2X_FW_RX_ALIGN_END
- IP_HEADER_ALIGNMENT_PADDING
;
3238 rxq_init
->cl_qzone_id
= fp
->cl_qzone_id
;
3239 rxq_init
->tpa_agg_sz
= tpa_agg_size
;
3240 rxq_init
->sge_buf_sz
= sge_sz
;
3241 rxq_init
->max_sges_pkt
= max_sge
;
3242 rxq_init
->rss_engine_id
= BP_FUNC(bp
);
3243 rxq_init
->mcast_engine_id
= BP_FUNC(bp
);
3245 /* Maximum number or simultaneous TPA aggregation for this Queue.
3247 * For PF Clients it should be the maximum available number.
3248 * VF driver(s) may want to define it to a smaller value.
3250 rxq_init
->max_tpa_queues
= MAX_AGG_QS(bp
);
3252 rxq_init
->cache_line_log
= BNX2X_RX_ALIGN_SHIFT
;
3253 rxq_init
->fw_sb_id
= fp
->fw_sb_id
;
3256 rxq_init
->sb_cq_index
= HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS
;
3258 rxq_init
->sb_cq_index
= HC_INDEX_ETH_RX_CQ_CONS
;
3259 /* configure silent vlan removal
3260 * if multi function mode is afex, then mask default vlan
3262 if (IS_MF_AFEX(bp
)) {
3263 rxq_init
->silent_removal_value
= bp
->afex_def_vlan_tag
;
3264 rxq_init
->silent_removal_mask
= VLAN_VID_MASK
;
3268 static void bnx2x_pf_tx_q_prep(struct bnx2x
*bp
,
3269 struct bnx2x_fastpath
*fp
, struct bnx2x_txq_setup_params
*txq_init
,
3272 txq_init
->dscr_map
= fp
->txdata_ptr
[cos
]->tx_desc_mapping
;
3273 txq_init
->sb_cq_index
= HC_INDEX_ETH_FIRST_TX_CQ_CONS
+ cos
;
3274 txq_init
->traffic_type
= LLFC_TRAFFIC_TYPE_NW
;
3275 txq_init
->fw_sb_id
= fp
->fw_sb_id
;
3278 * set the tss leading client id for TX classification ==
3279 * leading RSS client id
3281 txq_init
->tss_leading_cl_id
= bnx2x_fp(bp
, 0, cl_id
);
3283 if (IS_FCOE_FP(fp
)) {
3284 txq_init
->sb_cq_index
= HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS
;
3285 txq_init
->traffic_type
= LLFC_TRAFFIC_TYPE_FCOE
;
3289 static void bnx2x_pf_init(struct bnx2x
*bp
)
3291 struct bnx2x_func_init_params func_init
= {0};
3292 struct event_ring_data eq_data
= { {0} };
3294 if (!CHIP_IS_E1x(bp
)) {
3295 /* reset IGU PF statistics: MSIX + ATTN */
3297 REG_WR(bp
, IGU_REG_STATISTIC_NUM_MESSAGE_SENT
+
3298 BNX2X_IGU_STAS_MSG_VF_CNT
*4 +
3299 (CHIP_MODE_IS_4_PORT(bp
) ?
3300 BP_FUNC(bp
) : BP_VN(bp
))*4, 0);
3302 REG_WR(bp
, IGU_REG_STATISTIC_NUM_MESSAGE_SENT
+
3303 BNX2X_IGU_STAS_MSG_VF_CNT
*4 +
3304 BNX2X_IGU_STAS_MSG_PF_CNT
*4 +
3305 (CHIP_MODE_IS_4_PORT(bp
) ?
3306 BP_FUNC(bp
) : BP_VN(bp
))*4, 0);
3309 func_init
.spq_active
= true;
3310 func_init
.pf_id
= BP_FUNC(bp
);
3311 func_init
.func_id
= BP_FUNC(bp
);
3312 func_init
.spq_map
= bp
->spq_mapping
;
3313 func_init
.spq_prod
= bp
->spq_prod_idx
;
3315 bnx2x_func_init(bp
, &func_init
);
3317 memset(&(bp
->cmng
), 0, sizeof(struct cmng_struct_per_port
));
3320 * Congestion management values depend on the link rate
3321 * There is no active link so initial link rate is set to 10 Gbps.
3322 * When the link comes up The congestion management values are
3323 * re-calculated according to the actual link rate.
3325 bp
->link_vars
.line_speed
= SPEED_10000
;
3326 bnx2x_cmng_fns_init(bp
, true, bnx2x_get_cmng_fns_mode(bp
));
3328 /* Only the PMF sets the HW */
3330 storm_memset_cmng(bp
, &bp
->cmng
, BP_PORT(bp
));
3332 /* init Event Queue - PCI bus guarantees correct endianity*/
3333 eq_data
.base_addr
.hi
= U64_HI(bp
->eq_mapping
);
3334 eq_data
.base_addr
.lo
= U64_LO(bp
->eq_mapping
);
3335 eq_data
.producer
= bp
->eq_prod
;
3336 eq_data
.index_id
= HC_SP_INDEX_EQ_CONS
;
3337 eq_data
.sb_id
= DEF_SB_ID
;
3338 storm_memset_eq_data(bp
, &eq_data
, BP_FUNC(bp
));
3341 static void bnx2x_e1h_disable(struct bnx2x
*bp
)
3343 int port
= BP_PORT(bp
);
3345 bnx2x_tx_disable(bp
);
3347 REG_WR(bp
, NIG_REG_LLH0_FUNC_EN
+ port
*8, 0);
3350 static void bnx2x_e1h_enable(struct bnx2x
*bp
)
3352 int port
= BP_PORT(bp
);
3354 if (!(IS_MF_UFP(bp
) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp
)))
3355 REG_WR(bp
, NIG_REG_LLH0_FUNC_EN
+ port
* 8, 1);
3357 /* Tx queue should be only re-enabled */
3358 netif_tx_wake_all_queues(bp
->dev
);
3361 * Should not call netif_carrier_on since it will be called if the link
3362 * is up when checking for link state
3366 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3368 static void bnx2x_drv_info_ether_stat(struct bnx2x
*bp
)
3370 struct eth_stats_info
*ether_stat
=
3371 &bp
->slowpath
->drv_info_to_mcp
.ether_stat
;
3372 struct bnx2x_vlan_mac_obj
*mac_obj
=
3373 &bp
->sp_objs
->mac_obj
;
3376 strlcpy(ether_stat
->version
, DRV_MODULE_VERSION
,
3377 ETH_STAT_INFO_VERSION_LEN
);
3379 /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3380 * mac_local field in ether_stat struct. The base address is offset by 2
3381 * bytes to account for the field being 8 bytes but a mac address is
3382 * only 6 bytes. Likewise, the stride for the get_n_elements function is
3383 * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3384 * allocated by the ether_stat struct, so the macs will land in their
3387 for (i
= 0; i
< DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED
; i
++)
3388 memset(ether_stat
->mac_local
+ i
, 0,
3389 sizeof(ether_stat
->mac_local
[0]));
3390 mac_obj
->get_n_elements(bp
, &bp
->sp_objs
[0].mac_obj
,
3391 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED
,
3392 ether_stat
->mac_local
+ MAC_PAD
, MAC_PAD
,
3394 ether_stat
->mtu_size
= bp
->dev
->mtu
;
3395 if (bp
->dev
->features
& NETIF_F_RXCSUM
)
3396 ether_stat
->feature_flags
|= FEATURE_ETH_CHKSUM_OFFLOAD_MASK
;
3397 if (bp
->dev
->features
& NETIF_F_TSO
)
3398 ether_stat
->feature_flags
|= FEATURE_ETH_LSO_MASK
;
3399 ether_stat
->feature_flags
|= bp
->common
.boot_mode
;
3401 ether_stat
->promiscuous_mode
= (bp
->dev
->flags
& IFF_PROMISC
) ? 1 : 0;
3403 ether_stat
->txq_size
= bp
->tx_ring_size
;
3404 ether_stat
->rxq_size
= bp
->rx_ring_size
;
3406 #ifdef CONFIG_BNX2X_SRIOV
3407 ether_stat
->vf_cnt
= IS_SRIOV(bp
) ? bp
->vfdb
->sriov
.nr_virtfn
: 0;
3411 static void bnx2x_drv_info_fcoe_stat(struct bnx2x
*bp
)
3413 struct bnx2x_dcbx_app_params
*app
= &bp
->dcbx_port_params
.app
;
3414 struct fcoe_stats_info
*fcoe_stat
=
3415 &bp
->slowpath
->drv_info_to_mcp
.fcoe_stat
;
3417 if (!CNIC_LOADED(bp
))
3420 memcpy(fcoe_stat
->mac_local
+ MAC_PAD
, bp
->fip_mac
, ETH_ALEN
);
3422 fcoe_stat
->qos_priority
=
3423 app
->traffic_type_priority
[LLFC_TRAFFIC_TYPE_FCOE
];
3425 /* insert FCoE stats from ramrod response */
3427 struct tstorm_per_queue_stats
*fcoe_q_tstorm_stats
=
3428 &bp
->fw_stats_data
->queue_stats
[FCOE_IDX(bp
)].
3429 tstorm_queue_statistics
;
3431 struct xstorm_per_queue_stats
*fcoe_q_xstorm_stats
=
3432 &bp
->fw_stats_data
->queue_stats
[FCOE_IDX(bp
)].
3433 xstorm_queue_statistics
;
3435 struct fcoe_statistics_params
*fw_fcoe_stat
=
3436 &bp
->fw_stats_data
->fcoe
;
3438 ADD_64_LE(fcoe_stat
->rx_bytes_hi
, LE32_0
,
3439 fcoe_stat
->rx_bytes_lo
,
3440 fw_fcoe_stat
->rx_stat0
.fcoe_rx_byte_cnt
);
3442 ADD_64_LE(fcoe_stat
->rx_bytes_hi
,
3443 fcoe_q_tstorm_stats
->rcv_ucast_bytes
.hi
,
3444 fcoe_stat
->rx_bytes_lo
,
3445 fcoe_q_tstorm_stats
->rcv_ucast_bytes
.lo
);
3447 ADD_64_LE(fcoe_stat
->rx_bytes_hi
,
3448 fcoe_q_tstorm_stats
->rcv_bcast_bytes
.hi
,
3449 fcoe_stat
->rx_bytes_lo
,
3450 fcoe_q_tstorm_stats
->rcv_bcast_bytes
.lo
);
3452 ADD_64_LE(fcoe_stat
->rx_bytes_hi
,
3453 fcoe_q_tstorm_stats
->rcv_mcast_bytes
.hi
,
3454 fcoe_stat
->rx_bytes_lo
,
3455 fcoe_q_tstorm_stats
->rcv_mcast_bytes
.lo
);
3457 ADD_64_LE(fcoe_stat
->rx_frames_hi
, LE32_0
,
3458 fcoe_stat
->rx_frames_lo
,
3459 fw_fcoe_stat
->rx_stat0
.fcoe_rx_pkt_cnt
);
3461 ADD_64_LE(fcoe_stat
->rx_frames_hi
, LE32_0
,
3462 fcoe_stat
->rx_frames_lo
,
3463 fcoe_q_tstorm_stats
->rcv_ucast_pkts
);
3465 ADD_64_LE(fcoe_stat
->rx_frames_hi
, LE32_0
,
3466 fcoe_stat
->rx_frames_lo
,
3467 fcoe_q_tstorm_stats
->rcv_bcast_pkts
);
3469 ADD_64_LE(fcoe_stat
->rx_frames_hi
, LE32_0
,
3470 fcoe_stat
->rx_frames_lo
,
3471 fcoe_q_tstorm_stats
->rcv_mcast_pkts
);
3473 ADD_64_LE(fcoe_stat
->tx_bytes_hi
, LE32_0
,
3474 fcoe_stat
->tx_bytes_lo
,
3475 fw_fcoe_stat
->tx_stat
.fcoe_tx_byte_cnt
);
3477 ADD_64_LE(fcoe_stat
->tx_bytes_hi
,
3478 fcoe_q_xstorm_stats
->ucast_bytes_sent
.hi
,
3479 fcoe_stat
->tx_bytes_lo
,
3480 fcoe_q_xstorm_stats
->ucast_bytes_sent
.lo
);
3482 ADD_64_LE(fcoe_stat
->tx_bytes_hi
,
3483 fcoe_q_xstorm_stats
->bcast_bytes_sent
.hi
,
3484 fcoe_stat
->tx_bytes_lo
,
3485 fcoe_q_xstorm_stats
->bcast_bytes_sent
.lo
);
3487 ADD_64_LE(fcoe_stat
->tx_bytes_hi
,
3488 fcoe_q_xstorm_stats
->mcast_bytes_sent
.hi
,
3489 fcoe_stat
->tx_bytes_lo
,
3490 fcoe_q_xstorm_stats
->mcast_bytes_sent
.lo
);
3492 ADD_64_LE(fcoe_stat
->tx_frames_hi
, LE32_0
,
3493 fcoe_stat
->tx_frames_lo
,
3494 fw_fcoe_stat
->tx_stat
.fcoe_tx_pkt_cnt
);
3496 ADD_64_LE(fcoe_stat
->tx_frames_hi
, LE32_0
,
3497 fcoe_stat
->tx_frames_lo
,
3498 fcoe_q_xstorm_stats
->ucast_pkts_sent
);
3500 ADD_64_LE(fcoe_stat
->tx_frames_hi
, LE32_0
,
3501 fcoe_stat
->tx_frames_lo
,
3502 fcoe_q_xstorm_stats
->bcast_pkts_sent
);
3504 ADD_64_LE(fcoe_stat
->tx_frames_hi
, LE32_0
,
3505 fcoe_stat
->tx_frames_lo
,
3506 fcoe_q_xstorm_stats
->mcast_pkts_sent
);
3509 /* ask L5 driver to add data to the struct */
3510 bnx2x_cnic_notify(bp
, CNIC_CTL_FCOE_STATS_GET_CMD
);
3513 static void bnx2x_drv_info_iscsi_stat(struct bnx2x
*bp
)
3515 struct bnx2x_dcbx_app_params
*app
= &bp
->dcbx_port_params
.app
;
3516 struct iscsi_stats_info
*iscsi_stat
=
3517 &bp
->slowpath
->drv_info_to_mcp
.iscsi_stat
;
3519 if (!CNIC_LOADED(bp
))
3522 memcpy(iscsi_stat
->mac_local
+ MAC_PAD
, bp
->cnic_eth_dev
.iscsi_mac
,
3525 iscsi_stat
->qos_priority
=
3526 app
->traffic_type_priority
[LLFC_TRAFFIC_TYPE_ISCSI
];
3528 /* ask L5 driver to add data to the struct */
3529 bnx2x_cnic_notify(bp
, CNIC_CTL_ISCSI_STATS_GET_CMD
);
3532 /* called due to MCP event (on pmf):
3533 * reread new bandwidth configuration
3535 * notify others function about the change
3537 static void bnx2x_config_mf_bw(struct bnx2x
*bp
)
3539 if (bp
->link_vars
.link_up
) {
3540 bnx2x_cmng_fns_init(bp
, true, CMNG_FNS_MINMAX
);
3541 bnx2x_link_sync_notify(bp
);
3543 storm_memset_cmng(bp
, &bp
->cmng
, BP_PORT(bp
));
3546 static void bnx2x_set_mf_bw(struct bnx2x
*bp
)
3548 bnx2x_config_mf_bw(bp
);
3549 bnx2x_fw_command(bp
, DRV_MSG_CODE_SET_MF_BW_ACK
, 0);
3552 static void bnx2x_handle_eee_event(struct bnx2x
*bp
)
3554 DP(BNX2X_MSG_MCP
, "EEE - LLDP event\n");
3555 bnx2x_fw_command(bp
, DRV_MSG_CODE_EEE_RESULTS_ACK
, 0);
3558 #define BNX2X_UPDATE_DRV_INFO_IND_LENGTH (20)
3559 #define BNX2X_UPDATE_DRV_INFO_IND_COUNT (25)
3561 static void bnx2x_handle_drv_info_req(struct bnx2x
*bp
)
3563 enum drv_info_opcode op_code
;
3564 u32 drv_info_ctl
= SHMEM2_RD(bp
, drv_info_control
);
3565 bool release
= false;
3568 /* if drv_info version supported by MFW doesn't match - send NACK */
3569 if ((drv_info_ctl
& DRV_INFO_CONTROL_VER_MASK
) != DRV_INFO_CUR_VER
) {
3570 bnx2x_fw_command(bp
, DRV_MSG_CODE_DRV_INFO_NACK
, 0);
3574 op_code
= (drv_info_ctl
& DRV_INFO_CONTROL_OP_CODE_MASK
) >>
3575 DRV_INFO_CONTROL_OP_CODE_SHIFT
;
3577 /* Must prevent other flows from accessing drv_info_to_mcp */
3578 mutex_lock(&bp
->drv_info_mutex
);
3580 memset(&bp
->slowpath
->drv_info_to_mcp
, 0,
3581 sizeof(union drv_info_to_mcp
));
3584 case ETH_STATS_OPCODE
:
3585 bnx2x_drv_info_ether_stat(bp
);
3587 case FCOE_STATS_OPCODE
:
3588 bnx2x_drv_info_fcoe_stat(bp
);
3590 case ISCSI_STATS_OPCODE
:
3591 bnx2x_drv_info_iscsi_stat(bp
);
3594 /* if op code isn't supported - send NACK */
3595 bnx2x_fw_command(bp
, DRV_MSG_CODE_DRV_INFO_NACK
, 0);
3599 /* if we got drv_info attn from MFW then these fields are defined in
3602 SHMEM2_WR(bp
, drv_info_host_addr_lo
,
3603 U64_LO(bnx2x_sp_mapping(bp
, drv_info_to_mcp
)));
3604 SHMEM2_WR(bp
, drv_info_host_addr_hi
,
3605 U64_HI(bnx2x_sp_mapping(bp
, drv_info_to_mcp
)));
3607 bnx2x_fw_command(bp
, DRV_MSG_CODE_DRV_INFO_ACK
, 0);
3609 /* Since possible management wants both this and get_driver_version
3610 * need to wait until management notifies us it finished utilizing
3613 if (!SHMEM2_HAS(bp
, mfw_drv_indication
)) {
3614 DP(BNX2X_MSG_MCP
, "Management does not support indication\n");
3615 } else if (!bp
->drv_info_mng_owner
) {
3616 u32 bit
= MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp
) >> 1));
3618 for (wait
= 0; wait
< BNX2X_UPDATE_DRV_INFO_IND_COUNT
; wait
++) {
3619 u32 indication
= SHMEM2_RD(bp
, mfw_drv_indication
);
3621 /* Management is done; need to clear indication */
3622 if (indication
& bit
) {
3623 SHMEM2_WR(bp
, mfw_drv_indication
,
3629 msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH
);
3633 DP(BNX2X_MSG_MCP
, "Management did not release indication\n");
3634 bp
->drv_info_mng_owner
= true;
3638 mutex_unlock(&bp
->drv_info_mutex
);
3641 static u32
bnx2x_update_mng_version_utility(u8
*version
, bool bnx2x_format
)
3647 i
= sscanf(version
, "1.%c%hhd.%hhd.%hhd",
3648 &vals
[0], &vals
[1], &vals
[2], &vals
[3]);
3652 i
= sscanf(version
, "%hhd.%hhd.%hhd.%hhd",
3653 &vals
[0], &vals
[1], &vals
[2], &vals
[3]);
3659 return (vals
[0] << 24) | (vals
[1] << 16) | (vals
[2] << 8) | vals
[3];
3662 void bnx2x_update_mng_version(struct bnx2x
*bp
)
3664 u32 iscsiver
= DRV_VER_NOT_LOADED
;
3665 u32 fcoever
= DRV_VER_NOT_LOADED
;
3666 u32 ethver
= DRV_VER_NOT_LOADED
;
3667 int idx
= BP_FW_MB_IDX(bp
);
3670 if (!SHMEM2_HAS(bp
, func_os_drv_ver
))
3673 mutex_lock(&bp
->drv_info_mutex
);
3674 /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */
3675 if (bp
->drv_info_mng_owner
)
3678 if (bp
->state
!= BNX2X_STATE_OPEN
)
3681 /* Parse ethernet driver version */
3682 ethver
= bnx2x_update_mng_version_utility(DRV_MODULE_VERSION
, true);
3683 if (!CNIC_LOADED(bp
))
3686 /* Try getting storage driver version via cnic */
3687 memset(&bp
->slowpath
->drv_info_to_mcp
, 0,
3688 sizeof(union drv_info_to_mcp
));
3689 bnx2x_drv_info_iscsi_stat(bp
);
3690 version
= bp
->slowpath
->drv_info_to_mcp
.iscsi_stat
.version
;
3691 iscsiver
= bnx2x_update_mng_version_utility(version
, false);
3693 memset(&bp
->slowpath
->drv_info_to_mcp
, 0,
3694 sizeof(union drv_info_to_mcp
));
3695 bnx2x_drv_info_fcoe_stat(bp
);
3696 version
= bp
->slowpath
->drv_info_to_mcp
.fcoe_stat
.version
;
3697 fcoever
= bnx2x_update_mng_version_utility(version
, false);
3700 SHMEM2_WR(bp
, func_os_drv_ver
[idx
].versions
[DRV_PERS_ETHERNET
], ethver
);
3701 SHMEM2_WR(bp
, func_os_drv_ver
[idx
].versions
[DRV_PERS_ISCSI
], iscsiver
);
3702 SHMEM2_WR(bp
, func_os_drv_ver
[idx
].versions
[DRV_PERS_FCOE
], fcoever
);
3704 mutex_unlock(&bp
->drv_info_mutex
);
3706 DP(BNX2X_MSG_MCP
, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n",
3707 ethver
, iscsiver
, fcoever
);
3710 void bnx2x_update_mfw_dump(struct bnx2x
*bp
)
3715 if (!SHMEM2_HAS(bp
, drv_info
))
3718 /* Update Driver load time, possibly broken in y2038 */
3719 SHMEM2_WR(bp
, drv_info
.epoc
, (u32
)ktime_get_real_seconds());
3721 drv_ver
= bnx2x_update_mng_version_utility(DRV_MODULE_VERSION
, true);
3722 SHMEM2_WR(bp
, drv_info
.drv_ver
, drv_ver
);
3724 SHMEM2_WR(bp
, drv_info
.fw_ver
, REG_RD(bp
, XSEM_REG_PRAM
));
3726 /* Check & notify On-Chip dump. */
3727 valid_dump
= SHMEM2_RD(bp
, drv_info
.valid_dump
);
3729 if (valid_dump
& FIRST_DUMP_VALID
)
3730 DP(NETIF_MSG_IFUP
, "A valid On-Chip MFW dump found on 1st partition\n");
3732 if (valid_dump
& SECOND_DUMP_VALID
)
3733 DP(NETIF_MSG_IFUP
, "A valid On-Chip MFW dump found on 2nd partition\n");
3736 static void bnx2x_oem_event(struct bnx2x
*bp
, u32 event
)
3738 u32 cmd_ok
, cmd_fail
;
3741 if (event
& DRV_STATUS_DCC_EVENT_MASK
&&
3742 event
& DRV_STATUS_OEM_EVENT_MASK
) {
3743 BNX2X_ERR("Received simultaneous events %08x\n", event
);
3747 if (event
& DRV_STATUS_DCC_EVENT_MASK
) {
3748 cmd_fail
= DRV_MSG_CODE_DCC_FAILURE
;
3749 cmd_ok
= DRV_MSG_CODE_DCC_OK
;
3750 } else /* if (event & DRV_STATUS_OEM_EVENT_MASK) */ {
3751 cmd_fail
= DRV_MSG_CODE_OEM_FAILURE
;
3752 cmd_ok
= DRV_MSG_CODE_OEM_OK
;
3755 DP(BNX2X_MSG_MCP
, "oem_event 0x%x\n", event
);
3757 if (event
& (DRV_STATUS_DCC_DISABLE_ENABLE_PF
|
3758 DRV_STATUS_OEM_DISABLE_ENABLE_PF
)) {
3759 /* This is the only place besides the function initialization
3760 * where the bp->flags can change so it is done without any
3763 if (bp
->mf_config
[BP_VN(bp
)] & FUNC_MF_CFG_FUNC_DISABLED
) {
3764 DP(BNX2X_MSG_MCP
, "mf_cfg function disabled\n");
3765 bp
->flags
|= MF_FUNC_DIS
;
3767 bnx2x_e1h_disable(bp
);
3769 DP(BNX2X_MSG_MCP
, "mf_cfg function enabled\n");
3770 bp
->flags
&= ~MF_FUNC_DIS
;
3772 bnx2x_e1h_enable(bp
);
3774 event
&= ~(DRV_STATUS_DCC_DISABLE_ENABLE_PF
|
3775 DRV_STATUS_OEM_DISABLE_ENABLE_PF
);
3778 if (event
& (DRV_STATUS_DCC_BANDWIDTH_ALLOCATION
|
3779 DRV_STATUS_OEM_BANDWIDTH_ALLOCATION
)) {
3780 bnx2x_config_mf_bw(bp
);
3781 event
&= ~(DRV_STATUS_DCC_BANDWIDTH_ALLOCATION
|
3782 DRV_STATUS_OEM_BANDWIDTH_ALLOCATION
);
3785 /* Report results to MCP */
3787 bnx2x_fw_command(bp
, cmd_fail
, 0);
3789 bnx2x_fw_command(bp
, cmd_ok
, 0);
3792 /* must be called under the spq lock */
3793 static struct eth_spe
*bnx2x_sp_get_next(struct bnx2x
*bp
)
3795 struct eth_spe
*next_spe
= bp
->spq_prod_bd
;
3797 if (bp
->spq_prod_bd
== bp
->spq_last_bd
) {
3798 bp
->spq_prod_bd
= bp
->spq
;
3799 bp
->spq_prod_idx
= 0;
3800 DP(BNX2X_MSG_SP
, "end of spq\n");
3808 /* must be called under the spq lock */
3809 static void bnx2x_sp_prod_update(struct bnx2x
*bp
)
3811 int func
= BP_FUNC(bp
);
3814 * Make sure that BD data is updated before writing the producer:
3815 * BD data is written to the memory, the producer is read from the
3816 * memory, thus we need a full memory barrier to ensure the ordering.
3820 REG_WR16(bp
, BAR_XSTRORM_INTMEM
+ XSTORM_SPQ_PROD_OFFSET(func
),
3826 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3828 * @cmd: command to check
3829 * @cmd_type: command type
3831 static bool bnx2x_is_contextless_ramrod(int cmd
, int cmd_type
)
3833 if ((cmd_type
== NONE_CONNECTION_TYPE
) ||
3834 (cmd
== RAMROD_CMD_ID_ETH_FORWARD_SETUP
) ||
3835 (cmd
== RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES
) ||
3836 (cmd
== RAMROD_CMD_ID_ETH_FILTER_RULES
) ||
3837 (cmd
== RAMROD_CMD_ID_ETH_MULTICAST_RULES
) ||
3838 (cmd
== RAMROD_CMD_ID_ETH_SET_MAC
) ||
3839 (cmd
== RAMROD_CMD_ID_ETH_RSS_UPDATE
))
3846 * bnx2x_sp_post - place a single command on an SP ring
3848 * @bp: driver handle
3849 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3850 * @cid: SW CID the command is related to
3851 * @data_hi: command private data address (high 32 bits)
3852 * @data_lo: command private data address (low 32 bits)
3853 * @cmd_type: command type (e.g. NONE, ETH)
3855 * SP data is handled as if it's always an address pair, thus data fields are
3856 * not swapped to little endian in upper functions. Instead this function swaps
3857 * data as if it's two u32 fields.
3859 int bnx2x_sp_post(struct bnx2x
*bp
, int command
, int cid
,
3860 u32 data_hi
, u32 data_lo
, int cmd_type
)
3862 struct eth_spe
*spe
;
3864 bool common
= bnx2x_is_contextless_ramrod(command
, cmd_type
);
3866 #ifdef BNX2X_STOP_ON_ERROR
3867 if (unlikely(bp
->panic
)) {
3868 BNX2X_ERR("Can't post SP when there is panic\n");
3873 spin_lock_bh(&bp
->spq_lock
);
3876 if (!atomic_read(&bp
->eq_spq_left
)) {
3877 BNX2X_ERR("BUG! EQ ring full!\n");
3878 spin_unlock_bh(&bp
->spq_lock
);
3882 } else if (!atomic_read(&bp
->cq_spq_left
)) {
3883 BNX2X_ERR("BUG! SPQ ring full!\n");
3884 spin_unlock_bh(&bp
->spq_lock
);
3889 spe
= bnx2x_sp_get_next(bp
);
3891 /* CID needs port number to be encoded int it */
3892 spe
->hdr
.conn_and_cmd_data
=
3893 cpu_to_le32((command
<< SPE_HDR_CMD_ID_SHIFT
) |
3896 /* In some cases, type may already contain the func-id
3897 * mainly in SRIOV related use cases, so we add it here only
3898 * if it's not already set.
3900 if (!(cmd_type
& SPE_HDR_FUNCTION_ID
)) {
3901 type
= (cmd_type
<< SPE_HDR_CONN_TYPE_SHIFT
) &
3903 type
|= ((BP_FUNC(bp
) << SPE_HDR_FUNCTION_ID_SHIFT
) &
3904 SPE_HDR_FUNCTION_ID
);
3909 spe
->hdr
.type
= cpu_to_le16(type
);
3911 spe
->data
.update_data_addr
.hi
= cpu_to_le32(data_hi
);
3912 spe
->data
.update_data_addr
.lo
= cpu_to_le32(data_lo
);
3915 * It's ok if the actual decrement is issued towards the memory
3916 * somewhere between the spin_lock and spin_unlock. Thus no
3917 * more explicit memory barrier is needed.
3920 atomic_dec(&bp
->eq_spq_left
);
3922 atomic_dec(&bp
->cq_spq_left
);
3925 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3926 bp
->spq_prod_idx
, (u32
)U64_HI(bp
->spq_mapping
),
3927 (u32
)(U64_LO(bp
->spq_mapping
) +
3928 (void *)bp
->spq_prod_bd
- (void *)bp
->spq
), command
, common
,
3929 HW_CID(bp
, cid
), data_hi
, data_lo
, type
,
3930 atomic_read(&bp
->cq_spq_left
), atomic_read(&bp
->eq_spq_left
));
3932 bnx2x_sp_prod_update(bp
);
3933 spin_unlock_bh(&bp
->spq_lock
);
3937 /* acquire split MCP access lock register */
3938 static int bnx2x_acquire_alr(struct bnx2x
*bp
)
3944 for (j
= 0; j
< 1000; j
++) {
3945 REG_WR(bp
, MCP_REG_MCPR_ACCESS_LOCK
, MCPR_ACCESS_LOCK_LOCK
);
3946 val
= REG_RD(bp
, MCP_REG_MCPR_ACCESS_LOCK
);
3947 if (val
& MCPR_ACCESS_LOCK_LOCK
)
3950 usleep_range(5000, 10000);
3952 if (!(val
& MCPR_ACCESS_LOCK_LOCK
)) {
3953 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3960 /* release split MCP access lock register */
3961 static void bnx2x_release_alr(struct bnx2x
*bp
)
3963 REG_WR(bp
, MCP_REG_MCPR_ACCESS_LOCK
, 0);
3966 #define BNX2X_DEF_SB_ATT_IDX 0x0001
3967 #define BNX2X_DEF_SB_IDX 0x0002
3969 static u16
bnx2x_update_dsb_idx(struct bnx2x
*bp
)
3971 struct host_sp_status_block
*def_sb
= bp
->def_status_blk
;
3974 barrier(); /* status block is written to by the chip */
3975 if (bp
->def_att_idx
!= def_sb
->atten_status_block
.attn_bits_index
) {
3976 bp
->def_att_idx
= def_sb
->atten_status_block
.attn_bits_index
;
3977 rc
|= BNX2X_DEF_SB_ATT_IDX
;
3980 if (bp
->def_idx
!= def_sb
->sp_sb
.running_index
) {
3981 bp
->def_idx
= def_sb
->sp_sb
.running_index
;
3982 rc
|= BNX2X_DEF_SB_IDX
;
3985 /* Do not reorder: indices reading should complete before handling */
3991 * slow path service functions
3994 static void bnx2x_attn_int_asserted(struct bnx2x
*bp
, u32 asserted
)
3996 int port
= BP_PORT(bp
);
3997 u32 aeu_addr
= port
? MISC_REG_AEU_MASK_ATTN_FUNC_1
:
3998 MISC_REG_AEU_MASK_ATTN_FUNC_0
;
3999 u32 nig_int_mask_addr
= port
? NIG_REG_MASK_INTERRUPT_PORT1
:
4000 NIG_REG_MASK_INTERRUPT_PORT0
;
4005 if (bp
->attn_state
& asserted
)
4006 BNX2X_ERR("IGU ERROR\n");
4008 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_PORT0_ATT_MASK
+ port
);
4009 aeu_mask
= REG_RD(bp
, aeu_addr
);
4011 DP(NETIF_MSG_HW
, "aeu_mask %x newly asserted %x\n",
4012 aeu_mask
, asserted
);
4013 aeu_mask
&= ~(asserted
& 0x3ff);
4014 DP(NETIF_MSG_HW
, "new mask %x\n", aeu_mask
);
4016 REG_WR(bp
, aeu_addr
, aeu_mask
);
4017 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_PORT0_ATT_MASK
+ port
);
4019 DP(NETIF_MSG_HW
, "attn_state %x\n", bp
->attn_state
);
4020 bp
->attn_state
|= asserted
;
4021 DP(NETIF_MSG_HW
, "new state %x\n", bp
->attn_state
);
4023 if (asserted
& ATTN_HARD_WIRED_MASK
) {
4024 if (asserted
& ATTN_NIG_FOR_FUNC
) {
4026 bnx2x_acquire_phy_lock(bp
);
4028 /* save nig interrupt mask */
4029 nig_mask
= REG_RD(bp
, nig_int_mask_addr
);
4031 /* If nig_mask is not set, no need to call the update
4035 REG_WR(bp
, nig_int_mask_addr
, 0);
4037 bnx2x_link_attn(bp
);
4040 /* handle unicore attn? */
4042 if (asserted
& ATTN_SW_TIMER_4_FUNC
)
4043 DP(NETIF_MSG_HW
, "ATTN_SW_TIMER_4_FUNC!\n");
4045 if (asserted
& GPIO_2_FUNC
)
4046 DP(NETIF_MSG_HW
, "GPIO_2_FUNC!\n");
4048 if (asserted
& GPIO_3_FUNC
)
4049 DP(NETIF_MSG_HW
, "GPIO_3_FUNC!\n");
4051 if (asserted
& GPIO_4_FUNC
)
4052 DP(NETIF_MSG_HW
, "GPIO_4_FUNC!\n");
4055 if (asserted
& ATTN_GENERAL_ATTN_1
) {
4056 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_1!\n");
4057 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_1
, 0x0);
4059 if (asserted
& ATTN_GENERAL_ATTN_2
) {
4060 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_2!\n");
4061 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_2
, 0x0);
4063 if (asserted
& ATTN_GENERAL_ATTN_3
) {
4064 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_3!\n");
4065 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_3
, 0x0);
4068 if (asserted
& ATTN_GENERAL_ATTN_4
) {
4069 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_4!\n");
4070 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_4
, 0x0);
4072 if (asserted
& ATTN_GENERAL_ATTN_5
) {
4073 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_5!\n");
4074 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_5
, 0x0);
4076 if (asserted
& ATTN_GENERAL_ATTN_6
) {
4077 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_6!\n");
4078 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_6
, 0x0);
4082 } /* if hardwired */
4084 if (bp
->common
.int_block
== INT_BLOCK_HC
)
4085 reg_addr
= (HC_REG_COMMAND_REG
+ port
*32 +
4086 COMMAND_REG_ATTN_BITS_SET
);
4088 reg_addr
= (BAR_IGU_INTMEM
+ IGU_CMD_ATTN_BIT_SET_UPPER
*8);
4090 DP(NETIF_MSG_HW
, "about to mask 0x%08x at %s addr 0x%x\n", asserted
,
4091 (bp
->common
.int_block
== INT_BLOCK_HC
) ? "HC" : "IGU", reg_addr
);
4092 REG_WR(bp
, reg_addr
, asserted
);
4094 /* now set back the mask */
4095 if (asserted
& ATTN_NIG_FOR_FUNC
) {
4096 /* Verify that IGU ack through BAR was written before restoring
4097 * NIG mask. This loop should exit after 2-3 iterations max.
4099 if (bp
->common
.int_block
!= INT_BLOCK_HC
) {
4100 u32 cnt
= 0, igu_acked
;
4102 igu_acked
= REG_RD(bp
,
4103 IGU_REG_ATTENTION_ACK_BITS
);
4104 } while (((igu_acked
& ATTN_NIG_FOR_FUNC
) == 0) &&
4105 (++cnt
< MAX_IGU_ATTN_ACK_TO
));
4108 "Failed to verify IGU ack on time\n");
4111 REG_WR(bp
, nig_int_mask_addr
, nig_mask
);
4112 bnx2x_release_phy_lock(bp
);
4116 static void bnx2x_fan_failure(struct bnx2x
*bp
)
4118 int port
= BP_PORT(bp
);
4120 /* mark the failure */
4123 dev_info
.port_hw_config
[port
].external_phy_config
);
4125 ext_phy_config
&= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK
;
4126 ext_phy_config
|= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE
;
4127 SHMEM_WR(bp
, dev_info
.port_hw_config
[port
].external_phy_config
,
4130 /* log the failure */
4131 netdev_err(bp
->dev
, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
4132 "Please contact OEM Support for assistance\n");
4134 /* Schedule device reset (unload)
4135 * This is due to some boards consuming sufficient power when driver is
4136 * up to overheat if fan fails.
4138 bnx2x_schedule_sp_rtnl(bp
, BNX2X_SP_RTNL_FAN_FAILURE
, 0);
4141 static void bnx2x_attn_int_deasserted0(struct bnx2x
*bp
, u32 attn
)
4143 int port
= BP_PORT(bp
);
4147 reg_offset
= (port
? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0
:
4148 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0
);
4150 if (attn
& AEU_INPUTS_ATTN_BITS_SPIO5
) {
4152 val
= REG_RD(bp
, reg_offset
);
4153 val
&= ~AEU_INPUTS_ATTN_BITS_SPIO5
;
4154 REG_WR(bp
, reg_offset
, val
);
4156 BNX2X_ERR("SPIO5 hw attention\n");
4158 /* Fan failure attention */
4159 bnx2x_hw_reset_phy(&bp
->link_params
);
4160 bnx2x_fan_failure(bp
);
4163 if ((attn
& bp
->link_vars
.aeu_int_mask
) && bp
->port
.pmf
) {
4164 bnx2x_acquire_phy_lock(bp
);
4165 bnx2x_handle_module_detect_int(&bp
->link_params
);
4166 bnx2x_release_phy_lock(bp
);
4169 if (attn
& HW_INTERRUPT_ASSERT_SET_0
) {
4171 val
= REG_RD(bp
, reg_offset
);
4172 val
&= ~(attn
& HW_INTERRUPT_ASSERT_SET_0
);
4173 REG_WR(bp
, reg_offset
, val
);
4175 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
4176 (u32
)(attn
& HW_INTERRUPT_ASSERT_SET_0
));
4181 static void bnx2x_attn_int_deasserted1(struct bnx2x
*bp
, u32 attn
)
4185 if (attn
& AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT
) {
4187 val
= REG_RD(bp
, DORQ_REG_DORQ_INT_STS_CLR
);
4188 BNX2X_ERR("DB hw attention 0x%x\n", val
);
4189 /* DORQ discard attention */
4191 BNX2X_ERR("FATAL error from DORQ\n");
4194 if (attn
& HW_INTERRUPT_ASSERT_SET_1
) {
4196 int port
= BP_PORT(bp
);
4199 reg_offset
= (port
? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1
:
4200 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1
);
4202 val
= REG_RD(bp
, reg_offset
);
4203 val
&= ~(attn
& HW_INTERRUPT_ASSERT_SET_1
);
4204 REG_WR(bp
, reg_offset
, val
);
4206 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
4207 (u32
)(attn
& HW_INTERRUPT_ASSERT_SET_1
));
4212 static void bnx2x_attn_int_deasserted2(struct bnx2x
*bp
, u32 attn
)
4216 if (attn
& AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT
) {
4218 val
= REG_RD(bp
, CFC_REG_CFC_INT_STS_CLR
);
4219 BNX2X_ERR("CFC hw attention 0x%x\n", val
);
4220 /* CFC error attention */
4222 BNX2X_ERR("FATAL error from CFC\n");
4225 if (attn
& AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT
) {
4226 val
= REG_RD(bp
, PXP_REG_PXP_INT_STS_CLR_0
);
4227 BNX2X_ERR("PXP hw attention-0 0x%x\n", val
);
4228 /* RQ_USDMDP_FIFO_OVERFLOW */
4230 BNX2X_ERR("FATAL error from PXP\n");
4232 if (!CHIP_IS_E1x(bp
)) {
4233 val
= REG_RD(bp
, PXP_REG_PXP_INT_STS_CLR_1
);
4234 BNX2X_ERR("PXP hw attention-1 0x%x\n", val
);
4238 if (attn
& HW_INTERRUPT_ASSERT_SET_2
) {
4240 int port
= BP_PORT(bp
);
4243 reg_offset
= (port
? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2
:
4244 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2
);
4246 val
= REG_RD(bp
, reg_offset
);
4247 val
&= ~(attn
& HW_INTERRUPT_ASSERT_SET_2
);
4248 REG_WR(bp
, reg_offset
, val
);
4250 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
4251 (u32
)(attn
& HW_INTERRUPT_ASSERT_SET_2
));
4256 static void bnx2x_attn_int_deasserted3(struct bnx2x
*bp
, u32 attn
)
4260 if (attn
& EVEREST_GEN_ATTN_IN_USE_MASK
) {
4262 if (attn
& BNX2X_PMF_LINK_ASSERT
) {
4263 int func
= BP_FUNC(bp
);
4265 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_12
+ func
*4, 0);
4266 bnx2x_read_mf_cfg(bp
);
4267 bp
->mf_config
[BP_VN(bp
)] = MF_CFG_RD(bp
,
4268 func_mf_config
[BP_ABS_FUNC(bp
)].config
);
4270 func_mb
[BP_FW_MB_IDX(bp
)].drv_status
);
4272 if (val
& (DRV_STATUS_DCC_EVENT_MASK
|
4273 DRV_STATUS_OEM_EVENT_MASK
))
4275 (val
& (DRV_STATUS_DCC_EVENT_MASK
|
4276 DRV_STATUS_OEM_EVENT_MASK
)));
4278 if (val
& DRV_STATUS_SET_MF_BW
)
4279 bnx2x_set_mf_bw(bp
);
4281 if (val
& DRV_STATUS_DRV_INFO_REQ
)
4282 bnx2x_handle_drv_info_req(bp
);
4284 if (val
& DRV_STATUS_VF_DISABLED
)
4285 bnx2x_schedule_iov_task(bp
,
4286 BNX2X_IOV_HANDLE_FLR
);
4288 if ((bp
->port
.pmf
== 0) && (val
& DRV_STATUS_PMF
))
4289 bnx2x_pmf_update(bp
);
4292 (val
& DRV_STATUS_DCBX_NEGOTIATION_RESULTS
) &&
4293 bp
->dcbx_enabled
> 0)
4294 /* start dcbx state machine */
4295 bnx2x_dcbx_set_params(bp
,
4296 BNX2X_DCBX_STATE_NEG_RECEIVED
);
4297 if (val
& DRV_STATUS_AFEX_EVENT_MASK
)
4298 bnx2x_handle_afex_cmd(bp
,
4299 val
& DRV_STATUS_AFEX_EVENT_MASK
);
4300 if (val
& DRV_STATUS_EEE_NEGOTIATION_RESULTS
)
4301 bnx2x_handle_eee_event(bp
);
4303 if (val
& DRV_STATUS_OEM_UPDATE_SVID
)
4304 bnx2x_handle_update_svid_cmd(bp
);
4306 if (bp
->link_vars
.periodic_flags
&
4307 PERIODIC_FLAGS_LINK_EVENT
) {
4308 /* sync with link */
4309 bnx2x_acquire_phy_lock(bp
);
4310 bp
->link_vars
.periodic_flags
&=
4311 ~PERIODIC_FLAGS_LINK_EVENT
;
4312 bnx2x_release_phy_lock(bp
);
4314 bnx2x_link_sync_notify(bp
);
4315 bnx2x_link_report(bp
);
4317 /* Always call it here: bnx2x_link_report() will
4318 * prevent the link indication duplication.
4320 bnx2x__link_status_update(bp
);
4321 } else if (attn
& BNX2X_MC_ASSERT_BITS
) {
4323 BNX2X_ERR("MC assert!\n");
4324 bnx2x_mc_assert(bp
);
4325 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_10
, 0);
4326 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_9
, 0);
4327 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_8
, 0);
4328 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_7
, 0);
4331 } else if (attn
& BNX2X_MCP_ASSERT
) {
4333 BNX2X_ERR("MCP assert!\n");
4334 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_11
, 0);
4338 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn
);
4341 if (attn
& EVEREST_LATCHED_ATTN_IN_USE_MASK
) {
4342 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn
);
4343 if (attn
& BNX2X_GRC_TIMEOUT
) {
4344 val
= CHIP_IS_E1(bp
) ? 0 :
4345 REG_RD(bp
, MISC_REG_GRC_TIMEOUT_ATTN
);
4346 BNX2X_ERR("GRC time-out 0x%08x\n", val
);
4348 if (attn
& BNX2X_GRC_RSV
) {
4349 val
= CHIP_IS_E1(bp
) ? 0 :
4350 REG_RD(bp
, MISC_REG_GRC_RSV_ATTN
);
4351 BNX2X_ERR("GRC reserved 0x%08x\n", val
);
4353 REG_WR(bp
, MISC_REG_AEU_CLR_LATCH_SIGNAL
, 0x7ff);
4359 * 0-7 - Engine0 load counter.
4360 * 8-15 - Engine1 load counter.
4361 * 16 - Engine0 RESET_IN_PROGRESS bit.
4362 * 17 - Engine1 RESET_IN_PROGRESS bit.
4363 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4365 * 19 - Engine1 ONE_IS_LOADED.
4366 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
4367 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
4368 * just the one belonging to its engine).
4371 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
4373 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
4374 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
4375 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
4376 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
4377 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
4378 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
4379 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
4382 * Set the GLOBAL_RESET bit.
4384 * Should be run under rtnl lock
4386 void bnx2x_set_reset_global(struct bnx2x
*bp
)
4389 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4390 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
4391 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
| BNX2X_GLOBAL_RESET_BIT
);
4392 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4396 * Clear the GLOBAL_RESET bit.
4398 * Should be run under rtnl lock
4400 static void bnx2x_clear_reset_global(struct bnx2x
*bp
)
4403 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4404 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
4405 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
& (~BNX2X_GLOBAL_RESET_BIT
));
4406 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4410 * Checks the GLOBAL_RESET bit.
4412 * should be run under rtnl lock
4414 static bool bnx2x_reset_is_global(struct bnx2x
*bp
)
4416 u32 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
4418 DP(NETIF_MSG_HW
, "GEN_REG_VAL=0x%08x\n", val
);
4419 return (val
& BNX2X_GLOBAL_RESET_BIT
) ? true : false;
4423 * Clear RESET_IN_PROGRESS bit for the current engine.
4425 * Should be run under rtnl lock
4427 static void bnx2x_set_reset_done(struct bnx2x
*bp
)
4430 u32 bit
= BP_PATH(bp
) ?
4431 BNX2X_PATH1_RST_IN_PROG_BIT
: BNX2X_PATH0_RST_IN_PROG_BIT
;
4432 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4433 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
4437 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
);
4439 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4443 * Set RESET_IN_PROGRESS for the current engine.
4445 * should be run under rtnl lock
4447 void bnx2x_set_reset_in_progress(struct bnx2x
*bp
)
4450 u32 bit
= BP_PATH(bp
) ?
4451 BNX2X_PATH1_RST_IN_PROG_BIT
: BNX2X_PATH0_RST_IN_PROG_BIT
;
4452 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4453 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
4457 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
);
4458 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4462 * Checks the RESET_IN_PROGRESS bit for the given engine.
4463 * should be run under rtnl lock
4465 bool bnx2x_reset_is_done(struct bnx2x
*bp
, int engine
)
4467 u32 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
4469 BNX2X_PATH1_RST_IN_PROG_BIT
: BNX2X_PATH0_RST_IN_PROG_BIT
;
4471 /* return false if bit is set */
4472 return (val
& bit
) ? false : true;
4476 * set pf load for the current pf.
4478 * should be run under rtnl lock
4480 void bnx2x_set_pf_load(struct bnx2x
*bp
)
4483 u32 mask
= BP_PATH(bp
) ? BNX2X_PATH1_LOAD_CNT_MASK
:
4484 BNX2X_PATH0_LOAD_CNT_MASK
;
4485 u32 shift
= BP_PATH(bp
) ? BNX2X_PATH1_LOAD_CNT_SHIFT
:
4486 BNX2X_PATH0_LOAD_CNT_SHIFT
;
4488 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4489 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
4491 DP(NETIF_MSG_IFUP
, "Old GEN_REG_VAL=0x%08x\n", val
);
4493 /* get the current counter value */
4494 val1
= (val
& mask
) >> shift
;
4496 /* set bit of that PF */
4497 val1
|= (1 << bp
->pf_num
);
4499 /* clear the old value */
4502 /* set the new one */
4503 val
|= ((val1
<< shift
) & mask
);
4505 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
);
4506 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4510 * bnx2x_clear_pf_load - clear pf load mark
4512 * @bp: driver handle
4514 * Should be run under rtnl lock.
4515 * Decrements the load counter for the current engine. Returns
4516 * whether other functions are still loaded
4518 bool bnx2x_clear_pf_load(struct bnx2x
*bp
)
4521 u32 mask
= BP_PATH(bp
) ? BNX2X_PATH1_LOAD_CNT_MASK
:
4522 BNX2X_PATH0_LOAD_CNT_MASK
;
4523 u32 shift
= BP_PATH(bp
) ? BNX2X_PATH1_LOAD_CNT_SHIFT
:
4524 BNX2X_PATH0_LOAD_CNT_SHIFT
;
4526 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4527 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
4528 DP(NETIF_MSG_IFDOWN
, "Old GEN_REG_VAL=0x%08x\n", val
);
4530 /* get the current counter value */
4531 val1
= (val
& mask
) >> shift
;
4533 /* clear bit of that PF */
4534 val1
&= ~(1 << bp
->pf_num
);
4536 /* clear the old value */
4539 /* set the new one */
4540 val
|= ((val1
<< shift
) & mask
);
4542 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
);
4543 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4548 * Read the load status for the current engine.
4550 * should be run under rtnl lock
4552 static bool bnx2x_get_load_status(struct bnx2x
*bp
, int engine
)
4554 u32 mask
= (engine
? BNX2X_PATH1_LOAD_CNT_MASK
:
4555 BNX2X_PATH0_LOAD_CNT_MASK
);
4556 u32 shift
= (engine
? BNX2X_PATH1_LOAD_CNT_SHIFT
:
4557 BNX2X_PATH0_LOAD_CNT_SHIFT
);
4558 u32 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
4560 DP(NETIF_MSG_HW
| NETIF_MSG_IFUP
, "GLOB_REG=0x%08x\n", val
);
4562 val
= (val
& mask
) >> shift
;
4564 DP(NETIF_MSG_HW
| NETIF_MSG_IFUP
, "load mask for engine %d = 0x%x\n",
4570 static void _print_parity(struct bnx2x
*bp
, u32 reg
)
4572 pr_cont(" [0x%08x] ", REG_RD(bp
, reg
));
4575 static void _print_next_block(int idx
, const char *blk
)
4577 pr_cont("%s%s", idx
? ", " : "", blk
);
4580 static bool bnx2x_check_blocks_with_parity0(struct bnx2x
*bp
, u32 sig
,
4581 int *par_num
, bool print
)
4589 for (i
= 0; sig
; i
++) {
4590 cur_bit
= (0x1UL
<< i
);
4591 if (sig
& cur_bit
) {
4592 res
|= true; /* Each bit is real error! */
4596 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR
:
4597 _print_next_block((*par_num
)++, "BRB");
4599 BRB1_REG_BRB1_PRTY_STS
);
4601 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR
:
4602 _print_next_block((*par_num
)++,
4604 _print_parity(bp
, PRS_REG_PRS_PRTY_STS
);
4606 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR
:
4607 _print_next_block((*par_num
)++, "TSDM");
4609 TSDM_REG_TSDM_PRTY_STS
);
4611 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR
:
4612 _print_next_block((*par_num
)++,
4614 _print_parity(bp
, SRC_REG_SRC_PRTY_STS
);
4616 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR
:
4617 _print_next_block((*par_num
)++, "TCM");
4618 _print_parity(bp
, TCM_REG_TCM_PRTY_STS
);
4620 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR
:
4621 _print_next_block((*par_num
)++,
4624 TSEM_REG_TSEM_PRTY_STS_0
);
4626 TSEM_REG_TSEM_PRTY_STS_1
);
4628 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR
:
4629 _print_next_block((*par_num
)++, "XPB");
4630 _print_parity(bp
, GRCBASE_XPB
+
4631 PB_REG_PB_PRTY_STS
);
4644 static bool bnx2x_check_blocks_with_parity1(struct bnx2x
*bp
, u32 sig
,
4645 int *par_num
, bool *global
,
4654 for (i
= 0; sig
; i
++) {
4655 cur_bit
= (0x1UL
<< i
);
4656 if (sig
& cur_bit
) {
4657 res
|= true; /* Each bit is real error! */
4659 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR
:
4661 _print_next_block((*par_num
)++, "PBF");
4662 _print_parity(bp
, PBF_REG_PBF_PRTY_STS
);
4665 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR
:
4667 _print_next_block((*par_num
)++, "QM");
4668 _print_parity(bp
, QM_REG_QM_PRTY_STS
);
4671 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR
:
4673 _print_next_block((*par_num
)++, "TM");
4674 _print_parity(bp
, TM_REG_TM_PRTY_STS
);
4677 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR
:
4679 _print_next_block((*par_num
)++, "XSDM");
4681 XSDM_REG_XSDM_PRTY_STS
);
4684 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR
:
4686 _print_next_block((*par_num
)++, "XCM");
4687 _print_parity(bp
, XCM_REG_XCM_PRTY_STS
);
4690 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR
:
4692 _print_next_block((*par_num
)++,
4695 XSEM_REG_XSEM_PRTY_STS_0
);
4697 XSEM_REG_XSEM_PRTY_STS_1
);
4700 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR
:
4702 _print_next_block((*par_num
)++,
4705 DORQ_REG_DORQ_PRTY_STS
);
4708 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR
:
4710 _print_next_block((*par_num
)++, "NIG");
4711 if (CHIP_IS_E1x(bp
)) {
4713 NIG_REG_NIG_PRTY_STS
);
4716 NIG_REG_NIG_PRTY_STS_0
);
4718 NIG_REG_NIG_PRTY_STS_1
);
4722 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR
:
4724 _print_next_block((*par_num
)++,
4728 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR
:
4730 _print_next_block((*par_num
)++,
4732 _print_parity(bp
, DBG_REG_DBG_PRTY_STS
);
4735 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR
:
4737 _print_next_block((*par_num
)++, "USDM");
4739 USDM_REG_USDM_PRTY_STS
);
4742 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR
:
4744 _print_next_block((*par_num
)++, "UCM");
4745 _print_parity(bp
, UCM_REG_UCM_PRTY_STS
);
4748 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR
:
4750 _print_next_block((*par_num
)++,
4753 USEM_REG_USEM_PRTY_STS_0
);
4755 USEM_REG_USEM_PRTY_STS_1
);
4758 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR
:
4760 _print_next_block((*par_num
)++, "UPB");
4761 _print_parity(bp
, GRCBASE_UPB
+
4762 PB_REG_PB_PRTY_STS
);
4765 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR
:
4767 _print_next_block((*par_num
)++, "CSDM");
4769 CSDM_REG_CSDM_PRTY_STS
);
4772 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR
:
4774 _print_next_block((*par_num
)++, "CCM");
4775 _print_parity(bp
, CCM_REG_CCM_PRTY_STS
);
4788 static bool bnx2x_check_blocks_with_parity2(struct bnx2x
*bp
, u32 sig
,
4789 int *par_num
, bool print
)
4797 for (i
= 0; sig
; i
++) {
4798 cur_bit
= (0x1UL
<< i
);
4799 if (sig
& cur_bit
) {
4800 res
= true; /* Each bit is real error! */
4803 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR
:
4804 _print_next_block((*par_num
)++,
4807 CSEM_REG_CSEM_PRTY_STS_0
);
4809 CSEM_REG_CSEM_PRTY_STS_1
);
4811 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR
:
4812 _print_next_block((*par_num
)++, "PXP");
4813 _print_parity(bp
, PXP_REG_PXP_PRTY_STS
);
4815 PXP2_REG_PXP2_PRTY_STS_0
);
4817 PXP2_REG_PXP2_PRTY_STS_1
);
4819 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
:
4820 _print_next_block((*par_num
)++,
4821 "PXPPCICLOCKCLIENT");
4823 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR
:
4824 _print_next_block((*par_num
)++, "CFC");
4826 CFC_REG_CFC_PRTY_STS
);
4828 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR
:
4829 _print_next_block((*par_num
)++, "CDU");
4830 _print_parity(bp
, CDU_REG_CDU_PRTY_STS
);
4832 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR
:
4833 _print_next_block((*par_num
)++, "DMAE");
4835 DMAE_REG_DMAE_PRTY_STS
);
4837 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR
:
4838 _print_next_block((*par_num
)++, "IGU");
4839 if (CHIP_IS_E1x(bp
))
4841 HC_REG_HC_PRTY_STS
);
4844 IGU_REG_IGU_PRTY_STS
);
4846 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR
:
4847 _print_next_block((*par_num
)++, "MISC");
4849 MISC_REG_MISC_PRTY_STS
);
4862 static bool bnx2x_check_blocks_with_parity3(struct bnx2x
*bp
, u32 sig
,
4863 int *par_num
, bool *global
,
4870 for (i
= 0; sig
; i
++) {
4871 cur_bit
= (0x1UL
<< i
);
4872 if (sig
& cur_bit
) {
4874 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY
:
4876 _print_next_block((*par_num
)++,
4881 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY
:
4883 _print_next_block((*par_num
)++,
4888 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY
:
4890 _print_next_block((*par_num
)++,
4895 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY
:
4897 /* clear latched SCPAD PATIRY from MCP */
4898 REG_WR(bp
, MISC_REG_AEU_CLR_LATCH_SIGNAL
,
4911 static bool bnx2x_check_blocks_with_parity4(struct bnx2x
*bp
, u32 sig
,
4912 int *par_num
, bool print
)
4920 for (i
= 0; sig
; i
++) {
4921 cur_bit
= (0x1UL
<< i
);
4922 if (sig
& cur_bit
) {
4923 res
= true; /* Each bit is real error! */
4926 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
:
4927 _print_next_block((*par_num
)++,
4930 PGLUE_B_REG_PGLUE_B_PRTY_STS
);
4932 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR
:
4933 _print_next_block((*par_num
)++, "ATC");
4935 ATC_REG_ATC_PRTY_STS
);
4947 static bool bnx2x_parity_attn(struct bnx2x
*bp
, bool *global
, bool print
,
4952 if ((sig
[0] & HW_PRTY_ASSERT_SET_0
) ||
4953 (sig
[1] & HW_PRTY_ASSERT_SET_1
) ||
4954 (sig
[2] & HW_PRTY_ASSERT_SET_2
) ||
4955 (sig
[3] & HW_PRTY_ASSERT_SET_3
) ||
4956 (sig
[4] & HW_PRTY_ASSERT_SET_4
)) {
4959 DP(NETIF_MSG_HW
, "Was parity error: HW block parity attention:\n"
4960 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4961 sig
[0] & HW_PRTY_ASSERT_SET_0
,
4962 sig
[1] & HW_PRTY_ASSERT_SET_1
,
4963 sig
[2] & HW_PRTY_ASSERT_SET_2
,
4964 sig
[3] & HW_PRTY_ASSERT_SET_3
,
4965 sig
[4] & HW_PRTY_ASSERT_SET_4
);
4967 if (((sig
[0] & HW_PRTY_ASSERT_SET_0
) ||
4968 (sig
[1] & HW_PRTY_ASSERT_SET_1
) ||
4969 (sig
[2] & HW_PRTY_ASSERT_SET_2
) ||
4970 (sig
[4] & HW_PRTY_ASSERT_SET_4
)) ||
4971 (sig
[3] & HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD
)) {
4973 "Parity errors detected in blocks: ");
4978 res
|= bnx2x_check_blocks_with_parity0(bp
,
4979 sig
[0] & HW_PRTY_ASSERT_SET_0
, &par_num
, print
);
4980 res
|= bnx2x_check_blocks_with_parity1(bp
,
4981 sig
[1] & HW_PRTY_ASSERT_SET_1
, &par_num
, global
, print
);
4982 res
|= bnx2x_check_blocks_with_parity2(bp
,
4983 sig
[2] & HW_PRTY_ASSERT_SET_2
, &par_num
, print
);
4984 res
|= bnx2x_check_blocks_with_parity3(bp
,
4985 sig
[3] & HW_PRTY_ASSERT_SET_3
, &par_num
, global
, print
);
4986 res
|= bnx2x_check_blocks_with_parity4(bp
,
4987 sig
[4] & HW_PRTY_ASSERT_SET_4
, &par_num
, print
);
4997 * bnx2x_chk_parity_attn - checks for parity attentions.
4999 * @bp: driver handle
5000 * @global: true if there was a global attention
5001 * @print: show parity attention in syslog
5003 bool bnx2x_chk_parity_attn(struct bnx2x
*bp
, bool *global
, bool print
)
5005 struct attn_route attn
= { {0} };
5006 int port
= BP_PORT(bp
);
5008 attn
.sig
[0] = REG_RD(bp
,
5009 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0
+
5011 attn
.sig
[1] = REG_RD(bp
,
5012 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0
+
5014 attn
.sig
[2] = REG_RD(bp
,
5015 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0
+
5017 attn
.sig
[3] = REG_RD(bp
,
5018 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0
+
5020 /* Since MCP attentions can't be disabled inside the block, we need to
5021 * read AEU registers to see whether they're currently disabled
5023 attn
.sig
[3] &= ((REG_RD(bp
,
5024 !port
? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
5025 : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0
) &
5026 MISC_AEU_ENABLE_MCP_PRTY_BITS
) |
5027 ~MISC_AEU_ENABLE_MCP_PRTY_BITS
);
5029 if (!CHIP_IS_E1x(bp
))
5030 attn
.sig
[4] = REG_RD(bp
,
5031 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0
+
5034 return bnx2x_parity_attn(bp
, global
, print
, attn
.sig
);
5037 static void bnx2x_attn_int_deasserted4(struct bnx2x
*bp
, u32 attn
)
5040 if (attn
& AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT
) {
5042 val
= REG_RD(bp
, PGLUE_B_REG_PGLUE_B_INT_STS_CLR
);
5043 BNX2X_ERR("PGLUE hw attention 0x%x\n", val
);
5044 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR
)
5045 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
5046 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR
)
5047 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
5048 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN
)
5049 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
5050 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN
)
5051 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
5053 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN
)
5054 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
5056 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN
)
5057 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
5058 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN
)
5059 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
5060 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN
)
5061 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
5062 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW
)
5063 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
5065 if (attn
& AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT
) {
5066 val
= REG_RD(bp
, ATC_REG_ATC_INT_STS_CLR
);
5067 BNX2X_ERR("ATC hw attention 0x%x\n", val
);
5068 if (val
& ATC_ATC_INT_STS_REG_ADDRESS_ERROR
)
5069 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
5070 if (val
& ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND
)
5071 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
5072 if (val
& ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS
)
5073 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
5074 if (val
& ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT
)
5075 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
5076 if (val
& ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR
)
5077 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
5078 if (val
& ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU
)
5079 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
5082 if (attn
& (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
|
5083 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR
)) {
5084 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
5085 (u32
)(attn
& (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
|
5086 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR
)));
5090 static void bnx2x_attn_int_deasserted(struct bnx2x
*bp
, u32 deasserted
)
5092 struct attn_route attn
, *group_mask
;
5093 int port
= BP_PORT(bp
);
5098 bool global
= false;
5100 /* need to take HW lock because MCP or other port might also
5101 try to handle this event */
5102 bnx2x_acquire_alr(bp
);
5104 if (bnx2x_chk_parity_attn(bp
, &global
, true)) {
5105 #ifndef BNX2X_STOP_ON_ERROR
5106 bp
->recovery_state
= BNX2X_RECOVERY_INIT
;
5107 schedule_delayed_work(&bp
->sp_rtnl_task
, 0);
5108 /* Disable HW interrupts */
5109 bnx2x_int_disable(bp
);
5110 /* In case of parity errors don't handle attentions so that
5111 * other function would "see" parity errors.
5116 bnx2x_release_alr(bp
);
5120 attn
.sig
[0] = REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0
+ port
*4);
5121 attn
.sig
[1] = REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0
+ port
*4);
5122 attn
.sig
[2] = REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0
+ port
*4);
5123 attn
.sig
[3] = REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0
+ port
*4);
5124 if (!CHIP_IS_E1x(bp
))
5126 REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0
+ port
*4);
5130 DP(NETIF_MSG_HW
, "attn: %08x %08x %08x %08x %08x\n",
5131 attn
.sig
[0], attn
.sig
[1], attn
.sig
[2], attn
.sig
[3], attn
.sig
[4]);
5133 for (index
= 0; index
< MAX_DYNAMIC_ATTN_GRPS
; index
++) {
5134 if (deasserted
& (1 << index
)) {
5135 group_mask
= &bp
->attn_group
[index
];
5137 DP(NETIF_MSG_HW
, "group[%d]: %08x %08x %08x %08x %08x\n",
5139 group_mask
->sig
[0], group_mask
->sig
[1],
5140 group_mask
->sig
[2], group_mask
->sig
[3],
5141 group_mask
->sig
[4]);
5143 bnx2x_attn_int_deasserted4(bp
,
5144 attn
.sig
[4] & group_mask
->sig
[4]);
5145 bnx2x_attn_int_deasserted3(bp
,
5146 attn
.sig
[3] & group_mask
->sig
[3]);
5147 bnx2x_attn_int_deasserted1(bp
,
5148 attn
.sig
[1] & group_mask
->sig
[1]);
5149 bnx2x_attn_int_deasserted2(bp
,
5150 attn
.sig
[2] & group_mask
->sig
[2]);
5151 bnx2x_attn_int_deasserted0(bp
,
5152 attn
.sig
[0] & group_mask
->sig
[0]);
5156 bnx2x_release_alr(bp
);
5158 if (bp
->common
.int_block
== INT_BLOCK_HC
)
5159 reg_addr
= (HC_REG_COMMAND_REG
+ port
*32 +
5160 COMMAND_REG_ATTN_BITS_CLR
);
5162 reg_addr
= (BAR_IGU_INTMEM
+ IGU_CMD_ATTN_BIT_CLR_UPPER
*8);
5165 DP(NETIF_MSG_HW
, "about to mask 0x%08x at %s addr 0x%x\n", val
,
5166 (bp
->common
.int_block
== INT_BLOCK_HC
) ? "HC" : "IGU", reg_addr
);
5167 REG_WR(bp
, reg_addr
, val
);
5169 if (~bp
->attn_state
& deasserted
)
5170 BNX2X_ERR("IGU ERROR\n");
5172 reg_addr
= port
? MISC_REG_AEU_MASK_ATTN_FUNC_1
:
5173 MISC_REG_AEU_MASK_ATTN_FUNC_0
;
5175 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_PORT0_ATT_MASK
+ port
);
5176 aeu_mask
= REG_RD(bp
, reg_addr
);
5178 DP(NETIF_MSG_HW
, "aeu_mask %x newly deasserted %x\n",
5179 aeu_mask
, deasserted
);
5180 aeu_mask
|= (deasserted
& 0x3ff);
5181 DP(NETIF_MSG_HW
, "new mask %x\n", aeu_mask
);
5183 REG_WR(bp
, reg_addr
, aeu_mask
);
5184 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_PORT0_ATT_MASK
+ port
);
5186 DP(NETIF_MSG_HW
, "attn_state %x\n", bp
->attn_state
);
5187 bp
->attn_state
&= ~deasserted
;
5188 DP(NETIF_MSG_HW
, "new state %x\n", bp
->attn_state
);
5191 static void bnx2x_attn_int(struct bnx2x
*bp
)
5193 /* read local copy of bits */
5194 u32 attn_bits
= le32_to_cpu(bp
->def_status_blk
->atten_status_block
.
5196 u32 attn_ack
= le32_to_cpu(bp
->def_status_blk
->atten_status_block
.
5198 u32 attn_state
= bp
->attn_state
;
5200 /* look for changed bits */
5201 u32 asserted
= attn_bits
& ~attn_ack
& ~attn_state
;
5202 u32 deasserted
= ~attn_bits
& attn_ack
& attn_state
;
5205 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
5206 attn_bits
, attn_ack
, asserted
, deasserted
);
5208 if (~(attn_bits
^ attn_ack
) & (attn_bits
^ attn_state
))
5209 BNX2X_ERR("BAD attention state\n");
5211 /* handle bits that were raised */
5213 bnx2x_attn_int_asserted(bp
, asserted
);
5216 bnx2x_attn_int_deasserted(bp
, deasserted
);
5219 void bnx2x_igu_ack_sb(struct bnx2x
*bp
, u8 igu_sb_id
, u8 segment
,
5220 u16 index
, u8 op
, u8 update
)
5222 u32 igu_addr
= bp
->igu_base_addr
;
5223 igu_addr
+= (IGU_CMD_INT_ACK_BASE
+ igu_sb_id
)*8;
5224 bnx2x_igu_ack_sb_gen(bp
, igu_sb_id
, segment
, index
, op
, update
,
5228 static void bnx2x_update_eq_prod(struct bnx2x
*bp
, u16 prod
)
5230 /* No memory barriers */
5231 storm_memset_eq_prod(bp
, prod
, BP_FUNC(bp
));
5232 mmiowb(); /* keep prod updates ordered */
5235 static int bnx2x_cnic_handle_cfc_del(struct bnx2x
*bp
, u32 cid
,
5236 union event_ring_elem
*elem
)
5238 u8 err
= elem
->message
.error
;
5240 if (!bp
->cnic_eth_dev
.starting_cid
||
5241 (cid
< bp
->cnic_eth_dev
.starting_cid
&&
5242 cid
!= bp
->cnic_eth_dev
.iscsi_l2_cid
))
5245 DP(BNX2X_MSG_SP
, "got delete ramrod for CNIC CID %d\n", cid
);
5247 if (unlikely(err
)) {
5249 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
5251 bnx2x_panic_dump(bp
, false);
5253 bnx2x_cnic_cfc_comp(bp
, cid
, err
);
5257 static void bnx2x_handle_mcast_eqe(struct bnx2x
*bp
)
5259 struct bnx2x_mcast_ramrod_params rparam
;
5262 memset(&rparam
, 0, sizeof(rparam
));
5264 rparam
.mcast_obj
= &bp
->mcast_obj
;
5266 netif_addr_lock_bh(bp
->dev
);
5268 /* Clear pending state for the last command */
5269 bp
->mcast_obj
.raw
.clear_pending(&bp
->mcast_obj
.raw
);
5271 /* If there are pending mcast commands - send them */
5272 if (bp
->mcast_obj
.check_pending(&bp
->mcast_obj
)) {
5273 rc
= bnx2x_config_mcast(bp
, &rparam
, BNX2X_MCAST_CMD_CONT
);
5275 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
5279 netif_addr_unlock_bh(bp
->dev
);
5282 static void bnx2x_handle_classification_eqe(struct bnx2x
*bp
,
5283 union event_ring_elem
*elem
)
5285 unsigned long ramrod_flags
= 0;
5287 u32 echo
= le32_to_cpu(elem
->message
.data
.eth_event
.echo
);
5288 u32 cid
= echo
& BNX2X_SWCID_MASK
;
5289 struct bnx2x_vlan_mac_obj
*vlan_mac_obj
;
5291 /* Always push next commands out, don't wait here */
5292 __set_bit(RAMROD_CONT
, &ramrod_flags
);
5294 switch (echo
>> BNX2X_SWCID_SHIFT
) {
5295 case BNX2X_FILTER_MAC_PENDING
:
5296 DP(BNX2X_MSG_SP
, "Got SETUP_MAC completions\n");
5297 if (CNIC_LOADED(bp
) && (cid
== BNX2X_ISCSI_ETH_CID(bp
)))
5298 vlan_mac_obj
= &bp
->iscsi_l2_mac_obj
;
5300 vlan_mac_obj
= &bp
->sp_objs
[cid
].mac_obj
;
5303 case BNX2X_FILTER_VLAN_PENDING
:
5304 DP(BNX2X_MSG_SP
, "Got SETUP_VLAN completions\n");
5305 vlan_mac_obj
= &bp
->sp_objs
[cid
].vlan_obj
;
5307 case BNX2X_FILTER_MCAST_PENDING
:
5308 DP(BNX2X_MSG_SP
, "Got SETUP_MCAST completions\n");
5309 /* This is only relevant for 57710 where multicast MACs are
5310 * configured as unicast MACs using the same ramrod.
5312 bnx2x_handle_mcast_eqe(bp
);
5315 BNX2X_ERR("Unsupported classification command: 0x%x\n", echo
);
5319 rc
= vlan_mac_obj
->complete(bp
, vlan_mac_obj
, elem
, &ramrod_flags
);
5322 BNX2X_ERR("Failed to schedule new commands: %d\n", rc
);
5324 DP(BNX2X_MSG_SP
, "Scheduled next pending commands...\n");
5327 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x
*bp
, bool start
);
5329 static void bnx2x_handle_rx_mode_eqe(struct bnx2x
*bp
)
5331 netif_addr_lock_bh(bp
->dev
);
5333 clear_bit(BNX2X_FILTER_RX_MODE_PENDING
, &bp
->sp_state
);
5335 /* Send rx_mode command again if was requested */
5336 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED
, &bp
->sp_state
))
5337 bnx2x_set_storm_rx_mode(bp
);
5338 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED
,
5340 bnx2x_set_iscsi_eth_rx_mode(bp
, true);
5341 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED
,
5343 bnx2x_set_iscsi_eth_rx_mode(bp
, false);
5345 netif_addr_unlock_bh(bp
->dev
);
5348 static void bnx2x_after_afex_vif_lists(struct bnx2x
*bp
,
5349 union event_ring_elem
*elem
)
5351 if (elem
->message
.data
.vif_list_event
.echo
== VIF_LIST_RULE_GET
) {
5353 "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5354 elem
->message
.data
.vif_list_event
.func_bit_map
);
5355 bnx2x_fw_command(bp
, DRV_MSG_CODE_AFEX_LISTGET_ACK
,
5356 elem
->message
.data
.vif_list_event
.func_bit_map
);
5357 } else if (elem
->message
.data
.vif_list_event
.echo
==
5358 VIF_LIST_RULE_SET
) {
5359 DP(BNX2X_MSG_SP
, "afex: ramrod completed VIF LIST_SET\n");
5360 bnx2x_fw_command(bp
, DRV_MSG_CODE_AFEX_LISTSET_ACK
, 0);
5364 /* called with rtnl_lock */
5365 static void bnx2x_after_function_update(struct bnx2x
*bp
)
5368 struct bnx2x_fastpath
*fp
;
5369 struct bnx2x_queue_state_params queue_params
= {NULL
};
5370 struct bnx2x_queue_update_params
*q_update_params
=
5371 &queue_params
.params
.update
;
5373 /* Send Q update command with afex vlan removal values for all Qs */
5374 queue_params
.cmd
= BNX2X_Q_CMD_UPDATE
;
5376 /* set silent vlan removal values according to vlan mode */
5377 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG
,
5378 &q_update_params
->update_flags
);
5379 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM
,
5380 &q_update_params
->update_flags
);
5381 __set_bit(RAMROD_COMP_WAIT
, &queue_params
.ramrod_flags
);
5383 /* in access mode mark mask and value are 0 to strip all vlans */
5384 if (bp
->afex_vlan_mode
== FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE
) {
5385 q_update_params
->silent_removal_value
= 0;
5386 q_update_params
->silent_removal_mask
= 0;
5388 q_update_params
->silent_removal_value
=
5389 (bp
->afex_def_vlan_tag
& VLAN_VID_MASK
);
5390 q_update_params
->silent_removal_mask
= VLAN_VID_MASK
;
5393 for_each_eth_queue(bp
, q
) {
5394 /* Set the appropriate Queue object */
5396 queue_params
.q_obj
= &bnx2x_sp_obj(bp
, fp
).q_obj
;
5398 /* send the ramrod */
5399 rc
= bnx2x_queue_state_change(bp
, &queue_params
);
5401 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5405 if (!NO_FCOE(bp
) && CNIC_ENABLED(bp
)) {
5406 fp
= &bp
->fp
[FCOE_IDX(bp
)];
5407 queue_params
.q_obj
= &bnx2x_sp_obj(bp
, fp
).q_obj
;
5409 /* clear pending completion bit */
5410 __clear_bit(RAMROD_COMP_WAIT
, &queue_params
.ramrod_flags
);
5412 /* mark latest Q bit */
5413 smp_mb__before_atomic();
5414 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING
, &bp
->sp_state
);
5415 smp_mb__after_atomic();
5417 /* send Q update ramrod for FCoE Q */
5418 rc
= bnx2x_queue_state_change(bp
, &queue_params
);
5420 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5423 /* If no FCoE ring - ACK MCP now */
5424 bnx2x_link_report(bp
);
5425 bnx2x_fw_command(bp
, DRV_MSG_CODE_AFEX_VIFSET_ACK
, 0);
5429 static struct bnx2x_queue_sp_obj
*bnx2x_cid_to_q_obj(
5430 struct bnx2x
*bp
, u32 cid
)
5432 DP(BNX2X_MSG_SP
, "retrieving fp from cid %d\n", cid
);
5434 if (CNIC_LOADED(bp
) && (cid
== BNX2X_FCOE_ETH_CID(bp
)))
5435 return &bnx2x_fcoe_sp_obj(bp
, q_obj
);
5437 return &bp
->sp_objs
[CID_TO_FP(cid
, bp
)].q_obj
;
5440 static void bnx2x_eq_int(struct bnx2x
*bp
)
5442 u16 hw_cons
, sw_cons
, sw_prod
;
5443 union event_ring_elem
*elem
;
5447 int rc
, spqe_cnt
= 0;
5448 struct bnx2x_queue_sp_obj
*q_obj
;
5449 struct bnx2x_func_sp_obj
*f_obj
= &bp
->func_obj
;
5450 struct bnx2x_raw_obj
*rss_raw
= &bp
->rss_conf_obj
.raw
;
5452 hw_cons
= le16_to_cpu(*bp
->eq_cons_sb
);
5454 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5455 * when we get the next-page we need to adjust so the loop
5456 * condition below will be met. The next element is the size of a
5457 * regular element and hence incrementing by 1
5459 if ((hw_cons
& EQ_DESC_MAX_PAGE
) == EQ_DESC_MAX_PAGE
)
5462 /* This function may never run in parallel with itself for a
5463 * specific bp, thus there is no need in "paired" read memory
5466 sw_cons
= bp
->eq_cons
;
5467 sw_prod
= bp
->eq_prod
;
5469 DP(BNX2X_MSG_SP
, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
5470 hw_cons
, sw_cons
, atomic_read(&bp
->eq_spq_left
));
5472 for (; sw_cons
!= hw_cons
;
5473 sw_prod
= NEXT_EQ_IDX(sw_prod
), sw_cons
= NEXT_EQ_IDX(sw_cons
)) {
5475 elem
= &bp
->eq_ring
[EQ_DESC(sw_cons
)];
5477 rc
= bnx2x_iov_eq_sp_event(bp
, elem
);
5479 DP(BNX2X_MSG_IOV
, "bnx2x_iov_eq_sp_event returned %d\n",
5484 opcode
= elem
->message
.opcode
;
5486 /* handle eq element */
5488 case EVENT_RING_OPCODE_VF_PF_CHANNEL
:
5489 bnx2x_vf_mbx_schedule(bp
,
5490 &elem
->message
.data
.vf_pf_event
);
5493 case EVENT_RING_OPCODE_STAT_QUERY
:
5494 DP_AND((BNX2X_MSG_SP
| BNX2X_MSG_STATS
),
5495 "got statistics comp event %d\n",
5497 /* nothing to do with stats comp */
5500 case EVENT_RING_OPCODE_CFC_DEL
:
5501 /* handle according to cid range */
5503 * we may want to verify here that the bp state is
5507 /* elem CID originates from FW; actually LE */
5508 cid
= SW_CID(elem
->message
.data
.cfc_del_event
.cid
);
5511 "got delete ramrod for MULTI[%d]\n", cid
);
5513 if (CNIC_LOADED(bp
) &&
5514 !bnx2x_cnic_handle_cfc_del(bp
, cid
, elem
))
5517 q_obj
= bnx2x_cid_to_q_obj(bp
, cid
);
5519 if (q_obj
->complete_cmd(bp
, q_obj
, BNX2X_Q_CMD_CFC_DEL
))
5524 case EVENT_RING_OPCODE_STOP_TRAFFIC
:
5525 DP(BNX2X_MSG_SP
| BNX2X_MSG_DCB
, "got STOP TRAFFIC\n");
5526 bnx2x_dcbx_set_params(bp
, BNX2X_DCBX_STATE_TX_PAUSED
);
5527 if (f_obj
->complete_cmd(bp
, f_obj
,
5528 BNX2X_F_CMD_TX_STOP
))
5532 case EVENT_RING_OPCODE_START_TRAFFIC
:
5533 DP(BNX2X_MSG_SP
| BNX2X_MSG_DCB
, "got START TRAFFIC\n");
5534 bnx2x_dcbx_set_params(bp
, BNX2X_DCBX_STATE_TX_RELEASED
);
5535 if (f_obj
->complete_cmd(bp
, f_obj
,
5536 BNX2X_F_CMD_TX_START
))
5540 case EVENT_RING_OPCODE_FUNCTION_UPDATE
:
5541 echo
= elem
->message
.data
.function_update_event
.echo
;
5542 if (echo
== SWITCH_UPDATE
) {
5543 DP(BNX2X_MSG_SP
| NETIF_MSG_IFUP
,
5544 "got FUNC_SWITCH_UPDATE ramrod\n");
5545 if (f_obj
->complete_cmd(
5546 bp
, f_obj
, BNX2X_F_CMD_SWITCH_UPDATE
))
5550 int cmd
= BNX2X_SP_RTNL_AFEX_F_UPDATE
;
5552 DP(BNX2X_MSG_SP
| BNX2X_MSG_MCP
,
5553 "AFEX: ramrod completed FUNCTION_UPDATE\n");
5554 f_obj
->complete_cmd(bp
, f_obj
,
5555 BNX2X_F_CMD_AFEX_UPDATE
);
5557 /* We will perform the Queues update from
5558 * sp_rtnl task as all Queue SP operations
5559 * should run under rtnl_lock.
5561 bnx2x_schedule_sp_rtnl(bp
, cmd
, 0);
5566 case EVENT_RING_OPCODE_AFEX_VIF_LISTS
:
5567 f_obj
->complete_cmd(bp
, f_obj
,
5568 BNX2X_F_CMD_AFEX_VIFLISTS
);
5569 bnx2x_after_afex_vif_lists(bp
, elem
);
5571 case EVENT_RING_OPCODE_FUNCTION_START
:
5572 DP(BNX2X_MSG_SP
| NETIF_MSG_IFUP
,
5573 "got FUNC_START ramrod\n");
5574 if (f_obj
->complete_cmd(bp
, f_obj
, BNX2X_F_CMD_START
))
5579 case EVENT_RING_OPCODE_FUNCTION_STOP
:
5580 DP(BNX2X_MSG_SP
| NETIF_MSG_IFUP
,
5581 "got FUNC_STOP ramrod\n");
5582 if (f_obj
->complete_cmd(bp
, f_obj
, BNX2X_F_CMD_STOP
))
5587 case EVENT_RING_OPCODE_SET_TIMESYNC
:
5588 DP(BNX2X_MSG_SP
| BNX2X_MSG_PTP
,
5589 "got set_timesync ramrod completion\n");
5590 if (f_obj
->complete_cmd(bp
, f_obj
,
5591 BNX2X_F_CMD_SET_TIMESYNC
))
5596 switch (opcode
| bp
->state
) {
5597 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES
|
5599 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES
|
5600 BNX2X_STATE_OPENING_WAIT4_PORT
):
5601 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES
|
5602 BNX2X_STATE_CLOSING_WAIT4_HALT
):
5603 DP(BNX2X_MSG_SP
, "got RSS_UPDATE ramrod. CID %d\n",
5604 SW_CID(elem
->message
.data
.eth_event
.echo
));
5605 rss_raw
->clear_pending(rss_raw
);
5608 case (EVENT_RING_OPCODE_SET_MAC
| BNX2X_STATE_OPEN
):
5609 case (EVENT_RING_OPCODE_SET_MAC
| BNX2X_STATE_DIAG
):
5610 case (EVENT_RING_OPCODE_SET_MAC
|
5611 BNX2X_STATE_CLOSING_WAIT4_HALT
):
5612 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES
|
5614 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES
|
5616 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES
|
5617 BNX2X_STATE_CLOSING_WAIT4_HALT
):
5618 DP(BNX2X_MSG_SP
, "got (un)set vlan/mac ramrod\n");
5619 bnx2x_handle_classification_eqe(bp
, elem
);
5622 case (EVENT_RING_OPCODE_MULTICAST_RULES
|
5624 case (EVENT_RING_OPCODE_MULTICAST_RULES
|
5626 case (EVENT_RING_OPCODE_MULTICAST_RULES
|
5627 BNX2X_STATE_CLOSING_WAIT4_HALT
):
5628 DP(BNX2X_MSG_SP
, "got mcast ramrod\n");
5629 bnx2x_handle_mcast_eqe(bp
);
5632 case (EVENT_RING_OPCODE_FILTERS_RULES
|
5634 case (EVENT_RING_OPCODE_FILTERS_RULES
|
5636 case (EVENT_RING_OPCODE_FILTERS_RULES
|
5637 BNX2X_STATE_CLOSING_WAIT4_HALT
):
5638 DP(BNX2X_MSG_SP
, "got rx_mode ramrod\n");
5639 bnx2x_handle_rx_mode_eqe(bp
);
5642 /* unknown event log error and continue */
5643 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5644 elem
->message
.opcode
, bp
->state
);
5650 smp_mb__before_atomic();
5651 atomic_add(spqe_cnt
, &bp
->eq_spq_left
);
5653 bp
->eq_cons
= sw_cons
;
5654 bp
->eq_prod
= sw_prod
;
5655 /* Make sure that above mem writes were issued towards the memory */
5658 /* update producer */
5659 bnx2x_update_eq_prod(bp
, bp
->eq_prod
);
5662 static void bnx2x_sp_task(struct work_struct
*work
)
5664 struct bnx2x
*bp
= container_of(work
, struct bnx2x
, sp_task
.work
);
5666 DP(BNX2X_MSG_SP
, "sp task invoked\n");
5668 /* make sure the atomic interrupt_occurred has been written */
5670 if (atomic_read(&bp
->interrupt_occurred
)) {
5672 /* what work needs to be performed? */
5673 u16 status
= bnx2x_update_dsb_idx(bp
);
5675 DP(BNX2X_MSG_SP
, "status %x\n", status
);
5676 DP(BNX2X_MSG_SP
, "setting interrupt_occurred to 0\n");
5677 atomic_set(&bp
->interrupt_occurred
, 0);
5680 if (status
& BNX2X_DEF_SB_ATT_IDX
) {
5682 status
&= ~BNX2X_DEF_SB_ATT_IDX
;
5685 /* SP events: STAT_QUERY and others */
5686 if (status
& BNX2X_DEF_SB_IDX
) {
5687 struct bnx2x_fastpath
*fp
= bnx2x_fcoe_fp(bp
);
5689 if (FCOE_INIT(bp
) &&
5690 (bnx2x_has_rx_work(fp
) || bnx2x_has_tx_work(fp
))) {
5691 /* Prevent local bottom-halves from running as
5692 * we are going to change the local NAPI list.
5695 napi_schedule(&bnx2x_fcoe(bp
, napi
));
5699 /* Handle EQ completions */
5701 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
, USTORM_ID
,
5702 le16_to_cpu(bp
->def_idx
), IGU_INT_NOP
, 1);
5704 status
&= ~BNX2X_DEF_SB_IDX
;
5707 /* if status is non zero then perhaps something went wrong */
5708 if (unlikely(status
))
5710 "got an unknown interrupt! (status 0x%x)\n", status
);
5712 /* ack status block only if something was actually handled */
5713 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
, ATTENTION_ID
,
5714 le16_to_cpu(bp
->def_att_idx
), IGU_INT_ENABLE
, 1);
5717 /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5718 if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK
,
5720 bnx2x_link_report(bp
);
5721 bnx2x_fw_command(bp
, DRV_MSG_CODE_AFEX_VIFSET_ACK
, 0);
5725 irqreturn_t
bnx2x_msix_sp_int(int irq
, void *dev_instance
)
5727 struct net_device
*dev
= dev_instance
;
5728 struct bnx2x
*bp
= netdev_priv(dev
);
5730 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
, USTORM_ID
, 0,
5731 IGU_INT_DISABLE
, 0);
5733 #ifdef BNX2X_STOP_ON_ERROR
5734 if (unlikely(bp
->panic
))
5738 if (CNIC_LOADED(bp
)) {
5739 struct cnic_ops
*c_ops
;
5742 c_ops
= rcu_dereference(bp
->cnic_ops
);
5744 c_ops
->cnic_handler(bp
->cnic_data
, NULL
);
5748 /* schedule sp task to perform default status block work, ack
5749 * attentions and enable interrupts.
5751 bnx2x_schedule_sp_task(bp
);
5756 /* end of slow path */
5758 void bnx2x_drv_pulse(struct bnx2x
*bp
)
5760 SHMEM_WR(bp
, func_mb
[BP_FW_MB_IDX(bp
)].drv_pulse_mb
,
5761 bp
->fw_drv_pulse_wr_seq
);
5764 static void bnx2x_timer(struct timer_list
*t
)
5766 struct bnx2x
*bp
= from_timer(bp
, t
, timer
);
5768 if (!netif_running(bp
->dev
))
5773 int mb_idx
= BP_FW_MB_IDX(bp
);
5777 ++bp
->fw_drv_pulse_wr_seq
;
5778 bp
->fw_drv_pulse_wr_seq
&= DRV_PULSE_SEQ_MASK
;
5779 drv_pulse
= bp
->fw_drv_pulse_wr_seq
;
5780 bnx2x_drv_pulse(bp
);
5782 mcp_pulse
= (SHMEM_RD(bp
, func_mb
[mb_idx
].mcp_pulse_mb
) &
5783 MCP_PULSE_SEQ_MASK
);
5784 /* The delta between driver pulse and mcp response
5785 * should not get too big. If the MFW is more than 5 pulses
5786 * behind, we should worry about it enough to generate an error
5789 if (((drv_pulse
- mcp_pulse
) & MCP_PULSE_SEQ_MASK
) > 5)
5790 BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5791 drv_pulse
, mcp_pulse
);
5794 if (bp
->state
== BNX2X_STATE_OPEN
)
5795 bnx2x_stats_handle(bp
, STATS_EVENT_UPDATE
);
5797 /* sample pf vf bulletin board for new posts from pf */
5799 bnx2x_timer_sriov(bp
);
5801 mod_timer(&bp
->timer
, jiffies
+ bp
->current_interval
);
5804 /* end of Statistics */
5809 * nic init service functions
5812 static void bnx2x_fill(struct bnx2x
*bp
, u32 addr
, int fill
, u32 len
)
5815 if (!(len
%4) && !(addr
%4))
5816 for (i
= 0; i
< len
; i
+= 4)
5817 REG_WR(bp
, addr
+ i
, fill
);
5819 for (i
= 0; i
< len
; i
++)
5820 REG_WR8(bp
, addr
+ i
, fill
);
5823 /* helper: writes FP SP data to FW - data_size in dwords */
5824 static void bnx2x_wr_fp_sb_data(struct bnx2x
*bp
,
5830 for (index
= 0; index
< data_size
; index
++)
5831 REG_WR(bp
, BAR_CSTRORM_INTMEM
+
5832 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id
) +
5834 *(sb_data_p
+ index
));
5837 static void bnx2x_zero_fp_sb(struct bnx2x
*bp
, int fw_sb_id
)
5841 struct hc_status_block_data_e2 sb_data_e2
;
5842 struct hc_status_block_data_e1x sb_data_e1x
;
5844 /* disable the function first */
5845 if (!CHIP_IS_E1x(bp
)) {
5846 memset(&sb_data_e2
, 0, sizeof(struct hc_status_block_data_e2
));
5847 sb_data_e2
.common
.state
= SB_DISABLED
;
5848 sb_data_e2
.common
.p_func
.vf_valid
= false;
5849 sb_data_p
= (u32
*)&sb_data_e2
;
5850 data_size
= sizeof(struct hc_status_block_data_e2
)/sizeof(u32
);
5852 memset(&sb_data_e1x
, 0,
5853 sizeof(struct hc_status_block_data_e1x
));
5854 sb_data_e1x
.common
.state
= SB_DISABLED
;
5855 sb_data_e1x
.common
.p_func
.vf_valid
= false;
5856 sb_data_p
= (u32
*)&sb_data_e1x
;
5857 data_size
= sizeof(struct hc_status_block_data_e1x
)/sizeof(u32
);
5859 bnx2x_wr_fp_sb_data(bp
, fw_sb_id
, sb_data_p
, data_size
);
5861 bnx2x_fill(bp
, BAR_CSTRORM_INTMEM
+
5862 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id
), 0,
5863 CSTORM_STATUS_BLOCK_SIZE
);
5864 bnx2x_fill(bp
, BAR_CSTRORM_INTMEM
+
5865 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id
), 0,
5866 CSTORM_SYNC_BLOCK_SIZE
);
5869 /* helper: writes SP SB data to FW */
5870 static void bnx2x_wr_sp_sb_data(struct bnx2x
*bp
,
5871 struct hc_sp_status_block_data
*sp_sb_data
)
5873 int func
= BP_FUNC(bp
);
5875 for (i
= 0; i
< sizeof(struct hc_sp_status_block_data
)/sizeof(u32
); i
++)
5876 REG_WR(bp
, BAR_CSTRORM_INTMEM
+
5877 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func
) +
5879 *((u32
*)sp_sb_data
+ i
));
5882 static void bnx2x_zero_sp_sb(struct bnx2x
*bp
)
5884 int func
= BP_FUNC(bp
);
5885 struct hc_sp_status_block_data sp_sb_data
;
5886 memset(&sp_sb_data
, 0, sizeof(struct hc_sp_status_block_data
));
5888 sp_sb_data
.state
= SB_DISABLED
;
5889 sp_sb_data
.p_func
.vf_valid
= false;
5891 bnx2x_wr_sp_sb_data(bp
, &sp_sb_data
);
5893 bnx2x_fill(bp
, BAR_CSTRORM_INTMEM
+
5894 CSTORM_SP_STATUS_BLOCK_OFFSET(func
), 0,
5895 CSTORM_SP_STATUS_BLOCK_SIZE
);
5896 bnx2x_fill(bp
, BAR_CSTRORM_INTMEM
+
5897 CSTORM_SP_SYNC_BLOCK_OFFSET(func
), 0,
5898 CSTORM_SP_SYNC_BLOCK_SIZE
);
5901 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm
*hc_sm
,
5902 int igu_sb_id
, int igu_seg_id
)
5904 hc_sm
->igu_sb_id
= igu_sb_id
;
5905 hc_sm
->igu_seg_id
= igu_seg_id
;
5906 hc_sm
->timer_value
= 0xFF;
5907 hc_sm
->time_to_expire
= 0xFFFFFFFF;
5910 /* allocates state machine ids. */
5911 static void bnx2x_map_sb_state_machines(struct hc_index_data
*index_data
)
5913 /* zero out state machine indices */
5915 index_data
[HC_INDEX_ETH_RX_CQ_CONS
].flags
&= ~HC_INDEX_DATA_SM_ID
;
5918 index_data
[HC_INDEX_OOO_TX_CQ_CONS
].flags
&= ~HC_INDEX_DATA_SM_ID
;
5919 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS0
].flags
&= ~HC_INDEX_DATA_SM_ID
;
5920 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS1
].flags
&= ~HC_INDEX_DATA_SM_ID
;
5921 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS2
].flags
&= ~HC_INDEX_DATA_SM_ID
;
5925 index_data
[HC_INDEX_ETH_RX_CQ_CONS
].flags
|=
5926 SM_RX_ID
<< HC_INDEX_DATA_SM_ID_SHIFT
;
5929 index_data
[HC_INDEX_OOO_TX_CQ_CONS
].flags
|=
5930 SM_TX_ID
<< HC_INDEX_DATA_SM_ID_SHIFT
;
5931 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS0
].flags
|=
5932 SM_TX_ID
<< HC_INDEX_DATA_SM_ID_SHIFT
;
5933 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS1
].flags
|=
5934 SM_TX_ID
<< HC_INDEX_DATA_SM_ID_SHIFT
;
5935 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS2
].flags
|=
5936 SM_TX_ID
<< HC_INDEX_DATA_SM_ID_SHIFT
;
5939 void bnx2x_init_sb(struct bnx2x
*bp
, dma_addr_t mapping
, int vfid
,
5940 u8 vf_valid
, int fw_sb_id
, int igu_sb_id
)
5944 struct hc_status_block_data_e2 sb_data_e2
;
5945 struct hc_status_block_data_e1x sb_data_e1x
;
5946 struct hc_status_block_sm
*hc_sm_p
;
5950 if (CHIP_INT_MODE_IS_BC(bp
))
5951 igu_seg_id
= HC_SEG_ACCESS_NORM
;
5953 igu_seg_id
= IGU_SEG_ACCESS_NORM
;
5955 bnx2x_zero_fp_sb(bp
, fw_sb_id
);
5957 if (!CHIP_IS_E1x(bp
)) {
5958 memset(&sb_data_e2
, 0, sizeof(struct hc_status_block_data_e2
));
5959 sb_data_e2
.common
.state
= SB_ENABLED
;
5960 sb_data_e2
.common
.p_func
.pf_id
= BP_FUNC(bp
);
5961 sb_data_e2
.common
.p_func
.vf_id
= vfid
;
5962 sb_data_e2
.common
.p_func
.vf_valid
= vf_valid
;
5963 sb_data_e2
.common
.p_func
.vnic_id
= BP_VN(bp
);
5964 sb_data_e2
.common
.same_igu_sb_1b
= true;
5965 sb_data_e2
.common
.host_sb_addr
.hi
= U64_HI(mapping
);
5966 sb_data_e2
.common
.host_sb_addr
.lo
= U64_LO(mapping
);
5967 hc_sm_p
= sb_data_e2
.common
.state_machine
;
5968 sb_data_p
= (u32
*)&sb_data_e2
;
5969 data_size
= sizeof(struct hc_status_block_data_e2
)/sizeof(u32
);
5970 bnx2x_map_sb_state_machines(sb_data_e2
.index_data
);
5972 memset(&sb_data_e1x
, 0,
5973 sizeof(struct hc_status_block_data_e1x
));
5974 sb_data_e1x
.common
.state
= SB_ENABLED
;
5975 sb_data_e1x
.common
.p_func
.pf_id
= BP_FUNC(bp
);
5976 sb_data_e1x
.common
.p_func
.vf_id
= 0xff;
5977 sb_data_e1x
.common
.p_func
.vf_valid
= false;
5978 sb_data_e1x
.common
.p_func
.vnic_id
= BP_VN(bp
);
5979 sb_data_e1x
.common
.same_igu_sb_1b
= true;
5980 sb_data_e1x
.common
.host_sb_addr
.hi
= U64_HI(mapping
);
5981 sb_data_e1x
.common
.host_sb_addr
.lo
= U64_LO(mapping
);
5982 hc_sm_p
= sb_data_e1x
.common
.state_machine
;
5983 sb_data_p
= (u32
*)&sb_data_e1x
;
5984 data_size
= sizeof(struct hc_status_block_data_e1x
)/sizeof(u32
);
5985 bnx2x_map_sb_state_machines(sb_data_e1x
.index_data
);
5988 bnx2x_setup_ndsb_state_machine(&hc_sm_p
[SM_RX_ID
],
5989 igu_sb_id
, igu_seg_id
);
5990 bnx2x_setup_ndsb_state_machine(&hc_sm_p
[SM_TX_ID
],
5991 igu_sb_id
, igu_seg_id
);
5993 DP(NETIF_MSG_IFUP
, "Init FW SB %d\n", fw_sb_id
);
5995 /* write indices to HW - PCI guarantees endianity of regpairs */
5996 bnx2x_wr_fp_sb_data(bp
, fw_sb_id
, sb_data_p
, data_size
);
5999 static void bnx2x_update_coalesce_sb(struct bnx2x
*bp
, u8 fw_sb_id
,
6000 u16 tx_usec
, u16 rx_usec
)
6002 bnx2x_update_coalesce_sb_index(bp
, fw_sb_id
, HC_INDEX_ETH_RX_CQ_CONS
,
6004 bnx2x_update_coalesce_sb_index(bp
, fw_sb_id
,
6005 HC_INDEX_ETH_TX_CQ_CONS_COS0
, false,
6007 bnx2x_update_coalesce_sb_index(bp
, fw_sb_id
,
6008 HC_INDEX_ETH_TX_CQ_CONS_COS1
, false,
6010 bnx2x_update_coalesce_sb_index(bp
, fw_sb_id
,
6011 HC_INDEX_ETH_TX_CQ_CONS_COS2
, false,
6015 static void bnx2x_init_def_sb(struct bnx2x
*bp
)
6017 struct host_sp_status_block
*def_sb
= bp
->def_status_blk
;
6018 dma_addr_t mapping
= bp
->def_status_blk_mapping
;
6019 int igu_sp_sb_index
;
6021 int port
= BP_PORT(bp
);
6022 int func
= BP_FUNC(bp
);
6023 int reg_offset
, reg_offset_en5
;
6026 struct hc_sp_status_block_data sp_sb_data
;
6027 memset(&sp_sb_data
, 0, sizeof(struct hc_sp_status_block_data
));
6029 if (CHIP_INT_MODE_IS_BC(bp
)) {
6030 igu_sp_sb_index
= DEF_SB_IGU_ID
;
6031 igu_seg_id
= HC_SEG_ACCESS_DEF
;
6033 igu_sp_sb_index
= bp
->igu_dsb_id
;
6034 igu_seg_id
= IGU_SEG_ACCESS_DEF
;
6038 section
= ((u64
)mapping
) + offsetof(struct host_sp_status_block
,
6039 atten_status_block
);
6040 def_sb
->atten_status_block
.status_block_id
= igu_sp_sb_index
;
6044 reg_offset
= (port
? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0
:
6045 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0
);
6046 reg_offset_en5
= (port
? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0
:
6047 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0
);
6048 for (index
= 0; index
< MAX_DYNAMIC_ATTN_GRPS
; index
++) {
6050 /* take care of sig[0]..sig[4] */
6051 for (sindex
= 0; sindex
< 4; sindex
++)
6052 bp
->attn_group
[index
].sig
[sindex
] =
6053 REG_RD(bp
, reg_offset
+ sindex
*0x4 + 0x10*index
);
6055 if (!CHIP_IS_E1x(bp
))
6057 * enable5 is separate from the rest of the registers,
6058 * and therefore the address skip is 4
6059 * and not 16 between the different groups
6061 bp
->attn_group
[index
].sig
[4] = REG_RD(bp
,
6062 reg_offset_en5
+ 0x4*index
);
6064 bp
->attn_group
[index
].sig
[4] = 0;
6067 if (bp
->common
.int_block
== INT_BLOCK_HC
) {
6068 reg_offset
= (port
? HC_REG_ATTN_MSG1_ADDR_L
:
6069 HC_REG_ATTN_MSG0_ADDR_L
);
6071 REG_WR(bp
, reg_offset
, U64_LO(section
));
6072 REG_WR(bp
, reg_offset
+ 4, U64_HI(section
));
6073 } else if (!CHIP_IS_E1x(bp
)) {
6074 REG_WR(bp
, IGU_REG_ATTN_MSG_ADDR_L
, U64_LO(section
));
6075 REG_WR(bp
, IGU_REG_ATTN_MSG_ADDR_H
, U64_HI(section
));
6078 section
= ((u64
)mapping
) + offsetof(struct host_sp_status_block
,
6081 bnx2x_zero_sp_sb(bp
);
6083 /* PCI guarantees endianity of regpairs */
6084 sp_sb_data
.state
= SB_ENABLED
;
6085 sp_sb_data
.host_sb_addr
.lo
= U64_LO(section
);
6086 sp_sb_data
.host_sb_addr
.hi
= U64_HI(section
);
6087 sp_sb_data
.igu_sb_id
= igu_sp_sb_index
;
6088 sp_sb_data
.igu_seg_id
= igu_seg_id
;
6089 sp_sb_data
.p_func
.pf_id
= func
;
6090 sp_sb_data
.p_func
.vnic_id
= BP_VN(bp
);
6091 sp_sb_data
.p_func
.vf_id
= 0xff;
6093 bnx2x_wr_sp_sb_data(bp
, &sp_sb_data
);
6095 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
, USTORM_ID
, 0, IGU_INT_ENABLE
, 0);
6098 void bnx2x_update_coalesce(struct bnx2x
*bp
)
6102 for_each_eth_queue(bp
, i
)
6103 bnx2x_update_coalesce_sb(bp
, bp
->fp
[i
].fw_sb_id
,
6104 bp
->tx_ticks
, bp
->rx_ticks
);
6107 static void bnx2x_init_sp_ring(struct bnx2x
*bp
)
6109 spin_lock_init(&bp
->spq_lock
);
6110 atomic_set(&bp
->cq_spq_left
, MAX_SPQ_PENDING
);
6112 bp
->spq_prod_idx
= 0;
6113 bp
->dsb_sp_prod
= BNX2X_SP_DSB_INDEX
;
6114 bp
->spq_prod_bd
= bp
->spq
;
6115 bp
->spq_last_bd
= bp
->spq_prod_bd
+ MAX_SP_DESC_CNT
;
6118 static void bnx2x_init_eq_ring(struct bnx2x
*bp
)
6121 for (i
= 1; i
<= NUM_EQ_PAGES
; i
++) {
6122 union event_ring_elem
*elem
=
6123 &bp
->eq_ring
[EQ_DESC_CNT_PAGE
* i
- 1];
6125 elem
->next_page
.addr
.hi
=
6126 cpu_to_le32(U64_HI(bp
->eq_mapping
+
6127 BCM_PAGE_SIZE
* (i
% NUM_EQ_PAGES
)));
6128 elem
->next_page
.addr
.lo
=
6129 cpu_to_le32(U64_LO(bp
->eq_mapping
+
6130 BCM_PAGE_SIZE
*(i
% NUM_EQ_PAGES
)));
6133 bp
->eq_prod
= NUM_EQ_DESC
;
6134 bp
->eq_cons_sb
= BNX2X_EQ_INDEX
;
6135 /* we want a warning message before it gets wrought... */
6136 atomic_set(&bp
->eq_spq_left
,
6137 min_t(int, MAX_SP_DESC_CNT
- MAX_SPQ_PENDING
, NUM_EQ_DESC
) - 1);
6140 /* called with netif_addr_lock_bh() */
6141 static int bnx2x_set_q_rx_mode(struct bnx2x
*bp
, u8 cl_id
,
6142 unsigned long rx_mode_flags
,
6143 unsigned long rx_accept_flags
,
6144 unsigned long tx_accept_flags
,
6145 unsigned long ramrod_flags
)
6147 struct bnx2x_rx_mode_ramrod_params ramrod_param
;
6150 memset(&ramrod_param
, 0, sizeof(ramrod_param
));
6152 /* Prepare ramrod parameters */
6153 ramrod_param
.cid
= 0;
6154 ramrod_param
.cl_id
= cl_id
;
6155 ramrod_param
.rx_mode_obj
= &bp
->rx_mode_obj
;
6156 ramrod_param
.func_id
= BP_FUNC(bp
);
6158 ramrod_param
.pstate
= &bp
->sp_state
;
6159 ramrod_param
.state
= BNX2X_FILTER_RX_MODE_PENDING
;
6161 ramrod_param
.rdata
= bnx2x_sp(bp
, rx_mode_rdata
);
6162 ramrod_param
.rdata_mapping
= bnx2x_sp_mapping(bp
, rx_mode_rdata
);
6164 set_bit(BNX2X_FILTER_RX_MODE_PENDING
, &bp
->sp_state
);
6166 ramrod_param
.ramrod_flags
= ramrod_flags
;
6167 ramrod_param
.rx_mode_flags
= rx_mode_flags
;
6169 ramrod_param
.rx_accept_flags
= rx_accept_flags
;
6170 ramrod_param
.tx_accept_flags
= tx_accept_flags
;
6172 rc
= bnx2x_config_rx_mode(bp
, &ramrod_param
);
6174 BNX2X_ERR("Set rx_mode %d failed\n", bp
->rx_mode
);
6181 static int bnx2x_fill_accept_flags(struct bnx2x
*bp
, u32 rx_mode
,
6182 unsigned long *rx_accept_flags
,
6183 unsigned long *tx_accept_flags
)
6185 /* Clear the flags first */
6186 *rx_accept_flags
= 0;
6187 *tx_accept_flags
= 0;
6190 case BNX2X_RX_MODE_NONE
:
6192 * 'drop all' supersedes any accept flags that may have been
6193 * passed to the function.
6196 case BNX2X_RX_MODE_NORMAL
:
6197 __set_bit(BNX2X_ACCEPT_UNICAST
, rx_accept_flags
);
6198 __set_bit(BNX2X_ACCEPT_MULTICAST
, rx_accept_flags
);
6199 __set_bit(BNX2X_ACCEPT_BROADCAST
, rx_accept_flags
);
6201 /* internal switching mode */
6202 __set_bit(BNX2X_ACCEPT_UNICAST
, tx_accept_flags
);
6203 __set_bit(BNX2X_ACCEPT_MULTICAST
, tx_accept_flags
);
6204 __set_bit(BNX2X_ACCEPT_BROADCAST
, tx_accept_flags
);
6206 if (bp
->accept_any_vlan
) {
6207 __set_bit(BNX2X_ACCEPT_ANY_VLAN
, rx_accept_flags
);
6208 __set_bit(BNX2X_ACCEPT_ANY_VLAN
, tx_accept_flags
);
6212 case BNX2X_RX_MODE_ALLMULTI
:
6213 __set_bit(BNX2X_ACCEPT_UNICAST
, rx_accept_flags
);
6214 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST
, rx_accept_flags
);
6215 __set_bit(BNX2X_ACCEPT_BROADCAST
, rx_accept_flags
);
6217 /* internal switching mode */
6218 __set_bit(BNX2X_ACCEPT_UNICAST
, tx_accept_flags
);
6219 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST
, tx_accept_flags
);
6220 __set_bit(BNX2X_ACCEPT_BROADCAST
, tx_accept_flags
);
6222 if (bp
->accept_any_vlan
) {
6223 __set_bit(BNX2X_ACCEPT_ANY_VLAN
, rx_accept_flags
);
6224 __set_bit(BNX2X_ACCEPT_ANY_VLAN
, tx_accept_flags
);
6228 case BNX2X_RX_MODE_PROMISC
:
6229 /* According to definition of SI mode, iface in promisc mode
6230 * should receive matched and unmatched (in resolution of port)
6233 __set_bit(BNX2X_ACCEPT_UNMATCHED
, rx_accept_flags
);
6234 __set_bit(BNX2X_ACCEPT_UNICAST
, rx_accept_flags
);
6235 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST
, rx_accept_flags
);
6236 __set_bit(BNX2X_ACCEPT_BROADCAST
, rx_accept_flags
);
6238 /* internal switching mode */
6239 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST
, tx_accept_flags
);
6240 __set_bit(BNX2X_ACCEPT_BROADCAST
, tx_accept_flags
);
6243 __set_bit(BNX2X_ACCEPT_ALL_UNICAST
, tx_accept_flags
);
6245 __set_bit(BNX2X_ACCEPT_UNICAST
, tx_accept_flags
);
6247 __set_bit(BNX2X_ACCEPT_ANY_VLAN
, rx_accept_flags
);
6248 __set_bit(BNX2X_ACCEPT_ANY_VLAN
, tx_accept_flags
);
6252 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode
);
6259 /* called with netif_addr_lock_bh() */
6260 static int bnx2x_set_storm_rx_mode(struct bnx2x
*bp
)
6262 unsigned long rx_mode_flags
= 0, ramrod_flags
= 0;
6263 unsigned long rx_accept_flags
= 0, tx_accept_flags
= 0;
6267 /* Configure rx_mode of FCoE Queue */
6268 __set_bit(BNX2X_RX_MODE_FCOE_ETH
, &rx_mode_flags
);
6270 rc
= bnx2x_fill_accept_flags(bp
, bp
->rx_mode
, &rx_accept_flags
,
6275 __set_bit(RAMROD_RX
, &ramrod_flags
);
6276 __set_bit(RAMROD_TX
, &ramrod_flags
);
6278 return bnx2x_set_q_rx_mode(bp
, bp
->fp
->cl_id
, rx_mode_flags
,
6279 rx_accept_flags
, tx_accept_flags
,
6283 static void bnx2x_init_internal_common(struct bnx2x
*bp
)
6287 /* Zero this manually as its initialization is
6288 currently missing in the initTool */
6289 for (i
= 0; i
< (USTORM_AGG_DATA_SIZE
>> 2); i
++)
6290 REG_WR(bp
, BAR_USTRORM_INTMEM
+
6291 USTORM_AGG_DATA_OFFSET
+ i
* 4, 0);
6292 if (!CHIP_IS_E1x(bp
)) {
6293 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+ CSTORM_IGU_MODE_OFFSET
,
6294 CHIP_INT_MODE_IS_BC(bp
) ?
6295 HC_IGU_BC_MODE
: HC_IGU_NBC_MODE
);
6299 static void bnx2x_init_internal(struct bnx2x
*bp
, u32 load_code
)
6301 switch (load_code
) {
6302 case FW_MSG_CODE_DRV_LOAD_COMMON
:
6303 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP
:
6304 bnx2x_init_internal_common(bp
);
6307 case FW_MSG_CODE_DRV_LOAD_PORT
:
6311 case FW_MSG_CODE_DRV_LOAD_FUNCTION
:
6312 /* internal memory per function is
6313 initialized inside bnx2x_pf_init */
6317 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code
);
6322 static inline u8
bnx2x_fp_igu_sb_id(struct bnx2x_fastpath
*fp
)
6324 return fp
->bp
->igu_base_sb
+ fp
->index
+ CNIC_SUPPORT(fp
->bp
);
6327 static inline u8
bnx2x_fp_fw_sb_id(struct bnx2x_fastpath
*fp
)
6329 return fp
->bp
->base_fw_ndsb
+ fp
->index
+ CNIC_SUPPORT(fp
->bp
);
6332 static u8
bnx2x_fp_cl_id(struct bnx2x_fastpath
*fp
)
6334 if (CHIP_IS_E1x(fp
->bp
))
6335 return BP_L_ID(fp
->bp
) + fp
->index
;
6336 else /* We want Client ID to be the same as IGU SB ID for 57712 */
6337 return bnx2x_fp_igu_sb_id(fp
);
6340 static void bnx2x_init_eth_fp(struct bnx2x
*bp
, int fp_idx
)
6342 struct bnx2x_fastpath
*fp
= &bp
->fp
[fp_idx
];
6344 unsigned long q_type
= 0;
6345 u32 cids
[BNX2X_MULTI_TX_COS
] = { 0 };
6346 fp
->rx_queue
= fp_idx
;
6348 fp
->cl_id
= bnx2x_fp_cl_id(fp
);
6349 fp
->fw_sb_id
= bnx2x_fp_fw_sb_id(fp
);
6350 fp
->igu_sb_id
= bnx2x_fp_igu_sb_id(fp
);
6351 /* qZone id equals to FW (per path) client id */
6352 fp
->cl_qzone_id
= bnx2x_fp_qzone_id(fp
);
6355 fp
->ustorm_rx_prods_offset
= bnx2x_rx_ustorm_prods_offset(fp
);
6357 /* Setup SB indices */
6358 fp
->rx_cons_sb
= BNX2X_RX_SB_INDEX
;
6360 /* Configure Queue State object */
6361 __set_bit(BNX2X_Q_TYPE_HAS_RX
, &q_type
);
6362 __set_bit(BNX2X_Q_TYPE_HAS_TX
, &q_type
);
6364 BUG_ON(fp
->max_cos
> BNX2X_MULTI_TX_COS
);
6367 for_each_cos_in_tx_queue(fp
, cos
) {
6368 bnx2x_init_txdata(bp
, fp
->txdata_ptr
[cos
],
6369 CID_COS_TO_TX_ONLY_CID(fp
->cid
, cos
, bp
),
6370 FP_COS_TO_TXQ(fp
, cos
, bp
),
6371 BNX2X_TX_SB_INDEX_BASE
+ cos
, fp
);
6372 cids
[cos
] = fp
->txdata_ptr
[cos
]->cid
;
6375 /* nothing more for vf to do here */
6379 bnx2x_init_sb(bp
, fp
->status_blk_mapping
, BNX2X_VF_ID_INVALID
, false,
6380 fp
->fw_sb_id
, fp
->igu_sb_id
);
6381 bnx2x_update_fpsb_idx(fp
);
6382 bnx2x_init_queue_obj(bp
, &bnx2x_sp_obj(bp
, fp
).q_obj
, fp
->cl_id
, cids
,
6383 fp
->max_cos
, BP_FUNC(bp
), bnx2x_sp(bp
, q_rdata
),
6384 bnx2x_sp_mapping(bp
, q_rdata
), q_type
);
6387 * Configure classification DBs: Always enable Tx switching
6389 bnx2x_init_vlan_mac_fp_objs(fp
, BNX2X_OBJ_TYPE_RX_TX
);
6392 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6393 fp_idx
, bp
, fp
->status_blk
.e2_sb
, fp
->cl_id
, fp
->fw_sb_id
,
6397 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata
*txdata
)
6401 for (i
= 1; i
<= NUM_TX_RINGS
; i
++) {
6402 struct eth_tx_next_bd
*tx_next_bd
=
6403 &txdata
->tx_desc_ring
[TX_DESC_CNT
* i
- 1].next_bd
;
6405 tx_next_bd
->addr_hi
=
6406 cpu_to_le32(U64_HI(txdata
->tx_desc_mapping
+
6407 BCM_PAGE_SIZE
*(i
% NUM_TX_RINGS
)));
6408 tx_next_bd
->addr_lo
=
6409 cpu_to_le32(U64_LO(txdata
->tx_desc_mapping
+
6410 BCM_PAGE_SIZE
*(i
% NUM_TX_RINGS
)));
6413 *txdata
->tx_cons_sb
= cpu_to_le16(0);
6415 SET_FLAG(txdata
->tx_db
.data
.header
.header
, DOORBELL_HDR_DB_TYPE
, 1);
6416 txdata
->tx_db
.data
.zero_fill1
= 0;
6417 txdata
->tx_db
.data
.prod
= 0;
6419 txdata
->tx_pkt_prod
= 0;
6420 txdata
->tx_pkt_cons
= 0;
6421 txdata
->tx_bd_prod
= 0;
6422 txdata
->tx_bd_cons
= 0;
6426 static void bnx2x_init_tx_rings_cnic(struct bnx2x
*bp
)
6430 for_each_tx_queue_cnic(bp
, i
)
6431 bnx2x_init_tx_ring_one(bp
->fp
[i
].txdata_ptr
[0]);
6434 static void bnx2x_init_tx_rings(struct bnx2x
*bp
)
6439 for_each_eth_queue(bp
, i
)
6440 for_each_cos_in_tx_queue(&bp
->fp
[i
], cos
)
6441 bnx2x_init_tx_ring_one(bp
->fp
[i
].txdata_ptr
[cos
]);
6444 static void bnx2x_init_fcoe_fp(struct bnx2x
*bp
)
6446 struct bnx2x_fastpath
*fp
= bnx2x_fcoe_fp(bp
);
6447 unsigned long q_type
= 0;
6449 bnx2x_fcoe(bp
, rx_queue
) = BNX2X_NUM_ETH_QUEUES(bp
);
6450 bnx2x_fcoe(bp
, cl_id
) = bnx2x_cnic_eth_cl_id(bp
,
6451 BNX2X_FCOE_ETH_CL_ID_IDX
);
6452 bnx2x_fcoe(bp
, cid
) = BNX2X_FCOE_ETH_CID(bp
);
6453 bnx2x_fcoe(bp
, fw_sb_id
) = DEF_SB_ID
;
6454 bnx2x_fcoe(bp
, igu_sb_id
) = bp
->igu_dsb_id
;
6455 bnx2x_fcoe(bp
, rx_cons_sb
) = BNX2X_FCOE_L2_RX_INDEX
;
6456 bnx2x_init_txdata(bp
, bnx2x_fcoe(bp
, txdata_ptr
[0]),
6457 fp
->cid
, FCOE_TXQ_IDX(bp
), BNX2X_FCOE_L2_TX_INDEX
,
6460 DP(NETIF_MSG_IFUP
, "created fcoe tx data (fp index %d)\n", fp
->index
);
6462 /* qZone id equals to FW (per path) client id */
6463 bnx2x_fcoe(bp
, cl_qzone_id
) = bnx2x_fp_qzone_id(fp
);
6465 bnx2x_fcoe(bp
, ustorm_rx_prods_offset
) =
6466 bnx2x_rx_ustorm_prods_offset(fp
);
6468 /* Configure Queue State object */
6469 __set_bit(BNX2X_Q_TYPE_HAS_RX
, &q_type
);
6470 __set_bit(BNX2X_Q_TYPE_HAS_TX
, &q_type
);
6472 /* No multi-CoS for FCoE L2 client */
6473 BUG_ON(fp
->max_cos
!= 1);
6475 bnx2x_init_queue_obj(bp
, &bnx2x_sp_obj(bp
, fp
).q_obj
, fp
->cl_id
,
6476 &fp
->cid
, 1, BP_FUNC(bp
), bnx2x_sp(bp
, q_rdata
),
6477 bnx2x_sp_mapping(bp
, q_rdata
), q_type
);
6480 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6481 fp
->index
, bp
, fp
->status_blk
.e2_sb
, fp
->cl_id
, fp
->fw_sb_id
,
6485 void bnx2x_nic_init_cnic(struct bnx2x
*bp
)
6488 bnx2x_init_fcoe_fp(bp
);
6490 bnx2x_init_sb(bp
, bp
->cnic_sb_mapping
,
6491 BNX2X_VF_ID_INVALID
, false,
6492 bnx2x_cnic_fw_sb_id(bp
), bnx2x_cnic_igu_sb_id(bp
));
6494 /* ensure status block indices were read */
6496 bnx2x_init_rx_rings_cnic(bp
);
6497 bnx2x_init_tx_rings_cnic(bp
);
6504 void bnx2x_pre_irq_nic_init(struct bnx2x
*bp
)
6508 /* Setup NIC internals and enable interrupts */
6509 for_each_eth_queue(bp
, i
)
6510 bnx2x_init_eth_fp(bp
, i
);
6512 /* ensure status block indices were read */
6514 bnx2x_init_rx_rings(bp
);
6515 bnx2x_init_tx_rings(bp
);
6518 /* Initialize MOD_ABS interrupts */
6519 bnx2x_init_mod_abs_int(bp
, &bp
->link_vars
, bp
->common
.chip_id
,
6520 bp
->common
.shmem_base
,
6521 bp
->common
.shmem2_base
, BP_PORT(bp
));
6523 /* initialize the default status block and sp ring */
6524 bnx2x_init_def_sb(bp
);
6525 bnx2x_update_dsb_idx(bp
);
6526 bnx2x_init_sp_ring(bp
);
6528 bnx2x_memset_stats(bp
);
6532 void bnx2x_post_irq_nic_init(struct bnx2x
*bp
, u32 load_code
)
6534 bnx2x_init_eq_ring(bp
);
6535 bnx2x_init_internal(bp
, load_code
);
6537 bnx2x_stats_init(bp
);
6539 /* flush all before enabling interrupts */
6543 bnx2x_int_enable(bp
);
6545 /* Check for SPIO5 */
6546 bnx2x_attn_int_deasserted0(bp
,
6547 REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0
+ BP_PORT(bp
)*4) &
6548 AEU_INPUTS_ATTN_BITS_SPIO5
);
6551 /* gzip service functions */
6552 static int bnx2x_gunzip_init(struct bnx2x
*bp
)
6554 bp
->gunzip_buf
= dma_alloc_coherent(&bp
->pdev
->dev
, FW_BUF_SIZE
,
6555 &bp
->gunzip_mapping
, GFP_KERNEL
);
6556 if (bp
->gunzip_buf
== NULL
)
6559 bp
->strm
= kmalloc(sizeof(*bp
->strm
), GFP_KERNEL
);
6560 if (bp
->strm
== NULL
)
6563 bp
->strm
->workspace
= vmalloc(zlib_inflate_workspacesize());
6564 if (bp
->strm
->workspace
== NULL
)
6574 dma_free_coherent(&bp
->pdev
->dev
, FW_BUF_SIZE
, bp
->gunzip_buf
,
6575 bp
->gunzip_mapping
);
6576 bp
->gunzip_buf
= NULL
;
6579 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
6583 static void bnx2x_gunzip_end(struct bnx2x
*bp
)
6586 vfree(bp
->strm
->workspace
);
6591 if (bp
->gunzip_buf
) {
6592 dma_free_coherent(&bp
->pdev
->dev
, FW_BUF_SIZE
, bp
->gunzip_buf
,
6593 bp
->gunzip_mapping
);
6594 bp
->gunzip_buf
= NULL
;
6598 static int bnx2x_gunzip(struct bnx2x
*bp
, const u8
*zbuf
, int len
)
6602 /* check gzip header */
6603 if ((zbuf
[0] != 0x1f) || (zbuf
[1] != 0x8b) || (zbuf
[2] != Z_DEFLATED
)) {
6604 BNX2X_ERR("Bad gzip header\n");
6612 if (zbuf
[3] & FNAME
)
6613 while ((zbuf
[n
++] != 0) && (n
< len
));
6615 bp
->strm
->next_in
= (typeof(bp
->strm
->next_in
))zbuf
+ n
;
6616 bp
->strm
->avail_in
= len
- n
;
6617 bp
->strm
->next_out
= bp
->gunzip_buf
;
6618 bp
->strm
->avail_out
= FW_BUF_SIZE
;
6620 rc
= zlib_inflateInit2(bp
->strm
, -MAX_WBITS
);
6624 rc
= zlib_inflate(bp
->strm
, Z_FINISH
);
6625 if ((rc
!= Z_OK
) && (rc
!= Z_STREAM_END
))
6626 netdev_err(bp
->dev
, "Firmware decompression error: %s\n",
6629 bp
->gunzip_outlen
= (FW_BUF_SIZE
- bp
->strm
->avail_out
);
6630 if (bp
->gunzip_outlen
& 0x3)
6632 "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
6634 bp
->gunzip_outlen
>>= 2;
6636 zlib_inflateEnd(bp
->strm
);
6638 if (rc
== Z_STREAM_END
)
6644 /* nic load/unload */
6647 * General service functions
6650 /* send a NIG loopback debug packet */
6651 static void bnx2x_lb_pckt(struct bnx2x
*bp
)
6655 /* Ethernet source and destination addresses */
6656 wb_write
[0] = 0x55555555;
6657 wb_write
[1] = 0x55555555;
6658 wb_write
[2] = 0x20; /* SOP */
6659 REG_WR_DMAE(bp
, NIG_REG_DEBUG_PACKET_LB
, wb_write
, 3);
6661 /* NON-IP protocol */
6662 wb_write
[0] = 0x09000000;
6663 wb_write
[1] = 0x55555555;
6664 wb_write
[2] = 0x10; /* EOP, eop_bvalid = 0 */
6665 REG_WR_DMAE(bp
, NIG_REG_DEBUG_PACKET_LB
, wb_write
, 3);
6668 /* some of the internal memories
6669 * are not directly readable from the driver
6670 * to test them we send debug packets
6672 static int bnx2x_int_mem_test(struct bnx2x
*bp
)
6678 if (CHIP_REV_IS_FPGA(bp
))
6680 else if (CHIP_REV_IS_EMUL(bp
))
6685 /* Disable inputs of parser neighbor blocks */
6686 REG_WR(bp
, TSDM_REG_ENABLE_IN1
, 0x0);
6687 REG_WR(bp
, TCM_REG_PRS_IFEN
, 0x0);
6688 REG_WR(bp
, CFC_REG_DEBUG0
, 0x1);
6689 REG_WR(bp
, NIG_REG_PRS_REQ_IN_EN
, 0x0);
6691 /* Write 0 to parser credits for CFC search request */
6692 REG_WR(bp
, PRS_REG_CFC_SEARCH_INITIAL_CREDIT
, 0x0);
6694 /* send Ethernet packet */
6697 /* TODO do i reset NIG statistic? */
6698 /* Wait until NIG register shows 1 packet of size 0x10 */
6699 count
= 1000 * factor
;
6702 bnx2x_read_dmae(bp
, NIG_REG_STAT2_BRB_OCTET
, 2);
6703 val
= *bnx2x_sp(bp
, wb_data
[0]);
6707 usleep_range(10000, 20000);
6711 BNX2X_ERR("NIG timeout val = 0x%x\n", val
);
6715 /* Wait until PRS register shows 1 packet */
6716 count
= 1000 * factor
;
6718 val
= REG_RD(bp
, PRS_REG_NUM_OF_PACKETS
);
6722 usleep_range(10000, 20000);
6726 BNX2X_ERR("PRS timeout val = 0x%x\n", val
);
6730 /* Reset and init BRB, PRS */
6731 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
, 0x03);
6733 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
, 0x03);
6735 bnx2x_init_block(bp
, BLOCK_BRB1
, PHASE_COMMON
);
6736 bnx2x_init_block(bp
, BLOCK_PRS
, PHASE_COMMON
);
6738 DP(NETIF_MSG_HW
, "part2\n");
6740 /* Disable inputs of parser neighbor blocks */
6741 REG_WR(bp
, TSDM_REG_ENABLE_IN1
, 0x0);
6742 REG_WR(bp
, TCM_REG_PRS_IFEN
, 0x0);
6743 REG_WR(bp
, CFC_REG_DEBUG0
, 0x1);
6744 REG_WR(bp
, NIG_REG_PRS_REQ_IN_EN
, 0x0);
6746 /* Write 0 to parser credits for CFC search request */
6747 REG_WR(bp
, PRS_REG_CFC_SEARCH_INITIAL_CREDIT
, 0x0);
6749 /* send 10 Ethernet packets */
6750 for (i
= 0; i
< 10; i
++)
6753 /* Wait until NIG register shows 10 + 1
6754 packets of size 11*0x10 = 0xb0 */
6755 count
= 1000 * factor
;
6758 bnx2x_read_dmae(bp
, NIG_REG_STAT2_BRB_OCTET
, 2);
6759 val
= *bnx2x_sp(bp
, wb_data
[0]);
6763 usleep_range(10000, 20000);
6767 BNX2X_ERR("NIG timeout val = 0x%x\n", val
);
6771 /* Wait until PRS register shows 2 packets */
6772 val
= REG_RD(bp
, PRS_REG_NUM_OF_PACKETS
);
6774 BNX2X_ERR("PRS timeout val = 0x%x\n", val
);
6776 /* Write 1 to parser credits for CFC search request */
6777 REG_WR(bp
, PRS_REG_CFC_SEARCH_INITIAL_CREDIT
, 0x1);
6779 /* Wait until PRS register shows 3 packets */
6780 msleep(10 * factor
);
6781 /* Wait until NIG register shows 1 packet of size 0x10 */
6782 val
= REG_RD(bp
, PRS_REG_NUM_OF_PACKETS
);
6784 BNX2X_ERR("PRS timeout val = 0x%x\n", val
);
6786 /* clear NIG EOP FIFO */
6787 for (i
= 0; i
< 11; i
++)
6788 REG_RD(bp
, NIG_REG_INGRESS_EOP_LB_FIFO
);
6789 val
= REG_RD(bp
, NIG_REG_INGRESS_EOP_LB_EMPTY
);
6791 BNX2X_ERR("clear of NIG failed\n");
6795 /* Reset and init BRB, PRS, NIG */
6796 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
, 0x03);
6798 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
, 0x03);
6800 bnx2x_init_block(bp
, BLOCK_BRB1
, PHASE_COMMON
);
6801 bnx2x_init_block(bp
, BLOCK_PRS
, PHASE_COMMON
);
6802 if (!CNIC_SUPPORT(bp
))
6804 REG_WR(bp
, PRS_REG_NIC_MODE
, 1);
6806 /* Enable inputs of parser neighbor blocks */
6807 REG_WR(bp
, TSDM_REG_ENABLE_IN1
, 0x7fffffff);
6808 REG_WR(bp
, TCM_REG_PRS_IFEN
, 0x1);
6809 REG_WR(bp
, CFC_REG_DEBUG0
, 0x0);
6810 REG_WR(bp
, NIG_REG_PRS_REQ_IN_EN
, 0x1);
6812 DP(NETIF_MSG_HW
, "done\n");
6817 static void bnx2x_enable_blocks_attention(struct bnx2x
*bp
)
6821 REG_WR(bp
, PXP_REG_PXP_INT_MASK_0
, 0);
6822 if (!CHIP_IS_E1x(bp
))
6823 REG_WR(bp
, PXP_REG_PXP_INT_MASK_1
, 0x40);
6825 REG_WR(bp
, PXP_REG_PXP_INT_MASK_1
, 0);
6826 REG_WR(bp
, DORQ_REG_DORQ_INT_MASK
, 0);
6827 REG_WR(bp
, CFC_REG_CFC_INT_MASK
, 0);
6829 * mask read length error interrupts in brb for parser
6830 * (parsing unit and 'checksum and crc' unit)
6831 * these errors are legal (PU reads fixed length and CAC can cause
6832 * read length error on truncated packets)
6834 REG_WR(bp
, BRB1_REG_BRB1_INT_MASK
, 0xFC00);
6835 REG_WR(bp
, QM_REG_QM_INT_MASK
, 0);
6836 REG_WR(bp
, TM_REG_TM_INT_MASK
, 0);
6837 REG_WR(bp
, XSDM_REG_XSDM_INT_MASK_0
, 0);
6838 REG_WR(bp
, XSDM_REG_XSDM_INT_MASK_1
, 0);
6839 REG_WR(bp
, XCM_REG_XCM_INT_MASK
, 0);
6840 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6841 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6842 REG_WR(bp
, USDM_REG_USDM_INT_MASK_0
, 0);
6843 REG_WR(bp
, USDM_REG_USDM_INT_MASK_1
, 0);
6844 REG_WR(bp
, UCM_REG_UCM_INT_MASK
, 0);
6845 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6846 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6847 REG_WR(bp
, GRCBASE_UPB
+ PB_REG_PB_INT_MASK
, 0);
6848 REG_WR(bp
, CSDM_REG_CSDM_INT_MASK_0
, 0);
6849 REG_WR(bp
, CSDM_REG_CSDM_INT_MASK_1
, 0);
6850 REG_WR(bp
, CCM_REG_CCM_INT_MASK
, 0);
6851 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6852 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6854 val
= PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
|
6855 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
|
6856 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
;
6857 if (!CHIP_IS_E1x(bp
))
6858 val
|= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
|
6859 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED
;
6860 REG_WR(bp
, PXP2_REG_PXP2_INT_MASK_0
, val
);
6862 REG_WR(bp
, TSDM_REG_TSDM_INT_MASK_0
, 0);
6863 REG_WR(bp
, TSDM_REG_TSDM_INT_MASK_1
, 0);
6864 REG_WR(bp
, TCM_REG_TCM_INT_MASK
, 0);
6865 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6867 if (!CHIP_IS_E1x(bp
))
6868 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6869 REG_WR(bp
, TSEM_REG_TSEM_INT_MASK_1
, 0x07ff);
6871 REG_WR(bp
, CDU_REG_CDU_INT_MASK
, 0);
6872 REG_WR(bp
, DMAE_REG_DMAE_INT_MASK
, 0);
6873 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6874 REG_WR(bp
, PBF_REG_PBF_INT_MASK
, 0x18); /* bit 3,4 masked */
6877 static void bnx2x_reset_common(struct bnx2x
*bp
)
6882 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
,
6885 if (CHIP_IS_E3(bp
)) {
6886 val
|= MISC_REGISTERS_RESET_REG_2_MSTAT0
;
6887 val
|= MISC_REGISTERS_RESET_REG_2_MSTAT1
;
6890 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
, val
);
6893 static void bnx2x_setup_dmae(struct bnx2x
*bp
)
6896 spin_lock_init(&bp
->dmae_lock
);
6899 static void bnx2x_init_pxp(struct bnx2x
*bp
)
6902 int r_order
, w_order
;
6904 pcie_capability_read_word(bp
->pdev
, PCI_EXP_DEVCTL
, &devctl
);
6905 DP(NETIF_MSG_HW
, "read 0x%x from devctl\n", devctl
);
6906 w_order
= ((devctl
& PCI_EXP_DEVCTL_PAYLOAD
) >> 5);
6908 r_order
= ((devctl
& PCI_EXP_DEVCTL_READRQ
) >> 12);
6910 DP(NETIF_MSG_HW
, "force read order to %d\n", bp
->mrrs
);
6914 bnx2x_init_pxp_arb(bp
, r_order
, w_order
);
6917 static void bnx2x_setup_fan_failure_detection(struct bnx2x
*bp
)
6927 val
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.config2
) &
6928 SHARED_HW_CFG_FAN_FAILURE_MASK
;
6930 if (val
== SHARED_HW_CFG_FAN_FAILURE_ENABLED
)
6934 * The fan failure mechanism is usually related to the PHY type since
6935 * the power consumption of the board is affected by the PHY. Currently,
6936 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6938 else if (val
== SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE
)
6939 for (port
= PORT_0
; port
< PORT_MAX
; port
++) {
6941 bnx2x_fan_failure_det_req(
6943 bp
->common
.shmem_base
,
6944 bp
->common
.shmem2_base
,
6948 DP(NETIF_MSG_HW
, "fan detection setting: %d\n", is_required
);
6950 if (is_required
== 0)
6953 /* Fan failure is indicated by SPIO 5 */
6954 bnx2x_set_spio(bp
, MISC_SPIO_SPIO5
, MISC_SPIO_INPUT_HI_Z
);
6956 /* set to active low mode */
6957 val
= REG_RD(bp
, MISC_REG_SPIO_INT
);
6958 val
|= (MISC_SPIO_SPIO5
<< MISC_SPIO_INT_OLD_SET_POS
);
6959 REG_WR(bp
, MISC_REG_SPIO_INT
, val
);
6961 /* enable interrupt to signal the IGU */
6962 val
= REG_RD(bp
, MISC_REG_SPIO_EVENT_EN
);
6963 val
|= MISC_SPIO_SPIO5
;
6964 REG_WR(bp
, MISC_REG_SPIO_EVENT_EN
, val
);
6967 void bnx2x_pf_disable(struct bnx2x
*bp
)
6969 u32 val
= REG_RD(bp
, IGU_REG_PF_CONFIGURATION
);
6970 val
&= ~IGU_PF_CONF_FUNC_EN
;
6972 REG_WR(bp
, IGU_REG_PF_CONFIGURATION
, val
);
6973 REG_WR(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
, 0);
6974 REG_WR(bp
, CFC_REG_WEAK_ENABLE_PF
, 0);
6977 static void bnx2x__common_init_phy(struct bnx2x
*bp
)
6979 u32 shmem_base
[2], shmem2_base
[2];
6980 /* Avoid common init in case MFW supports LFA */
6981 if (SHMEM2_RD(bp
, size
) >
6982 (u32
)offsetof(struct shmem2_region
, lfa_host_addr
[BP_PORT(bp
)]))
6984 shmem_base
[0] = bp
->common
.shmem_base
;
6985 shmem2_base
[0] = bp
->common
.shmem2_base
;
6986 if (!CHIP_IS_E1x(bp
)) {
6988 SHMEM2_RD(bp
, other_shmem_base_addr
);
6990 SHMEM2_RD(bp
, other_shmem2_base_addr
);
6992 bnx2x_acquire_phy_lock(bp
);
6993 bnx2x_common_init_phy(bp
, shmem_base
, shmem2_base
,
6994 bp
->common
.chip_id
);
6995 bnx2x_release_phy_lock(bp
);
6998 static void bnx2x_config_endianity(struct bnx2x
*bp
, u32 val
)
7000 REG_WR(bp
, PXP2_REG_RQ_QM_ENDIAN_M
, val
);
7001 REG_WR(bp
, PXP2_REG_RQ_TM_ENDIAN_M
, val
);
7002 REG_WR(bp
, PXP2_REG_RQ_SRC_ENDIAN_M
, val
);
7003 REG_WR(bp
, PXP2_REG_RQ_CDU_ENDIAN_M
, val
);
7004 REG_WR(bp
, PXP2_REG_RQ_DBG_ENDIAN_M
, val
);
7006 /* make sure this value is 0 */
7007 REG_WR(bp
, PXP2_REG_RQ_HC_ENDIAN_M
, 0);
7009 REG_WR(bp
, PXP2_REG_RD_QM_SWAP_MODE
, val
);
7010 REG_WR(bp
, PXP2_REG_RD_TM_SWAP_MODE
, val
);
7011 REG_WR(bp
, PXP2_REG_RD_SRC_SWAP_MODE
, val
);
7012 REG_WR(bp
, PXP2_REG_RD_CDURD_SWAP_MODE
, val
);
7015 static void bnx2x_set_endianity(struct bnx2x
*bp
)
7018 bnx2x_config_endianity(bp
, 1);
7020 bnx2x_config_endianity(bp
, 0);
7024 static void bnx2x_reset_endianity(struct bnx2x
*bp
)
7026 bnx2x_config_endianity(bp
, 0);
7030 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
7032 * @bp: driver handle
7034 static int bnx2x_init_hw_common(struct bnx2x
*bp
)
7038 DP(NETIF_MSG_HW
, "starting common init func %d\n", BP_ABS_FUNC(bp
));
7041 * take the RESET lock to protect undi_unload flow from accessing
7042 * registers while we're resetting the chip
7044 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RESET
);
7046 bnx2x_reset_common(bp
);
7047 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
, 0xffffffff);
7050 if (CHIP_IS_E3(bp
)) {
7051 val
|= MISC_REGISTERS_RESET_REG_2_MSTAT0
;
7052 val
|= MISC_REGISTERS_RESET_REG_2_MSTAT1
;
7054 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_SET
, val
);
7056 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RESET
);
7058 bnx2x_init_block(bp
, BLOCK_MISC
, PHASE_COMMON
);
7060 if (!CHIP_IS_E1x(bp
)) {
7064 * 4-port mode or 2-port mode we need to turn of master-enable
7065 * for everyone, after that, turn it back on for self.
7066 * so, we disregard multi-function or not, and always disable
7067 * for all functions on the given path, this means 0,2,4,6 for
7068 * path 0 and 1,3,5,7 for path 1
7070 for (abs_func_id
= BP_PATH(bp
);
7071 abs_func_id
< E2_FUNC_MAX
*2; abs_func_id
+= 2) {
7072 if (abs_func_id
== BP_ABS_FUNC(bp
)) {
7074 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
,
7079 bnx2x_pretend_func(bp
, abs_func_id
);
7080 /* clear pf enable */
7081 bnx2x_pf_disable(bp
);
7082 bnx2x_pretend_func(bp
, BP_ABS_FUNC(bp
));
7086 bnx2x_init_block(bp
, BLOCK_PXP
, PHASE_COMMON
);
7087 if (CHIP_IS_E1(bp
)) {
7088 /* enable HW interrupt from PXP on USDM overflow
7089 bit 16 on INT_MASK_0 */
7090 REG_WR(bp
, PXP_REG_PXP_INT_MASK_0
, 0);
7093 bnx2x_init_block(bp
, BLOCK_PXP2
, PHASE_COMMON
);
7095 bnx2x_set_endianity(bp
);
7096 bnx2x_ilt_init_page_size(bp
, INITOP_SET
);
7098 if (CHIP_REV_IS_FPGA(bp
) && CHIP_IS_E1H(bp
))
7099 REG_WR(bp
, PXP2_REG_PGL_TAGS_LIMIT
, 0x1);
7101 /* let the HW do it's magic ... */
7103 /* finish PXP init */
7104 val
= REG_RD(bp
, PXP2_REG_RQ_CFG_DONE
);
7106 BNX2X_ERR("PXP2 CFG failed\n");
7109 val
= REG_RD(bp
, PXP2_REG_RD_INIT_DONE
);
7111 BNX2X_ERR("PXP2 RD_INIT failed\n");
7115 /* Timers bug workaround E2 only. We need to set the entire ILT to
7116 * have entries with value "0" and valid bit on.
7117 * This needs to be done by the first PF that is loaded in a path
7118 * (i.e. common phase)
7120 if (!CHIP_IS_E1x(bp
)) {
7121 /* In E2 there is a bug in the timers block that can cause function 6 / 7
7122 * (i.e. vnic3) to start even if it is marked as "scan-off".
7123 * This occurs when a different function (func2,3) is being marked
7124 * as "scan-off". Real-life scenario for example: if a driver is being
7125 * load-unloaded while func6,7 are down. This will cause the timer to access
7126 * the ilt, translate to a logical address and send a request to read/write.
7127 * Since the ilt for the function that is down is not valid, this will cause
7128 * a translation error which is unrecoverable.
7129 * The Workaround is intended to make sure that when this happens nothing fatal
7130 * will occur. The workaround:
7131 * 1. First PF driver which loads on a path will:
7132 * a. After taking the chip out of reset, by using pretend,
7133 * it will write "0" to the following registers of
7135 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
7136 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
7137 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
7138 * And for itself it will write '1' to
7139 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
7140 * dmae-operations (writing to pram for example.)
7141 * note: can be done for only function 6,7 but cleaner this
7143 * b. Write zero+valid to the entire ILT.
7144 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
7145 * VNIC3 (of that port). The range allocated will be the
7146 * entire ILT. This is needed to prevent ILT range error.
7147 * 2. Any PF driver load flow:
7148 * a. ILT update with the physical addresses of the allocated
7150 * b. Wait 20msec. - note that this timeout is needed to make
7151 * sure there are no requests in one of the PXP internal
7152 * queues with "old" ILT addresses.
7153 * c. PF enable in the PGLC.
7154 * d. Clear the was_error of the PF in the PGLC. (could have
7155 * occurred while driver was down)
7156 * e. PF enable in the CFC (WEAK + STRONG)
7157 * f. Timers scan enable
7158 * 3. PF driver unload flow:
7159 * a. Clear the Timers scan_en.
7160 * b. Polling for scan_on=0 for that PF.
7161 * c. Clear the PF enable bit in the PXP.
7162 * d. Clear the PF enable in the CFC (WEAK + STRONG)
7163 * e. Write zero+valid to all ILT entries (The valid bit must
7165 * f. If this is VNIC 3 of a port then also init
7166 * first_timers_ilt_entry to zero and last_timers_ilt_entry
7167 * to the last entry in the ILT.
7170 * Currently the PF error in the PGLC is non recoverable.
7171 * In the future the there will be a recovery routine for this error.
7172 * Currently attention is masked.
7173 * Having an MCP lock on the load/unload process does not guarantee that
7174 * there is no Timer disable during Func6/7 enable. This is because the
7175 * Timers scan is currently being cleared by the MCP on FLR.
7176 * Step 2.d can be done only for PF6/7 and the driver can also check if
7177 * there is error before clearing it. But the flow above is simpler and
7179 * All ILT entries are written by zero+valid and not just PF6/7
7180 * ILT entries since in the future the ILT entries allocation for
7181 * PF-s might be dynamic.
7183 struct ilt_client_info ilt_cli
;
7184 struct bnx2x_ilt ilt
;
7185 memset(&ilt_cli
, 0, sizeof(struct ilt_client_info
));
7186 memset(&ilt
, 0, sizeof(struct bnx2x_ilt
));
7188 /* initialize dummy TM client */
7190 ilt_cli
.end
= ILT_NUM_PAGE_ENTRIES
- 1;
7191 ilt_cli
.client_num
= ILT_CLIENT_TM
;
7193 /* Step 1: set zeroes to all ilt page entries with valid bit on
7194 * Step 2: set the timers first/last ilt entry to point
7195 * to the entire range to prevent ILT range error for 3rd/4th
7196 * vnic (this code assumes existence of the vnic)
7198 * both steps performed by call to bnx2x_ilt_client_init_op()
7199 * with dummy TM client
7201 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
7202 * and his brother are split registers
7204 bnx2x_pretend_func(bp
, (BP_PATH(bp
) + 6));
7205 bnx2x_ilt_client_init_op_ilt(bp
, &ilt
, &ilt_cli
, INITOP_CLEAR
);
7206 bnx2x_pretend_func(bp
, BP_ABS_FUNC(bp
));
7208 REG_WR(bp
, PXP2_REG_RQ_DRAM_ALIGN
, BNX2X_PXP_DRAM_ALIGN
);
7209 REG_WR(bp
, PXP2_REG_RQ_DRAM_ALIGN_RD
, BNX2X_PXP_DRAM_ALIGN
);
7210 REG_WR(bp
, PXP2_REG_RQ_DRAM_ALIGN_SEL
, 1);
7213 REG_WR(bp
, PXP2_REG_RQ_DISABLE_INPUTS
, 0);
7214 REG_WR(bp
, PXP2_REG_RD_DISABLE_INPUTS
, 0);
7216 if (!CHIP_IS_E1x(bp
)) {
7217 int factor
= CHIP_REV_IS_EMUL(bp
) ? 1000 :
7218 (CHIP_REV_IS_FPGA(bp
) ? 400 : 0);
7219 bnx2x_init_block(bp
, BLOCK_PGLUE_B
, PHASE_COMMON
);
7221 bnx2x_init_block(bp
, BLOCK_ATC
, PHASE_COMMON
);
7223 /* let the HW do it's magic ... */
7226 val
= REG_RD(bp
, ATC_REG_ATC_INIT_DONE
);
7227 } while (factor
-- && (val
!= 1));
7230 BNX2X_ERR("ATC_INIT failed\n");
7235 bnx2x_init_block(bp
, BLOCK_DMAE
, PHASE_COMMON
);
7237 bnx2x_iov_init_dmae(bp
);
7239 /* clean the DMAE memory */
7241 bnx2x_init_fill(bp
, TSEM_REG_PRAM
, 0, 8, 1);
7243 bnx2x_init_block(bp
, BLOCK_TCM
, PHASE_COMMON
);
7245 bnx2x_init_block(bp
, BLOCK_UCM
, PHASE_COMMON
);
7247 bnx2x_init_block(bp
, BLOCK_CCM
, PHASE_COMMON
);
7249 bnx2x_init_block(bp
, BLOCK_XCM
, PHASE_COMMON
);
7251 bnx2x_read_dmae(bp
, XSEM_REG_PASSIVE_BUFFER
, 3);
7252 bnx2x_read_dmae(bp
, CSEM_REG_PASSIVE_BUFFER
, 3);
7253 bnx2x_read_dmae(bp
, TSEM_REG_PASSIVE_BUFFER
, 3);
7254 bnx2x_read_dmae(bp
, USEM_REG_PASSIVE_BUFFER
, 3);
7256 bnx2x_init_block(bp
, BLOCK_QM
, PHASE_COMMON
);
7258 /* QM queues pointers table */
7259 bnx2x_qm_init_ptr_table(bp
, bp
->qm_cid_count
, INITOP_SET
);
7261 /* soft reset pulse */
7262 REG_WR(bp
, QM_REG_SOFT_RESET
, 1);
7263 REG_WR(bp
, QM_REG_SOFT_RESET
, 0);
7265 if (CNIC_SUPPORT(bp
))
7266 bnx2x_init_block(bp
, BLOCK_TM
, PHASE_COMMON
);
7268 bnx2x_init_block(bp
, BLOCK_DORQ
, PHASE_COMMON
);
7270 if (!CHIP_REV_IS_SLOW(bp
))
7271 /* enable hw interrupt from doorbell Q */
7272 REG_WR(bp
, DORQ_REG_DORQ_INT_MASK
, 0);
7274 bnx2x_init_block(bp
, BLOCK_BRB1
, PHASE_COMMON
);
7276 bnx2x_init_block(bp
, BLOCK_PRS
, PHASE_COMMON
);
7277 REG_WR(bp
, PRS_REG_A_PRSU_20
, 0xf);
7279 if (!CHIP_IS_E1(bp
))
7280 REG_WR(bp
, PRS_REG_E1HOV_MODE
, bp
->path_has_ovlan
);
7282 if (!CHIP_IS_E1x(bp
) && !CHIP_IS_E3B0(bp
)) {
7283 if (IS_MF_AFEX(bp
)) {
7284 /* configure that VNTag and VLAN headers must be
7285 * received in afex mode
7287 REG_WR(bp
, PRS_REG_HDRS_AFTER_BASIC
, 0xE);
7288 REG_WR(bp
, PRS_REG_MUST_HAVE_HDRS
, 0xA);
7289 REG_WR(bp
, PRS_REG_HDRS_AFTER_TAG_0
, 0x6);
7290 REG_WR(bp
, PRS_REG_TAG_ETHERTYPE_0
, 0x8926);
7291 REG_WR(bp
, PRS_REG_TAG_LEN_0
, 0x4);
7293 /* Bit-map indicating which L2 hdrs may appear
7294 * after the basic Ethernet header
7296 REG_WR(bp
, PRS_REG_HDRS_AFTER_BASIC
,
7297 bp
->path_has_ovlan
? 7 : 6);
7301 bnx2x_init_block(bp
, BLOCK_TSDM
, PHASE_COMMON
);
7302 bnx2x_init_block(bp
, BLOCK_CSDM
, PHASE_COMMON
);
7303 bnx2x_init_block(bp
, BLOCK_USDM
, PHASE_COMMON
);
7304 bnx2x_init_block(bp
, BLOCK_XSDM
, PHASE_COMMON
);
7306 if (!CHIP_IS_E1x(bp
)) {
7307 /* reset VFC memories */
7308 REG_WR(bp
, TSEM_REG_FAST_MEMORY
+ VFC_REG_MEMORIES_RST
,
7309 VFC_MEMORIES_RST_REG_CAM_RST
|
7310 VFC_MEMORIES_RST_REG_RAM_RST
);
7311 REG_WR(bp
, XSEM_REG_FAST_MEMORY
+ VFC_REG_MEMORIES_RST
,
7312 VFC_MEMORIES_RST_REG_CAM_RST
|
7313 VFC_MEMORIES_RST_REG_RAM_RST
);
7318 bnx2x_init_block(bp
, BLOCK_TSEM
, PHASE_COMMON
);
7319 bnx2x_init_block(bp
, BLOCK_USEM
, PHASE_COMMON
);
7320 bnx2x_init_block(bp
, BLOCK_CSEM
, PHASE_COMMON
);
7321 bnx2x_init_block(bp
, BLOCK_XSEM
, PHASE_COMMON
);
7324 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
,
7326 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
,
7329 bnx2x_init_block(bp
, BLOCK_UPB
, PHASE_COMMON
);
7330 bnx2x_init_block(bp
, BLOCK_XPB
, PHASE_COMMON
);
7331 bnx2x_init_block(bp
, BLOCK_PBF
, PHASE_COMMON
);
7333 if (!CHIP_IS_E1x(bp
)) {
7334 if (IS_MF_AFEX(bp
)) {
7335 /* configure that VNTag and VLAN headers must be
7338 REG_WR(bp
, PBF_REG_HDRS_AFTER_BASIC
, 0xE);
7339 REG_WR(bp
, PBF_REG_MUST_HAVE_HDRS
, 0xA);
7340 REG_WR(bp
, PBF_REG_HDRS_AFTER_TAG_0
, 0x6);
7341 REG_WR(bp
, PBF_REG_TAG_ETHERTYPE_0
, 0x8926);
7342 REG_WR(bp
, PBF_REG_TAG_LEN_0
, 0x4);
7344 REG_WR(bp
, PBF_REG_HDRS_AFTER_BASIC
,
7345 bp
->path_has_ovlan
? 7 : 6);
7349 REG_WR(bp
, SRC_REG_SOFT_RST
, 1);
7351 bnx2x_init_block(bp
, BLOCK_SRC
, PHASE_COMMON
);
7353 if (CNIC_SUPPORT(bp
)) {
7354 REG_WR(bp
, SRC_REG_KEYSEARCH_0
, 0x63285672);
7355 REG_WR(bp
, SRC_REG_KEYSEARCH_1
, 0x24b8f2cc);
7356 REG_WR(bp
, SRC_REG_KEYSEARCH_2
, 0x223aef9b);
7357 REG_WR(bp
, SRC_REG_KEYSEARCH_3
, 0x26001e3a);
7358 REG_WR(bp
, SRC_REG_KEYSEARCH_4
, 0x7ae91116);
7359 REG_WR(bp
, SRC_REG_KEYSEARCH_5
, 0x5ce5230b);
7360 REG_WR(bp
, SRC_REG_KEYSEARCH_6
, 0x298d8adf);
7361 REG_WR(bp
, SRC_REG_KEYSEARCH_7
, 0x6eb0ff09);
7362 REG_WR(bp
, SRC_REG_KEYSEARCH_8
, 0x1830f82f);
7363 REG_WR(bp
, SRC_REG_KEYSEARCH_9
, 0x01e46be7);
7365 REG_WR(bp
, SRC_REG_SOFT_RST
, 0);
7367 if (sizeof(union cdu_context
) != 1024)
7368 /* we currently assume that a context is 1024 bytes */
7369 dev_alert(&bp
->pdev
->dev
,
7370 "please adjust the size of cdu_context(%ld)\n",
7371 (long)sizeof(union cdu_context
));
7373 bnx2x_init_block(bp
, BLOCK_CDU
, PHASE_COMMON
);
7374 val
= (4 << 24) + (0 << 12) + 1024;
7375 REG_WR(bp
, CDU_REG_CDU_GLOBAL_PARAMS
, val
);
7377 bnx2x_init_block(bp
, BLOCK_CFC
, PHASE_COMMON
);
7378 REG_WR(bp
, CFC_REG_INIT_REG
, 0x7FF);
7379 /* enable context validation interrupt from CFC */
7380 REG_WR(bp
, CFC_REG_CFC_INT_MASK
, 0);
7382 /* set the thresholds to prevent CFC/CDU race */
7383 REG_WR(bp
, CFC_REG_DEBUG0
, 0x20020000);
7385 bnx2x_init_block(bp
, BLOCK_HC
, PHASE_COMMON
);
7387 if (!CHIP_IS_E1x(bp
) && BP_NOMCP(bp
))
7388 REG_WR(bp
, IGU_REG_RESET_MEMORIES
, 0x36);
7390 bnx2x_init_block(bp
, BLOCK_IGU
, PHASE_COMMON
);
7391 bnx2x_init_block(bp
, BLOCK_MISC_AEU
, PHASE_COMMON
);
7393 /* Reset PCIE errors for debug */
7394 REG_WR(bp
, 0x2814, 0xffffffff);
7395 REG_WR(bp
, 0x3820, 0xffffffff);
7397 if (!CHIP_IS_E1x(bp
)) {
7398 REG_WR(bp
, PCICFG_OFFSET
+ PXPCS_TL_CONTROL_5
,
7399 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1
|
7400 PXPCS_TL_CONTROL_5_ERR_UNSPPORT
));
7401 REG_WR(bp
, PCICFG_OFFSET
+ PXPCS_TL_FUNC345_STAT
,
7402 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4
|
7403 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3
|
7404 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2
));
7405 REG_WR(bp
, PCICFG_OFFSET
+ PXPCS_TL_FUNC678_STAT
,
7406 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7
|
7407 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6
|
7408 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5
));
7411 bnx2x_init_block(bp
, BLOCK_NIG
, PHASE_COMMON
);
7412 if (!CHIP_IS_E1(bp
)) {
7413 /* in E3 this done in per-port section */
7414 if (!CHIP_IS_E3(bp
))
7415 REG_WR(bp
, NIG_REG_LLH_MF_MODE
, IS_MF(bp
));
7417 if (CHIP_IS_E1H(bp
))
7418 /* not applicable for E2 (and above ...) */
7419 REG_WR(bp
, NIG_REG_LLH_E1HOV_MODE
, IS_MF_SD(bp
));
7421 if (CHIP_REV_IS_SLOW(bp
))
7424 /* finish CFC init */
7425 val
= reg_poll(bp
, CFC_REG_LL_INIT_DONE
, 1, 100, 10);
7427 BNX2X_ERR("CFC LL_INIT failed\n");
7430 val
= reg_poll(bp
, CFC_REG_AC_INIT_DONE
, 1, 100, 10);
7432 BNX2X_ERR("CFC AC_INIT failed\n");
7435 val
= reg_poll(bp
, CFC_REG_CAM_INIT_DONE
, 1, 100, 10);
7437 BNX2X_ERR("CFC CAM_INIT failed\n");
7440 REG_WR(bp
, CFC_REG_DEBUG0
, 0);
7442 if (CHIP_IS_E1(bp
)) {
7443 /* read NIG statistic
7444 to see if this is our first up since powerup */
7445 bnx2x_read_dmae(bp
, NIG_REG_STAT2_BRB_OCTET
, 2);
7446 val
= *bnx2x_sp(bp
, wb_data
[0]);
7448 /* do internal memory self test */
7449 if ((val
== 0) && bnx2x_int_mem_test(bp
)) {
7450 BNX2X_ERR("internal mem self test failed\n");
7455 bnx2x_setup_fan_failure_detection(bp
);
7457 /* clear PXP2 attentions */
7458 REG_RD(bp
, PXP2_REG_PXP2_INT_STS_CLR_0
);
7460 bnx2x_enable_blocks_attention(bp
);
7461 bnx2x_enable_blocks_parity(bp
);
7463 if (!BP_NOMCP(bp
)) {
7464 if (CHIP_IS_E1x(bp
))
7465 bnx2x__common_init_phy(bp
);
7467 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
7469 if (SHMEM2_HAS(bp
, netproc_fw_ver
))
7470 SHMEM2_WR(bp
, netproc_fw_ver
, REG_RD(bp
, XSEM_REG_PRAM
));
7476 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7478 * @bp: driver handle
7480 static int bnx2x_init_hw_common_chip(struct bnx2x
*bp
)
7482 int rc
= bnx2x_init_hw_common(bp
);
7487 /* In E2 2-PORT mode, same ext phy is used for the two paths */
7489 bnx2x__common_init_phy(bp
);
7494 static int bnx2x_init_hw_port(struct bnx2x
*bp
)
7496 int port
= BP_PORT(bp
);
7497 int init_phase
= port
? PHASE_PORT1
: PHASE_PORT0
;
7501 DP(NETIF_MSG_HW
, "starting port init port %d\n", port
);
7503 REG_WR(bp
, NIG_REG_MASK_INTERRUPT_PORT0
+ port
*4, 0);
7505 bnx2x_init_block(bp
, BLOCK_MISC
, init_phase
);
7506 bnx2x_init_block(bp
, BLOCK_PXP
, init_phase
);
7507 bnx2x_init_block(bp
, BLOCK_PXP2
, init_phase
);
7509 /* Timers bug workaround: disables the pf_master bit in pglue at
7510 * common phase, we need to enable it here before any dmae access are
7511 * attempted. Therefore we manually added the enable-master to the
7512 * port phase (it also happens in the function phase)
7514 if (!CHIP_IS_E1x(bp
))
7515 REG_WR(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
, 1);
7517 bnx2x_init_block(bp
, BLOCK_ATC
, init_phase
);
7518 bnx2x_init_block(bp
, BLOCK_DMAE
, init_phase
);
7519 bnx2x_init_block(bp
, BLOCK_PGLUE_B
, init_phase
);
7520 bnx2x_init_block(bp
, BLOCK_QM
, init_phase
);
7522 bnx2x_init_block(bp
, BLOCK_TCM
, init_phase
);
7523 bnx2x_init_block(bp
, BLOCK_UCM
, init_phase
);
7524 bnx2x_init_block(bp
, BLOCK_CCM
, init_phase
);
7525 bnx2x_init_block(bp
, BLOCK_XCM
, init_phase
);
7527 /* QM cid (connection) count */
7528 bnx2x_qm_init_cid_count(bp
, bp
->qm_cid_count
, INITOP_SET
);
7530 if (CNIC_SUPPORT(bp
)) {
7531 bnx2x_init_block(bp
, BLOCK_TM
, init_phase
);
7532 REG_WR(bp
, TM_REG_LIN0_SCAN_TIME
+ port
*4, 20);
7533 REG_WR(bp
, TM_REG_LIN0_MAX_ACTIVE_CID
+ port
*4, 31);
7536 bnx2x_init_block(bp
, BLOCK_DORQ
, init_phase
);
7538 bnx2x_init_block(bp
, BLOCK_BRB1
, init_phase
);
7540 if (CHIP_IS_E1(bp
) || CHIP_IS_E1H(bp
)) {
7543 low
= ((bp
->flags
& ONE_PORT_FLAG
) ? 160 : 246);
7544 else if (bp
->dev
->mtu
> 4096) {
7545 if (bp
->flags
& ONE_PORT_FLAG
)
7549 /* (24*1024 + val*4)/256 */
7550 low
= 96 + (val
/64) +
7551 ((val
% 64) ? 1 : 0);
7554 low
= ((bp
->flags
& ONE_PORT_FLAG
) ? 80 : 160);
7555 high
= low
+ 56; /* 14*1024/256 */
7556 REG_WR(bp
, BRB1_REG_PAUSE_LOW_THRESHOLD_0
+ port
*4, low
);
7557 REG_WR(bp
, BRB1_REG_PAUSE_HIGH_THRESHOLD_0
+ port
*4, high
);
7560 if (CHIP_MODE_IS_4_PORT(bp
))
7561 REG_WR(bp
, (BP_PORT(bp
) ?
7562 BRB1_REG_MAC_GUARANTIED_1
:
7563 BRB1_REG_MAC_GUARANTIED_0
), 40);
7565 bnx2x_init_block(bp
, BLOCK_PRS
, init_phase
);
7566 if (CHIP_IS_E3B0(bp
)) {
7567 if (IS_MF_AFEX(bp
)) {
7568 /* configure headers for AFEX mode */
7569 REG_WR(bp
, BP_PORT(bp
) ?
7570 PRS_REG_HDRS_AFTER_BASIC_PORT_1
:
7571 PRS_REG_HDRS_AFTER_BASIC_PORT_0
, 0xE);
7572 REG_WR(bp
, BP_PORT(bp
) ?
7573 PRS_REG_HDRS_AFTER_TAG_0_PORT_1
:
7574 PRS_REG_HDRS_AFTER_TAG_0_PORT_0
, 0x6);
7575 REG_WR(bp
, BP_PORT(bp
) ?
7576 PRS_REG_MUST_HAVE_HDRS_PORT_1
:
7577 PRS_REG_MUST_HAVE_HDRS_PORT_0
, 0xA);
7579 /* Ovlan exists only if we are in multi-function +
7580 * switch-dependent mode, in switch-independent there
7581 * is no ovlan headers
7583 REG_WR(bp
, BP_PORT(bp
) ?
7584 PRS_REG_HDRS_AFTER_BASIC_PORT_1
:
7585 PRS_REG_HDRS_AFTER_BASIC_PORT_0
,
7586 (bp
->path_has_ovlan
? 7 : 6));
7590 bnx2x_init_block(bp
, BLOCK_TSDM
, init_phase
);
7591 bnx2x_init_block(bp
, BLOCK_CSDM
, init_phase
);
7592 bnx2x_init_block(bp
, BLOCK_USDM
, init_phase
);
7593 bnx2x_init_block(bp
, BLOCK_XSDM
, init_phase
);
7595 bnx2x_init_block(bp
, BLOCK_TSEM
, init_phase
);
7596 bnx2x_init_block(bp
, BLOCK_USEM
, init_phase
);
7597 bnx2x_init_block(bp
, BLOCK_CSEM
, init_phase
);
7598 bnx2x_init_block(bp
, BLOCK_XSEM
, init_phase
);
7600 bnx2x_init_block(bp
, BLOCK_UPB
, init_phase
);
7601 bnx2x_init_block(bp
, BLOCK_XPB
, init_phase
);
7603 bnx2x_init_block(bp
, BLOCK_PBF
, init_phase
);
7605 if (CHIP_IS_E1x(bp
)) {
7606 /* configure PBF to work without PAUSE mtu 9000 */
7607 REG_WR(bp
, PBF_REG_P0_PAUSE_ENABLE
+ port
*4, 0);
7609 /* update threshold */
7610 REG_WR(bp
, PBF_REG_P0_ARB_THRSH
+ port
*4, (9040/16));
7611 /* update init credit */
7612 REG_WR(bp
, PBF_REG_P0_INIT_CRD
+ port
*4, (9040/16) + 553 - 22);
7615 REG_WR(bp
, PBF_REG_INIT_P0
+ port
*4, 1);
7617 REG_WR(bp
, PBF_REG_INIT_P0
+ port
*4, 0);
7620 if (CNIC_SUPPORT(bp
))
7621 bnx2x_init_block(bp
, BLOCK_SRC
, init_phase
);
7623 bnx2x_init_block(bp
, BLOCK_CDU
, init_phase
);
7624 bnx2x_init_block(bp
, BLOCK_CFC
, init_phase
);
7626 if (CHIP_IS_E1(bp
)) {
7627 REG_WR(bp
, HC_REG_LEADING_EDGE_0
+ port
*8, 0);
7628 REG_WR(bp
, HC_REG_TRAILING_EDGE_0
+ port
*8, 0);
7630 bnx2x_init_block(bp
, BLOCK_HC
, init_phase
);
7632 bnx2x_init_block(bp
, BLOCK_IGU
, init_phase
);
7634 bnx2x_init_block(bp
, BLOCK_MISC_AEU
, init_phase
);
7635 /* init aeu_mask_attn_func_0/1:
7636 * - SF mode: bits 3-7 are masked. Only bits 0-2 are in use
7637 * - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
7638 * bits 4-7 are used for "per vn group attention" */
7639 val
= IS_MF(bp
) ? 0xF7 : 0x7;
7640 /* Enable DCBX attention for all but E1 */
7641 val
|= CHIP_IS_E1(bp
) ? 0 : 0x10;
7642 REG_WR(bp
, MISC_REG_AEU_MASK_ATTN_FUNC_0
+ port
*4, val
);
7644 /* SCPAD_PARITY should NOT trigger close the gates */
7645 reg
= port
? MISC_REG_AEU_ENABLE4_NIG_1
: MISC_REG_AEU_ENABLE4_NIG_0
;
7648 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY
);
7650 reg
= port
? MISC_REG_AEU_ENABLE4_PXP_1
: MISC_REG_AEU_ENABLE4_PXP_0
;
7653 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY
);
7655 bnx2x_init_block(bp
, BLOCK_NIG
, init_phase
);
7657 if (!CHIP_IS_E1x(bp
)) {
7658 /* Bit-map indicating which L2 hdrs may appear after the
7659 * basic Ethernet header
7662 REG_WR(bp
, BP_PORT(bp
) ?
7663 NIG_REG_P1_HDRS_AFTER_BASIC
:
7664 NIG_REG_P0_HDRS_AFTER_BASIC
, 0xE);
7666 REG_WR(bp
, BP_PORT(bp
) ?
7667 NIG_REG_P1_HDRS_AFTER_BASIC
:
7668 NIG_REG_P0_HDRS_AFTER_BASIC
,
7669 IS_MF_SD(bp
) ? 7 : 6);
7672 REG_WR(bp
, BP_PORT(bp
) ?
7673 NIG_REG_LLH1_MF_MODE
:
7674 NIG_REG_LLH_MF_MODE
, IS_MF(bp
));
7676 if (!CHIP_IS_E3(bp
))
7677 REG_WR(bp
, NIG_REG_XGXS_SERDES0_MODE_SEL
+ port
*4, 1);
7679 if (!CHIP_IS_E1(bp
)) {
7680 /* 0x2 disable mf_ov, 0x1 enable */
7681 REG_WR(bp
, NIG_REG_LLH0_BRB1_DRV_MASK_MF
+ port
*4,
7682 (IS_MF_SD(bp
) ? 0x1 : 0x2));
7684 if (!CHIP_IS_E1x(bp
)) {
7686 switch (bp
->mf_mode
) {
7687 case MULTI_FUNCTION_SD
:
7690 case MULTI_FUNCTION_SI
:
7691 case MULTI_FUNCTION_AFEX
:
7696 REG_WR(bp
, (BP_PORT(bp
) ? NIG_REG_LLH1_CLS_TYPE
:
7697 NIG_REG_LLH0_CLS_TYPE
), val
);
7700 REG_WR(bp
, NIG_REG_LLFC_ENABLE_0
+ port
*4, 0);
7701 REG_WR(bp
, NIG_REG_LLFC_OUT_EN_0
+ port
*4, 0);
7702 REG_WR(bp
, NIG_REG_PAUSE_ENABLE_0
+ port
*4, 1);
7706 /* If SPIO5 is set to generate interrupts, enable it for this port */
7707 val
= REG_RD(bp
, MISC_REG_SPIO_EVENT_EN
);
7708 if (val
& MISC_SPIO_SPIO5
) {
7709 u32 reg_addr
= (port
? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0
:
7710 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0
);
7711 val
= REG_RD(bp
, reg_addr
);
7712 val
|= AEU_INPUTS_ATTN_BITS_SPIO5
;
7713 REG_WR(bp
, reg_addr
, val
);
7719 static void bnx2x_ilt_wr(struct bnx2x
*bp
, u32 index
, dma_addr_t addr
)
7725 reg
= PXP2_REG_RQ_ONCHIP_AT
+ index
*8;
7727 reg
= PXP2_REG_RQ_ONCHIP_AT_B0
+ index
*8;
7729 wb_write
[0] = ONCHIP_ADDR1(addr
);
7730 wb_write
[1] = ONCHIP_ADDR2(addr
);
7731 REG_WR_DMAE(bp
, reg
, wb_write
, 2);
7734 void bnx2x_igu_clear_sb_gen(struct bnx2x
*bp
, u8 func
, u8 idu_sb_id
, bool is_pf
)
7736 u32 data
, ctl
, cnt
= 100;
7737 u32 igu_addr_data
= IGU_REG_COMMAND_REG_32LSB_DATA
;
7738 u32 igu_addr_ctl
= IGU_REG_COMMAND_REG_CTRL
;
7739 u32 igu_addr_ack
= IGU_REG_CSTORM_TYPE_0_SB_CLEANUP
+ (idu_sb_id
/32)*4;
7740 u32 sb_bit
= 1 << (idu_sb_id
%32);
7741 u32 func_encode
= func
| (is_pf
? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT
;
7742 u32 addr_encode
= IGU_CMD_E2_PROD_UPD_BASE
+ idu_sb_id
;
7744 /* Not supported in BC mode */
7745 if (CHIP_INT_MODE_IS_BC(bp
))
7748 data
= (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7749 << IGU_REGULAR_CLEANUP_TYPE_SHIFT
) |
7750 IGU_REGULAR_CLEANUP_SET
|
7751 IGU_REGULAR_BCLEANUP
;
7753 ctl
= addr_encode
<< IGU_CTRL_REG_ADDRESS_SHIFT
|
7754 func_encode
<< IGU_CTRL_REG_FID_SHIFT
|
7755 IGU_CTRL_CMD_TYPE_WR
<< IGU_CTRL_REG_TYPE_SHIFT
;
7757 DP(NETIF_MSG_HW
, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7758 data
, igu_addr_data
);
7759 REG_WR(bp
, igu_addr_data
, data
);
7762 DP(NETIF_MSG_HW
, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7764 REG_WR(bp
, igu_addr_ctl
, ctl
);
7768 /* wait for clean up to finish */
7769 while (!(REG_RD(bp
, igu_addr_ack
) & sb_bit
) && --cnt
)
7772 if (!(REG_RD(bp
, igu_addr_ack
) & sb_bit
)) {
7774 "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7775 idu_sb_id
, idu_sb_id
/32, idu_sb_id
%32, cnt
);
7779 static void bnx2x_igu_clear_sb(struct bnx2x
*bp
, u8 idu_sb_id
)
7781 bnx2x_igu_clear_sb_gen(bp
, BP_FUNC(bp
), idu_sb_id
, true /*PF*/);
7784 static void bnx2x_clear_func_ilt(struct bnx2x
*bp
, u32 func
)
7786 u32 i
, base
= FUNC_ILT_BASE(func
);
7787 for (i
= base
; i
< base
+ ILT_PER_FUNC
; i
++)
7788 bnx2x_ilt_wr(bp
, i
, 0);
7791 static void bnx2x_init_searcher(struct bnx2x
*bp
)
7793 int port
= BP_PORT(bp
);
7794 bnx2x_src_init_t2(bp
, bp
->t2
, bp
->t2_mapping
, SRC_CONN_NUM
);
7795 /* T1 hash bits value determines the T1 number of entries */
7796 REG_WR(bp
, SRC_REG_NUMBER_HASH_BITS0
+ port
*4, SRC_HASH_BITS
);
7799 static inline int bnx2x_func_switch_update(struct bnx2x
*bp
, int suspend
)
7802 struct bnx2x_func_state_params func_params
= {NULL
};
7803 struct bnx2x_func_switch_update_params
*switch_update_params
=
7804 &func_params
.params
.switch_update
;
7806 /* Prepare parameters for function state transitions */
7807 __set_bit(RAMROD_COMP_WAIT
, &func_params
.ramrod_flags
);
7808 __set_bit(RAMROD_RETRY
, &func_params
.ramrod_flags
);
7810 func_params
.f_obj
= &bp
->func_obj
;
7811 func_params
.cmd
= BNX2X_F_CMD_SWITCH_UPDATE
;
7813 /* Function parameters */
7814 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG
,
7815 &switch_update_params
->changes
);
7817 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND
,
7818 &switch_update_params
->changes
);
7820 rc
= bnx2x_func_state_change(bp
, &func_params
);
7825 static int bnx2x_reset_nic_mode(struct bnx2x
*bp
)
7827 int rc
, i
, port
= BP_PORT(bp
);
7828 int vlan_en
= 0, mac_en
[NUM_MACS
];
7830 /* Close input from network */
7831 if (bp
->mf_mode
== SINGLE_FUNCTION
) {
7832 bnx2x_set_rx_filter(&bp
->link_params
, 0);
7834 vlan_en
= REG_RD(bp
, port
? NIG_REG_LLH1_FUNC_EN
:
7835 NIG_REG_LLH0_FUNC_EN
);
7836 REG_WR(bp
, port
? NIG_REG_LLH1_FUNC_EN
:
7837 NIG_REG_LLH0_FUNC_EN
, 0);
7838 for (i
= 0; i
< NUM_MACS
; i
++) {
7839 mac_en
[i
] = REG_RD(bp
, port
?
7840 (NIG_REG_LLH1_FUNC_MEM_ENABLE
+
7842 (NIG_REG_LLH0_FUNC_MEM_ENABLE
+
7844 REG_WR(bp
, port
? (NIG_REG_LLH1_FUNC_MEM_ENABLE
+
7846 (NIG_REG_LLH0_FUNC_MEM_ENABLE
+ 4 * i
), 0);
7850 /* Close BMC to host */
7851 REG_WR(bp
, port
? NIG_REG_P0_TX_MNG_HOST_ENABLE
:
7852 NIG_REG_P1_TX_MNG_HOST_ENABLE
, 0);
7854 /* Suspend Tx switching to the PF. Completion of this ramrod
7855 * further guarantees that all the packets of that PF / child
7856 * VFs in BRB were processed by the Parser, so it is safe to
7857 * change the NIC_MODE register.
7859 rc
= bnx2x_func_switch_update(bp
, 1);
7861 BNX2X_ERR("Can't suspend tx-switching!\n");
7865 /* Change NIC_MODE register */
7866 REG_WR(bp
, PRS_REG_NIC_MODE
, 0);
7868 /* Open input from network */
7869 if (bp
->mf_mode
== SINGLE_FUNCTION
) {
7870 bnx2x_set_rx_filter(&bp
->link_params
, 1);
7872 REG_WR(bp
, port
? NIG_REG_LLH1_FUNC_EN
:
7873 NIG_REG_LLH0_FUNC_EN
, vlan_en
);
7874 for (i
= 0; i
< NUM_MACS
; i
++) {
7875 REG_WR(bp
, port
? (NIG_REG_LLH1_FUNC_MEM_ENABLE
+
7877 (NIG_REG_LLH0_FUNC_MEM_ENABLE
+ 4 * i
),
7882 /* Enable BMC to host */
7883 REG_WR(bp
, port
? NIG_REG_P0_TX_MNG_HOST_ENABLE
:
7884 NIG_REG_P1_TX_MNG_HOST_ENABLE
, 1);
7886 /* Resume Tx switching to the PF */
7887 rc
= bnx2x_func_switch_update(bp
, 0);
7889 BNX2X_ERR("Can't resume tx-switching!\n");
7893 DP(NETIF_MSG_IFUP
, "NIC MODE disabled\n");
7897 int bnx2x_init_hw_func_cnic(struct bnx2x
*bp
)
7901 bnx2x_ilt_init_op_cnic(bp
, INITOP_SET
);
7903 if (CONFIGURE_NIC_MODE(bp
)) {
7904 /* Configure searcher as part of function hw init */
7905 bnx2x_init_searcher(bp
);
7907 /* Reset NIC mode */
7908 rc
= bnx2x_reset_nic_mode(bp
);
7910 BNX2X_ERR("Can't change NIC mode!\n");
7917 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
7918 * and boot began, or when kdump kernel was loaded. Either case would invalidate
7919 * the addresses of the transaction, resulting in was-error bit set in the pci
7920 * causing all hw-to-host pcie transactions to timeout. If this happened we want
7921 * to clear the interrupt which detected this from the pglueb and the was done
7924 static void bnx2x_clean_pglue_errors(struct bnx2x
*bp
)
7926 if (!CHIP_IS_E1x(bp
))
7927 REG_WR(bp
, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR
,
7928 1 << BP_ABS_FUNC(bp
));
7931 static int bnx2x_init_hw_func(struct bnx2x
*bp
)
7933 int port
= BP_PORT(bp
);
7934 int func
= BP_FUNC(bp
);
7935 int init_phase
= PHASE_PF0
+ func
;
7936 struct bnx2x_ilt
*ilt
= BP_ILT(bp
);
7939 u32 main_mem_base
, main_mem_size
, main_mem_prty_clr
;
7940 int i
, main_mem_width
, rc
;
7942 DP(NETIF_MSG_HW
, "starting func init func %d\n", func
);
7944 /* FLR cleanup - hmmm */
7945 if (!CHIP_IS_E1x(bp
)) {
7946 rc
= bnx2x_pf_flr_clnup(bp
);
7953 /* set MSI reconfigure capability */
7954 if (bp
->common
.int_block
== INT_BLOCK_HC
) {
7955 addr
= (port
? HC_REG_CONFIG_1
: HC_REG_CONFIG_0
);
7956 val
= REG_RD(bp
, addr
);
7957 val
|= HC_CONFIG_0_REG_MSI_ATTN_EN_0
;
7958 REG_WR(bp
, addr
, val
);
7961 bnx2x_init_block(bp
, BLOCK_PXP
, init_phase
);
7962 bnx2x_init_block(bp
, BLOCK_PXP2
, init_phase
);
7965 cdu_ilt_start
= ilt
->clients
[ILT_CLIENT_CDU
].start
;
7968 cdu_ilt_start
+= BNX2X_FIRST_VF_CID
/ILT_PAGE_CIDS
;
7969 cdu_ilt_start
= bnx2x_iov_init_ilt(bp
, cdu_ilt_start
);
7971 /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7972 * those of the VFs, so start line should be reset
7974 cdu_ilt_start
= ilt
->clients
[ILT_CLIENT_CDU
].start
;
7975 for (i
= 0; i
< L2_ILT_LINES(bp
); i
++) {
7976 ilt
->lines
[cdu_ilt_start
+ i
].page
= bp
->context
[i
].vcxt
;
7977 ilt
->lines
[cdu_ilt_start
+ i
].page_mapping
=
7978 bp
->context
[i
].cxt_mapping
;
7979 ilt
->lines
[cdu_ilt_start
+ i
].size
= bp
->context
[i
].size
;
7982 bnx2x_ilt_init_op(bp
, INITOP_SET
);
7984 if (!CONFIGURE_NIC_MODE(bp
)) {
7985 bnx2x_init_searcher(bp
);
7986 REG_WR(bp
, PRS_REG_NIC_MODE
, 0);
7987 DP(NETIF_MSG_IFUP
, "NIC MODE disabled\n");
7990 REG_WR(bp
, PRS_REG_NIC_MODE
, 1);
7991 DP(NETIF_MSG_IFUP
, "NIC MODE configured\n");
7994 if (!CHIP_IS_E1x(bp
)) {
7995 u32 pf_conf
= IGU_PF_CONF_FUNC_EN
;
7997 /* Turn on a single ISR mode in IGU if driver is going to use
8000 if (!(bp
->flags
& USING_MSIX_FLAG
))
8001 pf_conf
|= IGU_PF_CONF_SINGLE_ISR_EN
;
8003 * Timers workaround bug: function init part.
8004 * Need to wait 20msec after initializing ILT,
8005 * needed to make sure there are no requests in
8006 * one of the PXP internal queues with "old" ILT addresses
8010 * Master enable - Due to WB DMAE writes performed before this
8011 * register is re-initialized as part of the regular function
8014 REG_WR(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
, 1);
8015 /* Enable the function in IGU */
8016 REG_WR(bp
, IGU_REG_PF_CONFIGURATION
, pf_conf
);
8021 bnx2x_init_block(bp
, BLOCK_PGLUE_B
, init_phase
);
8023 bnx2x_clean_pglue_errors(bp
);
8025 bnx2x_init_block(bp
, BLOCK_ATC
, init_phase
);
8026 bnx2x_init_block(bp
, BLOCK_DMAE
, init_phase
);
8027 bnx2x_init_block(bp
, BLOCK_NIG
, init_phase
);
8028 bnx2x_init_block(bp
, BLOCK_SRC
, init_phase
);
8029 bnx2x_init_block(bp
, BLOCK_MISC
, init_phase
);
8030 bnx2x_init_block(bp
, BLOCK_TCM
, init_phase
);
8031 bnx2x_init_block(bp
, BLOCK_UCM
, init_phase
);
8032 bnx2x_init_block(bp
, BLOCK_CCM
, init_phase
);
8033 bnx2x_init_block(bp
, BLOCK_XCM
, init_phase
);
8034 bnx2x_init_block(bp
, BLOCK_TSEM
, init_phase
);
8035 bnx2x_init_block(bp
, BLOCK_USEM
, init_phase
);
8036 bnx2x_init_block(bp
, BLOCK_CSEM
, init_phase
);
8037 bnx2x_init_block(bp
, BLOCK_XSEM
, init_phase
);
8039 if (!CHIP_IS_E1x(bp
))
8040 REG_WR(bp
, QM_REG_PF_EN
, 1);
8042 if (!CHIP_IS_E1x(bp
)) {
8043 REG_WR(bp
, TSEM_REG_VFPF_ERR_NUM
, BNX2X_MAX_NUM_OF_VFS
+ func
);
8044 REG_WR(bp
, USEM_REG_VFPF_ERR_NUM
, BNX2X_MAX_NUM_OF_VFS
+ func
);
8045 REG_WR(bp
, CSEM_REG_VFPF_ERR_NUM
, BNX2X_MAX_NUM_OF_VFS
+ func
);
8046 REG_WR(bp
, XSEM_REG_VFPF_ERR_NUM
, BNX2X_MAX_NUM_OF_VFS
+ func
);
8048 bnx2x_init_block(bp
, BLOCK_QM
, init_phase
);
8050 bnx2x_init_block(bp
, BLOCK_TM
, init_phase
);
8051 bnx2x_init_block(bp
, BLOCK_DORQ
, init_phase
);
8052 REG_WR(bp
, DORQ_REG_MODE_ACT
, 1); /* no dpm */
8054 bnx2x_iov_init_dq(bp
);
8056 bnx2x_init_block(bp
, BLOCK_BRB1
, init_phase
);
8057 bnx2x_init_block(bp
, BLOCK_PRS
, init_phase
);
8058 bnx2x_init_block(bp
, BLOCK_TSDM
, init_phase
);
8059 bnx2x_init_block(bp
, BLOCK_CSDM
, init_phase
);
8060 bnx2x_init_block(bp
, BLOCK_USDM
, init_phase
);
8061 bnx2x_init_block(bp
, BLOCK_XSDM
, init_phase
);
8062 bnx2x_init_block(bp
, BLOCK_UPB
, init_phase
);
8063 bnx2x_init_block(bp
, BLOCK_XPB
, init_phase
);
8064 bnx2x_init_block(bp
, BLOCK_PBF
, init_phase
);
8065 if (!CHIP_IS_E1x(bp
))
8066 REG_WR(bp
, PBF_REG_DISABLE_PF
, 0);
8068 bnx2x_init_block(bp
, BLOCK_CDU
, init_phase
);
8070 bnx2x_init_block(bp
, BLOCK_CFC
, init_phase
);
8072 if (!CHIP_IS_E1x(bp
))
8073 REG_WR(bp
, CFC_REG_WEAK_ENABLE_PF
, 1);
8076 if (!(IS_MF_UFP(bp
) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp
))) {
8077 REG_WR(bp
, NIG_REG_LLH0_FUNC_EN
+ port
* 8, 1);
8078 REG_WR(bp
, NIG_REG_LLH0_FUNC_VLAN_ID
+ port
* 8,
8083 bnx2x_init_block(bp
, BLOCK_MISC_AEU
, init_phase
);
8085 /* HC init per function */
8086 if (bp
->common
.int_block
== INT_BLOCK_HC
) {
8087 if (CHIP_IS_E1H(bp
)) {
8088 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_12
+ func
*4, 0);
8090 REG_WR(bp
, HC_REG_LEADING_EDGE_0
+ port
*8, 0);
8091 REG_WR(bp
, HC_REG_TRAILING_EDGE_0
+ port
*8, 0);
8093 bnx2x_init_block(bp
, BLOCK_HC
, init_phase
);
8096 int num_segs
, sb_idx
, prod_offset
;
8098 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_12
+ func
*4, 0);
8100 if (!CHIP_IS_E1x(bp
)) {
8101 REG_WR(bp
, IGU_REG_LEADING_EDGE_LATCH
, 0);
8102 REG_WR(bp
, IGU_REG_TRAILING_EDGE_LATCH
, 0);
8105 bnx2x_init_block(bp
, BLOCK_IGU
, init_phase
);
8107 if (!CHIP_IS_E1x(bp
)) {
8111 * E2 mode: address 0-135 match to the mapping memory;
8112 * 136 - PF0 default prod; 137 - PF1 default prod;
8113 * 138 - PF2 default prod; 139 - PF3 default prod;
8114 * 140 - PF0 attn prod; 141 - PF1 attn prod;
8115 * 142 - PF2 attn prod; 143 - PF3 attn prod;
8118 * E1.5 mode - In backward compatible mode;
8119 * for non default SB; each even line in the memory
8120 * holds the U producer and each odd line hold
8121 * the C producer. The first 128 producers are for
8122 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
8123 * producers are for the DSB for each PF.
8124 * Each PF has five segments: (the order inside each
8125 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
8126 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
8127 * 144-147 attn prods;
8129 /* non-default-status-blocks */
8130 num_segs
= CHIP_INT_MODE_IS_BC(bp
) ?
8131 IGU_BC_NDSB_NUM_SEGS
: IGU_NORM_NDSB_NUM_SEGS
;
8132 for (sb_idx
= 0; sb_idx
< bp
->igu_sb_cnt
; sb_idx
++) {
8133 prod_offset
= (bp
->igu_base_sb
+ sb_idx
) *
8136 for (i
= 0; i
< num_segs
; i
++) {
8137 addr
= IGU_REG_PROD_CONS_MEMORY
+
8138 (prod_offset
+ i
) * 4;
8139 REG_WR(bp
, addr
, 0);
8141 /* send consumer update with value 0 */
8142 bnx2x_ack_sb(bp
, bp
->igu_base_sb
+ sb_idx
,
8143 USTORM_ID
, 0, IGU_INT_NOP
, 1);
8144 bnx2x_igu_clear_sb(bp
,
8145 bp
->igu_base_sb
+ sb_idx
);
8148 /* default-status-blocks */
8149 num_segs
= CHIP_INT_MODE_IS_BC(bp
) ?
8150 IGU_BC_DSB_NUM_SEGS
: IGU_NORM_DSB_NUM_SEGS
;
8152 if (CHIP_MODE_IS_4_PORT(bp
))
8153 dsb_idx
= BP_FUNC(bp
);
8155 dsb_idx
= BP_VN(bp
);
8157 prod_offset
= (CHIP_INT_MODE_IS_BC(bp
) ?
8158 IGU_BC_BASE_DSB_PROD
+ dsb_idx
:
8159 IGU_NORM_BASE_DSB_PROD
+ dsb_idx
);
8162 * igu prods come in chunks of E1HVN_MAX (4) -
8163 * does not matters what is the current chip mode
8165 for (i
= 0; i
< (num_segs
* E1HVN_MAX
);
8167 addr
= IGU_REG_PROD_CONS_MEMORY
+
8168 (prod_offset
+ i
)*4;
8169 REG_WR(bp
, addr
, 0);
8171 /* send consumer update with 0 */
8172 if (CHIP_INT_MODE_IS_BC(bp
)) {
8173 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
8174 USTORM_ID
, 0, IGU_INT_NOP
, 1);
8175 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
8176 CSTORM_ID
, 0, IGU_INT_NOP
, 1);
8177 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
8178 XSTORM_ID
, 0, IGU_INT_NOP
, 1);
8179 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
8180 TSTORM_ID
, 0, IGU_INT_NOP
, 1);
8181 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
8182 ATTENTION_ID
, 0, IGU_INT_NOP
, 1);
8184 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
8185 USTORM_ID
, 0, IGU_INT_NOP
, 1);
8186 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
8187 ATTENTION_ID
, 0, IGU_INT_NOP
, 1);
8189 bnx2x_igu_clear_sb(bp
, bp
->igu_dsb_id
);
8191 /* !!! These should become driver const once
8192 rf-tool supports split-68 const */
8193 REG_WR(bp
, IGU_REG_SB_INT_BEFORE_MASK_LSB
, 0);
8194 REG_WR(bp
, IGU_REG_SB_INT_BEFORE_MASK_MSB
, 0);
8195 REG_WR(bp
, IGU_REG_SB_MASK_LSB
, 0);
8196 REG_WR(bp
, IGU_REG_SB_MASK_MSB
, 0);
8197 REG_WR(bp
, IGU_REG_PBA_STATUS_LSB
, 0);
8198 REG_WR(bp
, IGU_REG_PBA_STATUS_MSB
, 0);
8202 /* Reset PCIE errors for debug */
8203 REG_WR(bp
, 0x2114, 0xffffffff);
8204 REG_WR(bp
, 0x2120, 0xffffffff);
8206 if (CHIP_IS_E1x(bp
)) {
8207 main_mem_size
= HC_REG_MAIN_MEMORY_SIZE
/ 2; /*dwords*/
8208 main_mem_base
= HC_REG_MAIN_MEMORY
+
8209 BP_PORT(bp
) * (main_mem_size
* 4);
8210 main_mem_prty_clr
= HC_REG_HC_PRTY_STS_CLR
;
8213 val
= REG_RD(bp
, main_mem_prty_clr
);
8216 "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
8219 /* Clear "false" parity errors in MSI-X table */
8220 for (i
= main_mem_base
;
8221 i
< main_mem_base
+ main_mem_size
* 4;
8222 i
+= main_mem_width
) {
8223 bnx2x_read_dmae(bp
, i
, main_mem_width
/ 4);
8224 bnx2x_write_dmae(bp
, bnx2x_sp_mapping(bp
, wb_data
),
8225 i
, main_mem_width
/ 4);
8227 /* Clear HC parity attention */
8228 REG_RD(bp
, main_mem_prty_clr
);
8231 #ifdef BNX2X_STOP_ON_ERROR
8232 /* Enable STORMs SP logging */
8233 REG_WR8(bp
, BAR_USTRORM_INTMEM
+
8234 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp
)), 1);
8235 REG_WR8(bp
, BAR_TSTRORM_INTMEM
+
8236 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp
)), 1);
8237 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+
8238 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp
)), 1);
8239 REG_WR8(bp
, BAR_XSTRORM_INTMEM
+
8240 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp
)), 1);
8243 bnx2x_phy_probe(&bp
->link_params
);
8248 void bnx2x_free_mem_cnic(struct bnx2x
*bp
)
8250 bnx2x_ilt_mem_op_cnic(bp
, ILT_MEMOP_FREE
);
8252 if (!CHIP_IS_E1x(bp
))
8253 BNX2X_PCI_FREE(bp
->cnic_sb
.e2_sb
, bp
->cnic_sb_mapping
,
8254 sizeof(struct host_hc_status_block_e2
));
8256 BNX2X_PCI_FREE(bp
->cnic_sb
.e1x_sb
, bp
->cnic_sb_mapping
,
8257 sizeof(struct host_hc_status_block_e1x
));
8259 BNX2X_PCI_FREE(bp
->t2
, bp
->t2_mapping
, SRC_T2_SZ
);
8262 void bnx2x_free_mem(struct bnx2x
*bp
)
8266 BNX2X_PCI_FREE(bp
->fw_stats
, bp
->fw_stats_mapping
,
8267 bp
->fw_stats_data_sz
+ bp
->fw_stats_req_sz
);
8272 BNX2X_PCI_FREE(bp
->def_status_blk
, bp
->def_status_blk_mapping
,
8273 sizeof(struct host_sp_status_block
));
8275 BNX2X_PCI_FREE(bp
->slowpath
, bp
->slowpath_mapping
,
8276 sizeof(struct bnx2x_slowpath
));
8278 for (i
= 0; i
< L2_ILT_LINES(bp
); i
++)
8279 BNX2X_PCI_FREE(bp
->context
[i
].vcxt
, bp
->context
[i
].cxt_mapping
,
8280 bp
->context
[i
].size
);
8281 bnx2x_ilt_mem_op(bp
, ILT_MEMOP_FREE
);
8283 BNX2X_FREE(bp
->ilt
->lines
);
8285 BNX2X_PCI_FREE(bp
->spq
, bp
->spq_mapping
, BCM_PAGE_SIZE
);
8287 BNX2X_PCI_FREE(bp
->eq_ring
, bp
->eq_mapping
,
8288 BCM_PAGE_SIZE
* NUM_EQ_PAGES
);
8290 BNX2X_PCI_FREE(bp
->t2
, bp
->t2_mapping
, SRC_T2_SZ
);
8292 bnx2x_iov_free_mem(bp
);
8295 int bnx2x_alloc_mem_cnic(struct bnx2x
*bp
)
8297 if (!CHIP_IS_E1x(bp
)) {
8298 /* size = the status block + ramrod buffers */
8299 bp
->cnic_sb
.e2_sb
= BNX2X_PCI_ALLOC(&bp
->cnic_sb_mapping
,
8300 sizeof(struct host_hc_status_block_e2
));
8301 if (!bp
->cnic_sb
.e2_sb
)
8304 bp
->cnic_sb
.e1x_sb
= BNX2X_PCI_ALLOC(&bp
->cnic_sb_mapping
,
8305 sizeof(struct host_hc_status_block_e1x
));
8306 if (!bp
->cnic_sb
.e1x_sb
)
8310 if (CONFIGURE_NIC_MODE(bp
) && !bp
->t2
) {
8311 /* allocate searcher T2 table, as it wasn't allocated before */
8312 bp
->t2
= BNX2X_PCI_ALLOC(&bp
->t2_mapping
, SRC_T2_SZ
);
8317 /* write address to which L5 should insert its values */
8318 bp
->cnic_eth_dev
.addr_drv_info_to_mcp
=
8319 &bp
->slowpath
->drv_info_to_mcp
;
8321 if (bnx2x_ilt_mem_op_cnic(bp
, ILT_MEMOP_ALLOC
))
8327 bnx2x_free_mem_cnic(bp
);
8328 BNX2X_ERR("Can't allocate memory\n");
8332 int bnx2x_alloc_mem(struct bnx2x
*bp
)
8334 int i
, allocated
, context_size
;
8336 if (!CONFIGURE_NIC_MODE(bp
) && !bp
->t2
) {
8337 /* allocate searcher T2 table */
8338 bp
->t2
= BNX2X_PCI_ALLOC(&bp
->t2_mapping
, SRC_T2_SZ
);
8343 bp
->def_status_blk
= BNX2X_PCI_ALLOC(&bp
->def_status_blk_mapping
,
8344 sizeof(struct host_sp_status_block
));
8345 if (!bp
->def_status_blk
)
8348 bp
->slowpath
= BNX2X_PCI_ALLOC(&bp
->slowpath_mapping
,
8349 sizeof(struct bnx2x_slowpath
));
8353 /* Allocate memory for CDU context:
8354 * This memory is allocated separately and not in the generic ILT
8355 * functions because CDU differs in few aspects:
8356 * 1. There are multiple entities allocating memory for context -
8357 * 'regular' driver, CNIC and SRIOV driver. Each separately controls
8358 * its own ILT lines.
8359 * 2. Since CDU page-size is not a single 4KB page (which is the case
8360 * for the other ILT clients), to be efficient we want to support
8361 * allocation of sub-page-size in the last entry.
8362 * 3. Context pointers are used by the driver to pass to FW / update
8363 * the context (for the other ILT clients the pointers are used just to
8364 * free the memory during unload).
8366 context_size
= sizeof(union cdu_context
) * BNX2X_L2_CID_COUNT(bp
);
8368 for (i
= 0, allocated
= 0; allocated
< context_size
; i
++) {
8369 bp
->context
[i
].size
= min(CDU_ILT_PAGE_SZ
,
8370 (context_size
- allocated
));
8371 bp
->context
[i
].vcxt
= BNX2X_PCI_ALLOC(&bp
->context
[i
].cxt_mapping
,
8372 bp
->context
[i
].size
);
8373 if (!bp
->context
[i
].vcxt
)
8375 allocated
+= bp
->context
[i
].size
;
8377 bp
->ilt
->lines
= kcalloc(ILT_MAX_LINES
, sizeof(struct ilt_line
),
8379 if (!bp
->ilt
->lines
)
8382 if (bnx2x_ilt_mem_op(bp
, ILT_MEMOP_ALLOC
))
8385 if (bnx2x_iov_alloc_mem(bp
))
8388 /* Slow path ring */
8389 bp
->spq
= BNX2X_PCI_ALLOC(&bp
->spq_mapping
, BCM_PAGE_SIZE
);
8394 bp
->eq_ring
= BNX2X_PCI_ALLOC(&bp
->eq_mapping
,
8395 BCM_PAGE_SIZE
* NUM_EQ_PAGES
);
8403 BNX2X_ERR("Can't allocate memory\n");
8408 * Init service functions
8411 int bnx2x_set_mac_one(struct bnx2x
*bp
, u8
*mac
,
8412 struct bnx2x_vlan_mac_obj
*obj
, bool set
,
8413 int mac_type
, unsigned long *ramrod_flags
)
8416 struct bnx2x_vlan_mac_ramrod_params ramrod_param
;
8418 memset(&ramrod_param
, 0, sizeof(ramrod_param
));
8420 /* Fill general parameters */
8421 ramrod_param
.vlan_mac_obj
= obj
;
8422 ramrod_param
.ramrod_flags
= *ramrod_flags
;
8424 /* Fill a user request section if needed */
8425 if (!test_bit(RAMROD_CONT
, ramrod_flags
)) {
8426 memcpy(ramrod_param
.user_req
.u
.mac
.mac
, mac
, ETH_ALEN
);
8428 __set_bit(mac_type
, &ramrod_param
.user_req
.vlan_mac_flags
);
8430 /* Set the command: ADD or DEL */
8432 ramrod_param
.user_req
.cmd
= BNX2X_VLAN_MAC_ADD
;
8434 ramrod_param
.user_req
.cmd
= BNX2X_VLAN_MAC_DEL
;
8437 rc
= bnx2x_config_vlan_mac(bp
, &ramrod_param
);
8439 if (rc
== -EEXIST
) {
8440 DP(BNX2X_MSG_SP
, "Failed to schedule ADD operations: %d\n", rc
);
8441 /* do not treat adding same MAC as error */
8444 BNX2X_ERR("%s MAC failed\n", (set
? "Set" : "Del"));
8449 int bnx2x_set_vlan_one(struct bnx2x
*bp
, u16 vlan
,
8450 struct bnx2x_vlan_mac_obj
*obj
, bool set
,
8451 unsigned long *ramrod_flags
)
8454 struct bnx2x_vlan_mac_ramrod_params ramrod_param
;
8456 memset(&ramrod_param
, 0, sizeof(ramrod_param
));
8458 /* Fill general parameters */
8459 ramrod_param
.vlan_mac_obj
= obj
;
8460 ramrod_param
.ramrod_flags
= *ramrod_flags
;
8462 /* Fill a user request section if needed */
8463 if (!test_bit(RAMROD_CONT
, ramrod_flags
)) {
8464 ramrod_param
.user_req
.u
.vlan
.vlan
= vlan
;
8465 /* Set the command: ADD or DEL */
8467 ramrod_param
.user_req
.cmd
= BNX2X_VLAN_MAC_ADD
;
8469 ramrod_param
.user_req
.cmd
= BNX2X_VLAN_MAC_DEL
;
8472 rc
= bnx2x_config_vlan_mac(bp
, &ramrod_param
);
8474 if (rc
== -EEXIST
) {
8475 /* Do not treat adding same vlan as error. */
8476 DP(BNX2X_MSG_SP
, "Failed to schedule ADD operations: %d\n", rc
);
8478 } else if (rc
< 0) {
8479 BNX2X_ERR("%s VLAN failed\n", (set
? "Set" : "Del"));
8485 int bnx2x_del_all_macs(struct bnx2x
*bp
,
8486 struct bnx2x_vlan_mac_obj
*mac_obj
,
8487 int mac_type
, bool wait_for_comp
)
8490 unsigned long ramrod_flags
= 0, vlan_mac_flags
= 0;
8492 /* Wait for completion of requested */
8494 __set_bit(RAMROD_COMP_WAIT
, &ramrod_flags
);
8496 /* Set the mac type of addresses we want to clear */
8497 __set_bit(mac_type
, &vlan_mac_flags
);
8499 rc
= mac_obj
->delete_all(bp
, mac_obj
, &vlan_mac_flags
, &ramrod_flags
);
8501 BNX2X_ERR("Failed to delete MACs: %d\n", rc
);
8506 int bnx2x_set_eth_mac(struct bnx2x
*bp
, bool set
)
8509 unsigned long ramrod_flags
= 0;
8511 DP(NETIF_MSG_IFUP
, "Adding Eth MAC\n");
8512 __set_bit(RAMROD_COMP_WAIT
, &ramrod_flags
);
8513 return bnx2x_set_mac_one(bp
, bp
->dev
->dev_addr
,
8514 &bp
->sp_objs
->mac_obj
, set
,
8515 BNX2X_ETH_MAC
, &ramrod_flags
);
8517 return bnx2x_vfpf_config_mac(bp
, bp
->dev
->dev_addr
,
8518 bp
->fp
->index
, set
);
8522 int bnx2x_setup_leading(struct bnx2x
*bp
)
8525 return bnx2x_setup_queue(bp
, &bp
->fp
[0], true);
8527 return bnx2x_vfpf_setup_q(bp
, &bp
->fp
[0], true);
8531 * bnx2x_set_int_mode - configure interrupt mode
8533 * @bp: driver handle
8535 * In case of MSI-X it will also try to enable MSI-X.
8537 int bnx2x_set_int_mode(struct bnx2x
*bp
)
8541 if (IS_VF(bp
) && int_mode
!= BNX2X_INT_MODE_MSIX
) {
8542 BNX2X_ERR("VF not loaded since interrupt mode not msix\n");
8547 case BNX2X_INT_MODE_MSIX
:
8548 /* attempt to enable msix */
8549 rc
= bnx2x_enable_msix(bp
);
8555 /* vfs use only msix */
8556 if (rc
&& IS_VF(bp
))
8559 /* failed to enable multiple MSI-X */
8560 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
8562 1 + bp
->num_cnic_queues
);
8564 /* falling through... */
8565 case BNX2X_INT_MODE_MSI
:
8566 bnx2x_enable_msi(bp
);
8568 /* falling through... */
8569 case BNX2X_INT_MODE_INTX
:
8570 bp
->num_ethernet_queues
= 1;
8571 bp
->num_queues
= bp
->num_ethernet_queues
+ bp
->num_cnic_queues
;
8572 BNX2X_DEV_INFO("set number of queues to 1\n");
8575 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8581 /* must be called prior to any HW initializations */
8582 static inline u16
bnx2x_cid_ilt_lines(struct bnx2x
*bp
)
8585 return (BNX2X_FIRST_VF_CID
+ BNX2X_VF_CIDS
)/ILT_PAGE_CIDS
;
8586 return L2_ILT_LINES(bp
);
8589 void bnx2x_ilt_set_info(struct bnx2x
*bp
)
8591 struct ilt_client_info
*ilt_client
;
8592 struct bnx2x_ilt
*ilt
= BP_ILT(bp
);
8595 ilt
->start_line
= FUNC_ILT_BASE(BP_FUNC(bp
));
8596 DP(BNX2X_MSG_SP
, "ilt starts at line %d\n", ilt
->start_line
);
8599 ilt_client
= &ilt
->clients
[ILT_CLIENT_CDU
];
8600 ilt_client
->client_num
= ILT_CLIENT_CDU
;
8601 ilt_client
->page_size
= CDU_ILT_PAGE_SZ
;
8602 ilt_client
->flags
= ILT_CLIENT_SKIP_MEM
;
8603 ilt_client
->start
= line
;
8604 line
+= bnx2x_cid_ilt_lines(bp
);
8606 if (CNIC_SUPPORT(bp
))
8607 line
+= CNIC_ILT_LINES
;
8608 ilt_client
->end
= line
- 1;
8610 DP(NETIF_MSG_IFUP
, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8613 ilt_client
->page_size
,
8615 ilog2(ilt_client
->page_size
>> 12));
8618 if (QM_INIT(bp
->qm_cid_count
)) {
8619 ilt_client
= &ilt
->clients
[ILT_CLIENT_QM
];
8620 ilt_client
->client_num
= ILT_CLIENT_QM
;
8621 ilt_client
->page_size
= QM_ILT_PAGE_SZ
;
8622 ilt_client
->flags
= 0;
8623 ilt_client
->start
= line
;
8625 /* 4 bytes for each cid */
8626 line
+= DIV_ROUND_UP(bp
->qm_cid_count
* QM_QUEUES_PER_FUNC
* 4,
8629 ilt_client
->end
= line
- 1;
8632 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8635 ilt_client
->page_size
,
8637 ilog2(ilt_client
->page_size
>> 12));
8640 if (CNIC_SUPPORT(bp
)) {
8642 ilt_client
= &ilt
->clients
[ILT_CLIENT_SRC
];
8643 ilt_client
->client_num
= ILT_CLIENT_SRC
;
8644 ilt_client
->page_size
= SRC_ILT_PAGE_SZ
;
8645 ilt_client
->flags
= 0;
8646 ilt_client
->start
= line
;
8647 line
+= SRC_ILT_LINES
;
8648 ilt_client
->end
= line
- 1;
8651 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8654 ilt_client
->page_size
,
8656 ilog2(ilt_client
->page_size
>> 12));
8659 ilt_client
= &ilt
->clients
[ILT_CLIENT_TM
];
8660 ilt_client
->client_num
= ILT_CLIENT_TM
;
8661 ilt_client
->page_size
= TM_ILT_PAGE_SZ
;
8662 ilt_client
->flags
= 0;
8663 ilt_client
->start
= line
;
8664 line
+= TM_ILT_LINES
;
8665 ilt_client
->end
= line
- 1;
8668 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8671 ilt_client
->page_size
,
8673 ilog2(ilt_client
->page_size
>> 12));
8676 BUG_ON(line
> ILT_MAX_LINES
);
8680 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8682 * @bp: driver handle
8683 * @fp: pointer to fastpath
8684 * @init_params: pointer to parameters structure
8686 * parameters configured:
8687 * - HC configuration
8688 * - Queue's CDU context
8690 static void bnx2x_pf_q_prep_init(struct bnx2x
*bp
,
8691 struct bnx2x_fastpath
*fp
, struct bnx2x_queue_init_params
*init_params
)
8694 int cxt_index
, cxt_offset
;
8696 /* FCoE Queue uses Default SB, thus has no HC capabilities */
8697 if (!IS_FCOE_FP(fp
)) {
8698 __set_bit(BNX2X_Q_FLG_HC
, &init_params
->rx
.flags
);
8699 __set_bit(BNX2X_Q_FLG_HC
, &init_params
->tx
.flags
);
8701 /* If HC is supported, enable host coalescing in the transition
8704 __set_bit(BNX2X_Q_FLG_HC_EN
, &init_params
->rx
.flags
);
8705 __set_bit(BNX2X_Q_FLG_HC_EN
, &init_params
->tx
.flags
);
8708 init_params
->rx
.hc_rate
= bp
->rx_ticks
?
8709 (1000000 / bp
->rx_ticks
) : 0;
8710 init_params
->tx
.hc_rate
= bp
->tx_ticks
?
8711 (1000000 / bp
->tx_ticks
) : 0;
8714 init_params
->rx
.fw_sb_id
= init_params
->tx
.fw_sb_id
=
8718 * CQ index among the SB indices: FCoE clients uses the default
8719 * SB, therefore it's different.
8721 init_params
->rx
.sb_cq_index
= HC_INDEX_ETH_RX_CQ_CONS
;
8722 init_params
->tx
.sb_cq_index
= HC_INDEX_ETH_FIRST_TX_CQ_CONS
;
8725 /* set maximum number of COSs supported by this queue */
8726 init_params
->max_cos
= fp
->max_cos
;
8728 DP(NETIF_MSG_IFUP
, "fp: %d setting queue params max cos to: %d\n",
8729 fp
->index
, init_params
->max_cos
);
8731 /* set the context pointers queue object */
8732 for (cos
= FIRST_TX_COS_INDEX
; cos
< init_params
->max_cos
; cos
++) {
8733 cxt_index
= fp
->txdata_ptr
[cos
]->cid
/ ILT_PAGE_CIDS
;
8734 cxt_offset
= fp
->txdata_ptr
[cos
]->cid
- (cxt_index
*
8736 init_params
->cxts
[cos
] =
8737 &bp
->context
[cxt_index
].vcxt
[cxt_offset
].eth
;
8741 static int bnx2x_setup_tx_only(struct bnx2x
*bp
, struct bnx2x_fastpath
*fp
,
8742 struct bnx2x_queue_state_params
*q_params
,
8743 struct bnx2x_queue_setup_tx_only_params
*tx_only_params
,
8744 int tx_index
, bool leading
)
8746 memset(tx_only_params
, 0, sizeof(*tx_only_params
));
8748 /* Set the command */
8749 q_params
->cmd
= BNX2X_Q_CMD_SETUP_TX_ONLY
;
8751 /* Set tx-only QUEUE flags: don't zero statistics */
8752 tx_only_params
->flags
= bnx2x_get_common_flags(bp
, fp
, false);
8754 /* choose the index of the cid to send the slow path on */
8755 tx_only_params
->cid_index
= tx_index
;
8757 /* Set general TX_ONLY_SETUP parameters */
8758 bnx2x_pf_q_prep_general(bp
, fp
, &tx_only_params
->gen_params
, tx_index
);
8760 /* Set Tx TX_ONLY_SETUP parameters */
8761 bnx2x_pf_tx_q_prep(bp
, fp
, &tx_only_params
->txq_params
, tx_index
);
8764 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8765 tx_index
, q_params
->q_obj
->cids
[FIRST_TX_COS_INDEX
],
8766 q_params
->q_obj
->cids
[tx_index
], q_params
->q_obj
->cl_id
,
8767 tx_only_params
->gen_params
.spcl_id
, tx_only_params
->flags
);
8769 /* send the ramrod */
8770 return bnx2x_queue_state_change(bp
, q_params
);
8774 * bnx2x_setup_queue - setup queue
8776 * @bp: driver handle
8777 * @fp: pointer to fastpath
8778 * @leading: is leading
8780 * This function performs 2 steps in a Queue state machine
8781 * actually: 1) RESET->INIT 2) INIT->SETUP
8784 int bnx2x_setup_queue(struct bnx2x
*bp
, struct bnx2x_fastpath
*fp
,
8787 struct bnx2x_queue_state_params q_params
= {NULL
};
8788 struct bnx2x_queue_setup_params
*setup_params
=
8789 &q_params
.params
.setup
;
8790 struct bnx2x_queue_setup_tx_only_params
*tx_only_params
=
8791 &q_params
.params
.tx_only
;
8795 DP(NETIF_MSG_IFUP
, "setting up queue %d\n", fp
->index
);
8797 /* reset IGU state skip FCoE L2 queue */
8798 if (!IS_FCOE_FP(fp
))
8799 bnx2x_ack_sb(bp
, fp
->igu_sb_id
, USTORM_ID
, 0,
8802 q_params
.q_obj
= &bnx2x_sp_obj(bp
, fp
).q_obj
;
8803 /* We want to wait for completion in this context */
8804 __set_bit(RAMROD_COMP_WAIT
, &q_params
.ramrod_flags
);
8806 /* Prepare the INIT parameters */
8807 bnx2x_pf_q_prep_init(bp
, fp
, &q_params
.params
.init
);
8809 /* Set the command */
8810 q_params
.cmd
= BNX2X_Q_CMD_INIT
;
8812 /* Change the state to INIT */
8813 rc
= bnx2x_queue_state_change(bp
, &q_params
);
8815 BNX2X_ERR("Queue(%d) INIT failed\n", fp
->index
);
8819 DP(NETIF_MSG_IFUP
, "init complete\n");
8821 /* Now move the Queue to the SETUP state... */
8822 memset(setup_params
, 0, sizeof(*setup_params
));
8824 /* Set QUEUE flags */
8825 setup_params
->flags
= bnx2x_get_q_flags(bp
, fp
, leading
);
8827 /* Set general SETUP parameters */
8828 bnx2x_pf_q_prep_general(bp
, fp
, &setup_params
->gen_params
,
8829 FIRST_TX_COS_INDEX
);
8831 bnx2x_pf_rx_q_prep(bp
, fp
, &setup_params
->pause_params
,
8832 &setup_params
->rxq_params
);
8834 bnx2x_pf_tx_q_prep(bp
, fp
, &setup_params
->txq_params
,
8835 FIRST_TX_COS_INDEX
);
8837 /* Set the command */
8838 q_params
.cmd
= BNX2X_Q_CMD_SETUP
;
8841 bp
->fcoe_init
= true;
8843 /* Change the state to SETUP */
8844 rc
= bnx2x_queue_state_change(bp
, &q_params
);
8846 BNX2X_ERR("Queue(%d) SETUP failed\n", fp
->index
);
8850 /* loop through the relevant tx-only indices */
8851 for (tx_index
= FIRST_TX_ONLY_COS_INDEX
;
8852 tx_index
< fp
->max_cos
;
8855 /* prepare and send tx-only ramrod*/
8856 rc
= bnx2x_setup_tx_only(bp
, fp
, &q_params
,
8857 tx_only_params
, tx_index
, leading
);
8859 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8860 fp
->index
, tx_index
);
8868 static int bnx2x_stop_queue(struct bnx2x
*bp
, int index
)
8870 struct bnx2x_fastpath
*fp
= &bp
->fp
[index
];
8871 struct bnx2x_fp_txdata
*txdata
;
8872 struct bnx2x_queue_state_params q_params
= {NULL
};
8875 DP(NETIF_MSG_IFDOWN
, "stopping queue %d cid %d\n", index
, fp
->cid
);
8877 q_params
.q_obj
= &bnx2x_sp_obj(bp
, fp
).q_obj
;
8878 /* We want to wait for completion in this context */
8879 __set_bit(RAMROD_COMP_WAIT
, &q_params
.ramrod_flags
);
8881 /* close tx-only connections */
8882 for (tx_index
= FIRST_TX_ONLY_COS_INDEX
;
8883 tx_index
< fp
->max_cos
;
8886 /* ascertain this is a normal queue*/
8887 txdata
= fp
->txdata_ptr
[tx_index
];
8889 DP(NETIF_MSG_IFDOWN
, "stopping tx-only queue %d\n",
8892 /* send halt terminate on tx-only connection */
8893 q_params
.cmd
= BNX2X_Q_CMD_TERMINATE
;
8894 memset(&q_params
.params
.terminate
, 0,
8895 sizeof(q_params
.params
.terminate
));
8896 q_params
.params
.terminate
.cid_index
= tx_index
;
8898 rc
= bnx2x_queue_state_change(bp
, &q_params
);
8902 /* send halt terminate on tx-only connection */
8903 q_params
.cmd
= BNX2X_Q_CMD_CFC_DEL
;
8904 memset(&q_params
.params
.cfc_del
, 0,
8905 sizeof(q_params
.params
.cfc_del
));
8906 q_params
.params
.cfc_del
.cid_index
= tx_index
;
8907 rc
= bnx2x_queue_state_change(bp
, &q_params
);
8911 /* Stop the primary connection: */
8912 /* ...halt the connection */
8913 q_params
.cmd
= BNX2X_Q_CMD_HALT
;
8914 rc
= bnx2x_queue_state_change(bp
, &q_params
);
8918 /* ...terminate the connection */
8919 q_params
.cmd
= BNX2X_Q_CMD_TERMINATE
;
8920 memset(&q_params
.params
.terminate
, 0,
8921 sizeof(q_params
.params
.terminate
));
8922 q_params
.params
.terminate
.cid_index
= FIRST_TX_COS_INDEX
;
8923 rc
= bnx2x_queue_state_change(bp
, &q_params
);
8926 /* ...delete cfc entry */
8927 q_params
.cmd
= BNX2X_Q_CMD_CFC_DEL
;
8928 memset(&q_params
.params
.cfc_del
, 0,
8929 sizeof(q_params
.params
.cfc_del
));
8930 q_params
.params
.cfc_del
.cid_index
= FIRST_TX_COS_INDEX
;
8931 return bnx2x_queue_state_change(bp
, &q_params
);
8934 static void bnx2x_reset_func(struct bnx2x
*bp
)
8936 int port
= BP_PORT(bp
);
8937 int func
= BP_FUNC(bp
);
8940 /* Disable the function in the FW */
8941 REG_WR8(bp
, BAR_XSTRORM_INTMEM
+ XSTORM_FUNC_EN_OFFSET(func
), 0);
8942 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+ CSTORM_FUNC_EN_OFFSET(func
), 0);
8943 REG_WR8(bp
, BAR_TSTRORM_INTMEM
+ TSTORM_FUNC_EN_OFFSET(func
), 0);
8944 REG_WR8(bp
, BAR_USTRORM_INTMEM
+ USTORM_FUNC_EN_OFFSET(func
), 0);
8947 for_each_eth_queue(bp
, i
) {
8948 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
8949 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+
8950 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp
->fw_sb_id
),
8954 if (CNIC_LOADED(bp
))
8956 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+
8957 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8958 (bnx2x_cnic_fw_sb_id(bp
)), SB_DISABLED
);
8961 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+
8962 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func
),
8965 for (i
= 0; i
< XSTORM_SPQ_DATA_SIZE
/ 4; i
++)
8966 REG_WR(bp
, BAR_XSTRORM_INTMEM
+ XSTORM_SPQ_DATA_OFFSET(func
),
8970 if (bp
->common
.int_block
== INT_BLOCK_HC
) {
8971 REG_WR(bp
, HC_REG_LEADING_EDGE_0
+ port
*8, 0);
8972 REG_WR(bp
, HC_REG_TRAILING_EDGE_0
+ port
*8, 0);
8974 REG_WR(bp
, IGU_REG_LEADING_EDGE_LATCH
, 0);
8975 REG_WR(bp
, IGU_REG_TRAILING_EDGE_LATCH
, 0);
8978 if (CNIC_LOADED(bp
)) {
8979 /* Disable Timer scan */
8980 REG_WR(bp
, TM_REG_EN_LINEAR0_TIMER
+ port
*4, 0);
8982 * Wait for at least 10ms and up to 2 second for the timers
8985 for (i
= 0; i
< 200; i
++) {
8986 usleep_range(10000, 20000);
8987 if (!REG_RD(bp
, TM_REG_LIN0_SCAN_ON
+ port
*4))
8992 bnx2x_clear_func_ilt(bp
, func
);
8994 /* Timers workaround bug for E2: if this is vnic-3,
8995 * we need to set the entire ilt range for this timers.
8997 if (!CHIP_IS_E1x(bp
) && BP_VN(bp
) == 3) {
8998 struct ilt_client_info ilt_cli
;
8999 /* use dummy TM client */
9000 memset(&ilt_cli
, 0, sizeof(struct ilt_client_info
));
9002 ilt_cli
.end
= ILT_NUM_PAGE_ENTRIES
- 1;
9003 ilt_cli
.client_num
= ILT_CLIENT_TM
;
9005 bnx2x_ilt_boundry_init_op(bp
, &ilt_cli
, 0, INITOP_CLEAR
);
9008 /* this assumes that reset_port() called before reset_func()*/
9009 if (!CHIP_IS_E1x(bp
))
9010 bnx2x_pf_disable(bp
);
9015 static void bnx2x_reset_port(struct bnx2x
*bp
)
9017 int port
= BP_PORT(bp
);
9020 /* Reset physical Link */
9021 bnx2x__link_reset(bp
);
9023 REG_WR(bp
, NIG_REG_MASK_INTERRUPT_PORT0
+ port
*4, 0);
9025 /* Do not rcv packets to BRB */
9026 REG_WR(bp
, NIG_REG_LLH0_BRB1_DRV_MASK
+ port
*4, 0x0);
9027 /* Do not direct rcv packets that are not for MCP to the BRB */
9028 REG_WR(bp
, (port
? NIG_REG_LLH1_BRB1_NOT_MCP
:
9029 NIG_REG_LLH0_BRB1_NOT_MCP
), 0x0);
9032 REG_WR(bp
, MISC_REG_AEU_MASK_ATTN_FUNC_0
+ port
*4, 0);
9035 /* Check for BRB port occupancy */
9036 val
= REG_RD(bp
, BRB1_REG_PORT_NUM_OCC_BLOCKS_0
+ port
*4);
9038 DP(NETIF_MSG_IFDOWN
,
9039 "BRB1 is not empty %d blocks are occupied\n", val
);
9041 /* TODO: Close Doorbell port? */
9044 static int bnx2x_reset_hw(struct bnx2x
*bp
, u32 load_code
)
9046 struct bnx2x_func_state_params func_params
= {NULL
};
9048 /* Prepare parameters for function state transitions */
9049 __set_bit(RAMROD_COMP_WAIT
, &func_params
.ramrod_flags
);
9051 func_params
.f_obj
= &bp
->func_obj
;
9052 func_params
.cmd
= BNX2X_F_CMD_HW_RESET
;
9054 func_params
.params
.hw_init
.load_phase
= load_code
;
9056 return bnx2x_func_state_change(bp
, &func_params
);
9059 static int bnx2x_func_stop(struct bnx2x
*bp
)
9061 struct bnx2x_func_state_params func_params
= {NULL
};
9064 /* Prepare parameters for function state transitions */
9065 __set_bit(RAMROD_COMP_WAIT
, &func_params
.ramrod_flags
);
9066 func_params
.f_obj
= &bp
->func_obj
;
9067 func_params
.cmd
= BNX2X_F_CMD_STOP
;
9070 * Try to stop the function the 'good way'. If fails (in case
9071 * of a parity error during bnx2x_chip_cleanup()) and we are
9072 * not in a debug mode, perform a state transaction in order to
9073 * enable further HW_RESET transaction.
9075 rc
= bnx2x_func_state_change(bp
, &func_params
);
9077 #ifdef BNX2X_STOP_ON_ERROR
9080 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
9081 __set_bit(RAMROD_DRV_CLR_ONLY
, &func_params
.ramrod_flags
);
9082 return bnx2x_func_state_change(bp
, &func_params
);
9090 * bnx2x_send_unload_req - request unload mode from the MCP.
9092 * @bp: driver handle
9093 * @unload_mode: requested function's unload mode
9095 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
9097 u32
bnx2x_send_unload_req(struct bnx2x
*bp
, int unload_mode
)
9100 int port
= BP_PORT(bp
);
9102 /* Select the UNLOAD request mode */
9103 if (unload_mode
== UNLOAD_NORMAL
)
9104 reset_code
= DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS
;
9106 else if (bp
->flags
& NO_WOL_FLAG
)
9107 reset_code
= DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP
;
9110 u32 emac_base
= port
? GRCBASE_EMAC1
: GRCBASE_EMAC0
;
9111 u8
*mac_addr
= bp
->dev
->dev_addr
;
9112 struct pci_dev
*pdev
= bp
->pdev
;
9116 /* The mac address is written to entries 1-4 to
9117 * preserve entry 0 which is used by the PMF
9119 u8 entry
= (BP_VN(bp
) + 1)*8;
9121 val
= (mac_addr
[0] << 8) | mac_addr
[1];
9122 EMAC_WR(bp
, EMAC_REG_EMAC_MAC_MATCH
+ entry
, val
);
9124 val
= (mac_addr
[2] << 24) | (mac_addr
[3] << 16) |
9125 (mac_addr
[4] << 8) | mac_addr
[5];
9126 EMAC_WR(bp
, EMAC_REG_EMAC_MAC_MATCH
+ entry
+ 4, val
);
9128 /* Enable the PME and clear the status */
9129 pci_read_config_word(pdev
, pdev
->pm_cap
+ PCI_PM_CTRL
, &pmc
);
9130 pmc
|= PCI_PM_CTRL_PME_ENABLE
| PCI_PM_CTRL_PME_STATUS
;
9131 pci_write_config_word(pdev
, pdev
->pm_cap
+ PCI_PM_CTRL
, pmc
);
9133 reset_code
= DRV_MSG_CODE_UNLOAD_REQ_WOL_EN
;
9136 reset_code
= DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS
;
9138 /* Send the request to the MCP */
9140 reset_code
= bnx2x_fw_command(bp
, reset_code
, 0);
9142 int path
= BP_PATH(bp
);
9144 DP(NETIF_MSG_IFDOWN
, "NO MCP - load counts[%d] %d, %d, %d\n",
9145 path
, bnx2x_load_count
[path
][0], bnx2x_load_count
[path
][1],
9146 bnx2x_load_count
[path
][2]);
9147 bnx2x_load_count
[path
][0]--;
9148 bnx2x_load_count
[path
][1 + port
]--;
9149 DP(NETIF_MSG_IFDOWN
, "NO MCP - new load counts[%d] %d, %d, %d\n",
9150 path
, bnx2x_load_count
[path
][0], bnx2x_load_count
[path
][1],
9151 bnx2x_load_count
[path
][2]);
9152 if (bnx2x_load_count
[path
][0] == 0)
9153 reset_code
= FW_MSG_CODE_DRV_UNLOAD_COMMON
;
9154 else if (bnx2x_load_count
[path
][1 + port
] == 0)
9155 reset_code
= FW_MSG_CODE_DRV_UNLOAD_PORT
;
9157 reset_code
= FW_MSG_CODE_DRV_UNLOAD_FUNCTION
;
9164 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
9166 * @bp: driver handle
9167 * @keep_link: true iff link should be kept up
9169 void bnx2x_send_unload_done(struct bnx2x
*bp
, bool keep_link
)
9171 u32 reset_param
= keep_link
? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET
: 0;
9173 /* Report UNLOAD_DONE to MCP */
9175 bnx2x_fw_command(bp
, DRV_MSG_CODE_UNLOAD_DONE
, reset_param
);
9178 static int bnx2x_func_wait_started(struct bnx2x
*bp
)
9181 int msix
= (bp
->flags
& USING_MSIX_FLAG
) ? 1 : 0;
9187 * (assumption: No Attention from MCP at this stage)
9188 * PMF probably in the middle of TX disable/enable transaction
9189 * 1. Sync IRS for default SB
9190 * 2. Sync SP queue - this guarantees us that attention handling started
9191 * 3. Wait, that TX disable/enable transaction completes
9193 * 1+2 guarantee that if DCBx attention was scheduled it already changed
9194 * pending bit of transaction from STARTED-->TX_STOPPED, if we already
9195 * received completion for the transaction the state is TX_STOPPED.
9196 * State will return to STARTED after completion of TX_STOPPED-->STARTED
9200 /* make sure default SB ISR is done */
9202 synchronize_irq(bp
->msix_table
[0].vector
);
9204 synchronize_irq(bp
->pdev
->irq
);
9206 flush_workqueue(bnx2x_wq
);
9207 flush_workqueue(bnx2x_iov_wq
);
9209 while (bnx2x_func_get_state(bp
, &bp
->func_obj
) !=
9210 BNX2X_F_STATE_STARTED
&& tout
--)
9213 if (bnx2x_func_get_state(bp
, &bp
->func_obj
) !=
9214 BNX2X_F_STATE_STARTED
) {
9215 #ifdef BNX2X_STOP_ON_ERROR
9216 BNX2X_ERR("Wrong function state\n");
9220 * Failed to complete the transaction in a "good way"
9221 * Force both transactions with CLR bit
9223 struct bnx2x_func_state_params func_params
= {NULL
};
9225 DP(NETIF_MSG_IFDOWN
,
9226 "Hmmm... Unexpected function state! Forcing STARTED-->TX_STOPPED-->STARTED\n");
9228 func_params
.f_obj
= &bp
->func_obj
;
9229 __set_bit(RAMROD_DRV_CLR_ONLY
,
9230 &func_params
.ramrod_flags
);
9232 /* STARTED-->TX_ST0PPED */
9233 func_params
.cmd
= BNX2X_F_CMD_TX_STOP
;
9234 bnx2x_func_state_change(bp
, &func_params
);
9236 /* TX_ST0PPED-->STARTED */
9237 func_params
.cmd
= BNX2X_F_CMD_TX_START
;
9238 return bnx2x_func_state_change(bp
, &func_params
);
9245 static void bnx2x_disable_ptp(struct bnx2x
*bp
)
9247 int port
= BP_PORT(bp
);
9249 /* Disable sending PTP packets to host */
9250 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_TO_HOST
:
9251 NIG_REG_P0_LLH_PTP_TO_HOST
, 0x0);
9253 /* Reset PTP event detection rules */
9254 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_PARAM_MASK
:
9255 NIG_REG_P0_LLH_PTP_PARAM_MASK
, 0x7FF);
9256 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_RULE_MASK
:
9257 NIG_REG_P0_LLH_PTP_RULE_MASK
, 0x3FFF);
9258 REG_WR(bp
, port
? NIG_REG_P1_TLLH_PTP_PARAM_MASK
:
9259 NIG_REG_P0_TLLH_PTP_PARAM_MASK
, 0x7FF);
9260 REG_WR(bp
, port
? NIG_REG_P1_TLLH_PTP_RULE_MASK
:
9261 NIG_REG_P0_TLLH_PTP_RULE_MASK
, 0x3FFF);
9263 /* Disable the PTP feature */
9264 REG_WR(bp
, port
? NIG_REG_P1_PTP_EN
:
9265 NIG_REG_P0_PTP_EN
, 0x0);
9268 /* Called during unload, to stop PTP-related stuff */
9269 static void bnx2x_stop_ptp(struct bnx2x
*bp
)
9271 /* Cancel PTP work queue. Should be done after the Tx queues are
9272 * drained to prevent additional scheduling.
9274 cancel_work_sync(&bp
->ptp_task
);
9276 if (bp
->ptp_tx_skb
) {
9277 dev_kfree_skb_any(bp
->ptp_tx_skb
);
9278 bp
->ptp_tx_skb
= NULL
;
9281 /* Disable PTP in HW */
9282 bnx2x_disable_ptp(bp
);
9284 DP(BNX2X_MSG_PTP
, "PTP stop ended successfully\n");
9287 void bnx2x_chip_cleanup(struct bnx2x
*bp
, int unload_mode
, bool keep_link
)
9289 int port
= BP_PORT(bp
);
9292 struct bnx2x_mcast_ramrod_params rparam
= {NULL
};
9295 /* Wait until tx fastpath tasks complete */
9296 for_each_tx_queue(bp
, i
) {
9297 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
9299 for_each_cos_in_tx_queue(fp
, cos
)
9300 rc
= bnx2x_clean_tx_queue(bp
, fp
->txdata_ptr
[cos
]);
9301 #ifdef BNX2X_STOP_ON_ERROR
9307 /* Give HW time to discard old tx messages */
9308 usleep_range(1000, 2000);
9310 /* Clean all ETH MACs */
9311 rc
= bnx2x_del_all_macs(bp
, &bp
->sp_objs
[0].mac_obj
, BNX2X_ETH_MAC
,
9314 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc
);
9316 /* Clean up UC list */
9317 rc
= bnx2x_del_all_macs(bp
, &bp
->sp_objs
[0].mac_obj
, BNX2X_UC_LIST_MAC
,
9320 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
9324 if (!CHIP_IS_E1(bp
))
9325 REG_WR(bp
, NIG_REG_LLH0_FUNC_EN
+ port
*8, 0);
9327 /* Set "drop all" (stop Rx).
9328 * We need to take a netif_addr_lock() here in order to prevent
9329 * a race between the completion code and this code.
9331 netif_addr_lock_bh(bp
->dev
);
9332 /* Schedule the rx_mode command */
9333 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING
, &bp
->sp_state
))
9334 set_bit(BNX2X_FILTER_RX_MODE_SCHED
, &bp
->sp_state
);
9335 else if (bp
->slowpath
)
9336 bnx2x_set_storm_rx_mode(bp
);
9338 /* Cleanup multicast configuration */
9339 rparam
.mcast_obj
= &bp
->mcast_obj
;
9340 rc
= bnx2x_config_mcast(bp
, &rparam
, BNX2X_MCAST_CMD_DEL
);
9342 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc
);
9344 netif_addr_unlock_bh(bp
->dev
);
9346 bnx2x_iov_chip_cleanup(bp
);
9349 * Send the UNLOAD_REQUEST to the MCP. This will return if
9350 * this function should perform FUNC, PORT or COMMON HW
9353 reset_code
= bnx2x_send_unload_req(bp
, unload_mode
);
9356 * (assumption: No Attention from MCP at this stage)
9357 * PMF probably in the middle of TX disable/enable transaction
9359 rc
= bnx2x_func_wait_started(bp
);
9361 BNX2X_ERR("bnx2x_func_wait_started failed\n");
9362 #ifdef BNX2X_STOP_ON_ERROR
9367 /* Close multi and leading connections
9368 * Completions for ramrods are collected in a synchronous way
9370 for_each_eth_queue(bp
, i
)
9371 if (bnx2x_stop_queue(bp
, i
))
9372 #ifdef BNX2X_STOP_ON_ERROR
9378 if (CNIC_LOADED(bp
)) {
9379 for_each_cnic_queue(bp
, i
)
9380 if (bnx2x_stop_queue(bp
, i
))
9381 #ifdef BNX2X_STOP_ON_ERROR
9388 /* If SP settings didn't get completed so far - something
9389 * very wrong has happen.
9391 if (!bnx2x_wait_sp_comp(bp
, ~0x0UL
))
9392 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
9394 #ifndef BNX2X_STOP_ON_ERROR
9397 rc
= bnx2x_func_stop(bp
);
9399 BNX2X_ERR("Function stop failed!\n");
9400 #ifdef BNX2X_STOP_ON_ERROR
9405 /* stop_ptp should be after the Tx queues are drained to prevent
9406 * scheduling to the cancelled PTP work queue. It should also be after
9407 * function stop ramrod is sent, since as part of this ramrod FW access
9410 if (bp
->flags
& PTP_SUPPORTED
)
9413 /* Disable HW interrupts, NAPI */
9414 bnx2x_netif_stop(bp
, 1);
9415 /* Delete all NAPI objects */
9416 bnx2x_del_all_napi(bp
);
9417 if (CNIC_LOADED(bp
))
9418 bnx2x_del_all_napi_cnic(bp
);
9423 /* Reset the chip, unless PCI function is offline. If we reach this
9424 * point following a PCI error handling, it means device is really
9425 * in a bad state and we're about to remove it, so reset the chip
9426 * is not a good idea.
9428 if (!pci_channel_offline(bp
->pdev
)) {
9429 rc
= bnx2x_reset_hw(bp
, reset_code
);
9431 BNX2X_ERR("HW_RESET failed\n");
9434 /* Report UNLOAD_DONE to MCP */
9435 bnx2x_send_unload_done(bp
, keep_link
);
9438 void bnx2x_disable_close_the_gate(struct bnx2x
*bp
)
9442 DP(NETIF_MSG_IFDOWN
, "Disabling \"close the gates\"\n");
9444 if (CHIP_IS_E1(bp
)) {
9445 int port
= BP_PORT(bp
);
9446 u32 addr
= port
? MISC_REG_AEU_MASK_ATTN_FUNC_1
:
9447 MISC_REG_AEU_MASK_ATTN_FUNC_0
;
9449 val
= REG_RD(bp
, addr
);
9451 REG_WR(bp
, addr
, val
);
9453 val
= REG_RD(bp
, MISC_REG_AEU_GENERAL_MASK
);
9454 val
&= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK
|
9455 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK
);
9456 REG_WR(bp
, MISC_REG_AEU_GENERAL_MASK
, val
);
9460 /* Close gates #2, #3 and #4: */
9461 static void bnx2x_set_234_gates(struct bnx2x
*bp
, bool close
)
9465 /* Gates #2 and #4a are closed/opened for "not E1" only */
9466 if (!CHIP_IS_E1(bp
)) {
9468 REG_WR(bp
, PXP_REG_HST_DISCARD_DOORBELLS
, !!close
);
9470 REG_WR(bp
, PXP_REG_HST_DISCARD_INTERNAL_WRITES
, !!close
);
9474 if (CHIP_IS_E1x(bp
)) {
9475 /* Prevent interrupts from HC on both ports */
9476 val
= REG_RD(bp
, HC_REG_CONFIG_1
);
9477 REG_WR(bp
, HC_REG_CONFIG_1
,
9478 (!close
) ? (val
| HC_CONFIG_1_REG_BLOCK_DISABLE_1
) :
9479 (val
& ~(u32
)HC_CONFIG_1_REG_BLOCK_DISABLE_1
));
9481 val
= REG_RD(bp
, HC_REG_CONFIG_0
);
9482 REG_WR(bp
, HC_REG_CONFIG_0
,
9483 (!close
) ? (val
| HC_CONFIG_0_REG_BLOCK_DISABLE_0
) :
9484 (val
& ~(u32
)HC_CONFIG_0_REG_BLOCK_DISABLE_0
));
9486 /* Prevent incoming interrupts in IGU */
9487 val
= REG_RD(bp
, IGU_REG_BLOCK_CONFIGURATION
);
9489 REG_WR(bp
, IGU_REG_BLOCK_CONFIGURATION
,
9491 (val
| IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE
) :
9492 (val
& ~(u32
)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE
));
9495 DP(NETIF_MSG_HW
| NETIF_MSG_IFUP
, "%s gates #2, #3 and #4\n",
9496 close
? "closing" : "opening");
9500 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
9502 static void bnx2x_clp_reset_prep(struct bnx2x
*bp
, u32
*magic_val
)
9504 /* Do some magic... */
9505 u32 val
= MF_CFG_RD(bp
, shared_mf_config
.clp_mb
);
9506 *magic_val
= val
& SHARED_MF_CLP_MAGIC
;
9507 MF_CFG_WR(bp
, shared_mf_config
.clp_mb
, val
| SHARED_MF_CLP_MAGIC
);
9511 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
9513 * @bp: driver handle
9514 * @magic_val: old value of the `magic' bit.
9516 static void bnx2x_clp_reset_done(struct bnx2x
*bp
, u32 magic_val
)
9518 /* Restore the `magic' bit value... */
9519 u32 val
= MF_CFG_RD(bp
, shared_mf_config
.clp_mb
);
9520 MF_CFG_WR(bp
, shared_mf_config
.clp_mb
,
9521 (val
& (~SHARED_MF_CLP_MAGIC
)) | magic_val
);
9525 * bnx2x_reset_mcp_prep - prepare for MCP reset.
9527 * @bp: driver handle
9528 * @magic_val: old value of 'magic' bit.
9530 * Takes care of CLP configurations.
9532 static void bnx2x_reset_mcp_prep(struct bnx2x
*bp
, u32
*magic_val
)
9535 u32 validity_offset
;
9537 DP(NETIF_MSG_HW
| NETIF_MSG_IFUP
, "Starting\n");
9539 /* Set `magic' bit in order to save MF config */
9540 if (!CHIP_IS_E1(bp
))
9541 bnx2x_clp_reset_prep(bp
, magic_val
);
9543 /* Get shmem offset */
9544 shmem
= REG_RD(bp
, MISC_REG_SHARED_MEM_ADDR
);
9546 offsetof(struct shmem_region
, validity_map
[BP_PORT(bp
)]);
9548 /* Clear validity map flags */
9550 REG_WR(bp
, shmem
+ validity_offset
, 0);
9553 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
9554 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
9557 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
9559 * @bp: driver handle
9561 static void bnx2x_mcp_wait_one(struct bnx2x
*bp
)
9563 /* special handling for emulation and FPGA,
9564 wait 10 times longer */
9565 if (CHIP_REV_IS_SLOW(bp
))
9566 msleep(MCP_ONE_TIMEOUT
*10);
9568 msleep(MCP_ONE_TIMEOUT
);
9572 * initializes bp->common.shmem_base and waits for validity signature to appear
9574 static int bnx2x_init_shmem(struct bnx2x
*bp
)
9580 bp
->common
.shmem_base
= REG_RD(bp
, MISC_REG_SHARED_MEM_ADDR
);
9581 if (bp
->common
.shmem_base
) {
9582 val
= SHMEM_RD(bp
, validity_map
[BP_PORT(bp
)]);
9583 if (val
& SHR_MEM_VALIDITY_MB
)
9587 bnx2x_mcp_wait_one(bp
);
9589 } while (cnt
++ < (MCP_TIMEOUT
/ MCP_ONE_TIMEOUT
));
9591 BNX2X_ERR("BAD MCP validity signature\n");
9596 static int bnx2x_reset_mcp_comp(struct bnx2x
*bp
, u32 magic_val
)
9598 int rc
= bnx2x_init_shmem(bp
);
9600 /* Restore the `magic' bit value */
9601 if (!CHIP_IS_E1(bp
))
9602 bnx2x_clp_reset_done(bp
, magic_val
);
9607 static void bnx2x_pxp_prep(struct bnx2x
*bp
)
9609 if (!CHIP_IS_E1(bp
)) {
9610 REG_WR(bp
, PXP2_REG_RD_START_INIT
, 0);
9611 REG_WR(bp
, PXP2_REG_RQ_RBC_DONE
, 0);
9617 * Reset the whole chip except for:
9619 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9622 * - MISC (including AEU)
9626 static void bnx2x_process_kill_chip_reset(struct bnx2x
*bp
, bool global
)
9628 u32 not_reset_mask1
, reset_mask1
, not_reset_mask2
, reset_mask2
;
9629 u32 global_bits2
, stay_reset2
;
9632 * Bits that have to be set in reset_mask2 if we want to reset 'global'
9633 * (per chip) blocks.
9636 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU
|
9637 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE
;
9639 /* Don't reset the following blocks.
9640 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9641 * reset, as in 4 port device they might still be owned
9642 * by the MCP (there is only one leader per path).
9645 MISC_REGISTERS_RESET_REG_1_RST_HC
|
9646 MISC_REGISTERS_RESET_REG_1_RST_PXPV
|
9647 MISC_REGISTERS_RESET_REG_1_RST_PXP
;
9650 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO
|
9651 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE
|
9652 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE
|
9653 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE
|
9654 MISC_REGISTERS_RESET_REG_2_RST_RBCN
|
9655 MISC_REGISTERS_RESET_REG_2_RST_GRC
|
9656 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE
|
9657 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B
|
9658 MISC_REGISTERS_RESET_REG_2_RST_ATC
|
9659 MISC_REGISTERS_RESET_REG_2_PGLC
|
9660 MISC_REGISTERS_RESET_REG_2_RST_BMAC0
|
9661 MISC_REGISTERS_RESET_REG_2_RST_BMAC1
|
9662 MISC_REGISTERS_RESET_REG_2_RST_EMAC0
|
9663 MISC_REGISTERS_RESET_REG_2_RST_EMAC1
|
9664 MISC_REGISTERS_RESET_REG_2_UMAC0
|
9665 MISC_REGISTERS_RESET_REG_2_UMAC1
;
9668 * Keep the following blocks in reset:
9669 * - all xxMACs are handled by the bnx2x_link code.
9672 MISC_REGISTERS_RESET_REG_2_XMAC
|
9673 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT
;
9675 /* Full reset masks according to the chip */
9676 reset_mask1
= 0xffffffff;
9679 reset_mask2
= 0xffff;
9680 else if (CHIP_IS_E1H(bp
))
9681 reset_mask2
= 0x1ffff;
9682 else if (CHIP_IS_E2(bp
))
9683 reset_mask2
= 0xfffff;
9684 else /* CHIP_IS_E3 */
9685 reset_mask2
= 0x3ffffff;
9687 /* Don't reset global blocks unless we need to */
9689 reset_mask2
&= ~global_bits2
;
9692 * In case of attention in the QM, we need to reset PXP
9693 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9694 * because otherwise QM reset would release 'close the gates' shortly
9695 * before resetting the PXP, then the PSWRQ would send a write
9696 * request to PGLUE. Then when PXP is reset, PGLUE would try to
9697 * read the payload data from PSWWR, but PSWWR would not
9698 * respond. The write queue in PGLUE would stuck, dmae commands
9699 * would not return. Therefore it's important to reset the second
9700 * reset register (containing the
9701 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9702 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9705 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
,
9706 reset_mask2
& (~not_reset_mask2
));
9708 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
,
9709 reset_mask1
& (~not_reset_mask1
));
9714 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_SET
,
9715 reset_mask2
& (~stay_reset2
));
9720 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
, reset_mask1
);
9725 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9726 * It should get cleared in no more than 1s.
9728 * @bp: driver handle
9730 * It should get cleared in no more than 1s. Returns 0 if
9731 * pending writes bit gets cleared.
9733 static int bnx2x_er_poll_igu_vq(struct bnx2x
*bp
)
9739 pend_bits
= REG_RD(bp
, IGU_REG_PENDING_BITS_STATUS
);
9744 usleep_range(1000, 2000);
9745 } while (cnt
-- > 0);
9748 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9756 static int bnx2x_process_kill(struct bnx2x
*bp
, bool global
)
9760 u32 sr_cnt
, blk_cnt
, port_is_idle_0
, port_is_idle_1
, pgl_exp_rom2
;
9763 /* Empty the Tetris buffer, wait for 1s */
9765 sr_cnt
= REG_RD(bp
, PXP2_REG_RD_SR_CNT
);
9766 blk_cnt
= REG_RD(bp
, PXP2_REG_RD_BLK_CNT
);
9767 port_is_idle_0
= REG_RD(bp
, PXP2_REG_RD_PORT_IS_IDLE_0
);
9768 port_is_idle_1
= REG_RD(bp
, PXP2_REG_RD_PORT_IS_IDLE_1
);
9769 pgl_exp_rom2
= REG_RD(bp
, PXP2_REG_PGL_EXP_ROM2
);
9771 tags_63_32
= REG_RD(bp
, PGLUE_B_REG_TAGS_63_32
);
9773 if ((sr_cnt
== 0x7e) && (blk_cnt
== 0xa0) &&
9774 ((port_is_idle_0
& 0x1) == 0x1) &&
9775 ((port_is_idle_1
& 0x1) == 0x1) &&
9776 (pgl_exp_rom2
== 0xffffffff) &&
9777 (!CHIP_IS_E3(bp
) || (tags_63_32
== 0xffffffff)))
9779 usleep_range(1000, 2000);
9780 } while (cnt
-- > 0);
9783 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9784 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9785 sr_cnt
, blk_cnt
, port_is_idle_0
, port_is_idle_1
,
9792 /* Close gates #2, #3 and #4 */
9793 bnx2x_set_234_gates(bp
, true);
9795 /* Poll for IGU VQs for 57712 and newer chips */
9796 if (!CHIP_IS_E1x(bp
) && bnx2x_er_poll_igu_vq(bp
))
9799 /* TBD: Indicate that "process kill" is in progress to MCP */
9801 /* Clear "unprepared" bit */
9802 REG_WR(bp
, MISC_REG_UNPREPARED
, 0);
9805 /* Make sure all is written to the chip before the reset */
9808 /* Wait for 1ms to empty GLUE and PCI-E core queues,
9809 * PSWHST, GRC and PSWRD Tetris buffer.
9811 usleep_range(1000, 2000);
9813 /* Prepare to chip reset: */
9816 bnx2x_reset_mcp_prep(bp
, &val
);
9822 /* reset the chip */
9823 bnx2x_process_kill_chip_reset(bp
, global
);
9826 /* clear errors in PGB */
9827 if (!CHIP_IS_E1x(bp
))
9828 REG_WR(bp
, PGLUE_B_REG_LATCHED_ERRORS_CLR
, 0x7f);
9830 /* Recover after reset: */
9832 if (global
&& bnx2x_reset_mcp_comp(bp
, val
))
9835 /* TBD: Add resetting the NO_MCP mode DB here */
9837 /* Open the gates #2, #3 and #4 */
9838 bnx2x_set_234_gates(bp
, false);
9840 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9841 * reset state, re-enable attentions. */
9846 static int bnx2x_leader_reset(struct bnx2x
*bp
)
9849 bool global
= bnx2x_reset_is_global(bp
);
9852 /* if not going to reset MCP - load "fake" driver to reset HW while
9853 * driver is owner of the HW
9855 if (!global
&& !BP_NOMCP(bp
)) {
9856 load_code
= bnx2x_fw_command(bp
, DRV_MSG_CODE_LOAD_REQ
,
9857 DRV_MSG_CODE_LOAD_REQ_WITH_LFA
);
9859 BNX2X_ERR("MCP response failure, aborting\n");
9861 goto exit_leader_reset
;
9863 if ((load_code
!= FW_MSG_CODE_DRV_LOAD_COMMON_CHIP
) &&
9864 (load_code
!= FW_MSG_CODE_DRV_LOAD_COMMON
)) {
9865 BNX2X_ERR("MCP unexpected resp, aborting\n");
9867 goto exit_leader_reset2
;
9869 load_code
= bnx2x_fw_command(bp
, DRV_MSG_CODE_LOAD_DONE
, 0);
9871 BNX2X_ERR("MCP response failure, aborting\n");
9873 goto exit_leader_reset2
;
9877 /* Try to recover after the failure */
9878 if (bnx2x_process_kill(bp
, global
)) {
9879 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9882 goto exit_leader_reset2
;
9886 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9889 bnx2x_set_reset_done(bp
);
9891 bnx2x_clear_reset_global(bp
);
9894 /* unload "fake driver" if it was loaded */
9895 if (!global
&& !BP_NOMCP(bp
)) {
9896 bnx2x_fw_command(bp
, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP
, 0);
9897 bnx2x_fw_command(bp
, DRV_MSG_CODE_UNLOAD_DONE
, 0);
9901 bnx2x_release_leader_lock(bp
);
9906 static void bnx2x_recovery_failed(struct bnx2x
*bp
)
9908 netdev_err(bp
->dev
, "Recovery has failed. Power cycle is needed.\n");
9910 /* Disconnect this device */
9911 netif_device_detach(bp
->dev
);
9914 * Block ifup for all function on this engine until "process kill"
9917 bnx2x_set_reset_in_progress(bp
);
9919 /* Shut down the power */
9920 bnx2x_set_power_state(bp
, PCI_D3hot
);
9922 bp
->recovery_state
= BNX2X_RECOVERY_FAILED
;
9928 * Assumption: runs under rtnl lock. This together with the fact
9929 * that it's called only from bnx2x_sp_rtnl() ensure that it
9930 * will never be called when netif_running(bp->dev) is false.
9932 static void bnx2x_parity_recover(struct bnx2x
*bp
)
9934 bool global
= false;
9935 u32 error_recovered
, error_unrecovered
;
9938 DP(NETIF_MSG_HW
, "Handling parity\n");
9940 switch (bp
->recovery_state
) {
9941 case BNX2X_RECOVERY_INIT
:
9942 DP(NETIF_MSG_HW
, "State is BNX2X_RECOVERY_INIT\n");
9943 is_parity
= bnx2x_chk_parity_attn(bp
, &global
, false);
9944 WARN_ON(!is_parity
);
9946 /* Try to get a LEADER_LOCK HW lock */
9947 if (bnx2x_trylock_leader_lock(bp
)) {
9948 bnx2x_set_reset_in_progress(bp
);
9950 * Check if there is a global attention and if
9951 * there was a global attention, set the global
9956 bnx2x_set_reset_global(bp
);
9961 /* Stop the driver */
9962 /* If interface has been removed - break */
9963 if (bnx2x_nic_unload(bp
, UNLOAD_RECOVERY
, false))
9966 bp
->recovery_state
= BNX2X_RECOVERY_WAIT
;
9968 /* Ensure "is_leader", MCP command sequence and
9969 * "recovery_state" update values are seen on other
9975 case BNX2X_RECOVERY_WAIT
:
9976 DP(NETIF_MSG_HW
, "State is BNX2X_RECOVERY_WAIT\n");
9977 if (bp
->is_leader
) {
9978 int other_engine
= BP_PATH(bp
) ? 0 : 1;
9979 bool other_load_status
=
9980 bnx2x_get_load_status(bp
, other_engine
);
9982 bnx2x_get_load_status(bp
, BP_PATH(bp
));
9983 global
= bnx2x_reset_is_global(bp
);
9986 * In case of a parity in a global block, let
9987 * the first leader that performs a
9988 * leader_reset() reset the global blocks in
9989 * order to clear global attentions. Otherwise
9990 * the gates will remain closed for that
9994 (global
&& other_load_status
)) {
9995 /* Wait until all other functions get
9998 schedule_delayed_work(&bp
->sp_rtnl_task
,
10002 /* If all other functions got down -
10003 * try to bring the chip back to
10004 * normal. In any case it's an exit
10005 * point for a leader.
10007 if (bnx2x_leader_reset(bp
)) {
10008 bnx2x_recovery_failed(bp
);
10012 /* If we are here, means that the
10013 * leader has succeeded and doesn't
10014 * want to be a leader any more. Try
10015 * to continue as a none-leader.
10019 } else { /* non-leader */
10020 if (!bnx2x_reset_is_done(bp
, BP_PATH(bp
))) {
10021 /* Try to get a LEADER_LOCK HW lock as
10022 * long as a former leader may have
10023 * been unloaded by the user or
10024 * released a leadership by another
10027 if (bnx2x_trylock_leader_lock(bp
)) {
10028 /* I'm a leader now! Restart a
10035 schedule_delayed_work(&bp
->sp_rtnl_task
,
10041 * If there was a global attention, wait
10042 * for it to be cleared.
10044 if (bnx2x_reset_is_global(bp
)) {
10045 schedule_delayed_work(
10052 bp
->eth_stats
.recoverable_error
;
10053 error_unrecovered
=
10054 bp
->eth_stats
.unrecoverable_error
;
10055 bp
->recovery_state
=
10056 BNX2X_RECOVERY_NIC_LOADING
;
10057 if (bnx2x_nic_load(bp
, LOAD_NORMAL
)) {
10058 error_unrecovered
++;
10059 netdev_err(bp
->dev
,
10060 "Recovery failed. Power cycle needed\n");
10061 /* Disconnect this device */
10062 netif_device_detach(bp
->dev
);
10063 /* Shut down the power */
10064 bnx2x_set_power_state(
10068 bp
->recovery_state
=
10069 BNX2X_RECOVERY_DONE
;
10073 bp
->eth_stats
.recoverable_error
=
10075 bp
->eth_stats
.unrecoverable_error
=
10087 static int bnx2x_udp_port_update(struct bnx2x
*bp
)
10089 struct bnx2x_func_switch_update_params
*switch_update_params
;
10090 struct bnx2x_func_state_params func_params
= {NULL
};
10091 struct bnx2x_udp_tunnel
*udp_tunnel
;
10092 u16 vxlan_port
= 0, geneve_port
= 0;
10095 switch_update_params
= &func_params
.params
.switch_update
;
10097 /* Prepare parameters for function state transitions */
10098 __set_bit(RAMROD_COMP_WAIT
, &func_params
.ramrod_flags
);
10099 __set_bit(RAMROD_RETRY
, &func_params
.ramrod_flags
);
10101 func_params
.f_obj
= &bp
->func_obj
;
10102 func_params
.cmd
= BNX2X_F_CMD_SWITCH_UPDATE
;
10104 /* Function parameters */
10105 __set_bit(BNX2X_F_UPDATE_TUNNEL_CFG_CHNG
,
10106 &switch_update_params
->changes
);
10108 if (bp
->udp_tunnel_ports
[BNX2X_UDP_PORT_GENEVE
].count
) {
10109 udp_tunnel
= &bp
->udp_tunnel_ports
[BNX2X_UDP_PORT_GENEVE
];
10110 geneve_port
= udp_tunnel
->dst_port
;
10111 switch_update_params
->geneve_dst_port
= geneve_port
;
10114 if (bp
->udp_tunnel_ports
[BNX2X_UDP_PORT_VXLAN
].count
) {
10115 udp_tunnel
= &bp
->udp_tunnel_ports
[BNX2X_UDP_PORT_VXLAN
];
10116 vxlan_port
= udp_tunnel
->dst_port
;
10117 switch_update_params
->vxlan_dst_port
= vxlan_port
;
10120 /* Re-enable inner-rss for the offloaded UDP tunnels */
10121 __set_bit(BNX2X_F_UPDATE_TUNNEL_INNER_RSS
,
10122 &switch_update_params
->changes
);
10124 rc
= bnx2x_func_state_change(bp
, &func_params
);
10126 BNX2X_ERR("failed to set UDP dst port to %04x %04x (rc = 0x%x)\n",
10127 vxlan_port
, geneve_port
, rc
);
10130 "Configured UDP ports: Vxlan [%04x] Geneve [%04x]\n",
10131 vxlan_port
, geneve_port
);
10136 static void __bnx2x_add_udp_port(struct bnx2x
*bp
, u16 port
,
10137 enum bnx2x_udp_port_type type
)
10139 struct bnx2x_udp_tunnel
*udp_port
= &bp
->udp_tunnel_ports
[type
];
10141 if (!netif_running(bp
->dev
) || !IS_PF(bp
) || CHIP_IS_E1x(bp
))
10144 if (udp_port
->count
&& udp_port
->dst_port
== port
) {
10149 if (udp_port
->count
) {
10151 "UDP tunnel [%d] - destination port limit reached\n",
10156 udp_port
->dst_port
= port
;
10157 udp_port
->count
= 1;
10158 bnx2x_schedule_sp_rtnl(bp
, BNX2X_SP_RTNL_CHANGE_UDP_PORT
, 0);
10161 static void __bnx2x_del_udp_port(struct bnx2x
*bp
, u16 port
,
10162 enum bnx2x_udp_port_type type
)
10164 struct bnx2x_udp_tunnel
*udp_port
= &bp
->udp_tunnel_ports
[type
];
10166 if (!IS_PF(bp
) || CHIP_IS_E1x(bp
))
10169 if (!udp_port
->count
|| udp_port
->dst_port
!= port
) {
10170 DP(BNX2X_MSG_SP
, "Invalid UDP tunnel [%d] port\n",
10175 /* Remove reference, and make certain it's no longer in use */
10177 if (udp_port
->count
)
10179 udp_port
->dst_port
= 0;
10181 if (netif_running(bp
->dev
))
10182 bnx2x_schedule_sp_rtnl(bp
, BNX2X_SP_RTNL_CHANGE_UDP_PORT
, 0);
10184 DP(BNX2X_MSG_SP
, "Deleted UDP tunnel [%d] port %d\n",
10188 static void bnx2x_udp_tunnel_add(struct net_device
*netdev
,
10189 struct udp_tunnel_info
*ti
)
10191 struct bnx2x
*bp
= netdev_priv(netdev
);
10192 u16 t_port
= ntohs(ti
->port
);
10194 switch (ti
->type
) {
10195 case UDP_TUNNEL_TYPE_VXLAN
:
10196 __bnx2x_add_udp_port(bp
, t_port
, BNX2X_UDP_PORT_VXLAN
);
10198 case UDP_TUNNEL_TYPE_GENEVE
:
10199 __bnx2x_add_udp_port(bp
, t_port
, BNX2X_UDP_PORT_GENEVE
);
10206 static void bnx2x_udp_tunnel_del(struct net_device
*netdev
,
10207 struct udp_tunnel_info
*ti
)
10209 struct bnx2x
*bp
= netdev_priv(netdev
);
10210 u16 t_port
= ntohs(ti
->port
);
10212 switch (ti
->type
) {
10213 case UDP_TUNNEL_TYPE_VXLAN
:
10214 __bnx2x_del_udp_port(bp
, t_port
, BNX2X_UDP_PORT_VXLAN
);
10216 case UDP_TUNNEL_TYPE_GENEVE
:
10217 __bnx2x_del_udp_port(bp
, t_port
, BNX2X_UDP_PORT_GENEVE
);
10224 static int bnx2x_close(struct net_device
*dev
);
10226 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
10227 * scheduled on a general queue in order to prevent a dead lock.
10229 static void bnx2x_sp_rtnl_task(struct work_struct
*work
)
10231 struct bnx2x
*bp
= container_of(work
, struct bnx2x
, sp_rtnl_task
.work
);
10235 if (!netif_running(bp
->dev
)) {
10240 if (unlikely(bp
->recovery_state
!= BNX2X_RECOVERY_DONE
)) {
10241 #ifdef BNX2X_STOP_ON_ERROR
10242 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10243 "you will need to reboot when done\n");
10244 goto sp_rtnl_not_reset
;
10247 * Clear all pending SP commands as we are going to reset the
10250 bp
->sp_rtnl_state
= 0;
10253 bnx2x_parity_recover(bp
);
10259 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT
, &bp
->sp_rtnl_state
)) {
10260 #ifdef BNX2X_STOP_ON_ERROR
10261 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10262 "you will need to reboot when done\n");
10263 goto sp_rtnl_not_reset
;
10267 * Clear all pending SP commands as we are going to reset the
10270 bp
->sp_rtnl_state
= 0;
10273 bnx2x_nic_unload(bp
, UNLOAD_NORMAL
, true);
10274 /* When ret value shows failure of allocation failure,
10275 * the nic is rebooted again. If open still fails, a error
10276 * message to notify the user.
10278 if (bnx2x_nic_load(bp
, LOAD_NORMAL
) == -ENOMEM
) {
10279 bnx2x_nic_unload(bp
, UNLOAD_NORMAL
, true);
10280 if (bnx2x_nic_load(bp
, LOAD_NORMAL
))
10281 BNX2X_ERR("Open the NIC fails again!\n");
10286 #ifdef BNX2X_STOP_ON_ERROR
10289 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC
, &bp
->sp_rtnl_state
))
10290 bnx2x_setup_tc(bp
->dev
, bp
->dcbx_port_params
.ets
.num_of_cos
);
10291 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE
, &bp
->sp_rtnl_state
))
10292 bnx2x_after_function_update(bp
);
10294 * in case of fan failure we need to reset id if the "stop on error"
10295 * debug flag is set, since we trying to prevent permanent overheating
10298 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE
, &bp
->sp_rtnl_state
)) {
10299 DP(NETIF_MSG_HW
, "fan failure detected. Unloading driver\n");
10300 netif_device_detach(bp
->dev
);
10301 bnx2x_close(bp
->dev
);
10306 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST
, &bp
->sp_rtnl_state
)) {
10308 "sending set mcast vf pf channel message from rtnl sp-task\n");
10309 bnx2x_vfpf_set_mcast(bp
->dev
);
10311 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN
,
10312 &bp
->sp_rtnl_state
)){
10313 if (netif_carrier_ok(bp
->dev
)) {
10314 bnx2x_tx_disable(bp
);
10315 BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n");
10319 if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE
, &bp
->sp_rtnl_state
)) {
10320 DP(BNX2X_MSG_SP
, "Handling Rx Mode setting\n");
10321 bnx2x_set_rx_mode_inner(bp
);
10324 if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN
,
10325 &bp
->sp_rtnl_state
))
10326 bnx2x_pf_set_vfs_vlan(bp
);
10328 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP
, &bp
->sp_rtnl_state
)) {
10329 bnx2x_dcbx_stop_hw_tx(bp
);
10330 bnx2x_dcbx_resume_hw_tx(bp
);
10333 if (test_and_clear_bit(BNX2X_SP_RTNL_GET_DRV_VERSION
,
10334 &bp
->sp_rtnl_state
))
10335 bnx2x_update_mng_version(bp
);
10337 if (test_and_clear_bit(BNX2X_SP_RTNL_CHANGE_UDP_PORT
,
10338 &bp
->sp_rtnl_state
)) {
10339 if (bnx2x_udp_port_update(bp
)) {
10340 /* On error, forget configuration */
10341 memset(bp
->udp_tunnel_ports
, 0,
10342 sizeof(struct bnx2x_udp_tunnel
) *
10343 BNX2X_UDP_PORT_MAX
);
10345 /* Since we don't store additional port information,
10346 * if no ports are configured for any feature ask for
10347 * information about currently configured ports.
10349 if (!bp
->udp_tunnel_ports
[BNX2X_UDP_PORT_VXLAN
].count
&&
10350 !bp
->udp_tunnel_ports
[BNX2X_UDP_PORT_GENEVE
].count
)
10351 udp_tunnel_get_rx_info(bp
->dev
);
10355 /* work which needs rtnl lock not-taken (as it takes the lock itself and
10356 * can be called from other contexts as well)
10360 /* enable SR-IOV if applicable */
10361 if (IS_SRIOV(bp
) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV
,
10362 &bp
->sp_rtnl_state
)) {
10363 bnx2x_disable_sriov(bp
);
10364 bnx2x_enable_sriov(bp
);
10368 static void bnx2x_period_task(struct work_struct
*work
)
10370 struct bnx2x
*bp
= container_of(work
, struct bnx2x
, period_task
.work
);
10372 if (!netif_running(bp
->dev
))
10373 goto period_task_exit
;
10375 if (CHIP_REV_IS_SLOW(bp
)) {
10376 BNX2X_ERR("period task called on emulation, ignoring\n");
10377 goto period_task_exit
;
10380 bnx2x_acquire_phy_lock(bp
);
10382 * The barrier is needed to ensure the ordering between the writing to
10383 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
10384 * the reading here.
10387 if (bp
->port
.pmf
) {
10388 bnx2x_period_func(&bp
->link_params
, &bp
->link_vars
);
10390 /* Re-queue task in 1 sec */
10391 queue_delayed_work(bnx2x_wq
, &bp
->period_task
, 1*HZ
);
10394 bnx2x_release_phy_lock(bp
);
10400 * Init service functions
10403 static u32
bnx2x_get_pretend_reg(struct bnx2x
*bp
)
10405 u32 base
= PXP2_REG_PGL_PRETEND_FUNC_F0
;
10406 u32 stride
= PXP2_REG_PGL_PRETEND_FUNC_F1
- base
;
10407 return base
+ (BP_ABS_FUNC(bp
)) * stride
;
10410 static bool bnx2x_prev_unload_close_umac(struct bnx2x
*bp
,
10411 u8 port
, u32 reset_reg
,
10412 struct bnx2x_mac_vals
*vals
)
10414 u32 mask
= MISC_REGISTERS_RESET_REG_2_UMAC0
<< port
;
10417 if (!(mask
& reset_reg
))
10420 BNX2X_DEV_INFO("Disable umac Rx %02x\n", port
);
10421 base_addr
= port
? GRCBASE_UMAC1
: GRCBASE_UMAC0
;
10422 vals
->umac_addr
[port
] = base_addr
+ UMAC_REG_COMMAND_CONFIG
;
10423 vals
->umac_val
[port
] = REG_RD(bp
, vals
->umac_addr
[port
]);
10424 REG_WR(bp
, vals
->umac_addr
[port
], 0);
10429 static void bnx2x_prev_unload_close_mac(struct bnx2x
*bp
,
10430 struct bnx2x_mac_vals
*vals
)
10432 u32 val
, base_addr
, offset
, mask
, reset_reg
;
10433 bool mac_stopped
= false;
10434 u8 port
= BP_PORT(bp
);
10436 /* reset addresses as they also mark which values were changed */
10437 memset(vals
, 0, sizeof(*vals
));
10439 reset_reg
= REG_RD(bp
, MISC_REG_RESET_REG_2
);
10441 if (!CHIP_IS_E3(bp
)) {
10442 val
= REG_RD(bp
, NIG_REG_BMAC0_REGS_OUT_EN
+ port
* 4);
10443 mask
= MISC_REGISTERS_RESET_REG_2_RST_BMAC0
<< port
;
10444 if ((mask
& reset_reg
) && val
) {
10446 BNX2X_DEV_INFO("Disable bmac Rx\n");
10447 base_addr
= BP_PORT(bp
) ? NIG_REG_INGRESS_BMAC1_MEM
10448 : NIG_REG_INGRESS_BMAC0_MEM
;
10449 offset
= CHIP_IS_E2(bp
) ? BIGMAC2_REGISTER_BMAC_CONTROL
10450 : BIGMAC_REGISTER_BMAC_CONTROL
;
10453 * use rd/wr since we cannot use dmae. This is safe
10454 * since MCP won't access the bus due to the request
10455 * to unload, and no function on the path can be
10456 * loaded at this time.
10458 wb_data
[0] = REG_RD(bp
, base_addr
+ offset
);
10459 wb_data
[1] = REG_RD(bp
, base_addr
+ offset
+ 0x4);
10460 vals
->bmac_addr
= base_addr
+ offset
;
10461 vals
->bmac_val
[0] = wb_data
[0];
10462 vals
->bmac_val
[1] = wb_data
[1];
10463 wb_data
[0] &= ~BMAC_CONTROL_RX_ENABLE
;
10464 REG_WR(bp
, vals
->bmac_addr
, wb_data
[0]);
10465 REG_WR(bp
, vals
->bmac_addr
+ 0x4, wb_data
[1]);
10467 BNX2X_DEV_INFO("Disable emac Rx\n");
10468 vals
->emac_addr
= NIG_REG_NIG_EMAC0_EN
+ BP_PORT(bp
)*4;
10469 vals
->emac_val
= REG_RD(bp
, vals
->emac_addr
);
10470 REG_WR(bp
, vals
->emac_addr
, 0);
10471 mac_stopped
= true;
10473 if (reset_reg
& MISC_REGISTERS_RESET_REG_2_XMAC
) {
10474 BNX2X_DEV_INFO("Disable xmac Rx\n");
10475 base_addr
= BP_PORT(bp
) ? GRCBASE_XMAC1
: GRCBASE_XMAC0
;
10476 val
= REG_RD(bp
, base_addr
+ XMAC_REG_PFC_CTRL_HI
);
10477 REG_WR(bp
, base_addr
+ XMAC_REG_PFC_CTRL_HI
,
10479 REG_WR(bp
, base_addr
+ XMAC_REG_PFC_CTRL_HI
,
10481 vals
->xmac_addr
= base_addr
+ XMAC_REG_CTRL
;
10482 vals
->xmac_val
= REG_RD(bp
, vals
->xmac_addr
);
10483 REG_WR(bp
, vals
->xmac_addr
, 0);
10484 mac_stopped
= true;
10487 mac_stopped
|= bnx2x_prev_unload_close_umac(bp
, 0,
10489 mac_stopped
|= bnx2x_prev_unload_close_umac(bp
, 1,
10497 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
10498 #define BNX2X_PREV_UNDI_PROD_ADDR_H(f) (BAR_TSTRORM_INTMEM + \
10499 0x1848 + ((f) << 4))
10500 #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
10501 #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
10502 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
10504 #define BCM_5710_UNDI_FW_MF_MAJOR (0x07)
10505 #define BCM_5710_UNDI_FW_MF_MINOR (0x08)
10506 #define BCM_5710_UNDI_FW_MF_VERS (0x05)
10508 static bool bnx2x_prev_is_after_undi(struct bnx2x
*bp
)
10510 /* UNDI marks its presence in DORQ -
10511 * it initializes CID offset for normal bell to 0x7
10513 if (!(REG_RD(bp
, MISC_REG_RESET_REG_1
) &
10514 MISC_REGISTERS_RESET_REG_1_RST_DORQ
))
10517 if (REG_RD(bp
, DORQ_REG_NORM_CID_OFST
) == 0x7) {
10518 BNX2X_DEV_INFO("UNDI previously loaded\n");
10525 static void bnx2x_prev_unload_undi_inc(struct bnx2x
*bp
, u8 inc
)
10530 if (BP_FUNC(bp
) < 2)
10531 addr
= BNX2X_PREV_UNDI_PROD_ADDR(BP_PORT(bp
));
10533 addr
= BNX2X_PREV_UNDI_PROD_ADDR_H(BP_FUNC(bp
) - 2);
10535 tmp_reg
= REG_RD(bp
, addr
);
10536 rcq
= BNX2X_PREV_UNDI_RCQ(tmp_reg
) + inc
;
10537 bd
= BNX2X_PREV_UNDI_BD(tmp_reg
) + inc
;
10539 tmp_reg
= BNX2X_PREV_UNDI_PROD(rcq
, bd
);
10540 REG_WR(bp
, addr
, tmp_reg
);
10542 BNX2X_DEV_INFO("UNDI producer [%d/%d][%08x] rings bd -> 0x%04x, rcq -> 0x%04x\n",
10543 BP_PORT(bp
), BP_FUNC(bp
), addr
, bd
, rcq
);
10546 static int bnx2x_prev_mcp_done(struct bnx2x
*bp
)
10548 u32 rc
= bnx2x_fw_command(bp
, DRV_MSG_CODE_UNLOAD_DONE
,
10549 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET
);
10551 BNX2X_ERR("MCP response failure, aborting\n");
10558 static struct bnx2x_prev_path_list
*
10559 bnx2x_prev_path_get_entry(struct bnx2x
*bp
)
10561 struct bnx2x_prev_path_list
*tmp_list
;
10563 list_for_each_entry(tmp_list
, &bnx2x_prev_list
, list
)
10564 if (PCI_SLOT(bp
->pdev
->devfn
) == tmp_list
->slot
&&
10565 bp
->pdev
->bus
->number
== tmp_list
->bus
&&
10566 BP_PATH(bp
) == tmp_list
->path
)
10572 static int bnx2x_prev_path_mark_eeh(struct bnx2x
*bp
)
10574 struct bnx2x_prev_path_list
*tmp_list
;
10577 rc
= down_interruptible(&bnx2x_prev_sem
);
10579 BNX2X_ERR("Received %d when tried to take lock\n", rc
);
10583 tmp_list
= bnx2x_prev_path_get_entry(bp
);
10588 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
10592 up(&bnx2x_prev_sem
);
10597 static bool bnx2x_prev_is_path_marked(struct bnx2x
*bp
)
10599 struct bnx2x_prev_path_list
*tmp_list
;
10602 if (down_trylock(&bnx2x_prev_sem
))
10605 tmp_list
= bnx2x_prev_path_get_entry(bp
);
10607 if (tmp_list
->aer
) {
10608 DP(NETIF_MSG_HW
, "Path %d was marked by AER\n",
10612 BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
10617 up(&bnx2x_prev_sem
);
10622 bool bnx2x_port_after_undi(struct bnx2x
*bp
)
10624 struct bnx2x_prev_path_list
*entry
;
10627 down(&bnx2x_prev_sem
);
10629 entry
= bnx2x_prev_path_get_entry(bp
);
10630 val
= !!(entry
&& (entry
->undi
& (1 << BP_PORT(bp
))));
10632 up(&bnx2x_prev_sem
);
10637 static int bnx2x_prev_mark_path(struct bnx2x
*bp
, bool after_undi
)
10639 struct bnx2x_prev_path_list
*tmp_list
;
10642 rc
= down_interruptible(&bnx2x_prev_sem
);
10644 BNX2X_ERR("Received %d when tried to take lock\n", rc
);
10648 /* Check whether the entry for this path already exists */
10649 tmp_list
= bnx2x_prev_path_get_entry(bp
);
10651 if (!tmp_list
->aer
) {
10652 BNX2X_ERR("Re-Marking the path.\n");
10654 DP(NETIF_MSG_HW
, "Removing AER indication from path %d\n",
10658 up(&bnx2x_prev_sem
);
10661 up(&bnx2x_prev_sem
);
10663 /* Create an entry for this path and add it */
10664 tmp_list
= kmalloc(sizeof(struct bnx2x_prev_path_list
), GFP_KERNEL
);
10666 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
10670 tmp_list
->bus
= bp
->pdev
->bus
->number
;
10671 tmp_list
->slot
= PCI_SLOT(bp
->pdev
->devfn
);
10672 tmp_list
->path
= BP_PATH(bp
);
10674 tmp_list
->undi
= after_undi
? (1 << BP_PORT(bp
)) : 0;
10676 rc
= down_interruptible(&bnx2x_prev_sem
);
10678 BNX2X_ERR("Received %d when tried to take lock\n", rc
);
10681 DP(NETIF_MSG_HW
, "Marked path [%d] - finished previous unload\n",
10683 list_add(&tmp_list
->list
, &bnx2x_prev_list
);
10684 up(&bnx2x_prev_sem
);
10690 static int bnx2x_do_flr(struct bnx2x
*bp
)
10692 struct pci_dev
*dev
= bp
->pdev
;
10694 if (CHIP_IS_E1x(bp
)) {
10695 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
10699 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
10700 if (bp
->common
.bc_ver
< REQ_BC_VER_4_INITIATE_FLR
) {
10701 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
10702 bp
->common
.bc_ver
);
10706 if (!pci_wait_for_pending_transaction(dev
))
10707 dev_err(&dev
->dev
, "transaction is not cleared; proceeding with reset anyway\n");
10709 BNX2X_DEV_INFO("Initiating FLR\n");
10710 bnx2x_fw_command(bp
, DRV_MSG_CODE_INITIATE_FLR
, 0);
10715 static int bnx2x_prev_unload_uncommon(struct bnx2x
*bp
)
10719 BNX2X_DEV_INFO("Uncommon unload Flow\n");
10721 /* Test if previous unload process was already finished for this path */
10722 if (bnx2x_prev_is_path_marked(bp
))
10723 return bnx2x_prev_mcp_done(bp
);
10725 BNX2X_DEV_INFO("Path is unmarked\n");
10727 /* Cannot proceed with FLR if UNDI is loaded, since FW does not match */
10728 if (bnx2x_prev_is_after_undi(bp
))
10731 /* If function has FLR capabilities, and existing FW version matches
10732 * the one required, then FLR will be sufficient to clean any residue
10733 * left by previous driver
10735 rc
= bnx2x_compare_fw_ver(bp
, FW_MSG_CODE_DRV_LOAD_FUNCTION
, false);
10738 /* fw version is good */
10739 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
10740 rc
= bnx2x_do_flr(bp
);
10744 /* FLR was performed */
10745 BNX2X_DEV_INFO("FLR successful\n");
10749 BNX2X_DEV_INFO("Could not FLR\n");
10752 /* Close the MCP request, return failure*/
10753 rc
= bnx2x_prev_mcp_done(bp
);
10755 rc
= BNX2X_PREV_WAIT_NEEDED
;
10760 static int bnx2x_prev_unload_common(struct bnx2x
*bp
)
10762 u32 reset_reg
, tmp_reg
= 0, rc
;
10763 bool prev_undi
= false;
10764 struct bnx2x_mac_vals mac_vals
;
10766 /* It is possible a previous function received 'common' answer,
10767 * but hasn't loaded yet, therefore creating a scenario of
10768 * multiple functions receiving 'common' on the same path.
10770 BNX2X_DEV_INFO("Common unload Flow\n");
10772 memset(&mac_vals
, 0, sizeof(mac_vals
));
10774 if (bnx2x_prev_is_path_marked(bp
))
10775 return bnx2x_prev_mcp_done(bp
);
10777 reset_reg
= REG_RD(bp
, MISC_REG_RESET_REG_1
);
10779 /* Reset should be performed after BRB is emptied */
10780 if (reset_reg
& MISC_REGISTERS_RESET_REG_1_RST_BRB1
) {
10781 u32 timer_count
= 1000;
10783 /* Close the MAC Rx to prevent BRB from filling up */
10784 bnx2x_prev_unload_close_mac(bp
, &mac_vals
);
10786 /* close LLH filters for both ports towards the BRB */
10787 bnx2x_set_rx_filter(&bp
->link_params
, 0);
10788 bp
->link_params
.port
^= 1;
10789 bnx2x_set_rx_filter(&bp
->link_params
, 0);
10790 bp
->link_params
.port
^= 1;
10792 /* Check if the UNDI driver was previously loaded */
10793 if (bnx2x_prev_is_after_undi(bp
)) {
10795 /* clear the UNDI indication */
10796 REG_WR(bp
, DORQ_REG_NORM_CID_OFST
, 0);
10797 /* clear possible idle check errors */
10798 REG_RD(bp
, NIG_REG_NIG_INT_STS_CLR_0
);
10800 if (!CHIP_IS_E1x(bp
))
10801 /* block FW from writing to host */
10802 REG_WR(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
, 0);
10804 /* wait until BRB is empty */
10805 tmp_reg
= REG_RD(bp
, BRB1_REG_NUM_OF_FULL_BLOCKS
);
10806 while (timer_count
) {
10807 u32 prev_brb
= tmp_reg
;
10809 tmp_reg
= REG_RD(bp
, BRB1_REG_NUM_OF_FULL_BLOCKS
);
10813 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg
);
10815 /* reset timer as long as BRB actually gets emptied */
10816 if (prev_brb
> tmp_reg
)
10817 timer_count
= 1000;
10821 /* If UNDI resides in memory, manually increment it */
10823 bnx2x_prev_unload_undi_inc(bp
, 1);
10829 BNX2X_ERR("Failed to empty BRB, hope for the best\n");
10832 /* No packets are in the pipeline, path is ready for reset */
10833 bnx2x_reset_common(bp
);
10835 if (mac_vals
.xmac_addr
)
10836 REG_WR(bp
, mac_vals
.xmac_addr
, mac_vals
.xmac_val
);
10837 if (mac_vals
.umac_addr
[0])
10838 REG_WR(bp
, mac_vals
.umac_addr
[0], mac_vals
.umac_val
[0]);
10839 if (mac_vals
.umac_addr
[1])
10840 REG_WR(bp
, mac_vals
.umac_addr
[1], mac_vals
.umac_val
[1]);
10841 if (mac_vals
.emac_addr
)
10842 REG_WR(bp
, mac_vals
.emac_addr
, mac_vals
.emac_val
);
10843 if (mac_vals
.bmac_addr
) {
10844 REG_WR(bp
, mac_vals
.bmac_addr
, mac_vals
.bmac_val
[0]);
10845 REG_WR(bp
, mac_vals
.bmac_addr
+ 4, mac_vals
.bmac_val
[1]);
10848 rc
= bnx2x_prev_mark_path(bp
, prev_undi
);
10850 bnx2x_prev_mcp_done(bp
);
10854 return bnx2x_prev_mcp_done(bp
);
10857 static int bnx2x_prev_unload(struct bnx2x
*bp
)
10859 int time_counter
= 10;
10860 u32 rc
, fw
, hw_lock_reg
, hw_lock_val
;
10861 BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10863 /* clear hw from errors which may have resulted from an interrupted
10864 * dmae transaction.
10866 bnx2x_clean_pglue_errors(bp
);
10868 /* Release previously held locks */
10869 hw_lock_reg
= (BP_FUNC(bp
) <= 5) ?
10870 (MISC_REG_DRIVER_CONTROL_1
+ BP_FUNC(bp
) * 8) :
10871 (MISC_REG_DRIVER_CONTROL_7
+ (BP_FUNC(bp
) - 6) * 8);
10873 hw_lock_val
= REG_RD(bp
, hw_lock_reg
);
10875 if (hw_lock_val
& HW_LOCK_RESOURCE_NVRAM
) {
10876 BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10877 REG_WR(bp
, MCP_REG_MCPR_NVM_SW_ARB
,
10878 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1
<< BP_PORT(bp
)));
10881 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10882 REG_WR(bp
, hw_lock_reg
, 0xffffffff);
10884 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10886 if (MCPR_ACCESS_LOCK_LOCK
& REG_RD(bp
, MCP_REG_MCPR_ACCESS_LOCK
)) {
10887 BNX2X_DEV_INFO("Release previously held alr\n");
10888 bnx2x_release_alr(bp
);
10893 /* Lock MCP using an unload request */
10894 fw
= bnx2x_fw_command(bp
, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS
, 0);
10896 BNX2X_ERR("MCP response failure, aborting\n");
10901 rc
= down_interruptible(&bnx2x_prev_sem
);
10903 BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10906 /* If Path is marked by EEH, ignore unload status */
10907 aer
= !!(bnx2x_prev_path_get_entry(bp
) &&
10908 bnx2x_prev_path_get_entry(bp
)->aer
);
10909 up(&bnx2x_prev_sem
);
10912 if (fw
== FW_MSG_CODE_DRV_UNLOAD_COMMON
|| aer
) {
10913 rc
= bnx2x_prev_unload_common(bp
);
10917 /* non-common reply from MCP might require looping */
10918 rc
= bnx2x_prev_unload_uncommon(bp
);
10919 if (rc
!= BNX2X_PREV_WAIT_NEEDED
)
10923 } while (--time_counter
);
10925 if (!time_counter
|| rc
) {
10926 BNX2X_DEV_INFO("Unloading previous driver did not occur, Possibly due to MF UNDI\n");
10927 rc
= -EPROBE_DEFER
;
10930 /* Mark function if its port was used to boot from SAN */
10931 if (bnx2x_port_after_undi(bp
))
10932 bp
->link_params
.feature_config_flags
|=
10933 FEATURE_CONFIG_BOOT_FROM_SAN
;
10935 BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc
);
10940 static void bnx2x_get_common_hwinfo(struct bnx2x
*bp
)
10942 u32 val
, val2
, val3
, val4
, id
, boot_mode
;
10945 /* Get the chip revision id and number. */
10946 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10947 val
= REG_RD(bp
, MISC_REG_CHIP_NUM
);
10948 id
= ((val
& 0xffff) << 16);
10949 val
= REG_RD(bp
, MISC_REG_CHIP_REV
);
10950 id
|= ((val
& 0xf) << 12);
10952 /* Metal is read from PCI regs, but we can't access >=0x400 from
10953 * the configuration space (so we need to reg_rd)
10955 val
= REG_RD(bp
, PCICFG_OFFSET
+ PCI_ID_VAL3
);
10956 id
|= (((val
>> 24) & 0xf) << 4);
10957 val
= REG_RD(bp
, MISC_REG_BOND_ID
);
10959 bp
->common
.chip_id
= id
;
10961 /* force 57811 according to MISC register */
10962 if (REG_RD(bp
, MISC_REG_CHIP_TYPE
) & MISC_REG_CHIP_TYPE_57811_MASK
) {
10963 if (CHIP_IS_57810(bp
))
10964 bp
->common
.chip_id
= (CHIP_NUM_57811
<< 16) |
10965 (bp
->common
.chip_id
& 0x0000FFFF);
10966 else if (CHIP_IS_57810_MF(bp
))
10967 bp
->common
.chip_id
= (CHIP_NUM_57811_MF
<< 16) |
10968 (bp
->common
.chip_id
& 0x0000FFFF);
10969 bp
->common
.chip_id
|= 0x1;
10972 /* Set doorbell size */
10973 bp
->db_size
= (1 << BNX2X_DB_SHIFT
);
10975 if (!CHIP_IS_E1x(bp
)) {
10976 val
= REG_RD(bp
, MISC_REG_PORT4MODE_EN_OVWR
);
10977 if ((val
& 1) == 0)
10978 val
= REG_RD(bp
, MISC_REG_PORT4MODE_EN
);
10980 val
= (val
>> 1) & 1;
10981 BNX2X_DEV_INFO("chip is in %s\n", val
? "4_PORT_MODE" :
10983 bp
->common
.chip_port_mode
= val
? CHIP_4_PORT_MODE
:
10986 if (CHIP_MODE_IS_4_PORT(bp
))
10987 bp
->pfid
= (bp
->pf_num
>> 1); /* 0..3 */
10989 bp
->pfid
= (bp
->pf_num
& 0x6); /* 0, 2, 4, 6 */
10991 bp
->common
.chip_port_mode
= CHIP_PORT_MODE_NONE
; /* N/A */
10992 bp
->pfid
= bp
->pf_num
; /* 0..7 */
10995 BNX2X_DEV_INFO("pf_id: %x", bp
->pfid
);
10997 bp
->link_params
.chip_id
= bp
->common
.chip_id
;
10998 BNX2X_DEV_INFO("chip ID is 0x%x\n", id
);
11000 val
= (REG_RD(bp
, 0x2874) & 0x55);
11001 if ((bp
->common
.chip_id
& 0x1) ||
11002 (CHIP_IS_E1(bp
) && val
) || (CHIP_IS_E1H(bp
) && (val
== 0x55))) {
11003 bp
->flags
|= ONE_PORT_FLAG
;
11004 BNX2X_DEV_INFO("single port device\n");
11007 val
= REG_RD(bp
, MCP_REG_MCPR_NVM_CFG4
);
11008 bp
->common
.flash_size
= (BNX2X_NVRAM_1MB_SIZE
<<
11009 (val
& MCPR_NVM_CFG4_FLASH_SIZE
));
11010 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
11011 bp
->common
.flash_size
, bp
->common
.flash_size
);
11013 bnx2x_init_shmem(bp
);
11015 bp
->common
.shmem2_base
= REG_RD(bp
, (BP_PATH(bp
) ?
11016 MISC_REG_GENERIC_CR_1
:
11017 MISC_REG_GENERIC_CR_0
));
11019 bp
->link_params
.shmem_base
= bp
->common
.shmem_base
;
11020 bp
->link_params
.shmem2_base
= bp
->common
.shmem2_base
;
11021 if (SHMEM2_RD(bp
, size
) >
11022 (u32
)offsetof(struct shmem2_region
, lfa_host_addr
[BP_PORT(bp
)]))
11023 bp
->link_params
.lfa_base
=
11024 REG_RD(bp
, bp
->common
.shmem2_base
+
11025 (u32
)offsetof(struct shmem2_region
,
11026 lfa_host_addr
[BP_PORT(bp
)]));
11028 bp
->link_params
.lfa_base
= 0;
11029 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
11030 bp
->common
.shmem_base
, bp
->common
.shmem2_base
);
11032 if (!bp
->common
.shmem_base
) {
11033 BNX2X_DEV_INFO("MCP not active\n");
11034 bp
->flags
|= NO_MCP_FLAG
;
11038 bp
->common
.hw_config
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.config
);
11039 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp
->common
.hw_config
);
11041 bp
->link_params
.hw_led_mode
= ((bp
->common
.hw_config
&
11042 SHARED_HW_CFG_LED_MODE_MASK
) >>
11043 SHARED_HW_CFG_LED_MODE_SHIFT
);
11045 bp
->link_params
.feature_config_flags
= 0;
11046 val
= SHMEM_RD(bp
, dev_info
.shared_feature_config
.config
);
11047 if (val
& SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED
)
11048 bp
->link_params
.feature_config_flags
|=
11049 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED
;
11051 bp
->link_params
.feature_config_flags
&=
11052 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED
;
11054 val
= SHMEM_RD(bp
, dev_info
.bc_rev
) >> 8;
11055 bp
->common
.bc_ver
= val
;
11056 BNX2X_DEV_INFO("bc_ver %X\n", val
);
11057 if (val
< BNX2X_BC_VER
) {
11058 /* for now only warn
11059 * later we might need to enforce this */
11060 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
11061 BNX2X_BC_VER
, val
);
11063 bp
->link_params
.feature_config_flags
|=
11064 (val
>= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL
) ?
11065 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY
: 0;
11067 bp
->link_params
.feature_config_flags
|=
11068 (val
>= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL
) ?
11069 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY
: 0;
11070 bp
->link_params
.feature_config_flags
|=
11071 (val
>= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED
) ?
11072 FEATURE_CONFIG_BC_SUPPORTS_AFEX
: 0;
11073 bp
->link_params
.feature_config_flags
|=
11074 (val
>= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED
) ?
11075 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED
: 0;
11077 bp
->link_params
.feature_config_flags
|=
11078 (val
>= REQ_BC_VER_4_MT_SUPPORTED
) ?
11079 FEATURE_CONFIG_MT_SUPPORT
: 0;
11081 bp
->flags
|= (val
>= REQ_BC_VER_4_PFC_STATS_SUPPORTED
) ?
11082 BC_SUPPORTS_PFC_STATS
: 0;
11084 bp
->flags
|= (val
>= REQ_BC_VER_4_FCOE_FEATURES
) ?
11085 BC_SUPPORTS_FCOE_FEATURES
: 0;
11087 bp
->flags
|= (val
>= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF
) ?
11088 BC_SUPPORTS_DCBX_MSG_NON_PMF
: 0;
11090 bp
->flags
|= (val
>= REQ_BC_VER_4_RMMOD_CMD
) ?
11091 BC_SUPPORTS_RMMOD_CMD
: 0;
11093 boot_mode
= SHMEM_RD(bp
,
11094 dev_info
.port_feature_config
[BP_PORT(bp
)].mba_config
) &
11095 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK
;
11096 switch (boot_mode
) {
11097 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE
:
11098 bp
->common
.boot_mode
= FEATURE_ETH_BOOTMODE_PXE
;
11100 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB
:
11101 bp
->common
.boot_mode
= FEATURE_ETH_BOOTMODE_ISCSI
;
11103 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT
:
11104 bp
->common
.boot_mode
= FEATURE_ETH_BOOTMODE_FCOE
;
11106 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE
:
11107 bp
->common
.boot_mode
= FEATURE_ETH_BOOTMODE_NONE
;
11111 pci_read_config_word(bp
->pdev
, bp
->pdev
->pm_cap
+ PCI_PM_PMC
, &pmc
);
11112 bp
->flags
|= (pmc
& PCI_PM_CAP_PME_D3cold
) ? 0 : NO_WOL_FLAG
;
11114 BNX2X_DEV_INFO("%sWoL capable\n",
11115 (bp
->flags
& NO_WOL_FLAG
) ? "not " : "");
11117 val
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.part_num
);
11118 val2
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.part_num
[4]);
11119 val3
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.part_num
[8]);
11120 val4
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.part_num
[12]);
11122 dev_info(&bp
->pdev
->dev
, "part number %X-%X-%X-%X\n",
11123 val
, val2
, val3
, val4
);
11126 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
11127 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
11129 static int bnx2x_get_igu_cam_info(struct bnx2x
*bp
)
11131 int pfid
= BP_FUNC(bp
);
11134 u8 fid
, igu_sb_cnt
= 0;
11136 bp
->igu_base_sb
= 0xff;
11137 if (CHIP_INT_MODE_IS_BC(bp
)) {
11138 int vn
= BP_VN(bp
);
11139 igu_sb_cnt
= bp
->igu_sb_cnt
;
11140 bp
->igu_base_sb
= (CHIP_MODE_IS_4_PORT(bp
) ? pfid
: vn
) *
11143 bp
->igu_dsb_id
= E1HVN_MAX
* FP_SB_MAX_E1x
+
11144 (CHIP_MODE_IS_4_PORT(bp
) ? pfid
: vn
);
11149 /* IGU in normal mode - read CAM */
11150 for (igu_sb_id
= 0; igu_sb_id
< IGU_REG_MAPPING_MEMORY_SIZE
;
11152 val
= REG_RD(bp
, IGU_REG_MAPPING_MEMORY
+ igu_sb_id
* 4);
11153 if (!(val
& IGU_REG_MAPPING_MEMORY_VALID
))
11155 fid
= IGU_FID(val
);
11156 if ((fid
& IGU_FID_ENCODE_IS_PF
)) {
11157 if ((fid
& IGU_FID_PF_NUM_MASK
) != pfid
)
11159 if (IGU_VEC(val
) == 0)
11160 /* default status block */
11161 bp
->igu_dsb_id
= igu_sb_id
;
11163 if (bp
->igu_base_sb
== 0xff)
11164 bp
->igu_base_sb
= igu_sb_id
;
11170 #ifdef CONFIG_PCI_MSI
11171 /* Due to new PF resource allocation by MFW T7.4 and above, it's
11172 * optional that number of CAM entries will not be equal to the value
11173 * advertised in PCI.
11174 * Driver should use the minimal value of both as the actual status
11177 bp
->igu_sb_cnt
= min_t(int, bp
->igu_sb_cnt
, igu_sb_cnt
);
11180 if (igu_sb_cnt
== 0) {
11181 BNX2X_ERR("CAM configuration error\n");
11188 static void bnx2x_link_settings_supported(struct bnx2x
*bp
, u32 switch_cfg
)
11190 int cfg_size
= 0, idx
, port
= BP_PORT(bp
);
11192 /* Aggregation of supported attributes of all external phys */
11193 bp
->port
.supported
[0] = 0;
11194 bp
->port
.supported
[1] = 0;
11195 switch (bp
->link_params
.num_phys
) {
11197 bp
->port
.supported
[0] = bp
->link_params
.phy
[INT_PHY
].supported
;
11201 bp
->port
.supported
[0] = bp
->link_params
.phy
[EXT_PHY1
].supported
;
11205 if (bp
->link_params
.multi_phy_config
&
11206 PORT_HW_CFG_PHY_SWAPPED_ENABLED
) {
11207 bp
->port
.supported
[1] =
11208 bp
->link_params
.phy
[EXT_PHY1
].supported
;
11209 bp
->port
.supported
[0] =
11210 bp
->link_params
.phy
[EXT_PHY2
].supported
;
11212 bp
->port
.supported
[0] =
11213 bp
->link_params
.phy
[EXT_PHY1
].supported
;
11214 bp
->port
.supported
[1] =
11215 bp
->link_params
.phy
[EXT_PHY2
].supported
;
11221 if (!(bp
->port
.supported
[0] || bp
->port
.supported
[1])) {
11222 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
11224 dev_info
.port_hw_config
[port
].external_phy_config
),
11226 dev_info
.port_hw_config
[port
].external_phy_config2
));
11230 if (CHIP_IS_E3(bp
))
11231 bp
->port
.phy_addr
= REG_RD(bp
, MISC_REG_WC0_CTRL_PHY_ADDR
);
11233 switch (switch_cfg
) {
11234 case SWITCH_CFG_1G
:
11235 bp
->port
.phy_addr
= REG_RD(
11236 bp
, NIG_REG_SERDES0_CTRL_PHY_ADDR
+ port
*0x10);
11238 case SWITCH_CFG_10G
:
11239 bp
->port
.phy_addr
= REG_RD(
11240 bp
, NIG_REG_XGXS0_CTRL_PHY_ADDR
+ port
*0x18);
11243 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
11244 bp
->port
.link_config
[0]);
11248 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp
->port
.phy_addr
);
11249 /* mask what we support according to speed_cap_mask per configuration */
11250 for (idx
= 0; idx
< cfg_size
; idx
++) {
11251 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
11252 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF
))
11253 bp
->port
.supported
[idx
] &= ~SUPPORTED_10baseT_Half
;
11255 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
11256 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL
))
11257 bp
->port
.supported
[idx
] &= ~SUPPORTED_10baseT_Full
;
11259 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
11260 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF
))
11261 bp
->port
.supported
[idx
] &= ~SUPPORTED_100baseT_Half
;
11263 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
11264 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL
))
11265 bp
->port
.supported
[idx
] &= ~SUPPORTED_100baseT_Full
;
11267 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
11268 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
))
11269 bp
->port
.supported
[idx
] &= ~(SUPPORTED_1000baseT_Half
|
11270 SUPPORTED_1000baseT_Full
);
11272 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
11273 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G
))
11274 bp
->port
.supported
[idx
] &= ~SUPPORTED_2500baseX_Full
;
11276 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
11277 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
))
11278 bp
->port
.supported
[idx
] &= ~SUPPORTED_10000baseT_Full
;
11280 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
11281 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G
))
11282 bp
->port
.supported
[idx
] &= ~SUPPORTED_20000baseKR2_Full
;
11285 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp
->port
.supported
[0],
11286 bp
->port
.supported
[1]);
11289 static void bnx2x_link_settings_requested(struct bnx2x
*bp
)
11291 u32 link_config
, idx
, cfg_size
= 0;
11292 bp
->port
.advertising
[0] = 0;
11293 bp
->port
.advertising
[1] = 0;
11294 switch (bp
->link_params
.num_phys
) {
11303 for (idx
= 0; idx
< cfg_size
; idx
++) {
11304 bp
->link_params
.req_duplex
[idx
] = DUPLEX_FULL
;
11305 link_config
= bp
->port
.link_config
[idx
];
11306 switch (link_config
& PORT_FEATURE_LINK_SPEED_MASK
) {
11307 case PORT_FEATURE_LINK_SPEED_AUTO
:
11308 if (bp
->port
.supported
[idx
] & SUPPORTED_Autoneg
) {
11309 bp
->link_params
.req_line_speed
[idx
] =
11311 bp
->port
.advertising
[idx
] |=
11312 bp
->port
.supported
[idx
];
11313 if (bp
->link_params
.phy
[EXT_PHY1
].type
==
11314 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833
)
11315 bp
->port
.advertising
[idx
] |=
11316 (SUPPORTED_100baseT_Half
|
11317 SUPPORTED_100baseT_Full
);
11319 /* force 10G, no AN */
11320 bp
->link_params
.req_line_speed
[idx
] =
11322 bp
->port
.advertising
[idx
] |=
11323 (ADVERTISED_10000baseT_Full
|
11329 case PORT_FEATURE_LINK_SPEED_10M_FULL
:
11330 if (bp
->port
.supported
[idx
] & SUPPORTED_10baseT_Full
) {
11331 bp
->link_params
.req_line_speed
[idx
] =
11333 bp
->port
.advertising
[idx
] |=
11334 (ADVERTISED_10baseT_Full
|
11337 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11339 bp
->link_params
.speed_cap_mask
[idx
]);
11344 case PORT_FEATURE_LINK_SPEED_10M_HALF
:
11345 if (bp
->port
.supported
[idx
] & SUPPORTED_10baseT_Half
) {
11346 bp
->link_params
.req_line_speed
[idx
] =
11348 bp
->link_params
.req_duplex
[idx
] =
11350 bp
->port
.advertising
[idx
] |=
11351 (ADVERTISED_10baseT_Half
|
11354 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11356 bp
->link_params
.speed_cap_mask
[idx
]);
11361 case PORT_FEATURE_LINK_SPEED_100M_FULL
:
11362 if (bp
->port
.supported
[idx
] &
11363 SUPPORTED_100baseT_Full
) {
11364 bp
->link_params
.req_line_speed
[idx
] =
11366 bp
->port
.advertising
[idx
] |=
11367 (ADVERTISED_100baseT_Full
|
11370 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11372 bp
->link_params
.speed_cap_mask
[idx
]);
11377 case PORT_FEATURE_LINK_SPEED_100M_HALF
:
11378 if (bp
->port
.supported
[idx
] &
11379 SUPPORTED_100baseT_Half
) {
11380 bp
->link_params
.req_line_speed
[idx
] =
11382 bp
->link_params
.req_duplex
[idx
] =
11384 bp
->port
.advertising
[idx
] |=
11385 (ADVERTISED_100baseT_Half
|
11388 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11390 bp
->link_params
.speed_cap_mask
[idx
]);
11395 case PORT_FEATURE_LINK_SPEED_1G
:
11396 if (bp
->port
.supported
[idx
] &
11397 SUPPORTED_1000baseT_Full
) {
11398 bp
->link_params
.req_line_speed
[idx
] =
11400 bp
->port
.advertising
[idx
] |=
11401 (ADVERTISED_1000baseT_Full
|
11403 } else if (bp
->port
.supported
[idx
] &
11404 SUPPORTED_1000baseKX_Full
) {
11405 bp
->link_params
.req_line_speed
[idx
] =
11407 bp
->port
.advertising
[idx
] |=
11408 ADVERTISED_1000baseKX_Full
;
11410 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11412 bp
->link_params
.speed_cap_mask
[idx
]);
11417 case PORT_FEATURE_LINK_SPEED_2_5G
:
11418 if (bp
->port
.supported
[idx
] &
11419 SUPPORTED_2500baseX_Full
) {
11420 bp
->link_params
.req_line_speed
[idx
] =
11422 bp
->port
.advertising
[idx
] |=
11423 (ADVERTISED_2500baseX_Full
|
11426 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11428 bp
->link_params
.speed_cap_mask
[idx
]);
11433 case PORT_FEATURE_LINK_SPEED_10G_CX4
:
11434 if (bp
->port
.supported
[idx
] &
11435 SUPPORTED_10000baseT_Full
) {
11436 bp
->link_params
.req_line_speed
[idx
] =
11438 bp
->port
.advertising
[idx
] |=
11439 (ADVERTISED_10000baseT_Full
|
11441 } else if (bp
->port
.supported
[idx
] &
11442 SUPPORTED_10000baseKR_Full
) {
11443 bp
->link_params
.req_line_speed
[idx
] =
11445 bp
->port
.advertising
[idx
] |=
11446 (ADVERTISED_10000baseKR_Full
|
11449 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11451 bp
->link_params
.speed_cap_mask
[idx
]);
11455 case PORT_FEATURE_LINK_SPEED_20G
:
11456 bp
->link_params
.req_line_speed
[idx
] = SPEED_20000
;
11460 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
11462 bp
->link_params
.req_line_speed
[idx
] =
11464 bp
->port
.advertising
[idx
] =
11465 bp
->port
.supported
[idx
];
11469 bp
->link_params
.req_flow_ctrl
[idx
] = (link_config
&
11470 PORT_FEATURE_FLOW_CONTROL_MASK
);
11471 if (bp
->link_params
.req_flow_ctrl
[idx
] ==
11472 BNX2X_FLOW_CTRL_AUTO
) {
11473 if (!(bp
->port
.supported
[idx
] & SUPPORTED_Autoneg
))
11474 bp
->link_params
.req_flow_ctrl
[idx
] =
11475 BNX2X_FLOW_CTRL_NONE
;
11477 bnx2x_set_requested_fc(bp
);
11480 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
11481 bp
->link_params
.req_line_speed
[idx
],
11482 bp
->link_params
.req_duplex
[idx
],
11483 bp
->link_params
.req_flow_ctrl
[idx
],
11484 bp
->port
.advertising
[idx
]);
11488 static void bnx2x_set_mac_buf(u8
*mac_buf
, u32 mac_lo
, u16 mac_hi
)
11490 __be16 mac_hi_be
= cpu_to_be16(mac_hi
);
11491 __be32 mac_lo_be
= cpu_to_be32(mac_lo
);
11492 memcpy(mac_buf
, &mac_hi_be
, sizeof(mac_hi_be
));
11493 memcpy(mac_buf
+ sizeof(mac_hi_be
), &mac_lo_be
, sizeof(mac_lo_be
));
11496 static void bnx2x_get_port_hwinfo(struct bnx2x
*bp
)
11498 int port
= BP_PORT(bp
);
11500 u32 ext_phy_type
, ext_phy_config
, eee_mode
;
11502 bp
->link_params
.bp
= bp
;
11503 bp
->link_params
.port
= port
;
11505 bp
->link_params
.lane_config
=
11506 SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].lane_config
);
11508 bp
->link_params
.speed_cap_mask
[0] =
11510 dev_info
.port_hw_config
[port
].speed_capability_mask
) &
11511 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK
;
11512 bp
->link_params
.speed_cap_mask
[1] =
11514 dev_info
.port_hw_config
[port
].speed_capability_mask2
) &
11515 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK
;
11516 bp
->port
.link_config
[0] =
11517 SHMEM_RD(bp
, dev_info
.port_feature_config
[port
].link_config
);
11519 bp
->port
.link_config
[1] =
11520 SHMEM_RD(bp
, dev_info
.port_feature_config
[port
].link_config2
);
11522 bp
->link_params
.multi_phy_config
=
11523 SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].multi_phy_config
);
11524 /* If the device is capable of WoL, set the default state according
11527 config
= SHMEM_RD(bp
, dev_info
.port_feature_config
[port
].config
);
11528 bp
->wol
= (!(bp
->flags
& NO_WOL_FLAG
) &&
11529 (config
& PORT_FEATURE_WOL_ENABLED
));
11531 if ((config
& PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK
) ==
11532 PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE
&& !IS_MF(bp
))
11533 bp
->flags
|= NO_ISCSI_FLAG
;
11534 if ((config
& PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK
) ==
11535 PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI
&& !(IS_MF(bp
)))
11536 bp
->flags
|= NO_FCOE_FLAG
;
11538 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n",
11539 bp
->link_params
.lane_config
,
11540 bp
->link_params
.speed_cap_mask
[0],
11541 bp
->port
.link_config
[0]);
11543 bp
->link_params
.switch_cfg
= (bp
->port
.link_config
[0] &
11544 PORT_FEATURE_CONNECTED_SWITCH_MASK
);
11545 bnx2x_phy_probe(&bp
->link_params
);
11546 bnx2x_link_settings_supported(bp
, bp
->link_params
.switch_cfg
);
11548 bnx2x_link_settings_requested(bp
);
11551 * If connected directly, work with the internal PHY, otherwise, work
11552 * with the external PHY
11556 dev_info
.port_hw_config
[port
].external_phy_config
);
11557 ext_phy_type
= XGXS_EXT_PHY_TYPE(ext_phy_config
);
11558 if (ext_phy_type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
)
11559 bp
->mdio
.prtad
= bp
->port
.phy_addr
;
11561 else if ((ext_phy_type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE
) &&
11562 (ext_phy_type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN
))
11564 XGXS_EXT_PHY_ADDR(ext_phy_config
);
11566 /* Configure link feature according to nvram value */
11567 eee_mode
= (((SHMEM_RD(bp
, dev_info
.
11568 port_feature_config
[port
].eee_power_mode
)) &
11569 PORT_FEAT_CFG_EEE_POWER_MODE_MASK
) >>
11570 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT
);
11571 if (eee_mode
!= PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED
) {
11572 bp
->link_params
.eee_mode
= EEE_MODE_ADV_LPI
|
11573 EEE_MODE_ENABLE_LPI
|
11574 EEE_MODE_OUTPUT_TIME
;
11576 bp
->link_params
.eee_mode
= 0;
11580 void bnx2x_get_iscsi_info(struct bnx2x
*bp
)
11582 u32 no_flags
= NO_ISCSI_FLAG
;
11583 int port
= BP_PORT(bp
);
11584 u32 max_iscsi_conn
= FW_ENCODE_32BIT_PATTERN
^ SHMEM_RD(bp
,
11585 drv_lic_key
[port
].max_iscsi_conn
);
11587 if (!CNIC_SUPPORT(bp
)) {
11588 bp
->flags
|= no_flags
;
11592 /* Get the number of maximum allowed iSCSI connections */
11593 bp
->cnic_eth_dev
.max_iscsi_conn
=
11594 (max_iscsi_conn
& BNX2X_MAX_ISCSI_INIT_CONN_MASK
) >>
11595 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT
;
11597 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
11598 bp
->cnic_eth_dev
.max_iscsi_conn
);
11601 * If maximum allowed number of connections is zero -
11602 * disable the feature.
11604 if (!bp
->cnic_eth_dev
.max_iscsi_conn
)
11605 bp
->flags
|= no_flags
;
11608 static void bnx2x_get_ext_wwn_info(struct bnx2x
*bp
, int func
)
11611 bp
->cnic_eth_dev
.fcoe_wwn_port_name_hi
=
11612 MF_CFG_RD(bp
, func_ext_config
[func
].fcoe_wwn_port_name_upper
);
11613 bp
->cnic_eth_dev
.fcoe_wwn_port_name_lo
=
11614 MF_CFG_RD(bp
, func_ext_config
[func
].fcoe_wwn_port_name_lower
);
11617 bp
->cnic_eth_dev
.fcoe_wwn_node_name_hi
=
11618 MF_CFG_RD(bp
, func_ext_config
[func
].fcoe_wwn_node_name_upper
);
11619 bp
->cnic_eth_dev
.fcoe_wwn_node_name_lo
=
11620 MF_CFG_RD(bp
, func_ext_config
[func
].fcoe_wwn_node_name_lower
);
11623 static int bnx2x_shared_fcoe_funcs(struct bnx2x
*bp
)
11630 /* iterate over absolute function ids for this path: */
11631 for (fid
= BP_PATH(bp
); fid
< E2_FUNC_MAX
* 2; fid
+= 2) {
11632 if (IS_MF_SD(bp
)) {
11633 u32 cfg
= MF_CFG_RD(bp
,
11634 func_mf_config
[fid
].config
);
11636 if (!(cfg
& FUNC_MF_CFG_FUNC_HIDE
) &&
11637 ((cfg
& FUNC_MF_CFG_PROTOCOL_MASK
) ==
11638 FUNC_MF_CFG_PROTOCOL_FCOE
))
11641 u32 cfg
= MF_CFG_RD(bp
,
11642 func_ext_config
[fid
].
11645 if ((cfg
& MACP_FUNC_CFG_FLAGS_ENABLED
) &&
11646 (cfg
& MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD
))
11651 int port
, port_cnt
= CHIP_MODE_IS_4_PORT(bp
) ? 2 : 1;
11653 for (port
= 0; port
< port_cnt
; port
++) {
11654 u32 lic
= SHMEM_RD(bp
,
11655 drv_lic_key
[port
].max_fcoe_conn
) ^
11656 FW_ENCODE_32BIT_PATTERN
;
11665 static void bnx2x_get_fcoe_info(struct bnx2x
*bp
)
11667 int port
= BP_PORT(bp
);
11668 int func
= BP_ABS_FUNC(bp
);
11669 u32 max_fcoe_conn
= FW_ENCODE_32BIT_PATTERN
^ SHMEM_RD(bp
,
11670 drv_lic_key
[port
].max_fcoe_conn
);
11671 u8 num_fcoe_func
= bnx2x_shared_fcoe_funcs(bp
);
11673 if (!CNIC_SUPPORT(bp
)) {
11674 bp
->flags
|= NO_FCOE_FLAG
;
11678 /* Get the number of maximum allowed FCoE connections */
11679 bp
->cnic_eth_dev
.max_fcoe_conn
=
11680 (max_fcoe_conn
& BNX2X_MAX_FCOE_INIT_CONN_MASK
) >>
11681 BNX2X_MAX_FCOE_INIT_CONN_SHIFT
;
11683 /* Calculate the number of maximum allowed FCoE tasks */
11684 bp
->cnic_eth_dev
.max_fcoe_exchanges
= MAX_NUM_FCOE_TASKS_PER_ENGINE
;
11686 /* check if FCoE resources must be shared between different functions */
11688 bp
->cnic_eth_dev
.max_fcoe_exchanges
/= num_fcoe_func
;
11690 /* Read the WWN: */
11693 bp
->cnic_eth_dev
.fcoe_wwn_port_name_hi
=
11695 dev_info
.port_hw_config
[port
].
11696 fcoe_wwn_port_name_upper
);
11697 bp
->cnic_eth_dev
.fcoe_wwn_port_name_lo
=
11699 dev_info
.port_hw_config
[port
].
11700 fcoe_wwn_port_name_lower
);
11703 bp
->cnic_eth_dev
.fcoe_wwn_node_name_hi
=
11705 dev_info
.port_hw_config
[port
].
11706 fcoe_wwn_node_name_upper
);
11707 bp
->cnic_eth_dev
.fcoe_wwn_node_name_lo
=
11709 dev_info
.port_hw_config
[port
].
11710 fcoe_wwn_node_name_lower
);
11711 } else if (!IS_MF_SD(bp
)) {
11712 /* Read the WWN info only if the FCoE feature is enabled for
11715 if (BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp
))
11716 bnx2x_get_ext_wwn_info(bp
, func
);
11718 if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp
) && !CHIP_IS_E1x(bp
))
11719 bnx2x_get_ext_wwn_info(bp
, func
);
11722 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp
->cnic_eth_dev
.max_fcoe_conn
);
11725 * If maximum allowed number of connections is zero -
11726 * disable the feature.
11728 if (!bp
->cnic_eth_dev
.max_fcoe_conn
)
11729 bp
->flags
|= NO_FCOE_FLAG
;
11732 static void bnx2x_get_cnic_info(struct bnx2x
*bp
)
11735 * iSCSI may be dynamically disabled but reading
11736 * info here we will decrease memory usage by driver
11737 * if the feature is disabled for good
11739 bnx2x_get_iscsi_info(bp
);
11740 bnx2x_get_fcoe_info(bp
);
11743 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x
*bp
)
11746 int func
= BP_ABS_FUNC(bp
);
11747 int port
= BP_PORT(bp
);
11748 u8
*iscsi_mac
= bp
->cnic_eth_dev
.iscsi_mac
;
11749 u8
*fip_mac
= bp
->fip_mac
;
11752 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
11753 * FCoE MAC then the appropriate feature should be disabled.
11754 * In non SD mode features configuration comes from struct
11757 if (!IS_MF_SD(bp
)) {
11758 u32 cfg
= MF_CFG_RD(bp
, func_ext_config
[func
].func_cfg
);
11759 if (cfg
& MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD
) {
11760 val2
= MF_CFG_RD(bp
, func_ext_config
[func
].
11761 iscsi_mac_addr_upper
);
11762 val
= MF_CFG_RD(bp
, func_ext_config
[func
].
11763 iscsi_mac_addr_lower
);
11764 bnx2x_set_mac_buf(iscsi_mac
, val
, val2
);
11766 ("Read iSCSI MAC: %pM\n", iscsi_mac
);
11768 bp
->flags
|= NO_ISCSI_OOO_FLAG
| NO_ISCSI_FLAG
;
11771 if (cfg
& MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD
) {
11772 val2
= MF_CFG_RD(bp
, func_ext_config
[func
].
11773 fcoe_mac_addr_upper
);
11774 val
= MF_CFG_RD(bp
, func_ext_config
[func
].
11775 fcoe_mac_addr_lower
);
11776 bnx2x_set_mac_buf(fip_mac
, val
, val2
);
11778 ("Read FCoE L2 MAC: %pM\n", fip_mac
);
11780 bp
->flags
|= NO_FCOE_FLAG
;
11783 bp
->mf_ext_config
= cfg
;
11785 } else { /* SD MODE */
11786 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp
)) {
11787 /* use primary mac as iscsi mac */
11788 memcpy(iscsi_mac
, bp
->dev
->dev_addr
, ETH_ALEN
);
11790 BNX2X_DEV_INFO("SD ISCSI MODE\n");
11792 ("Read iSCSI MAC: %pM\n", iscsi_mac
);
11793 } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp
)) {
11794 /* use primary mac as fip mac */
11795 memcpy(fip_mac
, bp
->dev
->dev_addr
, ETH_ALEN
);
11796 BNX2X_DEV_INFO("SD FCoE MODE\n");
11798 ("Read FIP MAC: %pM\n", fip_mac
);
11802 /* If this is a storage-only interface, use SAN mac as
11803 * primary MAC. Notice that for SD this is already the case,
11804 * as the SAN mac was copied from the primary MAC.
11806 if (IS_MF_FCOE_AFEX(bp
))
11807 memcpy(bp
->dev
->dev_addr
, fip_mac
, ETH_ALEN
);
11809 val2
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].
11811 val
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].
11813 bnx2x_set_mac_buf(iscsi_mac
, val
, val2
);
11815 val2
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].
11816 fcoe_fip_mac_upper
);
11817 val
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].
11818 fcoe_fip_mac_lower
);
11819 bnx2x_set_mac_buf(fip_mac
, val
, val2
);
11822 /* Disable iSCSI OOO if MAC configuration is invalid. */
11823 if (!is_valid_ether_addr(iscsi_mac
)) {
11824 bp
->flags
|= NO_ISCSI_OOO_FLAG
| NO_ISCSI_FLAG
;
11825 eth_zero_addr(iscsi_mac
);
11828 /* Disable FCoE if MAC configuration is invalid. */
11829 if (!is_valid_ether_addr(fip_mac
)) {
11830 bp
->flags
|= NO_FCOE_FLAG
;
11831 eth_zero_addr(bp
->fip_mac
);
11835 static void bnx2x_get_mac_hwinfo(struct bnx2x
*bp
)
11838 int func
= BP_ABS_FUNC(bp
);
11839 int port
= BP_PORT(bp
);
11841 /* Zero primary MAC configuration */
11842 eth_zero_addr(bp
->dev
->dev_addr
);
11844 if (BP_NOMCP(bp
)) {
11845 BNX2X_ERROR("warning: random MAC workaround active\n");
11846 eth_hw_addr_random(bp
->dev
);
11847 } else if (IS_MF(bp
)) {
11848 val2
= MF_CFG_RD(bp
, func_mf_config
[func
].mac_upper
);
11849 val
= MF_CFG_RD(bp
, func_mf_config
[func
].mac_lower
);
11850 if ((val2
!= FUNC_MF_CFG_UPPERMAC_DEFAULT
) &&
11851 (val
!= FUNC_MF_CFG_LOWERMAC_DEFAULT
))
11852 bnx2x_set_mac_buf(bp
->dev
->dev_addr
, val
, val2
);
11854 if (CNIC_SUPPORT(bp
))
11855 bnx2x_get_cnic_mac_hwinfo(bp
);
11857 /* in SF read MACs from port configuration */
11858 val2
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].mac_upper
);
11859 val
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].mac_lower
);
11860 bnx2x_set_mac_buf(bp
->dev
->dev_addr
, val
, val2
);
11862 if (CNIC_SUPPORT(bp
))
11863 bnx2x_get_cnic_mac_hwinfo(bp
);
11866 if (!BP_NOMCP(bp
)) {
11867 /* Read physical port identifier from shmem */
11868 val2
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].mac_upper
);
11869 val
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].mac_lower
);
11870 bnx2x_set_mac_buf(bp
->phys_port_id
, val
, val2
);
11871 bp
->flags
|= HAS_PHYS_PORT_ID
;
11874 memcpy(bp
->link_params
.mac_addr
, bp
->dev
->dev_addr
, ETH_ALEN
);
11876 if (!is_valid_ether_addr(bp
->dev
->dev_addr
))
11877 dev_err(&bp
->pdev
->dev
,
11878 "bad Ethernet MAC address configuration: %pM\n"
11879 "change it manually before bringing up the appropriate network interface\n",
11880 bp
->dev
->dev_addr
);
11883 static bool bnx2x_get_dropless_info(struct bnx2x
*bp
)
11891 if (IS_MF(bp
) && !CHIP_IS_E1x(bp
)) {
11892 /* Take function: tmp = func */
11893 tmp
= BP_ABS_FUNC(bp
);
11894 cfg
= MF_CFG_RD(bp
, func_ext_config
[tmp
].func_cfg
);
11895 cfg
= !!(cfg
& MACP_FUNC_CFG_PAUSE_ON_HOST_RING
);
11897 /* Take port: tmp = port */
11900 dev_info
.port_hw_config
[tmp
].generic_features
);
11901 cfg
= !!(cfg
& PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED
);
11906 static void validate_set_si_mode(struct bnx2x
*bp
)
11908 u8 func
= BP_ABS_FUNC(bp
);
11911 val
= MF_CFG_RD(bp
, func_mf_config
[func
].mac_upper
);
11913 /* check for legal mac (upper bytes) */
11914 if (val
!= 0xffff) {
11915 bp
->mf_mode
= MULTI_FUNCTION_SI
;
11916 bp
->mf_config
[BP_VN(bp
)] =
11917 MF_CFG_RD(bp
, func_mf_config
[func
].config
);
11919 BNX2X_DEV_INFO("illegal MAC address for SI\n");
11922 static int bnx2x_get_hwinfo(struct bnx2x
*bp
)
11924 int /*abs*/func
= BP_ABS_FUNC(bp
);
11926 u32 val
= 0, val2
= 0;
11929 /* Validate that chip access is feasible */
11930 if (REG_RD(bp
, MISC_REG_CHIP_NUM
) == 0xffffffff) {
11931 dev_err(&bp
->pdev
->dev
,
11932 "Chip read returns all Fs. Preventing probe from continuing\n");
11936 bnx2x_get_common_hwinfo(bp
);
11939 * initialize IGU parameters
11941 if (CHIP_IS_E1x(bp
)) {
11942 bp
->common
.int_block
= INT_BLOCK_HC
;
11944 bp
->igu_dsb_id
= DEF_SB_IGU_ID
;
11945 bp
->igu_base_sb
= 0;
11947 bp
->common
.int_block
= INT_BLOCK_IGU
;
11949 /* do not allow device reset during IGU info processing */
11950 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RESET
);
11952 val
= REG_RD(bp
, IGU_REG_BLOCK_CONFIGURATION
);
11954 if (val
& IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN
) {
11957 BNX2X_DEV_INFO("FORCING Normal Mode\n");
11959 val
&= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN
);
11960 REG_WR(bp
, IGU_REG_BLOCK_CONFIGURATION
, val
);
11961 REG_WR(bp
, IGU_REG_RESET_MEMORIES
, 0x7f);
11963 while (tout
&& REG_RD(bp
, IGU_REG_RESET_MEMORIES
)) {
11965 usleep_range(1000, 2000);
11968 if (REG_RD(bp
, IGU_REG_RESET_MEMORIES
)) {
11969 dev_err(&bp
->pdev
->dev
,
11970 "FORCING Normal Mode failed!!!\n");
11971 bnx2x_release_hw_lock(bp
,
11972 HW_LOCK_RESOURCE_RESET
);
11977 if (val
& IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN
) {
11978 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
11979 bp
->common
.int_block
|= INT_BLOCK_MODE_BW_COMP
;
11981 BNX2X_DEV_INFO("IGU Normal Mode\n");
11983 rc
= bnx2x_get_igu_cam_info(bp
);
11984 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RESET
);
11990 * set base FW non-default (fast path) status block id, this value is
11991 * used to initialize the fw_sb_id saved on the fp/queue structure to
11992 * determine the id used by the FW.
11994 if (CHIP_IS_E1x(bp
))
11995 bp
->base_fw_ndsb
= BP_PORT(bp
) * FP_SB_MAX_E1x
+ BP_L_ID(bp
);
11997 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
11998 * the same queue are indicated on the same IGU SB). So we prefer
11999 * FW and IGU SBs to be the same value.
12001 bp
->base_fw_ndsb
= bp
->igu_base_sb
;
12003 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
12004 "base_fw_ndsb %d\n", bp
->igu_dsb_id
, bp
->igu_base_sb
,
12005 bp
->igu_sb_cnt
, bp
->base_fw_ndsb
);
12008 * Initialize MF configuration
12013 bp
->mf_sub_mode
= 0;
12015 mfw_vn
= BP_FW_MB_IDX(bp
);
12017 if (!CHIP_IS_E1(bp
) && !BP_NOMCP(bp
)) {
12018 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
12019 bp
->common
.shmem2_base
, SHMEM2_RD(bp
, size
),
12020 (u32
)offsetof(struct shmem2_region
, mf_cfg_addr
));
12022 if (SHMEM2_HAS(bp
, mf_cfg_addr
))
12023 bp
->common
.mf_cfg_base
= SHMEM2_RD(bp
, mf_cfg_addr
);
12025 bp
->common
.mf_cfg_base
= bp
->common
.shmem_base
+
12026 offsetof(struct shmem_region
, func_mb
) +
12027 E1H_FUNC_MAX
* sizeof(struct drv_func_mb
);
12029 * get mf configuration:
12030 * 1. Existence of MF configuration
12031 * 2. MAC address must be legal (check only upper bytes)
12032 * for Switch-Independent mode;
12033 * OVLAN must be legal for Switch-Dependent mode
12034 * 3. SF_MODE configures specific MF mode
12036 if (bp
->common
.mf_cfg_base
!= SHMEM_MF_CFG_ADDR_NONE
) {
12037 /* get mf configuration */
12039 dev_info
.shared_feature_config
.config
);
12040 val
&= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK
;
12043 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT
:
12044 validate_set_si_mode(bp
);
12046 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE
:
12047 if ((!CHIP_IS_E1x(bp
)) &&
12048 (MF_CFG_RD(bp
, func_mf_config
[func
].
12049 mac_upper
) != 0xffff) &&
12051 afex_driver_support
))) {
12052 bp
->mf_mode
= MULTI_FUNCTION_AFEX
;
12053 bp
->mf_config
[vn
] = MF_CFG_RD(bp
,
12054 func_mf_config
[func
].config
);
12056 BNX2X_DEV_INFO("can not configure afex mode\n");
12059 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED
:
12060 /* get OV configuration */
12061 val
= MF_CFG_RD(bp
,
12062 func_mf_config
[FUNC_0
].e1hov_tag
);
12063 val
&= FUNC_MF_CFG_E1HOV_TAG_MASK
;
12065 if (val
!= FUNC_MF_CFG_E1HOV_TAG_DEFAULT
) {
12066 bp
->mf_mode
= MULTI_FUNCTION_SD
;
12067 bp
->mf_config
[vn
] = MF_CFG_RD(bp
,
12068 func_mf_config
[func
].config
);
12070 BNX2X_DEV_INFO("illegal OV for SD\n");
12072 case SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE
:
12073 bp
->mf_mode
= MULTI_FUNCTION_SD
;
12074 bp
->mf_sub_mode
= SUB_MF_MODE_BD
;
12075 bp
->mf_config
[vn
] =
12077 func_mf_config
[func
].config
);
12079 if (SHMEM2_HAS(bp
, mtu_size
)) {
12080 int mtu_idx
= BP_FW_MB_IDX(bp
);
12084 mtu
= SHMEM2_RD(bp
, mtu_size
[mtu_idx
]);
12085 mtu_size
= (u16
)mtu
;
12086 DP(NETIF_MSG_IFUP
, "Read MTU size %04x [%08x]\n",
12089 /* if valid: update device mtu */
12090 if ((mtu_size
>= ETH_MIN_PACKET_SIZE
) &&
12092 ETH_MAX_JUMBO_PACKET_SIZE
))
12093 bp
->dev
->mtu
= mtu_size
;
12096 case SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE
:
12097 bp
->mf_mode
= MULTI_FUNCTION_SD
;
12098 bp
->mf_sub_mode
= SUB_MF_MODE_UFP
;
12099 bp
->mf_config
[vn
] =
12101 func_mf_config
[func
].config
);
12103 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF
:
12104 bp
->mf_config
[vn
] = 0;
12106 case SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE
:
12107 val2
= SHMEM_RD(bp
,
12108 dev_info
.shared_hw_config
.config_3
);
12109 val2
&= SHARED_HW_CFG_EXTENDED_MF_MODE_MASK
;
12111 case SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5
:
12112 validate_set_si_mode(bp
);
12114 SUB_MF_MODE_NPAR1_DOT_5
;
12117 /* Unknown configuration */
12118 bp
->mf_config
[vn
] = 0;
12119 BNX2X_DEV_INFO("unknown extended MF mode 0x%x\n",
12124 /* Unknown configuration: reset mf_config */
12125 bp
->mf_config
[vn
] = 0;
12126 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val
);
12130 BNX2X_DEV_INFO("%s function mode\n",
12131 IS_MF(bp
) ? "multi" : "single");
12133 switch (bp
->mf_mode
) {
12134 case MULTI_FUNCTION_SD
:
12135 val
= MF_CFG_RD(bp
, func_mf_config
[func
].e1hov_tag
) &
12136 FUNC_MF_CFG_E1HOV_TAG_MASK
;
12137 if (val
!= FUNC_MF_CFG_E1HOV_TAG_DEFAULT
) {
12139 bp
->path_has_ovlan
= true;
12141 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
12142 func
, bp
->mf_ov
, bp
->mf_ov
);
12143 } else if ((bp
->mf_sub_mode
== SUB_MF_MODE_UFP
) ||
12144 (bp
->mf_sub_mode
== SUB_MF_MODE_BD
)) {
12145 dev_err(&bp
->pdev
->dev
,
12146 "Unexpected - no valid MF OV for func %d in UFP/BD mode\n",
12148 bp
->path_has_ovlan
= true;
12150 dev_err(&bp
->pdev
->dev
,
12151 "No valid MF OV for func %d, aborting\n",
12156 case MULTI_FUNCTION_AFEX
:
12157 BNX2X_DEV_INFO("func %d is in MF afex mode\n", func
);
12159 case MULTI_FUNCTION_SI
:
12160 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
12165 dev_err(&bp
->pdev
->dev
,
12166 "VN %d is in a single function mode, aborting\n",
12173 /* check if other port on the path needs ovlan:
12174 * Since MF configuration is shared between ports
12175 * Possible mixed modes are only
12176 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
12178 if (CHIP_MODE_IS_4_PORT(bp
) &&
12179 !bp
->path_has_ovlan
&&
12181 bp
->common
.mf_cfg_base
!= SHMEM_MF_CFG_ADDR_NONE
) {
12182 u8 other_port
= !BP_PORT(bp
);
12183 u8 other_func
= BP_PATH(bp
) + 2*other_port
;
12184 val
= MF_CFG_RD(bp
,
12185 func_mf_config
[other_func
].e1hov_tag
);
12186 if (val
!= FUNC_MF_CFG_E1HOV_TAG_DEFAULT
)
12187 bp
->path_has_ovlan
= true;
12191 /* adjust igu_sb_cnt to MF for E1H */
12192 if (CHIP_IS_E1H(bp
) && IS_MF(bp
))
12193 bp
->igu_sb_cnt
= min_t(u8
, bp
->igu_sb_cnt
, E1H_MAX_MF_SB_COUNT
);
12196 bnx2x_get_port_hwinfo(bp
);
12198 /* Get MAC addresses */
12199 bnx2x_get_mac_hwinfo(bp
);
12201 bnx2x_get_cnic_info(bp
);
12206 static void bnx2x_read_fwinfo(struct bnx2x
*bp
)
12208 int cnt
, i
, block_end
, rodi
;
12209 char vpd_start
[BNX2X_VPD_LEN
+1];
12210 char str_id_reg
[VENDOR_ID_LEN
+1];
12211 char str_id_cap
[VENDOR_ID_LEN
+1];
12213 char *vpd_extended_data
= NULL
;
12216 cnt
= pci_read_vpd(bp
->pdev
, 0, BNX2X_VPD_LEN
, vpd_start
);
12217 memset(bp
->fw_ver
, 0, sizeof(bp
->fw_ver
));
12219 if (cnt
< BNX2X_VPD_LEN
)
12220 goto out_not_found
;
12222 /* VPD RO tag should be first tag after identifier string, hence
12223 * we should be able to find it in first BNX2X_VPD_LEN chars
12225 i
= pci_vpd_find_tag(vpd_start
, 0, BNX2X_VPD_LEN
,
12226 PCI_VPD_LRDT_RO_DATA
);
12228 goto out_not_found
;
12230 block_end
= i
+ PCI_VPD_LRDT_TAG_SIZE
+
12231 pci_vpd_lrdt_size(&vpd_start
[i
]);
12233 i
+= PCI_VPD_LRDT_TAG_SIZE
;
12235 if (block_end
> BNX2X_VPD_LEN
) {
12236 vpd_extended_data
= kmalloc(block_end
, GFP_KERNEL
);
12237 if (vpd_extended_data
== NULL
)
12238 goto out_not_found
;
12240 /* read rest of vpd image into vpd_extended_data */
12241 memcpy(vpd_extended_data
, vpd_start
, BNX2X_VPD_LEN
);
12242 cnt
= pci_read_vpd(bp
->pdev
, BNX2X_VPD_LEN
,
12243 block_end
- BNX2X_VPD_LEN
,
12244 vpd_extended_data
+ BNX2X_VPD_LEN
);
12245 if (cnt
< (block_end
- BNX2X_VPD_LEN
))
12246 goto out_not_found
;
12247 vpd_data
= vpd_extended_data
;
12249 vpd_data
= vpd_start
;
12251 /* now vpd_data holds full vpd content in both cases */
12253 rodi
= pci_vpd_find_info_keyword(vpd_data
, i
, block_end
,
12254 PCI_VPD_RO_KEYWORD_MFR_ID
);
12256 goto out_not_found
;
12258 len
= pci_vpd_info_field_size(&vpd_data
[rodi
]);
12260 if (len
!= VENDOR_ID_LEN
)
12261 goto out_not_found
;
12263 rodi
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
12265 /* vendor specific info */
12266 snprintf(str_id_reg
, VENDOR_ID_LEN
+ 1, "%04x", PCI_VENDOR_ID_DELL
);
12267 snprintf(str_id_cap
, VENDOR_ID_LEN
+ 1, "%04X", PCI_VENDOR_ID_DELL
);
12268 if (!strncmp(str_id_reg
, &vpd_data
[rodi
], VENDOR_ID_LEN
) ||
12269 !strncmp(str_id_cap
, &vpd_data
[rodi
], VENDOR_ID_LEN
)) {
12271 rodi
= pci_vpd_find_info_keyword(vpd_data
, i
, block_end
,
12272 PCI_VPD_RO_KEYWORD_VENDOR0
);
12274 len
= pci_vpd_info_field_size(&vpd_data
[rodi
]);
12276 rodi
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
12278 if (len
< 32 && (len
+ rodi
) <= BNX2X_VPD_LEN
) {
12279 memcpy(bp
->fw_ver
, &vpd_data
[rodi
], len
);
12280 bp
->fw_ver
[len
] = ' ';
12283 kfree(vpd_extended_data
);
12287 kfree(vpd_extended_data
);
12291 static void bnx2x_set_modes_bitmap(struct bnx2x
*bp
)
12295 if (CHIP_REV_IS_FPGA(bp
))
12296 SET_FLAGS(flags
, MODE_FPGA
);
12297 else if (CHIP_REV_IS_EMUL(bp
))
12298 SET_FLAGS(flags
, MODE_EMUL
);
12300 SET_FLAGS(flags
, MODE_ASIC
);
12302 if (CHIP_MODE_IS_4_PORT(bp
))
12303 SET_FLAGS(flags
, MODE_PORT4
);
12305 SET_FLAGS(flags
, MODE_PORT2
);
12307 if (CHIP_IS_E2(bp
))
12308 SET_FLAGS(flags
, MODE_E2
);
12309 else if (CHIP_IS_E3(bp
)) {
12310 SET_FLAGS(flags
, MODE_E3
);
12311 if (CHIP_REV(bp
) == CHIP_REV_Ax
)
12312 SET_FLAGS(flags
, MODE_E3_A0
);
12313 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
12314 SET_FLAGS(flags
, MODE_E3_B0
| MODE_COS3
);
12318 SET_FLAGS(flags
, MODE_MF
);
12319 switch (bp
->mf_mode
) {
12320 case MULTI_FUNCTION_SD
:
12321 SET_FLAGS(flags
, MODE_MF_SD
);
12323 case MULTI_FUNCTION_SI
:
12324 SET_FLAGS(flags
, MODE_MF_SI
);
12326 case MULTI_FUNCTION_AFEX
:
12327 SET_FLAGS(flags
, MODE_MF_AFEX
);
12331 SET_FLAGS(flags
, MODE_SF
);
12333 #if defined(__LITTLE_ENDIAN)
12334 SET_FLAGS(flags
, MODE_LITTLE_ENDIAN
);
12335 #else /*(__BIG_ENDIAN)*/
12336 SET_FLAGS(flags
, MODE_BIG_ENDIAN
);
12338 INIT_MODE_FLAGS(bp
) = flags
;
12341 static int bnx2x_init_bp(struct bnx2x
*bp
)
12346 mutex_init(&bp
->port
.phy_mutex
);
12347 mutex_init(&bp
->fw_mb_mutex
);
12348 mutex_init(&bp
->drv_info_mutex
);
12349 sema_init(&bp
->stats_lock
, 1);
12350 bp
->drv_info_mng_owner
= false;
12351 INIT_LIST_HEAD(&bp
->vlan_reg
);
12353 INIT_DELAYED_WORK(&bp
->sp_task
, bnx2x_sp_task
);
12354 INIT_DELAYED_WORK(&bp
->sp_rtnl_task
, bnx2x_sp_rtnl_task
);
12355 INIT_DELAYED_WORK(&bp
->period_task
, bnx2x_period_task
);
12356 INIT_DELAYED_WORK(&bp
->iov_task
, bnx2x_iov_task
);
12358 rc
= bnx2x_get_hwinfo(bp
);
12362 eth_zero_addr(bp
->dev
->dev_addr
);
12365 bnx2x_set_modes_bitmap(bp
);
12367 rc
= bnx2x_alloc_mem_bp(bp
);
12371 bnx2x_read_fwinfo(bp
);
12373 func
= BP_FUNC(bp
);
12375 /* need to reset chip if undi was active */
12376 if (IS_PF(bp
) && !BP_NOMCP(bp
)) {
12379 SHMEM_RD(bp
, func_mb
[BP_FW_MB_IDX(bp
)].drv_mb_header
) &
12380 DRV_MSG_SEQ_NUMBER_MASK
;
12381 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp
->fw_seq
);
12383 rc
= bnx2x_prev_unload(bp
);
12385 bnx2x_free_mem_bp(bp
);
12390 if (CHIP_REV_IS_FPGA(bp
))
12391 dev_err(&bp
->pdev
->dev
, "FPGA detected\n");
12393 if (BP_NOMCP(bp
) && (func
== 0))
12394 dev_err(&bp
->pdev
->dev
, "MCP disabled, must load devices in order!\n");
12396 bp
->disable_tpa
= disable_tpa
;
12397 bp
->disable_tpa
|= !!IS_MF_STORAGE_ONLY(bp
);
12398 /* Reduce memory usage in kdump environment by disabling TPA */
12399 bp
->disable_tpa
|= is_kdump_kernel();
12401 /* Set TPA flags */
12402 if (bp
->disable_tpa
) {
12403 bp
->dev
->hw_features
&= ~NETIF_F_LRO
;
12404 bp
->dev
->features
&= ~NETIF_F_LRO
;
12407 if (CHIP_IS_E1(bp
))
12408 bp
->dropless_fc
= 0;
12410 bp
->dropless_fc
= dropless_fc
| bnx2x_get_dropless_info(bp
);
12414 bp
->tx_ring_size
= IS_MF_STORAGE_ONLY(bp
) ? 0 : MAX_TX_AVAIL
;
12416 bp
->rx_ring_size
= MAX_RX_AVAIL
;
12418 /* make sure that the numbers are in the right granularity */
12419 bp
->tx_ticks
= (50 / BNX2X_BTR
) * BNX2X_BTR
;
12420 bp
->rx_ticks
= (25 / BNX2X_BTR
) * BNX2X_BTR
;
12422 bp
->current_interval
= CHIP_REV_IS_SLOW(bp
) ? 5*HZ
: HZ
;
12424 timer_setup(&bp
->timer
, bnx2x_timer
, 0);
12425 bp
->timer
.expires
= jiffies
+ bp
->current_interval
;
12427 if (SHMEM2_HAS(bp
, dcbx_lldp_params_offset
) &&
12428 SHMEM2_HAS(bp
, dcbx_lldp_dcbx_stat_offset
) &&
12429 SHMEM2_HAS(bp
, dcbx_en
) &&
12430 SHMEM2_RD(bp
, dcbx_lldp_params_offset
) &&
12431 SHMEM2_RD(bp
, dcbx_lldp_dcbx_stat_offset
) &&
12432 SHMEM2_RD(bp
, dcbx_en
[BP_PORT(bp
)])) {
12433 bnx2x_dcbx_set_state(bp
, true, BNX2X_DCBX_ENABLED_ON_NEG_ON
);
12434 bnx2x_dcbx_init_params(bp
);
12436 bnx2x_dcbx_set_state(bp
, false, BNX2X_DCBX_ENABLED_OFF
);
12439 if (CHIP_IS_E1x(bp
))
12440 bp
->cnic_base_cl_id
= FP_SB_MAX_E1x
;
12442 bp
->cnic_base_cl_id
= FP_SB_MAX_E2
;
12444 /* multiple tx priority */
12447 else if (CHIP_IS_E1x(bp
))
12448 bp
->max_cos
= BNX2X_MULTI_TX_COS_E1X
;
12449 else if (CHIP_IS_E2(bp
) || CHIP_IS_E3A0(bp
))
12450 bp
->max_cos
= BNX2X_MULTI_TX_COS_E2_E3A0
;
12451 else if (CHIP_IS_E3B0(bp
))
12452 bp
->max_cos
= BNX2X_MULTI_TX_COS_E3B0
;
12454 BNX2X_ERR("unknown chip %x revision %x\n",
12455 CHIP_NUM(bp
), CHIP_REV(bp
));
12456 BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp
->max_cos
);
12458 /* We need at least one default status block for slow-path events,
12459 * second status block for the L2 queue, and a third status block for
12460 * CNIC if supported.
12463 bp
->min_msix_vec_cnt
= 1;
12464 else if (CNIC_SUPPORT(bp
))
12465 bp
->min_msix_vec_cnt
= 3;
12466 else /* PF w/o cnic */
12467 bp
->min_msix_vec_cnt
= 2;
12468 BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp
->min_msix_vec_cnt
);
12470 bp
->dump_preset_idx
= 1;
12472 if (CHIP_IS_E3B0(bp
))
12473 bp
->flags
|= PTP_SUPPORTED
;
12478 /****************************************************************************
12479 * General service functions
12480 ****************************************************************************/
12483 * net_device service functions
12486 /* called with rtnl_lock */
12487 static int bnx2x_open(struct net_device
*dev
)
12489 struct bnx2x
*bp
= netdev_priv(dev
);
12492 bp
->stats_init
= true;
12494 netif_carrier_off(dev
);
12496 bnx2x_set_power_state(bp
, PCI_D0
);
12498 /* If parity had happen during the unload, then attentions
12499 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
12500 * want the first function loaded on the current engine to
12501 * complete the recovery.
12502 * Parity recovery is only relevant for PF driver.
12505 int other_engine
= BP_PATH(bp
) ? 0 : 1;
12506 bool other_load_status
, load_status
;
12507 bool global
= false;
12509 other_load_status
= bnx2x_get_load_status(bp
, other_engine
);
12510 load_status
= bnx2x_get_load_status(bp
, BP_PATH(bp
));
12511 if (!bnx2x_reset_is_done(bp
, BP_PATH(bp
)) ||
12512 bnx2x_chk_parity_attn(bp
, &global
, true)) {
12514 /* If there are attentions and they are in a
12515 * global blocks, set the GLOBAL_RESET bit
12516 * regardless whether it will be this function
12517 * that will complete the recovery or not.
12520 bnx2x_set_reset_global(bp
);
12522 /* Only the first function on the current
12523 * engine should try to recover in open. In case
12524 * of attentions in global blocks only the first
12525 * in the chip should try to recover.
12527 if ((!load_status
&&
12528 (!global
|| !other_load_status
)) &&
12529 bnx2x_trylock_leader_lock(bp
) &&
12530 !bnx2x_leader_reset(bp
)) {
12531 netdev_info(bp
->dev
,
12532 "Recovered in open\n");
12536 /* recovery has failed... */
12537 bnx2x_set_power_state(bp
, PCI_D3hot
);
12538 bp
->recovery_state
= BNX2X_RECOVERY_FAILED
;
12540 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
12541 "If you still see this message after a few retries then power cycle is required.\n");
12548 bp
->recovery_state
= BNX2X_RECOVERY_DONE
;
12549 rc
= bnx2x_nic_load(bp
, LOAD_OPEN
);
12554 udp_tunnel_get_rx_info(dev
);
12559 /* called with rtnl_lock */
12560 static int bnx2x_close(struct net_device
*dev
)
12562 struct bnx2x
*bp
= netdev_priv(dev
);
12564 /* Unload the driver, release IRQs */
12565 bnx2x_nic_unload(bp
, UNLOAD_CLOSE
, false);
12570 struct bnx2x_mcast_list_elem_group
12572 struct list_head mcast_group_link
;
12573 struct bnx2x_mcast_list_elem mcast_elems
[];
12576 #define MCAST_ELEMS_PER_PG \
12577 ((PAGE_SIZE - sizeof(struct bnx2x_mcast_list_elem_group)) / \
12578 sizeof(struct bnx2x_mcast_list_elem))
12580 static void bnx2x_free_mcast_macs_list(struct list_head
*mcast_group_list
)
12582 struct bnx2x_mcast_list_elem_group
*current_mcast_group
;
12584 while (!list_empty(mcast_group_list
)) {
12585 current_mcast_group
= list_first_entry(mcast_group_list
,
12586 struct bnx2x_mcast_list_elem_group
,
12588 list_del(¤t_mcast_group
->mcast_group_link
);
12589 free_page((unsigned long)current_mcast_group
);
12593 static int bnx2x_init_mcast_macs_list(struct bnx2x
*bp
,
12594 struct bnx2x_mcast_ramrod_params
*p
,
12595 struct list_head
*mcast_group_list
)
12597 struct bnx2x_mcast_list_elem
*mc_mac
;
12598 struct netdev_hw_addr
*ha
;
12599 struct bnx2x_mcast_list_elem_group
*current_mcast_group
= NULL
;
12600 int mc_count
= netdev_mc_count(bp
->dev
);
12603 INIT_LIST_HEAD(&p
->mcast_list
);
12604 netdev_for_each_mc_addr(ha
, bp
->dev
) {
12606 current_mcast_group
=
12607 (struct bnx2x_mcast_list_elem_group
*)
12608 __get_free_page(GFP_ATOMIC
);
12609 if (!current_mcast_group
) {
12610 bnx2x_free_mcast_macs_list(mcast_group_list
);
12611 BNX2X_ERR("Failed to allocate mc MAC list\n");
12614 list_add(¤t_mcast_group
->mcast_group_link
,
12617 mc_mac
= ¤t_mcast_group
->mcast_elems
[offset
];
12618 mc_mac
->mac
= bnx2x_mc_addr(ha
);
12619 list_add_tail(&mc_mac
->link
, &p
->mcast_list
);
12621 if (offset
== MCAST_ELEMS_PER_PG
)
12624 p
->mcast_list_len
= mc_count
;
12629 * bnx2x_set_uc_list - configure a new unicast MACs list.
12631 * @bp: driver handle
12633 * We will use zero (0) as a MAC type for these MACs.
12635 static int bnx2x_set_uc_list(struct bnx2x
*bp
)
12638 struct net_device
*dev
= bp
->dev
;
12639 struct netdev_hw_addr
*ha
;
12640 struct bnx2x_vlan_mac_obj
*mac_obj
= &bp
->sp_objs
->mac_obj
;
12641 unsigned long ramrod_flags
= 0;
12643 /* First schedule a cleanup up of old configuration */
12644 rc
= bnx2x_del_all_macs(bp
, mac_obj
, BNX2X_UC_LIST_MAC
, false);
12646 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc
);
12650 netdev_for_each_uc_addr(ha
, dev
) {
12651 rc
= bnx2x_set_mac_one(bp
, bnx2x_uc_addr(ha
), mac_obj
, true,
12652 BNX2X_UC_LIST_MAC
, &ramrod_flags
);
12653 if (rc
== -EEXIST
) {
12655 "Failed to schedule ADD operations: %d\n", rc
);
12656 /* do not treat adding same MAC as error */
12659 } else if (rc
< 0) {
12661 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
12667 /* Execute the pending commands */
12668 __set_bit(RAMROD_CONT
, &ramrod_flags
);
12669 return bnx2x_set_mac_one(bp
, NULL
, mac_obj
, false /* don't care */,
12670 BNX2X_UC_LIST_MAC
, &ramrod_flags
);
12673 static int bnx2x_set_mc_list_e1x(struct bnx2x
*bp
)
12675 LIST_HEAD(mcast_group_list
);
12676 struct net_device
*dev
= bp
->dev
;
12677 struct bnx2x_mcast_ramrod_params rparam
= {NULL
};
12680 rparam
.mcast_obj
= &bp
->mcast_obj
;
12682 /* first, clear all configured multicast MACs */
12683 rc
= bnx2x_config_mcast(bp
, &rparam
, BNX2X_MCAST_CMD_DEL
);
12685 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc
);
12689 /* then, configure a new MACs list */
12690 if (netdev_mc_count(dev
)) {
12691 rc
= bnx2x_init_mcast_macs_list(bp
, &rparam
, &mcast_group_list
);
12695 /* Now add the new MACs */
12696 rc
= bnx2x_config_mcast(bp
, &rparam
,
12697 BNX2X_MCAST_CMD_ADD
);
12699 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
12702 bnx2x_free_mcast_macs_list(&mcast_group_list
);
12708 static int bnx2x_set_mc_list(struct bnx2x
*bp
)
12710 LIST_HEAD(mcast_group_list
);
12711 struct bnx2x_mcast_ramrod_params rparam
= {NULL
};
12712 struct net_device
*dev
= bp
->dev
;
12715 /* On older adapters, we need to flush and re-add filters */
12716 if (CHIP_IS_E1x(bp
))
12717 return bnx2x_set_mc_list_e1x(bp
);
12719 rparam
.mcast_obj
= &bp
->mcast_obj
;
12721 if (netdev_mc_count(dev
)) {
12722 rc
= bnx2x_init_mcast_macs_list(bp
, &rparam
, &mcast_group_list
);
12726 /* Override the curently configured set of mc filters */
12727 rc
= bnx2x_config_mcast(bp
, &rparam
,
12728 BNX2X_MCAST_CMD_SET
);
12730 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
12733 bnx2x_free_mcast_macs_list(&mcast_group_list
);
12735 /* If no mc addresses are required, flush the configuration */
12736 rc
= bnx2x_config_mcast(bp
, &rparam
, BNX2X_MCAST_CMD_DEL
);
12738 BNX2X_ERR("Failed to clear multicast configuration %d\n",
12745 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
12746 static void bnx2x_set_rx_mode(struct net_device
*dev
)
12748 struct bnx2x
*bp
= netdev_priv(dev
);
12750 if (bp
->state
!= BNX2X_STATE_OPEN
) {
12751 DP(NETIF_MSG_IFUP
, "state is %x, returning\n", bp
->state
);
12754 /* Schedule an SP task to handle rest of change */
12755 bnx2x_schedule_sp_rtnl(bp
, BNX2X_SP_RTNL_RX_MODE
,
12760 void bnx2x_set_rx_mode_inner(struct bnx2x
*bp
)
12762 u32 rx_mode
= BNX2X_RX_MODE_NORMAL
;
12764 DP(NETIF_MSG_IFUP
, "dev->flags = %x\n", bp
->dev
->flags
);
12766 netif_addr_lock_bh(bp
->dev
);
12768 if (bp
->dev
->flags
& IFF_PROMISC
) {
12769 rx_mode
= BNX2X_RX_MODE_PROMISC
;
12770 } else if ((bp
->dev
->flags
& IFF_ALLMULTI
) ||
12771 ((netdev_mc_count(bp
->dev
) > BNX2X_MAX_MULTICAST
) &&
12773 rx_mode
= BNX2X_RX_MODE_ALLMULTI
;
12776 /* some multicasts */
12777 if (bnx2x_set_mc_list(bp
) < 0)
12778 rx_mode
= BNX2X_RX_MODE_ALLMULTI
;
12780 /* release bh lock, as bnx2x_set_uc_list might sleep */
12781 netif_addr_unlock_bh(bp
->dev
);
12782 if (bnx2x_set_uc_list(bp
) < 0)
12783 rx_mode
= BNX2X_RX_MODE_PROMISC
;
12784 netif_addr_lock_bh(bp
->dev
);
12786 /* configuring mcast to a vf involves sleeping (when we
12787 * wait for the pf's response).
12789 bnx2x_schedule_sp_rtnl(bp
,
12790 BNX2X_SP_RTNL_VFPF_MCAST
, 0);
12794 bp
->rx_mode
= rx_mode
;
12795 /* handle ISCSI SD mode */
12796 if (IS_MF_ISCSI_ONLY(bp
))
12797 bp
->rx_mode
= BNX2X_RX_MODE_NONE
;
12799 /* Schedule the rx_mode command */
12800 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING
, &bp
->sp_state
)) {
12801 set_bit(BNX2X_FILTER_RX_MODE_SCHED
, &bp
->sp_state
);
12802 netif_addr_unlock_bh(bp
->dev
);
12807 bnx2x_set_storm_rx_mode(bp
);
12808 netif_addr_unlock_bh(bp
->dev
);
12810 /* VF will need to request the PF to make this change, and so
12811 * the VF needs to release the bottom-half lock prior to the
12812 * request (as it will likely require sleep on the VF side)
12814 netif_addr_unlock_bh(bp
->dev
);
12815 bnx2x_vfpf_storm_rx_mode(bp
);
12819 /* called with rtnl_lock */
12820 static int bnx2x_mdio_read(struct net_device
*netdev
, int prtad
,
12821 int devad
, u16 addr
)
12823 struct bnx2x
*bp
= netdev_priv(netdev
);
12827 DP(NETIF_MSG_LINK
, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
12828 prtad
, devad
, addr
);
12830 /* The HW expects different devad if CL22 is used */
12831 devad
= (devad
== MDIO_DEVAD_NONE
) ? DEFAULT_PHY_DEV_ADDR
: devad
;
12833 bnx2x_acquire_phy_lock(bp
);
12834 rc
= bnx2x_phy_read(&bp
->link_params
, prtad
, devad
, addr
, &value
);
12835 bnx2x_release_phy_lock(bp
);
12836 DP(NETIF_MSG_LINK
, "mdio_read_val 0x%x rc = 0x%x\n", value
, rc
);
12843 /* called with rtnl_lock */
12844 static int bnx2x_mdio_write(struct net_device
*netdev
, int prtad
, int devad
,
12845 u16 addr
, u16 value
)
12847 struct bnx2x
*bp
= netdev_priv(netdev
);
12851 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
12852 prtad
, devad
, addr
, value
);
12854 /* The HW expects different devad if CL22 is used */
12855 devad
= (devad
== MDIO_DEVAD_NONE
) ? DEFAULT_PHY_DEV_ADDR
: devad
;
12857 bnx2x_acquire_phy_lock(bp
);
12858 rc
= bnx2x_phy_write(&bp
->link_params
, prtad
, devad
, addr
, value
);
12859 bnx2x_release_phy_lock(bp
);
12863 /* called with rtnl_lock */
12864 static int bnx2x_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
12866 struct bnx2x
*bp
= netdev_priv(dev
);
12867 struct mii_ioctl_data
*mdio
= if_mii(ifr
);
12869 if (!netif_running(dev
))
12873 case SIOCSHWTSTAMP
:
12874 return bnx2x_hwtstamp_ioctl(bp
, ifr
);
12876 DP(NETIF_MSG_LINK
, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
12877 mdio
->phy_id
, mdio
->reg_num
, mdio
->val_in
);
12878 return mdio_mii_ioctl(&bp
->mdio
, mdio
, cmd
);
12882 #ifdef CONFIG_NET_POLL_CONTROLLER
12883 static void poll_bnx2x(struct net_device
*dev
)
12885 struct bnx2x
*bp
= netdev_priv(dev
);
12888 for_each_eth_queue(bp
, i
) {
12889 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
12890 napi_schedule(&bnx2x_fp(bp
, fp
->index
, napi
));
12895 static int bnx2x_validate_addr(struct net_device
*dev
)
12897 struct bnx2x
*bp
= netdev_priv(dev
);
12899 /* query the bulletin board for mac address configured by the PF */
12901 bnx2x_sample_bulletin(bp
);
12903 if (!is_valid_ether_addr(dev
->dev_addr
)) {
12904 BNX2X_ERR("Non-valid Ethernet address\n");
12905 return -EADDRNOTAVAIL
;
12910 static int bnx2x_get_phys_port_id(struct net_device
*netdev
,
12911 struct netdev_phys_item_id
*ppid
)
12913 struct bnx2x
*bp
= netdev_priv(netdev
);
12915 if (!(bp
->flags
& HAS_PHYS_PORT_ID
))
12916 return -EOPNOTSUPP
;
12918 ppid
->id_len
= sizeof(bp
->phys_port_id
);
12919 memcpy(ppid
->id
, bp
->phys_port_id
, ppid
->id_len
);
12924 static netdev_features_t
bnx2x_features_check(struct sk_buff
*skb
,
12925 struct net_device
*dev
,
12926 netdev_features_t features
)
12928 features
= vlan_features_check(skb
, features
);
12929 return vxlan_features_check(skb
, features
);
12932 static int __bnx2x_vlan_configure_vid(struct bnx2x
*bp
, u16 vid
, bool add
)
12937 unsigned long ramrod_flags
= 0;
12939 __set_bit(RAMROD_COMP_WAIT
, &ramrod_flags
);
12940 rc
= bnx2x_set_vlan_one(bp
, vid
, &bp
->sp_objs
->vlan_obj
,
12941 add
, &ramrod_flags
);
12943 rc
= bnx2x_vfpf_update_vlan(bp
, vid
, bp
->fp
->index
, add
);
12949 static int bnx2x_vlan_configure_vid_list(struct bnx2x
*bp
)
12951 struct bnx2x_vlan_entry
*vlan
;
12954 /* Configure all non-configured entries */
12955 list_for_each_entry(vlan
, &bp
->vlan_reg
, link
) {
12959 if (bp
->vlan_cnt
>= bp
->vlan_credit
)
12962 rc
= __bnx2x_vlan_configure_vid(bp
, vlan
->vid
, true);
12964 BNX2X_ERR("Unable to config VLAN %d\n", vlan
->vid
);
12968 DP(NETIF_MSG_IFUP
, "HW configured for VLAN %d\n", vlan
->vid
);
12976 static void bnx2x_vlan_configure(struct bnx2x
*bp
, bool set_rx_mode
)
12978 bool need_accept_any_vlan
;
12980 need_accept_any_vlan
= !!bnx2x_vlan_configure_vid_list(bp
);
12982 if (bp
->accept_any_vlan
!= need_accept_any_vlan
) {
12983 bp
->accept_any_vlan
= need_accept_any_vlan
;
12984 DP(NETIF_MSG_IFUP
, "Accept all VLAN %s\n",
12985 bp
->accept_any_vlan
? "raised" : "cleared");
12988 bnx2x_set_rx_mode_inner(bp
);
12990 bnx2x_vfpf_storm_rx_mode(bp
);
12995 int bnx2x_vlan_reconfigure_vid(struct bnx2x
*bp
)
12997 struct bnx2x_vlan_entry
*vlan
;
12999 /* The hw forgot all entries after reload */
13000 list_for_each_entry(vlan
, &bp
->vlan_reg
, link
)
13004 /* Don't set rx mode here. Our caller will do it. */
13005 bnx2x_vlan_configure(bp
, false);
13010 static int bnx2x_vlan_rx_add_vid(struct net_device
*dev
, __be16 proto
, u16 vid
)
13012 struct bnx2x
*bp
= netdev_priv(dev
);
13013 struct bnx2x_vlan_entry
*vlan
;
13015 DP(NETIF_MSG_IFUP
, "Adding VLAN %d\n", vid
);
13017 vlan
= kmalloc(sizeof(*vlan
), GFP_KERNEL
);
13023 list_add_tail(&vlan
->link
, &bp
->vlan_reg
);
13025 if (netif_running(dev
))
13026 bnx2x_vlan_configure(bp
, true);
13031 static int bnx2x_vlan_rx_kill_vid(struct net_device
*dev
, __be16 proto
, u16 vid
)
13033 struct bnx2x
*bp
= netdev_priv(dev
);
13034 struct bnx2x_vlan_entry
*vlan
;
13035 bool found
= false;
13038 DP(NETIF_MSG_IFUP
, "Removing VLAN %d\n", vid
);
13040 list_for_each_entry(vlan
, &bp
->vlan_reg
, link
)
13041 if (vlan
->vid
== vid
) {
13047 BNX2X_ERR("Unable to kill VLAN %d - not found\n", vid
);
13051 if (netif_running(dev
) && vlan
->hw
) {
13052 rc
= __bnx2x_vlan_configure_vid(bp
, vid
, false);
13053 DP(NETIF_MSG_IFUP
, "HW deconfigured for VLAN %d\n", vid
);
13057 list_del(&vlan
->link
);
13060 if (netif_running(dev
))
13061 bnx2x_vlan_configure(bp
, true);
13063 DP(NETIF_MSG_IFUP
, "Removing VLAN result %d\n", rc
);
13068 static const struct net_device_ops bnx2x_netdev_ops
= {
13069 .ndo_open
= bnx2x_open
,
13070 .ndo_stop
= bnx2x_close
,
13071 .ndo_start_xmit
= bnx2x_start_xmit
,
13072 .ndo_select_queue
= bnx2x_select_queue
,
13073 .ndo_set_rx_mode
= bnx2x_set_rx_mode
,
13074 .ndo_set_mac_address
= bnx2x_change_mac_addr
,
13075 .ndo_validate_addr
= bnx2x_validate_addr
,
13076 .ndo_do_ioctl
= bnx2x_ioctl
,
13077 .ndo_change_mtu
= bnx2x_change_mtu
,
13078 .ndo_fix_features
= bnx2x_fix_features
,
13079 .ndo_set_features
= bnx2x_set_features
,
13080 .ndo_tx_timeout
= bnx2x_tx_timeout
,
13081 .ndo_vlan_rx_add_vid
= bnx2x_vlan_rx_add_vid
,
13082 .ndo_vlan_rx_kill_vid
= bnx2x_vlan_rx_kill_vid
,
13083 #ifdef CONFIG_NET_POLL_CONTROLLER
13084 .ndo_poll_controller
= poll_bnx2x
,
13086 .ndo_setup_tc
= __bnx2x_setup_tc
,
13087 #ifdef CONFIG_BNX2X_SRIOV
13088 .ndo_set_vf_mac
= bnx2x_set_vf_mac
,
13089 .ndo_set_vf_vlan
= bnx2x_set_vf_vlan
,
13090 .ndo_get_vf_config
= bnx2x_get_vf_config
,
13092 #ifdef NETDEV_FCOE_WWNN
13093 .ndo_fcoe_get_wwn
= bnx2x_fcoe_get_wwn
,
13096 .ndo_get_phys_port_id
= bnx2x_get_phys_port_id
,
13097 .ndo_set_vf_link_state
= bnx2x_set_vf_link_state
,
13098 .ndo_features_check
= bnx2x_features_check
,
13099 .ndo_udp_tunnel_add
= bnx2x_udp_tunnel_add
,
13100 .ndo_udp_tunnel_del
= bnx2x_udp_tunnel_del
,
13103 static int bnx2x_set_coherency_mask(struct bnx2x
*bp
)
13105 struct device
*dev
= &bp
->pdev
->dev
;
13107 if (dma_set_mask_and_coherent(dev
, DMA_BIT_MASK(64)) != 0 &&
13108 dma_set_mask_and_coherent(dev
, DMA_BIT_MASK(32)) != 0) {
13109 dev_err(dev
, "System does not support DMA, aborting\n");
13116 static void bnx2x_disable_pcie_error_reporting(struct bnx2x
*bp
)
13118 if (bp
->flags
& AER_ENABLED
) {
13119 pci_disable_pcie_error_reporting(bp
->pdev
);
13120 bp
->flags
&= ~AER_ENABLED
;
13124 static int bnx2x_init_dev(struct bnx2x
*bp
, struct pci_dev
*pdev
,
13125 struct net_device
*dev
, unsigned long board_type
)
13129 bool chip_is_e1x
= (board_type
== BCM57710
||
13130 board_type
== BCM57711
||
13131 board_type
== BCM57711E
);
13133 SET_NETDEV_DEV(dev
, &pdev
->dev
);
13138 rc
= pci_enable_device(pdev
);
13140 dev_err(&bp
->pdev
->dev
,
13141 "Cannot enable PCI device, aborting\n");
13145 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
13146 dev_err(&bp
->pdev
->dev
,
13147 "Cannot find PCI device base address, aborting\n");
13149 goto err_out_disable
;
13152 if (IS_PF(bp
) && !(pci_resource_flags(pdev
, 2) & IORESOURCE_MEM
)) {
13153 dev_err(&bp
->pdev
->dev
, "Cannot find second PCI device base address, aborting\n");
13155 goto err_out_disable
;
13158 pci_read_config_dword(pdev
, PCICFG_REVISION_ID_OFFSET
, &pci_cfg_dword
);
13159 if ((pci_cfg_dword
& PCICFG_REVESION_ID_MASK
) ==
13160 PCICFG_REVESION_ID_ERROR_VAL
) {
13161 pr_err("PCI device error, probably due to fan failure, aborting\n");
13163 goto err_out_disable
;
13166 if (atomic_read(&pdev
->enable_cnt
) == 1) {
13167 rc
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
13169 dev_err(&bp
->pdev
->dev
,
13170 "Cannot obtain PCI resources, aborting\n");
13171 goto err_out_disable
;
13174 pci_set_master(pdev
);
13175 pci_save_state(pdev
);
13179 if (!pdev
->pm_cap
) {
13180 dev_err(&bp
->pdev
->dev
,
13181 "Cannot find power management capability, aborting\n");
13183 goto err_out_release
;
13187 if (!pci_is_pcie(pdev
)) {
13188 dev_err(&bp
->pdev
->dev
, "Not PCI Express, aborting\n");
13190 goto err_out_release
;
13193 rc
= bnx2x_set_coherency_mask(bp
);
13195 goto err_out_release
;
13197 dev
->mem_start
= pci_resource_start(pdev
, 0);
13198 dev
->base_addr
= dev
->mem_start
;
13199 dev
->mem_end
= pci_resource_end(pdev
, 0);
13201 dev
->irq
= pdev
->irq
;
13203 bp
->regview
= pci_ioremap_bar(pdev
, 0);
13204 if (!bp
->regview
) {
13205 dev_err(&bp
->pdev
->dev
,
13206 "Cannot map register space, aborting\n");
13208 goto err_out_release
;
13211 /* In E1/E1H use pci device function given by kernel.
13212 * In E2/E3 read physical function from ME register since these chips
13213 * support Physical Device Assignment where kernel BDF maybe arbitrary
13214 * (depending on hypervisor).
13217 bp
->pf_num
= PCI_FUNC(pdev
->devfn
);
13220 pci_read_config_dword(bp
->pdev
,
13221 PCICFG_ME_REGISTER
, &pci_cfg_dword
);
13222 bp
->pf_num
= (u8
)((pci_cfg_dword
& ME_REG_ABS_PF_NUM
) >>
13223 ME_REG_ABS_PF_NUM_SHIFT
);
13225 BNX2X_DEV_INFO("me reg PF num: %d\n", bp
->pf_num
);
13227 /* clean indirect addresses */
13228 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_ADDRESS
,
13229 PCICFG_VENDOR_ID_OFFSET
);
13231 /* Set PCIe reset type to fundamental for EEH recovery */
13232 pdev
->needs_freset
= 1;
13234 /* AER (Advanced Error reporting) configuration */
13235 rc
= pci_enable_pcie_error_reporting(pdev
);
13237 bp
->flags
|= AER_ENABLED
;
13239 BNX2X_DEV_INFO("Failed To configure PCIe AER [%d]\n", rc
);
13242 * Clean the following indirect addresses for all functions since it
13243 * is not used by the driver.
13246 REG_WR(bp
, PXP2_REG_PGL_ADDR_88_F0
, 0);
13247 REG_WR(bp
, PXP2_REG_PGL_ADDR_8C_F0
, 0);
13248 REG_WR(bp
, PXP2_REG_PGL_ADDR_90_F0
, 0);
13249 REG_WR(bp
, PXP2_REG_PGL_ADDR_94_F0
, 0);
13252 REG_WR(bp
, PXP2_REG_PGL_ADDR_88_F1
, 0);
13253 REG_WR(bp
, PXP2_REG_PGL_ADDR_8C_F1
, 0);
13254 REG_WR(bp
, PXP2_REG_PGL_ADDR_90_F1
, 0);
13255 REG_WR(bp
, PXP2_REG_PGL_ADDR_94_F1
, 0);
13258 /* Enable internal target-read (in case we are probed after PF
13259 * FLR). Must be done prior to any BAR read access. Only for
13264 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ
, 1);
13267 dev
->watchdog_timeo
= TX_TIMEOUT
;
13269 dev
->netdev_ops
= &bnx2x_netdev_ops
;
13270 bnx2x_set_ethtool_ops(bp
, dev
);
13272 dev
->priv_flags
|= IFF_UNICAST_FLT
;
13274 dev
->hw_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
|
13275 NETIF_F_TSO
| NETIF_F_TSO_ECN
| NETIF_F_TSO6
|
13276 NETIF_F_RXCSUM
| NETIF_F_LRO
| NETIF_F_GRO
|
13277 NETIF_F_RXHASH
| NETIF_F_HW_VLAN_CTAG_TX
;
13278 if (!chip_is_e1x
) {
13279 dev
->hw_features
|= NETIF_F_GSO_GRE
| NETIF_F_GSO_GRE_CSUM
|
13280 NETIF_F_GSO_IPXIP4
|
13281 NETIF_F_GSO_UDP_TUNNEL
|
13282 NETIF_F_GSO_UDP_TUNNEL_CSUM
|
13283 NETIF_F_GSO_PARTIAL
;
13285 dev
->hw_enc_features
=
13286 NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
| NETIF_F_SG
|
13287 NETIF_F_TSO
| NETIF_F_TSO_ECN
| NETIF_F_TSO6
|
13288 NETIF_F_GSO_IPXIP4
|
13289 NETIF_F_GSO_GRE
| NETIF_F_GSO_GRE_CSUM
|
13290 NETIF_F_GSO_UDP_TUNNEL
| NETIF_F_GSO_UDP_TUNNEL_CSUM
|
13291 NETIF_F_GSO_PARTIAL
;
13293 dev
->gso_partial_features
= NETIF_F_GSO_GRE_CSUM
|
13294 NETIF_F_GSO_UDP_TUNNEL_CSUM
;
13297 dev
->vlan_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
|
13298 NETIF_F_TSO
| NETIF_F_TSO_ECN
| NETIF_F_TSO6
| NETIF_F_HIGHDMA
;
13302 bp
->accept_any_vlan
= true;
13304 dev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_FILTER
;
13306 /* For VF we'll know whether to enable VLAN filtering after
13307 * getting a response to CHANNEL_TLV_ACQUIRE from PF.
13310 dev
->features
|= dev
->hw_features
| NETIF_F_HW_VLAN_CTAG_RX
;
13311 dev
->features
|= NETIF_F_HIGHDMA
;
13313 /* Add Loopback capability to the device */
13314 dev
->hw_features
|= NETIF_F_LOOPBACK
;
13317 dev
->dcbnl_ops
= &bnx2x_dcbnl_ops
;
13320 /* MTU range, 46 - 9600 */
13321 dev
->min_mtu
= ETH_MIN_PACKET_SIZE
;
13322 dev
->max_mtu
= ETH_MAX_JUMBO_PACKET_SIZE
;
13324 /* get_port_hwinfo() will set prtad and mmds properly */
13325 bp
->mdio
.prtad
= MDIO_PRTAD_NONE
;
13327 bp
->mdio
.mode_support
= MDIO_SUPPORTS_C45
| MDIO_EMULATE_C22
;
13328 bp
->mdio
.dev
= dev
;
13329 bp
->mdio
.mdio_read
= bnx2x_mdio_read
;
13330 bp
->mdio
.mdio_write
= bnx2x_mdio_write
;
13335 if (atomic_read(&pdev
->enable_cnt
) == 1)
13336 pci_release_regions(pdev
);
13339 pci_disable_device(pdev
);
13345 static int bnx2x_check_firmware(struct bnx2x
*bp
)
13347 const struct firmware
*firmware
= bp
->firmware
;
13348 struct bnx2x_fw_file_hdr
*fw_hdr
;
13349 struct bnx2x_fw_file_section
*sections
;
13350 u32 offset
, len
, num_ops
;
13351 __be16
*ops_offsets
;
13355 if (firmware
->size
< sizeof(struct bnx2x_fw_file_hdr
)) {
13356 BNX2X_ERR("Wrong FW size\n");
13360 fw_hdr
= (struct bnx2x_fw_file_hdr
*)firmware
->data
;
13361 sections
= (struct bnx2x_fw_file_section
*)fw_hdr
;
13363 /* Make sure none of the offsets and sizes make us read beyond
13364 * the end of the firmware data */
13365 for (i
= 0; i
< sizeof(*fw_hdr
) / sizeof(*sections
); i
++) {
13366 offset
= be32_to_cpu(sections
[i
].offset
);
13367 len
= be32_to_cpu(sections
[i
].len
);
13368 if (offset
+ len
> firmware
->size
) {
13369 BNX2X_ERR("Section %d length is out of bounds\n", i
);
13374 /* Likewise for the init_ops offsets */
13375 offset
= be32_to_cpu(fw_hdr
->init_ops_offsets
.offset
);
13376 ops_offsets
= (__force __be16
*)(firmware
->data
+ offset
);
13377 num_ops
= be32_to_cpu(fw_hdr
->init_ops
.len
) / sizeof(struct raw_op
);
13379 for (i
= 0; i
< be32_to_cpu(fw_hdr
->init_ops_offsets
.len
) / 2; i
++) {
13380 if (be16_to_cpu(ops_offsets
[i
]) > num_ops
) {
13381 BNX2X_ERR("Section offset %d is out of bounds\n", i
);
13386 /* Check FW version */
13387 offset
= be32_to_cpu(fw_hdr
->fw_version
.offset
);
13388 fw_ver
= firmware
->data
+ offset
;
13389 if ((fw_ver
[0] != BCM_5710_FW_MAJOR_VERSION
) ||
13390 (fw_ver
[1] != BCM_5710_FW_MINOR_VERSION
) ||
13391 (fw_ver
[2] != BCM_5710_FW_REVISION_VERSION
) ||
13392 (fw_ver
[3] != BCM_5710_FW_ENGINEERING_VERSION
)) {
13393 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
13394 fw_ver
[0], fw_ver
[1], fw_ver
[2], fw_ver
[3],
13395 BCM_5710_FW_MAJOR_VERSION
,
13396 BCM_5710_FW_MINOR_VERSION
,
13397 BCM_5710_FW_REVISION_VERSION
,
13398 BCM_5710_FW_ENGINEERING_VERSION
);
13405 static void be32_to_cpu_n(const u8
*_source
, u8
*_target
, u32 n
)
13407 const __be32
*source
= (const __be32
*)_source
;
13408 u32
*target
= (u32
*)_target
;
13411 for (i
= 0; i
< n
/4; i
++)
13412 target
[i
] = be32_to_cpu(source
[i
]);
13416 Ops array is stored in the following format:
13417 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
13419 static void bnx2x_prep_ops(const u8
*_source
, u8
*_target
, u32 n
)
13421 const __be32
*source
= (const __be32
*)_source
;
13422 struct raw_op
*target
= (struct raw_op
*)_target
;
13425 for (i
= 0, j
= 0; i
< n
/8; i
++, j
+= 2) {
13426 tmp
= be32_to_cpu(source
[j
]);
13427 target
[i
].op
= (tmp
>> 24) & 0xff;
13428 target
[i
].offset
= tmp
& 0xffffff;
13429 target
[i
].raw_data
= be32_to_cpu(source
[j
+ 1]);
13433 /* IRO array is stored in the following format:
13434 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
13436 static void bnx2x_prep_iro(const u8
*_source
, u8
*_target
, u32 n
)
13438 const __be32
*source
= (const __be32
*)_source
;
13439 struct iro
*target
= (struct iro
*)_target
;
13442 for (i
= 0, j
= 0; i
< n
/sizeof(struct iro
); i
++) {
13443 target
[i
].base
= be32_to_cpu(source
[j
]);
13445 tmp
= be32_to_cpu(source
[j
]);
13446 target
[i
].m1
= (tmp
>> 16) & 0xffff;
13447 target
[i
].m2
= tmp
& 0xffff;
13449 tmp
= be32_to_cpu(source
[j
]);
13450 target
[i
].m3
= (tmp
>> 16) & 0xffff;
13451 target
[i
].size
= tmp
& 0xffff;
13456 static void be16_to_cpu_n(const u8
*_source
, u8
*_target
, u32 n
)
13458 const __be16
*source
= (const __be16
*)_source
;
13459 u16
*target
= (u16
*)_target
;
13462 for (i
= 0; i
< n
/2; i
++)
13463 target
[i
] = be16_to_cpu(source
[i
]);
13466 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
13468 u32 len = be32_to_cpu(fw_hdr->arr.len); \
13469 bp->arr = kmalloc(len, GFP_KERNEL); \
13472 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
13473 (u8 *)bp->arr, len); \
13476 static int bnx2x_init_firmware(struct bnx2x
*bp
)
13478 const char *fw_file_name
;
13479 struct bnx2x_fw_file_hdr
*fw_hdr
;
13485 if (CHIP_IS_E1(bp
))
13486 fw_file_name
= FW_FILE_NAME_E1
;
13487 else if (CHIP_IS_E1H(bp
))
13488 fw_file_name
= FW_FILE_NAME_E1H
;
13489 else if (!CHIP_IS_E1x(bp
))
13490 fw_file_name
= FW_FILE_NAME_E2
;
13492 BNX2X_ERR("Unsupported chip revision\n");
13495 BNX2X_DEV_INFO("Loading %s\n", fw_file_name
);
13497 rc
= request_firmware(&bp
->firmware
, fw_file_name
, &bp
->pdev
->dev
);
13499 BNX2X_ERR("Can't load firmware file %s\n",
13501 goto request_firmware_exit
;
13504 rc
= bnx2x_check_firmware(bp
);
13506 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name
);
13507 goto request_firmware_exit
;
13510 fw_hdr
= (struct bnx2x_fw_file_hdr
*)bp
->firmware
->data
;
13512 /* Initialize the pointers to the init arrays */
13515 BNX2X_ALLOC_AND_SET(init_data
, request_firmware_exit
, be32_to_cpu_n
);
13518 BNX2X_ALLOC_AND_SET(init_ops
, init_ops_alloc_err
, bnx2x_prep_ops
);
13521 BNX2X_ALLOC_AND_SET(init_ops_offsets
, init_offsets_alloc_err
,
13524 /* STORMs firmware */
13525 INIT_TSEM_INT_TABLE_DATA(bp
) = bp
->firmware
->data
+
13526 be32_to_cpu(fw_hdr
->tsem_int_table_data
.offset
);
13527 INIT_TSEM_PRAM_DATA(bp
) = bp
->firmware
->data
+
13528 be32_to_cpu(fw_hdr
->tsem_pram_data
.offset
);
13529 INIT_USEM_INT_TABLE_DATA(bp
) = bp
->firmware
->data
+
13530 be32_to_cpu(fw_hdr
->usem_int_table_data
.offset
);
13531 INIT_USEM_PRAM_DATA(bp
) = bp
->firmware
->data
+
13532 be32_to_cpu(fw_hdr
->usem_pram_data
.offset
);
13533 INIT_XSEM_INT_TABLE_DATA(bp
) = bp
->firmware
->data
+
13534 be32_to_cpu(fw_hdr
->xsem_int_table_data
.offset
);
13535 INIT_XSEM_PRAM_DATA(bp
) = bp
->firmware
->data
+
13536 be32_to_cpu(fw_hdr
->xsem_pram_data
.offset
);
13537 INIT_CSEM_INT_TABLE_DATA(bp
) = bp
->firmware
->data
+
13538 be32_to_cpu(fw_hdr
->csem_int_table_data
.offset
);
13539 INIT_CSEM_PRAM_DATA(bp
) = bp
->firmware
->data
+
13540 be32_to_cpu(fw_hdr
->csem_pram_data
.offset
);
13542 BNX2X_ALLOC_AND_SET(iro_arr
, iro_alloc_err
, bnx2x_prep_iro
);
13547 kfree(bp
->init_ops_offsets
);
13548 init_offsets_alloc_err
:
13549 kfree(bp
->init_ops
);
13550 init_ops_alloc_err
:
13551 kfree(bp
->init_data
);
13552 request_firmware_exit
:
13553 release_firmware(bp
->firmware
);
13554 bp
->firmware
= NULL
;
13559 static void bnx2x_release_firmware(struct bnx2x
*bp
)
13561 kfree(bp
->init_ops_offsets
);
13562 kfree(bp
->init_ops
);
13563 kfree(bp
->init_data
);
13564 release_firmware(bp
->firmware
);
13565 bp
->firmware
= NULL
;
13568 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv
= {
13569 .init_hw_cmn_chip
= bnx2x_init_hw_common_chip
,
13570 .init_hw_cmn
= bnx2x_init_hw_common
,
13571 .init_hw_port
= bnx2x_init_hw_port
,
13572 .init_hw_func
= bnx2x_init_hw_func
,
13574 .reset_hw_cmn
= bnx2x_reset_common
,
13575 .reset_hw_port
= bnx2x_reset_port
,
13576 .reset_hw_func
= bnx2x_reset_func
,
13578 .gunzip_init
= bnx2x_gunzip_init
,
13579 .gunzip_end
= bnx2x_gunzip_end
,
13581 .init_fw
= bnx2x_init_firmware
,
13582 .release_fw
= bnx2x_release_firmware
,
13585 void bnx2x__init_func_obj(struct bnx2x
*bp
)
13587 /* Prepare DMAE related driver resources */
13588 bnx2x_setup_dmae(bp
);
13590 bnx2x_init_func_obj(bp
, &bp
->func_obj
,
13591 bnx2x_sp(bp
, func_rdata
),
13592 bnx2x_sp_mapping(bp
, func_rdata
),
13593 bnx2x_sp(bp
, func_afex_rdata
),
13594 bnx2x_sp_mapping(bp
, func_afex_rdata
),
13595 &bnx2x_func_sp_drv
);
13598 /* must be called after sriov-enable */
13599 static int bnx2x_set_qm_cid_count(struct bnx2x
*bp
)
13601 int cid_count
= BNX2X_L2_MAX_CID(bp
);
13604 cid_count
+= BNX2X_VF_CIDS
;
13606 if (CNIC_SUPPORT(bp
))
13607 cid_count
+= CNIC_CID_MAX
;
13609 return roundup(cid_count
, QM_CID_ROUND
);
13613 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
13618 static int bnx2x_get_num_non_def_sbs(struct pci_dev
*pdev
, int cnic_cnt
)
13624 * If MSI-X is not supported - return number of SBs needed to support
13625 * one fast path queue: one FP queue + SB for CNIC
13627 if (!pdev
->msix_cap
) {
13628 dev_info(&pdev
->dev
, "no msix capability found\n");
13629 return 1 + cnic_cnt
;
13631 dev_info(&pdev
->dev
, "msix capability found\n");
13634 * The value in the PCI configuration space is the index of the last
13635 * entry, namely one less than the actual size of the table, which is
13636 * exactly what we want to return from this function: number of all SBs
13637 * without the default SB.
13638 * For VFs there is no default SB, then we return (index+1).
13640 pci_read_config_word(pdev
, pdev
->msix_cap
+ PCI_MSIX_FLAGS
, &control
);
13642 index
= control
& PCI_MSIX_FLAGS_QSIZE
;
13647 static int set_max_cos_est(int chip_id
)
13653 return BNX2X_MULTI_TX_COS_E1X
;
13656 return BNX2X_MULTI_TX_COS_E2_E3A0
;
13661 case BCM57840_4_10
:
13662 case BCM57840_2_20
:
13668 return BNX2X_MULTI_TX_COS_E3B0
;
13676 pr_err("Unknown board_type (%d), aborting\n", chip_id
);
13681 static int set_is_vf(int chip_id
)
13695 /* nig_tsgen registers relative address */
13696 #define tsgen_ctrl 0x0
13697 #define tsgen_freecount 0x10
13698 #define tsgen_synctime_t0 0x20
13699 #define tsgen_offset_t0 0x28
13700 #define tsgen_drift_t0 0x30
13701 #define tsgen_synctime_t1 0x58
13702 #define tsgen_offset_t1 0x60
13703 #define tsgen_drift_t1 0x68
13705 /* FW workaround for setting drift */
13706 static int bnx2x_send_update_drift_ramrod(struct bnx2x
*bp
, int drift_dir
,
13707 int best_val
, int best_period
)
13709 struct bnx2x_func_state_params func_params
= {NULL
};
13710 struct bnx2x_func_set_timesync_params
*set_timesync_params
=
13711 &func_params
.params
.set_timesync
;
13713 /* Prepare parameters for function state transitions */
13714 __set_bit(RAMROD_COMP_WAIT
, &func_params
.ramrod_flags
);
13715 __set_bit(RAMROD_RETRY
, &func_params
.ramrod_flags
);
13717 func_params
.f_obj
= &bp
->func_obj
;
13718 func_params
.cmd
= BNX2X_F_CMD_SET_TIMESYNC
;
13720 /* Function parameters */
13721 set_timesync_params
->drift_adjust_cmd
= TS_DRIFT_ADJUST_SET
;
13722 set_timesync_params
->offset_cmd
= TS_OFFSET_KEEP
;
13723 set_timesync_params
->add_sub_drift_adjust_value
=
13724 drift_dir
? TS_ADD_VALUE
: TS_SUB_VALUE
;
13725 set_timesync_params
->drift_adjust_value
= best_val
;
13726 set_timesync_params
->drift_adjust_period
= best_period
;
13728 return bnx2x_func_state_change(bp
, &func_params
);
13731 static int bnx2x_ptp_adjfreq(struct ptp_clock_info
*ptp
, s32 ppb
)
13733 struct bnx2x
*bp
= container_of(ptp
, struct bnx2x
, ptp_clock_info
);
13736 int val
, period
, period1
, period2
, dif
, dif1
, dif2
;
13737 int best_dif
= BNX2X_MAX_PHC_DRIFT
, best_period
= 0, best_val
= 0;
13739 DP(BNX2X_MSG_PTP
, "PTP adjfreq called, ppb = %d\n", ppb
);
13741 if (!netif_running(bp
->dev
)) {
13743 "PTP adjfreq called while the interface is down\n");
13754 best_period
= 0x1FFFFFF;
13755 } else if (ppb
>= BNX2X_MAX_PHC_DRIFT
) {
13759 /* Changed not to allow val = 8, 16, 24 as these values
13760 * are not supported in workaround.
13762 for (val
= 0; val
<= 31; val
++) {
13763 if ((val
& 0x7) == 0)
13765 period1
= val
* 1000000 / ppb
;
13766 period2
= period1
+ 1;
13768 dif1
= ppb
- (val
* 1000000 / period1
);
13770 dif1
= BNX2X_MAX_PHC_DRIFT
;
13773 dif2
= ppb
- (val
* 1000000 / period2
);
13776 dif
= (dif1
< dif2
) ? dif1
: dif2
;
13777 period
= (dif1
< dif2
) ? period1
: period2
;
13778 if (dif
< best_dif
) {
13781 best_period
= period
;
13786 rc
= bnx2x_send_update_drift_ramrod(bp
, drift_dir
, best_val
,
13789 BNX2X_ERR("Failed to set drift\n");
13793 DP(BNX2X_MSG_PTP
, "Configured val = %d, period = %d\n", best_val
,
13799 static int bnx2x_ptp_adjtime(struct ptp_clock_info
*ptp
, s64 delta
)
13801 struct bnx2x
*bp
= container_of(ptp
, struct bnx2x
, ptp_clock_info
);
13803 if (!netif_running(bp
->dev
)) {
13805 "PTP adjtime called while the interface is down\n");
13809 DP(BNX2X_MSG_PTP
, "PTP adjtime called, delta = %llx\n", delta
);
13811 timecounter_adjtime(&bp
->timecounter
, delta
);
13816 static int bnx2x_ptp_gettime(struct ptp_clock_info
*ptp
, struct timespec64
*ts
)
13818 struct bnx2x
*bp
= container_of(ptp
, struct bnx2x
, ptp_clock_info
);
13821 if (!netif_running(bp
->dev
)) {
13823 "PTP gettime called while the interface is down\n");
13827 ns
= timecounter_read(&bp
->timecounter
);
13829 DP(BNX2X_MSG_PTP
, "PTP gettime called, ns = %llu\n", ns
);
13831 *ts
= ns_to_timespec64(ns
);
13836 static int bnx2x_ptp_settime(struct ptp_clock_info
*ptp
,
13837 const struct timespec64
*ts
)
13839 struct bnx2x
*bp
= container_of(ptp
, struct bnx2x
, ptp_clock_info
);
13842 if (!netif_running(bp
->dev
)) {
13844 "PTP settime called while the interface is down\n");
13848 ns
= timespec64_to_ns(ts
);
13850 DP(BNX2X_MSG_PTP
, "PTP settime called, ns = %llu\n", ns
);
13852 /* Re-init the timecounter */
13853 timecounter_init(&bp
->timecounter
, &bp
->cyclecounter
, ns
);
13858 /* Enable (or disable) ancillary features of the phc subsystem */
13859 static int bnx2x_ptp_enable(struct ptp_clock_info
*ptp
,
13860 struct ptp_clock_request
*rq
, int on
)
13862 struct bnx2x
*bp
= container_of(ptp
, struct bnx2x
, ptp_clock_info
);
13864 BNX2X_ERR("PHC ancillary features are not supported\n");
13868 static void bnx2x_register_phc(struct bnx2x
*bp
)
13870 /* Fill the ptp_clock_info struct and register PTP clock*/
13871 bp
->ptp_clock_info
.owner
= THIS_MODULE
;
13872 snprintf(bp
->ptp_clock_info
.name
, 16, "%s", bp
->dev
->name
);
13873 bp
->ptp_clock_info
.max_adj
= BNX2X_MAX_PHC_DRIFT
; /* In PPB */
13874 bp
->ptp_clock_info
.n_alarm
= 0;
13875 bp
->ptp_clock_info
.n_ext_ts
= 0;
13876 bp
->ptp_clock_info
.n_per_out
= 0;
13877 bp
->ptp_clock_info
.pps
= 0;
13878 bp
->ptp_clock_info
.adjfreq
= bnx2x_ptp_adjfreq
;
13879 bp
->ptp_clock_info
.adjtime
= bnx2x_ptp_adjtime
;
13880 bp
->ptp_clock_info
.gettime64
= bnx2x_ptp_gettime
;
13881 bp
->ptp_clock_info
.settime64
= bnx2x_ptp_settime
;
13882 bp
->ptp_clock_info
.enable
= bnx2x_ptp_enable
;
13884 bp
->ptp_clock
= ptp_clock_register(&bp
->ptp_clock_info
, &bp
->pdev
->dev
);
13885 if (IS_ERR(bp
->ptp_clock
)) {
13886 bp
->ptp_clock
= NULL
;
13887 BNX2X_ERR("PTP clock registeration failed\n");
13891 static int bnx2x_init_one(struct pci_dev
*pdev
,
13892 const struct pci_device_id
*ent
)
13894 struct net_device
*dev
= NULL
;
13896 enum pcie_link_width pcie_width
;
13897 enum pci_bus_speed pcie_speed
;
13898 int rc
, max_non_def_sbs
;
13899 int rx_count
, tx_count
, rss_count
, doorbell_size
;
13904 /* Management FW 'remembers' living interfaces. Allow it some time
13905 * to forget previously living interfaces, allowing a proper re-load.
13907 if (is_kdump_kernel()) {
13908 ktime_t now
= ktime_get_boottime();
13909 ktime_t fw_ready_time
= ktime_set(5, 0);
13911 if (ktime_before(now
, fw_ready_time
))
13912 msleep(ktime_ms_delta(fw_ready_time
, now
));
13915 /* An estimated maximum supported CoS number according to the chip
13917 * We will try to roughly estimate the maximum number of CoSes this chip
13918 * may support in order to minimize the memory allocated for Tx
13919 * netdev_queue's. This number will be accurately calculated during the
13920 * initialization of bp->max_cos based on the chip versions AND chip
13921 * revision in the bnx2x_init_bp().
13923 max_cos_est
= set_max_cos_est(ent
->driver_data
);
13924 if (max_cos_est
< 0)
13925 return max_cos_est
;
13926 is_vf
= set_is_vf(ent
->driver_data
);
13927 cnic_cnt
= is_vf
? 0 : 1;
13929 max_non_def_sbs
= bnx2x_get_num_non_def_sbs(pdev
, cnic_cnt
);
13931 /* add another SB for VF as it has no default SB */
13932 max_non_def_sbs
+= is_vf
? 1 : 0;
13934 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
13935 rss_count
= max_non_def_sbs
- cnic_cnt
;
13940 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
13941 rx_count
= rss_count
+ cnic_cnt
;
13943 /* Maximum number of netdev Tx queues:
13944 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
13946 tx_count
= rss_count
* max_cos_est
+ cnic_cnt
;
13948 /* dev zeroed in init_etherdev */
13949 dev
= alloc_etherdev_mqs(sizeof(*bp
), tx_count
, rx_count
);
13953 bp
= netdev_priv(dev
);
13957 bp
->flags
|= IS_VF_FLAG
;
13959 bp
->igu_sb_cnt
= max_non_def_sbs
;
13960 bp
->igu_base_addr
= IS_VF(bp
) ? PXP_VF_ADDR_IGU_START
: BAR_IGU_INTMEM
;
13961 bp
->msg_enable
= debug
;
13962 bp
->cnic_support
= cnic_cnt
;
13963 bp
->cnic_probe
= bnx2x_cnic_probe
;
13965 pci_set_drvdata(pdev
, dev
);
13967 rc
= bnx2x_init_dev(bp
, pdev
, dev
, ent
->driver_data
);
13973 BNX2X_DEV_INFO("This is a %s function\n",
13974 IS_PF(bp
) ? "physical" : "virtual");
13975 BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp
) ? "on" : "off");
13976 BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs
);
13977 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
13978 tx_count
, rx_count
);
13980 rc
= bnx2x_init_bp(bp
);
13982 goto init_one_exit
;
13984 /* Map doorbells here as we need the real value of bp->max_cos which
13985 * is initialized in bnx2x_init_bp() to determine the number of
13989 bp
->doorbells
= bnx2x_vf_doorbells(bp
);
13990 rc
= bnx2x_vf_pci_alloc(bp
);
13992 goto init_one_freemem
;
13994 doorbell_size
= BNX2X_L2_MAX_CID(bp
) * (1 << BNX2X_DB_SHIFT
);
13995 if (doorbell_size
> pci_resource_len(pdev
, 2)) {
13996 dev_err(&bp
->pdev
->dev
,
13997 "Cannot map doorbells, bar size too small, aborting\n");
13999 goto init_one_freemem
;
14001 bp
->doorbells
= ioremap_nocache(pci_resource_start(pdev
, 2),
14004 if (!bp
->doorbells
) {
14005 dev_err(&bp
->pdev
->dev
,
14006 "Cannot map doorbell space, aborting\n");
14008 goto init_one_freemem
;
14012 rc
= bnx2x_vfpf_acquire(bp
, tx_count
, rx_count
);
14014 goto init_one_freemem
;
14016 #ifdef CONFIG_BNX2X_SRIOV
14017 /* VF with OLD Hypervisor or old PF do not support filtering */
14018 if (bp
->acquire_resp
.pfdev_info
.pf_cap
& PFVF_CAP_VLAN_FILTER
) {
14019 dev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_FILTER
;
14020 dev
->features
|= NETIF_F_HW_VLAN_CTAG_FILTER
;
14025 /* Enable SRIOV if capability found in configuration space */
14026 rc
= bnx2x_iov_init_one(bp
, int_mode
, BNX2X_MAX_NUM_OF_VFS
);
14028 goto init_one_freemem
;
14030 /* calc qm_cid_count */
14031 bp
->qm_cid_count
= bnx2x_set_qm_cid_count(bp
);
14032 BNX2X_DEV_INFO("qm_cid_count %d\n", bp
->qm_cid_count
);
14034 /* disable FCOE L2 queue for E1x*/
14035 if (CHIP_IS_E1x(bp
))
14036 bp
->flags
|= NO_FCOE_FLAG
;
14038 /* Set bp->num_queues for MSI-X mode*/
14039 bnx2x_set_num_queues(bp
);
14041 /* Configure interrupt mode: try to enable MSI-X/MSI if
14044 rc
= bnx2x_set_int_mode(bp
);
14046 dev_err(&pdev
->dev
, "Cannot set interrupts\n");
14047 goto init_one_freemem
;
14049 BNX2X_DEV_INFO("set interrupts successfully\n");
14051 /* register the net device */
14052 rc
= register_netdev(dev
);
14054 dev_err(&pdev
->dev
, "Cannot register net device\n");
14055 goto init_one_freemem
;
14057 BNX2X_DEV_INFO("device name after netdev register %s\n", dev
->name
);
14059 if (!NO_FCOE(bp
)) {
14060 /* Add storage MAC address */
14062 dev_addr_add(bp
->dev
, bp
->fip_mac
, NETDEV_HW_ADDR_T_SAN
);
14065 if (pcie_get_minimum_link(bp
->pdev
, &pcie_speed
, &pcie_width
) ||
14066 pcie_speed
== PCI_SPEED_UNKNOWN
||
14067 pcie_width
== PCIE_LNK_WIDTH_UNKNOWN
)
14068 BNX2X_DEV_INFO("Failed to determine PCI Express Bandwidth\n");
14071 "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
14072 board_info
[ent
->driver_data
].name
,
14073 (CHIP_REV(bp
) >> 12) + 'A', (CHIP_METAL(bp
) >> 4),
14075 pcie_speed
== PCIE_SPEED_2_5GT
? "2.5GHz" :
14076 pcie_speed
== PCIE_SPEED_5_0GT
? "5.0GHz" :
14077 pcie_speed
== PCIE_SPEED_8_0GT
? "8.0GHz" :
14079 dev
->base_addr
, bp
->pdev
->irq
, dev
->dev_addr
);
14081 bnx2x_register_phc(bp
);
14083 if (!IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp
))
14084 bnx2x_set_os_driver_state(bp
, OS_DRIVER_STATE_DISABLED
);
14089 bnx2x_free_mem_bp(bp
);
14092 bnx2x_disable_pcie_error_reporting(bp
);
14095 iounmap(bp
->regview
);
14097 if (IS_PF(bp
) && bp
->doorbells
)
14098 iounmap(bp
->doorbells
);
14102 if (atomic_read(&pdev
->enable_cnt
) == 1)
14103 pci_release_regions(pdev
);
14105 pci_disable_device(pdev
);
14110 static void __bnx2x_remove(struct pci_dev
*pdev
,
14111 struct net_device
*dev
,
14113 bool remove_netdev
)
14115 if (bp
->ptp_clock
) {
14116 ptp_clock_unregister(bp
->ptp_clock
);
14117 bp
->ptp_clock
= NULL
;
14120 /* Delete storage MAC address */
14121 if (!NO_FCOE(bp
)) {
14123 dev_addr_del(bp
->dev
, bp
->fip_mac
, NETDEV_HW_ADDR_T_SAN
);
14128 /* Delete app tlvs from dcbnl */
14129 bnx2x_dcbnl_update_applist(bp
, true);
14134 (bp
->flags
& BC_SUPPORTS_RMMOD_CMD
))
14135 bnx2x_fw_command(bp
, DRV_MSG_CODE_RMMOD
, 0);
14137 /* Close the interface - either directly or implicitly */
14138 if (remove_netdev
) {
14139 unregister_netdev(dev
);
14146 bnx2x_iov_remove_one(bp
);
14148 /* Power on: we can't let PCI layer write to us while we are in D3 */
14150 bnx2x_set_power_state(bp
, PCI_D0
);
14151 bnx2x_set_os_driver_state(bp
, OS_DRIVER_STATE_NOT_LOADED
);
14153 /* Set endianity registers to reset values in case next driver
14154 * boots in different endianty environment.
14156 bnx2x_reset_endianity(bp
);
14159 /* Disable MSI/MSI-X */
14160 bnx2x_disable_msi(bp
);
14164 bnx2x_set_power_state(bp
, PCI_D3hot
);
14166 /* Make sure RESET task is not scheduled before continuing */
14167 cancel_delayed_work_sync(&bp
->sp_rtnl_task
);
14169 /* send message via vfpf channel to release the resources of this vf */
14171 bnx2x_vfpf_release(bp
);
14173 /* Assumes no further PCIe PM changes will occur */
14174 if (system_state
== SYSTEM_POWER_OFF
) {
14175 pci_wake_from_d3(pdev
, bp
->wol
);
14176 pci_set_power_state(pdev
, PCI_D3hot
);
14179 bnx2x_disable_pcie_error_reporting(bp
);
14180 if (remove_netdev
) {
14182 iounmap(bp
->regview
);
14184 /* For vfs, doorbells are part of the regview and were unmapped
14185 * along with it. FW is only loaded by PF.
14189 iounmap(bp
->doorbells
);
14191 bnx2x_release_firmware(bp
);
14193 bnx2x_vf_pci_dealloc(bp
);
14195 bnx2x_free_mem_bp(bp
);
14199 if (atomic_read(&pdev
->enable_cnt
) == 1)
14200 pci_release_regions(pdev
);
14202 pci_disable_device(pdev
);
14206 static void bnx2x_remove_one(struct pci_dev
*pdev
)
14208 struct net_device
*dev
= pci_get_drvdata(pdev
);
14212 dev_err(&pdev
->dev
, "BAD net device from bnx2x_init_one\n");
14215 bp
= netdev_priv(dev
);
14217 __bnx2x_remove(pdev
, dev
, bp
, true);
14220 static int bnx2x_eeh_nic_unload(struct bnx2x
*bp
)
14222 bp
->state
= BNX2X_STATE_CLOSING_WAIT4_HALT
;
14224 bp
->rx_mode
= BNX2X_RX_MODE_NONE
;
14226 if (CNIC_LOADED(bp
))
14227 bnx2x_cnic_notify(bp
, CNIC_CTL_STOP_CMD
);
14230 bnx2x_tx_disable(bp
);
14231 /* Delete all NAPI objects */
14232 bnx2x_del_all_napi(bp
);
14233 if (CNIC_LOADED(bp
))
14234 bnx2x_del_all_napi_cnic(bp
);
14235 netdev_reset_tc(bp
->dev
);
14237 del_timer_sync(&bp
->timer
);
14238 cancel_delayed_work_sync(&bp
->sp_task
);
14239 cancel_delayed_work_sync(&bp
->period_task
);
14241 if (!down_timeout(&bp
->stats_lock
, HZ
/ 10)) {
14242 bp
->stats_state
= STATS_STATE_DISABLED
;
14243 up(&bp
->stats_lock
);
14246 bnx2x_save_statistics(bp
);
14248 netif_carrier_off(bp
->dev
);
14254 * bnx2x_io_error_detected - called when PCI error is detected
14255 * @pdev: Pointer to PCI device
14256 * @state: The current pci connection state
14258 * This function is called after a PCI bus error affecting
14259 * this device has been detected.
14261 static pci_ers_result_t
bnx2x_io_error_detected(struct pci_dev
*pdev
,
14262 pci_channel_state_t state
)
14264 struct net_device
*dev
= pci_get_drvdata(pdev
);
14265 struct bnx2x
*bp
= netdev_priv(dev
);
14269 BNX2X_ERR("IO error detected\n");
14271 netif_device_detach(dev
);
14273 if (state
== pci_channel_io_perm_failure
) {
14275 return PCI_ERS_RESULT_DISCONNECT
;
14278 if (netif_running(dev
))
14279 bnx2x_eeh_nic_unload(bp
);
14281 bnx2x_prev_path_mark_eeh(bp
);
14283 pci_disable_device(pdev
);
14287 /* Request a slot reset */
14288 return PCI_ERS_RESULT_NEED_RESET
;
14292 * bnx2x_io_slot_reset - called after the PCI bus has been reset
14293 * @pdev: Pointer to PCI device
14295 * Restart the card from scratch, as if from a cold-boot.
14297 static pci_ers_result_t
bnx2x_io_slot_reset(struct pci_dev
*pdev
)
14299 struct net_device
*dev
= pci_get_drvdata(pdev
);
14300 struct bnx2x
*bp
= netdev_priv(dev
);
14304 BNX2X_ERR("IO slot reset initializing...\n");
14305 if (pci_enable_device(pdev
)) {
14306 dev_err(&pdev
->dev
,
14307 "Cannot re-enable PCI device after reset\n");
14309 return PCI_ERS_RESULT_DISCONNECT
;
14312 pci_set_master(pdev
);
14313 pci_restore_state(pdev
);
14314 pci_save_state(pdev
);
14316 if (netif_running(dev
))
14317 bnx2x_set_power_state(bp
, PCI_D0
);
14319 if (netif_running(dev
)) {
14320 BNX2X_ERR("IO slot reset --> driver unload\n");
14322 /* MCP should have been reset; Need to wait for validity */
14323 bnx2x_init_shmem(bp
);
14325 if (IS_PF(bp
) && SHMEM2_HAS(bp
, drv_capabilities_flag
)) {
14329 drv_capabilities_flag
[BP_FW_MB_IDX(bp
)]);
14330 SHMEM2_WR(bp
, drv_capabilities_flag
[BP_FW_MB_IDX(bp
)],
14331 v
& ~DRV_FLAGS_CAPABILITIES_LOADED_L2
);
14333 bnx2x_drain_tx_queues(bp
);
14334 bnx2x_send_unload_req(bp
, UNLOAD_RECOVERY
);
14335 bnx2x_netif_stop(bp
, 1);
14336 bnx2x_free_irq(bp
);
14338 /* Report UNLOAD_DONE to MCP */
14339 bnx2x_send_unload_done(bp
, true);
14344 bnx2x_prev_unload(bp
);
14346 /* We should have reseted the engine, so It's fair to
14347 * assume the FW will no longer write to the bnx2x driver.
14349 bnx2x_squeeze_objects(bp
);
14350 bnx2x_free_skbs(bp
);
14351 for_each_rx_queue(bp
, i
)
14352 bnx2x_free_rx_sge_range(bp
, bp
->fp
+ i
, NUM_RX_SGE
);
14353 bnx2x_free_fp_mem(bp
);
14354 bnx2x_free_mem(bp
);
14356 bp
->state
= BNX2X_STATE_CLOSED
;
14361 /* If AER, perform cleanup of the PCIe registers */
14362 if (bp
->flags
& AER_ENABLED
) {
14363 if (pci_cleanup_aer_uncorrect_error_status(pdev
))
14364 BNX2X_ERR("pci_cleanup_aer_uncorrect_error_status failed\n");
14366 DP(NETIF_MSG_HW
, "pci_cleanup_aer_uncorrect_error_status succeeded\n");
14369 return PCI_ERS_RESULT_RECOVERED
;
14373 * bnx2x_io_resume - called when traffic can start flowing again
14374 * @pdev: Pointer to PCI device
14376 * This callback is called when the error recovery driver tells us that
14377 * its OK to resume normal operation.
14379 static void bnx2x_io_resume(struct pci_dev
*pdev
)
14381 struct net_device
*dev
= pci_get_drvdata(pdev
);
14382 struct bnx2x
*bp
= netdev_priv(dev
);
14384 if (bp
->recovery_state
!= BNX2X_RECOVERY_DONE
) {
14385 netdev_err(bp
->dev
, "Handling parity error recovery. Try again later\n");
14391 bp
->fw_seq
= SHMEM_RD(bp
, func_mb
[BP_FW_MB_IDX(bp
)].drv_mb_header
) &
14392 DRV_MSG_SEQ_NUMBER_MASK
;
14394 if (netif_running(dev
))
14395 bnx2x_nic_load(bp
, LOAD_NORMAL
);
14397 netif_device_attach(dev
);
14402 static const struct pci_error_handlers bnx2x_err_handler
= {
14403 .error_detected
= bnx2x_io_error_detected
,
14404 .slot_reset
= bnx2x_io_slot_reset
,
14405 .resume
= bnx2x_io_resume
,
14408 static void bnx2x_shutdown(struct pci_dev
*pdev
)
14410 struct net_device
*dev
= pci_get_drvdata(pdev
);
14416 bp
= netdev_priv(dev
);
14421 netif_device_detach(dev
);
14424 /* Don't remove the netdevice, as there are scenarios which will cause
14425 * the kernel to hang, e.g., when trying to remove bnx2i while the
14426 * rootfs is mounted from SAN.
14428 __bnx2x_remove(pdev
, dev
, bp
, false);
14431 static struct pci_driver bnx2x_pci_driver
= {
14432 .name
= DRV_MODULE_NAME
,
14433 .id_table
= bnx2x_pci_tbl
,
14434 .probe
= bnx2x_init_one
,
14435 .remove
= bnx2x_remove_one
,
14436 .suspend
= bnx2x_suspend
,
14437 .resume
= bnx2x_resume
,
14438 .err_handler
= &bnx2x_err_handler
,
14439 #ifdef CONFIG_BNX2X_SRIOV
14440 .sriov_configure
= bnx2x_sriov_configure
,
14442 .shutdown
= bnx2x_shutdown
,
14445 static int __init
bnx2x_init(void)
14449 pr_info("%s", version
);
14451 bnx2x_wq
= create_singlethread_workqueue("bnx2x");
14452 if (bnx2x_wq
== NULL
) {
14453 pr_err("Cannot create workqueue\n");
14456 bnx2x_iov_wq
= create_singlethread_workqueue("bnx2x_iov");
14457 if (!bnx2x_iov_wq
) {
14458 pr_err("Cannot create iov workqueue\n");
14459 destroy_workqueue(bnx2x_wq
);
14463 ret
= pci_register_driver(&bnx2x_pci_driver
);
14465 pr_err("Cannot register driver\n");
14466 destroy_workqueue(bnx2x_wq
);
14467 destroy_workqueue(bnx2x_iov_wq
);
14472 static void __exit
bnx2x_cleanup(void)
14474 struct list_head
*pos
, *q
;
14476 pci_unregister_driver(&bnx2x_pci_driver
);
14478 destroy_workqueue(bnx2x_wq
);
14479 destroy_workqueue(bnx2x_iov_wq
);
14481 /* Free globally allocated resources */
14482 list_for_each_safe(pos
, q
, &bnx2x_prev_list
) {
14483 struct bnx2x_prev_path_list
*tmp
=
14484 list_entry(pos
, struct bnx2x_prev_path_list
, list
);
14490 void bnx2x_notify_link_changed(struct bnx2x
*bp
)
14492 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_12
+ BP_FUNC(bp
)*sizeof(u32
), 1);
14495 module_init(bnx2x_init
);
14496 module_exit(bnx2x_cleanup
);
14499 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
14501 * @bp: driver handle
14502 * @set: set or clear the CAM entry
14504 * This function will wait until the ramrod completion returns.
14505 * Return 0 if success, -ENODEV if ramrod doesn't return.
14507 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x
*bp
)
14509 unsigned long ramrod_flags
= 0;
14511 __set_bit(RAMROD_COMP_WAIT
, &ramrod_flags
);
14512 return bnx2x_set_mac_one(bp
, bp
->cnic_eth_dev
.iscsi_mac
,
14513 &bp
->iscsi_l2_mac_obj
, true,
14514 BNX2X_ISCSI_ETH_MAC
, &ramrod_flags
);
14517 /* count denotes the number of new completions we have seen */
14518 static void bnx2x_cnic_sp_post(struct bnx2x
*bp
, int count
)
14520 struct eth_spe
*spe
;
14521 int cxt_index
, cxt_offset
;
14523 #ifdef BNX2X_STOP_ON_ERROR
14524 if (unlikely(bp
->panic
))
14528 spin_lock_bh(&bp
->spq_lock
);
14529 BUG_ON(bp
->cnic_spq_pending
< count
);
14530 bp
->cnic_spq_pending
-= count
;
14532 for (; bp
->cnic_kwq_pending
; bp
->cnic_kwq_pending
--) {
14533 u16 type
= (le16_to_cpu(bp
->cnic_kwq_cons
->hdr
.type
)
14534 & SPE_HDR_CONN_TYPE
) >>
14535 SPE_HDR_CONN_TYPE_SHIFT
;
14536 u8 cmd
= (le32_to_cpu(bp
->cnic_kwq_cons
->hdr
.conn_and_cmd_data
)
14537 >> SPE_HDR_CMD_ID_SHIFT
) & 0xff;
14539 /* Set validation for iSCSI L2 client before sending SETUP
14542 if (type
== ETH_CONNECTION_TYPE
) {
14543 if (cmd
== RAMROD_CMD_ID_ETH_CLIENT_SETUP
) {
14544 cxt_index
= BNX2X_ISCSI_ETH_CID(bp
) /
14546 cxt_offset
= BNX2X_ISCSI_ETH_CID(bp
) -
14547 (cxt_index
* ILT_PAGE_CIDS
);
14548 bnx2x_set_ctx_validation(bp
,
14549 &bp
->context
[cxt_index
].
14550 vcxt
[cxt_offset
].eth
,
14551 BNX2X_ISCSI_ETH_CID(bp
));
14556 * There may be not more than 8 L2, not more than 8 L5 SPEs
14557 * and in the air. We also check that number of outstanding
14558 * COMMON ramrods is not more than the EQ and SPQ can
14561 if (type
== ETH_CONNECTION_TYPE
) {
14562 if (!atomic_read(&bp
->cq_spq_left
))
14565 atomic_dec(&bp
->cq_spq_left
);
14566 } else if (type
== NONE_CONNECTION_TYPE
) {
14567 if (!atomic_read(&bp
->eq_spq_left
))
14570 atomic_dec(&bp
->eq_spq_left
);
14571 } else if ((type
== ISCSI_CONNECTION_TYPE
) ||
14572 (type
== FCOE_CONNECTION_TYPE
)) {
14573 if (bp
->cnic_spq_pending
>=
14574 bp
->cnic_eth_dev
.max_kwqe_pending
)
14577 bp
->cnic_spq_pending
++;
14579 BNX2X_ERR("Unknown SPE type: %d\n", type
);
14584 spe
= bnx2x_sp_get_next(bp
);
14585 *spe
= *bp
->cnic_kwq_cons
;
14587 DP(BNX2X_MSG_SP
, "pending on SPQ %d, on KWQ %d count %d\n",
14588 bp
->cnic_spq_pending
, bp
->cnic_kwq_pending
, count
);
14590 if (bp
->cnic_kwq_cons
== bp
->cnic_kwq_last
)
14591 bp
->cnic_kwq_cons
= bp
->cnic_kwq
;
14593 bp
->cnic_kwq_cons
++;
14595 bnx2x_sp_prod_update(bp
);
14596 spin_unlock_bh(&bp
->spq_lock
);
14599 static int bnx2x_cnic_sp_queue(struct net_device
*dev
,
14600 struct kwqe_16
*kwqes
[], u32 count
)
14602 struct bnx2x
*bp
= netdev_priv(dev
);
14605 #ifdef BNX2X_STOP_ON_ERROR
14606 if (unlikely(bp
->panic
)) {
14607 BNX2X_ERR("Can't post to SP queue while panic\n");
14612 if ((bp
->recovery_state
!= BNX2X_RECOVERY_DONE
) &&
14613 (bp
->recovery_state
!= BNX2X_RECOVERY_NIC_LOADING
)) {
14614 BNX2X_ERR("Handling parity error recovery. Try again later\n");
14618 spin_lock_bh(&bp
->spq_lock
);
14620 for (i
= 0; i
< count
; i
++) {
14621 struct eth_spe
*spe
= (struct eth_spe
*)kwqes
[i
];
14623 if (bp
->cnic_kwq_pending
== MAX_SP_DESC_CNT
)
14626 *bp
->cnic_kwq_prod
= *spe
;
14628 bp
->cnic_kwq_pending
++;
14630 DP(BNX2X_MSG_SP
, "L5 SPQE %x %x %x:%x pos %d\n",
14631 spe
->hdr
.conn_and_cmd_data
, spe
->hdr
.type
,
14632 spe
->data
.update_data_addr
.hi
,
14633 spe
->data
.update_data_addr
.lo
,
14634 bp
->cnic_kwq_pending
);
14636 if (bp
->cnic_kwq_prod
== bp
->cnic_kwq_last
)
14637 bp
->cnic_kwq_prod
= bp
->cnic_kwq
;
14639 bp
->cnic_kwq_prod
++;
14642 spin_unlock_bh(&bp
->spq_lock
);
14644 if (bp
->cnic_spq_pending
< bp
->cnic_eth_dev
.max_kwqe_pending
)
14645 bnx2x_cnic_sp_post(bp
, 0);
14650 static int bnx2x_cnic_ctl_send(struct bnx2x
*bp
, struct cnic_ctl_info
*ctl
)
14652 struct cnic_ops
*c_ops
;
14655 mutex_lock(&bp
->cnic_mutex
);
14656 c_ops
= rcu_dereference_protected(bp
->cnic_ops
,
14657 lockdep_is_held(&bp
->cnic_mutex
));
14659 rc
= c_ops
->cnic_ctl(bp
->cnic_data
, ctl
);
14660 mutex_unlock(&bp
->cnic_mutex
);
14665 static int bnx2x_cnic_ctl_send_bh(struct bnx2x
*bp
, struct cnic_ctl_info
*ctl
)
14667 struct cnic_ops
*c_ops
;
14671 c_ops
= rcu_dereference(bp
->cnic_ops
);
14673 rc
= c_ops
->cnic_ctl(bp
->cnic_data
, ctl
);
14680 * for commands that have no data
14682 int bnx2x_cnic_notify(struct bnx2x
*bp
, int cmd
)
14684 struct cnic_ctl_info ctl
= {0};
14688 return bnx2x_cnic_ctl_send(bp
, &ctl
);
14691 static void bnx2x_cnic_cfc_comp(struct bnx2x
*bp
, int cid
, u8 err
)
14693 struct cnic_ctl_info ctl
= {0};
14695 /* first we tell CNIC and only then we count this as a completion */
14696 ctl
.cmd
= CNIC_CTL_COMPLETION_CMD
;
14697 ctl
.data
.comp
.cid
= cid
;
14698 ctl
.data
.comp
.error
= err
;
14700 bnx2x_cnic_ctl_send_bh(bp
, &ctl
);
14701 bnx2x_cnic_sp_post(bp
, 0);
14704 /* Called with netif_addr_lock_bh() taken.
14705 * Sets an rx_mode config for an iSCSI ETH client.
14707 * Completion should be checked outside.
14709 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x
*bp
, bool start
)
14711 unsigned long accept_flags
= 0, ramrod_flags
= 0;
14712 u8 cl_id
= bnx2x_cnic_eth_cl_id(bp
, BNX2X_ISCSI_ETH_CL_ID_IDX
);
14713 int sched_state
= BNX2X_FILTER_ISCSI_ETH_STOP_SCHED
;
14716 /* Start accepting on iSCSI L2 ring. Accept all multicasts
14717 * because it's the only way for UIO Queue to accept
14718 * multicasts (in non-promiscuous mode only one Queue per
14719 * function will receive multicast packets (leading in our
14722 __set_bit(BNX2X_ACCEPT_UNICAST
, &accept_flags
);
14723 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST
, &accept_flags
);
14724 __set_bit(BNX2X_ACCEPT_BROADCAST
, &accept_flags
);
14725 __set_bit(BNX2X_ACCEPT_ANY_VLAN
, &accept_flags
);
14727 /* Clear STOP_PENDING bit if START is requested */
14728 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED
, &bp
->sp_state
);
14730 sched_state
= BNX2X_FILTER_ISCSI_ETH_START_SCHED
;
14732 /* Clear START_PENDING bit if STOP is requested */
14733 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED
, &bp
->sp_state
);
14735 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING
, &bp
->sp_state
))
14736 set_bit(sched_state
, &bp
->sp_state
);
14738 __set_bit(RAMROD_RX
, &ramrod_flags
);
14739 bnx2x_set_q_rx_mode(bp
, cl_id
, 0, accept_flags
, 0,
14744 static int bnx2x_drv_ctl(struct net_device
*dev
, struct drv_ctl_info
*ctl
)
14746 struct bnx2x
*bp
= netdev_priv(dev
);
14749 switch (ctl
->cmd
) {
14750 case DRV_CTL_CTXTBL_WR_CMD
: {
14751 u32 index
= ctl
->data
.io
.offset
;
14752 dma_addr_t addr
= ctl
->data
.io
.dma_addr
;
14754 bnx2x_ilt_wr(bp
, index
, addr
);
14758 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD
: {
14759 int count
= ctl
->data
.credit
.credit_count
;
14761 bnx2x_cnic_sp_post(bp
, count
);
14765 /* rtnl_lock is held. */
14766 case DRV_CTL_START_L2_CMD
: {
14767 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
14768 unsigned long sp_bits
= 0;
14770 /* Configure the iSCSI classification object */
14771 bnx2x_init_mac_obj(bp
, &bp
->iscsi_l2_mac_obj
,
14772 cp
->iscsi_l2_client_id
,
14773 cp
->iscsi_l2_cid
, BP_FUNC(bp
),
14774 bnx2x_sp(bp
, mac_rdata
),
14775 bnx2x_sp_mapping(bp
, mac_rdata
),
14776 BNX2X_FILTER_MAC_PENDING
,
14777 &bp
->sp_state
, BNX2X_OBJ_TYPE_RX
,
14780 /* Set iSCSI MAC address */
14781 rc
= bnx2x_set_iscsi_eth_mac_addr(bp
);
14788 /* Start accepting on iSCSI L2 ring */
14790 netif_addr_lock_bh(dev
);
14791 bnx2x_set_iscsi_eth_rx_mode(bp
, true);
14792 netif_addr_unlock_bh(dev
);
14794 /* bits to wait on */
14795 __set_bit(BNX2X_FILTER_RX_MODE_PENDING
, &sp_bits
);
14796 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED
, &sp_bits
);
14798 if (!bnx2x_wait_sp_comp(bp
, sp_bits
))
14799 BNX2X_ERR("rx_mode completion timed out!\n");
14804 /* rtnl_lock is held. */
14805 case DRV_CTL_STOP_L2_CMD
: {
14806 unsigned long sp_bits
= 0;
14808 /* Stop accepting on iSCSI L2 ring */
14809 netif_addr_lock_bh(dev
);
14810 bnx2x_set_iscsi_eth_rx_mode(bp
, false);
14811 netif_addr_unlock_bh(dev
);
14813 /* bits to wait on */
14814 __set_bit(BNX2X_FILTER_RX_MODE_PENDING
, &sp_bits
);
14815 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED
, &sp_bits
);
14817 if (!bnx2x_wait_sp_comp(bp
, sp_bits
))
14818 BNX2X_ERR("rx_mode completion timed out!\n");
14823 /* Unset iSCSI L2 MAC */
14824 rc
= bnx2x_del_all_macs(bp
, &bp
->iscsi_l2_mac_obj
,
14825 BNX2X_ISCSI_ETH_MAC
, true);
14828 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD
: {
14829 int count
= ctl
->data
.credit
.credit_count
;
14831 smp_mb__before_atomic();
14832 atomic_add(count
, &bp
->cq_spq_left
);
14833 smp_mb__after_atomic();
14836 case DRV_CTL_ULP_REGISTER_CMD
: {
14837 int ulp_type
= ctl
->data
.register_data
.ulp_type
;
14839 if (CHIP_IS_E3(bp
)) {
14840 int idx
= BP_FW_MB_IDX(bp
);
14841 u32 cap
= SHMEM2_RD(bp
, drv_capabilities_flag
[idx
]);
14842 int path
= BP_PATH(bp
);
14843 int port
= BP_PORT(bp
);
14845 u32 scratch_offset
;
14848 /* first write capability to shmem2 */
14849 if (ulp_type
== CNIC_ULP_ISCSI
)
14850 cap
|= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI
;
14851 else if (ulp_type
== CNIC_ULP_FCOE
)
14852 cap
|= DRV_FLAGS_CAPABILITIES_LOADED_FCOE
;
14853 SHMEM2_WR(bp
, drv_capabilities_flag
[idx
], cap
);
14855 if ((ulp_type
!= CNIC_ULP_FCOE
) ||
14856 (!SHMEM2_HAS(bp
, ncsi_oem_data_addr
)) ||
14857 (!(bp
->flags
& BC_SUPPORTS_FCOE_FEATURES
)))
14860 /* if reached here - should write fcoe capabilities */
14861 scratch_offset
= SHMEM2_RD(bp
, ncsi_oem_data_addr
);
14862 if (!scratch_offset
)
14864 scratch_offset
+= offsetof(struct glob_ncsi_oem_data
,
14865 fcoe_features
[path
][port
]);
14866 host_addr
= (u32
*) &(ctl
->data
.register_data
.
14868 for (i
= 0; i
< sizeof(struct fcoe_capabilities
);
14870 REG_WR(bp
, scratch_offset
+ i
,
14871 *(host_addr
+ i
/4));
14873 bnx2x_schedule_sp_rtnl(bp
, BNX2X_SP_RTNL_GET_DRV_VERSION
, 0);
14877 case DRV_CTL_ULP_UNREGISTER_CMD
: {
14878 int ulp_type
= ctl
->data
.ulp_type
;
14880 if (CHIP_IS_E3(bp
)) {
14881 int idx
= BP_FW_MB_IDX(bp
);
14884 cap
= SHMEM2_RD(bp
, drv_capabilities_flag
[idx
]);
14885 if (ulp_type
== CNIC_ULP_ISCSI
)
14886 cap
&= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI
;
14887 else if (ulp_type
== CNIC_ULP_FCOE
)
14888 cap
&= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE
;
14889 SHMEM2_WR(bp
, drv_capabilities_flag
[idx
], cap
);
14891 bnx2x_schedule_sp_rtnl(bp
, BNX2X_SP_RTNL_GET_DRV_VERSION
, 0);
14896 BNX2X_ERR("unknown command %x\n", ctl
->cmd
);
14900 /* For storage-only interfaces, change driver state */
14901 if (IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp
)) {
14902 switch (ctl
->drv_state
) {
14906 bnx2x_set_os_driver_state(bp
,
14907 OS_DRIVER_STATE_ACTIVE
);
14910 bnx2x_set_os_driver_state(bp
,
14911 OS_DRIVER_STATE_DISABLED
);
14914 bnx2x_set_os_driver_state(bp
,
14915 OS_DRIVER_STATE_NOT_LOADED
);
14918 BNX2X_ERR("Unknown cnic driver state: %d\n", ctl
->drv_state
);
14925 static int bnx2x_get_fc_npiv(struct net_device
*dev
,
14926 struct cnic_fc_npiv_tbl
*cnic_tbl
)
14928 struct bnx2x
*bp
= netdev_priv(dev
);
14929 struct bdn_fc_npiv_tbl
*tbl
= NULL
;
14930 u32 offset
, entries
;
14934 if (!SHMEM2_HAS(bp
, fc_npiv_nvram_tbl_addr
[0]))
14937 DP(BNX2X_MSG_MCP
, "About to read the FC-NPIV table\n");
14939 tbl
= kmalloc(sizeof(*tbl
), GFP_KERNEL
);
14941 BNX2X_ERR("Failed to allocate fc_npiv table\n");
14945 offset
= SHMEM2_RD(bp
, fc_npiv_nvram_tbl_addr
[BP_PORT(bp
)]);
14947 DP(BNX2X_MSG_MCP
, "No FC-NPIV in NVRAM\n");
14950 DP(BNX2X_MSG_MCP
, "Offset of FC-NPIV in NVRAM: %08x\n", offset
);
14952 /* Read the table contents from nvram */
14953 if (bnx2x_nvram_read(bp
, offset
, (u8
*)tbl
, sizeof(*tbl
))) {
14954 BNX2X_ERR("Failed to read FC-NPIV table\n");
14958 /* Since bnx2x_nvram_read() returns data in be32, we need to convert
14959 * the number of entries back to cpu endianness.
14961 entries
= tbl
->fc_npiv_cfg
.num_of_npiv
;
14962 entries
= (__force u32
)be32_to_cpu((__force __be32
)entries
);
14963 tbl
->fc_npiv_cfg
.num_of_npiv
= entries
;
14965 if (!tbl
->fc_npiv_cfg
.num_of_npiv
) {
14967 "No FC-NPIV table [valid, simply not present]\n");
14969 } else if (tbl
->fc_npiv_cfg
.num_of_npiv
> MAX_NUMBER_NPIV
) {
14970 BNX2X_ERR("FC-NPIV table with bad length 0x%08x\n",
14971 tbl
->fc_npiv_cfg
.num_of_npiv
);
14974 DP(BNX2X_MSG_MCP
, "Read 0x%08x entries from NVRAM\n",
14975 tbl
->fc_npiv_cfg
.num_of_npiv
);
14978 /* Copy the data into cnic-provided struct */
14979 cnic_tbl
->count
= tbl
->fc_npiv_cfg
.num_of_npiv
;
14980 for (i
= 0; i
< cnic_tbl
->count
; i
++) {
14981 memcpy(cnic_tbl
->wwpn
[i
], tbl
->settings
[i
].npiv_wwpn
, 8);
14982 memcpy(cnic_tbl
->wwnn
[i
], tbl
->settings
[i
].npiv_wwnn
, 8);
14991 void bnx2x_setup_cnic_irq_info(struct bnx2x
*bp
)
14993 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
14995 if (bp
->flags
& USING_MSIX_FLAG
) {
14996 cp
->drv_state
|= CNIC_DRV_STATE_USING_MSIX
;
14997 cp
->irq_arr
[0].irq_flags
|= CNIC_IRQ_FL_MSIX
;
14998 cp
->irq_arr
[0].vector
= bp
->msix_table
[1].vector
;
15000 cp
->drv_state
&= ~CNIC_DRV_STATE_USING_MSIX
;
15001 cp
->irq_arr
[0].irq_flags
&= ~CNIC_IRQ_FL_MSIX
;
15003 if (!CHIP_IS_E1x(bp
))
15004 cp
->irq_arr
[0].status_blk
= (void *)bp
->cnic_sb
.e2_sb
;
15006 cp
->irq_arr
[0].status_blk
= (void *)bp
->cnic_sb
.e1x_sb
;
15008 cp
->irq_arr
[0].status_blk_num
= bnx2x_cnic_fw_sb_id(bp
);
15009 cp
->irq_arr
[0].status_blk_num2
= bnx2x_cnic_igu_sb_id(bp
);
15010 cp
->irq_arr
[1].status_blk
= bp
->def_status_blk
;
15011 cp
->irq_arr
[1].status_blk_num
= DEF_SB_ID
;
15012 cp
->irq_arr
[1].status_blk_num2
= DEF_SB_IGU_ID
;
15017 void bnx2x_setup_cnic_info(struct bnx2x
*bp
)
15019 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
15021 cp
->ctx_tbl_offset
= FUNC_ILT_BASE(BP_FUNC(bp
)) +
15022 bnx2x_cid_ilt_lines(bp
);
15023 cp
->starting_cid
= bnx2x_cid_ilt_lines(bp
) * ILT_PAGE_CIDS
;
15024 cp
->fcoe_init_cid
= BNX2X_FCOE_ETH_CID(bp
);
15025 cp
->iscsi_l2_cid
= BNX2X_ISCSI_ETH_CID(bp
);
15027 DP(NETIF_MSG_IFUP
, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n",
15028 BNX2X_1st_NON_L2_ETH_CID(bp
), cp
->starting_cid
, cp
->fcoe_init_cid
,
15031 if (NO_ISCSI_OOO(bp
))
15032 cp
->drv_state
|= CNIC_DRV_STATE_NO_ISCSI_OOO
;
15035 static int bnx2x_register_cnic(struct net_device
*dev
, struct cnic_ops
*ops
,
15038 struct bnx2x
*bp
= netdev_priv(dev
);
15039 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
15042 DP(NETIF_MSG_IFUP
, "Register_cnic called\n");
15045 BNX2X_ERR("NULL ops received\n");
15049 if (!CNIC_SUPPORT(bp
)) {
15050 BNX2X_ERR("Can't register CNIC when not supported\n");
15051 return -EOPNOTSUPP
;
15054 if (!CNIC_LOADED(bp
)) {
15055 rc
= bnx2x_load_cnic(bp
);
15057 BNX2X_ERR("CNIC-related load failed\n");
15062 bp
->cnic_enabled
= true;
15064 bp
->cnic_kwq
= kzalloc(PAGE_SIZE
, GFP_KERNEL
);
15068 bp
->cnic_kwq_cons
= bp
->cnic_kwq
;
15069 bp
->cnic_kwq_prod
= bp
->cnic_kwq
;
15070 bp
->cnic_kwq_last
= bp
->cnic_kwq
+ MAX_SP_DESC_CNT
;
15072 bp
->cnic_spq_pending
= 0;
15073 bp
->cnic_kwq_pending
= 0;
15075 bp
->cnic_data
= data
;
15078 cp
->drv_state
|= CNIC_DRV_STATE_REGD
;
15079 cp
->iro_arr
= bp
->iro_arr
;
15081 bnx2x_setup_cnic_irq_info(bp
);
15083 rcu_assign_pointer(bp
->cnic_ops
, ops
);
15085 /* Schedule driver to read CNIC driver versions */
15086 bnx2x_schedule_sp_rtnl(bp
, BNX2X_SP_RTNL_GET_DRV_VERSION
, 0);
15091 static int bnx2x_unregister_cnic(struct net_device
*dev
)
15093 struct bnx2x
*bp
= netdev_priv(dev
);
15094 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
15096 mutex_lock(&bp
->cnic_mutex
);
15098 RCU_INIT_POINTER(bp
->cnic_ops
, NULL
);
15099 mutex_unlock(&bp
->cnic_mutex
);
15101 bp
->cnic_enabled
= false;
15102 kfree(bp
->cnic_kwq
);
15103 bp
->cnic_kwq
= NULL
;
15108 static struct cnic_eth_dev
*bnx2x_cnic_probe(struct net_device
*dev
)
15110 struct bnx2x
*bp
= netdev_priv(dev
);
15111 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
15113 /* If both iSCSI and FCoE are disabled - return NULL in
15114 * order to indicate CNIC that it should not try to work
15115 * with this device.
15117 if (NO_ISCSI(bp
) && NO_FCOE(bp
))
15120 cp
->drv_owner
= THIS_MODULE
;
15121 cp
->chip_id
= CHIP_ID(bp
);
15122 cp
->pdev
= bp
->pdev
;
15123 cp
->io_base
= bp
->regview
;
15124 cp
->io_base2
= bp
->doorbells
;
15125 cp
->max_kwqe_pending
= 8;
15126 cp
->ctx_blk_size
= CDU_ILT_PAGE_SZ
;
15127 cp
->ctx_tbl_offset
= FUNC_ILT_BASE(BP_FUNC(bp
)) +
15128 bnx2x_cid_ilt_lines(bp
);
15129 cp
->ctx_tbl_len
= CNIC_ILT_LINES
;
15130 cp
->starting_cid
= bnx2x_cid_ilt_lines(bp
) * ILT_PAGE_CIDS
;
15131 cp
->drv_submit_kwqes_16
= bnx2x_cnic_sp_queue
;
15132 cp
->drv_ctl
= bnx2x_drv_ctl
;
15133 cp
->drv_get_fc_npiv_tbl
= bnx2x_get_fc_npiv
;
15134 cp
->drv_register_cnic
= bnx2x_register_cnic
;
15135 cp
->drv_unregister_cnic
= bnx2x_unregister_cnic
;
15136 cp
->fcoe_init_cid
= BNX2X_FCOE_ETH_CID(bp
);
15137 cp
->iscsi_l2_client_id
=
15138 bnx2x_cnic_eth_cl_id(bp
, BNX2X_ISCSI_ETH_CL_ID_IDX
);
15139 cp
->iscsi_l2_cid
= BNX2X_ISCSI_ETH_CID(bp
);
15141 if (NO_ISCSI_OOO(bp
))
15142 cp
->drv_state
|= CNIC_DRV_STATE_NO_ISCSI_OOO
;
15145 cp
->drv_state
|= CNIC_DRV_STATE_NO_ISCSI
;
15148 cp
->drv_state
|= CNIC_DRV_STATE_NO_FCOE
;
15151 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
15153 cp
->ctx_tbl_offset
,
15159 static u32
bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath
*fp
)
15161 struct bnx2x
*bp
= fp
->bp
;
15162 u32 offset
= BAR_USTRORM_INTMEM
;
15165 return bnx2x_vf_ustorm_prods_offset(bp
, fp
);
15166 else if (!CHIP_IS_E1x(bp
))
15167 offset
+= USTORM_RX_PRODS_E2_OFFSET(fp
->cl_qzone_id
);
15169 offset
+= USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp
), fp
->cl_id
);
15174 /* called only on E1H or E2.
15175 * When pretending to be PF, the pretend value is the function number 0...7
15176 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
15179 int bnx2x_pretend_func(struct bnx2x
*bp
, u16 pretend_func_val
)
15183 if (CHIP_IS_E1H(bp
) && pretend_func_val
>= E1H_FUNC_MAX
)
15186 /* get my own pretend register */
15187 pretend_reg
= bnx2x_get_pretend_reg(bp
);
15188 REG_WR(bp
, pretend_reg
, pretend_func_val
);
15189 REG_RD(bp
, pretend_reg
);
15193 static void bnx2x_ptp_task(struct work_struct
*work
)
15195 struct bnx2x
*bp
= container_of(work
, struct bnx2x
, ptp_task
);
15196 int port
= BP_PORT(bp
);
15199 struct skb_shared_hwtstamps shhwtstamps
;
15201 /* Read Tx timestamp registers */
15202 val_seq
= REG_RD(bp
, port
? NIG_REG_P1_TLLH_PTP_BUF_SEQID
:
15203 NIG_REG_P0_TLLH_PTP_BUF_SEQID
);
15204 if (val_seq
& 0x10000) {
15205 /* There is a valid timestamp value */
15206 timestamp
= REG_RD(bp
, port
? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB
:
15207 NIG_REG_P0_TLLH_PTP_BUF_TS_MSB
);
15209 timestamp
|= REG_RD(bp
, port
? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB
:
15210 NIG_REG_P0_TLLH_PTP_BUF_TS_LSB
);
15211 /* Reset timestamp register to allow new timestamp */
15212 REG_WR(bp
, port
? NIG_REG_P1_TLLH_PTP_BUF_SEQID
:
15213 NIG_REG_P0_TLLH_PTP_BUF_SEQID
, 0x10000);
15214 ns
= timecounter_cyc2time(&bp
->timecounter
, timestamp
);
15216 memset(&shhwtstamps
, 0, sizeof(shhwtstamps
));
15217 shhwtstamps
.hwtstamp
= ns_to_ktime(ns
);
15218 skb_tstamp_tx(bp
->ptp_tx_skb
, &shhwtstamps
);
15219 dev_kfree_skb_any(bp
->ptp_tx_skb
);
15220 bp
->ptp_tx_skb
= NULL
;
15222 DP(BNX2X_MSG_PTP
, "Tx timestamp, timestamp cycles = %llu, ns = %llu\n",
15225 DP(BNX2X_MSG_PTP
, "There is no valid Tx timestamp yet\n");
15226 /* Reschedule to keep checking for a valid timestamp value */
15227 schedule_work(&bp
->ptp_task
);
15231 void bnx2x_set_rx_ts(struct bnx2x
*bp
, struct sk_buff
*skb
)
15233 int port
= BP_PORT(bp
);
15236 timestamp
= REG_RD(bp
, port
? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB
:
15237 NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB
);
15239 timestamp
|= REG_RD(bp
, port
? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB
:
15240 NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB
);
15242 /* Reset timestamp register to allow new timestamp */
15243 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID
:
15244 NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID
, 0x10000);
15246 ns
= timecounter_cyc2time(&bp
->timecounter
, timestamp
);
15248 skb_hwtstamps(skb
)->hwtstamp
= ns_to_ktime(ns
);
15250 DP(BNX2X_MSG_PTP
, "Rx timestamp, timestamp cycles = %llu, ns = %llu\n",
15255 static u64
bnx2x_cyclecounter_read(const struct cyclecounter
*cc
)
15257 struct bnx2x
*bp
= container_of(cc
, struct bnx2x
, cyclecounter
);
15258 int port
= BP_PORT(bp
);
15262 REG_RD_DMAE(bp
, port
? NIG_REG_TIMESYNC_GEN_REG
+ tsgen_synctime_t1
:
15263 NIG_REG_TIMESYNC_GEN_REG
+ tsgen_synctime_t0
, wb_data
, 2);
15264 phc_cycles
= wb_data
[1];
15265 phc_cycles
= (phc_cycles
<< 32) + wb_data
[0];
15267 DP(BNX2X_MSG_PTP
, "PHC read cycles = %llu\n", phc_cycles
);
15272 static void bnx2x_init_cyclecounter(struct bnx2x
*bp
)
15274 memset(&bp
->cyclecounter
, 0, sizeof(bp
->cyclecounter
));
15275 bp
->cyclecounter
.read
= bnx2x_cyclecounter_read
;
15276 bp
->cyclecounter
.mask
= CYCLECOUNTER_MASK(64);
15277 bp
->cyclecounter
.shift
= 0;
15278 bp
->cyclecounter
.mult
= 1;
15281 static int bnx2x_send_reset_timesync_ramrod(struct bnx2x
*bp
)
15283 struct bnx2x_func_state_params func_params
= {NULL
};
15284 struct bnx2x_func_set_timesync_params
*set_timesync_params
=
15285 &func_params
.params
.set_timesync
;
15287 /* Prepare parameters for function state transitions */
15288 __set_bit(RAMROD_COMP_WAIT
, &func_params
.ramrod_flags
);
15289 __set_bit(RAMROD_RETRY
, &func_params
.ramrod_flags
);
15291 func_params
.f_obj
= &bp
->func_obj
;
15292 func_params
.cmd
= BNX2X_F_CMD_SET_TIMESYNC
;
15294 /* Function parameters */
15295 set_timesync_params
->drift_adjust_cmd
= TS_DRIFT_ADJUST_RESET
;
15296 set_timesync_params
->offset_cmd
= TS_OFFSET_KEEP
;
15298 return bnx2x_func_state_change(bp
, &func_params
);
15301 static int bnx2x_enable_ptp_packets(struct bnx2x
*bp
)
15303 struct bnx2x_queue_state_params q_params
;
15306 /* send queue update ramrod to enable PTP packets */
15307 memset(&q_params
, 0, sizeof(q_params
));
15308 __set_bit(RAMROD_COMP_WAIT
, &q_params
.ramrod_flags
);
15309 q_params
.cmd
= BNX2X_Q_CMD_UPDATE
;
15310 __set_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG
,
15311 &q_params
.params
.update
.update_flags
);
15312 __set_bit(BNX2X_Q_UPDATE_PTP_PKTS
,
15313 &q_params
.params
.update
.update_flags
);
15315 /* send the ramrod on all the queues of the PF */
15316 for_each_eth_queue(bp
, i
) {
15317 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
15319 /* Set the appropriate Queue object */
15320 q_params
.q_obj
= &bnx2x_sp_obj(bp
, fp
).q_obj
;
15322 /* Update the Queue state */
15323 rc
= bnx2x_queue_state_change(bp
, &q_params
);
15325 BNX2X_ERR("Failed to enable PTP packets\n");
15333 int bnx2x_configure_ptp_filters(struct bnx2x
*bp
)
15335 int port
= BP_PORT(bp
);
15338 if (!bp
->hwtstamp_ioctl_called
)
15341 switch (bp
->tx_type
) {
15342 case HWTSTAMP_TX_ON
:
15343 bp
->flags
|= TX_TIMESTAMPING_EN
;
15344 REG_WR(bp
, port
? NIG_REG_P1_TLLH_PTP_PARAM_MASK
:
15345 NIG_REG_P0_TLLH_PTP_PARAM_MASK
, 0x6AA);
15346 REG_WR(bp
, port
? NIG_REG_P1_TLLH_PTP_RULE_MASK
:
15347 NIG_REG_P0_TLLH_PTP_RULE_MASK
, 0x3EEE);
15349 case HWTSTAMP_TX_ONESTEP_SYNC
:
15350 BNX2X_ERR("One-step timestamping is not supported\n");
15354 switch (bp
->rx_filter
) {
15355 case HWTSTAMP_FILTER_NONE
:
15357 case HWTSTAMP_FILTER_ALL
:
15358 case HWTSTAMP_FILTER_SOME
:
15359 case HWTSTAMP_FILTER_NTP_ALL
:
15360 bp
->rx_filter
= HWTSTAMP_FILTER_NONE
;
15362 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT
:
15363 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC
:
15364 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ
:
15365 bp
->rx_filter
= HWTSTAMP_FILTER_PTP_V1_L4_EVENT
;
15366 /* Initialize PTP detection for UDP/IPv4 events */
15367 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_PARAM_MASK
:
15368 NIG_REG_P0_LLH_PTP_PARAM_MASK
, 0x7EE);
15369 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_RULE_MASK
:
15370 NIG_REG_P0_LLH_PTP_RULE_MASK
, 0x3FFE);
15372 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT
:
15373 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC
:
15374 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
:
15375 bp
->rx_filter
= HWTSTAMP_FILTER_PTP_V2_L4_EVENT
;
15376 /* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */
15377 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_PARAM_MASK
:
15378 NIG_REG_P0_LLH_PTP_PARAM_MASK
, 0x7EA);
15379 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_RULE_MASK
:
15380 NIG_REG_P0_LLH_PTP_RULE_MASK
, 0x3FEE);
15382 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT
:
15383 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC
:
15384 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ
:
15385 bp
->rx_filter
= HWTSTAMP_FILTER_PTP_V2_L2_EVENT
;
15386 /* Initialize PTP detection L2 events */
15387 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_PARAM_MASK
:
15388 NIG_REG_P0_LLH_PTP_PARAM_MASK
, 0x6BF);
15389 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_RULE_MASK
:
15390 NIG_REG_P0_LLH_PTP_RULE_MASK
, 0x3EFF);
15393 case HWTSTAMP_FILTER_PTP_V2_EVENT
:
15394 case HWTSTAMP_FILTER_PTP_V2_SYNC
:
15395 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ
:
15396 bp
->rx_filter
= HWTSTAMP_FILTER_PTP_V2_EVENT
;
15397 /* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */
15398 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_PARAM_MASK
:
15399 NIG_REG_P0_LLH_PTP_PARAM_MASK
, 0x6AA);
15400 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_RULE_MASK
:
15401 NIG_REG_P0_LLH_PTP_RULE_MASK
, 0x3EEE);
15405 /* Indicate to FW that this PF expects recorded PTP packets */
15406 rc
= bnx2x_enable_ptp_packets(bp
);
15410 /* Enable sending PTP packets to host */
15411 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_TO_HOST
:
15412 NIG_REG_P0_LLH_PTP_TO_HOST
, 0x1);
15417 static int bnx2x_hwtstamp_ioctl(struct bnx2x
*bp
, struct ifreq
*ifr
)
15419 struct hwtstamp_config config
;
15422 DP(BNX2X_MSG_PTP
, "HWTSTAMP IOCTL called\n");
15424 if (copy_from_user(&config
, ifr
->ifr_data
, sizeof(config
)))
15427 DP(BNX2X_MSG_PTP
, "Requested tx_type: %d, requested rx_filters = %d\n",
15428 config
.tx_type
, config
.rx_filter
);
15430 if (config
.flags
) {
15431 BNX2X_ERR("config.flags is reserved for future use\n");
15435 bp
->hwtstamp_ioctl_called
= 1;
15436 bp
->tx_type
= config
.tx_type
;
15437 bp
->rx_filter
= config
.rx_filter
;
15439 rc
= bnx2x_configure_ptp_filters(bp
);
15443 config
.rx_filter
= bp
->rx_filter
;
15445 return copy_to_user(ifr
->ifr_data
, &config
, sizeof(config
)) ?
15449 /* Configures HW for PTP */
15450 static int bnx2x_configure_ptp(struct bnx2x
*bp
)
15452 int rc
, port
= BP_PORT(bp
);
15455 /* Reset PTP event detection rules - will be configured in the IOCTL */
15456 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_PARAM_MASK
:
15457 NIG_REG_P0_LLH_PTP_PARAM_MASK
, 0x7FF);
15458 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_RULE_MASK
:
15459 NIG_REG_P0_LLH_PTP_RULE_MASK
, 0x3FFF);
15460 REG_WR(bp
, port
? NIG_REG_P1_TLLH_PTP_PARAM_MASK
:
15461 NIG_REG_P0_TLLH_PTP_PARAM_MASK
, 0x7FF);
15462 REG_WR(bp
, port
? NIG_REG_P1_TLLH_PTP_RULE_MASK
:
15463 NIG_REG_P0_TLLH_PTP_RULE_MASK
, 0x3FFF);
15465 /* Disable PTP packets to host - will be configured in the IOCTL*/
15466 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_TO_HOST
:
15467 NIG_REG_P0_LLH_PTP_TO_HOST
, 0x0);
15469 /* Enable the PTP feature */
15470 REG_WR(bp
, port
? NIG_REG_P1_PTP_EN
:
15471 NIG_REG_P0_PTP_EN
, 0x3F);
15473 /* Enable the free-running counter */
15476 REG_WR_DMAE(bp
, NIG_REG_TIMESYNC_GEN_REG
+ tsgen_ctrl
, wb_data
, 2);
15478 /* Reset drift register (offset register is not reset) */
15479 rc
= bnx2x_send_reset_timesync_ramrod(bp
);
15481 BNX2X_ERR("Failed to reset PHC drift register\n");
15485 /* Reset possibly old timestamps */
15486 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID
:
15487 NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID
, 0x10000);
15488 REG_WR(bp
, port
? NIG_REG_P1_TLLH_PTP_BUF_SEQID
:
15489 NIG_REG_P0_TLLH_PTP_BUF_SEQID
, 0x10000);
15494 /* Called during load, to initialize PTP-related stuff */
15495 void bnx2x_init_ptp(struct bnx2x
*bp
)
15499 /* Configure PTP in HW */
15500 rc
= bnx2x_configure_ptp(bp
);
15502 BNX2X_ERR("Stopping PTP initialization\n");
15506 /* Init work queue for Tx timestamping */
15507 INIT_WORK(&bp
->ptp_task
, bnx2x_ptp_task
);
15509 /* Init cyclecounter and timecounter. This is done only in the first
15510 * load. If done in every load, PTP application will fail when doing
15511 * unload / load (e.g. MTU change) while it is running.
15513 if (!bp
->timecounter_init_done
) {
15514 bnx2x_init_cyclecounter(bp
);
15515 timecounter_init(&bp
->timecounter
, &bp
->cyclecounter
,
15516 ktime_to_ns(ktime_get_real()));
15517 bp
->timecounter_init_done
= 1;
15520 DP(BNX2X_MSG_PTP
, "PTP initialization ended successfully\n");