drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h

   1 /* bnx2x_reg.h: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2011 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * The registers description starts with the register Access type followed
  10  * by size in bits. For example [RW 32]. The access types are:
  11  * R  - Read only
  12  * RC - Clear on read
  13  * RW - Read/Write
  14  * ST - Statistics register (clear on read)
  15  * W  - Write only
  16  * WB - Wide bus register - the size is over 32 bits and it should be
  17  *      read/write in consecutive 32 bits accesses
  18  * WR - Write Clear (write 1 to clear the bit)
  19  *
  20  */
  21 #ifndef BNX2X_REG_H
  22 #define BNX2X_REG_H
  23
  24 #define ATC_ATC_INT_STS_REG_ADDRESS_ERROR                        (0x1<<0)
  25 #define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS                (0x1<<2)
  26 #define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU               (0x1<<5)
  27 #define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT                (0x1<<3)
  28 #define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR                       (0x1<<4)
  29 #define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND                 (0x1<<1)
  30 /* [RW 1] Initiate the ATC array - reset all the valid bits */
  31 #define ATC_REG_ATC_INIT_ARRAY                                   0x1100b8
  32 /* [R 1] ATC initalization done */
  33 #define ATC_REG_ATC_INIT_DONE                                    0x1100bc
  34 /* [RC 6] Interrupt register #0 read clear */
  35 #define ATC_REG_ATC_INT_STS_CLR                                  0x1101c0
  36 /* [RW 5] Parity mask register #0 read/write */
  37 #define ATC_REG_ATC_PRTY_MASK                                    0x1101d8
  38 /* [RC 5] Parity register #0 read clear */
  39 #define ATC_REG_ATC_PRTY_STS_CLR                                 0x1101d0
  40 /* [RW 19] Interrupt mask register #0 read/write */
  41 #define BRB1_REG_BRB1_INT_MASK                                   0x60128
  42 /* [R 19] Interrupt register #0 read */
  43 #define BRB1_REG_BRB1_INT_STS                                    0x6011c
  44 /* [RW 4] Parity mask register #0 read/write */
  45 #define BRB1_REG_BRB1_PRTY_MASK                                  0x60138
  46 /* [R 4] Parity register #0 read */
  47 #define BRB1_REG_BRB1_PRTY_STS                                   0x6012c
  48 /* [RC 4] Parity register #0 read clear */
  49 #define BRB1_REG_BRB1_PRTY_STS_CLR                               0x60130
  50 /* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At
  51  * address BRB1_IND_FREE_LIST_PRS_CRDT+1 initialize free tail. At address
  52  * BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning -
  53  * following reset the first rbc access to this reg must be write; there can
  54  * be no more rbc writes after the first one; there can be any number of rbc
  55  * read following the first write; rbc access not following these rules will
  56  * result in hang condition. */
  57 #define BRB1_REG_FREE_LIST_PRS_CRDT                              0x60200
  58 /* [RW 10] The number of free blocks below which the full signal to class 0
  59  * is asserted */
  60 #define BRB1_REG_FULL_0_XOFF_THRESHOLD_0                         0x601d0
  61 #define BRB1_REG_FULL_0_XOFF_THRESHOLD_1                         0x60230
  62 /* [RW 11] The number of free blocks above which the full signal to class 0
  63  * is de-asserted */
  64 #define BRB1_REG_FULL_0_XON_THRESHOLD_0                          0x601d4
  65 #define BRB1_REG_FULL_0_XON_THRESHOLD_1                          0x60234
  66 /* [RW 11] The number of free blocks below which the full signal to class 1
  67  * is asserted */
  68 #define BRB1_REG_FULL_1_XOFF_THRESHOLD_0                         0x601d8
  69 #define BRB1_REG_FULL_1_XOFF_THRESHOLD_1                         0x60238
  70 /* [RW 11] The number of free blocks above which the full signal to class 1
  71  * is de-asserted */
  72 #define BRB1_REG_FULL_1_XON_THRESHOLD_0                          0x601dc
  73 #define BRB1_REG_FULL_1_XON_THRESHOLD_1                          0x6023c
  74 /* [RW 11] The number of free blocks below which the full signal to the LB
  75  * port is asserted */
  76 #define BRB1_REG_FULL_LB_XOFF_THRESHOLD                          0x601e0
  77 /* [RW 10] The number of free blocks above which the full signal to the LB
  78  * port is de-asserted */
  79 #define BRB1_REG_FULL_LB_XON_THRESHOLD                           0x601e4
  80 /* [RW 10] The number of free blocks above which the High_llfc signal to
  81    interface #n is de-asserted. */
  82 #define BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD_0                      0x6014c
  83 /* [RW 10] The number of free blocks below which the High_llfc signal to
  84    interface #n is asserted. */
  85 #define BRB1_REG_HIGH_LLFC_LOW_THRESHOLD_0                       0x6013c
  86 /* [RW 11] The number of blocks guarantied for the LB port */
  87 #define BRB1_REG_LB_GUARANTIED                                   0x601ec
  88 /* [RW 11] The hysteresis on the guarantied buffer space for the Lb port
  89  * before signaling XON. */
  90 #define BRB1_REG_LB_GUARANTIED_HYST                              0x60264
  91 /* [RW 24] LL RAM data. */
  92 #define BRB1_REG_LL_RAM                                          0x61000
  93 /* [RW 10] The number of free blocks above which the Low_llfc signal to
  94    interface #n is de-asserted. */
  95 #define BRB1_REG_LOW_LLFC_HIGH_THRESHOLD_0                       0x6016c
  96 /* [RW 10] The number of free blocks below which the Low_llfc signal to
  97    interface #n is asserted. */
  98 #define BRB1_REG_LOW_LLFC_LOW_THRESHOLD_0                        0x6015c
  99 /* [RW 11] The number of blocks guarantied for class 0 in MAC 0. The
 100  * register is applicable only when per_class_guaranty_mode is set. */
 101 #define BRB1_REG_MAC_0_CLASS_0_GUARANTIED                        0x60244
 102 /* [RW 11] The hysteresis on the guarantied buffer space for class 0 in MAC
 103  * 1 before signaling XON. The register is applicable only when
 104  * per_class_guaranty_mode is set. */
 105 #define BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST                   0x60254
 106 /* [RW 11] The number of blocks guarantied for class 1 in MAC 0. The
 107  * register is applicable only when per_class_guaranty_mode is set. */
 108 #define BRB1_REG_MAC_0_CLASS_1_GUARANTIED                        0x60248
 109 /* [RW 11] The hysteresis on the guarantied buffer space for class 1in MAC 0
 110  * before signaling XON. The register is applicable only when
 111  * per_class_guaranty_mode is set. */
 112 #define BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST                   0x60258
 113 /* [RW 11] The number of blocks guarantied for class 0in MAC1.The register
 114  * is applicable only when per_class_guaranty_mode is set. */
 115 #define BRB1_REG_MAC_1_CLASS_0_GUARANTIED                        0x6024c
 116 /* [RW 11] The hysteresis on the guarantied buffer space for class 0 in MAC
 117  * 1 before signaling XON. The register is applicable only when
 118  * per_class_guaranty_mode is set. */
 119 #define BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST                   0x6025c
 120 /* [RW 11] The number of blocks guarantied for class 1 in MAC 1. The
 121  * register is applicable only when per_class_guaranty_mode is set. */
 122 #define BRB1_REG_MAC_1_CLASS_1_GUARANTIED                        0x60250
 123 /* [RW 11] The hysteresis on the guarantied buffer space for class 1 in MAC
 124  * 1 before signaling XON. The register is applicable only when
 125  * per_class_guaranty_mode is set. */
 126 #define BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST                   0x60260
 127 /* [RW 11] The number of blocks guarantied for the MAC port. The register is
 128  * applicable only when per_class_guaranty_mode is reset. */
 129 #define BRB1_REG_MAC_GUARANTIED_0                                0x601e8
 130 #define BRB1_REG_MAC_GUARANTIED_1                                0x60240
 131 /* [R 24] The number of full blocks. */
 132 #define BRB1_REG_NUM_OF_FULL_BLOCKS                              0x60090
 133 /* [ST 32] The number of cycles that the write_full signal towards MAC #0
 134    was asserted. */
 135 #define BRB1_REG_NUM_OF_FULL_CYCLES_0                            0x600c8
 136 #define BRB1_REG_NUM_OF_FULL_CYCLES_1                            0x600cc
 137 #define BRB1_REG_NUM_OF_FULL_CYCLES_4                            0x600d8
 138 /* [ST 32] The number of cycles that the pause signal towards MAC #0 was
 139    asserted. */
 140 #define BRB1_REG_NUM_OF_PAUSE_CYCLES_0                           0x600b8
 141 #define BRB1_REG_NUM_OF_PAUSE_CYCLES_1                           0x600bc
 142 /* [RW 10] The number of free blocks below which the pause signal to class 0
 143  * is asserted */
 144 #define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0                        0x601c0
 145 #define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1                        0x60220
 146 /* [RW 11] The number of free blocks above which the pause signal to class 0
 147  * is de-asserted */
 148 #define BRB1_REG_PAUSE_0_XON_THRESHOLD_0                         0x601c4
 149 #define BRB1_REG_PAUSE_0_XON_THRESHOLD_1                         0x60224
 150 /* [RW 11] The number of free blocks below which the pause signal to class 1
 151  * is asserted */
 152 #define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0                        0x601c8
 153 #define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1                        0x60228
 154 /* [RW 11] The number of free blocks above which the pause signal to class 1
 155  * is de-asserted */
 156 #define BRB1_REG_PAUSE_1_XON_THRESHOLD_0                         0x601cc
 157 #define BRB1_REG_PAUSE_1_XON_THRESHOLD_1                         0x6022c
 158 /* [RW 10] Write client 0: De-assert pause threshold. Not Functional */
 159 #define BRB1_REG_PAUSE_HIGH_THRESHOLD_0                          0x60078
 160 #define BRB1_REG_PAUSE_HIGH_THRESHOLD_1                          0x6007c
 161 /* [RW 10] Write client 0: Assert pause threshold. */
 162 #define BRB1_REG_PAUSE_LOW_THRESHOLD_0                           0x60068
 163 /* [RW 1] Indicates if to use per-class guaranty mode (new mode) or per-MAC
 164  * guaranty mode (backwards-compatible mode). 0=per-MAC guaranty mode (BC
 165  * mode). 1=per-class guaranty mode (new mode). */
 166 #define BRB1_REG_PER_CLASS_GUARANTY_MODE                         0x60268
 167 /* [R 24] The number of full blocks occpied by port. */
 168 #define BRB1_REG_PORT_NUM_OCC_BLOCKS_0                           0x60094
 169 /* [RW 1] Reset the design by software. */
 170 #define BRB1_REG_SOFT_RESET                                      0x600dc
 171 /* [R 5] Used to read the value of the XX protection CAM occupancy counter. */
 172 #define CCM_REG_CAM_OCCUP                                        0xd0188
 173 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
 174    acknowledge output is deasserted; all other signals are treated as usual;
 175    if 1 - normal activity. */
 176 #define CCM_REG_CCM_CFC_IFEN                                     0xd003c
 177 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
 178    disregarded; valid is deasserted; all other signals are treated as usual;
 179    if 1 - normal activity. */
 180 #define CCM_REG_CCM_CQM_IFEN                                     0xd000c
 181 /* [RW 1] If set the Q index; received from the QM is inserted to event ID.
 182    Otherwise 0 is inserted. */
 183 #define CCM_REG_CCM_CQM_USE_Q                                    0xd00c0
 184 /* [RW 11] Interrupt mask register #0 read/write */
 185 #define CCM_REG_CCM_INT_MASK                                     0xd01e4
 186 /* [R 11] Interrupt register #0 read */
 187 #define CCM_REG_CCM_INT_STS                                      0xd01d8
 188 /* [RW 27] Parity mask register #0 read/write */
 189 #define CCM_REG_CCM_PRTY_MASK                                    0xd01f4
 190 /* [R 27] Parity register #0 read */
 191 #define CCM_REG_CCM_PRTY_STS                                     0xd01e8
 192 /* [RC 27] Parity register #0 read clear */
 193 #define CCM_REG_CCM_PRTY_STS_CLR                                 0xd01ec
 194 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
 195    REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
 196    Is used to determine the number of the AG context REG-pairs written back;
 197    when the input message Reg1WbFlg isn't set. */
 198 #define CCM_REG_CCM_REG0_SZ                                      0xd00c4
 199 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
 200    disregarded; valid is deasserted; all other signals are treated as usual;
 201    if 1 - normal activity. */
 202 #define CCM_REG_CCM_STORM0_IFEN                                  0xd0004
 203 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
 204    disregarded; valid is deasserted; all other signals are treated as usual;
 205    if 1 - normal activity. */
 206 #define CCM_REG_CCM_STORM1_IFEN                                  0xd0008
 207 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
 208    disregarded; valid output is deasserted; all other signals are treated as
 209    usual; if 1 - normal activity. */
 210 #define CCM_REG_CDU_AG_RD_IFEN                                   0xd0030
 211 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
 212    are disregarded; all other signals are treated as usual; if 1 - normal
 213    activity. */
 214 #define CCM_REG_CDU_AG_WR_IFEN                                   0xd002c
 215 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
 216    disregarded; valid output is deasserted; all other signals are treated as
 217    usual; if 1 - normal activity. */
 218 #define CCM_REG_CDU_SM_RD_IFEN                                   0xd0038
 219 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
 220    input is disregarded; all other signals are treated as usual; if 1 -
 221    normal activity. */
 222 #define CCM_REG_CDU_SM_WR_IFEN                                   0xd0034
 223 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
 224    the initial credit value; read returns the current value of the credit
 225    counter. Must be initialized to 1 at start-up. */
 226 #define CCM_REG_CFC_INIT_CRD                                     0xd0204
 227 /* [RW 2] Auxiliary counter flag Q number 1. */
 228 #define CCM_REG_CNT_AUX1_Q                                       0xd00c8
 229 /* [RW 2] Auxiliary counter flag Q number 2. */
 230 #define CCM_REG_CNT_AUX2_Q                                       0xd00cc
 231 /* [RW 28] The CM header value for QM request (primary). */
 232 #define CCM_REG_CQM_CCM_HDR_P                                    0xd008c
 233 /* [RW 28] The CM header value for QM request (secondary). */
 234 #define CCM_REG_CQM_CCM_HDR_S                                    0xd0090
 235 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
 236    acknowledge output is deasserted; all other signals are treated as usual;
 237    if 1 - normal activity. */
 238 #define CCM_REG_CQM_CCM_IFEN                                     0xd0014
 239 /* [RW 6] QM output initial credit. Max credit available - 32. Write writes
 240    the initial credit value; read returns the current value of the credit
 241    counter. Must be initialized to 32 at start-up. */
 242 #define CCM_REG_CQM_INIT_CRD                                     0xd020c
 243 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
 244    stands for weight 8 (the most prioritised); 1 stands for weight 1(least
 245    prioritised); 2 stands for weight 2; tc. */
 246 #define CCM_REG_CQM_P_WEIGHT                                     0xd00b8
 247 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
 248    stands for weight 8 (the most prioritised); 1 stands for weight 1(least
 249    prioritised); 2 stands for weight 2; tc. */
 250 #define CCM_REG_CQM_S_WEIGHT                                     0xd00bc
 251 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
 252    acknowledge output is deasserted; all other signals are treated as usual;
 253    if 1 - normal activity. */
 254 #define CCM_REG_CSDM_IFEN                                        0xd0018
 255 /* [RC 1] Set when the message length mismatch (relative to last indication)
 256    at the SDM interface is detected. */
 257 #define CCM_REG_CSDM_LENGTH_MIS                                  0xd0170
 258 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
 259    weight 8 (the most prioritised); 1 stands for weight 1(least
 260    prioritised); 2 stands for weight 2; tc. */
 261 #define CCM_REG_CSDM_WEIGHT                                      0xd00b4
 262 /* [RW 28] The CM header for QM formatting in case of an error in the QM
 263    inputs. */
 264 #define CCM_REG_ERR_CCM_HDR                                      0xd0094
 265 /* [RW 8] The Event ID in case the input message ErrorFlg is set. */
 266 #define CCM_REG_ERR_EVNT_ID                                      0xd0098
 267 /* [RW 8] FIC0 output initial credit. Max credit available - 255. Write
 268    writes the initial credit value; read returns the current value of the
 269    credit counter. Must be initialized to 64 at start-up. */
 270 #define CCM_REG_FIC0_INIT_CRD                                    0xd0210
 271 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
 272    writes the initial credit value; read returns the current value of the
 273    credit counter. Must be initialized to 64 at start-up. */
 274 #define CCM_REG_FIC1_INIT_CRD                                    0xd0214
 275 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
 276    - strict priority defined by ~ccm_registers_gr_ag_pr.gr_ag_pr;
 277    ~ccm_registers_gr_ld0_pr.gr_ld0_pr and
 278    ~ccm_registers_gr_ld1_pr.gr_ld1_pr. Groups are according to channels and
 279    outputs to STORM: aggregation; load FIC0; load FIC1 and store. */
 280 #define CCM_REG_GR_ARB_TYPE                                      0xd015c
 281 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
 282    highest priority is 3. It is supposed; that the Store channel priority is
 283    the compliment to 4 of the rest priorities - Aggregation channel; Load
 284    (FIC0) channel and Load (FIC1). */
 285 #define CCM_REG_GR_LD0_PR                                        0xd0164
 286 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
 287    highest priority is 3. It is supposed; that the Store channel priority is
 288    the compliment to 4 of the rest priorities - Aggregation channel; Load
 289    (FIC0) channel and Load (FIC1). */
 290 #define CCM_REG_GR_LD1_PR                                        0xd0168
 291 /* [RW 2] General flags index. */
 292 #define CCM_REG_INV_DONE_Q                                       0xd0108
 293 /* [RW 4] The number of double REG-pairs(128 bits); loaded from the STORM
 294    context and sent to STORM; for a specific connection type. The double
 295    REG-pairs are used in order to align to STORM context row size of 128
 296    bits. The offset of these data in the STORM context is always 0. Index
 297    _(0..15) stands for the connection type (one of 16). */
 298 #define CCM_REG_N_SM_CTX_LD_0                                    0xd004c
 299 #define CCM_REG_N_SM_CTX_LD_1                                    0xd0050
 300 #define CCM_REG_N_SM_CTX_LD_2                                    0xd0054
 301 #define CCM_REG_N_SM_CTX_LD_3                                    0xd0058
 302 #define CCM_REG_N_SM_CTX_LD_4                                    0xd005c
 303 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
 304    acknowledge output is deasserted; all other signals are treated as usual;
 305    if 1 - normal activity. */
 306 #define CCM_REG_PBF_IFEN                                         0xd0028
 307 /* [RC 1] Set when the message length mismatch (relative to last indication)
 308    at the pbf interface is detected. */
 309 #define CCM_REG_PBF_LENGTH_MIS                                   0xd0180
 310 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
 311    weight 8 (the most prioritised); 1 stands for weight 1(least
 312    prioritised); 2 stands for weight 2; tc. */
 313 #define CCM_REG_PBF_WEIGHT                                       0xd00ac
 314 #define CCM_REG_PHYS_QNUM1_0                                     0xd0134
 315 #define CCM_REG_PHYS_QNUM1_1                                     0xd0138
 316 #define CCM_REG_PHYS_QNUM2_0                                     0xd013c
 317 #define CCM_REG_PHYS_QNUM2_1                                     0xd0140
 318 #define CCM_REG_PHYS_QNUM3_0                                     0xd0144
 319 #define CCM_REG_PHYS_QNUM3_1                                     0xd0148
 320 #define CCM_REG_QOS_PHYS_QNUM0_0                                 0xd0114
 321 #define CCM_REG_QOS_PHYS_QNUM0_1                                 0xd0118
 322 #define CCM_REG_QOS_PHYS_QNUM1_0                                 0xd011c
 323 #define CCM_REG_QOS_PHYS_QNUM1_1                                 0xd0120
 324 #define CCM_REG_QOS_PHYS_QNUM2_0                                 0xd0124
 325 #define CCM_REG_QOS_PHYS_QNUM2_1                                 0xd0128
 326 #define CCM_REG_QOS_PHYS_QNUM3_0                                 0xd012c
 327 #define CCM_REG_QOS_PHYS_QNUM3_1                                 0xd0130
 328 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
 329    disregarded; acknowledge output is deasserted; all other signals are
 330    treated as usual; if 1 - normal activity. */
 331 #define CCM_REG_STORM_CCM_IFEN                                   0xd0010
 332 /* [RC 1] Set when the message length mismatch (relative to last indication)
 333    at the STORM interface is detected. */
 334 #define CCM_REG_STORM_LENGTH_MIS                                 0xd016c
 335 /* [RW 3] The weight of the STORM input in the WRR (Weighted Round robin)
 336    mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for
 337    weight 1(least prioritised); 2 stands for weight 2 (more prioritised);
 338    tc. */
 339 #define CCM_REG_STORM_WEIGHT                                     0xd009c
 340 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
 341    disregarded; acknowledge output is deasserted; all other signals are
 342    treated as usual; if 1 - normal activity. */
 343 #define CCM_REG_TSEM_IFEN                                        0xd001c
 344 /* [RC 1] Set when the message length mismatch (relative to last indication)
 345    at the tsem interface is detected. */
 346 #define CCM_REG_TSEM_LENGTH_MIS                                  0xd0174
 347 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
 348    weight 8 (the most prioritised); 1 stands for weight 1(least
 349    prioritised); 2 stands for weight 2; tc. */
 350 #define CCM_REG_TSEM_WEIGHT                                      0xd00a0
 351 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
 352    disregarded; acknowledge output is deasserted; all other signals are
 353    treated as usual; if 1 - normal activity. */
 354 #define CCM_REG_USEM_IFEN                                        0xd0024
 355 /* [RC 1] Set when message length mismatch (relative to last indication) at
 356    the usem interface is detected. */
 357 #define CCM_REG_USEM_LENGTH_MIS                                  0xd017c
 358 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
 359    weight 8 (the most prioritised); 1 stands for weight 1(least
 360    prioritised); 2 stands for weight 2; tc. */
 361 #define CCM_REG_USEM_WEIGHT                                      0xd00a8
 362 /* [RW 1] Input xsem Interface enable. If 0 - the valid input is
 363    disregarded; acknowledge output is deasserted; all other signals are
 364    treated as usual; if 1 - normal activity. */
 365 #define CCM_REG_XSEM_IFEN                                        0xd0020
 366 /* [RC 1] Set when the message length mismatch (relative to last indication)
 367    at the xsem interface is detected. */
 368 #define CCM_REG_XSEM_LENGTH_MIS                                  0xd0178
 369 /* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
 370    weight 8 (the most prioritised); 1 stands for weight 1(least
 371    prioritised); 2 stands for weight 2; tc. */
 372 #define CCM_REG_XSEM_WEIGHT                                      0xd00a4
 373 /* [RW 19] Indirect access to the descriptor table of the XX protection
 374    mechanism. The fields are: [5:0] - message length; [12:6] - message
 375    pointer; 18:13] - next pointer. */
 376 #define CCM_REG_XX_DESCR_TABLE                                   0xd0300
 377 #define CCM_REG_XX_DESCR_TABLE_SIZE                              24
 378 /* [R 7] Used to read the value of XX protection Free counter. */
 379 #define CCM_REG_XX_FREE                                          0xd0184
 380 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
 381    of the Input Stage XX protection buffer by the XX protection pending
 382    messages. Max credit available - 127. Write writes the initial credit
 383    value; read returns the current value of the credit counter. Must be
 384    initialized to maximum XX protected message size - 2 at start-up. */
 385 #define CCM_REG_XX_INIT_CRD                                      0xd0220
 386 /* [RW 7] The maximum number of pending messages; which may be stored in XX
 387    protection. At read the ~ccm_registers_xx_free.xx_free counter is read.
 388    At write comprises the start value of the ~ccm_registers_xx_free.xx_free
 389    counter. */
 390 #define CCM_REG_XX_MSG_NUM                                       0xd0224
 391 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
 392 #define CCM_REG_XX_OVFL_EVNT_ID                                  0xd0044
 393 /* [RW 18] Indirect access to the XX table of the XX protection mechanism.
 394    The fields are: [5:0] - tail pointer; 11:6] - Link List size; 17:12] -
 395    header pointer. */
 396 #define CCM_REG_XX_TABLE                                         0xd0280
 397 #define CDU_REG_CDU_CHK_MASK0                                    0x101000
 398 #define CDU_REG_CDU_CHK_MASK1                                    0x101004
 399 #define CDU_REG_CDU_CONTROL0                                     0x101008
 400 #define CDU_REG_CDU_DEBUG                                        0x101010
 401 #define CDU_REG_CDU_GLOBAL_PARAMS                                0x101020
 402 /* [RW 7] Interrupt mask register #0 read/write */
 403 #define CDU_REG_CDU_INT_MASK                                     0x10103c
 404 /* [R 7] Interrupt register #0 read */
 405 #define CDU_REG_CDU_INT_STS                                      0x101030
 406 /* [RW 5] Parity mask register #0 read/write */
 407 #define CDU_REG_CDU_PRTY_MASK                                    0x10104c
 408 /* [R 5] Parity register #0 read */
 409 #define CDU_REG_CDU_PRTY_STS                                     0x101040
 410 /* [RC 5] Parity register #0 read clear */
 411 #define CDU_REG_CDU_PRTY_STS_CLR                                 0x101044
 412 /* [RC 32] logging of error data in case of a CDU load error:
 413    {expected_cid[15:0]; xpected_type[2:0]; xpected_region[2:0]; ctive_error;
 414    ype_error; ctual_active; ctual_compressed_context}; */
 415 #define CDU_REG_ERROR_DATA                                       0x101014
 416 /* [WB 216] L1TT ram access. each entry has the following format :
 417    {mrege_regions[7:0]; ffset12[5:0]...offset0[5:0];
 418    ength12[5:0]...length0[5:0]; d12[3:0]...id0[3:0]} */
 419 #define CDU_REG_L1TT                                             0x101800
 420 /* [WB 24] MATT ram access. each entry has the following
 421    format:{RegionLength[11:0]; egionOffset[11:0]} */
 422 #define CDU_REG_MATT                                             0x101100
 423 /* [RW 1] when this bit is set the CDU operates in e1hmf mode */
 424 #define CDU_REG_MF_MODE                                          0x101050
 425 /* [R 1] indication the initializing the activity counter by the hardware
 426    was done. */
 427 #define CFC_REG_AC_INIT_DONE                                     0x104078
 428 /* [RW 13] activity counter ram access */
 429 #define CFC_REG_ACTIVITY_COUNTER                                 0x104400
 430 #define CFC_REG_ACTIVITY_COUNTER_SIZE                            256
 431 /* [R 1] indication the initializing the cams by the hardware was done. */
 432 #define CFC_REG_CAM_INIT_DONE                                    0x10407c
 433 /* [RW 2] Interrupt mask register #0 read/write */
 434 #define CFC_REG_CFC_INT_MASK                                     0x104108
 435 /* [R 2] Interrupt register #0 read */
 436 #define CFC_REG_CFC_INT_STS                                      0x1040fc
 437 /* [RC 2] Interrupt register #0 read clear */
 438 #define CFC_REG_CFC_INT_STS_CLR                                  0x104100
 439 /* [RW 4] Parity mask register #0 read/write */
 440 #define CFC_REG_CFC_PRTY_MASK                                    0x104118
 441 /* [R 4] Parity register #0 read */
 442 #define CFC_REG_CFC_PRTY_STS                                     0x10410c
 443 /* [RC 4] Parity register #0 read clear */
 444 #define CFC_REG_CFC_PRTY_STS_CLR                                 0x104110
 445 /* [RW 21] CID cam access (21:1 - Data; alid - 0) */
 446 #define CFC_REG_CID_CAM                                          0x104800
 447 #define CFC_REG_CONTROL0                                         0x104028
 448 #define CFC_REG_DEBUG0                                           0x104050
 449 /* [RW 14] indicates per error (in #cfc_registers_cfc_error_vector.cfc_error
 450    vector) whether the cfc should be disabled upon it */
 451 #define CFC_REG_DISABLE_ON_ERROR                                 0x104044
 452 /* [RC 14] CFC error vector. when the CFC detects an internal error it will
 453    set one of these bits. the bit description can be found in CFC
 454    specifications */
 455 #define CFC_REG_ERROR_VECTOR                                     0x10403c
 456 /* [WB 93] LCID info ram access */
 457 #define CFC_REG_INFO_RAM                                         0x105000
 458 #define CFC_REG_INFO_RAM_SIZE                                    1024
 459 #define CFC_REG_INIT_REG                                         0x10404c
 460 #define CFC_REG_INTERFACES                                       0x104058
 461 /* [RW 24] {weight_load_client7[2:0] to weight_load_client0[2:0]}. this
 462    field allows changing the priorities of the weighted-round-robin arbiter
 463    which selects which CFC load client should be served next */
 464 #define CFC_REG_LCREQ_WEIGHTS                                    0x104084
 465 /* [RW 16] Link List ram access; data = {prev_lcid; ext_lcid} */
 466 #define CFC_REG_LINK_LIST                                        0x104c00
 467 #define CFC_REG_LINK_LIST_SIZE                                   256
 468 /* [R 1] indication the initializing the link list by the hardware was done. */
 469 #define CFC_REG_LL_INIT_DONE                                     0x104074
 470 /* [R 9] Number of allocated LCIDs which are at empty state */
 471 #define CFC_REG_NUM_LCIDS_ALLOC                                  0x104020
 472 /* [R 9] Number of Arriving LCIDs in Link List Block */
 473 #define CFC_REG_NUM_LCIDS_ARRIVING                               0x104004
 474 #define CFC_REG_NUM_LCIDS_INSIDE_PF                              0x104120
 475 /* [R 9] Number of Leaving LCIDs in Link List Block */
 476 #define CFC_REG_NUM_LCIDS_LEAVING                                0x104018
 477 #define CFC_REG_WEAK_ENABLE_PF                                   0x104124
 478 /* [RW 8] The event id for aggregated interrupt 0 */
 479 #define CSDM_REG_AGG_INT_EVENT_0                                 0xc2038
 480 #define CSDM_REG_AGG_INT_EVENT_10                                0xc2060
 481 #define CSDM_REG_AGG_INT_EVENT_11                                0xc2064
 482 #define CSDM_REG_AGG_INT_EVENT_12                                0xc2068
 483 #define CSDM_REG_AGG_INT_EVENT_13                                0xc206c
 484 #define CSDM_REG_AGG_INT_EVENT_14                                0xc2070
 485 #define CSDM_REG_AGG_INT_EVENT_15                                0xc2074
 486 #define CSDM_REG_AGG_INT_EVENT_16                                0xc2078
 487 #define CSDM_REG_AGG_INT_EVENT_2                                 0xc2040
 488 #define CSDM_REG_AGG_INT_EVENT_3                                 0xc2044
 489 #define CSDM_REG_AGG_INT_EVENT_4                                 0xc2048
 490 #define CSDM_REG_AGG_INT_EVENT_5                                 0xc204c
 491 #define CSDM_REG_AGG_INT_EVENT_6                                 0xc2050
 492 #define CSDM_REG_AGG_INT_EVENT_7                                 0xc2054
 493 #define CSDM_REG_AGG_INT_EVENT_8                                 0xc2058
 494 #define CSDM_REG_AGG_INT_EVENT_9                                 0xc205c
 495 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
 496    or auto-mask-mode (1) */
 497 #define CSDM_REG_AGG_INT_MODE_10                                 0xc21e0
 498 #define CSDM_REG_AGG_INT_MODE_11                                 0xc21e4
 499 #define CSDM_REG_AGG_INT_MODE_12                                 0xc21e8
 500 #define CSDM_REG_AGG_INT_MODE_13                                 0xc21ec
 501 #define CSDM_REG_AGG_INT_MODE_14                                 0xc21f0
 502 #define CSDM_REG_AGG_INT_MODE_15                                 0xc21f4
 503 #define CSDM_REG_AGG_INT_MODE_16                                 0xc21f8
 504 #define CSDM_REG_AGG_INT_MODE_6                                  0xc21d0
 505 #define CSDM_REG_AGG_INT_MODE_7                                  0xc21d4
 506 #define CSDM_REG_AGG_INT_MODE_8                                  0xc21d8
 507 #define CSDM_REG_AGG_INT_MODE_9                                  0xc21dc
 508 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
 509 #define CSDM_REG_CFC_RSP_START_ADDR                              0xc2008
 510 /* [RW 16] The maximum value of the completion counter #0 */
 511 #define CSDM_REG_CMP_COUNTER_MAX0                                0xc201c
 512 /* [RW 16] The maximum value of the completion counter #1 */
 513 #define CSDM_REG_CMP_COUNTER_MAX1                                0xc2020
 514 /* [RW 16] The maximum value of the completion counter #2 */
 515 #define CSDM_REG_CMP_COUNTER_MAX2                                0xc2024
 516 /* [RW 16] The maximum value of the completion counter #3 */
 517 #define CSDM_REG_CMP_COUNTER_MAX3                                0xc2028
 518 /* [RW 13] The start address in the internal RAM for the completion
 519    counters. */
 520 #define CSDM_REG_CMP_COUNTER_START_ADDR                          0xc200c
 521 /* [RW 32] Interrupt mask register #0 read/write */
 522 #define CSDM_REG_CSDM_INT_MASK_0                                 0xc229c
 523 #define CSDM_REG_CSDM_INT_MASK_1                                 0xc22ac
 524 /* [R 32] Interrupt register #0 read */
 525 #define CSDM_REG_CSDM_INT_STS_0                                  0xc2290
 526 #define CSDM_REG_CSDM_INT_STS_1                                  0xc22a0
 527 /* [RW 11] Parity mask register #0 read/write */
 528 #define CSDM_REG_CSDM_PRTY_MASK                                  0xc22bc
 529 /* [R 11] Parity register #0 read */
 530 #define CSDM_REG_CSDM_PRTY_STS                                   0xc22b0
 531 /* [RC 11] Parity register #0 read clear */
 532 #define CSDM_REG_CSDM_PRTY_STS_CLR                               0xc22b4
 533 #define CSDM_REG_ENABLE_IN1                                      0xc2238
 534 #define CSDM_REG_ENABLE_IN2                                      0xc223c
 535 #define CSDM_REG_ENABLE_OUT1                                     0xc2240
 536 #define CSDM_REG_ENABLE_OUT2                                     0xc2244
 537 /* [RW 4] The initial number of messages that can be sent to the pxp control
 538    interface without receiving any ACK. */
 539 #define CSDM_REG_INIT_CREDIT_PXP_CTRL                            0xc24bc
 540 /* [ST 32] The number of ACK after placement messages received */
 541 #define CSDM_REG_NUM_OF_ACK_AFTER_PLACE                          0xc227c
 542 /* [ST 32] The number of packet end messages received from the parser */
 543 #define CSDM_REG_NUM_OF_PKT_END_MSG                              0xc2274
 544 /* [ST 32] The number of requests received from the pxp async if */
 545 #define CSDM_REG_NUM_OF_PXP_ASYNC_REQ                            0xc2278
 546 /* [ST 32] The number of commands received in queue 0 */
 547 #define CSDM_REG_NUM_OF_Q0_CMD                                   0xc2248
 548 /* [ST 32] The number of commands received in queue 10 */
 549 #define CSDM_REG_NUM_OF_Q10_CMD                                  0xc226c
 550 /* [ST 32] The number of commands received in queue 11 */
 551 #define CSDM_REG_NUM_OF_Q11_CMD                                  0xc2270
 552 /* [ST 32] The number of commands received in queue 1 */
 553 #define CSDM_REG_NUM_OF_Q1_CMD                                   0xc224c
 554 /* [ST 32] The number of commands received in queue 3 */
 555 #define CSDM_REG_NUM_OF_Q3_CMD                                   0xc2250
 556 /* [ST 32] The number of commands received in queue 4 */
 557 #define CSDM_REG_NUM_OF_Q4_CMD                                   0xc2254
 558 /* [ST 32] The number of commands received in queue 5 */
 559 #define CSDM_REG_NUM_OF_Q5_CMD                                   0xc2258
 560 /* [ST 32] The number of commands received in queue 6 */
 561 #define CSDM_REG_NUM_OF_Q6_CMD                                   0xc225c
 562 /* [ST 32] The number of commands received in queue 7 */
 563 #define CSDM_REG_NUM_OF_Q7_CMD                                   0xc2260
 564 /* [ST 32] The number of commands received in queue 8 */
 565 #define CSDM_REG_NUM_OF_Q8_CMD                                   0xc2264
 566 /* [ST 32] The number of commands received in queue 9 */
 567 #define CSDM_REG_NUM_OF_Q9_CMD                                   0xc2268
 568 /* [RW 13] The start address in the internal RAM for queue counters */
 569 #define CSDM_REG_Q_COUNTER_START_ADDR                            0xc2010
 570 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
 571 #define CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY                        0xc2548
 572 /* [R 1] parser fifo empty in sdm_sync block */
 573 #define CSDM_REG_SYNC_PARSER_EMPTY                               0xc2550
 574 /* [R 1] parser serial fifo empty in sdm_sync block */
 575 #define CSDM_REG_SYNC_SYNC_EMPTY                                 0xc2558
 576 /* [RW 32] Tick for timer counter. Applicable only when
 577    ~csdm_registers_timer_tick_enable.timer_tick_enable =1 */
 578 #define CSDM_REG_TIMER_TICK                                      0xc2000
 579 /* [RW 5] The number of time_slots in the arbitration cycle */
 580 #define CSEM_REG_ARB_CYCLE_SIZE                                  0x200034
 581 /* [RW 3] The source that is associated with arbitration element 0. Source
 582    decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
 583    sleeping thread with priority 1; 4- sleeping thread with priority 2 */
 584 #define CSEM_REG_ARB_ELEMENT0                                    0x200020
 585 /* [RW 3] The source that is associated with arbitration element 1. Source
 586    decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
 587    sleeping thread with priority 1; 4- sleeping thread with priority 2.
 588    Could not be equal to register ~csem_registers_arb_element0.arb_element0 */
 589 #define CSEM_REG_ARB_ELEMENT1                                    0x200024
 590 /* [RW 3] The source that is associated with arbitration element 2. Source
 591    decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
 592    sleeping thread with priority 1; 4- sleeping thread with priority 2.
 593    Could not be equal to register ~csem_registers_arb_element0.arb_element0
 594    and ~csem_registers_arb_element1.arb_element1 */
 595 #define CSEM_REG_ARB_ELEMENT2                                    0x200028
 596 /* [RW 3] The source that is associated with arbitration element 3. Source
 597    decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
 598    sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
 599    not be equal to register ~csem_registers_arb_element0.arb_element0 and
 600    ~csem_registers_arb_element1.arb_element1 and
 601    ~csem_registers_arb_element2.arb_element2 */
 602 #define CSEM_REG_ARB_ELEMENT3                                    0x20002c
 603 /* [RW 3] The source that is associated with arbitration element 4. Source
 604    decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
 605    sleeping thread with priority 1; 4- sleeping thread with priority 2.
 606    Could not be equal to register ~csem_registers_arb_element0.arb_element0
 607    and ~csem_registers_arb_element1.arb_element1 and
 608    ~csem_registers_arb_element2.arb_element2 and
 609    ~csem_registers_arb_element3.arb_element3 */
 610 #define CSEM_REG_ARB_ELEMENT4                                    0x200030
 611 /* [RW 32] Interrupt mask register #0 read/write */
 612 #define CSEM_REG_CSEM_INT_MASK_0                                 0x200110
 613 #define CSEM_REG_CSEM_INT_MASK_1                                 0x200120
 614 /* [R 32] Interrupt register #0 read */
 615 #define CSEM_REG_CSEM_INT_STS_0                                  0x200104
 616 #define CSEM_REG_CSEM_INT_STS_1                                  0x200114
 617 /* [RW 32] Parity mask register #0 read/write */
 618 #define CSEM_REG_CSEM_PRTY_MASK_0                                0x200130
 619 #define CSEM_REG_CSEM_PRTY_MASK_1                                0x200140
 620 /* [R 32] Parity register #0 read */
 621 #define CSEM_REG_CSEM_PRTY_STS_0                                 0x200124
 622 #define CSEM_REG_CSEM_PRTY_STS_1                                 0x200134
 623 /* [RC 32] Parity register #0 read clear */
 624 #define CSEM_REG_CSEM_PRTY_STS_CLR_0                             0x200128
 625 #define CSEM_REG_CSEM_PRTY_STS_CLR_1                             0x200138
 626 #define CSEM_REG_ENABLE_IN                                       0x2000a4
 627 #define CSEM_REG_ENABLE_OUT                                      0x2000a8
 628 /* [RW 32] This address space contains all registers and memories that are
 629    placed in SEM_FAST block. The SEM_FAST registers are described in
 630    appendix B. In order to access the sem_fast registers the base address
 631    ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
 632 #define CSEM_REG_FAST_MEMORY                                     0x220000
 633 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
 634    by the microcode */
 635 #define CSEM_REG_FIC0_DISABLE                                    0x200224
 636 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
 637    by the microcode */
 638 #define CSEM_REG_FIC1_DISABLE                                    0x200234
 639 /* [RW 15] Interrupt table Read and write access to it is not possible in
 640    the middle of the work */
 641 #define CSEM_REG_INT_TABLE                                       0x200400
 642 /* [ST 24] Statistics register. The number of messages that entered through
 643    FIC0 */
 644 #define CSEM_REG_MSG_NUM_FIC0                                    0x200000
 645 /* [ST 24] Statistics register. The number of messages that entered through
 646    FIC1 */
 647 #define CSEM_REG_MSG_NUM_FIC1                                    0x200004
 648 /* [ST 24] Statistics register. The number of messages that were sent to
 649    FOC0 */
 650 #define CSEM_REG_MSG_NUM_FOC0                                    0x200008
 651 /* [ST 24] Statistics register. The number of messages that were sent to
 652    FOC1 */
 653 #define CSEM_REG_MSG_NUM_FOC1                                    0x20000c
 654 /* [ST 24] Statistics register. The number of messages that were sent to
 655    FOC2 */
 656 #define CSEM_REG_MSG_NUM_FOC2                                    0x200010
 657 /* [ST 24] Statistics register. The number of messages that were sent to
 658    FOC3 */
 659 #define CSEM_REG_MSG_NUM_FOC3                                    0x200014
 660 /* [RW 1] Disables input messages from the passive buffer May be updated
 661    during run_time by the microcode */
 662 #define CSEM_REG_PAS_DISABLE                                     0x20024c
 663 /* [WB 128] Debug only. Passive buffer memory */
 664 #define CSEM_REG_PASSIVE_BUFFER                                  0x202000
 665 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
 666 #define CSEM_REG_PRAM                                            0x240000
 667 /* [R 16] Valid sleeping threads indication have bit per thread */
 668 #define CSEM_REG_SLEEP_THREADS_VALID                             0x20026c
 669 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
 670 #define CSEM_REG_SLOW_EXT_STORE_EMPTY                            0x2002a0
 671 /* [RW 16] List of free threads . There is a bit per thread. */
 672 #define CSEM_REG_THREADS_LIST                                    0x2002e4
 673 /* [RW 3] The arbitration scheme of time_slot 0 */
 674 #define CSEM_REG_TS_0_AS                                         0x200038
 675 /* [RW 3] The arbitration scheme of time_slot 10 */
 676 #define CSEM_REG_TS_10_AS                                        0x200060
 677 /* [RW 3] The arbitration scheme of time_slot 11 */
 678 #define CSEM_REG_TS_11_AS                                        0x200064
 679 /* [RW 3] The arbitration scheme of time_slot 12 */
 680 #define CSEM_REG_TS_12_AS                                        0x200068
 681 /* [RW 3] The arbitration scheme of time_slot 13 */
 682 #define CSEM_REG_TS_13_AS                                        0x20006c
 683 /* [RW 3] The arbitration scheme of time_slot 14 */
 684 #define CSEM_REG_TS_14_AS                                        0x200070
 685 /* [RW 3] The arbitration scheme of time_slot 15 */
 686 #define CSEM_REG_TS_15_AS                                        0x200074
 687 /* [RW 3] The arbitration scheme of time_slot 16 */
 688 #define CSEM_REG_TS_16_AS                                        0x200078
 689 /* [RW 3] The arbitration scheme of time_slot 17 */
 690 #define CSEM_REG_TS_17_AS                                        0x20007c
 691 /* [RW 3] The arbitration scheme of time_slot 18 */
 692 #define CSEM_REG_TS_18_AS                                        0x200080
 693 /* [RW 3] The arbitration scheme of time_slot 1 */
 694 #define CSEM_REG_TS_1_AS                                         0x20003c
 695 /* [RW 3] The arbitration scheme of time_slot 2 */
 696 #define CSEM_REG_TS_2_AS                                         0x200040
 697 /* [RW 3] The arbitration scheme of time_slot 3 */
 698 #define CSEM_REG_TS_3_AS                                         0x200044
 699 /* [RW 3] The arbitration scheme of time_slot 4 */
 700 #define CSEM_REG_TS_4_AS                                         0x200048
 701 /* [RW 3] The arbitration scheme of time_slot 5 */
 702 #define CSEM_REG_TS_5_AS                                         0x20004c
 703 /* [RW 3] The arbitration scheme of time_slot 6 */
 704 #define CSEM_REG_TS_6_AS                                         0x200050
 705 /* [RW 3] The arbitration scheme of time_slot 7 */
 706 #define CSEM_REG_TS_7_AS                                         0x200054
 707 /* [RW 3] The arbitration scheme of time_slot 8 */
 708 #define CSEM_REG_TS_8_AS                                         0x200058
 709 /* [RW 3] The arbitration scheme of time_slot 9 */
 710 #define CSEM_REG_TS_9_AS                                         0x20005c
 711 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
 712  * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
 713 #define CSEM_REG_VFPF_ERR_NUM                                    0x200380
 714 /* [RW 1] Parity mask register #0 read/write */
 715 #define DBG_REG_DBG_PRTY_MASK                                    0xc0a8
 716 /* [R 1] Parity register #0 read */
 717 #define DBG_REG_DBG_PRTY_STS                                     0xc09c
 718 /* [RC 1] Parity register #0 read clear */
 719 #define DBG_REG_DBG_PRTY_STS_CLR                                 0xc0a0
 720 /* [RW 1] When set the DMAE will process the commands as in E1.5. 1.The
 721  * function that is used is always SRC-PCI; 2.VF_Valid = 0; 3.VFID=0;
 722  * 4.Completion function=0; 5.Error handling=0 */
 723 #define DMAE_REG_BACKWARD_COMP_EN                                0x10207c
 724 /* [RW 32] Commands memory. The address to command X; row Y is to calculated
 725    as 14*X+Y. */
 726 #define DMAE_REG_CMD_MEM                                         0x102400
 727 #define DMAE_REG_CMD_MEM_SIZE                                    224
 728 /* [RW 1] If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c
 729    initial value is all ones. */
 730 #define DMAE_REG_CRC16C_INIT                                     0x10201c
 731 /* [RW 1] If 0 - the CRC-16 T10 initial value is all zeroes; if 1 - the
 732    CRC-16 T10 initial value is all ones. */
 733 #define DMAE_REG_CRC16T10_INIT                                   0x102020
 734 /* [RW 2] Interrupt mask register #0 read/write */
 735 #define DMAE_REG_DMAE_INT_MASK                                   0x102054
 736 /* [RW 4] Parity mask register #0 read/write */
 737 #define DMAE_REG_DMAE_PRTY_MASK                                  0x102064
 738 /* [R 4] Parity register #0 read */
 739 #define DMAE_REG_DMAE_PRTY_STS                                   0x102058
 740 /* [RC 4] Parity register #0 read clear */
 741 #define DMAE_REG_DMAE_PRTY_STS_CLR                               0x10205c
 742 /* [RW 1] Command 0 go. */
 743 #define DMAE_REG_GO_C0                                           0x102080
 744 /* [RW 1] Command 1 go. */
 745 #define DMAE_REG_GO_C1                                           0x102084
 746 /* [RW 1] Command 10 go. */
 747 #define DMAE_REG_GO_C10                                          0x102088
 748 /* [RW 1] Command 11 go. */
 749 #define DMAE_REG_GO_C11                                          0x10208c
 750 /* [RW 1] Command 12 go. */
 751 #define DMAE_REG_GO_C12                                          0x102090
 752 /* [RW 1] Command 13 go. */
 753 #define DMAE_REG_GO_C13                                          0x102094
 754 /* [RW 1] Command 14 go. */
 755 #define DMAE_REG_GO_C14                                          0x102098
 756 /* [RW 1] Command 15 go. */
 757 #define DMAE_REG_GO_C15                                          0x10209c
 758 /* [RW 1] Command 2 go. */
 759 #define DMAE_REG_GO_C2                                           0x1020a0
 760 /* [RW 1] Command 3 go. */
 761 #define DMAE_REG_GO_C3                                           0x1020a4
 762 /* [RW 1] Command 4 go. */
 763 #define DMAE_REG_GO_C4                                           0x1020a8
 764 /* [RW 1] Command 5 go. */
 765 #define DMAE_REG_GO_C5                                           0x1020ac
 766 /* [RW 1] Command 6 go. */
 767 #define DMAE_REG_GO_C6                                           0x1020b0
 768 /* [RW 1] Command 7 go. */
 769 #define DMAE_REG_GO_C7                                           0x1020b4
 770 /* [RW 1] Command 8 go. */
 771 #define DMAE_REG_GO_C8                                           0x1020b8
 772 /* [RW 1] Command 9 go. */
 773 #define DMAE_REG_GO_C9                                           0x1020bc
 774 /* [RW 1] DMAE GRC Interface (Target; aster) enable. If 0 - the acknowledge
 775    input is disregarded; valid is deasserted; all other signals are treated
 776    as usual; if 1 - normal activity. */
 777 #define DMAE_REG_GRC_IFEN                                        0x102008
 778 /* [RW 1] DMAE PCI Interface (Request; ead; rite) enable. If 0 - the
 779    acknowledge input is disregarded; valid is deasserted; full is asserted;
 780    all other signals are treated as usual; if 1 - normal activity. */
 781 #define DMAE_REG_PCI_IFEN                                        0x102004
 782 /* [RW 4] DMAE- PCI Request Interface initial credit. Write writes the
 783    initial value to the credit counter; related to the address. Read returns
 784    the current value of the counter. */
 785 #define DMAE_REG_PXP_REQ_INIT_CRD                                0x1020c0
 786 /* [RW 8] Aggregation command. */
 787 #define DORQ_REG_AGG_CMD0                                        0x170060
 788 /* [RW 8] Aggregation command. */
 789 #define DORQ_REG_AGG_CMD1                                        0x170064
 790 /* [RW 8] Aggregation command. */
 791 #define DORQ_REG_AGG_CMD2                                        0x170068
 792 /* [RW 8] Aggregation command. */
 793 #define DORQ_REG_AGG_CMD3                                        0x17006c
 794 /* [RW 28] UCM Header. */
 795 #define DORQ_REG_CMHEAD_RX                                       0x170050
 796 /* [RW 32] Doorbell address for RBC doorbells (function 0). */
 797 #define DORQ_REG_DB_ADDR0                                        0x17008c
 798 /* [RW 5] Interrupt mask register #0 read/write */
 799 #define DORQ_REG_DORQ_INT_MASK                                   0x170180
 800 /* [R 5] Interrupt register #0 read */
 801 #define DORQ_REG_DORQ_INT_STS                                    0x170174
 802 /* [RC 5] Interrupt register #0 read clear */
 803 #define DORQ_REG_DORQ_INT_STS_CLR                                0x170178
 804 /* [RW 2] Parity mask register #0 read/write */
 805 #define DORQ_REG_DORQ_PRTY_MASK                                  0x170190
 806 /* [R 2] Parity register #0 read */
 807 #define DORQ_REG_DORQ_PRTY_STS                                   0x170184
 808 /* [RC 2] Parity register #0 read clear */
 809 #define DORQ_REG_DORQ_PRTY_STS_CLR                               0x170188
 810 /* [RW 8] The address to write the DPM CID to STORM. */
 811 #define DORQ_REG_DPM_CID_ADDR                                    0x170044
 812 /* [RW 5] The DPM mode CID extraction offset. */
 813 #define DORQ_REG_DPM_CID_OFST                                    0x170030
 814 /* [RW 12] The threshold of the DQ FIFO to send the almost full interrupt. */
 815 #define DORQ_REG_DQ_FIFO_AFULL_TH                                0x17007c
 816 /* [RW 12] The threshold of the DQ FIFO to send the full interrupt. */
 817 #define DORQ_REG_DQ_FIFO_FULL_TH                                 0x170078
 818 /* [R 13] Current value of the DQ FIFO fill level according to following
 819    pointer. The range is 0 - 256 FIFO rows; where each row stands for the
 820    doorbell. */
 821 #define DORQ_REG_DQ_FILL_LVLF                                    0x1700a4
 822 /* [R 1] DQ FIFO full status. Is set; when FIFO filling level is more or
 823    equal to full threshold; reset on full clear. */
 824 #define DORQ_REG_DQ_FULL_ST                                      0x1700c0
 825 /* [RW 28] The value sent to CM header in the case of CFC load error. */
 826 #define DORQ_REG_ERR_CMHEAD                                      0x170058
 827 #define DORQ_REG_IF_EN                                           0x170004
 828 #define DORQ_REG_MODE_ACT                                        0x170008
 829 /* [RW 5] The normal mode CID extraction offset. */
 830 #define DORQ_REG_NORM_CID_OFST                                   0x17002c
 831 /* [RW 28] TCM Header when only TCP context is loaded. */
 832 #define DORQ_REG_NORM_CMHEAD_TX                                  0x17004c
 833 /* [RW 3] The number of simultaneous outstanding requests to Context Fetch
 834    Interface. */
 835 #define DORQ_REG_OUTST_REQ                                       0x17003c
 836 #define DORQ_REG_PF_USAGE_CNT                                    0x1701d0
 837 #define DORQ_REG_REGN                                            0x170038
 838 /* [R 4] Current value of response A counter credit. Initial credit is
 839    configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
 840    register. */
 841 #define DORQ_REG_RSPA_CRD_CNT                                    0x1700ac
 842 /* [R 4] Current value of response B counter credit. Initial credit is
 843    configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
 844    register. */
 845 #define DORQ_REG_RSPB_CRD_CNT                                    0x1700b0
 846 /* [RW 4] The initial credit at the Doorbell Response Interface. The write
 847    writes the same initial credit to the rspa_crd_cnt and rspb_crd_cnt. The
 848    read reads this written value. */
 849 #define DORQ_REG_RSP_INIT_CRD                                    0x170048
 850 /* [RW 4] Initial activity counter value on the load request; when the
 851    shortcut is done. */
 852 #define DORQ_REG_SHRT_ACT_CNT                                    0x170070
 853 /* [RW 28] TCM Header when both ULP and TCP context is loaded. */
 854 #define DORQ_REG_SHRT_CMHEAD                                     0x170054
 855 #define HC_CONFIG_0_REG_ATTN_BIT_EN_0                            (0x1<<4)
 856 #define HC_CONFIG_0_REG_BLOCK_DISABLE_0                          (0x1<<0)
 857 #define HC_CONFIG_0_REG_INT_LINE_EN_0                            (0x1<<3)
 858 #define HC_CONFIG_0_REG_MSI_ATTN_EN_0                            (0x1<<7)
 859 #define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0                        (0x1<<2)
 860 #define HC_CONFIG_0_REG_SINGLE_ISR_EN_0                          (0x1<<1)
 861 #define HC_CONFIG_1_REG_BLOCK_DISABLE_1                          (0x1<<0)
 862 #define HC_REG_AGG_INT_0                                         0x108050
 863 #define HC_REG_AGG_INT_1                                         0x108054
 864 #define HC_REG_ATTN_BIT                                          0x108120
 865 #define HC_REG_ATTN_IDX                                          0x108100
 866 #define HC_REG_ATTN_MSG0_ADDR_L                                  0x108018
 867 #define HC_REG_ATTN_MSG1_ADDR_L                                  0x108020
 868 #define HC_REG_ATTN_NUM_P0                                       0x108038
 869 #define HC_REG_ATTN_NUM_P1                                       0x10803c
 870 #define HC_REG_COMMAND_REG                                       0x108180
 871 #define HC_REG_CONFIG_0                                          0x108000
 872 #define HC_REG_CONFIG_1                                          0x108004
 873 #define HC_REG_FUNC_NUM_P0                                       0x1080ac
 874 #define HC_REG_FUNC_NUM_P1                                       0x1080b0
 875 /* [RW 3] Parity mask register #0 read/write */
 876 #define HC_REG_HC_PRTY_MASK                                      0x1080a0
 877 /* [R 3] Parity register #0 read */
 878 #define HC_REG_HC_PRTY_STS                                       0x108094
 879 /* [RC 3] Parity register #0 read clear */
 880 #define HC_REG_HC_PRTY_STS_CLR                                   0x108098
 881 #define HC_REG_INT_MASK                                          0x108108
 882 #define HC_REG_LEADING_EDGE_0                                    0x108040
 883 #define HC_REG_LEADING_EDGE_1                                    0x108048
 884 #define HC_REG_MAIN_MEMORY                                       0x108800
 885 #define HC_REG_MAIN_MEMORY_SIZE                                  152
 886 #define HC_REG_P0_PROD_CONS                                      0x108200
 887 #define HC_REG_P1_PROD_CONS                                      0x108400
 888 #define HC_REG_PBA_COMMAND                                       0x108140
 889 #define HC_REG_PCI_CONFIG_0                                      0x108010
 890 #define HC_REG_PCI_CONFIG_1                                      0x108014
 891 #define HC_REG_STATISTIC_COUNTERS                                0x109000
 892 #define HC_REG_TRAILING_EDGE_0                                   0x108044
 893 #define HC_REG_TRAILING_EDGE_1                                   0x10804c
 894 #define HC_REG_UC_RAM_ADDR_0                                     0x108028
 895 #define HC_REG_UC_RAM_ADDR_1                                     0x108030
 896 #define HC_REG_USTORM_ADDR_FOR_COALESCE                          0x108068
 897 #define HC_REG_VQID_0                                            0x108008
 898 #define HC_REG_VQID_1                                            0x10800c
 899 #define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN             (0x1<<1)
 900 #define IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE                 (0x1<<0)
 901 #define IGU_REG_ATTENTION_ACK_BITS                               0x130108
 902 /* [R 4] Debug: attn_fsm */
 903 #define IGU_REG_ATTN_FSM                                         0x130054
 904 #define IGU_REG_ATTN_MSG_ADDR_H                          0x13011c
 905 #define IGU_REG_ATTN_MSG_ADDR_L                          0x130120
 906 /* [R 4] Debug: [3] - attention write done message is pending (0-no pending;
 907  * 1-pending). [2:0] = PFID. Pending means attention message was sent; but
 908  * write done didn't receive. */
 909 #define IGU_REG_ATTN_WRITE_DONE_PENDING                  0x130030
 910 #define IGU_REG_BLOCK_CONFIGURATION                              0x130000
 911 #define IGU_REG_COMMAND_REG_32LSB_DATA                           0x130124
 912 #define IGU_REG_COMMAND_REG_CTRL                                 0x13012c
 913 /* [WB_R 32] Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit
 914  * is clear. The bits in this registers are set and clear via the producer
 915  * command. Data valid only in addresses 0-4. all the rest are zero. */
 916 #define IGU_REG_CSTORM_TYPE_0_SB_CLEANUP                         0x130200
 917 /* [R 5] Debug: ctrl_fsm */
 918 #define IGU_REG_CTRL_FSM                                         0x130064
 919 /* [R 1] data available for error memory. If this bit is clear do not red
 920  * from error_handling_memory. */
 921 #define IGU_REG_ERROR_HANDLING_DATA_VALID                        0x130130
 922 /* [RW 11] Parity mask register #0 read/write */
 923 #define IGU_REG_IGU_PRTY_MASK                                    0x1300a8
 924 /* [R 11] Parity register #0 read */
 925 #define IGU_REG_IGU_PRTY_STS                                     0x13009c
 926 /* [RC 11] Parity register #0 read clear */
 927 #define IGU_REG_IGU_PRTY_STS_CLR                                 0x1300a0
 928 /* [R 4] Debug: int_handle_fsm */
 929 #define IGU_REG_INT_HANDLE_FSM                                   0x130050
 930 #define IGU_REG_LEADING_EDGE_LATCH                               0x130134
 931 /* [RW 14] mapping CAM; relevant for E2 operating mode only. [0] - valid.
 932  * [6:1] - vector number; [13:7] - FID (if VF - [13] = 0; [12:7] = VF
 933  * number; if PF - [13] = 1; [12:10] = 0; [9:7] = PF number); */
 934 #define IGU_REG_MAPPING_MEMORY                                   0x131000
 935 #define IGU_REG_MAPPING_MEMORY_SIZE                              136
 936 #define IGU_REG_PBA_STATUS_LSB                                   0x130138
 937 #define IGU_REG_PBA_STATUS_MSB                                   0x13013c
 938 #define IGU_REG_PCI_PF_MSI_EN                                    0x130140
 939 #define IGU_REG_PCI_PF_MSIX_EN                                   0x130144
 940 #define IGU_REG_PCI_PF_MSIX_FUNC_MASK                            0x130148
 941 /* [WB_R 32] Each bit represent the pending bits status for that SB. 0 = no
 942  * pending; 1 = pending. Pendings means interrupt was asserted; and write
 943  * done was not received. Data valid only in addresses 0-4. all the rest are
 944  * zero. */
 945 #define IGU_REG_PENDING_BITS_STATUS                              0x130300
 946 #define IGU_REG_PF_CONFIGURATION                                 0x130154
 947 /* [RW 20] producers only. E2 mode: address 0-135 match to the mapping
 948  * memory; 136 - PF0 default prod; 137 PF1 default prod; 138 - PF2 default
 949  * prod; 139 PF3 default prod; 140 - PF0 - ATTN prod; 141 - PF1 - ATTN prod;
 950  * 142 - PF2 - ATTN prod; 143 - PF3 - ATTN prod; 144-147 reserved. E1.5 mode
 951  * - In backward compatible mode; for non default SB; each even line in the
 952  * memory holds the U producer and each odd line hold the C producer. The
 953  * first 128 producer are for NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The
 954  * last 20 producers are for the DSB for each PF. each PF has five segments
 955  * (the order inside each segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
 956  * 132-135 C prods; 136-139 X prods; 140-143 T prods; 144-147 ATTN prods; */
 957 #define IGU_REG_PROD_CONS_MEMORY                                 0x132000
 958 /* [R 3] Debug: pxp_arb_fsm */
 959 #define IGU_REG_PXP_ARB_FSM                                      0x130068
 960 /* [RW 6] Write one for each bit will reset the appropriate memory. When the
 961  * memory reset finished the appropriate bit will be clear. Bit 0 - mapping
 962  * memory; Bit 1 - SB memory; Bit 2 - SB interrupt and mask register; Bit 3
 963  * - MSIX memory; Bit 4 - PBA memory; Bit 5 - statistics; */
 964 #define IGU_REG_RESET_MEMORIES                                   0x130158
 965 /* [R 4] Debug: sb_ctrl_fsm */
 966 #define IGU_REG_SB_CTRL_FSM                                      0x13004c
 967 #define IGU_REG_SB_INT_BEFORE_MASK_LSB                           0x13015c
 968 #define IGU_REG_SB_INT_BEFORE_MASK_MSB                           0x130160
 969 #define IGU_REG_SB_MASK_LSB                                      0x130164
 970 #define IGU_REG_SB_MASK_MSB                                      0x130168
 971 /* [RW 16] Number of command that were dropped without causing an interrupt
 972  * due to: read access for WO BAR address; or write access for RO BAR
 973  * address or any access for reserved address or PCI function error is set
 974  * and address is not MSIX; PBA or cleanup */
 975 #define IGU_REG_SILENT_DROP                                      0x13016c
 976 /* [RW 10] Number of MSI/MSIX/ATTN messages sent for the function: 0-63 -
 977  * number of MSIX messages per VF; 64-67 - number of MSI/MSIX messages per
 978  * PF; 68-71 number of ATTN messages per PF */
 979 #define IGU_REG_STATISTIC_NUM_MESSAGE_SENT                       0x130800
 980 /* [RW 32] Number of cycles the timer mask masking the IGU interrupt when a
 981  * timer mask command arrives. Value must be bigger than 100. */
 982 #define IGU_REG_TIMER_MASKING_VALUE                              0x13003c
 983 #define IGU_REG_TRAILING_EDGE_LATCH                              0x130104
 984 #define IGU_REG_VF_CONFIGURATION                                 0x130170
 985 /* [WB_R 32] Each bit represent write done pending bits status for that SB
 986  * (MSI/MSIX message was sent and write done was not received yet). 0 =
 987  * clear; 1 = set. Data valid only in addresses 0-4. all the rest are zero. */
 988 #define IGU_REG_WRITE_DONE_PENDING                               0x130480
 989 #define MCP_A_REG_MCPR_SCRATCH                                   0x3a0000
 990 #define MCP_REG_MCPR_CPU_PROGRAM_COUNTER                         0x8501c
 991 #define MCP_REG_MCPR_GP_INPUTS                                   0x800c0
 992 #define MCP_REG_MCPR_GP_OENABLE                                  0x800c8
 993 #define MCP_REG_MCPR_GP_OUTPUTS                                  0x800c4
 994 #define MCP_REG_MCPR_IMC_COMMAND                                 0x85900
 995 #define MCP_REG_MCPR_IMC_DATAREG0                                0x85920
 996 #define MCP_REG_MCPR_IMC_SLAVE_CONTROL                           0x85904
 997 #define MCP_REG_MCPR_CPU_PROGRAM_COUNTER                         0x8501c
 998 #define MCP_REG_MCPR_NVM_ACCESS_ENABLE                           0x86424
 999 #define MCP_REG_MCPR_NVM_ADDR                                    0x8640c
1000 #define MCP_REG_MCPR_NVM_CFG4                                    0x8642c
1001 #define MCP_REG_MCPR_NVM_COMMAND                                 0x86400
1002 #define MCP_REG_MCPR_NVM_READ                                    0x86410
1003 #define MCP_REG_MCPR_NVM_SW_ARB                                  0x86420
1004 #define MCP_REG_MCPR_NVM_WRITE                                   0x86408
1005 #define MCP_REG_MCPR_SCRATCH                                     0xa0000
1006 #define MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK             (0x1<<1)
1007 #define MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK             (0x1<<0)
1008 /* [R 32] read first 32 bit after inversion of function 0. mapped as
1009    follows: [0] NIG attention for function0; [1] NIG attention for
1010    function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp;
1011    [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9]
1012    GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE
1013    glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0;
1014    [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16]
1015    MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB
1016    Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw
1017    interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity
1018    error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw
1019    interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBF
1020    Parity error; [31] PBF Hw interrupt; */
1021 #define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0                       0xa42c
1022 #define MISC_REG_AEU_AFTER_INVERT_1_FUNC_1                       0xa430
1023 /* [R 32] read first 32 bit after inversion of mcp. mapped as follows: [0]
1024    NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
1025    mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
1026    [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
1027    PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
1028    function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
1029    Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
1030    mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
1031    BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
1032    Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
1033    interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
1034    Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
1035    interrupt; */
1036 #define MISC_REG_AEU_AFTER_INVERT_1_MCP                          0xa434
1037 /* [R 32] read second 32 bit after inversion of function 0. mapped as
1038    follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1039    Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1040    interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1041    error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1042    interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1043    NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1044    [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1045    interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1046    Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1047    Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1048    Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1049    interrupt; */
1050 #define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0                       0xa438
1051 #define MISC_REG_AEU_AFTER_INVERT_2_FUNC_1                       0xa43c
1052 /* [R 32] read second 32 bit after inversion of mcp. mapped as follows: [0]
1053    PBClient Parity error; [1] PBClient Hw interrupt; [2] QM Parity error;
1054    [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt;
1055    [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9]
1056    XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
1057    DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
1058    error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
1059    PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
1060    [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
1061    [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
1062    [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
1063    [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
1064 #define MISC_REG_AEU_AFTER_INVERT_2_MCP                          0xa440
1065 /* [R 32] read third 32 bit after inversion of function 0. mapped as
1066    follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity
1067    error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5]
1068    PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1069    interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1070    error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1071    Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1072    pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1073    MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1074    SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1075    timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1076    func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1077    attn1; */
1078 #define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0                       0xa444
1079 #define MISC_REG_AEU_AFTER_INVERT_3_FUNC_1                       0xa448
1080 /* [R 32] read third 32 bit after inversion of mcp. mapped as follows: [0]
1081    CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP
1082    Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient
1083    Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity
1084    error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw
1085    interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14]
1086    MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17]
1087    Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW
1088    timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3
1089    func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1
1090    func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW
1091    timers attn_4 func1; [30] General attn0; [31] General attn1; */
1092 #define MISC_REG_AEU_AFTER_INVERT_3_MCP                          0xa44c
1093 /* [R 32] read fourth 32 bit after inversion of function 0. mapped as
1094    follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1095    General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1096    [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1097    attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1098    [14] General attn16; [15] General attn17; [16] General attn18; [17]
1099    General attn19; [18] General attn20; [19] General attn21; [20] Main power
1100    interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1101    Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1102    Latched timeout attention; [27] GRC Latched reserved access attention;
1103    [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1104    Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1105 #define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0                       0xa450
1106 #define MISC_REG_AEU_AFTER_INVERT_4_FUNC_1                       0xa454
1107 /* [R 32] read fourth 32 bit after inversion of mcp. mapped as follows: [0]
1108    General attn2; [1] General attn3; [2] General attn4; [3] General attn5;
1109    [4] General attn6; [5] General attn7; [6] General attn8; [7] General
1110    attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11]
1111    General attn13; [12] General attn14; [13] General attn15; [14] General
1112    attn16; [15] General attn17; [16] General attn18; [17] General attn19;
1113    [18] General attn20; [19] General attn21; [20] Main power interrupt; [21]
1114    RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24]
1115    RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout
1116    attention; [27] GRC Latched reserved access attention; [28] MCP Latched
1117    rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched
1118    ump_tx_parity; [31] MCP Latched scpad_parity; */
1119 #define MISC_REG_AEU_AFTER_INVERT_4_MCP                          0xa458
1120 /* [R 32] Read fifth 32 bit after inversion of function 0. Mapped as
1121  * follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC
1122  * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]
1123  * CNIG attention (reserved); [7] CNIG parity (reserved); [31-8] Reserved; */
1124 #define MISC_REG_AEU_AFTER_INVERT_5_FUNC_0                       0xa700
1125 /* [W 14] write to this register results with the clear of the latched
1126    signals; one in d0 clears RBCR latch; one in d1 clears RBCT latch; one in
1127    d2 clears RBCN latch; one in d3 clears RBCU latch; one in d4 clears RBCP
1128    latch; one in d5 clears GRC Latched timeout attention; one in d6 clears
1129    GRC Latched reserved access attention; one in d7 clears Latched
1130    rom_parity; one in d8 clears Latched ump_rx_parity; one in d9 clears
1131    Latched ump_tx_parity; one in d10 clears Latched scpad_parity (both
1132    ports); one in d11 clears pxpv_misc_mps_attn; one in d12 clears
1133    pxp_misc_exp_rom_attn0; one in d13 clears pxp_misc_exp_rom_attn1; read
1134    from this register return zero */
1135 #define MISC_REG_AEU_CLR_LATCH_SIGNAL                            0xa45c
1136 /* [RW 32] first 32b for enabling the output for function 0 output0. mapped
1137    as follows: [0] NIG attention for function0; [1] NIG attention for
1138    function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
1139    0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1140    GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1141    function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1142    Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1143    SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
1144    indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1145    [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1146    SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1147    TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1148    TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1149 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0                        0xa06c
1150 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1                        0xa07c
1151 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2                        0xa08c
1152 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3                        0xa09c
1153 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_5                        0xa0bc
1154 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_6                        0xa0cc
1155 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_7                        0xa0dc
1156 /* [RW 32] first 32b for enabling the output for function 1 output0. mapped
1157    as follows: [0] NIG attention for function0; [1] NIG attention for
1158    function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function
1159    1; [5] GPIO4 function 1; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1160    GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1161    function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1162    Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1163    SPIO4; [15] SPIO5; [16] MSI/X indication for function 1; [17] MSI/X
1164    indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1165    [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1166    SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1167    TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1168    TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1169 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0                        0xa10c
1170 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1                        0xa11c
1171 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2                        0xa12c
1172 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3                        0xa13c
1173 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_5                        0xa15c
1174 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_6                        0xa16c
1175 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_7                        0xa17c
1176 /* [RW 32] first 32b for enabling the output for close the gate nig. mapped
1177    as follows: [0] NIG attention for function0; [1] NIG attention for
1178    function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
1179    0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1180    GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1181    function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1182    Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1183    SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
1184    indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1185    [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1186    SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1187    TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1188    TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1189 #define MISC_REG_AEU_ENABLE1_NIG_0                               0xa0ec
1190 #define MISC_REG_AEU_ENABLE1_NIG_1                               0xa18c
1191 /* [RW 32] first 32b for enabling the output for close the gate pxp. mapped
1192    as follows: [0] NIG attention for function0; [1] NIG attention for
1193    function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
1194    0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1195    GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1196    function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1197    Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1198    SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
1199    indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1200    [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1201    SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1202    TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1203    TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1204 #define MISC_REG_AEU_ENABLE1_PXP_0                               0xa0fc
1205 #define MISC_REG_AEU_ENABLE1_PXP_1                               0xa19c
1206 /* [RW 32] second 32b for enabling the output for function 0 output0. mapped
1207    as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1208    Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1209    interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1210    error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1211    interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1212    NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1213    [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1214    interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1215    Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1216    Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1217    Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1218    interrupt; */
1219 #define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0                        0xa070
1220 #define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1                        0xa080
1221 /* [RW 32] second 32b for enabling the output for function 1 output0. mapped
1222    as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1223    Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1224    interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1225    error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1226    interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1227    NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1228    [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1229    interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1230    Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1231    Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1232    Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1233    interrupt; */
1234 #define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0                        0xa110
1235 #define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1                        0xa120
1236 /* [RW 32] second 32b for enabling the output for close the gate nig. mapped
1237    as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1238    Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1239    interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1240    error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1241    interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1242    NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1243    [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1244    interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1245    Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1246    Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1247    Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1248    interrupt; */
1249 #define MISC_REG_AEU_ENABLE2_NIG_0                               0xa0f0
1250 #define MISC_REG_AEU_ENABLE2_NIG_1                               0xa190
1251 /* [RW 32] second 32b for enabling the output for close the gate pxp. mapped
1252    as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1253    Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1254    interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1255    error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1256    interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1257    NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1258    [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1259    interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1260    Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1261    Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1262    Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1263    interrupt; */
1264 #define MISC_REG_AEU_ENABLE2_PXP_0                               0xa100
1265 #define MISC_REG_AEU_ENABLE2_PXP_1                               0xa1a0
1266 /* [RW 32] third 32b for enabling the output for function 0 output0. mapped
1267    as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1268    Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1269    [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1270    interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1271    error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1272    Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1273    pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1274    MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1275    SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1276    timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1277    func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1278    attn1; */
1279 #define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0                        0xa074
1280 #define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1                        0xa084
1281 /* [RW 32] third 32b for enabling the output for function 1 output0. mapped
1282    as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1283    Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1284    [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1285    interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1286    error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1287    Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1288    pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1289    MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1290    SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1291    timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1292    func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1293    attn1; */
1294 #define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0                        0xa114
1295 #define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1                        0xa124
1296 /* [RW 32] third 32b for enabling the output for close the gate nig. mapped
1297    as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1298    Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1299    [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1300    interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1301    error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1302    Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1303    pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1304    MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1305    SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1306    timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1307    func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1308    attn1; */
1309 #define MISC_REG_AEU_ENABLE3_NIG_0                               0xa0f4
1310 #define MISC_REG_AEU_ENABLE3_NIG_1                               0xa194
1311 /* [RW 32] third 32b for enabling the output for close the gate pxp. mapped
1312    as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1313    Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1314    [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1315    interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1316    error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1317    Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1318    pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1319    MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1320    SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1321    timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1322    func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1323    attn1; */
1324 #define MISC_REG_AEU_ENABLE3_PXP_0                               0xa104
1325 #define MISC_REG_AEU_ENABLE3_PXP_1                               0xa1a4
1326 /* [RW 32] fourth 32b for enabling the output for function 0 output0.mapped
1327    as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1328    General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1329    [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1330    attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1331    [14] General attn16; [15] General attn17; [16] General attn18; [17]
1332    General attn19; [18] General attn20; [19] General attn21; [20] Main power
1333    interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1334    Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1335    Latched timeout attention; [27] GRC Latched reserved access attention;
1336    [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1337    Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1338 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0                        0xa078
1339 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2                        0xa098
1340 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_4                        0xa0b8
1341 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_5                        0xa0c8
1342 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_6                        0xa0d8
1343 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_7                        0xa0e8
1344 /* [RW 32] fourth 32b for enabling the output for function 1 output0.mapped
1345    as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1346    General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1347    [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1348    attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1349    [14] General attn16; [15] General attn17; [16] General attn18; [17]
1350    General attn19; [18] General attn20; [19] General attn21; [20] Main power
1351    interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1352    Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1353    Latched timeout attention; [27] GRC Latched reserved access attention;
1354    [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1355    Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1356 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0                        0xa118
1357 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2                        0xa138
1358 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_4                        0xa158
1359 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_5                        0xa168
1360 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_6                        0xa178
1361 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_7                        0xa188
1362 /* [RW 32] fourth 32b for enabling the output for close the gate nig.mapped
1363    as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1364    General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1365    [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1366    attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1367    [14] General attn16; [15] General attn17; [16] General attn18; [17]
1368    General attn19; [18] General attn20; [19] General attn21; [20] Main power
1369    interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1370    Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1371    Latched timeout attention; [27] GRC Latched reserved access attention;
1372    [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1373    Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1374 #define MISC_REG_AEU_ENABLE4_NIG_0                               0xa0f8
1375 #define MISC_REG_AEU_ENABLE4_NIG_1                               0xa198
1376 /* [RW 32] fourth 32b for enabling the output for close the gate pxp.mapped
1377    as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1378    General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1379    [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1380    attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1381    [14] General attn16; [15] General attn17; [16] General attn18; [17]
1382    General attn19; [18] General attn20; [19] General attn21; [20] Main power
1383    interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1384    Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1385    Latched timeout attention; [27] GRC Latched reserved access attention;
1386    [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1387    Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1388 #define MISC_REG_AEU_ENABLE4_PXP_0                               0xa108
1389 #define MISC_REG_AEU_ENABLE4_PXP_1                               0xa1a8
1390 /* [RW 32] fifth 32b for enabling the output for function 0 output0. Mapped
1391  * as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC
1392  * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]
1393  * mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1
1394  * parity; [31-10] Reserved; */
1395 #define MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0                        0xa688
1396 /* [RW 32] Fifth 32b for enabling the output for function 1 output0. Mapped
1397  * as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC
1398  * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]
1399  * mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1
1400  * parity; [31-10] Reserved; */
1401 #define MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0                        0xa6b0
1402 /* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu
1403    128 bit vector */
1404 #define MISC_REG_AEU_GENERAL_ATTN_0                              0xa000
1405 #define MISC_REG_AEU_GENERAL_ATTN_1                              0xa004
1406 #define MISC_REG_AEU_GENERAL_ATTN_10                             0xa028
1407 #define MISC_REG_AEU_GENERAL_ATTN_11                             0xa02c
1408 #define MISC_REG_AEU_GENERAL_ATTN_12                             0xa030
1409 #define MISC_REG_AEU_GENERAL_ATTN_2                              0xa008
1410 #define MISC_REG_AEU_GENERAL_ATTN_3                              0xa00c
1411 #define MISC_REG_AEU_GENERAL_ATTN_4                              0xa010
1412 #define MISC_REG_AEU_GENERAL_ATTN_5                              0xa014
1413 #define MISC_REG_AEU_GENERAL_ATTN_6                              0xa018
1414 #define MISC_REG_AEU_GENERAL_ATTN_7                              0xa01c
1415 #define MISC_REG_AEU_GENERAL_ATTN_8                              0xa020
1416 #define MISC_REG_AEU_GENERAL_ATTN_9                              0xa024
1417 #define MISC_REG_AEU_GENERAL_MASK                                0xa61c
1418 /* [RW 32] first 32b for inverting the input for function 0; for each bit:
1419    0= do not invert; 1= invert; mapped as follows: [0] NIG attention for
1420    function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp;
1421    [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1;
1422    [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1423    function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1424    Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1425    SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication
1426    for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS
1427    Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw
1428    interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM
1429    Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI
1430    Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1431 #define MISC_REG_AEU_INVERTER_1_FUNC_0                           0xa22c
1432 #define MISC_REG_AEU_INVERTER_1_FUNC_1                           0xa23c
1433 /* [RW 32] second 32b for inverting the input for function 0; for each bit:
1434    0= do not invert; 1= invert. mapped as follows: [0] PBClient Parity
1435    error; [1] PBClient Hw interrupt; [2] QM Parity error; [3] QM Hw
1436    interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM
1437    Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw
1438    interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
1439    DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
1440    error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
1441    PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
1442    [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
1443    [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
1444    [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
1445    [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
1446 #define MISC_REG_AEU_INVERTER_2_FUNC_0                           0xa230
1447 #define MISC_REG_AEU_INVERTER_2_FUNC_1                           0xa240
1448 /* [RW 10] [7:0] = mask 8 attention output signals toward IGU function0;
1449    [9:8] = raserved. Zero = mask; one = unmask */
1450 #define MISC_REG_AEU_MASK_ATTN_FUNC_0                            0xa060
1451 #define MISC_REG_AEU_MASK_ATTN_FUNC_1                            0xa064
1452 /* [RW 1] If set a system kill occurred */
1453 #define MISC_REG_AEU_SYS_KILL_OCCURRED                           0xa610
1454 /* [RW 32] Represent the status of the input vector to the AEU when a system
1455    kill occurred. The register is reset in por reset. Mapped as follows: [0]
1456    NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
1457    mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
1458    [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
1459    PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
1460    function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
1461    Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
1462    mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
1463    BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
1464    Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
1465    interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
1466    Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
1467    interrupt; */
1468 #define MISC_REG_AEU_SYS_KILL_STATUS_0                           0xa600
1469 #define MISC_REG_AEU_SYS_KILL_STATUS_1                           0xa604
1470 #define MISC_REG_AEU_SYS_KILL_STATUS_2                           0xa608
1471 #define MISC_REG_AEU_SYS_KILL_STATUS_3                           0xa60c
1472 /* [R 4] This field indicates the type of the device. '0' - 2 Ports; '1' - 1
1473    Port. */
1474 #define MISC_REG_BOND_ID                                         0xa400
1475 /* [R 8] These bits indicate the metal revision of the chip. This value
1476    starts at 0x00 for each all-layer tape-out and increments by one for each
1477    tape-out. */
1478 #define MISC_REG_CHIP_METAL                                      0xa404
1479 /* [R 16] These bits indicate the part number for the chip. */
1480 #define MISC_REG_CHIP_NUM                                        0xa408
1481 /* [R 4] These bits indicate the base revision of the chip. This value
1482    starts at 0x0 for the A0 tape-out and increments by one for each
1483    all-layer tape-out. */
1484 #define MISC_REG_CHIP_REV                                        0xa40c
1485 /* [RW 32] The following driver registers(1...16) represent 16 drivers and
1486    32 clients. Each client can be controlled by one driver only. One in each
1487    bit represent that this driver control the appropriate client (Ex: bit 5
1488    is set means this driver control client number 5). addr1 = set; addr0 =
1489    clear; read from both addresses will give the same result = status. write
1490    to address 1 will set a request to control all the clients that their
1491    appropriate bit (in the write command) is set. if the client is free (the
1492    appropriate bit in all the other drivers is clear) one will be written to
1493    that driver register; if the client isn't free the bit will remain zero.
1494    if the appropriate bit is set (the driver request to gain control on a
1495    client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1496    interrupt will be asserted). write to address 0 will set a request to
1497    free all the clients that their appropriate bit (in the write command) is
1498    set. if the appropriate bit is clear (the driver request to free a client
1499    it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1500    be asserted). */
1501 #define MISC_REG_DRIVER_CONTROL_1                                0xa510
1502 #define MISC_REG_DRIVER_CONTROL_7                                0xa3c8
1503 /* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0
1504    only. */
1505 #define MISC_REG_E1HMF_MODE                                      0xa5f8
1506 /* [R 1] Status of four port mode path swap input pin. */
1507 #define MISC_REG_FOUR_PORT_PATH_SWAP                             0xa75c
1508 /* [RW 2] 4 port path swap overwrite.[0] - Overwrite control; if it is 0 -
1509    the path_swap output is equal to 4 port mode path swap input pin; if it
1510    is 1 - the path_swap output is equal to bit[1] of this register; [1] -
1511    Overwrite value. If bit[0] of this register is 1 this is the value that
1512    receives the path_swap output. Reset on Hard reset. */
1513 #define MISC_REG_FOUR_PORT_PATH_SWAP_OVWR                        0xa738
1514 /* [R 1] Status of 4 port mode port swap input pin. */
1515 #define MISC_REG_FOUR_PORT_PORT_SWAP                             0xa754
1516 /* [RW 2] 4 port port swap overwrite.[0] - Overwrite control; if it is 0 -
1517    the port_swap output is equal to 4 port mode port swap input pin; if it
1518    is 1 - the port_swap output is equal to bit[1] of this register; [1] -
1519    Overwrite value. If bit[0] of this register is 1 this is the value that
1520    receives the port_swap output. Reset on Hard reset. */
1521 #define MISC_REG_FOUR_PORT_PORT_SWAP_OVWR                        0xa734
1522 /* [RW 32] Debug only: spare RW register reset by core reset */
1523 #define MISC_REG_GENERIC_CR_0                                    0xa460
1524 #define MISC_REG_GENERIC_CR_1                                    0xa464
1525 /* [RW 32] Debug only: spare RW register reset by por reset */
1526 #define MISC_REG_GENERIC_POR_1                                   0xa474
1527 /* [RW 32] Bit[0]: EPIO MODE SEL: Setting this bit to 1 will allow SW/FW to
1528    use all of the 32 Extended GPIO pins. Without setting this bit; an EPIO
1529    can not be configured as an output. Each output has its output enable in
1530    the MCP register space; but this bit needs to be set to make use of that.
1531    Bit[3:1] spare. Bit[4]: WCVTMON_PWRDN: Powerdown for Warpcore VTMON. When
1532    set to 1 - Powerdown. Bit[5]: WCVTMON_RESETB: Reset for Warpcore VTMON.
1533    When set to 0 - vTMON is in reset. Bit[6]: setting this bit will change
1534    the i/o to an output and will drive the TimeSync output. Bit[31:7]:
1535    spare. Global register. Reset by hard reset. */
1536 #define MISC_REG_GEN_PURP_HWG                                    0xa9a0
1537 /* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of
1538    these bits is written as a '1'; the corresponding SPIO bit will turn off
1539    it's drivers and become an input. This is the reset state of all GPIO
1540    pins. The read value of these bits will be a '1' if that last command
1541    (#SET; #CLR; or #FLOAT) for this bit was a #FLOAT. (reset value 0xff).
1542    [23-20] CLR port 1; 19-16] CLR port 0; When any of these bits is written
1543    as a '1'; the corresponding GPIO bit will drive low. The read value of
1544    these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for
1545    this bit was a #CLR. (reset value 0). [15-12] SET port 1; 11-8] port 0;
1546    SET When any of these bits is written as a '1'; the corresponding GPIO
1547    bit will drive high (if it has that capability). The read value of these
1548    bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this
1549    bit was a #SET. (reset value 0). [7-4] VALUE port 1; [3-0] VALUE port 0;
1550    RO; These bits indicate the read value of each of the eight GPIO pins.
1551    This is the result value of the pin; not the drive value. Writing these
1552    bits will have not effect. */
1553 #define MISC_REG_GPIO                                            0xa490
1554 /* [RW 8] These bits enable the GPIO_INTs to signals event to the
1555    IGU/MCP.according to the following map: [0] p0_gpio_0; [1] p0_gpio_1; [2]
1556    p0_gpio_2; [3] p0_gpio_3; [4] p1_gpio_0; [5] p1_gpio_1; [6] p1_gpio_2;
1557    [7] p1_gpio_3; */
1558 #define MISC_REG_GPIO_EVENT_EN                                   0xa2bc
1559 /* [RW 32] GPIO INT. [31-28] OLD_CLR port1; [27-24] OLD_CLR port0; Writing a
1560    '1' to these bit clears the corresponding bit in the #OLD_VALUE register.
1561    This will acknowledge an interrupt on the falling edge of corresponding
1562    GPIO input (reset value 0). [23-16] OLD_SET [23-16] port1; OLD_SET port0;
1563    Writing a '1' to these bit sets the corresponding bit in the #OLD_VALUE
1564    register. This will acknowledge an interrupt on the rising edge of
1565    corresponding SPIO input (reset value 0). [15-12] OLD_VALUE [11-8] port1;
1566    OLD_VALUE port0; RO; These bits indicate the old value of the GPIO input
1567    value. When the ~INT_STATE bit is set; this bit indicates the OLD value
1568    of the pin such that if ~INT_STATE is set and this bit is '0'; then the
1569    interrupt is due to a low to high edge. If ~INT_STATE is set and this bit
1570    is '1'; then the interrupt is due to a high to low edge (reset value 0).
1571    [7-4] INT_STATE port1; [3-0] INT_STATE RO port0; These bits indicate the
1572    current GPIO interrupt state for each GPIO pin. This bit is cleared when
1573    the appropriate #OLD_SET or #OLD_CLR command bit is written. This bit is
1574    set when the GPIO input does not match the current value in #OLD_VALUE
1575    (reset value 0). */
1576 #define MISC_REG_GPIO_INT                                        0xa494
1577 /* [R 28] this field hold the last information that caused reserved
1578    attention. bits [19:0] - address; [22:20] function; [23] reserved;
1579    [27:24] the master that caused the attention - according to the following
1580    encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
1581    dbu; 8 = dmae */
1582 #define MISC_REG_GRC_RSV_ATTN                                    0xa3c0
1583 /* [R 28] this field hold the last information that caused timeout
1584    attention. bits [19:0] - address; [22:20] function; [23] reserved;
1585    [27:24] the master that caused the attention - according to the following
1586    encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
1587    dbu; 8 = dmae */
1588 #define MISC_REG_GRC_TIMEOUT_ATTN                                0xa3c4
1589 /* [RW 1] Setting this bit enables a timer in the GRC block to timeout any
1590    access that does not finish within
1591    ~misc_registers_grc_timout_val.grc_timeout_val cycles. When this bit is
1592    cleared; this timeout is disabled. If this timeout occurs; the GRC shall
1593    assert it attention output. */
1594 #define MISC_REG_GRC_TIMEOUT_EN                                  0xa280
1595 /* [RW 28] 28 LSB of LCPLL first register; reset val = 521. inside order of
1596    the bits is: [2:0] OAC reset value 001) CML output buffer bias control;
1597    111 for +40%; 011 for +20%; 001 for 0%; 000 for -20%. [5:3] Icp_ctrl
1598    (reset value 001) Charge pump current control; 111 for 720u; 011 for
1599    600u; 001 for 480u and 000 for 360u. [7:6] Bias_ctrl (reset value 00)
1600    Global bias control; When bit 7 is high bias current will be 10 0gh; When
1601    bit 6 is high bias will be 100w; Valid values are 00; 10; 01. [10:8]
1602    Pll_observe (reset value 010) Bits to control observability. bit 10 is
1603    for test bias; bit 9 is for test CK; bit 8 is test Vc. [12:11] Vth_ctrl
1604    (reset value 00) Comparator threshold control. 00 for 0.6V; 01 for 0.54V
1605    and 10 for 0.66V. [13] pllSeqStart (reset value 0) Enables VCO tuning
1606    sequencer: 1= sequencer disabled; 0= sequencer enabled (inverted
1607    internally). [14] reserved (reset value 0) Reset for VCO sequencer is
1608    connected to RESET input directly. [15] capRetry_en (reset value 0)
1609    enable retry on cap search failure (inverted). [16] freqMonitor_e (reset
1610    value 0) bit to continuously monitor vco freq (inverted). [17]
1611    freqDetRestart_en (reset value 0) bit to enable restart when not freq
1612    locked (inverted). [18] freqDetRetry_en (reset value 0) bit to enable
1613    retry on freq det failure(inverted). [19] pllForceFdone_en (reset value
1614    0) bit to enable pllForceFdone & pllForceFpass into pllSeq. [20]
1615    pllForceFdone (reset value 0) bit to force freqDone. [21] pllForceFpass
1616    (reset value 0) bit to force freqPass. [22] pllForceDone_en (reset value
1617    0) bit to enable pllForceCapDone. [23] pllForceCapDone (reset value 0)
1618    bit to force capDone. [24] pllForceCapPass_en (reset value 0) bit to
1619    enable pllForceCapPass. [25] pllForceCapPass (reset value 0) bit to force
1620    capPass. [26] capRestart (reset value 0) bit to force cap sequencer to
1621    restart. [27] capSelectM_en (reset value 0) bit to enable cap select
1622    register bits. */
1623 #define MISC_REG_LCPLL_CTRL_1                                    0xa2a4
1624 #define MISC_REG_LCPLL_CTRL_REG_2                                0xa2a8
1625 /* [RW 4] Interrupt mask register #0 read/write */
1626 #define MISC_REG_MISC_INT_MASK                                   0xa388
1627 /* [RW 1] Parity mask register #0 read/write */
1628 #define MISC_REG_MISC_PRTY_MASK                                  0xa398
1629 /* [R 1] Parity register #0 read */
1630 #define MISC_REG_MISC_PRTY_STS                                   0xa38c
1631 /* [RC 1] Parity register #0 read clear */
1632 #define MISC_REG_MISC_PRTY_STS_CLR                               0xa390
1633 #define MISC_REG_NIG_WOL_P0                                      0xa270
1634 #define MISC_REG_NIG_WOL_P1                                      0xa274
1635 /* [R 1] If set indicate that the pcie_rst_b was asserted without perst
1636    assertion */
1637 #define MISC_REG_PCIE_HOT_RESET                                  0xa618
1638 /* [RW 32] 32 LSB of storm PLL first register; reset val = 0x 071d2911.
1639    inside order of the bits is: [0] P1 divider[0] (reset value 1); [1] P1
1640    divider[1] (reset value 0); [2] P1 divider[2] (reset value 0); [3] P1
1641    divider[3] (reset value 0); [4] P2 divider[0] (reset value 1); [5] P2
1642    divider[1] (reset value 0); [6] P2 divider[2] (reset value 0); [7] P2
1643    divider[3] (reset value 0); [8] ph_det_dis (reset value 1); [9]
1644    freq_det_dis (reset value 0); [10] Icpx[0] (reset value 0); [11] Icpx[1]
1645    (reset value 1); [12] Icpx[2] (reset value 0); [13] Icpx[3] (reset value
1646    1); [14] Icpx[4] (reset value 0); [15] Icpx[5] (reset value 0); [16]
1647    Rx[0] (reset value 1); [17] Rx[1] (reset value 0); [18] vc_en (reset
1648    value 1); [19] vco_rng[0] (reset value 1); [20] vco_rng[1] (reset value
1649    1); [21] Kvco_xf[0] (reset value 0); [22] Kvco_xf[1] (reset value 0);
1650    [23] Kvco_xf[2] (reset value 0); [24] Kvco_xs[0] (reset value 1); [25]
1651    Kvco_xs[1] (reset value 1); [26] Kvco_xs[2] (reset value 1); [27]
1652    testd_en (reset value 0); [28] testd_sel[0] (reset value 0); [29]
1653    testd_sel[1] (reset value 0); [30] testd_sel[2] (reset value 0); [31]
1654    testa_en (reset value 0); */
1655 #define MISC_REG_PLL_STORM_CTRL_1                                0xa294
1656 #define MISC_REG_PLL_STORM_CTRL_2                                0xa298
1657 #define MISC_REG_PLL_STORM_CTRL_3                                0xa29c
1658 #define MISC_REG_PLL_STORM_CTRL_4                                0xa2a0
1659 /* [R 1] Status of 4 port mode enable input pin. */
1660 #define MISC_REG_PORT4MODE_EN                                    0xa750
1661 /* [RW 2] 4 port mode enable overwrite.[0] - Overwrite control; if it is 0 -
1662  * the port4mode_en output is equal to 4 port mode input pin; if it is 1 -
1663  * the port4mode_en output is equal to bit[1] of this register; [1] -
1664  * Overwrite value. If bit[0] of this register is 1 this is the value that
1665  * receives the port4mode_en output . */
1666 #define MISC_REG_PORT4MODE_EN_OVWR                               0xa720
1667 /* [RW 32] reset reg#2; rite/read one = the specific block is out of reset;
1668    write/read zero = the specific block is in reset; addr 0-wr- the write
1669    value will be written to the register; addr 1-set - one will be written
1670    to all the bits that have the value of one in the data written (bits that
1671    have the value of zero will not be change) ; addr 2-clear - zero will be
1672    written to all the bits that have the value of one in the data written
1673    (bits that have the value of zero will not be change); addr 3-ignore;
1674    read ignore from all addr except addr 00; inside order of the bits is:
1675    [0] rst_bmac0; [1] rst_bmac1; [2] rst_emac0; [3] rst_emac1; [4] rst_grc;
1676    [5] rst_mcp_n_reset_reg_hard_core; [6] rst_ mcp_n_hard_core_rst_b; [7]
1677    rst_ mcp_n_reset_cmn_cpu; [8] rst_ mcp_n_reset_cmn_core; [9] rst_rbcn;
1678    [10] rst_dbg; [11] rst_misc_core; [12] rst_dbue (UART); [13]
1679    Pci_resetmdio_n; [14] rst_emac0_hard_core; [15] rst_emac1_hard_core; 16]
1680    rst_pxp_rq_rd_wr; 31:17] reserved */
1681 #define MISC_REG_RESET_REG_2                                     0xa590
1682 /* [RW 20] 20 bit GRC address where the scratch-pad of the MCP that is
1683    shared with the driver resides */
1684 #define MISC_REG_SHARED_MEM_ADDR                                 0xa2b4
1685 /* [RW 32] SPIO. [31-24] FLOAT When any of these bits is written as a '1';
1686    the corresponding SPIO bit will turn off it's drivers and become an
1687    input. This is the reset state of all SPIO pins. The read value of these
1688    bits will be a '1' if that last command (#SET; #CL; or #FLOAT) for this
1689    bit was a #FLOAT. (reset value 0xff). [23-16] CLR When any of these bits
1690    is written as a '1'; the corresponding SPIO bit will drive low. The read
1691    value of these bits will be a '1' if that last command (#SET; #CLR; or
1692 #FLOAT) for this bit was a #CLR. (reset value 0). [15-8] SET When any of
1693    these bits is written as a '1'; the corresponding SPIO bit will drive
1694    high (if it has that capability). The read value of these bits will be a
1695    '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #SET.
1696    (reset value 0). [7-0] VALUE RO; These bits indicate the read value of
1697    each of the eight SPIO pins. This is the result value of the pin; not the
1698    drive value. Writing these bits will have not effect. Each 8 bits field
1699    is divided as follows: [0] VAUX Enable; when pulsed low; enables supply
1700    from VAUX. (This is an output pin only; the FLOAT field is not applicable
1701    for this pin); [1] VAUX Disable; when pulsed low; disables supply form
1702    VAUX. (This is an output pin only; FLOAT field is not applicable for this
1703    pin); [2] SEL_VAUX_B - Control to power switching logic. Drive low to
1704    select VAUX supply. (This is an output pin only; it is not controlled by
1705    the SET and CLR fields; it is controlled by the Main Power SM; the FLOAT
1706    field is not applicable for this pin; only the VALUE fields is relevant -
1707    it reflects the output value); [3] port swap [4] spio_4; [5] spio_5; [6]
1708    Bit 0 of UMP device ID select; read by UMP firmware; [7] Bit 1 of UMP
1709    device ID select; read by UMP firmware. */
1710 #define MISC_REG_SPIO                                            0xa4fc
1711 /* [RW 8] These bits enable the SPIO_INTs to signals event to the IGU/MC.
1712    according to the following map: [3:0] reserved; [4] spio_4 [5] spio_5;
1713    [7:0] reserved */
1714 #define MISC_REG_SPIO_EVENT_EN                                   0xa2b8
1715 /* [RW 32] SPIO INT. [31-24] OLD_CLR Writing a '1' to these bit clears the
1716    corresponding bit in the #OLD_VALUE register. This will acknowledge an
1717    interrupt on the falling edge of corresponding SPIO input (reset value
1718    0). [23-16] OLD_SET Writing a '1' to these bit sets the corresponding bit
1719    in the #OLD_VALUE register. This will acknowledge an interrupt on the
1720    rising edge of corresponding SPIO input (reset value 0). [15-8] OLD_VALUE
1721    RO; These bits indicate the old value of the SPIO input value. When the
1722    ~INT_STATE bit is set; this bit indicates the OLD value of the pin such
1723    that if ~INT_STATE is set and this bit is '0'; then the interrupt is due
1724    to a low to high edge. If ~INT_STATE is set and this bit is '1'; then the
1725    interrupt is due to a high to low edge (reset value 0). [7-0] INT_STATE
1726    RO; These bits indicate the current SPIO interrupt state for each SPIO
1727    pin. This bit is cleared when the appropriate #OLD_SET or #OLD_CLR
1728    command bit is written. This bit is set when the SPIO input does not
1729    match the current value in #OLD_VALUE (reset value 0). */
1730 #define MISC_REG_SPIO_INT                                        0xa500
1731 /* [RW 32] reload value for counter 4 if reload; the value will be reload if
1732    the counter reached zero and the reload bit
1733    (~misc_registers_sw_timer_cfg_4.sw_timer_cfg_4[1] ) is set */
1734 #define MISC_REG_SW_TIMER_RELOAD_VAL_4                           0xa2fc
1735 /* [RW 32] the value of the counter for sw timers1-8. there are 8 addresses
1736    in this register. address 0 - timer 1; address 1 - timer 2, ...  address 7 -
1737    timer 8 */
1738 #define MISC_REG_SW_TIMER_VAL                                    0xa5c0
1739 /* [R 1] Status of two port mode path swap input pin. */
1740 #define MISC_REG_TWO_PORT_PATH_SWAP                              0xa758
1741 /* [RW 2] 2 port swap overwrite.[0] - Overwrite control; if it is 0 - the
1742    path_swap output is equal to 2 port mode path swap input pin; if it is 1
1743    - the path_swap output is equal to bit[1] of this register; [1] -
1744    Overwrite value. If bit[0] of this register is 1 this is the value that
1745    receives the path_swap output. Reset on Hard reset. */
1746 #define MISC_REG_TWO_PORT_PATH_SWAP_OVWR                         0xa72c
1747 /* [RW 1] Set by the MCP to remember if one or more of the drivers is/are
1748    loaded; 0-prepare; -unprepare */
1749 #define MISC_REG_UNPREPARED                                      0xa424
1750 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST      (0x1<<0)
1751 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST      (0x1<<1)
1752 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN    (0x1<<4)
1753 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST      (0x1<<2)
1754 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN       (0x1<<3)
1755 /* [RW 5] MDIO PHY Address. The WC uses this address to determine whether or
1756  * not it is the recipient of the message on the MDIO interface. The value
1757  * is compared to the value on ctrl_md_devad. Drives output
1758  * misc_xgxs0_phy_addr. Global register. */
1759 #define MISC_REG_WC0_CTRL_PHY_ADDR                               0xa9cc
1760 /* [RW 2] XMAC Core port mode. Indicates the number of ports on the system
1761    side. This should be less than or equal to phy_port_mode; if some of the
1762    ports are not used. This enables reduction of frequency on the core side.
1763    This is a strap input for the XMAC_MP core. 00 - Single Port Mode; 01 -
1764    Dual Port Mode; 10 - Tri Port Mode; 11 - Quad Port Mode. This is a strap
1765    input for the XMAC_MP core; and should be changed only while reset is
1766    held low. Reset on Hard reset. */
1767 #define MISC_REG_XMAC_CORE_PORT_MODE                             0xa964
1768 /* [RW 2] XMAC PHY port mode. Indicates the number of ports on the Warp
1769    Core. This is a strap input for the XMAC_MP core. 00 - Single Port Mode;
1770    01 - Dual Port Mode; 1x - Quad Port Mode; This is a strap input for the
1771    XMAC_MP core; and should be changed only while reset is held low. Reset
1772    on Hard reset. */
1773 #define MISC_REG_XMAC_PHY_PORT_MODE                              0xa960
1774 /* [RW 32] 1 [47] Packet Size = 64 Write to this register write bits 31:0.
1775  * Reads from this register will clear bits 31:0. */
1776 #define MSTAT_REG_RX_STAT_GR64_LO                                0x200
1777 /* [RW 32] 1 [00] Tx Good Packet Count Write to this register write bits
1778  * 31:0. Reads from this register will clear bits 31:0. */
1779 #define MSTAT_REG_TX_STAT_GTXPOK_LO                              0
1780 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST      (0x1<<0)
1781 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST      (0x1<<1)
1782 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN    (0x1<<4)
1783 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST      (0x1<<2)
1784 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN       (0x1<<3)
1785 #define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN                  (0x1<<0)
1786 #define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN                  (0x1<<0)
1787 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT      (0x1<<0)
1788 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS    (0x1<<9)
1789 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G          (0x1<<15)
1790 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS      (0xf<<18)
1791 /* [RW 1] Input enable for RX_BMAC0 IF */
1792 #define NIG_REG_BMAC0_IN_EN                                      0x100ac
1793 /* [RW 1] output enable for TX_BMAC0 IF */
1794 #define NIG_REG_BMAC0_OUT_EN                                     0x100e0
1795 /* [RW 1] output enable for TX BMAC pause port 0 IF */
1796 #define NIG_REG_BMAC0_PAUSE_OUT_EN                               0x10110
1797 /* [RW 1] output enable for RX_BMAC0_REGS IF */
1798 #define NIG_REG_BMAC0_REGS_OUT_EN                                0x100e8
1799 /* [RW 1] output enable for RX BRB1 port0 IF */
1800 #define NIG_REG_BRB0_OUT_EN                                      0x100f8
1801 /* [RW 1] Input enable for TX BRB1 pause port 0 IF */
1802 #define NIG_REG_BRB0_PAUSE_IN_EN                                 0x100c4
1803 /* [RW 1] output enable for RX BRB1 port1 IF */
1804 #define NIG_REG_BRB1_OUT_EN                                      0x100fc
1805 /* [RW 1] Input enable for TX BRB1 pause port 1 IF */
1806 #define NIG_REG_BRB1_PAUSE_IN_EN                                 0x100c8
1807 /* [RW 1] output enable for RX BRB1 LP IF */
1808 #define NIG_REG_BRB_LB_OUT_EN                                    0x10100
1809 /* [WB_W 82] Debug packet to LP from RBC; Data spelling:[63:0] data; 64]
1810    error; [67:65]eop_bvalid; [68]eop; [69]sop; [70]port_id; 71]flush;
1811    72:73]-vnic_num; 81:74]-sideband_info */
1812 #define NIG_REG_DEBUG_PACKET_LB                                  0x10800
1813 /* [RW 1] Input enable for TX Debug packet */
1814 #define NIG_REG_EGRESS_DEBUG_IN_EN                               0x100dc
1815 /* [RW 1] If 1 - egress drain mode for port0 is active. In this mode all
1816    packets from PBFare not forwarded to the MAC and just deleted from FIFO.
1817    First packet may be deleted from the middle. And last packet will be
1818    always deleted till the end. */
1819 #define NIG_REG_EGRESS_DRAIN0_MODE                               0x10060
1820 /* [RW 1] Output enable to EMAC0 */
1821 #define NIG_REG_EGRESS_EMAC0_OUT_EN                              0x10120
1822 /* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs
1823    to emac for port0; other way to bmac for port0 */
1824 #define NIG_REG_EGRESS_EMAC0_PORT                                0x10058
1825 /* [RW 1] Input enable for TX PBF user packet port0 IF */
1826 #define NIG_REG_EGRESS_PBF0_IN_EN                                0x100cc
1827 /* [RW 1] Input enable for TX PBF user packet port1 IF */
1828 #define NIG_REG_EGRESS_PBF1_IN_EN                                0x100d0
1829 /* [RW 1] Input enable for TX UMP management packet port0 IF */
1830 #define NIG_REG_EGRESS_UMP0_IN_EN                                0x100d4
1831 /* [RW 1] Input enable for RX_EMAC0 IF */
1832 #define NIG_REG_EMAC0_IN_EN                                      0x100a4
1833 /* [RW 1] output enable for TX EMAC pause port 0 IF */
1834 #define NIG_REG_EMAC0_PAUSE_OUT_EN                               0x10118
1835 /* [R 1] status from emac0. This bit is set when MDINT from either the
1836    EXT_MDINT pin or from the Copper PHY is driven low. This condition must
1837    be cleared in the attached PHY device that is driving the MINT pin. */
1838 #define NIG_REG_EMAC0_STATUS_MISC_MI_INT                         0x10494
1839 /* [WB 48] This address space contains BMAC0 registers. The BMAC registers
1840    are described in appendix A. In order to access the BMAC0 registers; the
1841    base address; NIG_REGISTERS_INGRESS_BMAC0_MEM; Offset: 0x10c00; should be
1842    added to each BMAC register offset */
1843 #define NIG_REG_INGRESS_BMAC0_MEM                                0x10c00
1844 /* [WB 48] This address space contains BMAC1 registers. The BMAC registers
1845    are described in appendix A. In order to access the BMAC0 registers; the
1846    base address; NIG_REGISTERS_INGRESS_BMAC1_MEM; Offset: 0x11000; should be
1847    added to each BMAC register offset */
1848 #define NIG_REG_INGRESS_BMAC1_MEM                                0x11000
1849 /* [R 1] FIFO empty in EOP descriptor FIFO of LP in NIG_RX_EOP */
1850 #define NIG_REG_INGRESS_EOP_LB_EMPTY                             0x104e0
1851 /* [RW 17] Debug only. RX_EOP_DSCR_lb_FIFO in NIG_RX_EOP. Data
1852    packet_length[13:0]; mac_error[14]; trunc_error[15]; parity[16] */
1853 #define NIG_REG_INGRESS_EOP_LB_FIFO                              0x104e4
1854 /* [RW 27] 0 - must be active for Everest A0; 1- for Everest B0 when latch
1855    logic for interrupts must be used. Enable per bit of interrupt of
1856    ~latch_status.latch_status */
1857 #define NIG_REG_LATCH_BC_0                                       0x16210
1858 /* [RW 27] Latch for each interrupt from Unicore.b[0]
1859    status_emac0_misc_mi_int; b[1] status_emac0_misc_mi_complete;
1860    b[2]status_emac0_misc_cfg_change; b[3]status_emac0_misc_link_status;
1861    b[4]status_emac0_misc_link_change; b[5]status_emac0_misc_attn;
1862    b[6]status_serdes0_mac_crs; b[7]status_serdes0_autoneg_complete;
1863    b[8]status_serdes0_fiber_rxact; b[9]status_serdes0_link_status;
1864    b[10]status_serdes0_mr_page_rx; b[11]status_serdes0_cl73_an_complete;
1865    b[12]status_serdes0_cl73_mr_page_rx; b[13]status_serdes0_rx_sigdet;
1866    b[14]status_xgxs0_remotemdioreq; b[15]status_xgxs0_link10g;
1867    b[16]status_xgxs0_autoneg_complete; b[17]status_xgxs0_fiber_rxact;
1868    b[21:18]status_xgxs0_link_status; b[22]status_xgxs0_mr_page_rx;
1869    b[23]status_xgxs0_cl73_an_complete; b[24]status_xgxs0_cl73_mr_page_rx;
1870    b[25]status_xgxs0_rx_sigdet; b[26]status_xgxs0_mac_crs */
1871 #define NIG_REG_LATCH_STATUS_0                                   0x18000
1872 /* [RW 1] led 10g for port 0 */
1873 #define NIG_REG_LED_10G_P0                                       0x10320
1874 /* [RW 1] led 10g for port 1 */
1875 #define NIG_REG_LED_10G_P1                                       0x10324
1876 /* [RW 1] Port0: This bit is set to enable the use of the
1877    ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 field
1878    defined below. If this bit is cleared; then the blink rate will be about
1879    8Hz. */
1880 #define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0                    0x10318
1881 /* [RW 12] Port0: Specifies the period of each blink cycle (on + off) for
1882    Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field
1883    is reset to 0x080; giving a default blink period of approximately 8Hz. */
1884 #define NIG_REG_LED_CONTROL_BLINK_RATE_P0                        0x10310
1885 /* [RW 1] Port0: If set along with the
1886  ~nig_registers_led_control_override_traffic_p0.led_control_override_traffic_p0
1887    bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED
1888    bit; the Traffic LED will blink with the blink rate specified in
1889    ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
1890    ~nig_registers_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
1891    fields. */
1892 #define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0                     0x10308
1893 /* [RW 1] Port0: If set overrides hardware control of the Traffic LED. The
1894    Traffic LED will then be controlled via bit ~nig_registers_
1895    led_control_traffic_p0.led_control_traffic_p0 and bit
1896    ~nig_registers_led_control_blink_traffic_p0.led_control_blink_traffic_p0 */
1897 #define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0                  0x102f8
1898 /* [RW 1] Port0: If set along with the led_control_override_trafic_p0 bit;
1899    turns on the Traffic LED. If the led_control_blink_traffic_p0 bit is also
1900    set; the LED will blink with blink rate specified in
1901    ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
1902    ~nig_regsters_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
1903    fields. */
1904 #define NIG_REG_LED_CONTROL_TRAFFIC_P0                           0x10300
1905 /* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3;
1906    9-11PHY7; 12 MAC4; 13-15 PHY10; */
1907 #define NIG_REG_LED_MODE_P0                                      0x102f0
1908 /* [RW 3] for port0 enable for llfc ppp and pause. b0 - brb1 enable; b1-
1909    tsdm enable; b2- usdm enable */
1910 #define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0                         0x16070
1911 #define NIG_REG_LLFC_EGRESS_SRC_ENABLE_1                         0x16074
1912 /* [RW 1] SAFC enable for port0. This register may get 1 only when
1913    ~ppp_enable.ppp_enable = 0 and pause_enable.pause_enable =0 for the same
1914    port */
1915 #define NIG_REG_LLFC_ENABLE_0                                    0x16208
1916 #define NIG_REG_LLFC_ENABLE_1                                    0x1620c
1917 /* [RW 16] classes are high-priority for port0 */
1918 #define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0                     0x16058
1919 #define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1                     0x1605c
1920 /* [RW 16] classes are low-priority for port0 */
1921 #define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0                      0x16060
1922 #define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1                      0x16064
1923 /* [RW 1] Output enable of message to LLFC BMAC IF for port0 */
1924 #define NIG_REG_LLFC_OUT_EN_0                                    0x160c8
1925 #define NIG_REG_LLFC_OUT_EN_1                                    0x160cc
1926 #define NIG_REG_LLH0_ACPI_PAT_0_CRC                              0x1015c
1927 #define NIG_REG_LLH0_ACPI_PAT_6_LEN                              0x10154
1928 #define NIG_REG_LLH0_BRB1_DRV_MASK                               0x10244
1929 #define NIG_REG_LLH0_BRB1_DRV_MASK_MF                            0x16048
1930 /* [RW 1] send to BRB1 if no match on any of RMP rules. */
1931 #define NIG_REG_LLH0_BRB1_NOT_MCP                                0x1025c
1932 /* [RW 2] Determine the classification participants. 0: no classification.1:
1933    classification upon VLAN id. 2: classification upon MAC address. 3:
1934    classification upon both VLAN id & MAC addr. */
1935 #define NIG_REG_LLH0_CLS_TYPE                                    0x16080
1936 /* [RW 32] cm header for llh0 */
1937 #define NIG_REG_LLH0_CM_HEADER                                   0x1007c
1938 #define NIG_REG_LLH0_DEST_IP_0_1                                 0x101dc
1939 #define NIG_REG_LLH0_DEST_MAC_0_0                                0x101c0
1940 /* [RW 16] destination TCP address 1. The LLH will look for this address in
1941    all incoming packets. */
1942 #define NIG_REG_LLH0_DEST_TCP_0                                  0x10220
1943 /* [RW 16] destination UDP address 1 The LLH will look for this address in
1944    all incoming packets. */
1945 #define NIG_REG_LLH0_DEST_UDP_0                                  0x10214
1946 #define NIG_REG_LLH0_ERROR_MASK                                  0x1008c
1947 /* [RW 8] event id for llh0 */
1948 #define NIG_REG_LLH0_EVENT_ID                                    0x10084
1949 #define NIG_REG_LLH0_FUNC_EN                                     0x160fc
1950 #define NIG_REG_LLH0_FUNC_MEM                                    0x16180
1951 #define NIG_REG_LLH0_FUNC_MEM_ENABLE                             0x16140
1952 #define NIG_REG_LLH0_FUNC_VLAN_ID                                0x16100
1953 /* [RW 1] Determine the IP version to look for in
1954    ~nig_registers_llh0_dest_ip_0.llh0_dest_ip_0. 0 - IPv6; 1-IPv4 */
1955 #define NIG_REG_LLH0_IPV4_IPV6_0                                 0x10208
1956 /* [RW 1] t bit for llh0 */
1957 #define NIG_REG_LLH0_T_BIT                                       0x10074
1958 /* [RW 12] VLAN ID 1. In case of VLAN packet the LLH will look for this ID. */
1959 #define NIG_REG_LLH0_VLAN_ID_0                                   0x1022c
1960 /* [RW 8] init credit counter for port0 in LLH */
1961 #define NIG_REG_LLH0_XCM_INIT_CREDIT                             0x10554
1962 #define NIG_REG_LLH0_XCM_MASK                                    0x10130
1963 #define NIG_REG_LLH1_BRB1_DRV_MASK                               0x10248
1964 /* [RW 1] send to BRB1 if no match on any of RMP rules. */
1965 #define NIG_REG_LLH1_BRB1_NOT_MCP                                0x102dc
1966 /* [RW 2] Determine the classification participants. 0: no classification.1:
1967    classification upon VLAN id. 2: classification upon MAC address. 3:
1968    classification upon both VLAN id & MAC addr. */
1969 #define NIG_REG_LLH1_CLS_TYPE                                    0x16084
1970 /* [RW 32] cm header for llh1 */
1971 #define NIG_REG_LLH1_CM_HEADER                                   0x10080
1972 #define NIG_REG_LLH1_ERROR_MASK                                  0x10090
1973 /* [RW 8] event id for llh1 */
1974 #define NIG_REG_LLH1_EVENT_ID                                    0x10088
1975 #define NIG_REG_LLH1_FUNC_MEM                                    0x161c0
1976 #define NIG_REG_LLH1_FUNC_MEM_ENABLE                             0x16160
1977 #define NIG_REG_LLH1_FUNC_MEM_SIZE                               16
1978 /* [RW 1] When this bit is set; the LLH will classify the packet before
1979  * sending it to the BRB or calculating WoL on it. This bit controls port 1
1980  * only. The legacy llh_multi_function_mode bit controls port 0. */
1981 #define NIG_REG_LLH1_MF_MODE                                     0x18614
1982 /* [RW 8] init credit counter for port1 in LLH */
1983 #define NIG_REG_LLH1_XCM_INIT_CREDIT                             0x10564
1984 #define NIG_REG_LLH1_XCM_MASK                                    0x10134
1985 /* [RW 1] When this bit is set; the LLH will expect all packets to be with
1986    e1hov */
1987 #define NIG_REG_LLH_E1HOV_MODE                                   0x160d8
1988 /* [RW 1] When this bit is set; the LLH will classify the packet before
1989    sending it to the BRB or calculating WoL on it. */
1990 #define NIG_REG_LLH_MF_MODE                                      0x16024
1991 #define NIG_REG_MASK_INTERRUPT_PORT0                             0x10330
1992 #define NIG_REG_MASK_INTERRUPT_PORT1                             0x10334
1993 /* [RW 1] Output signal from NIG to EMAC0. When set enables the EMAC0 block. */
1994 #define NIG_REG_NIG_EMAC0_EN                                     0x1003c
1995 /* [RW 1] Output signal from NIG to EMAC1. When set enables the EMAC1 block. */
1996 #define NIG_REG_NIG_EMAC1_EN                                     0x10040
1997 /* [RW 1] Output signal from NIG to TX_EMAC0. When set indicates to the
1998    EMAC0 to strip the CRC from the ingress packets. */
1999 #define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC                         0x10044
2000 /* [R 32] Interrupt register #0 read */
2001 #define NIG_REG_NIG_INT_STS_0                                    0x103b0
2002 #define NIG_REG_NIG_INT_STS_1                                    0x103c0
2003 /* [R 32] Legacy E1 and E1H location for parity error mask register. */
2004 #define NIG_REG_NIG_PRTY_MASK                                    0x103dc
2005 /* [RW 32] Parity mask register #0 read/write */
2006 #define NIG_REG_NIG_PRTY_MASK_0                                  0x183c8
2007 #define NIG_REG_NIG_PRTY_MASK_1                                  0x183d8
2008 /* [R 32] Legacy E1 and E1H location for parity error status register. */
2009 #define NIG_REG_NIG_PRTY_STS                                     0x103d0
2010 /* [R 32] Parity register #0 read */
2011 #define NIG_REG_NIG_PRTY_STS_0                                   0x183bc
2012 #define NIG_REG_NIG_PRTY_STS_1                                   0x183cc
2013 /* [R 32] Legacy E1 and E1H location for parity error status clear register. */
2014 #define NIG_REG_NIG_PRTY_STS_CLR                                 0x103d4
2015 /* [RC 32] Parity register #0 read clear */
2016 #define NIG_REG_NIG_PRTY_STS_CLR_0                               0x183c0
2017 #define NIG_REG_NIG_PRTY_STS_CLR_1                               0x183d0
2018 #define MCPR_IMC_COMMAND_ENABLE                                  (1L<<31)
2019 #define MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT                     16
2020 #define MCPR_IMC_COMMAND_OPERATION_BITSHIFT                      28
2021 #define MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT               8
2022 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2023  * Ethernet header. */
2024 #define NIG_REG_P0_HDRS_AFTER_BASIC                              0x18038
2025 /* [RW 1] HW PFC enable bit. Set this bit to enable the PFC functionality in
2026  * the NIG. Other flow control modes such as PAUSE and SAFC/LLFC should be
2027  * disabled when this bit is set. */
2028 #define NIG_REG_P0_HWPFC_ENABLE                          0x18078
2029 #define NIG_REG_P0_LLH_FUNC_MEM2                                 0x18480
2030 #define NIG_REG_P0_LLH_FUNC_MEM2_ENABLE                  0x18440
2031 /* [RW 1] Input enable for RX MAC interface. */
2032 #define NIG_REG_P0_MAC_IN_EN                                     0x185ac
2033 /* [RW 1] Output enable for TX MAC interface */
2034 #define NIG_REG_P0_MAC_OUT_EN                                    0x185b0
2035 /* [RW 1] Output enable for TX PAUSE signal to the MAC. */
2036 #define NIG_REG_P0_MAC_PAUSE_OUT_EN                              0x185b4
2037 /* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for
2038  * future expansion) each priorty is to be mapped to. Bits 3:0 specify the
2039  * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit
2040  * priority field is extracted from the outer-most VLAN in receive packet.
2041  * Only COS 0 and COS 1 are supported in E2. */
2042 #define NIG_REG_P0_PKT_PRIORITY_TO_COS                           0x18054
2043 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A
2044  * priority is mapped to COS 0 when the corresponding mask bit is 1. More
2045  * than one bit may be set; allowing multiple priorities to be mapped to one
2046  * COS. */
2047 #define NIG_REG_P0_RX_COS0_PRIORITY_MASK                         0x18058
2048 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A
2049  * priority is mapped to COS 1 when the corresponding mask bit is 1. More
2050  * than one bit may be set; allowing multiple priorities to be mapped to one
2051  * COS. */
2052 #define NIG_REG_P0_RX_COS1_PRIORITY_MASK                         0x1805c
2053 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A
2054  * priority is mapped to COS 2 when the corresponding mask bit is 1. More
2055  * than one bit may be set; allowing multiple priorities to be mapped to one
2056  * COS. */
2057 #define NIG_REG_P0_RX_COS2_PRIORITY_MASK                         0x186b0
2058 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 3. A
2059  * priority is mapped to COS 3 when the corresponding mask bit is 1. More
2060  * than one bit may be set; allowing multiple priorities to be mapped to one
2061  * COS. */
2062 #define NIG_REG_P0_RX_COS3_PRIORITY_MASK                         0x186b4
2063 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 4. A
2064  * priority is mapped to COS 4 when the corresponding mask bit is 1. More
2065  * than one bit may be set; allowing multiple priorities to be mapped to one
2066  * COS. */
2067 #define NIG_REG_P0_RX_COS4_PRIORITY_MASK                         0x186b8
2068 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 5. A
2069  * priority is mapped to COS 5 when the corresponding mask bit is 1. More
2070  * than one bit may be set; allowing multiple priorities to be mapped to one
2071  * COS. */
2072 #define NIG_REG_P0_RX_COS5_PRIORITY_MASK                         0x186bc
2073 /* [R 1] RX FIFO for receiving data from MAC is empty. */
2074 /* [RW 15] Specify which of the credit registers the client is to be mapped
2075  * to. Bits[2:0] are for client 0; bits [14:12] are for client 4. For
2076  * clients that are not subject to WFQ credit blocking - their
2077  * specifications here are not used. */
2078 #define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP                      0x180f0
2079 /* [RW 32] Specify which of the credit registers the client is to be mapped
2080  * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are
2081  * for client 0; bits [35:32] are for client 8. For clients that are not
2082  * subject to WFQ credit blocking - their specifications here are not used.
2083  * This is a new register (with 2_) added in E3 B0 to accommodate the 9
2084  * input clients to ETS arbiter. The reset default is set for management and
2085  * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2086  * use credit registers 0-5 respectively (0x543210876). Note that credit
2087  * registers can not be shared between clients. */
2088 #define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB                 0x18688
2089 /* [RW 4] Specify which of the credit registers the client is to be mapped
2090  * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are
2091  * for client 0; bits [35:32] are for client 8. For clients that are not
2092  * subject to WFQ credit blocking - their specifications here are not used.
2093  * This is a new register (with 2_) added in E3 B0 to accommodate the 9
2094  * input clients to ETS arbiter. The reset default is set for management and
2095  * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2096  * use credit registers 0-5 respectively (0x543210876). Note that credit
2097  * registers can not be shared between clients. */
2098 #define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB                 0x1868c
2099 /* [RW 5] Specify whether the client competes directly in the strict
2100  * priority arbiter. The bits are mapped according to client ID (client IDs
2101  * are defined in tx_arb_priority_client). Default value is set to enable
2102  * strict priorities for clients 0-2 -- management and debug traffic. */
2103 #define NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT                       0x180e8
2104 /* [RW 5] Specify whether the client is subject to WFQ credit blocking. The
2105  * bits are mapped according to client ID (client IDs are defined in
2106  * tx_arb_priority_client). Default value is 0 for not using WFQ credit
2107  * blocking. */
2108 #define NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ          0x180ec
2109 /* [RW 32] Specify the upper bound that credit register 0 is allowed to
2110  * reach. */
2111 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0                   0x1810c
2112 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1                   0x18110
2113 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2                   0x18114
2114 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3                   0x18118
2115 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4                   0x1811c
2116 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5                   0x186a0
2117 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6                   0x186a4
2118 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7                   0x186a8
2119 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8                   0x186ac
2120 /* [RW 32] Specify the weight (in bytes) to be added to credit register 0
2121  * when it is time to increment. */
2122 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0                        0x180f8
2123 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1                        0x180fc
2124 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2                        0x18100
2125 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3                        0x18104
2126 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4                        0x18108
2127 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5                        0x18690
2128 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6                        0x18694
2129 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7                        0x18698
2130 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8                        0x1869c
2131 /* [RW 12] Specify the number of strict priority arbitration slots between
2132  * two round-robin arbitration slots to avoid starvation. A value of 0 means
2133  * no strict priority cycles - the strict priority with anti-starvation
2134  * arbiter becomes a round-robin arbiter. */
2135 #define NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS                   0x180f4
2136 /* [RW 15] Specify the client number to be assigned to each priority of the
2137  * strict priority arbiter. Priority 0 is the highest priority. Bits [2:0]
2138  * are for priority 0 client; bits [14:12] are for priority 4 client. The
2139  * clients are assigned the following IDs: 0-management; 1-debug traffic
2140  * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1
2141  * traffic. The reset value[14:0] is set to 0x4688 (15'b100_011_010_001_000)
2142  * for management at priority 0; debug traffic at priorities 1 and 2; COS0
2143  * traffic at priority 3; and COS1 traffic at priority 4. */
2144 #define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT                        0x180e4
2145 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2146  * Ethernet header. */
2147 #define NIG_REG_P1_HDRS_AFTER_BASIC                              0x1818c
2148 #define NIG_REG_P1_LLH_FUNC_MEM2                                 0x184c0
2149 #define NIG_REG_P1_LLH_FUNC_MEM2_ENABLE                  0x18460
2150 /* [RW 32] Specify the client number to be assigned to each priority of the
2151  * strict priority arbiter. This register specifies bits 31:0 of the 36-bit
2152  * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
2153  * client; bits [35-32] are for priority 8 client. The clients are assigned
2154  * the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2155  * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
2156  * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2157  * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
2158  * accommodate the 9 input clients to ETS arbiter. */
2159 #define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB                   0x18680
2160 /* [RW 4] Specify the client number to be assigned to each priority of the
2161  * strict priority arbiter. This register specifies bits 35:32 of the 36-bit
2162  * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
2163  * client; bits [35-32] are for priority 8 client. The clients are assigned
2164  * the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2165  * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
2166  * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2167  * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
2168  * accommodate the 9 input clients to ETS arbiter. */
2169 #define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB                   0x18684
2170 #define NIG_REG_P1_MAC_IN_EN                                     0x185c0
2171 /* [RW 1] Output enable for TX MAC interface */
2172 #define NIG_REG_P1_MAC_OUT_EN                                    0x185c4
2173 /* [RW 1] Output enable for TX PAUSE signal to the MAC. */
2174 #define NIG_REG_P1_MAC_PAUSE_OUT_EN                              0x185c8
2175 /* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for
2176  * future expansion) each priorty is to be mapped to. Bits 3:0 specify the
2177  * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit
2178  * priority field is extracted from the outer-most VLAN in receive packet.
2179  * Only COS 0 and COS 1 are supported in E2. */
2180 #define NIG_REG_P1_PKT_PRIORITY_TO_COS                           0x181a8
2181 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A
2182  * priority is mapped to COS 0 when the corresponding mask bit is 1. More
2183  * than one bit may be set; allowing multiple priorities to be mapped to one
2184  * COS. */
2185 #define NIG_REG_P1_RX_COS0_PRIORITY_MASK                         0x181ac
2186 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A
2187  * priority is mapped to COS 1 when the corresponding mask bit is 1. More
2188  * than one bit may be set; allowing multiple priorities to be mapped to one
2189  * COS. */
2190 #define NIG_REG_P1_RX_COS1_PRIORITY_MASK                         0x181b0
2191 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A
2192  * priority is mapped to COS 2 when the corresponding mask bit is 1. More
2193  * than one bit may be set; allowing multiple priorities to be mapped to one
2194  * COS. */
2195 #define NIG_REG_P1_RX_COS2_PRIORITY_MASK                         0x186f8
2196 /* [R 1] RX FIFO for receiving data from MAC is empty. */
2197 #define NIG_REG_P1_RX_MACFIFO_EMPTY                              0x1858c
2198 /* [R 1] TLLH FIFO is empty. */
2199 #define NIG_REG_P1_TLLH_FIFO_EMPTY                               0x18338
2200 /* [RW 32] Specify which of the credit registers the client is to be mapped
2201  * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are
2202  * for client 0; bits [35:32] are for client 8. For clients that are not
2203  * subject to WFQ credit blocking - their specifications here are not used.
2204  * This is a new register (with 2_) added in E3 B0 to accommodate the 9
2205  * input clients to ETS arbiter. The reset default is set for management and
2206  * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2207  * use credit registers 0-5 respectively (0x543210876). Note that credit
2208  * registers can not be shared between clients. Note also that there are
2209  * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only
2210  * credit registers 0-5 are valid. This register should be configured
2211  * appropriately before enabling WFQ. */
2212 #define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB                 0x186e8
2213 /* [RW 4] Specify which of the credit registers the client is to be mapped
2214  * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are
2215  * for client 0; bits [35:32] are for client 8. For clients that are not
2216  * subject to WFQ credit blocking - their specifications here are not used.
2217  * This is a new register (with 2_) added in E3 B0 to accommodate the 9
2218  * input clients to ETS arbiter. The reset default is set for management and
2219  * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2220  * use credit registers 0-5 respectively (0x543210876). Note that credit
2221  * registers can not be shared between clients. Note also that there are
2222  * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only
2223  * credit registers 0-5 are valid. This register should be configured
2224  * appropriately before enabling WFQ. */
2225 #define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB                 0x186ec
2226 /* [RW 9] Specify whether the client competes directly in the strict
2227  * priority arbiter. The bits are mapped according to client ID (client IDs
2228  * are defined in tx_arb_priority_client2): 0-management; 1-debug traffic
2229  * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1
2230  * traffic; 5-COS2 traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic.
2231  * Default value is set to enable strict priorities for all clients. */
2232 #define NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT                       0x18234
2233 /* [RW 9] Specify whether the client is subject to WFQ credit blocking. The
2234  * bits are mapped according to client ID (client IDs are defined in
2235  * tx_arb_priority_client2): 0-management; 1-debug traffic from this port;
2236  * 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2
2237  * traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. Default value is
2238  * 0 for not using WFQ credit blocking. */
2239 #define NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ                  0x18238
2240 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0                   0x18258
2241 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1                   0x1825c
2242 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2                   0x18260
2243 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3                   0x18264
2244 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4                   0x18268
2245 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5                   0x186f4
2246 /* [RW 32] Specify the weight (in bytes) to be added to credit register 0
2247  * when it is time to increment. */
2248 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0                        0x18244
2249 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1                        0x18248
2250 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2                        0x1824c
2251 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3                        0x18250
2252 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4                        0x18254
2253 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5                        0x186f0
2254 /* [RW 12] Specify the number of strict priority arbitration slots between
2255    two round-robin arbitration slots to avoid starvation. A value of 0 means
2256    no strict priority cycles - the strict priority with anti-starvation
2257    arbiter becomes a round-robin arbiter. */
2258 #define NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS                   0x18240
2259 /* [RW 32] Specify the client number to be assigned to each priority of the
2260    strict priority arbiter. This register specifies bits 31:0 of the 36-bit
2261    value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
2262    client; bits [35-32] are for priority 8 client. The clients are assigned
2263    the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2264    traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
2265    6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2266    set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
2267    accommodate the 9 input clients to ETS arbiter. Note that this register
2268    is the same as the one for port 0, except that port 1 only has COS 0-2
2269    traffic. There is no traffic for COS 3-5 of port 1. */
2270 #define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB                   0x186e0
2271 /* [RW 4] Specify the client number to be assigned to each priority of the
2272    strict priority arbiter. This register specifies bits 35:32 of the 36-bit
2273    value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
2274    client; bits [35-32] are for priority 8 client. The clients are assigned
2275    the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2276    traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
2277    6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2278    set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
2279    accommodate the 9 input clients to ETS arbiter. Note that this register
2280    is the same as the one for port 0, except that port 1 only has COS 0-2
2281    traffic. There is no traffic for COS 3-5 of port 1. */
2282 #define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB                   0x186e4
2283 /* [R 1] TX FIFO for transmitting data to MAC is empty. */
2284 #define NIG_REG_P1_TX_MACFIFO_EMPTY                              0x18594
2285 /* [R 1] FIFO empty status of the MCP TX FIFO used for storing MCP packets
2286    forwarded to the host. */
2287 #define NIG_REG_P1_TX_MNG_HOST_FIFO_EMPTY                        0x182b8
2288 /* [RW 32] Specify the upper bound that credit register 0 is allowed to
2289  * reach. */
2290 /* [RW 1] Pause enable for port0. This register may get 1 only when
2291    ~safc_enable.safc_enable = 0 and ppp_enable.ppp_enable =0 for the same
2292    port */
2293 #define NIG_REG_PAUSE_ENABLE_0                                   0x160c0
2294 #define NIG_REG_PAUSE_ENABLE_1                                   0x160c4
2295 /* [RW 1] Input enable for RX PBF LP IF */
2296 #define NIG_REG_PBF_LB_IN_EN                                     0x100b4
2297 /* [RW 1] Value of this register will be transmitted to port swap when
2298    ~nig_registers_strap_override.strap_override =1 */
2299 #define NIG_REG_PORT_SWAP                                        0x10394
2300 /* [RW 1] PPP enable for port0. This register may get 1 only when
2301  * ~safc_enable.safc_enable = 0 and pause_enable.pause_enable =0 for the
2302  * same port */
2303 #define NIG_REG_PPP_ENABLE_0                                     0x160b0
2304 #define NIG_REG_PPP_ENABLE_1                                     0x160b4
2305 /* [RW 1] output enable for RX parser descriptor IF */
2306 #define NIG_REG_PRS_EOP_OUT_EN                                   0x10104
2307 /* [RW 1] Input enable for RX parser request IF */
2308 #define NIG_REG_PRS_REQ_IN_EN                                    0x100b8
2309 /* [RW 5] control to serdes - CL45 DEVAD */
2310 #define NIG_REG_SERDES0_CTRL_MD_DEVAD                            0x10370
2311 /* [RW 1] control to serdes; 0 - clause 45; 1 - clause 22 */
2312 #define NIG_REG_SERDES0_CTRL_MD_ST                               0x1036c
2313 /* [RW 5] control to serdes - CL22 PHY_ADD and CL45 PRTAD */
2314 #define NIG_REG_SERDES0_CTRL_PHY_ADDR                            0x10374
2315 /* [R 1] status from serdes0 that inputs to interrupt logic of link status */
2316 #define NIG_REG_SERDES0_STATUS_LINK_STATUS                       0x10578
2317 /* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
2318    for port0 */
2319 #define NIG_REG_STAT0_BRB_DISCARD                                0x105f0
2320 /* [R 32] Rx statistics : In user packets truncated due to BRB backpressure
2321    for port0 */
2322 #define NIG_REG_STAT0_BRB_TRUNCATE                               0x105f8
2323 /* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
2324    between 1024 and 1522 bytes for port0 */
2325 #define NIG_REG_STAT0_EGRESS_MAC_PKT0                            0x10750
2326 /* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
2327    between 1523 bytes and above for port0 */
2328 #define NIG_REG_STAT0_EGRESS_MAC_PKT1                            0x10760
2329 /* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
2330    for port1 */
2331 #define NIG_REG_STAT1_BRB_DISCARD                                0x10628
2332 /* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
2333    between 1024 and 1522 bytes for port1 */
2334 #define NIG_REG_STAT1_EGRESS_MAC_PKT0                            0x107a0
2335 /* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
2336    between 1523 bytes and above for port1 */
2337 #define NIG_REG_STAT1_EGRESS_MAC_PKT1                            0x107b0
2338 /* [WB_R 64] Rx statistics : User octets received for LP */
2339 #define NIG_REG_STAT2_BRB_OCTET                                  0x107e0
2340 #define NIG_REG_STATUS_INTERRUPT_PORT0                           0x10328
2341 #define NIG_REG_STATUS_INTERRUPT_PORT1                           0x1032c
2342 /* [RW 1] port swap mux selection. If this register equal to 0 then port
2343    swap is equal to SPIO pin that inputs from ifmux_serdes_swap. If 1 then
2344    ort swap is equal to ~nig_registers_port_swap.port_swap */
2345 #define NIG_REG_STRAP_OVERRIDE                                   0x10398
2346 /* [RW 1] output enable for RX_XCM0 IF */
2347 #define NIG_REG_XCM0_OUT_EN                                      0x100f0
2348 /* [RW 1] output enable for RX_XCM1 IF */
2349 #define NIG_REG_XCM1_OUT_EN                                      0x100f4
2350 /* [RW 1] control to xgxs - remote PHY in-band MDIO */
2351 #define NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST                       0x10348
2352 /* [RW 5] control to xgxs - CL45 DEVAD */
2353 #define NIG_REG_XGXS0_CTRL_MD_DEVAD                              0x1033c
2354 /* [RW 1] control to xgxs; 0 - clause 45; 1 - clause 22 */
2355 #define NIG_REG_XGXS0_CTRL_MD_ST                                 0x10338
2356 /* [RW 5] control to xgxs - CL22 PHY_ADD and CL45 PRTAD */
2357 #define NIG_REG_XGXS0_CTRL_PHY_ADDR                              0x10340
2358 /* [R 1] status from xgxs0 that inputs to interrupt logic of link10g. */
2359 #define NIG_REG_XGXS0_STATUS_LINK10G                             0x10680
2360 /* [R 4] status from xgxs0 that inputs to interrupt logic of link status */
2361 #define NIG_REG_XGXS0_STATUS_LINK_STATUS                         0x10684
2362 /* [RW 2] selection for XGXS lane of port 0 in NIG_MUX block */
2363 #define NIG_REG_XGXS_LANE_SEL_P0                                 0x102e8
2364 /* [RW 1] selection for port0 for NIG_MUX block : 0 = SerDes; 1 = XGXS */
2365 #define NIG_REG_XGXS_SERDES0_MODE_SEL                            0x102e0
2366 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT  (0x1<<0)
2367 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS (0x1<<9)
2368 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G      (0x1<<15)
2369 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS  (0xf<<18)
2370 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 18
2371 /* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter. */
2372 #define PBF_REG_COS0_UPPER_BOUND                                 0x15c05c
2373 /* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter
2374  * of port 0. */
2375 #define PBF_REG_COS0_UPPER_BOUND_P0                              0x15c2cc
2376 /* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter
2377  * of port 1. */
2378 #define PBF_REG_COS0_UPPER_BOUND_P1                              0x15c2e4
2379 /* [RW 31] The weight of COS0 in the ETS command arbiter. */
2380 #define PBF_REG_COS0_WEIGHT                                      0x15c054
2381 /* [RW 31] The weight of COS0 in port 0 ETS command arbiter. */
2382 #define PBF_REG_COS0_WEIGHT_P0                                   0x15c2a8
2383 /* [RW 31] The weight of COS0 in port 1 ETS command arbiter. */
2384 #define PBF_REG_COS0_WEIGHT_P1                                   0x15c2c0
2385 /* [RW 31] The upper bound of the weight of COS1 in the ETS command arbiter. */
2386 #define PBF_REG_COS1_UPPER_BOUND                                 0x15c060
2387 /* [RW 31] The weight of COS1 in the ETS command arbiter. */
2388 #define PBF_REG_COS1_WEIGHT                                      0x15c058
2389 /* [RW 31] The weight of COS1 in port 0 ETS command arbiter. */
2390 #define PBF_REG_COS1_WEIGHT_P0                                   0x15c2ac
2391 /* [RW 31] The weight of COS1 in port 1 ETS command arbiter. */
2392 #define PBF_REG_COS1_WEIGHT_P1                                   0x15c2c4
2393 /* [RW 31] The weight of COS2 in port 0 ETS command arbiter. */
2394 #define PBF_REG_COS2_WEIGHT_P0                                   0x15c2b0
2395 /* [RW 31] The weight of COS2 in port 1 ETS command arbiter. */
2396 #define PBF_REG_COS2_WEIGHT_P1                                   0x15c2c8
2397 /* [RW 31] The weight of COS3 in port 0 ETS command arbiter. */
2398 #define PBF_REG_COS3_WEIGHT_P0                                   0x15c2b4
2399 /* [RW 31] The weight of COS4 in port 0 ETS command arbiter. */
2400 #define PBF_REG_COS4_WEIGHT_P0                                   0x15c2b8
2401 /* [RW 31] The weight of COS5 in port 0 ETS command arbiter. */
2402 #define PBF_REG_COS5_WEIGHT_P0                                   0x15c2bc
2403 /* [R 11] Current credit for the LB queue in the tx port buffers in 16 byte
2404  * lines. */
2405 #define PBF_REG_CREDIT_LB_Q                                      0x140338
2406 /* [R 11] Current credit for queue 0 in the tx port buffers in 16 byte
2407  * lines. */
2408 #define PBF_REG_CREDIT_Q0                                        0x14033c
2409 /* [R 11] Current credit for queue 1 in the tx port buffers in 16 byte
2410  * lines. */
2411 #define PBF_REG_CREDIT_Q1                                        0x140340
2412 /* [RW 1] Disable processing further tasks from port 0 (after ending the
2413    current task in process). */
2414 #define PBF_REG_DISABLE_NEW_TASK_PROC_P0                         0x14005c
2415 /* [RW 1] Disable processing further tasks from port 1 (after ending the
2416    current task in process). */
2417 #define PBF_REG_DISABLE_NEW_TASK_PROC_P1                         0x140060
2418 /* [RW 1] Disable processing further tasks from port 4 (after ending the
2419    current task in process). */
2420 #define PBF_REG_DISABLE_NEW_TASK_PROC_P4                         0x14006c
2421 #define PBF_REG_DISABLE_PF                                       0x1402e8
2422 /* [RW 18] For port 0: For each client that is subject to WFQ (the
2423  * corresponding bit is 1); indicates to which of the credit registers this
2424  * client is mapped. For clients which are not credit blocked; their mapping
2425  * is dont care. */
2426 #define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0                     0x15c288
2427 /* [RW 9] For port 1: For each client that is subject to WFQ (the
2428  * corresponding bit is 1); indicates to which of the credit registers this
2429  * client is mapped. For clients which are not credit blocked; their mapping
2430  * is dont care. */
2431 #define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1                     0x15c28c
2432 /* [RW 6] For port 0: Bit per client to indicate if the client competes in
2433  * the strict priority arbiter directly (corresponding bit = 1); or first
2434  * goes to the RR arbiter (corresponding bit = 0); and then competes in the
2435  * lowest priority in the strict-priority arbiter. */
2436 #define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0                      0x15c278
2437 /* [RW 3] For port 1: Bit per client to indicate if the client competes in
2438  * the strict priority arbiter directly (corresponding bit = 1); or first
2439  * goes to the RR arbiter (corresponding bit = 0); and then competes in the
2440  * lowest priority in the strict-priority arbiter. */
2441 #define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1                      0x15c27c
2442 /* [RW 6] For port 0: Bit per client to indicate if the client is subject to
2443  * WFQ credit blocking (corresponding bit = 1). */
2444 #define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0                 0x15c280
2445 /* [RW 3] For port 0: Bit per client to indicate if the client is subject to
2446  * WFQ credit blocking (corresponding bit = 1). */
2447 #define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1                 0x15c284
2448 /* [RW 16] For port 0: The number of strict priority arbitration slots
2449  * between 2 RR arbitration slots. A value of 0 means no strict priority
2450  * cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR
2451  * arbiter. */
2452 #define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0                  0x15c2a0
2453 /* [RW 16] For port 1: The number of strict priority arbitration slots
2454  * between 2 RR arbitration slots. A value of 0 means no strict priority
2455  * cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR
2456  * arbiter. */
2457 #define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1                  0x15c2a4
2458 /* [RW 18] For port 0: Indicates which client is connected to each priority
2459  * in the strict-priority arbiter. Priority 0 is the highest priority, and
2460  * priority 5 is the lowest; to which the RR output is connected to (this is
2461  * not configurable). */
2462 #define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0                       0x15c270
2463 /* [RW 9] For port 1: Indicates which client is connected to each priority
2464  * in the strict-priority arbiter. Priority 0 is the highest priority, and
2465  * priority 5 is the lowest; to which the RR output is connected to (this is
2466  * not configurable). */
2467 #define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1                       0x15c274
2468 /* [RW 1] Indicates that ETS is performed between the COSes in the command
2469  * arbiter. If reset strict priority w/ anti-starvation will be performed
2470  * w/o WFQ. */
2471 #define PBF_REG_ETS_ENABLED                                      0x15c050
2472 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2473  * Ethernet header. */
2474 #define PBF_REG_HDRS_AFTER_BASIC                                 0x15c0a8
2475 /* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */
2476 #define PBF_REG_HDRS_AFTER_TAG_0                                 0x15c0b8
2477 /* [R 1] Removed for E3 B0 - Indicates which COS is conncted to the highest
2478  * priority in the command arbiter. */
2479 #define PBF_REG_HIGH_PRIORITY_COS_NUM                            0x15c04c
2480 #define PBF_REG_IF_ENABLE_REG                                    0x140044
2481 /* [RW 1] Init bit. When set the initial credits are copied to the credit
2482    registers (except the port credits). Should be set and then reset after
2483    the configuration of the block has ended. */
2484 #define PBF_REG_INIT                                             0x140000
2485 /* [RW 11] Initial credit for the LB queue in the tx port buffers in 16 byte
2486  * lines. */
2487 #define PBF_REG_INIT_CRD_LB_Q                                    0x15c248
2488 /* [RW 11] Initial credit for queue 0 in the tx port buffers in 16 byte
2489  * lines. */
2490 #define PBF_REG_INIT_CRD_Q0                                      0x15c230
2491 /* [RW 11] Initial credit for queue 1 in the tx port buffers in 16 byte
2492  * lines. */
2493 #define PBF_REG_INIT_CRD_Q1                                      0x15c234
2494 /* [RW 1] Init bit for port 0. When set the initial credit of port 0 is
2495    copied to the credit register. Should be set and then reset after the
2496    configuration of the port has ended. */
2497 #define PBF_REG_INIT_P0                                          0x140004
2498 /* [RW 1] Init bit for port 1. When set the initial credit of port 1 is
2499    copied to the credit register. Should be set and then reset after the
2500    configuration of the port has ended. */
2501 #define PBF_REG_INIT_P1                                          0x140008
2502 /* [RW 1] Init bit for port 4. When set the initial credit of port 4 is
2503    copied to the credit register. Should be set and then reset after the
2504    configuration of the port has ended. */
2505 #define PBF_REG_INIT_P4                                          0x14000c
2506 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2507  * the LB queue. Reset upon init. */
2508 #define PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q                      0x140354
2509 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2510  * queue 0. Reset upon init. */
2511 #define PBF_REG_INTERNAL_CRD_FREED_CNT_Q0                        0x140358
2512 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2513  * queue 1. Reset upon init. */
2514 #define PBF_REG_INTERNAL_CRD_FREED_CNT_Q1                        0x14035c
2515 /* [RW 1] Enable for mac interface 0. */
2516 #define PBF_REG_MAC_IF0_ENABLE                                   0x140030
2517 /* [RW 1] Enable for mac interface 1. */
2518 #define PBF_REG_MAC_IF1_ENABLE                                   0x140034
2519 /* [RW 1] Enable for the loopback interface. */
2520 #define PBF_REG_MAC_LB_ENABLE                                    0x140040
2521 /* [RW 6] Bit-map indicating which headers must appear in the packet */
2522 #define PBF_REG_MUST_HAVE_HDRS                                   0x15c0c4
2523 /* [RW 16] The number of strict priority arbitration slots between 2 RR
2524  * arbitration slots. A value of 0 means no strict priority cycles; i.e. the
2525  * strict-priority w/ anti-starvation arbiter is a RR arbiter. */
2526 #define PBF_REG_NUM_STRICT_ARB_SLOTS                             0x15c064
2527 /* [RW 10] Port 0 threshold used by arbiter in 16 byte lines used when pause
2528    not suppoterd. */
2529 #define PBF_REG_P0_ARB_THRSH                                     0x1400e4
2530 /* [R 11] Current credit for port 0 in the tx port buffers in 16 byte lines. */
2531 #define PBF_REG_P0_CREDIT                                        0x140200
2532 /* [RW 11] Initial credit for port 0 in the tx port buffers in 16 byte
2533    lines. */
2534 #define PBF_REG_P0_INIT_CRD                                      0x1400d0
2535 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2536  * port 0. Reset upon init. */
2537 #define PBF_REG_P0_INTERNAL_CRD_FREED_CNT                        0x140308
2538 /* [R 1] Removed for E3 B0 - Indication that pause is enabled for port 0. */
2539 #define PBF_REG_P0_PAUSE_ENABLE                                  0x140014
2540 /* [R 8] Removed for E3 B0 - Number of tasks in port 0 task queue. */
2541 #define PBF_REG_P0_TASK_CNT                                      0x140204
2542 /* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
2543  * freed from the task queue of port 0. Reset upon init. */
2544 #define PBF_REG_P0_TQ_LINES_FREED_CNT                            0x1402f0
2545 /* [R 12] Number of 8 bytes lines occupied in the task queue of port 0. */
2546 #define PBF_REG_P0_TQ_OCCUPANCY                                  0x1402fc
2547 /* [R 11] Removed for E3 B0 - Current credit for port 1 in the tx port
2548  * buffers in 16 byte lines. */
2549 #define PBF_REG_P1_CREDIT                                        0x140208
2550 /* [R 11] Removed for E3 B0 - Initial credit for port 0 in the tx port
2551  * buffers in 16 byte lines. */
2552 #define PBF_REG_P1_INIT_CRD                                      0x1400d4
2553 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2554  * port 1. Reset upon init. */
2555 #define PBF_REG_P1_INTERNAL_CRD_FREED_CNT                        0x14030c
2556 /* [R 8] Removed for E3 B0 - Number of tasks in port 1 task queue. */
2557 #define PBF_REG_P1_TASK_CNT                                      0x14020c
2558 /* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
2559  * freed from the task queue of port 1. Reset upon init. */
2560 #define PBF_REG_P1_TQ_LINES_FREED_CNT                            0x1402f4
2561 /* [R 12] Number of 8 bytes lines occupied in the task queue of port 1. */
2562 #define PBF_REG_P1_TQ_OCCUPANCY                                  0x140300
2563 /* [R 11] Current credit for port 4 in the tx port buffers in 16 byte lines. */
2564 #define PBF_REG_P4_CREDIT                                        0x140210
2565 /* [RW 11] Initial credit for port 4 in the tx port buffers in 16 byte
2566    lines. */
2567 #define PBF_REG_P4_INIT_CRD                                      0x1400e0
2568 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2569  * port 4. Reset upon init. */
2570 #define PBF_REG_P4_INTERNAL_CRD_FREED_CNT                        0x140310
2571 /* [R 8] Removed for E3 B0 - Number of tasks in port 4 task queue. */
2572 #define PBF_REG_P4_TASK_CNT                                      0x140214
2573 /* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
2574  * freed from the task queue of port 4. Reset upon init. */
2575 #define PBF_REG_P4_TQ_LINES_FREED_CNT                            0x1402f8
2576 /* [R 12] Number of 8 bytes lines occupied in the task queue of port 4. */
2577 #define PBF_REG_P4_TQ_OCCUPANCY                                  0x140304
2578 /* [RW 5] Interrupt mask register #0 read/write */
2579 #define PBF_REG_PBF_INT_MASK                                     0x1401d4
2580 /* [R 5] Interrupt register #0 read */
2581 #define PBF_REG_PBF_INT_STS                                      0x1401c8
2582 /* [RW 20] Parity mask register #0 read/write */
2583 #define PBF_REG_PBF_PRTY_MASK                                    0x1401e4
2584 /* [RC 20] Parity register #0 read clear */
2585 #define PBF_REG_PBF_PRTY_STS_CLR                                 0x1401dc
2586 /* [RW 16] The Ethernet type value for L2 tag 0 */
2587 #define PBF_REG_TAG_ETHERTYPE_0                                  0x15c090
2588 /* [RW 4] The length of the info field for L2 tag 0. The length is between
2589  * 2B and 14B; in 2B granularity */
2590 #define PBF_REG_TAG_LEN_0                                        0x15c09c
2591 /* [R 32] Cyclic counter for number of 8 byte lines freed from the LB task
2592  * queue. Reset upon init. */
2593 #define PBF_REG_TQ_LINES_FREED_CNT_LB_Q                          0x14038c
2594 /* [R 32] Cyclic counter for number of 8 byte lines freed from the task
2595  * queue 0. Reset upon init. */
2596 #define PBF_REG_TQ_LINES_FREED_CNT_Q0                            0x140390
2597 /* [R 32] Cyclic counter for number of 8 byte lines freed from task queue 1.
2598  * Reset upon init. */
2599 #define PBF_REG_TQ_LINES_FREED_CNT_Q1                            0x140394
2600 /* [R 13] Number of 8 bytes lines occupied in the task queue of the LB
2601  * queue. */
2602 #define PBF_REG_TQ_OCCUPANCY_LB_Q                                0x1403a8
2603 /* [R 13] Number of 8 bytes lines occupied in the task queue of queue 0. */
2604 #define PBF_REG_TQ_OCCUPANCY_Q0                                  0x1403ac
2605 /* [R 13] Number of 8 bytes lines occupied in the task queue of queue 1. */
2606 #define PBF_REG_TQ_OCCUPANCY_Q1                                  0x1403b0
2607 #define PB_REG_CONTROL                                           0
2608 /* [RW 2] Interrupt mask register #0 read/write */
2609 #define PB_REG_PB_INT_MASK                                       0x28
2610 /* [R 2] Interrupt register #0 read */
2611 #define PB_REG_PB_INT_STS                                        0x1c
2612 /* [RW 4] Parity mask register #0 read/write */
2613 #define PB_REG_PB_PRTY_MASK                                      0x38
2614 /* [R 4] Parity register #0 read */
2615 #define PB_REG_PB_PRTY_STS                                       0x2c
2616 /* [RC 4] Parity register #0 read clear */
2617 #define PB_REG_PB_PRTY_STS_CLR                                   0x30
2618 #define PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR                (0x1<<0)
2619 #define PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW        (0x1<<8)
2620 #define PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR       (0x1<<1)
2621 #define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN              (0x1<<6)
2622 #define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN        (0x1<<7)
2623 #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN  (0x1<<4)
2624 #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN     (0x1<<3)
2625 #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN   (0x1<<5)
2626 #define PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN               (0x1<<2)
2627 /* [R 8] Config space A attention dirty bits. Each bit indicates that the
2628  * corresponding PF generates config space A attention. Set by PXP. Reset by
2629  * MCP writing 1 to icfg_space_a_request_clr. Note: register contains bits
2630  * from both paths. */
2631 #define PGLUE_B_REG_CFG_SPACE_A_REQUEST                  0x9010
2632 /* [R 8] Config space B attention dirty bits. Each bit indicates that the
2633  * corresponding PF generates config space B attention. Set by PXP. Reset by
2634  * MCP writing 1 to icfg_space_b_request_clr. Note: register contains bits
2635  * from both paths. */
2636 #define PGLUE_B_REG_CFG_SPACE_B_REQUEST                  0x9014
2637 /* [RW 1] Type A PF enable inbound interrupt table for CSDM. 0 - disable; 1
2638  * - enable. */
2639 #define PGLUE_B_REG_CSDM_INB_INT_A_PF_ENABLE                     0x9194
2640 /* [RW 18] Type B VF inbound interrupt table for CSDM: bits[17:9]-mask;
2641  * its[8:0]-address. Bits [1:0] must be zero (DW resolution address). */
2642 #define PGLUE_B_REG_CSDM_INB_INT_B_VF                            0x916c
2643 /* [RW 1] Type B VF enable inbound interrupt table for CSDM. 0 - disable; 1
2644  * - enable. */
2645 #define PGLUE_B_REG_CSDM_INB_INT_B_VF_ENABLE                     0x919c
2646 /* [RW 16] Start offset of CSDM zone A (queue zone) in the internal RAM */
2647 #define PGLUE_B_REG_CSDM_START_OFFSET_A                  0x9100
2648 /* [RW 16] Start offset of CSDM zone B (legacy zone) in the internal RAM */
2649 #define PGLUE_B_REG_CSDM_START_OFFSET_B                  0x9108
2650 /* [RW 5] VF Shift of CSDM zone B (legacy zone) in the internal RAM */
2651 #define PGLUE_B_REG_CSDM_VF_SHIFT_B                              0x9110
2652 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
2653 #define PGLUE_B_REG_CSDM_ZONE_A_SIZE_PF                  0x91ac
2654 /* [R 8] FLR request attention dirty bits for PFs 0 to 7. Each bit indicates
2655  * that the FLR register of the corresponding PF was set. Set by PXP. Reset
2656  * by MCP writing 1 to flr_request_pf_7_0_clr. Note: register contains bits
2657  * from both paths. */
2658 #define PGLUE_B_REG_FLR_REQUEST_PF_7_0                           0x9028
2659 /* [W 8] FLR request attention dirty bits clear for PFs 0 to 7. MCP writes 1
2660  * to a bit in this register in order to clear the corresponding bit in
2661  * flr_request_pf_7_0 register. Note: register contains bits from both
2662  * paths. */
2663 #define PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR                       0x9418
2664 /* [R 32] FLR request attention dirty bits for VFs 96 to 127. Each bit
2665  * indicates that the FLR register of the corresponding VF was set. Set by
2666  * PXP. Reset by MCP writing 1 to flr_request_vf_127_96_clr. */
2667 #define PGLUE_B_REG_FLR_REQUEST_VF_127_96                        0x9024
2668 /* [R 32] FLR request attention dirty bits for VFs 0 to 31. Each bit
2669  * indicates that the FLR register of the corresponding VF was set. Set by
2670  * PXP. Reset by MCP writing 1 to flr_request_vf_31_0_clr. */
2671 #define PGLUE_B_REG_FLR_REQUEST_VF_31_0                  0x9018
2672 /* [R 32] FLR request attention dirty bits for VFs 32 to 63. Each bit
2673  * indicates that the FLR register of the corresponding VF was set. Set by
2674  * PXP. Reset by MCP writing 1 to flr_request_vf_63_32_clr. */
2675 #define PGLUE_B_REG_FLR_REQUEST_VF_63_32                         0x901c
2676 /* [R 32] FLR request attention dirty bits for VFs 64 to 95. Each bit
2677  * indicates that the FLR register of the corresponding VF was set. Set by
2678  * PXP. Reset by MCP writing 1 to flr_request_vf_95_64_clr. */
2679 #define PGLUE_B_REG_FLR_REQUEST_VF_95_64                         0x9020
2680 /* [R 8] Each bit indicates an incorrect behavior in user RX interface. Bit
2681  * 0 - Target memory read arrived with a correctable error. Bit 1 - Target
2682  * memory read arrived with an uncorrectable error. Bit 2 - Configuration RW
2683  * arrived with a correctable error. Bit 3 - Configuration RW arrived with
2684  * an uncorrectable error. Bit 4 - Completion with Configuration Request
2685  * Retry Status. Bit 5 - Expansion ROM access received with a write request.
2686  * Bit 6 - Completion with pcie_rx_err of 0000; CMPL_STATUS of non-zero; and
2687  * pcie_rx_last not asserted. Bit 7 - Completion with pcie_rx_err of 1010;
2688  * and pcie_rx_last not asserted. */
2689 #define PGLUE_B_REG_INCORRECT_RCV_DETAILS                        0x9068
2690 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER          0x942c
2691 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ             0x9430
2692 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_WRITE            0x9434
2693 #define PGLUE_B_REG_INTERNAL_VFID_ENABLE                         0x9438
2694 /* [R 9] Interrupt register #0 read */
2695 #define PGLUE_B_REG_PGLUE_B_INT_STS                              0x9298
2696 /* [RC 9] Interrupt register #0 read clear */
2697 #define PGLUE_B_REG_PGLUE_B_INT_STS_CLR                  0x929c
2698 /* [RW 2] Parity mask register #0 read/write */
2699 #define PGLUE_B_REG_PGLUE_B_PRTY_MASK                            0x92b4
2700 /* [R 2] Parity register #0 read */
2701 #define PGLUE_B_REG_PGLUE_B_PRTY_STS                             0x92a8
2702 /* [RC 2] Parity register #0 read clear */
2703 #define PGLUE_B_REG_PGLUE_B_PRTY_STS_CLR                         0x92ac
2704 /* [R 13] Details of first request received with error. [2:0] - PFID. [3] -
2705  * VF_VALID. [9:4] - VFID. [11:10] - Error Code - 0 - Indicates Completion
2706  * Timeout of a User Tx non-posted request. 1 - unsupported request. 2 -
2707  * completer abort. 3 - Illegal value for this field. [12] valid - indicates
2708  * if there was a completion error since the last time this register was
2709  * cleared. */
2710 #define PGLUE_B_REG_RX_ERR_DETAILS                               0x9080
2711 /* [R 18] Details of first ATS Translation Completion request received with
2712  * error. [2:0] - PFID. [3] - VF_VALID. [9:4] - VFID. [11:10] - Error Code -
2713  * 0 - Indicates Completion Timeout of a User Tx non-posted request. 1 -
2714  * unsupported request. 2 - completer abort. 3 - Illegal value for this
2715  * field. [16:12] - ATC OTB EntryID. [17] valid - indicates if there was a
2716  * completion error since the last time this register was cleared. */
2717 #define PGLUE_B_REG_RX_TCPL_ERR_DETAILS                  0x9084
2718 /* [W 8] Debug only - Shadow BME bits clear for PFs 0 to 7. MCP writes 1 to
2719  * a bit in this register in order to clear the corresponding bit in
2720  * shadow_bme_pf_7_0 register. MCP should never use this unless a
2721  * work-around is needed. Note: register contains bits from both paths. */
2722 #define PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR                        0x9458
2723 /* [R 8] SR IOV disabled attention dirty bits. Each bit indicates that the
2724  * VF enable register of the corresponding PF is written to 0 and was
2725  * previously 1. Set by PXP. Reset by MCP writing 1 to
2726  * sr_iov_disabled_request_clr. Note: register contains bits from both
2727  * paths. */
2728 #define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST                      0x9030
2729 /* [R 32] Indicates the status of tags 32-63. 0 - tags is used - read
2730  * completion did not return yet. 1 - tag is unused. Same functionality as
2731  * pxp2_registers_pgl_exp_rom_data2 for tags 0-31. */
2732 #define PGLUE_B_REG_TAGS_63_32                                   0x9244
2733 /* [RW 1] Type A PF enable inbound interrupt table for TSDM. 0 - disable; 1
2734  * - enable. */
2735 #define PGLUE_B_REG_TSDM_INB_INT_A_PF_ENABLE                     0x9170
2736 /* [RW 16] Start offset of TSDM zone A (queue zone) in the internal RAM */
2737 #define PGLUE_B_REG_TSDM_START_OFFSET_A                  0x90c4
2738 /* [RW 16] Start offset of TSDM zone B (legacy zone) in the internal RAM */
2739 #define PGLUE_B_REG_TSDM_START_OFFSET_B                  0x90cc
2740 /* [RW 5] VF Shift of TSDM zone B (legacy zone) in the internal RAM */
2741 #define PGLUE_B_REG_TSDM_VF_SHIFT_B                              0x90d4
2742 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
2743 #define PGLUE_B_REG_TSDM_ZONE_A_SIZE_PF                  0x91a0
2744 /* [R 32] Address [31:0] of first read request not submitted due to error */
2745 #define PGLUE_B_REG_TX_ERR_RD_ADD_31_0                           0x9098
2746 /* [R 32] Address [63:32] of first read request not submitted due to error */
2747 #define PGLUE_B_REG_TX_ERR_RD_ADD_63_32                  0x909c
2748 /* [R 31] Details of first read request not submitted due to error. [4:0]
2749  * VQID. [5] TREQ. 1 - Indicates the request is a Translation Request.
2750  * [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25] -
2751  * VFID. */
2752 #define PGLUE_B_REG_TX_ERR_RD_DETAILS                            0x90a0
2753 /* [R 26] Details of first read request not submitted due to error. [15:0]
2754  * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type -
2755  * [21] - Indicates was_error was set; [22] - Indicates BME was cleared;
2756  * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent
2757  * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid -
2758  * indicates if there was a request not submitted due to error since the
2759  * last time this register was cleared. */
2760 #define PGLUE_B_REG_TX_ERR_RD_DETAILS2                           0x90a4
2761 /* [R 32] Address [31:0] of first write request not submitted due to error */
2762 #define PGLUE_B_REG_TX_ERR_WR_ADD_31_0                           0x9088
2763 /* [R 32] Address [63:32] of first write request not submitted due to error */
2764 #define PGLUE_B_REG_TX_ERR_WR_ADD_63_32                  0x908c
2765 /* [R 31] Details of first write request not submitted due to error. [4:0]
2766  * VQID. [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25]
2767  * - VFID. */
2768 #define PGLUE_B_REG_TX_ERR_WR_DETAILS                            0x9090
2769 /* [R 26] Details of first write request not submitted due to error. [15:0]
2770  * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type -
2771  * [21] - Indicates was_error was set; [22] - Indicates BME was cleared;
2772  * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent
2773  * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid -
2774  * indicates if there was a request not submitted due to error since the
2775  * last time this register was cleared. */
2776 #define PGLUE_B_REG_TX_ERR_WR_DETAILS2                           0x9094
2777 /* [RW 10] Type A PF/VF inbound interrupt table for USDM: bits[9:5]-mask;
2778  * its[4:0]-address relative to start_offset_a. Bits [1:0] can have any
2779  * value (Byte resolution address). */
2780 #define PGLUE_B_REG_USDM_INB_INT_A_0                             0x9128
2781 #define PGLUE_B_REG_USDM_INB_INT_A_1                             0x912c
2782 #define PGLUE_B_REG_USDM_INB_INT_A_2                             0x9130
2783 #define PGLUE_B_REG_USDM_INB_INT_A_3                             0x9134
2784 #define PGLUE_B_REG_USDM_INB_INT_A_4                             0x9138
2785 #define PGLUE_B_REG_USDM_INB_INT_A_5                             0x913c
2786 #define PGLUE_B_REG_USDM_INB_INT_A_6                             0x9140
2787 /* [RW 1] Type A PF enable inbound interrupt table for USDM. 0 - disable; 1
2788  * - enable. */
2789 #define PGLUE_B_REG_USDM_INB_INT_A_PF_ENABLE                     0x917c
2790 /* [RW 1] Type A VF enable inbound interrupt table for USDM. 0 - disable; 1
2791  * - enable. */
2792 #define PGLUE_B_REG_USDM_INB_INT_A_VF_ENABLE                     0x9180
2793 /* [RW 1] Type B VF enable inbound interrupt table for USDM. 0 - disable; 1
2794  * - enable. */
2795 #define PGLUE_B_REG_USDM_INB_INT_B_VF_ENABLE                     0x9184
2796 /* [RW 16] Start offset of USDM zone A (queue zone) in the internal RAM */
2797 #define PGLUE_B_REG_USDM_START_OFFSET_A                  0x90d8
2798 /* [RW 16] Start offset of USDM zone B (legacy zone) in the internal RAM */
2799 #define PGLUE_B_REG_USDM_START_OFFSET_B                  0x90e0
2800 /* [RW 5] VF Shift of USDM zone B (legacy zone) in the internal RAM */
2801 #define PGLUE_B_REG_USDM_VF_SHIFT_B                              0x90e8
2802 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
2803 #define PGLUE_B_REG_USDM_ZONE_A_SIZE_PF                  0x91a4
2804 /* [R 26] Details of first target VF request accessing VF GRC space that
2805  * failed permission check. [14:0] Address. [15] w_nr: 0 - Read; 1 - Write.
2806  * [21:16] VFID. [24:22] - PFID. [25] valid - indicates if there was a
2807  * request accessing VF GRC space that failed permission check since the
2808  * last time this register was cleared. Permission checks are: function
2809  * permission; R/W permission; address range permission. */
2810 #define PGLUE_B_REG_VF_GRC_SPACE_VIOLATION_DETAILS               0x9234
2811 /* [R 31] Details of first target VF request with length violation (too many
2812  * DWs) accessing BAR0. [12:0] Address in DWs (bits [14:2] of byte address).
2813  * [14:13] BAR. [20:15] VFID. [23:21] - PFID. [29:24] - Length in DWs. [30]
2814  * valid - indicates if there was a request with length violation since the
2815  * last time this register was cleared. Length violations: length of more
2816  * than 2DWs; length of 2DWs and address not QW aligned; window is GRC and
2817  * length is more than 1 DW. */
2818 #define PGLUE_B_REG_VF_LENGTH_VIOLATION_DETAILS          0x9230
2819 /* [R 8] Was_error indication dirty bits for PFs 0 to 7. Each bit indicates
2820  * that there was a completion with uncorrectable error for the
2821  * corresponding PF. Set by PXP. Reset by MCP writing 1 to
2822  * was_error_pf_7_0_clr. */
2823 #define PGLUE_B_REG_WAS_ERROR_PF_7_0                             0x907c
2824 /* [W 8] Was_error indication dirty bits clear for PFs 0 to 7. MCP writes 1
2825  * to a bit in this register in order to clear the corresponding bit in
2826  * flr_request_pf_7_0 register. */
2827 #define PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR                         0x9470
2828 /* [R 32] Was_error indication dirty bits for VFs 96 to 127. Each bit
2829  * indicates that there was a completion with uncorrectable error for the
2830  * corresponding VF. Set by PXP. Reset by MCP writing 1 to
2831  * was_error_vf_127_96_clr. */
2832 #define PGLUE_B_REG_WAS_ERROR_VF_127_96                  0x9078
2833 /* [W 32] Was_error indication dirty bits clear for VFs 96 to 127. MCP
2834  * writes 1 to a bit in this register in order to clear the corresponding
2835  * bit in was_error_vf_127_96 register. */
2836 #define PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR                      0x9474
2837 /* [R 32] Was_error indication dirty bits for VFs 0 to 31. Each bit
2838  * indicates that there was a completion with uncorrectable error for the
2839  * corresponding VF. Set by PXP. Reset by MCP writing 1 to
2840  * was_error_vf_31_0_clr. */
2841 #define PGLUE_B_REG_WAS_ERROR_VF_31_0                            0x906c
2842 /* [W 32] Was_error indication dirty bits clear for VFs 0 to 31. MCP writes
2843  * 1 to a bit in this register in order to clear the corresponding bit in
2844  * was_error_vf_31_0 register. */
2845 #define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR                        0x9478
2846 /* [R 32] Was_error indication dirty bits for VFs 32 to 63. Each bit
2847  * indicates that there was a completion with uncorrectable error for the
2848  * corresponding VF. Set by PXP. Reset by MCP writing 1 to
2849  * was_error_vf_63_32_clr. */
2850 #define PGLUE_B_REG_WAS_ERROR_VF_63_32                           0x9070
2851 /* [W 32] Was_error indication dirty bits clear for VFs 32 to 63. MCP writes
2852  * 1 to a bit in this register in order to clear the corresponding bit in
2853  * was_error_vf_63_32 register. */
2854 #define PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR                       0x947c
2855 /* [R 32] Was_error indication dirty bits for VFs 64 to 95. Each bit
2856  * indicates that there was a completion with uncorrectable error for the
2857  * corresponding VF. Set by PXP. Reset by MCP writing 1 to
2858  * was_error_vf_95_64_clr. */
2859 #define PGLUE_B_REG_WAS_ERROR_VF_95_64                           0x9074
2860 /* [W 32] Was_error indication dirty bits clear for VFs 64 to 95. MCP writes
2861  * 1 to a bit in this register in order to clear the corresponding bit in
2862  * was_error_vf_95_64 register. */
2863 #define PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR                       0x9480
2864 /* [RW 1] Type A PF enable inbound interrupt table for XSDM. 0 - disable; 1
2865  * - enable. */
2866 #define PGLUE_B_REG_XSDM_INB_INT_A_PF_ENABLE                     0x9188
2867 /* [RW 16] Start offset of XSDM zone A (queue zone) in the internal RAM */
2868 #define PGLUE_B_REG_XSDM_START_OFFSET_A                  0x90ec
2869 /* [RW 16] Start offset of XSDM zone B (legacy zone) in the internal RAM */
2870 #define PGLUE_B_REG_XSDM_START_OFFSET_B                  0x90f4
2871 /* [RW 5] VF Shift of XSDM zone B (legacy zone) in the internal RAM */
2872 #define PGLUE_B_REG_XSDM_VF_SHIFT_B                              0x90fc
2873 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
2874 #define PGLUE_B_REG_XSDM_ZONE_A_SIZE_PF                  0x91a8
2875 #define PRS_REG_A_PRSU_20                                        0x40134
2876 /* [R 8] debug only: CFC load request current credit. Transaction based. */
2877 #define PRS_REG_CFC_LD_CURRENT_CREDIT                            0x40164
2878 /* [R 8] debug only: CFC search request current credit. Transaction based. */
2879 #define PRS_REG_CFC_SEARCH_CURRENT_CREDIT                        0x40168
2880 /* [RW 6] The initial credit for the search message to the CFC interface.
2881    Credit is transaction based. */
2882 #define PRS_REG_CFC_SEARCH_INITIAL_CREDIT                        0x4011c
2883 /* [RW 24] CID for port 0 if no match */
2884 #define PRS_REG_CID_PORT_0                                       0x400fc
2885 /* [RW 32] The CM header for flush message where 'load existed' bit in CFC
2886    load response is reset and packet type is 0. Used in packet start message
2887    to TCM. */
2888 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0                         0x400dc
2889 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1                         0x400e0
2890 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2                         0x400e4
2891 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3                         0x400e8
2892 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4                         0x400ec
2893 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_5                         0x400f0
2894 /* [RW 32] The CM header for flush message where 'load existed' bit in CFC
2895    load response is set and packet type is 0. Used in packet start message
2896    to TCM. */
2897 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0                      0x400bc
2898 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1                      0x400c0
2899 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2                      0x400c4
2900 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3                      0x400c8
2901 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4                      0x400cc
2902 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_5                      0x400d0
2903 /* [RW 32] The CM header for a match and packet type 1 for loopback port.
2904    Used in packet start message to TCM. */
2905 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_1                           0x4009c
2906 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_2                           0x400a0
2907 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_3                           0x400a4
2908 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_4                           0x400a8
2909 /* [RW 32] The CM header for a match and packet type 0. Used in packet start
2910    message to TCM. */
2911 #define PRS_REG_CM_HDR_TYPE_0                                    0x40078
2912 #define PRS_REG_CM_HDR_TYPE_1                                    0x4007c
2913 #define PRS_REG_CM_HDR_TYPE_2                                    0x40080
2914 #define PRS_REG_CM_HDR_TYPE_3                                    0x40084
2915 #define PRS_REG_CM_HDR_TYPE_4                                    0x40088
2916 /* [RW 32] The CM header in case there was not a match on the connection */
2917 #define PRS_REG_CM_NO_MATCH_HDR                                  0x400b8
2918 /* [RW 1] Indicates if in e1hov mode. 0=non-e1hov mode; 1=e1hov mode. */
2919 #define PRS_REG_E1HOV_MODE                                       0x401c8
2920 /* [RW 8] The 8-bit event ID for a match and packet type 1. Used in packet
2921    start message to TCM. */
2922 #define PRS_REG_EVENT_ID_1                                       0x40054
2923 #define PRS_REG_EVENT_ID_2                                       0x40058
2924 #define PRS_REG_EVENT_ID_3                                       0x4005c
2925 /* [RW 16] The Ethernet type value for FCoE */
2926 #define PRS_REG_FCOE_TYPE                                        0x401d0
2927 /* [RW 8] Context region for flush packet with packet type 0. Used in CFC
2928    load request message. */
2929 #define PRS_REG_FLUSH_REGIONS_TYPE_0                             0x40004
2930 #define PRS_REG_FLUSH_REGIONS_TYPE_1                             0x40008
2931 #define PRS_REG_FLUSH_REGIONS_TYPE_2                             0x4000c
2932 #define PRS_REG_FLUSH_REGIONS_TYPE_3                             0x40010
2933 #define PRS_REG_FLUSH_REGIONS_TYPE_4                             0x40014
2934 #define PRS_REG_FLUSH_REGIONS_TYPE_5                             0x40018
2935 #define PRS_REG_FLUSH_REGIONS_TYPE_6                             0x4001c
2936 #define PRS_REG_FLUSH_REGIONS_TYPE_7                             0x40020
2937 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2938  * Ethernet header. */
2939 #define PRS_REG_HDRS_AFTER_BASIC                                 0x40238
2940 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2941  * Ethernet header for port 0 packets. */
2942 #define PRS_REG_HDRS_AFTER_BASIC_PORT_0                          0x40270
2943 #define PRS_REG_HDRS_AFTER_BASIC_PORT_1                          0x40290
2944 /* [R 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */
2945 #define PRS_REG_HDRS_AFTER_TAG_0                                 0x40248
2946 /* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 for
2947  * port 0 packets */
2948 #define PRS_REG_HDRS_AFTER_TAG_0_PORT_0                          0x40280
2949 #define PRS_REG_HDRS_AFTER_TAG_0_PORT_1                          0x402a0
2950 /* [RW 4] The increment value to send in the CFC load request message */
2951 #define PRS_REG_INC_VALUE                                        0x40048
2952 /* [RW 6] Bit-map indicating which headers must appear in the packet */
2953 #define PRS_REG_MUST_HAVE_HDRS                                   0x40254
2954 /* [RW 6] Bit-map indicating which headers must appear in the packet for
2955  * port 0 packets */
2956 #define PRS_REG_MUST_HAVE_HDRS_PORT_0                            0x4028c
2957 #define PRS_REG_MUST_HAVE_HDRS_PORT_1                            0x402ac
2958 #define PRS_REG_NIC_MODE                                         0x40138
2959 /* [RW 8] The 8-bit event ID for cases where there is no match on the
2960    connection. Used in packet start message to TCM. */
2961 #define PRS_REG_NO_MATCH_EVENT_ID                                0x40070
2962 /* [ST 24] The number of input CFC flush packets */
2963 #define PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES                        0x40128
2964 /* [ST 32] The number of cycles the Parser halted its operation since it
2965    could not allocate the next serial number */
2966 #define PRS_REG_NUM_OF_DEAD_CYCLES                               0x40130
2967 /* [ST 24] The number of input packets */
2968 #define PRS_REG_NUM_OF_PACKETS                                   0x40124
2969 /* [ST 24] The number of input transparent flush packets */
2970 #define PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES                0x4012c
2971 /* [RW 8] Context region for received Ethernet packet with a match and
2972    packet type 0. Used in CFC load request message */
2973 #define PRS_REG_PACKET_REGIONS_TYPE_0                            0x40028
2974 #define PRS_REG_PACKET_REGIONS_TYPE_1                            0x4002c
2975 #define PRS_REG_PACKET_REGIONS_TYPE_2                            0x40030
2976 #define PRS_REG_PACKET_REGIONS_TYPE_3                            0x40034
2977 #define PRS_REG_PACKET_REGIONS_TYPE_4                            0x40038
2978 #define PRS_REG_PACKET_REGIONS_TYPE_5                            0x4003c
2979 #define PRS_REG_PACKET_REGIONS_TYPE_6                            0x40040
2980 #define PRS_REG_PACKET_REGIONS_TYPE_7                            0x40044
2981 /* [R 2] debug only: Number of pending requests for CAC on port 0. */
2982 #define PRS_REG_PENDING_BRB_CAC0_RQ                              0x40174
2983 /* [R 2] debug only: Number of pending requests for header parsing. */
2984 #define PRS_REG_PENDING_BRB_PRS_RQ                               0x40170
2985 /* [R 1] Interrupt register #0 read */
2986 #define PRS_REG_PRS_INT_STS                                      0x40188
2987 /* [RW 8] Parity mask register #0 read/write */
2988 #define PRS_REG_PRS_PRTY_MASK                                    0x401a4
2989 /* [R 8] Parity register #0 read */
2990 #define PRS_REG_PRS_PRTY_STS                                     0x40198
2991 /* [RC 8] Parity register #0 read clear */
2992 #define PRS_REG_PRS_PRTY_STS_CLR                                 0x4019c
2993 /* [RW 8] Context region for pure acknowledge packets. Used in CFC load
2994    request message */
2995 #define PRS_REG_PURE_REGIONS                                     0x40024
2996 /* [R 32] debug only: Serial number status lsb 32 bits. '1' indicates this
2997    serail number was released by SDM but cannot be used because a previous
2998    serial number was not released. */
2999 #define PRS_REG_SERIAL_NUM_STATUS_LSB                            0x40154
3000 /* [R 32] debug only: Serial number status msb 32 bits. '1' indicates this
3001    serail number was released by SDM but cannot be used because a previous
3002    serial number was not released. */
3003 #define PRS_REG_SERIAL_NUM_STATUS_MSB                            0x40158
3004 /* [R 4] debug only: SRC current credit. Transaction based. */
3005 #define PRS_REG_SRC_CURRENT_CREDIT                               0x4016c
3006 /* [RW 16] The Ethernet type value for L2 tag 0 */
3007 #define PRS_REG_TAG_ETHERTYPE_0                                  0x401d4
3008 /* [RW 4] The length of the info field for L2 tag 0. The length is between
3009  * 2B and 14B; in 2B granularity */
3010 #define PRS_REG_TAG_LEN_0                                        0x4022c
3011 /* [R 8] debug only: TCM current credit. Cycle based. */
3012 #define PRS_REG_TCM_CURRENT_CREDIT                               0x40160
3013 /* [R 8] debug only: TSDM current credit. Transaction based. */
3014 #define PRS_REG_TSDM_CURRENT_CREDIT                              0x4015c
3015 #define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT                     (0x1<<19)
3016 #define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF                      (0x1<<20)
3017 #define PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN                   (0x1<<22)
3018 #define PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED                (0x1<<23)
3019 #define PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED               (0x1<<24)
3020 #define PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR               (0x1<<7)
3021 #define PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR           (0x1<<7)
3022 /* [R 6] Debug only: Number of used entries in the data FIFO */
3023 #define PXP2_REG_HST_DATA_FIFO_STATUS                            0x12047c
3024 /* [R 7] Debug only: Number of used entries in the header FIFO */
3025 #define PXP2_REG_HST_HEADER_FIFO_STATUS                          0x120478
3026 #define PXP2_REG_PGL_ADDR_88_F0                                  0x120534
3027 /* [R 32] GRC address for configuration access to PCIE config address 0x88.
3028  * any write to this PCIE address will cause a GRC write access to the
3029  * address that's in t this register */
3030 #define PXP2_REG_PGL_ADDR_88_F1                                  0x120544
3031 #define PXP2_REG_PGL_ADDR_8C_F0                                  0x120538
3032 /* [R 32] GRC address for configuration access to PCIE config address 0x8c.
3033  * any write to this PCIE address will cause a GRC write access to the
3034  * address that's in t this register */
3035 #define PXP2_REG_PGL_ADDR_8C_F1                                  0x120548
3036 #define PXP2_REG_PGL_ADDR_90_F0                                  0x12053c
3037 /* [R 32] GRC address for configuration access to PCIE config address 0x90.
3038  * any write to this PCIE address will cause a GRC write access to the
3039  * address that's in t this register */
3040 #define PXP2_REG_PGL_ADDR_90_F1                                  0x12054c
3041 #define PXP2_REG_PGL_ADDR_94_F0                                  0x120540
3042 /* [R 32] GRC address for configuration access to PCIE config address 0x94.
3043  * any write to this PCIE address will cause a GRC write access to the
3044  * address that's in t this register */
3045 #define PXP2_REG_PGL_ADDR_94_F1                                  0x120550
3046 #define PXP2_REG_PGL_CONTROL0                                    0x120490
3047 #define PXP2_REG_PGL_CONTROL1                                    0x120514
3048 #define PXP2_REG_PGL_DEBUG                                       0x120520
3049 /* [RW 32] third dword data of expansion rom request. this register is
3050    special. reading from it provides a vector outstanding read requests. if
3051    a bit is zero it means that a read request on the corresponding tag did
3052    not finish yet (not all completions have arrived for it) */
3053 #define PXP2_REG_PGL_EXP_ROM2                                    0x120808
3054 /* [RW 32] Inbound interrupt table for CSDM: bits[31:16]-mask;
3055    its[15:0]-address */
3056 #define PXP2_REG_PGL_INT_CSDM_0                                  0x1204f4
3057 #define PXP2_REG_PGL_INT_CSDM_1                                  0x1204f8
3058 #define PXP2_REG_PGL_INT_CSDM_2                                  0x1204fc
3059 #define PXP2_REG_PGL_INT_CSDM_3                                  0x120500
3060 #define PXP2_REG_PGL_INT_CSDM_4                                  0x120504
3061 #define PXP2_REG_PGL_INT_CSDM_5                                  0x120508
3062 #define PXP2_REG_PGL_INT_CSDM_6                                  0x12050c
3063 #define PXP2_REG_PGL_INT_CSDM_7                                  0x120510
3064 /* [RW 32] Inbound interrupt table for TSDM: bits[31:16]-mask;
3065    its[15:0]-address */
3066 #define PXP2_REG_PGL_INT_TSDM_0                                  0x120494
3067 #define PXP2_REG_PGL_INT_TSDM_1                                  0x120498
3068 #define PXP2_REG_PGL_INT_TSDM_2                                  0x12049c
3069 #define PXP2_REG_PGL_INT_TSDM_3                                  0x1204a0
3070 #define PXP2_REG_PGL_INT_TSDM_4                                  0x1204a4
3071 #define PXP2_REG_PGL_INT_TSDM_5                                  0x1204a8
3072 #define PXP2_REG_PGL_INT_TSDM_6                                  0x1204ac
3073 #define PXP2_REG_PGL_INT_TSDM_7                                  0x1204b0
3074 /* [RW 32] Inbound interrupt table for USDM: bits[31:16]-mask;
3075    its[15:0]-address */
3076 #define PXP2_REG_PGL_INT_USDM_0                                  0x1204b4
3077 #define PXP2_REG_PGL_INT_USDM_1                                  0x1204b8
3078 #define PXP2_REG_PGL_INT_USDM_2                                  0x1204bc
3079 #define PXP2_REG_PGL_INT_USDM_3                                  0x1204c0
3080 #define PXP2_REG_PGL_INT_USDM_4                                  0x1204c4
3081 #define PXP2_REG_PGL_INT_USDM_5                                  0x1204c8
3082 #define PXP2_REG_PGL_INT_USDM_6                                  0x1204cc
3083 #define PXP2_REG_PGL_INT_USDM_7                                  0x1204d0
3084 /* [RW 32] Inbound interrupt table for XSDM: bits[31:16]-mask;
3085    its[15:0]-address */
3086 #define PXP2_REG_PGL_INT_XSDM_0                                  0x1204d4
3087 #define PXP2_REG_PGL_INT_XSDM_1                                  0x1204d8
3088 #define PXP2_REG_PGL_INT_XSDM_2                                  0x1204dc
3089 #define PXP2_REG_PGL_INT_XSDM_3                                  0x1204e0
3090 #define PXP2_REG_PGL_INT_XSDM_4                                  0x1204e4
3091 #define PXP2_REG_PGL_INT_XSDM_5                                  0x1204e8
3092 #define PXP2_REG_PGL_INT_XSDM_6                                  0x1204ec
3093 #define PXP2_REG_PGL_INT_XSDM_7                                  0x1204f0
3094 /* [RW 3] this field allows one function to pretend being another function
3095    when accessing any BAR mapped resource within the device. the value of
3096    the field is the number of the function that will be accessed
3097    effectively. after software write to this bit it must read it in order to
3098    know that the new value is updated */
3099 #define PXP2_REG_PGL_PRETEND_FUNC_F0                             0x120674
3100 #define PXP2_REG_PGL_PRETEND_FUNC_F1                             0x120678
3101 #define PXP2_REG_PGL_PRETEND_FUNC_F2                             0x12067c
3102 #define PXP2_REG_PGL_PRETEND_FUNC_F3                             0x120680
3103 #define PXP2_REG_PGL_PRETEND_FUNC_F4                             0x120684
3104 #define PXP2_REG_PGL_PRETEND_FUNC_F5                             0x120688
3105 #define PXP2_REG_PGL_PRETEND_FUNC_F6                             0x12068c
3106 #define PXP2_REG_PGL_PRETEND_FUNC_F7                             0x120690
3107 /* [R 1] this bit indicates that a read request was blocked because of
3108    bus_master_en was deasserted */
3109 #define PXP2_REG_PGL_READ_BLOCKED                                0x120568
3110 #define PXP2_REG_PGL_TAGS_LIMIT                                  0x1205a8
3111 /* [R 18] debug only */
3112 #define PXP2_REG_PGL_TXW_CDTS                                    0x12052c
3113 /* [R 1] this bit indicates that a write request was blocked because of
3114    bus_master_en was deasserted */
3115 #define PXP2_REG_PGL_WRITE_BLOCKED                               0x120564
3116 #define PXP2_REG_PSWRQ_BW_ADD1                                   0x1201c0
3117 #define PXP2_REG_PSWRQ_BW_ADD10                                  0x1201e4
3118 #define PXP2_REG_PSWRQ_BW_ADD11                                  0x1201e8
3119 #define PXP2_REG_PSWRQ_BW_ADD2                                   0x1201c4
3120 #define PXP2_REG_PSWRQ_BW_ADD28                                  0x120228
3121 #define PXP2_REG_PSWRQ_BW_ADD3                                   0x1201c8
3122 #define PXP2_REG_PSWRQ_BW_ADD6                                   0x1201d4
3123 #define PXP2_REG_PSWRQ_BW_ADD7                                   0x1201d8
3124 #define PXP2_REG_PSWRQ_BW_ADD8                                   0x1201dc
3125 #define PXP2_REG_PSWRQ_BW_ADD9                                   0x1201e0
3126 #define PXP2_REG_PSWRQ_BW_CREDIT                                 0x12032c
3127 #define PXP2_REG_PSWRQ_BW_L1                                     0x1202b0
3128 #define PXP2_REG_PSWRQ_BW_L10                                    0x1202d4
3129 #define PXP2_REG_PSWRQ_BW_L11                                    0x1202d8
3130 #define PXP2_REG_PSWRQ_BW_L2                                     0x1202b4
3131 #define PXP2_REG_PSWRQ_BW_L28                                    0x120318
3132 #define PXP2_REG_PSWRQ_BW_L3                                     0x1202b8
3133 #define PXP2_REG_PSWRQ_BW_L6                                     0x1202c4
3134 #define PXP2_REG_PSWRQ_BW_L7                                     0x1202c8
3135 #define PXP2_REG_PSWRQ_BW_L8                                     0x1202cc
3136 #define PXP2_REG_PSWRQ_BW_L9                                     0x1202d0
3137 #define PXP2_REG_PSWRQ_BW_RD                                     0x120324
3138 #define PXP2_REG_PSWRQ_BW_UB1                                    0x120238
3139 #define PXP2_REG_PSWRQ_BW_UB10                                   0x12025c
3140 #define PXP2_REG_PSWRQ_BW_UB11                                   0x120260
3141 #define PXP2_REG_PSWRQ_BW_UB2                                    0x12023c
3142 #define PXP2_REG_PSWRQ_BW_UB28                                   0x1202a0
3143 #define PXP2_REG_PSWRQ_BW_UB3                                    0x120240
3144 #define PXP2_REG_PSWRQ_BW_UB6                                    0x12024c
3145 #define PXP2_REG_PSWRQ_BW_UB7                                    0x120250
3146 #define PXP2_REG_PSWRQ_BW_UB8                                    0x120254
3147 #define PXP2_REG_PSWRQ_BW_UB9                                    0x120258
3148 #define PXP2_REG_PSWRQ_BW_WR                                     0x120328
3149 #define PXP2_REG_PSWRQ_CDU0_L2P                                  0x120000
3150 #define PXP2_REG_PSWRQ_QM0_L2P                                   0x120038
3151 #define PXP2_REG_PSWRQ_SRC0_L2P                                  0x120054
3152 #define PXP2_REG_PSWRQ_TM0_L2P                                   0x12001c
3153 #define PXP2_REG_PSWRQ_TSDM0_L2P                                 0x1200e0
3154 /* [RW 32] Interrupt mask register #0 read/write */
3155 #define PXP2_REG_PXP2_INT_MASK_0                                 0x120578
3156 /* [R 32] Interrupt register #0 read */
3157 #define PXP2_REG_PXP2_INT_STS_0                                  0x12056c
3158 #define PXP2_REG_PXP2_INT_STS_1                                  0x120608
3159 /* [RC 32] Interrupt register #0 read clear */
3160 #define PXP2_REG_PXP2_INT_STS_CLR_0                              0x120570
3161 /* [RW 32] Parity mask register #0 read/write */
3162 #define PXP2_REG_PXP2_PRTY_MASK_0                                0x120588
3163 #define PXP2_REG_PXP2_PRTY_MASK_1                                0x120598
3164 /* [R 32] Parity register #0 read */
3165 #define PXP2_REG_PXP2_PRTY_STS_0                                 0x12057c
3166 #define PXP2_REG_PXP2_PRTY_STS_1                                 0x12058c
3167 /* [RC 32] Parity register #0 read clear */
3168 #define PXP2_REG_PXP2_PRTY_STS_CLR_0                             0x120580
3169 #define PXP2_REG_PXP2_PRTY_STS_CLR_1                             0x120590
3170 /* [R 1] Debug only: The 'almost full' indication from each fifo (gives
3171    indication about backpressure) */
3172 #define PXP2_REG_RD_ALMOST_FULL_0                                0x120424
3173 /* [R 8] Debug only: The blocks counter - number of unused block ids */
3174 #define PXP2_REG_RD_BLK_CNT                                      0x120418
3175 /* [RW 8] Debug only: Total number of available blocks in Tetris Buffer.
3176    Must be bigger than 6. Normally should not be changed. */
3177 #define PXP2_REG_RD_BLK_NUM_CFG                                  0x12040c
3178 /* [RW 2] CDU byte swapping mode configuration for master read requests */
3179 #define PXP2_REG_RD_CDURD_SWAP_MODE                              0x120404
3180 /* [RW 1] When '1'; inputs to the PSWRD block are ignored */
3181 #define PXP2_REG_RD_DISABLE_INPUTS                               0x120374
3182 /* [R 1] PSWRD internal memories initialization is done */
3183 #define PXP2_REG_RD_INIT_DONE                                    0x120370
3184 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3185    allocated for vq10 */
3186 #define PXP2_REG_RD_MAX_BLKS_VQ10                                0x1203a0
3187 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3188    allocated for vq11 */
3189 #define PXP2_REG_RD_MAX_BLKS_VQ11                                0x1203a4
3190 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3191    allocated for vq17 */
3192 #define PXP2_REG_RD_MAX_BLKS_VQ17                                0x1203bc
3193 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3194    allocated for vq18 */
3195 #define PXP2_REG_RD_MAX_BLKS_VQ18                                0x1203c0
3196 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3197    allocated for vq19 */
3198 #define PXP2_REG_RD_MAX_BLKS_VQ19                                0x1203c4
3199 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3200    allocated for vq22 */
3201 #define PXP2_REG_RD_MAX_BLKS_VQ22                                0x1203d0
3202 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3203    allocated for vq25 */
3204 #define PXP2_REG_RD_MAX_BLKS_VQ25                                0x1203dc
3205 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3206    allocated for vq6 */
3207 #define PXP2_REG_RD_MAX_BLKS_VQ6                                 0x120390
3208 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3209    allocated for vq9 */
3210 #define PXP2_REG_RD_MAX_BLKS_VQ9                                 0x12039c
3211 /* [RW 2] PBF byte swapping mode configuration for master read requests */
3212 #define PXP2_REG_RD_PBF_SWAP_MODE                                0x1203f4
3213 /* [R 1] Debug only: Indication if delivery ports are idle */
3214 #define PXP2_REG_RD_PORT_IS_IDLE_0                               0x12041c
3215 #define PXP2_REG_RD_PORT_IS_IDLE_1                               0x120420
3216 /* [RW 2] QM byte swapping mode configuration for master read requests */
3217 #define PXP2_REG_RD_QM_SWAP_MODE                                 0x1203f8
3218 /* [R 7] Debug only: The SR counter - number of unused sub request ids */
3219 #define PXP2_REG_RD_SR_CNT                                       0x120414
3220 /* [RW 2] SRC byte swapping mode configuration for master read requests */
3221 #define PXP2_REG_RD_SRC_SWAP_MODE                                0x120400
3222 /* [RW 7] Debug only: Total number of available PCI read sub-requests. Must
3223    be bigger than 1. Normally should not be changed. */
3224 #define PXP2_REG_RD_SR_NUM_CFG                                   0x120408
3225 /* [RW 1] Signals the PSWRD block to start initializing internal memories */
3226 #define PXP2_REG_RD_START_INIT                                   0x12036c
3227 /* [RW 2] TM byte swapping mode configuration for master read requests */
3228 #define PXP2_REG_RD_TM_SWAP_MODE                                 0x1203fc
3229 /* [RW 10] Bandwidth addition to VQ0 write requests */
3230 #define PXP2_REG_RQ_BW_RD_ADD0                                   0x1201bc
3231 /* [RW 10] Bandwidth addition to VQ12 read requests */
3232 #define PXP2_REG_RQ_BW_RD_ADD12                                  0x1201ec
3233 /* [RW 10] Bandwidth addition to VQ13 read requests */
3234 #define PXP2_REG_RQ_BW_RD_ADD13                                  0x1201f0
3235 /* [RW 10] Bandwidth addition to VQ14 read requests */
3236 #define PXP2_REG_RQ_BW_RD_ADD14                                  0x1201f4
3237 /* [RW 10] Bandwidth addition to VQ15 read requests */
3238 #define PXP2_REG_RQ_BW_RD_ADD15                                  0x1201f8
3239 /* [RW 10] Bandwidth addition to VQ16 read requests */
3240 #define PXP2_REG_RQ_BW_RD_ADD16                                  0x1201fc
3241 /* [RW 10] Bandwidth addition to VQ17 read requests */
3242 #define PXP2_REG_RQ_BW_RD_ADD17                                  0x120200
3243 /* [RW 10] Bandwidth addition to VQ18 read requests */
3244 #define PXP2_REG_RQ_BW_RD_ADD18                                  0x120204
3245 /* [RW 10] Bandwidth addition to VQ19 read requests */
3246 #define PXP2_REG_RQ_BW_RD_ADD19                                  0x120208
3247 /* [RW 10] Bandwidth addition to VQ20 read requests */
3248 #define PXP2_REG_RQ_BW_RD_ADD20                                  0x12020c
3249 /* [RW 10] Bandwidth addition to VQ22 read requests */
3250 #define PXP2_REG_RQ_BW_RD_ADD22                                  0x120210
3251 /* [RW 10] Bandwidth addition to VQ23 read requests */
3252 #define PXP2_REG_RQ_BW_RD_ADD23                                  0x120214
3253 /* [RW 10] Bandwidth addition to VQ24 read requests */
3254 #define PXP2_REG_RQ_BW_RD_ADD24                                  0x120218
3255 /* [RW 10] Bandwidth addition to VQ25 read requests */
3256 #define PXP2_REG_RQ_BW_RD_ADD25                                  0x12021c
3257 /* [RW 10] Bandwidth addition to VQ26 read requests */
3258 #define PXP2_REG_RQ_BW_RD_ADD26                                  0x120220
3259 /* [RW 10] Bandwidth addition to VQ27 read requests */
3260 #define PXP2_REG_RQ_BW_RD_ADD27                                  0x120224
3261 /* [RW 10] Bandwidth addition to VQ4 read requests */
3262 #define PXP2_REG_RQ_BW_RD_ADD4                                   0x1201cc
3263 /* [RW 10] Bandwidth addition to VQ5 read requests */
3264 #define PXP2_REG_RQ_BW_RD_ADD5                                   0x1201d0
3265 /* [RW 10] Bandwidth Typical L for VQ0 Read requests */
3266 #define PXP2_REG_RQ_BW_RD_L0                                     0x1202ac
3267 /* [RW 10] Bandwidth Typical L for VQ12 Read requests */
3268 #define PXP2_REG_RQ_BW_RD_L12                                    0x1202dc
3269 /* [RW 10] Bandwidth Typical L for VQ13 Read requests */
3270 #define PXP2_REG_RQ_BW_RD_L13                                    0x1202e0
3271 /* [RW 10] Bandwidth Typical L for VQ14 Read requests */
3272 #define PXP2_REG_RQ_BW_RD_L14                                    0x1202e4
3273 /* [RW 10] Bandwidth Typical L for VQ15 Read requests */
3274 #define PXP2_REG_RQ_BW_RD_L15                                    0x1202e8
3275 /* [RW 10] Bandwidth Typical L for VQ16 Read requests */
3276 #define PXP2_REG_RQ_BW_RD_L16                                    0x1202ec
3277 /* [RW 10] Bandwidth Typical L for VQ17 Read requests */
3278 #define PXP2_REG_RQ_BW_RD_L17                                    0x1202f0
3279 /* [RW 10] Bandwidth Typical L for VQ18 Read requests */
3280 #define PXP2_REG_RQ_BW_RD_L18                                    0x1202f4
3281 /* [RW 10] Bandwidth Typical L for VQ19 Read requests */
3282 #define PXP2_REG_RQ_BW_RD_L19                                    0x1202f8
3283 /* [RW 10] Bandwidth Typical L for VQ20 Read requests */
3284 #define PXP2_REG_RQ_BW_RD_L20                                    0x1202fc
3285 /* [RW 10] Bandwidth Typical L for VQ22 Read requests */
3286 #define PXP2_REG_RQ_BW_RD_L22                                    0x120300
3287 /* [RW 10] Bandwidth Typical L for VQ23 Read requests */
3288 #define PXP2_REG_RQ_BW_RD_L23                                    0x120304
3289 /* [RW 10] Bandwidth Typical L for VQ24 Read requests */
3290 #define PXP2_REG_RQ_BW_RD_L24                                    0x120308
3291 /* [RW 10] Bandwidth Typical L for VQ25 Read requests */
3292 #define PXP2_REG_RQ_BW_RD_L25                                    0x12030c
3293 /* [RW 10] Bandwidth Typical L for VQ26 Read requests */
3294 #define PXP2_REG_RQ_BW_RD_L26                                    0x120310
3295 /* [RW 10] Bandwidth Typical L for VQ27 Read requests */
3296 #define PXP2_REG_RQ_BW_RD_L27                                    0x120314
3297 /* [RW 10] Bandwidth Typical L for VQ4 Read requests */
3298 #define PXP2_REG_RQ_BW_RD_L4                                     0x1202bc
3299 /* [RW 10] Bandwidth Typical L for VQ5 Read- currently not used */
3300 #define PXP2_REG_RQ_BW_RD_L5                                     0x1202c0
3301 /* [RW 7] Bandwidth upper bound for VQ0 read requests */
3302 #define PXP2_REG_RQ_BW_RD_UBOUND0                                0x120234
3303 /* [RW 7] Bandwidth upper bound for VQ12 read requests */
3304 #define PXP2_REG_RQ_BW_RD_UBOUND12                               0x120264
3305 /* [RW 7] Bandwidth upper bound for VQ13 read requests */
3306 #define PXP2_REG_RQ_BW_RD_UBOUND13                               0x120268
3307 /* [RW 7] Bandwidth upper bound for VQ14 read requests */
3308 #define PXP2_REG_RQ_BW_RD_UBOUND14                               0x12026c
3309 /* [RW 7] Bandwidth upper bound for VQ15 read requests */
3310 #define PXP2_REG_RQ_BW_RD_UBOUND15                               0x120270
3311 /* [RW 7] Bandwidth upper bound for VQ16 read requests */
3312 #define PXP2_REG_RQ_BW_RD_UBOUND16                               0x120274
3313 /* [RW 7] Bandwidth upper bound for VQ17 read requests */
3314 #define PXP2_REG_RQ_BW_RD_UBOUND17                               0x120278
3315 /* [RW 7] Bandwidth upper bound for VQ18 read requests */
3316 #define PXP2_REG_RQ_BW_RD_UBOUND18                               0x12027c
3317 /* [RW 7] Bandwidth upper bound for VQ19 read requests */
3318 #define PXP2_REG_RQ_BW_RD_UBOUND19                               0x120280
3319 /* [RW 7] Bandwidth upper bound for VQ20 read requests */
3320 #define PXP2_REG_RQ_BW_RD_UBOUND20                               0x120284
3321 /* [RW 7] Bandwidth upper bound for VQ22 read requests */
3322 #define PXP2_REG_RQ_BW_RD_UBOUND22                               0x120288
3323 /* [RW 7] Bandwidth upper bound for VQ23 read requests */
3324 #define PXP2_REG_RQ_BW_RD_UBOUND23                               0x12028c
3325 /* [RW 7] Bandwidth upper bound for VQ24 read requests */
3326 #define PXP2_REG_RQ_BW_RD_UBOUND24                               0x120290
3327 /* [RW 7] Bandwidth upper bound for VQ25 read requests */
3328 #define PXP2_REG_RQ_BW_RD_UBOUND25                               0x120294
3329 /* [RW 7] Bandwidth upper bound for VQ26 read requests */
3330 #define PXP2_REG_RQ_BW_RD_UBOUND26                               0x120298
3331 /* [RW 7] Bandwidth upper bound for VQ27 read requests */
3332 #define PXP2_REG_RQ_BW_RD_UBOUND27                               0x12029c
3333 /* [RW 7] Bandwidth upper bound for VQ4 read requests */
3334 #define PXP2_REG_RQ_BW_RD_UBOUND4                                0x120244
3335 /* [RW 7] Bandwidth upper bound for VQ5 read requests */
3336 #define PXP2_REG_RQ_BW_RD_UBOUND5                                0x120248
3337 /* [RW 10] Bandwidth addition to VQ29 write requests */
3338 #define PXP2_REG_RQ_BW_WR_ADD29                                  0x12022c
3339 /* [RW 10] Bandwidth addition to VQ30 write requests */
3340 #define PXP2_REG_RQ_BW_WR_ADD30                                  0x120230
3341 /* [RW 10] Bandwidth Typical L for VQ29 Write requests */
3342 #define PXP2_REG_RQ_BW_WR_L29                                    0x12031c
3343 /* [RW 10] Bandwidth Typical L for VQ30 Write requests */
3344 #define PXP2_REG_RQ_BW_WR_L30                                    0x120320
3345 /* [RW 7] Bandwidth upper bound for VQ29 */
3346 #define PXP2_REG_RQ_BW_WR_UBOUND29                               0x1202a4
3347 /* [RW 7] Bandwidth upper bound for VQ30 */
3348 #define PXP2_REG_RQ_BW_WR_UBOUND30                               0x1202a8
3349 /* [RW 18] external first_mem_addr field in L2P table for CDU module port 0 */
3350 #define PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR                         0x120008
3351 /* [RW 2] Endian mode for cdu */
3352 #define PXP2_REG_RQ_CDU_ENDIAN_M                                 0x1201a0
3353 #define PXP2_REG_RQ_CDU_FIRST_ILT                                0x12061c
3354 #define PXP2_REG_RQ_CDU_LAST_ILT                                 0x120620
3355 /* [RW 3] page size in L2P table for CDU module; -4k; -8k; -16k; -32k; -64k;
3356    -128k */
3357 #define PXP2_REG_RQ_CDU_P_SIZE                                   0x120018
3358 /* [R 1] 1' indicates that the requester has finished its internal
3359    configuration */
3360 #define PXP2_REG_RQ_CFG_DONE                                     0x1201b4
3361 /* [RW 2] Endian mode for debug */
3362 #define PXP2_REG_RQ_DBG_ENDIAN_M                                 0x1201a4
3363 /* [RW 1] When '1'; requests will enter input buffers but wont get out
3364    towards the glue */
3365 #define PXP2_REG_RQ_DISABLE_INPUTS                               0x120330
3366 /* [RW 4] Determines alignment of write SRs when a request is split into
3367  * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B
3368  * aligned. 4 - 512B aligned. */
3369 #define PXP2_REG_RQ_DRAM_ALIGN                                   0x1205b0
3370 /* [RW 4] Determines alignment of read SRs when a request is split into
3371  * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B
3372  * aligned. 4 - 512B aligned. */
3373 #define PXP2_REG_RQ_DRAM_ALIGN_RD                                0x12092c
3374 /* [RW 1] when set the new alignment method (E2) will be applied; when reset
3375  * the original alignment method (E1 E1H) will be applied */
3376 #define PXP2_REG_RQ_DRAM_ALIGN_SEL                               0x120930
3377 /* [RW 1] If 1 ILT failiue will not result in ELT access; An interrupt will
3378    be asserted */
3379 #define PXP2_REG_RQ_ELT_DISABLE                                  0x12066c
3380 /* [RW 2] Endian mode for hc */
3381 #define PXP2_REG_RQ_HC_ENDIAN_M                                  0x1201a8
3382 /* [RW 1] when '0' ILT logic will work as in A0; otherwise B0; for back
3383    compatibility needs; Note that different registers are used per mode */
3384 #define PXP2_REG_RQ_ILT_MODE                                     0x1205b4
3385 /* [WB 53] Onchip address table */
3386 #define PXP2_REG_RQ_ONCHIP_AT                                    0x122000
3387 /* [WB 53] Onchip address table - B0 */
3388 #define PXP2_REG_RQ_ONCHIP_AT_B0                                 0x128000
3389 /* [RW 13] Pending read limiter threshold; in Dwords */
3390 #define PXP2_REG_RQ_PDR_LIMIT                                    0x12033c
3391 /* [RW 2] Endian mode for qm */
3392 #define PXP2_REG_RQ_QM_ENDIAN_M                                  0x120194
3393 #define PXP2_REG_RQ_QM_FIRST_ILT                                 0x120634
3394 #define PXP2_REG_RQ_QM_LAST_ILT                                  0x120638
3395 /* [RW 3] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k;
3396    -128k */
3397 #define PXP2_REG_RQ_QM_P_SIZE                                    0x120050
3398 /* [RW 1] 1' indicates that the RBC has finished configuring the PSWRQ */
3399 #define PXP2_REG_RQ_RBC_DONE                                     0x1201b0
3400 /* [RW 3] Max burst size filed for read requests port 0; 000 - 128B;
3401    001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
3402 #define PXP2_REG_RQ_RD_MBS0                                      0x120160
3403 /* [RW 3] Max burst size filed for read requests port 1; 000 - 128B;
3404    001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
3405 #define PXP2_REG_RQ_RD_MBS1                                      0x120168
3406 /* [RW 2] Endian mode for src */
3407 #define PXP2_REG_RQ_SRC_ENDIAN_M                                 0x12019c
3408 #define PXP2_REG_RQ_SRC_FIRST_ILT                                0x12063c
3409 #define PXP2_REG_RQ_SRC_LAST_ILT                                 0x120640
3410 /* [RW 3] page size in L2P table for SRC module; -4k; -8k; -16k; -32k; -64k;
3411    -128k */
3412 #define PXP2_REG_RQ_SRC_P_SIZE                                   0x12006c
3413 /* [RW 2] Endian mode for tm */
3414 #define PXP2_REG_RQ_TM_ENDIAN_M                                  0x120198
3415 #define PXP2_REG_RQ_TM_FIRST_ILT                                 0x120644
3416 #define PXP2_REG_RQ_TM_LAST_ILT                                  0x120648
3417 /* [RW 3] page size in L2P table for TM module; -4k; -8k; -16k; -32k; -64k;
3418    -128k */
3419 #define PXP2_REG_RQ_TM_P_SIZE                                    0x120034
3420 /* [R 5] Number of entries in the ufifo; his fifo has l2p completions */
3421 #define PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY                           0x12080c
3422 /* [RW 18] external first_mem_addr field in L2P table for USDM module port 0 */
3423 #define PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR                        0x120094
3424 /* [R 8] Number of entries occupied by vq 0 in pswrq memory */
3425 #define PXP2_REG_RQ_VQ0_ENTRY_CNT                                0x120810
3426 /* [R 8] Number of entries occupied by vq 10 in pswrq memory */
3427 #define PXP2_REG_RQ_VQ10_ENTRY_CNT                               0x120818
3428 /* [R 8] Number of entries occupied by vq 11 in pswrq memory */
3429 #define PXP2_REG_RQ_VQ11_ENTRY_CNT                               0x120820
3430 /* [R 8] Number of entries occupied by vq 12 in pswrq memory */
3431 #define PXP2_REG_RQ_VQ12_ENTRY_CNT                               0x120828
3432 /* [R 8] Number of entries occupied by vq 13 in pswrq memory */
3433 #define PXP2_REG_RQ_VQ13_ENTRY_CNT                               0x120830
3434 /* [R 8] Number of entries occupied by vq 14 in pswrq memory */
3435 #define PXP2_REG_RQ_VQ14_ENTRY_CNT                               0x120838
3436 /* [R 8] Number of entries occupied by vq 15 in pswrq memory */
3437 #define PXP2_REG_RQ_VQ15_ENTRY_CNT                               0x120840
3438 /* [R 8] Number of entries occupied by vq 16 in pswrq memory */
3439 #define PXP2_REG_RQ_VQ16_ENTRY_CNT                               0x120848
3440 /* [R 8] Number of entries occupied by vq 17 in pswrq memory */
3441 #define PXP2_REG_RQ_VQ17_ENTRY_CNT                               0x120850
3442 /* [R 8] Number of entries occupied by vq 18 in pswrq memory */
3443 #define PXP2_REG_RQ_VQ18_ENTRY_CNT                               0x120858
3444 /* [R 8] Number of entries occupied by vq 19 in pswrq memory */
3445 #define PXP2_REG_RQ_VQ19_ENTRY_CNT                               0x120860
3446 /* [R 8] Number of entries occupied by vq 1 in pswrq memory */
3447 #define PXP2_REG_RQ_VQ1_ENTRY_CNT                                0x120868
3448 /* [R 8] Number of entries occupied by vq 20 in pswrq memory */
3449 #define PXP2_REG_RQ_VQ20_ENTRY_CNT                               0x120870
3450 /* [R 8] Number of entries occupied by vq 21 in pswrq memory */
3451 #define PXP2_REG_RQ_VQ21_ENTRY_CNT                               0x120878
3452 /* [R 8] Number of entries occupied by vq 22 in pswrq memory */
3453 #define PXP2_REG_RQ_VQ22_ENTRY_CNT                               0x120880
3454 /* [R 8] Number of entries occupied by vq 23 in pswrq memory */
3455 #define PXP2_REG_RQ_VQ23_ENTRY_CNT                               0x120888
3456 /* [R 8] Number of entries occupied by vq 24 in pswrq memory */
3457 #define PXP2_REG_RQ_VQ24_ENTRY_CNT                               0x120890
3458 /* [R 8] Number of entries occupied by vq 25 in pswrq memory */
3459 #define PXP2_REG_RQ_VQ25_ENTRY_CNT                               0x120898
3460 /* [R 8] Number of entries occupied by vq 26 in pswrq memory */
3461 #define PXP2_REG_RQ_VQ26_ENTRY_CNT                               0x1208a0
3462 /* [R 8] Number of entries occupied by vq 27 in pswrq memory */
3463 #define PXP2_REG_RQ_VQ27_ENTRY_CNT                               0x1208a8
3464 /* [R 8] Number of entries occupied by vq 28 in pswrq memory */
3465 #define PXP2_REG_RQ_VQ28_ENTRY_CNT                               0x1208b0
3466 /* [R 8] Number of entries occupied by vq 29 in pswrq memory */
3467 #define PXP2_REG_RQ_VQ29_ENTRY_CNT                               0x1208b8
3468 /* [R 8] Number of entries occupied by vq 2 in pswrq memory */
3469 #define PXP2_REG_RQ_VQ2_ENTRY_CNT                                0x1208c0
3470 /* [R 8] Number of entries occupied by vq 30 in pswrq memory */
3471 #define PXP2_REG_RQ_VQ30_ENTRY_CNT                               0x1208c8
3472 /* [R 8] Number of entries occupied by vq 31 in pswrq memory */
3473 #define PXP2_REG_RQ_VQ31_ENTRY_CNT                               0x1208d0
3474 /* [R 8] Number of entries occupied by vq 3 in pswrq memory */
3475 #define PXP2_REG_RQ_VQ3_ENTRY_CNT                                0x1208d8
3476 /* [R 8] Number of entries occupied by vq 4 in pswrq memory */
3477 #define PXP2_REG_RQ_VQ4_ENTRY_CNT                                0x1208e0
3478 /* [R 8] Number of entries occupied by vq 5 in pswrq memory */
3479 #define PXP2_REG_RQ_VQ5_ENTRY_CNT                                0x1208e8
3480 /* [R 8] Number of entries occupied by vq 6 in pswrq memory */
3481 #define PXP2_REG_RQ_VQ6_ENTRY_CNT                                0x1208f0
3482 /* [R 8] Number of entries occupied by vq 7 in pswrq memory */
3483 #define PXP2_REG_RQ_VQ7_ENTRY_CNT                                0x1208f8
3484 /* [R 8] Number of entries occupied by vq 8 in pswrq memory */
3485 #define PXP2_REG_RQ_VQ8_ENTRY_CNT                                0x120900
3486 /* [R 8] Number of entries occupied by vq 9 in pswrq memory */
3487 #define PXP2_REG_RQ_VQ9_ENTRY_CNT                                0x120908
3488 /* [RW 3] Max burst size filed for write requests port 0; 000 - 128B;
3489    001:256B; 010: 512B; */
3490 #define PXP2_REG_RQ_WR_MBS0                                      0x12015c
3491 /* [RW 3] Max burst size filed for write requests port 1; 000 - 128B;
3492    001:256B; 010: 512B; */
3493 #define PXP2_REG_RQ_WR_MBS1                                      0x120164
3494 /* [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in the
3495    buffer reaches this number has_payload will be asserted */
3496 #define PXP2_REG_WR_CDU_MPS                                      0x1205f0
3497 /* [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in the
3498    buffer reaches this number has_payload will be asserted */
3499 #define PXP2_REG_WR_CSDM_MPS                                     0x1205d0
3500 /* [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in the
3501    buffer reaches this number has_payload will be asserted */
3502 #define PXP2_REG_WR_DBG_MPS                                      0x1205e8
3503 /* [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in the
3504    buffer reaches this number has_payload will be asserted */
3505 #define PXP2_REG_WR_DMAE_MPS                                     0x1205ec
3506 /* [RW 10] if Number of entries in dmae fifo will be higher than this
3507    threshold then has_payload indication will be asserted; the default value
3508    should be equal to &gt;  write MBS size! */
3509 #define PXP2_REG_WR_DMAE_TH                                      0x120368
3510 /* [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in the
3511    buffer reaches this number has_payload will be asserted */
3512 #define PXP2_REG_WR_HC_MPS                                       0x1205c8
3513 /* [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in the
3514    buffer reaches this number has_payload will be asserted */
3515 #define PXP2_REG_WR_QM_MPS                                       0x1205dc
3516 /* [RW 1] 0 - working in A0 mode;  - working in B0 mode */
3517 #define PXP2_REG_WR_REV_MODE                                     0x120670
3518 /* [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in the
3519    buffer reaches this number has_payload will be asserted */
3520 #define PXP2_REG_WR_SRC_MPS                                      0x1205e4
3521 /* [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in the
3522    buffer reaches this number has_payload will be asserted */
3523 #define PXP2_REG_WR_TM_MPS                                       0x1205e0
3524 /* [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in the
3525    buffer reaches this number has_payload will be asserted */
3526 #define PXP2_REG_WR_TSDM_MPS                                     0x1205d4
3527 /* [RW 10] if Number of entries in usdmdp fifo will be higher than this
3528    threshold then has_payload indication will be asserted; the default value
3529    should be equal to &gt;  write MBS size! */
3530 #define PXP2_REG_WR_USDMDP_TH                                    0x120348
3531 /* [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in the
3532    buffer reaches this number has_payload will be asserted */
3533 #define PXP2_REG_WR_USDM_MPS                                     0x1205cc
3534 /* [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in the
3535    buffer reaches this number has_payload will be asserted */
3536 #define PXP2_REG_WR_XSDM_MPS                                     0x1205d8
3537 /* [R 1] debug only: Indication if PSWHST arbiter is idle */
3538 #define PXP_REG_HST_ARB_IS_IDLE                                  0x103004
3539 /* [R 8] debug only: A bit mask for all PSWHST arbiter clients. '1' means
3540    this client is waiting for the arbiter. */
3541 #define PXP_REG_HST_CLIENTS_WAITING_TO_ARB                       0x103008
3542 /* [RW 1] When 1; doorbells are discarded and not passed to doorbell queue
3543    block. Should be used for close the gates. */
3544 #define PXP_REG_HST_DISCARD_DOORBELLS                            0x1030a4
3545 /* [R 1] debug only: '1' means this PSWHST is discarding doorbells. This bit
3546    should update according to 'hst_discard_doorbells' register when the state
3547    machine is idle */
3548 #define PXP_REG_HST_DISCARD_DOORBELLS_STATUS                     0x1030a0
3549 /* [RW 1] When 1; new internal writes arriving to the block are discarded.
3550    Should be used for close the gates. */
3551 #define PXP_REG_HST_DISCARD_INTERNAL_WRITES                      0x1030a8
3552 /* [R 6] debug only: A bit mask for all PSWHST internal write clients. '1'
3553    means this PSWHST is discarding inputs from this client. Each bit should
3554    update according to 'hst_discard_internal_writes' register when the state
3555    machine is idle. */
3556 #define PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS               0x10309c
3557 /* [WB 160] Used for initialization of the inbound interrupts memory */
3558 #define PXP_REG_HST_INBOUND_INT                                  0x103800
3559 /* [RW 32] Interrupt mask register #0 read/write */
3560 #define PXP_REG_PXP_INT_MASK_0                                   0x103074
3561 #define PXP_REG_PXP_INT_MASK_1                                   0x103084
3562 /* [R 32] Interrupt register #0 read */
3563 #define PXP_REG_PXP_INT_STS_0                                    0x103068
3564 #define PXP_REG_PXP_INT_STS_1                                    0x103078
3565 /* [RC 32] Interrupt register #0 read clear */
3566 #define PXP_REG_PXP_INT_STS_CLR_0                                0x10306c
3567 #define PXP_REG_PXP_INT_STS_CLR_1                                0x10307c
3568 /* [RW 27] Parity mask register #0 read/write */
3569 #define PXP_REG_PXP_PRTY_MASK                                    0x103094
3570 /* [R 26] Parity register #0 read */
3571 #define PXP_REG_PXP_PRTY_STS                                     0x103088
3572 /* [RC 27] Parity register #0 read clear */
3573 #define PXP_REG_PXP_PRTY_STS_CLR                                 0x10308c
3574 /* [RW 4] The activity counter initial increment value sent in the load
3575    request */
3576 #define QM_REG_ACTCTRINITVAL_0                                   0x168040
3577 #define QM_REG_ACTCTRINITVAL_1                                   0x168044
3578 #define QM_REG_ACTCTRINITVAL_2                                   0x168048
3579 #define QM_REG_ACTCTRINITVAL_3                                   0x16804c
3580 /* [RW 32] The base logical address (in bytes) of each physical queue. The
3581    index I represents the physical queue number. The 12 lsbs are ignore and
3582    considered zero so practically there are only 20 bits in this register;
3583    queues 63-0 */
3584 #define QM_REG_BASEADDR                                          0x168900
3585 /* [RW 32] The base logical address (in bytes) of each physical queue. The
3586    index I represents the physical queue number. The 12 lsbs are ignore and
3587    considered zero so practically there are only 20 bits in this register;
3588    queues 127-64 */
3589 #define QM_REG_BASEADDR_EXT_A                                    0x16e100
3590 /* [RW 16] The byte credit cost for each task. This value is for both ports */
3591 #define QM_REG_BYTECRDCOST                                       0x168234
3592 /* [RW 16] The initial byte credit value for both ports. */
3593 #define QM_REG_BYTECRDINITVAL                                    0x168238
3594 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3595    queue uses port 0 else it uses port 1; queues 31-0 */
3596 #define QM_REG_BYTECRDPORT_LSB                                   0x168228
3597 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3598    queue uses port 0 else it uses port 1; queues 95-64 */
3599 #define QM_REG_BYTECRDPORT_LSB_EXT_A                             0x16e520
3600 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3601    queue uses port 0 else it uses port 1; queues 63-32 */
3602 #define QM_REG_BYTECRDPORT_MSB                                   0x168224
3603 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3604    queue uses port 0 else it uses port 1; queues 127-96 */
3605 #define QM_REG_BYTECRDPORT_MSB_EXT_A                             0x16e51c
3606 /* [RW 16] The byte credit value that if above the QM is considered almost
3607    full */
3608 #define QM_REG_BYTECREDITAFULLTHR                                0x168094
3609 /* [RW 4] The initial credit for interface */
3610 #define QM_REG_CMINITCRD_0                                       0x1680cc
3611 #define QM_REG_BYTECRDCMDQ_0                                     0x16e6e8
3612 #define QM_REG_CMINITCRD_1                                       0x1680d0
3613 #define QM_REG_CMINITCRD_2                                       0x1680d4
3614 #define QM_REG_CMINITCRD_3                                       0x1680d8
3615 #define QM_REG_CMINITCRD_4                                       0x1680dc
3616 #define QM_REG_CMINITCRD_5                                       0x1680e0
3617 #define QM_REG_CMINITCRD_6                                       0x1680e4
3618 #define QM_REG_CMINITCRD_7                                       0x1680e8
3619 /* [RW 8] A mask bit per CM interface. If this bit is 0 then this interface
3620    is masked */
3621 #define QM_REG_CMINTEN                                           0x1680ec
3622 /* [RW 12] A bit vector which indicates which one of the queues are tied to
3623    interface 0 */
3624 #define QM_REG_CMINTVOQMASK_0                                    0x1681f4
3625 #define QM_REG_CMINTVOQMASK_1                                    0x1681f8
3626 #define QM_REG_CMINTVOQMASK_2                                    0x1681fc
3627 #define QM_REG_CMINTVOQMASK_3                                    0x168200
3628 #define QM_REG_CMINTVOQMASK_4                                    0x168204
3629 #define QM_REG_CMINTVOQMASK_5                                    0x168208
3630 #define QM_REG_CMINTVOQMASK_6                                    0x16820c
3631 #define QM_REG_CMINTVOQMASK_7                                    0x168210
3632 /* [RW 20] The number of connections divided by 16 which dictates the size
3633    of each queue which belongs to even function number. */
3634 #define QM_REG_CONNNUM_0                                         0x168020
3635 /* [R 6] Keep the fill level of the fifo from write client 4 */
3636 #define QM_REG_CQM_WRC_FIFOLVL                                   0x168018
3637 /* [RW 8] The context regions sent in the CFC load request */
3638 #define QM_REG_CTXREG_0                                          0x168030
3639 #define QM_REG_CTXREG_1                                          0x168034
3640 #define QM_REG_CTXREG_2                                          0x168038
3641 #define QM_REG_CTXREG_3                                          0x16803c
3642 /* [RW 12] The VOQ mask used to select the VOQs which needs to be full for
3643    bypass enable */
3644 #define QM_REG_ENBYPVOQMASK                                      0x16823c
3645 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
3646    physical queue uses the byte credit; queues 31-0 */
3647 #define QM_REG_ENBYTECRD_LSB                                     0x168220
3648 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
3649    physical queue uses the byte credit; queues 95-64 */
3650 #define QM_REG_ENBYTECRD_LSB_EXT_A                               0x16e518
3651 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
3652    physical queue uses the byte credit; queues 63-32 */
3653 #define QM_REG_ENBYTECRD_MSB                                     0x16821c
3654 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
3655    physical queue uses the byte credit; queues 127-96 */
3656 #define QM_REG_ENBYTECRD_MSB_EXT_A                               0x16e514
3657 /* [RW 4] If cleared then the secondary interface will not be served by the
3658    RR arbiter */
3659 #define QM_REG_ENSEC                                             0x1680f0
3660 /* [RW 32] NA */
3661 #define QM_REG_FUNCNUMSEL_LSB                                    0x168230
3662 /* [RW 32] NA */
3663 #define QM_REG_FUNCNUMSEL_MSB                                    0x16822c
3664 /* [RW 32] A mask register to mask the Almost empty signals which will not
3665    be use for the almost empty indication to the HW block; queues 31:0 */
3666 #define QM_REG_HWAEMPTYMASK_LSB                                  0x168218
3667 /* [RW 32] A mask register to mask the Almost empty signals which will not
3668    be use for the almost empty indication to the HW block; queues 95-64 */
3669 #define QM_REG_HWAEMPTYMASK_LSB_EXT_A                            0x16e510
3670 /* [RW 32] A mask register to mask the Almost empty signals which will not
3671    be use for the almost empty indication to the HW block; queues 63:32 */
3672 #define QM_REG_HWAEMPTYMASK_MSB                                  0x168214
3673 /* [RW 32] A mask register to mask the Almost empty signals which will not
3674    be use for the almost empty indication to the HW block; queues 127-96 */
3675 #define QM_REG_HWAEMPTYMASK_MSB_EXT_A                            0x16e50c
3676 /* [RW 4] The number of outstanding request to CFC */
3677 #define QM_REG_OUTLDREQ                                          0x168804
3678 /* [RC 1] A flag to indicate that overflow error occurred in one of the
3679    queues. */
3680 #define QM_REG_OVFERROR                                          0x16805c
3681 /* [RC 7] the Q where the overflow occurs */
3682 #define QM_REG_OVFQNUM                                           0x168058
3683 /* [R 16] Pause state for physical queues 15-0 */
3684 #define QM_REG_PAUSESTATE0                                       0x168410
3685 /* [R 16] Pause state for physical queues 31-16 */
3686 #define QM_REG_PAUSESTATE1                                       0x168414
3687 /* [R 16] Pause state for physical queues 47-32 */
3688 #define QM_REG_PAUSESTATE2                                       0x16e684
3689 /* [R 16] Pause state for physical queues 63-48 */
3690 #define QM_REG_PAUSESTATE3                                       0x16e688
3691 /* [R 16] Pause state for physical queues 79-64 */
3692 #define QM_REG_PAUSESTATE4                                       0x16e68c
3693 /* [R 16] Pause state for physical queues 95-80 */
3694 #define QM_REG_PAUSESTATE5                                       0x16e690
3695 /* [R 16] Pause state for physical queues 111-96 */
3696 #define QM_REG_PAUSESTATE6                                       0x16e694
3697 /* [R 16] Pause state for physical queues 127-112 */
3698 #define QM_REG_PAUSESTATE7                                       0x16e698
3699 /* [RW 2] The PCI attributes field used in the PCI request. */
3700 #define QM_REG_PCIREQAT                                          0x168054
3701 #define QM_REG_PF_EN                                             0x16e70c
3702 /* [R 24] The number of tasks stored in the QM for the PF. only even
3703  * functions are valid in E2 (odd I registers will be hard wired to 0) */
3704 #define QM_REG_PF_USG_CNT_0                                      0x16e040
3705 /* [R 16] NOT USED */
3706 #define QM_REG_PORT0BYTECRD                                      0x168300
3707 /* [R 16] The byte credit of port 1 */
3708 #define QM_REG_PORT1BYTECRD                                      0x168304
3709 /* [RW 3] pci function number of queues 15-0 */
3710 #define QM_REG_PQ2PCIFUNC_0                                      0x16e6bc
3711 #define QM_REG_PQ2PCIFUNC_1                                      0x16e6c0
3712 #define QM_REG_PQ2PCIFUNC_2                                      0x16e6c4
3713 #define QM_REG_PQ2PCIFUNC_3                                      0x16e6c8
3714 #define QM_REG_PQ2PCIFUNC_4                                      0x16e6cc
3715 #define QM_REG_PQ2PCIFUNC_5                                      0x16e6d0
3716 #define QM_REG_PQ2PCIFUNC_6                                      0x16e6d4
3717 #define QM_REG_PQ2PCIFUNC_7                                      0x16e6d8
3718 /* [WB 54] Pointer Table Memory for queues 63-0; The mapping is as follow:
3719    ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read
3720    bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
3721 #define QM_REG_PTRTBL                                            0x168a00
3722 /* [WB 54] Pointer Table Memory for queues 127-64; The mapping is as follow:
3723    ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read
3724    bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
3725 #define QM_REG_PTRTBL_EXT_A                                      0x16e200
3726 /* [RW 2] Interrupt mask register #0 read/write */
3727 #define QM_REG_QM_INT_MASK                                       0x168444
3728 /* [R 2] Interrupt register #0 read */
3729 #define QM_REG_QM_INT_STS                                        0x168438
3730 /* [RW 12] Parity mask register #0 read/write */
3731 #define QM_REG_QM_PRTY_MASK                                      0x168454
3732 /* [R 12] Parity register #0 read */
3733 #define QM_REG_QM_PRTY_STS                                       0x168448
3734 /* [RC 12] Parity register #0 read clear */
3735 #define QM_REG_QM_PRTY_STS_CLR                                   0x16844c
3736 /* [R 32] Current queues in pipeline: Queues from 32 to 63 */
3737 #define QM_REG_QSTATUS_HIGH                                      0x16802c
3738 /* [R 32] Current queues in pipeline: Queues from 96 to 127 */
3739 #define QM_REG_QSTATUS_HIGH_EXT_A                                0x16e408
3740 /* [R 32] Current queues in pipeline: Queues from 0 to 31 */
3741 #define QM_REG_QSTATUS_LOW                                       0x168028
3742 /* [R 32] Current queues in pipeline: Queues from 64 to 95 */
3743 #define QM_REG_QSTATUS_LOW_EXT_A                                 0x16e404
3744 /* [R 24] The number of tasks queued for each queue; queues 63-0 */
3745 #define QM_REG_QTASKCTR_0                                        0x168308
3746 /* [R 24] The number of tasks queued for each queue; queues 127-64 */
3747 #define QM_REG_QTASKCTR_EXT_A_0                                  0x16e584
3748 /* [RW 4] Queue tied to VOQ */
3749 #define QM_REG_QVOQIDX_0                                         0x1680f4
3750 #define QM_REG_QVOQIDX_10                                        0x16811c
3751 #define QM_REG_QVOQIDX_100                                       0x16e49c
3752 #define QM_REG_QVOQIDX_101                                       0x16e4a0
3753 #define QM_REG_QVOQIDX_102                                       0x16e4a4
3754 #define QM_REG_QVOQIDX_103                                       0x16e4a8
3755 #define QM_REG_QVOQIDX_104                                       0x16e4ac
3756 #define QM_REG_QVOQIDX_105                                       0x16e4b0
3757 #define QM_REG_QVOQIDX_106                                       0x16e4b4
3758 #define QM_REG_QVOQIDX_107                                       0x16e4b8
3759 #define QM_REG_QVOQIDX_108                                       0x16e4bc
3760 #define QM_REG_QVOQIDX_109                                       0x16e4c0
3761 #define QM_REG_QVOQIDX_11                                        0x168120
3762 #define QM_REG_QVOQIDX_110                                       0x16e4c4
3763 #define QM_REG_QVOQIDX_111                                       0x16e4c8
3764 #define QM_REG_QVOQIDX_112                                       0x16e4cc
3765 #define QM_REG_QVOQIDX_113                                       0x16e4d0
3766 #define QM_REG_QVOQIDX_114                                       0x16e4d4
3767 #define QM_REG_QVOQIDX_115                                       0x16e4d8
3768 #define QM_REG_QVOQIDX_116                                       0x16e4dc
3769 #define QM_REG_QVOQIDX_117                                       0x16e4e0
3770 #define QM_REG_QVOQIDX_118                                       0x16e4e4
3771 #define QM_REG_QVOQIDX_119                                       0x16e4e8
3772 #define QM_REG_QVOQIDX_12                                        0x168124
3773 #define QM_REG_QVOQIDX_120                                       0x16e4ec
3774 #define QM_REG_QVOQIDX_121                                       0x16e4f0
3775 #define QM_REG_QVOQIDX_122                                       0x16e4f4
3776 #define QM_REG_QVOQIDX_123                                       0x16e4f8
3777 #define QM_REG_QVOQIDX_124                                       0x16e4fc
3778 #define QM_REG_QVOQIDX_125                                       0x16e500
3779 #define QM_REG_QVOQIDX_126                                       0x16e504
3780 #define QM_REG_QVOQIDX_127                                       0x16e508
3781 #define QM_REG_QVOQIDX_13                                        0x168128
3782 #define QM_REG_QVOQIDX_14                                        0x16812c
3783 #define QM_REG_QVOQIDX_15                                        0x168130
3784 #define QM_REG_QVOQIDX_16                                        0x168134
3785 #define QM_REG_QVOQIDX_17                                        0x168138
3786 #define QM_REG_QVOQIDX_21                                        0x168148
3787 #define QM_REG_QVOQIDX_22                                        0x16814c
3788 #define QM_REG_QVOQIDX_23                                        0x168150
3789 #define QM_REG_QVOQIDX_24                                        0x168154
3790 #define QM_REG_QVOQIDX_25                                        0x168158
3791 #define QM_REG_QVOQIDX_26                                        0x16815c
3792 #define QM_REG_QVOQIDX_27                                        0x168160
3793 #define QM_REG_QVOQIDX_28                                        0x168164
3794 #define QM_REG_QVOQIDX_29                                        0x168168
3795 #define QM_REG_QVOQIDX_30                                        0x16816c
3796 #define QM_REG_QVOQIDX_31                                        0x168170
3797 #define QM_REG_QVOQIDX_32                                        0x168174
3798 #define QM_REG_QVOQIDX_33                                        0x168178
3799 #define QM_REG_QVOQIDX_34                                        0x16817c
3800 #define QM_REG_QVOQIDX_35                                        0x168180
3801 #define QM_REG_QVOQIDX_36                                        0x168184
3802 #define QM_REG_QVOQIDX_37                                        0x168188
3803 #define QM_REG_QVOQIDX_38                                        0x16818c
3804 #define QM_REG_QVOQIDX_39                                        0x168190
3805 #define QM_REG_QVOQIDX_40                                        0x168194
3806 #define QM_REG_QVOQIDX_41                                        0x168198
3807 #define QM_REG_QVOQIDX_42                                        0x16819c
3808 #define QM_REG_QVOQIDX_43                                        0x1681a0
3809 #define QM_REG_QVOQIDX_44                                        0x1681a4
3810 #define QM_REG_QVOQIDX_45                                        0x1681a8
3811 #define QM_REG_QVOQIDX_46                                        0x1681ac
3812 #define QM_REG_QVOQIDX_47                                        0x1681b0
3813 #define QM_REG_QVOQIDX_48                                        0x1681b4
3814 #define QM_REG_QVOQIDX_49                                        0x1681b8
3815 #define QM_REG_QVOQIDX_5                                         0x168108
3816 #define QM_REG_QVOQIDX_50                                        0x1681bc
3817 #define QM_REG_QVOQIDX_51                                        0x1681c0
3818 #define QM_REG_QVOQIDX_52                                        0x1681c4
3819 #define QM_REG_QVOQIDX_53                                        0x1681c8
3820 #define QM_REG_QVOQIDX_54                                        0x1681cc
3821 #define QM_REG_QVOQIDX_55                                        0x1681d0
3822 #define QM_REG_QVOQIDX_56                                        0x1681d4
3823 #define QM_REG_QVOQIDX_57                                        0x1681d8
3824 #define QM_REG_QVOQIDX_58                                        0x1681dc
3825 #define QM_REG_QVOQIDX_59                                        0x1681e0
3826 #define QM_REG_QVOQIDX_6                                         0x16810c
3827 #define QM_REG_QVOQIDX_60                                        0x1681e4
3828 #define QM_REG_QVOQIDX_61                                        0x1681e8
3829 #define QM_REG_QVOQIDX_62                                        0x1681ec
3830 #define QM_REG_QVOQIDX_63                                        0x1681f0
3831 #define QM_REG_QVOQIDX_64                                        0x16e40c
3832 #define QM_REG_QVOQIDX_65                                        0x16e410
3833 #define QM_REG_QVOQIDX_69                                        0x16e420
3834 #define QM_REG_QVOQIDX_7                                         0x168110
3835 #define QM_REG_QVOQIDX_70                                        0x16e424
3836 #define QM_REG_QVOQIDX_71                                        0x16e428
3837 #define QM_REG_QVOQIDX_72                                        0x16e42c
3838 #define QM_REG_QVOQIDX_73                                        0x16e430
3839 #define QM_REG_QVOQIDX_74                                        0x16e434
3840 #define QM_REG_QVOQIDX_75                                        0x16e438
3841 #define QM_REG_QVOQIDX_76                                        0x16e43c
3842 #define QM_REG_QVOQIDX_77                                        0x16e440
3843 #define QM_REG_QVOQIDX_78                                        0x16e444
3844 #define QM_REG_QVOQIDX_79                                        0x16e448
3845 #define QM_REG_QVOQIDX_8                                         0x168114
3846 #define QM_REG_QVOQIDX_80                                        0x16e44c
3847 #define QM_REG_QVOQIDX_81                                        0x16e450
3848 #define QM_REG_QVOQIDX_85                                        0x16e460
3849 #define QM_REG_QVOQIDX_86                                        0x16e464
3850 #define QM_REG_QVOQIDX_87                                        0x16e468
3851 #define QM_REG_QVOQIDX_88                                        0x16e46c
3852 #define QM_REG_QVOQIDX_89                                        0x16e470
3853 #define QM_REG_QVOQIDX_9                                         0x168118
3854 #define QM_REG_QVOQIDX_90                                        0x16e474
3855 #define QM_REG_QVOQIDX_91                                        0x16e478
3856 #define QM_REG_QVOQIDX_92                                        0x16e47c
3857 #define QM_REG_QVOQIDX_93                                        0x16e480
3858 #define QM_REG_QVOQIDX_94                                        0x16e484
3859 #define QM_REG_QVOQIDX_95                                        0x16e488
3860 #define QM_REG_QVOQIDX_96                                        0x16e48c
3861 #define QM_REG_QVOQIDX_97                                        0x16e490
3862 #define QM_REG_QVOQIDX_98                                        0x16e494
3863 #define QM_REG_QVOQIDX_99                                        0x16e498
3864 /* [RW 1] Initialization bit command */
3865 #define QM_REG_SOFT_RESET                                        0x168428
3866 /* [RW 8] The credit cost per every task in the QM. A value per each VOQ */
3867 #define QM_REG_TASKCRDCOST_0                                     0x16809c
3868 #define QM_REG_TASKCRDCOST_1                                     0x1680a0
3869 #define QM_REG_TASKCRDCOST_2                                     0x1680a4
3870 #define QM_REG_TASKCRDCOST_4                                     0x1680ac
3871 #define QM_REG_TASKCRDCOST_5                                     0x1680b0
3872 /* [R 6] Keep the fill level of the fifo from write client 3 */
3873 #define QM_REG_TQM_WRC_FIFOLVL                                   0x168010
3874 /* [R 6] Keep the fill level of the fifo from write client 2 */
3875 #define QM_REG_UQM_WRC_FIFOLVL                                   0x168008
3876 /* [RC 32] Credit update error register */
3877 #define QM_REG_VOQCRDERRREG                                      0x168408
3878 /* [R 16] The credit value for each VOQ */
3879 #define QM_REG_VOQCREDIT_0                                       0x1682d0
3880 #define QM_REG_VOQCREDIT_1                                       0x1682d4
3881 #define QM_REG_VOQCREDIT_4                                       0x1682e0
3882 /* [RW 16] The credit value that if above the QM is considered almost full */
3883 #define QM_REG_VOQCREDITAFULLTHR                                 0x168090
3884 /* [RW 16] The init and maximum credit for each VoQ */
3885 #define QM_REG_VOQINITCREDIT_0                                   0x168060
3886 #define QM_REG_VOQINITCREDIT_1                                   0x168064
3887 #define QM_REG_VOQINITCREDIT_2                                   0x168068
3888 #define QM_REG_VOQINITCREDIT_4                                   0x168070
3889 #define QM_REG_VOQINITCREDIT_5                                   0x168074
3890 /* [RW 1] The port of which VOQ belongs */
3891 #define QM_REG_VOQPORT_0                                         0x1682a0
3892 #define QM_REG_VOQPORT_1                                         0x1682a4
3893 #define QM_REG_VOQPORT_2                                         0x1682a8
3894 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3895 #define QM_REG_VOQQMASK_0_LSB                                    0x168240
3896 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3897 #define QM_REG_VOQQMASK_0_LSB_EXT_A                              0x16e524
3898 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3899 #define QM_REG_VOQQMASK_0_MSB                                    0x168244
3900 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3901 #define QM_REG_VOQQMASK_0_MSB_EXT_A                              0x16e528
3902 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3903 #define QM_REG_VOQQMASK_10_LSB                                   0x168290
3904 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3905 #define QM_REG_VOQQMASK_10_LSB_EXT_A                             0x16e574
3906 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3907 #define QM_REG_VOQQMASK_10_MSB                                   0x168294
3908 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3909 #define QM_REG_VOQQMASK_10_MSB_EXT_A                             0x16e578
3910 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3911 #define QM_REG_VOQQMASK_11_LSB                                   0x168298
3912 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3913 #define QM_REG_VOQQMASK_11_LSB_EXT_A                             0x16e57c
3914 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3915 #define QM_REG_VOQQMASK_11_MSB                                   0x16829c
3916 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3917 #define QM_REG_VOQQMASK_11_MSB_EXT_A                             0x16e580
3918 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3919 #define QM_REG_VOQQMASK_1_LSB                                    0x168248
3920 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3921 #define QM_REG_VOQQMASK_1_LSB_EXT_A                              0x16e52c
3922 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3923 #define QM_REG_VOQQMASK_1_MSB                                    0x16824c
3924 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3925 #define QM_REG_VOQQMASK_1_MSB_EXT_A                              0x16e530
3926 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3927 #define QM_REG_VOQQMASK_2_LSB                                    0x168250
3928 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3929 #define QM_REG_VOQQMASK_2_LSB_EXT_A                              0x16e534
3930 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3931 #define QM_REG_VOQQMASK_2_MSB                                    0x168254
3932 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3933 #define QM_REG_VOQQMASK_2_MSB_EXT_A                              0x16e538
3934 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3935 #define QM_REG_VOQQMASK_3_LSB                                    0x168258
3936 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3937 #define QM_REG_VOQQMASK_3_LSB_EXT_A                              0x16e53c
3938 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3939 #define QM_REG_VOQQMASK_3_MSB_EXT_A                              0x16e540
3940 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3941 #define QM_REG_VOQQMASK_4_LSB                                    0x168260
3942 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3943 #define QM_REG_VOQQMASK_4_LSB_EXT_A                              0x16e544
3944 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3945 #define QM_REG_VOQQMASK_4_MSB                                    0x168264
3946 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3947 #define QM_REG_VOQQMASK_4_MSB_EXT_A                              0x16e548
3948 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3949 #define QM_REG_VOQQMASK_5_LSB                                    0x168268
3950 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3951 #define QM_REG_VOQQMASK_5_LSB_EXT_A                              0x16e54c
3952 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3953 #define QM_REG_VOQQMASK_5_MSB                                    0x16826c
3954 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3955 #define QM_REG_VOQQMASK_5_MSB_EXT_A                              0x16e550
3956 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3957 #define QM_REG_VOQQMASK_6_LSB                                    0x168270
3958 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3959 #define QM_REG_VOQQMASK_6_LSB_EXT_A                              0x16e554
3960 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3961 #define QM_REG_VOQQMASK_6_MSB                                    0x168274
3962 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3963 #define QM_REG_VOQQMASK_6_MSB_EXT_A                              0x16e558
3964 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3965 #define QM_REG_VOQQMASK_7_LSB                                    0x168278
3966 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3967 #define QM_REG_VOQQMASK_7_LSB_EXT_A                              0x16e55c
3968 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3969 #define QM_REG_VOQQMASK_7_MSB                                    0x16827c
3970 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3971 #define QM_REG_VOQQMASK_7_MSB_EXT_A                              0x16e560
3972 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3973 #define QM_REG_VOQQMASK_8_LSB                                    0x168280
3974 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3975 #define QM_REG_VOQQMASK_8_LSB_EXT_A                              0x16e564
3976 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3977 #define QM_REG_VOQQMASK_8_MSB                                    0x168284
3978 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3979 #define QM_REG_VOQQMASK_8_MSB_EXT_A                              0x16e568
3980 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3981 #define QM_REG_VOQQMASK_9_LSB                                    0x168288
3982 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3983 #define QM_REG_VOQQMASK_9_LSB_EXT_A                              0x16e56c
3984 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3985 #define QM_REG_VOQQMASK_9_MSB_EXT_A                              0x16e570
3986 /* [RW 32] Wrr weights */
3987 #define QM_REG_WRRWEIGHTS_0                                      0x16880c
3988 #define QM_REG_WRRWEIGHTS_1                                      0x168810
3989 #define QM_REG_WRRWEIGHTS_10                                     0x168814
3990 #define QM_REG_WRRWEIGHTS_11                                     0x168818
3991 #define QM_REG_WRRWEIGHTS_12                                     0x16881c
3992 #define QM_REG_WRRWEIGHTS_13                                     0x168820
3993 #define QM_REG_WRRWEIGHTS_14                                     0x168824
3994 #define QM_REG_WRRWEIGHTS_15                                     0x168828
3995 #define QM_REG_WRRWEIGHTS_16                                     0x16e000
3996 #define QM_REG_WRRWEIGHTS_17                                     0x16e004
3997 #define QM_REG_WRRWEIGHTS_18                                     0x16e008
3998 #define QM_REG_WRRWEIGHTS_19                                     0x16e00c
3999 #define QM_REG_WRRWEIGHTS_2                                      0x16882c
4000 #define QM_REG_WRRWEIGHTS_20                                     0x16e010
4001 #define QM_REG_WRRWEIGHTS_21                                     0x16e014
4002 #define QM_REG_WRRWEIGHTS_22                                     0x16e018
4003 #define QM_REG_WRRWEIGHTS_23                                     0x16e01c
4004 #define QM_REG_WRRWEIGHTS_24                                     0x16e020
4005 #define QM_REG_WRRWEIGHTS_25                                     0x16e024
4006 #define QM_REG_WRRWEIGHTS_26                                     0x16e028
4007 #define QM_REG_WRRWEIGHTS_27                                     0x16e02c
4008 #define QM_REG_WRRWEIGHTS_28                                     0x16e030
4009 #define QM_REG_WRRWEIGHTS_29                                     0x16e034
4010 #define QM_REG_WRRWEIGHTS_3                                      0x168830
4011 #define QM_REG_WRRWEIGHTS_30                                     0x16e038
4012 #define QM_REG_WRRWEIGHTS_31                                     0x16e03c
4013 #define QM_REG_WRRWEIGHTS_4                                      0x168834
4014 #define QM_REG_WRRWEIGHTS_5                                      0x168838
4015 #define QM_REG_WRRWEIGHTS_6                                      0x16883c
4016 #define QM_REG_WRRWEIGHTS_7                                      0x168840
4017 #define QM_REG_WRRWEIGHTS_8                                      0x168844
4018 #define QM_REG_WRRWEIGHTS_9                                      0x168848
4019 /* [R 6] Keep the fill level of the fifo from write client 1 */
4020 #define QM_REG_XQM_WRC_FIFOLVL                                   0x168000
4021 /* [W 1] reset to parity interrupt */
4022 #define SEM_FAST_REG_PARITY_RST                                  0x18840
4023 #define SRC_REG_COUNTFREE0                                       0x40500
4024 /* [RW 1] If clr the searcher is compatible to E1 A0 - support only two
4025    ports. If set the searcher support 8 functions. */
4026 #define SRC_REG_E1HMF_ENABLE                                     0x404cc
4027 #define SRC_REG_FIRSTFREE0                                       0x40510
4028 #define SRC_REG_KEYRSS0_0                                        0x40408
4029 #define SRC_REG_KEYRSS0_7                                        0x40424
4030 #define SRC_REG_KEYRSS1_9                                        0x40454
4031 #define SRC_REG_KEYSEARCH_0                                      0x40458
4032 #define SRC_REG_KEYSEARCH_1                                      0x4045c
4033 #define SRC_REG_KEYSEARCH_2                                      0x40460
4034 #define SRC_REG_KEYSEARCH_3                                      0x40464
4035 #define SRC_REG_KEYSEARCH_4                                      0x40468
4036 #define SRC_REG_KEYSEARCH_5                                      0x4046c
4037 #define SRC_REG_KEYSEARCH_6                                      0x40470
4038 #define SRC_REG_KEYSEARCH_7                                      0x40474
4039 #define SRC_REG_KEYSEARCH_8                                      0x40478
4040 #define SRC_REG_KEYSEARCH_9                                      0x4047c
4041 #define SRC_REG_LASTFREE0                                        0x40530
4042 #define SRC_REG_NUMBER_HASH_BITS0                                0x40400
4043 /* [RW 1] Reset internal state machines. */
4044 #define SRC_REG_SOFT_RST                                         0x4049c
4045 /* [R 3] Interrupt register #0 read */
4046 #define SRC_REG_SRC_INT_STS                                      0x404ac
4047 /* [RW 3] Parity mask register #0 read/write */
4048 #define SRC_REG_SRC_PRTY_MASK                                    0x404c8
4049 /* [R 3] Parity register #0 read */
4050 #define SRC_REG_SRC_PRTY_STS                                     0x404bc
4051 /* [RC 3] Parity register #0 read clear */
4052 #define SRC_REG_SRC_PRTY_STS_CLR                                 0x404c0
4053 /* [R 4] Used to read the value of the XX protection CAM occupancy counter. */
4054 #define TCM_REG_CAM_OCCUP                                        0x5017c
4055 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
4056    disregarded; valid output is deasserted; all other signals are treated as
4057    usual; if 1 - normal activity. */
4058 #define TCM_REG_CDU_AG_RD_IFEN                                   0x50034
4059 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
4060    are disregarded; all other signals are treated as usual; if 1 - normal
4061    activity. */
4062 #define TCM_REG_CDU_AG_WR_IFEN                                   0x50030
4063 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
4064    disregarded; valid output is deasserted; all other signals are treated as
4065    usual; if 1 - normal activity. */
4066 #define TCM_REG_CDU_SM_RD_IFEN                                   0x5003c
4067 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
4068    input is disregarded; all other signals are treated as usual; if 1 -
4069    normal activity. */
4070 #define TCM_REG_CDU_SM_WR_IFEN                                   0x50038
4071 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
4072    the initial credit value; read returns the current value of the credit
4073    counter. Must be initialized to 1 at start-up. */
4074 #define TCM_REG_CFC_INIT_CRD                                     0x50204
4075 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
4076    weight 8 (the most prioritised); 1 stands for weight 1(least
4077    prioritised); 2 stands for weight 2; tc. */
4078 #define TCM_REG_CP_WEIGHT                                        0x500c0
4079 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
4080    disregarded; acknowledge output is deasserted; all other signals are
4081    treated as usual; if 1 - normal activity. */
4082 #define TCM_REG_CSEM_IFEN                                        0x5002c
4083 /* [RC 1] Message length mismatch (relative to last indication) at the In#9
4084    interface. */
4085 #define TCM_REG_CSEM_LENGTH_MIS                                  0x50174
4086 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
4087    weight 8 (the most prioritised); 1 stands for weight 1(least
4088    prioritised); 2 stands for weight 2; tc. */
4089 #define TCM_REG_CSEM_WEIGHT                                      0x500bc
4090 /* [RW 8] The Event ID in case of ErrorFlg is set in the input message. */
4091 #define TCM_REG_ERR_EVNT_ID                                      0x500a0
4092 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
4093 #define TCM_REG_ERR_TCM_HDR                                      0x5009c
4094 /* [RW 8] The Event ID for Timers expiration. */
4095 #define TCM_REG_EXPR_EVNT_ID                                     0x500a4
4096 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
4097    writes the initial credit value; read returns the current value of the
4098    credit counter. Must be initialized to 64 at start-up. */
4099 #define TCM_REG_FIC0_INIT_CRD                                    0x5020c
4100 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
4101    writes the initial credit value; read returns the current value of the
4102    credit counter. Must be initialized to 64 at start-up. */
4103 #define TCM_REG_FIC1_INIT_CRD                                    0x50210
4104 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
4105    - strict priority defined by ~tcm_registers_gr_ag_pr.gr_ag_pr;
4106    ~tcm_registers_gr_ld0_pr.gr_ld0_pr and
4107    ~tcm_registers_gr_ld1_pr.gr_ld1_pr. */
4108 #define TCM_REG_GR_ARB_TYPE                                      0x50114
4109 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
4110    highest priority is 3. It is supposed that the Store channel is the
4111    compliment of the other 3 groups. */
4112 #define TCM_REG_GR_LD0_PR                                        0x5011c
4113 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
4114    highest priority is 3. It is supposed that the Store channel is the
4115    compliment of the other 3 groups. */
4116 #define TCM_REG_GR_LD1_PR                                        0x50120
4117 /* [RW 4] The number of double REG-pairs; loaded from the STORM context and
4118    sent to STORM; for a specific connection type. The double REG-pairs are
4119    used to align to STORM context row size of 128 bits. The offset of these
4120    data in the STORM context is always 0. Index _i stands for the connection
4121    type (one of 16). */
4122 #define TCM_REG_N_SM_CTX_LD_0                                    0x50050
4123 #define TCM_REG_N_SM_CTX_LD_1                                    0x50054
4124 #define TCM_REG_N_SM_CTX_LD_2                                    0x50058
4125 #define TCM_REG_N_SM_CTX_LD_3                                    0x5005c
4126 #define TCM_REG_N_SM_CTX_LD_4                                    0x50060
4127 #define TCM_REG_N_SM_CTX_LD_5                                    0x50064
4128 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
4129    acknowledge output is deasserted; all other signals are treated as usual;
4130    if 1 - normal activity. */
4131 #define TCM_REG_PBF_IFEN                                         0x50024
4132 /* [RC 1] Message length mismatch (relative to last indication) at the In#7
4133    interface. */
4134 #define TCM_REG_PBF_LENGTH_MIS                                   0x5016c
4135 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
4136    weight 8 (the most prioritised); 1 stands for weight 1(least
4137    prioritised); 2 stands for weight 2; tc. */
4138 #define TCM_REG_PBF_WEIGHT                                       0x500b4
4139 #define TCM_REG_PHYS_QNUM0_0                                     0x500e0
4140 #define TCM_REG_PHYS_QNUM0_1                                     0x500e4
4141 #define TCM_REG_PHYS_QNUM1_0                                     0x500e8
4142 #define TCM_REG_PHYS_QNUM1_1                                     0x500ec
4143 #define TCM_REG_PHYS_QNUM2_0                                     0x500f0
4144 #define TCM_REG_PHYS_QNUM2_1                                     0x500f4
4145 #define TCM_REG_PHYS_QNUM3_0                                     0x500f8
4146 #define TCM_REG_PHYS_QNUM3_1                                     0x500fc
4147 /* [RW 1] Input prs Interface enable. If 0 - the valid input is disregarded;
4148    acknowledge output is deasserted; all other signals are treated as usual;
4149    if 1 - normal activity. */
4150 #define TCM_REG_PRS_IFEN                                         0x50020
4151 /* [RC 1] Message length mismatch (relative to last indication) at the In#6
4152    interface. */
4153 #define TCM_REG_PRS_LENGTH_MIS                                   0x50168
4154 /* [RW 3] The weight of the input prs in the WRR mechanism. 0 stands for
4155    weight 8 (the most prioritised); 1 stands for weight 1(least
4156    prioritised); 2 stands for weight 2; tc. */
4157 #define TCM_REG_PRS_WEIGHT                                       0x500b0
4158 /* [RW 8] The Event ID for Timers formatting in case of stop done. */
4159 #define TCM_REG_STOP_EVNT_ID                                     0x500a8
4160 /* [RC 1] Message length mismatch (relative to last indication) at the STORM
4161    interface. */
4162 #define TCM_REG_STORM_LENGTH_MIS                                 0x50160
4163 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
4164    disregarded; acknowledge output is deasserted; all other signals are
4165    treated as usual; if 1 - normal activity. */
4166 #define TCM_REG_STORM_TCM_IFEN                                   0x50010
4167 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
4168    weight 8 (the most prioritised); 1 stands for weight 1(least
4169    prioritised); 2 stands for weight 2; tc. */
4170 #define TCM_REG_STORM_WEIGHT                                     0x500ac
4171 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
4172    acknowledge output is deasserted; all other signals are treated as usual;
4173    if 1 - normal activity. */
4174 #define TCM_REG_TCM_CFC_IFEN                                     0x50040
4175 /* [RW 11] Interrupt mask register #0 read/write */
4176 #define TCM_REG_TCM_INT_MASK                                     0x501dc
4177 /* [R 11] Interrupt register #0 read */
4178 #define TCM_REG_TCM_INT_STS                                      0x501d0
4179 /* [RW 27] Parity mask register #0 read/write */
4180 #define TCM_REG_TCM_PRTY_MASK                                    0x501ec
4181 /* [R 27] Parity register #0 read */
4182 #define TCM_REG_TCM_PRTY_STS                                     0x501e0
4183 /* [RC 27] Parity register #0 read clear */
4184 #define TCM_REG_TCM_PRTY_STS_CLR                                 0x501e4
4185 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
4186    REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
4187    Is used to determine the number of the AG context REG-pairs written back;
4188    when the input message Reg1WbFlg isn't set. */
4189 #define TCM_REG_TCM_REG0_SZ                                      0x500d8
4190 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
4191    disregarded; valid is deasserted; all other signals are treated as usual;
4192    if 1 - normal activity. */
4193 #define TCM_REG_TCM_STORM0_IFEN                                  0x50004
4194 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
4195    disregarded; valid is deasserted; all other signals are treated as usual;
4196    if 1 - normal activity. */
4197 #define TCM_REG_TCM_STORM1_IFEN                                  0x50008
4198 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
4199    disregarded; valid is deasserted; all other signals are treated as usual;
4200    if 1 - normal activity. */
4201 #define TCM_REG_TCM_TQM_IFEN                                     0x5000c
4202 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
4203 #define TCM_REG_TCM_TQM_USE_Q                                    0x500d4
4204 /* [RW 28] The CM header for Timers expiration command. */
4205 #define TCM_REG_TM_TCM_HDR                                       0x50098
4206 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
4207    disregarded; acknowledge output is deasserted; all other signals are
4208    treated as usual; if 1 - normal activity. */
4209 #define TCM_REG_TM_TCM_IFEN                                      0x5001c
4210 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
4211    weight 8 (the most prioritised); 1 stands for weight 1(least
4212    prioritised); 2 stands for weight 2; tc. */
4213 #define TCM_REG_TM_WEIGHT                                        0x500d0
4214 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
4215    the initial credit value; read returns the current value of the credit
4216    counter. Must be initialized to 32 at start-up. */
4217 #define TCM_REG_TQM_INIT_CRD                                     0x5021c
4218 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
4219    stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4220    prioritised); 2 stands for weight 2; tc. */
4221 #define TCM_REG_TQM_P_WEIGHT                                     0x500c8
4222 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
4223    stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4224    prioritised); 2 stands for weight 2; tc. */
4225 #define TCM_REG_TQM_S_WEIGHT                                     0x500cc
4226 /* [RW 28] The CM header value for QM request (primary). */
4227 #define TCM_REG_TQM_TCM_HDR_P                                    0x50090
4228 /* [RW 28] The CM header value for QM request (secondary). */
4229 #define TCM_REG_TQM_TCM_HDR_S                                    0x50094
4230 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
4231    acknowledge output is deasserted; all other signals are treated as usual;
4232    if 1 - normal activity. */
4233 #define TCM_REG_TQM_TCM_IFEN                                     0x50014
4234 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
4235    acknowledge output is deasserted; all other signals are treated as usual;
4236    if 1 - normal activity. */
4237 #define TCM_REG_TSDM_IFEN                                        0x50018
4238 /* [RC 1] Message length mismatch (relative to last indication) at the SDM
4239    interface. */
4240 #define TCM_REG_TSDM_LENGTH_MIS                                  0x50164
4241 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
4242    weight 8 (the most prioritised); 1 stands for weight 1(least
4243    prioritised); 2 stands for weight 2; tc. */
4244 #define TCM_REG_TSDM_WEIGHT                                      0x500c4
4245 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
4246    disregarded; acknowledge output is deasserted; all other signals are
4247    treated as usual; if 1 - normal activity. */
4248 #define TCM_REG_USEM_IFEN                                        0x50028
4249 /* [RC 1] Message length mismatch (relative to last indication) at the In#8
4250    interface. */
4251 #define TCM_REG_USEM_LENGTH_MIS                                  0x50170
4252 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
4253    weight 8 (the most prioritised); 1 stands for weight 1(least
4254    prioritised); 2 stands for weight 2; tc. */
4255 #define TCM_REG_USEM_WEIGHT                                      0x500b8
4256 /* [RW 21] Indirect access to the descriptor table of the XX protection
4257    mechanism. The fields are: [5:0] - length of the message; 15:6] - message
4258    pointer; 20:16] - next pointer. */
4259 #define TCM_REG_XX_DESCR_TABLE                                   0x50280
4260 #define TCM_REG_XX_DESCR_TABLE_SIZE                              29
4261 /* [R 6] Use to read the value of XX protection Free counter. */
4262 #define TCM_REG_XX_FREE                                          0x50178
4263 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
4264    of the Input Stage XX protection buffer by the XX protection pending
4265    messages. Max credit available - 127.Write writes the initial credit
4266    value; read returns the current value of the credit counter. Must be
4267    initialized to 19 at start-up. */
4268 #define TCM_REG_XX_INIT_CRD                                      0x50220
4269 /* [RW 6] Maximum link list size (messages locked) per connection in the XX
4270    protection. */
4271 #define TCM_REG_XX_MAX_LL_SZ                                     0x50044
4272 /* [RW 6] The maximum number of pending messages; which may be stored in XX
4273    protection. ~tcm_registers_xx_free.xx_free is read on read. */
4274 #define TCM_REG_XX_MSG_NUM                                       0x50224
4275 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
4276 #define TCM_REG_XX_OVFL_EVNT_ID                                  0x50048
4277 /* [RW 16] Indirect access to the XX table of the XX protection mechanism.
4278    The fields are:[4:0] - tail pointer; [10:5] - Link List size; 15:11] -
4279    header pointer. */
4280 #define TCM_REG_XX_TABLE                                         0x50240
4281 /* [RW 4] Load value for cfc ac credit cnt. */
4282 #define TM_REG_CFC_AC_CRDCNT_VAL                                 0x164208
4283 /* [RW 4] Load value for cfc cld credit cnt. */
4284 #define TM_REG_CFC_CLD_CRDCNT_VAL                                0x164210
4285 /* [RW 8] Client0 context region. */
4286 #define TM_REG_CL0_CONT_REGION                                   0x164030
4287 /* [RW 8] Client1 context region. */
4288 #define TM_REG_CL1_CONT_REGION                                   0x164034
4289 /* [RW 8] Client2 context region. */
4290 #define TM_REG_CL2_CONT_REGION                                   0x164038
4291 /* [RW 2] Client in High priority client number. */
4292 #define TM_REG_CLIN_PRIOR0_CLIENT                                0x164024
4293 /* [RW 4] Load value for clout0 cred cnt. */
4294 #define TM_REG_CLOUT_CRDCNT0_VAL                                 0x164220
4295 /* [RW 4] Load value for clout1 cred cnt. */
4296 #define TM_REG_CLOUT_CRDCNT1_VAL                                 0x164228
4297 /* [RW 4] Load value for clout2 cred cnt. */
4298 #define TM_REG_CLOUT_CRDCNT2_VAL                                 0x164230
4299 /* [RW 1] Enable client0 input. */
4300 #define TM_REG_EN_CL0_INPUT                                      0x164008
4301 /* [RW 1] Enable client1 input. */
4302 #define TM_REG_EN_CL1_INPUT                                      0x16400c
4303 /* [RW 1] Enable client2 input. */
4304 #define TM_REG_EN_CL2_INPUT                                      0x164010
4305 #define TM_REG_EN_LINEAR0_TIMER                                  0x164014
4306 /* [RW 1] Enable real time counter. */
4307 #define TM_REG_EN_REAL_TIME_CNT                                  0x1640d8
4308 /* [RW 1] Enable for Timers state machines. */
4309 #define TM_REG_EN_TIMERS                                         0x164000
4310 /* [RW 4] Load value for expiration credit cnt. CFC max number of
4311    outstanding load requests for timers (expiration) context loading. */
4312 #define TM_REG_EXP_CRDCNT_VAL                                    0x164238
4313 /* [RW 32] Linear0 logic address. */
4314 #define TM_REG_LIN0_LOGIC_ADDR                                   0x164240
4315 /* [RW 18] Linear0 Max active cid (in banks of 32 entries). */
4316 #define TM_REG_LIN0_MAX_ACTIVE_CID                               0x164048
4317 /* [ST 16] Linear0 Number of scans counter. */
4318 #define TM_REG_LIN0_NUM_SCANS                                    0x1640a0
4319 /* [WB 64] Linear0 phy address. */
4320 #define TM_REG_LIN0_PHY_ADDR                                     0x164270
4321 /* [RW 1] Linear0 physical address valid. */
4322 #define TM_REG_LIN0_PHY_ADDR_VALID                               0x164248
4323 #define TM_REG_LIN0_SCAN_ON                                      0x1640d0
4324 /* [RW 24] Linear0 array scan timeout. */
4325 #define TM_REG_LIN0_SCAN_TIME                                    0x16403c
4326 #define TM_REG_LIN0_VNIC_UC                                      0x164128
4327 /* [RW 32] Linear1 logic address. */
4328 #define TM_REG_LIN1_LOGIC_ADDR                                   0x164250
4329 /* [WB 64] Linear1 phy address. */
4330 #define TM_REG_LIN1_PHY_ADDR                                     0x164280
4331 /* [RW 1] Linear1 physical address valid. */
4332 #define TM_REG_LIN1_PHY_ADDR_VALID                               0x164258
4333 /* [RW 6] Linear timer set_clear fifo threshold. */
4334 #define TM_REG_LIN_SETCLR_FIFO_ALFULL_THR                        0x164070
4335 /* [RW 2] Load value for pci arbiter credit cnt. */
4336 #define TM_REG_PCIARB_CRDCNT_VAL                                 0x164260
4337 /* [RW 20] The amount of hardware cycles for each timer tick. */
4338 #define TM_REG_TIMER_TICK_SIZE                                   0x16401c
4339 /* [RW 8] Timers Context region. */
4340 #define TM_REG_TM_CONTEXT_REGION                                 0x164044
4341 /* [RW 1] Interrupt mask register #0 read/write */
4342 #define TM_REG_TM_INT_MASK                                       0x1640fc
4343 /* [R 1] Interrupt register #0 read */
4344 #define TM_REG_TM_INT_STS                                        0x1640f0
4345 /* [RW 7] Parity mask register #0 read/write */
4346 #define TM_REG_TM_PRTY_MASK                                      0x16410c
4347 /* [RC 7] Parity register #0 read clear */
4348 #define TM_REG_TM_PRTY_STS_CLR                                   0x164104
4349 /* [RW 8] The event id for aggregated interrupt 0 */
4350 #define TSDM_REG_AGG_INT_EVENT_0                                 0x42038
4351 #define TSDM_REG_AGG_INT_EVENT_1                                 0x4203c
4352 #define TSDM_REG_AGG_INT_EVENT_2                                 0x42040
4353 #define TSDM_REG_AGG_INT_EVENT_3                                 0x42044
4354 #define TSDM_REG_AGG_INT_EVENT_4                                 0x42048
4355 /* [RW 1] The T bit for aggregated interrupt 0 */
4356 #define TSDM_REG_AGG_INT_T_0                                     0x420b8
4357 #define TSDM_REG_AGG_INT_T_1                                     0x420bc
4358 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
4359 #define TSDM_REG_CFC_RSP_START_ADDR                              0x42008
4360 /* [RW 16] The maximum value of the completion counter #0 */
4361 #define TSDM_REG_CMP_COUNTER_MAX0                                0x4201c
4362 /* [RW 16] The maximum value of the completion counter #1 */
4363 #define TSDM_REG_CMP_COUNTER_MAX1                                0x42020
4364 /* [RW 16] The maximum value of the completion counter #2 */
4365 #define TSDM_REG_CMP_COUNTER_MAX2                                0x42024
4366 /* [RW 16] The maximum value of the completion counter #3 */
4367 #define TSDM_REG_CMP_COUNTER_MAX3                                0x42028
4368 /* [RW 13] The start address in the internal RAM for the completion
4369    counters. */
4370 #define TSDM_REG_CMP_COUNTER_START_ADDR                          0x4200c
4371 #define TSDM_REG_ENABLE_IN1                                      0x42238
4372 #define TSDM_REG_ENABLE_IN2                                      0x4223c
4373 #define TSDM_REG_ENABLE_OUT1                                     0x42240
4374 #define TSDM_REG_ENABLE_OUT2                                     0x42244
4375 /* [RW 4] The initial number of messages that can be sent to the pxp control
4376    interface without receiving any ACK. */
4377 #define TSDM_REG_INIT_CREDIT_PXP_CTRL                            0x424bc
4378 /* [ST 32] The number of ACK after placement messages received */
4379 #define TSDM_REG_NUM_OF_ACK_AFTER_PLACE                          0x4227c
4380 /* [ST 32] The number of packet end messages received from the parser */
4381 #define TSDM_REG_NUM_OF_PKT_END_MSG                              0x42274
4382 /* [ST 32] The number of requests received from the pxp async if */
4383 #define TSDM_REG_NUM_OF_PXP_ASYNC_REQ                            0x42278
4384 /* [ST 32] The number of commands received in queue 0 */
4385 #define TSDM_REG_NUM_OF_Q0_CMD                                   0x42248
4386 /* [ST 32] The number of commands received in queue 10 */
4387 #define TSDM_REG_NUM_OF_Q10_CMD                                  0x4226c
4388 /* [ST 32] The number of commands received in queue 11 */
4389 #define TSDM_REG_NUM_OF_Q11_CMD                                  0x42270
4390 /* [ST 32] The number of commands received in queue 1 */
4391 #define TSDM_REG_NUM_OF_Q1_CMD                                   0x4224c
4392 /* [ST 32] The number of commands received in queue 3 */
4393 #define TSDM_REG_NUM_OF_Q3_CMD                                   0x42250
4394 /* [ST 32] The number of commands received in queue 4 */
4395 #define TSDM_REG_NUM_OF_Q4_CMD                                   0x42254
4396 /* [ST 32] The number of commands received in queue 5 */
4397 #define TSDM_REG_NUM_OF_Q5_CMD                                   0x42258
4398 /* [ST 32] The number of commands received in queue 6 */
4399 #define TSDM_REG_NUM_OF_Q6_CMD                                   0x4225c
4400 /* [ST 32] The number of commands received in queue 7 */
4401 #define TSDM_REG_NUM_OF_Q7_CMD                                   0x42260
4402 /* [ST 32] The number of commands received in queue 8 */
4403 #define TSDM_REG_NUM_OF_Q8_CMD                                   0x42264
4404 /* [ST 32] The number of commands received in queue 9 */
4405 #define TSDM_REG_NUM_OF_Q9_CMD                                   0x42268
4406 /* [RW 13] The start address in the internal RAM for the packet end message */
4407 #define TSDM_REG_PCK_END_MSG_START_ADDR                          0x42014
4408 /* [RW 13] The start address in the internal RAM for queue counters */
4409 #define TSDM_REG_Q_COUNTER_START_ADDR                            0x42010
4410 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
4411 #define TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY                        0x42548
4412 /* [R 1] parser fifo empty in sdm_sync block */
4413 #define TSDM_REG_SYNC_PARSER_EMPTY                               0x42550
4414 /* [R 1] parser serial fifo empty in sdm_sync block */
4415 #define TSDM_REG_SYNC_SYNC_EMPTY                                 0x42558
4416 /* [RW 32] Tick for timer counter. Applicable only when
4417    ~tsdm_registers_timer_tick_enable.timer_tick_enable =1 */
4418 #define TSDM_REG_TIMER_TICK                                      0x42000
4419 /* [RW 32] Interrupt mask register #0 read/write */
4420 #define TSDM_REG_TSDM_INT_MASK_0                                 0x4229c
4421 #define TSDM_REG_TSDM_INT_MASK_1                                 0x422ac
4422 /* [R 32] Interrupt register #0 read */
4423 #define TSDM_REG_TSDM_INT_STS_0                                  0x42290
4424 #define TSDM_REG_TSDM_INT_STS_1                                  0x422a0
4425 /* [RW 11] Parity mask register #0 read/write */
4426 #define TSDM_REG_TSDM_PRTY_MASK                                  0x422bc
4427 /* [R 11] Parity register #0 read */
4428 #define TSDM_REG_TSDM_PRTY_STS                                   0x422b0
4429 /* [RC 11] Parity register #0 read clear */
4430 #define TSDM_REG_TSDM_PRTY_STS_CLR                               0x422b4
4431 /* [RW 5] The number of time_slots in the arbitration cycle */
4432 #define TSEM_REG_ARB_CYCLE_SIZE                                  0x180034
4433 /* [RW 3] The source that is associated with arbitration element 0. Source
4434    decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4435    sleeping thread with priority 1; 4- sleeping thread with priority 2 */
4436 #define TSEM_REG_ARB_ELEMENT0                                    0x180020
4437 /* [RW 3] The source that is associated with arbitration element 1. Source
4438    decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4439    sleeping thread with priority 1; 4- sleeping thread with priority 2.
4440    Could not be equal to register ~tsem_registers_arb_element0.arb_element0 */
4441 #define TSEM_REG_ARB_ELEMENT1                                    0x180024
4442 /* [RW 3] The source that is associated with arbitration element 2. Source
4443    decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4444    sleeping thread with priority 1; 4- sleeping thread with priority 2.
4445    Could not be equal to register ~tsem_registers_arb_element0.arb_element0
4446    and ~tsem_registers_arb_element1.arb_element1 */
4447 #define TSEM_REG_ARB_ELEMENT2                                    0x180028
4448 /* [RW 3] The source that is associated with arbitration element 3. Source
4449    decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4450    sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
4451    not be equal to register ~tsem_registers_arb_element0.arb_element0 and
4452    ~tsem_registers_arb_element1.arb_element1 and
4453    ~tsem_registers_arb_element2.arb_element2 */
4454 #define TSEM_REG_ARB_ELEMENT3                                    0x18002c
4455 /* [RW 3] The source that is associated with arbitration element 4. Source
4456    decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4457    sleeping thread with priority 1; 4- sleeping thread with priority 2.
4458    Could not be equal to register ~tsem_registers_arb_element0.arb_element0
4459    and ~tsem_registers_arb_element1.arb_element1 and
4460    ~tsem_registers_arb_element2.arb_element2 and
4461    ~tsem_registers_arb_element3.arb_element3 */
4462 #define TSEM_REG_ARB_ELEMENT4                                    0x180030
4463 #define TSEM_REG_ENABLE_IN                                       0x1800a4
4464 #define TSEM_REG_ENABLE_OUT                                      0x1800a8
4465 /* [RW 32] This address space contains all registers and memories that are
4466    placed in SEM_FAST block. The SEM_FAST registers are described in
4467    appendix B. In order to access the sem_fast registers the base address
4468    ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
4469 #define TSEM_REG_FAST_MEMORY                                     0x1a0000
4470 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
4471    by the microcode */
4472 #define TSEM_REG_FIC0_DISABLE                                    0x180224
4473 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
4474    by the microcode */
4475 #define TSEM_REG_FIC1_DISABLE                                    0x180234
4476 /* [RW 15] Interrupt table Read and write access to it is not possible in
4477    the middle of the work */
4478 #define TSEM_REG_INT_TABLE                                       0x180400
4479 /* [ST 24] Statistics register. The number of messages that entered through
4480    FIC0 */
4481 #define TSEM_REG_MSG_NUM_FIC0                                    0x180000
4482 /* [ST 24] Statistics register. The number of messages that entered through
4483    FIC1 */
4484 #define TSEM_REG_MSG_NUM_FIC1                                    0x180004
4485 /* [ST 24] Statistics register. The number of messages that were sent to
4486    FOC0 */
4487 #define TSEM_REG_MSG_NUM_FOC0                                    0x180008
4488 /* [ST 24] Statistics register. The number of messages that were sent to
4489    FOC1 */
4490 #define TSEM_REG_MSG_NUM_FOC1                                    0x18000c
4491 /* [ST 24] Statistics register. The number of messages that were sent to
4492    FOC2 */
4493 #define TSEM_REG_MSG_NUM_FOC2                                    0x180010
4494 /* [ST 24] Statistics register. The number of messages that were sent to
4495    FOC3 */
4496 #define TSEM_REG_MSG_NUM_FOC3                                    0x180014
4497 /* [RW 1] Disables input messages from the passive buffer May be updated
4498    during run_time by the microcode */
4499 #define TSEM_REG_PAS_DISABLE                                     0x18024c
4500 /* [WB 128] Debug only. Passive buffer memory */
4501 #define TSEM_REG_PASSIVE_BUFFER                                  0x181000
4502 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
4503 #define TSEM_REG_PRAM                                            0x1c0000
4504 /* [R 8] Valid sleeping threads indication have bit per thread */
4505 #define TSEM_REG_SLEEP_THREADS_VALID                             0x18026c
4506 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
4507 #define TSEM_REG_SLOW_EXT_STORE_EMPTY                            0x1802a0
4508 /* [RW 8] List of free threads . There is a bit per thread. */
4509 #define TSEM_REG_THREADS_LIST                                    0x1802e4
4510 /* [RC 32] Parity register #0 read clear */
4511 #define TSEM_REG_TSEM_PRTY_STS_CLR_0                             0x180118
4512 #define TSEM_REG_TSEM_PRTY_STS_CLR_1                             0x180128
4513 /* [RW 3] The arbitration scheme of time_slot 0 */
4514 #define TSEM_REG_TS_0_AS                                         0x180038
4515 /* [RW 3] The arbitration scheme of time_slot 10 */
4516 #define TSEM_REG_TS_10_AS                                        0x180060
4517 /* [RW 3] The arbitration scheme of time_slot 11 */
4518 #define TSEM_REG_TS_11_AS                                        0x180064
4519 /* [RW 3] The arbitration scheme of time_slot 12 */
4520 #define TSEM_REG_TS_12_AS                                        0x180068
4521 /* [RW 3] The arbitration scheme of time_slot 13 */
4522 #define TSEM_REG_TS_13_AS                                        0x18006c
4523 /* [RW 3] The arbitration scheme of time_slot 14 */
4524 #define TSEM_REG_TS_14_AS                                        0x180070
4525 /* [RW 3] The arbitration scheme of time_slot 15 */
4526 #define TSEM_REG_TS_15_AS                                        0x180074
4527 /* [RW 3] The arbitration scheme of time_slot 16 */
4528 #define TSEM_REG_TS_16_AS                                        0x180078
4529 /* [RW 3] The arbitration scheme of time_slot 17 */
4530 #define TSEM_REG_TS_17_AS                                        0x18007c
4531 /* [RW 3] The arbitration scheme of time_slot 18 */
4532 #define TSEM_REG_TS_18_AS                                        0x180080
4533 /* [RW 3] The arbitration scheme of time_slot 1 */
4534 #define TSEM_REG_TS_1_AS                                         0x18003c
4535 /* [RW 3] The arbitration scheme of time_slot 2 */
4536 #define TSEM_REG_TS_2_AS                                         0x180040
4537 /* [RW 3] The arbitration scheme of time_slot 3 */
4538 #define TSEM_REG_TS_3_AS                                         0x180044
4539 /* [RW 3] The arbitration scheme of time_slot 4 */
4540 #define TSEM_REG_TS_4_AS                                         0x180048
4541 /* [RW 3] The arbitration scheme of time_slot 5 */
4542 #define TSEM_REG_TS_5_AS                                         0x18004c
4543 /* [RW 3] The arbitration scheme of time_slot 6 */
4544 #define TSEM_REG_TS_6_AS                                         0x180050
4545 /* [RW 3] The arbitration scheme of time_slot 7 */
4546 #define TSEM_REG_TS_7_AS                                         0x180054
4547 /* [RW 3] The arbitration scheme of time_slot 8 */
4548 #define TSEM_REG_TS_8_AS                                         0x180058
4549 /* [RW 3] The arbitration scheme of time_slot 9 */
4550 #define TSEM_REG_TS_9_AS                                         0x18005c
4551 /* [RW 32] Interrupt mask register #0 read/write */
4552 #define TSEM_REG_TSEM_INT_MASK_0                                 0x180100
4553 #define TSEM_REG_TSEM_INT_MASK_1                                 0x180110
4554 /* [R 32] Interrupt register #0 read */
4555 #define TSEM_REG_TSEM_INT_STS_0                                  0x1800f4
4556 #define TSEM_REG_TSEM_INT_STS_1                                  0x180104
4557 /* [RW 32] Parity mask register #0 read/write */
4558 #define TSEM_REG_TSEM_PRTY_MASK_0                                0x180120
4559 #define TSEM_REG_TSEM_PRTY_MASK_1                                0x180130
4560 /* [R 32] Parity register #0 read */
4561 #define TSEM_REG_TSEM_PRTY_STS_0                                 0x180114
4562 #define TSEM_REG_TSEM_PRTY_STS_1                                 0x180124
4563 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
4564  * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
4565 #define TSEM_REG_VFPF_ERR_NUM                                    0x180380
4566 /* [RW 32] Indirect access to AG context with 32-bits granularity. The bits
4567  * [10:8] of the address should be the offset within the accessed LCID
4568  * context; the bits [7:0] are the accessed LCID.Example: to write to REG10
4569  * LCID100. The RBC address should be 12'ha64. */
4570 #define UCM_REG_AG_CTX                                           0xe2000
4571 /* [R 5] Used to read the XX protection CAM occupancy counter. */
4572 #define UCM_REG_CAM_OCCUP                                        0xe0170
4573 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
4574    disregarded; valid output is deasserted; all other signals are treated as
4575    usual; if 1 - normal activity. */
4576 #define UCM_REG_CDU_AG_RD_IFEN                                   0xe0038
4577 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
4578    are disregarded; all other signals are treated as usual; if 1 - normal
4579    activity. */
4580 #define UCM_REG_CDU_AG_WR_IFEN                                   0xe0034
4581 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
4582    disregarded; valid output is deasserted; all other signals are treated as
4583    usual; if 1 - normal activity. */
4584 #define UCM_REG_CDU_SM_RD_IFEN                                   0xe0040
4585 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
4586    input is disregarded; all other signals are treated as usual; if 1 -
4587    normal activity. */
4588 #define UCM_REG_CDU_SM_WR_IFEN                                   0xe003c
4589 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
4590    the initial credit value; read returns the current value of the credit
4591    counter. Must be initialized to 1 at start-up. */
4592 #define UCM_REG_CFC_INIT_CRD                                     0xe0204
4593 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
4594    weight 8 (the most prioritised); 1 stands for weight 1(least
4595    prioritised); 2 stands for weight 2; tc. */
4596 #define UCM_REG_CP_WEIGHT                                        0xe00c4
4597 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
4598    disregarded; acknowledge output is deasserted; all other signals are
4599    treated as usual; if 1 - normal activity. */
4600 #define UCM_REG_CSEM_IFEN                                        0xe0028
4601 /* [RC 1] Set when the message length mismatch (relative to last indication)
4602    at the csem interface is detected. */
4603 #define UCM_REG_CSEM_LENGTH_MIS                                  0xe0160
4604 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
4605    weight 8 (the most prioritised); 1 stands for weight 1(least
4606    prioritised); 2 stands for weight 2; tc. */
4607 #define UCM_REG_CSEM_WEIGHT                                      0xe00b8
4608 /* [RW 1] Input dorq Interface enable. If 0 - the valid input is
4609    disregarded; acknowledge output is deasserted; all other signals are
4610    treated as usual; if 1 - normal activity. */
4611 #define UCM_REG_DORQ_IFEN                                        0xe0030
4612 /* [RC 1] Set when the message length mismatch (relative to last indication)
4613    at the dorq interface is detected. */
4614 #define UCM_REG_DORQ_LENGTH_MIS                                  0xe0168
4615 /* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for
4616    weight 8 (the most prioritised); 1 stands for weight 1(least
4617    prioritised); 2 stands for weight 2; tc. */
4618 #define UCM_REG_DORQ_WEIGHT                                      0xe00c0
4619 /* [RW 8] The Event ID in case ErrorFlg input message bit is set. */
4620 #define UCM_REG_ERR_EVNT_ID                                      0xe00a4
4621 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
4622 #define UCM_REG_ERR_UCM_HDR                                      0xe00a0
4623 /* [RW 8] The Event ID for Timers expiration. */
4624 #define UCM_REG_EXPR_EVNT_ID                                     0xe00a8
4625 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
4626    writes the initial credit value; read returns the current value of the
4627    credit counter. Must be initialized to 64 at start-up. */
4628 #define UCM_REG_FIC0_INIT_CRD                                    0xe020c
4629 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
4630    writes the initial credit value; read returns the current value of the
4631    credit counter. Must be initialized to 64 at start-up. */
4632 #define UCM_REG_FIC1_INIT_CRD                                    0xe0210
4633 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
4634    - strict priority defined by ~ucm_registers_gr_ag_pr.gr_ag_pr;
4635    ~ucm_registers_gr_ld0_pr.gr_ld0_pr and
4636    ~ucm_registers_gr_ld1_pr.gr_ld1_pr. */
4637 #define UCM_REG_GR_ARB_TYPE                                      0xe0144
4638 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
4639    highest priority is 3. It is supposed that the Store channel group is
4640    compliment to the others. */
4641 #define UCM_REG_GR_LD0_PR                                        0xe014c
4642 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
4643    highest priority is 3. It is supposed that the Store channel group is
4644    compliment to the others. */
4645 #define UCM_REG_GR_LD1_PR                                        0xe0150
4646 /* [RW 2] The queue index for invalidate counter flag decision. */
4647 #define UCM_REG_INV_CFLG_Q                                       0xe00e4
4648 /* [RW 5] The number of double REG-pairs; loaded from the STORM context and
4649    sent to STORM; for a specific connection type. the double REG-pairs are
4650    used in order to align to STORM context row size of 128 bits. The offset
4651    of these data in the STORM context is always 0. Index _i stands for the
4652    connection type (one of 16). */
4653 #define UCM_REG_N_SM_CTX_LD_0                                    0xe0054
4654 #define UCM_REG_N_SM_CTX_LD_1                                    0xe0058
4655 #define UCM_REG_N_SM_CTX_LD_2                                    0xe005c
4656 #define UCM_REG_N_SM_CTX_LD_3                                    0xe0060
4657 #define UCM_REG_N_SM_CTX_LD_4                                    0xe0064
4658 #define UCM_REG_N_SM_CTX_LD_5                                    0xe0068
4659 #define UCM_REG_PHYS_QNUM0_0                                     0xe0110
4660 #define UCM_REG_PHYS_QNUM0_1                                     0xe0114
4661 #define UCM_REG_PHYS_QNUM1_0                                     0xe0118
4662 #define UCM_REG_PHYS_QNUM1_1                                     0xe011c
4663 #define UCM_REG_PHYS_QNUM2_0                                     0xe0120
4664 #define UCM_REG_PHYS_QNUM2_1                                     0xe0124
4665 #define UCM_REG_PHYS_QNUM3_0                                     0xe0128
4666 #define UCM_REG_PHYS_QNUM3_1                                     0xe012c
4667 /* [RW 8] The Event ID for Timers formatting in case of stop done. */
4668 #define UCM_REG_STOP_EVNT_ID                                     0xe00ac
4669 /* [RC 1] Set when the message length mismatch (relative to last indication)
4670    at the STORM interface is detected. */
4671 #define UCM_REG_STORM_LENGTH_MIS                                 0xe0154
4672 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
4673    disregarded; acknowledge output is deasserted; all other signals are
4674    treated as usual; if 1 - normal activity. */
4675 #define UCM_REG_STORM_UCM_IFEN                                   0xe0010
4676 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
4677    weight 8 (the most prioritised); 1 stands for weight 1(least
4678    prioritised); 2 stands for weight 2; tc. */
4679 #define UCM_REG_STORM_WEIGHT                                     0xe00b0
4680 /* [RW 4] Timers output initial credit. Max credit available - 15.Write
4681    writes the initial credit value; read returns the current value of the
4682    credit counter. Must be initialized to 4 at start-up. */
4683 #define UCM_REG_TM_INIT_CRD                                      0xe021c
4684 /* [RW 28] The CM header for Timers expiration command. */
4685 #define UCM_REG_TM_UCM_HDR                                       0xe009c
4686 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
4687    disregarded; acknowledge output is deasserted; all other signals are
4688    treated as usual; if 1 - normal activity. */
4689 #define UCM_REG_TM_UCM_IFEN                                      0xe001c
4690 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
4691    weight 8 (the most prioritised); 1 stands for weight 1(least
4692    prioritised); 2 stands for weight 2; tc. */
4693 #define UCM_REG_TM_WEIGHT                                        0xe00d4
4694 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
4695    disregarded; acknowledge output is deasserted; all other signals are
4696    treated as usual; if 1 - normal activity. */
4697 #define UCM_REG_TSEM_IFEN                                        0xe0024
4698 /* [RC 1] Set when the message length mismatch (relative to last indication)
4699    at the tsem interface is detected. */
4700 #define UCM_REG_TSEM_LENGTH_MIS                                  0xe015c
4701 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
4702    weight 8 (the most prioritised); 1 stands for weight 1(least
4703    prioritised); 2 stands for weight 2; tc. */
4704 #define UCM_REG_TSEM_WEIGHT                                      0xe00b4
4705 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
4706    acknowledge output is deasserted; all other signals are treated as usual;
4707    if 1 - normal activity. */
4708 #define UCM_REG_UCM_CFC_IFEN                                     0xe0044
4709 /* [RW 11] Interrupt mask register #0 read/write */
4710 #define UCM_REG_UCM_INT_MASK                                     0xe01d4
4711 /* [R 11] Interrupt register #0 read */
4712 #define UCM_REG_UCM_INT_STS                                      0xe01c8
4713 /* [RW 27] Parity mask register #0 read/write */
4714 #define UCM_REG_UCM_PRTY_MASK                                    0xe01e4
4715 /* [R 27] Parity register #0 read */
4716 #define UCM_REG_UCM_PRTY_STS                                     0xe01d8
4717 /* [RC 27] Parity register #0 read clear */
4718 #define UCM_REG_UCM_PRTY_STS_CLR                                 0xe01dc
4719 /* [RW 2] The size of AG context region 0 in REG-pairs. Designates the MS
4720    REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
4721    Is used to determine the number of the AG context REG-pairs written back;
4722    when the Reg1WbFlg isn't set. */
4723 #define UCM_REG_UCM_REG0_SZ                                      0xe00dc
4724 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
4725    disregarded; valid is deasserted; all other signals are treated as usual;
4726    if 1 - normal activity. */
4727 #define UCM_REG_UCM_STORM0_IFEN                                  0xe0004
4728 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
4729    disregarded; valid is deasserted; all other signals are treated as usual;
4730    if 1 - normal activity. */
4731 #define UCM_REG_UCM_STORM1_IFEN                                  0xe0008
4732 /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
4733    disregarded; acknowledge output is deasserted; all other signals are
4734    treated as usual; if 1 - normal activity. */
4735 #define UCM_REG_UCM_TM_IFEN                                      0xe0020
4736 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
4737    disregarded; valid is deasserted; all other signals are treated as usual;
4738    if 1 - normal activity. */
4739 #define UCM_REG_UCM_UQM_IFEN                                     0xe000c
4740 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
4741 #define UCM_REG_UCM_UQM_USE_Q                                    0xe00d8
4742 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
4743    the initial credit value; read returns the current value of the credit
4744    counter. Must be initialized to 32 at start-up. */
4745 #define UCM_REG_UQM_INIT_CRD                                     0xe0220
4746 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
4747    stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4748    prioritised); 2 stands for weight 2; tc. */
4749 #define UCM_REG_UQM_P_WEIGHT                                     0xe00cc
4750 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
4751    stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4752    prioritised); 2 stands for weight 2; tc. */
4753 #define UCM_REG_UQM_S_WEIGHT                                     0xe00d0
4754 /* [RW 28] The CM header value for QM request (primary). */
4755 #define UCM_REG_UQM_UCM_HDR_P                                    0xe0094
4756 /* [RW 28] The CM header value for QM request (secondary). */
4757 #define UCM_REG_UQM_UCM_HDR_S                                    0xe0098
4758 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
4759    acknowledge output is deasserted; all other signals are treated as usual;
4760    if 1 - normal activity. */
4761 #define UCM_REG_UQM_UCM_IFEN                                     0xe0014
4762 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
4763    acknowledge output is deasserted; all other signals are treated as usual;
4764    if 1 - normal activity. */
4765 #define UCM_REG_USDM_IFEN                                        0xe0018
4766 /* [RC 1] Set when the message length mismatch (relative to last indication)
4767    at the SDM interface is detected. */
4768 #define UCM_REG_USDM_LENGTH_MIS                                  0xe0158
4769 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
4770    weight 8 (the most prioritised); 1 stands for weight 1(least
4771    prioritised); 2 stands for weight 2; tc. */
4772 #define UCM_REG_USDM_WEIGHT                                      0xe00c8
4773 /* [RW 1] Input xsem Interface enable. If 0 - the valid input is
4774    disregarded; acknowledge output is deasserted; all other signals are
4775    treated as usual; if 1 - normal activity. */
4776 #define UCM_REG_XSEM_IFEN                                        0xe002c
4777 /* [RC 1] Set when the message length mismatch (relative to last indication)
4778    at the xsem interface isdetected. */
4779 #define UCM_REG_XSEM_LENGTH_MIS                                  0xe0164
4780 /* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
4781    weight 8 (the most prioritised); 1 stands for weight 1(least
4782    prioritised); 2 stands for weight 2; tc. */
4783 #define UCM_REG_XSEM_WEIGHT                                      0xe00bc
4784 /* [RW 20] Indirect access to the descriptor table of the XX protection
4785    mechanism. The fields are:[5:0] - message length; 14:6] - message
4786    pointer; 19:15] - next pointer. */
4787 #define UCM_REG_XX_DESCR_TABLE                                   0xe0280
4788 #define UCM_REG_XX_DESCR_TABLE_SIZE                              27
4789 /* [R 6] Use to read the XX protection Free counter. */
4790 #define UCM_REG_XX_FREE                                          0xe016c
4791 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
4792    of the Input Stage XX protection buffer by the XX protection pending
4793    messages. Write writes the initial credit value; read returns the current
4794    value of the credit counter. Must be initialized to 12 at start-up. */
4795 #define UCM_REG_XX_INIT_CRD                                      0xe0224
4796 /* [RW 6] The maximum number of pending messages; which may be stored in XX
4797    protection. ~ucm_registers_xx_free.xx_free read on read. */
4798 #define UCM_REG_XX_MSG_NUM                                       0xe0228
4799 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
4800 #define UCM_REG_XX_OVFL_EVNT_ID                                  0xe004c
4801 /* [RW 16] Indirect access to the XX table of the XX protection mechanism.
4802    The fields are: [4:0] - tail pointer; 10:5] - Link List size; 15:11] -
4803    header pointer. */
4804 #define UCM_REG_XX_TABLE                                         0xe0300
4805 #define UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE                  (0x1<<28)
4806 #define UMAC_COMMAND_CONFIG_REG_LOOP_ENA                         (0x1<<15)
4807 #define UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK                    (0x1<<24)
4808 #define UMAC_COMMAND_CONFIG_REG_PAD_EN                           (0x1<<5)
4809 #define UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE                     (0x1<<8)
4810 #define UMAC_COMMAND_CONFIG_REG_PROMIS_EN                        (0x1<<4)
4811 #define UMAC_COMMAND_CONFIG_REG_RX_ENA                           (0x1<<1)
4812 #define UMAC_COMMAND_CONFIG_REG_SW_RESET                         (0x1<<13)
4813 #define UMAC_COMMAND_CONFIG_REG_TX_ENA                           (0x1<<0)
4814 #define UMAC_REG_COMMAND_CONFIG                                  0x8
4815 /* [RW 32] Register Bit 0 refers to Bit 16 of the MAC address; Bit 1 refers
4816  * to bit 17 of the MAC address etc. */
4817 #define UMAC_REG_MAC_ADDR0                                       0xc
4818 /* [RW 16] Register Bit 0 refers to Bit 0 of the MAC address; Register Bit 1
4819  * refers to Bit 1 of the MAC address etc. Bits 16 to 31 are reserved. */
4820 #define UMAC_REG_MAC_ADDR1                                       0x10
4821 /* [RW 14] Defines a 14-Bit maximum frame length used by the MAC receive
4822  * logic to check frames. */
4823 #define UMAC_REG_MAXFR                                           0x14
4824 /* [RW 8] The event id for aggregated interrupt 0 */
4825 #define USDM_REG_AGG_INT_EVENT_0                                 0xc4038
4826 #define USDM_REG_AGG_INT_EVENT_1                                 0xc403c
4827 #define USDM_REG_AGG_INT_EVENT_2                                 0xc4040
4828 #define USDM_REG_AGG_INT_EVENT_4                                 0xc4048
4829 #define USDM_REG_AGG_INT_EVENT_5                                 0xc404c
4830 #define USDM_REG_AGG_INT_EVENT_6                                 0xc4050
4831 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
4832    or auto-mask-mode (1) */
4833 #define USDM_REG_AGG_INT_MODE_0                                  0xc41b8
4834 #define USDM_REG_AGG_INT_MODE_1                                  0xc41bc
4835 #define USDM_REG_AGG_INT_MODE_4                                  0xc41c8
4836 #define USDM_REG_AGG_INT_MODE_5                                  0xc41cc
4837 #define USDM_REG_AGG_INT_MODE_6                                  0xc41d0
4838 /* [RW 1] The T bit for aggregated interrupt 5 */
4839 #define USDM_REG_AGG_INT_T_5                                     0xc40cc
4840 #define USDM_REG_AGG_INT_T_6                                     0xc40d0
4841 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
4842 #define USDM_REG_CFC_RSP_START_ADDR                              0xc4008
4843 /* [RW 16] The maximum value of the completion counter #0 */
4844 #define USDM_REG_CMP_COUNTER_MAX0                                0xc401c
4845 /* [RW 16] The maximum value of the completion counter #1 */
4846 #define USDM_REG_CMP_COUNTER_MAX1                                0xc4020
4847 /* [RW 16] The maximum value of the completion counter #2 */
4848 #define USDM_REG_CMP_COUNTER_MAX2                                0xc4024
4849 /* [RW 16] The maximum value of the completion counter #3 */
4850 #define USDM_REG_CMP_COUNTER_MAX3                                0xc4028
4851 /* [RW 13] The start address in the internal RAM for the completion
4852    counters. */
4853 #define USDM_REG_CMP_COUNTER_START_ADDR                          0xc400c
4854 #define USDM_REG_ENABLE_IN1                                      0xc4238
4855 #define USDM_REG_ENABLE_IN2                                      0xc423c
4856 #define USDM_REG_ENABLE_OUT1                                     0xc4240
4857 #define USDM_REG_ENABLE_OUT2                                     0xc4244
4858 /* [RW 4] The initial number of messages that can be sent to the pxp control
4859    interface without receiving any ACK. */
4860 #define USDM_REG_INIT_CREDIT_PXP_CTRL                            0xc44c0
4861 /* [ST 32] The number of ACK after placement messages received */
4862 #define USDM_REG_NUM_OF_ACK_AFTER_PLACE                          0xc4280
4863 /* [ST 32] The number of packet end messages received from the parser */
4864 #define USDM_REG_NUM_OF_PKT_END_MSG                              0xc4278
4865 /* [ST 32] The number of requests received from the pxp async if */
4866 #define USDM_REG_NUM_OF_PXP_ASYNC_REQ                            0xc427c
4867 /* [ST 32] The number of commands received in queue 0 */
4868 #define USDM_REG_NUM_OF_Q0_CMD                                   0xc4248
4869 /* [ST 32] The number of commands received in queue 10 */
4870 #define USDM_REG_NUM_OF_Q10_CMD                                  0xc4270
4871 /* [ST 32] The number of commands received in queue 11 */
4872 #define USDM_REG_NUM_OF_Q11_CMD                                  0xc4274
4873 /* [ST 32] The number of commands received in queue 1 */
4874 #define USDM_REG_NUM_OF_Q1_CMD                                   0xc424c
4875 /* [ST 32] The number of commands received in queue 2 */
4876 #define USDM_REG_NUM_OF_Q2_CMD                                   0xc4250
4877 /* [ST 32] The number of commands received in queue 3 */
4878 #define USDM_REG_NUM_OF_Q3_CMD                                   0xc4254
4879 /* [ST 32] The number of commands received in queue 4 */
4880 #define USDM_REG_NUM_OF_Q4_CMD                                   0xc4258
4881 /* [ST 32] The number of commands received in queue 5 */
4882 #define USDM_REG_NUM_OF_Q5_CMD                                   0xc425c
4883 /* [ST 32] The number of commands received in queue 6 */
4884 #define USDM_REG_NUM_OF_Q6_CMD                                   0xc4260
4885 /* [ST 32] The number of commands received in queue 7 */
4886 #define USDM_REG_NUM_OF_Q7_CMD                                   0xc4264
4887 /* [ST 32] The number of commands received in queue 8 */
4888 #define USDM_REG_NUM_OF_Q8_CMD                                   0xc4268
4889 /* [ST 32] The number of commands received in queue 9 */
4890 #define USDM_REG_NUM_OF_Q9_CMD                                   0xc426c
4891 /* [RW 13] The start address in the internal RAM for the packet end message */
4892 #define USDM_REG_PCK_END_MSG_START_ADDR                          0xc4014
4893 /* [RW 13] The start address in the internal RAM for queue counters */
4894 #define USDM_REG_Q_COUNTER_START_ADDR                            0xc4010
4895 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
4896 #define USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY                        0xc4550
4897 /* [R 1] parser fifo empty in sdm_sync block */
4898 #define USDM_REG_SYNC_PARSER_EMPTY                               0xc4558
4899 /* [R 1] parser serial fifo empty in sdm_sync block */
4900 #define USDM_REG_SYNC_SYNC_EMPTY                                 0xc4560
4901 /* [RW 32] Tick for timer counter. Applicable only when
4902    ~usdm_registers_timer_tick_enable.timer_tick_enable =1 */
4903 #define USDM_REG_TIMER_TICK                                      0xc4000
4904 /* [RW 32] Interrupt mask register #0 read/write */
4905 #define USDM_REG_USDM_INT_MASK_0                                 0xc42a0
4906 #define USDM_REG_USDM_INT_MASK_1                                 0xc42b0
4907 /* [R 32] Interrupt register #0 read */
4908 #define USDM_REG_USDM_INT_STS_0                                  0xc4294
4909 #define USDM_REG_USDM_INT_STS_1                                  0xc42a4
4910 /* [RW 11] Parity mask register #0 read/write */
4911 #define USDM_REG_USDM_PRTY_MASK                                  0xc42c0
4912 /* [R 11] Parity register #0 read */
4913 #define USDM_REG_USDM_PRTY_STS                                   0xc42b4
4914 /* [RC 11] Parity register #0 read clear */
4915 #define USDM_REG_USDM_PRTY_STS_CLR                               0xc42b8
4916 /* [RW 5] The number of time_slots in the arbitration cycle */
4917 #define USEM_REG_ARB_CYCLE_SIZE                                  0x300034
4918 /* [RW 3] The source that is associated with arbitration element 0. Source
4919    decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4920    sleeping thread with priority 1; 4- sleeping thread with priority 2 */
4921 #define USEM_REG_ARB_ELEMENT0                                    0x300020
4922 /* [RW 3] The source that is associated with arbitration element 1. Source
4923    decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4924    sleeping thread with priority 1; 4- sleeping thread with priority 2.
4925    Could not be equal to register ~usem_registers_arb_element0.arb_element0 */
4926 #define USEM_REG_ARB_ELEMENT1                                    0x300024
4927 /* [RW 3] The source that is associated with arbitration element 2. Source
4928    decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4929    sleeping thread with priority 1; 4- sleeping thread with priority 2.
4930    Could not be equal to register ~usem_registers_arb_element0.arb_element0
4931    and ~usem_registers_arb_element1.arb_element1 */
4932 #define USEM_REG_ARB_ELEMENT2                                    0x300028
4933 /* [RW 3] The source that is associated with arbitration element 3. Source
4934    decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4935    sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
4936    not be equal to register ~usem_registers_arb_element0.arb_element0 and
4937    ~usem_registers_arb_element1.arb_element1 and
4938    ~usem_registers_arb_element2.arb_element2 */
4939 #define USEM_REG_ARB_ELEMENT3                                    0x30002c
4940 /* [RW 3] The source that is associated with arbitration element 4. Source
4941    decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4942    sleeping thread with priority 1; 4- sleeping thread with priority 2.
4943    Could not be equal to register ~usem_registers_arb_element0.arb_element0
4944    and ~usem_registers_arb_element1.arb_element1 and
4945    ~usem_registers_arb_element2.arb_element2 and
4946    ~usem_registers_arb_element3.arb_element3 */
4947 #define USEM_REG_ARB_ELEMENT4                                    0x300030
4948 #define USEM_REG_ENABLE_IN                                       0x3000a4
4949 #define USEM_REG_ENABLE_OUT                                      0x3000a8
4950 /* [RW 32] This address space contains all registers and memories that are
4951    placed in SEM_FAST block. The SEM_FAST registers are described in
4952    appendix B. In order to access the sem_fast registers the base address
4953    ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
4954 #define USEM_REG_FAST_MEMORY                                     0x320000
4955 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
4956    by the microcode */
4957 #define USEM_REG_FIC0_DISABLE                                    0x300224
4958 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
4959    by the microcode */
4960 #define USEM_REG_FIC1_DISABLE                                    0x300234
4961 /* [RW 15] Interrupt table Read and write access to it is not possible in
4962    the middle of the work */
4963 #define USEM_REG_INT_TABLE                                       0x300400
4964 /* [ST 24] Statistics register. The number of messages that entered through
4965    FIC0 */
4966 #define USEM_REG_MSG_NUM_FIC0                                    0x300000
4967 /* [ST 24] Statistics register. The number of messages that entered through
4968    FIC1 */
4969 #define USEM_REG_MSG_NUM_FIC1                                    0x300004
4970 /* [ST 24] Statistics register. The number of messages that were sent to
4971    FOC0 */
4972 #define USEM_REG_MSG_NUM_FOC0                                    0x300008
4973 /* [ST 24] Statistics register. The number of messages that were sent to
4974    FOC1 */
4975 #define USEM_REG_MSG_NUM_FOC1                                    0x30000c
4976 /* [ST 24] Statistics register. The number of messages that were sent to
4977    FOC2 */
4978 #define USEM_REG_MSG_NUM_FOC2                                    0x300010
4979 /* [ST 24] Statistics register. The number of messages that were sent to
4980    FOC3 */
4981 #define USEM_REG_MSG_NUM_FOC3                                    0x300014
4982 /* [RW 1] Disables input messages from the passive buffer May be updated
4983    during run_time by the microcode */
4984 #define USEM_REG_PAS_DISABLE                                     0x30024c
4985 /* [WB 128] Debug only. Passive buffer memory */
4986 #define USEM_REG_PASSIVE_BUFFER                                  0x302000
4987 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
4988 #define USEM_REG_PRAM                                            0x340000
4989 /* [R 16] Valid sleeping threads indication have bit per thread */
4990 #define USEM_REG_SLEEP_THREADS_VALID                             0x30026c
4991 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
4992 #define USEM_REG_SLOW_EXT_STORE_EMPTY                            0x3002a0
4993 /* [RW 16] List of free threads . There is a bit per thread. */
4994 #define USEM_REG_THREADS_LIST                                    0x3002e4
4995 /* [RW 3] The arbitration scheme of time_slot 0 */
4996 #define USEM_REG_TS_0_AS                                         0x300038
4997 /* [RW 3] The arbitration scheme of time_slot 10 */
4998 #define USEM_REG_TS_10_AS                                        0x300060
4999 /* [RW 3] The arbitration scheme of time_slot 11 */
5000 #define USEM_REG_TS_11_AS                                        0x300064
5001 /* [RW 3] The arbitration scheme of time_slot 12 */
5002 #define USEM_REG_TS_12_AS                                        0x300068
5003 /* [RW 3] The arbitration scheme of time_slot 13 */
5004 #define USEM_REG_TS_13_AS                                        0x30006c
5005 /* [RW 3] The arbitration scheme of time_slot 14 */
5006 #define USEM_REG_TS_14_AS                                        0x300070
5007 /* [RW 3] The arbitration scheme of time_slot 15 */
5008 #define USEM_REG_TS_15_AS                                        0x300074
5009 /* [RW 3] The arbitration scheme of time_slot 16 */
5010 #define USEM_REG_TS_16_AS                                        0x300078
5011 /* [RW 3] The arbitration scheme of time_slot 17 */
5012 #define USEM_REG_TS_17_AS                                        0x30007c
5013 /* [RW 3] The arbitration scheme of time_slot 18 */
5014 #define USEM_REG_TS_18_AS                                        0x300080
5015 /* [RW 3] The arbitration scheme of time_slot 1 */
5016 #define USEM_REG_TS_1_AS                                         0x30003c
5017 /* [RW 3] The arbitration scheme of time_slot 2 */
5018 #define USEM_REG_TS_2_AS                                         0x300040
5019 /* [RW 3] The arbitration scheme of time_slot 3 */
5020 #define USEM_REG_TS_3_AS                                         0x300044
5021 /* [RW 3] The arbitration scheme of time_slot 4 */
5022 #define USEM_REG_TS_4_AS                                         0x300048
5023 /* [RW 3] The arbitration scheme of time_slot 5 */
5024 #define USEM_REG_TS_5_AS                                         0x30004c
5025 /* [RW 3] The arbitration scheme of time_slot 6 */
5026 #define USEM_REG_TS_6_AS                                         0x300050
5027 /* [RW 3] The arbitration scheme of time_slot 7 */
5028 #define USEM_REG_TS_7_AS                                         0x300054
5029 /* [RW 3] The arbitration scheme of time_slot 8 */
5030 #define USEM_REG_TS_8_AS                                         0x300058
5031 /* [RW 3] The arbitration scheme of time_slot 9 */
5032 #define USEM_REG_TS_9_AS                                         0x30005c
5033 /* [RW 32] Interrupt mask register #0 read/write */
5034 #define USEM_REG_USEM_INT_MASK_0                                 0x300110
5035 #define USEM_REG_USEM_INT_MASK_1                                 0x300120
5036 /* [R 32] Interrupt register #0 read */
5037 #define USEM_REG_USEM_INT_STS_0                                  0x300104
5038 #define USEM_REG_USEM_INT_STS_1                                  0x300114
5039 /* [RW 32] Parity mask register #0 read/write */
5040 #define USEM_REG_USEM_PRTY_MASK_0                                0x300130
5041 #define USEM_REG_USEM_PRTY_MASK_1                                0x300140
5042 /* [R 32] Parity register #0 read */
5043 #define USEM_REG_USEM_PRTY_STS_0                                 0x300124
5044 #define USEM_REG_USEM_PRTY_STS_1                                 0x300134
5045 /* [RC 32] Parity register #0 read clear */
5046 #define USEM_REG_USEM_PRTY_STS_CLR_0                             0x300128
5047 #define USEM_REG_USEM_PRTY_STS_CLR_1                             0x300138
5048 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
5049  * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
5050 #define USEM_REG_VFPF_ERR_NUM                                    0x300380
5051 #define VFC_MEMORIES_RST_REG_CAM_RST                             (0x1<<0)
5052 #define VFC_MEMORIES_RST_REG_RAM_RST                             (0x1<<1)
5053 #define VFC_REG_MEMORIES_RST                                     0x1943c
5054 /* [RW 32] Indirect access to AG context with 32-bits granularity. The bits
5055  * [12:8] of the address should be the offset within the accessed LCID
5056  * context; the bits [7:0] are the accessed LCID.Example: to write to REG10
5057  * LCID100. The RBC address should be 13'ha64. */
5058 #define XCM_REG_AG_CTX                                           0x28000
5059 /* [RW 2] The queue index for registration on Aux1 counter flag. */
5060 #define XCM_REG_AUX1_Q                                           0x20134
5061 /* [RW 2] Per each decision rule the queue index to register to. */
5062 #define XCM_REG_AUX_CNT_FLG_Q_19                                 0x201b0
5063 /* [R 5] Used to read the XX protection CAM occupancy counter. */
5064 #define XCM_REG_CAM_OCCUP                                        0x20244
5065 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
5066    disregarded; valid output is deasserted; all other signals are treated as
5067    usual; if 1 - normal activity. */
5068 #define XCM_REG_CDU_AG_RD_IFEN                                   0x20044
5069 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
5070    are disregarded; all other signals are treated as usual; if 1 - normal
5071    activity. */
5072 #define XCM_REG_CDU_AG_WR_IFEN                                   0x20040
5073 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
5074    disregarded; valid output is deasserted; all other signals are treated as
5075    usual; if 1 - normal activity. */
5076 #define XCM_REG_CDU_SM_RD_IFEN                                   0x2004c
5077 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
5078    input is disregarded; all other signals are treated as usual; if 1 -
5079    normal activity. */
5080 #define XCM_REG_CDU_SM_WR_IFEN                                   0x20048
5081 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
5082    the initial credit value; read returns the current value of the credit
5083    counter. Must be initialized to 1 at start-up. */
5084 #define XCM_REG_CFC_INIT_CRD                                     0x20404
5085 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
5086    weight 8 (the most prioritised); 1 stands for weight 1(least
5087    prioritised); 2 stands for weight 2; tc. */
5088 #define XCM_REG_CP_WEIGHT                                        0x200dc
5089 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
5090    disregarded; acknowledge output is deasserted; all other signals are
5091    treated as usual; if 1 - normal activity. */
5092 #define XCM_REG_CSEM_IFEN                                        0x20028
5093 /* [RC 1] Set at message length mismatch (relative to last indication) at
5094    the csem interface. */
5095 #define XCM_REG_CSEM_LENGTH_MIS                                  0x20228
5096 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
5097    weight 8 (the most prioritised); 1 stands for weight 1(least
5098    prioritised); 2 stands for weight 2; tc. */
5099 #define XCM_REG_CSEM_WEIGHT                                      0x200c4
5100 /* [RW 1] Input dorq Interface enable. If 0 - the valid input is
5101    disregarded; acknowledge output is deasserted; all other signals are
5102    treated as usual; if 1 - normal activity. */
5103 #define XCM_REG_DORQ_IFEN                                        0x20030
5104 /* [RC 1] Set at message length mismatch (relative to last indication) at
5105    the dorq interface. */
5106 #define XCM_REG_DORQ_LENGTH_MIS                                  0x20230
5107 /* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for
5108    weight 8 (the most prioritised); 1 stands for weight 1(least
5109    prioritised); 2 stands for weight 2; tc. */
5110 #define XCM_REG_DORQ_WEIGHT                                      0x200cc
5111 /* [RW 8] The Event ID in case the ErrorFlg input message bit is set. */
5112 #define XCM_REG_ERR_EVNT_ID                                      0x200b0
5113 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
5114 #define XCM_REG_ERR_XCM_HDR                                      0x200ac
5115 /* [RW 8] The Event ID for Timers expiration. */
5116 #define XCM_REG_EXPR_EVNT_ID                                     0x200b4
5117 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
5118    writes the initial credit value; read returns the current value of the
5119    credit counter. Must be initialized to 64 at start-up. */
5120 #define XCM_REG_FIC0_INIT_CRD                                    0x2040c
5121 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
5122    writes the initial credit value; read returns the current value of the
5123    credit counter. Must be initialized to 64 at start-up. */
5124 #define XCM_REG_FIC1_INIT_CRD                                    0x20410
5125 #define XCM_REG_GLB_DEL_ACK_MAX_CNT_0                            0x20118
5126 #define XCM_REG_GLB_DEL_ACK_MAX_CNT_1                            0x2011c
5127 #define XCM_REG_GLB_DEL_ACK_TMR_VAL_0                            0x20108
5128 #define XCM_REG_GLB_DEL_ACK_TMR_VAL_1                            0x2010c
5129 /* [RW 1] Arbitratiojn between Input Arbiter groups: 0 - fair Round-Robin; 1
5130    - strict priority defined by ~xcm_registers_gr_ag_pr.gr_ag_pr;
5131    ~xcm_registers_gr_ld0_pr.gr_ld0_pr and
5132    ~xcm_registers_gr_ld1_pr.gr_ld1_pr. */
5133 #define XCM_REG_GR_ARB_TYPE                                      0x2020c
5134 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
5135    highest priority is 3. It is supposed that the Channel group is the
5136    compliment of the other 3 groups. */
5137 #define XCM_REG_GR_LD0_PR                                        0x20214
5138 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
5139    highest priority is 3. It is supposed that the Channel group is the
5140    compliment of the other 3 groups. */
5141 #define XCM_REG_GR_LD1_PR                                        0x20218
5142 /* [RW 1] Input nig0 Interface enable. If 0 - the valid input is
5143    disregarded; acknowledge output is deasserted; all other signals are
5144    treated as usual; if 1 - normal activity. */
5145 #define XCM_REG_NIG0_IFEN                                        0x20038
5146 /* [RC 1] Set at message length mismatch (relative to last indication) at
5147    the nig0 interface. */
5148 #define XCM_REG_NIG0_LENGTH_MIS                                  0x20238
5149 /* [RW 3] The weight of the input nig0 in the WRR mechanism. 0 stands for
5150    weight 8 (the most prioritised); 1 stands for weight 1(least
5151    prioritised); 2 stands for weight 2; tc. */
5152 #define XCM_REG_NIG0_WEIGHT                                      0x200d4
5153 /* [RW 1] Input nig1 Interface enable. If 0 - the valid input is
5154    disregarded; acknowledge output is deasserted; all other signals are
5155    treated as usual; if 1 - normal activity. */
5156 #define XCM_REG_NIG1_IFEN                                        0x2003c
5157 /* [RC 1] Set at message length mismatch (relative to last indication) at
5158    the nig1 interface. */
5159 #define XCM_REG_NIG1_LENGTH_MIS                                  0x2023c
5160 /* [RW 5] The number of double REG-pairs; loaded from the STORM context and
5161    sent to STORM; for a specific connection type. The double REG-pairs are
5162    used in order to align to STORM context row size of 128 bits. The offset
5163    of these data in the STORM context is always 0. Index _i stands for the
5164    connection type (one of 16). */
5165 #define XCM_REG_N_SM_CTX_LD_0                                    0x20060
5166 #define XCM_REG_N_SM_CTX_LD_1                                    0x20064
5167 #define XCM_REG_N_SM_CTX_LD_2                                    0x20068
5168 #define XCM_REG_N_SM_CTX_LD_3                                    0x2006c
5169 #define XCM_REG_N_SM_CTX_LD_4                                    0x20070
5170 #define XCM_REG_N_SM_CTX_LD_5                                    0x20074
5171 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
5172    acknowledge output is deasserted; all other signals are treated as usual;
5173    if 1 - normal activity. */
5174 #define XCM_REG_PBF_IFEN                                         0x20034
5175 /* [RC 1] Set at message length mismatch (relative to last indication) at
5176    the pbf interface. */
5177 #define XCM_REG_PBF_LENGTH_MIS                                   0x20234
5178 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
5179    weight 8 (the most prioritised); 1 stands for weight 1(least
5180    prioritised); 2 stands for weight 2; tc. */
5181 #define XCM_REG_PBF_WEIGHT                                       0x200d0
5182 #define XCM_REG_PHYS_QNUM3_0                                     0x20100
5183 #define XCM_REG_PHYS_QNUM3_1                                     0x20104
5184 /* [RW 8] The Event ID for Timers formatting in case of stop done. */
5185 #define XCM_REG_STOP_EVNT_ID                                     0x200b8
5186 /* [RC 1] Set at message length mismatch (relative to last indication) at
5187    the STORM interface. */
5188 #define XCM_REG_STORM_LENGTH_MIS                                 0x2021c
5189 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
5190    weight 8 (the most prioritised); 1 stands for weight 1(least
5191    prioritised); 2 stands for weight 2; tc. */
5192 #define XCM_REG_STORM_WEIGHT                                     0x200bc
5193 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
5194    disregarded; acknowledge output is deasserted; all other signals are
5195    treated as usual; if 1 - normal activity. */
5196 #define XCM_REG_STORM_XCM_IFEN                                   0x20010
5197 /* [RW 4] Timers output initial credit. Max credit available - 15.Write
5198    writes the initial credit value; read returns the current value of the
5199    credit counter. Must be initialized to 4 at start-up. */
5200 #define XCM_REG_TM_INIT_CRD                                      0x2041c
5201 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
5202    weight 8 (the most prioritised); 1 stands for weight 1(least
5203    prioritised); 2 stands for weight 2; tc. */
5204 #define XCM_REG_TM_WEIGHT                                        0x200ec
5205 /* [RW 28] The CM header for Timers expiration command. */
5206 #define XCM_REG_TM_XCM_HDR                                       0x200a8
5207 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
5208    disregarded; acknowledge output is deasserted; all other signals are
5209    treated as usual; if 1 - normal activity. */
5210 #define XCM_REG_TM_XCM_IFEN                                      0x2001c
5211 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
5212    disregarded; acknowledge output is deasserted; all other signals are
5213    treated as usual; if 1 - normal activity. */
5214 #define XCM_REG_TSEM_IFEN                                        0x20024
5215 /* [RC 1] Set at message length mismatch (relative to last indication) at
5216    the tsem interface. */
5217 #define XCM_REG_TSEM_LENGTH_MIS                                  0x20224
5218 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
5219    weight 8 (the most prioritised); 1 stands for weight 1(least
5220    prioritised); 2 stands for weight 2; tc. */
5221 #define XCM_REG_TSEM_WEIGHT                                      0x200c0
5222 /* [RW 2] The queue index for registration on UNA greater NXT decision rule. */
5223 #define XCM_REG_UNA_GT_NXT_Q                                     0x20120
5224 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
5225    disregarded; acknowledge output is deasserted; all other signals are
5226    treated as usual; if 1 - normal activity. */
5227 #define XCM_REG_USEM_IFEN                                        0x2002c
5228 /* [RC 1] Message length mismatch (relative to last indication) at the usem
5229    interface. */
5230 #define XCM_REG_USEM_LENGTH_MIS                                  0x2022c
5231 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
5232    weight 8 (the most prioritised); 1 stands for weight 1(least
5233    prioritised); 2 stands for weight 2; tc. */
5234 #define XCM_REG_USEM_WEIGHT                                      0x200c8
5235 #define XCM_REG_WU_DA_CNT_CMD00                                  0x201d4
5236 #define XCM_REG_WU_DA_CNT_CMD01                                  0x201d8
5237 #define XCM_REG_WU_DA_CNT_CMD10                                  0x201dc
5238 #define XCM_REG_WU_DA_CNT_CMD11                                  0x201e0
5239 #define XCM_REG_WU_DA_CNT_UPD_VAL00                              0x201e4
5240 #define XCM_REG_WU_DA_CNT_UPD_VAL01                              0x201e8
5241 #define XCM_REG_WU_DA_CNT_UPD_VAL10                              0x201ec
5242 #define XCM_REG_WU_DA_CNT_UPD_VAL11                              0x201f0
5243 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00                      0x201c4
5244 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01                      0x201c8
5245 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10                      0x201cc
5246 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11                      0x201d0
5247 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
5248    acknowledge output is deasserted; all other signals are treated as usual;
5249    if 1 - normal activity. */
5250 #define XCM_REG_XCM_CFC_IFEN                                     0x20050
5251 /* [RW 14] Interrupt mask register #0 read/write */
5252 #define XCM_REG_XCM_INT_MASK                                     0x202b4
5253 /* [R 14] Interrupt register #0 read */
5254 #define XCM_REG_XCM_INT_STS                                      0x202a8
5255 /* [RW 30] Parity mask register #0 read/write */
5256 #define XCM_REG_XCM_PRTY_MASK                                    0x202c4
5257 /* [R 30] Parity register #0 read */
5258 #define XCM_REG_XCM_PRTY_STS                                     0x202b8
5259 /* [RC 30] Parity register #0 read clear */
5260 #define XCM_REG_XCM_PRTY_STS_CLR                                 0x202bc
5261
5262 /* [RW 4] The size of AG context region 0 in REG-pairs. Designates the MS
5263    REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
5264    Is used to determine the number of the AG context REG-pairs written back;
5265    when the Reg1WbFlg isn't set. */
5266 #define XCM_REG_XCM_REG0_SZ                                      0x200f4
5267 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
5268    disregarded; valid is deasserted; all other signals are treated as usual;
5269    if 1 - normal activity. */
5270 #define XCM_REG_XCM_STORM0_IFEN                                  0x20004
5271 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
5272    disregarded; valid is deasserted; all other signals are treated as usual;
5273    if 1 - normal activity. */
5274 #define XCM_REG_XCM_STORM1_IFEN                                  0x20008
5275 /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
5276    disregarded; acknowledge output is deasserted; all other signals are
5277    treated as usual; if 1 - normal activity. */
5278 #define XCM_REG_XCM_TM_IFEN                                      0x20020
5279 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
5280    disregarded; valid is deasserted; all other signals are treated as usual;
5281    if 1 - normal activity. */
5282 #define XCM_REG_XCM_XQM_IFEN                                     0x2000c
5283 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
5284 #define XCM_REG_XCM_XQM_USE_Q                                    0x200f0
5285 /* [RW 4] The value by which CFC updates the activity counter at QM bypass. */
5286 #define XCM_REG_XQM_BYP_ACT_UPD                                  0x200fc
5287 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
5288    the initial credit value; read returns the current value of the credit
5289    counter. Must be initialized to 32 at start-up. */
5290 #define XCM_REG_XQM_INIT_CRD                                     0x20420
5291 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
5292    stands for weight 8 (the most prioritised); 1 stands for weight 1(least
5293    prioritised); 2 stands for weight 2; tc. */
5294 #define XCM_REG_XQM_P_WEIGHT                                     0x200e4
5295 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
5296    stands for weight 8 (the most prioritised); 1 stands for weight 1(least
5297    prioritised); 2 stands for weight 2; tc. */
5298 #define XCM_REG_XQM_S_WEIGHT                                     0x200e8
5299 /* [RW 28] The CM header value for QM request (primary). */
5300 #define XCM_REG_XQM_XCM_HDR_P                                    0x200a0
5301 /* [RW 28] The CM header value for QM request (secondary). */
5302 #define XCM_REG_XQM_XCM_HDR_S                                    0x200a4
5303 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
5304    acknowledge output is deasserted; all other signals are treated as usual;
5305    if 1 - normal activity. */
5306 #define XCM_REG_XQM_XCM_IFEN                                     0x20014
5307 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
5308    acknowledge output is deasserted; all other signals are treated as usual;
5309    if 1 - normal activity. */
5310 #define XCM_REG_XSDM_IFEN                                        0x20018
5311 /* [RC 1] Set at message length mismatch (relative to last indication) at
5312    the SDM interface. */
5313 #define XCM_REG_XSDM_LENGTH_MIS                                  0x20220
5314 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
5315    weight 8 (the most prioritised); 1 stands for weight 1(least
5316    prioritised); 2 stands for weight 2; tc. */
5317 #define XCM_REG_XSDM_WEIGHT                                      0x200e0
5318 /* [RW 17] Indirect access to the descriptor table of the XX protection
5319    mechanism. The fields are: [5:0] - message length; 11:6] - message
5320    pointer; 16:12] - next pointer. */
5321 #define XCM_REG_XX_DESCR_TABLE                                   0x20480
5322 #define XCM_REG_XX_DESCR_TABLE_SIZE                              32
5323 /* [R 6] Used to read the XX protection Free counter. */
5324 #define XCM_REG_XX_FREE                                          0x20240
5325 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
5326    of the Input Stage XX protection buffer by the XX protection pending
5327    messages. Max credit available - 3.Write writes the initial credit value;
5328    read returns the current value of the credit counter. Must be initialized
5329    to 2 at start-up. */
5330 #define XCM_REG_XX_INIT_CRD                                      0x20424
5331 /* [RW 6] The maximum number of pending messages; which may be stored in XX
5332    protection. ~xcm_registers_xx_free.xx_free read on read. */
5333 #define XCM_REG_XX_MSG_NUM                                       0x20428
5334 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
5335 #define XCM_REG_XX_OVFL_EVNT_ID                                  0x20058
5336 #define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS    (0x1<<0)
5337 #define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS   (0x1<<1)
5338 #define XMAC_CTRL_REG_LINE_LOCAL_LPBK                            (0x1<<2)
5339 #define XMAC_CTRL_REG_RX_EN                                      (0x1<<1)
5340 #define XMAC_CTRL_REG_SOFT_RESET                                 (0x1<<6)
5341 #define XMAC_CTRL_REG_TX_EN                                      (0x1<<0)
5342 #define XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN                          (0x1<<18)
5343 #define XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN                          (0x1<<17)
5344 #define XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN                      (0x1<<0)
5345 #define XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN                        (0x1<<3)
5346 #define XMAC_PFC_CTRL_HI_REG_RX_PFC_EN                           (0x1<<4)
5347 #define XMAC_PFC_CTRL_HI_REG_TX_PFC_EN                           (0x1<<5)
5348 #define XMAC_REG_CLEAR_RX_LSS_STATUS                             0x60
5349 #define XMAC_REG_CTRL                                            0
5350 /* [RW 16] Upper 48 bits of ctrl_sa register. Used as the SA in PAUSE/PFC
5351  * packets transmitted by the MAC */
5352 #define XMAC_REG_CTRL_SA_HI                                      0x2c
5353 /* [RW 32] Lower 48 bits of ctrl_sa register. Used as the SA in PAUSE/PFC
5354  * packets transmitted by the MAC */
5355 #define XMAC_REG_CTRL_SA_LO                                      0x28
5356 #define XMAC_REG_PAUSE_CTRL                                      0x68
5357 #define XMAC_REG_PFC_CTRL                                        0x70
5358 #define XMAC_REG_PFC_CTRL_HI                                     0x74
5359 #define XMAC_REG_RX_LSS_STATUS                                   0x58
5360 /* [RW 14] Maximum packet size in receive direction; exclusive of preamble &
5361  * CRC in strip mode */
5362 #define XMAC_REG_RX_MAX_SIZE                                     0x40
5363 #define XMAC_REG_TX_CTRL                                         0x20
5364 /* [RW 16] Indirect access to the XX table of the XX protection mechanism.
5365    The fields are:[4:0] - tail pointer; 9:5] - Link List size; 14:10] -
5366    header pointer. */
5367 #define XCM_REG_XX_TABLE                                         0x20500
5368 /* [RW 8] The event id for aggregated interrupt 0 */
5369 #define XSDM_REG_AGG_INT_EVENT_0                                 0x166038
5370 #define XSDM_REG_AGG_INT_EVENT_1                                 0x16603c
5371 #define XSDM_REG_AGG_INT_EVENT_10                                0x166060
5372 #define XSDM_REG_AGG_INT_EVENT_11                                0x166064
5373 #define XSDM_REG_AGG_INT_EVENT_12                                0x166068
5374 #define XSDM_REG_AGG_INT_EVENT_13                                0x16606c
5375 #define XSDM_REG_AGG_INT_EVENT_14                                0x166070
5376 #define XSDM_REG_AGG_INT_EVENT_2                                 0x166040
5377 #define XSDM_REG_AGG_INT_EVENT_3                                 0x166044
5378 #define XSDM_REG_AGG_INT_EVENT_4                                 0x166048
5379 #define XSDM_REG_AGG_INT_EVENT_5                                 0x16604c
5380 #define XSDM_REG_AGG_INT_EVENT_6                                 0x166050
5381 #define XSDM_REG_AGG_INT_EVENT_7                                 0x166054
5382 #define XSDM_REG_AGG_INT_EVENT_8                                 0x166058
5383 #define XSDM_REG_AGG_INT_EVENT_9                                 0x16605c
5384 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
5385    or auto-mask-mode (1) */
5386 #define XSDM_REG_AGG_INT_MODE_0                                  0x1661b8
5387 #define XSDM_REG_AGG_INT_MODE_1                                  0x1661bc
5388 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
5389 #define XSDM_REG_CFC_RSP_START_ADDR                              0x166008
5390 /* [RW 16] The maximum value of the completion counter #0 */
5391 #define XSDM_REG_CMP_COUNTER_MAX0                                0x16601c
5392 /* [RW 16] The maximum value of the completion counter #1 */
5393 #define XSDM_REG_CMP_COUNTER_MAX1                                0x166020
5394 /* [RW 16] The maximum value of the completion counter #2 */
5395 #define XSDM_REG_CMP_COUNTER_MAX2                                0x166024
5396 /* [RW 16] The maximum value of the completion counter #3 */
5397 #define XSDM_REG_CMP_COUNTER_MAX3                                0x166028
5398 /* [RW 13] The start address in the internal RAM for the completion
5399    counters. */
5400 #define XSDM_REG_CMP_COUNTER_START_ADDR                          0x16600c
5401 #define XSDM_REG_ENABLE_IN1                                      0x166238
5402 #define XSDM_REG_ENABLE_IN2                                      0x16623c
5403 #define XSDM_REG_ENABLE_OUT1                                     0x166240
5404 #define XSDM_REG_ENABLE_OUT2                                     0x166244
5405 /* [RW 4] The initial number of messages that can be sent to the pxp control
5406    interface without receiving any ACK. */
5407 #define XSDM_REG_INIT_CREDIT_PXP_CTRL                            0x1664bc
5408 /* [ST 32] The number of ACK after placement messages received */
5409 #define XSDM_REG_NUM_OF_ACK_AFTER_PLACE                          0x16627c
5410 /* [ST 32] The number of packet end messages received from the parser */
5411 #define XSDM_REG_NUM_OF_PKT_END_MSG                              0x166274
5412 /* [ST 32] The number of requests received from the pxp async if */
5413 #define XSDM_REG_NUM_OF_PXP_ASYNC_REQ                            0x166278
5414 /* [ST 32] The number of commands received in queue 0 */
5415 #define XSDM_REG_NUM_OF_Q0_CMD                                   0x166248
5416 /* [ST 32] The number of commands received in queue 10 */
5417 #define XSDM_REG_NUM_OF_Q10_CMD                                  0x16626c
5418 /* [ST 32] The number of commands received in queue 11 */
5419 #define XSDM_REG_NUM_OF_Q11_CMD                                  0x166270
5420 /* [ST 32] The number of commands received in queue 1 */
5421 #define XSDM_REG_NUM_OF_Q1_CMD                                   0x16624c
5422 /* [ST 32] The number of commands received in queue 3 */
5423 #define XSDM_REG_NUM_OF_Q3_CMD                                   0x166250
5424 /* [ST 32] The number of commands received in queue 4 */
5425 #define XSDM_REG_NUM_OF_Q4_CMD                                   0x166254
5426 /* [ST 32] The number of commands received in queue 5 */
5427 #define XSDM_REG_NUM_OF_Q5_CMD                                   0x166258
5428 /* [ST 32] The number of commands received in queue 6 */
5429 #define XSDM_REG_NUM_OF_Q6_CMD                                   0x16625c
5430 /* [ST 32] The number of commands received in queue 7 */
5431 #define XSDM_REG_NUM_OF_Q7_CMD                                   0x166260
5432 /* [ST 32] The number of commands received in queue 8 */
5433 #define XSDM_REG_NUM_OF_Q8_CMD                                   0x166264
5434 /* [ST 32] The number of commands received in queue 9 */
5435 #define XSDM_REG_NUM_OF_Q9_CMD                                   0x166268
5436 /* [RW 13] The start address in the internal RAM for queue counters */
5437 #define XSDM_REG_Q_COUNTER_START_ADDR                            0x166010
5438 /* [W 17] Generate an operation after completion; bit-16 is
5439  * AggVectIdx_valid; bits 15:8 are AggVectIdx; bits 7:5 are the TRIG and
5440  * bits 4:0 are the T124Param[4:0] */
5441 #define XSDM_REG_OPERATION_GEN                                   0x1664c4
5442 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
5443 #define XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY                        0x166548
5444 /* [R 1] parser fifo empty in sdm_sync block */
5445 #define XSDM_REG_SYNC_PARSER_EMPTY                               0x166550
5446 /* [R 1] parser serial fifo empty in sdm_sync block */
5447 #define XSDM_REG_SYNC_SYNC_EMPTY                                 0x166558
5448 /* [RW 32] Tick for timer counter. Applicable only when
5449    ~xsdm_registers_timer_tick_enable.timer_tick_enable =1 */
5450 #define XSDM_REG_TIMER_TICK                                      0x166000
5451 /* [RW 32] Interrupt mask register #0 read/write */
5452 #define XSDM_REG_XSDM_INT_MASK_0                                 0x16629c
5453 #define XSDM_REG_XSDM_INT_MASK_1                                 0x1662ac
5454 /* [R 32] Interrupt register #0 read */
5455 #define XSDM_REG_XSDM_INT_STS_0                                  0x166290
5456 #define XSDM_REG_XSDM_INT_STS_1                                  0x1662a0
5457 /* [RW 11] Parity mask register #0 read/write */
5458 #define XSDM_REG_XSDM_PRTY_MASK                                  0x1662bc
5459 /* [R 11] Parity register #0 read */
5460 #define XSDM_REG_XSDM_PRTY_STS                                   0x1662b0
5461 /* [RC 11] Parity register #0 read clear */
5462 #define XSDM_REG_XSDM_PRTY_STS_CLR                               0x1662b4
5463 /* [RW 5] The number of time_slots in the arbitration cycle */
5464 #define XSEM_REG_ARB_CYCLE_SIZE                                  0x280034
5465 /* [RW 3] The source that is associated with arbitration element 0. Source
5466    decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5467    sleeping thread with priority 1; 4- sleeping thread with priority 2 */
5468 #define XSEM_REG_ARB_ELEMENT0                                    0x280020
5469 /* [RW 3] The source that is associated with arbitration element 1. Source
5470    decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5471    sleeping thread with priority 1; 4- sleeping thread with priority 2.
5472    Could not be equal to register ~xsem_registers_arb_element0.arb_element0 */
5473 #define XSEM_REG_ARB_ELEMENT1                                    0x280024
5474 /* [RW 3] The source that is associated with arbitration element 2. Source
5475    decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5476    sleeping thread with priority 1; 4- sleeping thread with priority 2.
5477    Could not be equal to register ~xsem_registers_arb_element0.arb_element0
5478    and ~xsem_registers_arb_element1.arb_element1 */
5479 #define XSEM_REG_ARB_ELEMENT2                                    0x280028
5480 /* [RW 3] The source that is associated with arbitration element 3. Source
5481    decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5482    sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
5483    not be equal to register ~xsem_registers_arb_element0.arb_element0 and
5484    ~xsem_registers_arb_element1.arb_element1 and
5485    ~xsem_registers_arb_element2.arb_element2 */
5486 #define XSEM_REG_ARB_ELEMENT3                                    0x28002c
5487 /* [RW 3] The source that is associated with arbitration element 4. Source
5488    decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5489    sleeping thread with priority 1; 4- sleeping thread with priority 2.
5490    Could not be equal to register ~xsem_registers_arb_element0.arb_element0
5491    and ~xsem_registers_arb_element1.arb_element1 and
5492    ~xsem_registers_arb_element2.arb_element2 and
5493    ~xsem_registers_arb_element3.arb_element3 */
5494 #define XSEM_REG_ARB_ELEMENT4                                    0x280030
5495 #define XSEM_REG_ENABLE_IN                                       0x2800a4
5496 #define XSEM_REG_ENABLE_OUT                                      0x2800a8
5497 /* [RW 32] This address space contains all registers and memories that are
5498    placed in SEM_FAST block. The SEM_FAST registers are described in
5499    appendix B. In order to access the sem_fast registers the base address
5500    ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
5501 #define XSEM_REG_FAST_MEMORY                                     0x2a0000
5502 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
5503    by the microcode */
5504 #define XSEM_REG_FIC0_DISABLE                                    0x280224
5505 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
5506    by the microcode */
5507 #define XSEM_REG_FIC1_DISABLE                                    0x280234
5508 /* [RW 15] Interrupt table Read and write access to it is not possible in
5509    the middle of the work */
5510 #define XSEM_REG_INT_TABLE                                       0x280400
5511 /* [ST 24] Statistics register. The number of messages that entered through
5512    FIC0 */
5513 #define XSEM_REG_MSG_NUM_FIC0                                    0x280000
5514 /* [ST 24] Statistics register. The number of messages that entered through
5515    FIC1 */
5516 #define XSEM_REG_MSG_NUM_FIC1                                    0x280004
5517 /* [ST 24] Statistics register. The number of messages that were sent to
5518    FOC0 */
5519 #define XSEM_REG_MSG_NUM_FOC0                                    0x280008
5520 /* [ST 24] Statistics register. The number of messages that were sent to
5521    FOC1 */
5522 #define XSEM_REG_MSG_NUM_FOC1                                    0x28000c
5523 /* [ST 24] Statistics register. The number of messages that were sent to
5524    FOC2 */
5525 #define XSEM_REG_MSG_NUM_FOC2                                    0x280010
5526 /* [ST 24] Statistics register. The number of messages that were sent to
5527    FOC3 */
5528 #define XSEM_REG_MSG_NUM_FOC3                                    0x280014
5529 /* [RW 1] Disables input messages from the passive buffer May be updated
5530    during run_time by the microcode */
5531 #define XSEM_REG_PAS_DISABLE                                     0x28024c
5532 /* [WB 128] Debug only. Passive buffer memory */
5533 #define XSEM_REG_PASSIVE_BUFFER                                  0x282000
5534 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
5535 #define XSEM_REG_PRAM                                            0x2c0000
5536 /* [R 16] Valid sleeping threads indication have bit per thread */
5537 #define XSEM_REG_SLEEP_THREADS_VALID                             0x28026c
5538 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
5539 #define XSEM_REG_SLOW_EXT_STORE_EMPTY                            0x2802a0
5540 /* [RW 16] List of free threads . There is a bit per thread. */
5541 #define XSEM_REG_THREADS_LIST                                    0x2802e4
5542 /* [RW 3] The arbitration scheme of time_slot 0 */
5543 #define XSEM_REG_TS_0_AS                                         0x280038
5544 /* [RW 3] The arbitration scheme of time_slot 10 */
5545 #define XSEM_REG_TS_10_AS                                        0x280060
5546 /* [RW 3] The arbitration scheme of time_slot 11 */
5547 #define XSEM_REG_TS_11_AS                                        0x280064
5548 /* [RW 3] The arbitration scheme of time_slot 12 */
5549 #define XSEM_REG_TS_12_AS                                        0x280068
5550 /* [RW 3] The arbitration scheme of time_slot 13 */
5551 #define XSEM_REG_TS_13_AS                                        0x28006c
5552 /* [RW 3] The arbitration scheme of time_slot 14 */
5553 #define XSEM_REG_TS_14_AS                                        0x280070
5554 /* [RW 3] The arbitration scheme of time_slot 15 */
5555 #define XSEM_REG_TS_15_AS                                        0x280074
5556 /* [RW 3] The arbitration scheme of time_slot 16 */
5557 #define XSEM_REG_TS_16_AS                                        0x280078
5558 /* [RW 3] The arbitration scheme of time_slot 17 */
5559 #define XSEM_REG_TS_17_AS                                        0x28007c
5560 /* [RW 3] The arbitration scheme of time_slot 18 */
5561 #define XSEM_REG_TS_18_AS                                        0x280080
5562 /* [RW 3] The arbitration scheme of time_slot 1 */
5563 #define XSEM_REG_TS_1_AS                                         0x28003c
5564 /* [RW 3] The arbitration scheme of time_slot 2 */
5565 #define XSEM_REG_TS_2_AS                                         0x280040
5566 /* [RW 3] The arbitration scheme of time_slot 3 */
5567 #define XSEM_REG_TS_3_AS                                         0x280044
5568 /* [RW 3] The arbitration scheme of time_slot 4 */
5569 #define XSEM_REG_TS_4_AS                                         0x280048
5570 /* [RW 3] The arbitration scheme of time_slot 5 */
5571 #define XSEM_REG_TS_5_AS                                         0x28004c
5572 /* [RW 3] The arbitration scheme of time_slot 6 */
5573 #define XSEM_REG_TS_6_AS                                         0x280050
5574 /* [RW 3] The arbitration scheme of time_slot 7 */
5575 #define XSEM_REG_TS_7_AS                                         0x280054
5576 /* [RW 3] The arbitration scheme of time_slot 8 */
5577 #define XSEM_REG_TS_8_AS                                         0x280058
5578 /* [RW 3] The arbitration scheme of time_slot 9 */
5579 #define XSEM_REG_TS_9_AS                                         0x28005c
5580 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
5581  * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
5582 #define XSEM_REG_VFPF_ERR_NUM                                    0x280380
5583 /* [RW 32] Interrupt mask register #0 read/write */
5584 #define XSEM_REG_XSEM_INT_MASK_0                                 0x280110
5585 #define XSEM_REG_XSEM_INT_MASK_1                                 0x280120
5586 /* [R 32] Interrupt register #0 read */
5587 #define XSEM_REG_XSEM_INT_STS_0                                  0x280104
5588 #define XSEM_REG_XSEM_INT_STS_1                                  0x280114
5589 /* [RW 32] Parity mask register #0 read/write */
5590 #define XSEM_REG_XSEM_PRTY_MASK_0                                0x280130
5591 #define XSEM_REG_XSEM_PRTY_MASK_1                                0x280140
5592 /* [R 32] Parity register #0 read */
5593 #define XSEM_REG_XSEM_PRTY_STS_0                                 0x280124
5594 #define XSEM_REG_XSEM_PRTY_STS_1                                 0x280134
5595 /* [RC 32] Parity register #0 read clear */
5596 #define XSEM_REG_XSEM_PRTY_STS_CLR_0                             0x280128
5597 #define XSEM_REG_XSEM_PRTY_STS_CLR_1                             0x280138
5598 #define MCPR_NVM_ACCESS_ENABLE_EN                                (1L<<0)
5599 #define MCPR_NVM_ACCESS_ENABLE_WR_EN                             (1L<<1)
5600 #define MCPR_NVM_ADDR_NVM_ADDR_VALUE                             (0xffffffL<<0)
5601 #define MCPR_NVM_CFG4_FLASH_SIZE                                 (0x7L<<0)
5602 #define MCPR_NVM_COMMAND_DOIT                                    (1L<<4)
5603 #define MCPR_NVM_COMMAND_DONE                                    (1L<<3)
5604 #define MCPR_NVM_COMMAND_FIRST                                   (1L<<7)
5605 #define MCPR_NVM_COMMAND_LAST                                    (1L<<8)
5606 #define MCPR_NVM_COMMAND_WR                                      (1L<<5)
5607 #define MCPR_NVM_SW_ARB_ARB_ARB1                                 (1L<<9)
5608 #define MCPR_NVM_SW_ARB_ARB_REQ_CLR1                             (1L<<5)
5609 #define MCPR_NVM_SW_ARB_ARB_REQ_SET1                             (1L<<1)
5610 #define BIGMAC_REGISTER_BMAC_CONTROL                             (0x00<<3)
5611 #define BIGMAC_REGISTER_BMAC_XGXS_CONTROL                        (0x01<<3)
5612 #define BIGMAC_REGISTER_CNT_MAX_SIZE                             (0x05<<3)
5613 #define BIGMAC_REGISTER_RX_CONTROL                               (0x21<<3)
5614 #define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS                         (0x46<<3)
5615 #define BIGMAC_REGISTER_RX_LSS_STATUS                            (0x43<<3)
5616 #define BIGMAC_REGISTER_RX_MAX_SIZE                              (0x23<<3)
5617 #define BIGMAC_REGISTER_RX_STAT_GR64                             (0x26<<3)
5618 #define BIGMAC_REGISTER_RX_STAT_GRIPJ                            (0x42<<3)
5619 #define BIGMAC_REGISTER_TX_CONTROL                               (0x07<<3)
5620 #define BIGMAC_REGISTER_TX_MAX_SIZE                              (0x09<<3)
5621 #define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD                       (0x0A<<3)
5622 #define BIGMAC_REGISTER_TX_SOURCE_ADDR                           (0x08<<3)
5623 #define BIGMAC_REGISTER_TX_STAT_GTBYT                            (0x20<<3)
5624 #define BIGMAC_REGISTER_TX_STAT_GTPKT                            (0x0C<<3)
5625 #define BIGMAC2_REGISTER_BMAC_CONTROL                            (0x00<<3)
5626 #define BIGMAC2_REGISTER_BMAC_XGXS_CONTROL                       (0x01<<3)
5627 #define BIGMAC2_REGISTER_CNT_MAX_SIZE                            (0x05<<3)
5628 #define BIGMAC2_REGISTER_PFC_CONTROL                             (0x06<<3)
5629 #define BIGMAC2_REGISTER_RX_CONTROL                              (0x3A<<3)
5630 #define BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS                        (0x62<<3)
5631 #define BIGMAC2_REGISTER_RX_LSS_STAT                             (0x3E<<3)
5632 #define BIGMAC2_REGISTER_RX_MAX_SIZE                             (0x3C<<3)
5633 #define BIGMAC2_REGISTER_RX_STAT_GR64                            (0x40<<3)
5634 #define BIGMAC2_REGISTER_RX_STAT_GRIPJ                           (0x5f<<3)
5635 #define BIGMAC2_REGISTER_RX_STAT_GRPP                            (0x51<<3)
5636 #define BIGMAC2_REGISTER_TX_CONTROL                              (0x1C<<3)
5637 #define BIGMAC2_REGISTER_TX_MAX_SIZE                             (0x1E<<3)
5638 #define BIGMAC2_REGISTER_TX_PAUSE_CONTROL                        (0x20<<3)
5639 #define BIGMAC2_REGISTER_TX_SOURCE_ADDR                  (0x1D<<3)
5640 #define BIGMAC2_REGISTER_TX_STAT_GTBYT                           (0x39<<3)
5641 #define BIGMAC2_REGISTER_TX_STAT_GTPOK                           (0x22<<3)
5642 #define BIGMAC2_REGISTER_TX_STAT_GTPP                            (0x24<<3)
5643 #define EMAC_LED_1000MB_OVERRIDE                                 (1L<<1)
5644 #define EMAC_LED_100MB_OVERRIDE                                  (1L<<2)
5645 #define EMAC_LED_10MB_OVERRIDE                                   (1L<<3)
5646 #define EMAC_LED_2500MB_OVERRIDE                                 (1L<<12)
5647 #define EMAC_LED_OVERRIDE                                        (1L<<0)
5648 #define EMAC_LED_TRAFFIC                                         (1L<<6)
5649 #define EMAC_MDIO_COMM_COMMAND_ADDRESS                           (0L<<26)
5650 #define EMAC_MDIO_COMM_COMMAND_READ_22                           (2L<<26)
5651 #define EMAC_MDIO_COMM_COMMAND_READ_45                           (3L<<26)
5652 #define EMAC_MDIO_COMM_COMMAND_WRITE_22                          (1L<<26)
5653 #define EMAC_MDIO_COMM_COMMAND_WRITE_45                          (1L<<26)
5654 #define EMAC_MDIO_COMM_DATA                                      (0xffffL<<0)
5655 #define EMAC_MDIO_COMM_START_BUSY                                (1L<<29)
5656 #define EMAC_MDIO_MODE_AUTO_POLL                                 (1L<<4)
5657 #define EMAC_MDIO_MODE_CLAUSE_45                                 (1L<<31)
5658 #define EMAC_MDIO_MODE_CLOCK_CNT                                 (0x3ffL<<16)
5659 #define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT                        16
5660 #define EMAC_MDIO_STATUS_10MB                                    (1L<<1)
5661 #define EMAC_MODE_25G_MODE                                       (1L<<5)
5662 #define EMAC_MODE_HALF_DUPLEX                                    (1L<<1)
5663 #define EMAC_MODE_PORT_GMII                                      (2L<<2)
5664 #define EMAC_MODE_PORT_MII                                       (1L<<2)
5665 #define EMAC_MODE_PORT_MII_10M                                   (3L<<2)
5666 #define EMAC_MODE_RESET                                          (1L<<0)
5667 #define EMAC_REG_EMAC_LED                                        0xc
5668 #define EMAC_REG_EMAC_MAC_MATCH                                  0x10
5669 #define EMAC_REG_EMAC_MDIO_COMM                                  0xac
5670 #define EMAC_REG_EMAC_MDIO_MODE                                  0xb4
5671 #define EMAC_REG_EMAC_MDIO_STATUS                                0xb0
5672 #define EMAC_REG_EMAC_MODE                                       0x0
5673 #define EMAC_REG_EMAC_RX_MODE                                    0xc8
5674 #define EMAC_REG_EMAC_RX_MTU_SIZE                                0x9c
5675 #define EMAC_REG_EMAC_RX_STAT_AC                                 0x180
5676 #define EMAC_REG_EMAC_RX_STAT_AC_28                              0x1f4
5677 #define EMAC_REG_EMAC_RX_STAT_AC_COUNT                           23
5678 #define EMAC_REG_EMAC_TX_MODE                                    0xbc
5679 #define EMAC_REG_EMAC_TX_STAT_AC                                 0x280
5680 #define EMAC_REG_EMAC_TX_STAT_AC_COUNT                           22
5681 #define EMAC_REG_RX_PFC_MODE                                     0x320
5682 #define EMAC_REG_RX_PFC_MODE_PRIORITIES                          (1L<<2)
5683 #define EMAC_REG_RX_PFC_MODE_RX_EN                               (1L<<1)
5684 #define EMAC_REG_RX_PFC_MODE_TX_EN                               (1L<<0)
5685 #define EMAC_REG_RX_PFC_PARAM                                    0x324
5686 #define EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT                    0
5687 #define EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT               16
5688 #define EMAC_REG_RX_PFC_STATS_XOFF_RCVD                          0x328
5689 #define EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT                    (0xffff<<0)
5690 #define EMAC_REG_RX_PFC_STATS_XOFF_SENT                          0x330
5691 #define EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT                    (0xffff<<0)
5692 #define EMAC_REG_RX_PFC_STATS_XON_RCVD                           0x32c
5693 #define EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT                     (0xffff<<0)
5694 #define EMAC_REG_RX_PFC_STATS_XON_SENT                           0x334
5695 #define EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT                     (0xffff<<0)
5696 #define EMAC_RX_MODE_FLOW_EN                                     (1L<<2)
5697 #define EMAC_RX_MODE_KEEP_MAC_CONTROL                            (1L<<3)
5698 #define EMAC_RX_MODE_KEEP_VLAN_TAG                               (1L<<10)
5699 #define EMAC_RX_MODE_PROMISCUOUS                                 (1L<<8)
5700 #define EMAC_RX_MODE_RESET                                       (1L<<0)
5701 #define EMAC_RX_MTU_SIZE_JUMBO_ENA                               (1L<<31)
5702 #define EMAC_TX_MODE_EXT_PAUSE_EN                                (1L<<3)
5703 #define EMAC_TX_MODE_FLOW_EN                                     (1L<<4)
5704 #define EMAC_TX_MODE_RESET                                       (1L<<0)
5705 #define MISC_REGISTERS_GPIO_0                                    0
5706 #define MISC_REGISTERS_GPIO_1                                    1
5707 #define MISC_REGISTERS_GPIO_2                                    2
5708 #define MISC_REGISTERS_GPIO_3                                    3
5709 #define MISC_REGISTERS_GPIO_CLR_POS                              16
5710 #define MISC_REGISTERS_GPIO_FLOAT                                (0xffL<<24)
5711 #define MISC_REGISTERS_GPIO_FLOAT_POS                            24
5712 #define MISC_REGISTERS_GPIO_HIGH                                 1
5713 #define MISC_REGISTERS_GPIO_INPUT_HI_Z                           2
5714 #define MISC_REGISTERS_GPIO_INT_CLR_POS                          24
5715 #define MISC_REGISTERS_GPIO_INT_OUTPUT_CLR                       0
5716 #define MISC_REGISTERS_GPIO_INT_OUTPUT_SET                       1
5717 #define MISC_REGISTERS_GPIO_INT_SET_POS                          16
5718 #define MISC_REGISTERS_GPIO_LOW                                  0
5719 #define MISC_REGISTERS_GPIO_OUTPUT_HIGH                          1
5720 #define MISC_REGISTERS_GPIO_OUTPUT_LOW                           0
5721 #define MISC_REGISTERS_GPIO_PORT_SHIFT                           4
5722 #define MISC_REGISTERS_GPIO_SET_POS                              8
5723 #define MISC_REGISTERS_RESET_REG_1_CLEAR                         0x588
5724 #define MISC_REGISTERS_RESET_REG_1_RST_HC                        (0x1<<29)
5725 #define MISC_REGISTERS_RESET_REG_1_RST_NIG                       (0x1<<7)
5726 #define MISC_REGISTERS_RESET_REG_1_RST_PXP                       (0x1<<26)
5727 #define MISC_REGISTERS_RESET_REG_1_RST_PXPV                      (0x1<<27)
5728 #define MISC_REGISTERS_RESET_REG_1_SET                           0x584
5729 #define MISC_REGISTERS_RESET_REG_2_CLEAR                         0x598
5730 #define MISC_REGISTERS_RESET_REG_2_MSTAT0                        (0x1<<24)
5731 #define MISC_REGISTERS_RESET_REG_2_MSTAT1                        (0x1<<25)
5732 #define MISC_REGISTERS_RESET_REG_2_PGLC                          (0x1<<19)
5733 #define MISC_REGISTERS_RESET_REG_2_RST_ATC                       (0x1<<17)
5734 #define MISC_REGISTERS_RESET_REG_2_RST_BMAC0                     (0x1<<0)
5735 #define MISC_REGISTERS_RESET_REG_2_RST_BMAC1                     (0x1<<1)
5736 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC0                     (0x1<<2)
5737 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE           (0x1<<14)
5738 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC1                     (0x1<<3)
5739 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE           (0x1<<15)
5740 #define MISC_REGISTERS_RESET_REG_2_RST_GRC                       (0x1<<4)
5741 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B     (0x1<<6)
5742 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE      (0x1<<8)
5743 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU       (0x1<<7)
5744 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE (0x1<<5)
5745 #define MISC_REGISTERS_RESET_REG_2_RST_MDIO                      (0x1<<13)
5746 #define MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE                 (0x1<<11)
5747 #define MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO                  (0x1<<13)
5748 #define MISC_REGISTERS_RESET_REG_2_RST_RBCN                      (0x1<<9)
5749 #define MISC_REGISTERS_RESET_REG_2_SET                           0x594
5750 #define MISC_REGISTERS_RESET_REG_2_UMAC0                         (0x1<<20)
5751 #define MISC_REGISTERS_RESET_REG_2_UMAC1                         (0x1<<21)
5752 #define MISC_REGISTERS_RESET_REG_2_XMAC                          (0x1<<22)
5753 #define MISC_REGISTERS_RESET_REG_2_XMAC_SOFT                     (0x1<<23)
5754 #define MISC_REGISTERS_RESET_REG_3_CLEAR                         0x5a8
5755 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ     (0x1<<1)
5756 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN   (0x1<<2)
5757 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3)
5758 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW  (0x1<<0)
5759 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ       (0x1<<5)
5760 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN     (0x1<<6)
5761 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD  (0x1<<7)
5762 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW    (0x1<<4)
5763 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1<<8)
5764 #define MISC_REGISTERS_RESET_REG_3_SET                           0x5a4
5765 #define MISC_REGISTERS_SPIO_4                                    4
5766 #define MISC_REGISTERS_SPIO_5                                    5
5767 #define MISC_REGISTERS_SPIO_7                                    7
5768 #define MISC_REGISTERS_SPIO_CLR_POS                              16
5769 #define MISC_REGISTERS_SPIO_FLOAT                                (0xffL<<24)
5770 #define MISC_REGISTERS_SPIO_FLOAT_POS                            24
5771 #define MISC_REGISTERS_SPIO_INPUT_HI_Z                           2
5772 #define MISC_REGISTERS_SPIO_INT_OLD_SET_POS                      16
5773 #define MISC_REGISTERS_SPIO_OUTPUT_HIGH                          1
5774 #define MISC_REGISTERS_SPIO_OUTPUT_LOW                           0
5775 #define MISC_REGISTERS_SPIO_SET_POS                              8
5776 #define HW_LOCK_DRV_FLAGS                                        10
5777 #define HW_LOCK_MAX_RESOURCE_VALUE                               31
5778 #define HW_LOCK_RESOURCE_GPIO                                    1
5779 #define HW_LOCK_RESOURCE_MDIO                                    0
5780 #define HW_LOCK_RESOURCE_PORT0_ATT_MASK                          3
5781 #define HW_LOCK_RESOURCE_RECOVERY_LEADER_0                       8
5782 #define HW_LOCK_RESOURCE_RECOVERY_LEADER_1                       9
5783 #define HW_LOCK_RESOURCE_SPIO                                    2
5784 #define HW_LOCK_RESOURCE_RESET                                   5
5785 #define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT                    (0x1<<4)
5786 #define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR                    (0x1<<5)
5787 #define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR                    (0x1<<18)
5788 #define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT                    (0x1<<31)
5789 #define AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR                    (0x1<<30)
5790 #define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT                    (0x1<<9)
5791 #define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR                    (0x1<<8)
5792 #define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT                    (0x1<<7)
5793 #define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR                    (0x1<<6)
5794 #define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT                   (0x1<<29)
5795 #define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR                   (0x1<<28)
5796 #define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT                  (0x1<<1)
5797 #define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR                  (0x1<<0)
5798 #define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR                  (0x1<<18)
5799 #define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT                   (0x1<<11)
5800 #define AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR                   (0x1<<10)
5801 #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT              (0x1<<13)
5802 #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR              (0x1<<12)
5803 #define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0                    (0x1<<2)
5804 #define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR                    (0x1<<12)
5805 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY              (0x1<<28)
5806 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY            (0x1<<31)
5807 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY           (0x1<<29)
5808 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY           (0x1<<30)
5809 #define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT                   (0x1<<15)
5810 #define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR                   (0x1<<14)
5811 #define AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR                    (0x1<<14)
5812 #define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR                 (0x1<<20)
5813 #define AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT               (0x1<<31)
5814 #define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR               (0x1<<30)
5815 #define AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR                    (0x1<<0)
5816 #define AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT                  (0x1<<2)
5817 #define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR                  (0x1<<3)
5818 #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT      (0x1<<5)
5819 #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR      (0x1<<4)
5820 #define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT                    (0x1<<3)
5821 #define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR                    (0x1<<2)
5822 #define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT                     (0x1<<3)
5823 #define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR                     (0x1<<2)
5824 #define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR               (0x1<<22)
5825 #define AEU_INPUTS_ATTN_BITS_SPIO5                               (0x1<<15)
5826 #define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT                    (0x1<<27)
5827 #define AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR                    (0x1<<26)
5828 #define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT                 (0x1<<5)
5829 #define AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR                 (0x1<<4)
5830 #define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT                   (0x1<<25)
5831 #define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR                   (0x1<<24)
5832 #define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT                  (0x1<<29)
5833 #define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR                  (0x1<<28)
5834 #define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT                    (0x1<<23)
5835 #define AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR                    (0x1<<22)
5836 #define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT                    (0x1<<27)
5837 #define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR                    (0x1<<26)
5838 #define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT                   (0x1<<21)
5839 #define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR                   (0x1<<20)
5840 #define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT                  (0x1<<25)
5841 #define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR                  (0x1<<24)
5842 #define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR          (0x1<<16)
5843 #define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT                    (0x1<<9)
5844 #define AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR                    (0x1<<8)
5845 #define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT                   (0x1<<7)
5846 #define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR                   (0x1<<6)
5847 #define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT                  (0x1<<11)
5848 #define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR                  (0x1<<10)
5849
5850 #define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0                   (0x1<<5)
5851 #define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1                   (0x1<<9)
5852
5853 #define RESERVED_GENERAL_ATTENTION_BIT_0        0
5854
5855 #define EVEREST_GEN_ATTN_IN_USE_MASK            0x7ffe0
5856 #define EVEREST_LATCHED_ATTN_IN_USE_MASK        0xffe00000
5857
5858 #define RESERVED_GENERAL_ATTENTION_BIT_6        6
5859 #define RESERVED_GENERAL_ATTENTION_BIT_7        7
5860 #define RESERVED_GENERAL_ATTENTION_BIT_8        8
5861 #define RESERVED_GENERAL_ATTENTION_BIT_9        9
5862 #define RESERVED_GENERAL_ATTENTION_BIT_10       10
5863 #define RESERVED_GENERAL_ATTENTION_BIT_11       11
5864 #define RESERVED_GENERAL_ATTENTION_BIT_12       12
5865 #define RESERVED_GENERAL_ATTENTION_BIT_13       13
5866 #define RESERVED_GENERAL_ATTENTION_BIT_14       14
5867 #define RESERVED_GENERAL_ATTENTION_BIT_15       15
5868 #define RESERVED_GENERAL_ATTENTION_BIT_16       16
5869 #define RESERVED_GENERAL_ATTENTION_BIT_17       17
5870 #define RESERVED_GENERAL_ATTENTION_BIT_18       18
5871 #define RESERVED_GENERAL_ATTENTION_BIT_19       19
5872 #define RESERVED_GENERAL_ATTENTION_BIT_20       20
5873 #define RESERVED_GENERAL_ATTENTION_BIT_21       21
5874
5875 /* storm asserts attention bits */
5876 #define TSTORM_FATAL_ASSERT_ATTENTION_BIT     RESERVED_GENERAL_ATTENTION_BIT_7
5877 #define USTORM_FATAL_ASSERT_ATTENTION_BIT     RESERVED_GENERAL_ATTENTION_BIT_8
5878 #define CSTORM_FATAL_ASSERT_ATTENTION_BIT     RESERVED_GENERAL_ATTENTION_BIT_9
5879 #define XSTORM_FATAL_ASSERT_ATTENTION_BIT     RESERVED_GENERAL_ATTENTION_BIT_10
5880
5881 /* mcp error attention bit */
5882 #define MCP_FATAL_ASSERT_ATTENTION_BIT        RESERVED_GENERAL_ATTENTION_BIT_11
5883
5884 /*E1H NIG status sync attention mapped to group 4-7*/
5885 #define LINK_SYNC_ATTENTION_BIT_FUNC_0      RESERVED_GENERAL_ATTENTION_BIT_12
5886 #define LINK_SYNC_ATTENTION_BIT_FUNC_1      RESERVED_GENERAL_ATTENTION_BIT_13
5887 #define LINK_SYNC_ATTENTION_BIT_FUNC_2      RESERVED_GENERAL_ATTENTION_BIT_14
5888 #define LINK_SYNC_ATTENTION_BIT_FUNC_3      RESERVED_GENERAL_ATTENTION_BIT_15
5889 #define LINK_SYNC_ATTENTION_BIT_FUNC_4      RESERVED_GENERAL_ATTENTION_BIT_16
5890 #define LINK_SYNC_ATTENTION_BIT_FUNC_5      RESERVED_GENERAL_ATTENTION_BIT_17
5891 #define LINK_SYNC_ATTENTION_BIT_FUNC_6      RESERVED_GENERAL_ATTENTION_BIT_18
5892 #define LINK_SYNC_ATTENTION_BIT_FUNC_7      RESERVED_GENERAL_ATTENTION_BIT_19
5893
5894
5895 #define LATCHED_ATTN_RBCR                       23
5896 #define LATCHED_ATTN_RBCT                       24
5897 #define LATCHED_ATTN_RBCN                       25
5898 #define LATCHED_ATTN_RBCU                       26
5899 #define LATCHED_ATTN_RBCP                       27
5900 #define LATCHED_ATTN_TIMEOUT_GRC                28
5901 #define LATCHED_ATTN_RSVD_GRC                   29
5902 #define LATCHED_ATTN_ROM_PARITY_MCP             30
5903 #define LATCHED_ATTN_UM_RX_PARITY_MCP           31
5904 #define LATCHED_ATTN_UM_TX_PARITY_MCP           32
5905 #define LATCHED_ATTN_SCPAD_PARITY_MCP           33
5906
5907 #define GENERAL_ATTEN_WORD(atten_name)         ((94 + atten_name) / 32)
5908 #define GENERAL_ATTEN_OFFSET(atten_name)\
5909         (1UL << ((94 + atten_name) % 32))
5910 /*
5911  * This file defines GRC base address for every block.
5912  * This file is included by chipsim, asm microcode and cpp microcode.
5913  * These values are used in Design.xml on regBase attribute
5914  * Use the base with the generated offsets of specific registers.
5915  */
5916
5917 #define GRCBASE_PXPCS           0x000000
5918 #define GRCBASE_PCICONFIG       0x002000
5919 #define GRCBASE_PCIREG          0x002400
5920 #define GRCBASE_EMAC0           0x008000
5921 #define GRCBASE_EMAC1           0x008400
5922 #define GRCBASE_DBU             0x008800
5923 #define GRCBASE_MISC            0x00A000
5924 #define GRCBASE_DBG             0x00C000
5925 #define GRCBASE_NIG             0x010000
5926 #define GRCBASE_XCM             0x020000
5927 #define GRCBASE_PRS             0x040000
5928 #define GRCBASE_SRCH            0x040400
5929 #define GRCBASE_TSDM            0x042000
5930 #define GRCBASE_TCM             0x050000
5931 #define GRCBASE_BRB1            0x060000
5932 #define GRCBASE_MCP             0x080000
5933 #define GRCBASE_UPB             0x0C1000
5934 #define GRCBASE_CSDM            0x0C2000
5935 #define GRCBASE_USDM            0x0C4000
5936 #define GRCBASE_CCM             0x0D0000
5937 #define GRCBASE_UCM             0x0E0000
5938 #define GRCBASE_CDU             0x101000
5939 #define GRCBASE_DMAE            0x102000
5940 #define GRCBASE_PXP             0x103000
5941 #define GRCBASE_CFC             0x104000
5942 #define GRCBASE_HC              0x108000
5943 #define GRCBASE_PXP2            0x120000
5944 #define GRCBASE_PBF             0x140000
5945 #define GRCBASE_UMAC0           0x160000
5946 #define GRCBASE_UMAC1           0x160400
5947 #define GRCBASE_XPB             0x161000
5948 #define GRCBASE_MSTAT0      0x162000
5949 #define GRCBASE_MSTAT1      0x162800
5950 #define GRCBASE_XMAC0           0x163000
5951 #define GRCBASE_XMAC1           0x163800
5952 #define GRCBASE_TIMERS          0x164000
5953 #define GRCBASE_XSDM            0x166000
5954 #define GRCBASE_QM              0x168000
5955 #define GRCBASE_DQ              0x170000
5956 #define GRCBASE_TSEM            0x180000
5957 #define GRCBASE_CSEM            0x200000
5958 #define GRCBASE_XSEM            0x280000
5959 #define GRCBASE_USEM            0x300000
5960 #define GRCBASE_MISC_AEU        GRCBASE_MISC
5961
5962
5963 /* offset of configuration space in the pci core register */
5964 #define PCICFG_OFFSET                                   0x2000
5965 #define PCICFG_VENDOR_ID_OFFSET                         0x00
5966 #define PCICFG_DEVICE_ID_OFFSET                         0x02
5967 #define PCICFG_COMMAND_OFFSET                           0x04
5968 #define PCICFG_COMMAND_IO_SPACE                 (1<<0)
5969 #define PCICFG_COMMAND_MEM_SPACE                (1<<1)
5970 #define PCICFG_COMMAND_BUS_MASTER               (1<<2)
5971 #define PCICFG_COMMAND_SPECIAL_CYCLES           (1<<3)
5972 #define PCICFG_COMMAND_MWI_CYCLES               (1<<4)
5973 #define PCICFG_COMMAND_VGA_SNOOP                (1<<5)
5974 #define PCICFG_COMMAND_PERR_ENA                 (1<<6)
5975 #define PCICFG_COMMAND_STEPPING                 (1<<7)
5976 #define PCICFG_COMMAND_SERR_ENA                 (1<<8)
5977 #define PCICFG_COMMAND_FAST_B2B                 (1<<9)
5978 #define PCICFG_COMMAND_INT_DISABLE              (1<<10)
5979 #define PCICFG_COMMAND_RESERVED                 (0x1f<<11)
5980 #define PCICFG_STATUS_OFFSET                            0x06
5981 #define PCICFG_REVESION_ID_OFFSET                       0x08
5982 #define PCICFG_CACHE_LINE_SIZE                          0x0c
5983 #define PCICFG_LATENCY_TIMER                            0x0d
5984 #define PCICFG_BAR_1_LOW                                0x10
5985 #define PCICFG_BAR_1_HIGH                               0x14
5986 #define PCICFG_BAR_2_LOW                                0x18
5987 #define PCICFG_BAR_2_HIGH                               0x1c
5988 #define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET               0x2c
5989 #define PCICFG_SUBSYSTEM_ID_OFFSET                      0x2e
5990 #define PCICFG_INT_LINE                                 0x3c
5991 #define PCICFG_INT_PIN                                  0x3d
5992 #define PCICFG_PM_CAPABILITY                            0x48
5993 #define PCICFG_PM_CAPABILITY_VERSION            (0x3<<16)
5994 #define PCICFG_PM_CAPABILITY_CLOCK              (1<<19)
5995 #define PCICFG_PM_CAPABILITY_RESERVED           (1<<20)
5996 #define PCICFG_PM_CAPABILITY_DSI                (1<<21)
5997 #define PCICFG_PM_CAPABILITY_AUX_CURRENT        (0x7<<22)
5998 #define PCICFG_PM_CAPABILITY_D1_SUPPORT         (1<<25)
5999 #define PCICFG_PM_CAPABILITY_D2_SUPPORT         (1<<26)
6000 #define PCICFG_PM_CAPABILITY_PME_IN_D0          (1<<27)
6001 #define PCICFG_PM_CAPABILITY_PME_IN_D1          (1<<28)
6002 #define PCICFG_PM_CAPABILITY_PME_IN_D2          (1<<29)
6003 #define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT      (1<<30)
6004 #define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD     (1<<31)
6005 #define PCICFG_PM_CSR_OFFSET                            0x4c
6006 #define PCICFG_PM_CSR_STATE                     (0x3<<0)
6007 #define PCICFG_PM_CSR_PME_ENABLE                (1<<8)
6008 #define PCICFG_PM_CSR_PME_STATUS                (1<<15)
6009 #define PCICFG_MSI_CAP_ID_OFFSET                        0x58
6010 #define PCICFG_MSI_CONTROL_ENABLE               (0x1<<16)
6011 #define PCICFG_MSI_CONTROL_MCAP                 (0x7<<17)
6012 #define PCICFG_MSI_CONTROL_MENA                 (0x7<<20)
6013 #define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP      (0x1<<23)
6014 #define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE   (0x1<<24)
6015 #define PCICFG_GRC_ADDRESS                              0x78
6016 #define PCICFG_GRC_DATA                                 0x80
6017 #define PCICFG_MSIX_CAP_ID_OFFSET                       0xa0
6018 #define PCICFG_MSIX_CONTROL_TABLE_SIZE          (0x7ff<<16)
6019 #define PCICFG_MSIX_CONTROL_RESERVED            (0x7<<27)
6020 #define PCICFG_MSIX_CONTROL_FUNC_MASK           (0x1<<30)
6021 #define PCICFG_MSIX_CONTROL_MSIX_ENABLE         (0x1<<31)
6022
6023 #define PCICFG_DEVICE_CONTROL                           0xb4
6024 #define PCICFG_DEVICE_STATUS                            0xb6
6025 #define PCICFG_DEVICE_STATUS_CORR_ERR_DET       (1<<0)
6026 #define PCICFG_DEVICE_STATUS_NON_FATAL_ERR_DET  (1<<1)
6027 #define PCICFG_DEVICE_STATUS_FATAL_ERR_DET      (1<<2)
6028 #define PCICFG_DEVICE_STATUS_UNSUP_REQ_DET      (1<<3)
6029 #define PCICFG_DEVICE_STATUS_AUX_PWR_DET        (1<<4)
6030 #define PCICFG_DEVICE_STATUS_NO_PEND            (1<<5)
6031 #define PCICFG_LINK_CONTROL                             0xbc
6032
6033
6034 #define BAR_USTRORM_INTMEM                              0x400000
6035 #define BAR_CSTRORM_INTMEM                              0x410000
6036 #define BAR_XSTRORM_INTMEM                              0x420000
6037 #define BAR_TSTRORM_INTMEM                              0x430000
6038
6039 /* for accessing the IGU in case of status block ACK */
6040 #define BAR_IGU_INTMEM                                  0x440000
6041
6042 #define BAR_DOORBELL_OFFSET                             0x800000
6043
6044 #define BAR_ME_REGISTER                                 0x450000
6045
6046 /* config_2 offset */
6047 #define GRC_CONFIG_2_SIZE_REG                           0x408
6048 #define PCI_CONFIG_2_BAR1_SIZE                  (0xfL<<0)
6049 #define PCI_CONFIG_2_BAR1_SIZE_DISABLED         (0L<<0)
6050 #define PCI_CONFIG_2_BAR1_SIZE_64K              (1L<<0)
6051 #define PCI_CONFIG_2_BAR1_SIZE_128K             (2L<<0)
6052 #define PCI_CONFIG_2_BAR1_SIZE_256K             (3L<<0)
6053 #define PCI_CONFIG_2_BAR1_SIZE_512K             (4L<<0)
6054 #define PCI_CONFIG_2_BAR1_SIZE_1M               (5L<<0)
6055 #define PCI_CONFIG_2_BAR1_SIZE_2M               (6L<<0)
6056 #define PCI_CONFIG_2_BAR1_SIZE_4M               (7L<<0)
6057 #define PCI_CONFIG_2_BAR1_SIZE_8M               (8L<<0)
6058 #define PCI_CONFIG_2_BAR1_SIZE_16M              (9L<<0)
6059 #define PCI_CONFIG_2_BAR1_SIZE_32M              (10L<<0)
6060 #define PCI_CONFIG_2_BAR1_SIZE_64M              (11L<<0)
6061 #define PCI_CONFIG_2_BAR1_SIZE_128M             (12L<<0)
6062 #define PCI_CONFIG_2_BAR1_SIZE_256M             (13L<<0)
6063 #define PCI_CONFIG_2_BAR1_SIZE_512M             (14L<<0)
6064 #define PCI_CONFIG_2_BAR1_SIZE_1G               (15L<<0)
6065 #define PCI_CONFIG_2_BAR1_64ENA                 (1L<<4)
6066 #define PCI_CONFIG_2_EXP_ROM_RETRY              (1L<<5)
6067 #define PCI_CONFIG_2_CFG_CYCLE_RETRY            (1L<<6)
6068 #define PCI_CONFIG_2_FIRST_CFG_DONE             (1L<<7)
6069 #define PCI_CONFIG_2_EXP_ROM_SIZE               (0xffL<<8)
6070 #define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED      (0L<<8)
6071 #define PCI_CONFIG_2_EXP_ROM_SIZE_2K            (1L<<8)
6072 #define PCI_CONFIG_2_EXP_ROM_SIZE_4K            (2L<<8)
6073 #define PCI_CONFIG_2_EXP_ROM_SIZE_8K            (3L<<8)
6074 #define PCI_CONFIG_2_EXP_ROM_SIZE_16K           (4L<<8)
6075 #define PCI_CONFIG_2_EXP_ROM_SIZE_32K           (5L<<8)
6076 #define PCI_CONFIG_2_EXP_ROM_SIZE_64K           (6L<<8)
6077 #define PCI_CONFIG_2_EXP_ROM_SIZE_128K          (7L<<8)
6078 #define PCI_CONFIG_2_EXP_ROM_SIZE_256K          (8L<<8)
6079 #define PCI_CONFIG_2_EXP_ROM_SIZE_512K          (9L<<8)
6080 #define PCI_CONFIG_2_EXP_ROM_SIZE_1M            (10L<<8)
6081 #define PCI_CONFIG_2_EXP_ROM_SIZE_2M            (11L<<8)
6082 #define PCI_CONFIG_2_EXP_ROM_SIZE_4M            (12L<<8)
6083 #define PCI_CONFIG_2_EXP_ROM_SIZE_8M            (13L<<8)
6084 #define PCI_CONFIG_2_EXP_ROM_SIZE_16M           (14L<<8)
6085 #define PCI_CONFIG_2_EXP_ROM_SIZE_32M           (15L<<8)
6086 #define PCI_CONFIG_2_BAR_PREFETCH               (1L<<16)
6087 #define PCI_CONFIG_2_RESERVED0                  (0x7fffL<<17)
6088
6089 /* config_3 offset */
6090 #define GRC_CONFIG_3_SIZE_REG                           0x40c
6091 #define PCI_CONFIG_3_STICKY_BYTE                (0xffL<<0)
6092 #define PCI_CONFIG_3_FORCE_PME                  (1L<<24)
6093 #define PCI_CONFIG_3_PME_STATUS                 (1L<<25)
6094 #define PCI_CONFIG_3_PME_ENABLE                 (1L<<26)
6095 #define PCI_CONFIG_3_PM_STATE                   (0x3L<<27)
6096 #define PCI_CONFIG_3_VAUX_PRESET                (1L<<30)
6097 #define PCI_CONFIG_3_PCI_POWER                  (1L<<31)
6098
6099 #define GRC_BAR2_CONFIG                                 0x4e0
6100 #define PCI_CONFIG_2_BAR2_SIZE                  (0xfL<<0)
6101 #define PCI_CONFIG_2_BAR2_SIZE_DISABLED         (0L<<0)
6102 #define PCI_CONFIG_2_BAR2_SIZE_64K              (1L<<0)
6103 #define PCI_CONFIG_2_BAR2_SIZE_128K             (2L<<0)
6104 #define PCI_CONFIG_2_BAR2_SIZE_256K             (3L<<0)
6105 #define PCI_CONFIG_2_BAR2_SIZE_512K             (4L<<0)
6106 #define PCI_CONFIG_2_BAR2_SIZE_1M               (5L<<0)
6107 #define PCI_CONFIG_2_BAR2_SIZE_2M               (6L<<0)
6108 #define PCI_CONFIG_2_BAR2_SIZE_4M               (7L<<0)
6109 #define PCI_CONFIG_2_BAR2_SIZE_8M               (8L<<0)
6110 #define PCI_CONFIG_2_BAR2_SIZE_16M              (9L<<0)
6111 #define PCI_CONFIG_2_BAR2_SIZE_32M              (10L<<0)
6112 #define PCI_CONFIG_2_BAR2_SIZE_64M              (11L<<0)
6113 #define PCI_CONFIG_2_BAR2_SIZE_128M             (12L<<0)
6114 #define PCI_CONFIG_2_BAR2_SIZE_256M             (13L<<0)
6115 #define PCI_CONFIG_2_BAR2_SIZE_512M             (14L<<0)
6116 #define PCI_CONFIG_2_BAR2_SIZE_1G               (15L<<0)
6117 #define PCI_CONFIG_2_BAR2_64ENA                 (1L<<4)
6118
6119 #define PCI_PM_DATA_A                                   0x410
6120 #define PCI_PM_DATA_B                                   0x414
6121 #define PCI_ID_VAL1                                     0x434
6122 #define PCI_ID_VAL2                                     0x438
6123
6124 #define PXPCS_TL_CONTROL_5                  0x814
6125 #define PXPCS_TL_CONTROL_5_UNKNOWNTYPE_ERR_ATTN    (1 << 29) /*WC*/
6126 #define PXPCS_TL_CONTROL_5_BOUNDARY4K_ERR_ATTN     (1 << 28)   /*WC*/
6127 #define PXPCS_TL_CONTROL_5_MRRS_ERR_ATTN   (1 << 27)   /*WC*/
6128 #define PXPCS_TL_CONTROL_5_MPS_ERR_ATTN    (1 << 26)   /*WC*/
6129 #define PXPCS_TL_CONTROL_5_TTX_BRIDGE_FORWARD_ERR  (1 << 25)   /*WC*/
6130 #define PXPCS_TL_CONTROL_5_TTX_TXINTF_OVERFLOW     (1 << 24)   /*WC*/
6131 #define PXPCS_TL_CONTROL_5_PHY_ERR_ATTN    (1 << 23)   /*RO*/
6132 #define PXPCS_TL_CONTROL_5_DL_ERR_ATTN     (1 << 22)   /*RO*/
6133 #define PXPCS_TL_CONTROL_5_TTX_ERR_NP_TAG_IN_USE   (1 << 21)   /*WC*/
6134 #define PXPCS_TL_CONTROL_5_TRX_ERR_UNEXP_RTAG  (1 << 20)   /*WC*/
6135 #define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT1   (1 << 19)   /*WC*/
6136 #define PXPCS_TL_CONTROL_5_ERR_UNSPPORT1   (1 << 18)   /*WC*/
6137 #define PXPCS_TL_CONTROL_5_ERR_ECRC1   (1 << 17)   /*WC*/
6138 #define PXPCS_TL_CONTROL_5_ERR_MALF_TLP1   (1 << 16)   /*WC*/
6139 #define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW1   (1 << 15)   /*WC*/
6140 #define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL1  (1 << 14)   /*WC*/
6141 #define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT1    (1 << 13)   /*WC*/
6142 #define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT1    (1 << 12)   /*WC*/
6143 #define PXPCS_TL_CONTROL_5_ERR_FC_PRTL1    (1 << 11)   /*WC*/
6144 #define PXPCS_TL_CONTROL_5_ERR_PSND_TLP1   (1 << 10)   /*WC*/
6145 #define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT    (1 << 9)    /*WC*/
6146 #define PXPCS_TL_CONTROL_5_ERR_UNSPPORT    (1 << 8)    /*WC*/
6147 #define PXPCS_TL_CONTROL_5_ERR_ECRC    (1 << 7)    /*WC*/
6148 #define PXPCS_TL_CONTROL_5_ERR_MALF_TLP    (1 << 6)    /*WC*/
6149 #define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW    (1 << 5)    /*WC*/
6150 #define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL   (1 << 4)    /*WC*/
6151 #define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT     (1 << 3)    /*WC*/
6152 #define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT     (1 << 2)    /*WC*/
6153 #define PXPCS_TL_CONTROL_5_ERR_FC_PRTL     (1 << 1)    /*WC*/
6154 #define PXPCS_TL_CONTROL_5_ERR_PSND_TLP    (1 << 0)    /*WC*/
6155
6156
6157 #define PXPCS_TL_FUNC345_STAT      0x854
6158 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT4    (1 << 29)   /* WC */
6159 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4\
6160         (1 << 28) /* Unsupported Request Error Status in function4, if \
6161         set, generate pcie_err_attn output when this error is seen. WC */
6162 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC4\
6163         (1 << 27) /* ECRC Error TLP Status Status in function 4, if set, \
6164         generate pcie_err_attn output when this error is seen.. WC */
6165 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP4\
6166         (1 << 26) /* Malformed TLP Status Status in function 4, if set, \
6167         generate pcie_err_attn output when this error is seen.. WC */
6168 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW4\
6169         (1 << 25) /* Receiver Overflow Status Status in function 4, if \
6170         set, generate pcie_err_attn output when this error is seen.. WC \
6171         */
6172 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL4\
6173         (1 << 24) /* Unexpected Completion Status Status in function 4, \
6174         if set, generate pcie_err_attn output when this error is seen. WC \
6175         */
6176 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT4\
6177         (1 << 23) /* Receive UR Statusin function 4. If set, generate \
6178         pcie_err_attn output when this error is seen. WC */
6179 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT4\
6180         (1 << 22) /* Completer Timeout Status Status in function 4, if \
6181         set, generate pcie_err_attn output when this error is seen. WC */
6182 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL4\
6183         (1 << 21) /* Flow Control Protocol Error Status Status in \
6184         function 4, if set, generate pcie_err_attn output when this error \
6185         is seen. WC */
6186 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP4\
6187         (1 << 20) /* Poisoned Error Status Status in function 4, if set, \
6188         generate pcie_err_attn output when this error is seen.. WC */
6189 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT3    (1 << 19)   /* WC */
6190 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3\
6191         (1 << 18) /* Unsupported Request Error Status in function3, if \
6192         set, generate pcie_err_attn output when this error is seen. WC */
6193 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC3\
6194         (1 << 17) /* ECRC Error TLP Status Status in function 3, if set, \
6195         generate pcie_err_attn output when this error is seen.. WC */
6196 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP3\
6197         (1 << 16) /* Malformed TLP Status Status in function 3, if set, \
6198         generate pcie_err_attn output when this error is seen.. WC */
6199 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW3\
6200         (1 << 15) /* Receiver Overflow Status Status in function 3, if \
6201         set, generate pcie_err_attn output when this error is seen.. WC \
6202         */
6203 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL3\
6204         (1 << 14) /* Unexpected Completion Status Status in function 3, \
6205         if set, generate pcie_err_attn output when this error is seen. WC \
6206         */
6207 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT3\
6208         (1 << 13) /* Receive UR Statusin function 3. If set, generate \
6209         pcie_err_attn output when this error is seen. WC */
6210 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT3\
6211         (1 << 12) /* Completer Timeout Status Status in function 3, if \
6212         set, generate pcie_err_attn output when this error is seen. WC */
6213 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL3\
6214         (1 << 11) /* Flow Control Protocol Error Status Status in \
6215         function 3, if set, generate pcie_err_attn output when this error \
6216         is seen. WC */
6217 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP3\
6218         (1 << 10) /* Poisoned Error Status Status in function 3, if set, \
6219         generate pcie_err_attn output when this error is seen.. WC */
6220 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT2    (1 << 9)    /* WC */
6221 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2\
6222         (1 << 8) /* Unsupported Request Error Status for Function 2, if \
6223         set, generate pcie_err_attn output when this error is seen. WC */
6224 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC2\
6225         (1 << 7) /* ECRC Error TLP Status Status for Function 2, if set, \
6226         generate pcie_err_attn output when this error is seen.. WC */
6227 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP2\
6228         (1 << 6) /* Malformed TLP Status Status for Function 2, if set, \
6229         generate pcie_err_attn output when this error is seen.. WC */
6230 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW2\
6231         (1 << 5) /* Receiver Overflow Status Status for Function 2, if \
6232         set, generate pcie_err_attn output when this error is seen.. WC \
6233         */
6234 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL2\
6235         (1 << 4) /* Unexpected Completion Status Status for Function 2, \
6236         if set, generate pcie_err_attn output when this error is seen. WC \
6237         */
6238 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT2\
6239         (1 << 3) /* Receive UR Statusfor Function 2. If set, generate \
6240         pcie_err_attn output when this error is seen. WC */
6241 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT2\
6242         (1 << 2) /* Completer Timeout Status Status for Function 2, if \
6243         set, generate pcie_err_attn output when this error is seen. WC */
6244 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL2\
6245         (1 << 1) /* Flow Control Protocol Error Status Status for \
6246         Function 2, if set, generate pcie_err_attn output when this error \
6247         is seen. WC */
6248 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP2\
6249         (1 << 0) /* Poisoned Error Status Status for Function 2, if set, \
6250         generate pcie_err_attn output when this error is seen.. WC */
6251
6252
6253 #define PXPCS_TL_FUNC678_STAT  0x85C
6254 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT7    (1 << 29)   /*    WC */
6255 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7\
6256         (1 << 28) /* Unsupported Request Error Status in function7, if \
6257         set, generate pcie_err_attn output when this error is seen. WC */
6258 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC7\
6259         (1 << 27) /* ECRC Error TLP Status Status in function 7, if set, \
6260         generate pcie_err_attn output when this error is seen.. WC */
6261 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP7\
6262         (1 << 26) /* Malformed TLP Status Status in function 7, if set, \
6263         generate pcie_err_attn output when this error is seen.. WC */
6264 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW7\
6265         (1 << 25) /* Receiver Overflow Status Status in function 7, if \
6266         set, generate pcie_err_attn output when this error is seen.. WC \
6267         */
6268 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL7\
6269         (1 << 24) /* Unexpected Completion Status Status in function 7, \
6270         if set, generate pcie_err_attn output when this error is seen. WC \
6271         */
6272 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT7\
6273         (1 << 23) /* Receive UR Statusin function 7. If set, generate \
6274         pcie_err_attn output when this error is seen. WC */
6275 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT7\
6276         (1 << 22) /* Completer Timeout Status Status in function 7, if \
6277         set, generate pcie_err_attn output when this error is seen. WC */
6278 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL7\
6279         (1 << 21) /* Flow Control Protocol Error Status Status in \
6280         function 7, if set, generate pcie_err_attn output when this error \
6281         is seen. WC */
6282 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP7\
6283         (1 << 20) /* Poisoned Error Status Status in function 7, if set, \
6284         generate pcie_err_attn output when this error is seen.. WC */
6285 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT6    (1 << 19)    /*    WC */
6286 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6\
6287         (1 << 18) /* Unsupported Request Error Status in function6, if \
6288         set, generate pcie_err_attn output when this error is seen. WC */
6289 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC6\
6290         (1 << 17) /* ECRC Error TLP Status Status in function 6, if set, \
6291         generate pcie_err_attn output when this error is seen.. WC */
6292 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP6\
6293         (1 << 16) /* Malformed TLP Status Status in function 6, if set, \
6294         generate pcie_err_attn output when this error is seen.. WC */
6295 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW6\
6296         (1 << 15) /* Receiver Overflow Status Status in function 6, if \
6297         set, generate pcie_err_attn output when this error is seen.. WC \
6298         */
6299 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL6\
6300         (1 << 14) /* Unexpected Completion Status Status in function 6, \
6301         if set, generate pcie_err_attn output when this error is seen. WC \
6302         */
6303 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT6\
6304         (1 << 13) /* Receive UR Statusin function 6. If set, generate \
6305         pcie_err_attn output when this error is seen. WC */
6306 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT6\
6307         (1 << 12) /* Completer Timeout Status Status in function 6, if \
6308         set, generate pcie_err_attn output when this error is seen. WC */
6309 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL6\
6310         (1 << 11) /* Flow Control Protocol Error Status Status in \
6311         function 6, if set, generate pcie_err_attn output when this error \
6312         is seen. WC */
6313 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP6\
6314         (1 << 10) /* Poisoned Error Status Status in function 6, if set, \
6315         generate pcie_err_attn output when this error is seen.. WC */
6316 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT5    (1 << 9) /*    WC */
6317 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5\
6318         (1 << 8) /* Unsupported Request Error Status for Function 5, if \
6319         set, generate pcie_err_attn output when this error is seen. WC */
6320 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC5\
6321         (1 << 7) /* ECRC Error TLP Status Status for Function 5, if set, \
6322         generate pcie_err_attn output when this error is seen.. WC */
6323 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP5\
6324         (1 << 6) /* Malformed TLP Status Status for Function 5, if set, \
6325         generate pcie_err_attn output when this error is seen.. WC */
6326 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW5\
6327         (1 << 5) /* Receiver Overflow Status Status for Function 5, if \
6328         set, generate pcie_err_attn output when this error is seen.. WC \
6329         */
6330 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL5\
6331         (1 << 4) /* Unexpected Completion Status Status for Function 5, \
6332         if set, generate pcie_err_attn output when this error is seen. WC \
6333         */
6334 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT5\
6335         (1 << 3) /* Receive UR Statusfor Function 5. If set, generate \
6336         pcie_err_attn output when this error is seen. WC */
6337 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT5\
6338         (1 << 2) /* Completer Timeout Status Status for Function 5, if \
6339         set, generate pcie_err_attn output when this error is seen. WC */
6340 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL5\
6341         (1 << 1) /* Flow Control Protocol Error Status Status for \
6342         Function 5, if set, generate pcie_err_attn output when this error \
6343         is seen. WC */
6344 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP5\
6345         (1 << 0) /* Poisoned Error Status Status for Function 5, if set, \
6346         generate pcie_err_attn output when this error is seen.. WC */
6347
6348
6349 #define BAR_USTRORM_INTMEM                              0x400000
6350 #define BAR_CSTRORM_INTMEM                              0x410000
6351 #define BAR_XSTRORM_INTMEM                              0x420000
6352 #define BAR_TSTRORM_INTMEM                              0x430000
6353
6354 /* for accessing the IGU in case of status block ACK */
6355 #define BAR_IGU_INTMEM                                  0x440000
6356
6357 #define BAR_DOORBELL_OFFSET                             0x800000
6358
6359 #define BAR_ME_REGISTER                         0x450000
6360 #define ME_REG_PF_NUM_SHIFT             0
6361 #define ME_REG_PF_NUM\
6362         (7L<<ME_REG_PF_NUM_SHIFT) /* Relative PF Num */
6363 #define ME_REG_VF_VALID         (1<<8)
6364 #define ME_REG_VF_NUM_SHIFT             9
6365 #define ME_REG_VF_NUM_MASK              (0x3f<<ME_REG_VF_NUM_SHIFT)
6366 #define ME_REG_VF_ERR                   (0x1<<3)
6367 #define ME_REG_ABS_PF_NUM_SHIFT 16
6368 #define ME_REG_ABS_PF_NUM\
6369         (7L<<ME_REG_ABS_PF_NUM_SHIFT) /* Absolute PF Num */
6370
6371
6372 #define MDIO_REG_BANK_CL73_IEEEB0       0x0
6373 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL        0x0
6374 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN     0x0200
6375 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN          0x1000
6376 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST       0x8000
6377
6378 #define MDIO_REG_BANK_CL73_IEEEB1       0x10
6379 #define MDIO_CL73_IEEEB1_AN_ADV1                0x00
6380 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE                  0x0400
6381 #define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC             0x0800
6382 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH             0x0C00
6383 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK             0x0C00
6384 #define MDIO_CL73_IEEEB1_AN_ADV2                0x01
6385 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M             0x0000
6386 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX          0x0020
6387 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4           0x0040
6388 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR            0x0080
6389 #define MDIO_CL73_IEEEB1_AN_LP_ADV1             0x03
6390 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE               0x0400
6391 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC          0x0800
6392 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH          0x0C00
6393 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK          0x0C00
6394
6395 #define MDIO_REG_BANK_RX0                               0x80b0
6396 #define MDIO_RX0_RX_STATUS                              0x10
6397 #define MDIO_RX0_RX_STATUS_SIGDET                       0x8000
6398 #define MDIO_RX0_RX_STATUS_RX_SEQ_DONE                  0x1000
6399 #define MDIO_RX0_RX_EQ_BOOST                            0x1c
6400 #define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK        0x7
6401 #define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL                0x10
6402
6403 #define MDIO_REG_BANK_RX1                               0x80c0
6404 #define MDIO_RX1_RX_EQ_BOOST                            0x1c
6405 #define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK        0x7
6406 #define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL                0x10
6407
6408 #define MDIO_REG_BANK_RX2                               0x80d0
6409 #define MDIO_RX2_RX_EQ_BOOST                            0x1c
6410 #define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK        0x7
6411 #define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL                0x10
6412
6413 #define MDIO_REG_BANK_RX3                               0x80e0
6414 #define MDIO_RX3_RX_EQ_BOOST                            0x1c
6415 #define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK        0x7
6416 #define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL                0x10
6417
6418 #define MDIO_REG_BANK_RX_ALL                            0x80f0
6419 #define MDIO_RX_ALL_RX_EQ_BOOST                         0x1c
6420 #define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK     0x7
6421 #define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL     0x10
6422
6423 #define MDIO_REG_BANK_TX0                               0x8060
6424 #define MDIO_TX0_TX_DRIVER                              0x17
6425 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK             0xf000
6426 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT            12
6427 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK                 0x0f00
6428 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT                8
6429 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK              0x00f0
6430 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT             4
6431 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK                0x000e
6432 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT               1
6433 #define MDIO_TX0_TX_DRIVER_ICBUF1T                      1
6434
6435 #define MDIO_REG_BANK_TX1                               0x8070
6436 #define MDIO_TX1_TX_DRIVER                              0x17
6437 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK             0xf000
6438 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT            12
6439 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK                 0x0f00
6440 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT                8
6441 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK              0x00f0
6442 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT             4
6443 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK                0x000e
6444 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT               1
6445 #define MDIO_TX0_TX_DRIVER_ICBUF1T                      1
6446
6447 #define MDIO_REG_BANK_TX2                               0x8080
6448 #define MDIO_TX2_TX_DRIVER                              0x17
6449 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK             0xf000
6450 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT            12
6451 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK                 0x0f00
6452 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT                8
6453 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK              0x00f0
6454 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT             4
6455 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK                0x000e
6456 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT               1
6457 #define MDIO_TX0_TX_DRIVER_ICBUF1T                      1
6458
6459 #define MDIO_REG_BANK_TX3                               0x8090
6460 #define MDIO_TX3_TX_DRIVER                              0x17
6461 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK             0xf000
6462 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT            12
6463 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK                 0x0f00
6464 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT                8
6465 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK              0x00f0
6466 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT             4
6467 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK                0x000e
6468 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT               1
6469 #define MDIO_TX0_TX_DRIVER_ICBUF1T                      1
6470
6471 #define MDIO_REG_BANK_XGXS_BLOCK0                       0x8000
6472 #define MDIO_BLOCK0_XGXS_CONTROL                        0x10
6473
6474 #define MDIO_REG_BANK_XGXS_BLOCK1                       0x8010
6475 #define MDIO_BLOCK1_LANE_CTRL0                          0x15
6476 #define MDIO_BLOCK1_LANE_CTRL1                          0x16
6477 #define MDIO_BLOCK1_LANE_CTRL2                          0x17
6478 #define MDIO_BLOCK1_LANE_PRBS                           0x19
6479
6480 #define MDIO_REG_BANK_XGXS_BLOCK2                       0x8100
6481 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP                     0x10
6482 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE              0x8000
6483 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE        0x4000
6484 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP             0x11
6485 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE              0x8000
6486 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G       0x14
6487 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS      0x0001
6488 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS    0x0010
6489 #define MDIO_XGXS_BLOCK2_TEST_MODE_LANE         0x15
6490
6491 #define MDIO_REG_BANK_GP_STATUS                         0x8120
6492 #define MDIO_GP_STATUS_TOP_AN_STATUS1                           0x1B
6493 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE     0x0001
6494 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE     0x0002
6495 #define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS               0x0004
6496 #define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS             0x0008
6497 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE     0x0010
6498 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE       0x0020
6499 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE    0x0040
6500 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE    0x0080
6501 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK         0x3f00
6502 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M          0x0000
6503 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M         0x0100
6504 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G           0x0200
6505 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G         0x0300
6506 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G           0x0400
6507 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G           0x0500
6508 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG      0x0600
6509 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4      0x0700
6510 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG      0x0800
6511 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G        0x0900
6512 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G          0x0A00
6513 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G          0x0B00
6514 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G          0x0C00
6515 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX        0x0D00
6516 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4      0x0E00
6517 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR       0x0F00
6518 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI      0x1B00
6519 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS    0x1E00
6520 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI      0x1F00
6521
6522
6523 #define MDIO_REG_BANK_10G_PARALLEL_DETECT               0x8130
6524 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS             0x10
6525 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK             0x8000
6526 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL            0x11
6527 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN       0x1
6528 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK               0x13
6529 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT           (0xb71<<1)
6530
6531 #define MDIO_REG_BANK_SERDES_DIGITAL                    0x8300
6532 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1                    0x10
6533 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE                 0x0001
6534 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF                     0x0002
6535 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN           0x0004
6536 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT       0x0008
6537 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET                    0x0010
6538 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE                  0x0020
6539 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2                    0x11
6540 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN                  0x0001
6541 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR                 0x0040
6542 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1                     0x14
6543 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII                       0x0001
6544 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK                        0x0002
6545 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX                      0x0004
6546 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK                  0x0018
6547 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT                 3
6548 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G                  0x0018
6549 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G                    0x0010
6550 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M                  0x0008
6551 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M                   0x0000
6552 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2                     0x15
6553 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED                 0x0002
6554 #define MDIO_SERDES_DIGITAL_MISC1                               0x18
6555 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK                       0xE000
6556 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M                        0x0000
6557 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M                       0x2000
6558 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M                       0x4000
6559 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M                    0x6000
6560 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M                     0x8000
6561 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL                       0x0010
6562 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK                      0x000f
6563 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G                      0x0000
6564 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G                        0x0001
6565 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G                        0x0002
6566 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG                   0x0003
6567 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4                   0x0004
6568 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G                       0x0005
6569 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G                     0x0006
6570 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G                       0x0007
6571 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G                       0x0008
6572 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G                       0x0009
6573
6574 #define MDIO_REG_BANK_OVER_1G                           0x8320
6575 #define MDIO_OVER_1G_DIGCTL_3_4                                 0x14
6576 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK                              0xffe0
6577 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT                             5
6578 #define MDIO_OVER_1G_UP1                                        0x19
6579 #define MDIO_OVER_1G_UP1_2_5G                                           0x0001
6580 #define MDIO_OVER_1G_UP1_5G                                             0x0002
6581 #define MDIO_OVER_1G_UP1_6G                                             0x0004
6582 #define MDIO_OVER_1G_UP1_10G                                            0x0010
6583 #define MDIO_OVER_1G_UP1_10GH                                           0x0008
6584 #define MDIO_OVER_1G_UP1_12G                                            0x0020
6585 #define MDIO_OVER_1G_UP1_12_5G                                          0x0040
6586 #define MDIO_OVER_1G_UP1_13G                                            0x0080
6587 #define MDIO_OVER_1G_UP1_15G                                            0x0100
6588 #define MDIO_OVER_1G_UP1_16G                                            0x0200
6589 #define MDIO_OVER_1G_UP2                                        0x1A
6590 #define MDIO_OVER_1G_UP2_IPREDRIVER_MASK                                0x0007
6591 #define MDIO_OVER_1G_UP2_IDRIVER_MASK                                   0x0038
6592 #define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK                               0x03C0
6593 #define MDIO_OVER_1G_UP3                                        0x1B
6594 #define MDIO_OVER_1G_UP3_HIGIG2                                         0x0001
6595 #define MDIO_OVER_1G_LP_UP1                                     0x1C
6596 #define MDIO_OVER_1G_LP_UP2                                     0x1D
6597 #define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK                         0x03ff
6598 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK                            0x0780
6599 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT                           7
6600 #define MDIO_OVER_1G_LP_UP3                                             0x1E
6601
6602 #define MDIO_REG_BANK_REMOTE_PHY                        0x8330
6603 #define MDIO_REMOTE_PHY_MISC_RX_STATUS                          0x10
6604 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG     0x0010
6605 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG   0x0600
6606
6607 #define MDIO_REG_BANK_BAM_NEXT_PAGE                     0x8350
6608 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL                   0x10
6609 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE                  0x0001
6610 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN                  0x0002
6611
6612 #define MDIO_REG_BANK_CL73_USERB0               0x8370
6613 #define MDIO_CL73_USERB0_CL73_UCTRL                             0x10
6614 #define MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL                       0x0002
6615 #define MDIO_CL73_USERB0_CL73_USTAT1                            0x11
6616 #define MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK                  0x0100
6617 #define MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37                0x0400
6618 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1                         0x12
6619 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN                          0x8000
6620 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN             0x4000
6621 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN              0x2000
6622 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3                         0x14
6623 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR                 0x0001
6624
6625 #define MDIO_REG_BANK_AER_BLOCK                 0xFFD0
6626 #define MDIO_AER_BLOCK_AER_REG                                  0x1E
6627
6628 #define MDIO_REG_BANK_COMBO_IEEE0               0xFFE0
6629 #define MDIO_COMBO_IEEE0_MII_CONTROL                            0x10
6630 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK                   0x2040
6631 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10                     0x0000
6632 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100                    0x2000
6633 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000                   0x0040
6634 #define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX                         0x0100
6635 #define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN                          0x0200
6636 #define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN                               0x1000
6637 #define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK                            0x4000
6638 #define MDIO_COMBO_IEEO_MII_CONTROL_RESET                               0x8000
6639 #define MDIO_COMBO_IEEE0_MII_STATUS                             0x11
6640 #define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS                           0x0004
6641 #define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE                    0x0020
6642 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV                           0x14
6643 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX                       0x0020
6644 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX                       0x0040
6645 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK                        0x0180
6646 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE                        0x0000
6647 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC                   0x0080
6648 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC                  0x0100
6649 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH                        0x0180
6650 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE                         0x8000
6651 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1         0x15
6652 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE       0x8000
6653 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK             0x4000
6654 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK      0x0180
6655 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE      0x0000
6656 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH      0x0180
6657 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP    0x0040
6658 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP    0x0020
6659 /*WhenthelinkpartnerisinSGMIImode(bit0=1),then
6660 bit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge.
6661 Theotherbitsarereservedandshouldbezero*/
6662 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE      0x0001
6663
6664
6665 #define MDIO_PMA_DEVAD                  0x1
6666 /*ieee*/
6667 #define MDIO_PMA_REG_CTRL               0x0
6668 #define MDIO_PMA_REG_STATUS             0x1
6669 #define MDIO_PMA_REG_10G_CTRL2          0x7
6670 #define MDIO_PMA_REG_TX_DISABLE         0x0009
6671 #define MDIO_PMA_REG_RX_SD              0xa
6672 /*bcm*/
6673 #define MDIO_PMA_REG_BCM_CTRL           0x0096
6674 #define MDIO_PMA_REG_FEC_CTRL           0x00ab
6675 #define MDIO_PMA_REG_PHY_IDENTIFIER     0xc800
6676 #define MDIO_PMA_REG_DIGITAL_CTRL       0xc808
6677 #define MDIO_PMA_REG_DIGITAL_STATUS     0xc809
6678 #define MDIO_PMA_REG_TX_POWER_DOWN      0xca02
6679 #define MDIO_PMA_REG_CMU_PLL_BYPASS     0xca09
6680 #define MDIO_PMA_REG_MISC_CTRL          0xca0a
6681 #define MDIO_PMA_REG_GEN_CTRL           0xca10
6682 #define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP     0x0188
6683 #define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET           0x018a
6684 #define MDIO_PMA_REG_M8051_MSGIN_REG    0xca12
6685 #define MDIO_PMA_REG_M8051_MSGOUT_REG   0xca13
6686 #define MDIO_PMA_REG_ROM_VER1           0xca19
6687 #define MDIO_PMA_REG_ROM_VER2           0xca1a
6688 #define MDIO_PMA_REG_EDC_FFE_MAIN       0xca1b
6689 #define MDIO_PMA_REG_PLL_BANDWIDTH      0xca1d
6690 #define MDIO_PMA_REG_PLL_CTRL           0xca1e
6691 #define MDIO_PMA_REG_MISC_CTRL0         0xca23
6692 #define MDIO_PMA_REG_LRM_MODE           0xca3f
6693 #define MDIO_PMA_REG_CDR_BANDWIDTH      0xca46
6694 #define MDIO_PMA_REG_MISC_CTRL1         0xca85
6695
6696 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL          0x8000
6697 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK      0x000c
6698 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE           0x0000
6699 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE       0x0004
6700 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS    0x0008
6701 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED         0x000c
6702 #define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT      0x8002
6703 #define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR      0x8003
6704 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF     0xc820
6705 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff
6706 #define MDIO_PMA_REG_8726_TX_CTRL1              0xca01
6707 #define MDIO_PMA_REG_8726_TX_CTRL2              0xca05
6708
6709 #define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR   0x8005
6710 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF     0x8007
6711 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff
6712 #define MDIO_PMA_REG_8727_TX_CTRL1              0xca02
6713 #define MDIO_PMA_REG_8727_TX_CTRL2              0xca05
6714 #define MDIO_PMA_REG_8727_PCS_OPT_CTRL          0xc808
6715 #define MDIO_PMA_REG_8727_GPIO_CTRL             0xc80e
6716 #define MDIO_PMA_REG_8727_PCS_GP                0xc842
6717 #define MDIO_PMA_REG_8727_OPT_CFG_REG           0xc8e4
6718
6719 #define MDIO_AN_REG_8727_MISC_CTRL              0x8309
6720
6721 #define MDIO_PMA_REG_8073_CHIP_REV                      0xc801
6722 #define MDIO_PMA_REG_8073_SPEED_LINK_STATUS             0xc820
6723 #define MDIO_PMA_REG_8073_XAUI_WA                       0xc841
6724 #define MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL              0xcd08
6725
6726 #define MDIO_PMA_REG_7101_RESET         0xc000
6727 #define MDIO_PMA_REG_7107_LED_CNTL      0xc007
6728 #define MDIO_PMA_REG_7107_LINK_LED_CNTL 0xc009
6729 #define MDIO_PMA_REG_7101_VER1          0xc026
6730 #define MDIO_PMA_REG_7101_VER2          0xc027
6731
6732 #define MDIO_PMA_REG_8481_PMD_SIGNAL                    0xa811
6733 #define MDIO_PMA_REG_8481_LED1_MASK                     0xa82c
6734 #define MDIO_PMA_REG_8481_LED2_MASK                     0xa82f
6735 #define MDIO_PMA_REG_8481_LED3_MASK                     0xa832
6736 #define MDIO_PMA_REG_8481_LED3_BLINK                    0xa834
6737 #define MDIO_PMA_REG_8481_LED5_MASK                     0xa838
6738 #define MDIO_PMA_REG_8481_SIGNAL_MASK                   0xa835
6739 #define MDIO_PMA_REG_8481_LINK_SIGNAL                   0xa83b
6740 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK  0x800
6741 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT 11
6742
6743
6744 #define MDIO_WIS_DEVAD                  0x2
6745 /*bcm*/
6746 #define MDIO_WIS_REG_LASI_CNTL          0x9002
6747 #define MDIO_WIS_REG_LASI_STATUS        0x9005
6748
6749 #define MDIO_PCS_DEVAD                  0x3
6750 #define MDIO_PCS_REG_STATUS             0x0020
6751 #define MDIO_PCS_REG_LASI_STATUS        0x9005
6752 #define MDIO_PCS_REG_7101_DSP_ACCESS    0xD000
6753 #define MDIO_PCS_REG_7101_SPI_MUX       0xD008
6754 #define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A
6755 #define MDIO_PCS_REG_7101_SPI_RESET_BIT (5)
6756 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A
6757 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6)
6758 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD   (0xC7)
6759 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2)
6760 #define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028
6761
6762
6763 #define MDIO_XS_DEVAD                   0x4
6764 #define MDIO_XS_PLL_SEQUENCER           0x8000
6765 #define MDIO_XS_SFX7101_XGXS_TEST1      0xc00a
6766
6767 #define MDIO_XS_8706_REG_BANK_RX0       0x80bc
6768 #define MDIO_XS_8706_REG_BANK_RX1       0x80cc
6769 #define MDIO_XS_8706_REG_BANK_RX2       0x80dc
6770 #define MDIO_XS_8706_REG_BANK_RX3       0x80ec
6771 #define MDIO_XS_8706_REG_BANK_RXA       0x80fc
6772
6773 #define MDIO_XS_REG_8073_RX_CTRL_PCIE   0x80FA
6774
6775 #define MDIO_AN_DEVAD                   0x7
6776 /*ieee*/
6777 #define MDIO_AN_REG_CTRL                0x0000
6778 #define MDIO_AN_REG_STATUS              0x0001
6779 #define MDIO_AN_REG_STATUS_AN_COMPLETE          0x0020
6780 #define MDIO_AN_REG_ADV_PAUSE           0x0010
6781 #define MDIO_AN_REG_ADV_PAUSE_PAUSE             0x0400
6782 #define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC        0x0800
6783 #define MDIO_AN_REG_ADV_PAUSE_BOTH              0x0C00
6784 #define MDIO_AN_REG_ADV_PAUSE_MASK              0x0C00
6785 #define MDIO_AN_REG_ADV                 0x0011
6786 #define MDIO_AN_REG_ADV2                0x0012
6787 #define MDIO_AN_REG_LP_AUTO_NEG         0x0013
6788 #define MDIO_AN_REG_MASTER_STATUS       0x0021
6789 /*bcm*/
6790 #define MDIO_AN_REG_LINK_STATUS         0x8304
6791 #define MDIO_AN_REG_CL37_CL73           0x8370
6792 #define MDIO_AN_REG_CL37_AN             0xffe0
6793 #define MDIO_AN_REG_CL37_FC_LD          0xffe4
6794 #define MDIO_AN_REG_CL37_FC_LP          0xffe5
6795
6796 #define MDIO_AN_REG_8073_2_5G           0x8329
6797 #define MDIO_AN_REG_8073_BAM            0x8350
6798
6799 #define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL      0x0020
6800 #define MDIO_AN_REG_8481_LEGACY_MII_CTRL        0xffe0
6801 #define MDIO_AN_REG_8481_LEGACY_MII_STATUS      0xffe1
6802 #define MDIO_AN_REG_8481_LEGACY_AN_ADV          0xffe4
6803 #define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION    0xffe6
6804 #define MDIO_AN_REG_8481_1000T_CTRL             0xffe9
6805 #define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW    0xfff5
6806 #define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS   0xfff7
6807 #define MDIO_AN_REG_8481_AUX_CTRL               0xfff8
6808 #define MDIO_AN_REG_8481_LEGACY_SHADOW          0xfffc
6809
6810 /* BCM84823 only */
6811 #define MDIO_CTL_DEVAD                  0x1e
6812 #define MDIO_CTL_REG_84823_MEDIA                0x401a
6813 #define MDIO_CTL_REG_84823_MEDIA_MAC_MASK               0x0018
6814         /* These pins configure the BCM84823 interface to MAC after reset. */
6815 #define MDIO_CTL_REG_84823_CTRL_MAC_XFI                 0x0008
6816 #define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M             0x0010
6817         /* These pins configure the BCM84823 interface to Line after reset. */
6818 #define MDIO_CTL_REG_84823_MEDIA_LINE_MASK              0x0060
6819 #define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L            0x0020
6820 #define MDIO_CTL_REG_84823_MEDIA_LINE_XFI               0x0040
6821         /* When this pin is active high during reset, 10GBASE-T core is power
6822          * down, When it is active low the 10GBASE-T is power up
6823          */
6824 #define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN       0x0080
6825 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK          0x0100
6826 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER        0x0000
6827 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER         0x0100
6828 #define MDIO_CTL_REG_84823_MEDIA_FIBER_1G                       0x1000
6829 #define MDIO_CTL_REG_84823_USER_CTRL_REG                0x4005
6830 #define MDIO_CTL_REG_84823_USER_CTRL_CMS                0x0080
6831
6832 #define MDIO_PMA_REG_84823_CTL_LED_CTL_1                0xa8e3
6833 #define MDIO_PMA_REG_84823_LED3_STRETCH_EN              0x0080
6834
6835 /* BCM84833 only */
6836 #define MDIO_84833_TOP_CFG_XGPHY_STRAP1                 0x401a
6837 #define MDIO_84833_SUPER_ISOLATE                0x8000
6838 /* These are mailbox register set used by 84833. */
6839 #define MDIO_84833_TOP_CFG_SCRATCH_REG0                 0x4005
6840 #define MDIO_84833_TOP_CFG_SCRATCH_REG1                 0x4006
6841 #define MDIO_84833_TOP_CFG_SCRATCH_REG2                 0x4007
6842 #define MDIO_84833_TOP_CFG_SCRATCH_REG3                 0x4008
6843 #define MDIO_84833_TOP_CFG_SCRATCH_REG4                 0x4009
6844 #define MDIO_84833_TOP_CFG_DATA3_REG                    0x4011
6845 #define MDIO_84833_TOP_CFG_DATA4_REG                    0x4012
6846
6847 /* Mailbox command set used by 84833. */
6848 #define PHY84833_DIAG_CMD_PAIR_SWAP_CHANGE              0x2
6849 /* Mailbox status set used by 84833. */
6850 #define PHY84833_CMD_RECEIVED                           0x0001
6851 #define PHY84833_CMD_IN_PROGRESS                        0x0002
6852 #define PHY84833_CMD_COMPLETE_PASS                      0x0004
6853 #define PHY84833_CMD_COMPLETE_ERROR                     0x0008
6854 #define PHY84833_CMD_OPEN_FOR_CMDS                      0x0010
6855 #define PHY84833_CMD_SYSTEM_BOOT                        0x0020
6856 #define PHY84833_CMD_NOT_OPEN_FOR_CMDS                  0x0040
6857 #define PHY84833_CMD_CLEAR_COMPLETE                     0x0080
6858 #define PHY84833_CMD_OPEN_OVERRIDE                      0xa5a5
6859
6860
6861 /* 84833 F/W Feature Commands */
6862 #define PHY84833_DIAG_CMD_GET_EEE_MODE                  0x27
6863 #define PHY84833_DIAG_CMD_SET_EEE_MODE                  0x28
6864
6865 /* Warpcore clause 45 addressing */
6866 #define MDIO_WC_DEVAD                                   0x3
6867 #define MDIO_WC_REG_IEEE0BLK_MIICNTL                    0x0
6868 #define MDIO_WC_REG_IEEE0BLK_AUTONEGNP                  0x7
6869 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0       0x10
6870 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1       0x11
6871 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2       0x12
6872 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY     0x4000
6873 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ         0x8000
6874 #define MDIO_WC_REG_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150  0x96
6875 #define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL                0x8000
6876 #define MDIO_WC_REG_XGXSBLK0_MISCCONTROL1               0x800e
6877 #define MDIO_WC_REG_XGXSBLK1_DESKEW                     0x8010
6878 #define MDIO_WC_REG_XGXSBLK1_LANECTRL0                  0x8015
6879 #define MDIO_WC_REG_XGXSBLK1_LANECTRL1                  0x8016
6880 #define MDIO_WC_REG_XGXSBLK1_LANECTRL2                  0x8017
6881 #define MDIO_WC_REG_TX0_ANA_CTRL0                       0x8061
6882 #define MDIO_WC_REG_TX1_ANA_CTRL0                       0x8071
6883 #define MDIO_WC_REG_TX2_ANA_CTRL0                       0x8081
6884 #define MDIO_WC_REG_TX3_ANA_CTRL0                       0x8091
6885 #define MDIO_WC_REG_TX0_TX_DRIVER                       0x8067
6886 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET            0x04
6887 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK                      0x00f0
6888 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET                0x08
6889 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_MASK                          0x0f00
6890 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET            0x0c
6891 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_MASK                      0x7000
6892 #define MDIO_WC_REG_TX1_TX_DRIVER                       0x8077
6893 #define MDIO_WC_REG_TX2_TX_DRIVER                       0x8087
6894 #define MDIO_WC_REG_TX3_TX_DRIVER                       0x8097
6895 #define MDIO_WC_REG_RX0_ANARXCONTROL1G                  0x80b9
6896 #define MDIO_WC_REG_RX2_ANARXCONTROL1G                  0x80d9
6897 #define MDIO_WC_REG_RX0_PCI_CTRL                        0x80ba
6898 #define MDIO_WC_REG_RX1_PCI_CTRL                        0x80ca
6899 #define MDIO_WC_REG_RX2_PCI_CTRL                        0x80da
6900 #define MDIO_WC_REG_RX3_PCI_CTRL                        0x80ea
6901 #define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G           0x8104
6902 #define MDIO_WC_REG_XGXS_STATUS3                        0x8129
6903 #define MDIO_WC_REG_PAR_DET_10G_STATUS                  0x8130
6904 #define MDIO_WC_REG_PAR_DET_10G_CTRL                    0x8131
6905 #define MDIO_WC_REG_XGXS_X2_CONTROL2                    0x8141
6906 #define MDIO_WC_REG_XGXS_RX_LN_SWAP1                    0x816B
6907 #define MDIO_WC_REG_XGXS_TX_LN_SWAP1                    0x8169
6908 #define MDIO_WC_REG_GP2_STATUS_GP_2_0                   0x81d0
6909 #define MDIO_WC_REG_GP2_STATUS_GP_2_1                   0x81d1
6910 #define MDIO_WC_REG_GP2_STATUS_GP_2_2                   0x81d2
6911 #define MDIO_WC_REG_GP2_STATUS_GP_2_3                   0x81d3
6912 #define MDIO_WC_REG_GP2_STATUS_GP_2_4                   0x81d4
6913 #define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP                0x81EE
6914 #define MDIO_WC_REG_UC_INFO_B1_VERSION                  0x81F0
6915 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE            0x81F2
6916 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET    0x0
6917 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT        0x0
6918 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR     0x1
6919 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC        0x2
6920 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI      0x3
6921 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G     0x4
6922 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET    0x4
6923 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET    0x8
6924 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET    0xc
6925 #define MDIO_WC_REG_UC_INFO_B1_CRC                      0x81FE
6926 #define MDIO_WC_REG_DSC_SMC                             0x8213
6927 #define MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0               0x821e
6928 #define MDIO_WC_REG_TX_FIR_TAP                          0x82e2
6929 #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET           0x00
6930 #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK                     0x000f
6931 #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET          0x04
6932 #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK            0x03f0
6933 #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET          0x0a
6934 #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK            0x7c00
6935 #define MDIO_WC_REG_TX_FIR_TAP_ENABLE           0x8000
6936 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL      0x82e3
6937 #define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL        0x82e6
6938 #define MDIO_WC_REG_CL72_USERB0_CL72_BR_DEF_CTRL        0x82e7
6939 #define MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL       0x82e8
6940 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL      0x82ec
6941 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1         0x8300
6942 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2         0x8301
6943 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3         0x8302
6944 #define MDIO_WC_REG_SERDESDIGITAL_STATUS1000X1          0x8304
6945 #define MDIO_WC_REG_SERDESDIGITAL_MISC1                 0x8308
6946 #define MDIO_WC_REG_SERDESDIGITAL_MISC2                 0x8309
6947 #define MDIO_WC_REG_DIGITAL3_UP1                        0x8329
6948 #define MDIO_WC_REG_DIGITAL4_MISC3                      0x833c
6949 #define MDIO_WC_REG_DIGITAL5_MISC6                      0x8345
6950 #define MDIO_WC_REG_DIGITAL5_MISC7                      0x8349
6951 #define MDIO_WC_REG_DIGITAL5_ACTUAL_SPEED               0x834e
6952 #define MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL           0x8350
6953 #define MDIO_WC_REG_CL49_USERB0_CTRL                    0x8368
6954 #define MDIO_WC_REG_TX66_CONTROL                        0x83b0
6955 #define MDIO_WC_REG_RX66_CONTROL                        0x83c0
6956 #define MDIO_WC_REG_RX66_SCW0                           0x83c2
6957 #define MDIO_WC_REG_RX66_SCW1                           0x83c3
6958 #define MDIO_WC_REG_RX66_SCW2                           0x83c4
6959 #define MDIO_WC_REG_RX66_SCW3                           0x83c5
6960 #define MDIO_WC_REG_RX66_SCW0_MASK                      0x83c6
6961 #define MDIO_WC_REG_RX66_SCW1_MASK                      0x83c7
6962 #define MDIO_WC_REG_RX66_SCW2_MASK                      0x83c8
6963 #define MDIO_WC_REG_RX66_SCW3_MASK                      0x83c9
6964 #define MDIO_WC_REG_FX100_CTRL1                         0x8400
6965 #define MDIO_WC_REG_FX100_CTRL3                         0x8402
6966
6967 #define MDIO_WC_REG_MICROBLK_CMD                        0xffc2
6968 #define MDIO_WC_REG_MICROBLK_DL_STATUS                  0xffc5
6969 #define MDIO_WC_REG_MICROBLK_CMD3                       0xffcc
6970
6971 #define MDIO_WC_REG_AERBLK_AER                          0xffde
6972 #define MDIO_WC_REG_COMBO_IEEE0_MIICTRL                 0xffe0
6973 #define MDIO_WC_REG_COMBO_IEEE0_MIIISTAT                0xffe1
6974
6975 #define MDIO_WC0_XGXS_BLK2_LANE_RESET                   0x810A
6976 #define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT       0
6977 #define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT       4
6978
6979 #define MDIO_WC0_XGXS_BLK6_XGXS_X2_CONTROL2             0x8141
6980
6981 #define DIGITAL5_ACTUAL_SPEED_TX_MASK                   0x003f
6982
6983 /* 54618se */
6984 #define MDIO_REG_GPHY_PHYID_LSB                         0x3
6985 #define MDIO_REG_GPHY_ID_54618SE                0x5cd5
6986 #define MDIO_REG_GPHY_CL45_ADDR_REG                     0xd
6987 #define MDIO_REG_GPHY_CL45_DATA_REG                     0xe
6988 #define MDIO_REG_GPHY_EEE_ADV                   0x3c
6989 #define MDIO_REG_GPHY_EEE_1G            (0x1 << 2)
6990 #define MDIO_REG_GPHY_EEE_100           (0x1 << 1)
6991 #define MDIO_REG_GPHY_EEE_RESOLVED              0x803e
6992 #define MDIO_REG_INTR_STATUS                            0x1a
6993 #define MDIO_REG_INTR_MASK                              0x1b
6994 #define MDIO_REG_INTR_MASK_LINK_STATUS                  (0x1 << 1)
6995 #define MDIO_REG_GPHY_SHADOW                            0x1c
6996 #define MDIO_REG_GPHY_SHADOW_LED_SEL1                   (0x0d << 10)
6997 #define MDIO_REG_GPHY_SHADOW_LED_SEL2                   (0x0e << 10)
6998 #define MDIO_REG_GPHY_SHADOW_WR_ENA                     (0x1 << 15)
6999 #define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED               (0x1e << 10)
7000 #define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD              (0x1 << 8)
7001
7002 #define IGU_FUNC_BASE                   0x0400
7003
7004 #define IGU_ADDR_MSIX                   0x0000
7005 #define IGU_ADDR_INT_ACK                0x0200
7006 #define IGU_ADDR_PROD_UPD               0x0201
7007 #define IGU_ADDR_ATTN_BITS_UPD  0x0202
7008 #define IGU_ADDR_ATTN_BITS_SET  0x0203
7009 #define IGU_ADDR_ATTN_BITS_CLR  0x0204
7010 #define IGU_ADDR_COALESCE_NOW   0x0205
7011 #define IGU_ADDR_SIMD_MASK              0x0206
7012 #define IGU_ADDR_SIMD_NOMASK    0x0207
7013 #define IGU_ADDR_MSI_CTL                0x0210
7014 #define IGU_ADDR_MSI_ADDR_LO    0x0211
7015 #define IGU_ADDR_MSI_ADDR_HI    0x0212
7016 #define IGU_ADDR_MSI_DATA               0x0213
7017
7018 #define IGU_USE_REGISTER_ustorm_type_0_sb_cleanup  0
7019 #define IGU_USE_REGISTER_ustorm_type_1_sb_cleanup  1
7020 #define IGU_USE_REGISTER_cstorm_type_0_sb_cleanup  2
7021 #define IGU_USE_REGISTER_cstorm_type_1_sb_cleanup  3
7022
7023 #define COMMAND_REG_INT_ACK         0x0
7024 #define COMMAND_REG_PROD_UPD        0x4
7025 #define COMMAND_REG_ATTN_BITS_UPD   0x8
7026 #define COMMAND_REG_ATTN_BITS_SET   0xc
7027 #define COMMAND_REG_ATTN_BITS_CLR   0x10
7028 #define COMMAND_REG_COALESCE_NOW    0x14
7029 #define COMMAND_REG_SIMD_MASK       0x18
7030 #define COMMAND_REG_SIMD_NOMASK     0x1c
7031
7032
7033 #define IGU_MEM_BASE                                            0x0000
7034
7035 #define IGU_MEM_MSIX_BASE                                       0x0000
7036 #define IGU_MEM_MSIX_UPPER                                      0x007f
7037 #define IGU_MEM_MSIX_RESERVED_UPPER                     0x01ff
7038
7039 #define IGU_MEM_PBA_MSIX_BASE                           0x0200
7040 #define IGU_MEM_PBA_MSIX_UPPER                          0x0200
7041
7042 #define IGU_CMD_BACKWARD_COMP_PROD_UPD          0x0201
7043 #define IGU_MEM_PBA_MSIX_RESERVED_UPPER         0x03ff
7044
7045 #define IGU_CMD_INT_ACK_BASE                            0x0400
7046 #define IGU_CMD_INT_ACK_UPPER\
7047         (IGU_CMD_INT_ACK_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1)
7048 #define IGU_CMD_INT_ACK_RESERVED_UPPER          0x04ff
7049
7050 #define IGU_CMD_E2_PROD_UPD_BASE                        0x0500
7051 #define IGU_CMD_E2_PROD_UPD_UPPER\
7052         (IGU_CMD_E2_PROD_UPD_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1)
7053 #define IGU_CMD_E2_PROD_UPD_RESERVED_UPPER      0x059f
7054
7055 #define IGU_CMD_ATTN_BIT_UPD_UPPER                      0x05a0
7056 #define IGU_CMD_ATTN_BIT_SET_UPPER                      0x05a1
7057 #define IGU_CMD_ATTN_BIT_CLR_UPPER                      0x05a2
7058
7059 #define IGU_REG_SISR_MDPC_WMASK_UPPER           0x05a3
7060 #define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER       0x05a4
7061 #define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER       0x05a5
7062 #define IGU_REG_SISR_MDPC_WOMASK_UPPER          0x05a6
7063
7064 #define IGU_REG_RESERVED_UPPER                          0x05ff
7065 /* Fields of IGU PF CONFIGRATION REGISTER */
7066 #define IGU_PF_CONF_FUNC_EN       (0x1<<0)  /* function enable        */
7067 #define IGU_PF_CONF_MSI_MSIX_EN   (0x1<<1)  /* MSI/MSIX enable        */
7068 #define IGU_PF_CONF_INT_LINE_EN   (0x1<<2)  /* INT enable             */
7069 #define IGU_PF_CONF_ATTN_BIT_EN   (0x1<<3)  /* attention enable       */
7070 #define IGU_PF_CONF_SINGLE_ISR_EN (0x1<<4)  /* single ISR mode enable */
7071 #define IGU_PF_CONF_SIMD_MODE     (0x1<<5)  /* simd all ones mode     */
7072
7073 /* Fields of IGU VF CONFIGRATION REGISTER */
7074 #define IGU_VF_CONF_FUNC_EN        (0x1<<0)  /* function enable        */
7075 #define IGU_VF_CONF_MSI_MSIX_EN    (0x1<<1)  /* MSI/MSIX enable        */
7076 #define IGU_VF_CONF_PARENT_MASK    (0x3<<2)  /* Parent PF              */
7077 #define IGU_VF_CONF_PARENT_SHIFT   2         /* Parent PF              */
7078 #define IGU_VF_CONF_SINGLE_ISR_EN  (0x1<<4)  /* single ISR mode enable */
7079
7080
7081 #define IGU_BC_DSB_NUM_SEGS    5
7082 #define IGU_BC_NDSB_NUM_SEGS   2
7083 #define IGU_NORM_DSB_NUM_SEGS  2
7084 #define IGU_NORM_NDSB_NUM_SEGS 1
7085 #define IGU_BC_BASE_DSB_PROD   128
7086 #define IGU_NORM_BASE_DSB_PROD 136
7087
7088         /* FID (if VF - [6] = 0; [5:0] = VF number; if PF - [6] = 1; \
7089         [5:2] = 0; [1:0] = PF number) */
7090 #define IGU_FID_ENCODE_IS_PF        (0x1<<6)
7091 #define IGU_FID_ENCODE_IS_PF_SHIFT  6
7092 #define IGU_FID_VF_NUM_MASK         (0x3f)
7093 #define IGU_FID_PF_NUM_MASK         (0x7)
7094
7095 #define IGU_REG_MAPPING_MEMORY_VALID            (1<<0)
7096 #define IGU_REG_MAPPING_MEMORY_VECTOR_MASK      (0x3F<<1)
7097 #define IGU_REG_MAPPING_MEMORY_VECTOR_SHIFT     1
7098 #define IGU_REG_MAPPING_MEMORY_FID_MASK (0x7F<<7)
7099 #define IGU_REG_MAPPING_MEMORY_FID_SHIFT        7
7100
7101
7102 #define CDU_REGION_NUMBER_XCM_AG 2
7103 #define CDU_REGION_NUMBER_UCM_AG 4
7104
7105
7106 /**
7107  * String-to-compress [31:8] = CID (all 24 bits)
7108  * String-to-compress [7:4] = Region
7109  * String-to-compress [3:0] = Type
7110  */
7111 #define CDU_VALID_DATA(_cid, _region, _type)\
7112         (((_cid) << 8) | (((_region)&0xf)<<4) | (((_type)&0xf)))
7113 #define CDU_CRC8(_cid, _region, _type)\
7114         (calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff))
7115 #define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type)\
7116         (0x80 | ((CDU_CRC8(_cid, _region, _type)) & 0x7f))
7117 #define CDU_RSRVD_VALUE_TYPE_B(_crc, _type)\
7118         (0x80 | ((_type)&0xf << 3) | ((CDU_CRC8(_cid, _region, _type)) & 0x7))
7119 #define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val) ((_val) & ~0x80)
7120
7121 /******************************************************************************
7122  * Description:
7123  *         Calculates crc 8 on a word value: polynomial 0-1-2-8
7124  *         Code was translated from Verilog.
7125  * Return:
7126  *****************************************************************************/
7127 static inline u8 calc_crc8(u32 data, u8 crc)
7128 {
7129         u8 D[32];
7130         u8 NewCRC[8];
7131         u8 C[8];
7132         u8 crc_res;
7133         u8 i;
7134
7135         /* split the data into 31 bits */
7136         for (i = 0; i < 32; i++) {
7137                 D[i] = (u8)(data & 1);
7138                 data = data >> 1;
7139         }
7140
7141         /* split the crc into 8 bits */
7142         for (i = 0; i < 8; i++) {
7143                 C[i] = crc & 1;
7144                 crc = crc >> 1;
7145         }
7146
7147         NewCRC[0] = D[31] ^ D[30] ^ D[28] ^ D[23] ^ D[21] ^ D[19] ^ D[18] ^
7148                     D[16] ^ D[14] ^ D[12] ^ D[8] ^ D[7] ^ D[6] ^ D[0] ^ C[4] ^
7149                     C[6] ^ C[7];
7150         NewCRC[1] = D[30] ^ D[29] ^ D[28] ^ D[24] ^ D[23] ^ D[22] ^ D[21] ^
7151                     D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^
7152                     D[12] ^ D[9] ^ D[6] ^ D[1] ^ D[0] ^ C[0] ^ C[4] ^ C[5] ^
7153                     C[6];
7154         NewCRC[2] = D[29] ^ D[28] ^ D[25] ^ D[24] ^ D[22] ^ D[17] ^ D[15] ^
7155                     D[13] ^ D[12] ^ D[10] ^ D[8] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^
7156                     C[0] ^ C[1] ^ C[4] ^ C[5];
7157         NewCRC[3] = D[30] ^ D[29] ^ D[26] ^ D[25] ^ D[23] ^ D[18] ^ D[16] ^
7158                     D[14] ^ D[13] ^ D[11] ^ D[9] ^ D[7] ^ D[3] ^ D[2] ^ D[1] ^
7159                     C[1] ^ C[2] ^ C[5] ^ C[6];
7160         NewCRC[4] = D[31] ^ D[30] ^ D[27] ^ D[26] ^ D[24] ^ D[19] ^ D[17] ^
7161                     D[15] ^ D[14] ^ D[12] ^ D[10] ^ D[8] ^ D[4] ^ D[3] ^ D[2] ^
7162                     C[0] ^ C[2] ^ C[3] ^ C[6] ^ C[7];
7163         NewCRC[5] = D[31] ^ D[28] ^ D[27] ^ D[25] ^ D[20] ^ D[18] ^ D[16] ^
7164                     D[15] ^ D[13] ^ D[11] ^ D[9] ^ D[5] ^ D[4] ^ D[3] ^ C[1] ^
7165                     C[3] ^ C[4] ^ C[7];
7166         NewCRC[6] = D[29] ^ D[28] ^ D[26] ^ D[21] ^ D[19] ^ D[17] ^ D[16] ^
7167                     D[14] ^ D[12] ^ D[10] ^ D[6] ^ D[5] ^ D[4] ^ C[2] ^ C[4] ^
7168                     C[5];
7169         NewCRC[7] = D[30] ^ D[29] ^ D[27] ^ D[22] ^ D[20] ^ D[18] ^ D[17] ^
7170                     D[15] ^ D[13] ^ D[11] ^ D[7] ^ D[6] ^ D[5] ^ C[3] ^ C[5] ^
7171                     C[6];
7172
7173         crc_res = 0;
7174         for (i = 0; i < 8; i++)
7175                 crc_res |= (NewCRC[i] << i);
7176
7177         return crc_res;
7178 }
7179
7180
7181 #endif /* BNX2X_REG_H */