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1 /* bnx2x_sp.h: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2011-2012 Broadcom Corporation
4 *
5 * Unless you and Broadcom execute a separate written software license
6 * agreement governing use of this software, this software is licensed to you
7 * under the terms of the GNU General Public License version 2, available
8 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
9 *
10 * Notwithstanding the above, under no circumstances may you combine this
11 * software in any way with any other Broadcom software provided under a
12 * license other than the GPL, without Broadcom's express prior written
13 * consent.
14 *
15 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
16 * Written by: Vladislav Zolotarov
17 *
18 */
19 #ifndef BNX2X_SP_VERBS
20 #define BNX2X_SP_VERBS
21
22 struct bnx2x;
23 struct eth_context;
24
25 /* Bits representing general command's configuration */
26 enum {
27 RAMROD_TX,
28 RAMROD_RX,
29 /* Wait until all pending commands complete */
30 RAMROD_COMP_WAIT,
31 /* Don't send a ramrod, only update a registry */
32 RAMROD_DRV_CLR_ONLY,
33 /* Configure HW according to the current object state */
34 RAMROD_RESTORE,
35 /* Execute the next command now */
36 RAMROD_EXEC,
37 /*
38 * Don't add a new command and continue execution of posponed
39 * commands. If not set a new command will be added to the
40 * pending commands list.
41 */
42 RAMROD_CONT,
43 };
44
45 typedef enum {
46 BNX2X_OBJ_TYPE_RX,
47 BNX2X_OBJ_TYPE_TX,
48 BNX2X_OBJ_TYPE_RX_TX,
49 } bnx2x_obj_type;
50
51 /* Filtering states */
52 enum {
53 BNX2X_FILTER_MAC_PENDING,
54 BNX2X_FILTER_VLAN_PENDING,
55 BNX2X_FILTER_VLAN_MAC_PENDING,
56 BNX2X_FILTER_RX_MODE_PENDING,
57 BNX2X_FILTER_RX_MODE_SCHED,
58 BNX2X_FILTER_ISCSI_ETH_START_SCHED,
59 BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
60 BNX2X_FILTER_FCOE_ETH_START_SCHED,
61 BNX2X_FILTER_FCOE_ETH_STOP_SCHED,
62 BNX2X_FILTER_MCAST_PENDING,
63 BNX2X_FILTER_MCAST_SCHED,
64 BNX2X_FILTER_RSS_CONF_PENDING,
65 };
66
67 struct bnx2x_raw_obj {
68 u8 func_id;
69
70 /* Queue params */
71 u8 cl_id;
72 u32 cid;
73
74 /* Ramrod data buffer params */
75 void *rdata;
76 dma_addr_t rdata_mapping;
77
78 /* Ramrod state params */
79 int state; /* "ramrod is pending" state bit */
80 unsigned long *pstate; /* pointer to state buffer */
81
82 bnx2x_obj_type obj_type;
83
84 int (*wait_comp)(struct bnx2x *bp,
85 struct bnx2x_raw_obj *o);
86
87 bool (*check_pending)(struct bnx2x_raw_obj *o);
88 void (*clear_pending)(struct bnx2x_raw_obj *o);
89 void (*set_pending)(struct bnx2x_raw_obj *o);
90 };
91
92 /************************* VLAN-MAC commands related parameters ***************/
93 struct bnx2x_mac_ramrod_data {
94 u8 mac[ETH_ALEN];
95 };
96
97 struct bnx2x_vlan_ramrod_data {
98 u16 vlan;
99 };
100
101 struct bnx2x_vlan_mac_ramrod_data {
102 u8 mac[ETH_ALEN];
103 u16 vlan;
104 };
105
106 union bnx2x_classification_ramrod_data {
107 struct bnx2x_mac_ramrod_data mac;
108 struct bnx2x_vlan_ramrod_data vlan;
109 struct bnx2x_vlan_mac_ramrod_data vlan_mac;
110 };
111
112 /* VLAN_MAC commands */
113 enum bnx2x_vlan_mac_cmd {
114 BNX2X_VLAN_MAC_ADD,
115 BNX2X_VLAN_MAC_DEL,
116 BNX2X_VLAN_MAC_MOVE,
117 };
118
119 struct bnx2x_vlan_mac_data {
120 /* Requested command: BNX2X_VLAN_MAC_XX */
121 enum bnx2x_vlan_mac_cmd cmd;
122 /*
123 * used to contain the data related vlan_mac_flags bits from
124 * ramrod parameters.
125 */
126 unsigned long vlan_mac_flags;
127
128 /* Needed for MOVE command */
129 struct bnx2x_vlan_mac_obj *target_obj;
130
131 union bnx2x_classification_ramrod_data u;
132 };
133
134 /*************************** Exe Queue obj ************************************/
135 union bnx2x_exe_queue_cmd_data {
136 struct bnx2x_vlan_mac_data vlan_mac;
137
138 struct {
139 /* TODO */
140 } mcast;
141 };
142
143 struct bnx2x_exeq_elem {
144 struct list_head link;
145
146 /* Length of this element in the exe_chunk. */
147 int cmd_len;
148
149 union bnx2x_exe_queue_cmd_data cmd_data;
150 };
151
152 union bnx2x_qable_obj;
153
154 union bnx2x_exeq_comp_elem {
155 union event_ring_elem *elem;
156 };
157
158 struct bnx2x_exe_queue_obj;
159
160 typedef int (*exe_q_validate)(struct bnx2x *bp,
161 union bnx2x_qable_obj *o,
162 struct bnx2x_exeq_elem *elem);
163
164 typedef int (*exe_q_remove)(struct bnx2x *bp,
165 union bnx2x_qable_obj *o,
166 struct bnx2x_exeq_elem *elem);
167
168 /**
169 * @return positive is entry was optimized, 0 - if not, negative
170 * in case of an error.
171 */
172 typedef int (*exe_q_optimize)(struct bnx2x *bp,
173 union bnx2x_qable_obj *o,
174 struct bnx2x_exeq_elem *elem);
175 typedef int (*exe_q_execute)(struct bnx2x *bp,
176 union bnx2x_qable_obj *o,
177 struct list_head *exe_chunk,
178 unsigned long *ramrod_flags);
179 typedef struct bnx2x_exeq_elem *
180 (*exe_q_get)(struct bnx2x_exe_queue_obj *o,
181 struct bnx2x_exeq_elem *elem);
182
183 struct bnx2x_exe_queue_obj {
184 /*
185 * Commands pending for an execution.
186 */
187 struct list_head exe_queue;
188
189 /*
190 * Commands pending for an completion.
191 */
192 struct list_head pending_comp;
193
194 spinlock_t lock;
195
196 /* Maximum length of commands' list for one execution */
197 int exe_chunk_len;
198
199 union bnx2x_qable_obj *owner;
200
201 /****** Virtual functions ******/
202 /**
203 * Called before commands execution for commands that are really
204 * going to be executed (after 'optimize').
205 *
206 * Must run under exe_queue->lock
207 */
208 exe_q_validate validate;
209
210 /**
211 * Called before removing pending commands, cleaning allocated
212 * resources (e.g., credits from validate)
213 */
214 exe_q_remove remove;
215
216 /**
217 * This will try to cancel the current pending commands list
218 * considering the new command.
219 *
220 * Returns the number of optimized commands or a negative error code
221 *
222 * Must run under exe_queue->lock
223 */
224 exe_q_optimize optimize;
225
226 /**
227 * Run the next commands chunk (owner specific).
228 */
229 exe_q_execute execute;
230
231 /**
232 * Return the exe_queue element containing the specific command
233 * if any. Otherwise return NULL.
234 */
235 exe_q_get get;
236 };
237 /***************** Classification verbs: Set/Del MAC/VLAN/VLAN-MAC ************/
238 /*
239 * Element in the VLAN_MAC registry list having all currenty configured
240 * rules.
241 */
242 struct bnx2x_vlan_mac_registry_elem {
243 struct list_head link;
244
245 /*
246 * Used to store the cam offset used for the mac/vlan/vlan-mac.
247 * Relevant for 57710 and 57711 only. VLANs and MACs share the
248 * same CAM for these chips.
249 */
250 int cam_offset;
251
252 /* Needed for DEL and RESTORE flows */
253 unsigned long vlan_mac_flags;
254
255 union bnx2x_classification_ramrod_data u;
256 };
257
258 /* Bits representing VLAN_MAC commands specific flags */
259 enum {
260 BNX2X_UC_LIST_MAC,
261 BNX2X_ETH_MAC,
262 BNX2X_ISCSI_ETH_MAC,
263 BNX2X_NETQ_ETH_MAC,
264 BNX2X_DONT_CONSUME_CAM_CREDIT,
265 BNX2X_DONT_CONSUME_CAM_CREDIT_DEST,
266 };
267
268 struct bnx2x_vlan_mac_ramrod_params {
269 /* Object to run the command from */
270 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
271
272 /* General command flags: COMP_WAIT, etc. */
273 unsigned long ramrod_flags;
274
275 /* Command specific configuration request */
276 struct bnx2x_vlan_mac_data user_req;
277 };
278
279 struct bnx2x_vlan_mac_obj {
280 struct bnx2x_raw_obj raw;
281
282 /* Bookkeeping list: will prevent the addition of already existing
283 * entries.
284 */
285 struct list_head head;
286
287 /* TODO: Add it's initialization in the init functions */
288 struct bnx2x_exe_queue_obj exe_queue;
289
290 /* MACs credit pool */
291 struct bnx2x_credit_pool_obj *macs_pool;
292
293 /* VLANs credit pool */
294 struct bnx2x_credit_pool_obj *vlans_pool;
295
296 /* RAMROD command to be used */
297 int ramrod_cmd;
298
299 /* copy first n elements onto preallocated buffer
300 *
301 * @param n number of elements to get
302 * @param buf buffer preallocated by caller into which elements
303 * will be copied. Note elements are 4-byte aligned
304 * so buffer size must be able to accomodate the
305 * aligned elements.
306 *
307 * @return number of copied bytes
308 */
309 int (*get_n_elements)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o,
310 int n, u8 *buf);
311
312 /**
313 * Checks if ADD-ramrod with the given params may be performed.
314 *
315 * @return zero if the element may be added
316 */
317
318 int (*check_add)(struct bnx2x_vlan_mac_obj *o,
319 union bnx2x_classification_ramrod_data *data);
320
321 /**
322 * Checks if DEL-ramrod with the given params may be performed.
323 *
324 * @return true if the element may be deleted
325 */
326 struct bnx2x_vlan_mac_registry_elem *
327 (*check_del)(struct bnx2x_vlan_mac_obj *o,
328 union bnx2x_classification_ramrod_data *data);
329
330 /**
331 * Checks if DEL-ramrod with the given params may be performed.
332 *
333 * @return true if the element may be deleted
334 */
335 bool (*check_move)(struct bnx2x_vlan_mac_obj *src_o,
336 struct bnx2x_vlan_mac_obj *dst_o,
337 union bnx2x_classification_ramrod_data *data);
338
339 /**
340 * Update the relevant credit object(s) (consume/return
341 * correspondingly).
342 */
343 bool (*get_credit)(struct bnx2x_vlan_mac_obj *o);
344 bool (*put_credit)(struct bnx2x_vlan_mac_obj *o);
345 bool (*get_cam_offset)(struct bnx2x_vlan_mac_obj *o, int *offset);
346 bool (*put_cam_offset)(struct bnx2x_vlan_mac_obj *o, int offset);
347
348 /**
349 * Configures one rule in the ramrod data buffer.
350 */
351 void (*set_one_rule)(struct bnx2x *bp,
352 struct bnx2x_vlan_mac_obj *o,
353 struct bnx2x_exeq_elem *elem, int rule_idx,
354 int cam_offset);
355
356 /**
357 * Delete all configured elements having the given
358 * vlan_mac_flags specification. Assumes no pending for
359 * execution commands. Will schedule all all currently
360 * configured MACs/VLANs/VLAN-MACs matching the vlan_mac_flags
361 * specification for deletion and will use the given
362 * ramrod_flags for the last DEL operation.
363 *
364 * @param bp
365 * @param o
366 * @param ramrod_flags RAMROD_XX flags
367 *
368 * @return 0 if the last operation has completed successfully
369 * and there are no more elements left, positive value
370 * if there are pending for completion commands,
371 * negative value in case of failure.
372 */
373 int (*delete_all)(struct bnx2x *bp,
374 struct bnx2x_vlan_mac_obj *o,
375 unsigned long *vlan_mac_flags,
376 unsigned long *ramrod_flags);
377
378 /**
379 * Reconfigures the next MAC/VLAN/VLAN-MAC element from the previously
380 * configured elements list.
381 *
382 * @param bp
383 * @param p Command parameters (RAMROD_COMP_WAIT bit in
384 * ramrod_flags is only taken into an account)
385 * @param ppos a pointer to the cooky that should be given back in the
386 * next call to make function handle the next element. If
387 * *ppos is set to NULL it will restart the iterator.
388 * If returned *ppos == NULL this means that the last
389 * element has been handled.
390 *
391 * @return int
392 */
393 int (*restore)(struct bnx2x *bp,
394 struct bnx2x_vlan_mac_ramrod_params *p,
395 struct bnx2x_vlan_mac_registry_elem **ppos);
396
397 /**
398 * Should be called on a completion arival.
399 *
400 * @param bp
401 * @param o
402 * @param cqe Completion element we are handling
403 * @param ramrod_flags if RAMROD_CONT is set the next bulk of
404 * pending commands will be executed.
405 * RAMROD_DRV_CLR_ONLY and RAMROD_RESTORE
406 * may also be set if needed.
407 *
408 * @return 0 if there are neither pending nor waiting for
409 * completion commands. Positive value if there are
410 * pending for execution or for completion commands.
411 * Negative value in case of an error (including an
412 * error in the cqe).
413 */
414 int (*complete)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o,
415 union event_ring_elem *cqe,
416 unsigned long *ramrod_flags);
417
418 /**
419 * Wait for completion of all commands. Don't schedule new ones,
420 * just wait. It assumes that the completion code will schedule
421 * for new commands.
422 */
423 int (*wait)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o);
424 };
425
426 /** RX_MODE verbs:DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */
427
428 /* RX_MODE ramrod spesial flags: set in rx_mode_flags field in
429 * a bnx2x_rx_mode_ramrod_params.
430 */
431 enum {
432 BNX2X_RX_MODE_FCOE_ETH,
433 BNX2X_RX_MODE_ISCSI_ETH,
434 };
435
436 enum {
437 BNX2X_ACCEPT_UNICAST,
438 BNX2X_ACCEPT_MULTICAST,
439 BNX2X_ACCEPT_ALL_UNICAST,
440 BNX2X_ACCEPT_ALL_MULTICAST,
441 BNX2X_ACCEPT_BROADCAST,
442 BNX2X_ACCEPT_UNMATCHED,
443 BNX2X_ACCEPT_ANY_VLAN
444 };
445
446 struct bnx2x_rx_mode_ramrod_params {
447 struct bnx2x_rx_mode_obj *rx_mode_obj;
448 unsigned long *pstate;
449 int state;
450 u8 cl_id;
451 u32 cid;
452 u8 func_id;
453 unsigned long ramrod_flags;
454 unsigned long rx_mode_flags;
455
456 /*
457 * rdata is either a pointer to eth_filter_rules_ramrod_data(e2) or to
458 * a tstorm_eth_mac_filter_config (e1x).
459 */
460 void *rdata;
461 dma_addr_t rdata_mapping;
462
463 /* Rx mode settings */
464 unsigned long rx_accept_flags;
465
466 /* internal switching settings */
467 unsigned long tx_accept_flags;
468 };
469
470 struct bnx2x_rx_mode_obj {
471 int (*config_rx_mode)(struct bnx2x *bp,
472 struct bnx2x_rx_mode_ramrod_params *p);
473
474 int (*wait_comp)(struct bnx2x *bp,
475 struct bnx2x_rx_mode_ramrod_params *p);
476 };
477
478 /********************** Set multicast group ***********************************/
479
480 struct bnx2x_mcast_list_elem {
481 struct list_head link;
482 u8 *mac;
483 };
484
485 union bnx2x_mcast_config_data {
486 u8 *mac;
487 u8 bin; /* used in a RESTORE flow */
488 };
489
490 struct bnx2x_mcast_ramrod_params {
491 struct bnx2x_mcast_obj *mcast_obj;
492
493 /* Relevant options are RAMROD_COMP_WAIT and RAMROD_DRV_CLR_ONLY */
494 unsigned long ramrod_flags;
495
496 struct list_head mcast_list; /* list of struct bnx2x_mcast_list_elem */
497 /** TODO:
498 * - rename it to macs_num.
499 * - Add a new command type for handling pending commands
500 * (remove "zero semantics").
501 *
502 * Length of mcast_list. If zero and ADD_CONT command - post
503 * pending commands.
504 */
505 int mcast_list_len;
506 };
507
508 enum {
509 BNX2X_MCAST_CMD_ADD,
510 BNX2X_MCAST_CMD_CONT,
511 BNX2X_MCAST_CMD_DEL,
512 BNX2X_MCAST_CMD_RESTORE,
513 };
514
515 struct bnx2x_mcast_obj {
516 struct bnx2x_raw_obj raw;
517
518 union {
519 struct {
520 #define BNX2X_MCAST_BINS_NUM 256
521 #define BNX2X_MCAST_VEC_SZ (BNX2X_MCAST_BINS_NUM / 64)
522 u64 vec[BNX2X_MCAST_VEC_SZ];
523
524 /** Number of BINs to clear. Should be updated
525 * immediately when a command arrives in order to
526 * properly create DEL commands.
527 */
528 int num_bins_set;
529 } aprox_match;
530
531 struct {
532 struct list_head macs;
533 int num_macs_set;
534 } exact_match;
535 } registry;
536
537 /* Pending commands */
538 struct list_head pending_cmds_head;
539
540 /* A state that is set in raw.pstate, when there are pending commands */
541 int sched_state;
542
543 /* Maximal number of mcast MACs configured in one command */
544 int max_cmd_len;
545
546 /* Total number of currently pending MACs to configure: both
547 * in the pending commands list and in the current command.
548 */
549 int total_pending_num;
550
551 u8 engine_id;
552
553 /**
554 * @param cmd command to execute (BNX2X_MCAST_CMD_X, see above)
555 */
556 int (*config_mcast)(struct bnx2x *bp,
557 struct bnx2x_mcast_ramrod_params *p, int cmd);
558
559 /**
560 * Fills the ramrod data during the RESTORE flow.
561 *
562 * @param bp
563 * @param o
564 * @param start_idx Registry index to start from
565 * @param rdata_idx Index in the ramrod data to start from
566 *
567 * @return -1 if we handled the whole registry or index of the last
568 * handled registry element.
569 */
570 int (*hdl_restore)(struct bnx2x *bp, struct bnx2x_mcast_obj *o,
571 int start_bin, int *rdata_idx);
572
573 int (*enqueue_cmd)(struct bnx2x *bp, struct bnx2x_mcast_obj *o,
574 struct bnx2x_mcast_ramrod_params *p, int cmd);
575
576 void (*set_one_rule)(struct bnx2x *bp,
577 struct bnx2x_mcast_obj *o, int idx,
578 union bnx2x_mcast_config_data *cfg_data, int cmd);
579
580 /** Checks if there are more mcast MACs to be set or a previous
581 * command is still pending.
582 */
583 bool (*check_pending)(struct bnx2x_mcast_obj *o);
584
585 /**
586 * Set/Clear/Check SCHEDULED state of the object
587 */
588 void (*set_sched)(struct bnx2x_mcast_obj *o);
589 void (*clear_sched)(struct bnx2x_mcast_obj *o);
590 bool (*check_sched)(struct bnx2x_mcast_obj *o);
591
592 /* Wait until all pending commands complete */
593 int (*wait_comp)(struct bnx2x *bp, struct bnx2x_mcast_obj *o);
594
595 /**
596 * Handle the internal object counters needed for proper
597 * commands handling. Checks that the provided parameters are
598 * feasible.
599 */
600 int (*validate)(struct bnx2x *bp,
601 struct bnx2x_mcast_ramrod_params *p, int cmd);
602
603 /**
604 * Restore the values of internal counters in case of a failure.
605 */
606 void (*revert)(struct bnx2x *bp,
607 struct bnx2x_mcast_ramrod_params *p,
608 int old_num_bins);
609
610 int (*get_registry_size)(struct bnx2x_mcast_obj *o);
611 void (*set_registry_size)(struct bnx2x_mcast_obj *o, int n);
612 };
613
614 /*************************** Credit handling **********************************/
615 struct bnx2x_credit_pool_obj {
616
617 /* Current amount of credit in the pool */
618 atomic_t credit;
619
620 /* Maximum allowed credit. put() will check against it. */
621 int pool_sz;
622
623 /*
624 * Allocate a pool table statically.
625 *
626 * Currently the mamimum allowed size is MAX_MAC_CREDIT_E2(272)
627 *
628 * The set bit in the table will mean that the entry is available.
629 */
630 #define BNX2X_POOL_VEC_SIZE (MAX_MAC_CREDIT_E2 / 64)
631 u64 pool_mirror[BNX2X_POOL_VEC_SIZE];
632
633 /* Base pool offset (initialized differently */
634 int base_pool_offset;
635
636 /**
637 * Get the next free pool entry.
638 *
639 * @return true if there was a free entry in the pool
640 */
641 bool (*get_entry)(struct bnx2x_credit_pool_obj *o, int *entry);
642
643 /**
644 * Return the entry back to the pool.
645 *
646 * @return true if entry is legal and has been successfully
647 * returned to the pool.
648 */
649 bool (*put_entry)(struct bnx2x_credit_pool_obj *o, int entry);
650
651 /**
652 * Get the requested amount of credit from the pool.
653 *
654 * @param cnt Amount of requested credit
655 * @return true if the operation is successful
656 */
657 bool (*get)(struct bnx2x_credit_pool_obj *o, int cnt);
658
659 /**
660 * Returns the credit to the pool.
661 *
662 * @param cnt Amount of credit to return
663 * @return true if the operation is successful
664 */
665 bool (*put)(struct bnx2x_credit_pool_obj *o, int cnt);
666
667 /**
668 * Reads the current amount of credit.
669 */
670 int (*check)(struct bnx2x_credit_pool_obj *o);
671 };
672
673 /*************************** RSS configuration ********************************/
674 enum {
675 /* RSS_MODE bits are mutually exclusive */
676 BNX2X_RSS_MODE_DISABLED,
677 BNX2X_RSS_MODE_REGULAR,
678 BNX2X_RSS_MODE_VLAN_PRI,
679 BNX2X_RSS_MODE_E1HOV_PRI,
680 BNX2X_RSS_MODE_IP_DSCP,
681
682 BNX2X_RSS_SET_SRCH, /* Setup searcher, E1x specific flag */
683
684 BNX2X_RSS_IPV4,
685 BNX2X_RSS_IPV4_TCP,
686 BNX2X_RSS_IPV6,
687 BNX2X_RSS_IPV6_TCP,
688 };
689
690 struct bnx2x_config_rss_params {
691 struct bnx2x_rss_config_obj *rss_obj;
692
693 /* may have RAMROD_COMP_WAIT set only */
694 unsigned long ramrod_flags;
695
696 /* BNX2X_RSS_X bits */
697 unsigned long rss_flags;
698
699 /* Number hash bits to take into an account */
700 u8 rss_result_mask;
701
702 /* Indirection table */
703 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE];
704
705 /* RSS hash values */
706 u32 rss_key[10];
707
708 /* valid only iff BNX2X_RSS_UPDATE_TOE is set */
709 u16 toe_rss_bitmap;
710 };
711
712 struct bnx2x_rss_config_obj {
713 struct bnx2x_raw_obj raw;
714
715 /* RSS engine to use */
716 u8 engine_id;
717
718 /* Last configured indirection table */
719 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE];
720
721 int (*config_rss)(struct bnx2x *bp,
722 struct bnx2x_config_rss_params *p);
723 };
724
725 /*********************** Queue state update ***********************************/
726
727 /* UPDATE command options */
728 enum {
729 BNX2X_Q_UPDATE_IN_VLAN_REM,
730 BNX2X_Q_UPDATE_IN_VLAN_REM_CHNG,
731 BNX2X_Q_UPDATE_OUT_VLAN_REM,
732 BNX2X_Q_UPDATE_OUT_VLAN_REM_CHNG,
733 BNX2X_Q_UPDATE_ANTI_SPOOF,
734 BNX2X_Q_UPDATE_ANTI_SPOOF_CHNG,
735 BNX2X_Q_UPDATE_ACTIVATE,
736 BNX2X_Q_UPDATE_ACTIVATE_CHNG,
737 BNX2X_Q_UPDATE_DEF_VLAN_EN,
738 BNX2X_Q_UPDATE_DEF_VLAN_EN_CHNG,
739 BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
740 BNX2X_Q_UPDATE_SILENT_VLAN_REM
741 };
742
743 /* Allowed Queue states */
744 enum bnx2x_q_state {
745 BNX2X_Q_STATE_RESET,
746 BNX2X_Q_STATE_INITIALIZED,
747 BNX2X_Q_STATE_ACTIVE,
748 BNX2X_Q_STATE_MULTI_COS,
749 BNX2X_Q_STATE_MCOS_TERMINATED,
750 BNX2X_Q_STATE_INACTIVE,
751 BNX2X_Q_STATE_STOPPED,
752 BNX2X_Q_STATE_TERMINATED,
753 BNX2X_Q_STATE_FLRED,
754 BNX2X_Q_STATE_MAX,
755 };
756
757 /* Allowed commands */
758 enum bnx2x_queue_cmd {
759 BNX2X_Q_CMD_INIT,
760 BNX2X_Q_CMD_SETUP,
761 BNX2X_Q_CMD_SETUP_TX_ONLY,
762 BNX2X_Q_CMD_DEACTIVATE,
763 BNX2X_Q_CMD_ACTIVATE,
764 BNX2X_Q_CMD_UPDATE,
765 BNX2X_Q_CMD_UPDATE_TPA,
766 BNX2X_Q_CMD_HALT,
767 BNX2X_Q_CMD_CFC_DEL,
768 BNX2X_Q_CMD_TERMINATE,
769 BNX2X_Q_CMD_EMPTY,
770 BNX2X_Q_CMD_MAX,
771 };
772
773 /* queue SETUP + INIT flags */
774 enum {
775 BNX2X_Q_FLG_TPA,
776 BNX2X_Q_FLG_TPA_IPV6,
777 BNX2X_Q_FLG_TPA_GRO,
778 BNX2X_Q_FLG_STATS,
779 BNX2X_Q_FLG_ZERO_STATS,
780 BNX2X_Q_FLG_ACTIVE,
781 BNX2X_Q_FLG_OV,
782 BNX2X_Q_FLG_VLAN,
783 BNX2X_Q_FLG_COS,
784 BNX2X_Q_FLG_HC,
785 BNX2X_Q_FLG_HC_EN,
786 BNX2X_Q_FLG_DHC,
787 BNX2X_Q_FLG_FCOE,
788 BNX2X_Q_FLG_LEADING_RSS,
789 BNX2X_Q_FLG_MCAST,
790 BNX2X_Q_FLG_DEF_VLAN,
791 BNX2X_Q_FLG_TX_SWITCH,
792 BNX2X_Q_FLG_TX_SEC,
793 BNX2X_Q_FLG_ANTI_SPOOF,
794 BNX2X_Q_FLG_SILENT_VLAN_REM
795 };
796
797 /* Queue type options: queue type may be a compination of below. */
798 enum bnx2x_q_type {
799 /** TODO: Consider moving both these flags into the init()
800 * ramrod params.
801 */
802 BNX2X_Q_TYPE_HAS_RX,
803 BNX2X_Q_TYPE_HAS_TX,
804 };
805
806 #define BNX2X_PRIMARY_CID_INDEX 0
807 #define BNX2X_MULTI_TX_COS_E1X 3 /* QM only */
808 #define BNX2X_MULTI_TX_COS_E2_E3A0 2
809 #define BNX2X_MULTI_TX_COS_E3B0 3
810 #define BNX2X_MULTI_TX_COS 3 /* Maximum possible */
811
812
813 struct bnx2x_queue_init_params {
814 struct {
815 unsigned long flags;
816 u16 hc_rate;
817 u8 fw_sb_id;
818 u8 sb_cq_index;
819 } tx;
820
821 struct {
822 unsigned long flags;
823 u16 hc_rate;
824 u8 fw_sb_id;
825 u8 sb_cq_index;
826 } rx;
827
828 /* CID context in the host memory */
829 struct eth_context *cxts[BNX2X_MULTI_TX_COS];
830
831 /* maximum number of cos supported by hardware */
832 u8 max_cos;
833 };
834
835 struct bnx2x_queue_terminate_params {
836 /* index within the tx_only cids of this queue object */
837 u8 cid_index;
838 };
839
840 struct bnx2x_queue_cfc_del_params {
841 /* index within the tx_only cids of this queue object */
842 u8 cid_index;
843 };
844
845 struct bnx2x_queue_update_params {
846 unsigned long update_flags; /* BNX2X_Q_UPDATE_XX bits */
847 u16 def_vlan;
848 u16 silent_removal_value;
849 u16 silent_removal_mask;
850 /* index within the tx_only cids of this queue object */
851 u8 cid_index;
852 };
853
854 struct rxq_pause_params {
855 u16 bd_th_lo;
856 u16 bd_th_hi;
857 u16 rcq_th_lo;
858 u16 rcq_th_hi;
859 u16 sge_th_lo; /* valid iff BNX2X_Q_FLG_TPA */
860 u16 sge_th_hi; /* valid iff BNX2X_Q_FLG_TPA */
861 u16 pri_map;
862 };
863
864 /* general */
865 struct bnx2x_general_setup_params {
866 /* valid iff BNX2X_Q_FLG_STATS */
867 u8 stat_id;
868
869 u8 spcl_id;
870 u16 mtu;
871 u8 cos;
872 };
873
874 struct bnx2x_rxq_setup_params {
875 /* dma */
876 dma_addr_t dscr_map;
877 dma_addr_t sge_map;
878 dma_addr_t rcq_map;
879 dma_addr_t rcq_np_map;
880
881 u16 drop_flags;
882 u16 buf_sz;
883 u8 fw_sb_id;
884 u8 cl_qzone_id;
885
886 /* valid iff BNX2X_Q_FLG_TPA */
887 u16 tpa_agg_sz;
888 u16 sge_buf_sz;
889 u8 max_sges_pkt;
890 u8 max_tpa_queues;
891 u8 rss_engine_id;
892
893 u8 cache_line_log;
894
895 u8 sb_cq_index;
896
897 /* valid iff BXN2X_Q_FLG_SILENT_VLAN_REM */
898 u16 silent_removal_value;
899 u16 silent_removal_mask;
900 };
901
902 struct bnx2x_txq_setup_params {
903 /* dma */
904 dma_addr_t dscr_map;
905
906 u8 fw_sb_id;
907 u8 sb_cq_index;
908 u8 cos; /* valid iff BNX2X_Q_FLG_COS */
909 u16 traffic_type;
910 /* equals to the leading rss client id, used for TX classification*/
911 u8 tss_leading_cl_id;
912
913 /* valid iff BNX2X_Q_FLG_DEF_VLAN */
914 u16 default_vlan;
915 };
916
917 struct bnx2x_queue_setup_params {
918 struct bnx2x_general_setup_params gen_params;
919 struct bnx2x_txq_setup_params txq_params;
920 struct bnx2x_rxq_setup_params rxq_params;
921 struct rxq_pause_params pause_params;
922 unsigned long flags;
923 };
924
925 struct bnx2x_queue_setup_tx_only_params {
926 struct bnx2x_general_setup_params gen_params;
927 struct bnx2x_txq_setup_params txq_params;
928 unsigned long flags;
929 /* index within the tx_only cids of this queue object */
930 u8 cid_index;
931 };
932
933 struct bnx2x_queue_state_params {
934 struct bnx2x_queue_sp_obj *q_obj;
935
936 /* Current command */
937 enum bnx2x_queue_cmd cmd;
938
939 /* may have RAMROD_COMP_WAIT set only */
940 unsigned long ramrod_flags;
941
942 /* Params according to the current command */
943 union {
944 struct bnx2x_queue_update_params update;
945 struct bnx2x_queue_setup_params setup;
946 struct bnx2x_queue_init_params init;
947 struct bnx2x_queue_setup_tx_only_params tx_only;
948 struct bnx2x_queue_terminate_params terminate;
949 struct bnx2x_queue_cfc_del_params cfc_del;
950 } params;
951 };
952
953 struct bnx2x_queue_sp_obj {
954 u32 cids[BNX2X_MULTI_TX_COS];
955 u8 cl_id;
956 u8 func_id;
957
958 /*
959 * number of traffic classes supported by queue.
960 * The primary connection of the queue suppotrs the first traffic
961 * class. Any further traffic class is suppoted by a tx-only
962 * connection.
963 *
964 * Therefore max_cos is also a number of valid entries in the cids
965 * array.
966 */
967 u8 max_cos;
968 u8 num_tx_only, next_tx_only;
969
970 enum bnx2x_q_state state, next_state;
971
972 /* bits from enum bnx2x_q_type */
973 unsigned long type;
974
975 /* BNX2X_Q_CMD_XX bits. This object implements "one
976 * pending" paradigm but for debug and tracing purposes it's
977 * more convinient to have different bits for different
978 * commands.
979 */
980 unsigned long pending;
981
982 /* Buffer to use as a ramrod data and its mapping */
983 void *rdata;
984 dma_addr_t rdata_mapping;
985
986 /**
987 * Performs one state change according to the given parameters.
988 *
989 * @return 0 in case of success and negative value otherwise.
990 */
991 int (*send_cmd)(struct bnx2x *bp,
992 struct bnx2x_queue_state_params *params);
993
994 /**
995 * Sets the pending bit according to the requested transition.
996 */
997 int (*set_pending)(struct bnx2x_queue_sp_obj *o,
998 struct bnx2x_queue_state_params *params);
999
1000 /**
1001 * Checks that the requested state transition is legal.
1002 */
1003 int (*check_transition)(struct bnx2x *bp,
1004 struct bnx2x_queue_sp_obj *o,
1005 struct bnx2x_queue_state_params *params);
1006
1007 /**
1008 * Completes the pending command.
1009 */
1010 int (*complete_cmd)(struct bnx2x *bp,
1011 struct bnx2x_queue_sp_obj *o,
1012 enum bnx2x_queue_cmd);
1013
1014 int (*wait_comp)(struct bnx2x *bp,
1015 struct bnx2x_queue_sp_obj *o,
1016 enum bnx2x_queue_cmd cmd);
1017 };
1018
1019 /********************** Function state update *********************************/
1020 /* Allowed Function states */
1021 enum bnx2x_func_state {
1022 BNX2X_F_STATE_RESET,
1023 BNX2X_F_STATE_INITIALIZED,
1024 BNX2X_F_STATE_STARTED,
1025 BNX2X_F_STATE_TX_STOPPED,
1026 BNX2X_F_STATE_MAX,
1027 };
1028
1029 /* Allowed Function commands */
1030 enum bnx2x_func_cmd {
1031 BNX2X_F_CMD_HW_INIT,
1032 BNX2X_F_CMD_START,
1033 BNX2X_F_CMD_STOP,
1034 BNX2X_F_CMD_HW_RESET,
1035 BNX2X_F_CMD_TX_STOP,
1036 BNX2X_F_CMD_TX_START,
1037 BNX2X_F_CMD_MAX,
1038 };
1039
1040 struct bnx2x_func_hw_init_params {
1041 /* A load phase returned by MCP.
1042 *
1043 * May be:
1044 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP
1045 * FW_MSG_CODE_DRV_LOAD_COMMON
1046 * FW_MSG_CODE_DRV_LOAD_PORT
1047 * FW_MSG_CODE_DRV_LOAD_FUNCTION
1048 */
1049 u32 load_phase;
1050 };
1051
1052 struct bnx2x_func_hw_reset_params {
1053 /* A load phase returned by MCP.
1054 *
1055 * May be:
1056 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP
1057 * FW_MSG_CODE_DRV_LOAD_COMMON
1058 * FW_MSG_CODE_DRV_LOAD_PORT
1059 * FW_MSG_CODE_DRV_LOAD_FUNCTION
1060 */
1061 u32 reset_phase;
1062 };
1063
1064 struct bnx2x_func_start_params {
1065 /* Multi Function mode:
1066 * - Single Function
1067 * - Switch Dependent
1068 * - Switch Independent
1069 */
1070 u16 mf_mode;
1071
1072 /* Switch Dependent mode outer VLAN tag */
1073 u16 sd_vlan_tag;
1074
1075 /* Function cos mode */
1076 u8 network_cos_mode;
1077 };
1078
1079 struct bnx2x_func_tx_start_params {
1080 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES];
1081 u8 dcb_enabled;
1082 u8 dcb_version;
1083 u8 dont_add_pri_0_en;
1084 };
1085
1086 struct bnx2x_func_state_params {
1087 struct bnx2x_func_sp_obj *f_obj;
1088
1089 /* Current command */
1090 enum bnx2x_func_cmd cmd;
1091
1092 /* may have RAMROD_COMP_WAIT set only */
1093 unsigned long ramrod_flags;
1094
1095 /* Params according to the current command */
1096 union {
1097 struct bnx2x_func_hw_init_params hw_init;
1098 struct bnx2x_func_hw_reset_params hw_reset;
1099 struct bnx2x_func_start_params start;
1100 struct bnx2x_func_tx_start_params tx_start;
1101 } params;
1102 };
1103
1104 struct bnx2x_func_sp_drv_ops {
1105 /* Init tool + runtime initialization:
1106 * - Common Chip
1107 * - Common (per Path)
1108 * - Port
1109 * - Function phases
1110 */
1111 int (*init_hw_cmn_chip)(struct bnx2x *bp);
1112 int (*init_hw_cmn)(struct bnx2x *bp);
1113 int (*init_hw_port)(struct bnx2x *bp);
1114 int (*init_hw_func)(struct bnx2x *bp);
1115
1116 /* Reset Function HW: Common, Port, Function phases. */
1117 void (*reset_hw_cmn)(struct bnx2x *bp);
1118 void (*reset_hw_port)(struct bnx2x *bp);
1119 void (*reset_hw_func)(struct bnx2x *bp);
1120
1121 /* Init/Free GUNZIP resources */
1122 int (*gunzip_init)(struct bnx2x *bp);
1123 void (*gunzip_end)(struct bnx2x *bp);
1124
1125 /* Prepare/Release FW resources */
1126 int (*init_fw)(struct bnx2x *bp);
1127 void (*release_fw)(struct bnx2x *bp);
1128 };
1129
1130 struct bnx2x_func_sp_obj {
1131 enum bnx2x_func_state state, next_state;
1132
1133 /* BNX2X_FUNC_CMD_XX bits. This object implements "one
1134 * pending" paradigm but for debug and tracing purposes it's
1135 * more convinient to have different bits for different
1136 * commands.
1137 */
1138 unsigned long pending;
1139
1140 /* Buffer to use as a ramrod data and its mapping */
1141 void *rdata;
1142 dma_addr_t rdata_mapping;
1143
1144 /* this mutex validates that when pending flag is taken, the next
1145 * ramrod to be sent will be the one set the pending bit
1146 */
1147 struct mutex one_pending_mutex;
1148
1149 /* Driver interface */
1150 struct bnx2x_func_sp_drv_ops *drv;
1151
1152 /**
1153 * Performs one state change according to the given parameters.
1154 *
1155 * @return 0 in case of success and negative value otherwise.
1156 */
1157 int (*send_cmd)(struct bnx2x *bp,
1158 struct bnx2x_func_state_params *params);
1159
1160 /**
1161 * Checks that the requested state transition is legal.
1162 */
1163 int (*check_transition)(struct bnx2x *bp,
1164 struct bnx2x_func_sp_obj *o,
1165 struct bnx2x_func_state_params *params);
1166
1167 /**
1168 * Completes the pending command.
1169 */
1170 int (*complete_cmd)(struct bnx2x *bp,
1171 struct bnx2x_func_sp_obj *o,
1172 enum bnx2x_func_cmd cmd);
1173
1174 int (*wait_comp)(struct bnx2x *bp, struct bnx2x_func_sp_obj *o,
1175 enum bnx2x_func_cmd cmd);
1176 };
1177
1178 /********************** Interfaces ********************************************/
1179 /* Queueable objects set */
1180 union bnx2x_qable_obj {
1181 struct bnx2x_vlan_mac_obj vlan_mac;
1182 };
1183 /************** Function state update *********/
1184 void bnx2x_init_func_obj(struct bnx2x *bp,
1185 struct bnx2x_func_sp_obj *obj,
1186 void *rdata, dma_addr_t rdata_mapping,
1187 struct bnx2x_func_sp_drv_ops *drv_iface);
1188
1189 int bnx2x_func_state_change(struct bnx2x *bp,
1190 struct bnx2x_func_state_params *params);
1191
1192 enum bnx2x_func_state bnx2x_func_get_state(struct bnx2x *bp,
1193 struct bnx2x_func_sp_obj *o);
1194 /******************* Queue State **************/
1195 void bnx2x_init_queue_obj(struct bnx2x *bp,
1196 struct bnx2x_queue_sp_obj *obj, u8 cl_id, u32 *cids,
1197 u8 cid_cnt, u8 func_id, void *rdata,
1198 dma_addr_t rdata_mapping, unsigned long type);
1199
1200 int bnx2x_queue_state_change(struct bnx2x *bp,
1201 struct bnx2x_queue_state_params *params);
1202
1203 /********************* VLAN-MAC ****************/
1204 void bnx2x_init_mac_obj(struct bnx2x *bp,
1205 struct bnx2x_vlan_mac_obj *mac_obj,
1206 u8 cl_id, u32 cid, u8 func_id, void *rdata,
1207 dma_addr_t rdata_mapping, int state,
1208 unsigned long *pstate, bnx2x_obj_type type,
1209 struct bnx2x_credit_pool_obj *macs_pool);
1210
1211 void bnx2x_init_vlan_obj(struct bnx2x *bp,
1212 struct bnx2x_vlan_mac_obj *vlan_obj,
1213 u8 cl_id, u32 cid, u8 func_id, void *rdata,
1214 dma_addr_t rdata_mapping, int state,
1215 unsigned long *pstate, bnx2x_obj_type type,
1216 struct bnx2x_credit_pool_obj *vlans_pool);
1217
1218 void bnx2x_init_vlan_mac_obj(struct bnx2x *bp,
1219 struct bnx2x_vlan_mac_obj *vlan_mac_obj,
1220 u8 cl_id, u32 cid, u8 func_id, void *rdata,
1221 dma_addr_t rdata_mapping, int state,
1222 unsigned long *pstate, bnx2x_obj_type type,
1223 struct bnx2x_credit_pool_obj *macs_pool,
1224 struct bnx2x_credit_pool_obj *vlans_pool);
1225
1226 int bnx2x_config_vlan_mac(struct bnx2x *bp,
1227 struct bnx2x_vlan_mac_ramrod_params *p);
1228
1229 int bnx2x_vlan_mac_move(struct bnx2x *bp,
1230 struct bnx2x_vlan_mac_ramrod_params *p,
1231 struct bnx2x_vlan_mac_obj *dest_o);
1232
1233 /********************* RX MODE ****************/
1234
1235 void bnx2x_init_rx_mode_obj(struct bnx2x *bp,
1236 struct bnx2x_rx_mode_obj *o);
1237
1238 /**
1239 * Send and RX_MODE ramrod according to the provided parameters.
1240 *
1241 * @param bp
1242 * @param p Command parameters
1243 *
1244 * @return 0 - if operation was successfull and there is no pending completions,
1245 * positive number - if there are pending completions,
1246 * negative - if there were errors
1247 */
1248 int bnx2x_config_rx_mode(struct bnx2x *bp,
1249 struct bnx2x_rx_mode_ramrod_params *p);
1250
1251 /****************** MULTICASTS ****************/
1252
1253 void bnx2x_init_mcast_obj(struct bnx2x *bp,
1254 struct bnx2x_mcast_obj *mcast_obj,
1255 u8 mcast_cl_id, u32 mcast_cid, u8 func_id,
1256 u8 engine_id, void *rdata, dma_addr_t rdata_mapping,
1257 int state, unsigned long *pstate,
1258 bnx2x_obj_type type);
1259
1260 /**
1261 * Configure multicast MACs list. May configure a new list
1262 * provided in p->mcast_list (BNX2X_MCAST_CMD_ADD), clean up
1263 * (BNX2X_MCAST_CMD_DEL) or restore (BNX2X_MCAST_CMD_RESTORE) a current
1264 * configuration, continue to execute the pending commands
1265 * (BNX2X_MCAST_CMD_CONT).
1266 *
1267 * If previous command is still pending or if number of MACs to
1268 * configure is more that maximum number of MACs in one command,
1269 * the current command will be enqueued to the tail of the
1270 * pending commands list.
1271 *
1272 * @param bp
1273 * @param p
1274 * @param command to execute: BNX2X_MCAST_CMD_X
1275 *
1276 * @return 0 is operation was sucessfull and there are no pending completions,
1277 * negative if there were errors, positive if there are pending
1278 * completions.
1279 */
1280 int bnx2x_config_mcast(struct bnx2x *bp,
1281 struct bnx2x_mcast_ramrod_params *p, int cmd);
1282
1283 /****************** CREDIT POOL ****************/
1284 void bnx2x_init_mac_credit_pool(struct bnx2x *bp,
1285 struct bnx2x_credit_pool_obj *p, u8 func_id,
1286 u8 func_num);
1287 void bnx2x_init_vlan_credit_pool(struct bnx2x *bp,
1288 struct bnx2x_credit_pool_obj *p, u8 func_id,
1289 u8 func_num);
1290
1291
1292 /****************** RSS CONFIGURATION ****************/
1293 void bnx2x_init_rss_config_obj(struct bnx2x *bp,
1294 struct bnx2x_rss_config_obj *rss_obj,
1295 u8 cl_id, u32 cid, u8 func_id, u8 engine_id,
1296 void *rdata, dma_addr_t rdata_mapping,
1297 int state, unsigned long *pstate,
1298 bnx2x_obj_type type);
1299
1300 /**
1301 * Updates RSS configuration according to provided parameters.
1302 *
1303 * @param bp
1304 * @param p
1305 *
1306 * @return 0 in case of success
1307 */
1308 int bnx2x_config_rss(struct bnx2x *bp,
1309 struct bnx2x_config_rss_params *p);
1310
1311 /**
1312 * Return the current ind_table configuration.
1313 *
1314 * @param bp
1315 * @param ind_table buffer to fill with the current indirection
1316 * table content. Should be at least
1317 * T_ETH_INDIRECTION_TABLE_SIZE bytes long.
1318 */
1319 void bnx2x_get_rss_ind_table(struct bnx2x_rss_config_obj *rss_obj,
1320 u8 *ind_table);
1321
1322 #endif /* BNX2X_SP_VERBS */