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[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_stats.c
1 /* bnx2x_stats.c: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2011 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
20 #include "bnx2x_stats.h"
21 #include "bnx2x_cmn.h"
22
23
24 /* Statistics */
25
26 /*
27 * General service functions
28 */
29
30 static inline long bnx2x_hilo(u32 *hiref)
31 {
32 u32 lo = *(hiref + 1);
33 #if (BITS_PER_LONG == 64)
34 u32 hi = *hiref;
35
36 return HILO_U64(hi, lo);
37 #else
38 return lo;
39 #endif
40 }
41
42 static u16 bnx2x_get_port_stats_dma_len(struct bnx2x *bp)
43 {
44 u16 res = sizeof(struct host_port_stats) >> 2;
45
46 /* if PFC stats are not supported by the MFW, don't DMA them */
47 if (!(bp->flags & BC_SUPPORTS_PFC_STATS))
48 res -= (sizeof(u32)*4) >> 2;
49
50 return res;
51 }
52
53 /*
54 * Init service functions
55 */
56
57 /* Post the next statistics ramrod. Protect it with the spin in
58 * order to ensure the strict order between statistics ramrods
59 * (each ramrod has a sequence number passed in a
60 * bp->fw_stats_req->hdr.drv_stats_counter and ramrods must be
61 * sent in order).
62 */
63 static void bnx2x_storm_stats_post(struct bnx2x *bp)
64 {
65 if (!bp->stats_pending) {
66 int rc;
67
68 spin_lock_bh(&bp->stats_lock);
69
70 if (bp->stats_pending) {
71 spin_unlock_bh(&bp->stats_lock);
72 return;
73 }
74
75 bp->fw_stats_req->hdr.drv_stats_counter =
76 cpu_to_le16(bp->stats_counter++);
77
78 DP(NETIF_MSG_TIMER, "Sending statistics ramrod %d\n",
79 bp->fw_stats_req->hdr.drv_stats_counter);
80
81
82
83 /* send FW stats ramrod */
84 rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_STAT_QUERY, 0,
85 U64_HI(bp->fw_stats_req_mapping),
86 U64_LO(bp->fw_stats_req_mapping),
87 NONE_CONNECTION_TYPE);
88 if (rc == 0)
89 bp->stats_pending = 1;
90
91 spin_unlock_bh(&bp->stats_lock);
92 }
93 }
94
95 static void bnx2x_hw_stats_post(struct bnx2x *bp)
96 {
97 struct dmae_command *dmae = &bp->stats_dmae;
98 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
99
100 *stats_comp = DMAE_COMP_VAL;
101 if (CHIP_REV_IS_SLOW(bp))
102 return;
103
104 /* loader */
105 if (bp->executer_idx) {
106 int loader_idx = PMF_DMAE_C(bp);
107 u32 opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC,
108 true, DMAE_COMP_GRC);
109 opcode = bnx2x_dmae_opcode_clr_src_reset(opcode);
110
111 memset(dmae, 0, sizeof(struct dmae_command));
112 dmae->opcode = opcode;
113 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, dmae[0]));
114 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, dmae[0]));
115 dmae->dst_addr_lo = (DMAE_REG_CMD_MEM +
116 sizeof(struct dmae_command) *
117 (loader_idx + 1)) >> 2;
118 dmae->dst_addr_hi = 0;
119 dmae->len = sizeof(struct dmae_command) >> 2;
120 if (CHIP_IS_E1(bp))
121 dmae->len--;
122 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx + 1] >> 2;
123 dmae->comp_addr_hi = 0;
124 dmae->comp_val = 1;
125
126 *stats_comp = 0;
127 bnx2x_post_dmae(bp, dmae, loader_idx);
128
129 } else if (bp->func_stx) {
130 *stats_comp = 0;
131 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
132 }
133 }
134
135 static int bnx2x_stats_comp(struct bnx2x *bp)
136 {
137 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
138 int cnt = 10;
139
140 might_sleep();
141 while (*stats_comp != DMAE_COMP_VAL) {
142 if (!cnt) {
143 BNX2X_ERR("timeout waiting for stats finished\n");
144 break;
145 }
146 cnt--;
147 usleep_range(1000, 1000);
148 }
149 return 1;
150 }
151
152 /*
153 * Statistics service functions
154 */
155
156 static void bnx2x_stats_pmf_update(struct bnx2x *bp)
157 {
158 struct dmae_command *dmae;
159 u32 opcode;
160 int loader_idx = PMF_DMAE_C(bp);
161 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
162
163 /* sanity */
164 if (!IS_MF(bp) || !bp->port.pmf || !bp->port.port_stx) {
165 BNX2X_ERR("BUG!\n");
166 return;
167 }
168
169 bp->executer_idx = 0;
170
171 opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_GRC, DMAE_DST_PCI, false, 0);
172
173 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
174 dmae->opcode = bnx2x_dmae_opcode_add_comp(opcode, DMAE_COMP_GRC);
175 dmae->src_addr_lo = bp->port.port_stx >> 2;
176 dmae->src_addr_hi = 0;
177 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
178 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
179 dmae->len = DMAE_LEN32_RD_MAX;
180 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
181 dmae->comp_addr_hi = 0;
182 dmae->comp_val = 1;
183
184 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
185 dmae->opcode = bnx2x_dmae_opcode_add_comp(opcode, DMAE_COMP_PCI);
186 dmae->src_addr_lo = (bp->port.port_stx >> 2) + DMAE_LEN32_RD_MAX;
187 dmae->src_addr_hi = 0;
188 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats) +
189 DMAE_LEN32_RD_MAX * 4);
190 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats) +
191 DMAE_LEN32_RD_MAX * 4);
192 dmae->len = bnx2x_get_port_stats_dma_len(bp) - DMAE_LEN32_RD_MAX;
193
194 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
195 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
196 dmae->comp_val = DMAE_COMP_VAL;
197
198 *stats_comp = 0;
199 bnx2x_hw_stats_post(bp);
200 bnx2x_stats_comp(bp);
201 }
202
203 static void bnx2x_port_stats_init(struct bnx2x *bp)
204 {
205 struct dmae_command *dmae;
206 int port = BP_PORT(bp);
207 u32 opcode;
208 int loader_idx = PMF_DMAE_C(bp);
209 u32 mac_addr;
210 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
211
212 /* sanity */
213 if (!bp->link_vars.link_up || !bp->port.pmf) {
214 BNX2X_ERR("BUG!\n");
215 return;
216 }
217
218 bp->executer_idx = 0;
219
220 /* MCP */
221 opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC,
222 true, DMAE_COMP_GRC);
223
224 if (bp->port.port_stx) {
225
226 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
227 dmae->opcode = opcode;
228 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
229 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
230 dmae->dst_addr_lo = bp->port.port_stx >> 2;
231 dmae->dst_addr_hi = 0;
232 dmae->len = bnx2x_get_port_stats_dma_len(bp);
233 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
234 dmae->comp_addr_hi = 0;
235 dmae->comp_val = 1;
236 }
237
238 if (bp->func_stx) {
239
240 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
241 dmae->opcode = opcode;
242 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
243 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
244 dmae->dst_addr_lo = bp->func_stx >> 2;
245 dmae->dst_addr_hi = 0;
246 dmae->len = sizeof(struct host_func_stats) >> 2;
247 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
248 dmae->comp_addr_hi = 0;
249 dmae->comp_val = 1;
250 }
251
252 /* MAC */
253 opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_GRC, DMAE_DST_PCI,
254 true, DMAE_COMP_GRC);
255
256 /* EMAC is special */
257 if (bp->link_vars.mac_type == MAC_TYPE_EMAC) {
258 mac_addr = (port ? GRCBASE_EMAC1 : GRCBASE_EMAC0);
259
260 /* EMAC_REG_EMAC_RX_STAT_AC (EMAC_REG_EMAC_RX_STAT_AC_COUNT)*/
261 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
262 dmae->opcode = opcode;
263 dmae->src_addr_lo = (mac_addr +
264 EMAC_REG_EMAC_RX_STAT_AC) >> 2;
265 dmae->src_addr_hi = 0;
266 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
267 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
268 dmae->len = EMAC_REG_EMAC_RX_STAT_AC_COUNT;
269 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
270 dmae->comp_addr_hi = 0;
271 dmae->comp_val = 1;
272
273 /* EMAC_REG_EMAC_RX_STAT_AC_28 */
274 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
275 dmae->opcode = opcode;
276 dmae->src_addr_lo = (mac_addr +
277 EMAC_REG_EMAC_RX_STAT_AC_28) >> 2;
278 dmae->src_addr_hi = 0;
279 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
280 offsetof(struct emac_stats, rx_stat_falsecarriererrors));
281 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
282 offsetof(struct emac_stats, rx_stat_falsecarriererrors));
283 dmae->len = 1;
284 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
285 dmae->comp_addr_hi = 0;
286 dmae->comp_val = 1;
287
288 /* EMAC_REG_EMAC_TX_STAT_AC (EMAC_REG_EMAC_TX_STAT_AC_COUNT)*/
289 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
290 dmae->opcode = opcode;
291 dmae->src_addr_lo = (mac_addr +
292 EMAC_REG_EMAC_TX_STAT_AC) >> 2;
293 dmae->src_addr_hi = 0;
294 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
295 offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
296 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
297 offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
298 dmae->len = EMAC_REG_EMAC_TX_STAT_AC_COUNT;
299 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
300 dmae->comp_addr_hi = 0;
301 dmae->comp_val = 1;
302 } else {
303 u32 tx_src_addr_lo, rx_src_addr_lo;
304 u16 rx_len, tx_len;
305
306 /* configure the params according to MAC type */
307 switch (bp->link_vars.mac_type) {
308 case MAC_TYPE_BMAC:
309 mac_addr = (port ? NIG_REG_INGRESS_BMAC1_MEM :
310 NIG_REG_INGRESS_BMAC0_MEM);
311
312 /* BIGMAC_REGISTER_TX_STAT_GTPKT ..
313 BIGMAC_REGISTER_TX_STAT_GTBYT */
314 if (CHIP_IS_E1x(bp)) {
315 tx_src_addr_lo = (mac_addr +
316 BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
317 tx_len = (8 + BIGMAC_REGISTER_TX_STAT_GTBYT -
318 BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
319 rx_src_addr_lo = (mac_addr +
320 BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
321 rx_len = (8 + BIGMAC_REGISTER_RX_STAT_GRIPJ -
322 BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
323 } else {
324 tx_src_addr_lo = (mac_addr +
325 BIGMAC2_REGISTER_TX_STAT_GTPOK) >> 2;
326 tx_len = (8 + BIGMAC2_REGISTER_TX_STAT_GTBYT -
327 BIGMAC2_REGISTER_TX_STAT_GTPOK) >> 2;
328 rx_src_addr_lo = (mac_addr +
329 BIGMAC2_REGISTER_RX_STAT_GR64) >> 2;
330 rx_len = (8 + BIGMAC2_REGISTER_RX_STAT_GRIPJ -
331 BIGMAC2_REGISTER_RX_STAT_GR64) >> 2;
332 }
333 break;
334
335 case MAC_TYPE_UMAC: /* handled by MSTAT */
336 case MAC_TYPE_XMAC: /* handled by MSTAT */
337 default:
338 mac_addr = port ? GRCBASE_MSTAT1 : GRCBASE_MSTAT0;
339 tx_src_addr_lo = (mac_addr +
340 MSTAT_REG_TX_STAT_GTXPOK_LO) >> 2;
341 rx_src_addr_lo = (mac_addr +
342 MSTAT_REG_RX_STAT_GR64_LO) >> 2;
343 tx_len = sizeof(bp->slowpath->
344 mac_stats.mstat_stats.stats_tx) >> 2;
345 rx_len = sizeof(bp->slowpath->
346 mac_stats.mstat_stats.stats_rx) >> 2;
347 break;
348 }
349
350 /* TX stats */
351 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
352 dmae->opcode = opcode;
353 dmae->src_addr_lo = tx_src_addr_lo;
354 dmae->src_addr_hi = 0;
355 dmae->len = tx_len;
356 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
357 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
358 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
359 dmae->comp_addr_hi = 0;
360 dmae->comp_val = 1;
361
362 /* RX stats */
363 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
364 dmae->opcode = opcode;
365 dmae->src_addr_hi = 0;
366 dmae->src_addr_lo = rx_src_addr_lo;
367 dmae->dst_addr_lo =
368 U64_LO(bnx2x_sp_mapping(bp, mac_stats) + (tx_len << 2));
369 dmae->dst_addr_hi =
370 U64_HI(bnx2x_sp_mapping(bp, mac_stats) + (tx_len << 2));
371 dmae->len = rx_len;
372 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
373 dmae->comp_addr_hi = 0;
374 dmae->comp_val = 1;
375 }
376
377 /* NIG */
378 if (!CHIP_IS_E3(bp)) {
379 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
380 dmae->opcode = opcode;
381 dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT0 :
382 NIG_REG_STAT0_EGRESS_MAC_PKT0) >> 2;
383 dmae->src_addr_hi = 0;
384 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats) +
385 offsetof(struct nig_stats, egress_mac_pkt0_lo));
386 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats) +
387 offsetof(struct nig_stats, egress_mac_pkt0_lo));
388 dmae->len = (2*sizeof(u32)) >> 2;
389 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
390 dmae->comp_addr_hi = 0;
391 dmae->comp_val = 1;
392
393 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
394 dmae->opcode = opcode;
395 dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT1 :
396 NIG_REG_STAT0_EGRESS_MAC_PKT1) >> 2;
397 dmae->src_addr_hi = 0;
398 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats) +
399 offsetof(struct nig_stats, egress_mac_pkt1_lo));
400 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats) +
401 offsetof(struct nig_stats, egress_mac_pkt1_lo));
402 dmae->len = (2*sizeof(u32)) >> 2;
403 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
404 dmae->comp_addr_hi = 0;
405 dmae->comp_val = 1;
406 }
407
408 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
409 dmae->opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_GRC, DMAE_DST_PCI,
410 true, DMAE_COMP_PCI);
411 dmae->src_addr_lo = (port ? NIG_REG_STAT1_BRB_DISCARD :
412 NIG_REG_STAT0_BRB_DISCARD) >> 2;
413 dmae->src_addr_hi = 0;
414 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats));
415 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats));
416 dmae->len = (sizeof(struct nig_stats) - 4*sizeof(u32)) >> 2;
417
418 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
419 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
420 dmae->comp_val = DMAE_COMP_VAL;
421
422 *stats_comp = 0;
423 }
424
425 static void bnx2x_func_stats_init(struct bnx2x *bp)
426 {
427 struct dmae_command *dmae = &bp->stats_dmae;
428 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
429
430 /* sanity */
431 if (!bp->func_stx) {
432 BNX2X_ERR("BUG!\n");
433 return;
434 }
435
436 bp->executer_idx = 0;
437 memset(dmae, 0, sizeof(struct dmae_command));
438
439 dmae->opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC,
440 true, DMAE_COMP_PCI);
441 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
442 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
443 dmae->dst_addr_lo = bp->func_stx >> 2;
444 dmae->dst_addr_hi = 0;
445 dmae->len = sizeof(struct host_func_stats) >> 2;
446 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
447 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
448 dmae->comp_val = DMAE_COMP_VAL;
449
450 *stats_comp = 0;
451 }
452
453 static void bnx2x_stats_start(struct bnx2x *bp)
454 {
455 if (bp->port.pmf)
456 bnx2x_port_stats_init(bp);
457
458 else if (bp->func_stx)
459 bnx2x_func_stats_init(bp);
460
461 bnx2x_hw_stats_post(bp);
462 bnx2x_storm_stats_post(bp);
463 }
464
465 static void bnx2x_stats_pmf_start(struct bnx2x *bp)
466 {
467 bnx2x_stats_comp(bp);
468 bnx2x_stats_pmf_update(bp);
469 bnx2x_stats_start(bp);
470 }
471
472 static void bnx2x_stats_restart(struct bnx2x *bp)
473 {
474 bnx2x_stats_comp(bp);
475 bnx2x_stats_start(bp);
476 }
477
478 static void bnx2x_bmac_stats_update(struct bnx2x *bp)
479 {
480 struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
481 struct bnx2x_eth_stats *estats = &bp->eth_stats;
482 struct {
483 u32 lo;
484 u32 hi;
485 } diff;
486
487 if (CHIP_IS_E1x(bp)) {
488 struct bmac1_stats *new = bnx2x_sp(bp, mac_stats.bmac1_stats);
489
490 /* the macros below will use "bmac1_stats" type */
491 UPDATE_STAT64(rx_stat_grerb, rx_stat_ifhcinbadoctets);
492 UPDATE_STAT64(rx_stat_grfcs, rx_stat_dot3statsfcserrors);
493 UPDATE_STAT64(rx_stat_grund, rx_stat_etherstatsundersizepkts);
494 UPDATE_STAT64(rx_stat_grovr, rx_stat_dot3statsframestoolong);
495 UPDATE_STAT64(rx_stat_grfrg, rx_stat_etherstatsfragments);
496 UPDATE_STAT64(rx_stat_grjbr, rx_stat_etherstatsjabbers);
497 UPDATE_STAT64(rx_stat_grxcf, rx_stat_maccontrolframesreceived);
498 UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffstateentered);
499 UPDATE_STAT64(rx_stat_grxpf, rx_stat_mac_xpf);
500
501 UPDATE_STAT64(tx_stat_gtxpf, tx_stat_outxoffsent);
502 UPDATE_STAT64(tx_stat_gtxpf, tx_stat_flowcontroldone);
503 UPDATE_STAT64(tx_stat_gt64, tx_stat_etherstatspkts64octets);
504 UPDATE_STAT64(tx_stat_gt127,
505 tx_stat_etherstatspkts65octetsto127octets);
506 UPDATE_STAT64(tx_stat_gt255,
507 tx_stat_etherstatspkts128octetsto255octets);
508 UPDATE_STAT64(tx_stat_gt511,
509 tx_stat_etherstatspkts256octetsto511octets);
510 UPDATE_STAT64(tx_stat_gt1023,
511 tx_stat_etherstatspkts512octetsto1023octets);
512 UPDATE_STAT64(tx_stat_gt1518,
513 tx_stat_etherstatspkts1024octetsto1522octets);
514 UPDATE_STAT64(tx_stat_gt2047, tx_stat_mac_2047);
515 UPDATE_STAT64(tx_stat_gt4095, tx_stat_mac_4095);
516 UPDATE_STAT64(tx_stat_gt9216, tx_stat_mac_9216);
517 UPDATE_STAT64(tx_stat_gt16383, tx_stat_mac_16383);
518 UPDATE_STAT64(tx_stat_gterr,
519 tx_stat_dot3statsinternalmactransmiterrors);
520 UPDATE_STAT64(tx_stat_gtufl, tx_stat_mac_ufl);
521
522 } else {
523 struct bmac2_stats *new = bnx2x_sp(bp, mac_stats.bmac2_stats);
524
525 /* the macros below will use "bmac2_stats" type */
526 UPDATE_STAT64(rx_stat_grerb, rx_stat_ifhcinbadoctets);
527 UPDATE_STAT64(rx_stat_grfcs, rx_stat_dot3statsfcserrors);
528 UPDATE_STAT64(rx_stat_grund, rx_stat_etherstatsundersizepkts);
529 UPDATE_STAT64(rx_stat_grovr, rx_stat_dot3statsframestoolong);
530 UPDATE_STAT64(rx_stat_grfrg, rx_stat_etherstatsfragments);
531 UPDATE_STAT64(rx_stat_grjbr, rx_stat_etherstatsjabbers);
532 UPDATE_STAT64(rx_stat_grxcf, rx_stat_maccontrolframesreceived);
533 UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffstateentered);
534 UPDATE_STAT64(rx_stat_grxpf, rx_stat_mac_xpf);
535 UPDATE_STAT64(tx_stat_gtxpf, tx_stat_outxoffsent);
536 UPDATE_STAT64(tx_stat_gtxpf, tx_stat_flowcontroldone);
537 UPDATE_STAT64(tx_stat_gt64, tx_stat_etherstatspkts64octets);
538 UPDATE_STAT64(tx_stat_gt127,
539 tx_stat_etherstatspkts65octetsto127octets);
540 UPDATE_STAT64(tx_stat_gt255,
541 tx_stat_etherstatspkts128octetsto255octets);
542 UPDATE_STAT64(tx_stat_gt511,
543 tx_stat_etherstatspkts256octetsto511octets);
544 UPDATE_STAT64(tx_stat_gt1023,
545 tx_stat_etherstatspkts512octetsto1023octets);
546 UPDATE_STAT64(tx_stat_gt1518,
547 tx_stat_etherstatspkts1024octetsto1522octets);
548 UPDATE_STAT64(tx_stat_gt2047, tx_stat_mac_2047);
549 UPDATE_STAT64(tx_stat_gt4095, tx_stat_mac_4095);
550 UPDATE_STAT64(tx_stat_gt9216, tx_stat_mac_9216);
551 UPDATE_STAT64(tx_stat_gt16383, tx_stat_mac_16383);
552 UPDATE_STAT64(tx_stat_gterr,
553 tx_stat_dot3statsinternalmactransmiterrors);
554 UPDATE_STAT64(tx_stat_gtufl, tx_stat_mac_ufl);
555
556 /* collect PFC stats */
557 DIFF_64(diff.hi, new->tx_stat_gtpp_hi,
558 pstats->pfc_frames_tx_hi,
559 diff.lo, new->tx_stat_gtpp_lo,
560 pstats->pfc_frames_tx_lo);
561 pstats->pfc_frames_tx_hi = new->tx_stat_gtpp_hi;
562 pstats->pfc_frames_tx_lo = new->tx_stat_gtpp_lo;
563 ADD_64(pstats->pfc_frames_tx_hi, diff.hi,
564 pstats->pfc_frames_tx_lo, diff.lo);
565
566 DIFF_64(diff.hi, new->rx_stat_grpp_hi,
567 pstats->pfc_frames_rx_hi,
568 diff.lo, new->rx_stat_grpp_lo,
569 pstats->pfc_frames_rx_lo);
570 pstats->pfc_frames_rx_hi = new->rx_stat_grpp_hi;
571 pstats->pfc_frames_rx_lo = new->rx_stat_grpp_lo;
572 ADD_64(pstats->pfc_frames_rx_hi, diff.hi,
573 pstats->pfc_frames_rx_lo, diff.lo);
574 }
575
576 estats->pause_frames_received_hi =
577 pstats->mac_stx[1].rx_stat_mac_xpf_hi;
578 estats->pause_frames_received_lo =
579 pstats->mac_stx[1].rx_stat_mac_xpf_lo;
580
581 estats->pause_frames_sent_hi =
582 pstats->mac_stx[1].tx_stat_outxoffsent_hi;
583 estats->pause_frames_sent_lo =
584 pstats->mac_stx[1].tx_stat_outxoffsent_lo;
585
586 estats->pfc_frames_received_hi =
587 pstats->pfc_frames_rx_hi;
588 estats->pfc_frames_received_lo =
589 pstats->pfc_frames_rx_lo;
590 estats->pfc_frames_sent_hi =
591 pstats->pfc_frames_tx_hi;
592 estats->pfc_frames_sent_lo =
593 pstats->pfc_frames_tx_lo;
594 }
595
596 static void bnx2x_mstat_stats_update(struct bnx2x *bp)
597 {
598 struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
599 struct bnx2x_eth_stats *estats = &bp->eth_stats;
600
601 struct mstat_stats *new = bnx2x_sp(bp, mac_stats.mstat_stats);
602
603 ADD_STAT64(stats_rx.rx_grerb, rx_stat_ifhcinbadoctets);
604 ADD_STAT64(stats_rx.rx_grfcs, rx_stat_dot3statsfcserrors);
605 ADD_STAT64(stats_rx.rx_grund, rx_stat_etherstatsundersizepkts);
606 ADD_STAT64(stats_rx.rx_grovr, rx_stat_dot3statsframestoolong);
607 ADD_STAT64(stats_rx.rx_grfrg, rx_stat_etherstatsfragments);
608 ADD_STAT64(stats_rx.rx_grxcf, rx_stat_maccontrolframesreceived);
609 ADD_STAT64(stats_rx.rx_grxpf, rx_stat_xoffstateentered);
610 ADD_STAT64(stats_rx.rx_grxpf, rx_stat_mac_xpf);
611 ADD_STAT64(stats_tx.tx_gtxpf, tx_stat_outxoffsent);
612 ADD_STAT64(stats_tx.tx_gtxpf, tx_stat_flowcontroldone);
613
614 /* collect pfc stats */
615 ADD_64(pstats->pfc_frames_tx_hi, new->stats_tx.tx_gtxpp_hi,
616 pstats->pfc_frames_tx_lo, new->stats_tx.tx_gtxpp_lo);
617 ADD_64(pstats->pfc_frames_rx_hi, new->stats_rx.rx_grxpp_hi,
618 pstats->pfc_frames_rx_lo, new->stats_rx.rx_grxpp_lo);
619
620 ADD_STAT64(stats_tx.tx_gt64, tx_stat_etherstatspkts64octets);
621 ADD_STAT64(stats_tx.tx_gt127,
622 tx_stat_etherstatspkts65octetsto127octets);
623 ADD_STAT64(stats_tx.tx_gt255,
624 tx_stat_etherstatspkts128octetsto255octets);
625 ADD_STAT64(stats_tx.tx_gt511,
626 tx_stat_etherstatspkts256octetsto511octets);
627 ADD_STAT64(stats_tx.tx_gt1023,
628 tx_stat_etherstatspkts512octetsto1023octets);
629 ADD_STAT64(stats_tx.tx_gt1518,
630 tx_stat_etherstatspkts1024octetsto1522octets);
631 ADD_STAT64(stats_tx.tx_gt2047, tx_stat_mac_2047);
632
633 ADD_STAT64(stats_tx.tx_gt4095, tx_stat_mac_4095);
634 ADD_STAT64(stats_tx.tx_gt9216, tx_stat_mac_9216);
635 ADD_STAT64(stats_tx.tx_gt16383, tx_stat_mac_16383);
636
637 ADD_STAT64(stats_tx.tx_gterr,
638 tx_stat_dot3statsinternalmactransmiterrors);
639 ADD_STAT64(stats_tx.tx_gtufl, tx_stat_mac_ufl);
640
641 ADD_64(estats->etherstatspkts1024octetsto1522octets_hi,
642 new->stats_tx.tx_gt1518_hi,
643 estats->etherstatspkts1024octetsto1522octets_lo,
644 new->stats_tx.tx_gt1518_lo);
645
646 ADD_64(estats->etherstatspktsover1522octets_hi,
647 new->stats_tx.tx_gt2047_hi,
648 estats->etherstatspktsover1522octets_lo,
649 new->stats_tx.tx_gt2047_lo);
650
651 ADD_64(estats->etherstatspktsover1522octets_hi,
652 new->stats_tx.tx_gt4095_hi,
653 estats->etherstatspktsover1522octets_lo,
654 new->stats_tx.tx_gt4095_lo);
655
656 ADD_64(estats->etherstatspktsover1522octets_hi,
657 new->stats_tx.tx_gt9216_hi,
658 estats->etherstatspktsover1522octets_lo,
659 new->stats_tx.tx_gt9216_lo);
660
661
662 ADD_64(estats->etherstatspktsover1522octets_hi,
663 new->stats_tx.tx_gt16383_hi,
664 estats->etherstatspktsover1522octets_lo,
665 new->stats_tx.tx_gt16383_lo);
666
667 estats->pause_frames_received_hi =
668 pstats->mac_stx[1].rx_stat_mac_xpf_hi;
669 estats->pause_frames_received_lo =
670 pstats->mac_stx[1].rx_stat_mac_xpf_lo;
671
672 estats->pause_frames_sent_hi =
673 pstats->mac_stx[1].tx_stat_outxoffsent_hi;
674 estats->pause_frames_sent_lo =
675 pstats->mac_stx[1].tx_stat_outxoffsent_lo;
676
677 estats->pfc_frames_received_hi =
678 pstats->pfc_frames_rx_hi;
679 estats->pfc_frames_received_lo =
680 pstats->pfc_frames_rx_lo;
681 estats->pfc_frames_sent_hi =
682 pstats->pfc_frames_tx_hi;
683 estats->pfc_frames_sent_lo =
684 pstats->pfc_frames_tx_lo;
685 }
686
687 static void bnx2x_emac_stats_update(struct bnx2x *bp)
688 {
689 struct emac_stats *new = bnx2x_sp(bp, mac_stats.emac_stats);
690 struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
691 struct bnx2x_eth_stats *estats = &bp->eth_stats;
692
693 UPDATE_EXTEND_STAT(rx_stat_ifhcinbadoctets);
694 UPDATE_EXTEND_STAT(tx_stat_ifhcoutbadoctets);
695 UPDATE_EXTEND_STAT(rx_stat_dot3statsfcserrors);
696 UPDATE_EXTEND_STAT(rx_stat_dot3statsalignmenterrors);
697 UPDATE_EXTEND_STAT(rx_stat_dot3statscarriersenseerrors);
698 UPDATE_EXTEND_STAT(rx_stat_falsecarriererrors);
699 UPDATE_EXTEND_STAT(rx_stat_etherstatsundersizepkts);
700 UPDATE_EXTEND_STAT(rx_stat_dot3statsframestoolong);
701 UPDATE_EXTEND_STAT(rx_stat_etherstatsfragments);
702 UPDATE_EXTEND_STAT(rx_stat_etherstatsjabbers);
703 UPDATE_EXTEND_STAT(rx_stat_maccontrolframesreceived);
704 UPDATE_EXTEND_STAT(rx_stat_xoffstateentered);
705 UPDATE_EXTEND_STAT(rx_stat_xonpauseframesreceived);
706 UPDATE_EXTEND_STAT(rx_stat_xoffpauseframesreceived);
707 UPDATE_EXTEND_STAT(tx_stat_outxonsent);
708 UPDATE_EXTEND_STAT(tx_stat_outxoffsent);
709 UPDATE_EXTEND_STAT(tx_stat_flowcontroldone);
710 UPDATE_EXTEND_STAT(tx_stat_etherstatscollisions);
711 UPDATE_EXTEND_STAT(tx_stat_dot3statssinglecollisionframes);
712 UPDATE_EXTEND_STAT(tx_stat_dot3statsmultiplecollisionframes);
713 UPDATE_EXTEND_STAT(tx_stat_dot3statsdeferredtransmissions);
714 UPDATE_EXTEND_STAT(tx_stat_dot3statsexcessivecollisions);
715 UPDATE_EXTEND_STAT(tx_stat_dot3statslatecollisions);
716 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts64octets);
717 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts65octetsto127octets);
718 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts128octetsto255octets);
719 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts256octetsto511octets);
720 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts512octetsto1023octets);
721 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts1024octetsto1522octets);
722 UPDATE_EXTEND_STAT(tx_stat_etherstatspktsover1522octets);
723 UPDATE_EXTEND_STAT(tx_stat_dot3statsinternalmactransmiterrors);
724
725 estats->pause_frames_received_hi =
726 pstats->mac_stx[1].rx_stat_xonpauseframesreceived_hi;
727 estats->pause_frames_received_lo =
728 pstats->mac_stx[1].rx_stat_xonpauseframesreceived_lo;
729 ADD_64(estats->pause_frames_received_hi,
730 pstats->mac_stx[1].rx_stat_xoffpauseframesreceived_hi,
731 estats->pause_frames_received_lo,
732 pstats->mac_stx[1].rx_stat_xoffpauseframesreceived_lo);
733
734 estats->pause_frames_sent_hi =
735 pstats->mac_stx[1].tx_stat_outxonsent_hi;
736 estats->pause_frames_sent_lo =
737 pstats->mac_stx[1].tx_stat_outxonsent_lo;
738 ADD_64(estats->pause_frames_sent_hi,
739 pstats->mac_stx[1].tx_stat_outxoffsent_hi,
740 estats->pause_frames_sent_lo,
741 pstats->mac_stx[1].tx_stat_outxoffsent_lo);
742 }
743
744 static int bnx2x_hw_stats_update(struct bnx2x *bp)
745 {
746 struct nig_stats *new = bnx2x_sp(bp, nig_stats);
747 struct nig_stats *old = &(bp->port.old_nig_stats);
748 struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
749 struct bnx2x_eth_stats *estats = &bp->eth_stats;
750 struct {
751 u32 lo;
752 u32 hi;
753 } diff;
754
755 switch (bp->link_vars.mac_type) {
756 case MAC_TYPE_BMAC:
757 bnx2x_bmac_stats_update(bp);
758 break;
759
760 case MAC_TYPE_EMAC:
761 bnx2x_emac_stats_update(bp);
762 break;
763
764 case MAC_TYPE_UMAC:
765 case MAC_TYPE_XMAC:
766 bnx2x_mstat_stats_update(bp);
767 break;
768
769 case MAC_TYPE_NONE: /* unreached */
770 DP(BNX2X_MSG_STATS,
771 "stats updated by DMAE but no MAC active\n");
772 return -1;
773
774 default: /* unreached */
775 BNX2X_ERR("Unknown MAC type\n");
776 }
777
778 ADD_EXTEND_64(pstats->brb_drop_hi, pstats->brb_drop_lo,
779 new->brb_discard - old->brb_discard);
780 ADD_EXTEND_64(estats->brb_truncate_hi, estats->brb_truncate_lo,
781 new->brb_truncate - old->brb_truncate);
782
783 if (!CHIP_IS_E3(bp)) {
784 UPDATE_STAT64_NIG(egress_mac_pkt0,
785 etherstatspkts1024octetsto1522octets);
786 UPDATE_STAT64_NIG(egress_mac_pkt1,
787 etherstatspktsover1522octets);
788 }
789
790 memcpy(old, new, sizeof(struct nig_stats));
791
792 memcpy(&(estats->rx_stat_ifhcinbadoctets_hi), &(pstats->mac_stx[1]),
793 sizeof(struct mac_stx));
794 estats->brb_drop_hi = pstats->brb_drop_hi;
795 estats->brb_drop_lo = pstats->brb_drop_lo;
796
797 pstats->host_port_stats_counter++;
798
799 if (!BP_NOMCP(bp)) {
800 u32 nig_timer_max =
801 SHMEM_RD(bp, port_mb[BP_PORT(bp)].stat_nig_timer);
802 if (nig_timer_max != estats->nig_timer_max) {
803 estats->nig_timer_max = nig_timer_max;
804 BNX2X_ERR("NIG timer max (%u)\n",
805 estats->nig_timer_max);
806 }
807 }
808
809 return 0;
810 }
811
812 static int bnx2x_storm_stats_update(struct bnx2x *bp)
813 {
814 struct tstorm_per_port_stats *tport =
815 &bp->fw_stats_data->port.tstorm_port_statistics;
816 struct tstorm_per_pf_stats *tfunc =
817 &bp->fw_stats_data->pf.tstorm_pf_statistics;
818 struct host_func_stats *fstats = bnx2x_sp(bp, func_stats);
819 struct bnx2x_eth_stats *estats = &bp->eth_stats;
820 struct stats_counter *counters = &bp->fw_stats_data->storm_counters;
821 int i;
822 u16 cur_stats_counter;
823
824 /* Make sure we use the value of the counter
825 * used for sending the last stats ramrod.
826 */
827 spin_lock_bh(&bp->stats_lock);
828 cur_stats_counter = bp->stats_counter - 1;
829 spin_unlock_bh(&bp->stats_lock);
830
831 /* are storm stats valid? */
832 if (le16_to_cpu(counters->xstats_counter) != cur_stats_counter) {
833 DP(BNX2X_MSG_STATS, "stats not updated by xstorm"
834 " xstorm counter (0x%x) != stats_counter (0x%x)\n",
835 le16_to_cpu(counters->xstats_counter), bp->stats_counter);
836 return -EAGAIN;
837 }
838
839 if (le16_to_cpu(counters->ustats_counter) != cur_stats_counter) {
840 DP(BNX2X_MSG_STATS, "stats not updated by ustorm"
841 " ustorm counter (0x%x) != stats_counter (0x%x)\n",
842 le16_to_cpu(counters->ustats_counter), bp->stats_counter);
843 return -EAGAIN;
844 }
845
846 if (le16_to_cpu(counters->cstats_counter) != cur_stats_counter) {
847 DP(BNX2X_MSG_STATS, "stats not updated by cstorm"
848 " cstorm counter (0x%x) != stats_counter (0x%x)\n",
849 le16_to_cpu(counters->cstats_counter), bp->stats_counter);
850 return -EAGAIN;
851 }
852
853 if (le16_to_cpu(counters->tstats_counter) != cur_stats_counter) {
854 DP(BNX2X_MSG_STATS, "stats not updated by tstorm"
855 " tstorm counter (0x%x) != stats_counter (0x%x)\n",
856 le16_to_cpu(counters->tstats_counter), bp->stats_counter);
857 return -EAGAIN;
858 }
859
860 memcpy(&(fstats->total_bytes_received_hi),
861 &(bnx2x_sp(bp, func_stats_base)->total_bytes_received_hi),
862 sizeof(struct host_func_stats) - 2*sizeof(u32));
863 estats->error_bytes_received_hi = 0;
864 estats->error_bytes_received_lo = 0;
865 estats->etherstatsoverrsizepkts_hi = 0;
866 estats->etherstatsoverrsizepkts_lo = 0;
867 estats->no_buff_discard_hi = 0;
868 estats->no_buff_discard_lo = 0;
869 estats->total_tpa_aggregations_hi = 0;
870 estats->total_tpa_aggregations_lo = 0;
871 estats->total_tpa_aggregated_frames_hi = 0;
872 estats->total_tpa_aggregated_frames_lo = 0;
873 estats->total_tpa_bytes_hi = 0;
874 estats->total_tpa_bytes_lo = 0;
875
876 for_each_eth_queue(bp, i) {
877 struct bnx2x_fastpath *fp = &bp->fp[i];
878 struct tstorm_per_queue_stats *tclient =
879 &bp->fw_stats_data->queue_stats[i].
880 tstorm_queue_statistics;
881 struct tstorm_per_queue_stats *old_tclient = &fp->old_tclient;
882 struct ustorm_per_queue_stats *uclient =
883 &bp->fw_stats_data->queue_stats[i].
884 ustorm_queue_statistics;
885 struct ustorm_per_queue_stats *old_uclient = &fp->old_uclient;
886 struct xstorm_per_queue_stats *xclient =
887 &bp->fw_stats_data->queue_stats[i].
888 xstorm_queue_statistics;
889 struct xstorm_per_queue_stats *old_xclient = &fp->old_xclient;
890 struct bnx2x_eth_q_stats *qstats = &fp->eth_q_stats;
891 u32 diff;
892
893 DP(BNX2X_MSG_STATS, "queue[%d]: ucast_sent 0x%x, "
894 "bcast_sent 0x%x mcast_sent 0x%x\n",
895 i, xclient->ucast_pkts_sent,
896 xclient->bcast_pkts_sent, xclient->mcast_pkts_sent);
897
898 DP(BNX2X_MSG_STATS, "---------------\n");
899
900 qstats->total_broadcast_bytes_received_hi =
901 le32_to_cpu(tclient->rcv_bcast_bytes.hi);
902 qstats->total_broadcast_bytes_received_lo =
903 le32_to_cpu(tclient->rcv_bcast_bytes.lo);
904
905 qstats->total_multicast_bytes_received_hi =
906 le32_to_cpu(tclient->rcv_mcast_bytes.hi);
907 qstats->total_multicast_bytes_received_lo =
908 le32_to_cpu(tclient->rcv_mcast_bytes.lo);
909
910 qstats->total_unicast_bytes_received_hi =
911 le32_to_cpu(tclient->rcv_ucast_bytes.hi);
912 qstats->total_unicast_bytes_received_lo =
913 le32_to_cpu(tclient->rcv_ucast_bytes.lo);
914
915 /*
916 * sum to total_bytes_received all
917 * unicast/multicast/broadcast
918 */
919 qstats->total_bytes_received_hi =
920 qstats->total_broadcast_bytes_received_hi;
921 qstats->total_bytes_received_lo =
922 qstats->total_broadcast_bytes_received_lo;
923
924 ADD_64(qstats->total_bytes_received_hi,
925 qstats->total_multicast_bytes_received_hi,
926 qstats->total_bytes_received_lo,
927 qstats->total_multicast_bytes_received_lo);
928
929 ADD_64(qstats->total_bytes_received_hi,
930 qstats->total_unicast_bytes_received_hi,
931 qstats->total_bytes_received_lo,
932 qstats->total_unicast_bytes_received_lo);
933
934 qstats->valid_bytes_received_hi =
935 qstats->total_bytes_received_hi;
936 qstats->valid_bytes_received_lo =
937 qstats->total_bytes_received_lo;
938
939
940 UPDATE_EXTEND_TSTAT(rcv_ucast_pkts,
941 total_unicast_packets_received);
942 UPDATE_EXTEND_TSTAT(rcv_mcast_pkts,
943 total_multicast_packets_received);
944 UPDATE_EXTEND_TSTAT(rcv_bcast_pkts,
945 total_broadcast_packets_received);
946 UPDATE_EXTEND_TSTAT(pkts_too_big_discard,
947 etherstatsoverrsizepkts);
948 UPDATE_EXTEND_TSTAT(no_buff_discard, no_buff_discard);
949
950 SUB_EXTEND_USTAT(ucast_no_buff_pkts,
951 total_unicast_packets_received);
952 SUB_EXTEND_USTAT(mcast_no_buff_pkts,
953 total_multicast_packets_received);
954 SUB_EXTEND_USTAT(bcast_no_buff_pkts,
955 total_broadcast_packets_received);
956 UPDATE_EXTEND_USTAT(ucast_no_buff_pkts, no_buff_discard);
957 UPDATE_EXTEND_USTAT(mcast_no_buff_pkts, no_buff_discard);
958 UPDATE_EXTEND_USTAT(bcast_no_buff_pkts, no_buff_discard);
959
960 qstats->total_broadcast_bytes_transmitted_hi =
961 le32_to_cpu(xclient->bcast_bytes_sent.hi);
962 qstats->total_broadcast_bytes_transmitted_lo =
963 le32_to_cpu(xclient->bcast_bytes_sent.lo);
964
965 qstats->total_multicast_bytes_transmitted_hi =
966 le32_to_cpu(xclient->mcast_bytes_sent.hi);
967 qstats->total_multicast_bytes_transmitted_lo =
968 le32_to_cpu(xclient->mcast_bytes_sent.lo);
969
970 qstats->total_unicast_bytes_transmitted_hi =
971 le32_to_cpu(xclient->ucast_bytes_sent.hi);
972 qstats->total_unicast_bytes_transmitted_lo =
973 le32_to_cpu(xclient->ucast_bytes_sent.lo);
974 /*
975 * sum to total_bytes_transmitted all
976 * unicast/multicast/broadcast
977 */
978 qstats->total_bytes_transmitted_hi =
979 qstats->total_unicast_bytes_transmitted_hi;
980 qstats->total_bytes_transmitted_lo =
981 qstats->total_unicast_bytes_transmitted_lo;
982
983 ADD_64(qstats->total_bytes_transmitted_hi,
984 qstats->total_broadcast_bytes_transmitted_hi,
985 qstats->total_bytes_transmitted_lo,
986 qstats->total_broadcast_bytes_transmitted_lo);
987
988 ADD_64(qstats->total_bytes_transmitted_hi,
989 qstats->total_multicast_bytes_transmitted_hi,
990 qstats->total_bytes_transmitted_lo,
991 qstats->total_multicast_bytes_transmitted_lo);
992
993 UPDATE_EXTEND_XSTAT(ucast_pkts_sent,
994 total_unicast_packets_transmitted);
995 UPDATE_EXTEND_XSTAT(mcast_pkts_sent,
996 total_multicast_packets_transmitted);
997 UPDATE_EXTEND_XSTAT(bcast_pkts_sent,
998 total_broadcast_packets_transmitted);
999
1000 UPDATE_EXTEND_TSTAT(checksum_discard,
1001 total_packets_received_checksum_discarded);
1002 UPDATE_EXTEND_TSTAT(ttl0_discard,
1003 total_packets_received_ttl0_discarded);
1004
1005 UPDATE_EXTEND_XSTAT(error_drop_pkts,
1006 total_transmitted_dropped_packets_error);
1007
1008 /* TPA aggregations completed */
1009 UPDATE_EXTEND_USTAT(coalesced_events, total_tpa_aggregations);
1010 /* Number of network frames aggregated by TPA */
1011 UPDATE_EXTEND_USTAT(coalesced_pkts,
1012 total_tpa_aggregated_frames);
1013 /* Total number of bytes in completed TPA aggregations */
1014 qstats->total_tpa_bytes_lo =
1015 le32_to_cpu(uclient->coalesced_bytes.lo);
1016 qstats->total_tpa_bytes_hi =
1017 le32_to_cpu(uclient->coalesced_bytes.hi);
1018
1019 /* TPA stats per-function */
1020 ADD_64(estats->total_tpa_aggregations_hi,
1021 qstats->total_tpa_aggregations_hi,
1022 estats->total_tpa_aggregations_lo,
1023 qstats->total_tpa_aggregations_lo);
1024 ADD_64(estats->total_tpa_aggregated_frames_hi,
1025 qstats->total_tpa_aggregated_frames_hi,
1026 estats->total_tpa_aggregated_frames_lo,
1027 qstats->total_tpa_aggregated_frames_lo);
1028 ADD_64(estats->total_tpa_bytes_hi,
1029 qstats->total_tpa_bytes_hi,
1030 estats->total_tpa_bytes_lo,
1031 qstats->total_tpa_bytes_lo);
1032
1033 ADD_64(fstats->total_bytes_received_hi,
1034 qstats->total_bytes_received_hi,
1035 fstats->total_bytes_received_lo,
1036 qstats->total_bytes_received_lo);
1037 ADD_64(fstats->total_bytes_transmitted_hi,
1038 qstats->total_bytes_transmitted_hi,
1039 fstats->total_bytes_transmitted_lo,
1040 qstats->total_bytes_transmitted_lo);
1041 ADD_64(fstats->total_unicast_packets_received_hi,
1042 qstats->total_unicast_packets_received_hi,
1043 fstats->total_unicast_packets_received_lo,
1044 qstats->total_unicast_packets_received_lo);
1045 ADD_64(fstats->total_multicast_packets_received_hi,
1046 qstats->total_multicast_packets_received_hi,
1047 fstats->total_multicast_packets_received_lo,
1048 qstats->total_multicast_packets_received_lo);
1049 ADD_64(fstats->total_broadcast_packets_received_hi,
1050 qstats->total_broadcast_packets_received_hi,
1051 fstats->total_broadcast_packets_received_lo,
1052 qstats->total_broadcast_packets_received_lo);
1053 ADD_64(fstats->total_unicast_packets_transmitted_hi,
1054 qstats->total_unicast_packets_transmitted_hi,
1055 fstats->total_unicast_packets_transmitted_lo,
1056 qstats->total_unicast_packets_transmitted_lo);
1057 ADD_64(fstats->total_multicast_packets_transmitted_hi,
1058 qstats->total_multicast_packets_transmitted_hi,
1059 fstats->total_multicast_packets_transmitted_lo,
1060 qstats->total_multicast_packets_transmitted_lo);
1061 ADD_64(fstats->total_broadcast_packets_transmitted_hi,
1062 qstats->total_broadcast_packets_transmitted_hi,
1063 fstats->total_broadcast_packets_transmitted_lo,
1064 qstats->total_broadcast_packets_transmitted_lo);
1065 ADD_64(fstats->valid_bytes_received_hi,
1066 qstats->valid_bytes_received_hi,
1067 fstats->valid_bytes_received_lo,
1068 qstats->valid_bytes_received_lo);
1069
1070 ADD_64(estats->etherstatsoverrsizepkts_hi,
1071 qstats->etherstatsoverrsizepkts_hi,
1072 estats->etherstatsoverrsizepkts_lo,
1073 qstats->etherstatsoverrsizepkts_lo);
1074 ADD_64(estats->no_buff_discard_hi, qstats->no_buff_discard_hi,
1075 estats->no_buff_discard_lo, qstats->no_buff_discard_lo);
1076 }
1077
1078 ADD_64(fstats->total_bytes_received_hi,
1079 estats->rx_stat_ifhcinbadoctets_hi,
1080 fstats->total_bytes_received_lo,
1081 estats->rx_stat_ifhcinbadoctets_lo);
1082
1083 ADD_64(fstats->total_bytes_received_hi,
1084 tfunc->rcv_error_bytes.hi,
1085 fstats->total_bytes_received_lo,
1086 tfunc->rcv_error_bytes.lo);
1087
1088 memcpy(estats, &(fstats->total_bytes_received_hi),
1089 sizeof(struct host_func_stats) - 2*sizeof(u32));
1090
1091 ADD_64(estats->error_bytes_received_hi,
1092 tfunc->rcv_error_bytes.hi,
1093 estats->error_bytes_received_lo,
1094 tfunc->rcv_error_bytes.lo);
1095
1096 ADD_64(estats->etherstatsoverrsizepkts_hi,
1097 estats->rx_stat_dot3statsframestoolong_hi,
1098 estats->etherstatsoverrsizepkts_lo,
1099 estats->rx_stat_dot3statsframestoolong_lo);
1100 ADD_64(estats->error_bytes_received_hi,
1101 estats->rx_stat_ifhcinbadoctets_hi,
1102 estats->error_bytes_received_lo,
1103 estats->rx_stat_ifhcinbadoctets_lo);
1104
1105 if (bp->port.pmf) {
1106 estats->mac_filter_discard =
1107 le32_to_cpu(tport->mac_filter_discard);
1108 estats->mf_tag_discard =
1109 le32_to_cpu(tport->mf_tag_discard);
1110 estats->brb_truncate_discard =
1111 le32_to_cpu(tport->brb_truncate_discard);
1112 estats->mac_discard = le32_to_cpu(tport->mac_discard);
1113 }
1114
1115 fstats->host_func_stats_start = ++fstats->host_func_stats_end;
1116
1117 bp->stats_pending = 0;
1118
1119 return 0;
1120 }
1121
1122 static void bnx2x_net_stats_update(struct bnx2x *bp)
1123 {
1124 struct bnx2x_eth_stats *estats = &bp->eth_stats;
1125 struct net_device_stats *nstats = &bp->dev->stats;
1126 unsigned long tmp;
1127 int i;
1128
1129 nstats->rx_packets =
1130 bnx2x_hilo(&estats->total_unicast_packets_received_hi) +
1131 bnx2x_hilo(&estats->total_multicast_packets_received_hi) +
1132 bnx2x_hilo(&estats->total_broadcast_packets_received_hi);
1133
1134 nstats->tx_packets =
1135 bnx2x_hilo(&estats->total_unicast_packets_transmitted_hi) +
1136 bnx2x_hilo(&estats->total_multicast_packets_transmitted_hi) +
1137 bnx2x_hilo(&estats->total_broadcast_packets_transmitted_hi);
1138
1139 nstats->rx_bytes = bnx2x_hilo(&estats->total_bytes_received_hi);
1140
1141 nstats->tx_bytes = bnx2x_hilo(&estats->total_bytes_transmitted_hi);
1142
1143 tmp = estats->mac_discard;
1144 for_each_rx_queue(bp, i)
1145 tmp += le32_to_cpu(bp->fp[i].old_tclient.checksum_discard);
1146 nstats->rx_dropped = tmp;
1147
1148 nstats->tx_dropped = 0;
1149
1150 nstats->multicast =
1151 bnx2x_hilo(&estats->total_multicast_packets_received_hi);
1152
1153 nstats->collisions =
1154 bnx2x_hilo(&estats->tx_stat_etherstatscollisions_hi);
1155
1156 nstats->rx_length_errors =
1157 bnx2x_hilo(&estats->rx_stat_etherstatsundersizepkts_hi) +
1158 bnx2x_hilo(&estats->etherstatsoverrsizepkts_hi);
1159 nstats->rx_over_errors = bnx2x_hilo(&estats->brb_drop_hi) +
1160 bnx2x_hilo(&estats->brb_truncate_hi);
1161 nstats->rx_crc_errors =
1162 bnx2x_hilo(&estats->rx_stat_dot3statsfcserrors_hi);
1163 nstats->rx_frame_errors =
1164 bnx2x_hilo(&estats->rx_stat_dot3statsalignmenterrors_hi);
1165 nstats->rx_fifo_errors = bnx2x_hilo(&estats->no_buff_discard_hi);
1166 nstats->rx_missed_errors = 0;
1167
1168 nstats->rx_errors = nstats->rx_length_errors +
1169 nstats->rx_over_errors +
1170 nstats->rx_crc_errors +
1171 nstats->rx_frame_errors +
1172 nstats->rx_fifo_errors +
1173 nstats->rx_missed_errors;
1174
1175 nstats->tx_aborted_errors =
1176 bnx2x_hilo(&estats->tx_stat_dot3statslatecollisions_hi) +
1177 bnx2x_hilo(&estats->tx_stat_dot3statsexcessivecollisions_hi);
1178 nstats->tx_carrier_errors =
1179 bnx2x_hilo(&estats->rx_stat_dot3statscarriersenseerrors_hi);
1180 nstats->tx_fifo_errors = 0;
1181 nstats->tx_heartbeat_errors = 0;
1182 nstats->tx_window_errors = 0;
1183
1184 nstats->tx_errors = nstats->tx_aborted_errors +
1185 nstats->tx_carrier_errors +
1186 bnx2x_hilo(&estats->tx_stat_dot3statsinternalmactransmiterrors_hi);
1187 }
1188
1189 static void bnx2x_drv_stats_update(struct bnx2x *bp)
1190 {
1191 struct bnx2x_eth_stats *estats = &bp->eth_stats;
1192 int i;
1193
1194 estats->driver_xoff = 0;
1195 estats->rx_err_discard_pkt = 0;
1196 estats->rx_skb_alloc_failed = 0;
1197 estats->hw_csum_err = 0;
1198 for_each_queue(bp, i) {
1199 struct bnx2x_eth_q_stats *qstats = &bp->fp[i].eth_q_stats;
1200
1201 estats->driver_xoff += qstats->driver_xoff;
1202 estats->rx_err_discard_pkt += qstats->rx_err_discard_pkt;
1203 estats->rx_skb_alloc_failed += qstats->rx_skb_alloc_failed;
1204 estats->hw_csum_err += qstats->hw_csum_err;
1205 }
1206 }
1207
1208 static bool bnx2x_edebug_stats_stopped(struct bnx2x *bp)
1209 {
1210 u32 val;
1211
1212 if (SHMEM2_HAS(bp, edebug_driver_if[1])) {
1213 val = SHMEM2_RD(bp, edebug_driver_if[1]);
1214
1215 if (val == EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT)
1216 return true;
1217 }
1218
1219 return false;
1220 }
1221
1222 static void bnx2x_stats_update(struct bnx2x *bp)
1223 {
1224 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
1225
1226 if (bnx2x_edebug_stats_stopped(bp))
1227 return;
1228
1229 if (*stats_comp != DMAE_COMP_VAL)
1230 return;
1231
1232 if (bp->port.pmf)
1233 bnx2x_hw_stats_update(bp);
1234
1235 if (bnx2x_storm_stats_update(bp) && (bp->stats_pending++ == 3)) {
1236 BNX2X_ERR("storm stats were not updated for 3 times\n");
1237 bnx2x_panic();
1238 return;
1239 }
1240
1241 bnx2x_net_stats_update(bp);
1242 bnx2x_drv_stats_update(bp);
1243
1244 if (netif_msg_timer(bp)) {
1245 struct bnx2x_eth_stats *estats = &bp->eth_stats;
1246 int i, cos;
1247
1248 netdev_dbg(bp->dev, "brb drops %u brb truncate %u\n",
1249 estats->brb_drop_lo, estats->brb_truncate_lo);
1250
1251 for_each_eth_queue(bp, i) {
1252 struct bnx2x_fastpath *fp = &bp->fp[i];
1253 struct bnx2x_eth_q_stats *qstats = &fp->eth_q_stats;
1254
1255 pr_debug("%s: rx usage(%4u) *rx_cons_sb(%u) rx pkt(%lu) rx calls(%lu %lu)\n",
1256 fp->name, (le16_to_cpu(*fp->rx_cons_sb) -
1257 fp->rx_comp_cons),
1258 le16_to_cpu(*fp->rx_cons_sb),
1259 bnx2x_hilo(&qstats->
1260 total_unicast_packets_received_hi),
1261 fp->rx_calls, fp->rx_pkt);
1262 }
1263
1264 for_each_eth_queue(bp, i) {
1265 struct bnx2x_fastpath *fp = &bp->fp[i];
1266 struct bnx2x_fp_txdata *txdata;
1267 struct bnx2x_eth_q_stats *qstats = &fp->eth_q_stats;
1268 struct netdev_queue *txq;
1269
1270 pr_debug("%s: tx pkt(%lu) (Xoff events %u)",
1271 fp->name,
1272 bnx2x_hilo(
1273 &qstats->total_unicast_packets_transmitted_hi),
1274 qstats->driver_xoff);
1275
1276 for_each_cos_in_tx_queue(fp, cos) {
1277 txdata = &fp->txdata[cos];
1278 txq = netdev_get_tx_queue(bp->dev,
1279 FP_COS_TO_TXQ(fp, cos));
1280
1281 pr_debug("%d: tx avail(%4u) *tx_cons_sb(%u) tx calls (%lu) %s\n",
1282 cos,
1283 bnx2x_tx_avail(bp, txdata),
1284 le16_to_cpu(*txdata->tx_cons_sb),
1285 txdata->tx_pkt,
1286 (netif_tx_queue_stopped(txq) ?
1287 "Xoff" : "Xon")
1288 );
1289 }
1290 }
1291 }
1292
1293 bnx2x_hw_stats_post(bp);
1294 bnx2x_storm_stats_post(bp);
1295 }
1296
1297 static void bnx2x_port_stats_stop(struct bnx2x *bp)
1298 {
1299 struct dmae_command *dmae;
1300 u32 opcode;
1301 int loader_idx = PMF_DMAE_C(bp);
1302 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
1303
1304 bp->executer_idx = 0;
1305
1306 opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC, false, 0);
1307
1308 if (bp->port.port_stx) {
1309
1310 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
1311 if (bp->func_stx)
1312 dmae->opcode = bnx2x_dmae_opcode_add_comp(
1313 opcode, DMAE_COMP_GRC);
1314 else
1315 dmae->opcode = bnx2x_dmae_opcode_add_comp(
1316 opcode, DMAE_COMP_PCI);
1317
1318 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
1319 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
1320 dmae->dst_addr_lo = bp->port.port_stx >> 2;
1321 dmae->dst_addr_hi = 0;
1322 dmae->len = bnx2x_get_port_stats_dma_len(bp);
1323 if (bp->func_stx) {
1324 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
1325 dmae->comp_addr_hi = 0;
1326 dmae->comp_val = 1;
1327 } else {
1328 dmae->comp_addr_lo =
1329 U64_LO(bnx2x_sp_mapping(bp, stats_comp));
1330 dmae->comp_addr_hi =
1331 U64_HI(bnx2x_sp_mapping(bp, stats_comp));
1332 dmae->comp_val = DMAE_COMP_VAL;
1333
1334 *stats_comp = 0;
1335 }
1336 }
1337
1338 if (bp->func_stx) {
1339
1340 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
1341 dmae->opcode =
1342 bnx2x_dmae_opcode_add_comp(opcode, DMAE_COMP_PCI);
1343 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
1344 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
1345 dmae->dst_addr_lo = bp->func_stx >> 2;
1346 dmae->dst_addr_hi = 0;
1347 dmae->len = sizeof(struct host_func_stats) >> 2;
1348 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
1349 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
1350 dmae->comp_val = DMAE_COMP_VAL;
1351
1352 *stats_comp = 0;
1353 }
1354 }
1355
1356 static void bnx2x_stats_stop(struct bnx2x *bp)
1357 {
1358 int update = 0;
1359
1360 bnx2x_stats_comp(bp);
1361
1362 if (bp->port.pmf)
1363 update = (bnx2x_hw_stats_update(bp) == 0);
1364
1365 update |= (bnx2x_storm_stats_update(bp) == 0);
1366
1367 if (update) {
1368 bnx2x_net_stats_update(bp);
1369
1370 if (bp->port.pmf)
1371 bnx2x_port_stats_stop(bp);
1372
1373 bnx2x_hw_stats_post(bp);
1374 bnx2x_stats_comp(bp);
1375 }
1376 }
1377
1378 static void bnx2x_stats_do_nothing(struct bnx2x *bp)
1379 {
1380 }
1381
1382 static const struct {
1383 void (*action)(struct bnx2x *bp);
1384 enum bnx2x_stats_state next_state;
1385 } bnx2x_stats_stm[STATS_STATE_MAX][STATS_EVENT_MAX] = {
1386 /* state event */
1387 {
1388 /* DISABLED PMF */ {bnx2x_stats_pmf_update, STATS_STATE_DISABLED},
1389 /* LINK_UP */ {bnx2x_stats_start, STATS_STATE_ENABLED},
1390 /* UPDATE */ {bnx2x_stats_do_nothing, STATS_STATE_DISABLED},
1391 /* STOP */ {bnx2x_stats_do_nothing, STATS_STATE_DISABLED}
1392 },
1393 {
1394 /* ENABLED PMF */ {bnx2x_stats_pmf_start, STATS_STATE_ENABLED},
1395 /* LINK_UP */ {bnx2x_stats_restart, STATS_STATE_ENABLED},
1396 /* UPDATE */ {bnx2x_stats_update, STATS_STATE_ENABLED},
1397 /* STOP */ {bnx2x_stats_stop, STATS_STATE_DISABLED}
1398 }
1399 };
1400
1401 void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event)
1402 {
1403 enum bnx2x_stats_state state;
1404 if (unlikely(bp->panic))
1405 return;
1406
1407 spin_lock_bh(&bp->stats_lock);
1408 state = bp->stats_state;
1409 bp->stats_state = bnx2x_stats_stm[state][event].next_state;
1410 spin_unlock_bh(&bp->stats_lock);
1411
1412 bnx2x_stats_stm[state][event].action(bp);
1413
1414 if ((event != STATS_EVENT_UPDATE) || netif_msg_timer(bp))
1415 DP(BNX2X_MSG_STATS, "state %d -> event %d -> state %d\n",
1416 state, event, bp->stats_state);
1417 }
1418
1419 static void bnx2x_port_stats_base_init(struct bnx2x *bp)
1420 {
1421 struct dmae_command *dmae;
1422 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
1423
1424 /* sanity */
1425 if (!bp->port.pmf || !bp->port.port_stx) {
1426 BNX2X_ERR("BUG!\n");
1427 return;
1428 }
1429
1430 bp->executer_idx = 0;
1431
1432 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
1433 dmae->opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC,
1434 true, DMAE_COMP_PCI);
1435 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
1436 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
1437 dmae->dst_addr_lo = bp->port.port_stx >> 2;
1438 dmae->dst_addr_hi = 0;
1439 dmae->len = bnx2x_get_port_stats_dma_len(bp);
1440 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
1441 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
1442 dmae->comp_val = DMAE_COMP_VAL;
1443
1444 *stats_comp = 0;
1445 bnx2x_hw_stats_post(bp);
1446 bnx2x_stats_comp(bp);
1447 }
1448
1449 static void bnx2x_func_stats_base_init(struct bnx2x *bp)
1450 {
1451 int vn, vn_max = IS_MF(bp) ? BP_MAX_VN_NUM(bp) : E1VN_MAX;
1452 u32 func_stx;
1453
1454 /* sanity */
1455 if (!bp->port.pmf || !bp->func_stx) {
1456 BNX2X_ERR("BUG!\n");
1457 return;
1458 }
1459
1460 /* save our func_stx */
1461 func_stx = bp->func_stx;
1462
1463 for (vn = VN_0; vn < vn_max; vn++) {
1464 int mb_idx = BP_FW_MB_IDX_VN(bp, vn);
1465
1466 bp->func_stx = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_param);
1467 bnx2x_func_stats_init(bp);
1468 bnx2x_hw_stats_post(bp);
1469 bnx2x_stats_comp(bp);
1470 }
1471
1472 /* restore our func_stx */
1473 bp->func_stx = func_stx;
1474 }
1475
1476 static void bnx2x_func_stats_base_update(struct bnx2x *bp)
1477 {
1478 struct dmae_command *dmae = &bp->stats_dmae;
1479 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
1480
1481 /* sanity */
1482 if (!bp->func_stx) {
1483 BNX2X_ERR("BUG!\n");
1484 return;
1485 }
1486
1487 bp->executer_idx = 0;
1488 memset(dmae, 0, sizeof(struct dmae_command));
1489
1490 dmae->opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_GRC, DMAE_DST_PCI,
1491 true, DMAE_COMP_PCI);
1492 dmae->src_addr_lo = bp->func_stx >> 2;
1493 dmae->src_addr_hi = 0;
1494 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats_base));
1495 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats_base));
1496 dmae->len = sizeof(struct host_func_stats) >> 2;
1497 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
1498 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
1499 dmae->comp_val = DMAE_COMP_VAL;
1500
1501 *stats_comp = 0;
1502 bnx2x_hw_stats_post(bp);
1503 bnx2x_stats_comp(bp);
1504 }
1505
1506 /**
1507 * This function will prepare the statistics ramrod data the way
1508 * we will only have to increment the statistics counter and
1509 * send the ramrod each time we have to.
1510 *
1511 * @param bp
1512 */
1513 static inline void bnx2x_prep_fw_stats_req(struct bnx2x *bp)
1514 {
1515 int i;
1516 int first_queue_query_index;
1517 struct stats_query_header *stats_hdr = &bp->fw_stats_req->hdr;
1518
1519 dma_addr_t cur_data_offset;
1520 struct stats_query_entry *cur_query_entry;
1521
1522 stats_hdr->cmd_num = bp->fw_stats_num;
1523 stats_hdr->drv_stats_counter = 0;
1524
1525 /* storm_counters struct contains the counters of completed
1526 * statistics requests per storm which are incremented by FW
1527 * each time it completes hadning a statistics ramrod. We will
1528 * check these counters in the timer handler and discard a
1529 * (statistics) ramrod completion.
1530 */
1531 cur_data_offset = bp->fw_stats_data_mapping +
1532 offsetof(struct bnx2x_fw_stats_data, storm_counters);
1533
1534 stats_hdr->stats_counters_addrs.hi =
1535 cpu_to_le32(U64_HI(cur_data_offset));
1536 stats_hdr->stats_counters_addrs.lo =
1537 cpu_to_le32(U64_LO(cur_data_offset));
1538
1539 /* prepare to the first stats ramrod (will be completed with
1540 * the counters equal to zero) - init counters to somethig different.
1541 */
1542 memset(&bp->fw_stats_data->storm_counters, 0xff,
1543 sizeof(struct stats_counter));
1544
1545 /**** Port FW statistics data ****/
1546 cur_data_offset = bp->fw_stats_data_mapping +
1547 offsetof(struct bnx2x_fw_stats_data, port);
1548
1549 cur_query_entry = &bp->fw_stats_req->query[BNX2X_PORT_QUERY_IDX];
1550
1551 cur_query_entry->kind = STATS_TYPE_PORT;
1552 /* For port query index is a DONT CARE */
1553 cur_query_entry->index = BP_PORT(bp);
1554 /* For port query funcID is a DONT CARE */
1555 cur_query_entry->funcID = cpu_to_le16(BP_FUNC(bp));
1556 cur_query_entry->address.hi = cpu_to_le32(U64_HI(cur_data_offset));
1557 cur_query_entry->address.lo = cpu_to_le32(U64_LO(cur_data_offset));
1558
1559 /**** PF FW statistics data ****/
1560 cur_data_offset = bp->fw_stats_data_mapping +
1561 offsetof(struct bnx2x_fw_stats_data, pf);
1562
1563 cur_query_entry = &bp->fw_stats_req->query[BNX2X_PF_QUERY_IDX];
1564
1565 cur_query_entry->kind = STATS_TYPE_PF;
1566 /* For PF query index is a DONT CARE */
1567 cur_query_entry->index = BP_PORT(bp);
1568 cur_query_entry->funcID = cpu_to_le16(BP_FUNC(bp));
1569 cur_query_entry->address.hi = cpu_to_le32(U64_HI(cur_data_offset));
1570 cur_query_entry->address.lo = cpu_to_le32(U64_LO(cur_data_offset));
1571
1572 /**** FCoE FW statistics data ****/
1573 if (!NO_FCOE(bp)) {
1574 cur_data_offset = bp->fw_stats_data_mapping +
1575 offsetof(struct bnx2x_fw_stats_data, fcoe);
1576
1577 cur_query_entry =
1578 &bp->fw_stats_req->query[BNX2X_FCOE_QUERY_IDX];
1579
1580 cur_query_entry->kind = STATS_TYPE_FCOE;
1581 /* For FCoE query index is a DONT CARE */
1582 cur_query_entry->index = BP_PORT(bp);
1583 cur_query_entry->funcID = cpu_to_le16(BP_FUNC(bp));
1584 cur_query_entry->address.hi =
1585 cpu_to_le32(U64_HI(cur_data_offset));
1586 cur_query_entry->address.lo =
1587 cpu_to_le32(U64_LO(cur_data_offset));
1588 }
1589
1590 /**** Clients' queries ****/
1591 cur_data_offset = bp->fw_stats_data_mapping +
1592 offsetof(struct bnx2x_fw_stats_data, queue_stats);
1593
1594 /* first queue query index depends whether FCoE offloaded request will
1595 * be included in the ramrod
1596 */
1597 if (!NO_FCOE(bp))
1598 first_queue_query_index = BNX2X_FIRST_QUEUE_QUERY_IDX;
1599 else
1600 first_queue_query_index = BNX2X_FIRST_QUEUE_QUERY_IDX - 1;
1601
1602 for_each_eth_queue(bp, i) {
1603 cur_query_entry =
1604 &bp->fw_stats_req->
1605 query[first_queue_query_index + i];
1606
1607 cur_query_entry->kind = STATS_TYPE_QUEUE;
1608 cur_query_entry->index = bnx2x_stats_id(&bp->fp[i]);
1609 cur_query_entry->funcID = cpu_to_le16(BP_FUNC(bp));
1610 cur_query_entry->address.hi =
1611 cpu_to_le32(U64_HI(cur_data_offset));
1612 cur_query_entry->address.lo =
1613 cpu_to_le32(U64_LO(cur_data_offset));
1614
1615 cur_data_offset += sizeof(struct per_queue_stats);
1616 }
1617
1618 /* add FCoE queue query if needed */
1619 if (!NO_FCOE(bp)) {
1620 cur_query_entry =
1621 &bp->fw_stats_req->
1622 query[first_queue_query_index + i];
1623
1624 cur_query_entry->kind = STATS_TYPE_QUEUE;
1625 cur_query_entry->index = bnx2x_stats_id(&bp->fp[FCOE_IDX]);
1626 cur_query_entry->funcID = cpu_to_le16(BP_FUNC(bp));
1627 cur_query_entry->address.hi =
1628 cpu_to_le32(U64_HI(cur_data_offset));
1629 cur_query_entry->address.lo =
1630 cpu_to_le32(U64_LO(cur_data_offset));
1631 }
1632 }
1633
1634 void bnx2x_stats_init(struct bnx2x *bp)
1635 {
1636 int /*abs*/port = BP_PORT(bp);
1637 int mb_idx = BP_FW_MB_IDX(bp);
1638 int i;
1639
1640 bp->stats_pending = 0;
1641 bp->executer_idx = 0;
1642 bp->stats_counter = 0;
1643
1644 /* port and func stats for management */
1645 if (!BP_NOMCP(bp)) {
1646 bp->port.port_stx = SHMEM_RD(bp, port_mb[port].port_stx);
1647 bp->func_stx = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_param);
1648
1649 } else {
1650 bp->port.port_stx = 0;
1651 bp->func_stx = 0;
1652 }
1653 DP(BNX2X_MSG_STATS, "port_stx 0x%x func_stx 0x%x\n",
1654 bp->port.port_stx, bp->func_stx);
1655
1656 port = BP_PORT(bp);
1657 /* port stats */
1658 memset(&(bp->port.old_nig_stats), 0, sizeof(struct nig_stats));
1659 bp->port.old_nig_stats.brb_discard =
1660 REG_RD(bp, NIG_REG_STAT0_BRB_DISCARD + port*0x38);
1661 bp->port.old_nig_stats.brb_truncate =
1662 REG_RD(bp, NIG_REG_STAT0_BRB_TRUNCATE + port*0x38);
1663 if (!CHIP_IS_E3(bp)) {
1664 REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT0 + port*0x50,
1665 &(bp->port.old_nig_stats.egress_mac_pkt0_lo), 2);
1666 REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT1 + port*0x50,
1667 &(bp->port.old_nig_stats.egress_mac_pkt1_lo), 2);
1668 }
1669
1670 /* function stats */
1671 for_each_queue(bp, i) {
1672 struct bnx2x_fastpath *fp = &bp->fp[i];
1673
1674 memset(&fp->old_tclient, 0, sizeof(fp->old_tclient));
1675 memset(&fp->old_uclient, 0, sizeof(fp->old_uclient));
1676 memset(&fp->old_xclient, 0, sizeof(fp->old_xclient));
1677 memset(&fp->eth_q_stats, 0, sizeof(fp->eth_q_stats));
1678 }
1679
1680 /* Prepare statistics ramrod data */
1681 bnx2x_prep_fw_stats_req(bp);
1682
1683 memset(&bp->dev->stats, 0, sizeof(bp->dev->stats));
1684 memset(&bp->eth_stats, 0, sizeof(bp->eth_stats));
1685
1686 bp->stats_state = STATS_STATE_DISABLED;
1687
1688 if (bp->port.pmf) {
1689 if (bp->port.port_stx)
1690 bnx2x_port_stats_base_init(bp);
1691
1692 if (bp->func_stx)
1693 bnx2x_func_stats_base_init(bp);
1694
1695 } else if (bp->func_stx)
1696 bnx2x_func_stats_base_update(bp);
1697 }
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