1 /* Broadcom NetXtreme-C/E network driver.
3 * Copyright (c) 2014-2016 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
10 #include <linux/module.h>
12 #include <linux/stringify.h>
13 #include <linux/kernel.h>
14 #include <linux/timer.h>
15 #include <linux/errno.h>
16 #include <linux/ioport.h>
17 #include <linux/slab.h>
18 #include <linux/vmalloc.h>
19 #include <linux/interrupt.h>
20 #include <linux/pci.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23 #include <linux/skbuff.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/bitops.h>
27 #include <linux/irq.h>
28 #include <linux/delay.h>
29 #include <asm/byteorder.h>
31 #include <linux/time.h>
32 #include <linux/mii.h>
34 #include <linux/if_vlan.h>
35 #include <linux/rtc.h>
39 #include <net/checksum.h>
40 #include <net/ip6_checksum.h>
41 #include <net/udp_tunnel.h>
42 #include <linux/workqueue.h>
43 #include <linux/prefetch.h>
44 #include <linux/cache.h>
45 #include <linux/log2.h>
46 #include <linux/aer.h>
47 #include <linux/bitmap.h>
48 #include <linux/cpu_rmap.h>
53 #include "bnxt_sriov.h"
54 #include "bnxt_ethtool.h"
57 #define BNXT_TX_TIMEOUT (5 * HZ)
59 static const char version
[] =
60 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME
" v" DRV_MODULE_VERSION
"\n";
62 MODULE_LICENSE("GPL");
63 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
64 MODULE_VERSION(DRV_MODULE_VERSION
);
66 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
67 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
68 #define BNXT_RX_COPY_THRESH 256
70 #define BNXT_TX_PUSH_THRESH 164
103 /* indexed by enum above */
104 static const struct {
107 { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
108 { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
109 { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
110 { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
111 { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
112 { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
113 { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
114 { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
115 { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
116 { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
117 { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
118 { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
119 { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
120 { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
121 { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
122 { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
123 { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
124 { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
125 { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
126 { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
127 { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
128 { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
129 { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
130 { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
131 { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
132 { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
133 { "Broadcom NetXtreme-E Ethernet Virtual Function" },
134 { "Broadcom NetXtreme-C Ethernet Virtual Function" },
137 static const struct pci_device_id bnxt_pci_tbl
[] = {
138 { PCI_VDEVICE(BROADCOM
, 0x16c0), .driver_data
= BCM57417_NPAR
},
139 { PCI_VDEVICE(BROADCOM
, 0x16c8), .driver_data
= BCM57301
},
140 { PCI_VDEVICE(BROADCOM
, 0x16c9), .driver_data
= BCM57302
},
141 { PCI_VDEVICE(BROADCOM
, 0x16ca), .driver_data
= BCM57304
},
142 { PCI_VDEVICE(BROADCOM
, 0x16cc), .driver_data
= BCM57417_NPAR
},
143 { PCI_VDEVICE(BROADCOM
, 0x16cd), .driver_data
= BCM58700
},
144 { PCI_VDEVICE(BROADCOM
, 0x16ce), .driver_data
= BCM57311
},
145 { PCI_VDEVICE(BROADCOM
, 0x16cf), .driver_data
= BCM57312
},
146 { PCI_VDEVICE(BROADCOM
, 0x16d0), .driver_data
= BCM57402
},
147 { PCI_VDEVICE(BROADCOM
, 0x16d1), .driver_data
= BCM57404
},
148 { PCI_VDEVICE(BROADCOM
, 0x16d2), .driver_data
= BCM57406
},
149 { PCI_VDEVICE(BROADCOM
, 0x16d4), .driver_data
= BCM57402_NPAR
},
150 { PCI_VDEVICE(BROADCOM
, 0x16d5), .driver_data
= BCM57407
},
151 { PCI_VDEVICE(BROADCOM
, 0x16d6), .driver_data
= BCM57412
},
152 { PCI_VDEVICE(BROADCOM
, 0x16d7), .driver_data
= BCM57414
},
153 { PCI_VDEVICE(BROADCOM
, 0x16d8), .driver_data
= BCM57416
},
154 { PCI_VDEVICE(BROADCOM
, 0x16d9), .driver_data
= BCM57417
},
155 { PCI_VDEVICE(BROADCOM
, 0x16de), .driver_data
= BCM57412_NPAR
},
156 { PCI_VDEVICE(BROADCOM
, 0x16df), .driver_data
= BCM57314
},
157 { PCI_VDEVICE(BROADCOM
, 0x16e2), .driver_data
= BCM57417_SFP
},
158 { PCI_VDEVICE(BROADCOM
, 0x16e3), .driver_data
= BCM57416_SFP
},
159 { PCI_VDEVICE(BROADCOM
, 0x16e7), .driver_data
= BCM57404_NPAR
},
160 { PCI_VDEVICE(BROADCOM
, 0x16e8), .driver_data
= BCM57406_NPAR
},
161 { PCI_VDEVICE(BROADCOM
, 0x16e9), .driver_data
= BCM57407_SFP
},
162 { PCI_VDEVICE(BROADCOM
, 0x16ea), .driver_data
= BCM57407_NPAR
},
163 { PCI_VDEVICE(BROADCOM
, 0x16eb), .driver_data
= BCM57412_NPAR
},
164 { PCI_VDEVICE(BROADCOM
, 0x16ec), .driver_data
= BCM57414_NPAR
},
165 { PCI_VDEVICE(BROADCOM
, 0x16ed), .driver_data
= BCM57414_NPAR
},
166 { PCI_VDEVICE(BROADCOM
, 0x16ee), .driver_data
= BCM57416_NPAR
},
167 { PCI_VDEVICE(BROADCOM
, 0x16ef), .driver_data
= BCM57416_NPAR
},
168 #ifdef CONFIG_BNXT_SRIOV
169 { PCI_VDEVICE(BROADCOM
, 0x16c1), .driver_data
= NETXTREME_E_VF
},
170 { PCI_VDEVICE(BROADCOM
, 0x16cb), .driver_data
= NETXTREME_C_VF
},
171 { PCI_VDEVICE(BROADCOM
, 0x16d3), .driver_data
= NETXTREME_E_VF
},
172 { PCI_VDEVICE(BROADCOM
, 0x16dc), .driver_data
= NETXTREME_E_VF
},
173 { PCI_VDEVICE(BROADCOM
, 0x16e1), .driver_data
= NETXTREME_C_VF
},
174 { PCI_VDEVICE(BROADCOM
, 0x16e5), .driver_data
= NETXTREME_C_VF
},
179 MODULE_DEVICE_TABLE(pci
, bnxt_pci_tbl
);
181 static const u16 bnxt_vf_req_snif
[] = {
184 HWRM_CFA_L2_FILTER_ALLOC
,
187 static const u16 bnxt_async_events_arr
[] = {
188 ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE
,
189 ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD
,
190 ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED
,
191 ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE
,
192 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE
,
195 static bool bnxt_vf_pciid(enum board_idx idx
)
197 return (idx
== NETXTREME_C_VF
|| idx
== NETXTREME_E_VF
);
200 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
201 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
202 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
204 #define BNXT_CP_DB_REARM(db, raw_cons) \
205 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
207 #define BNXT_CP_DB(db, raw_cons) \
208 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
210 #define BNXT_CP_DB_IRQ_DIS(db) \
211 writel(DB_CP_IRQ_DIS_FLAGS, db)
213 static inline u32
bnxt_tx_avail(struct bnxt
*bp
, struct bnxt_tx_ring_info
*txr
)
215 /* Tell compiler to fetch tx indices from memory. */
218 return bp
->tx_ring_size
-
219 ((txr
->tx_prod
- txr
->tx_cons
) & bp
->tx_ring_mask
);
222 static const u16 bnxt_lhint_arr
[] = {
223 TX_BD_FLAGS_LHINT_512_AND_SMALLER
,
224 TX_BD_FLAGS_LHINT_512_TO_1023
,
225 TX_BD_FLAGS_LHINT_1024_TO_2047
,
226 TX_BD_FLAGS_LHINT_1024_TO_2047
,
227 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
228 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
229 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
230 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
231 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
232 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
233 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
234 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
235 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
236 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
237 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
238 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
239 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
240 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
241 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
244 static netdev_tx_t
bnxt_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
246 struct bnxt
*bp
= netdev_priv(dev
);
248 struct tx_bd_ext
*txbd1
;
249 struct netdev_queue
*txq
;
252 unsigned int length
, pad
= 0;
253 u32 len
, free_size
, vlan_tag_flags
, cfa_action
, flags
;
255 struct pci_dev
*pdev
= bp
->pdev
;
256 struct bnxt_tx_ring_info
*txr
;
257 struct bnxt_sw_tx_bd
*tx_buf
;
259 i
= skb_get_queue_mapping(skb
);
260 if (unlikely(i
>= bp
->tx_nr_rings
)) {
261 dev_kfree_skb_any(skb
);
265 txr
= &bp
->tx_ring
[i
];
266 txq
= netdev_get_tx_queue(dev
, i
);
269 free_size
= bnxt_tx_avail(bp
, txr
);
270 if (unlikely(free_size
< skb_shinfo(skb
)->nr_frags
+ 2)) {
271 netif_tx_stop_queue(txq
);
272 return NETDEV_TX_BUSY
;
276 len
= skb_headlen(skb
);
277 last_frag
= skb_shinfo(skb
)->nr_frags
;
279 txbd
= &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
281 txbd
->tx_bd_opaque
= prod
;
283 tx_buf
= &txr
->tx_buf_ring
[prod
];
285 tx_buf
->nr_frags
= last_frag
;
289 if (skb_vlan_tag_present(skb
)) {
290 vlan_tag_flags
= TX_BD_CFA_META_KEY_VLAN
|
291 skb_vlan_tag_get(skb
);
292 /* Currently supports 8021Q, 8021AD vlan offloads
293 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
295 if (skb
->vlan_proto
== htons(ETH_P_8021Q
))
296 vlan_tag_flags
|= 1 << TX_BD_CFA_META_TPID_SHIFT
;
299 if (free_size
== bp
->tx_ring_size
&& length
<= bp
->tx_push_thresh
) {
300 struct tx_push_buffer
*tx_push_buf
= txr
->tx_push
;
301 struct tx_push_bd
*tx_push
= &tx_push_buf
->push_bd
;
302 struct tx_bd_ext
*tx_push1
= &tx_push
->txbd2
;
303 void *pdata
= tx_push_buf
->data
;
307 /* Set COAL_NOW to be ready quickly for the next push */
308 tx_push
->tx_bd_len_flags_type
=
309 cpu_to_le32((length
<< TX_BD_LEN_SHIFT
) |
310 TX_BD_TYPE_LONG_TX_BD
|
311 TX_BD_FLAGS_LHINT_512_AND_SMALLER
|
312 TX_BD_FLAGS_COAL_NOW
|
313 TX_BD_FLAGS_PACKET_END
|
314 (2 << TX_BD_FLAGS_BD_CNT_SHIFT
));
316 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
317 tx_push1
->tx_bd_hsize_lflags
=
318 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM
);
320 tx_push1
->tx_bd_hsize_lflags
= 0;
322 tx_push1
->tx_bd_cfa_meta
= cpu_to_le32(vlan_tag_flags
);
323 tx_push1
->tx_bd_cfa_action
= cpu_to_le32(cfa_action
);
325 end
= pdata
+ length
;
326 end
= PTR_ALIGN(end
, 8) - 1;
329 skb_copy_from_linear_data(skb
, pdata
, len
);
331 for (j
= 0; j
< last_frag
; j
++) {
332 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[j
];
335 fptr
= skb_frag_address_safe(frag
);
339 memcpy(pdata
, fptr
, skb_frag_size(frag
));
340 pdata
+= skb_frag_size(frag
);
343 txbd
->tx_bd_len_flags_type
= tx_push
->tx_bd_len_flags_type
;
344 txbd
->tx_bd_haddr
= txr
->data_mapping
;
345 prod
= NEXT_TX(prod
);
346 txbd
= &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
347 memcpy(txbd
, tx_push1
, sizeof(*txbd
));
348 prod
= NEXT_TX(prod
);
350 cpu_to_le32(DB_KEY_TX_PUSH
| DB_LONG_TX_PUSH
| prod
);
354 netdev_tx_sent_queue(txq
, skb
->len
);
355 wmb(); /* Sync is_push and byte queue before pushing data */
357 push_len
= (length
+ sizeof(*tx_push
) + 7) / 8;
359 __iowrite64_copy(txr
->tx_doorbell
, tx_push_buf
, 16);
360 __iowrite32_copy(txr
->tx_doorbell
+ 4, tx_push_buf
+ 1,
361 (push_len
- 16) << 1);
363 __iowrite64_copy(txr
->tx_doorbell
, tx_push_buf
,
371 if (length
< BNXT_MIN_PKT_SIZE
) {
372 pad
= BNXT_MIN_PKT_SIZE
- length
;
373 if (skb_pad(skb
, pad
)) {
374 /* SKB already freed. */
378 length
= BNXT_MIN_PKT_SIZE
;
381 mapping
= dma_map_single(&pdev
->dev
, skb
->data
, len
, DMA_TO_DEVICE
);
383 if (unlikely(dma_mapping_error(&pdev
->dev
, mapping
))) {
384 dev_kfree_skb_any(skb
);
389 dma_unmap_addr_set(tx_buf
, mapping
, mapping
);
390 flags
= (len
<< TX_BD_LEN_SHIFT
) | TX_BD_TYPE_LONG_TX_BD
|
391 ((last_frag
+ 2) << TX_BD_FLAGS_BD_CNT_SHIFT
);
393 txbd
->tx_bd_haddr
= cpu_to_le64(mapping
);
395 prod
= NEXT_TX(prod
);
396 txbd1
= (struct tx_bd_ext
*)
397 &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
399 txbd1
->tx_bd_hsize_lflags
= 0;
400 if (skb_is_gso(skb
)) {
403 if (skb
->encapsulation
)
404 hdr_len
= skb_inner_network_offset(skb
) +
405 skb_inner_network_header_len(skb
) +
406 inner_tcp_hdrlen(skb
);
408 hdr_len
= skb_transport_offset(skb
) +
411 txbd1
->tx_bd_hsize_lflags
= cpu_to_le32(TX_BD_FLAGS_LSO
|
413 (hdr_len
<< (TX_BD_HSIZE_SHIFT
- 1)));
414 length
= skb_shinfo(skb
)->gso_size
;
415 txbd1
->tx_bd_mss
= cpu_to_le32(length
);
417 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
418 txbd1
->tx_bd_hsize_lflags
=
419 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM
);
420 txbd1
->tx_bd_mss
= 0;
424 flags
|= bnxt_lhint_arr
[length
];
425 txbd
->tx_bd_len_flags_type
= cpu_to_le32(flags
);
427 txbd1
->tx_bd_cfa_meta
= cpu_to_le32(vlan_tag_flags
);
428 txbd1
->tx_bd_cfa_action
= cpu_to_le32(cfa_action
);
429 for (i
= 0; i
< last_frag
; i
++) {
430 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
432 prod
= NEXT_TX(prod
);
433 txbd
= &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
435 len
= skb_frag_size(frag
);
436 mapping
= skb_frag_dma_map(&pdev
->dev
, frag
, 0, len
,
439 if (unlikely(dma_mapping_error(&pdev
->dev
, mapping
)))
442 tx_buf
= &txr
->tx_buf_ring
[prod
];
443 dma_unmap_addr_set(tx_buf
, mapping
, mapping
);
445 txbd
->tx_bd_haddr
= cpu_to_le64(mapping
);
447 flags
= len
<< TX_BD_LEN_SHIFT
;
448 txbd
->tx_bd_len_flags_type
= cpu_to_le32(flags
);
452 txbd
->tx_bd_len_flags_type
=
453 cpu_to_le32(((len
+ pad
) << TX_BD_LEN_SHIFT
) | flags
|
454 TX_BD_FLAGS_PACKET_END
);
456 netdev_tx_sent_queue(txq
, skb
->len
);
458 /* Sync BD data before updating doorbell */
461 prod
= NEXT_TX(prod
);
464 writel(DB_KEY_TX
| prod
, txr
->tx_doorbell
);
465 writel(DB_KEY_TX
| prod
, txr
->tx_doorbell
);
471 if (unlikely(bnxt_tx_avail(bp
, txr
) <= MAX_SKB_FRAGS
+ 1)) {
472 netif_tx_stop_queue(txq
);
474 /* netif_tx_stop_queue() must be done before checking
475 * tx index in bnxt_tx_avail() below, because in
476 * bnxt_tx_int(), we update tx index before checking for
477 * netif_tx_queue_stopped().
480 if (bnxt_tx_avail(bp
, txr
) > bp
->tx_wake_thresh
)
481 netif_tx_wake_queue(txq
);
488 /* start back at beginning and unmap skb */
490 tx_buf
= &txr
->tx_buf_ring
[prod
];
492 dma_unmap_single(&pdev
->dev
, dma_unmap_addr(tx_buf
, mapping
),
493 skb_headlen(skb
), PCI_DMA_TODEVICE
);
494 prod
= NEXT_TX(prod
);
496 /* unmap remaining mapped pages */
497 for (i
= 0; i
< last_frag
; i
++) {
498 prod
= NEXT_TX(prod
);
499 tx_buf
= &txr
->tx_buf_ring
[prod
];
500 dma_unmap_page(&pdev
->dev
, dma_unmap_addr(tx_buf
, mapping
),
501 skb_frag_size(&skb_shinfo(skb
)->frags
[i
]),
505 dev_kfree_skb_any(skb
);
509 static void bnxt_tx_int(struct bnxt
*bp
, struct bnxt_napi
*bnapi
, int nr_pkts
)
511 struct bnxt_tx_ring_info
*txr
= bnapi
->tx_ring
;
512 int index
= txr
- &bp
->tx_ring
[0];
513 struct netdev_queue
*txq
= netdev_get_tx_queue(bp
->dev
, index
);
514 u16 cons
= txr
->tx_cons
;
515 struct pci_dev
*pdev
= bp
->pdev
;
517 unsigned int tx_bytes
= 0;
519 for (i
= 0; i
< nr_pkts
; i
++) {
520 struct bnxt_sw_tx_bd
*tx_buf
;
524 tx_buf
= &txr
->tx_buf_ring
[cons
];
525 cons
= NEXT_TX(cons
);
529 if (tx_buf
->is_push
) {
534 dma_unmap_single(&pdev
->dev
, dma_unmap_addr(tx_buf
, mapping
),
535 skb_headlen(skb
), PCI_DMA_TODEVICE
);
536 last
= tx_buf
->nr_frags
;
538 for (j
= 0; j
< last
; j
++) {
539 cons
= NEXT_TX(cons
);
540 tx_buf
= &txr
->tx_buf_ring
[cons
];
543 dma_unmap_addr(tx_buf
, mapping
),
544 skb_frag_size(&skb_shinfo(skb
)->frags
[j
]),
549 cons
= NEXT_TX(cons
);
551 tx_bytes
+= skb
->len
;
552 dev_kfree_skb_any(skb
);
555 netdev_tx_completed_queue(txq
, nr_pkts
, tx_bytes
);
558 /* Need to make the tx_cons update visible to bnxt_start_xmit()
559 * before checking for netif_tx_queue_stopped(). Without the
560 * memory barrier, there is a small possibility that bnxt_start_xmit()
561 * will miss it and cause the queue to be stopped forever.
565 if (unlikely(netif_tx_queue_stopped(txq
)) &&
566 (bnxt_tx_avail(bp
, txr
) > bp
->tx_wake_thresh
)) {
567 __netif_tx_lock(txq
, smp_processor_id());
568 if (netif_tx_queue_stopped(txq
) &&
569 bnxt_tx_avail(bp
, txr
) > bp
->tx_wake_thresh
&&
570 txr
->dev_state
!= BNXT_DEV_STATE_CLOSING
)
571 netif_tx_wake_queue(txq
);
572 __netif_tx_unlock(txq
);
576 static inline u8
*__bnxt_alloc_rx_data(struct bnxt
*bp
, dma_addr_t
*mapping
,
580 struct pci_dev
*pdev
= bp
->pdev
;
582 data
= kmalloc(bp
->rx_buf_size
, gfp
);
586 *mapping
= dma_map_single(&pdev
->dev
, data
+ BNXT_RX_DMA_OFFSET
,
587 bp
->rx_buf_use_size
, PCI_DMA_FROMDEVICE
);
589 if (dma_mapping_error(&pdev
->dev
, *mapping
)) {
596 static inline int bnxt_alloc_rx_data(struct bnxt
*bp
,
597 struct bnxt_rx_ring_info
*rxr
,
600 struct rx_bd
*rxbd
= &rxr
->rx_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
601 struct bnxt_sw_rx_bd
*rx_buf
= &rxr
->rx_buf_ring
[prod
];
605 data
= __bnxt_alloc_rx_data(bp
, &mapping
, gfp
);
610 dma_unmap_addr_set(rx_buf
, mapping
, mapping
);
612 rxbd
->rx_bd_haddr
= cpu_to_le64(mapping
);
617 static void bnxt_reuse_rx_data(struct bnxt_rx_ring_info
*rxr
, u16 cons
,
620 u16 prod
= rxr
->rx_prod
;
621 struct bnxt_sw_rx_bd
*cons_rx_buf
, *prod_rx_buf
;
622 struct rx_bd
*cons_bd
, *prod_bd
;
624 prod_rx_buf
= &rxr
->rx_buf_ring
[prod
];
625 cons_rx_buf
= &rxr
->rx_buf_ring
[cons
];
627 prod_rx_buf
->data
= data
;
629 dma_unmap_addr_set(prod_rx_buf
, mapping
,
630 dma_unmap_addr(cons_rx_buf
, mapping
));
632 prod_bd
= &rxr
->rx_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
633 cons_bd
= &rxr
->rx_desc_ring
[RX_RING(cons
)][RX_IDX(cons
)];
635 prod_bd
->rx_bd_haddr
= cons_bd
->rx_bd_haddr
;
638 static inline u16
bnxt_find_next_agg_idx(struct bnxt_rx_ring_info
*rxr
, u16 idx
)
640 u16 next
, max
= rxr
->rx_agg_bmap_size
;
642 next
= find_next_zero_bit(rxr
->rx_agg_bmap
, max
, idx
);
644 next
= find_first_zero_bit(rxr
->rx_agg_bmap
, max
);
648 static inline int bnxt_alloc_rx_page(struct bnxt
*bp
,
649 struct bnxt_rx_ring_info
*rxr
,
653 &rxr
->rx_agg_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
654 struct bnxt_sw_rx_agg_bd
*rx_agg_buf
;
655 struct pci_dev
*pdev
= bp
->pdev
;
658 u16 sw_prod
= rxr
->rx_sw_agg_prod
;
659 unsigned int offset
= 0;
661 if (PAGE_SIZE
> BNXT_RX_PAGE_SIZE
) {
664 page
= alloc_page(gfp
);
668 rxr
->rx_page_offset
= 0;
670 offset
= rxr
->rx_page_offset
;
671 rxr
->rx_page_offset
+= BNXT_RX_PAGE_SIZE
;
672 if (rxr
->rx_page_offset
== PAGE_SIZE
)
677 page
= alloc_page(gfp
);
682 mapping
= dma_map_page(&pdev
->dev
, page
, offset
, BNXT_RX_PAGE_SIZE
,
684 if (dma_mapping_error(&pdev
->dev
, mapping
)) {
689 if (unlikely(test_bit(sw_prod
, rxr
->rx_agg_bmap
)))
690 sw_prod
= bnxt_find_next_agg_idx(rxr
, sw_prod
);
692 __set_bit(sw_prod
, rxr
->rx_agg_bmap
);
693 rx_agg_buf
= &rxr
->rx_agg_ring
[sw_prod
];
694 rxr
->rx_sw_agg_prod
= NEXT_RX_AGG(sw_prod
);
696 rx_agg_buf
->page
= page
;
697 rx_agg_buf
->offset
= offset
;
698 rx_agg_buf
->mapping
= mapping
;
699 rxbd
->rx_bd_haddr
= cpu_to_le64(mapping
);
700 rxbd
->rx_bd_opaque
= sw_prod
;
704 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi
*bnapi
, u16 cp_cons
,
707 struct bnxt
*bp
= bnapi
->bp
;
708 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
709 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
710 u16 prod
= rxr
->rx_agg_prod
;
711 u16 sw_prod
= rxr
->rx_sw_agg_prod
;
714 for (i
= 0; i
< agg_bufs
; i
++) {
716 struct rx_agg_cmp
*agg
;
717 struct bnxt_sw_rx_agg_bd
*cons_rx_buf
, *prod_rx_buf
;
718 struct rx_bd
*prod_bd
;
721 agg
= (struct rx_agg_cmp
*)
722 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
723 cons
= agg
->rx_agg_cmp_opaque
;
724 __clear_bit(cons
, rxr
->rx_agg_bmap
);
726 if (unlikely(test_bit(sw_prod
, rxr
->rx_agg_bmap
)))
727 sw_prod
= bnxt_find_next_agg_idx(rxr
, sw_prod
);
729 __set_bit(sw_prod
, rxr
->rx_agg_bmap
);
730 prod_rx_buf
= &rxr
->rx_agg_ring
[sw_prod
];
731 cons_rx_buf
= &rxr
->rx_agg_ring
[cons
];
733 /* It is possible for sw_prod to be equal to cons, so
734 * set cons_rx_buf->page to NULL first.
736 page
= cons_rx_buf
->page
;
737 cons_rx_buf
->page
= NULL
;
738 prod_rx_buf
->page
= page
;
739 prod_rx_buf
->offset
= cons_rx_buf
->offset
;
741 prod_rx_buf
->mapping
= cons_rx_buf
->mapping
;
743 prod_bd
= &rxr
->rx_agg_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
745 prod_bd
->rx_bd_haddr
= cpu_to_le64(cons_rx_buf
->mapping
);
746 prod_bd
->rx_bd_opaque
= sw_prod
;
748 prod
= NEXT_RX_AGG(prod
);
749 sw_prod
= NEXT_RX_AGG(sw_prod
);
750 cp_cons
= NEXT_CMP(cp_cons
);
752 rxr
->rx_agg_prod
= prod
;
753 rxr
->rx_sw_agg_prod
= sw_prod
;
756 static struct sk_buff
*bnxt_rx_skb(struct bnxt
*bp
,
757 struct bnxt_rx_ring_info
*rxr
, u16 cons
,
758 u16 prod
, u8
*data
, dma_addr_t dma_addr
,
764 err
= bnxt_alloc_rx_data(bp
, rxr
, prod
, GFP_ATOMIC
);
766 bnxt_reuse_rx_data(rxr
, cons
, data
);
770 skb
= build_skb(data
, 0);
771 dma_unmap_single(&bp
->pdev
->dev
, dma_addr
, bp
->rx_buf_use_size
,
778 skb_reserve(skb
, BNXT_RX_OFFSET
);
783 static struct sk_buff
*bnxt_rx_pages(struct bnxt
*bp
, struct bnxt_napi
*bnapi
,
784 struct sk_buff
*skb
, u16 cp_cons
,
787 struct pci_dev
*pdev
= bp
->pdev
;
788 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
789 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
790 u16 prod
= rxr
->rx_agg_prod
;
793 for (i
= 0; i
< agg_bufs
; i
++) {
795 struct rx_agg_cmp
*agg
;
796 struct bnxt_sw_rx_agg_bd
*cons_rx_buf
;
800 agg
= (struct rx_agg_cmp
*)
801 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
802 cons
= agg
->rx_agg_cmp_opaque
;
803 frag_len
= (le32_to_cpu(agg
->rx_agg_cmp_len_flags_type
) &
804 RX_AGG_CMP_LEN
) >> RX_AGG_CMP_LEN_SHIFT
;
806 cons_rx_buf
= &rxr
->rx_agg_ring
[cons
];
807 skb_fill_page_desc(skb
, i
, cons_rx_buf
->page
,
808 cons_rx_buf
->offset
, frag_len
);
809 __clear_bit(cons
, rxr
->rx_agg_bmap
);
811 /* It is possible for bnxt_alloc_rx_page() to allocate
812 * a sw_prod index that equals the cons index, so we
813 * need to clear the cons entry now.
815 mapping
= dma_unmap_addr(cons_rx_buf
, mapping
);
816 page
= cons_rx_buf
->page
;
817 cons_rx_buf
->page
= NULL
;
819 if (bnxt_alloc_rx_page(bp
, rxr
, prod
, GFP_ATOMIC
) != 0) {
820 struct skb_shared_info
*shinfo
;
821 unsigned int nr_frags
;
823 shinfo
= skb_shinfo(skb
);
824 nr_frags
= --shinfo
->nr_frags
;
825 __skb_frag_set_page(&shinfo
->frags
[nr_frags
], NULL
);
829 cons_rx_buf
->page
= page
;
831 /* Update prod since possibly some pages have been
834 rxr
->rx_agg_prod
= prod
;
835 bnxt_reuse_rx_agg_bufs(bnapi
, cp_cons
, agg_bufs
- i
);
839 dma_unmap_page(&pdev
->dev
, mapping
, BNXT_RX_PAGE_SIZE
,
842 skb
->data_len
+= frag_len
;
843 skb
->len
+= frag_len
;
844 skb
->truesize
+= PAGE_SIZE
;
846 prod
= NEXT_RX_AGG(prod
);
847 cp_cons
= NEXT_CMP(cp_cons
);
849 rxr
->rx_agg_prod
= prod
;
853 static int bnxt_agg_bufs_valid(struct bnxt
*bp
, struct bnxt_cp_ring_info
*cpr
,
854 u8 agg_bufs
, u32
*raw_cons
)
857 struct rx_agg_cmp
*agg
;
859 *raw_cons
= ADV_RAW_CMP(*raw_cons
, agg_bufs
);
860 last
= RING_CMP(*raw_cons
);
861 agg
= (struct rx_agg_cmp
*)
862 &cpr
->cp_desc_ring
[CP_RING(last
)][CP_IDX(last
)];
863 return RX_AGG_CMP_VALID(agg
, *raw_cons
);
866 static inline struct sk_buff
*bnxt_copy_skb(struct bnxt_napi
*bnapi
, u8
*data
,
870 struct bnxt
*bp
= bnapi
->bp
;
871 struct pci_dev
*pdev
= bp
->pdev
;
874 skb
= napi_alloc_skb(&bnapi
->napi
, len
);
878 dma_sync_single_for_cpu(&pdev
->dev
, mapping
,
879 bp
->rx_copy_thresh
, PCI_DMA_FROMDEVICE
);
881 memcpy(skb
->data
- BNXT_RX_OFFSET
, data
, len
+ BNXT_RX_OFFSET
);
883 dma_sync_single_for_device(&pdev
->dev
, mapping
,
891 static int bnxt_discard_rx(struct bnxt
*bp
, struct bnxt_napi
*bnapi
,
892 u32
*raw_cons
, void *cmp
)
894 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
895 struct rx_cmp
*rxcmp
= cmp
;
896 u32 tmp_raw_cons
= *raw_cons
;
897 u8 cmp_type
, agg_bufs
= 0;
899 cmp_type
= RX_CMP_TYPE(rxcmp
);
901 if (cmp_type
== CMP_TYPE_RX_L2_CMP
) {
902 agg_bufs
= (le32_to_cpu(rxcmp
->rx_cmp_misc_v1
) &
904 RX_CMP_AGG_BUFS_SHIFT
;
905 } else if (cmp_type
== CMP_TYPE_RX_L2_TPA_END_CMP
) {
906 struct rx_tpa_end_cmp
*tpa_end
= cmp
;
908 agg_bufs
= (le32_to_cpu(tpa_end
->rx_tpa_end_cmp_misc_v1
) &
909 RX_TPA_END_CMP_AGG_BUFS
) >>
910 RX_TPA_END_CMP_AGG_BUFS_SHIFT
;
914 if (!bnxt_agg_bufs_valid(bp
, cpr
, agg_bufs
, &tmp_raw_cons
))
917 *raw_cons
= tmp_raw_cons
;
921 static void bnxt_sched_reset(struct bnxt
*bp
, struct bnxt_rx_ring_info
*rxr
)
923 if (!rxr
->bnapi
->in_reset
) {
924 rxr
->bnapi
->in_reset
= true;
925 set_bit(BNXT_RESET_TASK_SP_EVENT
, &bp
->sp_event
);
926 schedule_work(&bp
->sp_task
);
928 rxr
->rx_next_cons
= 0xffff;
931 static void bnxt_tpa_start(struct bnxt
*bp
, struct bnxt_rx_ring_info
*rxr
,
932 struct rx_tpa_start_cmp
*tpa_start
,
933 struct rx_tpa_start_cmp_ext
*tpa_start1
)
935 u8 agg_id
= TPA_START_AGG_ID(tpa_start
);
937 struct bnxt_tpa_info
*tpa_info
;
938 struct bnxt_sw_rx_bd
*cons_rx_buf
, *prod_rx_buf
;
939 struct rx_bd
*prod_bd
;
942 cons
= tpa_start
->rx_tpa_start_cmp_opaque
;
944 cons_rx_buf
= &rxr
->rx_buf_ring
[cons
];
945 prod_rx_buf
= &rxr
->rx_buf_ring
[prod
];
946 tpa_info
= &rxr
->rx_tpa
[agg_id
];
948 if (unlikely(cons
!= rxr
->rx_next_cons
)) {
949 bnxt_sched_reset(bp
, rxr
);
953 prod_rx_buf
->data
= tpa_info
->data
;
955 mapping
= tpa_info
->mapping
;
956 dma_unmap_addr_set(prod_rx_buf
, mapping
, mapping
);
958 prod_bd
= &rxr
->rx_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
960 prod_bd
->rx_bd_haddr
= cpu_to_le64(mapping
);
962 tpa_info
->data
= cons_rx_buf
->data
;
963 cons_rx_buf
->data
= NULL
;
964 tpa_info
->mapping
= dma_unmap_addr(cons_rx_buf
, mapping
);
967 le32_to_cpu(tpa_start
->rx_tpa_start_cmp_len_flags_type
) >>
968 RX_TPA_START_CMP_LEN_SHIFT
;
969 if (likely(TPA_START_HASH_VALID(tpa_start
))) {
970 u32 hash_type
= TPA_START_HASH_TYPE(tpa_start
);
972 tpa_info
->hash_type
= PKT_HASH_TYPE_L4
;
973 tpa_info
->gso_type
= SKB_GSO_TCPV4
;
974 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
976 tpa_info
->gso_type
= SKB_GSO_TCPV6
;
978 le32_to_cpu(tpa_start
->rx_tpa_start_cmp_rss_hash
);
980 tpa_info
->hash_type
= PKT_HASH_TYPE_NONE
;
981 tpa_info
->gso_type
= 0;
982 if (netif_msg_rx_err(bp
))
983 netdev_warn(bp
->dev
, "TPA packet without valid hash\n");
985 tpa_info
->flags2
= le32_to_cpu(tpa_start1
->rx_tpa_start_cmp_flags2
);
986 tpa_info
->metadata
= le32_to_cpu(tpa_start1
->rx_tpa_start_cmp_metadata
);
987 tpa_info
->hdr_info
= le32_to_cpu(tpa_start1
->rx_tpa_start_cmp_hdr_info
);
989 rxr
->rx_prod
= NEXT_RX(prod
);
990 cons
= NEXT_RX(cons
);
991 rxr
->rx_next_cons
= NEXT_RX(cons
);
992 cons_rx_buf
= &rxr
->rx_buf_ring
[cons
];
994 bnxt_reuse_rx_data(rxr
, cons
, cons_rx_buf
->data
);
995 rxr
->rx_prod
= NEXT_RX(rxr
->rx_prod
);
996 cons_rx_buf
->data
= NULL
;
999 static void bnxt_abort_tpa(struct bnxt
*bp
, struct bnxt_napi
*bnapi
,
1000 u16 cp_cons
, u32 agg_bufs
)
1003 bnxt_reuse_rx_agg_bufs(bnapi
, cp_cons
, agg_bufs
);
1006 static struct sk_buff
*bnxt_gro_func_5731x(struct bnxt_tpa_info
*tpa_info
,
1007 int payload_off
, int tcp_ts
,
1008 struct sk_buff
*skb
)
1013 u16 outer_ip_off
, inner_ip_off
, inner_mac_off
;
1014 u32 hdr_info
= tpa_info
->hdr_info
;
1015 bool loopback
= false;
1017 inner_ip_off
= BNXT_TPA_INNER_L3_OFF(hdr_info
);
1018 inner_mac_off
= BNXT_TPA_INNER_L2_OFF(hdr_info
);
1019 outer_ip_off
= BNXT_TPA_OUTER_L3_OFF(hdr_info
);
1021 /* If the packet is an internal loopback packet, the offsets will
1022 * have an extra 4 bytes.
1024 if (inner_mac_off
== 4) {
1026 } else if (inner_mac_off
> 4) {
1027 __be16 proto
= *((__be16
*)(skb
->data
+ inner_ip_off
-
1030 /* We only support inner iPv4/ipv6. If we don't see the
1031 * correct protocol ID, it must be a loopback packet where
1032 * the offsets are off by 4.
1034 if (proto
!= htons(ETH_P_IP
) && proto
!= htons(ETH_P_IPV6
))
1038 /* internal loopback packet, subtract all offsets by 4 */
1044 nw_off
= inner_ip_off
- ETH_HLEN
;
1045 skb_set_network_header(skb
, nw_off
);
1046 if (tpa_info
->flags2
& RX_TPA_START_CMP_FLAGS2_IP_TYPE
) {
1047 struct ipv6hdr
*iph
= ipv6_hdr(skb
);
1049 skb_set_transport_header(skb
, nw_off
+ sizeof(struct ipv6hdr
));
1050 len
= skb
->len
- skb_transport_offset(skb
);
1052 th
->check
= ~tcp_v6_check(len
, &iph
->saddr
, &iph
->daddr
, 0);
1054 struct iphdr
*iph
= ip_hdr(skb
);
1056 skb_set_transport_header(skb
, nw_off
+ sizeof(struct iphdr
));
1057 len
= skb
->len
- skb_transport_offset(skb
);
1059 th
->check
= ~tcp_v4_check(len
, iph
->saddr
, iph
->daddr
, 0);
1062 if (inner_mac_off
) { /* tunnel */
1063 struct udphdr
*uh
= NULL
;
1064 __be16 proto
= *((__be16
*)(skb
->data
+ outer_ip_off
-
1067 if (proto
== htons(ETH_P_IP
)) {
1068 struct iphdr
*iph
= (struct iphdr
*)skb
->data
;
1070 if (iph
->protocol
== IPPROTO_UDP
)
1071 uh
= (struct udphdr
*)(iph
+ 1);
1073 struct ipv6hdr
*iph
= (struct ipv6hdr
*)skb
->data
;
1075 if (iph
->nexthdr
== IPPROTO_UDP
)
1076 uh
= (struct udphdr
*)(iph
+ 1);
1080 skb_shinfo(skb
)->gso_type
|=
1081 SKB_GSO_UDP_TUNNEL_CSUM
;
1083 skb_shinfo(skb
)->gso_type
|= SKB_GSO_UDP_TUNNEL
;
1090 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
1091 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1093 static struct sk_buff
*bnxt_gro_func_5730x(struct bnxt_tpa_info
*tpa_info
,
1094 int payload_off
, int tcp_ts
,
1095 struct sk_buff
*skb
)
1099 int len
, nw_off
, tcp_opt_len
= 0;
1104 if (tpa_info
->gso_type
== SKB_GSO_TCPV4
) {
1107 nw_off
= payload_off
- BNXT_IPV4_HDR_SIZE
- tcp_opt_len
-
1109 skb_set_network_header(skb
, nw_off
);
1111 skb_set_transport_header(skb
, nw_off
+ sizeof(struct iphdr
));
1112 len
= skb
->len
- skb_transport_offset(skb
);
1114 th
->check
= ~tcp_v4_check(len
, iph
->saddr
, iph
->daddr
, 0);
1115 } else if (tpa_info
->gso_type
== SKB_GSO_TCPV6
) {
1116 struct ipv6hdr
*iph
;
1118 nw_off
= payload_off
- BNXT_IPV6_HDR_SIZE
- tcp_opt_len
-
1120 skb_set_network_header(skb
, nw_off
);
1121 iph
= ipv6_hdr(skb
);
1122 skb_set_transport_header(skb
, nw_off
+ sizeof(struct ipv6hdr
));
1123 len
= skb
->len
- skb_transport_offset(skb
);
1125 th
->check
= ~tcp_v6_check(len
, &iph
->saddr
, &iph
->daddr
, 0);
1127 dev_kfree_skb_any(skb
);
1131 if (nw_off
) { /* tunnel */
1132 struct udphdr
*uh
= NULL
;
1134 if (skb
->protocol
== htons(ETH_P_IP
)) {
1135 struct iphdr
*iph
= (struct iphdr
*)skb
->data
;
1137 if (iph
->protocol
== IPPROTO_UDP
)
1138 uh
= (struct udphdr
*)(iph
+ 1);
1140 struct ipv6hdr
*iph
= (struct ipv6hdr
*)skb
->data
;
1142 if (iph
->nexthdr
== IPPROTO_UDP
)
1143 uh
= (struct udphdr
*)(iph
+ 1);
1147 skb_shinfo(skb
)->gso_type
|=
1148 SKB_GSO_UDP_TUNNEL_CSUM
;
1150 skb_shinfo(skb
)->gso_type
|= SKB_GSO_UDP_TUNNEL
;
1157 static inline struct sk_buff
*bnxt_gro_skb(struct bnxt
*bp
,
1158 struct bnxt_tpa_info
*tpa_info
,
1159 struct rx_tpa_end_cmp
*tpa_end
,
1160 struct rx_tpa_end_cmp_ext
*tpa_end1
,
1161 struct sk_buff
*skb
)
1167 segs
= TPA_END_TPA_SEGS(tpa_end
);
1171 NAPI_GRO_CB(skb
)->count
= segs
;
1172 skb_shinfo(skb
)->gso_size
=
1173 le32_to_cpu(tpa_end1
->rx_tpa_end_cmp_seg_len
);
1174 skb_shinfo(skb
)->gso_type
= tpa_info
->gso_type
;
1175 payload_off
= (le32_to_cpu(tpa_end
->rx_tpa_end_cmp_misc_v1
) &
1176 RX_TPA_END_CMP_PAYLOAD_OFFSET
) >>
1177 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT
;
1178 skb
= bp
->gro_func(tpa_info
, payload_off
, TPA_END_GRO_TS(tpa_end
), skb
);
1180 tcp_gro_complete(skb
);
1185 static inline struct sk_buff
*bnxt_tpa_end(struct bnxt
*bp
,
1186 struct bnxt_napi
*bnapi
,
1188 struct rx_tpa_end_cmp
*tpa_end
,
1189 struct rx_tpa_end_cmp_ext
*tpa_end1
,
1192 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1193 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
1194 u8 agg_id
= TPA_END_AGG_ID(tpa_end
);
1196 u16 cp_cons
= RING_CMP(*raw_cons
);
1198 struct bnxt_tpa_info
*tpa_info
;
1200 struct sk_buff
*skb
;
1202 if (unlikely(bnapi
->in_reset
)) {
1203 int rc
= bnxt_discard_rx(bp
, bnapi
, raw_cons
, tpa_end
);
1206 return ERR_PTR(-EBUSY
);
1210 tpa_info
= &rxr
->rx_tpa
[agg_id
];
1211 data
= tpa_info
->data
;
1213 len
= tpa_info
->len
;
1214 mapping
= tpa_info
->mapping
;
1216 agg_bufs
= (le32_to_cpu(tpa_end
->rx_tpa_end_cmp_misc_v1
) &
1217 RX_TPA_END_CMP_AGG_BUFS
) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT
;
1220 if (!bnxt_agg_bufs_valid(bp
, cpr
, agg_bufs
, raw_cons
))
1221 return ERR_PTR(-EBUSY
);
1224 cp_cons
= NEXT_CMP(cp_cons
);
1227 if (unlikely(agg_bufs
> MAX_SKB_FRAGS
)) {
1228 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
1229 netdev_warn(bp
->dev
, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1230 agg_bufs
, (int)MAX_SKB_FRAGS
);
1234 if (len
<= bp
->rx_copy_thresh
) {
1235 skb
= bnxt_copy_skb(bnapi
, data
, len
, mapping
);
1237 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
1242 dma_addr_t new_mapping
;
1244 new_data
= __bnxt_alloc_rx_data(bp
, &new_mapping
, GFP_ATOMIC
);
1246 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
1250 tpa_info
->data
= new_data
;
1251 tpa_info
->mapping
= new_mapping
;
1253 skb
= build_skb(data
, 0);
1254 dma_unmap_single(&bp
->pdev
->dev
, mapping
, bp
->rx_buf_use_size
,
1255 PCI_DMA_FROMDEVICE
);
1259 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
1262 skb_reserve(skb
, BNXT_RX_OFFSET
);
1267 skb
= bnxt_rx_pages(bp
, bnapi
, skb
, cp_cons
, agg_bufs
);
1269 /* Page reuse already handled by bnxt_rx_pages(). */
1273 skb
->protocol
= eth_type_trans(skb
, bp
->dev
);
1275 if (tpa_info
->hash_type
!= PKT_HASH_TYPE_NONE
)
1276 skb_set_hash(skb
, tpa_info
->rss_hash
, tpa_info
->hash_type
);
1278 if ((tpa_info
->flags2
& RX_CMP_FLAGS2_META_FORMAT_VLAN
) &&
1279 (skb
->dev
->features
& NETIF_F_HW_VLAN_CTAG_RX
)) {
1280 u16 vlan_proto
= tpa_info
->metadata
>>
1281 RX_CMP_FLAGS2_METADATA_TPID_SFT
;
1282 u16 vtag
= tpa_info
->metadata
& RX_CMP_FLAGS2_METADATA_VID_MASK
;
1284 __vlan_hwaccel_put_tag(skb
, htons(vlan_proto
), vtag
);
1287 skb_checksum_none_assert(skb
);
1288 if (likely(tpa_info
->flags2
& RX_TPA_START_CMP_FLAGS2_L4_CS_CALC
)) {
1289 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1291 (tpa_info
->flags2
& RX_CMP_FLAGS2_T_L4_CS_CALC
) >> 3;
1294 if (TPA_END_GRO(tpa_end
))
1295 skb
= bnxt_gro_skb(bp
, tpa_info
, tpa_end
, tpa_end1
, skb
);
1300 /* returns the following:
1301 * 1 - 1 packet successfully received
1302 * 0 - successful TPA_START, packet not completed yet
1303 * -EBUSY - completion ring does not have all the agg buffers yet
1304 * -ENOMEM - packet aborted due to out of memory
1305 * -EIO - packet aborted due to hw error indicated in BD
1307 static int bnxt_rx_pkt(struct bnxt
*bp
, struct bnxt_napi
*bnapi
, u32
*raw_cons
,
1310 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1311 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
1312 struct net_device
*dev
= bp
->dev
;
1313 struct rx_cmp
*rxcmp
;
1314 struct rx_cmp_ext
*rxcmp1
;
1315 u32 tmp_raw_cons
= *raw_cons
;
1316 u16 cons
, prod
, cp_cons
= RING_CMP(tmp_raw_cons
);
1317 struct bnxt_sw_rx_bd
*rx_buf
;
1319 u8
*data
, agg_bufs
, cmp_type
;
1320 dma_addr_t dma_addr
;
1321 struct sk_buff
*skb
;
1324 rxcmp
= (struct rx_cmp
*)
1325 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
1327 tmp_raw_cons
= NEXT_RAW_CMP(tmp_raw_cons
);
1328 cp_cons
= RING_CMP(tmp_raw_cons
);
1329 rxcmp1
= (struct rx_cmp_ext
*)
1330 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
1332 if (!RX_CMP_VALID(rxcmp1
, tmp_raw_cons
))
1335 cmp_type
= RX_CMP_TYPE(rxcmp
);
1337 prod
= rxr
->rx_prod
;
1339 if (cmp_type
== CMP_TYPE_RX_L2_TPA_START_CMP
) {
1340 bnxt_tpa_start(bp
, rxr
, (struct rx_tpa_start_cmp
*)rxcmp
,
1341 (struct rx_tpa_start_cmp_ext
*)rxcmp1
);
1343 goto next_rx_no_prod
;
1345 } else if (cmp_type
== CMP_TYPE_RX_L2_TPA_END_CMP
) {
1346 skb
= bnxt_tpa_end(bp
, bnapi
, &tmp_raw_cons
,
1347 (struct rx_tpa_end_cmp
*)rxcmp
,
1348 (struct rx_tpa_end_cmp_ext
*)rxcmp1
,
1351 if (unlikely(IS_ERR(skb
)))
1356 skb_record_rx_queue(skb
, bnapi
->index
);
1357 napi_gro_receive(&bnapi
->napi
, skb
);
1360 goto next_rx_no_prod
;
1363 cons
= rxcmp
->rx_cmp_opaque
;
1364 rx_buf
= &rxr
->rx_buf_ring
[cons
];
1365 data
= rx_buf
->data
;
1366 if (unlikely(cons
!= rxr
->rx_next_cons
)) {
1367 int rc1
= bnxt_discard_rx(bp
, bnapi
, raw_cons
, rxcmp
);
1369 bnxt_sched_reset(bp
, rxr
);
1374 agg_bufs
= (le32_to_cpu(rxcmp
->rx_cmp_misc_v1
) & RX_CMP_AGG_BUFS
) >>
1375 RX_CMP_AGG_BUFS_SHIFT
;
1378 if (!bnxt_agg_bufs_valid(bp
, cpr
, agg_bufs
, &tmp_raw_cons
))
1381 cp_cons
= NEXT_CMP(cp_cons
);
1385 rx_buf
->data
= NULL
;
1386 if (rxcmp1
->rx_cmp_cfa_code_errors_v2
& RX_CMP_L2_ERRORS
) {
1387 bnxt_reuse_rx_data(rxr
, cons
, data
);
1389 bnxt_reuse_rx_agg_bufs(bnapi
, cp_cons
, agg_bufs
);
1395 len
= le32_to_cpu(rxcmp
->rx_cmp_len_flags_type
) >> RX_CMP_LEN_SHIFT
;
1396 dma_addr
= dma_unmap_addr(rx_buf
, mapping
);
1398 if (len
<= bp
->rx_copy_thresh
) {
1399 skb
= bnxt_copy_skb(bnapi
, data
, len
, dma_addr
);
1400 bnxt_reuse_rx_data(rxr
, cons
, data
);
1406 skb
= bnxt_rx_skb(bp
, rxr
, cons
, prod
, data
, dma_addr
, len
);
1414 skb
= bnxt_rx_pages(bp
, bnapi
, skb
, cp_cons
, agg_bufs
);
1421 if (RX_CMP_HASH_VALID(rxcmp
)) {
1422 u32 hash_type
= RX_CMP_HASH_TYPE(rxcmp
);
1423 enum pkt_hash_types type
= PKT_HASH_TYPE_L4
;
1425 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1426 if (hash_type
!= 1 && hash_type
!= 3)
1427 type
= PKT_HASH_TYPE_L3
;
1428 skb_set_hash(skb
, le32_to_cpu(rxcmp
->rx_cmp_rss_hash
), type
);
1431 skb
->protocol
= eth_type_trans(skb
, dev
);
1433 if ((rxcmp1
->rx_cmp_flags2
&
1434 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN
)) &&
1435 (skb
->dev
->features
& NETIF_F_HW_VLAN_CTAG_RX
)) {
1436 u32 meta_data
= le32_to_cpu(rxcmp1
->rx_cmp_meta_data
);
1437 u16 vtag
= meta_data
& RX_CMP_FLAGS2_METADATA_VID_MASK
;
1438 u16 vlan_proto
= meta_data
>> RX_CMP_FLAGS2_METADATA_TPID_SFT
;
1440 __vlan_hwaccel_put_tag(skb
, htons(vlan_proto
), vtag
);
1443 skb_checksum_none_assert(skb
);
1444 if (RX_CMP_L4_CS_OK(rxcmp1
)) {
1445 if (dev
->features
& NETIF_F_RXCSUM
) {
1446 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1447 skb
->csum_level
= RX_CMP_ENCAP(rxcmp1
);
1450 if (rxcmp1
->rx_cmp_cfa_code_errors_v2
& RX_CMP_L4_CS_ERR_BITS
) {
1451 if (dev
->features
& NETIF_F_RXCSUM
)
1452 cpr
->rx_l4_csum_errors
++;
1456 skb_record_rx_queue(skb
, bnapi
->index
);
1457 napi_gro_receive(&bnapi
->napi
, skb
);
1461 rxr
->rx_prod
= NEXT_RX(prod
);
1462 rxr
->rx_next_cons
= NEXT_RX(cons
);
1465 *raw_cons
= tmp_raw_cons
;
1470 #define BNXT_GET_EVENT_PORT(data) \
1472 ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
1474 static int bnxt_async_event_process(struct bnxt
*bp
,
1475 struct hwrm_async_event_cmpl
*cmpl
)
1477 u16 event_id
= le16_to_cpu(cmpl
->event_id
);
1479 /* TODO CHIMP_FW: Define event id's for link change, error etc */
1481 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE
: {
1482 u32 data1
= le32_to_cpu(cmpl
->event_data1
);
1483 struct bnxt_link_info
*link_info
= &bp
->link_info
;
1486 goto async_event_process_exit
;
1487 if (data1
& 0x20000) {
1488 u16 fw_speed
= link_info
->force_link_speed
;
1489 u32 speed
= bnxt_fw_to_ethtool_speed(fw_speed
);
1491 netdev_warn(bp
->dev
, "Link speed %d no longer supported\n",
1494 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT
, &bp
->sp_event
);
1497 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE
:
1498 set_bit(BNXT_LINK_CHNG_SP_EVENT
, &bp
->sp_event
);
1500 case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD
:
1501 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT
, &bp
->sp_event
);
1503 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED
: {
1504 u32 data1
= le32_to_cpu(cmpl
->event_data1
);
1505 u16 port_id
= BNXT_GET_EVENT_PORT(data1
);
1510 if (bp
->pf
.port_id
!= port_id
)
1513 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT
, &bp
->sp_event
);
1516 case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE
:
1518 goto async_event_process_exit
;
1519 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT
, &bp
->sp_event
);
1522 goto async_event_process_exit
;
1524 schedule_work(&bp
->sp_task
);
1525 async_event_process_exit
:
1526 bnxt_ulp_async_events(bp
, cmpl
);
1530 static int bnxt_hwrm_handler(struct bnxt
*bp
, struct tx_cmp
*txcmp
)
1532 u16 cmpl_type
= TX_CMP_TYPE(txcmp
), vf_id
, seq_id
;
1533 struct hwrm_cmpl
*h_cmpl
= (struct hwrm_cmpl
*)txcmp
;
1534 struct hwrm_fwd_req_cmpl
*fwd_req_cmpl
=
1535 (struct hwrm_fwd_req_cmpl
*)txcmp
;
1537 switch (cmpl_type
) {
1538 case CMPL_BASE_TYPE_HWRM_DONE
:
1539 seq_id
= le16_to_cpu(h_cmpl
->sequence_id
);
1540 if (seq_id
== bp
->hwrm_intr_seq_id
)
1541 bp
->hwrm_intr_seq_id
= HWRM_SEQ_ID_INVALID
;
1543 netdev_err(bp
->dev
, "Invalid hwrm seq id %d\n", seq_id
);
1546 case CMPL_BASE_TYPE_HWRM_FWD_REQ
:
1547 vf_id
= le16_to_cpu(fwd_req_cmpl
->source_id
);
1549 if ((vf_id
< bp
->pf
.first_vf_id
) ||
1550 (vf_id
>= bp
->pf
.first_vf_id
+ bp
->pf
.active_vfs
)) {
1551 netdev_err(bp
->dev
, "Msg contains invalid VF id %x\n",
1556 set_bit(vf_id
- bp
->pf
.first_vf_id
, bp
->pf
.vf_event_bmap
);
1557 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT
, &bp
->sp_event
);
1558 schedule_work(&bp
->sp_task
);
1561 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT
:
1562 bnxt_async_event_process(bp
,
1563 (struct hwrm_async_event_cmpl
*)txcmp
);
1572 static irqreturn_t
bnxt_msix(int irq
, void *dev_instance
)
1574 struct bnxt_napi
*bnapi
= dev_instance
;
1575 struct bnxt
*bp
= bnapi
->bp
;
1576 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1577 u32 cons
= RING_CMP(cpr
->cp_raw_cons
);
1579 prefetch(&cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)]);
1580 napi_schedule(&bnapi
->napi
);
1584 static inline int bnxt_has_work(struct bnxt
*bp
, struct bnxt_cp_ring_info
*cpr
)
1586 u32 raw_cons
= cpr
->cp_raw_cons
;
1587 u16 cons
= RING_CMP(raw_cons
);
1588 struct tx_cmp
*txcmp
;
1590 txcmp
= &cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)];
1592 return TX_CMP_VALID(txcmp
, raw_cons
);
1595 static irqreturn_t
bnxt_inta(int irq
, void *dev_instance
)
1597 struct bnxt_napi
*bnapi
= dev_instance
;
1598 struct bnxt
*bp
= bnapi
->bp
;
1599 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1600 u32 cons
= RING_CMP(cpr
->cp_raw_cons
);
1603 prefetch(&cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)]);
1605 if (!bnxt_has_work(bp
, cpr
)) {
1606 int_status
= readl(bp
->bar0
+ BNXT_CAG_REG_LEGACY_INT_STATUS
);
1607 /* return if erroneous interrupt */
1608 if (!(int_status
& (0x10000 << cpr
->cp_ring_struct
.fw_ring_id
)))
1612 /* disable ring IRQ */
1613 BNXT_CP_DB_IRQ_DIS(cpr
->cp_doorbell
);
1615 /* Return here if interrupt is shared and is disabled. */
1616 if (unlikely(atomic_read(&bp
->intr_sem
) != 0))
1619 napi_schedule(&bnapi
->napi
);
1623 static int bnxt_poll_work(struct bnxt
*bp
, struct bnxt_napi
*bnapi
, int budget
)
1625 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1626 u32 raw_cons
= cpr
->cp_raw_cons
;
1630 bool rx_event
= false;
1631 bool agg_event
= false;
1632 struct tx_cmp
*txcmp
;
1637 cons
= RING_CMP(raw_cons
);
1638 txcmp
= &cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)];
1640 if (!TX_CMP_VALID(txcmp
, raw_cons
))
1643 /* The valid test of the entry must be done first before
1644 * reading any further.
1647 if (TX_CMP_TYPE(txcmp
) == CMP_TYPE_TX_L2_CMP
) {
1649 /* return full budget so NAPI will complete. */
1650 if (unlikely(tx_pkts
> bp
->tx_wake_thresh
))
1652 } else if ((TX_CMP_TYPE(txcmp
) & 0x30) == 0x10) {
1653 rc
= bnxt_rx_pkt(bp
, bnapi
, &raw_cons
, &agg_event
);
1654 if (likely(rc
>= 0))
1656 else if (rc
== -EBUSY
) /* partial completion */
1659 } else if (unlikely((TX_CMP_TYPE(txcmp
) ==
1660 CMPL_BASE_TYPE_HWRM_DONE
) ||
1661 (TX_CMP_TYPE(txcmp
) ==
1662 CMPL_BASE_TYPE_HWRM_FWD_REQ
) ||
1663 (TX_CMP_TYPE(txcmp
) ==
1664 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT
))) {
1665 bnxt_hwrm_handler(bp
, txcmp
);
1667 raw_cons
= NEXT_RAW_CMP(raw_cons
);
1669 if (rx_pkts
== budget
)
1673 cpr
->cp_raw_cons
= raw_cons
;
1674 /* ACK completion ring before freeing tx ring and producing new
1675 * buffers in rx/agg rings to prevent overflowing the completion
1678 BNXT_CP_DB(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
1681 bnxt_tx_int(bp
, bnapi
, tx_pkts
);
1684 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
1686 writel(DB_KEY_RX
| rxr
->rx_prod
, rxr
->rx_doorbell
);
1687 writel(DB_KEY_RX
| rxr
->rx_prod
, rxr
->rx_doorbell
);
1689 writel(DB_KEY_RX
| rxr
->rx_agg_prod
,
1690 rxr
->rx_agg_doorbell
);
1691 writel(DB_KEY_RX
| rxr
->rx_agg_prod
,
1692 rxr
->rx_agg_doorbell
);
1698 static int bnxt_poll_nitroa0(struct napi_struct
*napi
, int budget
)
1700 struct bnxt_napi
*bnapi
= container_of(napi
, struct bnxt_napi
, napi
);
1701 struct bnxt
*bp
= bnapi
->bp
;
1702 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1703 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
1704 struct tx_cmp
*txcmp
;
1705 struct rx_cmp_ext
*rxcmp1
;
1706 u32 cp_cons
, tmp_raw_cons
;
1707 u32 raw_cons
= cpr
->cp_raw_cons
;
1709 bool agg_event
= false;
1714 cp_cons
= RING_CMP(raw_cons
);
1715 txcmp
= &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
1717 if (!TX_CMP_VALID(txcmp
, raw_cons
))
1720 if ((TX_CMP_TYPE(txcmp
) & 0x30) == 0x10) {
1721 tmp_raw_cons
= NEXT_RAW_CMP(raw_cons
);
1722 cp_cons
= RING_CMP(tmp_raw_cons
);
1723 rxcmp1
= (struct rx_cmp_ext
*)
1724 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
1726 if (!RX_CMP_VALID(rxcmp1
, tmp_raw_cons
))
1729 /* force an error to recycle the buffer */
1730 rxcmp1
->rx_cmp_cfa_code_errors_v2
|=
1731 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR
);
1733 rc
= bnxt_rx_pkt(bp
, bnapi
, &raw_cons
, &agg_event
);
1734 if (likely(rc
== -EIO
))
1736 else if (rc
== -EBUSY
) /* partial completion */
1738 } else if (unlikely(TX_CMP_TYPE(txcmp
) ==
1739 CMPL_BASE_TYPE_HWRM_DONE
)) {
1740 bnxt_hwrm_handler(bp
, txcmp
);
1743 "Invalid completion received on special ring\n");
1745 raw_cons
= NEXT_RAW_CMP(raw_cons
);
1747 if (rx_pkts
== budget
)
1751 cpr
->cp_raw_cons
= raw_cons
;
1752 BNXT_CP_DB(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
1753 writel(DB_KEY_RX
| rxr
->rx_prod
, rxr
->rx_doorbell
);
1754 writel(DB_KEY_RX
| rxr
->rx_prod
, rxr
->rx_doorbell
);
1757 writel(DB_KEY_RX
| rxr
->rx_agg_prod
, rxr
->rx_agg_doorbell
);
1758 writel(DB_KEY_RX
| rxr
->rx_agg_prod
, rxr
->rx_agg_doorbell
);
1761 if (!bnxt_has_work(bp
, cpr
) && rx_pkts
< budget
) {
1762 napi_complete(napi
);
1763 BNXT_CP_DB_REARM(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
1768 static int bnxt_poll(struct napi_struct
*napi
, int budget
)
1770 struct bnxt_napi
*bnapi
= container_of(napi
, struct bnxt_napi
, napi
);
1771 struct bnxt
*bp
= bnapi
->bp
;
1772 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1776 work_done
+= bnxt_poll_work(bp
, bnapi
, budget
- work_done
);
1778 if (work_done
>= budget
)
1781 if (!bnxt_has_work(bp
, cpr
)) {
1782 if (napi_complete_done(napi
, work_done
))
1783 BNXT_CP_DB_REARM(cpr
->cp_doorbell
,
1792 static void bnxt_free_tx_skbs(struct bnxt
*bp
)
1795 struct pci_dev
*pdev
= bp
->pdev
;
1800 max_idx
= bp
->tx_nr_pages
* TX_DESC_CNT
;
1801 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
1802 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
1805 for (j
= 0; j
< max_idx
;) {
1806 struct bnxt_sw_tx_bd
*tx_buf
= &txr
->tx_buf_ring
[j
];
1807 struct sk_buff
*skb
= tx_buf
->skb
;
1817 if (tx_buf
->is_push
) {
1823 dma_unmap_single(&pdev
->dev
,
1824 dma_unmap_addr(tx_buf
, mapping
),
1828 last
= tx_buf
->nr_frags
;
1830 for (k
= 0; k
< last
; k
++, j
++) {
1831 int ring_idx
= j
& bp
->tx_ring_mask
;
1832 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[k
];
1834 tx_buf
= &txr
->tx_buf_ring
[ring_idx
];
1837 dma_unmap_addr(tx_buf
, mapping
),
1838 skb_frag_size(frag
), PCI_DMA_TODEVICE
);
1842 netdev_tx_reset_queue(netdev_get_tx_queue(bp
->dev
, i
));
1846 static void bnxt_free_rx_skbs(struct bnxt
*bp
)
1848 int i
, max_idx
, max_agg_idx
;
1849 struct pci_dev
*pdev
= bp
->pdev
;
1854 max_idx
= bp
->rx_nr_pages
* RX_DESC_CNT
;
1855 max_agg_idx
= bp
->rx_agg_nr_pages
* RX_DESC_CNT
;
1856 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
1857 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
1861 for (j
= 0; j
< MAX_TPA
; j
++) {
1862 struct bnxt_tpa_info
*tpa_info
=
1864 u8
*data
= tpa_info
->data
;
1871 dma_unmap_addr(tpa_info
, mapping
),
1872 bp
->rx_buf_use_size
,
1873 PCI_DMA_FROMDEVICE
);
1875 tpa_info
->data
= NULL
;
1881 for (j
= 0; j
< max_idx
; j
++) {
1882 struct bnxt_sw_rx_bd
*rx_buf
= &rxr
->rx_buf_ring
[j
];
1883 u8
*data
= rx_buf
->data
;
1888 dma_unmap_single(&pdev
->dev
,
1889 dma_unmap_addr(rx_buf
, mapping
),
1890 bp
->rx_buf_use_size
,
1891 PCI_DMA_FROMDEVICE
);
1893 rx_buf
->data
= NULL
;
1898 for (j
= 0; j
< max_agg_idx
; j
++) {
1899 struct bnxt_sw_rx_agg_bd
*rx_agg_buf
=
1900 &rxr
->rx_agg_ring
[j
];
1901 struct page
*page
= rx_agg_buf
->page
;
1906 dma_unmap_page(&pdev
->dev
,
1907 dma_unmap_addr(rx_agg_buf
, mapping
),
1908 BNXT_RX_PAGE_SIZE
, PCI_DMA_FROMDEVICE
);
1910 rx_agg_buf
->page
= NULL
;
1911 __clear_bit(j
, rxr
->rx_agg_bmap
);
1916 __free_page(rxr
->rx_page
);
1917 rxr
->rx_page
= NULL
;
1922 static void bnxt_free_skbs(struct bnxt
*bp
)
1924 bnxt_free_tx_skbs(bp
);
1925 bnxt_free_rx_skbs(bp
);
1928 static void bnxt_free_ring(struct bnxt
*bp
, struct bnxt_ring_struct
*ring
)
1930 struct pci_dev
*pdev
= bp
->pdev
;
1933 for (i
= 0; i
< ring
->nr_pages
; i
++) {
1934 if (!ring
->pg_arr
[i
])
1937 dma_free_coherent(&pdev
->dev
, ring
->page_size
,
1938 ring
->pg_arr
[i
], ring
->dma_arr
[i
]);
1940 ring
->pg_arr
[i
] = NULL
;
1943 dma_free_coherent(&pdev
->dev
, ring
->nr_pages
* 8,
1944 ring
->pg_tbl
, ring
->pg_tbl_map
);
1945 ring
->pg_tbl
= NULL
;
1947 if (ring
->vmem_size
&& *ring
->vmem
) {
1953 static int bnxt_alloc_ring(struct bnxt
*bp
, struct bnxt_ring_struct
*ring
)
1956 struct pci_dev
*pdev
= bp
->pdev
;
1958 if (ring
->nr_pages
> 1) {
1959 ring
->pg_tbl
= dma_alloc_coherent(&pdev
->dev
,
1967 for (i
= 0; i
< ring
->nr_pages
; i
++) {
1968 ring
->pg_arr
[i
] = dma_alloc_coherent(&pdev
->dev
,
1972 if (!ring
->pg_arr
[i
])
1975 if (ring
->nr_pages
> 1)
1976 ring
->pg_tbl
[i
] = cpu_to_le64(ring
->dma_arr
[i
]);
1979 if (ring
->vmem_size
) {
1980 *ring
->vmem
= vzalloc(ring
->vmem_size
);
1987 static void bnxt_free_rx_rings(struct bnxt
*bp
)
1994 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
1995 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
1996 struct bnxt_ring_struct
*ring
;
2001 kfree(rxr
->rx_agg_bmap
);
2002 rxr
->rx_agg_bmap
= NULL
;
2004 ring
= &rxr
->rx_ring_struct
;
2005 bnxt_free_ring(bp
, ring
);
2007 ring
= &rxr
->rx_agg_ring_struct
;
2008 bnxt_free_ring(bp
, ring
);
2012 static int bnxt_alloc_rx_rings(struct bnxt
*bp
)
2014 int i
, rc
, agg_rings
= 0, tpa_rings
= 0;
2019 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
)
2022 if (bp
->flags
& BNXT_FLAG_TPA
)
2025 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
2026 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
2027 struct bnxt_ring_struct
*ring
;
2029 ring
= &rxr
->rx_ring_struct
;
2031 rc
= bnxt_alloc_ring(bp
, ring
);
2038 ring
= &rxr
->rx_agg_ring_struct
;
2039 rc
= bnxt_alloc_ring(bp
, ring
);
2043 rxr
->rx_agg_bmap_size
= bp
->rx_agg_ring_mask
+ 1;
2044 mem_size
= rxr
->rx_agg_bmap_size
/ 8;
2045 rxr
->rx_agg_bmap
= kzalloc(mem_size
, GFP_KERNEL
);
2046 if (!rxr
->rx_agg_bmap
)
2050 rxr
->rx_tpa
= kcalloc(MAX_TPA
,
2051 sizeof(struct bnxt_tpa_info
),
2061 static void bnxt_free_tx_rings(struct bnxt
*bp
)
2064 struct pci_dev
*pdev
= bp
->pdev
;
2069 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
2070 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
2071 struct bnxt_ring_struct
*ring
;
2074 dma_free_coherent(&pdev
->dev
, bp
->tx_push_size
,
2075 txr
->tx_push
, txr
->tx_push_mapping
);
2076 txr
->tx_push
= NULL
;
2079 ring
= &txr
->tx_ring_struct
;
2081 bnxt_free_ring(bp
, ring
);
2085 static int bnxt_alloc_tx_rings(struct bnxt
*bp
)
2088 struct pci_dev
*pdev
= bp
->pdev
;
2090 bp
->tx_push_size
= 0;
2091 if (bp
->tx_push_thresh
) {
2094 push_size
= L1_CACHE_ALIGN(sizeof(struct tx_push_bd
) +
2095 bp
->tx_push_thresh
);
2097 if (push_size
> 256) {
2099 bp
->tx_push_thresh
= 0;
2102 bp
->tx_push_size
= push_size
;
2105 for (i
= 0, j
= 0; i
< bp
->tx_nr_rings
; i
++) {
2106 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
2107 struct bnxt_ring_struct
*ring
;
2109 ring
= &txr
->tx_ring_struct
;
2111 rc
= bnxt_alloc_ring(bp
, ring
);
2115 if (bp
->tx_push_size
) {
2118 /* One pre-allocated DMA buffer to backup
2121 txr
->tx_push
= dma_alloc_coherent(&pdev
->dev
,
2123 &txr
->tx_push_mapping
,
2129 mapping
= txr
->tx_push_mapping
+
2130 sizeof(struct tx_push_bd
);
2131 txr
->data_mapping
= cpu_to_le64(mapping
);
2133 memset(txr
->tx_push
, 0, sizeof(struct tx_push_bd
));
2135 ring
->queue_id
= bp
->q_info
[j
].queue_id
;
2136 if (i
% bp
->tx_nr_rings_per_tc
== (bp
->tx_nr_rings_per_tc
- 1))
2142 static void bnxt_free_cp_rings(struct bnxt
*bp
)
2149 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2150 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2151 struct bnxt_cp_ring_info
*cpr
;
2152 struct bnxt_ring_struct
*ring
;
2157 cpr
= &bnapi
->cp_ring
;
2158 ring
= &cpr
->cp_ring_struct
;
2160 bnxt_free_ring(bp
, ring
);
2164 static int bnxt_alloc_cp_rings(struct bnxt
*bp
)
2168 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2169 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2170 struct bnxt_cp_ring_info
*cpr
;
2171 struct bnxt_ring_struct
*ring
;
2176 cpr
= &bnapi
->cp_ring
;
2177 ring
= &cpr
->cp_ring_struct
;
2179 rc
= bnxt_alloc_ring(bp
, ring
);
2186 static void bnxt_init_ring_struct(struct bnxt
*bp
)
2190 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2191 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2192 struct bnxt_cp_ring_info
*cpr
;
2193 struct bnxt_rx_ring_info
*rxr
;
2194 struct bnxt_tx_ring_info
*txr
;
2195 struct bnxt_ring_struct
*ring
;
2200 cpr
= &bnapi
->cp_ring
;
2201 ring
= &cpr
->cp_ring_struct
;
2202 ring
->nr_pages
= bp
->cp_nr_pages
;
2203 ring
->page_size
= HW_CMPD_RING_SIZE
;
2204 ring
->pg_arr
= (void **)cpr
->cp_desc_ring
;
2205 ring
->dma_arr
= cpr
->cp_desc_mapping
;
2206 ring
->vmem_size
= 0;
2208 rxr
= bnapi
->rx_ring
;
2212 ring
= &rxr
->rx_ring_struct
;
2213 ring
->nr_pages
= bp
->rx_nr_pages
;
2214 ring
->page_size
= HW_RXBD_RING_SIZE
;
2215 ring
->pg_arr
= (void **)rxr
->rx_desc_ring
;
2216 ring
->dma_arr
= rxr
->rx_desc_mapping
;
2217 ring
->vmem_size
= SW_RXBD_RING_SIZE
* bp
->rx_nr_pages
;
2218 ring
->vmem
= (void **)&rxr
->rx_buf_ring
;
2220 ring
= &rxr
->rx_agg_ring_struct
;
2221 ring
->nr_pages
= bp
->rx_agg_nr_pages
;
2222 ring
->page_size
= HW_RXBD_RING_SIZE
;
2223 ring
->pg_arr
= (void **)rxr
->rx_agg_desc_ring
;
2224 ring
->dma_arr
= rxr
->rx_agg_desc_mapping
;
2225 ring
->vmem_size
= SW_RXBD_AGG_RING_SIZE
* bp
->rx_agg_nr_pages
;
2226 ring
->vmem
= (void **)&rxr
->rx_agg_ring
;
2229 txr
= bnapi
->tx_ring
;
2233 ring
= &txr
->tx_ring_struct
;
2234 ring
->nr_pages
= bp
->tx_nr_pages
;
2235 ring
->page_size
= HW_RXBD_RING_SIZE
;
2236 ring
->pg_arr
= (void **)txr
->tx_desc_ring
;
2237 ring
->dma_arr
= txr
->tx_desc_mapping
;
2238 ring
->vmem_size
= SW_TXBD_RING_SIZE
* bp
->tx_nr_pages
;
2239 ring
->vmem
= (void **)&txr
->tx_buf_ring
;
2243 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct
*ring
, u32 type
)
2247 struct rx_bd
**rx_buf_ring
;
2249 rx_buf_ring
= (struct rx_bd
**)ring
->pg_arr
;
2250 for (i
= 0, prod
= 0; i
< ring
->nr_pages
; i
++) {
2254 rxbd
= rx_buf_ring
[i
];
2258 for (j
= 0; j
< RX_DESC_CNT
; j
++, rxbd
++, prod
++) {
2259 rxbd
->rx_bd_len_flags_type
= cpu_to_le32(type
);
2260 rxbd
->rx_bd_opaque
= prod
;
2265 static int bnxt_init_one_rx_ring(struct bnxt
*bp
, int ring_nr
)
2267 struct net_device
*dev
= bp
->dev
;
2268 struct bnxt_rx_ring_info
*rxr
;
2269 struct bnxt_ring_struct
*ring
;
2273 type
= (bp
->rx_buf_use_size
<< RX_BD_LEN_SHIFT
) |
2274 RX_BD_TYPE_RX_PACKET_BD
| RX_BD_FLAGS_EOP
;
2276 if (NET_IP_ALIGN
== 2)
2277 type
|= RX_BD_FLAGS_SOP
;
2279 rxr
= &bp
->rx_ring
[ring_nr
];
2280 ring
= &rxr
->rx_ring_struct
;
2281 bnxt_init_rxbd_pages(ring
, type
);
2283 prod
= rxr
->rx_prod
;
2284 for (i
= 0; i
< bp
->rx_ring_size
; i
++) {
2285 if (bnxt_alloc_rx_data(bp
, rxr
, prod
, GFP_KERNEL
) != 0) {
2286 netdev_warn(dev
, "init'ed rx ring %d with %d/%d skbs only\n",
2287 ring_nr
, i
, bp
->rx_ring_size
);
2290 prod
= NEXT_RX(prod
);
2292 rxr
->rx_prod
= prod
;
2293 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
2295 ring
= &rxr
->rx_agg_ring_struct
;
2296 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
2298 if (!(bp
->flags
& BNXT_FLAG_AGG_RINGS
))
2301 type
= ((u32
)BNXT_RX_PAGE_SIZE
<< RX_BD_LEN_SHIFT
) |
2302 RX_BD_TYPE_RX_AGG_BD
| RX_BD_FLAGS_SOP
;
2304 bnxt_init_rxbd_pages(ring
, type
);
2306 prod
= rxr
->rx_agg_prod
;
2307 for (i
= 0; i
< bp
->rx_agg_ring_size
; i
++) {
2308 if (bnxt_alloc_rx_page(bp
, rxr
, prod
, GFP_KERNEL
) != 0) {
2309 netdev_warn(dev
, "init'ed rx ring %d with %d/%d pages only\n",
2310 ring_nr
, i
, bp
->rx_ring_size
);
2313 prod
= NEXT_RX_AGG(prod
);
2315 rxr
->rx_agg_prod
= prod
;
2317 if (bp
->flags
& BNXT_FLAG_TPA
) {
2322 for (i
= 0; i
< MAX_TPA
; i
++) {
2323 data
= __bnxt_alloc_rx_data(bp
, &mapping
,
2328 rxr
->rx_tpa
[i
].data
= data
;
2329 rxr
->rx_tpa
[i
].mapping
= mapping
;
2332 netdev_err(bp
->dev
, "No resource allocated for LRO/GRO\n");
2340 static int bnxt_init_rx_rings(struct bnxt
*bp
)
2344 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
2345 rc
= bnxt_init_one_rx_ring(bp
, i
);
2353 static int bnxt_init_tx_rings(struct bnxt
*bp
)
2357 bp
->tx_wake_thresh
= max_t(int, bp
->tx_ring_size
/ 2,
2360 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
2361 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
2362 struct bnxt_ring_struct
*ring
= &txr
->tx_ring_struct
;
2364 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
2370 static void bnxt_free_ring_grps(struct bnxt
*bp
)
2372 kfree(bp
->grp_info
);
2373 bp
->grp_info
= NULL
;
2376 static int bnxt_init_ring_grps(struct bnxt
*bp
, bool irq_re_init
)
2381 bp
->grp_info
= kcalloc(bp
->cp_nr_rings
,
2382 sizeof(struct bnxt_ring_grp_info
),
2387 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2389 bp
->grp_info
[i
].fw_stats_ctx
= INVALID_HW_RING_ID
;
2390 bp
->grp_info
[i
].fw_grp_id
= INVALID_HW_RING_ID
;
2391 bp
->grp_info
[i
].rx_fw_ring_id
= INVALID_HW_RING_ID
;
2392 bp
->grp_info
[i
].agg_fw_ring_id
= INVALID_HW_RING_ID
;
2393 bp
->grp_info
[i
].cp_fw_ring_id
= INVALID_HW_RING_ID
;
2398 static void bnxt_free_vnics(struct bnxt
*bp
)
2400 kfree(bp
->vnic_info
);
2401 bp
->vnic_info
= NULL
;
2405 static int bnxt_alloc_vnics(struct bnxt
*bp
)
2409 #ifdef CONFIG_RFS_ACCEL
2410 if (bp
->flags
& BNXT_FLAG_RFS
)
2411 num_vnics
+= bp
->rx_nr_rings
;
2414 if (BNXT_CHIP_TYPE_NITRO_A0(bp
))
2417 bp
->vnic_info
= kcalloc(num_vnics
, sizeof(struct bnxt_vnic_info
),
2422 bp
->nr_vnics
= num_vnics
;
2426 static void bnxt_init_vnics(struct bnxt
*bp
)
2430 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
2431 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[i
];
2433 vnic
->fw_vnic_id
= INVALID_HW_RING_ID
;
2434 vnic
->fw_rss_cos_lb_ctx
[0] = INVALID_HW_RING_ID
;
2435 vnic
->fw_rss_cos_lb_ctx
[1] = INVALID_HW_RING_ID
;
2436 vnic
->fw_l2_ctx_id
= INVALID_HW_RING_ID
;
2438 if (bp
->vnic_info
[i
].rss_hash_key
) {
2440 prandom_bytes(vnic
->rss_hash_key
,
2443 memcpy(vnic
->rss_hash_key
,
2444 bp
->vnic_info
[0].rss_hash_key
,
2450 static int bnxt_calc_nr_ring_pages(u32 ring_size
, int desc_per_pg
)
2454 pages
= ring_size
/ desc_per_pg
;
2461 while (pages
& (pages
- 1))
2467 static void bnxt_set_tpa_flags(struct bnxt
*bp
)
2469 bp
->flags
&= ~BNXT_FLAG_TPA
;
2470 if (bp
->flags
& BNXT_FLAG_NO_AGG_RINGS
)
2472 if (bp
->dev
->features
& NETIF_F_LRO
)
2473 bp
->flags
|= BNXT_FLAG_LRO
;
2474 if (bp
->dev
->features
& NETIF_F_GRO
)
2475 bp
->flags
|= BNXT_FLAG_GRO
;
2478 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2481 void bnxt_set_ring_params(struct bnxt
*bp
)
2483 u32 ring_size
, rx_size
, rx_space
;
2484 u32 agg_factor
= 0, agg_ring_size
= 0;
2486 /* 8 for CRC and VLAN */
2487 rx_size
= SKB_DATA_ALIGN(bp
->dev
->mtu
+ ETH_HLEN
+ NET_IP_ALIGN
+ 8);
2489 rx_space
= rx_size
+ NET_SKB_PAD
+
2490 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
2492 bp
->rx_copy_thresh
= BNXT_RX_COPY_THRESH
;
2493 ring_size
= bp
->rx_ring_size
;
2494 bp
->rx_agg_ring_size
= 0;
2495 bp
->rx_agg_nr_pages
= 0;
2497 if (bp
->flags
& BNXT_FLAG_TPA
)
2498 agg_factor
= min_t(u32
, 4, 65536 / BNXT_RX_PAGE_SIZE
);
2500 bp
->flags
&= ~BNXT_FLAG_JUMBO
;
2501 if (rx_space
> PAGE_SIZE
&& !(bp
->flags
& BNXT_FLAG_NO_AGG_RINGS
)) {
2504 bp
->flags
|= BNXT_FLAG_JUMBO
;
2505 jumbo_factor
= PAGE_ALIGN(bp
->dev
->mtu
- 40) >> PAGE_SHIFT
;
2506 if (jumbo_factor
> agg_factor
)
2507 agg_factor
= jumbo_factor
;
2509 agg_ring_size
= ring_size
* agg_factor
;
2511 if (agg_ring_size
) {
2512 bp
->rx_agg_nr_pages
= bnxt_calc_nr_ring_pages(agg_ring_size
,
2514 if (bp
->rx_agg_nr_pages
> MAX_RX_AGG_PAGES
) {
2515 u32 tmp
= agg_ring_size
;
2517 bp
->rx_agg_nr_pages
= MAX_RX_AGG_PAGES
;
2518 agg_ring_size
= MAX_RX_AGG_PAGES
* RX_DESC_CNT
- 1;
2519 netdev_warn(bp
->dev
, "rx agg ring size %d reduced to %d.\n",
2520 tmp
, agg_ring_size
);
2522 bp
->rx_agg_ring_size
= agg_ring_size
;
2523 bp
->rx_agg_ring_mask
= (bp
->rx_agg_nr_pages
* RX_DESC_CNT
) - 1;
2524 rx_size
= SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH
+ NET_IP_ALIGN
);
2525 rx_space
= rx_size
+ NET_SKB_PAD
+
2526 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
2529 bp
->rx_buf_use_size
= rx_size
;
2530 bp
->rx_buf_size
= rx_space
;
2532 bp
->rx_nr_pages
= bnxt_calc_nr_ring_pages(ring_size
, RX_DESC_CNT
);
2533 bp
->rx_ring_mask
= (bp
->rx_nr_pages
* RX_DESC_CNT
) - 1;
2535 ring_size
= bp
->tx_ring_size
;
2536 bp
->tx_nr_pages
= bnxt_calc_nr_ring_pages(ring_size
, TX_DESC_CNT
);
2537 bp
->tx_ring_mask
= (bp
->tx_nr_pages
* TX_DESC_CNT
) - 1;
2539 ring_size
= bp
->rx_ring_size
* (2 + agg_factor
) + bp
->tx_ring_size
;
2540 bp
->cp_ring_size
= ring_size
;
2542 bp
->cp_nr_pages
= bnxt_calc_nr_ring_pages(ring_size
, CP_DESC_CNT
);
2543 if (bp
->cp_nr_pages
> MAX_CP_PAGES
) {
2544 bp
->cp_nr_pages
= MAX_CP_PAGES
;
2545 bp
->cp_ring_size
= MAX_CP_PAGES
* CP_DESC_CNT
- 1;
2546 netdev_warn(bp
->dev
, "completion ring size %d reduced to %d.\n",
2547 ring_size
, bp
->cp_ring_size
);
2549 bp
->cp_bit
= bp
->cp_nr_pages
* CP_DESC_CNT
;
2550 bp
->cp_ring_mask
= bp
->cp_bit
- 1;
2553 static void bnxt_free_vnic_attributes(struct bnxt
*bp
)
2556 struct bnxt_vnic_info
*vnic
;
2557 struct pci_dev
*pdev
= bp
->pdev
;
2562 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
2563 vnic
= &bp
->vnic_info
[i
];
2565 kfree(vnic
->fw_grp_ids
);
2566 vnic
->fw_grp_ids
= NULL
;
2568 kfree(vnic
->uc_list
);
2569 vnic
->uc_list
= NULL
;
2571 if (vnic
->mc_list
) {
2572 dma_free_coherent(&pdev
->dev
, vnic
->mc_list_size
,
2573 vnic
->mc_list
, vnic
->mc_list_mapping
);
2574 vnic
->mc_list
= NULL
;
2577 if (vnic
->rss_table
) {
2578 dma_free_coherent(&pdev
->dev
, PAGE_SIZE
,
2580 vnic
->rss_table_dma_addr
);
2581 vnic
->rss_table
= NULL
;
2584 vnic
->rss_hash_key
= NULL
;
2589 static int bnxt_alloc_vnic_attributes(struct bnxt
*bp
)
2591 int i
, rc
= 0, size
;
2592 struct bnxt_vnic_info
*vnic
;
2593 struct pci_dev
*pdev
= bp
->pdev
;
2596 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
2597 vnic
= &bp
->vnic_info
[i
];
2599 if (vnic
->flags
& BNXT_VNIC_UCAST_FLAG
) {
2600 int mem_size
= (BNXT_MAX_UC_ADDRS
- 1) * ETH_ALEN
;
2603 vnic
->uc_list
= kmalloc(mem_size
, GFP_KERNEL
);
2604 if (!vnic
->uc_list
) {
2611 if (vnic
->flags
& BNXT_VNIC_MCAST_FLAG
) {
2612 vnic
->mc_list_size
= BNXT_MAX_MC_ADDRS
* ETH_ALEN
;
2614 dma_alloc_coherent(&pdev
->dev
,
2616 &vnic
->mc_list_mapping
,
2618 if (!vnic
->mc_list
) {
2624 if (vnic
->flags
& BNXT_VNIC_RSS_FLAG
)
2625 max_rings
= bp
->rx_nr_rings
;
2629 vnic
->fw_grp_ids
= kcalloc(max_rings
, sizeof(u16
), GFP_KERNEL
);
2630 if (!vnic
->fw_grp_ids
) {
2635 if ((bp
->flags
& BNXT_FLAG_NEW_RSS_CAP
) &&
2636 !(vnic
->flags
& BNXT_VNIC_RSS_FLAG
))
2639 /* Allocate rss table and hash key */
2640 vnic
->rss_table
= dma_alloc_coherent(&pdev
->dev
, PAGE_SIZE
,
2641 &vnic
->rss_table_dma_addr
,
2643 if (!vnic
->rss_table
) {
2648 size
= L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE
* sizeof(u16
));
2650 vnic
->rss_hash_key
= ((void *)vnic
->rss_table
) + size
;
2651 vnic
->rss_hash_key_dma_addr
= vnic
->rss_table_dma_addr
+ size
;
2659 static void bnxt_free_hwrm_resources(struct bnxt
*bp
)
2661 struct pci_dev
*pdev
= bp
->pdev
;
2663 dma_free_coherent(&pdev
->dev
, PAGE_SIZE
, bp
->hwrm_cmd_resp_addr
,
2664 bp
->hwrm_cmd_resp_dma_addr
);
2666 bp
->hwrm_cmd_resp_addr
= NULL
;
2667 if (bp
->hwrm_dbg_resp_addr
) {
2668 dma_free_coherent(&pdev
->dev
, HWRM_DBG_REG_BUF_SIZE
,
2669 bp
->hwrm_dbg_resp_addr
,
2670 bp
->hwrm_dbg_resp_dma_addr
);
2672 bp
->hwrm_dbg_resp_addr
= NULL
;
2676 static int bnxt_alloc_hwrm_resources(struct bnxt
*bp
)
2678 struct pci_dev
*pdev
= bp
->pdev
;
2680 bp
->hwrm_cmd_resp_addr
= dma_alloc_coherent(&pdev
->dev
, PAGE_SIZE
,
2681 &bp
->hwrm_cmd_resp_dma_addr
,
2683 if (!bp
->hwrm_cmd_resp_addr
)
2685 bp
->hwrm_dbg_resp_addr
= dma_alloc_coherent(&pdev
->dev
,
2686 HWRM_DBG_REG_BUF_SIZE
,
2687 &bp
->hwrm_dbg_resp_dma_addr
,
2689 if (!bp
->hwrm_dbg_resp_addr
)
2690 netdev_warn(bp
->dev
, "fail to alloc debug register dma mem\n");
2695 static void bnxt_free_stats(struct bnxt
*bp
)
2698 struct pci_dev
*pdev
= bp
->pdev
;
2700 if (bp
->hw_rx_port_stats
) {
2701 dma_free_coherent(&pdev
->dev
, bp
->hw_port_stats_size
,
2702 bp
->hw_rx_port_stats
,
2703 bp
->hw_rx_port_stats_map
);
2704 bp
->hw_rx_port_stats
= NULL
;
2705 bp
->flags
&= ~BNXT_FLAG_PORT_STATS
;
2711 size
= sizeof(struct ctx_hw_stats
);
2713 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2714 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2715 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
2717 if (cpr
->hw_stats
) {
2718 dma_free_coherent(&pdev
->dev
, size
, cpr
->hw_stats
,
2720 cpr
->hw_stats
= NULL
;
2725 static int bnxt_alloc_stats(struct bnxt
*bp
)
2728 struct pci_dev
*pdev
= bp
->pdev
;
2730 size
= sizeof(struct ctx_hw_stats
);
2732 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2733 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2734 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
2736 cpr
->hw_stats
= dma_alloc_coherent(&pdev
->dev
, size
,
2742 cpr
->hw_stats_ctx_id
= INVALID_STATS_CTX_ID
;
2745 if (BNXT_PF(bp
) && bp
->chip_num
!= CHIP_NUM_58700
) {
2746 bp
->hw_port_stats_size
= sizeof(struct rx_port_stats
) +
2747 sizeof(struct tx_port_stats
) + 1024;
2749 bp
->hw_rx_port_stats
=
2750 dma_alloc_coherent(&pdev
->dev
, bp
->hw_port_stats_size
,
2751 &bp
->hw_rx_port_stats_map
,
2753 if (!bp
->hw_rx_port_stats
)
2756 bp
->hw_tx_port_stats
= (void *)(bp
->hw_rx_port_stats
+ 1) +
2758 bp
->hw_tx_port_stats_map
= bp
->hw_rx_port_stats_map
+
2759 sizeof(struct rx_port_stats
) + 512;
2760 bp
->flags
|= BNXT_FLAG_PORT_STATS
;
2765 static void bnxt_clear_ring_indices(struct bnxt
*bp
)
2772 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2773 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2774 struct bnxt_cp_ring_info
*cpr
;
2775 struct bnxt_rx_ring_info
*rxr
;
2776 struct bnxt_tx_ring_info
*txr
;
2781 cpr
= &bnapi
->cp_ring
;
2782 cpr
->cp_raw_cons
= 0;
2784 txr
= bnapi
->tx_ring
;
2790 rxr
= bnapi
->rx_ring
;
2793 rxr
->rx_agg_prod
= 0;
2794 rxr
->rx_sw_agg_prod
= 0;
2795 rxr
->rx_next_cons
= 0;
2800 static void bnxt_free_ntp_fltrs(struct bnxt
*bp
, bool irq_reinit
)
2802 #ifdef CONFIG_RFS_ACCEL
2805 /* Under rtnl_lock and all our NAPIs have been disabled. It's
2806 * safe to delete the hash table.
2808 for (i
= 0; i
< BNXT_NTP_FLTR_HASH_SIZE
; i
++) {
2809 struct hlist_head
*head
;
2810 struct hlist_node
*tmp
;
2811 struct bnxt_ntuple_filter
*fltr
;
2813 head
= &bp
->ntp_fltr_hash_tbl
[i
];
2814 hlist_for_each_entry_safe(fltr
, tmp
, head
, hash
) {
2815 hlist_del(&fltr
->hash
);
2820 kfree(bp
->ntp_fltr_bmap
);
2821 bp
->ntp_fltr_bmap
= NULL
;
2823 bp
->ntp_fltr_count
= 0;
2827 static int bnxt_alloc_ntp_fltrs(struct bnxt
*bp
)
2829 #ifdef CONFIG_RFS_ACCEL
2832 if (!(bp
->flags
& BNXT_FLAG_RFS
))
2835 for (i
= 0; i
< BNXT_NTP_FLTR_HASH_SIZE
; i
++)
2836 INIT_HLIST_HEAD(&bp
->ntp_fltr_hash_tbl
[i
]);
2838 bp
->ntp_fltr_count
= 0;
2839 bp
->ntp_fltr_bmap
= kzalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR
),
2842 if (!bp
->ntp_fltr_bmap
)
2851 static void bnxt_free_mem(struct bnxt
*bp
, bool irq_re_init
)
2853 bnxt_free_vnic_attributes(bp
);
2854 bnxt_free_tx_rings(bp
);
2855 bnxt_free_rx_rings(bp
);
2856 bnxt_free_cp_rings(bp
);
2857 bnxt_free_ntp_fltrs(bp
, irq_re_init
);
2859 bnxt_free_stats(bp
);
2860 bnxt_free_ring_grps(bp
);
2861 bnxt_free_vnics(bp
);
2869 bnxt_clear_ring_indices(bp
);
2873 static int bnxt_alloc_mem(struct bnxt
*bp
, bool irq_re_init
)
2875 int i
, j
, rc
, size
, arr_size
;
2879 /* Allocate bnapi mem pointer array and mem block for
2882 arr_size
= L1_CACHE_ALIGN(sizeof(struct bnxt_napi
*) *
2884 size
= L1_CACHE_ALIGN(sizeof(struct bnxt_napi
));
2885 bnapi
= kzalloc(arr_size
+ size
* bp
->cp_nr_rings
, GFP_KERNEL
);
2891 for (i
= 0; i
< bp
->cp_nr_rings
; i
++, bnapi
+= size
) {
2892 bp
->bnapi
[i
] = bnapi
;
2893 bp
->bnapi
[i
]->index
= i
;
2894 bp
->bnapi
[i
]->bp
= bp
;
2897 bp
->rx_ring
= kcalloc(bp
->rx_nr_rings
,
2898 sizeof(struct bnxt_rx_ring_info
),
2903 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
2904 bp
->rx_ring
[i
].bnapi
= bp
->bnapi
[i
];
2905 bp
->bnapi
[i
]->rx_ring
= &bp
->rx_ring
[i
];
2908 bp
->tx_ring
= kcalloc(bp
->tx_nr_rings
,
2909 sizeof(struct bnxt_tx_ring_info
),
2914 if (bp
->flags
& BNXT_FLAG_SHARED_RINGS
)
2917 j
= bp
->rx_nr_rings
;
2919 for (i
= 0; i
< bp
->tx_nr_rings
; i
++, j
++) {
2920 bp
->tx_ring
[i
].bnapi
= bp
->bnapi
[j
];
2921 bp
->bnapi
[j
]->tx_ring
= &bp
->tx_ring
[i
];
2924 rc
= bnxt_alloc_stats(bp
);
2928 rc
= bnxt_alloc_ntp_fltrs(bp
);
2932 rc
= bnxt_alloc_vnics(bp
);
2937 bnxt_init_ring_struct(bp
);
2939 rc
= bnxt_alloc_rx_rings(bp
);
2943 rc
= bnxt_alloc_tx_rings(bp
);
2947 rc
= bnxt_alloc_cp_rings(bp
);
2951 bp
->vnic_info
[0].flags
|= BNXT_VNIC_RSS_FLAG
| BNXT_VNIC_MCAST_FLAG
|
2952 BNXT_VNIC_UCAST_FLAG
;
2953 rc
= bnxt_alloc_vnic_attributes(bp
);
2959 bnxt_free_mem(bp
, true);
2963 static void bnxt_disable_int(struct bnxt
*bp
)
2970 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2971 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2972 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
2974 BNXT_CP_DB(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
2978 static void bnxt_disable_int_sync(struct bnxt
*bp
)
2982 atomic_inc(&bp
->intr_sem
);
2984 bnxt_disable_int(bp
);
2985 for (i
= 0; i
< bp
->cp_nr_rings
; i
++)
2986 synchronize_irq(bp
->irq_tbl
[i
].vector
);
2989 static void bnxt_enable_int(struct bnxt
*bp
)
2993 atomic_set(&bp
->intr_sem
, 0);
2994 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2995 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2996 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
2998 BNXT_CP_DB_REARM(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
3002 void bnxt_hwrm_cmd_hdr_init(struct bnxt
*bp
, void *request
, u16 req_type
,
3003 u16 cmpl_ring
, u16 target_id
)
3005 struct input
*req
= request
;
3007 req
->req_type
= cpu_to_le16(req_type
);
3008 req
->cmpl_ring
= cpu_to_le16(cmpl_ring
);
3009 req
->target_id
= cpu_to_le16(target_id
);
3010 req
->resp_addr
= cpu_to_le64(bp
->hwrm_cmd_resp_dma_addr
);
3013 static int bnxt_hwrm_do_send_msg(struct bnxt
*bp
, void *msg
, u32 msg_len
,
3014 int timeout
, bool silent
)
3016 int i
, intr_process
, rc
, tmo_count
;
3017 struct input
*req
= msg
;
3019 __le32
*resp_len
, *valid
;
3020 u16 cp_ring_id
, len
= 0;
3021 struct hwrm_err_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3023 req
->seq_id
= cpu_to_le16(bp
->hwrm_cmd_seq
++);
3024 memset(resp
, 0, PAGE_SIZE
);
3025 cp_ring_id
= le16_to_cpu(req
->cmpl_ring
);
3026 intr_process
= (cp_ring_id
== INVALID_HW_RING_ID
) ? 0 : 1;
3028 /* Write request msg to hwrm channel */
3029 __iowrite32_copy(bp
->bar0
, data
, msg_len
/ 4);
3031 for (i
= msg_len
; i
< BNXT_HWRM_MAX_REQ_LEN
; i
+= 4)
3032 writel(0, bp
->bar0
+ i
);
3034 /* currently supports only one outstanding message */
3036 bp
->hwrm_intr_seq_id
= le16_to_cpu(req
->seq_id
);
3038 /* Ring channel doorbell */
3039 writel(1, bp
->bar0
+ 0x100);
3042 timeout
= DFLT_HWRM_CMD_TIMEOUT
;
3045 tmo_count
= timeout
* 40;
3047 /* Wait until hwrm response cmpl interrupt is processed */
3048 while (bp
->hwrm_intr_seq_id
!= HWRM_SEQ_ID_INVALID
&&
3050 usleep_range(25, 40);
3053 if (bp
->hwrm_intr_seq_id
!= HWRM_SEQ_ID_INVALID
) {
3054 netdev_err(bp
->dev
, "Resp cmpl intr err msg: 0x%x\n",
3055 le16_to_cpu(req
->req_type
));
3059 /* Check if response len is updated */
3060 resp_len
= bp
->hwrm_cmd_resp_addr
+ HWRM_RESP_LEN_OFFSET
;
3061 for (i
= 0; i
< tmo_count
; i
++) {
3062 len
= (le32_to_cpu(*resp_len
) & HWRM_RESP_LEN_MASK
) >>
3066 usleep_range(25, 40);
3069 if (i
>= tmo_count
) {
3070 netdev_err(bp
->dev
, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
3071 timeout
, le16_to_cpu(req
->req_type
),
3072 le16_to_cpu(req
->seq_id
), len
);
3076 /* Last word of resp contains valid bit */
3077 valid
= bp
->hwrm_cmd_resp_addr
+ len
- 4;
3078 for (i
= 0; i
< 5; i
++) {
3079 if (le32_to_cpu(*valid
) & HWRM_RESP_VALID_MASK
)
3085 netdev_err(bp
->dev
, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
3086 timeout
, le16_to_cpu(req
->req_type
),
3087 le16_to_cpu(req
->seq_id
), len
, *valid
);
3092 rc
= le16_to_cpu(resp
->error_code
);
3094 netdev_err(bp
->dev
, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
3095 le16_to_cpu(resp
->req_type
),
3096 le16_to_cpu(resp
->seq_id
), rc
);
3100 int _hwrm_send_message(struct bnxt
*bp
, void *msg
, u32 msg_len
, int timeout
)
3102 return bnxt_hwrm_do_send_msg(bp
, msg
, msg_len
, timeout
, false);
3105 int hwrm_send_message(struct bnxt
*bp
, void *msg
, u32 msg_len
, int timeout
)
3109 mutex_lock(&bp
->hwrm_cmd_lock
);
3110 rc
= _hwrm_send_message(bp
, msg
, msg_len
, timeout
);
3111 mutex_unlock(&bp
->hwrm_cmd_lock
);
3115 int hwrm_send_message_silent(struct bnxt
*bp
, void *msg
, u32 msg_len
,
3120 mutex_lock(&bp
->hwrm_cmd_lock
);
3121 rc
= bnxt_hwrm_do_send_msg(bp
, msg
, msg_len
, timeout
, true);
3122 mutex_unlock(&bp
->hwrm_cmd_lock
);
3126 int bnxt_hwrm_func_rgtr_async_events(struct bnxt
*bp
, unsigned long *bmap
,
3129 struct hwrm_func_drv_rgtr_input req
= {0};
3130 DECLARE_BITMAP(async_events_bmap
, 256);
3131 u32
*events
= (u32
*)async_events_bmap
;
3134 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_DRV_RGTR
, -1, -1);
3137 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD
);
3139 memset(async_events_bmap
, 0, sizeof(async_events_bmap
));
3140 for (i
= 0; i
< ARRAY_SIZE(bnxt_async_events_arr
); i
++)
3141 __set_bit(bnxt_async_events_arr
[i
], async_events_bmap
);
3143 if (bmap
&& bmap_size
) {
3144 for (i
= 0; i
< bmap_size
; i
++) {
3145 if (test_bit(i
, bmap
))
3146 __set_bit(i
, async_events_bmap
);
3150 for (i
= 0; i
< 8; i
++)
3151 req
.async_event_fwd
[i
] |= cpu_to_le32(events
[i
]);
3153 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3156 static int bnxt_hwrm_func_drv_rgtr(struct bnxt
*bp
)
3158 struct hwrm_func_drv_rgtr_input req
= {0};
3160 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_DRV_RGTR
, -1, -1);
3163 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE
|
3164 FUNC_DRV_RGTR_REQ_ENABLES_VER
);
3166 req
.os_type
= cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX
);
3167 req
.ver_maj
= DRV_VER_MAJ
;
3168 req
.ver_min
= DRV_VER_MIN
;
3169 req
.ver_upd
= DRV_VER_UPD
;
3172 DECLARE_BITMAP(vf_req_snif_bmap
, 256);
3173 u32
*data
= (u32
*)vf_req_snif_bmap
;
3176 memset(vf_req_snif_bmap
, 0, sizeof(vf_req_snif_bmap
));
3177 for (i
= 0; i
< ARRAY_SIZE(bnxt_vf_req_snif
); i
++)
3178 __set_bit(bnxt_vf_req_snif
[i
], vf_req_snif_bmap
);
3180 for (i
= 0; i
< 8; i
++)
3181 req
.vf_req_fwd
[i
] = cpu_to_le32(data
[i
]);
3184 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD
);
3187 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3190 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt
*bp
)
3192 struct hwrm_func_drv_unrgtr_input req
= {0};
3194 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_DRV_UNRGTR
, -1, -1);
3195 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3198 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt
*bp
, u8 tunnel_type
)
3201 struct hwrm_tunnel_dst_port_free_input req
= {0};
3203 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_TUNNEL_DST_PORT_FREE
, -1, -1);
3204 req
.tunnel_type
= tunnel_type
;
3206 switch (tunnel_type
) {
3207 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
:
3208 req
.tunnel_dst_port_id
= bp
->vxlan_fw_dst_port_id
;
3210 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
:
3211 req
.tunnel_dst_port_id
= bp
->nge_fw_dst_port_id
;
3217 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3219 netdev_err(bp
->dev
, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
3224 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt
*bp
, __be16 port
,
3228 struct hwrm_tunnel_dst_port_alloc_input req
= {0};
3229 struct hwrm_tunnel_dst_port_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3231 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_TUNNEL_DST_PORT_ALLOC
, -1, -1);
3233 req
.tunnel_type
= tunnel_type
;
3234 req
.tunnel_dst_port_val
= port
;
3236 mutex_lock(&bp
->hwrm_cmd_lock
);
3237 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3239 netdev_err(bp
->dev
, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
3244 switch (tunnel_type
) {
3245 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN
:
3246 bp
->vxlan_fw_dst_port_id
= resp
->tunnel_dst_port_id
;
3248 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE
:
3249 bp
->nge_fw_dst_port_id
= resp
->tunnel_dst_port_id
;
3256 mutex_unlock(&bp
->hwrm_cmd_lock
);
3260 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt
*bp
, u16 vnic_id
)
3262 struct hwrm_cfa_l2_set_rx_mask_input req
= {0};
3263 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
3265 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_L2_SET_RX_MASK
, -1, -1);
3266 req
.vnic_id
= cpu_to_le32(vnic
->fw_vnic_id
);
3268 req
.num_mc_entries
= cpu_to_le32(vnic
->mc_list_count
);
3269 req
.mc_tbl_addr
= cpu_to_le64(vnic
->mc_list_mapping
);
3270 req
.mask
= cpu_to_le32(vnic
->rx_mask
);
3271 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3274 #ifdef CONFIG_RFS_ACCEL
3275 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt
*bp
,
3276 struct bnxt_ntuple_filter
*fltr
)
3278 struct hwrm_cfa_ntuple_filter_free_input req
= {0};
3280 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_NTUPLE_FILTER_FREE
, -1, -1);
3281 req
.ntuple_filter_id
= fltr
->filter_id
;
3282 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3285 #define BNXT_NTP_FLTR_FLAGS \
3286 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
3287 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
3288 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
3289 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
3290 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
3291 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
3292 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
3293 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
3294 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
3295 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
3296 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
3297 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
3298 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
3299 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
3301 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt
*bp
,
3302 struct bnxt_ntuple_filter
*fltr
)
3305 struct hwrm_cfa_ntuple_filter_alloc_input req
= {0};
3306 struct hwrm_cfa_ntuple_filter_alloc_output
*resp
=
3307 bp
->hwrm_cmd_resp_addr
;
3308 struct flow_keys
*keys
= &fltr
->fkeys
;
3309 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[fltr
->rxq
+ 1];
3311 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_NTUPLE_FILTER_ALLOC
, -1, -1);
3312 req
.l2_filter_id
= bp
->vnic_info
[0].fw_l2_filter_id
[fltr
->l2_fltr_idx
];
3314 req
.enables
= cpu_to_le32(BNXT_NTP_FLTR_FLAGS
);
3316 req
.ethertype
= htons(ETH_P_IP
);
3317 memcpy(req
.src_macaddr
, fltr
->src_mac_addr
, ETH_ALEN
);
3318 req
.ip_addr_type
= CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4
;
3319 req
.ip_protocol
= keys
->basic
.ip_proto
;
3321 if (keys
->basic
.n_proto
== htons(ETH_P_IPV6
)) {
3324 req
.ethertype
= htons(ETH_P_IPV6
);
3326 CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6
;
3327 *(struct in6_addr
*)&req
.src_ipaddr
[0] =
3328 keys
->addrs
.v6addrs
.src
;
3329 *(struct in6_addr
*)&req
.dst_ipaddr
[0] =
3330 keys
->addrs
.v6addrs
.dst
;
3331 for (i
= 0; i
< 4; i
++) {
3332 req
.src_ipaddr_mask
[i
] = cpu_to_be32(0xffffffff);
3333 req
.dst_ipaddr_mask
[i
] = cpu_to_be32(0xffffffff);
3336 req
.src_ipaddr
[0] = keys
->addrs
.v4addrs
.src
;
3337 req
.src_ipaddr_mask
[0] = cpu_to_be32(0xffffffff);
3338 req
.dst_ipaddr
[0] = keys
->addrs
.v4addrs
.dst
;
3339 req
.dst_ipaddr_mask
[0] = cpu_to_be32(0xffffffff);
3342 req
.src_port
= keys
->ports
.src
;
3343 req
.src_port_mask
= cpu_to_be16(0xffff);
3344 req
.dst_port
= keys
->ports
.dst
;
3345 req
.dst_port_mask
= cpu_to_be16(0xffff);
3347 req
.dst_id
= cpu_to_le16(vnic
->fw_vnic_id
);
3348 mutex_lock(&bp
->hwrm_cmd_lock
);
3349 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3351 fltr
->filter_id
= resp
->ntuple_filter_id
;
3352 mutex_unlock(&bp
->hwrm_cmd_lock
);
3357 static int bnxt_hwrm_set_vnic_filter(struct bnxt
*bp
, u16 vnic_id
, u16 idx
,
3361 struct hwrm_cfa_l2_filter_alloc_input req
= {0};
3362 struct hwrm_cfa_l2_filter_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3364 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_L2_FILTER_ALLOC
, -1, -1);
3365 req
.flags
= cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX
);
3366 if (!BNXT_CHIP_TYPE_NITRO_A0(bp
))
3368 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST
);
3369 req
.dst_id
= cpu_to_le16(bp
->vnic_info
[vnic_id
].fw_vnic_id
);
3371 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR
|
3372 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID
|
3373 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK
);
3374 memcpy(req
.l2_addr
, mac_addr
, ETH_ALEN
);
3375 req
.l2_addr_mask
[0] = 0xff;
3376 req
.l2_addr_mask
[1] = 0xff;
3377 req
.l2_addr_mask
[2] = 0xff;
3378 req
.l2_addr_mask
[3] = 0xff;
3379 req
.l2_addr_mask
[4] = 0xff;
3380 req
.l2_addr_mask
[5] = 0xff;
3382 mutex_lock(&bp
->hwrm_cmd_lock
);
3383 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3385 bp
->vnic_info
[vnic_id
].fw_l2_filter_id
[idx
] =
3387 mutex_unlock(&bp
->hwrm_cmd_lock
);
3391 static int bnxt_hwrm_clear_vnic_filter(struct bnxt
*bp
)
3393 u16 i
, j
, num_of_vnics
= 1; /* only vnic 0 supported */
3396 /* Any associated ntuple filters will also be cleared by firmware. */
3397 mutex_lock(&bp
->hwrm_cmd_lock
);
3398 for (i
= 0; i
< num_of_vnics
; i
++) {
3399 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[i
];
3401 for (j
= 0; j
< vnic
->uc_filter_count
; j
++) {
3402 struct hwrm_cfa_l2_filter_free_input req
= {0};
3404 bnxt_hwrm_cmd_hdr_init(bp
, &req
,
3405 HWRM_CFA_L2_FILTER_FREE
, -1, -1);
3407 req
.l2_filter_id
= vnic
->fw_l2_filter_id
[j
];
3409 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3412 vnic
->uc_filter_count
= 0;
3414 mutex_unlock(&bp
->hwrm_cmd_lock
);
3419 static int bnxt_hwrm_vnic_set_tpa(struct bnxt
*bp
, u16 vnic_id
, u32 tpa_flags
)
3421 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
3422 struct hwrm_vnic_tpa_cfg_input req
= {0};
3424 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_TPA_CFG
, -1, -1);
3427 u16 mss
= bp
->dev
->mtu
- 40;
3428 u32 nsegs
, n
, segs
= 0, flags
;
3430 flags
= VNIC_TPA_CFG_REQ_FLAGS_TPA
|
3431 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA
|
3432 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE
|
3433 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN
|
3434 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ
;
3435 if (tpa_flags
& BNXT_FLAG_GRO
)
3436 flags
|= VNIC_TPA_CFG_REQ_FLAGS_GRO
;
3438 req
.flags
= cpu_to_le32(flags
);
3441 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS
|
3442 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS
|
3443 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN
);
3445 /* Number of segs are log2 units, and first packet is not
3446 * included as part of this units.
3448 if (mss
<= BNXT_RX_PAGE_SIZE
) {
3449 n
= BNXT_RX_PAGE_SIZE
/ mss
;
3450 nsegs
= (MAX_SKB_FRAGS
- 1) * n
;
3452 n
= mss
/ BNXT_RX_PAGE_SIZE
;
3453 if (mss
& (BNXT_RX_PAGE_SIZE
- 1))
3455 nsegs
= (MAX_SKB_FRAGS
- n
) / n
;
3458 segs
= ilog2(nsegs
);
3459 req
.max_agg_segs
= cpu_to_le16(segs
);
3460 req
.max_aggs
= cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX
);
3462 req
.min_agg_len
= cpu_to_le32(512);
3464 req
.vnic_id
= cpu_to_le16(vnic
->fw_vnic_id
);
3466 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3469 static int bnxt_hwrm_vnic_set_rss(struct bnxt
*bp
, u16 vnic_id
, bool set_rss
)
3471 u32 i
, j
, max_rings
;
3472 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
3473 struct hwrm_vnic_rss_cfg_input req
= {0};
3475 if (vnic
->fw_rss_cos_lb_ctx
[0] == INVALID_HW_RING_ID
)
3478 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_RSS_CFG
, -1, -1);
3480 req
.hash_type
= cpu_to_le32(bp
->rss_hash_cfg
);
3481 if (vnic
->flags
& BNXT_VNIC_RSS_FLAG
) {
3482 if (BNXT_CHIP_TYPE_NITRO_A0(bp
))
3483 max_rings
= bp
->rx_nr_rings
- 1;
3485 max_rings
= bp
->rx_nr_rings
;
3490 /* Fill the RSS indirection table with ring group ids */
3491 for (i
= 0, j
= 0; i
< HW_HASH_INDEX_SIZE
; i
++, j
++) {
3494 vnic
->rss_table
[i
] = cpu_to_le16(vnic
->fw_grp_ids
[j
]);
3497 req
.ring_grp_tbl_addr
= cpu_to_le64(vnic
->rss_table_dma_addr
);
3498 req
.hash_key_tbl_addr
=
3499 cpu_to_le64(vnic
->rss_hash_key_dma_addr
);
3501 req
.rss_ctx_idx
= cpu_to_le16(vnic
->fw_rss_cos_lb_ctx
[0]);
3502 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3505 static int bnxt_hwrm_vnic_set_hds(struct bnxt
*bp
, u16 vnic_id
)
3507 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
3508 struct hwrm_vnic_plcmodes_cfg_input req
= {0};
3510 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_PLCMODES_CFG
, -1, -1);
3511 req
.flags
= cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT
|
3512 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4
|
3513 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6
);
3515 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID
|
3516 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID
);
3517 /* thresholds not implemented in firmware yet */
3518 req
.jumbo_thresh
= cpu_to_le16(bp
->rx_copy_thresh
);
3519 req
.hds_threshold
= cpu_to_le16(bp
->rx_copy_thresh
);
3520 req
.vnic_id
= cpu_to_le32(vnic
->fw_vnic_id
);
3521 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3524 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt
*bp
, u16 vnic_id
,
3527 struct hwrm_vnic_rss_cos_lb_ctx_free_input req
= {0};
3529 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_RSS_COS_LB_CTX_FREE
, -1, -1);
3530 req
.rss_cos_lb_ctx_id
=
3531 cpu_to_le16(bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
[ctx_idx
]);
3533 hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3534 bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
[ctx_idx
] = INVALID_HW_RING_ID
;
3537 static void bnxt_hwrm_vnic_ctx_free(struct bnxt
*bp
)
3541 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
3542 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[i
];
3544 for (j
= 0; j
< BNXT_MAX_CTX_PER_VNIC
; j
++) {
3545 if (vnic
->fw_rss_cos_lb_ctx
[j
] != INVALID_HW_RING_ID
)
3546 bnxt_hwrm_vnic_ctx_free_one(bp
, i
, j
);
3549 bp
->rsscos_nr_ctxs
= 0;
3552 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt
*bp
, u16 vnic_id
, u16 ctx_idx
)
3555 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req
= {0};
3556 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output
*resp
=
3557 bp
->hwrm_cmd_resp_addr
;
3559 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC
, -1,
3562 mutex_lock(&bp
->hwrm_cmd_lock
);
3563 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3565 bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
[ctx_idx
] =
3566 le16_to_cpu(resp
->rss_cos_lb_ctx_id
);
3567 mutex_unlock(&bp
->hwrm_cmd_lock
);
3572 int bnxt_hwrm_vnic_cfg(struct bnxt
*bp
, u16 vnic_id
)
3574 unsigned int ring
= 0, grp_idx
;
3575 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
3576 struct hwrm_vnic_cfg_input req
= {0};
3579 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_CFG
, -1, -1);
3581 req
.enables
= cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP
);
3582 /* Only RSS support for now TBD: COS & LB */
3583 if (vnic
->fw_rss_cos_lb_ctx
[0] != INVALID_HW_RING_ID
) {
3584 req
.rss_rule
= cpu_to_le16(vnic
->fw_rss_cos_lb_ctx
[0]);
3585 req
.enables
|= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE
|
3586 VNIC_CFG_REQ_ENABLES_MRU
);
3587 } else if (vnic
->flags
& BNXT_VNIC_RFS_NEW_RSS_FLAG
) {
3589 cpu_to_le16(bp
->vnic_info
[0].fw_rss_cos_lb_ctx
[0]);
3590 req
.enables
|= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE
|
3591 VNIC_CFG_REQ_ENABLES_MRU
);
3592 req
.flags
|= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE
);
3594 req
.rss_rule
= cpu_to_le16(0xffff);
3597 if (BNXT_CHIP_TYPE_NITRO_A0(bp
) &&
3598 (vnic
->fw_rss_cos_lb_ctx
[0] != INVALID_HW_RING_ID
)) {
3599 req
.cos_rule
= cpu_to_le16(vnic
->fw_rss_cos_lb_ctx
[1]);
3600 req
.enables
|= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE
);
3602 req
.cos_rule
= cpu_to_le16(0xffff);
3605 if (vnic
->flags
& BNXT_VNIC_RSS_FLAG
)
3607 else if (vnic
->flags
& BNXT_VNIC_RFS_FLAG
)
3609 else if ((vnic_id
== 1) && BNXT_CHIP_TYPE_NITRO_A0(bp
))
3610 ring
= bp
->rx_nr_rings
- 1;
3612 grp_idx
= bp
->rx_ring
[ring
].bnapi
->index
;
3613 req
.vnic_id
= cpu_to_le16(vnic
->fw_vnic_id
);
3614 req
.dflt_ring_grp
= cpu_to_le16(bp
->grp_info
[grp_idx
].fw_grp_id
);
3616 req
.lb_rule
= cpu_to_le16(0xffff);
3617 req
.mru
= cpu_to_le16(bp
->dev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+
3620 #ifdef CONFIG_BNXT_SRIOV
3622 def_vlan
= bp
->vf
.vlan
;
3624 if ((bp
->flags
& BNXT_FLAG_STRIP_VLAN
) || def_vlan
)
3625 req
.flags
|= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE
);
3626 if (!vnic_id
&& bnxt_ulp_registered(bp
->edev
, BNXT_ROCE_ULP
))
3628 cpu_to_le32(VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE
);
3630 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3633 static int bnxt_hwrm_vnic_free_one(struct bnxt
*bp
, u16 vnic_id
)
3637 if (bp
->vnic_info
[vnic_id
].fw_vnic_id
!= INVALID_HW_RING_ID
) {
3638 struct hwrm_vnic_free_input req
= {0};
3640 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_FREE
, -1, -1);
3642 cpu_to_le32(bp
->vnic_info
[vnic_id
].fw_vnic_id
);
3644 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3647 bp
->vnic_info
[vnic_id
].fw_vnic_id
= INVALID_HW_RING_ID
;
3652 static void bnxt_hwrm_vnic_free(struct bnxt
*bp
)
3656 for (i
= 0; i
< bp
->nr_vnics
; i
++)
3657 bnxt_hwrm_vnic_free_one(bp
, i
);
3660 static int bnxt_hwrm_vnic_alloc(struct bnxt
*bp
, u16 vnic_id
,
3661 unsigned int start_rx_ring_idx
,
3662 unsigned int nr_rings
)
3665 unsigned int i
, j
, grp_idx
, end_idx
= start_rx_ring_idx
+ nr_rings
;
3666 struct hwrm_vnic_alloc_input req
= {0};
3667 struct hwrm_vnic_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3669 /* map ring groups to this vnic */
3670 for (i
= start_rx_ring_idx
, j
= 0; i
< end_idx
; i
++, j
++) {
3671 grp_idx
= bp
->rx_ring
[i
].bnapi
->index
;
3672 if (bp
->grp_info
[grp_idx
].fw_grp_id
== INVALID_HW_RING_ID
) {
3673 netdev_err(bp
->dev
, "Not enough ring groups avail:%x req:%x\n",
3677 bp
->vnic_info
[vnic_id
].fw_grp_ids
[j
] =
3678 bp
->grp_info
[grp_idx
].fw_grp_id
;
3681 bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
[0] = INVALID_HW_RING_ID
;
3682 bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
[1] = INVALID_HW_RING_ID
;
3684 req
.flags
= cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT
);
3686 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_ALLOC
, -1, -1);
3688 mutex_lock(&bp
->hwrm_cmd_lock
);
3689 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3691 bp
->vnic_info
[vnic_id
].fw_vnic_id
= le32_to_cpu(resp
->vnic_id
);
3692 mutex_unlock(&bp
->hwrm_cmd_lock
);
3696 static int bnxt_hwrm_vnic_qcaps(struct bnxt
*bp
)
3698 struct hwrm_vnic_qcaps_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3699 struct hwrm_vnic_qcaps_input req
= {0};
3702 if (bp
->hwrm_spec_code
< 0x10600)
3705 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_QCAPS
, -1, -1);
3706 mutex_lock(&bp
->hwrm_cmd_lock
);
3707 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3710 cpu_to_le32(VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP
))
3711 bp
->flags
|= BNXT_FLAG_NEW_RSS_CAP
;
3713 mutex_unlock(&bp
->hwrm_cmd_lock
);
3717 static int bnxt_hwrm_ring_grp_alloc(struct bnxt
*bp
)
3722 mutex_lock(&bp
->hwrm_cmd_lock
);
3723 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3724 struct hwrm_ring_grp_alloc_input req
= {0};
3725 struct hwrm_ring_grp_alloc_output
*resp
=
3726 bp
->hwrm_cmd_resp_addr
;
3727 unsigned int grp_idx
= bp
->rx_ring
[i
].bnapi
->index
;
3729 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_GRP_ALLOC
, -1, -1);
3731 req
.cr
= cpu_to_le16(bp
->grp_info
[grp_idx
].cp_fw_ring_id
);
3732 req
.rr
= cpu_to_le16(bp
->grp_info
[grp_idx
].rx_fw_ring_id
);
3733 req
.ar
= cpu_to_le16(bp
->grp_info
[grp_idx
].agg_fw_ring_id
);
3734 req
.sc
= cpu_to_le16(bp
->grp_info
[grp_idx
].fw_stats_ctx
);
3736 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3741 bp
->grp_info
[grp_idx
].fw_grp_id
=
3742 le32_to_cpu(resp
->ring_group_id
);
3744 mutex_unlock(&bp
->hwrm_cmd_lock
);
3748 static int bnxt_hwrm_ring_grp_free(struct bnxt
*bp
)
3752 struct hwrm_ring_grp_free_input req
= {0};
3757 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_GRP_FREE
, -1, -1);
3759 mutex_lock(&bp
->hwrm_cmd_lock
);
3760 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3761 if (bp
->grp_info
[i
].fw_grp_id
== INVALID_HW_RING_ID
)
3764 cpu_to_le32(bp
->grp_info
[i
].fw_grp_id
);
3766 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3770 bp
->grp_info
[i
].fw_grp_id
= INVALID_HW_RING_ID
;
3772 mutex_unlock(&bp
->hwrm_cmd_lock
);
3776 static int hwrm_ring_alloc_send_msg(struct bnxt
*bp
,
3777 struct bnxt_ring_struct
*ring
,
3778 u32 ring_type
, u32 map_index
,
3781 int rc
= 0, err
= 0;
3782 struct hwrm_ring_alloc_input req
= {0};
3783 struct hwrm_ring_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3786 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_ALLOC
, -1, -1);
3789 if (ring
->nr_pages
> 1) {
3790 req
.page_tbl_addr
= cpu_to_le64(ring
->pg_tbl_map
);
3791 /* Page size is in log2 units */
3792 req
.page_size
= BNXT_PAGE_SHIFT
;
3793 req
.page_tbl_depth
= 1;
3795 req
.page_tbl_addr
= cpu_to_le64(ring
->dma_arr
[0]);
3798 /* Association of ring index with doorbell index and MSIX number */
3799 req
.logical_id
= cpu_to_le16(map_index
);
3801 switch (ring_type
) {
3802 case HWRM_RING_ALLOC_TX
:
3803 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_TX
;
3804 /* Association of transmit ring with completion ring */
3806 cpu_to_le16(bp
->grp_info
[map_index
].cp_fw_ring_id
);
3807 req
.length
= cpu_to_le32(bp
->tx_ring_mask
+ 1);
3808 req
.stat_ctx_id
= cpu_to_le32(stats_ctx_id
);
3809 req
.queue_id
= cpu_to_le16(ring
->queue_id
);
3811 case HWRM_RING_ALLOC_RX
:
3812 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_RX
;
3813 req
.length
= cpu_to_le32(bp
->rx_ring_mask
+ 1);
3815 case HWRM_RING_ALLOC_AGG
:
3816 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_RX
;
3817 req
.length
= cpu_to_le32(bp
->rx_agg_ring_mask
+ 1);
3819 case HWRM_RING_ALLOC_CMPL
:
3820 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_CMPL
;
3821 req
.length
= cpu_to_le32(bp
->cp_ring_mask
+ 1);
3822 if (bp
->flags
& BNXT_FLAG_USING_MSIX
)
3823 req
.int_mode
= RING_ALLOC_REQ_INT_MODE_MSIX
;
3826 netdev_err(bp
->dev
, "hwrm alloc invalid ring type %d\n",
3831 mutex_lock(&bp
->hwrm_cmd_lock
);
3832 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3833 err
= le16_to_cpu(resp
->error_code
);
3834 ring_id
= le16_to_cpu(resp
->ring_id
);
3835 mutex_unlock(&bp
->hwrm_cmd_lock
);
3838 switch (ring_type
) {
3839 case RING_FREE_REQ_RING_TYPE_CMPL
:
3840 netdev_err(bp
->dev
, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
3844 case RING_FREE_REQ_RING_TYPE_RX
:
3845 netdev_err(bp
->dev
, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
3849 case RING_FREE_REQ_RING_TYPE_TX
:
3850 netdev_err(bp
->dev
, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
3855 netdev_err(bp
->dev
, "Invalid ring\n");
3859 ring
->fw_ring_id
= ring_id
;
3863 static int bnxt_hwrm_set_async_event_cr(struct bnxt
*bp
, int idx
)
3868 struct hwrm_func_cfg_input req
= {0};
3870 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_CFG
, -1, -1);
3871 req
.fid
= cpu_to_le16(0xffff);
3872 req
.enables
= cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR
);
3873 req
.async_event_cr
= cpu_to_le16(idx
);
3874 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3876 struct hwrm_func_vf_cfg_input req
= {0};
3878 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_VF_CFG
, -1, -1);
3880 cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR
);
3881 req
.async_event_cr
= cpu_to_le16(idx
);
3882 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3887 static int bnxt_hwrm_ring_alloc(struct bnxt
*bp
)
3891 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3892 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3893 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3894 struct bnxt_ring_struct
*ring
= &cpr
->cp_ring_struct
;
3896 cpr
->cp_doorbell
= bp
->bar1
+ i
* 0x80;
3897 rc
= hwrm_ring_alloc_send_msg(bp
, ring
, HWRM_RING_ALLOC_CMPL
, i
,
3898 INVALID_STATS_CTX_ID
);
3901 BNXT_CP_DB(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
3902 bp
->grp_info
[i
].cp_fw_ring_id
= ring
->fw_ring_id
;
3905 rc
= bnxt_hwrm_set_async_event_cr(bp
, ring
->fw_ring_id
);
3907 netdev_warn(bp
->dev
, "Failed to set async event completion ring.\n");
3911 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
3912 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
3913 struct bnxt_ring_struct
*ring
= &txr
->tx_ring_struct
;
3914 u32 map_idx
= txr
->bnapi
->index
;
3915 u16 fw_stats_ctx
= bp
->grp_info
[map_idx
].fw_stats_ctx
;
3917 rc
= hwrm_ring_alloc_send_msg(bp
, ring
, HWRM_RING_ALLOC_TX
,
3918 map_idx
, fw_stats_ctx
);
3921 txr
->tx_doorbell
= bp
->bar1
+ map_idx
* 0x80;
3924 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3925 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
3926 struct bnxt_ring_struct
*ring
= &rxr
->rx_ring_struct
;
3927 u32 map_idx
= rxr
->bnapi
->index
;
3929 rc
= hwrm_ring_alloc_send_msg(bp
, ring
, HWRM_RING_ALLOC_RX
,
3930 map_idx
, INVALID_STATS_CTX_ID
);
3933 rxr
->rx_doorbell
= bp
->bar1
+ map_idx
* 0x80;
3934 writel(DB_KEY_RX
| rxr
->rx_prod
, rxr
->rx_doorbell
);
3935 bp
->grp_info
[map_idx
].rx_fw_ring_id
= ring
->fw_ring_id
;
3938 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
) {
3939 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3940 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
3941 struct bnxt_ring_struct
*ring
=
3942 &rxr
->rx_agg_ring_struct
;
3943 u32 grp_idx
= rxr
->bnapi
->index
;
3944 u32 map_idx
= grp_idx
+ bp
->rx_nr_rings
;
3946 rc
= hwrm_ring_alloc_send_msg(bp
, ring
,
3947 HWRM_RING_ALLOC_AGG
,
3949 INVALID_STATS_CTX_ID
);
3953 rxr
->rx_agg_doorbell
= bp
->bar1
+ map_idx
* 0x80;
3954 writel(DB_KEY_RX
| rxr
->rx_agg_prod
,
3955 rxr
->rx_agg_doorbell
);
3956 bp
->grp_info
[grp_idx
].agg_fw_ring_id
= ring
->fw_ring_id
;
3963 static int hwrm_ring_free_send_msg(struct bnxt
*bp
,
3964 struct bnxt_ring_struct
*ring
,
3965 u32 ring_type
, int cmpl_ring_id
)
3968 struct hwrm_ring_free_input req
= {0};
3969 struct hwrm_ring_free_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3972 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_FREE
, cmpl_ring_id
, -1);
3973 req
.ring_type
= ring_type
;
3974 req
.ring_id
= cpu_to_le16(ring
->fw_ring_id
);
3976 mutex_lock(&bp
->hwrm_cmd_lock
);
3977 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3978 error_code
= le16_to_cpu(resp
->error_code
);
3979 mutex_unlock(&bp
->hwrm_cmd_lock
);
3981 if (rc
|| error_code
) {
3982 switch (ring_type
) {
3983 case RING_FREE_REQ_RING_TYPE_CMPL
:
3984 netdev_err(bp
->dev
, "hwrm_ring_free cp failed. rc:%d\n",
3987 case RING_FREE_REQ_RING_TYPE_RX
:
3988 netdev_err(bp
->dev
, "hwrm_ring_free rx failed. rc:%d\n",
3991 case RING_FREE_REQ_RING_TYPE_TX
:
3992 netdev_err(bp
->dev
, "hwrm_ring_free tx failed. rc:%d\n",
3996 netdev_err(bp
->dev
, "Invalid ring\n");
4003 static void bnxt_hwrm_ring_free(struct bnxt
*bp
, bool close_path
)
4010 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
4011 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
4012 struct bnxt_ring_struct
*ring
= &txr
->tx_ring_struct
;
4013 u32 grp_idx
= txr
->bnapi
->index
;
4014 u32 cmpl_ring_id
= bp
->grp_info
[grp_idx
].cp_fw_ring_id
;
4016 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
4017 hwrm_ring_free_send_msg(bp
, ring
,
4018 RING_FREE_REQ_RING_TYPE_TX
,
4019 close_path
? cmpl_ring_id
:
4020 INVALID_HW_RING_ID
);
4021 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
4025 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
4026 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
4027 struct bnxt_ring_struct
*ring
= &rxr
->rx_ring_struct
;
4028 u32 grp_idx
= rxr
->bnapi
->index
;
4029 u32 cmpl_ring_id
= bp
->grp_info
[grp_idx
].cp_fw_ring_id
;
4031 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
4032 hwrm_ring_free_send_msg(bp
, ring
,
4033 RING_FREE_REQ_RING_TYPE_RX
,
4034 close_path
? cmpl_ring_id
:
4035 INVALID_HW_RING_ID
);
4036 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
4037 bp
->grp_info
[grp_idx
].rx_fw_ring_id
=
4042 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
4043 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
4044 struct bnxt_ring_struct
*ring
= &rxr
->rx_agg_ring_struct
;
4045 u32 grp_idx
= rxr
->bnapi
->index
;
4046 u32 cmpl_ring_id
= bp
->grp_info
[grp_idx
].cp_fw_ring_id
;
4048 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
4049 hwrm_ring_free_send_msg(bp
, ring
,
4050 RING_FREE_REQ_RING_TYPE_RX
,
4051 close_path
? cmpl_ring_id
:
4052 INVALID_HW_RING_ID
);
4053 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
4054 bp
->grp_info
[grp_idx
].agg_fw_ring_id
=
4059 /* The completion rings are about to be freed. After that the
4060 * IRQ doorbell will not work anymore. So we need to disable
4063 bnxt_disable_int_sync(bp
);
4065 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4066 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4067 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
4068 struct bnxt_ring_struct
*ring
= &cpr
->cp_ring_struct
;
4070 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
4071 hwrm_ring_free_send_msg(bp
, ring
,
4072 RING_FREE_REQ_RING_TYPE_CMPL
,
4073 INVALID_HW_RING_ID
);
4074 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
4075 bp
->grp_info
[i
].cp_fw_ring_id
= INVALID_HW_RING_ID
;
4080 /* Caller must hold bp->hwrm_cmd_lock */
4081 int __bnxt_hwrm_get_tx_rings(struct bnxt
*bp
, u16 fid
, int *tx_rings
)
4083 struct hwrm_func_qcfg_output
*resp
= bp
->hwrm_cmd_resp_addr
;
4084 struct hwrm_func_qcfg_input req
= {0};
4087 if (bp
->hwrm_spec_code
< 0x10601)
4090 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_QCFG
, -1, -1);
4091 req
.fid
= cpu_to_le16(fid
);
4092 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4094 *tx_rings
= le16_to_cpu(resp
->alloc_tx_rings
);
4099 int bnxt_hwrm_reserve_tx_rings(struct bnxt
*bp
, int *tx_rings
)
4101 struct hwrm_func_cfg_input req
= {0};
4104 if (bp
->hwrm_spec_code
< 0x10601)
4110 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_CFG
, -1, -1);
4111 req
.fid
= cpu_to_le16(0xffff);
4112 req
.enables
= cpu_to_le32(FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS
);
4113 req
.num_tx_rings
= cpu_to_le16(*tx_rings
);
4114 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4118 mutex_lock(&bp
->hwrm_cmd_lock
);
4119 rc
= __bnxt_hwrm_get_tx_rings(bp
, 0xffff, tx_rings
);
4120 mutex_unlock(&bp
->hwrm_cmd_lock
);
4124 static void bnxt_hwrm_set_coal_params(struct bnxt
*bp
, u32 max_bufs
,
4125 u32 buf_tmrs
, u16 flags
,
4126 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input
*req
)
4128 req
->flags
= cpu_to_le16(flags
);
4129 req
->num_cmpl_dma_aggr
= cpu_to_le16((u16
)max_bufs
);
4130 req
->num_cmpl_dma_aggr_during_int
= cpu_to_le16(max_bufs
>> 16);
4131 req
->cmpl_aggr_dma_tmr
= cpu_to_le16((u16
)buf_tmrs
);
4132 req
->cmpl_aggr_dma_tmr_during_int
= cpu_to_le16(buf_tmrs
>> 16);
4133 /* Minimum time between 2 interrupts set to buf_tmr x 2 */
4134 req
->int_lat_tmr_min
= cpu_to_le16((u16
)buf_tmrs
* 2);
4135 req
->int_lat_tmr_max
= cpu_to_le16((u16
)buf_tmrs
* 4);
4136 req
->num_cmpl_aggr_int
= cpu_to_le16((u16
)max_bufs
* 4);
4139 int bnxt_hwrm_set_coal(struct bnxt
*bp
)
4142 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx
= {0},
4144 u16 max_buf
, max_buf_irq
;
4145 u16 buf_tmr
, buf_tmr_irq
;
4148 bnxt_hwrm_cmd_hdr_init(bp
, &req_rx
,
4149 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS
, -1, -1);
4150 bnxt_hwrm_cmd_hdr_init(bp
, &req_tx
,
4151 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS
, -1, -1);
4153 /* Each rx completion (2 records) should be DMAed immediately.
4154 * DMA 1/4 of the completion buffers at a time.
4156 max_buf
= min_t(u16
, bp
->rx_coal_bufs
/ 4, 2);
4157 /* max_buf must not be zero */
4158 max_buf
= clamp_t(u16
, max_buf
, 1, 63);
4159 max_buf_irq
= clamp_t(u16
, bp
->rx_coal_bufs_irq
, 1, 63);
4160 buf_tmr
= BNXT_USEC_TO_COAL_TIMER(bp
->rx_coal_ticks
);
4161 /* buf timer set to 1/4 of interrupt timer */
4162 buf_tmr
= max_t(u16
, buf_tmr
/ 4, 1);
4163 buf_tmr_irq
= BNXT_USEC_TO_COAL_TIMER(bp
->rx_coal_ticks_irq
);
4164 buf_tmr_irq
= max_t(u16
, buf_tmr_irq
, 1);
4166 flags
= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET
;
4168 /* RING_IDLE generates more IRQs for lower latency. Enable it only
4169 * if coal_ticks is less than 25 us.
4171 if (bp
->rx_coal_ticks
< 25)
4172 flags
|= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE
;
4174 bnxt_hwrm_set_coal_params(bp
, max_buf_irq
<< 16 | max_buf
,
4175 buf_tmr_irq
<< 16 | buf_tmr
, flags
, &req_rx
);
4177 /* max_buf must not be zero */
4178 max_buf
= clamp_t(u16
, bp
->tx_coal_bufs
, 1, 63);
4179 max_buf_irq
= clamp_t(u16
, bp
->tx_coal_bufs_irq
, 1, 63);
4180 buf_tmr
= BNXT_USEC_TO_COAL_TIMER(bp
->tx_coal_ticks
);
4181 /* buf timer set to 1/4 of interrupt timer */
4182 buf_tmr
= max_t(u16
, buf_tmr
/ 4, 1);
4183 buf_tmr_irq
= BNXT_USEC_TO_COAL_TIMER(bp
->tx_coal_ticks_irq
);
4184 buf_tmr_irq
= max_t(u16
, buf_tmr_irq
, 1);
4186 flags
= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET
;
4187 bnxt_hwrm_set_coal_params(bp
, max_buf_irq
<< 16 | max_buf
,
4188 buf_tmr_irq
<< 16 | buf_tmr
, flags
, &req_tx
);
4190 mutex_lock(&bp
->hwrm_cmd_lock
);
4191 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4192 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4195 if (!bnapi
->rx_ring
)
4197 req
->ring_id
= cpu_to_le16(bp
->grp_info
[i
].cp_fw_ring_id
);
4199 rc
= _hwrm_send_message(bp
, req
, sizeof(*req
),
4204 mutex_unlock(&bp
->hwrm_cmd_lock
);
4208 static int bnxt_hwrm_stat_ctx_free(struct bnxt
*bp
)
4211 struct hwrm_stat_ctx_free_input req
= {0};
4216 if (BNXT_CHIP_TYPE_NITRO_A0(bp
))
4219 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_STAT_CTX_FREE
, -1, -1);
4221 mutex_lock(&bp
->hwrm_cmd_lock
);
4222 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4223 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4224 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
4226 if (cpr
->hw_stats_ctx_id
!= INVALID_STATS_CTX_ID
) {
4227 req
.stat_ctx_id
= cpu_to_le32(cpr
->hw_stats_ctx_id
);
4229 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
4234 cpr
->hw_stats_ctx_id
= INVALID_STATS_CTX_ID
;
4237 mutex_unlock(&bp
->hwrm_cmd_lock
);
4241 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt
*bp
)
4244 struct hwrm_stat_ctx_alloc_input req
= {0};
4245 struct hwrm_stat_ctx_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
4247 if (BNXT_CHIP_TYPE_NITRO_A0(bp
))
4250 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_STAT_CTX_ALLOC
, -1, -1);
4252 req
.update_period_ms
= cpu_to_le32(bp
->stats_coal_ticks
/ 1000);
4254 mutex_lock(&bp
->hwrm_cmd_lock
);
4255 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4256 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4257 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
4259 req
.stats_dma_addr
= cpu_to_le64(cpr
->hw_stats_map
);
4261 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
4266 cpr
->hw_stats_ctx_id
= le32_to_cpu(resp
->stat_ctx_id
);
4268 bp
->grp_info
[i
].fw_stats_ctx
= cpr
->hw_stats_ctx_id
;
4270 mutex_unlock(&bp
->hwrm_cmd_lock
);
4274 static int bnxt_hwrm_func_qcfg(struct bnxt
*bp
)
4276 struct hwrm_func_qcfg_input req
= {0};
4277 struct hwrm_func_qcfg_output
*resp
= bp
->hwrm_cmd_resp_addr
;
4280 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_QCFG
, -1, -1);
4281 req
.fid
= cpu_to_le16(0xffff);
4282 mutex_lock(&bp
->hwrm_cmd_lock
);
4283 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4285 goto func_qcfg_exit
;
4287 #ifdef CONFIG_BNXT_SRIOV
4289 struct bnxt_vf_info
*vf
= &bp
->vf
;
4291 vf
->vlan
= le16_to_cpu(resp
->vlan
) & VLAN_VID_MASK
;
4294 switch (resp
->port_partition_type
) {
4295 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0
:
4296 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5
:
4297 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0
:
4298 bp
->port_partition_type
= resp
->port_partition_type
;
4303 mutex_unlock(&bp
->hwrm_cmd_lock
);
4307 static int bnxt_hwrm_func_qcaps(struct bnxt
*bp
)
4310 struct hwrm_func_qcaps_input req
= {0};
4311 struct hwrm_func_qcaps_output
*resp
= bp
->hwrm_cmd_resp_addr
;
4313 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_QCAPS
, -1, -1);
4314 req
.fid
= cpu_to_le16(0xffff);
4316 mutex_lock(&bp
->hwrm_cmd_lock
);
4317 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4319 goto hwrm_func_qcaps_exit
;
4321 if (resp
->flags
& cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED
))
4322 bp
->flags
|= BNXT_FLAG_ROCEV1_CAP
;
4323 if (resp
->flags
& cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED
))
4324 bp
->flags
|= BNXT_FLAG_ROCEV2_CAP
;
4326 bp
->tx_push_thresh
= 0;
4328 cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED
))
4329 bp
->tx_push_thresh
= BNXT_TX_PUSH_THRESH
;
4332 struct bnxt_pf_info
*pf
= &bp
->pf
;
4334 pf
->fw_fid
= le16_to_cpu(resp
->fid
);
4335 pf
->port_id
= le16_to_cpu(resp
->port_id
);
4336 bp
->dev
->dev_port
= pf
->port_id
;
4337 memcpy(pf
->mac_addr
, resp
->mac_address
, ETH_ALEN
);
4338 memcpy(bp
->dev
->dev_addr
, pf
->mac_addr
, ETH_ALEN
);
4339 pf
->max_rsscos_ctxs
= le16_to_cpu(resp
->max_rsscos_ctx
);
4340 pf
->max_cp_rings
= le16_to_cpu(resp
->max_cmpl_rings
);
4341 pf
->max_tx_rings
= le16_to_cpu(resp
->max_tx_rings
);
4342 pf
->max_rx_rings
= le16_to_cpu(resp
->max_rx_rings
);
4343 pf
->max_hw_ring_grps
= le32_to_cpu(resp
->max_hw_ring_grps
);
4344 if (!pf
->max_hw_ring_grps
)
4345 pf
->max_hw_ring_grps
= pf
->max_tx_rings
;
4346 pf
->max_l2_ctxs
= le16_to_cpu(resp
->max_l2_ctxs
);
4347 pf
->max_vnics
= le16_to_cpu(resp
->max_vnics
);
4348 pf
->max_stat_ctxs
= le16_to_cpu(resp
->max_stat_ctx
);
4349 pf
->first_vf_id
= le16_to_cpu(resp
->first_vf_id
);
4350 pf
->max_vfs
= le16_to_cpu(resp
->max_vfs
);
4351 pf
->max_encap_records
= le32_to_cpu(resp
->max_encap_records
);
4352 pf
->max_decap_records
= le32_to_cpu(resp
->max_decap_records
);
4353 pf
->max_tx_em_flows
= le32_to_cpu(resp
->max_tx_em_flows
);
4354 pf
->max_tx_wm_flows
= le32_to_cpu(resp
->max_tx_wm_flows
);
4355 pf
->max_rx_em_flows
= le32_to_cpu(resp
->max_rx_em_flows
);
4356 pf
->max_rx_wm_flows
= le32_to_cpu(resp
->max_rx_wm_flows
);
4358 #ifdef CONFIG_BNXT_SRIOV
4359 struct bnxt_vf_info
*vf
= &bp
->vf
;
4361 vf
->fw_fid
= le16_to_cpu(resp
->fid
);
4363 vf
->max_rsscos_ctxs
= le16_to_cpu(resp
->max_rsscos_ctx
);
4364 vf
->max_cp_rings
= le16_to_cpu(resp
->max_cmpl_rings
);
4365 vf
->max_tx_rings
= le16_to_cpu(resp
->max_tx_rings
);
4366 vf
->max_rx_rings
= le16_to_cpu(resp
->max_rx_rings
);
4367 vf
->max_hw_ring_grps
= le32_to_cpu(resp
->max_hw_ring_grps
);
4368 if (!vf
->max_hw_ring_grps
)
4369 vf
->max_hw_ring_grps
= vf
->max_tx_rings
;
4370 vf
->max_l2_ctxs
= le16_to_cpu(resp
->max_l2_ctxs
);
4371 vf
->max_vnics
= le16_to_cpu(resp
->max_vnics
);
4372 vf
->max_stat_ctxs
= le16_to_cpu(resp
->max_stat_ctx
);
4374 memcpy(vf
->mac_addr
, resp
->mac_address
, ETH_ALEN
);
4375 mutex_unlock(&bp
->hwrm_cmd_lock
);
4377 if (is_valid_ether_addr(vf
->mac_addr
)) {
4378 /* overwrite netdev dev_adr with admin VF MAC */
4379 memcpy(bp
->dev
->dev_addr
, vf
->mac_addr
, ETH_ALEN
);
4381 random_ether_addr(bp
->dev
->dev_addr
);
4382 rc
= bnxt_approve_mac(bp
, bp
->dev
->dev_addr
);
4388 hwrm_func_qcaps_exit
:
4389 mutex_unlock(&bp
->hwrm_cmd_lock
);
4393 static int bnxt_hwrm_func_reset(struct bnxt
*bp
)
4395 struct hwrm_func_reset_input req
= {0};
4397 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_RESET
, -1, -1);
4400 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_RESET_TIMEOUT
);
4403 static int bnxt_hwrm_queue_qportcfg(struct bnxt
*bp
)
4406 struct hwrm_queue_qportcfg_input req
= {0};
4407 struct hwrm_queue_qportcfg_output
*resp
= bp
->hwrm_cmd_resp_addr
;
4410 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_QUEUE_QPORTCFG
, -1, -1);
4412 mutex_lock(&bp
->hwrm_cmd_lock
);
4413 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4417 if (!resp
->max_configurable_queues
) {
4421 bp
->max_tc
= resp
->max_configurable_queues
;
4422 bp
->max_lltc
= resp
->max_configurable_lossless_queues
;
4423 if (bp
->max_tc
> BNXT_MAX_QUEUE
)
4424 bp
->max_tc
= BNXT_MAX_QUEUE
;
4426 if (resp
->queue_cfg_info
& QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG
)
4429 if (bp
->max_lltc
> bp
->max_tc
)
4430 bp
->max_lltc
= bp
->max_tc
;
4432 qptr
= &resp
->queue_id0
;
4433 for (i
= 0; i
< bp
->max_tc
; i
++) {
4434 bp
->q_info
[i
].queue_id
= *qptr
++;
4435 bp
->q_info
[i
].queue_profile
= *qptr
++;
4439 mutex_unlock(&bp
->hwrm_cmd_lock
);
4443 static int bnxt_hwrm_ver_get(struct bnxt
*bp
)
4446 struct hwrm_ver_get_input req
= {0};
4447 struct hwrm_ver_get_output
*resp
= bp
->hwrm_cmd_resp_addr
;
4449 bp
->hwrm_max_req_len
= HWRM_MAX_REQ_LEN
;
4450 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VER_GET
, -1, -1);
4451 req
.hwrm_intf_maj
= HWRM_VERSION_MAJOR
;
4452 req
.hwrm_intf_min
= HWRM_VERSION_MINOR
;
4453 req
.hwrm_intf_upd
= HWRM_VERSION_UPDATE
;
4454 mutex_lock(&bp
->hwrm_cmd_lock
);
4455 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4457 goto hwrm_ver_get_exit
;
4459 memcpy(&bp
->ver_resp
, resp
, sizeof(struct hwrm_ver_get_output
));
4461 bp
->hwrm_spec_code
= resp
->hwrm_intf_maj
<< 16 |
4462 resp
->hwrm_intf_min
<< 8 | resp
->hwrm_intf_upd
;
4463 if (resp
->hwrm_intf_maj
< 1) {
4464 netdev_warn(bp
->dev
, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
4465 resp
->hwrm_intf_maj
, resp
->hwrm_intf_min
,
4466 resp
->hwrm_intf_upd
);
4467 netdev_warn(bp
->dev
, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
4469 snprintf(bp
->fw_ver_str
, BC_HWRM_STR_LEN
, "%d.%d.%d/%d.%d.%d",
4470 resp
->hwrm_fw_maj
, resp
->hwrm_fw_min
, resp
->hwrm_fw_bld
,
4471 resp
->hwrm_intf_maj
, resp
->hwrm_intf_min
, resp
->hwrm_intf_upd
);
4473 bp
->hwrm_cmd_timeout
= le16_to_cpu(resp
->def_req_timeout
);
4474 if (!bp
->hwrm_cmd_timeout
)
4475 bp
->hwrm_cmd_timeout
= DFLT_HWRM_CMD_TIMEOUT
;
4477 if (resp
->hwrm_intf_maj
>= 1)
4478 bp
->hwrm_max_req_len
= le16_to_cpu(resp
->max_req_win_len
);
4480 bp
->chip_num
= le16_to_cpu(resp
->chip_num
);
4481 if (bp
->chip_num
== CHIP_NUM_58700
&& !resp
->chip_rev
&&
4483 bp
->flags
|= BNXT_FLAG_CHIP_NITRO_A0
;
4486 mutex_unlock(&bp
->hwrm_cmd_lock
);
4490 int bnxt_hwrm_fw_set_time(struct bnxt
*bp
)
4492 #if IS_ENABLED(CONFIG_RTC_LIB)
4493 struct hwrm_fw_set_time_input req
= {0};
4497 if (bp
->hwrm_spec_code
< 0x10400)
4500 do_gettimeofday(&tv
);
4501 rtc_time_to_tm(tv
.tv_sec
, &tm
);
4502 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FW_SET_TIME
, -1, -1);
4503 req
.year
= cpu_to_le16(1900 + tm
.tm_year
);
4504 req
.month
= 1 + tm
.tm_mon
;
4505 req
.day
= tm
.tm_mday
;
4506 req
.hour
= tm
.tm_hour
;
4507 req
.minute
= tm
.tm_min
;
4508 req
.second
= tm
.tm_sec
;
4509 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4515 static int bnxt_hwrm_port_qstats(struct bnxt
*bp
)
4518 struct bnxt_pf_info
*pf
= &bp
->pf
;
4519 struct hwrm_port_qstats_input req
= {0};
4521 if (!(bp
->flags
& BNXT_FLAG_PORT_STATS
))
4524 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_QSTATS
, -1, -1);
4525 req
.port_id
= cpu_to_le16(pf
->port_id
);
4526 req
.tx_stat_host_addr
= cpu_to_le64(bp
->hw_tx_port_stats_map
);
4527 req
.rx_stat_host_addr
= cpu_to_le64(bp
->hw_rx_port_stats_map
);
4528 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4532 static void bnxt_hwrm_free_tunnel_ports(struct bnxt
*bp
)
4534 if (bp
->vxlan_port_cnt
) {
4535 bnxt_hwrm_tunnel_dst_port_free(
4536 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
);
4538 bp
->vxlan_port_cnt
= 0;
4539 if (bp
->nge_port_cnt
) {
4540 bnxt_hwrm_tunnel_dst_port_free(
4541 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
);
4543 bp
->nge_port_cnt
= 0;
4546 static int bnxt_set_tpa(struct bnxt
*bp
, bool set_tpa
)
4552 tpa_flags
= bp
->flags
& BNXT_FLAG_TPA
;
4553 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
4554 rc
= bnxt_hwrm_vnic_set_tpa(bp
, i
, tpa_flags
);
4556 netdev_err(bp
->dev
, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
4564 static void bnxt_hwrm_clear_vnic_rss(struct bnxt
*bp
)
4568 for (i
= 0; i
< bp
->nr_vnics
; i
++)
4569 bnxt_hwrm_vnic_set_rss(bp
, i
, false);
4572 static void bnxt_hwrm_resource_free(struct bnxt
*bp
, bool close_path
,
4575 if (bp
->vnic_info
) {
4576 bnxt_hwrm_clear_vnic_filter(bp
);
4577 /* clear all RSS setting before free vnic ctx */
4578 bnxt_hwrm_clear_vnic_rss(bp
);
4579 bnxt_hwrm_vnic_ctx_free(bp
);
4580 /* before free the vnic, undo the vnic tpa settings */
4581 if (bp
->flags
& BNXT_FLAG_TPA
)
4582 bnxt_set_tpa(bp
, false);
4583 bnxt_hwrm_vnic_free(bp
);
4585 bnxt_hwrm_ring_free(bp
, close_path
);
4586 bnxt_hwrm_ring_grp_free(bp
);
4588 bnxt_hwrm_stat_ctx_free(bp
);
4589 bnxt_hwrm_free_tunnel_ports(bp
);
4593 static int bnxt_setup_vnic(struct bnxt
*bp
, u16 vnic_id
)
4595 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
4598 if (vnic
->flags
& BNXT_VNIC_RFS_NEW_RSS_FLAG
)
4601 /* allocate context for vnic */
4602 rc
= bnxt_hwrm_vnic_ctx_alloc(bp
, vnic_id
, 0);
4604 netdev_err(bp
->dev
, "hwrm vnic %d alloc failure rc: %x\n",
4606 goto vnic_setup_err
;
4608 bp
->rsscos_nr_ctxs
++;
4610 if (BNXT_CHIP_TYPE_NITRO_A0(bp
)) {
4611 rc
= bnxt_hwrm_vnic_ctx_alloc(bp
, vnic_id
, 1);
4613 netdev_err(bp
->dev
, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
4615 goto vnic_setup_err
;
4617 bp
->rsscos_nr_ctxs
++;
4621 /* configure default vnic, ring grp */
4622 rc
= bnxt_hwrm_vnic_cfg(bp
, vnic_id
);
4624 netdev_err(bp
->dev
, "hwrm vnic %d cfg failure rc: %x\n",
4626 goto vnic_setup_err
;
4629 /* Enable RSS hashing on vnic */
4630 rc
= bnxt_hwrm_vnic_set_rss(bp
, vnic_id
, true);
4632 netdev_err(bp
->dev
, "hwrm vnic %d set rss failure rc: %x\n",
4634 goto vnic_setup_err
;
4637 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
) {
4638 rc
= bnxt_hwrm_vnic_set_hds(bp
, vnic_id
);
4640 netdev_err(bp
->dev
, "hwrm vnic %d set hds failure rc: %x\n",
4649 static int bnxt_alloc_rfs_vnics(struct bnxt
*bp
)
4651 #ifdef CONFIG_RFS_ACCEL
4654 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
4655 struct bnxt_vnic_info
*vnic
;
4656 u16 vnic_id
= i
+ 1;
4659 if (vnic_id
>= bp
->nr_vnics
)
4662 vnic
= &bp
->vnic_info
[vnic_id
];
4663 vnic
->flags
|= BNXT_VNIC_RFS_FLAG
;
4664 if (bp
->flags
& BNXT_FLAG_NEW_RSS_CAP
)
4665 vnic
->flags
|= BNXT_VNIC_RFS_NEW_RSS_FLAG
;
4666 rc
= bnxt_hwrm_vnic_alloc(bp
, vnic_id
, ring_id
, 1);
4668 netdev_err(bp
->dev
, "hwrm vnic %d alloc failure rc: %x\n",
4672 rc
= bnxt_setup_vnic(bp
, vnic_id
);
4682 /* Allow PF and VF with default VLAN to be in promiscuous mode */
4683 static bool bnxt_promisc_ok(struct bnxt
*bp
)
4685 #ifdef CONFIG_BNXT_SRIOV
4686 if (BNXT_VF(bp
) && !bp
->vf
.vlan
)
4692 static int bnxt_setup_nitroa0_vnic(struct bnxt
*bp
)
4694 unsigned int rc
= 0;
4696 rc
= bnxt_hwrm_vnic_alloc(bp
, 1, bp
->rx_nr_rings
- 1, 1);
4698 netdev_err(bp
->dev
, "Cannot allocate special vnic for NS2 A0: %x\n",
4703 rc
= bnxt_hwrm_vnic_cfg(bp
, 1);
4705 netdev_err(bp
->dev
, "Cannot allocate special vnic for NS2 A0: %x\n",
4712 static int bnxt_cfg_rx_mode(struct bnxt
*);
4713 static bool bnxt_mc_list_updated(struct bnxt
*, u32
*);
4715 static int bnxt_init_chip(struct bnxt
*bp
, bool irq_re_init
)
4717 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
4719 unsigned int rx_nr_rings
= bp
->rx_nr_rings
;
4722 rc
= bnxt_hwrm_stat_ctx_alloc(bp
);
4724 netdev_err(bp
->dev
, "hwrm stat ctx alloc failure rc: %x\n",
4730 rc
= bnxt_hwrm_ring_alloc(bp
);
4732 netdev_err(bp
->dev
, "hwrm ring alloc failure rc: %x\n", rc
);
4736 rc
= bnxt_hwrm_ring_grp_alloc(bp
);
4738 netdev_err(bp
->dev
, "hwrm_ring_grp alloc failure: %x\n", rc
);
4742 if (BNXT_CHIP_TYPE_NITRO_A0(bp
))
4745 /* default vnic 0 */
4746 rc
= bnxt_hwrm_vnic_alloc(bp
, 0, 0, rx_nr_rings
);
4748 netdev_err(bp
->dev
, "hwrm vnic alloc failure rc: %x\n", rc
);
4752 rc
= bnxt_setup_vnic(bp
, 0);
4756 if (bp
->flags
& BNXT_FLAG_RFS
) {
4757 rc
= bnxt_alloc_rfs_vnics(bp
);
4762 if (bp
->flags
& BNXT_FLAG_TPA
) {
4763 rc
= bnxt_set_tpa(bp
, true);
4769 bnxt_update_vf_mac(bp
);
4771 /* Filter for default vnic 0 */
4772 rc
= bnxt_hwrm_set_vnic_filter(bp
, 0, 0, bp
->dev
->dev_addr
);
4774 netdev_err(bp
->dev
, "HWRM vnic filter failure rc: %x\n", rc
);
4777 vnic
->uc_filter_count
= 1;
4779 vnic
->rx_mask
= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST
;
4781 if ((bp
->dev
->flags
& IFF_PROMISC
) && bnxt_promisc_ok(bp
))
4782 vnic
->rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
;
4784 if (bp
->dev
->flags
& IFF_ALLMULTI
) {
4785 vnic
->rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
;
4786 vnic
->mc_list_count
= 0;
4790 bnxt_mc_list_updated(bp
, &mask
);
4791 vnic
->rx_mask
|= mask
;
4794 rc
= bnxt_cfg_rx_mode(bp
);
4798 rc
= bnxt_hwrm_set_coal(bp
);
4800 netdev_warn(bp
->dev
, "HWRM set coalescing failure rc: %x\n",
4803 if (BNXT_CHIP_TYPE_NITRO_A0(bp
)) {
4804 rc
= bnxt_setup_nitroa0_vnic(bp
);
4806 netdev_err(bp
->dev
, "Special vnic setup failure for NS2 A0 rc: %x\n",
4811 bnxt_hwrm_func_qcfg(bp
);
4812 netdev_update_features(bp
->dev
);
4818 bnxt_hwrm_resource_free(bp
, 0, true);
4823 static int bnxt_shutdown_nic(struct bnxt
*bp
, bool irq_re_init
)
4825 bnxt_hwrm_resource_free(bp
, 1, irq_re_init
);
4829 static int bnxt_init_nic(struct bnxt
*bp
, bool irq_re_init
)
4831 bnxt_init_rx_rings(bp
);
4832 bnxt_init_tx_rings(bp
);
4833 bnxt_init_ring_grps(bp
, irq_re_init
);
4834 bnxt_init_vnics(bp
);
4836 return bnxt_init_chip(bp
, irq_re_init
);
4839 static int bnxt_set_real_num_queues(struct bnxt
*bp
)
4842 struct net_device
*dev
= bp
->dev
;
4844 rc
= netif_set_real_num_tx_queues(dev
, bp
->tx_nr_rings
);
4848 rc
= netif_set_real_num_rx_queues(dev
, bp
->rx_nr_rings
);
4852 #ifdef CONFIG_RFS_ACCEL
4853 if (bp
->flags
& BNXT_FLAG_RFS
)
4854 dev
->rx_cpu_rmap
= alloc_irq_cpu_rmap(bp
->rx_nr_rings
);
4860 static int bnxt_trim_rings(struct bnxt
*bp
, int *rx
, int *tx
, int max
,
4863 int _rx
= *rx
, _tx
= *tx
;
4866 *rx
= min_t(int, _rx
, max
);
4867 *tx
= min_t(int, _tx
, max
);
4872 while (_rx
+ _tx
> max
) {
4873 if (_rx
> _tx
&& _rx
> 1)
4884 static void bnxt_setup_msix(struct bnxt
*bp
)
4886 const int len
= sizeof(bp
->irq_tbl
[0].name
);
4887 struct net_device
*dev
= bp
->dev
;
4890 tcs
= netdev_get_num_tc(dev
);
4892 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
/ tcs
;
4893 if (bp
->tx_nr_rings_per_tc
== 0) {
4894 netdev_reset_tc(dev
);
4895 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
;
4899 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
* tcs
;
4900 for (i
= 0; i
< tcs
; i
++) {
4901 count
= bp
->tx_nr_rings_per_tc
;
4903 netdev_set_tc_queue(dev
, i
, count
, off
);
4908 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4911 if (bp
->flags
& BNXT_FLAG_SHARED_RINGS
)
4913 else if (i
< bp
->rx_nr_rings
)
4918 snprintf(bp
->irq_tbl
[i
].name
, len
, "%s-%s-%d", dev
->name
, attr
,
4920 bp
->irq_tbl
[i
].handler
= bnxt_msix
;
4924 static void bnxt_setup_inta(struct bnxt
*bp
)
4926 const int len
= sizeof(bp
->irq_tbl
[0].name
);
4928 if (netdev_get_num_tc(bp
->dev
))
4929 netdev_reset_tc(bp
->dev
);
4931 snprintf(bp
->irq_tbl
[0].name
, len
, "%s-%s-%d", bp
->dev
->name
, "TxRx",
4933 bp
->irq_tbl
[0].handler
= bnxt_inta
;
4936 static int bnxt_setup_int_mode(struct bnxt
*bp
)
4940 if (bp
->flags
& BNXT_FLAG_USING_MSIX
)
4941 bnxt_setup_msix(bp
);
4943 bnxt_setup_inta(bp
);
4945 rc
= bnxt_set_real_num_queues(bp
);
4949 #ifdef CONFIG_RFS_ACCEL
4950 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt
*bp
)
4952 #if defined(CONFIG_BNXT_SRIOV)
4954 return bp
->vf
.max_rsscos_ctxs
;
4956 return bp
->pf
.max_rsscos_ctxs
;
4959 static unsigned int bnxt_get_max_func_vnics(struct bnxt
*bp
)
4961 #if defined(CONFIG_BNXT_SRIOV)
4963 return bp
->vf
.max_vnics
;
4965 return bp
->pf
.max_vnics
;
4969 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt
*bp
)
4971 #if defined(CONFIG_BNXT_SRIOV)
4973 return bp
->vf
.max_stat_ctxs
;
4975 return bp
->pf
.max_stat_ctxs
;
4978 void bnxt_set_max_func_stat_ctxs(struct bnxt
*bp
, unsigned int max
)
4980 #if defined(CONFIG_BNXT_SRIOV)
4982 bp
->vf
.max_stat_ctxs
= max
;
4985 bp
->pf
.max_stat_ctxs
= max
;
4988 unsigned int bnxt_get_max_func_cp_rings(struct bnxt
*bp
)
4990 #if defined(CONFIG_BNXT_SRIOV)
4992 return bp
->vf
.max_cp_rings
;
4994 return bp
->pf
.max_cp_rings
;
4997 void bnxt_set_max_func_cp_rings(struct bnxt
*bp
, unsigned int max
)
4999 #if defined(CONFIG_BNXT_SRIOV)
5001 bp
->vf
.max_cp_rings
= max
;
5004 bp
->pf
.max_cp_rings
= max
;
5007 static unsigned int bnxt_get_max_func_irqs(struct bnxt
*bp
)
5009 #if defined(CONFIG_BNXT_SRIOV)
5011 return bp
->vf
.max_irqs
;
5013 return bp
->pf
.max_irqs
;
5016 void bnxt_set_max_func_irqs(struct bnxt
*bp
, unsigned int max_irqs
)
5018 #if defined(CONFIG_BNXT_SRIOV)
5020 bp
->vf
.max_irqs
= max_irqs
;
5023 bp
->pf
.max_irqs
= max_irqs
;
5026 static int bnxt_init_msix(struct bnxt
*bp
)
5028 int i
, total_vecs
, rc
= 0, min
= 1;
5029 struct msix_entry
*msix_ent
;
5031 total_vecs
= bnxt_get_max_func_irqs(bp
);
5032 msix_ent
= kcalloc(total_vecs
, sizeof(struct msix_entry
), GFP_KERNEL
);
5036 for (i
= 0; i
< total_vecs
; i
++) {
5037 msix_ent
[i
].entry
= i
;
5038 msix_ent
[i
].vector
= 0;
5041 if (!(bp
->flags
& BNXT_FLAG_SHARED_RINGS
))
5044 total_vecs
= pci_enable_msix_range(bp
->pdev
, msix_ent
, min
, total_vecs
);
5045 if (total_vecs
< 0) {
5047 goto msix_setup_exit
;
5050 bp
->irq_tbl
= kcalloc(total_vecs
, sizeof(struct bnxt_irq
), GFP_KERNEL
);
5052 for (i
= 0; i
< total_vecs
; i
++)
5053 bp
->irq_tbl
[i
].vector
= msix_ent
[i
].vector
;
5055 bp
->total_irqs
= total_vecs
;
5056 /* Trim rings based upon num of vectors allocated */
5057 rc
= bnxt_trim_rings(bp
, &bp
->rx_nr_rings
, &bp
->tx_nr_rings
,
5058 total_vecs
, min
== 1);
5060 goto msix_setup_exit
;
5062 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
;
5063 bp
->cp_nr_rings
= (min
== 1) ?
5064 max_t(int, bp
->tx_nr_rings
, bp
->rx_nr_rings
) :
5065 bp
->tx_nr_rings
+ bp
->rx_nr_rings
;
5069 goto msix_setup_exit
;
5071 bp
->flags
|= BNXT_FLAG_USING_MSIX
;
5076 netdev_err(bp
->dev
, "bnxt_init_msix err: %x\n", rc
);
5079 pci_disable_msix(bp
->pdev
);
5084 static int bnxt_init_inta(struct bnxt
*bp
)
5086 bp
->irq_tbl
= kcalloc(1, sizeof(struct bnxt_irq
), GFP_KERNEL
);
5091 bp
->rx_nr_rings
= 1;
5092 bp
->tx_nr_rings
= 1;
5093 bp
->cp_nr_rings
= 1;
5094 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
;
5095 bp
->flags
|= BNXT_FLAG_SHARED_RINGS
;
5096 bp
->irq_tbl
[0].vector
= bp
->pdev
->irq
;
5100 static int bnxt_init_int_mode(struct bnxt
*bp
)
5104 if (bp
->flags
& BNXT_FLAG_MSIX_CAP
)
5105 rc
= bnxt_init_msix(bp
);
5107 if (!(bp
->flags
& BNXT_FLAG_USING_MSIX
) && BNXT_PF(bp
)) {
5108 /* fallback to INTA */
5109 rc
= bnxt_init_inta(bp
);
5114 static void bnxt_clear_int_mode(struct bnxt
*bp
)
5116 if (bp
->flags
& BNXT_FLAG_USING_MSIX
)
5117 pci_disable_msix(bp
->pdev
);
5121 bp
->flags
&= ~BNXT_FLAG_USING_MSIX
;
5124 static void bnxt_free_irq(struct bnxt
*bp
)
5126 struct bnxt_irq
*irq
;
5129 #ifdef CONFIG_RFS_ACCEL
5130 free_irq_cpu_rmap(bp
->dev
->rx_cpu_rmap
);
5131 bp
->dev
->rx_cpu_rmap
= NULL
;
5136 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
5137 irq
= &bp
->irq_tbl
[i
];
5139 free_irq(irq
->vector
, bp
->bnapi
[i
]);
5144 static int bnxt_request_irq(struct bnxt
*bp
)
5147 unsigned long flags
= 0;
5148 #ifdef CONFIG_RFS_ACCEL
5149 struct cpu_rmap
*rmap
= bp
->dev
->rx_cpu_rmap
;
5152 if (!(bp
->flags
& BNXT_FLAG_USING_MSIX
))
5153 flags
= IRQF_SHARED
;
5155 for (i
= 0, j
= 0; i
< bp
->cp_nr_rings
; i
++) {
5156 struct bnxt_irq
*irq
= &bp
->irq_tbl
[i
];
5157 #ifdef CONFIG_RFS_ACCEL
5158 if (rmap
&& bp
->bnapi
[i
]->rx_ring
) {
5159 rc
= irq_cpu_rmap_add(rmap
, irq
->vector
);
5161 netdev_warn(bp
->dev
, "failed adding irq rmap for ring %d\n",
5166 rc
= request_irq(irq
->vector
, irq
->handler
, flags
, irq
->name
,
5176 static void bnxt_del_napi(struct bnxt
*bp
)
5183 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
5184 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
5186 napi_hash_del(&bnapi
->napi
);
5187 netif_napi_del(&bnapi
->napi
);
5189 /* We called napi_hash_del() before netif_napi_del(), we need
5190 * to respect an RCU grace period before freeing napi structures.
5195 static void bnxt_init_napi(struct bnxt
*bp
)
5198 unsigned int cp_nr_rings
= bp
->cp_nr_rings
;
5199 struct bnxt_napi
*bnapi
;
5201 if (bp
->flags
& BNXT_FLAG_USING_MSIX
) {
5202 if (BNXT_CHIP_TYPE_NITRO_A0(bp
))
5204 for (i
= 0; i
< cp_nr_rings
; i
++) {
5205 bnapi
= bp
->bnapi
[i
];
5206 netif_napi_add(bp
->dev
, &bnapi
->napi
,
5209 if (BNXT_CHIP_TYPE_NITRO_A0(bp
)) {
5210 bnapi
= bp
->bnapi
[cp_nr_rings
];
5211 netif_napi_add(bp
->dev
, &bnapi
->napi
,
5212 bnxt_poll_nitroa0
, 64);
5215 bnapi
= bp
->bnapi
[0];
5216 netif_napi_add(bp
->dev
, &bnapi
->napi
, bnxt_poll
, 64);
5220 static void bnxt_disable_napi(struct bnxt
*bp
)
5227 for (i
= 0; i
< bp
->cp_nr_rings
; i
++)
5228 napi_disable(&bp
->bnapi
[i
]->napi
);
5231 static void bnxt_enable_napi(struct bnxt
*bp
)
5235 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
5236 bp
->bnapi
[i
]->in_reset
= false;
5237 napi_enable(&bp
->bnapi
[i
]->napi
);
5241 void bnxt_tx_disable(struct bnxt
*bp
)
5244 struct bnxt_tx_ring_info
*txr
;
5245 struct netdev_queue
*txq
;
5248 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
5249 txr
= &bp
->tx_ring
[i
];
5250 txq
= netdev_get_tx_queue(bp
->dev
, i
);
5251 txr
->dev_state
= BNXT_DEV_STATE_CLOSING
;
5254 /* Stop all TX queues */
5255 netif_tx_disable(bp
->dev
);
5256 netif_carrier_off(bp
->dev
);
5259 void bnxt_tx_enable(struct bnxt
*bp
)
5262 struct bnxt_tx_ring_info
*txr
;
5263 struct netdev_queue
*txq
;
5265 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
5266 txr
= &bp
->tx_ring
[i
];
5267 txq
= netdev_get_tx_queue(bp
->dev
, i
);
5270 netif_tx_wake_all_queues(bp
->dev
);
5271 if (bp
->link_info
.link_up
)
5272 netif_carrier_on(bp
->dev
);
5275 static void bnxt_report_link(struct bnxt
*bp
)
5277 if (bp
->link_info
.link_up
) {
5279 const char *flow_ctrl
;
5282 netif_carrier_on(bp
->dev
);
5283 if (bp
->link_info
.duplex
== BNXT_LINK_DUPLEX_FULL
)
5287 if (bp
->link_info
.pause
== BNXT_LINK_PAUSE_BOTH
)
5288 flow_ctrl
= "ON - receive & transmit";
5289 else if (bp
->link_info
.pause
== BNXT_LINK_PAUSE_TX
)
5290 flow_ctrl
= "ON - transmit";
5291 else if (bp
->link_info
.pause
== BNXT_LINK_PAUSE_RX
)
5292 flow_ctrl
= "ON - receive";
5295 speed
= bnxt_fw_to_ethtool_speed(bp
->link_info
.link_speed
);
5296 netdev_info(bp
->dev
, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
5297 speed
, duplex
, flow_ctrl
);
5298 if (bp
->flags
& BNXT_FLAG_EEE_CAP
)
5299 netdev_info(bp
->dev
, "EEE is %s\n",
5300 bp
->eee
.eee_active
? "active" :
5303 netif_carrier_off(bp
->dev
);
5304 netdev_err(bp
->dev
, "NIC Link is Down\n");
5308 static int bnxt_hwrm_phy_qcaps(struct bnxt
*bp
)
5311 struct hwrm_port_phy_qcaps_input req
= {0};
5312 struct hwrm_port_phy_qcaps_output
*resp
= bp
->hwrm_cmd_resp_addr
;
5313 struct bnxt_link_info
*link_info
= &bp
->link_info
;
5315 if (bp
->hwrm_spec_code
< 0x10201)
5318 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_QCAPS
, -1, -1);
5320 mutex_lock(&bp
->hwrm_cmd_lock
);
5321 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
5323 goto hwrm_phy_qcaps_exit
;
5325 if (resp
->eee_supported
& PORT_PHY_QCAPS_RESP_EEE_SUPPORTED
) {
5326 struct ethtool_eee
*eee
= &bp
->eee
;
5327 u16 fw_speeds
= le16_to_cpu(resp
->supported_speeds_eee_mode
);
5329 bp
->flags
|= BNXT_FLAG_EEE_CAP
;
5330 eee
->supported
= _bnxt_fw_to_ethtool_adv_spds(fw_speeds
, 0);
5331 bp
->lpi_tmr_lo
= le32_to_cpu(resp
->tx_lpi_timer_low
) &
5332 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK
;
5333 bp
->lpi_tmr_hi
= le32_to_cpu(resp
->valid_tx_lpi_timer_high
) &
5334 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK
;
5336 link_info
->support_auto_speeds
=
5337 le16_to_cpu(resp
->supported_speeds_auto_mode
);
5339 hwrm_phy_qcaps_exit
:
5340 mutex_unlock(&bp
->hwrm_cmd_lock
);
5344 static int bnxt_update_link(struct bnxt
*bp
, bool chng_link_state
)
5347 struct bnxt_link_info
*link_info
= &bp
->link_info
;
5348 struct hwrm_port_phy_qcfg_input req
= {0};
5349 struct hwrm_port_phy_qcfg_output
*resp
= bp
->hwrm_cmd_resp_addr
;
5350 u8 link_up
= link_info
->link_up
;
5353 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_QCFG
, -1, -1);
5355 mutex_lock(&bp
->hwrm_cmd_lock
);
5356 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
5358 mutex_unlock(&bp
->hwrm_cmd_lock
);
5362 memcpy(&link_info
->phy_qcfg_resp
, resp
, sizeof(*resp
));
5363 link_info
->phy_link_status
= resp
->link
;
5364 link_info
->duplex
= resp
->duplex
;
5365 link_info
->pause
= resp
->pause
;
5366 link_info
->auto_mode
= resp
->auto_mode
;
5367 link_info
->auto_pause_setting
= resp
->auto_pause
;
5368 link_info
->lp_pause
= resp
->link_partner_adv_pause
;
5369 link_info
->force_pause_setting
= resp
->force_pause
;
5370 link_info
->duplex_setting
= resp
->duplex
;
5371 if (link_info
->phy_link_status
== BNXT_LINK_LINK
)
5372 link_info
->link_speed
= le16_to_cpu(resp
->link_speed
);
5374 link_info
->link_speed
= 0;
5375 link_info
->force_link_speed
= le16_to_cpu(resp
->force_link_speed
);
5376 link_info
->support_speeds
= le16_to_cpu(resp
->support_speeds
);
5377 link_info
->auto_link_speeds
= le16_to_cpu(resp
->auto_link_speed_mask
);
5378 link_info
->lp_auto_link_speeds
=
5379 le16_to_cpu(resp
->link_partner_adv_speeds
);
5380 link_info
->preemphasis
= le32_to_cpu(resp
->preemphasis
);
5381 link_info
->phy_ver
[0] = resp
->phy_maj
;
5382 link_info
->phy_ver
[1] = resp
->phy_min
;
5383 link_info
->phy_ver
[2] = resp
->phy_bld
;
5384 link_info
->media_type
= resp
->media_type
;
5385 link_info
->phy_type
= resp
->phy_type
;
5386 link_info
->transceiver
= resp
->xcvr_pkg_type
;
5387 link_info
->phy_addr
= resp
->eee_config_phy_addr
&
5388 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK
;
5389 link_info
->module_status
= resp
->module_status
;
5391 if (bp
->flags
& BNXT_FLAG_EEE_CAP
) {
5392 struct ethtool_eee
*eee
= &bp
->eee
;
5395 eee
->eee_active
= 0;
5396 if (resp
->eee_config_phy_addr
&
5397 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE
) {
5398 eee
->eee_active
= 1;
5399 fw_speeds
= le16_to_cpu(
5400 resp
->link_partner_adv_eee_link_speed_mask
);
5401 eee
->lp_advertised
=
5402 _bnxt_fw_to_ethtool_adv_spds(fw_speeds
, 0);
5405 /* Pull initial EEE config */
5406 if (!chng_link_state
) {
5407 if (resp
->eee_config_phy_addr
&
5408 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED
)
5409 eee
->eee_enabled
= 1;
5411 fw_speeds
= le16_to_cpu(resp
->adv_eee_link_speed_mask
);
5413 _bnxt_fw_to_ethtool_adv_spds(fw_speeds
, 0);
5415 if (resp
->eee_config_phy_addr
&
5416 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI
) {
5419 eee
->tx_lpi_enabled
= 1;
5420 tmr
= resp
->xcvr_identifier_type_tx_lpi_timer
;
5421 eee
->tx_lpi_timer
= le32_to_cpu(tmr
) &
5422 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK
;
5426 /* TODO: need to add more logic to report VF link */
5427 if (chng_link_state
) {
5428 if (link_info
->phy_link_status
== BNXT_LINK_LINK
)
5429 link_info
->link_up
= 1;
5431 link_info
->link_up
= 0;
5432 if (link_up
!= link_info
->link_up
)
5433 bnxt_report_link(bp
);
5435 /* alwasy link down if not require to update link state */
5436 link_info
->link_up
= 0;
5438 mutex_unlock(&bp
->hwrm_cmd_lock
);
5440 diff
= link_info
->support_auto_speeds
^ link_info
->advertising
;
5441 if ((link_info
->support_auto_speeds
| diff
) !=
5442 link_info
->support_auto_speeds
) {
5443 /* An advertised speed is no longer supported, so we need to
5444 * update the advertisement settings. Caller holds RTNL
5445 * so we can modify link settings.
5447 link_info
->advertising
= link_info
->support_auto_speeds
;
5448 if (link_info
->autoneg
& BNXT_AUTONEG_SPEED
)
5449 bnxt_hwrm_set_link_setting(bp
, true, false);
5454 static void bnxt_get_port_module_status(struct bnxt
*bp
)
5456 struct bnxt_link_info
*link_info
= &bp
->link_info
;
5457 struct hwrm_port_phy_qcfg_output
*resp
= &link_info
->phy_qcfg_resp
;
5460 if (bnxt_update_link(bp
, true))
5463 module_status
= link_info
->module_status
;
5464 switch (module_status
) {
5465 case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX
:
5466 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN
:
5467 case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG
:
5468 netdev_warn(bp
->dev
, "Unqualified SFP+ module detected on port %d\n",
5470 if (bp
->hwrm_spec_code
>= 0x10201) {
5471 netdev_warn(bp
->dev
, "Module part number %s\n",
5472 resp
->phy_vendor_partnumber
);
5474 if (module_status
== PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX
)
5475 netdev_warn(bp
->dev
, "TX is disabled\n");
5476 if (module_status
== PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN
)
5477 netdev_warn(bp
->dev
, "SFP+ module is shutdown\n");
5482 bnxt_hwrm_set_pause_common(struct bnxt
*bp
, struct hwrm_port_phy_cfg_input
*req
)
5484 if (bp
->link_info
.autoneg
& BNXT_AUTONEG_FLOW_CTRL
) {
5485 if (bp
->hwrm_spec_code
>= 0x10201)
5487 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE
;
5488 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_RX
)
5489 req
->auto_pause
|= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX
;
5490 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_TX
)
5491 req
->auto_pause
|= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX
;
5493 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE
);
5495 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_RX
)
5496 req
->force_pause
|= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX
;
5497 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_TX
)
5498 req
->force_pause
|= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX
;
5500 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE
);
5501 if (bp
->hwrm_spec_code
>= 0x10201) {
5502 req
->auto_pause
= req
->force_pause
;
5503 req
->enables
|= cpu_to_le32(
5504 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE
);
5509 static void bnxt_hwrm_set_link_common(struct bnxt
*bp
,
5510 struct hwrm_port_phy_cfg_input
*req
)
5512 u8 autoneg
= bp
->link_info
.autoneg
;
5513 u16 fw_link_speed
= bp
->link_info
.req_link_speed
;
5514 u16 advertising
= bp
->link_info
.advertising
;
5516 if (autoneg
& BNXT_AUTONEG_SPEED
) {
5518 PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK
;
5520 req
->enables
|= cpu_to_le32(
5521 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK
);
5522 req
->auto_link_speed_mask
= cpu_to_le16(advertising
);
5524 req
->enables
|= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE
);
5526 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG
);
5528 req
->force_link_speed
= cpu_to_le16(fw_link_speed
);
5529 req
->flags
|= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE
);
5532 /* tell chimp that the setting takes effect immediately */
5533 req
->flags
|= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY
);
5536 int bnxt_hwrm_set_pause(struct bnxt
*bp
)
5538 struct hwrm_port_phy_cfg_input req
= {0};
5541 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_CFG
, -1, -1);
5542 bnxt_hwrm_set_pause_common(bp
, &req
);
5544 if ((bp
->link_info
.autoneg
& BNXT_AUTONEG_FLOW_CTRL
) ||
5545 bp
->link_info
.force_link_chng
)
5546 bnxt_hwrm_set_link_common(bp
, &req
);
5548 mutex_lock(&bp
->hwrm_cmd_lock
);
5549 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
5550 if (!rc
&& !(bp
->link_info
.autoneg
& BNXT_AUTONEG_FLOW_CTRL
)) {
5551 /* since changing of pause setting doesn't trigger any link
5552 * change event, the driver needs to update the current pause
5553 * result upon successfully return of the phy_cfg command
5555 bp
->link_info
.pause
=
5556 bp
->link_info
.force_pause_setting
= bp
->link_info
.req_flow_ctrl
;
5557 bp
->link_info
.auto_pause_setting
= 0;
5558 if (!bp
->link_info
.force_link_chng
)
5559 bnxt_report_link(bp
);
5561 bp
->link_info
.force_link_chng
= false;
5562 mutex_unlock(&bp
->hwrm_cmd_lock
);
5566 static void bnxt_hwrm_set_eee(struct bnxt
*bp
,
5567 struct hwrm_port_phy_cfg_input
*req
)
5569 struct ethtool_eee
*eee
= &bp
->eee
;
5571 if (eee
->eee_enabled
) {
5573 u32 flags
= PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE
;
5575 if (eee
->tx_lpi_enabled
)
5576 flags
|= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE
;
5578 flags
|= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE
;
5580 req
->flags
|= cpu_to_le32(flags
);
5581 eee_speeds
= bnxt_get_fw_auto_link_speeds(eee
->advertised
);
5582 req
->eee_link_speed_mask
= cpu_to_le16(eee_speeds
);
5583 req
->tx_lpi_timer
= cpu_to_le32(eee
->tx_lpi_timer
);
5585 req
->flags
|= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE
);
5589 int bnxt_hwrm_set_link_setting(struct bnxt
*bp
, bool set_pause
, bool set_eee
)
5591 struct hwrm_port_phy_cfg_input req
= {0};
5593 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_CFG
, -1, -1);
5595 bnxt_hwrm_set_pause_common(bp
, &req
);
5597 bnxt_hwrm_set_link_common(bp
, &req
);
5600 bnxt_hwrm_set_eee(bp
, &req
);
5601 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
5604 static int bnxt_hwrm_shutdown_link(struct bnxt
*bp
)
5606 struct hwrm_port_phy_cfg_input req
= {0};
5608 if (!BNXT_SINGLE_PF(bp
))
5611 if (pci_num_vf(bp
->pdev
))
5614 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_CFG
, -1, -1);
5615 req
.flags
= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN
);
5616 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
5619 static int bnxt_hwrm_port_led_qcaps(struct bnxt
*bp
)
5621 struct hwrm_port_led_qcaps_output
*resp
= bp
->hwrm_cmd_resp_addr
;
5622 struct hwrm_port_led_qcaps_input req
= {0};
5623 struct bnxt_pf_info
*pf
= &bp
->pf
;
5626 if (BNXT_VF(bp
) || bp
->hwrm_spec_code
< 0x10601)
5629 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_LED_QCAPS
, -1, -1);
5630 req
.port_id
= cpu_to_le16(pf
->port_id
);
5631 mutex_lock(&bp
->hwrm_cmd_lock
);
5632 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
5634 mutex_unlock(&bp
->hwrm_cmd_lock
);
5637 if (resp
->num_leds
> 0 && resp
->num_leds
< BNXT_MAX_LED
) {
5640 bp
->num_leds
= resp
->num_leds
;
5641 memcpy(bp
->leds
, &resp
->led0_id
, sizeof(bp
->leds
[0]) *
5643 for (i
= 0; i
< bp
->num_leds
; i
++) {
5644 struct bnxt_led_info
*led
= &bp
->leds
[i
];
5645 __le16 caps
= led
->led_state_caps
;
5647 if (!led
->led_group_id
||
5648 !BNXT_LED_ALT_BLINK_CAP(caps
)) {
5654 mutex_unlock(&bp
->hwrm_cmd_lock
);
5658 static bool bnxt_eee_config_ok(struct bnxt
*bp
)
5660 struct ethtool_eee
*eee
= &bp
->eee
;
5661 struct bnxt_link_info
*link_info
= &bp
->link_info
;
5663 if (!(bp
->flags
& BNXT_FLAG_EEE_CAP
))
5666 if (eee
->eee_enabled
) {
5668 _bnxt_fw_to_ethtool_adv_spds(link_info
->advertising
, 0);
5670 if (!(link_info
->autoneg
& BNXT_AUTONEG_SPEED
)) {
5671 eee
->eee_enabled
= 0;
5674 if (eee
->advertised
& ~advertising
) {
5675 eee
->advertised
= advertising
& eee
->supported
;
5682 static int bnxt_update_phy_setting(struct bnxt
*bp
)
5685 bool update_link
= false;
5686 bool update_pause
= false;
5687 bool update_eee
= false;
5688 struct bnxt_link_info
*link_info
= &bp
->link_info
;
5690 rc
= bnxt_update_link(bp
, true);
5692 netdev_err(bp
->dev
, "failed to update link (rc: %x)\n",
5696 if ((link_info
->autoneg
& BNXT_AUTONEG_FLOW_CTRL
) &&
5697 (link_info
->auto_pause_setting
& BNXT_LINK_PAUSE_BOTH
) !=
5698 link_info
->req_flow_ctrl
)
5699 update_pause
= true;
5700 if (!(link_info
->autoneg
& BNXT_AUTONEG_FLOW_CTRL
) &&
5701 link_info
->force_pause_setting
!= link_info
->req_flow_ctrl
)
5702 update_pause
= true;
5703 if (!(link_info
->autoneg
& BNXT_AUTONEG_SPEED
)) {
5704 if (BNXT_AUTO_MODE(link_info
->auto_mode
))
5706 if (link_info
->req_link_speed
!= link_info
->force_link_speed
)
5708 if (link_info
->req_duplex
!= link_info
->duplex_setting
)
5711 if (link_info
->auto_mode
== BNXT_LINK_AUTO_NONE
)
5713 if (link_info
->advertising
!= link_info
->auto_link_speeds
)
5717 /* The last close may have shutdown the link, so need to call
5718 * PHY_CFG to bring it back up.
5720 if (!netif_carrier_ok(bp
->dev
))
5723 if (!bnxt_eee_config_ok(bp
))
5727 rc
= bnxt_hwrm_set_link_setting(bp
, update_pause
, update_eee
);
5728 else if (update_pause
)
5729 rc
= bnxt_hwrm_set_pause(bp
);
5731 netdev_err(bp
->dev
, "failed to update phy setting (rc: %x)\n",
5739 /* Common routine to pre-map certain register block to different GRC window.
5740 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
5741 * in PF and 3 windows in VF that can be customized to map in different
5744 static void bnxt_preset_reg_win(struct bnxt
*bp
)
5747 /* CAG registers map to GRC window #4 */
5748 writel(BNXT_CAG_REG_BASE
,
5749 bp
->bar0
+ BNXT_GRCPF_REG_WINDOW_BASE_OUT
+ 12);
5753 static int __bnxt_open_nic(struct bnxt
*bp
, bool irq_re_init
, bool link_re_init
)
5757 bnxt_preset_reg_win(bp
);
5758 netif_carrier_off(bp
->dev
);
5760 rc
= bnxt_setup_int_mode(bp
);
5762 netdev_err(bp
->dev
, "bnxt_setup_int_mode err: %x\n",
5767 if ((bp
->flags
& BNXT_FLAG_RFS
) &&
5768 !(bp
->flags
& BNXT_FLAG_USING_MSIX
)) {
5769 /* disable RFS if falling back to INTA */
5770 bp
->dev
->hw_features
&= ~NETIF_F_NTUPLE
;
5771 bp
->flags
&= ~BNXT_FLAG_RFS
;
5774 rc
= bnxt_alloc_mem(bp
, irq_re_init
);
5776 netdev_err(bp
->dev
, "bnxt_alloc_mem err: %x\n", rc
);
5777 goto open_err_free_mem
;
5782 rc
= bnxt_request_irq(bp
);
5784 netdev_err(bp
->dev
, "bnxt_request_irq err: %x\n", rc
);
5789 bnxt_enable_napi(bp
);
5791 rc
= bnxt_init_nic(bp
, irq_re_init
);
5793 netdev_err(bp
->dev
, "bnxt_init_nic err: %x\n", rc
);
5798 rc
= bnxt_update_phy_setting(bp
);
5800 netdev_warn(bp
->dev
, "failed to update phy settings\n");
5804 udp_tunnel_get_rx_info(bp
->dev
);
5806 set_bit(BNXT_STATE_OPEN
, &bp
->state
);
5807 bnxt_enable_int(bp
);
5808 /* Enable TX queues */
5810 mod_timer(&bp
->timer
, jiffies
+ bp
->current_interval
);
5811 /* Poll link status and check for SFP+ module status */
5812 bnxt_get_port_module_status(bp
);
5817 bnxt_disable_napi(bp
);
5823 bnxt_free_mem(bp
, true);
5827 /* rtnl_lock held */
5828 int bnxt_open_nic(struct bnxt
*bp
, bool irq_re_init
, bool link_re_init
)
5832 rc
= __bnxt_open_nic(bp
, irq_re_init
, link_re_init
);
5834 netdev_err(bp
->dev
, "nic open fail (rc: %x)\n", rc
);
5840 static int bnxt_open(struct net_device
*dev
)
5842 struct bnxt
*bp
= netdev_priv(dev
);
5844 return __bnxt_open_nic(bp
, true, true);
5847 int bnxt_close_nic(struct bnxt
*bp
, bool irq_re_init
, bool link_re_init
)
5851 #ifdef CONFIG_BNXT_SRIOV
5852 if (bp
->sriov_cfg
) {
5853 rc
= wait_event_interruptible_timeout(bp
->sriov_cfg_wait
,
5855 BNXT_SRIOV_CFG_WAIT_TMO
);
5857 netdev_warn(bp
->dev
, "timeout waiting for SRIOV config operation to complete!\n");
5860 /* Change device state to avoid TX queue wake up's */
5861 bnxt_tx_disable(bp
);
5863 clear_bit(BNXT_STATE_OPEN
, &bp
->state
);
5864 smp_mb__after_atomic();
5865 while (test_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
))
5868 /* Flush rings and and disable interrupts */
5869 bnxt_shutdown_nic(bp
, irq_re_init
);
5871 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
5873 bnxt_disable_napi(bp
);
5874 del_timer_sync(&bp
->timer
);
5881 bnxt_free_mem(bp
, irq_re_init
);
5885 static int bnxt_close(struct net_device
*dev
)
5887 struct bnxt
*bp
= netdev_priv(dev
);
5889 bnxt_close_nic(bp
, true, true);
5890 bnxt_hwrm_shutdown_link(bp
);
5894 /* rtnl_lock held */
5895 static int bnxt_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
5901 if (!netif_running(dev
))
5908 if (!netif_running(dev
))
5921 bnxt_get_stats64(struct net_device
*dev
, struct rtnl_link_stats64
*stats
)
5924 struct bnxt
*bp
= netdev_priv(dev
);
5929 /* TODO check if we need to synchronize with bnxt_close path */
5930 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
5931 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
5932 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
5933 struct ctx_hw_stats
*hw_stats
= cpr
->hw_stats
;
5935 stats
->rx_packets
+= le64_to_cpu(hw_stats
->rx_ucast_pkts
);
5936 stats
->rx_packets
+= le64_to_cpu(hw_stats
->rx_mcast_pkts
);
5937 stats
->rx_packets
+= le64_to_cpu(hw_stats
->rx_bcast_pkts
);
5939 stats
->tx_packets
+= le64_to_cpu(hw_stats
->tx_ucast_pkts
);
5940 stats
->tx_packets
+= le64_to_cpu(hw_stats
->tx_mcast_pkts
);
5941 stats
->tx_packets
+= le64_to_cpu(hw_stats
->tx_bcast_pkts
);
5943 stats
->rx_bytes
+= le64_to_cpu(hw_stats
->rx_ucast_bytes
);
5944 stats
->rx_bytes
+= le64_to_cpu(hw_stats
->rx_mcast_bytes
);
5945 stats
->rx_bytes
+= le64_to_cpu(hw_stats
->rx_bcast_bytes
);
5947 stats
->tx_bytes
+= le64_to_cpu(hw_stats
->tx_ucast_bytes
);
5948 stats
->tx_bytes
+= le64_to_cpu(hw_stats
->tx_mcast_bytes
);
5949 stats
->tx_bytes
+= le64_to_cpu(hw_stats
->tx_bcast_bytes
);
5951 stats
->rx_missed_errors
+=
5952 le64_to_cpu(hw_stats
->rx_discard_pkts
);
5954 stats
->multicast
+= le64_to_cpu(hw_stats
->rx_mcast_pkts
);
5956 stats
->tx_dropped
+= le64_to_cpu(hw_stats
->tx_drop_pkts
);
5959 if (bp
->flags
& BNXT_FLAG_PORT_STATS
) {
5960 struct rx_port_stats
*rx
= bp
->hw_rx_port_stats
;
5961 struct tx_port_stats
*tx
= bp
->hw_tx_port_stats
;
5963 stats
->rx_crc_errors
= le64_to_cpu(rx
->rx_fcs_err_frames
);
5964 stats
->rx_frame_errors
= le64_to_cpu(rx
->rx_align_err_frames
);
5965 stats
->rx_length_errors
= le64_to_cpu(rx
->rx_undrsz_frames
) +
5966 le64_to_cpu(rx
->rx_ovrsz_frames
) +
5967 le64_to_cpu(rx
->rx_runt_frames
);
5968 stats
->rx_errors
= le64_to_cpu(rx
->rx_false_carrier_frames
) +
5969 le64_to_cpu(rx
->rx_jbr_frames
);
5970 stats
->collisions
= le64_to_cpu(tx
->tx_total_collisions
);
5971 stats
->tx_fifo_errors
= le64_to_cpu(tx
->tx_fifo_underruns
);
5972 stats
->tx_errors
= le64_to_cpu(tx
->tx_err
);
5976 static bool bnxt_mc_list_updated(struct bnxt
*bp
, u32
*rx_mask
)
5978 struct net_device
*dev
= bp
->dev
;
5979 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
5980 struct netdev_hw_addr
*ha
;
5983 bool update
= false;
5986 netdev_for_each_mc_addr(ha
, dev
) {
5987 if (mc_count
>= BNXT_MAX_MC_ADDRS
) {
5988 *rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
;
5989 vnic
->mc_list_count
= 0;
5993 if (!ether_addr_equal(haddr
, vnic
->mc_list
+ off
)) {
5994 memcpy(vnic
->mc_list
+ off
, haddr
, ETH_ALEN
);
6001 *rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST
;
6003 if (mc_count
!= vnic
->mc_list_count
) {
6004 vnic
->mc_list_count
= mc_count
;
6010 static bool bnxt_uc_list_updated(struct bnxt
*bp
)
6012 struct net_device
*dev
= bp
->dev
;
6013 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
6014 struct netdev_hw_addr
*ha
;
6017 if (netdev_uc_count(dev
) != (vnic
->uc_filter_count
- 1))
6020 netdev_for_each_uc_addr(ha
, dev
) {
6021 if (!ether_addr_equal(ha
->addr
, vnic
->uc_list
+ off
))
6029 static void bnxt_set_rx_mode(struct net_device
*dev
)
6031 struct bnxt
*bp
= netdev_priv(dev
);
6032 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
6033 u32 mask
= vnic
->rx_mask
;
6034 bool mc_update
= false;
6037 if (!netif_running(dev
))
6040 mask
&= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
|
6041 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST
|
6042 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
);
6044 if ((dev
->flags
& IFF_PROMISC
) && bnxt_promisc_ok(bp
))
6045 mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
;
6047 uc_update
= bnxt_uc_list_updated(bp
);
6049 if (dev
->flags
& IFF_ALLMULTI
) {
6050 mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
;
6051 vnic
->mc_list_count
= 0;
6053 mc_update
= bnxt_mc_list_updated(bp
, &mask
);
6056 if (mask
!= vnic
->rx_mask
|| uc_update
|| mc_update
) {
6057 vnic
->rx_mask
= mask
;
6059 set_bit(BNXT_RX_MASK_SP_EVENT
, &bp
->sp_event
);
6060 schedule_work(&bp
->sp_task
);
6064 static int bnxt_cfg_rx_mode(struct bnxt
*bp
)
6066 struct net_device
*dev
= bp
->dev
;
6067 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
6068 struct netdev_hw_addr
*ha
;
6072 netif_addr_lock_bh(dev
);
6073 uc_update
= bnxt_uc_list_updated(bp
);
6074 netif_addr_unlock_bh(dev
);
6079 mutex_lock(&bp
->hwrm_cmd_lock
);
6080 for (i
= 1; i
< vnic
->uc_filter_count
; i
++) {
6081 struct hwrm_cfa_l2_filter_free_input req
= {0};
6083 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_L2_FILTER_FREE
, -1,
6086 req
.l2_filter_id
= vnic
->fw_l2_filter_id
[i
];
6088 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
6091 mutex_unlock(&bp
->hwrm_cmd_lock
);
6093 vnic
->uc_filter_count
= 1;
6095 netif_addr_lock_bh(dev
);
6096 if (netdev_uc_count(dev
) > (BNXT_MAX_UC_ADDRS
- 1)) {
6097 vnic
->rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
;
6099 netdev_for_each_uc_addr(ha
, dev
) {
6100 memcpy(vnic
->uc_list
+ off
, ha
->addr
, ETH_ALEN
);
6102 vnic
->uc_filter_count
++;
6105 netif_addr_unlock_bh(dev
);
6107 for (i
= 1, off
= 0; i
< vnic
->uc_filter_count
; i
++, off
+= ETH_ALEN
) {
6108 rc
= bnxt_hwrm_set_vnic_filter(bp
, 0, i
, vnic
->uc_list
+ off
);
6110 netdev_err(bp
->dev
, "HWRM vnic filter failure rc: %x\n",
6112 vnic
->uc_filter_count
= i
;
6118 rc
= bnxt_hwrm_cfa_l2_set_rx_mask(bp
, 0);
6120 netdev_err(bp
->dev
, "HWRM cfa l2 rx mask failure rc: %x\n",
6126 /* If the chip and firmware supports RFS */
6127 static bool bnxt_rfs_supported(struct bnxt
*bp
)
6129 if (BNXT_PF(bp
) && !BNXT_CHIP_TYPE_NITRO_A0(bp
))
6131 if (bp
->flags
& BNXT_FLAG_NEW_RSS_CAP
)
6136 /* If runtime conditions support RFS */
6137 static bool bnxt_rfs_capable(struct bnxt
*bp
)
6139 #ifdef CONFIG_RFS_ACCEL
6140 int vnics
, max_vnics
, max_rss_ctxs
;
6142 if (BNXT_VF(bp
) || !(bp
->flags
& BNXT_FLAG_MSIX_CAP
))
6145 vnics
= 1 + bp
->rx_nr_rings
;
6146 max_vnics
= bnxt_get_max_func_vnics(bp
);
6147 max_rss_ctxs
= bnxt_get_max_func_rss_ctxs(bp
);
6149 /* RSS contexts not a limiting factor */
6150 if (bp
->flags
& BNXT_FLAG_NEW_RSS_CAP
)
6151 max_rss_ctxs
= max_vnics
;
6152 if (vnics
> max_vnics
|| vnics
> max_rss_ctxs
) {
6153 netdev_warn(bp
->dev
,
6154 "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
6155 min(max_rss_ctxs
- 1, max_vnics
- 1));
6165 static netdev_features_t
bnxt_fix_features(struct net_device
*dev
,
6166 netdev_features_t features
)
6168 struct bnxt
*bp
= netdev_priv(dev
);
6170 if ((features
& NETIF_F_NTUPLE
) && !bnxt_rfs_capable(bp
))
6171 features
&= ~NETIF_F_NTUPLE
;
6173 /* Both CTAG and STAG VLAN accelaration on the RX side have to be
6174 * turned on or off together.
6176 if ((features
& (NETIF_F_HW_VLAN_CTAG_RX
| NETIF_F_HW_VLAN_STAG_RX
)) !=
6177 (NETIF_F_HW_VLAN_CTAG_RX
| NETIF_F_HW_VLAN_STAG_RX
)) {
6178 if (dev
->features
& NETIF_F_HW_VLAN_CTAG_RX
)
6179 features
&= ~(NETIF_F_HW_VLAN_CTAG_RX
|
6180 NETIF_F_HW_VLAN_STAG_RX
);
6182 features
|= NETIF_F_HW_VLAN_CTAG_RX
|
6183 NETIF_F_HW_VLAN_STAG_RX
;
6185 #ifdef CONFIG_BNXT_SRIOV
6188 features
&= ~(NETIF_F_HW_VLAN_CTAG_RX
|
6189 NETIF_F_HW_VLAN_STAG_RX
);
6196 static int bnxt_set_features(struct net_device
*dev
, netdev_features_t features
)
6198 struct bnxt
*bp
= netdev_priv(dev
);
6199 u32 flags
= bp
->flags
;
6202 bool re_init
= false;
6203 bool update_tpa
= false;
6205 flags
&= ~BNXT_FLAG_ALL_CONFIG_FEATS
;
6206 if ((features
& NETIF_F_GRO
) && !BNXT_CHIP_TYPE_NITRO_A0(bp
))
6207 flags
|= BNXT_FLAG_GRO
;
6208 if (features
& NETIF_F_LRO
)
6209 flags
|= BNXT_FLAG_LRO
;
6211 if (bp
->flags
& BNXT_FLAG_NO_AGG_RINGS
)
6212 flags
&= ~BNXT_FLAG_TPA
;
6214 if (features
& NETIF_F_HW_VLAN_CTAG_RX
)
6215 flags
|= BNXT_FLAG_STRIP_VLAN
;
6217 if (features
& NETIF_F_NTUPLE
)
6218 flags
|= BNXT_FLAG_RFS
;
6220 changes
= flags
^ bp
->flags
;
6221 if (changes
& BNXT_FLAG_TPA
) {
6223 if ((bp
->flags
& BNXT_FLAG_TPA
) == 0 ||
6224 (flags
& BNXT_FLAG_TPA
) == 0)
6228 if (changes
& ~BNXT_FLAG_TPA
)
6231 if (flags
!= bp
->flags
) {
6232 u32 old_flags
= bp
->flags
;
6236 if (!test_bit(BNXT_STATE_OPEN
, &bp
->state
)) {
6238 bnxt_set_ring_params(bp
);
6243 bnxt_close_nic(bp
, false, false);
6245 bnxt_set_ring_params(bp
);
6247 return bnxt_open_nic(bp
, false, false);
6250 rc
= bnxt_set_tpa(bp
,
6251 (flags
& BNXT_FLAG_TPA
) ?
6254 bp
->flags
= old_flags
;
6260 static void bnxt_dump_tx_sw_state(struct bnxt_napi
*bnapi
)
6262 struct bnxt_tx_ring_info
*txr
= bnapi
->tx_ring
;
6263 int i
= bnapi
->index
;
6268 netdev_info(bnapi
->bp
->dev
, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
6269 i
, txr
->tx_ring_struct
.fw_ring_id
, txr
->tx_prod
,
6273 static void bnxt_dump_rx_sw_state(struct bnxt_napi
*bnapi
)
6275 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
6276 int i
= bnapi
->index
;
6281 netdev_info(bnapi
->bp
->dev
, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
6282 i
, rxr
->rx_ring_struct
.fw_ring_id
, rxr
->rx_prod
,
6283 rxr
->rx_agg_ring_struct
.fw_ring_id
, rxr
->rx_agg_prod
,
6284 rxr
->rx_sw_agg_prod
);
6287 static void bnxt_dump_cp_sw_state(struct bnxt_napi
*bnapi
)
6289 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
6290 int i
= bnapi
->index
;
6292 netdev_info(bnapi
->bp
->dev
, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
6293 i
, cpr
->cp_ring_struct
.fw_ring_id
, cpr
->cp_raw_cons
);
6296 static void bnxt_dbg_dump_states(struct bnxt
*bp
)
6299 struct bnxt_napi
*bnapi
;
6301 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
6302 bnapi
= bp
->bnapi
[i
];
6303 if (netif_msg_drv(bp
)) {
6304 bnxt_dump_tx_sw_state(bnapi
);
6305 bnxt_dump_rx_sw_state(bnapi
);
6306 bnxt_dump_cp_sw_state(bnapi
);
6311 static void bnxt_reset_task(struct bnxt
*bp
, bool silent
)
6314 bnxt_dbg_dump_states(bp
);
6315 if (netif_running(bp
->dev
)) {
6316 bnxt_close_nic(bp
, false, false);
6317 bnxt_open_nic(bp
, false, false);
6321 static void bnxt_tx_timeout(struct net_device
*dev
)
6323 struct bnxt
*bp
= netdev_priv(dev
);
6325 netdev_err(bp
->dev
, "TX timeout detected, starting reset task!\n");
6326 set_bit(BNXT_RESET_TASK_SP_EVENT
, &bp
->sp_event
);
6327 schedule_work(&bp
->sp_task
);
6330 #ifdef CONFIG_NET_POLL_CONTROLLER
6331 static void bnxt_poll_controller(struct net_device
*dev
)
6333 struct bnxt
*bp
= netdev_priv(dev
);
6336 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
6337 struct bnxt_irq
*irq
= &bp
->irq_tbl
[i
];
6339 disable_irq(irq
->vector
);
6340 irq
->handler(irq
->vector
, bp
->bnapi
[i
]);
6341 enable_irq(irq
->vector
);
6346 static void bnxt_timer(unsigned long data
)
6348 struct bnxt
*bp
= (struct bnxt
*)data
;
6349 struct net_device
*dev
= bp
->dev
;
6351 if (!netif_running(dev
))
6354 if (atomic_read(&bp
->intr_sem
) != 0)
6355 goto bnxt_restart_timer
;
6357 if (bp
->link_info
.link_up
&& (bp
->flags
& BNXT_FLAG_PORT_STATS
)) {
6358 set_bit(BNXT_PERIODIC_STATS_SP_EVENT
, &bp
->sp_event
);
6359 schedule_work(&bp
->sp_task
);
6362 mod_timer(&bp
->timer
, jiffies
+ bp
->current_interval
);
6365 static void bnxt_rtnl_lock_sp(struct bnxt
*bp
)
6367 /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK
6368 * set. If the device is being closed, bnxt_close() may be holding
6369 * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we
6370 * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
6372 clear_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
6376 static void bnxt_rtnl_unlock_sp(struct bnxt
*bp
)
6378 set_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
6382 /* Only called from bnxt_sp_task() */
6383 static void bnxt_reset(struct bnxt
*bp
, bool silent
)
6385 bnxt_rtnl_lock_sp(bp
);
6386 if (test_bit(BNXT_STATE_OPEN
, &bp
->state
))
6387 bnxt_reset_task(bp
, silent
);
6388 bnxt_rtnl_unlock_sp(bp
);
6391 static void bnxt_cfg_ntp_filters(struct bnxt
*);
6393 static void bnxt_sp_task(struct work_struct
*work
)
6395 struct bnxt
*bp
= container_of(work
, struct bnxt
, sp_task
);
6397 set_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
6398 smp_mb__after_atomic();
6399 if (!test_bit(BNXT_STATE_OPEN
, &bp
->state
)) {
6400 clear_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
6404 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT
, &bp
->sp_event
))
6405 bnxt_cfg_rx_mode(bp
);
6407 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT
, &bp
->sp_event
))
6408 bnxt_cfg_ntp_filters(bp
);
6409 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT
, &bp
->sp_event
))
6410 bnxt_hwrm_exec_fwd_req(bp
);
6411 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT
, &bp
->sp_event
)) {
6412 bnxt_hwrm_tunnel_dst_port_alloc(
6414 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
);
6416 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT
, &bp
->sp_event
)) {
6417 bnxt_hwrm_tunnel_dst_port_free(
6418 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
);
6420 if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT
, &bp
->sp_event
)) {
6421 bnxt_hwrm_tunnel_dst_port_alloc(
6423 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
);
6425 if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT
, &bp
->sp_event
)) {
6426 bnxt_hwrm_tunnel_dst_port_free(
6427 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
);
6429 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT
, &bp
->sp_event
))
6430 bnxt_hwrm_port_qstats(bp
);
6432 /* These functions below will clear BNXT_STATE_IN_SP_TASK. They
6433 * must be the last functions to be called before exiting.
6435 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT
, &bp
->sp_event
)) {
6438 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT
,
6440 bnxt_hwrm_phy_qcaps(bp
);
6442 bnxt_rtnl_lock_sp(bp
);
6443 if (test_bit(BNXT_STATE_OPEN
, &bp
->state
))
6444 rc
= bnxt_update_link(bp
, true);
6445 bnxt_rtnl_unlock_sp(bp
);
6447 netdev_err(bp
->dev
, "SP task can't update link (rc: %x)\n",
6450 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT
, &bp
->sp_event
)) {
6451 bnxt_rtnl_lock_sp(bp
);
6452 if (test_bit(BNXT_STATE_OPEN
, &bp
->state
))
6453 bnxt_get_port_module_status(bp
);
6454 bnxt_rtnl_unlock_sp(bp
);
6456 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT
, &bp
->sp_event
))
6457 bnxt_reset(bp
, false);
6459 if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT
, &bp
->sp_event
))
6460 bnxt_reset(bp
, true);
6462 smp_mb__before_atomic();
6463 clear_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
6466 static int bnxt_init_board(struct pci_dev
*pdev
, struct net_device
*dev
)
6469 struct bnxt
*bp
= netdev_priv(dev
);
6471 SET_NETDEV_DEV(dev
, &pdev
->dev
);
6473 /* enable device (incl. PCI PM wakeup), and bus-mastering */
6474 rc
= pci_enable_device(pdev
);
6476 dev_err(&pdev
->dev
, "Cannot enable PCI device, aborting\n");
6480 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
6482 "Cannot find PCI device base address, aborting\n");
6484 goto init_err_disable
;
6487 rc
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
6489 dev_err(&pdev
->dev
, "Cannot obtain PCI resources, aborting\n");
6490 goto init_err_disable
;
6493 if (dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(64)) != 0 &&
6494 dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(32)) != 0) {
6495 dev_err(&pdev
->dev
, "System does not support DMA, aborting\n");
6496 goto init_err_disable
;
6499 pci_set_master(pdev
);
6504 bp
->bar0
= pci_ioremap_bar(pdev
, 0);
6506 dev_err(&pdev
->dev
, "Cannot map device registers, aborting\n");
6508 goto init_err_release
;
6511 bp
->bar1
= pci_ioremap_bar(pdev
, 2);
6513 dev_err(&pdev
->dev
, "Cannot map doorbell registers, aborting\n");
6515 goto init_err_release
;
6518 bp
->bar2
= pci_ioremap_bar(pdev
, 4);
6520 dev_err(&pdev
->dev
, "Cannot map bar4 registers, aborting\n");
6522 goto init_err_release
;
6525 pci_enable_pcie_error_reporting(pdev
);
6527 INIT_WORK(&bp
->sp_task
, bnxt_sp_task
);
6529 spin_lock_init(&bp
->ntp_fltr_lock
);
6531 bp
->rx_ring_size
= BNXT_DEFAULT_RX_RING_SIZE
;
6532 bp
->tx_ring_size
= BNXT_DEFAULT_TX_RING_SIZE
;
6534 /* tick values in micro seconds */
6535 bp
->rx_coal_ticks
= 12;
6536 bp
->rx_coal_bufs
= 30;
6537 bp
->rx_coal_ticks_irq
= 1;
6538 bp
->rx_coal_bufs_irq
= 2;
6540 bp
->tx_coal_ticks
= 25;
6541 bp
->tx_coal_bufs
= 30;
6542 bp
->tx_coal_ticks_irq
= 2;
6543 bp
->tx_coal_bufs_irq
= 2;
6545 bp
->stats_coal_ticks
= BNXT_DEF_STATS_COAL_TICKS
;
6547 init_timer(&bp
->timer
);
6548 bp
->timer
.data
= (unsigned long)bp
;
6549 bp
->timer
.function
= bnxt_timer
;
6550 bp
->current_interval
= BNXT_TIMER_INTERVAL
;
6552 clear_bit(BNXT_STATE_OPEN
, &bp
->state
);
6558 pci_iounmap(pdev
, bp
->bar2
);
6563 pci_iounmap(pdev
, bp
->bar1
);
6568 pci_iounmap(pdev
, bp
->bar0
);
6572 pci_release_regions(pdev
);
6575 pci_disable_device(pdev
);
6581 /* rtnl_lock held */
6582 static int bnxt_change_mac_addr(struct net_device
*dev
, void *p
)
6584 struct sockaddr
*addr
= p
;
6585 struct bnxt
*bp
= netdev_priv(dev
);
6588 if (!is_valid_ether_addr(addr
->sa_data
))
6589 return -EADDRNOTAVAIL
;
6591 rc
= bnxt_approve_mac(bp
, addr
->sa_data
);
6595 if (ether_addr_equal(addr
->sa_data
, dev
->dev_addr
))
6598 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
6599 if (netif_running(dev
)) {
6600 bnxt_close_nic(bp
, false, false);
6601 rc
= bnxt_open_nic(bp
, false, false);
6607 /* rtnl_lock held */
6608 static int bnxt_change_mtu(struct net_device
*dev
, int new_mtu
)
6610 struct bnxt
*bp
= netdev_priv(dev
);
6612 if (netif_running(dev
))
6613 bnxt_close_nic(bp
, false, false);
6616 bnxt_set_ring_params(bp
);
6618 if (netif_running(dev
))
6619 return bnxt_open_nic(bp
, false, false);
6624 int bnxt_setup_mq_tc(struct net_device
*dev
, u8 tc
)
6626 struct bnxt
*bp
= netdev_priv(dev
);
6629 if (tc
> bp
->max_tc
) {
6630 netdev_err(dev
, "too many traffic classes requested: %d Max supported is %d\n",
6635 if (netdev_get_num_tc(dev
) == tc
)
6638 if (bp
->flags
& BNXT_FLAG_SHARED_RINGS
)
6642 int max_rx_rings
, max_tx_rings
, req_tx_rings
, rsv_tx_rings
, rc
;
6644 req_tx_rings
= bp
->tx_nr_rings_per_tc
* tc
;
6645 rc
= bnxt_get_max_rings(bp
, &max_rx_rings
, &max_tx_rings
, sh
);
6646 if (rc
|| req_tx_rings
> max_tx_rings
)
6649 rsv_tx_rings
= req_tx_rings
;
6650 if (bnxt_hwrm_reserve_tx_rings(bp
, &rsv_tx_rings
) ||
6651 rsv_tx_rings
< req_tx_rings
)
6655 /* Needs to close the device and do hw resource re-allocations */
6656 if (netif_running(bp
->dev
))
6657 bnxt_close_nic(bp
, true, false);
6660 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
* tc
;
6661 netdev_set_num_tc(dev
, tc
);
6663 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
;
6664 netdev_reset_tc(dev
);
6666 bp
->cp_nr_rings
= sh
? max_t(int, bp
->tx_nr_rings
, bp
->rx_nr_rings
) :
6667 bp
->tx_nr_rings
+ bp
->rx_nr_rings
;
6668 bp
->num_stat_ctxs
= bp
->cp_nr_rings
;
6670 if (netif_running(bp
->dev
))
6671 return bnxt_open_nic(bp
, true, false);
6676 static int bnxt_setup_tc(struct net_device
*dev
, u32 handle
, __be16 proto
,
6677 struct tc_to_netdev
*ntc
)
6679 if (ntc
->type
!= TC_SETUP_MQPRIO
)
6682 return bnxt_setup_mq_tc(dev
, ntc
->tc
);
6685 #ifdef CONFIG_RFS_ACCEL
6686 static bool bnxt_fltr_match(struct bnxt_ntuple_filter
*f1
,
6687 struct bnxt_ntuple_filter
*f2
)
6689 struct flow_keys
*keys1
= &f1
->fkeys
;
6690 struct flow_keys
*keys2
= &f2
->fkeys
;
6692 if (keys1
->addrs
.v4addrs
.src
== keys2
->addrs
.v4addrs
.src
&&
6693 keys1
->addrs
.v4addrs
.dst
== keys2
->addrs
.v4addrs
.dst
&&
6694 keys1
->ports
.ports
== keys2
->ports
.ports
&&
6695 keys1
->basic
.ip_proto
== keys2
->basic
.ip_proto
&&
6696 keys1
->basic
.n_proto
== keys2
->basic
.n_proto
&&
6697 ether_addr_equal(f1
->src_mac_addr
, f2
->src_mac_addr
) &&
6698 ether_addr_equal(f1
->dst_mac_addr
, f2
->dst_mac_addr
))
6704 static int bnxt_rx_flow_steer(struct net_device
*dev
, const struct sk_buff
*skb
,
6705 u16 rxq_index
, u32 flow_id
)
6707 struct bnxt
*bp
= netdev_priv(dev
);
6708 struct bnxt_ntuple_filter
*fltr
, *new_fltr
;
6709 struct flow_keys
*fkeys
;
6710 struct ethhdr
*eth
= (struct ethhdr
*)skb_mac_header(skb
);
6711 int rc
= 0, idx
, bit_id
, l2_idx
= 0;
6712 struct hlist_head
*head
;
6714 if (skb
->encapsulation
)
6715 return -EPROTONOSUPPORT
;
6717 if (!ether_addr_equal(dev
->dev_addr
, eth
->h_dest
)) {
6718 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
6721 netif_addr_lock_bh(dev
);
6722 for (j
= 0; j
< vnic
->uc_filter_count
; j
++, off
+= ETH_ALEN
) {
6723 if (ether_addr_equal(eth
->h_dest
,
6724 vnic
->uc_list
+ off
)) {
6729 netif_addr_unlock_bh(dev
);
6733 new_fltr
= kzalloc(sizeof(*new_fltr
), GFP_ATOMIC
);
6737 fkeys
= &new_fltr
->fkeys
;
6738 if (!skb_flow_dissect_flow_keys(skb
, fkeys
, 0)) {
6739 rc
= -EPROTONOSUPPORT
;
6743 if ((fkeys
->basic
.n_proto
!= htons(ETH_P_IP
) &&
6744 fkeys
->basic
.n_proto
!= htons(ETH_P_IPV6
)) ||
6745 ((fkeys
->basic
.ip_proto
!= IPPROTO_TCP
) &&
6746 (fkeys
->basic
.ip_proto
!= IPPROTO_UDP
))) {
6747 rc
= -EPROTONOSUPPORT
;
6750 if (fkeys
->basic
.n_proto
== htons(ETH_P_IPV6
) &&
6751 bp
->hwrm_spec_code
< 0x10601) {
6752 rc
= -EPROTONOSUPPORT
;
6756 memcpy(new_fltr
->dst_mac_addr
, eth
->h_dest
, ETH_ALEN
);
6757 memcpy(new_fltr
->src_mac_addr
, eth
->h_source
, ETH_ALEN
);
6759 idx
= skb_get_hash_raw(skb
) & BNXT_NTP_FLTR_HASH_MASK
;
6760 head
= &bp
->ntp_fltr_hash_tbl
[idx
];
6762 hlist_for_each_entry_rcu(fltr
, head
, hash
) {
6763 if (bnxt_fltr_match(fltr
, new_fltr
)) {
6771 spin_lock_bh(&bp
->ntp_fltr_lock
);
6772 bit_id
= bitmap_find_free_region(bp
->ntp_fltr_bmap
,
6773 BNXT_NTP_FLTR_MAX_FLTR
, 0);
6775 spin_unlock_bh(&bp
->ntp_fltr_lock
);
6780 new_fltr
->sw_id
= (u16
)bit_id
;
6781 new_fltr
->flow_id
= flow_id
;
6782 new_fltr
->l2_fltr_idx
= l2_idx
;
6783 new_fltr
->rxq
= rxq_index
;
6784 hlist_add_head_rcu(&new_fltr
->hash
, head
);
6785 bp
->ntp_fltr_count
++;
6786 spin_unlock_bh(&bp
->ntp_fltr_lock
);
6788 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT
, &bp
->sp_event
);
6789 schedule_work(&bp
->sp_task
);
6791 return new_fltr
->sw_id
;
6798 static void bnxt_cfg_ntp_filters(struct bnxt
*bp
)
6802 for (i
= 0; i
< BNXT_NTP_FLTR_HASH_SIZE
; i
++) {
6803 struct hlist_head
*head
;
6804 struct hlist_node
*tmp
;
6805 struct bnxt_ntuple_filter
*fltr
;
6808 head
= &bp
->ntp_fltr_hash_tbl
[i
];
6809 hlist_for_each_entry_safe(fltr
, tmp
, head
, hash
) {
6812 if (test_bit(BNXT_FLTR_VALID
, &fltr
->state
)) {
6813 if (rps_may_expire_flow(bp
->dev
, fltr
->rxq
,
6816 bnxt_hwrm_cfa_ntuple_filter_free(bp
,
6821 rc
= bnxt_hwrm_cfa_ntuple_filter_alloc(bp
,
6826 set_bit(BNXT_FLTR_VALID
, &fltr
->state
);
6830 spin_lock_bh(&bp
->ntp_fltr_lock
);
6831 hlist_del_rcu(&fltr
->hash
);
6832 bp
->ntp_fltr_count
--;
6833 spin_unlock_bh(&bp
->ntp_fltr_lock
);
6835 clear_bit(fltr
->sw_id
, bp
->ntp_fltr_bmap
);
6840 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT
, &bp
->sp_event
))
6841 netdev_info(bp
->dev
, "Receive PF driver unload event!");
6846 static void bnxt_cfg_ntp_filters(struct bnxt
*bp
)
6850 #endif /* CONFIG_RFS_ACCEL */
6852 static void bnxt_udp_tunnel_add(struct net_device
*dev
,
6853 struct udp_tunnel_info
*ti
)
6855 struct bnxt
*bp
= netdev_priv(dev
);
6857 if (ti
->sa_family
!= AF_INET6
&& ti
->sa_family
!= AF_INET
)
6860 if (!netif_running(dev
))
6864 case UDP_TUNNEL_TYPE_VXLAN
:
6865 if (bp
->vxlan_port_cnt
&& bp
->vxlan_port
!= ti
->port
)
6868 bp
->vxlan_port_cnt
++;
6869 if (bp
->vxlan_port_cnt
== 1) {
6870 bp
->vxlan_port
= ti
->port
;
6871 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT
, &bp
->sp_event
);
6872 schedule_work(&bp
->sp_task
);
6875 case UDP_TUNNEL_TYPE_GENEVE
:
6876 if (bp
->nge_port_cnt
&& bp
->nge_port
!= ti
->port
)
6880 if (bp
->nge_port_cnt
== 1) {
6881 bp
->nge_port
= ti
->port
;
6882 set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT
, &bp
->sp_event
);
6889 schedule_work(&bp
->sp_task
);
6892 static void bnxt_udp_tunnel_del(struct net_device
*dev
,
6893 struct udp_tunnel_info
*ti
)
6895 struct bnxt
*bp
= netdev_priv(dev
);
6897 if (ti
->sa_family
!= AF_INET6
&& ti
->sa_family
!= AF_INET
)
6900 if (!netif_running(dev
))
6904 case UDP_TUNNEL_TYPE_VXLAN
:
6905 if (!bp
->vxlan_port_cnt
|| bp
->vxlan_port
!= ti
->port
)
6907 bp
->vxlan_port_cnt
--;
6909 if (bp
->vxlan_port_cnt
!= 0)
6912 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT
, &bp
->sp_event
);
6914 case UDP_TUNNEL_TYPE_GENEVE
:
6915 if (!bp
->nge_port_cnt
|| bp
->nge_port
!= ti
->port
)
6919 if (bp
->nge_port_cnt
!= 0)
6922 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT
, &bp
->sp_event
);
6928 schedule_work(&bp
->sp_task
);
6931 static const struct net_device_ops bnxt_netdev_ops
= {
6932 .ndo_open
= bnxt_open
,
6933 .ndo_start_xmit
= bnxt_start_xmit
,
6934 .ndo_stop
= bnxt_close
,
6935 .ndo_get_stats64
= bnxt_get_stats64
,
6936 .ndo_set_rx_mode
= bnxt_set_rx_mode
,
6937 .ndo_do_ioctl
= bnxt_ioctl
,
6938 .ndo_validate_addr
= eth_validate_addr
,
6939 .ndo_set_mac_address
= bnxt_change_mac_addr
,
6940 .ndo_change_mtu
= bnxt_change_mtu
,
6941 .ndo_fix_features
= bnxt_fix_features
,
6942 .ndo_set_features
= bnxt_set_features
,
6943 .ndo_tx_timeout
= bnxt_tx_timeout
,
6944 #ifdef CONFIG_BNXT_SRIOV
6945 .ndo_get_vf_config
= bnxt_get_vf_config
,
6946 .ndo_set_vf_mac
= bnxt_set_vf_mac
,
6947 .ndo_set_vf_vlan
= bnxt_set_vf_vlan
,
6948 .ndo_set_vf_rate
= bnxt_set_vf_bw
,
6949 .ndo_set_vf_link_state
= bnxt_set_vf_link_state
,
6950 .ndo_set_vf_spoofchk
= bnxt_set_vf_spoofchk
,
6952 #ifdef CONFIG_NET_POLL_CONTROLLER
6953 .ndo_poll_controller
= bnxt_poll_controller
,
6955 .ndo_setup_tc
= bnxt_setup_tc
,
6956 #ifdef CONFIG_RFS_ACCEL
6957 .ndo_rx_flow_steer
= bnxt_rx_flow_steer
,
6959 .ndo_udp_tunnel_add
= bnxt_udp_tunnel_add
,
6960 .ndo_udp_tunnel_del
= bnxt_udp_tunnel_del
,
6963 static void bnxt_remove_one(struct pci_dev
*pdev
)
6965 struct net_device
*dev
= pci_get_drvdata(pdev
);
6966 struct bnxt
*bp
= netdev_priv(dev
);
6969 bnxt_sriov_disable(bp
);
6971 pci_disable_pcie_error_reporting(pdev
);
6972 unregister_netdev(dev
);
6973 cancel_work_sync(&bp
->sp_task
);
6976 bnxt_clear_int_mode(bp
);
6977 bnxt_hwrm_func_drv_unrgtr(bp
);
6978 bnxt_free_hwrm_resources(bp
);
6980 pci_iounmap(pdev
, bp
->bar2
);
6981 pci_iounmap(pdev
, bp
->bar1
);
6982 pci_iounmap(pdev
, bp
->bar0
);
6987 pci_release_regions(pdev
);
6988 pci_disable_device(pdev
);
6991 static int bnxt_probe_phy(struct bnxt
*bp
)
6994 struct bnxt_link_info
*link_info
= &bp
->link_info
;
6996 rc
= bnxt_hwrm_phy_qcaps(bp
);
6998 netdev_err(bp
->dev
, "Probe phy can't get phy capabilities (rc: %x)\n",
7003 rc
= bnxt_update_link(bp
, false);
7005 netdev_err(bp
->dev
, "Probe phy can't update link (rc: %x)\n",
7010 /* Older firmware does not have supported_auto_speeds, so assume
7011 * that all supported speeds can be autonegotiated.
7013 if (link_info
->auto_link_speeds
&& !link_info
->support_auto_speeds
)
7014 link_info
->support_auto_speeds
= link_info
->support_speeds
;
7016 /*initialize the ethool setting copy with NVM settings */
7017 if (BNXT_AUTO_MODE(link_info
->auto_mode
)) {
7018 link_info
->autoneg
= BNXT_AUTONEG_SPEED
;
7019 if (bp
->hwrm_spec_code
>= 0x10201) {
7020 if (link_info
->auto_pause_setting
&
7021 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE
)
7022 link_info
->autoneg
|= BNXT_AUTONEG_FLOW_CTRL
;
7024 link_info
->autoneg
|= BNXT_AUTONEG_FLOW_CTRL
;
7026 link_info
->advertising
= link_info
->auto_link_speeds
;
7028 link_info
->req_link_speed
= link_info
->force_link_speed
;
7029 link_info
->req_duplex
= link_info
->duplex_setting
;
7031 if (link_info
->autoneg
& BNXT_AUTONEG_FLOW_CTRL
)
7032 link_info
->req_flow_ctrl
=
7033 link_info
->auto_pause_setting
& BNXT_LINK_PAUSE_BOTH
;
7035 link_info
->req_flow_ctrl
= link_info
->force_pause_setting
;
7039 static int bnxt_get_max_irq(struct pci_dev
*pdev
)
7043 if (!pdev
->msix_cap
)
7046 pci_read_config_word(pdev
, pdev
->msix_cap
+ PCI_MSIX_FLAGS
, &ctrl
);
7047 return (ctrl
& PCI_MSIX_FLAGS_QSIZE
) + 1;
7050 static void _bnxt_get_max_rings(struct bnxt
*bp
, int *max_rx
, int *max_tx
,
7053 int max_ring_grps
= 0;
7055 #ifdef CONFIG_BNXT_SRIOV
7057 *max_tx
= bp
->vf
.max_tx_rings
;
7058 *max_rx
= bp
->vf
.max_rx_rings
;
7059 *max_cp
= min_t(int, bp
->vf
.max_irqs
, bp
->vf
.max_cp_rings
);
7060 *max_cp
= min_t(int, *max_cp
, bp
->vf
.max_stat_ctxs
);
7061 max_ring_grps
= bp
->vf
.max_hw_ring_grps
;
7065 *max_tx
= bp
->pf
.max_tx_rings
;
7066 *max_rx
= bp
->pf
.max_rx_rings
;
7067 *max_cp
= min_t(int, bp
->pf
.max_irqs
, bp
->pf
.max_cp_rings
);
7068 *max_cp
= min_t(int, *max_cp
, bp
->pf
.max_stat_ctxs
);
7069 max_ring_grps
= bp
->pf
.max_hw_ring_grps
;
7071 if (BNXT_CHIP_TYPE_NITRO_A0(bp
) && BNXT_PF(bp
)) {
7075 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
)
7077 *max_rx
= min_t(int, *max_rx
, max_ring_grps
);
7080 int bnxt_get_max_rings(struct bnxt
*bp
, int *max_rx
, int *max_tx
, bool shared
)
7084 _bnxt_get_max_rings(bp
, &rx
, &tx
, &cp
);
7085 if (!rx
|| !tx
|| !cp
)
7090 return bnxt_trim_rings(bp
, max_rx
, max_tx
, cp
, shared
);
7093 static int bnxt_get_dflt_rings(struct bnxt
*bp
, int *max_rx
, int *max_tx
,
7098 rc
= bnxt_get_max_rings(bp
, max_rx
, max_tx
, shared
);
7099 if (rc
&& (bp
->flags
& BNXT_FLAG_AGG_RINGS
)) {
7100 /* Not enough rings, try disabling agg rings. */
7101 bp
->flags
&= ~BNXT_FLAG_AGG_RINGS
;
7102 rc
= bnxt_get_max_rings(bp
, max_rx
, max_tx
, shared
);
7105 bp
->flags
|= BNXT_FLAG_NO_AGG_RINGS
;
7106 bp
->dev
->hw_features
&= ~NETIF_F_LRO
;
7107 bp
->dev
->features
&= ~NETIF_F_LRO
;
7108 bnxt_set_ring_params(bp
);
7111 if (bp
->flags
& BNXT_FLAG_ROCE_CAP
) {
7112 int max_cp
, max_stat
, max_irq
;
7114 /* Reserve minimum resources for RoCE */
7115 max_cp
= bnxt_get_max_func_cp_rings(bp
);
7116 max_stat
= bnxt_get_max_func_stat_ctxs(bp
);
7117 max_irq
= bnxt_get_max_func_irqs(bp
);
7118 if (max_cp
<= BNXT_MIN_ROCE_CP_RINGS
||
7119 max_irq
<= BNXT_MIN_ROCE_CP_RINGS
||
7120 max_stat
<= BNXT_MIN_ROCE_STAT_CTXS
)
7123 max_cp
-= BNXT_MIN_ROCE_CP_RINGS
;
7124 max_irq
-= BNXT_MIN_ROCE_CP_RINGS
;
7125 max_stat
-= BNXT_MIN_ROCE_STAT_CTXS
;
7126 max_cp
= min_t(int, max_cp
, max_irq
);
7127 max_cp
= min_t(int, max_cp
, max_stat
);
7128 rc
= bnxt_trim_rings(bp
, max_rx
, max_tx
, max_cp
, shared
);
7135 static int bnxt_set_dflt_rings(struct bnxt
*bp
)
7137 int dflt_rings
, max_rx_rings
, max_tx_rings
, rc
;
7141 bp
->flags
|= BNXT_FLAG_SHARED_RINGS
;
7142 dflt_rings
= netif_get_num_default_rss_queues();
7143 rc
= bnxt_get_dflt_rings(bp
, &max_rx_rings
, &max_tx_rings
, sh
);
7146 bp
->rx_nr_rings
= min_t(int, dflt_rings
, max_rx_rings
);
7147 bp
->tx_nr_rings_per_tc
= min_t(int, dflt_rings
, max_tx_rings
);
7149 rc
= bnxt_hwrm_reserve_tx_rings(bp
, &bp
->tx_nr_rings_per_tc
);
7151 netdev_warn(bp
->dev
, "Unable to reserve tx rings\n");
7153 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
;
7154 bp
->cp_nr_rings
= sh
? max_t(int, bp
->tx_nr_rings
, bp
->rx_nr_rings
) :
7155 bp
->tx_nr_rings
+ bp
->rx_nr_rings
;
7156 bp
->num_stat_ctxs
= bp
->cp_nr_rings
;
7157 if (BNXT_CHIP_TYPE_NITRO_A0(bp
)) {
7164 void bnxt_restore_pf_fw_resources(struct bnxt
*bp
)
7167 bnxt_hwrm_func_qcaps(bp
);
7168 bnxt_subtract_ulp_resources(bp
, BNXT_ROCE_ULP
);
7171 static void bnxt_parse_log_pcie_link(struct bnxt
*bp
)
7173 enum pcie_link_width width
= PCIE_LNK_WIDTH_UNKNOWN
;
7174 enum pci_bus_speed speed
= PCI_SPEED_UNKNOWN
;
7176 if (pcie_get_minimum_link(bp
->pdev
, &speed
, &width
) ||
7177 speed
== PCI_SPEED_UNKNOWN
|| width
== PCIE_LNK_WIDTH_UNKNOWN
)
7178 netdev_info(bp
->dev
, "Failed to determine PCIe Link Info\n");
7180 netdev_info(bp
->dev
, "PCIe: Speed %s Width x%d\n",
7181 speed
== PCIE_SPEED_2_5GT
? "2.5GT/s" :
7182 speed
== PCIE_SPEED_5_0GT
? "5.0GT/s" :
7183 speed
== PCIE_SPEED_8_0GT
? "8.0GT/s" :
7187 static int bnxt_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
7189 static int version_printed
;
7190 struct net_device
*dev
;
7194 if (pdev
->device
== 0x16cd && pci_is_bridge(pdev
))
7197 if (version_printed
++ == 0)
7198 pr_info("%s", version
);
7200 max_irqs
= bnxt_get_max_irq(pdev
);
7201 dev
= alloc_etherdev_mq(sizeof(*bp
), max_irqs
);
7205 bp
= netdev_priv(dev
);
7207 if (bnxt_vf_pciid(ent
->driver_data
))
7208 bp
->flags
|= BNXT_FLAG_VF
;
7211 bp
->flags
|= BNXT_FLAG_MSIX_CAP
;
7213 rc
= bnxt_init_board(pdev
, dev
);
7217 dev
->netdev_ops
= &bnxt_netdev_ops
;
7218 dev
->watchdog_timeo
= BNXT_TX_TIMEOUT
;
7219 dev
->ethtool_ops
= &bnxt_ethtool_ops
;
7221 pci_set_drvdata(pdev
, dev
);
7223 rc
= bnxt_alloc_hwrm_resources(bp
);
7227 mutex_init(&bp
->hwrm_cmd_lock
);
7228 rc
= bnxt_hwrm_ver_get(bp
);
7232 bnxt_hwrm_fw_set_time(bp
);
7234 dev
->hw_features
= NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
| NETIF_F_SG
|
7235 NETIF_F_TSO
| NETIF_F_TSO6
|
7236 NETIF_F_GSO_UDP_TUNNEL
| NETIF_F_GSO_GRE
|
7237 NETIF_F_GSO_IPXIP4
|
7238 NETIF_F_GSO_UDP_TUNNEL_CSUM
| NETIF_F_GSO_GRE_CSUM
|
7239 NETIF_F_GSO_PARTIAL
| NETIF_F_RXHASH
|
7240 NETIF_F_RXCSUM
| NETIF_F_GRO
;
7242 if (!BNXT_CHIP_TYPE_NITRO_A0(bp
))
7243 dev
->hw_features
|= NETIF_F_LRO
;
7245 dev
->hw_enc_features
=
7246 NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
| NETIF_F_SG
|
7247 NETIF_F_TSO
| NETIF_F_TSO6
|
7248 NETIF_F_GSO_UDP_TUNNEL
| NETIF_F_GSO_GRE
|
7249 NETIF_F_GSO_UDP_TUNNEL_CSUM
| NETIF_F_GSO_GRE_CSUM
|
7250 NETIF_F_GSO_IPXIP4
| NETIF_F_GSO_PARTIAL
;
7251 dev
->gso_partial_features
= NETIF_F_GSO_UDP_TUNNEL_CSUM
|
7252 NETIF_F_GSO_GRE_CSUM
;
7253 dev
->vlan_features
= dev
->hw_features
| NETIF_F_HIGHDMA
;
7254 dev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_RX
| NETIF_F_HW_VLAN_CTAG_TX
|
7255 NETIF_F_HW_VLAN_STAG_RX
| NETIF_F_HW_VLAN_STAG_TX
;
7256 dev
->features
|= dev
->hw_features
| NETIF_F_HIGHDMA
;
7257 dev
->priv_flags
|= IFF_UNICAST_FLT
;
7259 /* MTU range: 60 - 9500 */
7260 dev
->min_mtu
= ETH_ZLEN
;
7261 dev
->max_mtu
= 9500;
7265 #ifdef CONFIG_BNXT_SRIOV
7266 init_waitqueue_head(&bp
->sriov_cfg_wait
);
7268 bp
->gro_func
= bnxt_gro_func_5730x
;
7269 if (BNXT_CHIP_NUM_57X1X(bp
->chip_num
))
7270 bp
->gro_func
= bnxt_gro_func_5731x
;
7272 rc
= bnxt_hwrm_func_drv_rgtr(bp
);
7276 rc
= bnxt_hwrm_func_rgtr_async_events(bp
, NULL
, 0);
7280 bp
->ulp_probe
= bnxt_ulp_probe
;
7282 /* Get the MAX capabilities for this function */
7283 rc
= bnxt_hwrm_func_qcaps(bp
);
7285 netdev_err(bp
->dev
, "hwrm query capability failure rc: %x\n",
7291 rc
= bnxt_hwrm_queue_qportcfg(bp
);
7293 netdev_err(bp
->dev
, "hwrm query qportcfg failure rc: %x\n",
7299 bnxt_hwrm_func_qcfg(bp
);
7300 bnxt_hwrm_port_led_qcaps(bp
);
7302 bnxt_set_tpa_flags(bp
);
7303 bnxt_set_ring_params(bp
);
7304 bnxt_set_max_func_irqs(bp
, max_irqs
);
7305 rc
= bnxt_set_dflt_rings(bp
);
7307 netdev_err(bp
->dev
, "Not enough rings available.\n");
7312 /* Default RSS hash cfg. */
7313 bp
->rss_hash_cfg
= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4
|
7314 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4
|
7315 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6
|
7316 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6
;
7317 if (!BNXT_CHIP_NUM_57X0X(bp
->chip_num
) &&
7318 !BNXT_CHIP_TYPE_NITRO_A0(bp
) &&
7319 bp
->hwrm_spec_code
>= 0x10501) {
7320 bp
->flags
|= BNXT_FLAG_UDP_RSS_CAP
;
7321 bp
->rss_hash_cfg
|= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4
|
7322 VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6
;
7325 bnxt_hwrm_vnic_qcaps(bp
);
7326 if (bnxt_rfs_supported(bp
)) {
7327 dev
->hw_features
|= NETIF_F_NTUPLE
;
7328 if (bnxt_rfs_capable(bp
)) {
7329 bp
->flags
|= BNXT_FLAG_RFS
;
7330 dev
->features
|= NETIF_F_NTUPLE
;
7334 if (dev
->hw_features
& NETIF_F_HW_VLAN_CTAG_RX
)
7335 bp
->flags
|= BNXT_FLAG_STRIP_VLAN
;
7337 rc
= bnxt_probe_phy(bp
);
7341 rc
= bnxt_hwrm_func_reset(bp
);
7345 rc
= bnxt_init_int_mode(bp
);
7349 rc
= register_netdev(dev
);
7351 goto init_err_clr_int
;
7353 netdev_info(dev
, "%s found at mem %lx, node addr %pM\n",
7354 board_info
[ent
->driver_data
].name
,
7355 (long)pci_resource_start(pdev
, 0), dev
->dev_addr
);
7357 bnxt_parse_log_pcie_link(bp
);
7362 bnxt_clear_int_mode(bp
);
7365 pci_iounmap(pdev
, bp
->bar0
);
7366 pci_release_regions(pdev
);
7367 pci_disable_device(pdev
);
7375 * bnxt_io_error_detected - called when PCI error is detected
7376 * @pdev: Pointer to PCI device
7377 * @state: The current pci connection state
7379 * This function is called after a PCI bus error affecting
7380 * this device has been detected.
7382 static pci_ers_result_t
bnxt_io_error_detected(struct pci_dev
*pdev
,
7383 pci_channel_state_t state
)
7385 struct net_device
*netdev
= pci_get_drvdata(pdev
);
7386 struct bnxt
*bp
= netdev_priv(netdev
);
7388 netdev_info(netdev
, "PCI I/O error detected\n");
7391 netif_device_detach(netdev
);
7395 if (state
== pci_channel_io_perm_failure
) {
7397 return PCI_ERS_RESULT_DISCONNECT
;
7400 if (netif_running(netdev
))
7403 pci_disable_device(pdev
);
7406 /* Request a slot slot reset. */
7407 return PCI_ERS_RESULT_NEED_RESET
;
7411 * bnxt_io_slot_reset - called after the pci bus has been reset.
7412 * @pdev: Pointer to PCI device
7414 * Restart the card from scratch, as if from a cold-boot.
7415 * At this point, the card has exprienced a hard reset,
7416 * followed by fixups by BIOS, and has its config space
7417 * set up identically to what it was at cold boot.
7419 static pci_ers_result_t
bnxt_io_slot_reset(struct pci_dev
*pdev
)
7421 struct net_device
*netdev
= pci_get_drvdata(pdev
);
7422 struct bnxt
*bp
= netdev_priv(netdev
);
7424 pci_ers_result_t result
= PCI_ERS_RESULT_DISCONNECT
;
7426 netdev_info(bp
->dev
, "PCI Slot Reset\n");
7430 if (pci_enable_device(pdev
)) {
7432 "Cannot re-enable PCI device after reset.\n");
7434 pci_set_master(pdev
);
7436 err
= bnxt_hwrm_func_reset(bp
);
7437 if (!err
&& netif_running(netdev
))
7438 err
= bnxt_open(netdev
);
7441 result
= PCI_ERS_RESULT_RECOVERED
;
7446 if (result
!= PCI_ERS_RESULT_RECOVERED
&& netif_running(netdev
))
7451 err
= pci_cleanup_aer_uncorrect_error_status(pdev
);
7454 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7455 err
); /* non-fatal, continue */
7458 return PCI_ERS_RESULT_RECOVERED
;
7462 * bnxt_io_resume - called when traffic can start flowing again.
7463 * @pdev: Pointer to PCI device
7465 * This callback is called when the error recovery driver tells
7466 * us that its OK to resume normal operation.
7468 static void bnxt_io_resume(struct pci_dev
*pdev
)
7470 struct net_device
*netdev
= pci_get_drvdata(pdev
);
7474 netif_device_attach(netdev
);
7479 static const struct pci_error_handlers bnxt_err_handler
= {
7480 .error_detected
= bnxt_io_error_detected
,
7481 .slot_reset
= bnxt_io_slot_reset
,
7482 .resume
= bnxt_io_resume
7485 static struct pci_driver bnxt_pci_driver
= {
7486 .name
= DRV_MODULE_NAME
,
7487 .id_table
= bnxt_pci_tbl
,
7488 .probe
= bnxt_init_one
,
7489 .remove
= bnxt_remove_one
,
7490 .err_handler
= &bnxt_err_handler
,
7491 #if defined(CONFIG_BNXT_SRIOV)
7492 .sriov_configure
= bnxt_sriov_configure
,
7496 module_pci_driver(bnxt_pci_driver
);