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bnxt_en: Don't allow autoneg on cards that don't support it.
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / broadcom / bnxt / bnxt.c
1 /* Broadcom NetXtreme-C/E network driver.
2 *
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 */
9
10 #include <linux/module.h>
11
12 #include <linux/stringify.h>
13 #include <linux/kernel.h>
14 #include <linux/timer.h>
15 #include <linux/errno.h>
16 #include <linux/ioport.h>
17 #include <linux/slab.h>
18 #include <linux/vmalloc.h>
19 #include <linux/interrupt.h>
20 #include <linux/pci.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23 #include <linux/skbuff.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/bitops.h>
26 #include <linux/io.h>
27 #include <linux/irq.h>
28 #include <linux/delay.h>
29 #include <asm/byteorder.h>
30 #include <asm/page.h>
31 #include <linux/time.h>
32 #include <linux/mii.h>
33 #include <linux/if.h>
34 #include <linux/if_vlan.h>
35 #include <net/ip.h>
36 #include <net/tcp.h>
37 #include <net/udp.h>
38 #include <net/checksum.h>
39 #include <net/ip6_checksum.h>
40 #if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE)
41 #include <net/vxlan.h>
42 #endif
43 #ifdef CONFIG_NET_RX_BUSY_POLL
44 #include <net/busy_poll.h>
45 #endif
46 #include <linux/workqueue.h>
47 #include <linux/prefetch.h>
48 #include <linux/cache.h>
49 #include <linux/log2.h>
50 #include <linux/aer.h>
51 #include <linux/bitmap.h>
52 #include <linux/cpu_rmap.h>
53
54 #include "bnxt_hsi.h"
55 #include "bnxt.h"
56 #include "bnxt_sriov.h"
57 #include "bnxt_ethtool.h"
58
59 #define BNXT_TX_TIMEOUT (5 * HZ)
60
61 static const char version[] =
62 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
63
64 MODULE_LICENSE("GPL");
65 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
66 MODULE_VERSION(DRV_MODULE_VERSION);
67
68 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
69 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
70 #define BNXT_RX_COPY_THRESH 256
71
72 #define BNXT_TX_PUSH_THRESH 164
73
74 enum board_idx {
75 BCM57301,
76 BCM57302,
77 BCM57304,
78 BCM57311,
79 BCM57312,
80 BCM57402,
81 BCM57404,
82 BCM57406,
83 BCM57404_NPAR,
84 BCM57412,
85 BCM57414,
86 BCM57416,
87 BCM57417,
88 BCM57414_NPAR,
89 BCM57314,
90 BCM57304_VF,
91 BCM57404_VF,
92 BCM57414_VF,
93 BCM57314_VF,
94 };
95
96 /* indexed by enum above */
97 static const struct {
98 char *name;
99 } board_info[] = {
100 { "Broadcom BCM57301 NetXtreme-C Single-port 10Gb Ethernet" },
101 { "Broadcom BCM57302 NetXtreme-C Dual-port 10Gb/25Gb Ethernet" },
102 { "Broadcom BCM57304 NetXtreme-C Dual-port 10Gb/25Gb/40Gb/50Gb Ethernet" },
103 { "Broadcom BCM57311 NetXtreme-C Single-port 10Gb Ethernet" },
104 { "Broadcom BCM57312 NetXtreme-C Dual-port 10Gb/25Gb Ethernet" },
105 { "Broadcom BCM57402 NetXtreme-E Dual-port 10Gb Ethernet" },
106 { "Broadcom BCM57404 NetXtreme-E Dual-port 10Gb/25Gb Ethernet" },
107 { "Broadcom BCM57406 NetXtreme-E Dual-port 10GBase-T Ethernet" },
108 { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
109 { "Broadcom BCM57412 NetXtreme-E Dual-port 10Gb Ethernet" },
110 { "Broadcom BCM57414 NetXtreme-E Dual-port 10Gb/25Gb Ethernet" },
111 { "Broadcom BCM57416 NetXtreme-E Dual-port 10GBase-T Ethernet" },
112 { "Broadcom BCM57417 NetXtreme-E Dual-port 10GBase-T Ethernet" },
113 { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
114 { "Broadcom BCM57314 NetXtreme-C Dual-port 10Gb/25Gb/40Gb/50Gb Ethernet" },
115 { "Broadcom BCM57304 NetXtreme-C Ethernet Virtual Function" },
116 { "Broadcom BCM57404 NetXtreme-E Ethernet Virtual Function" },
117 { "Broadcom BCM57414 NetXtreme-E Ethernet Virtual Function" },
118 { "Broadcom BCM57314 NetXtreme-E Ethernet Virtual Function" },
119 };
120
121 static const struct pci_device_id bnxt_pci_tbl[] = {
122 { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
123 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
124 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
125 { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 },
126 { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 },
127 { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
128 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
129 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
130 { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57404_NPAR },
131 { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 },
132 { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 },
133 { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 },
134 { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 },
135 { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57414_NPAR },
136 { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
137 #ifdef CONFIG_BNXT_SRIOV
138 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = BCM57304_VF },
139 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = BCM57404_VF },
140 { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = BCM57414_VF },
141 { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = BCM57314_VF },
142 #endif
143 { 0 }
144 };
145
146 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
147
148 static const u16 bnxt_vf_req_snif[] = {
149 HWRM_FUNC_CFG,
150 HWRM_PORT_PHY_QCFG,
151 HWRM_CFA_L2_FILTER_ALLOC,
152 };
153
154 static const u16 bnxt_async_events_arr[] = {
155 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
156 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
157 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
158 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
159 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
160 };
161
162 static bool bnxt_vf_pciid(enum board_idx idx)
163 {
164 return (idx == BCM57304_VF || idx == BCM57404_VF ||
165 idx == BCM57314_VF || idx == BCM57414_VF);
166 }
167
168 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
169 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
170 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
171
172 #define BNXT_CP_DB_REARM(db, raw_cons) \
173 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
174
175 #define BNXT_CP_DB(db, raw_cons) \
176 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
177
178 #define BNXT_CP_DB_IRQ_DIS(db) \
179 writel(DB_CP_IRQ_DIS_FLAGS, db)
180
181 static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
182 {
183 /* Tell compiler to fetch tx indices from memory. */
184 barrier();
185
186 return bp->tx_ring_size -
187 ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask);
188 }
189
190 static const u16 bnxt_lhint_arr[] = {
191 TX_BD_FLAGS_LHINT_512_AND_SMALLER,
192 TX_BD_FLAGS_LHINT_512_TO_1023,
193 TX_BD_FLAGS_LHINT_1024_TO_2047,
194 TX_BD_FLAGS_LHINT_1024_TO_2047,
195 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
196 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
197 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
198 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
199 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
200 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
201 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
202 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
203 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
204 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
205 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
206 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
207 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
208 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
209 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
210 };
211
212 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
213 {
214 struct bnxt *bp = netdev_priv(dev);
215 struct tx_bd *txbd;
216 struct tx_bd_ext *txbd1;
217 struct netdev_queue *txq;
218 int i;
219 dma_addr_t mapping;
220 unsigned int length, pad = 0;
221 u32 len, free_size, vlan_tag_flags, cfa_action, flags;
222 u16 prod, last_frag;
223 struct pci_dev *pdev = bp->pdev;
224 struct bnxt_tx_ring_info *txr;
225 struct bnxt_sw_tx_bd *tx_buf;
226
227 i = skb_get_queue_mapping(skb);
228 if (unlikely(i >= bp->tx_nr_rings)) {
229 dev_kfree_skb_any(skb);
230 return NETDEV_TX_OK;
231 }
232
233 txr = &bp->tx_ring[i];
234 txq = netdev_get_tx_queue(dev, i);
235 prod = txr->tx_prod;
236
237 free_size = bnxt_tx_avail(bp, txr);
238 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
239 netif_tx_stop_queue(txq);
240 return NETDEV_TX_BUSY;
241 }
242
243 length = skb->len;
244 len = skb_headlen(skb);
245 last_frag = skb_shinfo(skb)->nr_frags;
246
247 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
248
249 txbd->tx_bd_opaque = prod;
250
251 tx_buf = &txr->tx_buf_ring[prod];
252 tx_buf->skb = skb;
253 tx_buf->nr_frags = last_frag;
254
255 vlan_tag_flags = 0;
256 cfa_action = 0;
257 if (skb_vlan_tag_present(skb)) {
258 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
259 skb_vlan_tag_get(skb);
260 /* Currently supports 8021Q, 8021AD vlan offloads
261 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
262 */
263 if (skb->vlan_proto == htons(ETH_P_8021Q))
264 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
265 }
266
267 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
268 struct tx_push_buffer *tx_push_buf = txr->tx_push;
269 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
270 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
271 void *pdata = tx_push_buf->data;
272 u64 *end;
273 int j, push_len;
274
275 /* Set COAL_NOW to be ready quickly for the next push */
276 tx_push->tx_bd_len_flags_type =
277 cpu_to_le32((length << TX_BD_LEN_SHIFT) |
278 TX_BD_TYPE_LONG_TX_BD |
279 TX_BD_FLAGS_LHINT_512_AND_SMALLER |
280 TX_BD_FLAGS_COAL_NOW |
281 TX_BD_FLAGS_PACKET_END |
282 (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
283
284 if (skb->ip_summed == CHECKSUM_PARTIAL)
285 tx_push1->tx_bd_hsize_lflags =
286 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
287 else
288 tx_push1->tx_bd_hsize_lflags = 0;
289
290 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
291 tx_push1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
292
293 end = pdata + length;
294 end = PTR_ALIGN(end, 8) - 1;
295 *end = 0;
296
297 skb_copy_from_linear_data(skb, pdata, len);
298 pdata += len;
299 for (j = 0; j < last_frag; j++) {
300 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
301 void *fptr;
302
303 fptr = skb_frag_address_safe(frag);
304 if (!fptr)
305 goto normal_tx;
306
307 memcpy(pdata, fptr, skb_frag_size(frag));
308 pdata += skb_frag_size(frag);
309 }
310
311 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
312 txbd->tx_bd_haddr = txr->data_mapping;
313 prod = NEXT_TX(prod);
314 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
315 memcpy(txbd, tx_push1, sizeof(*txbd));
316 prod = NEXT_TX(prod);
317 tx_push->doorbell =
318 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
319 txr->tx_prod = prod;
320
321 tx_buf->is_push = 1;
322 netdev_tx_sent_queue(txq, skb->len);
323 wmb(); /* Sync is_push and byte queue before pushing data */
324
325 push_len = (length + sizeof(*tx_push) + 7) / 8;
326 if (push_len > 16) {
327 __iowrite64_copy(txr->tx_doorbell, tx_push_buf, 16);
328 __iowrite64_copy(txr->tx_doorbell + 4, tx_push_buf + 1,
329 push_len - 16);
330 } else {
331 __iowrite64_copy(txr->tx_doorbell, tx_push_buf,
332 push_len);
333 }
334
335 goto tx_done;
336 }
337
338 normal_tx:
339 if (length < BNXT_MIN_PKT_SIZE) {
340 pad = BNXT_MIN_PKT_SIZE - length;
341 if (skb_pad(skb, pad)) {
342 /* SKB already freed. */
343 tx_buf->skb = NULL;
344 return NETDEV_TX_OK;
345 }
346 length = BNXT_MIN_PKT_SIZE;
347 }
348
349 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
350
351 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
352 dev_kfree_skb_any(skb);
353 tx_buf->skb = NULL;
354 return NETDEV_TX_OK;
355 }
356
357 dma_unmap_addr_set(tx_buf, mapping, mapping);
358 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
359 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
360
361 txbd->tx_bd_haddr = cpu_to_le64(mapping);
362
363 prod = NEXT_TX(prod);
364 txbd1 = (struct tx_bd_ext *)
365 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
366
367 txbd1->tx_bd_hsize_lflags = 0;
368 if (skb_is_gso(skb)) {
369 u32 hdr_len;
370
371 if (skb->encapsulation)
372 hdr_len = skb_inner_network_offset(skb) +
373 skb_inner_network_header_len(skb) +
374 inner_tcp_hdrlen(skb);
375 else
376 hdr_len = skb_transport_offset(skb) +
377 tcp_hdrlen(skb);
378
379 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
380 TX_BD_FLAGS_T_IPID |
381 (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
382 length = skb_shinfo(skb)->gso_size;
383 txbd1->tx_bd_mss = cpu_to_le32(length);
384 length += hdr_len;
385 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
386 txbd1->tx_bd_hsize_lflags =
387 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
388 txbd1->tx_bd_mss = 0;
389 }
390
391 length >>= 9;
392 flags |= bnxt_lhint_arr[length];
393 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
394
395 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
396 txbd1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
397 for (i = 0; i < last_frag; i++) {
398 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
399
400 prod = NEXT_TX(prod);
401 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
402
403 len = skb_frag_size(frag);
404 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
405 DMA_TO_DEVICE);
406
407 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
408 goto tx_dma_error;
409
410 tx_buf = &txr->tx_buf_ring[prod];
411 dma_unmap_addr_set(tx_buf, mapping, mapping);
412
413 txbd->tx_bd_haddr = cpu_to_le64(mapping);
414
415 flags = len << TX_BD_LEN_SHIFT;
416 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
417 }
418
419 flags &= ~TX_BD_LEN;
420 txbd->tx_bd_len_flags_type =
421 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
422 TX_BD_FLAGS_PACKET_END);
423
424 netdev_tx_sent_queue(txq, skb->len);
425
426 /* Sync BD data before updating doorbell */
427 wmb();
428
429 prod = NEXT_TX(prod);
430 txr->tx_prod = prod;
431
432 writel(DB_KEY_TX | prod, txr->tx_doorbell);
433 writel(DB_KEY_TX | prod, txr->tx_doorbell);
434
435 tx_done:
436
437 mmiowb();
438
439 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
440 netif_tx_stop_queue(txq);
441
442 /* netif_tx_stop_queue() must be done before checking
443 * tx index in bnxt_tx_avail() below, because in
444 * bnxt_tx_int(), we update tx index before checking for
445 * netif_tx_queue_stopped().
446 */
447 smp_mb();
448 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
449 netif_tx_wake_queue(txq);
450 }
451 return NETDEV_TX_OK;
452
453 tx_dma_error:
454 last_frag = i;
455
456 /* start back at beginning and unmap skb */
457 prod = txr->tx_prod;
458 tx_buf = &txr->tx_buf_ring[prod];
459 tx_buf->skb = NULL;
460 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
461 skb_headlen(skb), PCI_DMA_TODEVICE);
462 prod = NEXT_TX(prod);
463
464 /* unmap remaining mapped pages */
465 for (i = 0; i < last_frag; i++) {
466 prod = NEXT_TX(prod);
467 tx_buf = &txr->tx_buf_ring[prod];
468 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
469 skb_frag_size(&skb_shinfo(skb)->frags[i]),
470 PCI_DMA_TODEVICE);
471 }
472
473 dev_kfree_skb_any(skb);
474 return NETDEV_TX_OK;
475 }
476
477 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
478 {
479 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
480 int index = txr - &bp->tx_ring[0];
481 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, index);
482 u16 cons = txr->tx_cons;
483 struct pci_dev *pdev = bp->pdev;
484 int i;
485 unsigned int tx_bytes = 0;
486
487 for (i = 0; i < nr_pkts; i++) {
488 struct bnxt_sw_tx_bd *tx_buf;
489 struct sk_buff *skb;
490 int j, last;
491
492 tx_buf = &txr->tx_buf_ring[cons];
493 cons = NEXT_TX(cons);
494 skb = tx_buf->skb;
495 tx_buf->skb = NULL;
496
497 if (tx_buf->is_push) {
498 tx_buf->is_push = 0;
499 goto next_tx_int;
500 }
501
502 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
503 skb_headlen(skb), PCI_DMA_TODEVICE);
504 last = tx_buf->nr_frags;
505
506 for (j = 0; j < last; j++) {
507 cons = NEXT_TX(cons);
508 tx_buf = &txr->tx_buf_ring[cons];
509 dma_unmap_page(
510 &pdev->dev,
511 dma_unmap_addr(tx_buf, mapping),
512 skb_frag_size(&skb_shinfo(skb)->frags[j]),
513 PCI_DMA_TODEVICE);
514 }
515
516 next_tx_int:
517 cons = NEXT_TX(cons);
518
519 tx_bytes += skb->len;
520 dev_kfree_skb_any(skb);
521 }
522
523 netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
524 txr->tx_cons = cons;
525
526 /* Need to make the tx_cons update visible to bnxt_start_xmit()
527 * before checking for netif_tx_queue_stopped(). Without the
528 * memory barrier, there is a small possibility that bnxt_start_xmit()
529 * will miss it and cause the queue to be stopped forever.
530 */
531 smp_mb();
532
533 if (unlikely(netif_tx_queue_stopped(txq)) &&
534 (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
535 __netif_tx_lock(txq, smp_processor_id());
536 if (netif_tx_queue_stopped(txq) &&
537 bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
538 txr->dev_state != BNXT_DEV_STATE_CLOSING)
539 netif_tx_wake_queue(txq);
540 __netif_tx_unlock(txq);
541 }
542 }
543
544 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
545 gfp_t gfp)
546 {
547 u8 *data;
548 struct pci_dev *pdev = bp->pdev;
549
550 data = kmalloc(bp->rx_buf_size, gfp);
551 if (!data)
552 return NULL;
553
554 *mapping = dma_map_single(&pdev->dev, data + BNXT_RX_DMA_OFFSET,
555 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
556
557 if (dma_mapping_error(&pdev->dev, *mapping)) {
558 kfree(data);
559 data = NULL;
560 }
561 return data;
562 }
563
564 static inline int bnxt_alloc_rx_data(struct bnxt *bp,
565 struct bnxt_rx_ring_info *rxr,
566 u16 prod, gfp_t gfp)
567 {
568 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
569 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
570 u8 *data;
571 dma_addr_t mapping;
572
573 data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
574 if (!data)
575 return -ENOMEM;
576
577 rx_buf->data = data;
578 dma_unmap_addr_set(rx_buf, mapping, mapping);
579
580 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
581
582 return 0;
583 }
584
585 static void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons,
586 u8 *data)
587 {
588 u16 prod = rxr->rx_prod;
589 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
590 struct rx_bd *cons_bd, *prod_bd;
591
592 prod_rx_buf = &rxr->rx_buf_ring[prod];
593 cons_rx_buf = &rxr->rx_buf_ring[cons];
594
595 prod_rx_buf->data = data;
596
597 dma_unmap_addr_set(prod_rx_buf, mapping,
598 dma_unmap_addr(cons_rx_buf, mapping));
599
600 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
601 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
602
603 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
604 }
605
606 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
607 {
608 u16 next, max = rxr->rx_agg_bmap_size;
609
610 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
611 if (next >= max)
612 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
613 return next;
614 }
615
616 static inline int bnxt_alloc_rx_page(struct bnxt *bp,
617 struct bnxt_rx_ring_info *rxr,
618 u16 prod, gfp_t gfp)
619 {
620 struct rx_bd *rxbd =
621 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
622 struct bnxt_sw_rx_agg_bd *rx_agg_buf;
623 struct pci_dev *pdev = bp->pdev;
624 struct page *page;
625 dma_addr_t mapping;
626 u16 sw_prod = rxr->rx_sw_agg_prod;
627 unsigned int offset = 0;
628
629 if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
630 page = rxr->rx_page;
631 if (!page) {
632 page = alloc_page(gfp);
633 if (!page)
634 return -ENOMEM;
635 rxr->rx_page = page;
636 rxr->rx_page_offset = 0;
637 }
638 offset = rxr->rx_page_offset;
639 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
640 if (rxr->rx_page_offset == PAGE_SIZE)
641 rxr->rx_page = NULL;
642 else
643 get_page(page);
644 } else {
645 page = alloc_page(gfp);
646 if (!page)
647 return -ENOMEM;
648 }
649
650 mapping = dma_map_page(&pdev->dev, page, offset, BNXT_RX_PAGE_SIZE,
651 PCI_DMA_FROMDEVICE);
652 if (dma_mapping_error(&pdev->dev, mapping)) {
653 __free_page(page);
654 return -EIO;
655 }
656
657 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
658 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
659
660 __set_bit(sw_prod, rxr->rx_agg_bmap);
661 rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
662 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
663
664 rx_agg_buf->page = page;
665 rx_agg_buf->offset = offset;
666 rx_agg_buf->mapping = mapping;
667 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
668 rxbd->rx_bd_opaque = sw_prod;
669 return 0;
670 }
671
672 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons,
673 u32 agg_bufs)
674 {
675 struct bnxt *bp = bnapi->bp;
676 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
677 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
678 u16 prod = rxr->rx_agg_prod;
679 u16 sw_prod = rxr->rx_sw_agg_prod;
680 u32 i;
681
682 for (i = 0; i < agg_bufs; i++) {
683 u16 cons;
684 struct rx_agg_cmp *agg;
685 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
686 struct rx_bd *prod_bd;
687 struct page *page;
688
689 agg = (struct rx_agg_cmp *)
690 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
691 cons = agg->rx_agg_cmp_opaque;
692 __clear_bit(cons, rxr->rx_agg_bmap);
693
694 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
695 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
696
697 __set_bit(sw_prod, rxr->rx_agg_bmap);
698 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
699 cons_rx_buf = &rxr->rx_agg_ring[cons];
700
701 /* It is possible for sw_prod to be equal to cons, so
702 * set cons_rx_buf->page to NULL first.
703 */
704 page = cons_rx_buf->page;
705 cons_rx_buf->page = NULL;
706 prod_rx_buf->page = page;
707 prod_rx_buf->offset = cons_rx_buf->offset;
708
709 prod_rx_buf->mapping = cons_rx_buf->mapping;
710
711 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
712
713 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
714 prod_bd->rx_bd_opaque = sw_prod;
715
716 prod = NEXT_RX_AGG(prod);
717 sw_prod = NEXT_RX_AGG(sw_prod);
718 cp_cons = NEXT_CMP(cp_cons);
719 }
720 rxr->rx_agg_prod = prod;
721 rxr->rx_sw_agg_prod = sw_prod;
722 }
723
724 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
725 struct bnxt_rx_ring_info *rxr, u16 cons,
726 u16 prod, u8 *data, dma_addr_t dma_addr,
727 unsigned int len)
728 {
729 int err;
730 struct sk_buff *skb;
731
732 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
733 if (unlikely(err)) {
734 bnxt_reuse_rx_data(rxr, cons, data);
735 return NULL;
736 }
737
738 skb = build_skb(data, 0);
739 dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
740 PCI_DMA_FROMDEVICE);
741 if (!skb) {
742 kfree(data);
743 return NULL;
744 }
745
746 skb_reserve(skb, BNXT_RX_OFFSET);
747 skb_put(skb, len);
748 return skb;
749 }
750
751 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi,
752 struct sk_buff *skb, u16 cp_cons,
753 u32 agg_bufs)
754 {
755 struct pci_dev *pdev = bp->pdev;
756 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
757 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
758 u16 prod = rxr->rx_agg_prod;
759 u32 i;
760
761 for (i = 0; i < agg_bufs; i++) {
762 u16 cons, frag_len;
763 struct rx_agg_cmp *agg;
764 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
765 struct page *page;
766 dma_addr_t mapping;
767
768 agg = (struct rx_agg_cmp *)
769 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
770 cons = agg->rx_agg_cmp_opaque;
771 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
772 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
773
774 cons_rx_buf = &rxr->rx_agg_ring[cons];
775 skb_fill_page_desc(skb, i, cons_rx_buf->page,
776 cons_rx_buf->offset, frag_len);
777 __clear_bit(cons, rxr->rx_agg_bmap);
778
779 /* It is possible for bnxt_alloc_rx_page() to allocate
780 * a sw_prod index that equals the cons index, so we
781 * need to clear the cons entry now.
782 */
783 mapping = dma_unmap_addr(cons_rx_buf, mapping);
784 page = cons_rx_buf->page;
785 cons_rx_buf->page = NULL;
786
787 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
788 struct skb_shared_info *shinfo;
789 unsigned int nr_frags;
790
791 shinfo = skb_shinfo(skb);
792 nr_frags = --shinfo->nr_frags;
793 __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
794
795 dev_kfree_skb(skb);
796
797 cons_rx_buf->page = page;
798
799 /* Update prod since possibly some pages have been
800 * allocated already.
801 */
802 rxr->rx_agg_prod = prod;
803 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i);
804 return NULL;
805 }
806
807 dma_unmap_page(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
808 PCI_DMA_FROMDEVICE);
809
810 skb->data_len += frag_len;
811 skb->len += frag_len;
812 skb->truesize += PAGE_SIZE;
813
814 prod = NEXT_RX_AGG(prod);
815 cp_cons = NEXT_CMP(cp_cons);
816 }
817 rxr->rx_agg_prod = prod;
818 return skb;
819 }
820
821 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
822 u8 agg_bufs, u32 *raw_cons)
823 {
824 u16 last;
825 struct rx_agg_cmp *agg;
826
827 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
828 last = RING_CMP(*raw_cons);
829 agg = (struct rx_agg_cmp *)
830 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
831 return RX_AGG_CMP_VALID(agg, *raw_cons);
832 }
833
834 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
835 unsigned int len,
836 dma_addr_t mapping)
837 {
838 struct bnxt *bp = bnapi->bp;
839 struct pci_dev *pdev = bp->pdev;
840 struct sk_buff *skb;
841
842 skb = napi_alloc_skb(&bnapi->napi, len);
843 if (!skb)
844 return NULL;
845
846 dma_sync_single_for_cpu(&pdev->dev, mapping,
847 bp->rx_copy_thresh, PCI_DMA_FROMDEVICE);
848
849 memcpy(skb->data - BNXT_RX_OFFSET, data, len + BNXT_RX_OFFSET);
850
851 dma_sync_single_for_device(&pdev->dev, mapping,
852 bp->rx_copy_thresh,
853 PCI_DMA_FROMDEVICE);
854
855 skb_put(skb, len);
856 return skb;
857 }
858
859 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_napi *bnapi,
860 u32 *raw_cons, void *cmp)
861 {
862 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
863 struct rx_cmp *rxcmp = cmp;
864 u32 tmp_raw_cons = *raw_cons;
865 u8 cmp_type, agg_bufs = 0;
866
867 cmp_type = RX_CMP_TYPE(rxcmp);
868
869 if (cmp_type == CMP_TYPE_RX_L2_CMP) {
870 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
871 RX_CMP_AGG_BUFS) >>
872 RX_CMP_AGG_BUFS_SHIFT;
873 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
874 struct rx_tpa_end_cmp *tpa_end = cmp;
875
876 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
877 RX_TPA_END_CMP_AGG_BUFS) >>
878 RX_TPA_END_CMP_AGG_BUFS_SHIFT;
879 }
880
881 if (agg_bufs) {
882 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
883 return -EBUSY;
884 }
885 *raw_cons = tmp_raw_cons;
886 return 0;
887 }
888
889 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
890 {
891 if (!rxr->bnapi->in_reset) {
892 rxr->bnapi->in_reset = true;
893 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
894 schedule_work(&bp->sp_task);
895 }
896 rxr->rx_next_cons = 0xffff;
897 }
898
899 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
900 struct rx_tpa_start_cmp *tpa_start,
901 struct rx_tpa_start_cmp_ext *tpa_start1)
902 {
903 u8 agg_id = TPA_START_AGG_ID(tpa_start);
904 u16 cons, prod;
905 struct bnxt_tpa_info *tpa_info;
906 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
907 struct rx_bd *prod_bd;
908 dma_addr_t mapping;
909
910 cons = tpa_start->rx_tpa_start_cmp_opaque;
911 prod = rxr->rx_prod;
912 cons_rx_buf = &rxr->rx_buf_ring[cons];
913 prod_rx_buf = &rxr->rx_buf_ring[prod];
914 tpa_info = &rxr->rx_tpa[agg_id];
915
916 if (unlikely(cons != rxr->rx_next_cons)) {
917 bnxt_sched_reset(bp, rxr);
918 return;
919 }
920
921 prod_rx_buf->data = tpa_info->data;
922
923 mapping = tpa_info->mapping;
924 dma_unmap_addr_set(prod_rx_buf, mapping, mapping);
925
926 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
927
928 prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
929
930 tpa_info->data = cons_rx_buf->data;
931 cons_rx_buf->data = NULL;
932 tpa_info->mapping = dma_unmap_addr(cons_rx_buf, mapping);
933
934 tpa_info->len =
935 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
936 RX_TPA_START_CMP_LEN_SHIFT;
937 if (likely(TPA_START_HASH_VALID(tpa_start))) {
938 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
939
940 tpa_info->hash_type = PKT_HASH_TYPE_L4;
941 tpa_info->gso_type = SKB_GSO_TCPV4;
942 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
943 if (hash_type == 3)
944 tpa_info->gso_type = SKB_GSO_TCPV6;
945 tpa_info->rss_hash =
946 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
947 } else {
948 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
949 tpa_info->gso_type = 0;
950 if (netif_msg_rx_err(bp))
951 netdev_warn(bp->dev, "TPA packet without valid hash\n");
952 }
953 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
954 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
955 tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
956
957 rxr->rx_prod = NEXT_RX(prod);
958 cons = NEXT_RX(cons);
959 rxr->rx_next_cons = NEXT_RX(cons);
960 cons_rx_buf = &rxr->rx_buf_ring[cons];
961
962 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
963 rxr->rx_prod = NEXT_RX(rxr->rx_prod);
964 cons_rx_buf->data = NULL;
965 }
966
967 static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi,
968 u16 cp_cons, u32 agg_bufs)
969 {
970 if (agg_bufs)
971 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
972 }
973
974 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info,
975 int payload_off, int tcp_ts,
976 struct sk_buff *skb)
977 {
978 #ifdef CONFIG_INET
979 struct tcphdr *th;
980 int len, nw_off;
981 u16 outer_ip_off, inner_ip_off, inner_mac_off;
982 u32 hdr_info = tpa_info->hdr_info;
983 bool loopback = false;
984
985 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
986 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
987 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
988
989 /* If the packet is an internal loopback packet, the offsets will
990 * have an extra 4 bytes.
991 */
992 if (inner_mac_off == 4) {
993 loopback = true;
994 } else if (inner_mac_off > 4) {
995 __be16 proto = *((__be16 *)(skb->data + inner_ip_off -
996 ETH_HLEN - 2));
997
998 /* We only support inner iPv4/ipv6. If we don't see the
999 * correct protocol ID, it must be a loopback packet where
1000 * the offsets are off by 4.
1001 */
1002 if (proto != htons(ETH_P_IP) && proto && htons(ETH_P_IPV6))
1003 loopback = true;
1004 }
1005 if (loopback) {
1006 /* internal loopback packet, subtract all offsets by 4 */
1007 inner_ip_off -= 4;
1008 inner_mac_off -= 4;
1009 outer_ip_off -= 4;
1010 }
1011
1012 nw_off = inner_ip_off - ETH_HLEN;
1013 skb_set_network_header(skb, nw_off);
1014 if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) {
1015 struct ipv6hdr *iph = ipv6_hdr(skb);
1016
1017 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1018 len = skb->len - skb_transport_offset(skb);
1019 th = tcp_hdr(skb);
1020 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1021 } else {
1022 struct iphdr *iph = ip_hdr(skb);
1023
1024 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1025 len = skb->len - skb_transport_offset(skb);
1026 th = tcp_hdr(skb);
1027 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1028 }
1029
1030 if (inner_mac_off) { /* tunnel */
1031 struct udphdr *uh = NULL;
1032 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1033 ETH_HLEN - 2));
1034
1035 if (proto == htons(ETH_P_IP)) {
1036 struct iphdr *iph = (struct iphdr *)skb->data;
1037
1038 if (iph->protocol == IPPROTO_UDP)
1039 uh = (struct udphdr *)(iph + 1);
1040 } else {
1041 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1042
1043 if (iph->nexthdr == IPPROTO_UDP)
1044 uh = (struct udphdr *)(iph + 1);
1045 }
1046 if (uh) {
1047 if (uh->check)
1048 skb_shinfo(skb)->gso_type |=
1049 SKB_GSO_UDP_TUNNEL_CSUM;
1050 else
1051 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1052 }
1053 }
1054 #endif
1055 return skb;
1056 }
1057
1058 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
1059 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1060
1061 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info,
1062 int payload_off, int tcp_ts,
1063 struct sk_buff *skb)
1064 {
1065 #ifdef CONFIG_INET
1066 struct tcphdr *th;
1067 int len, nw_off, tcp_opt_len;
1068
1069 if (tcp_ts)
1070 tcp_opt_len = 12;
1071
1072 if (tpa_info->gso_type == SKB_GSO_TCPV4) {
1073 struct iphdr *iph;
1074
1075 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
1076 ETH_HLEN;
1077 skb_set_network_header(skb, nw_off);
1078 iph = ip_hdr(skb);
1079 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1080 len = skb->len - skb_transport_offset(skb);
1081 th = tcp_hdr(skb);
1082 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1083 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
1084 struct ipv6hdr *iph;
1085
1086 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
1087 ETH_HLEN;
1088 skb_set_network_header(skb, nw_off);
1089 iph = ipv6_hdr(skb);
1090 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1091 len = skb->len - skb_transport_offset(skb);
1092 th = tcp_hdr(skb);
1093 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1094 } else {
1095 dev_kfree_skb_any(skb);
1096 return NULL;
1097 }
1098 tcp_gro_complete(skb);
1099
1100 if (nw_off) { /* tunnel */
1101 struct udphdr *uh = NULL;
1102
1103 if (skb->protocol == htons(ETH_P_IP)) {
1104 struct iphdr *iph = (struct iphdr *)skb->data;
1105
1106 if (iph->protocol == IPPROTO_UDP)
1107 uh = (struct udphdr *)(iph + 1);
1108 } else {
1109 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1110
1111 if (iph->nexthdr == IPPROTO_UDP)
1112 uh = (struct udphdr *)(iph + 1);
1113 }
1114 if (uh) {
1115 if (uh->check)
1116 skb_shinfo(skb)->gso_type |=
1117 SKB_GSO_UDP_TUNNEL_CSUM;
1118 else
1119 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1120 }
1121 }
1122 #endif
1123 return skb;
1124 }
1125
1126 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp,
1127 struct bnxt_tpa_info *tpa_info,
1128 struct rx_tpa_end_cmp *tpa_end,
1129 struct rx_tpa_end_cmp_ext *tpa_end1,
1130 struct sk_buff *skb)
1131 {
1132 #ifdef CONFIG_INET
1133 int payload_off;
1134 u16 segs;
1135
1136 segs = TPA_END_TPA_SEGS(tpa_end);
1137 if (segs == 1)
1138 return skb;
1139
1140 NAPI_GRO_CB(skb)->count = segs;
1141 skb_shinfo(skb)->gso_size =
1142 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1143 skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1144 payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1145 RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
1146 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
1147 skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
1148 #endif
1149 return skb;
1150 }
1151
1152 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
1153 struct bnxt_napi *bnapi,
1154 u32 *raw_cons,
1155 struct rx_tpa_end_cmp *tpa_end,
1156 struct rx_tpa_end_cmp_ext *tpa_end1,
1157 bool *agg_event)
1158 {
1159 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1160 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1161 u8 agg_id = TPA_END_AGG_ID(tpa_end);
1162 u8 *data, agg_bufs;
1163 u16 cp_cons = RING_CMP(*raw_cons);
1164 unsigned int len;
1165 struct bnxt_tpa_info *tpa_info;
1166 dma_addr_t mapping;
1167 struct sk_buff *skb;
1168
1169 if (unlikely(bnapi->in_reset)) {
1170 int rc = bnxt_discard_rx(bp, bnapi, raw_cons, tpa_end);
1171
1172 if (rc < 0)
1173 return ERR_PTR(-EBUSY);
1174 return NULL;
1175 }
1176
1177 tpa_info = &rxr->rx_tpa[agg_id];
1178 data = tpa_info->data;
1179 prefetch(data);
1180 len = tpa_info->len;
1181 mapping = tpa_info->mapping;
1182
1183 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1184 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1185
1186 if (agg_bufs) {
1187 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1188 return ERR_PTR(-EBUSY);
1189
1190 *agg_event = true;
1191 cp_cons = NEXT_CMP(cp_cons);
1192 }
1193
1194 if (unlikely(agg_bufs > MAX_SKB_FRAGS)) {
1195 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1196 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1197 agg_bufs, (int)MAX_SKB_FRAGS);
1198 return NULL;
1199 }
1200
1201 if (len <= bp->rx_copy_thresh) {
1202 skb = bnxt_copy_skb(bnapi, data, len, mapping);
1203 if (!skb) {
1204 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1205 return NULL;
1206 }
1207 } else {
1208 u8 *new_data;
1209 dma_addr_t new_mapping;
1210
1211 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1212 if (!new_data) {
1213 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1214 return NULL;
1215 }
1216
1217 tpa_info->data = new_data;
1218 tpa_info->mapping = new_mapping;
1219
1220 skb = build_skb(data, 0);
1221 dma_unmap_single(&bp->pdev->dev, mapping, bp->rx_buf_use_size,
1222 PCI_DMA_FROMDEVICE);
1223
1224 if (!skb) {
1225 kfree(data);
1226 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1227 return NULL;
1228 }
1229 skb_reserve(skb, BNXT_RX_OFFSET);
1230 skb_put(skb, len);
1231 }
1232
1233 if (agg_bufs) {
1234 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1235 if (!skb) {
1236 /* Page reuse already handled by bnxt_rx_pages(). */
1237 return NULL;
1238 }
1239 }
1240 skb->protocol = eth_type_trans(skb, bp->dev);
1241
1242 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1243 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1244
1245 if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1246 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1247 u16 vlan_proto = tpa_info->metadata >>
1248 RX_CMP_FLAGS2_METADATA_TPID_SFT;
1249 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_VID_MASK;
1250
1251 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1252 }
1253
1254 skb_checksum_none_assert(skb);
1255 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1256 skb->ip_summed = CHECKSUM_UNNECESSARY;
1257 skb->csum_level =
1258 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1259 }
1260
1261 if (TPA_END_GRO(tpa_end))
1262 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb);
1263
1264 return skb;
1265 }
1266
1267 /* returns the following:
1268 * 1 - 1 packet successfully received
1269 * 0 - successful TPA_START, packet not completed yet
1270 * -EBUSY - completion ring does not have all the agg buffers yet
1271 * -ENOMEM - packet aborted due to out of memory
1272 * -EIO - packet aborted due to hw error indicated in BD
1273 */
1274 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons,
1275 bool *agg_event)
1276 {
1277 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1278 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1279 struct net_device *dev = bp->dev;
1280 struct rx_cmp *rxcmp;
1281 struct rx_cmp_ext *rxcmp1;
1282 u32 tmp_raw_cons = *raw_cons;
1283 u16 cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1284 struct bnxt_sw_rx_bd *rx_buf;
1285 unsigned int len;
1286 u8 *data, agg_bufs, cmp_type;
1287 dma_addr_t dma_addr;
1288 struct sk_buff *skb;
1289 int rc = 0;
1290
1291 rxcmp = (struct rx_cmp *)
1292 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1293
1294 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1295 cp_cons = RING_CMP(tmp_raw_cons);
1296 rxcmp1 = (struct rx_cmp_ext *)
1297 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1298
1299 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1300 return -EBUSY;
1301
1302 cmp_type = RX_CMP_TYPE(rxcmp);
1303
1304 prod = rxr->rx_prod;
1305
1306 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1307 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1308 (struct rx_tpa_start_cmp_ext *)rxcmp1);
1309
1310 goto next_rx_no_prod;
1311
1312 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1313 skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons,
1314 (struct rx_tpa_end_cmp *)rxcmp,
1315 (struct rx_tpa_end_cmp_ext *)rxcmp1,
1316 agg_event);
1317
1318 if (unlikely(IS_ERR(skb)))
1319 return -EBUSY;
1320
1321 rc = -ENOMEM;
1322 if (likely(skb)) {
1323 skb_record_rx_queue(skb, bnapi->index);
1324 skb_mark_napi_id(skb, &bnapi->napi);
1325 if (bnxt_busy_polling(bnapi))
1326 netif_receive_skb(skb);
1327 else
1328 napi_gro_receive(&bnapi->napi, skb);
1329 rc = 1;
1330 }
1331 goto next_rx_no_prod;
1332 }
1333
1334 cons = rxcmp->rx_cmp_opaque;
1335 rx_buf = &rxr->rx_buf_ring[cons];
1336 data = rx_buf->data;
1337 if (unlikely(cons != rxr->rx_next_cons)) {
1338 int rc1 = bnxt_discard_rx(bp, bnapi, raw_cons, rxcmp);
1339
1340 bnxt_sched_reset(bp, rxr);
1341 return rc1;
1342 }
1343 prefetch(data);
1344
1345 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) & RX_CMP_AGG_BUFS) >>
1346 RX_CMP_AGG_BUFS_SHIFT;
1347
1348 if (agg_bufs) {
1349 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1350 return -EBUSY;
1351
1352 cp_cons = NEXT_CMP(cp_cons);
1353 *agg_event = true;
1354 }
1355
1356 rx_buf->data = NULL;
1357 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1358 bnxt_reuse_rx_data(rxr, cons, data);
1359 if (agg_bufs)
1360 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1361
1362 rc = -EIO;
1363 goto next_rx;
1364 }
1365
1366 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1367 dma_addr = dma_unmap_addr(rx_buf, mapping);
1368
1369 if (len <= bp->rx_copy_thresh) {
1370 skb = bnxt_copy_skb(bnapi, data, len, dma_addr);
1371 bnxt_reuse_rx_data(rxr, cons, data);
1372 if (!skb) {
1373 rc = -ENOMEM;
1374 goto next_rx;
1375 }
1376 } else {
1377 skb = bnxt_rx_skb(bp, rxr, cons, prod, data, dma_addr, len);
1378 if (!skb) {
1379 rc = -ENOMEM;
1380 goto next_rx;
1381 }
1382 }
1383
1384 if (agg_bufs) {
1385 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1386 if (!skb) {
1387 rc = -ENOMEM;
1388 goto next_rx;
1389 }
1390 }
1391
1392 if (RX_CMP_HASH_VALID(rxcmp)) {
1393 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1394 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1395
1396 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1397 if (hash_type != 1 && hash_type != 3)
1398 type = PKT_HASH_TYPE_L3;
1399 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1400 }
1401
1402 skb->protocol = eth_type_trans(skb, dev);
1403
1404 if ((rxcmp1->rx_cmp_flags2 &
1405 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
1406 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1407 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1408 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_VID_MASK;
1409 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1410
1411 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1412 }
1413
1414 skb_checksum_none_assert(skb);
1415 if (RX_CMP_L4_CS_OK(rxcmp1)) {
1416 if (dev->features & NETIF_F_RXCSUM) {
1417 skb->ip_summed = CHECKSUM_UNNECESSARY;
1418 skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1419 }
1420 } else {
1421 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1422 if (dev->features & NETIF_F_RXCSUM)
1423 cpr->rx_l4_csum_errors++;
1424 }
1425 }
1426
1427 skb_record_rx_queue(skb, bnapi->index);
1428 skb_mark_napi_id(skb, &bnapi->napi);
1429 if (bnxt_busy_polling(bnapi))
1430 netif_receive_skb(skb);
1431 else
1432 napi_gro_receive(&bnapi->napi, skb);
1433 rc = 1;
1434
1435 next_rx:
1436 rxr->rx_prod = NEXT_RX(prod);
1437 rxr->rx_next_cons = NEXT_RX(cons);
1438
1439 next_rx_no_prod:
1440 *raw_cons = tmp_raw_cons;
1441
1442 return rc;
1443 }
1444
1445 #define BNXT_GET_EVENT_PORT(data) \
1446 ((data) & \
1447 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
1448
1449 static int bnxt_async_event_process(struct bnxt *bp,
1450 struct hwrm_async_event_cmpl *cmpl)
1451 {
1452 u16 event_id = le16_to_cpu(cmpl->event_id);
1453
1454 /* TODO CHIMP_FW: Define event id's for link change, error etc */
1455 switch (event_id) {
1456 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
1457 u32 data1 = le32_to_cpu(cmpl->event_data1);
1458 struct bnxt_link_info *link_info = &bp->link_info;
1459
1460 if (BNXT_VF(bp))
1461 goto async_event_process_exit;
1462 if (data1 & 0x20000) {
1463 u16 fw_speed = link_info->force_link_speed;
1464 u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
1465
1466 netdev_warn(bp->dev, "Link speed %d no longer supported\n",
1467 speed);
1468 }
1469 /* fall thru */
1470 }
1471 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
1472 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
1473 break;
1474 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
1475 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
1476 break;
1477 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
1478 u32 data1 = le32_to_cpu(cmpl->event_data1);
1479 u16 port_id = BNXT_GET_EVENT_PORT(data1);
1480
1481 if (BNXT_VF(bp))
1482 break;
1483
1484 if (bp->pf.port_id != port_id)
1485 break;
1486
1487 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
1488 break;
1489 }
1490 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE:
1491 if (BNXT_PF(bp))
1492 goto async_event_process_exit;
1493 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
1494 break;
1495 default:
1496 netdev_err(bp->dev, "unhandled ASYNC event (id 0x%x)\n",
1497 event_id);
1498 goto async_event_process_exit;
1499 }
1500 schedule_work(&bp->sp_task);
1501 async_event_process_exit:
1502 return 0;
1503 }
1504
1505 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1506 {
1507 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1508 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1509 struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1510 (struct hwrm_fwd_req_cmpl *)txcmp;
1511
1512 switch (cmpl_type) {
1513 case CMPL_BASE_TYPE_HWRM_DONE:
1514 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1515 if (seq_id == bp->hwrm_intr_seq_id)
1516 bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID;
1517 else
1518 netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1519 break;
1520
1521 case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1522 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1523
1524 if ((vf_id < bp->pf.first_vf_id) ||
1525 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1526 netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1527 vf_id);
1528 return -EINVAL;
1529 }
1530
1531 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1532 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1533 schedule_work(&bp->sp_task);
1534 break;
1535
1536 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1537 bnxt_async_event_process(bp,
1538 (struct hwrm_async_event_cmpl *)txcmp);
1539
1540 default:
1541 break;
1542 }
1543
1544 return 0;
1545 }
1546
1547 static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1548 {
1549 struct bnxt_napi *bnapi = dev_instance;
1550 struct bnxt *bp = bnapi->bp;
1551 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1552 u32 cons = RING_CMP(cpr->cp_raw_cons);
1553
1554 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1555 napi_schedule(&bnapi->napi);
1556 return IRQ_HANDLED;
1557 }
1558
1559 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1560 {
1561 u32 raw_cons = cpr->cp_raw_cons;
1562 u16 cons = RING_CMP(raw_cons);
1563 struct tx_cmp *txcmp;
1564
1565 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1566
1567 return TX_CMP_VALID(txcmp, raw_cons);
1568 }
1569
1570 static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1571 {
1572 struct bnxt_napi *bnapi = dev_instance;
1573 struct bnxt *bp = bnapi->bp;
1574 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1575 u32 cons = RING_CMP(cpr->cp_raw_cons);
1576 u32 int_status;
1577
1578 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1579
1580 if (!bnxt_has_work(bp, cpr)) {
1581 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
1582 /* return if erroneous interrupt */
1583 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1584 return IRQ_NONE;
1585 }
1586
1587 /* disable ring IRQ */
1588 BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell);
1589
1590 /* Return here if interrupt is shared and is disabled. */
1591 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1592 return IRQ_HANDLED;
1593
1594 napi_schedule(&bnapi->napi);
1595 return IRQ_HANDLED;
1596 }
1597
1598 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
1599 {
1600 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1601 u32 raw_cons = cpr->cp_raw_cons;
1602 u32 cons;
1603 int tx_pkts = 0;
1604 int rx_pkts = 0;
1605 bool rx_event = false;
1606 bool agg_event = false;
1607 struct tx_cmp *txcmp;
1608
1609 while (1) {
1610 int rc;
1611
1612 cons = RING_CMP(raw_cons);
1613 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1614
1615 if (!TX_CMP_VALID(txcmp, raw_cons))
1616 break;
1617
1618 /* The valid test of the entry must be done first before
1619 * reading any further.
1620 */
1621 dma_rmb();
1622 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1623 tx_pkts++;
1624 /* return full budget so NAPI will complete. */
1625 if (unlikely(tx_pkts > bp->tx_wake_thresh))
1626 rx_pkts = budget;
1627 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1628 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &agg_event);
1629 if (likely(rc >= 0))
1630 rx_pkts += rc;
1631 else if (rc == -EBUSY) /* partial completion */
1632 break;
1633 rx_event = true;
1634 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1635 CMPL_BASE_TYPE_HWRM_DONE) ||
1636 (TX_CMP_TYPE(txcmp) ==
1637 CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1638 (TX_CMP_TYPE(txcmp) ==
1639 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1640 bnxt_hwrm_handler(bp, txcmp);
1641 }
1642 raw_cons = NEXT_RAW_CMP(raw_cons);
1643
1644 if (rx_pkts == budget)
1645 break;
1646 }
1647
1648 cpr->cp_raw_cons = raw_cons;
1649 /* ACK completion ring before freeing tx ring and producing new
1650 * buffers in rx/agg rings to prevent overflowing the completion
1651 * ring.
1652 */
1653 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1654
1655 if (tx_pkts)
1656 bnxt_tx_int(bp, bnapi, tx_pkts);
1657
1658 if (rx_event) {
1659 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1660
1661 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1662 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1663 if (agg_event) {
1664 writel(DB_KEY_RX | rxr->rx_agg_prod,
1665 rxr->rx_agg_doorbell);
1666 writel(DB_KEY_RX | rxr->rx_agg_prod,
1667 rxr->rx_agg_doorbell);
1668 }
1669 }
1670 return rx_pkts;
1671 }
1672
1673 static int bnxt_poll(struct napi_struct *napi, int budget)
1674 {
1675 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1676 struct bnxt *bp = bnapi->bp;
1677 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1678 int work_done = 0;
1679
1680 if (!bnxt_lock_napi(bnapi))
1681 return budget;
1682
1683 while (1) {
1684 work_done += bnxt_poll_work(bp, bnapi, budget - work_done);
1685
1686 if (work_done >= budget)
1687 break;
1688
1689 if (!bnxt_has_work(bp, cpr)) {
1690 napi_complete(napi);
1691 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1692 break;
1693 }
1694 }
1695 mmiowb();
1696 bnxt_unlock_napi(bnapi);
1697 return work_done;
1698 }
1699
1700 #ifdef CONFIG_NET_RX_BUSY_POLL
1701 static int bnxt_busy_poll(struct napi_struct *napi)
1702 {
1703 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1704 struct bnxt *bp = bnapi->bp;
1705 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1706 int rx_work, budget = 4;
1707
1708 if (atomic_read(&bp->intr_sem) != 0)
1709 return LL_FLUSH_FAILED;
1710
1711 if (!bnxt_lock_poll(bnapi))
1712 return LL_FLUSH_BUSY;
1713
1714 rx_work = bnxt_poll_work(bp, bnapi, budget);
1715
1716 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1717
1718 bnxt_unlock_poll(bnapi);
1719 return rx_work;
1720 }
1721 #endif
1722
1723 static void bnxt_free_tx_skbs(struct bnxt *bp)
1724 {
1725 int i, max_idx;
1726 struct pci_dev *pdev = bp->pdev;
1727
1728 if (!bp->tx_ring)
1729 return;
1730
1731 max_idx = bp->tx_nr_pages * TX_DESC_CNT;
1732 for (i = 0; i < bp->tx_nr_rings; i++) {
1733 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
1734 int j;
1735
1736 for (j = 0; j < max_idx;) {
1737 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
1738 struct sk_buff *skb = tx_buf->skb;
1739 int k, last;
1740
1741 if (!skb) {
1742 j++;
1743 continue;
1744 }
1745
1746 tx_buf->skb = NULL;
1747
1748 if (tx_buf->is_push) {
1749 dev_kfree_skb(skb);
1750 j += 2;
1751 continue;
1752 }
1753
1754 dma_unmap_single(&pdev->dev,
1755 dma_unmap_addr(tx_buf, mapping),
1756 skb_headlen(skb),
1757 PCI_DMA_TODEVICE);
1758
1759 last = tx_buf->nr_frags;
1760 j += 2;
1761 for (k = 0; k < last; k++, j++) {
1762 int ring_idx = j & bp->tx_ring_mask;
1763 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
1764
1765 tx_buf = &txr->tx_buf_ring[ring_idx];
1766 dma_unmap_page(
1767 &pdev->dev,
1768 dma_unmap_addr(tx_buf, mapping),
1769 skb_frag_size(frag), PCI_DMA_TODEVICE);
1770 }
1771 dev_kfree_skb(skb);
1772 }
1773 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
1774 }
1775 }
1776
1777 static void bnxt_free_rx_skbs(struct bnxt *bp)
1778 {
1779 int i, max_idx, max_agg_idx;
1780 struct pci_dev *pdev = bp->pdev;
1781
1782 if (!bp->rx_ring)
1783 return;
1784
1785 max_idx = bp->rx_nr_pages * RX_DESC_CNT;
1786 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
1787 for (i = 0; i < bp->rx_nr_rings; i++) {
1788 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
1789 int j;
1790
1791 if (rxr->rx_tpa) {
1792 for (j = 0; j < MAX_TPA; j++) {
1793 struct bnxt_tpa_info *tpa_info =
1794 &rxr->rx_tpa[j];
1795 u8 *data = tpa_info->data;
1796
1797 if (!data)
1798 continue;
1799
1800 dma_unmap_single(
1801 &pdev->dev,
1802 dma_unmap_addr(tpa_info, mapping),
1803 bp->rx_buf_use_size,
1804 PCI_DMA_FROMDEVICE);
1805
1806 tpa_info->data = NULL;
1807
1808 kfree(data);
1809 }
1810 }
1811
1812 for (j = 0; j < max_idx; j++) {
1813 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
1814 u8 *data = rx_buf->data;
1815
1816 if (!data)
1817 continue;
1818
1819 dma_unmap_single(&pdev->dev,
1820 dma_unmap_addr(rx_buf, mapping),
1821 bp->rx_buf_use_size,
1822 PCI_DMA_FROMDEVICE);
1823
1824 rx_buf->data = NULL;
1825
1826 kfree(data);
1827 }
1828
1829 for (j = 0; j < max_agg_idx; j++) {
1830 struct bnxt_sw_rx_agg_bd *rx_agg_buf =
1831 &rxr->rx_agg_ring[j];
1832 struct page *page = rx_agg_buf->page;
1833
1834 if (!page)
1835 continue;
1836
1837 dma_unmap_page(&pdev->dev,
1838 dma_unmap_addr(rx_agg_buf, mapping),
1839 BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE);
1840
1841 rx_agg_buf->page = NULL;
1842 __clear_bit(j, rxr->rx_agg_bmap);
1843
1844 __free_page(page);
1845 }
1846 if (rxr->rx_page) {
1847 __free_page(rxr->rx_page);
1848 rxr->rx_page = NULL;
1849 }
1850 }
1851 }
1852
1853 static void bnxt_free_skbs(struct bnxt *bp)
1854 {
1855 bnxt_free_tx_skbs(bp);
1856 bnxt_free_rx_skbs(bp);
1857 }
1858
1859 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
1860 {
1861 struct pci_dev *pdev = bp->pdev;
1862 int i;
1863
1864 for (i = 0; i < ring->nr_pages; i++) {
1865 if (!ring->pg_arr[i])
1866 continue;
1867
1868 dma_free_coherent(&pdev->dev, ring->page_size,
1869 ring->pg_arr[i], ring->dma_arr[i]);
1870
1871 ring->pg_arr[i] = NULL;
1872 }
1873 if (ring->pg_tbl) {
1874 dma_free_coherent(&pdev->dev, ring->nr_pages * 8,
1875 ring->pg_tbl, ring->pg_tbl_map);
1876 ring->pg_tbl = NULL;
1877 }
1878 if (ring->vmem_size && *ring->vmem) {
1879 vfree(*ring->vmem);
1880 *ring->vmem = NULL;
1881 }
1882 }
1883
1884 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
1885 {
1886 int i;
1887 struct pci_dev *pdev = bp->pdev;
1888
1889 if (ring->nr_pages > 1) {
1890 ring->pg_tbl = dma_alloc_coherent(&pdev->dev,
1891 ring->nr_pages * 8,
1892 &ring->pg_tbl_map,
1893 GFP_KERNEL);
1894 if (!ring->pg_tbl)
1895 return -ENOMEM;
1896 }
1897
1898 for (i = 0; i < ring->nr_pages; i++) {
1899 ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
1900 ring->page_size,
1901 &ring->dma_arr[i],
1902 GFP_KERNEL);
1903 if (!ring->pg_arr[i])
1904 return -ENOMEM;
1905
1906 if (ring->nr_pages > 1)
1907 ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]);
1908 }
1909
1910 if (ring->vmem_size) {
1911 *ring->vmem = vzalloc(ring->vmem_size);
1912 if (!(*ring->vmem))
1913 return -ENOMEM;
1914 }
1915 return 0;
1916 }
1917
1918 static void bnxt_free_rx_rings(struct bnxt *bp)
1919 {
1920 int i;
1921
1922 if (!bp->rx_ring)
1923 return;
1924
1925 for (i = 0; i < bp->rx_nr_rings; i++) {
1926 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
1927 struct bnxt_ring_struct *ring;
1928
1929 kfree(rxr->rx_tpa);
1930 rxr->rx_tpa = NULL;
1931
1932 kfree(rxr->rx_agg_bmap);
1933 rxr->rx_agg_bmap = NULL;
1934
1935 ring = &rxr->rx_ring_struct;
1936 bnxt_free_ring(bp, ring);
1937
1938 ring = &rxr->rx_agg_ring_struct;
1939 bnxt_free_ring(bp, ring);
1940 }
1941 }
1942
1943 static int bnxt_alloc_rx_rings(struct bnxt *bp)
1944 {
1945 int i, rc, agg_rings = 0, tpa_rings = 0;
1946
1947 if (!bp->rx_ring)
1948 return -ENOMEM;
1949
1950 if (bp->flags & BNXT_FLAG_AGG_RINGS)
1951 agg_rings = 1;
1952
1953 if (bp->flags & BNXT_FLAG_TPA)
1954 tpa_rings = 1;
1955
1956 for (i = 0; i < bp->rx_nr_rings; i++) {
1957 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
1958 struct bnxt_ring_struct *ring;
1959
1960 ring = &rxr->rx_ring_struct;
1961
1962 rc = bnxt_alloc_ring(bp, ring);
1963 if (rc)
1964 return rc;
1965
1966 if (agg_rings) {
1967 u16 mem_size;
1968
1969 ring = &rxr->rx_agg_ring_struct;
1970 rc = bnxt_alloc_ring(bp, ring);
1971 if (rc)
1972 return rc;
1973
1974 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
1975 mem_size = rxr->rx_agg_bmap_size / 8;
1976 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
1977 if (!rxr->rx_agg_bmap)
1978 return -ENOMEM;
1979
1980 if (tpa_rings) {
1981 rxr->rx_tpa = kcalloc(MAX_TPA,
1982 sizeof(struct bnxt_tpa_info),
1983 GFP_KERNEL);
1984 if (!rxr->rx_tpa)
1985 return -ENOMEM;
1986 }
1987 }
1988 }
1989 return 0;
1990 }
1991
1992 static void bnxt_free_tx_rings(struct bnxt *bp)
1993 {
1994 int i;
1995 struct pci_dev *pdev = bp->pdev;
1996
1997 if (!bp->tx_ring)
1998 return;
1999
2000 for (i = 0; i < bp->tx_nr_rings; i++) {
2001 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2002 struct bnxt_ring_struct *ring;
2003
2004 if (txr->tx_push) {
2005 dma_free_coherent(&pdev->dev, bp->tx_push_size,
2006 txr->tx_push, txr->tx_push_mapping);
2007 txr->tx_push = NULL;
2008 }
2009
2010 ring = &txr->tx_ring_struct;
2011
2012 bnxt_free_ring(bp, ring);
2013 }
2014 }
2015
2016 static int bnxt_alloc_tx_rings(struct bnxt *bp)
2017 {
2018 int i, j, rc;
2019 struct pci_dev *pdev = bp->pdev;
2020
2021 bp->tx_push_size = 0;
2022 if (bp->tx_push_thresh) {
2023 int push_size;
2024
2025 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
2026 bp->tx_push_thresh);
2027
2028 if (push_size > 256) {
2029 push_size = 0;
2030 bp->tx_push_thresh = 0;
2031 }
2032
2033 bp->tx_push_size = push_size;
2034 }
2035
2036 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
2037 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2038 struct bnxt_ring_struct *ring;
2039
2040 ring = &txr->tx_ring_struct;
2041
2042 rc = bnxt_alloc_ring(bp, ring);
2043 if (rc)
2044 return rc;
2045
2046 if (bp->tx_push_size) {
2047 dma_addr_t mapping;
2048
2049 /* One pre-allocated DMA buffer to backup
2050 * TX push operation
2051 */
2052 txr->tx_push = dma_alloc_coherent(&pdev->dev,
2053 bp->tx_push_size,
2054 &txr->tx_push_mapping,
2055 GFP_KERNEL);
2056
2057 if (!txr->tx_push)
2058 return -ENOMEM;
2059
2060 mapping = txr->tx_push_mapping +
2061 sizeof(struct tx_push_bd);
2062 txr->data_mapping = cpu_to_le64(mapping);
2063
2064 memset(txr->tx_push, 0, sizeof(struct tx_push_bd));
2065 }
2066 ring->queue_id = bp->q_info[j].queue_id;
2067 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
2068 j++;
2069 }
2070 return 0;
2071 }
2072
2073 static void bnxt_free_cp_rings(struct bnxt *bp)
2074 {
2075 int i;
2076
2077 if (!bp->bnapi)
2078 return;
2079
2080 for (i = 0; i < bp->cp_nr_rings; i++) {
2081 struct bnxt_napi *bnapi = bp->bnapi[i];
2082 struct bnxt_cp_ring_info *cpr;
2083 struct bnxt_ring_struct *ring;
2084
2085 if (!bnapi)
2086 continue;
2087
2088 cpr = &bnapi->cp_ring;
2089 ring = &cpr->cp_ring_struct;
2090
2091 bnxt_free_ring(bp, ring);
2092 }
2093 }
2094
2095 static int bnxt_alloc_cp_rings(struct bnxt *bp)
2096 {
2097 int i, rc;
2098
2099 for (i = 0; i < bp->cp_nr_rings; i++) {
2100 struct bnxt_napi *bnapi = bp->bnapi[i];
2101 struct bnxt_cp_ring_info *cpr;
2102 struct bnxt_ring_struct *ring;
2103
2104 if (!bnapi)
2105 continue;
2106
2107 cpr = &bnapi->cp_ring;
2108 ring = &cpr->cp_ring_struct;
2109
2110 rc = bnxt_alloc_ring(bp, ring);
2111 if (rc)
2112 return rc;
2113 }
2114 return 0;
2115 }
2116
2117 static void bnxt_init_ring_struct(struct bnxt *bp)
2118 {
2119 int i;
2120
2121 for (i = 0; i < bp->cp_nr_rings; i++) {
2122 struct bnxt_napi *bnapi = bp->bnapi[i];
2123 struct bnxt_cp_ring_info *cpr;
2124 struct bnxt_rx_ring_info *rxr;
2125 struct bnxt_tx_ring_info *txr;
2126 struct bnxt_ring_struct *ring;
2127
2128 if (!bnapi)
2129 continue;
2130
2131 cpr = &bnapi->cp_ring;
2132 ring = &cpr->cp_ring_struct;
2133 ring->nr_pages = bp->cp_nr_pages;
2134 ring->page_size = HW_CMPD_RING_SIZE;
2135 ring->pg_arr = (void **)cpr->cp_desc_ring;
2136 ring->dma_arr = cpr->cp_desc_mapping;
2137 ring->vmem_size = 0;
2138
2139 rxr = bnapi->rx_ring;
2140 if (!rxr)
2141 goto skip_rx;
2142
2143 ring = &rxr->rx_ring_struct;
2144 ring->nr_pages = bp->rx_nr_pages;
2145 ring->page_size = HW_RXBD_RING_SIZE;
2146 ring->pg_arr = (void **)rxr->rx_desc_ring;
2147 ring->dma_arr = rxr->rx_desc_mapping;
2148 ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
2149 ring->vmem = (void **)&rxr->rx_buf_ring;
2150
2151 ring = &rxr->rx_agg_ring_struct;
2152 ring->nr_pages = bp->rx_agg_nr_pages;
2153 ring->page_size = HW_RXBD_RING_SIZE;
2154 ring->pg_arr = (void **)rxr->rx_agg_desc_ring;
2155 ring->dma_arr = rxr->rx_agg_desc_mapping;
2156 ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
2157 ring->vmem = (void **)&rxr->rx_agg_ring;
2158
2159 skip_rx:
2160 txr = bnapi->tx_ring;
2161 if (!txr)
2162 continue;
2163
2164 ring = &txr->tx_ring_struct;
2165 ring->nr_pages = bp->tx_nr_pages;
2166 ring->page_size = HW_RXBD_RING_SIZE;
2167 ring->pg_arr = (void **)txr->tx_desc_ring;
2168 ring->dma_arr = txr->tx_desc_mapping;
2169 ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
2170 ring->vmem = (void **)&txr->tx_buf_ring;
2171 }
2172 }
2173
2174 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
2175 {
2176 int i;
2177 u32 prod;
2178 struct rx_bd **rx_buf_ring;
2179
2180 rx_buf_ring = (struct rx_bd **)ring->pg_arr;
2181 for (i = 0, prod = 0; i < ring->nr_pages; i++) {
2182 int j;
2183 struct rx_bd *rxbd;
2184
2185 rxbd = rx_buf_ring[i];
2186 if (!rxbd)
2187 continue;
2188
2189 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
2190 rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
2191 rxbd->rx_bd_opaque = prod;
2192 }
2193 }
2194 }
2195
2196 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
2197 {
2198 struct net_device *dev = bp->dev;
2199 struct bnxt_rx_ring_info *rxr;
2200 struct bnxt_ring_struct *ring;
2201 u32 prod, type;
2202 int i;
2203
2204 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
2205 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
2206
2207 if (NET_IP_ALIGN == 2)
2208 type |= RX_BD_FLAGS_SOP;
2209
2210 rxr = &bp->rx_ring[ring_nr];
2211 ring = &rxr->rx_ring_struct;
2212 bnxt_init_rxbd_pages(ring, type);
2213
2214 prod = rxr->rx_prod;
2215 for (i = 0; i < bp->rx_ring_size; i++) {
2216 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
2217 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
2218 ring_nr, i, bp->rx_ring_size);
2219 break;
2220 }
2221 prod = NEXT_RX(prod);
2222 }
2223 rxr->rx_prod = prod;
2224 ring->fw_ring_id = INVALID_HW_RING_ID;
2225
2226 ring = &rxr->rx_agg_ring_struct;
2227 ring->fw_ring_id = INVALID_HW_RING_ID;
2228
2229 if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
2230 return 0;
2231
2232 type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
2233 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
2234
2235 bnxt_init_rxbd_pages(ring, type);
2236
2237 prod = rxr->rx_agg_prod;
2238 for (i = 0; i < bp->rx_agg_ring_size; i++) {
2239 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
2240 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
2241 ring_nr, i, bp->rx_ring_size);
2242 break;
2243 }
2244 prod = NEXT_RX_AGG(prod);
2245 }
2246 rxr->rx_agg_prod = prod;
2247
2248 if (bp->flags & BNXT_FLAG_TPA) {
2249 if (rxr->rx_tpa) {
2250 u8 *data;
2251 dma_addr_t mapping;
2252
2253 for (i = 0; i < MAX_TPA; i++) {
2254 data = __bnxt_alloc_rx_data(bp, &mapping,
2255 GFP_KERNEL);
2256 if (!data)
2257 return -ENOMEM;
2258
2259 rxr->rx_tpa[i].data = data;
2260 rxr->rx_tpa[i].mapping = mapping;
2261 }
2262 } else {
2263 netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2264 return -ENOMEM;
2265 }
2266 }
2267
2268 return 0;
2269 }
2270
2271 static int bnxt_init_rx_rings(struct bnxt *bp)
2272 {
2273 int i, rc = 0;
2274
2275 for (i = 0; i < bp->rx_nr_rings; i++) {
2276 rc = bnxt_init_one_rx_ring(bp, i);
2277 if (rc)
2278 break;
2279 }
2280
2281 return rc;
2282 }
2283
2284 static int bnxt_init_tx_rings(struct bnxt *bp)
2285 {
2286 u16 i;
2287
2288 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2289 MAX_SKB_FRAGS + 1);
2290
2291 for (i = 0; i < bp->tx_nr_rings; i++) {
2292 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2293 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2294
2295 ring->fw_ring_id = INVALID_HW_RING_ID;
2296 }
2297
2298 return 0;
2299 }
2300
2301 static void bnxt_free_ring_grps(struct bnxt *bp)
2302 {
2303 kfree(bp->grp_info);
2304 bp->grp_info = NULL;
2305 }
2306
2307 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2308 {
2309 int i;
2310
2311 if (irq_re_init) {
2312 bp->grp_info = kcalloc(bp->cp_nr_rings,
2313 sizeof(struct bnxt_ring_grp_info),
2314 GFP_KERNEL);
2315 if (!bp->grp_info)
2316 return -ENOMEM;
2317 }
2318 for (i = 0; i < bp->cp_nr_rings; i++) {
2319 if (irq_re_init)
2320 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
2321 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
2322 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
2323 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
2324 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
2325 }
2326 return 0;
2327 }
2328
2329 static void bnxt_free_vnics(struct bnxt *bp)
2330 {
2331 kfree(bp->vnic_info);
2332 bp->vnic_info = NULL;
2333 bp->nr_vnics = 0;
2334 }
2335
2336 static int bnxt_alloc_vnics(struct bnxt *bp)
2337 {
2338 int num_vnics = 1;
2339
2340 #ifdef CONFIG_RFS_ACCEL
2341 if (bp->flags & BNXT_FLAG_RFS)
2342 num_vnics += bp->rx_nr_rings;
2343 #endif
2344
2345 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
2346 GFP_KERNEL);
2347 if (!bp->vnic_info)
2348 return -ENOMEM;
2349
2350 bp->nr_vnics = num_vnics;
2351 return 0;
2352 }
2353
2354 static void bnxt_init_vnics(struct bnxt *bp)
2355 {
2356 int i;
2357
2358 for (i = 0; i < bp->nr_vnics; i++) {
2359 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2360
2361 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2362 vnic->fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
2363 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
2364
2365 if (bp->vnic_info[i].rss_hash_key) {
2366 if (i == 0)
2367 prandom_bytes(vnic->rss_hash_key,
2368 HW_HASH_KEY_SIZE);
2369 else
2370 memcpy(vnic->rss_hash_key,
2371 bp->vnic_info[0].rss_hash_key,
2372 HW_HASH_KEY_SIZE);
2373 }
2374 }
2375 }
2376
2377 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
2378 {
2379 int pages;
2380
2381 pages = ring_size / desc_per_pg;
2382
2383 if (!pages)
2384 return 1;
2385
2386 pages++;
2387
2388 while (pages & (pages - 1))
2389 pages++;
2390
2391 return pages;
2392 }
2393
2394 static void bnxt_set_tpa_flags(struct bnxt *bp)
2395 {
2396 bp->flags &= ~BNXT_FLAG_TPA;
2397 if (bp->dev->features & NETIF_F_LRO)
2398 bp->flags |= BNXT_FLAG_LRO;
2399 if (bp->dev->features & NETIF_F_GRO)
2400 bp->flags |= BNXT_FLAG_GRO;
2401 }
2402
2403 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2404 * be set on entry.
2405 */
2406 void bnxt_set_ring_params(struct bnxt *bp)
2407 {
2408 u32 ring_size, rx_size, rx_space;
2409 u32 agg_factor = 0, agg_ring_size = 0;
2410
2411 /* 8 for CRC and VLAN */
2412 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
2413
2414 rx_space = rx_size + NET_SKB_PAD +
2415 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2416
2417 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
2418 ring_size = bp->rx_ring_size;
2419 bp->rx_agg_ring_size = 0;
2420 bp->rx_agg_nr_pages = 0;
2421
2422 if (bp->flags & BNXT_FLAG_TPA)
2423 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
2424
2425 bp->flags &= ~BNXT_FLAG_JUMBO;
2426 if (rx_space > PAGE_SIZE) {
2427 u32 jumbo_factor;
2428
2429 bp->flags |= BNXT_FLAG_JUMBO;
2430 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
2431 if (jumbo_factor > agg_factor)
2432 agg_factor = jumbo_factor;
2433 }
2434 agg_ring_size = ring_size * agg_factor;
2435
2436 if (agg_ring_size) {
2437 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
2438 RX_DESC_CNT);
2439 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
2440 u32 tmp = agg_ring_size;
2441
2442 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
2443 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
2444 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
2445 tmp, agg_ring_size);
2446 }
2447 bp->rx_agg_ring_size = agg_ring_size;
2448 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
2449 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
2450 rx_space = rx_size + NET_SKB_PAD +
2451 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2452 }
2453
2454 bp->rx_buf_use_size = rx_size;
2455 bp->rx_buf_size = rx_space;
2456
2457 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
2458 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
2459
2460 ring_size = bp->tx_ring_size;
2461 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
2462 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
2463
2464 ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
2465 bp->cp_ring_size = ring_size;
2466
2467 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
2468 if (bp->cp_nr_pages > MAX_CP_PAGES) {
2469 bp->cp_nr_pages = MAX_CP_PAGES;
2470 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
2471 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
2472 ring_size, bp->cp_ring_size);
2473 }
2474 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
2475 bp->cp_ring_mask = bp->cp_bit - 1;
2476 }
2477
2478 static void bnxt_free_vnic_attributes(struct bnxt *bp)
2479 {
2480 int i;
2481 struct bnxt_vnic_info *vnic;
2482 struct pci_dev *pdev = bp->pdev;
2483
2484 if (!bp->vnic_info)
2485 return;
2486
2487 for (i = 0; i < bp->nr_vnics; i++) {
2488 vnic = &bp->vnic_info[i];
2489
2490 kfree(vnic->fw_grp_ids);
2491 vnic->fw_grp_ids = NULL;
2492
2493 kfree(vnic->uc_list);
2494 vnic->uc_list = NULL;
2495
2496 if (vnic->mc_list) {
2497 dma_free_coherent(&pdev->dev, vnic->mc_list_size,
2498 vnic->mc_list, vnic->mc_list_mapping);
2499 vnic->mc_list = NULL;
2500 }
2501
2502 if (vnic->rss_table) {
2503 dma_free_coherent(&pdev->dev, PAGE_SIZE,
2504 vnic->rss_table,
2505 vnic->rss_table_dma_addr);
2506 vnic->rss_table = NULL;
2507 }
2508
2509 vnic->rss_hash_key = NULL;
2510 vnic->flags = 0;
2511 }
2512 }
2513
2514 static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
2515 {
2516 int i, rc = 0, size;
2517 struct bnxt_vnic_info *vnic;
2518 struct pci_dev *pdev = bp->pdev;
2519 int max_rings;
2520
2521 for (i = 0; i < bp->nr_vnics; i++) {
2522 vnic = &bp->vnic_info[i];
2523
2524 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
2525 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
2526
2527 if (mem_size > 0) {
2528 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
2529 if (!vnic->uc_list) {
2530 rc = -ENOMEM;
2531 goto out;
2532 }
2533 }
2534 }
2535
2536 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
2537 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
2538 vnic->mc_list =
2539 dma_alloc_coherent(&pdev->dev,
2540 vnic->mc_list_size,
2541 &vnic->mc_list_mapping,
2542 GFP_KERNEL);
2543 if (!vnic->mc_list) {
2544 rc = -ENOMEM;
2545 goto out;
2546 }
2547 }
2548
2549 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
2550 max_rings = bp->rx_nr_rings;
2551 else
2552 max_rings = 1;
2553
2554 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
2555 if (!vnic->fw_grp_ids) {
2556 rc = -ENOMEM;
2557 goto out;
2558 }
2559
2560 /* Allocate rss table and hash key */
2561 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2562 &vnic->rss_table_dma_addr,
2563 GFP_KERNEL);
2564 if (!vnic->rss_table) {
2565 rc = -ENOMEM;
2566 goto out;
2567 }
2568
2569 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
2570
2571 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
2572 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
2573 }
2574 return 0;
2575
2576 out:
2577 return rc;
2578 }
2579
2580 static void bnxt_free_hwrm_resources(struct bnxt *bp)
2581 {
2582 struct pci_dev *pdev = bp->pdev;
2583
2584 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
2585 bp->hwrm_cmd_resp_dma_addr);
2586
2587 bp->hwrm_cmd_resp_addr = NULL;
2588 if (bp->hwrm_dbg_resp_addr) {
2589 dma_free_coherent(&pdev->dev, HWRM_DBG_REG_BUF_SIZE,
2590 bp->hwrm_dbg_resp_addr,
2591 bp->hwrm_dbg_resp_dma_addr);
2592
2593 bp->hwrm_dbg_resp_addr = NULL;
2594 }
2595 }
2596
2597 static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2598 {
2599 struct pci_dev *pdev = bp->pdev;
2600
2601 bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2602 &bp->hwrm_cmd_resp_dma_addr,
2603 GFP_KERNEL);
2604 if (!bp->hwrm_cmd_resp_addr)
2605 return -ENOMEM;
2606 bp->hwrm_dbg_resp_addr = dma_alloc_coherent(&pdev->dev,
2607 HWRM_DBG_REG_BUF_SIZE,
2608 &bp->hwrm_dbg_resp_dma_addr,
2609 GFP_KERNEL);
2610 if (!bp->hwrm_dbg_resp_addr)
2611 netdev_warn(bp->dev, "fail to alloc debug register dma mem\n");
2612
2613 return 0;
2614 }
2615
2616 static void bnxt_free_stats(struct bnxt *bp)
2617 {
2618 u32 size, i;
2619 struct pci_dev *pdev = bp->pdev;
2620
2621 if (bp->hw_rx_port_stats) {
2622 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size,
2623 bp->hw_rx_port_stats,
2624 bp->hw_rx_port_stats_map);
2625 bp->hw_rx_port_stats = NULL;
2626 bp->flags &= ~BNXT_FLAG_PORT_STATS;
2627 }
2628
2629 if (!bp->bnapi)
2630 return;
2631
2632 size = sizeof(struct ctx_hw_stats);
2633
2634 for (i = 0; i < bp->cp_nr_rings; i++) {
2635 struct bnxt_napi *bnapi = bp->bnapi[i];
2636 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2637
2638 if (cpr->hw_stats) {
2639 dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
2640 cpr->hw_stats_map);
2641 cpr->hw_stats = NULL;
2642 }
2643 }
2644 }
2645
2646 static int bnxt_alloc_stats(struct bnxt *bp)
2647 {
2648 u32 size, i;
2649 struct pci_dev *pdev = bp->pdev;
2650
2651 size = sizeof(struct ctx_hw_stats);
2652
2653 for (i = 0; i < bp->cp_nr_rings; i++) {
2654 struct bnxt_napi *bnapi = bp->bnapi[i];
2655 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2656
2657 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
2658 &cpr->hw_stats_map,
2659 GFP_KERNEL);
2660 if (!cpr->hw_stats)
2661 return -ENOMEM;
2662
2663 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
2664 }
2665
2666 if (BNXT_PF(bp)) {
2667 bp->hw_port_stats_size = sizeof(struct rx_port_stats) +
2668 sizeof(struct tx_port_stats) + 1024;
2669
2670 bp->hw_rx_port_stats =
2671 dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size,
2672 &bp->hw_rx_port_stats_map,
2673 GFP_KERNEL);
2674 if (!bp->hw_rx_port_stats)
2675 return -ENOMEM;
2676
2677 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) +
2678 512;
2679 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map +
2680 sizeof(struct rx_port_stats) + 512;
2681 bp->flags |= BNXT_FLAG_PORT_STATS;
2682 }
2683 return 0;
2684 }
2685
2686 static void bnxt_clear_ring_indices(struct bnxt *bp)
2687 {
2688 int i;
2689
2690 if (!bp->bnapi)
2691 return;
2692
2693 for (i = 0; i < bp->cp_nr_rings; i++) {
2694 struct bnxt_napi *bnapi = bp->bnapi[i];
2695 struct bnxt_cp_ring_info *cpr;
2696 struct bnxt_rx_ring_info *rxr;
2697 struct bnxt_tx_ring_info *txr;
2698
2699 if (!bnapi)
2700 continue;
2701
2702 cpr = &bnapi->cp_ring;
2703 cpr->cp_raw_cons = 0;
2704
2705 txr = bnapi->tx_ring;
2706 if (txr) {
2707 txr->tx_prod = 0;
2708 txr->tx_cons = 0;
2709 }
2710
2711 rxr = bnapi->rx_ring;
2712 if (rxr) {
2713 rxr->rx_prod = 0;
2714 rxr->rx_agg_prod = 0;
2715 rxr->rx_sw_agg_prod = 0;
2716 rxr->rx_next_cons = 0;
2717 }
2718 }
2719 }
2720
2721 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
2722 {
2723 #ifdef CONFIG_RFS_ACCEL
2724 int i;
2725
2726 /* Under rtnl_lock and all our NAPIs have been disabled. It's
2727 * safe to delete the hash table.
2728 */
2729 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
2730 struct hlist_head *head;
2731 struct hlist_node *tmp;
2732 struct bnxt_ntuple_filter *fltr;
2733
2734 head = &bp->ntp_fltr_hash_tbl[i];
2735 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
2736 hlist_del(&fltr->hash);
2737 kfree(fltr);
2738 }
2739 }
2740 if (irq_reinit) {
2741 kfree(bp->ntp_fltr_bmap);
2742 bp->ntp_fltr_bmap = NULL;
2743 }
2744 bp->ntp_fltr_count = 0;
2745 #endif
2746 }
2747
2748 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
2749 {
2750 #ifdef CONFIG_RFS_ACCEL
2751 int i, rc = 0;
2752
2753 if (!(bp->flags & BNXT_FLAG_RFS))
2754 return 0;
2755
2756 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
2757 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
2758
2759 bp->ntp_fltr_count = 0;
2760 bp->ntp_fltr_bmap = kzalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
2761 GFP_KERNEL);
2762
2763 if (!bp->ntp_fltr_bmap)
2764 rc = -ENOMEM;
2765
2766 return rc;
2767 #else
2768 return 0;
2769 #endif
2770 }
2771
2772 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
2773 {
2774 bnxt_free_vnic_attributes(bp);
2775 bnxt_free_tx_rings(bp);
2776 bnxt_free_rx_rings(bp);
2777 bnxt_free_cp_rings(bp);
2778 bnxt_free_ntp_fltrs(bp, irq_re_init);
2779 if (irq_re_init) {
2780 bnxt_free_stats(bp);
2781 bnxt_free_ring_grps(bp);
2782 bnxt_free_vnics(bp);
2783 kfree(bp->tx_ring);
2784 bp->tx_ring = NULL;
2785 kfree(bp->rx_ring);
2786 bp->rx_ring = NULL;
2787 kfree(bp->bnapi);
2788 bp->bnapi = NULL;
2789 } else {
2790 bnxt_clear_ring_indices(bp);
2791 }
2792 }
2793
2794 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
2795 {
2796 int i, j, rc, size, arr_size;
2797 void *bnapi;
2798
2799 if (irq_re_init) {
2800 /* Allocate bnapi mem pointer array and mem block for
2801 * all queues
2802 */
2803 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
2804 bp->cp_nr_rings);
2805 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
2806 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
2807 if (!bnapi)
2808 return -ENOMEM;
2809
2810 bp->bnapi = bnapi;
2811 bnapi += arr_size;
2812 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
2813 bp->bnapi[i] = bnapi;
2814 bp->bnapi[i]->index = i;
2815 bp->bnapi[i]->bp = bp;
2816 }
2817
2818 bp->rx_ring = kcalloc(bp->rx_nr_rings,
2819 sizeof(struct bnxt_rx_ring_info),
2820 GFP_KERNEL);
2821 if (!bp->rx_ring)
2822 return -ENOMEM;
2823
2824 for (i = 0; i < bp->rx_nr_rings; i++) {
2825 bp->rx_ring[i].bnapi = bp->bnapi[i];
2826 bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
2827 }
2828
2829 bp->tx_ring = kcalloc(bp->tx_nr_rings,
2830 sizeof(struct bnxt_tx_ring_info),
2831 GFP_KERNEL);
2832 if (!bp->tx_ring)
2833 return -ENOMEM;
2834
2835 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
2836 j = 0;
2837 else
2838 j = bp->rx_nr_rings;
2839
2840 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
2841 bp->tx_ring[i].bnapi = bp->bnapi[j];
2842 bp->bnapi[j]->tx_ring = &bp->tx_ring[i];
2843 }
2844
2845 rc = bnxt_alloc_stats(bp);
2846 if (rc)
2847 goto alloc_mem_err;
2848
2849 rc = bnxt_alloc_ntp_fltrs(bp);
2850 if (rc)
2851 goto alloc_mem_err;
2852
2853 rc = bnxt_alloc_vnics(bp);
2854 if (rc)
2855 goto alloc_mem_err;
2856 }
2857
2858 bnxt_init_ring_struct(bp);
2859
2860 rc = bnxt_alloc_rx_rings(bp);
2861 if (rc)
2862 goto alloc_mem_err;
2863
2864 rc = bnxt_alloc_tx_rings(bp);
2865 if (rc)
2866 goto alloc_mem_err;
2867
2868 rc = bnxt_alloc_cp_rings(bp);
2869 if (rc)
2870 goto alloc_mem_err;
2871
2872 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
2873 BNXT_VNIC_UCAST_FLAG;
2874 rc = bnxt_alloc_vnic_attributes(bp);
2875 if (rc)
2876 goto alloc_mem_err;
2877 return 0;
2878
2879 alloc_mem_err:
2880 bnxt_free_mem(bp, true);
2881 return rc;
2882 }
2883
2884 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
2885 u16 cmpl_ring, u16 target_id)
2886 {
2887 struct input *req = request;
2888
2889 req->req_type = cpu_to_le16(req_type);
2890 req->cmpl_ring = cpu_to_le16(cmpl_ring);
2891 req->target_id = cpu_to_le16(target_id);
2892 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
2893 }
2894
2895 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
2896 int timeout, bool silent)
2897 {
2898 int i, intr_process, rc, tmo_count;
2899 struct input *req = msg;
2900 u32 *data = msg;
2901 __le32 *resp_len, *valid;
2902 u16 cp_ring_id, len = 0;
2903 struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
2904
2905 req->seq_id = cpu_to_le16(bp->hwrm_cmd_seq++);
2906 memset(resp, 0, PAGE_SIZE);
2907 cp_ring_id = le16_to_cpu(req->cmpl_ring);
2908 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
2909
2910 /* Write request msg to hwrm channel */
2911 __iowrite32_copy(bp->bar0, data, msg_len / 4);
2912
2913 for (i = msg_len; i < BNXT_HWRM_MAX_REQ_LEN; i += 4)
2914 writel(0, bp->bar0 + i);
2915
2916 /* currently supports only one outstanding message */
2917 if (intr_process)
2918 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
2919
2920 /* Ring channel doorbell */
2921 writel(1, bp->bar0 + 0x100);
2922
2923 if (!timeout)
2924 timeout = DFLT_HWRM_CMD_TIMEOUT;
2925
2926 i = 0;
2927 tmo_count = timeout * 40;
2928 if (intr_process) {
2929 /* Wait until hwrm response cmpl interrupt is processed */
2930 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID &&
2931 i++ < tmo_count) {
2932 usleep_range(25, 40);
2933 }
2934
2935 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) {
2936 netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
2937 le16_to_cpu(req->req_type));
2938 return -1;
2939 }
2940 } else {
2941 /* Check if response len is updated */
2942 resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET;
2943 for (i = 0; i < tmo_count; i++) {
2944 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
2945 HWRM_RESP_LEN_SFT;
2946 if (len)
2947 break;
2948 usleep_range(25, 40);
2949 }
2950
2951 if (i >= tmo_count) {
2952 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
2953 timeout, le16_to_cpu(req->req_type),
2954 le16_to_cpu(req->seq_id), len);
2955 return -1;
2956 }
2957
2958 /* Last word of resp contains valid bit */
2959 valid = bp->hwrm_cmd_resp_addr + len - 4;
2960 for (i = 0; i < 5; i++) {
2961 if (le32_to_cpu(*valid) & HWRM_RESP_VALID_MASK)
2962 break;
2963 udelay(1);
2964 }
2965
2966 if (i >= 5) {
2967 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
2968 timeout, le16_to_cpu(req->req_type),
2969 le16_to_cpu(req->seq_id), len, *valid);
2970 return -1;
2971 }
2972 }
2973
2974 rc = le16_to_cpu(resp->error_code);
2975 if (rc && !silent)
2976 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
2977 le16_to_cpu(resp->req_type),
2978 le16_to_cpu(resp->seq_id), rc);
2979 return rc;
2980 }
2981
2982 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
2983 {
2984 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
2985 }
2986
2987 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
2988 {
2989 int rc;
2990
2991 mutex_lock(&bp->hwrm_cmd_lock);
2992 rc = _hwrm_send_message(bp, msg, msg_len, timeout);
2993 mutex_unlock(&bp->hwrm_cmd_lock);
2994 return rc;
2995 }
2996
2997 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
2998 int timeout)
2999 {
3000 int rc;
3001
3002 mutex_lock(&bp->hwrm_cmd_lock);
3003 rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3004 mutex_unlock(&bp->hwrm_cmd_lock);
3005 return rc;
3006 }
3007
3008 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
3009 {
3010 struct hwrm_func_drv_rgtr_input req = {0};
3011 int i;
3012 DECLARE_BITMAP(async_events_bmap, 256);
3013 u32 *events = (u32 *)async_events_bmap;
3014
3015 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3016
3017 req.enables =
3018 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
3019 FUNC_DRV_RGTR_REQ_ENABLES_VER |
3020 FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
3021
3022 memset(async_events_bmap, 0, sizeof(async_events_bmap));
3023 for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++)
3024 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
3025
3026 for (i = 0; i < 8; i++)
3027 req.async_event_fwd[i] |= cpu_to_le32(events[i]);
3028
3029 req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
3030 req.ver_maj = DRV_VER_MAJ;
3031 req.ver_min = DRV_VER_MIN;
3032 req.ver_upd = DRV_VER_UPD;
3033
3034 if (BNXT_PF(bp)) {
3035 DECLARE_BITMAP(vf_req_snif_bmap, 256);
3036 u32 *data = (u32 *)vf_req_snif_bmap;
3037
3038 memset(vf_req_snif_bmap, 0, sizeof(vf_req_snif_bmap));
3039 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++)
3040 __set_bit(bnxt_vf_req_snif[i], vf_req_snif_bmap);
3041
3042 for (i = 0; i < 8; i++)
3043 req.vf_req_fwd[i] = cpu_to_le32(data[i]);
3044
3045 req.enables |=
3046 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
3047 }
3048
3049 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3050 }
3051
3052 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
3053 {
3054 struct hwrm_func_drv_unrgtr_input req = {0};
3055
3056 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
3057 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3058 }
3059
3060 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
3061 {
3062 u32 rc = 0;
3063 struct hwrm_tunnel_dst_port_free_input req = {0};
3064
3065 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
3066 req.tunnel_type = tunnel_type;
3067
3068 switch (tunnel_type) {
3069 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
3070 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
3071 break;
3072 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
3073 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
3074 break;
3075 default:
3076 break;
3077 }
3078
3079 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3080 if (rc)
3081 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
3082 rc);
3083 return rc;
3084 }
3085
3086 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
3087 u8 tunnel_type)
3088 {
3089 u32 rc = 0;
3090 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3091 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3092
3093 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
3094
3095 req.tunnel_type = tunnel_type;
3096 req.tunnel_dst_port_val = port;
3097
3098 mutex_lock(&bp->hwrm_cmd_lock);
3099 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3100 if (rc) {
3101 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
3102 rc);
3103 goto err_out;
3104 }
3105
3106 if (tunnel_type & TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN)
3107 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3108
3109 else if (tunnel_type & TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE)
3110 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
3111 err_out:
3112 mutex_unlock(&bp->hwrm_cmd_lock);
3113 return rc;
3114 }
3115
3116 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
3117 {
3118 struct hwrm_cfa_l2_set_rx_mask_input req = {0};
3119 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3120
3121 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
3122 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3123
3124 req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
3125 req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
3126 req.mask = cpu_to_le32(vnic->rx_mask);
3127 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3128 }
3129
3130 #ifdef CONFIG_RFS_ACCEL
3131 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
3132 struct bnxt_ntuple_filter *fltr)
3133 {
3134 struct hwrm_cfa_ntuple_filter_free_input req = {0};
3135
3136 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
3137 req.ntuple_filter_id = fltr->filter_id;
3138 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3139 }
3140
3141 #define BNXT_NTP_FLTR_FLAGS \
3142 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
3143 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
3144 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
3145 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
3146 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
3147 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
3148 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
3149 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
3150 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
3151 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
3152 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
3153 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
3154 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
3155 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
3156
3157 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
3158 struct bnxt_ntuple_filter *fltr)
3159 {
3160 int rc = 0;
3161 struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
3162 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3163 bp->hwrm_cmd_resp_addr;
3164 struct flow_keys *keys = &fltr->fkeys;
3165 struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1];
3166
3167 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
3168 req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[0];
3169
3170 req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
3171
3172 req.ethertype = htons(ETH_P_IP);
3173 memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
3174 req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
3175 req.ip_protocol = keys->basic.ip_proto;
3176
3177 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
3178 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3179 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
3180 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3181
3182 req.src_port = keys->ports.src;
3183 req.src_port_mask = cpu_to_be16(0xffff);
3184 req.dst_port = keys->ports.dst;
3185 req.dst_port_mask = cpu_to_be16(0xffff);
3186
3187 req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
3188 mutex_lock(&bp->hwrm_cmd_lock);
3189 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3190 if (!rc)
3191 fltr->filter_id = resp->ntuple_filter_id;
3192 mutex_unlock(&bp->hwrm_cmd_lock);
3193 return rc;
3194 }
3195 #endif
3196
3197 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
3198 u8 *mac_addr)
3199 {
3200 u32 rc = 0;
3201 struct hwrm_cfa_l2_filter_alloc_input req = {0};
3202 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3203
3204 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
3205 req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX |
3206 CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
3207 req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
3208 req.enables =
3209 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
3210 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
3211 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
3212 memcpy(req.l2_addr, mac_addr, ETH_ALEN);
3213 req.l2_addr_mask[0] = 0xff;
3214 req.l2_addr_mask[1] = 0xff;
3215 req.l2_addr_mask[2] = 0xff;
3216 req.l2_addr_mask[3] = 0xff;
3217 req.l2_addr_mask[4] = 0xff;
3218 req.l2_addr_mask[5] = 0xff;
3219
3220 mutex_lock(&bp->hwrm_cmd_lock);
3221 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3222 if (!rc)
3223 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
3224 resp->l2_filter_id;
3225 mutex_unlock(&bp->hwrm_cmd_lock);
3226 return rc;
3227 }
3228
3229 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
3230 {
3231 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
3232 int rc = 0;
3233
3234 /* Any associated ntuple filters will also be cleared by firmware. */
3235 mutex_lock(&bp->hwrm_cmd_lock);
3236 for (i = 0; i < num_of_vnics; i++) {
3237 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3238
3239 for (j = 0; j < vnic->uc_filter_count; j++) {
3240 struct hwrm_cfa_l2_filter_free_input req = {0};
3241
3242 bnxt_hwrm_cmd_hdr_init(bp, &req,
3243 HWRM_CFA_L2_FILTER_FREE, -1, -1);
3244
3245 req.l2_filter_id = vnic->fw_l2_filter_id[j];
3246
3247 rc = _hwrm_send_message(bp, &req, sizeof(req),
3248 HWRM_CMD_TIMEOUT);
3249 }
3250 vnic->uc_filter_count = 0;
3251 }
3252 mutex_unlock(&bp->hwrm_cmd_lock);
3253
3254 return rc;
3255 }
3256
3257 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
3258 {
3259 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3260 struct hwrm_vnic_tpa_cfg_input req = {0};
3261
3262 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
3263
3264 if (tpa_flags) {
3265 u16 mss = bp->dev->mtu - 40;
3266 u32 nsegs, n, segs = 0, flags;
3267
3268 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
3269 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
3270 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
3271 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
3272 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
3273 if (tpa_flags & BNXT_FLAG_GRO)
3274 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
3275
3276 req.flags = cpu_to_le32(flags);
3277
3278 req.enables =
3279 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
3280 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
3281 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
3282
3283 /* Number of segs are log2 units, and first packet is not
3284 * included as part of this units.
3285 */
3286 if (mss <= BNXT_RX_PAGE_SIZE) {
3287 n = BNXT_RX_PAGE_SIZE / mss;
3288 nsegs = (MAX_SKB_FRAGS - 1) * n;
3289 } else {
3290 n = mss / BNXT_RX_PAGE_SIZE;
3291 if (mss & (BNXT_RX_PAGE_SIZE - 1))
3292 n++;
3293 nsegs = (MAX_SKB_FRAGS - n) / n;
3294 }
3295
3296 segs = ilog2(nsegs);
3297 req.max_agg_segs = cpu_to_le16(segs);
3298 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
3299
3300 req.min_agg_len = cpu_to_le32(512);
3301 }
3302 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3303
3304 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3305 }
3306
3307 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
3308 {
3309 u32 i, j, max_rings;
3310 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3311 struct hwrm_vnic_rss_cfg_input req = {0};
3312
3313 if (vnic->fw_rss_cos_lb_ctx == INVALID_HW_RING_ID)
3314 return 0;
3315
3316 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
3317 if (set_rss) {
3318 vnic->hash_type = BNXT_RSS_HASH_TYPE_FLAG_IPV4 |
3319 BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV4 |
3320 BNXT_RSS_HASH_TYPE_FLAG_IPV6 |
3321 BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV6;
3322
3323 req.hash_type = cpu_to_le32(vnic->hash_type);
3324
3325 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3326 max_rings = bp->rx_nr_rings;
3327 else
3328 max_rings = 1;
3329
3330 /* Fill the RSS indirection table with ring group ids */
3331 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
3332 if (j == max_rings)
3333 j = 0;
3334 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
3335 }
3336
3337 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
3338 req.hash_key_tbl_addr =
3339 cpu_to_le64(vnic->rss_hash_key_dma_addr);
3340 }
3341 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx);
3342 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3343 }
3344
3345 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
3346 {
3347 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3348 struct hwrm_vnic_plcmodes_cfg_input req = {0};
3349
3350 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
3351 req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
3352 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
3353 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
3354 req.enables =
3355 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
3356 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
3357 /* thresholds not implemented in firmware yet */
3358 req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
3359 req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
3360 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3361 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3362 }
3363
3364 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id)
3365 {
3366 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
3367
3368 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
3369 req.rss_cos_lb_ctx_id =
3370 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx);
3371
3372 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3373 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
3374 }
3375
3376 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
3377 {
3378 int i;
3379
3380 for (i = 0; i < bp->nr_vnics; i++) {
3381 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3382
3383 if (vnic->fw_rss_cos_lb_ctx != INVALID_HW_RING_ID)
3384 bnxt_hwrm_vnic_ctx_free_one(bp, i);
3385 }
3386 bp->rsscos_nr_ctxs = 0;
3387 }
3388
3389 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id)
3390 {
3391 int rc;
3392 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
3393 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
3394 bp->hwrm_cmd_resp_addr;
3395
3396 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
3397 -1);
3398
3399 mutex_lock(&bp->hwrm_cmd_lock);
3400 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3401 if (!rc)
3402 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx =
3403 le16_to_cpu(resp->rss_cos_lb_ctx_id);
3404 mutex_unlock(&bp->hwrm_cmd_lock);
3405
3406 return rc;
3407 }
3408
3409 static int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
3410 {
3411 unsigned int ring = 0, grp_idx;
3412 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3413 struct hwrm_vnic_cfg_input req = {0};
3414 u16 def_vlan = 0;
3415
3416 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
3417 /* Only RSS support for now TBD: COS & LB */
3418 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP |
3419 VNIC_CFG_REQ_ENABLES_RSS_RULE);
3420 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx);
3421 req.cos_rule = cpu_to_le16(0xffff);
3422 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3423 ring = 0;
3424 else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
3425 ring = vnic_id - 1;
3426
3427 grp_idx = bp->rx_ring[ring].bnapi->index;
3428 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3429 req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
3430
3431 req.lb_rule = cpu_to_le16(0xffff);
3432 req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
3433 VLAN_HLEN);
3434
3435 #ifdef CONFIG_BNXT_SRIOV
3436 if (BNXT_VF(bp))
3437 def_vlan = bp->vf.vlan;
3438 #endif
3439 if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
3440 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
3441
3442 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3443 }
3444
3445 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
3446 {
3447 u32 rc = 0;
3448
3449 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
3450 struct hwrm_vnic_free_input req = {0};
3451
3452 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
3453 req.vnic_id =
3454 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
3455
3456 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3457 if (rc)
3458 return rc;
3459 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
3460 }
3461 return rc;
3462 }
3463
3464 static void bnxt_hwrm_vnic_free(struct bnxt *bp)
3465 {
3466 u16 i;
3467
3468 for (i = 0; i < bp->nr_vnics; i++)
3469 bnxt_hwrm_vnic_free_one(bp, i);
3470 }
3471
3472 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
3473 unsigned int start_rx_ring_idx,
3474 unsigned int nr_rings)
3475 {
3476 int rc = 0;
3477 unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
3478 struct hwrm_vnic_alloc_input req = {0};
3479 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3480
3481 /* map ring groups to this vnic */
3482 for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
3483 grp_idx = bp->rx_ring[i].bnapi->index;
3484 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
3485 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
3486 j, nr_rings);
3487 break;
3488 }
3489 bp->vnic_info[vnic_id].fw_grp_ids[j] =
3490 bp->grp_info[grp_idx].fw_grp_id;
3491 }
3492
3493 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
3494 if (vnic_id == 0)
3495 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
3496
3497 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
3498
3499 mutex_lock(&bp->hwrm_cmd_lock);
3500 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3501 if (!rc)
3502 bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id);
3503 mutex_unlock(&bp->hwrm_cmd_lock);
3504 return rc;
3505 }
3506
3507 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
3508 {
3509 u16 i;
3510 u32 rc = 0;
3511
3512 mutex_lock(&bp->hwrm_cmd_lock);
3513 for (i = 0; i < bp->rx_nr_rings; i++) {
3514 struct hwrm_ring_grp_alloc_input req = {0};
3515 struct hwrm_ring_grp_alloc_output *resp =
3516 bp->hwrm_cmd_resp_addr;
3517 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
3518
3519 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
3520
3521 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
3522 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
3523 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
3524 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
3525
3526 rc = _hwrm_send_message(bp, &req, sizeof(req),
3527 HWRM_CMD_TIMEOUT);
3528 if (rc)
3529 break;
3530
3531 bp->grp_info[grp_idx].fw_grp_id =
3532 le32_to_cpu(resp->ring_group_id);
3533 }
3534 mutex_unlock(&bp->hwrm_cmd_lock);
3535 return rc;
3536 }
3537
3538 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
3539 {
3540 u16 i;
3541 u32 rc = 0;
3542 struct hwrm_ring_grp_free_input req = {0};
3543
3544 if (!bp->grp_info)
3545 return 0;
3546
3547 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
3548
3549 mutex_lock(&bp->hwrm_cmd_lock);
3550 for (i = 0; i < bp->cp_nr_rings; i++) {
3551 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
3552 continue;
3553 req.ring_group_id =
3554 cpu_to_le32(bp->grp_info[i].fw_grp_id);
3555
3556 rc = _hwrm_send_message(bp, &req, sizeof(req),
3557 HWRM_CMD_TIMEOUT);
3558 if (rc)
3559 break;
3560 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
3561 }
3562 mutex_unlock(&bp->hwrm_cmd_lock);
3563 return rc;
3564 }
3565
3566 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
3567 struct bnxt_ring_struct *ring,
3568 u32 ring_type, u32 map_index,
3569 u32 stats_ctx_id)
3570 {
3571 int rc = 0, err = 0;
3572 struct hwrm_ring_alloc_input req = {0};
3573 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3574 u16 ring_id;
3575
3576 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
3577
3578 req.enables = 0;
3579 if (ring->nr_pages > 1) {
3580 req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map);
3581 /* Page size is in log2 units */
3582 req.page_size = BNXT_PAGE_SHIFT;
3583 req.page_tbl_depth = 1;
3584 } else {
3585 req.page_tbl_addr = cpu_to_le64(ring->dma_arr[0]);
3586 }
3587 req.fbo = 0;
3588 /* Association of ring index with doorbell index and MSIX number */
3589 req.logical_id = cpu_to_le16(map_index);
3590
3591 switch (ring_type) {
3592 case HWRM_RING_ALLOC_TX:
3593 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
3594 /* Association of transmit ring with completion ring */
3595 req.cmpl_ring_id =
3596 cpu_to_le16(bp->grp_info[map_index].cp_fw_ring_id);
3597 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
3598 req.stat_ctx_id = cpu_to_le32(stats_ctx_id);
3599 req.queue_id = cpu_to_le16(ring->queue_id);
3600 break;
3601 case HWRM_RING_ALLOC_RX:
3602 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3603 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
3604 break;
3605 case HWRM_RING_ALLOC_AGG:
3606 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3607 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
3608 break;
3609 case HWRM_RING_ALLOC_CMPL:
3610 req.ring_type = RING_ALLOC_REQ_RING_TYPE_CMPL;
3611 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
3612 if (bp->flags & BNXT_FLAG_USING_MSIX)
3613 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
3614 break;
3615 default:
3616 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
3617 ring_type);
3618 return -1;
3619 }
3620
3621 mutex_lock(&bp->hwrm_cmd_lock);
3622 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3623 err = le16_to_cpu(resp->error_code);
3624 ring_id = le16_to_cpu(resp->ring_id);
3625 mutex_unlock(&bp->hwrm_cmd_lock);
3626
3627 if (rc || err) {
3628 switch (ring_type) {
3629 case RING_FREE_REQ_RING_TYPE_CMPL:
3630 netdev_err(bp->dev, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
3631 rc, err);
3632 return -1;
3633
3634 case RING_FREE_REQ_RING_TYPE_RX:
3635 netdev_err(bp->dev, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
3636 rc, err);
3637 return -1;
3638
3639 case RING_FREE_REQ_RING_TYPE_TX:
3640 netdev_err(bp->dev, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
3641 rc, err);
3642 return -1;
3643
3644 default:
3645 netdev_err(bp->dev, "Invalid ring\n");
3646 return -1;
3647 }
3648 }
3649 ring->fw_ring_id = ring_id;
3650 return rc;
3651 }
3652
3653 static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
3654 {
3655 int i, rc = 0;
3656
3657 for (i = 0; i < bp->cp_nr_rings; i++) {
3658 struct bnxt_napi *bnapi = bp->bnapi[i];
3659 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3660 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3661
3662 cpr->cp_doorbell = bp->bar1 + i * 0x80;
3663 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL, i,
3664 INVALID_STATS_CTX_ID);
3665 if (rc)
3666 goto err_out;
3667 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
3668 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
3669 }
3670
3671 for (i = 0; i < bp->tx_nr_rings; i++) {
3672 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3673 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
3674 u32 map_idx = txr->bnapi->index;
3675 u16 fw_stats_ctx = bp->grp_info[map_idx].fw_stats_ctx;
3676
3677 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_TX,
3678 map_idx, fw_stats_ctx);
3679 if (rc)
3680 goto err_out;
3681 txr->tx_doorbell = bp->bar1 + map_idx * 0x80;
3682 }
3683
3684 for (i = 0; i < bp->rx_nr_rings; i++) {
3685 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3686 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
3687 u32 map_idx = rxr->bnapi->index;
3688
3689 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_RX,
3690 map_idx, INVALID_STATS_CTX_ID);
3691 if (rc)
3692 goto err_out;
3693 rxr->rx_doorbell = bp->bar1 + map_idx * 0x80;
3694 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
3695 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
3696 }
3697
3698 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
3699 for (i = 0; i < bp->rx_nr_rings; i++) {
3700 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3701 struct bnxt_ring_struct *ring =
3702 &rxr->rx_agg_ring_struct;
3703 u32 grp_idx = rxr->bnapi->index;
3704 u32 map_idx = grp_idx + bp->rx_nr_rings;
3705
3706 rc = hwrm_ring_alloc_send_msg(bp, ring,
3707 HWRM_RING_ALLOC_AGG,
3708 map_idx,
3709 INVALID_STATS_CTX_ID);
3710 if (rc)
3711 goto err_out;
3712
3713 rxr->rx_agg_doorbell = bp->bar1 + map_idx * 0x80;
3714 writel(DB_KEY_RX | rxr->rx_agg_prod,
3715 rxr->rx_agg_doorbell);
3716 bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
3717 }
3718 }
3719 err_out:
3720 return rc;
3721 }
3722
3723 static int hwrm_ring_free_send_msg(struct bnxt *bp,
3724 struct bnxt_ring_struct *ring,
3725 u32 ring_type, int cmpl_ring_id)
3726 {
3727 int rc;
3728 struct hwrm_ring_free_input req = {0};
3729 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
3730 u16 error_code;
3731
3732 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
3733 req.ring_type = ring_type;
3734 req.ring_id = cpu_to_le16(ring->fw_ring_id);
3735
3736 mutex_lock(&bp->hwrm_cmd_lock);
3737 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3738 error_code = le16_to_cpu(resp->error_code);
3739 mutex_unlock(&bp->hwrm_cmd_lock);
3740
3741 if (rc || error_code) {
3742 switch (ring_type) {
3743 case RING_FREE_REQ_RING_TYPE_CMPL:
3744 netdev_err(bp->dev, "hwrm_ring_free cp failed. rc:%d\n",
3745 rc);
3746 return rc;
3747 case RING_FREE_REQ_RING_TYPE_RX:
3748 netdev_err(bp->dev, "hwrm_ring_free rx failed. rc:%d\n",
3749 rc);
3750 return rc;
3751 case RING_FREE_REQ_RING_TYPE_TX:
3752 netdev_err(bp->dev, "hwrm_ring_free tx failed. rc:%d\n",
3753 rc);
3754 return rc;
3755 default:
3756 netdev_err(bp->dev, "Invalid ring\n");
3757 return -1;
3758 }
3759 }
3760 return 0;
3761 }
3762
3763 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
3764 {
3765 int i;
3766
3767 if (!bp->bnapi)
3768 return;
3769
3770 for (i = 0; i < bp->tx_nr_rings; i++) {
3771 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3772 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
3773 u32 grp_idx = txr->bnapi->index;
3774 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
3775
3776 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3777 hwrm_ring_free_send_msg(bp, ring,
3778 RING_FREE_REQ_RING_TYPE_TX,
3779 close_path ? cmpl_ring_id :
3780 INVALID_HW_RING_ID);
3781 ring->fw_ring_id = INVALID_HW_RING_ID;
3782 }
3783 }
3784
3785 for (i = 0; i < bp->rx_nr_rings; i++) {
3786 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3787 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
3788 u32 grp_idx = rxr->bnapi->index;
3789 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
3790
3791 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3792 hwrm_ring_free_send_msg(bp, ring,
3793 RING_FREE_REQ_RING_TYPE_RX,
3794 close_path ? cmpl_ring_id :
3795 INVALID_HW_RING_ID);
3796 ring->fw_ring_id = INVALID_HW_RING_ID;
3797 bp->grp_info[grp_idx].rx_fw_ring_id =
3798 INVALID_HW_RING_ID;
3799 }
3800 }
3801
3802 for (i = 0; i < bp->rx_nr_rings; i++) {
3803 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3804 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
3805 u32 grp_idx = rxr->bnapi->index;
3806 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
3807
3808 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3809 hwrm_ring_free_send_msg(bp, ring,
3810 RING_FREE_REQ_RING_TYPE_RX,
3811 close_path ? cmpl_ring_id :
3812 INVALID_HW_RING_ID);
3813 ring->fw_ring_id = INVALID_HW_RING_ID;
3814 bp->grp_info[grp_idx].agg_fw_ring_id =
3815 INVALID_HW_RING_ID;
3816 }
3817 }
3818
3819 for (i = 0; i < bp->cp_nr_rings; i++) {
3820 struct bnxt_napi *bnapi = bp->bnapi[i];
3821 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3822 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3823
3824 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3825 hwrm_ring_free_send_msg(bp, ring,
3826 RING_FREE_REQ_RING_TYPE_CMPL,
3827 INVALID_HW_RING_ID);
3828 ring->fw_ring_id = INVALID_HW_RING_ID;
3829 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
3830 }
3831 }
3832 }
3833
3834 static void bnxt_hwrm_set_coal_params(struct bnxt *bp, u32 max_bufs,
3835 u32 buf_tmrs, u16 flags,
3836 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
3837 {
3838 req->flags = cpu_to_le16(flags);
3839 req->num_cmpl_dma_aggr = cpu_to_le16((u16)max_bufs);
3840 req->num_cmpl_dma_aggr_during_int = cpu_to_le16(max_bufs >> 16);
3841 req->cmpl_aggr_dma_tmr = cpu_to_le16((u16)buf_tmrs);
3842 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(buf_tmrs >> 16);
3843 /* Minimum time between 2 interrupts set to buf_tmr x 2 */
3844 req->int_lat_tmr_min = cpu_to_le16((u16)buf_tmrs * 2);
3845 req->int_lat_tmr_max = cpu_to_le16((u16)buf_tmrs * 4);
3846 req->num_cmpl_aggr_int = cpu_to_le16((u16)max_bufs * 4);
3847 }
3848
3849 int bnxt_hwrm_set_coal(struct bnxt *bp)
3850 {
3851 int i, rc = 0;
3852 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
3853 req_tx = {0}, *req;
3854 u16 max_buf, max_buf_irq;
3855 u16 buf_tmr, buf_tmr_irq;
3856 u32 flags;
3857
3858 bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
3859 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
3860 bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
3861 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
3862
3863 /* Each rx completion (2 records) should be DMAed immediately.
3864 * DMA 1/4 of the completion buffers at a time.
3865 */
3866 max_buf = min_t(u16, bp->rx_coal_bufs / 4, 2);
3867 /* max_buf must not be zero */
3868 max_buf = clamp_t(u16, max_buf, 1, 63);
3869 max_buf_irq = clamp_t(u16, bp->rx_coal_bufs_irq, 1, 63);
3870 buf_tmr = BNXT_USEC_TO_COAL_TIMER(bp->rx_coal_ticks);
3871 /* buf timer set to 1/4 of interrupt timer */
3872 buf_tmr = max_t(u16, buf_tmr / 4, 1);
3873 buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(bp->rx_coal_ticks_irq);
3874 buf_tmr_irq = max_t(u16, buf_tmr_irq, 1);
3875
3876 flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
3877
3878 /* RING_IDLE generates more IRQs for lower latency. Enable it only
3879 * if coal_ticks is less than 25 us.
3880 */
3881 if (bp->rx_coal_ticks < 25)
3882 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
3883
3884 bnxt_hwrm_set_coal_params(bp, max_buf_irq << 16 | max_buf,
3885 buf_tmr_irq << 16 | buf_tmr, flags, &req_rx);
3886
3887 /* max_buf must not be zero */
3888 max_buf = clamp_t(u16, bp->tx_coal_bufs, 1, 63);
3889 max_buf_irq = clamp_t(u16, bp->tx_coal_bufs_irq, 1, 63);
3890 buf_tmr = BNXT_USEC_TO_COAL_TIMER(bp->tx_coal_ticks);
3891 /* buf timer set to 1/4 of interrupt timer */
3892 buf_tmr = max_t(u16, buf_tmr / 4, 1);
3893 buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(bp->tx_coal_ticks_irq);
3894 buf_tmr_irq = max_t(u16, buf_tmr_irq, 1);
3895
3896 flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
3897 bnxt_hwrm_set_coal_params(bp, max_buf_irq << 16 | max_buf,
3898 buf_tmr_irq << 16 | buf_tmr, flags, &req_tx);
3899
3900 mutex_lock(&bp->hwrm_cmd_lock);
3901 for (i = 0; i < bp->cp_nr_rings; i++) {
3902 struct bnxt_napi *bnapi = bp->bnapi[i];
3903
3904 req = &req_rx;
3905 if (!bnapi->rx_ring)
3906 req = &req_tx;
3907 req->ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id);
3908
3909 rc = _hwrm_send_message(bp, req, sizeof(*req),
3910 HWRM_CMD_TIMEOUT);
3911 if (rc)
3912 break;
3913 }
3914 mutex_unlock(&bp->hwrm_cmd_lock);
3915 return rc;
3916 }
3917
3918 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
3919 {
3920 int rc = 0, i;
3921 struct hwrm_stat_ctx_free_input req = {0};
3922
3923 if (!bp->bnapi)
3924 return 0;
3925
3926 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
3927
3928 mutex_lock(&bp->hwrm_cmd_lock);
3929 for (i = 0; i < bp->cp_nr_rings; i++) {
3930 struct bnxt_napi *bnapi = bp->bnapi[i];
3931 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3932
3933 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
3934 req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
3935
3936 rc = _hwrm_send_message(bp, &req, sizeof(req),
3937 HWRM_CMD_TIMEOUT);
3938 if (rc)
3939 break;
3940
3941 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
3942 }
3943 }
3944 mutex_unlock(&bp->hwrm_cmd_lock);
3945 return rc;
3946 }
3947
3948 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
3949 {
3950 int rc = 0, i;
3951 struct hwrm_stat_ctx_alloc_input req = {0};
3952 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3953
3954 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
3955
3956 req.update_period_ms = cpu_to_le32(1000);
3957
3958 mutex_lock(&bp->hwrm_cmd_lock);
3959 for (i = 0; i < bp->cp_nr_rings; i++) {
3960 struct bnxt_napi *bnapi = bp->bnapi[i];
3961 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3962
3963 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
3964
3965 rc = _hwrm_send_message(bp, &req, sizeof(req),
3966 HWRM_CMD_TIMEOUT);
3967 if (rc)
3968 break;
3969
3970 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
3971
3972 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
3973 }
3974 mutex_unlock(&bp->hwrm_cmd_lock);
3975 return 0;
3976 }
3977
3978 static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
3979 {
3980 struct hwrm_func_qcfg_input req = {0};
3981 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3982 int rc;
3983
3984 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
3985 req.fid = cpu_to_le16(0xffff);
3986 mutex_lock(&bp->hwrm_cmd_lock);
3987 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3988 if (rc)
3989 goto func_qcfg_exit;
3990
3991 #ifdef CONFIG_BNXT_SRIOV
3992 if (BNXT_VF(bp)) {
3993 struct bnxt_vf_info *vf = &bp->vf;
3994
3995 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
3996 }
3997 #endif
3998 switch (resp->port_partition_type) {
3999 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
4000 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
4001 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0:
4002 bp->port_partition_type = resp->port_partition_type;
4003 break;
4004 }
4005
4006 func_qcfg_exit:
4007 mutex_unlock(&bp->hwrm_cmd_lock);
4008 return rc;
4009 }
4010
4011 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
4012 {
4013 int rc = 0;
4014 struct hwrm_func_qcaps_input req = {0};
4015 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4016
4017 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
4018 req.fid = cpu_to_le16(0xffff);
4019
4020 mutex_lock(&bp->hwrm_cmd_lock);
4021 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4022 if (rc)
4023 goto hwrm_func_qcaps_exit;
4024
4025 if (BNXT_PF(bp)) {
4026 struct bnxt_pf_info *pf = &bp->pf;
4027
4028 pf->fw_fid = le16_to_cpu(resp->fid);
4029 pf->port_id = le16_to_cpu(resp->port_id);
4030 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
4031 memcpy(bp->dev->dev_addr, pf->mac_addr, ETH_ALEN);
4032 pf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
4033 pf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
4034 pf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
4035 pf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
4036 pf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
4037 if (!pf->max_hw_ring_grps)
4038 pf->max_hw_ring_grps = pf->max_tx_rings;
4039 pf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
4040 pf->max_vnics = le16_to_cpu(resp->max_vnics);
4041 pf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
4042 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
4043 pf->max_vfs = le16_to_cpu(resp->max_vfs);
4044 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
4045 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
4046 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
4047 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
4048 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
4049 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
4050 } else {
4051 #ifdef CONFIG_BNXT_SRIOV
4052 struct bnxt_vf_info *vf = &bp->vf;
4053
4054 vf->fw_fid = le16_to_cpu(resp->fid);
4055 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
4056 if (is_valid_ether_addr(vf->mac_addr))
4057 /* overwrite netdev dev_adr with admin VF MAC */
4058 memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
4059 else
4060 random_ether_addr(bp->dev->dev_addr);
4061
4062 vf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
4063 vf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
4064 vf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
4065 vf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
4066 vf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
4067 if (!vf->max_hw_ring_grps)
4068 vf->max_hw_ring_grps = vf->max_tx_rings;
4069 vf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
4070 vf->max_vnics = le16_to_cpu(resp->max_vnics);
4071 vf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
4072 #endif
4073 }
4074
4075 bp->tx_push_thresh = 0;
4076 if (resp->flags &
4077 cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED))
4078 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
4079
4080 hwrm_func_qcaps_exit:
4081 mutex_unlock(&bp->hwrm_cmd_lock);
4082 return rc;
4083 }
4084
4085 static int bnxt_hwrm_func_reset(struct bnxt *bp)
4086 {
4087 struct hwrm_func_reset_input req = {0};
4088
4089 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
4090 req.enables = 0;
4091
4092 return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
4093 }
4094
4095 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
4096 {
4097 int rc = 0;
4098 struct hwrm_queue_qportcfg_input req = {0};
4099 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
4100 u8 i, *qptr;
4101
4102 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
4103
4104 mutex_lock(&bp->hwrm_cmd_lock);
4105 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4106 if (rc)
4107 goto qportcfg_exit;
4108
4109 if (!resp->max_configurable_queues) {
4110 rc = -EINVAL;
4111 goto qportcfg_exit;
4112 }
4113 bp->max_tc = resp->max_configurable_queues;
4114 if (bp->max_tc > BNXT_MAX_QUEUE)
4115 bp->max_tc = BNXT_MAX_QUEUE;
4116
4117 qptr = &resp->queue_id0;
4118 for (i = 0; i < bp->max_tc; i++) {
4119 bp->q_info[i].queue_id = *qptr++;
4120 bp->q_info[i].queue_profile = *qptr++;
4121 }
4122
4123 qportcfg_exit:
4124 mutex_unlock(&bp->hwrm_cmd_lock);
4125 return rc;
4126 }
4127
4128 static int bnxt_hwrm_ver_get(struct bnxt *bp)
4129 {
4130 int rc;
4131 struct hwrm_ver_get_input req = {0};
4132 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
4133
4134 bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
4135 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
4136 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
4137 req.hwrm_intf_min = HWRM_VERSION_MINOR;
4138 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
4139 mutex_lock(&bp->hwrm_cmd_lock);
4140 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4141 if (rc)
4142 goto hwrm_ver_get_exit;
4143
4144 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
4145
4146 bp->hwrm_spec_code = resp->hwrm_intf_maj << 16 |
4147 resp->hwrm_intf_min << 8 | resp->hwrm_intf_upd;
4148 if (resp->hwrm_intf_maj < 1) {
4149 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
4150 resp->hwrm_intf_maj, resp->hwrm_intf_min,
4151 resp->hwrm_intf_upd);
4152 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
4153 }
4154 snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d/%d.%d.%d",
4155 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld,
4156 resp->hwrm_intf_maj, resp->hwrm_intf_min, resp->hwrm_intf_upd);
4157
4158 bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
4159 if (!bp->hwrm_cmd_timeout)
4160 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
4161
4162 if (resp->hwrm_intf_maj >= 1)
4163 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
4164
4165 bp->chip_num = le16_to_cpu(resp->chip_num);
4166
4167 hwrm_ver_get_exit:
4168 mutex_unlock(&bp->hwrm_cmd_lock);
4169 return rc;
4170 }
4171
4172 static int bnxt_hwrm_port_qstats(struct bnxt *bp)
4173 {
4174 int rc;
4175 struct bnxt_pf_info *pf = &bp->pf;
4176 struct hwrm_port_qstats_input req = {0};
4177
4178 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
4179 return 0;
4180
4181 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
4182 req.port_id = cpu_to_le16(pf->port_id);
4183 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map);
4184 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map);
4185 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4186 return rc;
4187 }
4188
4189 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
4190 {
4191 if (bp->vxlan_port_cnt) {
4192 bnxt_hwrm_tunnel_dst_port_free(
4193 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
4194 }
4195 bp->vxlan_port_cnt = 0;
4196 if (bp->nge_port_cnt) {
4197 bnxt_hwrm_tunnel_dst_port_free(
4198 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
4199 }
4200 bp->nge_port_cnt = 0;
4201 }
4202
4203 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
4204 {
4205 int rc, i;
4206 u32 tpa_flags = 0;
4207
4208 if (set_tpa)
4209 tpa_flags = bp->flags & BNXT_FLAG_TPA;
4210 for (i = 0; i < bp->nr_vnics; i++) {
4211 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
4212 if (rc) {
4213 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
4214 rc, i);
4215 return rc;
4216 }
4217 }
4218 return 0;
4219 }
4220
4221 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
4222 {
4223 int i;
4224
4225 for (i = 0; i < bp->nr_vnics; i++)
4226 bnxt_hwrm_vnic_set_rss(bp, i, false);
4227 }
4228
4229 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
4230 bool irq_re_init)
4231 {
4232 if (bp->vnic_info) {
4233 bnxt_hwrm_clear_vnic_filter(bp);
4234 /* clear all RSS setting before free vnic ctx */
4235 bnxt_hwrm_clear_vnic_rss(bp);
4236 bnxt_hwrm_vnic_ctx_free(bp);
4237 /* before free the vnic, undo the vnic tpa settings */
4238 if (bp->flags & BNXT_FLAG_TPA)
4239 bnxt_set_tpa(bp, false);
4240 bnxt_hwrm_vnic_free(bp);
4241 }
4242 bnxt_hwrm_ring_free(bp, close_path);
4243 bnxt_hwrm_ring_grp_free(bp);
4244 if (irq_re_init) {
4245 bnxt_hwrm_stat_ctx_free(bp);
4246 bnxt_hwrm_free_tunnel_ports(bp);
4247 }
4248 }
4249
4250 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
4251 {
4252 int rc;
4253
4254 /* allocate context for vnic */
4255 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id);
4256 if (rc) {
4257 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
4258 vnic_id, rc);
4259 goto vnic_setup_err;
4260 }
4261 bp->rsscos_nr_ctxs++;
4262
4263 /* configure default vnic, ring grp */
4264 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
4265 if (rc) {
4266 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
4267 vnic_id, rc);
4268 goto vnic_setup_err;
4269 }
4270
4271 /* Enable RSS hashing on vnic */
4272 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
4273 if (rc) {
4274 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
4275 vnic_id, rc);
4276 goto vnic_setup_err;
4277 }
4278
4279 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
4280 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
4281 if (rc) {
4282 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
4283 vnic_id, rc);
4284 }
4285 }
4286
4287 vnic_setup_err:
4288 return rc;
4289 }
4290
4291 static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
4292 {
4293 #ifdef CONFIG_RFS_ACCEL
4294 int i, rc = 0;
4295
4296 for (i = 0; i < bp->rx_nr_rings; i++) {
4297 u16 vnic_id = i + 1;
4298 u16 ring_id = i;
4299
4300 if (vnic_id >= bp->nr_vnics)
4301 break;
4302
4303 bp->vnic_info[vnic_id].flags |= BNXT_VNIC_RFS_FLAG;
4304 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
4305 if (rc) {
4306 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
4307 vnic_id, rc);
4308 break;
4309 }
4310 rc = bnxt_setup_vnic(bp, vnic_id);
4311 if (rc)
4312 break;
4313 }
4314 return rc;
4315 #else
4316 return 0;
4317 #endif
4318 }
4319
4320 static int bnxt_cfg_rx_mode(struct bnxt *);
4321 static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
4322
4323 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
4324 {
4325 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4326 int rc = 0;
4327
4328 if (irq_re_init) {
4329 rc = bnxt_hwrm_stat_ctx_alloc(bp);
4330 if (rc) {
4331 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
4332 rc);
4333 goto err_out;
4334 }
4335 }
4336
4337 rc = bnxt_hwrm_ring_alloc(bp);
4338 if (rc) {
4339 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
4340 goto err_out;
4341 }
4342
4343 rc = bnxt_hwrm_ring_grp_alloc(bp);
4344 if (rc) {
4345 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
4346 goto err_out;
4347 }
4348
4349 /* default vnic 0 */
4350 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, bp->rx_nr_rings);
4351 if (rc) {
4352 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
4353 goto err_out;
4354 }
4355
4356 rc = bnxt_setup_vnic(bp, 0);
4357 if (rc)
4358 goto err_out;
4359
4360 if (bp->flags & BNXT_FLAG_RFS) {
4361 rc = bnxt_alloc_rfs_vnics(bp);
4362 if (rc)
4363 goto err_out;
4364 }
4365
4366 if (bp->flags & BNXT_FLAG_TPA) {
4367 rc = bnxt_set_tpa(bp, true);
4368 if (rc)
4369 goto err_out;
4370 }
4371
4372 if (BNXT_VF(bp))
4373 bnxt_update_vf_mac(bp);
4374
4375 /* Filter for default vnic 0 */
4376 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
4377 if (rc) {
4378 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
4379 goto err_out;
4380 }
4381 vnic->uc_filter_count = 1;
4382
4383 vnic->rx_mask = CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
4384
4385 if ((bp->dev->flags & IFF_PROMISC) && BNXT_PF(bp))
4386 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
4387
4388 if (bp->dev->flags & IFF_ALLMULTI) {
4389 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
4390 vnic->mc_list_count = 0;
4391 } else {
4392 u32 mask = 0;
4393
4394 bnxt_mc_list_updated(bp, &mask);
4395 vnic->rx_mask |= mask;
4396 }
4397
4398 rc = bnxt_cfg_rx_mode(bp);
4399 if (rc)
4400 goto err_out;
4401
4402 rc = bnxt_hwrm_set_coal(bp);
4403 if (rc)
4404 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
4405 rc);
4406
4407 if (BNXT_VF(bp)) {
4408 bnxt_hwrm_func_qcfg(bp);
4409 netdev_update_features(bp->dev);
4410 }
4411
4412 return 0;
4413
4414 err_out:
4415 bnxt_hwrm_resource_free(bp, 0, true);
4416
4417 return rc;
4418 }
4419
4420 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
4421 {
4422 bnxt_hwrm_resource_free(bp, 1, irq_re_init);
4423 return 0;
4424 }
4425
4426 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
4427 {
4428 bnxt_init_rx_rings(bp);
4429 bnxt_init_tx_rings(bp);
4430 bnxt_init_ring_grps(bp, irq_re_init);
4431 bnxt_init_vnics(bp);
4432
4433 return bnxt_init_chip(bp, irq_re_init);
4434 }
4435
4436 static void bnxt_disable_int(struct bnxt *bp)
4437 {
4438 int i;
4439
4440 if (!bp->bnapi)
4441 return;
4442
4443 for (i = 0; i < bp->cp_nr_rings; i++) {
4444 struct bnxt_napi *bnapi = bp->bnapi[i];
4445 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4446
4447 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
4448 }
4449 }
4450
4451 static void bnxt_enable_int(struct bnxt *bp)
4452 {
4453 int i;
4454
4455 atomic_set(&bp->intr_sem, 0);
4456 for (i = 0; i < bp->cp_nr_rings; i++) {
4457 struct bnxt_napi *bnapi = bp->bnapi[i];
4458 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4459
4460 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
4461 }
4462 }
4463
4464 static int bnxt_set_real_num_queues(struct bnxt *bp)
4465 {
4466 int rc;
4467 struct net_device *dev = bp->dev;
4468
4469 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings);
4470 if (rc)
4471 return rc;
4472
4473 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
4474 if (rc)
4475 return rc;
4476
4477 #ifdef CONFIG_RFS_ACCEL
4478 if (bp->flags & BNXT_FLAG_RFS)
4479 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
4480 #endif
4481
4482 return rc;
4483 }
4484
4485 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
4486 bool shared)
4487 {
4488 int _rx = *rx, _tx = *tx;
4489
4490 if (shared) {
4491 *rx = min_t(int, _rx, max);
4492 *tx = min_t(int, _tx, max);
4493 } else {
4494 if (max < 2)
4495 return -ENOMEM;
4496
4497 while (_rx + _tx > max) {
4498 if (_rx > _tx && _rx > 1)
4499 _rx--;
4500 else if (_tx > 1)
4501 _tx--;
4502 }
4503 *rx = _rx;
4504 *tx = _tx;
4505 }
4506 return 0;
4507 }
4508
4509 static int bnxt_setup_msix(struct bnxt *bp)
4510 {
4511 struct msix_entry *msix_ent;
4512 struct net_device *dev = bp->dev;
4513 int i, total_vecs, rc = 0, min = 1;
4514 const int len = sizeof(bp->irq_tbl[0].name);
4515
4516 bp->flags &= ~BNXT_FLAG_USING_MSIX;
4517 total_vecs = bp->cp_nr_rings;
4518
4519 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
4520 if (!msix_ent)
4521 return -ENOMEM;
4522
4523 for (i = 0; i < total_vecs; i++) {
4524 msix_ent[i].entry = i;
4525 msix_ent[i].vector = 0;
4526 }
4527
4528 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
4529 min = 2;
4530
4531 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
4532 if (total_vecs < 0) {
4533 rc = -ENODEV;
4534 goto msix_setup_exit;
4535 }
4536
4537 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
4538 if (bp->irq_tbl) {
4539 int tcs;
4540
4541 /* Trim rings based upon num of vectors allocated */
4542 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
4543 total_vecs, min == 1);
4544 if (rc)
4545 goto msix_setup_exit;
4546
4547 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4548 tcs = netdev_get_num_tc(dev);
4549 if (tcs > 1) {
4550 bp->tx_nr_rings_per_tc = bp->tx_nr_rings / tcs;
4551 if (bp->tx_nr_rings_per_tc == 0) {
4552 netdev_reset_tc(dev);
4553 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4554 } else {
4555 int i, off, count;
4556
4557 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs;
4558 for (i = 0; i < tcs; i++) {
4559 count = bp->tx_nr_rings_per_tc;
4560 off = i * count;
4561 netdev_set_tc_queue(dev, i, count, off);
4562 }
4563 }
4564 }
4565 bp->cp_nr_rings = total_vecs;
4566
4567 for (i = 0; i < bp->cp_nr_rings; i++) {
4568 char *attr;
4569
4570 bp->irq_tbl[i].vector = msix_ent[i].vector;
4571 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
4572 attr = "TxRx";
4573 else if (i < bp->rx_nr_rings)
4574 attr = "rx";
4575 else
4576 attr = "tx";
4577
4578 snprintf(bp->irq_tbl[i].name, len,
4579 "%s-%s-%d", dev->name, attr, i);
4580 bp->irq_tbl[i].handler = bnxt_msix;
4581 }
4582 rc = bnxt_set_real_num_queues(bp);
4583 if (rc)
4584 goto msix_setup_exit;
4585 } else {
4586 rc = -ENOMEM;
4587 goto msix_setup_exit;
4588 }
4589 bp->flags |= BNXT_FLAG_USING_MSIX;
4590 kfree(msix_ent);
4591 return 0;
4592
4593 msix_setup_exit:
4594 netdev_err(bp->dev, "bnxt_setup_msix err: %x\n", rc);
4595 pci_disable_msix(bp->pdev);
4596 kfree(msix_ent);
4597 return rc;
4598 }
4599
4600 static int bnxt_setup_inta(struct bnxt *bp)
4601 {
4602 int rc;
4603 const int len = sizeof(bp->irq_tbl[0].name);
4604
4605 if (netdev_get_num_tc(bp->dev))
4606 netdev_reset_tc(bp->dev);
4607
4608 bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
4609 if (!bp->irq_tbl) {
4610 rc = -ENOMEM;
4611 return rc;
4612 }
4613 bp->rx_nr_rings = 1;
4614 bp->tx_nr_rings = 1;
4615 bp->cp_nr_rings = 1;
4616 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4617 bp->flags |= BNXT_FLAG_SHARED_RINGS;
4618 bp->irq_tbl[0].vector = bp->pdev->irq;
4619 snprintf(bp->irq_tbl[0].name, len,
4620 "%s-%s-%d", bp->dev->name, "TxRx", 0);
4621 bp->irq_tbl[0].handler = bnxt_inta;
4622 rc = bnxt_set_real_num_queues(bp);
4623 return rc;
4624 }
4625
4626 static int bnxt_setup_int_mode(struct bnxt *bp)
4627 {
4628 int rc = 0;
4629
4630 if (bp->flags & BNXT_FLAG_MSIX_CAP)
4631 rc = bnxt_setup_msix(bp);
4632
4633 if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
4634 /* fallback to INTA */
4635 rc = bnxt_setup_inta(bp);
4636 }
4637 return rc;
4638 }
4639
4640 static void bnxt_free_irq(struct bnxt *bp)
4641 {
4642 struct bnxt_irq *irq;
4643 int i;
4644
4645 #ifdef CONFIG_RFS_ACCEL
4646 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
4647 bp->dev->rx_cpu_rmap = NULL;
4648 #endif
4649 if (!bp->irq_tbl)
4650 return;
4651
4652 for (i = 0; i < bp->cp_nr_rings; i++) {
4653 irq = &bp->irq_tbl[i];
4654 if (irq->requested)
4655 free_irq(irq->vector, bp->bnapi[i]);
4656 irq->requested = 0;
4657 }
4658 if (bp->flags & BNXT_FLAG_USING_MSIX)
4659 pci_disable_msix(bp->pdev);
4660 kfree(bp->irq_tbl);
4661 bp->irq_tbl = NULL;
4662 }
4663
4664 static int bnxt_request_irq(struct bnxt *bp)
4665 {
4666 int i, j, rc = 0;
4667 unsigned long flags = 0;
4668 #ifdef CONFIG_RFS_ACCEL
4669 struct cpu_rmap *rmap = bp->dev->rx_cpu_rmap;
4670 #endif
4671
4672 if (!(bp->flags & BNXT_FLAG_USING_MSIX))
4673 flags = IRQF_SHARED;
4674
4675 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
4676 struct bnxt_irq *irq = &bp->irq_tbl[i];
4677 #ifdef CONFIG_RFS_ACCEL
4678 if (rmap && bp->bnapi[i]->rx_ring) {
4679 rc = irq_cpu_rmap_add(rmap, irq->vector);
4680 if (rc)
4681 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
4682 j);
4683 j++;
4684 }
4685 #endif
4686 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
4687 bp->bnapi[i]);
4688 if (rc)
4689 break;
4690
4691 irq->requested = 1;
4692 }
4693 return rc;
4694 }
4695
4696 static void bnxt_del_napi(struct bnxt *bp)
4697 {
4698 int i;
4699
4700 if (!bp->bnapi)
4701 return;
4702
4703 for (i = 0; i < bp->cp_nr_rings; i++) {
4704 struct bnxt_napi *bnapi = bp->bnapi[i];
4705
4706 napi_hash_del(&bnapi->napi);
4707 netif_napi_del(&bnapi->napi);
4708 }
4709 }
4710
4711 static void bnxt_init_napi(struct bnxt *bp)
4712 {
4713 int i;
4714 struct bnxt_napi *bnapi;
4715
4716 if (bp->flags & BNXT_FLAG_USING_MSIX) {
4717 for (i = 0; i < bp->cp_nr_rings; i++) {
4718 bnapi = bp->bnapi[i];
4719 netif_napi_add(bp->dev, &bnapi->napi,
4720 bnxt_poll, 64);
4721 }
4722 } else {
4723 bnapi = bp->bnapi[0];
4724 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
4725 }
4726 }
4727
4728 static void bnxt_disable_napi(struct bnxt *bp)
4729 {
4730 int i;
4731
4732 if (!bp->bnapi)
4733 return;
4734
4735 for (i = 0; i < bp->cp_nr_rings; i++) {
4736 napi_disable(&bp->bnapi[i]->napi);
4737 bnxt_disable_poll(bp->bnapi[i]);
4738 }
4739 }
4740
4741 static void bnxt_enable_napi(struct bnxt *bp)
4742 {
4743 int i;
4744
4745 for (i = 0; i < bp->cp_nr_rings; i++) {
4746 bp->bnapi[i]->in_reset = false;
4747 bnxt_enable_poll(bp->bnapi[i]);
4748 napi_enable(&bp->bnapi[i]->napi);
4749 }
4750 }
4751
4752 static void bnxt_tx_disable(struct bnxt *bp)
4753 {
4754 int i;
4755 struct bnxt_tx_ring_info *txr;
4756 struct netdev_queue *txq;
4757
4758 if (bp->tx_ring) {
4759 for (i = 0; i < bp->tx_nr_rings; i++) {
4760 txr = &bp->tx_ring[i];
4761 txq = netdev_get_tx_queue(bp->dev, i);
4762 __netif_tx_lock(txq, smp_processor_id());
4763 txr->dev_state = BNXT_DEV_STATE_CLOSING;
4764 __netif_tx_unlock(txq);
4765 }
4766 }
4767 /* Stop all TX queues */
4768 netif_tx_disable(bp->dev);
4769 netif_carrier_off(bp->dev);
4770 }
4771
4772 static void bnxt_tx_enable(struct bnxt *bp)
4773 {
4774 int i;
4775 struct bnxt_tx_ring_info *txr;
4776 struct netdev_queue *txq;
4777
4778 for (i = 0; i < bp->tx_nr_rings; i++) {
4779 txr = &bp->tx_ring[i];
4780 txq = netdev_get_tx_queue(bp->dev, i);
4781 txr->dev_state = 0;
4782 }
4783 netif_tx_wake_all_queues(bp->dev);
4784 if (bp->link_info.link_up)
4785 netif_carrier_on(bp->dev);
4786 }
4787
4788 static void bnxt_report_link(struct bnxt *bp)
4789 {
4790 if (bp->link_info.link_up) {
4791 const char *duplex;
4792 const char *flow_ctrl;
4793 u16 speed;
4794
4795 netif_carrier_on(bp->dev);
4796 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
4797 duplex = "full";
4798 else
4799 duplex = "half";
4800 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
4801 flow_ctrl = "ON - receive & transmit";
4802 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
4803 flow_ctrl = "ON - transmit";
4804 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
4805 flow_ctrl = "ON - receive";
4806 else
4807 flow_ctrl = "none";
4808 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
4809 netdev_info(bp->dev, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
4810 speed, duplex, flow_ctrl);
4811 if (bp->flags & BNXT_FLAG_EEE_CAP)
4812 netdev_info(bp->dev, "EEE is %s\n",
4813 bp->eee.eee_active ? "active" :
4814 "not active");
4815 } else {
4816 netif_carrier_off(bp->dev);
4817 netdev_err(bp->dev, "NIC Link is Down\n");
4818 }
4819 }
4820
4821 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
4822 {
4823 int rc = 0;
4824 struct hwrm_port_phy_qcaps_input req = {0};
4825 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4826 struct bnxt_link_info *link_info = &bp->link_info;
4827
4828 if (bp->hwrm_spec_code < 0x10201)
4829 return 0;
4830
4831 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
4832
4833 mutex_lock(&bp->hwrm_cmd_lock);
4834 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4835 if (rc)
4836 goto hwrm_phy_qcaps_exit;
4837
4838 if (resp->eee_supported & PORT_PHY_QCAPS_RESP_EEE_SUPPORTED) {
4839 struct ethtool_eee *eee = &bp->eee;
4840 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
4841
4842 bp->flags |= BNXT_FLAG_EEE_CAP;
4843 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
4844 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
4845 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
4846 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
4847 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
4848 }
4849 link_info->support_auto_speeds =
4850 le16_to_cpu(resp->supported_speeds_auto_mode);
4851
4852 hwrm_phy_qcaps_exit:
4853 mutex_unlock(&bp->hwrm_cmd_lock);
4854 return rc;
4855 }
4856
4857 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
4858 {
4859 int rc = 0;
4860 struct bnxt_link_info *link_info = &bp->link_info;
4861 struct hwrm_port_phy_qcfg_input req = {0};
4862 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4863 u8 link_up = link_info->link_up;
4864
4865 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
4866
4867 mutex_lock(&bp->hwrm_cmd_lock);
4868 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4869 if (rc) {
4870 mutex_unlock(&bp->hwrm_cmd_lock);
4871 return rc;
4872 }
4873
4874 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
4875 link_info->phy_link_status = resp->link;
4876 link_info->duplex = resp->duplex;
4877 link_info->pause = resp->pause;
4878 link_info->auto_mode = resp->auto_mode;
4879 link_info->auto_pause_setting = resp->auto_pause;
4880 link_info->lp_pause = resp->link_partner_adv_pause;
4881 link_info->force_pause_setting = resp->force_pause;
4882 link_info->duplex_setting = resp->duplex;
4883 if (link_info->phy_link_status == BNXT_LINK_LINK)
4884 link_info->link_speed = le16_to_cpu(resp->link_speed);
4885 else
4886 link_info->link_speed = 0;
4887 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
4888 link_info->support_speeds = le16_to_cpu(resp->support_speeds);
4889 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
4890 link_info->lp_auto_link_speeds =
4891 le16_to_cpu(resp->link_partner_adv_speeds);
4892 link_info->preemphasis = le32_to_cpu(resp->preemphasis);
4893 link_info->phy_ver[0] = resp->phy_maj;
4894 link_info->phy_ver[1] = resp->phy_min;
4895 link_info->phy_ver[2] = resp->phy_bld;
4896 link_info->media_type = resp->media_type;
4897 link_info->phy_type = resp->phy_type;
4898 link_info->transceiver = resp->xcvr_pkg_type;
4899 link_info->phy_addr = resp->eee_config_phy_addr &
4900 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
4901 link_info->module_status = resp->module_status;
4902
4903 if (bp->flags & BNXT_FLAG_EEE_CAP) {
4904 struct ethtool_eee *eee = &bp->eee;
4905 u16 fw_speeds;
4906
4907 eee->eee_active = 0;
4908 if (resp->eee_config_phy_addr &
4909 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
4910 eee->eee_active = 1;
4911 fw_speeds = le16_to_cpu(
4912 resp->link_partner_adv_eee_link_speed_mask);
4913 eee->lp_advertised =
4914 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
4915 }
4916
4917 /* Pull initial EEE config */
4918 if (!chng_link_state) {
4919 if (resp->eee_config_phy_addr &
4920 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
4921 eee->eee_enabled = 1;
4922
4923 fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
4924 eee->advertised =
4925 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
4926
4927 if (resp->eee_config_phy_addr &
4928 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
4929 __le32 tmr;
4930
4931 eee->tx_lpi_enabled = 1;
4932 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
4933 eee->tx_lpi_timer = le32_to_cpu(tmr) &
4934 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
4935 }
4936 }
4937 }
4938 /* TODO: need to add more logic to report VF link */
4939 if (chng_link_state) {
4940 if (link_info->phy_link_status == BNXT_LINK_LINK)
4941 link_info->link_up = 1;
4942 else
4943 link_info->link_up = 0;
4944 if (link_up != link_info->link_up)
4945 bnxt_report_link(bp);
4946 } else {
4947 /* alwasy link down if not require to update link state */
4948 link_info->link_up = 0;
4949 }
4950 mutex_unlock(&bp->hwrm_cmd_lock);
4951 return 0;
4952 }
4953
4954 static void bnxt_get_port_module_status(struct bnxt *bp)
4955 {
4956 struct bnxt_link_info *link_info = &bp->link_info;
4957 struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
4958 u8 module_status;
4959
4960 if (bnxt_update_link(bp, true))
4961 return;
4962
4963 module_status = link_info->module_status;
4964 switch (module_status) {
4965 case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX:
4966 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
4967 case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG:
4968 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
4969 bp->pf.port_id);
4970 if (bp->hwrm_spec_code >= 0x10201) {
4971 netdev_warn(bp->dev, "Module part number %s\n",
4972 resp->phy_vendor_partnumber);
4973 }
4974 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX)
4975 netdev_warn(bp->dev, "TX is disabled\n");
4976 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN)
4977 netdev_warn(bp->dev, "SFP+ module is shutdown\n");
4978 }
4979 }
4980
4981 static void
4982 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
4983 {
4984 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
4985 if (bp->hwrm_spec_code >= 0x10201)
4986 req->auto_pause =
4987 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
4988 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
4989 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
4990 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
4991 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
4992 req->enables |=
4993 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
4994 } else {
4995 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
4996 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
4997 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
4998 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
4999 req->enables |=
5000 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
5001 if (bp->hwrm_spec_code >= 0x10201) {
5002 req->auto_pause = req->force_pause;
5003 req->enables |= cpu_to_le32(
5004 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
5005 }
5006 }
5007 }
5008
5009 static void bnxt_hwrm_set_link_common(struct bnxt *bp,
5010 struct hwrm_port_phy_cfg_input *req)
5011 {
5012 u8 autoneg = bp->link_info.autoneg;
5013 u16 fw_link_speed = bp->link_info.req_link_speed;
5014 u32 advertising = bp->link_info.advertising;
5015
5016 if (autoneg & BNXT_AUTONEG_SPEED) {
5017 req->auto_mode |=
5018 PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
5019
5020 req->enables |= cpu_to_le32(
5021 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
5022 req->auto_link_speed_mask = cpu_to_le16(advertising);
5023
5024 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
5025 req->flags |=
5026 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
5027 } else {
5028 req->force_link_speed = cpu_to_le16(fw_link_speed);
5029 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
5030 }
5031
5032 /* tell chimp that the setting takes effect immediately */
5033 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
5034 }
5035
5036 int bnxt_hwrm_set_pause(struct bnxt *bp)
5037 {
5038 struct hwrm_port_phy_cfg_input req = {0};
5039 int rc;
5040
5041 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
5042 bnxt_hwrm_set_pause_common(bp, &req);
5043
5044 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
5045 bp->link_info.force_link_chng)
5046 bnxt_hwrm_set_link_common(bp, &req);
5047
5048 mutex_lock(&bp->hwrm_cmd_lock);
5049 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5050 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
5051 /* since changing of pause setting doesn't trigger any link
5052 * change event, the driver needs to update the current pause
5053 * result upon successfully return of the phy_cfg command
5054 */
5055 bp->link_info.pause =
5056 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
5057 bp->link_info.auto_pause_setting = 0;
5058 if (!bp->link_info.force_link_chng)
5059 bnxt_report_link(bp);
5060 }
5061 bp->link_info.force_link_chng = false;
5062 mutex_unlock(&bp->hwrm_cmd_lock);
5063 return rc;
5064 }
5065
5066 static void bnxt_hwrm_set_eee(struct bnxt *bp,
5067 struct hwrm_port_phy_cfg_input *req)
5068 {
5069 struct ethtool_eee *eee = &bp->eee;
5070
5071 if (eee->eee_enabled) {
5072 u16 eee_speeds;
5073 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
5074
5075 if (eee->tx_lpi_enabled)
5076 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
5077 else
5078 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
5079
5080 req->flags |= cpu_to_le32(flags);
5081 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
5082 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
5083 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
5084 } else {
5085 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
5086 }
5087 }
5088
5089 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
5090 {
5091 struct hwrm_port_phy_cfg_input req = {0};
5092
5093 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
5094 if (set_pause)
5095 bnxt_hwrm_set_pause_common(bp, &req);
5096
5097 bnxt_hwrm_set_link_common(bp, &req);
5098
5099 if (set_eee)
5100 bnxt_hwrm_set_eee(bp, &req);
5101 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5102 }
5103
5104 static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
5105 {
5106 struct hwrm_port_phy_cfg_input req = {0};
5107
5108 if (!BNXT_SINGLE_PF(bp))
5109 return 0;
5110
5111 if (pci_num_vf(bp->pdev))
5112 return 0;
5113
5114 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
5115 req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DOWN);
5116 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5117 }
5118
5119 static bool bnxt_eee_config_ok(struct bnxt *bp)
5120 {
5121 struct ethtool_eee *eee = &bp->eee;
5122 struct bnxt_link_info *link_info = &bp->link_info;
5123
5124 if (!(bp->flags & BNXT_FLAG_EEE_CAP))
5125 return true;
5126
5127 if (eee->eee_enabled) {
5128 u32 advertising =
5129 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
5130
5131 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
5132 eee->eee_enabled = 0;
5133 return false;
5134 }
5135 if (eee->advertised & ~advertising) {
5136 eee->advertised = advertising & eee->supported;
5137 return false;
5138 }
5139 }
5140 return true;
5141 }
5142
5143 static int bnxt_update_phy_setting(struct bnxt *bp)
5144 {
5145 int rc;
5146 bool update_link = false;
5147 bool update_pause = false;
5148 bool update_eee = false;
5149 struct bnxt_link_info *link_info = &bp->link_info;
5150
5151 rc = bnxt_update_link(bp, true);
5152 if (rc) {
5153 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
5154 rc);
5155 return rc;
5156 }
5157 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
5158 (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
5159 link_info->req_flow_ctrl)
5160 update_pause = true;
5161 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
5162 link_info->force_pause_setting != link_info->req_flow_ctrl)
5163 update_pause = true;
5164 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
5165 if (BNXT_AUTO_MODE(link_info->auto_mode))
5166 update_link = true;
5167 if (link_info->req_link_speed != link_info->force_link_speed)
5168 update_link = true;
5169 if (link_info->req_duplex != link_info->duplex_setting)
5170 update_link = true;
5171 } else {
5172 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
5173 update_link = true;
5174 if (link_info->advertising != link_info->auto_link_speeds)
5175 update_link = true;
5176 }
5177
5178 if (!bnxt_eee_config_ok(bp))
5179 update_eee = true;
5180
5181 if (update_link)
5182 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
5183 else if (update_pause)
5184 rc = bnxt_hwrm_set_pause(bp);
5185 if (rc) {
5186 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
5187 rc);
5188 return rc;
5189 }
5190
5191 return rc;
5192 }
5193
5194 /* Common routine to pre-map certain register block to different GRC window.
5195 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
5196 * in PF and 3 windows in VF that can be customized to map in different
5197 * register blocks.
5198 */
5199 static void bnxt_preset_reg_win(struct bnxt *bp)
5200 {
5201 if (BNXT_PF(bp)) {
5202 /* CAG registers map to GRC window #4 */
5203 writel(BNXT_CAG_REG_BASE,
5204 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
5205 }
5206 }
5207
5208 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
5209 {
5210 int rc = 0;
5211
5212 bnxt_preset_reg_win(bp);
5213 netif_carrier_off(bp->dev);
5214 if (irq_re_init) {
5215 rc = bnxt_setup_int_mode(bp);
5216 if (rc) {
5217 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
5218 rc);
5219 return rc;
5220 }
5221 }
5222 if ((bp->flags & BNXT_FLAG_RFS) &&
5223 !(bp->flags & BNXT_FLAG_USING_MSIX)) {
5224 /* disable RFS if falling back to INTA */
5225 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
5226 bp->flags &= ~BNXT_FLAG_RFS;
5227 }
5228
5229 rc = bnxt_alloc_mem(bp, irq_re_init);
5230 if (rc) {
5231 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
5232 goto open_err_free_mem;
5233 }
5234
5235 if (irq_re_init) {
5236 bnxt_init_napi(bp);
5237 rc = bnxt_request_irq(bp);
5238 if (rc) {
5239 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
5240 goto open_err;
5241 }
5242 }
5243
5244 bnxt_enable_napi(bp);
5245
5246 rc = bnxt_init_nic(bp, irq_re_init);
5247 if (rc) {
5248 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
5249 goto open_err;
5250 }
5251
5252 if (link_re_init) {
5253 rc = bnxt_update_phy_setting(bp);
5254 if (rc)
5255 netdev_warn(bp->dev, "failed to update phy settings\n");
5256 }
5257
5258 if (irq_re_init) {
5259 #if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE)
5260 vxlan_get_rx_port(bp->dev);
5261 #endif
5262 if (!bnxt_hwrm_tunnel_dst_port_alloc(
5263 bp, htons(0x17c1),
5264 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE))
5265 bp->nge_port_cnt = 1;
5266 }
5267
5268 set_bit(BNXT_STATE_OPEN, &bp->state);
5269 bnxt_enable_int(bp);
5270 /* Enable TX queues */
5271 bnxt_tx_enable(bp);
5272 mod_timer(&bp->timer, jiffies + bp->current_interval);
5273 /* Poll link status and check for SFP+ module status */
5274 bnxt_get_port_module_status(bp);
5275
5276 return 0;
5277
5278 open_err:
5279 bnxt_disable_napi(bp);
5280 bnxt_del_napi(bp);
5281
5282 open_err_free_mem:
5283 bnxt_free_skbs(bp);
5284 bnxt_free_irq(bp);
5285 bnxt_free_mem(bp, true);
5286 return rc;
5287 }
5288
5289 /* rtnl_lock held */
5290 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
5291 {
5292 int rc = 0;
5293
5294 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
5295 if (rc) {
5296 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
5297 dev_close(bp->dev);
5298 }
5299 return rc;
5300 }
5301
5302 static int bnxt_open(struct net_device *dev)
5303 {
5304 struct bnxt *bp = netdev_priv(dev);
5305 int rc = 0;
5306
5307 rc = bnxt_hwrm_func_reset(bp);
5308 if (rc) {
5309 netdev_err(bp->dev, "hwrm chip reset failure rc: %x\n",
5310 rc);
5311 rc = -1;
5312 return rc;
5313 }
5314 return __bnxt_open_nic(bp, true, true);
5315 }
5316
5317 static void bnxt_disable_int_sync(struct bnxt *bp)
5318 {
5319 int i;
5320
5321 atomic_inc(&bp->intr_sem);
5322 if (!netif_running(bp->dev))
5323 return;
5324
5325 bnxt_disable_int(bp);
5326 for (i = 0; i < bp->cp_nr_rings; i++)
5327 synchronize_irq(bp->irq_tbl[i].vector);
5328 }
5329
5330 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
5331 {
5332 int rc = 0;
5333
5334 #ifdef CONFIG_BNXT_SRIOV
5335 if (bp->sriov_cfg) {
5336 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
5337 !bp->sriov_cfg,
5338 BNXT_SRIOV_CFG_WAIT_TMO);
5339 if (rc)
5340 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
5341 }
5342 #endif
5343 /* Change device state to avoid TX queue wake up's */
5344 bnxt_tx_disable(bp);
5345
5346 clear_bit(BNXT_STATE_OPEN, &bp->state);
5347 smp_mb__after_atomic();
5348 while (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state))
5349 msleep(20);
5350
5351 /* Flush rings before disabling interrupts */
5352 bnxt_shutdown_nic(bp, irq_re_init);
5353
5354 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
5355
5356 bnxt_disable_napi(bp);
5357 bnxt_disable_int_sync(bp);
5358 del_timer_sync(&bp->timer);
5359 bnxt_free_skbs(bp);
5360
5361 if (irq_re_init) {
5362 bnxt_free_irq(bp);
5363 bnxt_del_napi(bp);
5364 }
5365 bnxt_free_mem(bp, irq_re_init);
5366 return rc;
5367 }
5368
5369 static int bnxt_close(struct net_device *dev)
5370 {
5371 struct bnxt *bp = netdev_priv(dev);
5372
5373 bnxt_close_nic(bp, true, true);
5374 bnxt_hwrm_shutdown_link(bp);
5375 return 0;
5376 }
5377
5378 /* rtnl_lock held */
5379 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5380 {
5381 switch (cmd) {
5382 case SIOCGMIIPHY:
5383 /* fallthru */
5384 case SIOCGMIIREG: {
5385 if (!netif_running(dev))
5386 return -EAGAIN;
5387
5388 return 0;
5389 }
5390
5391 case SIOCSMIIREG:
5392 if (!netif_running(dev))
5393 return -EAGAIN;
5394
5395 return 0;
5396
5397 default:
5398 /* do nothing */
5399 break;
5400 }
5401 return -EOPNOTSUPP;
5402 }
5403
5404 static struct rtnl_link_stats64 *
5405 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
5406 {
5407 u32 i;
5408 struct bnxt *bp = netdev_priv(dev);
5409
5410 memset(stats, 0, sizeof(struct rtnl_link_stats64));
5411
5412 if (!bp->bnapi)
5413 return stats;
5414
5415 /* TODO check if we need to synchronize with bnxt_close path */
5416 for (i = 0; i < bp->cp_nr_rings; i++) {
5417 struct bnxt_napi *bnapi = bp->bnapi[i];
5418 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5419 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
5420
5421 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
5422 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
5423 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
5424
5425 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
5426 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
5427 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
5428
5429 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
5430 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
5431 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
5432
5433 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
5434 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
5435 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
5436
5437 stats->rx_missed_errors +=
5438 le64_to_cpu(hw_stats->rx_discard_pkts);
5439
5440 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
5441
5442 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
5443 }
5444
5445 if (bp->flags & BNXT_FLAG_PORT_STATS) {
5446 struct rx_port_stats *rx = bp->hw_rx_port_stats;
5447 struct tx_port_stats *tx = bp->hw_tx_port_stats;
5448
5449 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames);
5450 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames);
5451 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) +
5452 le64_to_cpu(rx->rx_ovrsz_frames) +
5453 le64_to_cpu(rx->rx_runt_frames);
5454 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) +
5455 le64_to_cpu(rx->rx_jbr_frames);
5456 stats->collisions = le64_to_cpu(tx->tx_total_collisions);
5457 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns);
5458 stats->tx_errors = le64_to_cpu(tx->tx_err);
5459 }
5460
5461 return stats;
5462 }
5463
5464 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
5465 {
5466 struct net_device *dev = bp->dev;
5467 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5468 struct netdev_hw_addr *ha;
5469 u8 *haddr;
5470 int mc_count = 0;
5471 bool update = false;
5472 int off = 0;
5473
5474 netdev_for_each_mc_addr(ha, dev) {
5475 if (mc_count >= BNXT_MAX_MC_ADDRS) {
5476 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
5477 vnic->mc_list_count = 0;
5478 return false;
5479 }
5480 haddr = ha->addr;
5481 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
5482 memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
5483 update = true;
5484 }
5485 off += ETH_ALEN;
5486 mc_count++;
5487 }
5488 if (mc_count)
5489 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
5490
5491 if (mc_count != vnic->mc_list_count) {
5492 vnic->mc_list_count = mc_count;
5493 update = true;
5494 }
5495 return update;
5496 }
5497
5498 static bool bnxt_uc_list_updated(struct bnxt *bp)
5499 {
5500 struct net_device *dev = bp->dev;
5501 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5502 struct netdev_hw_addr *ha;
5503 int off = 0;
5504
5505 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
5506 return true;
5507
5508 netdev_for_each_uc_addr(ha, dev) {
5509 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
5510 return true;
5511
5512 off += ETH_ALEN;
5513 }
5514 return false;
5515 }
5516
5517 static void bnxt_set_rx_mode(struct net_device *dev)
5518 {
5519 struct bnxt *bp = netdev_priv(dev);
5520 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5521 u32 mask = vnic->rx_mask;
5522 bool mc_update = false;
5523 bool uc_update;
5524
5525 if (!netif_running(dev))
5526 return;
5527
5528 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
5529 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
5530 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST);
5531
5532 /* Only allow PF to be in promiscuous mode */
5533 if ((dev->flags & IFF_PROMISC) && BNXT_PF(bp))
5534 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
5535
5536 uc_update = bnxt_uc_list_updated(bp);
5537
5538 if (dev->flags & IFF_ALLMULTI) {
5539 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
5540 vnic->mc_list_count = 0;
5541 } else {
5542 mc_update = bnxt_mc_list_updated(bp, &mask);
5543 }
5544
5545 if (mask != vnic->rx_mask || uc_update || mc_update) {
5546 vnic->rx_mask = mask;
5547
5548 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
5549 schedule_work(&bp->sp_task);
5550 }
5551 }
5552
5553 static int bnxt_cfg_rx_mode(struct bnxt *bp)
5554 {
5555 struct net_device *dev = bp->dev;
5556 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5557 struct netdev_hw_addr *ha;
5558 int i, off = 0, rc;
5559 bool uc_update;
5560
5561 netif_addr_lock_bh(dev);
5562 uc_update = bnxt_uc_list_updated(bp);
5563 netif_addr_unlock_bh(dev);
5564
5565 if (!uc_update)
5566 goto skip_uc;
5567
5568 mutex_lock(&bp->hwrm_cmd_lock);
5569 for (i = 1; i < vnic->uc_filter_count; i++) {
5570 struct hwrm_cfa_l2_filter_free_input req = {0};
5571
5572 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
5573 -1);
5574
5575 req.l2_filter_id = vnic->fw_l2_filter_id[i];
5576
5577 rc = _hwrm_send_message(bp, &req, sizeof(req),
5578 HWRM_CMD_TIMEOUT);
5579 }
5580 mutex_unlock(&bp->hwrm_cmd_lock);
5581
5582 vnic->uc_filter_count = 1;
5583
5584 netif_addr_lock_bh(dev);
5585 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
5586 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
5587 } else {
5588 netdev_for_each_uc_addr(ha, dev) {
5589 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
5590 off += ETH_ALEN;
5591 vnic->uc_filter_count++;
5592 }
5593 }
5594 netif_addr_unlock_bh(dev);
5595
5596 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
5597 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
5598 if (rc) {
5599 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
5600 rc);
5601 vnic->uc_filter_count = i;
5602 return rc;
5603 }
5604 }
5605
5606 skip_uc:
5607 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
5608 if (rc)
5609 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n",
5610 rc);
5611
5612 return rc;
5613 }
5614
5615 static bool bnxt_rfs_capable(struct bnxt *bp)
5616 {
5617 #ifdef CONFIG_RFS_ACCEL
5618 struct bnxt_pf_info *pf = &bp->pf;
5619 int vnics;
5620
5621 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_MSIX_CAP))
5622 return false;
5623
5624 vnics = 1 + bp->rx_nr_rings;
5625 if (vnics > pf->max_rsscos_ctxs || vnics > pf->max_vnics)
5626 return false;
5627
5628 return true;
5629 #else
5630 return false;
5631 #endif
5632 }
5633
5634 static netdev_features_t bnxt_fix_features(struct net_device *dev,
5635 netdev_features_t features)
5636 {
5637 struct bnxt *bp = netdev_priv(dev);
5638
5639 if (!bnxt_rfs_capable(bp))
5640 features &= ~NETIF_F_NTUPLE;
5641
5642 /* Both CTAG and STAG VLAN accelaration on the RX side have to be
5643 * turned on or off together.
5644 */
5645 if ((features & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) !=
5646 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) {
5647 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
5648 features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
5649 NETIF_F_HW_VLAN_STAG_RX);
5650 else
5651 features |= NETIF_F_HW_VLAN_CTAG_RX |
5652 NETIF_F_HW_VLAN_STAG_RX;
5653 }
5654 #ifdef CONFIG_BNXT_SRIOV
5655 if (BNXT_VF(bp)) {
5656 if (bp->vf.vlan) {
5657 features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
5658 NETIF_F_HW_VLAN_STAG_RX);
5659 }
5660 }
5661 #endif
5662 return features;
5663 }
5664
5665 static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
5666 {
5667 struct bnxt *bp = netdev_priv(dev);
5668 u32 flags = bp->flags;
5669 u32 changes;
5670 int rc = 0;
5671 bool re_init = false;
5672 bool update_tpa = false;
5673
5674 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
5675 if ((features & NETIF_F_GRO) && (bp->pdev->revision > 0))
5676 flags |= BNXT_FLAG_GRO;
5677 if (features & NETIF_F_LRO)
5678 flags |= BNXT_FLAG_LRO;
5679
5680 if (features & NETIF_F_HW_VLAN_CTAG_RX)
5681 flags |= BNXT_FLAG_STRIP_VLAN;
5682
5683 if (features & NETIF_F_NTUPLE)
5684 flags |= BNXT_FLAG_RFS;
5685
5686 changes = flags ^ bp->flags;
5687 if (changes & BNXT_FLAG_TPA) {
5688 update_tpa = true;
5689 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
5690 (flags & BNXT_FLAG_TPA) == 0)
5691 re_init = true;
5692 }
5693
5694 if (changes & ~BNXT_FLAG_TPA)
5695 re_init = true;
5696
5697 if (flags != bp->flags) {
5698 u32 old_flags = bp->flags;
5699
5700 bp->flags = flags;
5701
5702 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
5703 if (update_tpa)
5704 bnxt_set_ring_params(bp);
5705 return rc;
5706 }
5707
5708 if (re_init) {
5709 bnxt_close_nic(bp, false, false);
5710 if (update_tpa)
5711 bnxt_set_ring_params(bp);
5712
5713 return bnxt_open_nic(bp, false, false);
5714 }
5715 if (update_tpa) {
5716 rc = bnxt_set_tpa(bp,
5717 (flags & BNXT_FLAG_TPA) ?
5718 true : false);
5719 if (rc)
5720 bp->flags = old_flags;
5721 }
5722 }
5723 return rc;
5724 }
5725
5726 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
5727 {
5728 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
5729 int i = bnapi->index;
5730
5731 if (!txr)
5732 return;
5733
5734 netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
5735 i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
5736 txr->tx_cons);
5737 }
5738
5739 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
5740 {
5741 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
5742 int i = bnapi->index;
5743
5744 if (!rxr)
5745 return;
5746
5747 netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
5748 i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
5749 rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
5750 rxr->rx_sw_agg_prod);
5751 }
5752
5753 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
5754 {
5755 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5756 int i = bnapi->index;
5757
5758 netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
5759 i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
5760 }
5761
5762 static void bnxt_dbg_dump_states(struct bnxt *bp)
5763 {
5764 int i;
5765 struct bnxt_napi *bnapi;
5766
5767 for (i = 0; i < bp->cp_nr_rings; i++) {
5768 bnapi = bp->bnapi[i];
5769 if (netif_msg_drv(bp)) {
5770 bnxt_dump_tx_sw_state(bnapi);
5771 bnxt_dump_rx_sw_state(bnapi);
5772 bnxt_dump_cp_sw_state(bnapi);
5773 }
5774 }
5775 }
5776
5777 static void bnxt_reset_task(struct bnxt *bp, bool silent)
5778 {
5779 if (!silent)
5780 bnxt_dbg_dump_states(bp);
5781 if (netif_running(bp->dev)) {
5782 bnxt_close_nic(bp, false, false);
5783 bnxt_open_nic(bp, false, false);
5784 }
5785 }
5786
5787 static void bnxt_tx_timeout(struct net_device *dev)
5788 {
5789 struct bnxt *bp = netdev_priv(dev);
5790
5791 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n");
5792 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
5793 schedule_work(&bp->sp_task);
5794 }
5795
5796 #ifdef CONFIG_NET_POLL_CONTROLLER
5797 static void bnxt_poll_controller(struct net_device *dev)
5798 {
5799 struct bnxt *bp = netdev_priv(dev);
5800 int i;
5801
5802 for (i = 0; i < bp->cp_nr_rings; i++) {
5803 struct bnxt_irq *irq = &bp->irq_tbl[i];
5804
5805 disable_irq(irq->vector);
5806 irq->handler(irq->vector, bp->bnapi[i]);
5807 enable_irq(irq->vector);
5808 }
5809 }
5810 #endif
5811
5812 static void bnxt_timer(unsigned long data)
5813 {
5814 struct bnxt *bp = (struct bnxt *)data;
5815 struct net_device *dev = bp->dev;
5816
5817 if (!netif_running(dev))
5818 return;
5819
5820 if (atomic_read(&bp->intr_sem) != 0)
5821 goto bnxt_restart_timer;
5822
5823 if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS)) {
5824 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
5825 schedule_work(&bp->sp_task);
5826 }
5827 bnxt_restart_timer:
5828 mod_timer(&bp->timer, jiffies + bp->current_interval);
5829 }
5830
5831 /* Only called from bnxt_sp_task() */
5832 static void bnxt_reset(struct bnxt *bp, bool silent)
5833 {
5834 /* bnxt_reset_task() calls bnxt_close_nic() which waits
5835 * for BNXT_STATE_IN_SP_TASK to clear.
5836 * If there is a parallel dev_close(), bnxt_close() may be holding
5837 * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we
5838 * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
5839 */
5840 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5841 rtnl_lock();
5842 if (test_bit(BNXT_STATE_OPEN, &bp->state))
5843 bnxt_reset_task(bp, silent);
5844 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5845 rtnl_unlock();
5846 }
5847
5848 static void bnxt_cfg_ntp_filters(struct bnxt *);
5849
5850 static void bnxt_sp_task(struct work_struct *work)
5851 {
5852 struct bnxt *bp = container_of(work, struct bnxt, sp_task);
5853 int rc;
5854
5855 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5856 smp_mb__after_atomic();
5857 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
5858 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5859 return;
5860 }
5861
5862 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
5863 bnxt_cfg_rx_mode(bp);
5864
5865 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
5866 bnxt_cfg_ntp_filters(bp);
5867 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
5868 rc = bnxt_update_link(bp, true);
5869 if (rc)
5870 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
5871 rc);
5872 }
5873 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
5874 bnxt_hwrm_exec_fwd_req(bp);
5875 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
5876 bnxt_hwrm_tunnel_dst_port_alloc(
5877 bp, bp->vxlan_port,
5878 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
5879 }
5880 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
5881 bnxt_hwrm_tunnel_dst_port_free(
5882 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
5883 }
5884 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
5885 bnxt_reset(bp, false);
5886
5887 if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
5888 bnxt_reset(bp, true);
5889
5890 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event))
5891 bnxt_get_port_module_status(bp);
5892
5893 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event))
5894 bnxt_hwrm_port_qstats(bp);
5895
5896 smp_mb__before_atomic();
5897 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5898 }
5899
5900 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
5901 {
5902 int rc;
5903 struct bnxt *bp = netdev_priv(dev);
5904
5905 SET_NETDEV_DEV(dev, &pdev->dev);
5906
5907 /* enable device (incl. PCI PM wakeup), and bus-mastering */
5908 rc = pci_enable_device(pdev);
5909 if (rc) {
5910 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
5911 goto init_err;
5912 }
5913
5914 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
5915 dev_err(&pdev->dev,
5916 "Cannot find PCI device base address, aborting\n");
5917 rc = -ENODEV;
5918 goto init_err_disable;
5919 }
5920
5921 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
5922 if (rc) {
5923 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
5924 goto init_err_disable;
5925 }
5926
5927 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
5928 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
5929 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
5930 goto init_err_disable;
5931 }
5932
5933 pci_set_master(pdev);
5934
5935 bp->dev = dev;
5936 bp->pdev = pdev;
5937
5938 bp->bar0 = pci_ioremap_bar(pdev, 0);
5939 if (!bp->bar0) {
5940 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
5941 rc = -ENOMEM;
5942 goto init_err_release;
5943 }
5944
5945 bp->bar1 = pci_ioremap_bar(pdev, 2);
5946 if (!bp->bar1) {
5947 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
5948 rc = -ENOMEM;
5949 goto init_err_release;
5950 }
5951
5952 bp->bar2 = pci_ioremap_bar(pdev, 4);
5953 if (!bp->bar2) {
5954 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
5955 rc = -ENOMEM;
5956 goto init_err_release;
5957 }
5958
5959 pci_enable_pcie_error_reporting(pdev);
5960
5961 INIT_WORK(&bp->sp_task, bnxt_sp_task);
5962
5963 spin_lock_init(&bp->ntp_fltr_lock);
5964
5965 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
5966 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
5967
5968 /* tick values in micro seconds */
5969 bp->rx_coal_ticks = 12;
5970 bp->rx_coal_bufs = 30;
5971 bp->rx_coal_ticks_irq = 1;
5972 bp->rx_coal_bufs_irq = 2;
5973
5974 bp->tx_coal_ticks = 25;
5975 bp->tx_coal_bufs = 30;
5976 bp->tx_coal_ticks_irq = 2;
5977 bp->tx_coal_bufs_irq = 2;
5978
5979 init_timer(&bp->timer);
5980 bp->timer.data = (unsigned long)bp;
5981 bp->timer.function = bnxt_timer;
5982 bp->current_interval = BNXT_TIMER_INTERVAL;
5983
5984 clear_bit(BNXT_STATE_OPEN, &bp->state);
5985
5986 return 0;
5987
5988 init_err_release:
5989 if (bp->bar2) {
5990 pci_iounmap(pdev, bp->bar2);
5991 bp->bar2 = NULL;
5992 }
5993
5994 if (bp->bar1) {
5995 pci_iounmap(pdev, bp->bar1);
5996 bp->bar1 = NULL;
5997 }
5998
5999 if (bp->bar0) {
6000 pci_iounmap(pdev, bp->bar0);
6001 bp->bar0 = NULL;
6002 }
6003
6004 pci_release_regions(pdev);
6005
6006 init_err_disable:
6007 pci_disable_device(pdev);
6008
6009 init_err:
6010 return rc;
6011 }
6012
6013 /* rtnl_lock held */
6014 static int bnxt_change_mac_addr(struct net_device *dev, void *p)
6015 {
6016 struct sockaddr *addr = p;
6017 struct bnxt *bp = netdev_priv(dev);
6018 int rc = 0;
6019
6020 if (!is_valid_ether_addr(addr->sa_data))
6021 return -EADDRNOTAVAIL;
6022
6023 rc = bnxt_approve_mac(bp, addr->sa_data);
6024 if (rc)
6025 return rc;
6026
6027 if (ether_addr_equal(addr->sa_data, dev->dev_addr))
6028 return 0;
6029
6030 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6031 if (netif_running(dev)) {
6032 bnxt_close_nic(bp, false, false);
6033 rc = bnxt_open_nic(bp, false, false);
6034 }
6035
6036 return rc;
6037 }
6038
6039 /* rtnl_lock held */
6040 static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
6041 {
6042 struct bnxt *bp = netdev_priv(dev);
6043
6044 if (new_mtu < 60 || new_mtu > 9000)
6045 return -EINVAL;
6046
6047 if (netif_running(dev))
6048 bnxt_close_nic(bp, false, false);
6049
6050 dev->mtu = new_mtu;
6051 bnxt_set_ring_params(bp);
6052
6053 if (netif_running(dev))
6054 return bnxt_open_nic(bp, false, false);
6055
6056 return 0;
6057 }
6058
6059 static int bnxt_setup_tc(struct net_device *dev, u32 handle, __be16 proto,
6060 struct tc_to_netdev *ntc)
6061 {
6062 struct bnxt *bp = netdev_priv(dev);
6063 u8 tc;
6064
6065 if (ntc->type != TC_SETUP_MQPRIO)
6066 return -EINVAL;
6067
6068 tc = ntc->tc;
6069
6070 if (tc > bp->max_tc) {
6071 netdev_err(dev, "too many traffic classes requested: %d Max supported is %d\n",
6072 tc, bp->max_tc);
6073 return -EINVAL;
6074 }
6075
6076 if (netdev_get_num_tc(dev) == tc)
6077 return 0;
6078
6079 if (tc) {
6080 int max_rx_rings, max_tx_rings, rc;
6081 bool sh = false;
6082
6083 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
6084 sh = true;
6085
6086 rc = bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, sh);
6087 if (rc || bp->tx_nr_rings_per_tc * tc > max_tx_rings)
6088 return -ENOMEM;
6089 }
6090
6091 /* Needs to close the device and do hw resource re-allocations */
6092 if (netif_running(bp->dev))
6093 bnxt_close_nic(bp, true, false);
6094
6095 if (tc) {
6096 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
6097 netdev_set_num_tc(dev, tc);
6098 } else {
6099 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
6100 netdev_reset_tc(dev);
6101 }
6102 bp->cp_nr_rings = max_t(int, bp->tx_nr_rings, bp->rx_nr_rings);
6103 bp->num_stat_ctxs = bp->cp_nr_rings;
6104
6105 if (netif_running(bp->dev))
6106 return bnxt_open_nic(bp, true, false);
6107
6108 return 0;
6109 }
6110
6111 #ifdef CONFIG_RFS_ACCEL
6112 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
6113 struct bnxt_ntuple_filter *f2)
6114 {
6115 struct flow_keys *keys1 = &f1->fkeys;
6116 struct flow_keys *keys2 = &f2->fkeys;
6117
6118 if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
6119 keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
6120 keys1->ports.ports == keys2->ports.ports &&
6121 keys1->basic.ip_proto == keys2->basic.ip_proto &&
6122 keys1->basic.n_proto == keys2->basic.n_proto &&
6123 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr))
6124 return true;
6125
6126 return false;
6127 }
6128
6129 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
6130 u16 rxq_index, u32 flow_id)
6131 {
6132 struct bnxt *bp = netdev_priv(dev);
6133 struct bnxt_ntuple_filter *fltr, *new_fltr;
6134 struct flow_keys *fkeys;
6135 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
6136 int rc = 0, idx, bit_id;
6137 struct hlist_head *head;
6138
6139 if (skb->encapsulation)
6140 return -EPROTONOSUPPORT;
6141
6142 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
6143 if (!new_fltr)
6144 return -ENOMEM;
6145
6146 fkeys = &new_fltr->fkeys;
6147 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
6148 rc = -EPROTONOSUPPORT;
6149 goto err_free;
6150 }
6151
6152 if ((fkeys->basic.n_proto != htons(ETH_P_IP)) ||
6153 ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
6154 (fkeys->basic.ip_proto != IPPROTO_UDP))) {
6155 rc = -EPROTONOSUPPORT;
6156 goto err_free;
6157 }
6158
6159 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
6160
6161 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
6162 head = &bp->ntp_fltr_hash_tbl[idx];
6163 rcu_read_lock();
6164 hlist_for_each_entry_rcu(fltr, head, hash) {
6165 if (bnxt_fltr_match(fltr, new_fltr)) {
6166 rcu_read_unlock();
6167 rc = 0;
6168 goto err_free;
6169 }
6170 }
6171 rcu_read_unlock();
6172
6173 spin_lock_bh(&bp->ntp_fltr_lock);
6174 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
6175 BNXT_NTP_FLTR_MAX_FLTR, 0);
6176 if (bit_id < 0) {
6177 spin_unlock_bh(&bp->ntp_fltr_lock);
6178 rc = -ENOMEM;
6179 goto err_free;
6180 }
6181
6182 new_fltr->sw_id = (u16)bit_id;
6183 new_fltr->flow_id = flow_id;
6184 new_fltr->rxq = rxq_index;
6185 hlist_add_head_rcu(&new_fltr->hash, head);
6186 bp->ntp_fltr_count++;
6187 spin_unlock_bh(&bp->ntp_fltr_lock);
6188
6189 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
6190 schedule_work(&bp->sp_task);
6191
6192 return new_fltr->sw_id;
6193
6194 err_free:
6195 kfree(new_fltr);
6196 return rc;
6197 }
6198
6199 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
6200 {
6201 int i;
6202
6203 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
6204 struct hlist_head *head;
6205 struct hlist_node *tmp;
6206 struct bnxt_ntuple_filter *fltr;
6207 int rc;
6208
6209 head = &bp->ntp_fltr_hash_tbl[i];
6210 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
6211 bool del = false;
6212
6213 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
6214 if (rps_may_expire_flow(bp->dev, fltr->rxq,
6215 fltr->flow_id,
6216 fltr->sw_id)) {
6217 bnxt_hwrm_cfa_ntuple_filter_free(bp,
6218 fltr);
6219 del = true;
6220 }
6221 } else {
6222 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
6223 fltr);
6224 if (rc)
6225 del = true;
6226 else
6227 set_bit(BNXT_FLTR_VALID, &fltr->state);
6228 }
6229
6230 if (del) {
6231 spin_lock_bh(&bp->ntp_fltr_lock);
6232 hlist_del_rcu(&fltr->hash);
6233 bp->ntp_fltr_count--;
6234 spin_unlock_bh(&bp->ntp_fltr_lock);
6235 synchronize_rcu();
6236 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
6237 kfree(fltr);
6238 }
6239 }
6240 }
6241 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
6242 netdev_info(bp->dev, "Receive PF driver unload event!");
6243 }
6244
6245 #else
6246
6247 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
6248 {
6249 }
6250
6251 #endif /* CONFIG_RFS_ACCEL */
6252
6253 static void bnxt_add_vxlan_port(struct net_device *dev, sa_family_t sa_family,
6254 __be16 port)
6255 {
6256 struct bnxt *bp = netdev_priv(dev);
6257
6258 if (!netif_running(dev))
6259 return;
6260
6261 if (sa_family != AF_INET6 && sa_family != AF_INET)
6262 return;
6263
6264 if (bp->vxlan_port_cnt && bp->vxlan_port != port)
6265 return;
6266
6267 bp->vxlan_port_cnt++;
6268 if (bp->vxlan_port_cnt == 1) {
6269 bp->vxlan_port = port;
6270 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
6271 schedule_work(&bp->sp_task);
6272 }
6273 }
6274
6275 static void bnxt_del_vxlan_port(struct net_device *dev, sa_family_t sa_family,
6276 __be16 port)
6277 {
6278 struct bnxt *bp = netdev_priv(dev);
6279
6280 if (!netif_running(dev))
6281 return;
6282
6283 if (sa_family != AF_INET6 && sa_family != AF_INET)
6284 return;
6285
6286 if (bp->vxlan_port_cnt && bp->vxlan_port == port) {
6287 bp->vxlan_port_cnt--;
6288
6289 if (bp->vxlan_port_cnt == 0) {
6290 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
6291 schedule_work(&bp->sp_task);
6292 }
6293 }
6294 }
6295
6296 static const struct net_device_ops bnxt_netdev_ops = {
6297 .ndo_open = bnxt_open,
6298 .ndo_start_xmit = bnxt_start_xmit,
6299 .ndo_stop = bnxt_close,
6300 .ndo_get_stats64 = bnxt_get_stats64,
6301 .ndo_set_rx_mode = bnxt_set_rx_mode,
6302 .ndo_do_ioctl = bnxt_ioctl,
6303 .ndo_validate_addr = eth_validate_addr,
6304 .ndo_set_mac_address = bnxt_change_mac_addr,
6305 .ndo_change_mtu = bnxt_change_mtu,
6306 .ndo_fix_features = bnxt_fix_features,
6307 .ndo_set_features = bnxt_set_features,
6308 .ndo_tx_timeout = bnxt_tx_timeout,
6309 #ifdef CONFIG_BNXT_SRIOV
6310 .ndo_get_vf_config = bnxt_get_vf_config,
6311 .ndo_set_vf_mac = bnxt_set_vf_mac,
6312 .ndo_set_vf_vlan = bnxt_set_vf_vlan,
6313 .ndo_set_vf_rate = bnxt_set_vf_bw,
6314 .ndo_set_vf_link_state = bnxt_set_vf_link_state,
6315 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk,
6316 #endif
6317 #ifdef CONFIG_NET_POLL_CONTROLLER
6318 .ndo_poll_controller = bnxt_poll_controller,
6319 #endif
6320 .ndo_setup_tc = bnxt_setup_tc,
6321 #ifdef CONFIG_RFS_ACCEL
6322 .ndo_rx_flow_steer = bnxt_rx_flow_steer,
6323 #endif
6324 .ndo_add_vxlan_port = bnxt_add_vxlan_port,
6325 .ndo_del_vxlan_port = bnxt_del_vxlan_port,
6326 #ifdef CONFIG_NET_RX_BUSY_POLL
6327 .ndo_busy_poll = bnxt_busy_poll,
6328 #endif
6329 };
6330
6331 static void bnxt_remove_one(struct pci_dev *pdev)
6332 {
6333 struct net_device *dev = pci_get_drvdata(pdev);
6334 struct bnxt *bp = netdev_priv(dev);
6335
6336 if (BNXT_PF(bp))
6337 bnxt_sriov_disable(bp);
6338
6339 pci_disable_pcie_error_reporting(pdev);
6340 unregister_netdev(dev);
6341 cancel_work_sync(&bp->sp_task);
6342 bp->sp_event = 0;
6343
6344 bnxt_hwrm_func_drv_unrgtr(bp);
6345 bnxt_free_hwrm_resources(bp);
6346 pci_iounmap(pdev, bp->bar2);
6347 pci_iounmap(pdev, bp->bar1);
6348 pci_iounmap(pdev, bp->bar0);
6349 free_netdev(dev);
6350
6351 pci_release_regions(pdev);
6352 pci_disable_device(pdev);
6353 }
6354
6355 static int bnxt_probe_phy(struct bnxt *bp)
6356 {
6357 int rc = 0;
6358 struct bnxt_link_info *link_info = &bp->link_info;
6359
6360 rc = bnxt_hwrm_phy_qcaps(bp);
6361 if (rc) {
6362 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
6363 rc);
6364 return rc;
6365 }
6366
6367 rc = bnxt_update_link(bp, false);
6368 if (rc) {
6369 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
6370 rc);
6371 return rc;
6372 }
6373
6374 /* Older firmware does not have supported_auto_speeds, so assume
6375 * that all supported speeds can be autonegotiated.
6376 */
6377 if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
6378 link_info->support_auto_speeds = link_info->support_speeds;
6379
6380 /*initialize the ethool setting copy with NVM settings */
6381 if (BNXT_AUTO_MODE(link_info->auto_mode)) {
6382 link_info->autoneg = BNXT_AUTONEG_SPEED;
6383 if (bp->hwrm_spec_code >= 0x10201) {
6384 if (link_info->auto_pause_setting &
6385 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
6386 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
6387 } else {
6388 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
6389 }
6390 link_info->advertising = link_info->auto_link_speeds;
6391 } else {
6392 link_info->req_link_speed = link_info->force_link_speed;
6393 link_info->req_duplex = link_info->duplex_setting;
6394 }
6395 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
6396 link_info->req_flow_ctrl =
6397 link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
6398 else
6399 link_info->req_flow_ctrl = link_info->force_pause_setting;
6400 return rc;
6401 }
6402
6403 static int bnxt_get_max_irq(struct pci_dev *pdev)
6404 {
6405 u16 ctrl;
6406
6407 if (!pdev->msix_cap)
6408 return 1;
6409
6410 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
6411 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
6412 }
6413
6414 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
6415 int *max_cp)
6416 {
6417 int max_ring_grps = 0;
6418
6419 #ifdef CONFIG_BNXT_SRIOV
6420 if (!BNXT_PF(bp)) {
6421 *max_tx = bp->vf.max_tx_rings;
6422 *max_rx = bp->vf.max_rx_rings;
6423 *max_cp = min_t(int, bp->vf.max_irqs, bp->vf.max_cp_rings);
6424 *max_cp = min_t(int, *max_cp, bp->vf.max_stat_ctxs);
6425 max_ring_grps = bp->vf.max_hw_ring_grps;
6426 } else
6427 #endif
6428 {
6429 *max_tx = bp->pf.max_tx_rings;
6430 *max_rx = bp->pf.max_rx_rings;
6431 *max_cp = min_t(int, bp->pf.max_irqs, bp->pf.max_cp_rings);
6432 *max_cp = min_t(int, *max_cp, bp->pf.max_stat_ctxs);
6433 max_ring_grps = bp->pf.max_hw_ring_grps;
6434 }
6435
6436 if (bp->flags & BNXT_FLAG_AGG_RINGS)
6437 *max_rx >>= 1;
6438 *max_rx = min_t(int, *max_rx, max_ring_grps);
6439 }
6440
6441 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
6442 {
6443 int rx, tx, cp;
6444
6445 _bnxt_get_max_rings(bp, &rx, &tx, &cp);
6446 if (!rx || !tx || !cp)
6447 return -ENOMEM;
6448
6449 *max_rx = rx;
6450 *max_tx = tx;
6451 return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
6452 }
6453
6454 static int bnxt_set_dflt_rings(struct bnxt *bp)
6455 {
6456 int dflt_rings, max_rx_rings, max_tx_rings, rc;
6457 bool sh = true;
6458
6459 if (sh)
6460 bp->flags |= BNXT_FLAG_SHARED_RINGS;
6461 dflt_rings = netif_get_num_default_rss_queues();
6462 rc = bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, sh);
6463 if (rc)
6464 return rc;
6465 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
6466 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
6467 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
6468 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
6469 bp->tx_nr_rings + bp->rx_nr_rings;
6470 bp->num_stat_ctxs = bp->cp_nr_rings;
6471 return rc;
6472 }
6473
6474 static void bnxt_parse_log_pcie_link(struct bnxt *bp)
6475 {
6476 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
6477 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
6478
6479 if (pcie_get_minimum_link(bp->pdev, &speed, &width) ||
6480 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
6481 netdev_info(bp->dev, "Failed to determine PCIe Link Info\n");
6482 else
6483 netdev_info(bp->dev, "PCIe: Speed %s Width x%d\n",
6484 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
6485 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
6486 speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
6487 "Unknown", width);
6488 }
6489
6490 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6491 {
6492 static int version_printed;
6493 struct net_device *dev;
6494 struct bnxt *bp;
6495 int rc, max_irqs;
6496
6497 if (version_printed++ == 0)
6498 pr_info("%s", version);
6499
6500 max_irqs = bnxt_get_max_irq(pdev);
6501 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
6502 if (!dev)
6503 return -ENOMEM;
6504
6505 bp = netdev_priv(dev);
6506
6507 if (bnxt_vf_pciid(ent->driver_data))
6508 bp->flags |= BNXT_FLAG_VF;
6509
6510 if (pdev->msix_cap)
6511 bp->flags |= BNXT_FLAG_MSIX_CAP;
6512
6513 rc = bnxt_init_board(pdev, dev);
6514 if (rc < 0)
6515 goto init_err_free;
6516
6517 dev->netdev_ops = &bnxt_netdev_ops;
6518 dev->watchdog_timeo = BNXT_TX_TIMEOUT;
6519 dev->ethtool_ops = &bnxt_ethtool_ops;
6520
6521 pci_set_drvdata(pdev, dev);
6522
6523 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
6524 NETIF_F_TSO | NETIF_F_TSO6 |
6525 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
6526 NETIF_F_GSO_IPXIP4 |
6527 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
6528 NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
6529 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO;
6530
6531 dev->hw_enc_features =
6532 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
6533 NETIF_F_TSO | NETIF_F_TSO6 |
6534 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
6535 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
6536 NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;
6537 dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
6538 NETIF_F_GSO_GRE_CSUM;
6539 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
6540 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
6541 NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
6542 dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
6543 dev->priv_flags |= IFF_UNICAST_FLT;
6544
6545 #ifdef CONFIG_BNXT_SRIOV
6546 init_waitqueue_head(&bp->sriov_cfg_wait);
6547 #endif
6548 rc = bnxt_alloc_hwrm_resources(bp);
6549 if (rc)
6550 goto init_err;
6551
6552 mutex_init(&bp->hwrm_cmd_lock);
6553 rc = bnxt_hwrm_ver_get(bp);
6554 if (rc)
6555 goto init_err;
6556
6557 bp->gro_func = bnxt_gro_func_5730x;
6558 if (BNXT_CHIP_NUM_57X1X(bp->chip_num))
6559 bp->gro_func = bnxt_gro_func_5731x;
6560
6561 rc = bnxt_hwrm_func_drv_rgtr(bp);
6562 if (rc)
6563 goto init_err;
6564
6565 /* Get the MAX capabilities for this function */
6566 rc = bnxt_hwrm_func_qcaps(bp);
6567 if (rc) {
6568 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
6569 rc);
6570 rc = -1;
6571 goto init_err;
6572 }
6573
6574 rc = bnxt_hwrm_queue_qportcfg(bp);
6575 if (rc) {
6576 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
6577 rc);
6578 rc = -1;
6579 goto init_err;
6580 }
6581
6582 bnxt_hwrm_func_qcfg(bp);
6583
6584 bnxt_set_tpa_flags(bp);
6585 bnxt_set_ring_params(bp);
6586 if (BNXT_PF(bp))
6587 bp->pf.max_irqs = max_irqs;
6588 #if defined(CONFIG_BNXT_SRIOV)
6589 else
6590 bp->vf.max_irqs = max_irqs;
6591 #endif
6592 bnxt_set_dflt_rings(bp);
6593
6594 if (BNXT_PF(bp)) {
6595 dev->hw_features |= NETIF_F_NTUPLE;
6596 if (bnxt_rfs_capable(bp)) {
6597 bp->flags |= BNXT_FLAG_RFS;
6598 dev->features |= NETIF_F_NTUPLE;
6599 }
6600 }
6601
6602 if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
6603 bp->flags |= BNXT_FLAG_STRIP_VLAN;
6604
6605 rc = bnxt_probe_phy(bp);
6606 if (rc)
6607 goto init_err;
6608
6609 rc = register_netdev(dev);
6610 if (rc)
6611 goto init_err;
6612
6613 netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
6614 board_info[ent->driver_data].name,
6615 (long)pci_resource_start(pdev, 0), dev->dev_addr);
6616
6617 bnxt_parse_log_pcie_link(bp);
6618
6619 return 0;
6620
6621 init_err:
6622 pci_iounmap(pdev, bp->bar0);
6623 pci_release_regions(pdev);
6624 pci_disable_device(pdev);
6625
6626 init_err_free:
6627 free_netdev(dev);
6628 return rc;
6629 }
6630
6631 /**
6632 * bnxt_io_error_detected - called when PCI error is detected
6633 * @pdev: Pointer to PCI device
6634 * @state: The current pci connection state
6635 *
6636 * This function is called after a PCI bus error affecting
6637 * this device has been detected.
6638 */
6639 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
6640 pci_channel_state_t state)
6641 {
6642 struct net_device *netdev = pci_get_drvdata(pdev);
6643
6644 netdev_info(netdev, "PCI I/O error detected\n");
6645
6646 rtnl_lock();
6647 netif_device_detach(netdev);
6648
6649 if (state == pci_channel_io_perm_failure) {
6650 rtnl_unlock();
6651 return PCI_ERS_RESULT_DISCONNECT;
6652 }
6653
6654 if (netif_running(netdev))
6655 bnxt_close(netdev);
6656
6657 pci_disable_device(pdev);
6658 rtnl_unlock();
6659
6660 /* Request a slot slot reset. */
6661 return PCI_ERS_RESULT_NEED_RESET;
6662 }
6663
6664 /**
6665 * bnxt_io_slot_reset - called after the pci bus has been reset.
6666 * @pdev: Pointer to PCI device
6667 *
6668 * Restart the card from scratch, as if from a cold-boot.
6669 * At this point, the card has exprienced a hard reset,
6670 * followed by fixups by BIOS, and has its config space
6671 * set up identically to what it was at cold boot.
6672 */
6673 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
6674 {
6675 struct net_device *netdev = pci_get_drvdata(pdev);
6676 struct bnxt *bp = netdev_priv(netdev);
6677 int err = 0;
6678 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
6679
6680 netdev_info(bp->dev, "PCI Slot Reset\n");
6681
6682 rtnl_lock();
6683
6684 if (pci_enable_device(pdev)) {
6685 dev_err(&pdev->dev,
6686 "Cannot re-enable PCI device after reset.\n");
6687 } else {
6688 pci_set_master(pdev);
6689
6690 if (netif_running(netdev))
6691 err = bnxt_open(netdev);
6692
6693 if (!err)
6694 result = PCI_ERS_RESULT_RECOVERED;
6695 }
6696
6697 if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev))
6698 dev_close(netdev);
6699
6700 rtnl_unlock();
6701
6702 err = pci_cleanup_aer_uncorrect_error_status(pdev);
6703 if (err) {
6704 dev_err(&pdev->dev,
6705 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
6706 err); /* non-fatal, continue */
6707 }
6708
6709 return PCI_ERS_RESULT_RECOVERED;
6710 }
6711
6712 /**
6713 * bnxt_io_resume - called when traffic can start flowing again.
6714 * @pdev: Pointer to PCI device
6715 *
6716 * This callback is called when the error recovery driver tells
6717 * us that its OK to resume normal operation.
6718 */
6719 static void bnxt_io_resume(struct pci_dev *pdev)
6720 {
6721 struct net_device *netdev = pci_get_drvdata(pdev);
6722
6723 rtnl_lock();
6724
6725 netif_device_attach(netdev);
6726
6727 rtnl_unlock();
6728 }
6729
6730 static const struct pci_error_handlers bnxt_err_handler = {
6731 .error_detected = bnxt_io_error_detected,
6732 .slot_reset = bnxt_io_slot_reset,
6733 .resume = bnxt_io_resume
6734 };
6735
6736 static struct pci_driver bnxt_pci_driver = {
6737 .name = DRV_MODULE_NAME,
6738 .id_table = bnxt_pci_tbl,
6739 .probe = bnxt_init_one,
6740 .remove = bnxt_remove_one,
6741 .err_handler = &bnxt_err_handler,
6742 #if defined(CONFIG_BNXT_SRIOV)
6743 .sriov_configure = bnxt_sriov_configure,
6744 #endif
6745 };
6746
6747 module_pci_driver(bnxt_pci_driver);
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