1 /* Broadcom NetXtreme-C/E network driver.
3 * Copyright (c) 2014-2015 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
10 #include <linux/module.h>
12 #include <linux/stringify.h>
13 #include <linux/kernel.h>
14 #include <linux/timer.h>
15 #include <linux/errno.h>
16 #include <linux/ioport.h>
17 #include <linux/slab.h>
18 #include <linux/vmalloc.h>
19 #include <linux/interrupt.h>
20 #include <linux/pci.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23 #include <linux/skbuff.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/bitops.h>
27 #include <linux/irq.h>
28 #include <linux/delay.h>
29 #include <asm/byteorder.h>
31 #include <linux/time.h>
32 #include <linux/mii.h>
34 #include <linux/if_vlan.h>
38 #include <net/checksum.h>
39 #include <net/ip6_checksum.h>
40 #if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE)
41 #include <net/vxlan.h>
43 #ifdef CONFIG_NET_RX_BUSY_POLL
44 #include <net/busy_poll.h>
46 #include <linux/workqueue.h>
47 #include <linux/prefetch.h>
48 #include <linux/cache.h>
49 #include <linux/log2.h>
50 #include <linux/aer.h>
51 #include <linux/bitmap.h>
52 #include <linux/cpu_rmap.h>
56 #include "bnxt_sriov.h"
57 #include "bnxt_ethtool.h"
59 #define BNXT_TX_TIMEOUT (5 * HZ)
61 static const char version
[] =
62 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME
" v" DRV_MODULE_VERSION
"\n";
64 MODULE_LICENSE("GPL");
65 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
66 MODULE_VERSION(DRV_MODULE_VERSION
);
68 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
69 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
70 #define BNXT_RX_COPY_THRESH 256
72 #define BNXT_TX_PUSH_THRESH 164
85 /* indexed by enum above */
89 { "Broadcom BCM57301 NetXtreme-C Single-port 10Gb Ethernet" },
90 { "Broadcom BCM57302 NetXtreme-C Dual-port 10Gb/25Gb Ethernet" },
91 { "Broadcom BCM57304 NetXtreme-C Dual-port 10Gb/25Gb/40Gb/50Gb Ethernet" },
92 { "Broadcom BCM57402 NetXtreme-E Dual-port 10Gb Ethernet" },
93 { "Broadcom BCM57404 NetXtreme-E Dual-port 10Gb/25Gb Ethernet" },
94 { "Broadcom BCM57406 NetXtreme-E Dual-port 10GBase-T Ethernet" },
95 { "Broadcom BCM57304 NetXtreme-C Ethernet Virtual Function" },
96 { "Broadcom BCM57404 NetXtreme-E Ethernet Virtual Function" },
99 static const struct pci_device_id bnxt_pci_tbl
[] = {
100 { PCI_VDEVICE(BROADCOM
, 0x16c8), .driver_data
= BCM57301
},
101 { PCI_VDEVICE(BROADCOM
, 0x16c9), .driver_data
= BCM57302
},
102 { PCI_VDEVICE(BROADCOM
, 0x16ca), .driver_data
= BCM57304
},
103 { PCI_VDEVICE(BROADCOM
, 0x16d0), .driver_data
= BCM57402
},
104 { PCI_VDEVICE(BROADCOM
, 0x16d1), .driver_data
= BCM57404
},
105 { PCI_VDEVICE(BROADCOM
, 0x16d2), .driver_data
= BCM57406
},
106 #ifdef CONFIG_BNXT_SRIOV
107 { PCI_VDEVICE(BROADCOM
, 0x16cb), .driver_data
= BCM57304_VF
},
108 { PCI_VDEVICE(BROADCOM
, 0x16d3), .driver_data
= BCM57404_VF
},
113 MODULE_DEVICE_TABLE(pci
, bnxt_pci_tbl
);
115 static const u16 bnxt_vf_req_snif
[] = {
118 HWRM_CFA_L2_FILTER_ALLOC
,
121 static bool bnxt_vf_pciid(enum board_idx idx
)
123 return (idx
== BCM57304_VF
|| idx
== BCM57404_VF
);
126 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
127 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
128 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
130 #define BNXT_CP_DB_REARM(db, raw_cons) \
131 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
133 #define BNXT_CP_DB(db, raw_cons) \
134 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
136 #define BNXT_CP_DB_IRQ_DIS(db) \
137 writel(DB_CP_IRQ_DIS_FLAGS, db)
139 static inline u32
bnxt_tx_avail(struct bnxt
*bp
, struct bnxt_tx_ring_info
*txr
)
141 /* Tell compiler to fetch tx indices from memory. */
144 return bp
->tx_ring_size
-
145 ((txr
->tx_prod
- txr
->tx_cons
) & bp
->tx_ring_mask
);
148 static const u16 bnxt_lhint_arr
[] = {
149 TX_BD_FLAGS_LHINT_512_AND_SMALLER
,
150 TX_BD_FLAGS_LHINT_512_TO_1023
,
151 TX_BD_FLAGS_LHINT_1024_TO_2047
,
152 TX_BD_FLAGS_LHINT_1024_TO_2047
,
153 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
154 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
155 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
156 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
157 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
158 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
159 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
160 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
161 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
162 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
163 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
164 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
165 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
166 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
167 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
170 static netdev_tx_t
bnxt_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
172 struct bnxt
*bp
= netdev_priv(dev
);
174 struct tx_bd_ext
*txbd1
;
175 struct netdev_queue
*txq
;
178 unsigned int length
, pad
= 0;
179 u32 len
, free_size
, vlan_tag_flags
, cfa_action
, flags
;
181 struct pci_dev
*pdev
= bp
->pdev
;
182 struct bnxt_tx_ring_info
*txr
;
183 struct bnxt_sw_tx_bd
*tx_buf
;
185 i
= skb_get_queue_mapping(skb
);
186 if (unlikely(i
>= bp
->tx_nr_rings
)) {
187 dev_kfree_skb_any(skb
);
191 txr
= &bp
->tx_ring
[i
];
192 txq
= netdev_get_tx_queue(dev
, i
);
195 free_size
= bnxt_tx_avail(bp
, txr
);
196 if (unlikely(free_size
< skb_shinfo(skb
)->nr_frags
+ 2)) {
197 netif_tx_stop_queue(txq
);
198 return NETDEV_TX_BUSY
;
202 len
= skb_headlen(skb
);
203 last_frag
= skb_shinfo(skb
)->nr_frags
;
205 txbd
= &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
207 txbd
->tx_bd_opaque
= prod
;
209 tx_buf
= &txr
->tx_buf_ring
[prod
];
211 tx_buf
->nr_frags
= last_frag
;
215 if (skb_vlan_tag_present(skb
)) {
216 vlan_tag_flags
= TX_BD_CFA_META_KEY_VLAN
|
217 skb_vlan_tag_get(skb
);
218 /* Currently supports 8021Q, 8021AD vlan offloads
219 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
221 if (skb
->vlan_proto
== htons(ETH_P_8021Q
))
222 vlan_tag_flags
|= 1 << TX_BD_CFA_META_TPID_SHIFT
;
225 if (free_size
== bp
->tx_ring_size
&& length
<= bp
->tx_push_thresh
) {
226 struct tx_push_buffer
*tx_push_buf
= txr
->tx_push
;
227 struct tx_push_bd
*tx_push
= &tx_push_buf
->push_bd
;
228 struct tx_bd_ext
*tx_push1
= &tx_push
->txbd2
;
229 void *pdata
= tx_push_buf
->data
;
233 /* Set COAL_NOW to be ready quickly for the next push */
234 tx_push
->tx_bd_len_flags_type
=
235 cpu_to_le32((length
<< TX_BD_LEN_SHIFT
) |
236 TX_BD_TYPE_LONG_TX_BD
|
237 TX_BD_FLAGS_LHINT_512_AND_SMALLER
|
238 TX_BD_FLAGS_COAL_NOW
|
239 TX_BD_FLAGS_PACKET_END
|
240 (2 << TX_BD_FLAGS_BD_CNT_SHIFT
));
242 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
243 tx_push1
->tx_bd_hsize_lflags
=
244 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM
);
246 tx_push1
->tx_bd_hsize_lflags
= 0;
248 tx_push1
->tx_bd_cfa_meta
= cpu_to_le32(vlan_tag_flags
);
249 tx_push1
->tx_bd_cfa_action
= cpu_to_le32(cfa_action
);
251 end
= PTR_ALIGN(pdata
+ length
+ 1, 8) - 1;
254 skb_copy_from_linear_data(skb
, pdata
, len
);
256 for (j
= 0; j
< last_frag
; j
++) {
257 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[j
];
260 fptr
= skb_frag_address_safe(frag
);
264 memcpy(pdata
, fptr
, skb_frag_size(frag
));
265 pdata
+= skb_frag_size(frag
);
268 txbd
->tx_bd_len_flags_type
= tx_push
->tx_bd_len_flags_type
;
269 txbd
->tx_bd_haddr
= txr
->data_mapping
;
270 prod
= NEXT_TX(prod
);
271 txbd
= &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
272 memcpy(txbd
, tx_push1
, sizeof(*txbd
));
273 prod
= NEXT_TX(prod
);
275 cpu_to_le32(DB_KEY_TX_PUSH
| DB_LONG_TX_PUSH
| prod
);
278 netdev_tx_sent_queue(txq
, skb
->len
);
280 push_len
= (length
+ sizeof(*tx_push
) + 7) / 8;
282 __iowrite64_copy(txr
->tx_doorbell
, tx_push_buf
, 16);
283 __iowrite64_copy(txr
->tx_doorbell
+ 4, tx_push_buf
+ 1,
286 __iowrite64_copy(txr
->tx_doorbell
, tx_push_buf
,
295 if (length
< BNXT_MIN_PKT_SIZE
) {
296 pad
= BNXT_MIN_PKT_SIZE
- length
;
297 if (skb_pad(skb
, pad
)) {
298 /* SKB already freed. */
302 length
= BNXT_MIN_PKT_SIZE
;
305 mapping
= dma_map_single(&pdev
->dev
, skb
->data
, len
, DMA_TO_DEVICE
);
307 if (unlikely(dma_mapping_error(&pdev
->dev
, mapping
))) {
308 dev_kfree_skb_any(skb
);
313 dma_unmap_addr_set(tx_buf
, mapping
, mapping
);
314 flags
= (len
<< TX_BD_LEN_SHIFT
) | TX_BD_TYPE_LONG_TX_BD
|
315 ((last_frag
+ 2) << TX_BD_FLAGS_BD_CNT_SHIFT
);
317 txbd
->tx_bd_haddr
= cpu_to_le64(mapping
);
319 prod
= NEXT_TX(prod
);
320 txbd1
= (struct tx_bd_ext
*)
321 &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
323 txbd1
->tx_bd_hsize_lflags
= 0;
324 if (skb_is_gso(skb
)) {
327 if (skb
->encapsulation
)
328 hdr_len
= skb_inner_network_offset(skb
) +
329 skb_inner_network_header_len(skb
) +
330 inner_tcp_hdrlen(skb
);
332 hdr_len
= skb_transport_offset(skb
) +
335 txbd1
->tx_bd_hsize_lflags
= cpu_to_le32(TX_BD_FLAGS_LSO
|
337 (hdr_len
<< (TX_BD_HSIZE_SHIFT
- 1)));
338 length
= skb_shinfo(skb
)->gso_size
;
339 txbd1
->tx_bd_mss
= cpu_to_le32(length
);
341 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
342 txbd1
->tx_bd_hsize_lflags
=
343 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM
);
344 txbd1
->tx_bd_mss
= 0;
348 flags
|= bnxt_lhint_arr
[length
];
349 txbd
->tx_bd_len_flags_type
= cpu_to_le32(flags
);
351 txbd1
->tx_bd_cfa_meta
= cpu_to_le32(vlan_tag_flags
);
352 txbd1
->tx_bd_cfa_action
= cpu_to_le32(cfa_action
);
353 for (i
= 0; i
< last_frag
; i
++) {
354 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
356 prod
= NEXT_TX(prod
);
357 txbd
= &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
359 len
= skb_frag_size(frag
);
360 mapping
= skb_frag_dma_map(&pdev
->dev
, frag
, 0, len
,
363 if (unlikely(dma_mapping_error(&pdev
->dev
, mapping
)))
366 tx_buf
= &txr
->tx_buf_ring
[prod
];
367 dma_unmap_addr_set(tx_buf
, mapping
, mapping
);
369 txbd
->tx_bd_haddr
= cpu_to_le64(mapping
);
371 flags
= len
<< TX_BD_LEN_SHIFT
;
372 txbd
->tx_bd_len_flags_type
= cpu_to_le32(flags
);
376 txbd
->tx_bd_len_flags_type
=
377 cpu_to_le32(((len
+ pad
) << TX_BD_LEN_SHIFT
) | flags
|
378 TX_BD_FLAGS_PACKET_END
);
380 netdev_tx_sent_queue(txq
, skb
->len
);
382 /* Sync BD data before updating doorbell */
385 prod
= NEXT_TX(prod
);
388 writel(DB_KEY_TX
| prod
, txr
->tx_doorbell
);
389 writel(DB_KEY_TX
| prod
, txr
->tx_doorbell
);
395 if (unlikely(bnxt_tx_avail(bp
, txr
) <= MAX_SKB_FRAGS
+ 1)) {
396 netif_tx_stop_queue(txq
);
398 /* netif_tx_stop_queue() must be done before checking
399 * tx index in bnxt_tx_avail() below, because in
400 * bnxt_tx_int(), we update tx index before checking for
401 * netif_tx_queue_stopped().
404 if (bnxt_tx_avail(bp
, txr
) > bp
->tx_wake_thresh
)
405 netif_tx_wake_queue(txq
);
412 /* start back at beginning and unmap skb */
414 tx_buf
= &txr
->tx_buf_ring
[prod
];
416 dma_unmap_single(&pdev
->dev
, dma_unmap_addr(tx_buf
, mapping
),
417 skb_headlen(skb
), PCI_DMA_TODEVICE
);
418 prod
= NEXT_TX(prod
);
420 /* unmap remaining mapped pages */
421 for (i
= 0; i
< last_frag
; i
++) {
422 prod
= NEXT_TX(prod
);
423 tx_buf
= &txr
->tx_buf_ring
[prod
];
424 dma_unmap_page(&pdev
->dev
, dma_unmap_addr(tx_buf
, mapping
),
425 skb_frag_size(&skb_shinfo(skb
)->frags
[i
]),
429 dev_kfree_skb_any(skb
);
433 static void bnxt_tx_int(struct bnxt
*bp
, struct bnxt_napi
*bnapi
, int nr_pkts
)
435 struct bnxt_tx_ring_info
*txr
= bnapi
->tx_ring
;
436 int index
= txr
- &bp
->tx_ring
[0];
437 struct netdev_queue
*txq
= netdev_get_tx_queue(bp
->dev
, index
);
438 u16 cons
= txr
->tx_cons
;
439 struct pci_dev
*pdev
= bp
->pdev
;
441 unsigned int tx_bytes
= 0;
443 for (i
= 0; i
< nr_pkts
; i
++) {
444 struct bnxt_sw_tx_bd
*tx_buf
;
448 tx_buf
= &txr
->tx_buf_ring
[cons
];
449 cons
= NEXT_TX(cons
);
453 if (tx_buf
->is_push
) {
458 dma_unmap_single(&pdev
->dev
, dma_unmap_addr(tx_buf
, mapping
),
459 skb_headlen(skb
), PCI_DMA_TODEVICE
);
460 last
= tx_buf
->nr_frags
;
462 for (j
= 0; j
< last
; j
++) {
463 cons
= NEXT_TX(cons
);
464 tx_buf
= &txr
->tx_buf_ring
[cons
];
467 dma_unmap_addr(tx_buf
, mapping
),
468 skb_frag_size(&skb_shinfo(skb
)->frags
[j
]),
473 cons
= NEXT_TX(cons
);
475 tx_bytes
+= skb
->len
;
476 dev_kfree_skb_any(skb
);
479 netdev_tx_completed_queue(txq
, nr_pkts
, tx_bytes
);
482 /* Need to make the tx_cons update visible to bnxt_start_xmit()
483 * before checking for netif_tx_queue_stopped(). Without the
484 * memory barrier, there is a small possibility that bnxt_start_xmit()
485 * will miss it and cause the queue to be stopped forever.
489 if (unlikely(netif_tx_queue_stopped(txq
)) &&
490 (bnxt_tx_avail(bp
, txr
) > bp
->tx_wake_thresh
)) {
491 __netif_tx_lock(txq
, smp_processor_id());
492 if (netif_tx_queue_stopped(txq
) &&
493 bnxt_tx_avail(bp
, txr
) > bp
->tx_wake_thresh
&&
494 txr
->dev_state
!= BNXT_DEV_STATE_CLOSING
)
495 netif_tx_wake_queue(txq
);
496 __netif_tx_unlock(txq
);
500 static inline u8
*__bnxt_alloc_rx_data(struct bnxt
*bp
, dma_addr_t
*mapping
,
504 struct pci_dev
*pdev
= bp
->pdev
;
506 data
= kmalloc(bp
->rx_buf_size
, gfp
);
510 *mapping
= dma_map_single(&pdev
->dev
, data
+ BNXT_RX_DMA_OFFSET
,
511 bp
->rx_buf_use_size
, PCI_DMA_FROMDEVICE
);
513 if (dma_mapping_error(&pdev
->dev
, *mapping
)) {
520 static inline int bnxt_alloc_rx_data(struct bnxt
*bp
,
521 struct bnxt_rx_ring_info
*rxr
,
524 struct rx_bd
*rxbd
= &rxr
->rx_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
525 struct bnxt_sw_rx_bd
*rx_buf
= &rxr
->rx_buf_ring
[prod
];
529 data
= __bnxt_alloc_rx_data(bp
, &mapping
, gfp
);
534 dma_unmap_addr_set(rx_buf
, mapping
, mapping
);
536 rxbd
->rx_bd_haddr
= cpu_to_le64(mapping
);
541 static void bnxt_reuse_rx_data(struct bnxt_rx_ring_info
*rxr
, u16 cons
,
544 u16 prod
= rxr
->rx_prod
;
545 struct bnxt_sw_rx_bd
*cons_rx_buf
, *prod_rx_buf
;
546 struct rx_bd
*cons_bd
, *prod_bd
;
548 prod_rx_buf
= &rxr
->rx_buf_ring
[prod
];
549 cons_rx_buf
= &rxr
->rx_buf_ring
[cons
];
551 prod_rx_buf
->data
= data
;
553 dma_unmap_addr_set(prod_rx_buf
, mapping
,
554 dma_unmap_addr(cons_rx_buf
, mapping
));
556 prod_bd
= &rxr
->rx_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
557 cons_bd
= &rxr
->rx_desc_ring
[RX_RING(cons
)][RX_IDX(cons
)];
559 prod_bd
->rx_bd_haddr
= cons_bd
->rx_bd_haddr
;
562 static inline u16
bnxt_find_next_agg_idx(struct bnxt_rx_ring_info
*rxr
, u16 idx
)
564 u16 next
, max
= rxr
->rx_agg_bmap_size
;
566 next
= find_next_zero_bit(rxr
->rx_agg_bmap
, max
, idx
);
568 next
= find_first_zero_bit(rxr
->rx_agg_bmap
, max
);
572 static inline int bnxt_alloc_rx_page(struct bnxt
*bp
,
573 struct bnxt_rx_ring_info
*rxr
,
577 &rxr
->rx_agg_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
578 struct bnxt_sw_rx_agg_bd
*rx_agg_buf
;
579 struct pci_dev
*pdev
= bp
->pdev
;
582 u16 sw_prod
= rxr
->rx_sw_agg_prod
;
584 page
= alloc_page(gfp
);
588 mapping
= dma_map_page(&pdev
->dev
, page
, 0, PAGE_SIZE
,
590 if (dma_mapping_error(&pdev
->dev
, mapping
)) {
595 if (unlikely(test_bit(sw_prod
, rxr
->rx_agg_bmap
)))
596 sw_prod
= bnxt_find_next_agg_idx(rxr
, sw_prod
);
598 __set_bit(sw_prod
, rxr
->rx_agg_bmap
);
599 rx_agg_buf
= &rxr
->rx_agg_ring
[sw_prod
];
600 rxr
->rx_sw_agg_prod
= NEXT_RX_AGG(sw_prod
);
602 rx_agg_buf
->page
= page
;
603 rx_agg_buf
->mapping
= mapping
;
604 rxbd
->rx_bd_haddr
= cpu_to_le64(mapping
);
605 rxbd
->rx_bd_opaque
= sw_prod
;
609 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi
*bnapi
, u16 cp_cons
,
612 struct bnxt
*bp
= bnapi
->bp
;
613 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
614 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
615 u16 prod
= rxr
->rx_agg_prod
;
616 u16 sw_prod
= rxr
->rx_sw_agg_prod
;
619 for (i
= 0; i
< agg_bufs
; i
++) {
621 struct rx_agg_cmp
*agg
;
622 struct bnxt_sw_rx_agg_bd
*cons_rx_buf
, *prod_rx_buf
;
623 struct rx_bd
*prod_bd
;
626 agg
= (struct rx_agg_cmp
*)
627 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
628 cons
= agg
->rx_agg_cmp_opaque
;
629 __clear_bit(cons
, rxr
->rx_agg_bmap
);
631 if (unlikely(test_bit(sw_prod
, rxr
->rx_agg_bmap
)))
632 sw_prod
= bnxt_find_next_agg_idx(rxr
, sw_prod
);
634 __set_bit(sw_prod
, rxr
->rx_agg_bmap
);
635 prod_rx_buf
= &rxr
->rx_agg_ring
[sw_prod
];
636 cons_rx_buf
= &rxr
->rx_agg_ring
[cons
];
638 /* It is possible for sw_prod to be equal to cons, so
639 * set cons_rx_buf->page to NULL first.
641 page
= cons_rx_buf
->page
;
642 cons_rx_buf
->page
= NULL
;
643 prod_rx_buf
->page
= page
;
645 prod_rx_buf
->mapping
= cons_rx_buf
->mapping
;
647 prod_bd
= &rxr
->rx_agg_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
649 prod_bd
->rx_bd_haddr
= cpu_to_le64(cons_rx_buf
->mapping
);
650 prod_bd
->rx_bd_opaque
= sw_prod
;
652 prod
= NEXT_RX_AGG(prod
);
653 sw_prod
= NEXT_RX_AGG(sw_prod
);
654 cp_cons
= NEXT_CMP(cp_cons
);
656 rxr
->rx_agg_prod
= prod
;
657 rxr
->rx_sw_agg_prod
= sw_prod
;
660 static struct sk_buff
*bnxt_rx_skb(struct bnxt
*bp
,
661 struct bnxt_rx_ring_info
*rxr
, u16 cons
,
662 u16 prod
, u8
*data
, dma_addr_t dma_addr
,
668 err
= bnxt_alloc_rx_data(bp
, rxr
, prod
, GFP_ATOMIC
);
670 bnxt_reuse_rx_data(rxr
, cons
, data
);
674 skb
= build_skb(data
, 0);
675 dma_unmap_single(&bp
->pdev
->dev
, dma_addr
, bp
->rx_buf_use_size
,
682 skb_reserve(skb
, BNXT_RX_OFFSET
);
687 static struct sk_buff
*bnxt_rx_pages(struct bnxt
*bp
, struct bnxt_napi
*bnapi
,
688 struct sk_buff
*skb
, u16 cp_cons
,
691 struct pci_dev
*pdev
= bp
->pdev
;
692 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
693 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
694 u16 prod
= rxr
->rx_agg_prod
;
697 for (i
= 0; i
< agg_bufs
; i
++) {
699 struct rx_agg_cmp
*agg
;
700 struct bnxt_sw_rx_agg_bd
*cons_rx_buf
;
704 agg
= (struct rx_agg_cmp
*)
705 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
706 cons
= agg
->rx_agg_cmp_opaque
;
707 frag_len
= (le32_to_cpu(agg
->rx_agg_cmp_len_flags_type
) &
708 RX_AGG_CMP_LEN
) >> RX_AGG_CMP_LEN_SHIFT
;
710 cons_rx_buf
= &rxr
->rx_agg_ring
[cons
];
711 skb_fill_page_desc(skb
, i
, cons_rx_buf
->page
, 0, frag_len
);
712 __clear_bit(cons
, rxr
->rx_agg_bmap
);
714 /* It is possible for bnxt_alloc_rx_page() to allocate
715 * a sw_prod index that equals the cons index, so we
716 * need to clear the cons entry now.
718 mapping
= dma_unmap_addr(cons_rx_buf
, mapping
);
719 page
= cons_rx_buf
->page
;
720 cons_rx_buf
->page
= NULL
;
722 if (bnxt_alloc_rx_page(bp
, rxr
, prod
, GFP_ATOMIC
) != 0) {
723 struct skb_shared_info
*shinfo
;
724 unsigned int nr_frags
;
726 shinfo
= skb_shinfo(skb
);
727 nr_frags
= --shinfo
->nr_frags
;
728 __skb_frag_set_page(&shinfo
->frags
[nr_frags
], NULL
);
732 cons_rx_buf
->page
= page
;
734 /* Update prod since possibly some pages have been
737 rxr
->rx_agg_prod
= prod
;
738 bnxt_reuse_rx_agg_bufs(bnapi
, cp_cons
, agg_bufs
- i
);
742 dma_unmap_page(&pdev
->dev
, mapping
, PAGE_SIZE
,
745 skb
->data_len
+= frag_len
;
746 skb
->len
+= frag_len
;
747 skb
->truesize
+= PAGE_SIZE
;
749 prod
= NEXT_RX_AGG(prod
);
750 cp_cons
= NEXT_CMP(cp_cons
);
752 rxr
->rx_agg_prod
= prod
;
756 static int bnxt_agg_bufs_valid(struct bnxt
*bp
, struct bnxt_cp_ring_info
*cpr
,
757 u8 agg_bufs
, u32
*raw_cons
)
760 struct rx_agg_cmp
*agg
;
762 *raw_cons
= ADV_RAW_CMP(*raw_cons
, agg_bufs
);
763 last
= RING_CMP(*raw_cons
);
764 agg
= (struct rx_agg_cmp
*)
765 &cpr
->cp_desc_ring
[CP_RING(last
)][CP_IDX(last
)];
766 return RX_AGG_CMP_VALID(agg
, *raw_cons
);
769 static inline struct sk_buff
*bnxt_copy_skb(struct bnxt_napi
*bnapi
, u8
*data
,
773 struct bnxt
*bp
= bnapi
->bp
;
774 struct pci_dev
*pdev
= bp
->pdev
;
777 skb
= napi_alloc_skb(&bnapi
->napi
, len
);
781 dma_sync_single_for_cpu(&pdev
->dev
, mapping
,
782 bp
->rx_copy_thresh
, PCI_DMA_FROMDEVICE
);
784 memcpy(skb
->data
- BNXT_RX_OFFSET
, data
, len
+ BNXT_RX_OFFSET
);
786 dma_sync_single_for_device(&pdev
->dev
, mapping
,
794 static void bnxt_tpa_start(struct bnxt
*bp
, struct bnxt_rx_ring_info
*rxr
,
795 struct rx_tpa_start_cmp
*tpa_start
,
796 struct rx_tpa_start_cmp_ext
*tpa_start1
)
798 u8 agg_id
= TPA_START_AGG_ID(tpa_start
);
800 struct bnxt_tpa_info
*tpa_info
;
801 struct bnxt_sw_rx_bd
*cons_rx_buf
, *prod_rx_buf
;
802 struct rx_bd
*prod_bd
;
805 cons
= tpa_start
->rx_tpa_start_cmp_opaque
;
807 cons_rx_buf
= &rxr
->rx_buf_ring
[cons
];
808 prod_rx_buf
= &rxr
->rx_buf_ring
[prod
];
809 tpa_info
= &rxr
->rx_tpa
[agg_id
];
811 prod_rx_buf
->data
= tpa_info
->data
;
813 mapping
= tpa_info
->mapping
;
814 dma_unmap_addr_set(prod_rx_buf
, mapping
, mapping
);
816 prod_bd
= &rxr
->rx_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
818 prod_bd
->rx_bd_haddr
= cpu_to_le64(mapping
);
820 tpa_info
->data
= cons_rx_buf
->data
;
821 cons_rx_buf
->data
= NULL
;
822 tpa_info
->mapping
= dma_unmap_addr(cons_rx_buf
, mapping
);
825 le32_to_cpu(tpa_start
->rx_tpa_start_cmp_len_flags_type
) >>
826 RX_TPA_START_CMP_LEN_SHIFT
;
827 if (likely(TPA_START_HASH_VALID(tpa_start
))) {
828 u32 hash_type
= TPA_START_HASH_TYPE(tpa_start
);
830 tpa_info
->hash_type
= PKT_HASH_TYPE_L4
;
831 tpa_info
->gso_type
= SKB_GSO_TCPV4
;
832 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
834 tpa_info
->gso_type
= SKB_GSO_TCPV6
;
836 le32_to_cpu(tpa_start
->rx_tpa_start_cmp_rss_hash
);
838 tpa_info
->hash_type
= PKT_HASH_TYPE_NONE
;
839 tpa_info
->gso_type
= 0;
840 if (netif_msg_rx_err(bp
))
841 netdev_warn(bp
->dev
, "TPA packet without valid hash\n");
843 tpa_info
->flags2
= le32_to_cpu(tpa_start1
->rx_tpa_start_cmp_flags2
);
844 tpa_info
->metadata
= le32_to_cpu(tpa_start1
->rx_tpa_start_cmp_metadata
);
846 rxr
->rx_prod
= NEXT_RX(prod
);
847 cons
= NEXT_RX(cons
);
848 cons_rx_buf
= &rxr
->rx_buf_ring
[cons
];
850 bnxt_reuse_rx_data(rxr
, cons
, cons_rx_buf
->data
);
851 rxr
->rx_prod
= NEXT_RX(rxr
->rx_prod
);
852 cons_rx_buf
->data
= NULL
;
855 static void bnxt_abort_tpa(struct bnxt
*bp
, struct bnxt_napi
*bnapi
,
856 u16 cp_cons
, u32 agg_bufs
)
859 bnxt_reuse_rx_agg_bufs(bnapi
, cp_cons
, agg_bufs
);
862 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
863 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
865 static inline struct sk_buff
*bnxt_gro_skb(struct bnxt_tpa_info
*tpa_info
,
866 struct rx_tpa_end_cmp
*tpa_end
,
867 struct rx_tpa_end_cmp_ext
*tpa_end1
,
872 int payload_off
, tcp_opt_len
= 0;
876 segs
= TPA_END_TPA_SEGS(tpa_end
);
880 NAPI_GRO_CB(skb
)->count
= segs
;
881 skb_shinfo(skb
)->gso_size
=
882 le32_to_cpu(tpa_end1
->rx_tpa_end_cmp_seg_len
);
883 skb_shinfo(skb
)->gso_type
= tpa_info
->gso_type
;
884 payload_off
= (le32_to_cpu(tpa_end
->rx_tpa_end_cmp_misc_v1
) &
885 RX_TPA_END_CMP_PAYLOAD_OFFSET
) >>
886 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT
;
887 if (TPA_END_GRO_TS(tpa_end
))
890 if (tpa_info
->gso_type
== SKB_GSO_TCPV4
) {
893 nw_off
= payload_off
- BNXT_IPV4_HDR_SIZE
- tcp_opt_len
-
895 skb_set_network_header(skb
, nw_off
);
897 skb_set_transport_header(skb
, nw_off
+ sizeof(struct iphdr
));
898 len
= skb
->len
- skb_transport_offset(skb
);
900 th
->check
= ~tcp_v4_check(len
, iph
->saddr
, iph
->daddr
, 0);
901 } else if (tpa_info
->gso_type
== SKB_GSO_TCPV6
) {
904 nw_off
= payload_off
- BNXT_IPV6_HDR_SIZE
- tcp_opt_len
-
906 skb_set_network_header(skb
, nw_off
);
908 skb_set_transport_header(skb
, nw_off
+ sizeof(struct ipv6hdr
));
909 len
= skb
->len
- skb_transport_offset(skb
);
911 th
->check
= ~tcp_v6_check(len
, &iph
->saddr
, &iph
->daddr
, 0);
913 dev_kfree_skb_any(skb
);
916 tcp_gro_complete(skb
);
918 if (nw_off
) { /* tunnel */
919 struct udphdr
*uh
= NULL
;
921 if (skb
->protocol
== htons(ETH_P_IP
)) {
922 struct iphdr
*iph
= (struct iphdr
*)skb
->data
;
924 if (iph
->protocol
== IPPROTO_UDP
)
925 uh
= (struct udphdr
*)(iph
+ 1);
927 struct ipv6hdr
*iph
= (struct ipv6hdr
*)skb
->data
;
929 if (iph
->nexthdr
== IPPROTO_UDP
)
930 uh
= (struct udphdr
*)(iph
+ 1);
934 skb_shinfo(skb
)->gso_type
|=
935 SKB_GSO_UDP_TUNNEL_CSUM
;
937 skb_shinfo(skb
)->gso_type
|= SKB_GSO_UDP_TUNNEL
;
944 static inline struct sk_buff
*bnxt_tpa_end(struct bnxt
*bp
,
945 struct bnxt_napi
*bnapi
,
947 struct rx_tpa_end_cmp
*tpa_end
,
948 struct rx_tpa_end_cmp_ext
*tpa_end1
,
951 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
952 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
953 u8 agg_id
= TPA_END_AGG_ID(tpa_end
);
955 u16 cp_cons
= RING_CMP(*raw_cons
);
957 struct bnxt_tpa_info
*tpa_info
;
961 tpa_info
= &rxr
->rx_tpa
[agg_id
];
962 data
= tpa_info
->data
;
965 mapping
= tpa_info
->mapping
;
967 agg_bufs
= (le32_to_cpu(tpa_end
->rx_tpa_end_cmp_misc_v1
) &
968 RX_TPA_END_CMP_AGG_BUFS
) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT
;
971 if (!bnxt_agg_bufs_valid(bp
, cpr
, agg_bufs
, raw_cons
))
972 return ERR_PTR(-EBUSY
);
975 cp_cons
= NEXT_CMP(cp_cons
);
978 if (unlikely(agg_bufs
> MAX_SKB_FRAGS
)) {
979 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
980 netdev_warn(bp
->dev
, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
981 agg_bufs
, (int)MAX_SKB_FRAGS
);
985 if (len
<= bp
->rx_copy_thresh
) {
986 skb
= bnxt_copy_skb(bnapi
, data
, len
, mapping
);
988 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
993 dma_addr_t new_mapping
;
995 new_data
= __bnxt_alloc_rx_data(bp
, &new_mapping
, GFP_ATOMIC
);
997 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
1001 tpa_info
->data
= new_data
;
1002 tpa_info
->mapping
= new_mapping
;
1004 skb
= build_skb(data
, 0);
1005 dma_unmap_single(&bp
->pdev
->dev
, mapping
, bp
->rx_buf_use_size
,
1006 PCI_DMA_FROMDEVICE
);
1010 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
1013 skb_reserve(skb
, BNXT_RX_OFFSET
);
1018 skb
= bnxt_rx_pages(bp
, bnapi
, skb
, cp_cons
, agg_bufs
);
1020 /* Page reuse already handled by bnxt_rx_pages(). */
1024 skb
->protocol
= eth_type_trans(skb
, bp
->dev
);
1026 if (tpa_info
->hash_type
!= PKT_HASH_TYPE_NONE
)
1027 skb_set_hash(skb
, tpa_info
->rss_hash
, tpa_info
->hash_type
);
1029 if (tpa_info
->flags2
& RX_CMP_FLAGS2_META_FORMAT_VLAN
) {
1030 netdev_features_t features
= skb
->dev
->features
;
1031 u16 vlan_proto
= tpa_info
->metadata
>>
1032 RX_CMP_FLAGS2_METADATA_TPID_SFT
;
1034 if (((features
& NETIF_F_HW_VLAN_CTAG_RX
) &&
1035 vlan_proto
== ETH_P_8021Q
) ||
1036 ((features
& NETIF_F_HW_VLAN_STAG_RX
) &&
1037 vlan_proto
== ETH_P_8021AD
)) {
1038 __vlan_hwaccel_put_tag(skb
, htons(vlan_proto
),
1039 tpa_info
->metadata
&
1040 RX_CMP_FLAGS2_METADATA_VID_MASK
);
1044 skb_checksum_none_assert(skb
);
1045 if (likely(tpa_info
->flags2
& RX_TPA_START_CMP_FLAGS2_L4_CS_CALC
)) {
1046 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1048 (tpa_info
->flags2
& RX_CMP_FLAGS2_T_L4_CS_CALC
) >> 3;
1051 if (TPA_END_GRO(tpa_end
))
1052 skb
= bnxt_gro_skb(tpa_info
, tpa_end
, tpa_end1
, skb
);
1057 /* returns the following:
1058 * 1 - 1 packet successfully received
1059 * 0 - successful TPA_START, packet not completed yet
1060 * -EBUSY - completion ring does not have all the agg buffers yet
1061 * -ENOMEM - packet aborted due to out of memory
1062 * -EIO - packet aborted due to hw error indicated in BD
1064 static int bnxt_rx_pkt(struct bnxt
*bp
, struct bnxt_napi
*bnapi
, u32
*raw_cons
,
1067 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1068 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
1069 struct net_device
*dev
= bp
->dev
;
1070 struct rx_cmp
*rxcmp
;
1071 struct rx_cmp_ext
*rxcmp1
;
1072 u32 tmp_raw_cons
= *raw_cons
;
1073 u16 cons
, prod
, cp_cons
= RING_CMP(tmp_raw_cons
);
1074 struct bnxt_sw_rx_bd
*rx_buf
;
1076 u8
*data
, agg_bufs
, cmp_type
;
1077 dma_addr_t dma_addr
;
1078 struct sk_buff
*skb
;
1081 rxcmp
= (struct rx_cmp
*)
1082 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
1084 tmp_raw_cons
= NEXT_RAW_CMP(tmp_raw_cons
);
1085 cp_cons
= RING_CMP(tmp_raw_cons
);
1086 rxcmp1
= (struct rx_cmp_ext
*)
1087 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
1089 if (!RX_CMP_VALID(rxcmp1
, tmp_raw_cons
))
1092 cmp_type
= RX_CMP_TYPE(rxcmp
);
1094 prod
= rxr
->rx_prod
;
1096 if (cmp_type
== CMP_TYPE_RX_L2_TPA_START_CMP
) {
1097 bnxt_tpa_start(bp
, rxr
, (struct rx_tpa_start_cmp
*)rxcmp
,
1098 (struct rx_tpa_start_cmp_ext
*)rxcmp1
);
1100 goto next_rx_no_prod
;
1102 } else if (cmp_type
== CMP_TYPE_RX_L2_TPA_END_CMP
) {
1103 skb
= bnxt_tpa_end(bp
, bnapi
, &tmp_raw_cons
,
1104 (struct rx_tpa_end_cmp
*)rxcmp
,
1105 (struct rx_tpa_end_cmp_ext
*)rxcmp1
,
1108 if (unlikely(IS_ERR(skb
)))
1113 skb_record_rx_queue(skb
, bnapi
->index
);
1114 skb_mark_napi_id(skb
, &bnapi
->napi
);
1115 if (bnxt_busy_polling(bnapi
))
1116 netif_receive_skb(skb
);
1118 napi_gro_receive(&bnapi
->napi
, skb
);
1121 goto next_rx_no_prod
;
1124 cons
= rxcmp
->rx_cmp_opaque
;
1125 rx_buf
= &rxr
->rx_buf_ring
[cons
];
1126 data
= rx_buf
->data
;
1129 agg_bufs
= (le32_to_cpu(rxcmp
->rx_cmp_misc_v1
) & RX_CMP_AGG_BUFS
) >>
1130 RX_CMP_AGG_BUFS_SHIFT
;
1133 if (!bnxt_agg_bufs_valid(bp
, cpr
, agg_bufs
, &tmp_raw_cons
))
1136 cp_cons
= NEXT_CMP(cp_cons
);
1140 rx_buf
->data
= NULL
;
1141 if (rxcmp1
->rx_cmp_cfa_code_errors_v2
& RX_CMP_L2_ERRORS
) {
1142 bnxt_reuse_rx_data(rxr
, cons
, data
);
1144 bnxt_reuse_rx_agg_bufs(bnapi
, cp_cons
, agg_bufs
);
1150 len
= le32_to_cpu(rxcmp
->rx_cmp_len_flags_type
) >> RX_CMP_LEN_SHIFT
;
1151 dma_addr
= dma_unmap_addr(rx_buf
, mapping
);
1153 if (len
<= bp
->rx_copy_thresh
) {
1154 skb
= bnxt_copy_skb(bnapi
, data
, len
, dma_addr
);
1155 bnxt_reuse_rx_data(rxr
, cons
, data
);
1161 skb
= bnxt_rx_skb(bp
, rxr
, cons
, prod
, data
, dma_addr
, len
);
1169 skb
= bnxt_rx_pages(bp
, bnapi
, skb
, cp_cons
, agg_bufs
);
1176 if (RX_CMP_HASH_VALID(rxcmp
)) {
1177 u32 hash_type
= RX_CMP_HASH_TYPE(rxcmp
);
1178 enum pkt_hash_types type
= PKT_HASH_TYPE_L4
;
1180 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1181 if (hash_type
!= 1 && hash_type
!= 3)
1182 type
= PKT_HASH_TYPE_L3
;
1183 skb_set_hash(skb
, le32_to_cpu(rxcmp
->rx_cmp_rss_hash
), type
);
1186 skb
->protocol
= eth_type_trans(skb
, dev
);
1188 if (rxcmp1
->rx_cmp_flags2
&
1189 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN
)) {
1190 netdev_features_t features
= skb
->dev
->features
;
1191 u32 meta_data
= le32_to_cpu(rxcmp1
->rx_cmp_meta_data
);
1192 u16 vlan_proto
= meta_data
>> RX_CMP_FLAGS2_METADATA_TPID_SFT
;
1194 if (((features
& NETIF_F_HW_VLAN_CTAG_RX
) &&
1195 vlan_proto
== ETH_P_8021Q
) ||
1196 ((features
& NETIF_F_HW_VLAN_STAG_RX
) &&
1197 vlan_proto
== ETH_P_8021AD
))
1198 __vlan_hwaccel_put_tag(skb
, htons(vlan_proto
),
1200 RX_CMP_FLAGS2_METADATA_VID_MASK
);
1203 skb_checksum_none_assert(skb
);
1204 if (RX_CMP_L4_CS_OK(rxcmp1
)) {
1205 if (dev
->features
& NETIF_F_RXCSUM
) {
1206 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1207 skb
->csum_level
= RX_CMP_ENCAP(rxcmp1
);
1210 if (rxcmp1
->rx_cmp_cfa_code_errors_v2
& RX_CMP_L4_CS_ERR_BITS
) {
1211 if (dev
->features
& NETIF_F_RXCSUM
)
1212 cpr
->rx_l4_csum_errors
++;
1216 skb_record_rx_queue(skb
, bnapi
->index
);
1217 skb_mark_napi_id(skb
, &bnapi
->napi
);
1218 if (bnxt_busy_polling(bnapi
))
1219 netif_receive_skb(skb
);
1221 napi_gro_receive(&bnapi
->napi
, skb
);
1225 rxr
->rx_prod
= NEXT_RX(prod
);
1228 *raw_cons
= tmp_raw_cons
;
1233 static int bnxt_async_event_process(struct bnxt
*bp
,
1234 struct hwrm_async_event_cmpl
*cmpl
)
1236 u16 event_id
= le16_to_cpu(cmpl
->event_id
);
1238 /* TODO CHIMP_FW: Define event id's for link change, error etc */
1240 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE
:
1241 set_bit(BNXT_LINK_CHNG_SP_EVENT
, &bp
->sp_event
);
1243 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD
:
1244 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT
, &bp
->sp_event
);
1247 netdev_err(bp
->dev
, "unhandled ASYNC event (id 0x%x)\n",
1249 goto async_event_process_exit
;
1251 schedule_work(&bp
->sp_task
);
1252 async_event_process_exit
:
1256 static int bnxt_hwrm_handler(struct bnxt
*bp
, struct tx_cmp
*txcmp
)
1258 u16 cmpl_type
= TX_CMP_TYPE(txcmp
), vf_id
, seq_id
;
1259 struct hwrm_cmpl
*h_cmpl
= (struct hwrm_cmpl
*)txcmp
;
1260 struct hwrm_fwd_req_cmpl
*fwd_req_cmpl
=
1261 (struct hwrm_fwd_req_cmpl
*)txcmp
;
1263 switch (cmpl_type
) {
1264 case CMPL_BASE_TYPE_HWRM_DONE
:
1265 seq_id
= le16_to_cpu(h_cmpl
->sequence_id
);
1266 if (seq_id
== bp
->hwrm_intr_seq_id
)
1267 bp
->hwrm_intr_seq_id
= HWRM_SEQ_ID_INVALID
;
1269 netdev_err(bp
->dev
, "Invalid hwrm seq id %d\n", seq_id
);
1272 case CMPL_BASE_TYPE_HWRM_FWD_REQ
:
1273 vf_id
= le16_to_cpu(fwd_req_cmpl
->source_id
);
1275 if ((vf_id
< bp
->pf
.first_vf_id
) ||
1276 (vf_id
>= bp
->pf
.first_vf_id
+ bp
->pf
.active_vfs
)) {
1277 netdev_err(bp
->dev
, "Msg contains invalid VF id %x\n",
1282 set_bit(vf_id
- bp
->pf
.first_vf_id
, bp
->pf
.vf_event_bmap
);
1283 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT
, &bp
->sp_event
);
1284 schedule_work(&bp
->sp_task
);
1287 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT
:
1288 bnxt_async_event_process(bp
,
1289 (struct hwrm_async_event_cmpl
*)txcmp
);
1298 static irqreturn_t
bnxt_msix(int irq
, void *dev_instance
)
1300 struct bnxt_napi
*bnapi
= dev_instance
;
1301 struct bnxt
*bp
= bnapi
->bp
;
1302 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1303 u32 cons
= RING_CMP(cpr
->cp_raw_cons
);
1305 prefetch(&cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)]);
1306 napi_schedule(&bnapi
->napi
);
1310 static inline int bnxt_has_work(struct bnxt
*bp
, struct bnxt_cp_ring_info
*cpr
)
1312 u32 raw_cons
= cpr
->cp_raw_cons
;
1313 u16 cons
= RING_CMP(raw_cons
);
1314 struct tx_cmp
*txcmp
;
1316 txcmp
= &cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)];
1318 return TX_CMP_VALID(txcmp
, raw_cons
);
1321 static irqreturn_t
bnxt_inta(int irq
, void *dev_instance
)
1323 struct bnxt_napi
*bnapi
= dev_instance
;
1324 struct bnxt
*bp
= bnapi
->bp
;
1325 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1326 u32 cons
= RING_CMP(cpr
->cp_raw_cons
);
1329 prefetch(&cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)]);
1331 if (!bnxt_has_work(bp
, cpr
)) {
1332 int_status
= readl(bp
->bar0
+ BNXT_CAG_REG_LEGACY_INT_STATUS
);
1333 /* return if erroneous interrupt */
1334 if (!(int_status
& (0x10000 << cpr
->cp_ring_struct
.fw_ring_id
)))
1338 /* disable ring IRQ */
1339 BNXT_CP_DB_IRQ_DIS(cpr
->cp_doorbell
);
1341 /* Return here if interrupt is shared and is disabled. */
1342 if (unlikely(atomic_read(&bp
->intr_sem
) != 0))
1345 napi_schedule(&bnapi
->napi
);
1349 static int bnxt_poll_work(struct bnxt
*bp
, struct bnxt_napi
*bnapi
, int budget
)
1351 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1352 u32 raw_cons
= cpr
->cp_raw_cons
;
1356 bool rx_event
= false;
1357 bool agg_event
= false;
1358 struct tx_cmp
*txcmp
;
1363 cons
= RING_CMP(raw_cons
);
1364 txcmp
= &cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)];
1366 if (!TX_CMP_VALID(txcmp
, raw_cons
))
1369 if (TX_CMP_TYPE(txcmp
) == CMP_TYPE_TX_L2_CMP
) {
1371 /* return full budget so NAPI will complete. */
1372 if (unlikely(tx_pkts
> bp
->tx_wake_thresh
))
1374 } else if ((TX_CMP_TYPE(txcmp
) & 0x30) == 0x10) {
1375 rc
= bnxt_rx_pkt(bp
, bnapi
, &raw_cons
, &agg_event
);
1376 if (likely(rc
>= 0))
1378 else if (rc
== -EBUSY
) /* partial completion */
1381 } else if (unlikely((TX_CMP_TYPE(txcmp
) ==
1382 CMPL_BASE_TYPE_HWRM_DONE
) ||
1383 (TX_CMP_TYPE(txcmp
) ==
1384 CMPL_BASE_TYPE_HWRM_FWD_REQ
) ||
1385 (TX_CMP_TYPE(txcmp
) ==
1386 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT
))) {
1387 bnxt_hwrm_handler(bp
, txcmp
);
1389 raw_cons
= NEXT_RAW_CMP(raw_cons
);
1391 if (rx_pkts
== budget
)
1395 cpr
->cp_raw_cons
= raw_cons
;
1396 /* ACK completion ring before freeing tx ring and producing new
1397 * buffers in rx/agg rings to prevent overflowing the completion
1400 BNXT_CP_DB(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
1403 bnxt_tx_int(bp
, bnapi
, tx_pkts
);
1406 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
1408 writel(DB_KEY_RX
| rxr
->rx_prod
, rxr
->rx_doorbell
);
1409 writel(DB_KEY_RX
| rxr
->rx_prod
, rxr
->rx_doorbell
);
1411 writel(DB_KEY_RX
| rxr
->rx_agg_prod
,
1412 rxr
->rx_agg_doorbell
);
1413 writel(DB_KEY_RX
| rxr
->rx_agg_prod
,
1414 rxr
->rx_agg_doorbell
);
1420 static int bnxt_poll(struct napi_struct
*napi
, int budget
)
1422 struct bnxt_napi
*bnapi
= container_of(napi
, struct bnxt_napi
, napi
);
1423 struct bnxt
*bp
= bnapi
->bp
;
1424 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1427 if (!bnxt_lock_napi(bnapi
))
1431 work_done
+= bnxt_poll_work(bp
, bnapi
, budget
- work_done
);
1433 if (work_done
>= budget
)
1436 if (!bnxt_has_work(bp
, cpr
)) {
1437 napi_complete(napi
);
1438 BNXT_CP_DB_REARM(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
1443 bnxt_unlock_napi(bnapi
);
1447 #ifdef CONFIG_NET_RX_BUSY_POLL
1448 static int bnxt_busy_poll(struct napi_struct
*napi
)
1450 struct bnxt_napi
*bnapi
= container_of(napi
, struct bnxt_napi
, napi
);
1451 struct bnxt
*bp
= bnapi
->bp
;
1452 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1453 int rx_work
, budget
= 4;
1455 if (atomic_read(&bp
->intr_sem
) != 0)
1456 return LL_FLUSH_FAILED
;
1458 if (!bnxt_lock_poll(bnapi
))
1459 return LL_FLUSH_BUSY
;
1461 rx_work
= bnxt_poll_work(bp
, bnapi
, budget
);
1463 BNXT_CP_DB_REARM(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
1465 bnxt_unlock_poll(bnapi
);
1470 static void bnxt_free_tx_skbs(struct bnxt
*bp
)
1473 struct pci_dev
*pdev
= bp
->pdev
;
1478 max_idx
= bp
->tx_nr_pages
* TX_DESC_CNT
;
1479 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
1480 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
1483 for (j
= 0; j
< max_idx
;) {
1484 struct bnxt_sw_tx_bd
*tx_buf
= &txr
->tx_buf_ring
[j
];
1485 struct sk_buff
*skb
= tx_buf
->skb
;
1495 if (tx_buf
->is_push
) {
1501 dma_unmap_single(&pdev
->dev
,
1502 dma_unmap_addr(tx_buf
, mapping
),
1506 last
= tx_buf
->nr_frags
;
1508 for (k
= 0; k
< last
; k
++, j
++) {
1509 int ring_idx
= j
& bp
->tx_ring_mask
;
1510 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[k
];
1512 tx_buf
= &txr
->tx_buf_ring
[ring_idx
];
1515 dma_unmap_addr(tx_buf
, mapping
),
1516 skb_frag_size(frag
), PCI_DMA_TODEVICE
);
1520 netdev_tx_reset_queue(netdev_get_tx_queue(bp
->dev
, i
));
1524 static void bnxt_free_rx_skbs(struct bnxt
*bp
)
1526 int i
, max_idx
, max_agg_idx
;
1527 struct pci_dev
*pdev
= bp
->pdev
;
1532 max_idx
= bp
->rx_nr_pages
* RX_DESC_CNT
;
1533 max_agg_idx
= bp
->rx_agg_nr_pages
* RX_DESC_CNT
;
1534 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
1535 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
1539 for (j
= 0; j
< MAX_TPA
; j
++) {
1540 struct bnxt_tpa_info
*tpa_info
=
1542 u8
*data
= tpa_info
->data
;
1549 dma_unmap_addr(tpa_info
, mapping
),
1550 bp
->rx_buf_use_size
,
1551 PCI_DMA_FROMDEVICE
);
1553 tpa_info
->data
= NULL
;
1559 for (j
= 0; j
< max_idx
; j
++) {
1560 struct bnxt_sw_rx_bd
*rx_buf
= &rxr
->rx_buf_ring
[j
];
1561 u8
*data
= rx_buf
->data
;
1566 dma_unmap_single(&pdev
->dev
,
1567 dma_unmap_addr(rx_buf
, mapping
),
1568 bp
->rx_buf_use_size
,
1569 PCI_DMA_FROMDEVICE
);
1571 rx_buf
->data
= NULL
;
1576 for (j
= 0; j
< max_agg_idx
; j
++) {
1577 struct bnxt_sw_rx_agg_bd
*rx_agg_buf
=
1578 &rxr
->rx_agg_ring
[j
];
1579 struct page
*page
= rx_agg_buf
->page
;
1584 dma_unmap_page(&pdev
->dev
,
1585 dma_unmap_addr(rx_agg_buf
, mapping
),
1586 PAGE_SIZE
, PCI_DMA_FROMDEVICE
);
1588 rx_agg_buf
->page
= NULL
;
1589 __clear_bit(j
, rxr
->rx_agg_bmap
);
1596 static void bnxt_free_skbs(struct bnxt
*bp
)
1598 bnxt_free_tx_skbs(bp
);
1599 bnxt_free_rx_skbs(bp
);
1602 static void bnxt_free_ring(struct bnxt
*bp
, struct bnxt_ring_struct
*ring
)
1604 struct pci_dev
*pdev
= bp
->pdev
;
1607 for (i
= 0; i
< ring
->nr_pages
; i
++) {
1608 if (!ring
->pg_arr
[i
])
1611 dma_free_coherent(&pdev
->dev
, ring
->page_size
,
1612 ring
->pg_arr
[i
], ring
->dma_arr
[i
]);
1614 ring
->pg_arr
[i
] = NULL
;
1617 dma_free_coherent(&pdev
->dev
, ring
->nr_pages
* 8,
1618 ring
->pg_tbl
, ring
->pg_tbl_map
);
1619 ring
->pg_tbl
= NULL
;
1621 if (ring
->vmem_size
&& *ring
->vmem
) {
1627 static int bnxt_alloc_ring(struct bnxt
*bp
, struct bnxt_ring_struct
*ring
)
1630 struct pci_dev
*pdev
= bp
->pdev
;
1632 if (ring
->nr_pages
> 1) {
1633 ring
->pg_tbl
= dma_alloc_coherent(&pdev
->dev
,
1641 for (i
= 0; i
< ring
->nr_pages
; i
++) {
1642 ring
->pg_arr
[i
] = dma_alloc_coherent(&pdev
->dev
,
1646 if (!ring
->pg_arr
[i
])
1649 if (ring
->nr_pages
> 1)
1650 ring
->pg_tbl
[i
] = cpu_to_le64(ring
->dma_arr
[i
]);
1653 if (ring
->vmem_size
) {
1654 *ring
->vmem
= vzalloc(ring
->vmem_size
);
1661 static void bnxt_free_rx_rings(struct bnxt
*bp
)
1668 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
1669 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
1670 struct bnxt_ring_struct
*ring
;
1675 kfree(rxr
->rx_agg_bmap
);
1676 rxr
->rx_agg_bmap
= NULL
;
1678 ring
= &rxr
->rx_ring_struct
;
1679 bnxt_free_ring(bp
, ring
);
1681 ring
= &rxr
->rx_agg_ring_struct
;
1682 bnxt_free_ring(bp
, ring
);
1686 static int bnxt_alloc_rx_rings(struct bnxt
*bp
)
1688 int i
, rc
, agg_rings
= 0, tpa_rings
= 0;
1693 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
)
1696 if (bp
->flags
& BNXT_FLAG_TPA
)
1699 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
1700 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
1701 struct bnxt_ring_struct
*ring
;
1703 ring
= &rxr
->rx_ring_struct
;
1705 rc
= bnxt_alloc_ring(bp
, ring
);
1712 ring
= &rxr
->rx_agg_ring_struct
;
1713 rc
= bnxt_alloc_ring(bp
, ring
);
1717 rxr
->rx_agg_bmap_size
= bp
->rx_agg_ring_mask
+ 1;
1718 mem_size
= rxr
->rx_agg_bmap_size
/ 8;
1719 rxr
->rx_agg_bmap
= kzalloc(mem_size
, GFP_KERNEL
);
1720 if (!rxr
->rx_agg_bmap
)
1724 rxr
->rx_tpa
= kcalloc(MAX_TPA
,
1725 sizeof(struct bnxt_tpa_info
),
1735 static void bnxt_free_tx_rings(struct bnxt
*bp
)
1738 struct pci_dev
*pdev
= bp
->pdev
;
1743 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
1744 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
1745 struct bnxt_ring_struct
*ring
;
1748 dma_free_coherent(&pdev
->dev
, bp
->tx_push_size
,
1749 txr
->tx_push
, txr
->tx_push_mapping
);
1750 txr
->tx_push
= NULL
;
1753 ring
= &txr
->tx_ring_struct
;
1755 bnxt_free_ring(bp
, ring
);
1759 static int bnxt_alloc_tx_rings(struct bnxt
*bp
)
1762 struct pci_dev
*pdev
= bp
->pdev
;
1764 bp
->tx_push_size
= 0;
1765 if (bp
->tx_push_thresh
) {
1768 push_size
= L1_CACHE_ALIGN(sizeof(struct tx_push_bd
) +
1769 bp
->tx_push_thresh
);
1771 if (push_size
> 256) {
1773 bp
->tx_push_thresh
= 0;
1776 bp
->tx_push_size
= push_size
;
1779 for (i
= 0, j
= 0; i
< bp
->tx_nr_rings
; i
++) {
1780 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
1781 struct bnxt_ring_struct
*ring
;
1783 ring
= &txr
->tx_ring_struct
;
1785 rc
= bnxt_alloc_ring(bp
, ring
);
1789 if (bp
->tx_push_size
) {
1792 /* One pre-allocated DMA buffer to backup
1795 txr
->tx_push
= dma_alloc_coherent(&pdev
->dev
,
1797 &txr
->tx_push_mapping
,
1803 mapping
= txr
->tx_push_mapping
+
1804 sizeof(struct tx_push_bd
);
1805 txr
->data_mapping
= cpu_to_le64(mapping
);
1807 memset(txr
->tx_push
, 0, sizeof(struct tx_push_bd
));
1809 ring
->queue_id
= bp
->q_info
[j
].queue_id
;
1810 if (i
% bp
->tx_nr_rings_per_tc
== (bp
->tx_nr_rings_per_tc
- 1))
1816 static void bnxt_free_cp_rings(struct bnxt
*bp
)
1823 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
1824 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
1825 struct bnxt_cp_ring_info
*cpr
;
1826 struct bnxt_ring_struct
*ring
;
1831 cpr
= &bnapi
->cp_ring
;
1832 ring
= &cpr
->cp_ring_struct
;
1834 bnxt_free_ring(bp
, ring
);
1838 static int bnxt_alloc_cp_rings(struct bnxt
*bp
)
1842 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
1843 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
1844 struct bnxt_cp_ring_info
*cpr
;
1845 struct bnxt_ring_struct
*ring
;
1850 cpr
= &bnapi
->cp_ring
;
1851 ring
= &cpr
->cp_ring_struct
;
1853 rc
= bnxt_alloc_ring(bp
, ring
);
1860 static void bnxt_init_ring_struct(struct bnxt
*bp
)
1864 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
1865 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
1866 struct bnxt_cp_ring_info
*cpr
;
1867 struct bnxt_rx_ring_info
*rxr
;
1868 struct bnxt_tx_ring_info
*txr
;
1869 struct bnxt_ring_struct
*ring
;
1874 cpr
= &bnapi
->cp_ring
;
1875 ring
= &cpr
->cp_ring_struct
;
1876 ring
->nr_pages
= bp
->cp_nr_pages
;
1877 ring
->page_size
= HW_CMPD_RING_SIZE
;
1878 ring
->pg_arr
= (void **)cpr
->cp_desc_ring
;
1879 ring
->dma_arr
= cpr
->cp_desc_mapping
;
1880 ring
->vmem_size
= 0;
1882 rxr
= bnapi
->rx_ring
;
1886 ring
= &rxr
->rx_ring_struct
;
1887 ring
->nr_pages
= bp
->rx_nr_pages
;
1888 ring
->page_size
= HW_RXBD_RING_SIZE
;
1889 ring
->pg_arr
= (void **)rxr
->rx_desc_ring
;
1890 ring
->dma_arr
= rxr
->rx_desc_mapping
;
1891 ring
->vmem_size
= SW_RXBD_RING_SIZE
* bp
->rx_nr_pages
;
1892 ring
->vmem
= (void **)&rxr
->rx_buf_ring
;
1894 ring
= &rxr
->rx_agg_ring_struct
;
1895 ring
->nr_pages
= bp
->rx_agg_nr_pages
;
1896 ring
->page_size
= HW_RXBD_RING_SIZE
;
1897 ring
->pg_arr
= (void **)rxr
->rx_agg_desc_ring
;
1898 ring
->dma_arr
= rxr
->rx_agg_desc_mapping
;
1899 ring
->vmem_size
= SW_RXBD_AGG_RING_SIZE
* bp
->rx_agg_nr_pages
;
1900 ring
->vmem
= (void **)&rxr
->rx_agg_ring
;
1903 txr
= bnapi
->tx_ring
;
1907 ring
= &txr
->tx_ring_struct
;
1908 ring
->nr_pages
= bp
->tx_nr_pages
;
1909 ring
->page_size
= HW_RXBD_RING_SIZE
;
1910 ring
->pg_arr
= (void **)txr
->tx_desc_ring
;
1911 ring
->dma_arr
= txr
->tx_desc_mapping
;
1912 ring
->vmem_size
= SW_TXBD_RING_SIZE
* bp
->tx_nr_pages
;
1913 ring
->vmem
= (void **)&txr
->tx_buf_ring
;
1917 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct
*ring
, u32 type
)
1921 struct rx_bd
**rx_buf_ring
;
1923 rx_buf_ring
= (struct rx_bd
**)ring
->pg_arr
;
1924 for (i
= 0, prod
= 0; i
< ring
->nr_pages
; i
++) {
1928 rxbd
= rx_buf_ring
[i
];
1932 for (j
= 0; j
< RX_DESC_CNT
; j
++, rxbd
++, prod
++) {
1933 rxbd
->rx_bd_len_flags_type
= cpu_to_le32(type
);
1934 rxbd
->rx_bd_opaque
= prod
;
1939 static int bnxt_init_one_rx_ring(struct bnxt
*bp
, int ring_nr
)
1941 struct net_device
*dev
= bp
->dev
;
1942 struct bnxt_rx_ring_info
*rxr
;
1943 struct bnxt_ring_struct
*ring
;
1947 type
= (bp
->rx_buf_use_size
<< RX_BD_LEN_SHIFT
) |
1948 RX_BD_TYPE_RX_PACKET_BD
| RX_BD_FLAGS_EOP
;
1950 if (NET_IP_ALIGN
== 2)
1951 type
|= RX_BD_FLAGS_SOP
;
1953 rxr
= &bp
->rx_ring
[ring_nr
];
1954 ring
= &rxr
->rx_ring_struct
;
1955 bnxt_init_rxbd_pages(ring
, type
);
1957 prod
= rxr
->rx_prod
;
1958 for (i
= 0; i
< bp
->rx_ring_size
; i
++) {
1959 if (bnxt_alloc_rx_data(bp
, rxr
, prod
, GFP_KERNEL
) != 0) {
1960 netdev_warn(dev
, "init'ed rx ring %d with %d/%d skbs only\n",
1961 ring_nr
, i
, bp
->rx_ring_size
);
1964 prod
= NEXT_RX(prod
);
1966 rxr
->rx_prod
= prod
;
1967 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
1969 ring
= &rxr
->rx_agg_ring_struct
;
1970 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
1972 if (!(bp
->flags
& BNXT_FLAG_AGG_RINGS
))
1975 type
= ((u32
)PAGE_SIZE
<< RX_BD_LEN_SHIFT
) |
1976 RX_BD_TYPE_RX_AGG_BD
| RX_BD_FLAGS_SOP
;
1978 bnxt_init_rxbd_pages(ring
, type
);
1980 prod
= rxr
->rx_agg_prod
;
1981 for (i
= 0; i
< bp
->rx_agg_ring_size
; i
++) {
1982 if (bnxt_alloc_rx_page(bp
, rxr
, prod
, GFP_KERNEL
) != 0) {
1983 netdev_warn(dev
, "init'ed rx ring %d with %d/%d pages only\n",
1984 ring_nr
, i
, bp
->rx_ring_size
);
1987 prod
= NEXT_RX_AGG(prod
);
1989 rxr
->rx_agg_prod
= prod
;
1991 if (bp
->flags
& BNXT_FLAG_TPA
) {
1996 for (i
= 0; i
< MAX_TPA
; i
++) {
1997 data
= __bnxt_alloc_rx_data(bp
, &mapping
,
2002 rxr
->rx_tpa
[i
].data
= data
;
2003 rxr
->rx_tpa
[i
].mapping
= mapping
;
2006 netdev_err(bp
->dev
, "No resource allocated for LRO/GRO\n");
2014 static int bnxt_init_rx_rings(struct bnxt
*bp
)
2018 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
2019 rc
= bnxt_init_one_rx_ring(bp
, i
);
2027 static int bnxt_init_tx_rings(struct bnxt
*bp
)
2031 bp
->tx_wake_thresh
= max_t(int, bp
->tx_ring_size
/ 2,
2034 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
2035 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
2036 struct bnxt_ring_struct
*ring
= &txr
->tx_ring_struct
;
2038 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
2044 static void bnxt_free_ring_grps(struct bnxt
*bp
)
2046 kfree(bp
->grp_info
);
2047 bp
->grp_info
= NULL
;
2050 static int bnxt_init_ring_grps(struct bnxt
*bp
, bool irq_re_init
)
2055 bp
->grp_info
= kcalloc(bp
->cp_nr_rings
,
2056 sizeof(struct bnxt_ring_grp_info
),
2061 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2063 bp
->grp_info
[i
].fw_stats_ctx
= INVALID_HW_RING_ID
;
2064 bp
->grp_info
[i
].fw_grp_id
= INVALID_HW_RING_ID
;
2065 bp
->grp_info
[i
].rx_fw_ring_id
= INVALID_HW_RING_ID
;
2066 bp
->grp_info
[i
].agg_fw_ring_id
= INVALID_HW_RING_ID
;
2067 bp
->grp_info
[i
].cp_fw_ring_id
= INVALID_HW_RING_ID
;
2072 static void bnxt_free_vnics(struct bnxt
*bp
)
2074 kfree(bp
->vnic_info
);
2075 bp
->vnic_info
= NULL
;
2079 static int bnxt_alloc_vnics(struct bnxt
*bp
)
2083 #ifdef CONFIG_RFS_ACCEL
2084 if (bp
->flags
& BNXT_FLAG_RFS
)
2085 num_vnics
+= bp
->rx_nr_rings
;
2088 bp
->vnic_info
= kcalloc(num_vnics
, sizeof(struct bnxt_vnic_info
),
2093 bp
->nr_vnics
= num_vnics
;
2097 static void bnxt_init_vnics(struct bnxt
*bp
)
2101 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
2102 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[i
];
2104 vnic
->fw_vnic_id
= INVALID_HW_RING_ID
;
2105 vnic
->fw_rss_cos_lb_ctx
= INVALID_HW_RING_ID
;
2106 vnic
->fw_l2_ctx_id
= INVALID_HW_RING_ID
;
2108 if (bp
->vnic_info
[i
].rss_hash_key
) {
2110 prandom_bytes(vnic
->rss_hash_key
,
2113 memcpy(vnic
->rss_hash_key
,
2114 bp
->vnic_info
[0].rss_hash_key
,
2120 static int bnxt_calc_nr_ring_pages(u32 ring_size
, int desc_per_pg
)
2124 pages
= ring_size
/ desc_per_pg
;
2131 while (pages
& (pages
- 1))
2137 static void bnxt_set_tpa_flags(struct bnxt
*bp
)
2139 bp
->flags
&= ~BNXT_FLAG_TPA
;
2140 if (bp
->dev
->features
& NETIF_F_LRO
)
2141 bp
->flags
|= BNXT_FLAG_LRO
;
2142 if ((bp
->dev
->features
& NETIF_F_GRO
) && (bp
->pdev
->revision
> 0))
2143 bp
->flags
|= BNXT_FLAG_GRO
;
2146 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2149 void bnxt_set_ring_params(struct bnxt
*bp
)
2151 u32 ring_size
, rx_size
, rx_space
;
2152 u32 agg_factor
= 0, agg_ring_size
= 0;
2154 /* 8 for CRC and VLAN */
2155 rx_size
= SKB_DATA_ALIGN(bp
->dev
->mtu
+ ETH_HLEN
+ NET_IP_ALIGN
+ 8);
2157 rx_space
= rx_size
+ NET_SKB_PAD
+
2158 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
2160 bp
->rx_copy_thresh
= BNXT_RX_COPY_THRESH
;
2161 ring_size
= bp
->rx_ring_size
;
2162 bp
->rx_agg_ring_size
= 0;
2163 bp
->rx_agg_nr_pages
= 0;
2165 if (bp
->flags
& BNXT_FLAG_TPA
)
2168 bp
->flags
&= ~BNXT_FLAG_JUMBO
;
2169 if (rx_space
> PAGE_SIZE
) {
2172 bp
->flags
|= BNXT_FLAG_JUMBO
;
2173 jumbo_factor
= PAGE_ALIGN(bp
->dev
->mtu
- 40) >> PAGE_SHIFT
;
2174 if (jumbo_factor
> agg_factor
)
2175 agg_factor
= jumbo_factor
;
2177 agg_ring_size
= ring_size
* agg_factor
;
2179 if (agg_ring_size
) {
2180 bp
->rx_agg_nr_pages
= bnxt_calc_nr_ring_pages(agg_ring_size
,
2182 if (bp
->rx_agg_nr_pages
> MAX_RX_AGG_PAGES
) {
2183 u32 tmp
= agg_ring_size
;
2185 bp
->rx_agg_nr_pages
= MAX_RX_AGG_PAGES
;
2186 agg_ring_size
= MAX_RX_AGG_PAGES
* RX_DESC_CNT
- 1;
2187 netdev_warn(bp
->dev
, "rx agg ring size %d reduced to %d.\n",
2188 tmp
, agg_ring_size
);
2190 bp
->rx_agg_ring_size
= agg_ring_size
;
2191 bp
->rx_agg_ring_mask
= (bp
->rx_agg_nr_pages
* RX_DESC_CNT
) - 1;
2192 rx_size
= SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH
+ NET_IP_ALIGN
);
2193 rx_space
= rx_size
+ NET_SKB_PAD
+
2194 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
2197 bp
->rx_buf_use_size
= rx_size
;
2198 bp
->rx_buf_size
= rx_space
;
2200 bp
->rx_nr_pages
= bnxt_calc_nr_ring_pages(ring_size
, RX_DESC_CNT
);
2201 bp
->rx_ring_mask
= (bp
->rx_nr_pages
* RX_DESC_CNT
) - 1;
2203 ring_size
= bp
->tx_ring_size
;
2204 bp
->tx_nr_pages
= bnxt_calc_nr_ring_pages(ring_size
, TX_DESC_CNT
);
2205 bp
->tx_ring_mask
= (bp
->tx_nr_pages
* TX_DESC_CNT
) - 1;
2207 ring_size
= bp
->rx_ring_size
* (2 + agg_factor
) + bp
->tx_ring_size
;
2208 bp
->cp_ring_size
= ring_size
;
2210 bp
->cp_nr_pages
= bnxt_calc_nr_ring_pages(ring_size
, CP_DESC_CNT
);
2211 if (bp
->cp_nr_pages
> MAX_CP_PAGES
) {
2212 bp
->cp_nr_pages
= MAX_CP_PAGES
;
2213 bp
->cp_ring_size
= MAX_CP_PAGES
* CP_DESC_CNT
- 1;
2214 netdev_warn(bp
->dev
, "completion ring size %d reduced to %d.\n",
2215 ring_size
, bp
->cp_ring_size
);
2217 bp
->cp_bit
= bp
->cp_nr_pages
* CP_DESC_CNT
;
2218 bp
->cp_ring_mask
= bp
->cp_bit
- 1;
2221 static void bnxt_free_vnic_attributes(struct bnxt
*bp
)
2224 struct bnxt_vnic_info
*vnic
;
2225 struct pci_dev
*pdev
= bp
->pdev
;
2230 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
2231 vnic
= &bp
->vnic_info
[i
];
2233 kfree(vnic
->fw_grp_ids
);
2234 vnic
->fw_grp_ids
= NULL
;
2236 kfree(vnic
->uc_list
);
2237 vnic
->uc_list
= NULL
;
2239 if (vnic
->mc_list
) {
2240 dma_free_coherent(&pdev
->dev
, vnic
->mc_list_size
,
2241 vnic
->mc_list
, vnic
->mc_list_mapping
);
2242 vnic
->mc_list
= NULL
;
2245 if (vnic
->rss_table
) {
2246 dma_free_coherent(&pdev
->dev
, PAGE_SIZE
,
2248 vnic
->rss_table_dma_addr
);
2249 vnic
->rss_table
= NULL
;
2252 vnic
->rss_hash_key
= NULL
;
2257 static int bnxt_alloc_vnic_attributes(struct bnxt
*bp
)
2259 int i
, rc
= 0, size
;
2260 struct bnxt_vnic_info
*vnic
;
2261 struct pci_dev
*pdev
= bp
->pdev
;
2264 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
2265 vnic
= &bp
->vnic_info
[i
];
2267 if (vnic
->flags
& BNXT_VNIC_UCAST_FLAG
) {
2268 int mem_size
= (BNXT_MAX_UC_ADDRS
- 1) * ETH_ALEN
;
2271 vnic
->uc_list
= kmalloc(mem_size
, GFP_KERNEL
);
2272 if (!vnic
->uc_list
) {
2279 if (vnic
->flags
& BNXT_VNIC_MCAST_FLAG
) {
2280 vnic
->mc_list_size
= BNXT_MAX_MC_ADDRS
* ETH_ALEN
;
2282 dma_alloc_coherent(&pdev
->dev
,
2284 &vnic
->mc_list_mapping
,
2286 if (!vnic
->mc_list
) {
2292 if (vnic
->flags
& BNXT_VNIC_RSS_FLAG
)
2293 max_rings
= bp
->rx_nr_rings
;
2297 vnic
->fw_grp_ids
= kcalloc(max_rings
, sizeof(u16
), GFP_KERNEL
);
2298 if (!vnic
->fw_grp_ids
) {
2303 /* Allocate rss table and hash key */
2304 vnic
->rss_table
= dma_alloc_coherent(&pdev
->dev
, PAGE_SIZE
,
2305 &vnic
->rss_table_dma_addr
,
2307 if (!vnic
->rss_table
) {
2312 size
= L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE
* sizeof(u16
));
2314 vnic
->rss_hash_key
= ((void *)vnic
->rss_table
) + size
;
2315 vnic
->rss_hash_key_dma_addr
= vnic
->rss_table_dma_addr
+ size
;
2323 static void bnxt_free_hwrm_resources(struct bnxt
*bp
)
2325 struct pci_dev
*pdev
= bp
->pdev
;
2327 dma_free_coherent(&pdev
->dev
, PAGE_SIZE
, bp
->hwrm_cmd_resp_addr
,
2328 bp
->hwrm_cmd_resp_dma_addr
);
2330 bp
->hwrm_cmd_resp_addr
= NULL
;
2331 if (bp
->hwrm_dbg_resp_addr
) {
2332 dma_free_coherent(&pdev
->dev
, HWRM_DBG_REG_BUF_SIZE
,
2333 bp
->hwrm_dbg_resp_addr
,
2334 bp
->hwrm_dbg_resp_dma_addr
);
2336 bp
->hwrm_dbg_resp_addr
= NULL
;
2340 static int bnxt_alloc_hwrm_resources(struct bnxt
*bp
)
2342 struct pci_dev
*pdev
= bp
->pdev
;
2344 bp
->hwrm_cmd_resp_addr
= dma_alloc_coherent(&pdev
->dev
, PAGE_SIZE
,
2345 &bp
->hwrm_cmd_resp_dma_addr
,
2347 if (!bp
->hwrm_cmd_resp_addr
)
2349 bp
->hwrm_dbg_resp_addr
= dma_alloc_coherent(&pdev
->dev
,
2350 HWRM_DBG_REG_BUF_SIZE
,
2351 &bp
->hwrm_dbg_resp_dma_addr
,
2353 if (!bp
->hwrm_dbg_resp_addr
)
2354 netdev_warn(bp
->dev
, "fail to alloc debug register dma mem\n");
2359 static void bnxt_free_stats(struct bnxt
*bp
)
2362 struct pci_dev
*pdev
= bp
->pdev
;
2367 size
= sizeof(struct ctx_hw_stats
);
2369 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2370 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2371 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
2373 if (cpr
->hw_stats
) {
2374 dma_free_coherent(&pdev
->dev
, size
, cpr
->hw_stats
,
2376 cpr
->hw_stats
= NULL
;
2381 static int bnxt_alloc_stats(struct bnxt
*bp
)
2384 struct pci_dev
*pdev
= bp
->pdev
;
2386 size
= sizeof(struct ctx_hw_stats
);
2388 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2389 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2390 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
2392 cpr
->hw_stats
= dma_alloc_coherent(&pdev
->dev
, size
,
2398 cpr
->hw_stats_ctx_id
= INVALID_STATS_CTX_ID
;
2403 static void bnxt_clear_ring_indices(struct bnxt
*bp
)
2410 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2411 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2412 struct bnxt_cp_ring_info
*cpr
;
2413 struct bnxt_rx_ring_info
*rxr
;
2414 struct bnxt_tx_ring_info
*txr
;
2419 cpr
= &bnapi
->cp_ring
;
2420 cpr
->cp_raw_cons
= 0;
2422 txr
= bnapi
->tx_ring
;
2428 rxr
= bnapi
->rx_ring
;
2431 rxr
->rx_agg_prod
= 0;
2432 rxr
->rx_sw_agg_prod
= 0;
2437 static void bnxt_free_ntp_fltrs(struct bnxt
*bp
, bool irq_reinit
)
2439 #ifdef CONFIG_RFS_ACCEL
2442 /* Under rtnl_lock and all our NAPIs have been disabled. It's
2443 * safe to delete the hash table.
2445 for (i
= 0; i
< BNXT_NTP_FLTR_HASH_SIZE
; i
++) {
2446 struct hlist_head
*head
;
2447 struct hlist_node
*tmp
;
2448 struct bnxt_ntuple_filter
*fltr
;
2450 head
= &bp
->ntp_fltr_hash_tbl
[i
];
2451 hlist_for_each_entry_safe(fltr
, tmp
, head
, hash
) {
2452 hlist_del(&fltr
->hash
);
2457 kfree(bp
->ntp_fltr_bmap
);
2458 bp
->ntp_fltr_bmap
= NULL
;
2460 bp
->ntp_fltr_count
= 0;
2464 static int bnxt_alloc_ntp_fltrs(struct bnxt
*bp
)
2466 #ifdef CONFIG_RFS_ACCEL
2469 if (!(bp
->flags
& BNXT_FLAG_RFS
))
2472 for (i
= 0; i
< BNXT_NTP_FLTR_HASH_SIZE
; i
++)
2473 INIT_HLIST_HEAD(&bp
->ntp_fltr_hash_tbl
[i
]);
2475 bp
->ntp_fltr_count
= 0;
2476 bp
->ntp_fltr_bmap
= kzalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR
),
2479 if (!bp
->ntp_fltr_bmap
)
2488 static void bnxt_free_mem(struct bnxt
*bp
, bool irq_re_init
)
2490 bnxt_free_vnic_attributes(bp
);
2491 bnxt_free_tx_rings(bp
);
2492 bnxt_free_rx_rings(bp
);
2493 bnxt_free_cp_rings(bp
);
2494 bnxt_free_ntp_fltrs(bp
, irq_re_init
);
2496 bnxt_free_stats(bp
);
2497 bnxt_free_ring_grps(bp
);
2498 bnxt_free_vnics(bp
);
2506 bnxt_clear_ring_indices(bp
);
2510 static int bnxt_alloc_mem(struct bnxt
*bp
, bool irq_re_init
)
2512 int i
, j
, rc
, size
, arr_size
;
2516 /* Allocate bnapi mem pointer array and mem block for
2519 arr_size
= L1_CACHE_ALIGN(sizeof(struct bnxt_napi
*) *
2521 size
= L1_CACHE_ALIGN(sizeof(struct bnxt_napi
));
2522 bnapi
= kzalloc(arr_size
+ size
* bp
->cp_nr_rings
, GFP_KERNEL
);
2528 for (i
= 0; i
< bp
->cp_nr_rings
; i
++, bnapi
+= size
) {
2529 bp
->bnapi
[i
] = bnapi
;
2530 bp
->bnapi
[i
]->index
= i
;
2531 bp
->bnapi
[i
]->bp
= bp
;
2534 bp
->rx_ring
= kcalloc(bp
->rx_nr_rings
,
2535 sizeof(struct bnxt_rx_ring_info
),
2540 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
2541 bp
->rx_ring
[i
].bnapi
= bp
->bnapi
[i
];
2542 bp
->bnapi
[i
]->rx_ring
= &bp
->rx_ring
[i
];
2545 bp
->tx_ring
= kcalloc(bp
->tx_nr_rings
,
2546 sizeof(struct bnxt_tx_ring_info
),
2551 if (bp
->flags
& BNXT_FLAG_SHARED_RINGS
)
2554 j
= bp
->rx_nr_rings
;
2556 for (i
= 0; i
< bp
->tx_nr_rings
; i
++, j
++) {
2557 bp
->tx_ring
[i
].bnapi
= bp
->bnapi
[j
];
2558 bp
->bnapi
[j
]->tx_ring
= &bp
->tx_ring
[i
];
2561 rc
= bnxt_alloc_stats(bp
);
2565 rc
= bnxt_alloc_ntp_fltrs(bp
);
2569 rc
= bnxt_alloc_vnics(bp
);
2574 bnxt_init_ring_struct(bp
);
2576 rc
= bnxt_alloc_rx_rings(bp
);
2580 rc
= bnxt_alloc_tx_rings(bp
);
2584 rc
= bnxt_alloc_cp_rings(bp
);
2588 bp
->vnic_info
[0].flags
|= BNXT_VNIC_RSS_FLAG
| BNXT_VNIC_MCAST_FLAG
|
2589 BNXT_VNIC_UCAST_FLAG
;
2590 rc
= bnxt_alloc_vnic_attributes(bp
);
2596 bnxt_free_mem(bp
, true);
2600 void bnxt_hwrm_cmd_hdr_init(struct bnxt
*bp
, void *request
, u16 req_type
,
2601 u16 cmpl_ring
, u16 target_id
)
2603 struct hwrm_cmd_req_hdr
*req
= request
;
2605 req
->cmpl_ring_req_type
=
2606 cpu_to_le32(req_type
| (cmpl_ring
<< HWRM_CMPL_RING_SFT
));
2607 req
->target_id_seq_id
= cpu_to_le32(target_id
<< HWRM_TARGET_FID_SFT
);
2608 req
->resp_addr
= cpu_to_le64(bp
->hwrm_cmd_resp_dma_addr
);
2611 int _hwrm_send_message(struct bnxt
*bp
, void *msg
, u32 msg_len
, int timeout
)
2613 int i
, intr_process
, rc
;
2614 struct hwrm_cmd_req_hdr
*req
= msg
;
2616 __le32
*resp_len
, *valid
;
2617 u16 cp_ring_id
, len
= 0;
2618 struct hwrm_err_output
*resp
= bp
->hwrm_cmd_resp_addr
;
2620 req
->target_id_seq_id
|= cpu_to_le32(bp
->hwrm_cmd_seq
++);
2621 memset(resp
, 0, PAGE_SIZE
);
2622 cp_ring_id
= (le32_to_cpu(req
->cmpl_ring_req_type
) &
2623 HWRM_CMPL_RING_MASK
) >>
2625 intr_process
= (cp_ring_id
== INVALID_HW_RING_ID
) ? 0 : 1;
2627 /* Write request msg to hwrm channel */
2628 __iowrite32_copy(bp
->bar0
, data
, msg_len
/ 4);
2630 for (i
= msg_len
; i
< HWRM_MAX_REQ_LEN
; i
+= 4)
2631 writel(0, bp
->bar0
+ i
);
2633 /* currently supports only one outstanding message */
2635 bp
->hwrm_intr_seq_id
= le32_to_cpu(req
->target_id_seq_id
) &
2638 /* Ring channel doorbell */
2639 writel(1, bp
->bar0
+ 0x100);
2643 /* Wait until hwrm response cmpl interrupt is processed */
2644 while (bp
->hwrm_intr_seq_id
!= HWRM_SEQ_ID_INVALID
&&
2646 usleep_range(600, 800);
2649 if (bp
->hwrm_intr_seq_id
!= HWRM_SEQ_ID_INVALID
) {
2650 netdev_err(bp
->dev
, "Resp cmpl intr err msg: 0x%x\n",
2651 req
->cmpl_ring_req_type
);
2655 /* Check if response len is updated */
2656 resp_len
= bp
->hwrm_cmd_resp_addr
+ HWRM_RESP_LEN_OFFSET
;
2657 for (i
= 0; i
< timeout
; i
++) {
2658 len
= (le32_to_cpu(*resp_len
) & HWRM_RESP_LEN_MASK
) >>
2662 usleep_range(600, 800);
2666 netdev_err(bp
->dev
, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
2667 timeout
, req
->cmpl_ring_req_type
,
2668 req
->target_id_seq_id
, *resp_len
);
2672 /* Last word of resp contains valid bit */
2673 valid
= bp
->hwrm_cmd_resp_addr
+ len
- 4;
2674 for (i
= 0; i
< timeout
; i
++) {
2675 if (le32_to_cpu(*valid
) & HWRM_RESP_VALID_MASK
)
2677 usleep_range(600, 800);
2681 netdev_err(bp
->dev
, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
2682 timeout
, req
->cmpl_ring_req_type
,
2683 req
->target_id_seq_id
, len
, *valid
);
2688 rc
= le16_to_cpu(resp
->error_code
);
2690 netdev_err(bp
->dev
, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
2691 le16_to_cpu(resp
->req_type
),
2692 le16_to_cpu(resp
->seq_id
), rc
);
2698 int hwrm_send_message(struct bnxt
*bp
, void *msg
, u32 msg_len
, int timeout
)
2702 mutex_lock(&bp
->hwrm_cmd_lock
);
2703 rc
= _hwrm_send_message(bp
, msg
, msg_len
, timeout
);
2704 mutex_unlock(&bp
->hwrm_cmd_lock
);
2708 static int bnxt_hwrm_func_drv_rgtr(struct bnxt
*bp
)
2710 struct hwrm_func_drv_rgtr_input req
= {0};
2713 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_DRV_RGTR
, -1, -1);
2716 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE
|
2717 FUNC_DRV_RGTR_REQ_ENABLES_VER
|
2718 FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD
);
2720 /* TODO: current async event fwd bits are not defined and the firmware
2721 * only checks if it is non-zero to enable async event forwarding
2723 req
.async_event_fwd
[0] |= cpu_to_le32(1);
2724 req
.os_type
= cpu_to_le16(1);
2725 req
.ver_maj
= DRV_VER_MAJ
;
2726 req
.ver_min
= DRV_VER_MIN
;
2727 req
.ver_upd
= DRV_VER_UPD
;
2730 DECLARE_BITMAP(vf_req_snif_bmap
, 256);
2731 u32
*data
= (u32
*)vf_req_snif_bmap
;
2733 memset(vf_req_snif_bmap
, 0, sizeof(vf_req_snif_bmap
));
2734 for (i
= 0; i
< ARRAY_SIZE(bnxt_vf_req_snif
); i
++)
2735 __set_bit(bnxt_vf_req_snif
[i
], vf_req_snif_bmap
);
2737 for (i
= 0; i
< 8; i
++)
2738 req
.vf_req_fwd
[i
] = cpu_to_le32(data
[i
]);
2741 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD
);
2744 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2747 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt
*bp
)
2749 struct hwrm_func_drv_unrgtr_input req
= {0};
2751 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_DRV_UNRGTR
, -1, -1);
2752 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2755 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt
*bp
, u8 tunnel_type
)
2758 struct hwrm_tunnel_dst_port_free_input req
= {0};
2760 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_TUNNEL_DST_PORT_FREE
, -1, -1);
2761 req
.tunnel_type
= tunnel_type
;
2763 switch (tunnel_type
) {
2764 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
:
2765 req
.tunnel_dst_port_id
= bp
->vxlan_fw_dst_port_id
;
2767 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
:
2768 req
.tunnel_dst_port_id
= bp
->nge_fw_dst_port_id
;
2774 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2776 netdev_err(bp
->dev
, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
2781 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt
*bp
, __be16 port
,
2785 struct hwrm_tunnel_dst_port_alloc_input req
= {0};
2786 struct hwrm_tunnel_dst_port_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
2788 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_TUNNEL_DST_PORT_ALLOC
, -1, -1);
2790 req
.tunnel_type
= tunnel_type
;
2791 req
.tunnel_dst_port_val
= port
;
2793 mutex_lock(&bp
->hwrm_cmd_lock
);
2794 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2796 netdev_err(bp
->dev
, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
2801 if (tunnel_type
& TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN
)
2802 bp
->vxlan_fw_dst_port_id
= resp
->tunnel_dst_port_id
;
2804 else if (tunnel_type
& TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE
)
2805 bp
->nge_fw_dst_port_id
= resp
->tunnel_dst_port_id
;
2807 mutex_unlock(&bp
->hwrm_cmd_lock
);
2811 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt
*bp
, u16 vnic_id
)
2813 struct hwrm_cfa_l2_set_rx_mask_input req
= {0};
2814 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
2816 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_L2_SET_RX_MASK
, -1, -1);
2817 req
.vnic_id
= cpu_to_le32(vnic
->fw_vnic_id
);
2819 req
.num_mc_entries
= cpu_to_le32(vnic
->mc_list_count
);
2820 req
.mc_tbl_addr
= cpu_to_le64(vnic
->mc_list_mapping
);
2821 req
.mask
= cpu_to_le32(vnic
->rx_mask
);
2822 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2825 #ifdef CONFIG_RFS_ACCEL
2826 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt
*bp
,
2827 struct bnxt_ntuple_filter
*fltr
)
2829 struct hwrm_cfa_ntuple_filter_free_input req
= {0};
2831 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_NTUPLE_FILTER_FREE
, -1, -1);
2832 req
.ntuple_filter_id
= fltr
->filter_id
;
2833 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2836 #define BNXT_NTP_FLTR_FLAGS \
2837 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
2838 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
2839 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
2840 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
2841 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
2842 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
2843 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
2844 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
2845 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
2846 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
2847 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
2848 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
2849 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
2850 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
2852 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt
*bp
,
2853 struct bnxt_ntuple_filter
*fltr
)
2856 struct hwrm_cfa_ntuple_filter_alloc_input req
= {0};
2857 struct hwrm_cfa_ntuple_filter_alloc_output
*resp
=
2858 bp
->hwrm_cmd_resp_addr
;
2859 struct flow_keys
*keys
= &fltr
->fkeys
;
2860 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[fltr
->rxq
+ 1];
2862 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_NTUPLE_FILTER_ALLOC
, -1, -1);
2863 req
.l2_filter_id
= bp
->vnic_info
[0].fw_l2_filter_id
[0];
2865 req
.enables
= cpu_to_le32(BNXT_NTP_FLTR_FLAGS
);
2867 req
.ethertype
= htons(ETH_P_IP
);
2868 memcpy(req
.src_macaddr
, fltr
->src_mac_addr
, ETH_ALEN
);
2869 req
.ip_addr_type
= CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4
;
2870 req
.ip_protocol
= keys
->basic
.ip_proto
;
2872 req
.src_ipaddr
[0] = keys
->addrs
.v4addrs
.src
;
2873 req
.src_ipaddr_mask
[0] = cpu_to_be32(0xffffffff);
2874 req
.dst_ipaddr
[0] = keys
->addrs
.v4addrs
.dst
;
2875 req
.dst_ipaddr_mask
[0] = cpu_to_be32(0xffffffff);
2877 req
.src_port
= keys
->ports
.src
;
2878 req
.src_port_mask
= cpu_to_be16(0xffff);
2879 req
.dst_port
= keys
->ports
.dst
;
2880 req
.dst_port_mask
= cpu_to_be16(0xffff);
2882 req
.dst_id
= cpu_to_le16(vnic
->fw_vnic_id
);
2883 mutex_lock(&bp
->hwrm_cmd_lock
);
2884 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2886 fltr
->filter_id
= resp
->ntuple_filter_id
;
2887 mutex_unlock(&bp
->hwrm_cmd_lock
);
2892 static int bnxt_hwrm_set_vnic_filter(struct bnxt
*bp
, u16 vnic_id
, u16 idx
,
2896 struct hwrm_cfa_l2_filter_alloc_input req
= {0};
2897 struct hwrm_cfa_l2_filter_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
2899 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_L2_FILTER_ALLOC
, -1, -1);
2900 req
.flags
= cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX
|
2901 CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST
);
2902 req
.dst_id
= cpu_to_le16(bp
->vnic_info
[vnic_id
].fw_vnic_id
);
2904 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR
|
2905 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID
|
2906 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK
);
2907 memcpy(req
.l2_addr
, mac_addr
, ETH_ALEN
);
2908 req
.l2_addr_mask
[0] = 0xff;
2909 req
.l2_addr_mask
[1] = 0xff;
2910 req
.l2_addr_mask
[2] = 0xff;
2911 req
.l2_addr_mask
[3] = 0xff;
2912 req
.l2_addr_mask
[4] = 0xff;
2913 req
.l2_addr_mask
[5] = 0xff;
2915 mutex_lock(&bp
->hwrm_cmd_lock
);
2916 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2918 bp
->vnic_info
[vnic_id
].fw_l2_filter_id
[idx
] =
2920 mutex_unlock(&bp
->hwrm_cmd_lock
);
2924 static int bnxt_hwrm_clear_vnic_filter(struct bnxt
*bp
)
2926 u16 i
, j
, num_of_vnics
= 1; /* only vnic 0 supported */
2929 /* Any associated ntuple filters will also be cleared by firmware. */
2930 mutex_lock(&bp
->hwrm_cmd_lock
);
2931 for (i
= 0; i
< num_of_vnics
; i
++) {
2932 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[i
];
2934 for (j
= 0; j
< vnic
->uc_filter_count
; j
++) {
2935 struct hwrm_cfa_l2_filter_free_input req
= {0};
2937 bnxt_hwrm_cmd_hdr_init(bp
, &req
,
2938 HWRM_CFA_L2_FILTER_FREE
, -1, -1);
2940 req
.l2_filter_id
= vnic
->fw_l2_filter_id
[j
];
2942 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
2945 vnic
->uc_filter_count
= 0;
2947 mutex_unlock(&bp
->hwrm_cmd_lock
);
2952 static int bnxt_hwrm_vnic_set_tpa(struct bnxt
*bp
, u16 vnic_id
, u32 tpa_flags
)
2954 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
2955 struct hwrm_vnic_tpa_cfg_input req
= {0};
2957 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_TPA_CFG
, -1, -1);
2960 u16 mss
= bp
->dev
->mtu
- 40;
2961 u32 nsegs
, n
, segs
= 0, flags
;
2963 flags
= VNIC_TPA_CFG_REQ_FLAGS_TPA
|
2964 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA
|
2965 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE
|
2966 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN
|
2967 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ
;
2968 if (tpa_flags
& BNXT_FLAG_GRO
)
2969 flags
|= VNIC_TPA_CFG_REQ_FLAGS_GRO
;
2971 req
.flags
= cpu_to_le32(flags
);
2974 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS
|
2975 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS
|
2976 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN
);
2978 /* Number of segs are log2 units, and first packet is not
2979 * included as part of this units.
2981 if (mss
<= PAGE_SIZE
) {
2982 n
= PAGE_SIZE
/ mss
;
2983 nsegs
= (MAX_SKB_FRAGS
- 1) * n
;
2985 n
= mss
/ PAGE_SIZE
;
2986 if (mss
& (PAGE_SIZE
- 1))
2988 nsegs
= (MAX_SKB_FRAGS
- n
) / n
;
2991 segs
= ilog2(nsegs
);
2992 req
.max_agg_segs
= cpu_to_le16(segs
);
2993 req
.max_aggs
= cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX
);
2995 req
.min_agg_len
= cpu_to_le32(512);
2997 req
.vnic_id
= cpu_to_le16(vnic
->fw_vnic_id
);
2999 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3002 static int bnxt_hwrm_vnic_set_rss(struct bnxt
*bp
, u16 vnic_id
, bool set_rss
)
3004 u32 i
, j
, max_rings
;
3005 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
3006 struct hwrm_vnic_rss_cfg_input req
= {0};
3008 if (vnic
->fw_rss_cos_lb_ctx
== INVALID_HW_RING_ID
)
3011 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_RSS_CFG
, -1, -1);
3013 vnic
->hash_type
= BNXT_RSS_HASH_TYPE_FLAG_IPV4
|
3014 BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV4
|
3015 BNXT_RSS_HASH_TYPE_FLAG_IPV6
|
3016 BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV6
;
3018 req
.hash_type
= cpu_to_le32(vnic
->hash_type
);
3020 if (vnic
->flags
& BNXT_VNIC_RSS_FLAG
)
3021 max_rings
= bp
->rx_nr_rings
;
3025 /* Fill the RSS indirection table with ring group ids */
3026 for (i
= 0, j
= 0; i
< HW_HASH_INDEX_SIZE
; i
++, j
++) {
3029 vnic
->rss_table
[i
] = cpu_to_le16(vnic
->fw_grp_ids
[j
]);
3032 req
.ring_grp_tbl_addr
= cpu_to_le64(vnic
->rss_table_dma_addr
);
3033 req
.hash_key_tbl_addr
=
3034 cpu_to_le64(vnic
->rss_hash_key_dma_addr
);
3036 req
.rss_ctx_idx
= cpu_to_le16(vnic
->fw_rss_cos_lb_ctx
);
3037 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3040 static int bnxt_hwrm_vnic_set_hds(struct bnxt
*bp
, u16 vnic_id
)
3042 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
3043 struct hwrm_vnic_plcmodes_cfg_input req
= {0};
3045 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_PLCMODES_CFG
, -1, -1);
3046 req
.flags
= cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT
|
3047 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4
|
3048 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6
);
3050 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID
|
3051 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID
);
3052 /* thresholds not implemented in firmware yet */
3053 req
.jumbo_thresh
= cpu_to_le16(bp
->rx_copy_thresh
);
3054 req
.hds_threshold
= cpu_to_le16(bp
->rx_copy_thresh
);
3055 req
.vnic_id
= cpu_to_le32(vnic
->fw_vnic_id
);
3056 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3059 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt
*bp
, u16 vnic_id
)
3061 struct hwrm_vnic_rss_cos_lb_ctx_free_input req
= {0};
3063 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_RSS_COS_LB_CTX_FREE
, -1, -1);
3064 req
.rss_cos_lb_ctx_id
=
3065 cpu_to_le16(bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
);
3067 hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3068 bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
= INVALID_HW_RING_ID
;
3071 static void bnxt_hwrm_vnic_ctx_free(struct bnxt
*bp
)
3075 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
3076 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[i
];
3078 if (vnic
->fw_rss_cos_lb_ctx
!= INVALID_HW_RING_ID
)
3079 bnxt_hwrm_vnic_ctx_free_one(bp
, i
);
3081 bp
->rsscos_nr_ctxs
= 0;
3084 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt
*bp
, u16 vnic_id
)
3087 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req
= {0};
3088 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output
*resp
=
3089 bp
->hwrm_cmd_resp_addr
;
3091 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC
, -1,
3094 mutex_lock(&bp
->hwrm_cmd_lock
);
3095 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3097 bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
=
3098 le16_to_cpu(resp
->rss_cos_lb_ctx_id
);
3099 mutex_unlock(&bp
->hwrm_cmd_lock
);
3104 static int bnxt_hwrm_vnic_cfg(struct bnxt
*bp
, u16 vnic_id
)
3106 unsigned int ring
= 0, grp_idx
;
3107 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
3108 struct hwrm_vnic_cfg_input req
= {0};
3110 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_CFG
, -1, -1);
3111 /* Only RSS support for now TBD: COS & LB */
3112 req
.enables
= cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP
|
3113 VNIC_CFG_REQ_ENABLES_RSS_RULE
);
3114 req
.rss_rule
= cpu_to_le16(vnic
->fw_rss_cos_lb_ctx
);
3115 req
.cos_rule
= cpu_to_le16(0xffff);
3116 if (vnic
->flags
& BNXT_VNIC_RSS_FLAG
)
3118 else if (vnic
->flags
& BNXT_VNIC_RFS_FLAG
)
3121 grp_idx
= bp
->rx_ring
[ring
].bnapi
->index
;
3122 req
.vnic_id
= cpu_to_le16(vnic
->fw_vnic_id
);
3123 req
.dflt_ring_grp
= cpu_to_le16(bp
->grp_info
[grp_idx
].fw_grp_id
);
3125 req
.lb_rule
= cpu_to_le16(0xffff);
3126 req
.mru
= cpu_to_le16(bp
->dev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+
3129 if (bp
->flags
& BNXT_FLAG_STRIP_VLAN
)
3130 req
.flags
|= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE
);
3132 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3135 static int bnxt_hwrm_vnic_free_one(struct bnxt
*bp
, u16 vnic_id
)
3139 if (bp
->vnic_info
[vnic_id
].fw_vnic_id
!= INVALID_HW_RING_ID
) {
3140 struct hwrm_vnic_free_input req
= {0};
3142 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_FREE
, -1, -1);
3144 cpu_to_le32(bp
->vnic_info
[vnic_id
].fw_vnic_id
);
3146 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3149 bp
->vnic_info
[vnic_id
].fw_vnic_id
= INVALID_HW_RING_ID
;
3154 static void bnxt_hwrm_vnic_free(struct bnxt
*bp
)
3158 for (i
= 0; i
< bp
->nr_vnics
; i
++)
3159 bnxt_hwrm_vnic_free_one(bp
, i
);
3162 static int bnxt_hwrm_vnic_alloc(struct bnxt
*bp
, u16 vnic_id
,
3163 unsigned int start_rx_ring_idx
,
3164 unsigned int nr_rings
)
3167 unsigned int i
, j
, grp_idx
, end_idx
= start_rx_ring_idx
+ nr_rings
;
3168 struct hwrm_vnic_alloc_input req
= {0};
3169 struct hwrm_vnic_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3171 /* map ring groups to this vnic */
3172 for (i
= start_rx_ring_idx
, j
= 0; i
< end_idx
; i
++, j
++) {
3173 grp_idx
= bp
->rx_ring
[i
].bnapi
->index
;
3174 if (bp
->grp_info
[grp_idx
].fw_grp_id
== INVALID_HW_RING_ID
) {
3175 netdev_err(bp
->dev
, "Not enough ring groups avail:%x req:%x\n",
3179 bp
->vnic_info
[vnic_id
].fw_grp_ids
[j
] =
3180 bp
->grp_info
[grp_idx
].fw_grp_id
;
3183 bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
= INVALID_HW_RING_ID
;
3185 req
.flags
= cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT
);
3187 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_ALLOC
, -1, -1);
3189 mutex_lock(&bp
->hwrm_cmd_lock
);
3190 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3192 bp
->vnic_info
[vnic_id
].fw_vnic_id
= le32_to_cpu(resp
->vnic_id
);
3193 mutex_unlock(&bp
->hwrm_cmd_lock
);
3197 static int bnxt_hwrm_ring_grp_alloc(struct bnxt
*bp
)
3202 mutex_lock(&bp
->hwrm_cmd_lock
);
3203 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3204 struct hwrm_ring_grp_alloc_input req
= {0};
3205 struct hwrm_ring_grp_alloc_output
*resp
=
3206 bp
->hwrm_cmd_resp_addr
;
3207 unsigned int grp_idx
= bp
->rx_ring
[i
].bnapi
->index
;
3209 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_GRP_ALLOC
, -1, -1);
3211 req
.cr
= cpu_to_le16(bp
->grp_info
[grp_idx
].cp_fw_ring_id
);
3212 req
.rr
= cpu_to_le16(bp
->grp_info
[grp_idx
].rx_fw_ring_id
);
3213 req
.ar
= cpu_to_le16(bp
->grp_info
[grp_idx
].agg_fw_ring_id
);
3214 req
.sc
= cpu_to_le16(bp
->grp_info
[grp_idx
].fw_stats_ctx
);
3216 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3221 bp
->grp_info
[grp_idx
].fw_grp_id
=
3222 le32_to_cpu(resp
->ring_group_id
);
3224 mutex_unlock(&bp
->hwrm_cmd_lock
);
3228 static int bnxt_hwrm_ring_grp_free(struct bnxt
*bp
)
3232 struct hwrm_ring_grp_free_input req
= {0};
3237 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_GRP_FREE
, -1, -1);
3239 mutex_lock(&bp
->hwrm_cmd_lock
);
3240 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3241 if (bp
->grp_info
[i
].fw_grp_id
== INVALID_HW_RING_ID
)
3244 cpu_to_le32(bp
->grp_info
[i
].fw_grp_id
);
3246 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3250 bp
->grp_info
[i
].fw_grp_id
= INVALID_HW_RING_ID
;
3252 mutex_unlock(&bp
->hwrm_cmd_lock
);
3256 static int hwrm_ring_alloc_send_msg(struct bnxt
*bp
,
3257 struct bnxt_ring_struct
*ring
,
3258 u32 ring_type
, u32 map_index
,
3261 int rc
= 0, err
= 0;
3262 struct hwrm_ring_alloc_input req
= {0};
3263 struct hwrm_ring_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3266 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_ALLOC
, -1, -1);
3269 if (ring
->nr_pages
> 1) {
3270 req
.page_tbl_addr
= cpu_to_le64(ring
->pg_tbl_map
);
3271 /* Page size is in log2 units */
3272 req
.page_size
= BNXT_PAGE_SHIFT
;
3273 req
.page_tbl_depth
= 1;
3275 req
.page_tbl_addr
= cpu_to_le64(ring
->dma_arr
[0]);
3278 /* Association of ring index with doorbell index and MSIX number */
3279 req
.logical_id
= cpu_to_le16(map_index
);
3281 switch (ring_type
) {
3282 case HWRM_RING_ALLOC_TX
:
3283 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_TX
;
3284 /* Association of transmit ring with completion ring */
3286 cpu_to_le16(bp
->grp_info
[map_index
].cp_fw_ring_id
);
3287 req
.length
= cpu_to_le32(bp
->tx_ring_mask
+ 1);
3288 req
.stat_ctx_id
= cpu_to_le32(stats_ctx_id
);
3289 req
.queue_id
= cpu_to_le16(ring
->queue_id
);
3291 case HWRM_RING_ALLOC_RX
:
3292 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_RX
;
3293 req
.length
= cpu_to_le32(bp
->rx_ring_mask
+ 1);
3295 case HWRM_RING_ALLOC_AGG
:
3296 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_RX
;
3297 req
.length
= cpu_to_le32(bp
->rx_agg_ring_mask
+ 1);
3299 case HWRM_RING_ALLOC_CMPL
:
3300 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_CMPL
;
3301 req
.length
= cpu_to_le32(bp
->cp_ring_mask
+ 1);
3302 if (bp
->flags
& BNXT_FLAG_USING_MSIX
)
3303 req
.int_mode
= RING_ALLOC_REQ_INT_MODE_MSIX
;
3306 netdev_err(bp
->dev
, "hwrm alloc invalid ring type %d\n",
3311 mutex_lock(&bp
->hwrm_cmd_lock
);
3312 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3313 err
= le16_to_cpu(resp
->error_code
);
3314 ring_id
= le16_to_cpu(resp
->ring_id
);
3315 mutex_unlock(&bp
->hwrm_cmd_lock
);
3318 switch (ring_type
) {
3319 case RING_FREE_REQ_RING_TYPE_CMPL
:
3320 netdev_err(bp
->dev
, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
3324 case RING_FREE_REQ_RING_TYPE_RX
:
3325 netdev_err(bp
->dev
, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
3329 case RING_FREE_REQ_RING_TYPE_TX
:
3330 netdev_err(bp
->dev
, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
3335 netdev_err(bp
->dev
, "Invalid ring\n");
3339 ring
->fw_ring_id
= ring_id
;
3343 static int bnxt_hwrm_ring_alloc(struct bnxt
*bp
)
3347 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3348 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3349 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3350 struct bnxt_ring_struct
*ring
= &cpr
->cp_ring_struct
;
3352 rc
= hwrm_ring_alloc_send_msg(bp
, ring
, HWRM_RING_ALLOC_CMPL
, i
,
3353 INVALID_STATS_CTX_ID
);
3356 cpr
->cp_doorbell
= bp
->bar1
+ i
* 0x80;
3357 BNXT_CP_DB(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
3358 bp
->grp_info
[i
].cp_fw_ring_id
= ring
->fw_ring_id
;
3361 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
3362 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
3363 struct bnxt_ring_struct
*ring
= &txr
->tx_ring_struct
;
3364 u32 map_idx
= txr
->bnapi
->index
;
3365 u16 fw_stats_ctx
= bp
->grp_info
[map_idx
].fw_stats_ctx
;
3367 rc
= hwrm_ring_alloc_send_msg(bp
, ring
, HWRM_RING_ALLOC_TX
,
3368 map_idx
, fw_stats_ctx
);
3371 txr
->tx_doorbell
= bp
->bar1
+ map_idx
* 0x80;
3374 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3375 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
3376 struct bnxt_ring_struct
*ring
= &rxr
->rx_ring_struct
;
3377 u32 map_idx
= rxr
->bnapi
->index
;
3379 rc
= hwrm_ring_alloc_send_msg(bp
, ring
, HWRM_RING_ALLOC_RX
,
3380 map_idx
, INVALID_STATS_CTX_ID
);
3383 rxr
->rx_doorbell
= bp
->bar1
+ map_idx
* 0x80;
3384 writel(DB_KEY_RX
| rxr
->rx_prod
, rxr
->rx_doorbell
);
3385 bp
->grp_info
[map_idx
].rx_fw_ring_id
= ring
->fw_ring_id
;
3388 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
) {
3389 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3390 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
3391 struct bnxt_ring_struct
*ring
=
3392 &rxr
->rx_agg_ring_struct
;
3393 u32 grp_idx
= rxr
->bnapi
->index
;
3394 u32 map_idx
= grp_idx
+ bp
->rx_nr_rings
;
3396 rc
= hwrm_ring_alloc_send_msg(bp
, ring
,
3397 HWRM_RING_ALLOC_AGG
,
3399 INVALID_STATS_CTX_ID
);
3403 rxr
->rx_agg_doorbell
= bp
->bar1
+ map_idx
* 0x80;
3404 writel(DB_KEY_RX
| rxr
->rx_agg_prod
,
3405 rxr
->rx_agg_doorbell
);
3406 bp
->grp_info
[grp_idx
].agg_fw_ring_id
= ring
->fw_ring_id
;
3413 static int hwrm_ring_free_send_msg(struct bnxt
*bp
,
3414 struct bnxt_ring_struct
*ring
,
3415 u32 ring_type
, int cmpl_ring_id
)
3418 struct hwrm_ring_free_input req
= {0};
3419 struct hwrm_ring_free_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3422 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_FREE
, cmpl_ring_id
, -1);
3423 req
.ring_type
= ring_type
;
3424 req
.ring_id
= cpu_to_le16(ring
->fw_ring_id
);
3426 mutex_lock(&bp
->hwrm_cmd_lock
);
3427 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3428 error_code
= le16_to_cpu(resp
->error_code
);
3429 mutex_unlock(&bp
->hwrm_cmd_lock
);
3431 if (rc
|| error_code
) {
3432 switch (ring_type
) {
3433 case RING_FREE_REQ_RING_TYPE_CMPL
:
3434 netdev_err(bp
->dev
, "hwrm_ring_free cp failed. rc:%d\n",
3437 case RING_FREE_REQ_RING_TYPE_RX
:
3438 netdev_err(bp
->dev
, "hwrm_ring_free rx failed. rc:%d\n",
3441 case RING_FREE_REQ_RING_TYPE_TX
:
3442 netdev_err(bp
->dev
, "hwrm_ring_free tx failed. rc:%d\n",
3446 netdev_err(bp
->dev
, "Invalid ring\n");
3453 static void bnxt_hwrm_ring_free(struct bnxt
*bp
, bool close_path
)
3460 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
3461 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
3462 struct bnxt_ring_struct
*ring
= &txr
->tx_ring_struct
;
3463 u32 grp_idx
= txr
->bnapi
->index
;
3464 u32 cmpl_ring_id
= bp
->grp_info
[grp_idx
].cp_fw_ring_id
;
3466 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
3467 hwrm_ring_free_send_msg(bp
, ring
,
3468 RING_FREE_REQ_RING_TYPE_TX
,
3469 close_path
? cmpl_ring_id
:
3470 INVALID_HW_RING_ID
);
3471 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
3475 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3476 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
3477 struct bnxt_ring_struct
*ring
= &rxr
->rx_ring_struct
;
3478 u32 grp_idx
= rxr
->bnapi
->index
;
3479 u32 cmpl_ring_id
= bp
->grp_info
[grp_idx
].cp_fw_ring_id
;
3481 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
3482 hwrm_ring_free_send_msg(bp
, ring
,
3483 RING_FREE_REQ_RING_TYPE_RX
,
3484 close_path
? cmpl_ring_id
:
3485 INVALID_HW_RING_ID
);
3486 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
3487 bp
->grp_info
[grp_idx
].rx_fw_ring_id
=
3492 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3493 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
3494 struct bnxt_ring_struct
*ring
= &rxr
->rx_agg_ring_struct
;
3495 u32 grp_idx
= rxr
->bnapi
->index
;
3496 u32 cmpl_ring_id
= bp
->grp_info
[grp_idx
].cp_fw_ring_id
;
3498 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
3499 hwrm_ring_free_send_msg(bp
, ring
,
3500 RING_FREE_REQ_RING_TYPE_RX
,
3501 close_path
? cmpl_ring_id
:
3502 INVALID_HW_RING_ID
);
3503 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
3504 bp
->grp_info
[grp_idx
].agg_fw_ring_id
=
3509 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3510 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3511 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3512 struct bnxt_ring_struct
*ring
= &cpr
->cp_ring_struct
;
3514 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
3515 hwrm_ring_free_send_msg(bp
, ring
,
3516 RING_FREE_REQ_RING_TYPE_CMPL
,
3517 INVALID_HW_RING_ID
);
3518 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
3519 bp
->grp_info
[i
].cp_fw_ring_id
= INVALID_HW_RING_ID
;
3524 static void bnxt_hwrm_set_coal_params(struct bnxt
*bp
, u32 max_bufs
,
3525 u32 buf_tmrs
, u16 flags
,
3526 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input
*req
)
3528 req
->flags
= cpu_to_le16(flags
);
3529 req
->num_cmpl_dma_aggr
= cpu_to_le16((u16
)max_bufs
);
3530 req
->num_cmpl_dma_aggr_during_int
= cpu_to_le16(max_bufs
>> 16);
3531 req
->cmpl_aggr_dma_tmr
= cpu_to_le16((u16
)buf_tmrs
);
3532 req
->cmpl_aggr_dma_tmr_during_int
= cpu_to_le16(buf_tmrs
>> 16);
3533 /* Minimum time between 2 interrupts set to buf_tmr x 2 */
3534 req
->int_lat_tmr_min
= cpu_to_le16((u16
)buf_tmrs
* 2);
3535 req
->int_lat_tmr_max
= cpu_to_le16((u16
)buf_tmrs
* 4);
3536 req
->num_cmpl_aggr_int
= cpu_to_le16((u16
)max_bufs
* 4);
3539 int bnxt_hwrm_set_coal(struct bnxt
*bp
)
3542 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req
= {0};
3543 u16 max_buf
, max_buf_irq
;
3544 u16 buf_tmr
, buf_tmr_irq
;
3547 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS
,
3550 /* Each rx completion (2 records) should be DMAed immediately.
3551 * DMA 1/4 of the completion buffers at a time.
3553 max_buf
= min_t(u16
, bp
->rx_coal_bufs
/ 4, 2);
3554 /* max_buf must not be zero */
3555 max_buf
= clamp_t(u16
, max_buf
, 1, 63);
3556 max_buf_irq
= clamp_t(u16
, bp
->rx_coal_bufs_irq
, 1, 63);
3557 buf_tmr
= BNXT_USEC_TO_COAL_TIMER(bp
->rx_coal_ticks
);
3558 /* buf timer set to 1/4 of interrupt timer */
3559 buf_tmr
= max_t(u16
, buf_tmr
/ 4, 1);
3560 buf_tmr_irq
= BNXT_USEC_TO_COAL_TIMER(bp
->rx_coal_ticks_irq
);
3561 buf_tmr_irq
= max_t(u16
, buf_tmr_irq
, 1);
3563 flags
= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET
;
3565 /* RING_IDLE generates more IRQs for lower latency. Enable it only
3566 * if coal_ticks is less than 25 us.
3568 if (bp
->rx_coal_ticks
< 25)
3569 flags
|= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE
;
3571 bnxt_hwrm_set_coal_params(bp
, max_buf_irq
<< 16 | max_buf
,
3572 buf_tmr_irq
<< 16 | buf_tmr
, flags
, &req
);
3574 mutex_lock(&bp
->hwrm_cmd_lock
);
3575 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3576 req
.ring_id
= cpu_to_le16(bp
->grp_info
[i
].cp_fw_ring_id
);
3578 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3583 mutex_unlock(&bp
->hwrm_cmd_lock
);
3587 static int bnxt_hwrm_stat_ctx_free(struct bnxt
*bp
)
3590 struct hwrm_stat_ctx_free_input req
= {0};
3595 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_STAT_CTX_FREE
, -1, -1);
3597 mutex_lock(&bp
->hwrm_cmd_lock
);
3598 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3599 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3600 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3602 if (cpr
->hw_stats_ctx_id
!= INVALID_STATS_CTX_ID
) {
3603 req
.stat_ctx_id
= cpu_to_le32(cpr
->hw_stats_ctx_id
);
3605 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3610 cpr
->hw_stats_ctx_id
= INVALID_STATS_CTX_ID
;
3613 mutex_unlock(&bp
->hwrm_cmd_lock
);
3617 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt
*bp
)
3620 struct hwrm_stat_ctx_alloc_input req
= {0};
3621 struct hwrm_stat_ctx_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3623 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_STAT_CTX_ALLOC
, -1, -1);
3625 req
.update_period_ms
= cpu_to_le32(1000);
3627 mutex_lock(&bp
->hwrm_cmd_lock
);
3628 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3629 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3630 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3632 req
.stats_dma_addr
= cpu_to_le64(cpr
->hw_stats_map
);
3634 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3639 cpr
->hw_stats_ctx_id
= le32_to_cpu(resp
->stat_ctx_id
);
3641 bp
->grp_info
[i
].fw_stats_ctx
= cpr
->hw_stats_ctx_id
;
3643 mutex_unlock(&bp
->hwrm_cmd_lock
);
3647 int bnxt_hwrm_func_qcaps(struct bnxt
*bp
)
3650 struct hwrm_func_qcaps_input req
= {0};
3651 struct hwrm_func_qcaps_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3653 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_QCAPS
, -1, -1);
3654 req
.fid
= cpu_to_le16(0xffff);
3656 mutex_lock(&bp
->hwrm_cmd_lock
);
3657 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3659 goto hwrm_func_qcaps_exit
;
3662 struct bnxt_pf_info
*pf
= &bp
->pf
;
3664 pf
->fw_fid
= le16_to_cpu(resp
->fid
);
3665 pf
->port_id
= le16_to_cpu(resp
->port_id
);
3666 memcpy(pf
->mac_addr
, resp
->perm_mac_address
, ETH_ALEN
);
3667 memcpy(bp
->dev
->dev_addr
, pf
->mac_addr
, ETH_ALEN
);
3668 pf
->max_rsscos_ctxs
= le16_to_cpu(resp
->max_rsscos_ctx
);
3669 pf
->max_cp_rings
= le16_to_cpu(resp
->max_cmpl_rings
);
3670 pf
->max_tx_rings
= le16_to_cpu(resp
->max_tx_rings
);
3671 pf
->max_rx_rings
= le16_to_cpu(resp
->max_rx_rings
);
3672 pf
->max_hw_ring_grps
= le32_to_cpu(resp
->max_hw_ring_grps
);
3673 if (!pf
->max_hw_ring_grps
)
3674 pf
->max_hw_ring_grps
= pf
->max_tx_rings
;
3675 pf
->max_l2_ctxs
= le16_to_cpu(resp
->max_l2_ctxs
);
3676 pf
->max_vnics
= le16_to_cpu(resp
->max_vnics
);
3677 pf
->max_stat_ctxs
= le16_to_cpu(resp
->max_stat_ctx
);
3678 pf
->first_vf_id
= le16_to_cpu(resp
->first_vf_id
);
3679 pf
->max_vfs
= le16_to_cpu(resp
->max_vfs
);
3680 pf
->max_encap_records
= le32_to_cpu(resp
->max_encap_records
);
3681 pf
->max_decap_records
= le32_to_cpu(resp
->max_decap_records
);
3682 pf
->max_tx_em_flows
= le32_to_cpu(resp
->max_tx_em_flows
);
3683 pf
->max_tx_wm_flows
= le32_to_cpu(resp
->max_tx_wm_flows
);
3684 pf
->max_rx_em_flows
= le32_to_cpu(resp
->max_rx_em_flows
);
3685 pf
->max_rx_wm_flows
= le32_to_cpu(resp
->max_rx_wm_flows
);
3687 #ifdef CONFIG_BNXT_SRIOV
3688 struct bnxt_vf_info
*vf
= &bp
->vf
;
3690 vf
->fw_fid
= le16_to_cpu(resp
->fid
);
3691 memcpy(vf
->mac_addr
, resp
->perm_mac_address
, ETH_ALEN
);
3692 if (is_valid_ether_addr(vf
->mac_addr
))
3693 /* overwrite netdev dev_adr with admin VF MAC */
3694 memcpy(bp
->dev
->dev_addr
, vf
->mac_addr
, ETH_ALEN
);
3696 random_ether_addr(bp
->dev
->dev_addr
);
3698 vf
->max_rsscos_ctxs
= le16_to_cpu(resp
->max_rsscos_ctx
);
3699 vf
->max_cp_rings
= le16_to_cpu(resp
->max_cmpl_rings
);
3700 vf
->max_tx_rings
= le16_to_cpu(resp
->max_tx_rings
);
3701 vf
->max_rx_rings
= le16_to_cpu(resp
->max_rx_rings
);
3702 vf
->max_hw_ring_grps
= le32_to_cpu(resp
->max_hw_ring_grps
);
3703 if (!vf
->max_hw_ring_grps
)
3704 vf
->max_hw_ring_grps
= vf
->max_tx_rings
;
3705 vf
->max_l2_ctxs
= le16_to_cpu(resp
->max_l2_ctxs
);
3706 vf
->max_vnics
= le16_to_cpu(resp
->max_vnics
);
3707 vf
->max_stat_ctxs
= le16_to_cpu(resp
->max_stat_ctx
);
3711 bp
->tx_push_thresh
= 0;
3713 cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED
))
3714 bp
->tx_push_thresh
= BNXT_TX_PUSH_THRESH
;
3716 hwrm_func_qcaps_exit
:
3717 mutex_unlock(&bp
->hwrm_cmd_lock
);
3721 static int bnxt_hwrm_func_reset(struct bnxt
*bp
)
3723 struct hwrm_func_reset_input req
= {0};
3725 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_RESET
, -1, -1);
3728 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_RESET_TIMEOUT
);
3731 static int bnxt_hwrm_queue_qportcfg(struct bnxt
*bp
)
3734 struct hwrm_queue_qportcfg_input req
= {0};
3735 struct hwrm_queue_qportcfg_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3738 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_QUEUE_QPORTCFG
, -1, -1);
3740 mutex_lock(&bp
->hwrm_cmd_lock
);
3741 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3745 if (!resp
->max_configurable_queues
) {
3749 bp
->max_tc
= resp
->max_configurable_queues
;
3750 if (bp
->max_tc
> BNXT_MAX_QUEUE
)
3751 bp
->max_tc
= BNXT_MAX_QUEUE
;
3753 qptr
= &resp
->queue_id0
;
3754 for (i
= 0; i
< bp
->max_tc
; i
++) {
3755 bp
->q_info
[i
].queue_id
= *qptr
++;
3756 bp
->q_info
[i
].queue_profile
= *qptr
++;
3760 mutex_unlock(&bp
->hwrm_cmd_lock
);
3764 static int bnxt_hwrm_ver_get(struct bnxt
*bp
)
3767 struct hwrm_ver_get_input req
= {0};
3768 struct hwrm_ver_get_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3770 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VER_GET
, -1, -1);
3771 req
.hwrm_intf_maj
= HWRM_VERSION_MAJOR
;
3772 req
.hwrm_intf_min
= HWRM_VERSION_MINOR
;
3773 req
.hwrm_intf_upd
= HWRM_VERSION_UPDATE
;
3774 mutex_lock(&bp
->hwrm_cmd_lock
);
3775 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3777 goto hwrm_ver_get_exit
;
3779 memcpy(&bp
->ver_resp
, resp
, sizeof(struct hwrm_ver_get_output
));
3781 if (resp
->hwrm_intf_maj
< 1) {
3782 netdev_warn(bp
->dev
, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
3783 resp
->hwrm_intf_maj
, resp
->hwrm_intf_min
,
3784 resp
->hwrm_intf_upd
);
3785 netdev_warn(bp
->dev
, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
3787 snprintf(bp
->fw_ver_str
, BC_HWRM_STR_LEN
, "bc %d.%d.%d rm %d.%d.%d",
3788 resp
->hwrm_fw_maj
, resp
->hwrm_fw_min
, resp
->hwrm_fw_bld
,
3789 resp
->hwrm_intf_maj
, resp
->hwrm_intf_min
, resp
->hwrm_intf_upd
);
3792 mutex_unlock(&bp
->hwrm_cmd_lock
);
3796 static void bnxt_hwrm_free_tunnel_ports(struct bnxt
*bp
)
3798 if (bp
->vxlan_port_cnt
) {
3799 bnxt_hwrm_tunnel_dst_port_free(
3800 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
);
3802 bp
->vxlan_port_cnt
= 0;
3803 if (bp
->nge_port_cnt
) {
3804 bnxt_hwrm_tunnel_dst_port_free(
3805 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
);
3807 bp
->nge_port_cnt
= 0;
3810 static int bnxt_set_tpa(struct bnxt
*bp
, bool set_tpa
)
3816 tpa_flags
= bp
->flags
& BNXT_FLAG_TPA
;
3817 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
3818 rc
= bnxt_hwrm_vnic_set_tpa(bp
, i
, tpa_flags
);
3820 netdev_err(bp
->dev
, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
3828 static void bnxt_hwrm_clear_vnic_rss(struct bnxt
*bp
)
3832 for (i
= 0; i
< bp
->nr_vnics
; i
++)
3833 bnxt_hwrm_vnic_set_rss(bp
, i
, false);
3836 static void bnxt_hwrm_resource_free(struct bnxt
*bp
, bool close_path
,
3839 if (bp
->vnic_info
) {
3840 bnxt_hwrm_clear_vnic_filter(bp
);
3841 /* clear all RSS setting before free vnic ctx */
3842 bnxt_hwrm_clear_vnic_rss(bp
);
3843 bnxt_hwrm_vnic_ctx_free(bp
);
3844 /* before free the vnic, undo the vnic tpa settings */
3845 if (bp
->flags
& BNXT_FLAG_TPA
)
3846 bnxt_set_tpa(bp
, false);
3847 bnxt_hwrm_vnic_free(bp
);
3849 bnxt_hwrm_ring_free(bp
, close_path
);
3850 bnxt_hwrm_ring_grp_free(bp
);
3852 bnxt_hwrm_stat_ctx_free(bp
);
3853 bnxt_hwrm_free_tunnel_ports(bp
);
3857 static int bnxt_setup_vnic(struct bnxt
*bp
, u16 vnic_id
)
3861 /* allocate context for vnic */
3862 rc
= bnxt_hwrm_vnic_ctx_alloc(bp
, vnic_id
);
3864 netdev_err(bp
->dev
, "hwrm vnic %d alloc failure rc: %x\n",
3866 goto vnic_setup_err
;
3868 bp
->rsscos_nr_ctxs
++;
3870 /* configure default vnic, ring grp */
3871 rc
= bnxt_hwrm_vnic_cfg(bp
, vnic_id
);
3873 netdev_err(bp
->dev
, "hwrm vnic %d cfg failure rc: %x\n",
3875 goto vnic_setup_err
;
3878 /* Enable RSS hashing on vnic */
3879 rc
= bnxt_hwrm_vnic_set_rss(bp
, vnic_id
, true);
3881 netdev_err(bp
->dev
, "hwrm vnic %d set rss failure rc: %x\n",
3883 goto vnic_setup_err
;
3886 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
) {
3887 rc
= bnxt_hwrm_vnic_set_hds(bp
, vnic_id
);
3889 netdev_err(bp
->dev
, "hwrm vnic %d set hds failure rc: %x\n",
3898 static int bnxt_alloc_rfs_vnics(struct bnxt
*bp
)
3900 #ifdef CONFIG_RFS_ACCEL
3903 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3904 u16 vnic_id
= i
+ 1;
3907 if (vnic_id
>= bp
->nr_vnics
)
3910 bp
->vnic_info
[vnic_id
].flags
|= BNXT_VNIC_RFS_FLAG
;
3911 rc
= bnxt_hwrm_vnic_alloc(bp
, vnic_id
, ring_id
, 1);
3913 netdev_err(bp
->dev
, "hwrm vnic %d alloc failure rc: %x\n",
3917 rc
= bnxt_setup_vnic(bp
, vnic_id
);
3927 static int bnxt_cfg_rx_mode(struct bnxt
*);
3929 static int bnxt_init_chip(struct bnxt
*bp
, bool irq_re_init
)
3934 rc
= bnxt_hwrm_stat_ctx_alloc(bp
);
3936 netdev_err(bp
->dev
, "hwrm stat ctx alloc failure rc: %x\n",
3942 rc
= bnxt_hwrm_ring_alloc(bp
);
3944 netdev_err(bp
->dev
, "hwrm ring alloc failure rc: %x\n", rc
);
3948 rc
= bnxt_hwrm_ring_grp_alloc(bp
);
3950 netdev_err(bp
->dev
, "hwrm_ring_grp alloc failure: %x\n", rc
);
3954 /* default vnic 0 */
3955 rc
= bnxt_hwrm_vnic_alloc(bp
, 0, 0, bp
->rx_nr_rings
);
3957 netdev_err(bp
->dev
, "hwrm vnic alloc failure rc: %x\n", rc
);
3961 rc
= bnxt_setup_vnic(bp
, 0);
3965 if (bp
->flags
& BNXT_FLAG_RFS
) {
3966 rc
= bnxt_alloc_rfs_vnics(bp
);
3971 if (bp
->flags
& BNXT_FLAG_TPA
) {
3972 rc
= bnxt_set_tpa(bp
, true);
3978 bnxt_update_vf_mac(bp
);
3980 /* Filter for default vnic 0 */
3981 rc
= bnxt_hwrm_set_vnic_filter(bp
, 0, 0, bp
->dev
->dev_addr
);
3983 netdev_err(bp
->dev
, "HWRM vnic filter failure rc: %x\n", rc
);
3986 bp
->vnic_info
[0].uc_filter_count
= 1;
3988 bp
->vnic_info
[0].rx_mask
= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST
;
3990 if ((bp
->dev
->flags
& IFF_PROMISC
) && BNXT_PF(bp
))
3991 bp
->vnic_info
[0].rx_mask
|=
3992 CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
;
3994 rc
= bnxt_cfg_rx_mode(bp
);
3998 rc
= bnxt_hwrm_set_coal(bp
);
4000 netdev_warn(bp
->dev
, "HWRM set coalescing failure rc: %x\n",
4006 bnxt_hwrm_resource_free(bp
, 0, true);
4011 static int bnxt_shutdown_nic(struct bnxt
*bp
, bool irq_re_init
)
4013 bnxt_hwrm_resource_free(bp
, 1, irq_re_init
);
4017 static int bnxt_init_nic(struct bnxt
*bp
, bool irq_re_init
)
4019 bnxt_init_rx_rings(bp
);
4020 bnxt_init_tx_rings(bp
);
4021 bnxt_init_ring_grps(bp
, irq_re_init
);
4022 bnxt_init_vnics(bp
);
4024 return bnxt_init_chip(bp
, irq_re_init
);
4027 static void bnxt_disable_int(struct bnxt
*bp
)
4034 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4035 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4036 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
4038 BNXT_CP_DB(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
4042 static void bnxt_enable_int(struct bnxt
*bp
)
4046 atomic_set(&bp
->intr_sem
, 0);
4047 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4048 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4049 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
4051 BNXT_CP_DB_REARM(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
4055 static int bnxt_set_real_num_queues(struct bnxt
*bp
)
4058 struct net_device
*dev
= bp
->dev
;
4060 rc
= netif_set_real_num_tx_queues(dev
, bp
->tx_nr_rings
);
4064 rc
= netif_set_real_num_rx_queues(dev
, bp
->rx_nr_rings
);
4068 #ifdef CONFIG_RFS_ACCEL
4069 if (bp
->flags
& BNXT_FLAG_RFS
)
4070 dev
->rx_cpu_rmap
= alloc_irq_cpu_rmap(bp
->rx_nr_rings
);
4076 static int bnxt_trim_rings(struct bnxt
*bp
, int *rx
, int *tx
, int max
,
4079 int _rx
= *rx
, _tx
= *tx
;
4082 *rx
= min_t(int, _rx
, max
);
4083 *tx
= min_t(int, _tx
, max
);
4088 while (_rx
+ _tx
> max
) {
4089 if (_rx
> _tx
&& _rx
> 1)
4100 static int bnxt_setup_msix(struct bnxt
*bp
)
4102 struct msix_entry
*msix_ent
;
4103 struct net_device
*dev
= bp
->dev
;
4104 int i
, total_vecs
, rc
= 0, min
= 1;
4105 const int len
= sizeof(bp
->irq_tbl
[0].name
);
4107 bp
->flags
&= ~BNXT_FLAG_USING_MSIX
;
4108 total_vecs
= bp
->cp_nr_rings
;
4110 msix_ent
= kcalloc(total_vecs
, sizeof(struct msix_entry
), GFP_KERNEL
);
4114 for (i
= 0; i
< total_vecs
; i
++) {
4115 msix_ent
[i
].entry
= i
;
4116 msix_ent
[i
].vector
= 0;
4119 if (!(bp
->flags
& BNXT_FLAG_SHARED_RINGS
))
4122 total_vecs
= pci_enable_msix_range(bp
->pdev
, msix_ent
, min
, total_vecs
);
4123 if (total_vecs
< 0) {
4125 goto msix_setup_exit
;
4128 bp
->irq_tbl
= kcalloc(total_vecs
, sizeof(struct bnxt_irq
), GFP_KERNEL
);
4132 /* Trim rings based upon num of vectors allocated */
4133 rc
= bnxt_trim_rings(bp
, &bp
->rx_nr_rings
, &bp
->tx_nr_rings
,
4134 total_vecs
, min
== 1);
4136 goto msix_setup_exit
;
4138 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
;
4139 tcs
= netdev_get_num_tc(dev
);
4141 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
/ tcs
;
4142 if (bp
->tx_nr_rings_per_tc
== 0) {
4143 netdev_reset_tc(dev
);
4144 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
;
4148 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
* tcs
;
4149 for (i
= 0; i
< tcs
; i
++) {
4150 count
= bp
->tx_nr_rings_per_tc
;
4152 netdev_set_tc_queue(dev
, i
, count
, off
);
4156 bp
->cp_nr_rings
= total_vecs
;
4158 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4161 bp
->irq_tbl
[i
].vector
= msix_ent
[i
].vector
;
4162 if (bp
->flags
& BNXT_FLAG_SHARED_RINGS
)
4164 else if (i
< bp
->rx_nr_rings
)
4169 snprintf(bp
->irq_tbl
[i
].name
, len
,
4170 "%s-%s-%d", dev
->name
, attr
, i
);
4171 bp
->irq_tbl
[i
].handler
= bnxt_msix
;
4173 rc
= bnxt_set_real_num_queues(bp
);
4175 goto msix_setup_exit
;
4178 goto msix_setup_exit
;
4180 bp
->flags
|= BNXT_FLAG_USING_MSIX
;
4185 netdev_err(bp
->dev
, "bnxt_setup_msix err: %x\n", rc
);
4186 pci_disable_msix(bp
->pdev
);
4191 static int bnxt_setup_inta(struct bnxt
*bp
)
4194 const int len
= sizeof(bp
->irq_tbl
[0].name
);
4196 if (netdev_get_num_tc(bp
->dev
))
4197 netdev_reset_tc(bp
->dev
);
4199 bp
->irq_tbl
= kcalloc(1, sizeof(struct bnxt_irq
), GFP_KERNEL
);
4204 bp
->rx_nr_rings
= 1;
4205 bp
->tx_nr_rings
= 1;
4206 bp
->cp_nr_rings
= 1;
4207 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
;
4208 bp
->flags
|= BNXT_FLAG_SHARED_RINGS
;
4209 bp
->irq_tbl
[0].vector
= bp
->pdev
->irq
;
4210 snprintf(bp
->irq_tbl
[0].name
, len
,
4211 "%s-%s-%d", bp
->dev
->name
, "TxRx", 0);
4212 bp
->irq_tbl
[0].handler
= bnxt_inta
;
4213 rc
= bnxt_set_real_num_queues(bp
);
4217 static int bnxt_setup_int_mode(struct bnxt
*bp
)
4221 if (bp
->flags
& BNXT_FLAG_MSIX_CAP
)
4222 rc
= bnxt_setup_msix(bp
);
4224 if (!(bp
->flags
& BNXT_FLAG_USING_MSIX
)) {
4225 /* fallback to INTA */
4226 rc
= bnxt_setup_inta(bp
);
4231 static void bnxt_free_irq(struct bnxt
*bp
)
4233 struct bnxt_irq
*irq
;
4236 #ifdef CONFIG_RFS_ACCEL
4237 free_irq_cpu_rmap(bp
->dev
->rx_cpu_rmap
);
4238 bp
->dev
->rx_cpu_rmap
= NULL
;
4243 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4244 irq
= &bp
->irq_tbl
[i
];
4246 free_irq(irq
->vector
, bp
->bnapi
[i
]);
4249 if (bp
->flags
& BNXT_FLAG_USING_MSIX
)
4250 pci_disable_msix(bp
->pdev
);
4255 static int bnxt_request_irq(struct bnxt
*bp
)
4258 unsigned long flags
= 0;
4259 #ifdef CONFIG_RFS_ACCEL
4260 struct cpu_rmap
*rmap
= bp
->dev
->rx_cpu_rmap
;
4263 if (!(bp
->flags
& BNXT_FLAG_USING_MSIX
))
4264 flags
= IRQF_SHARED
;
4266 for (i
= 0, j
= 0; i
< bp
->cp_nr_rings
; i
++) {
4267 struct bnxt_irq
*irq
= &bp
->irq_tbl
[i
];
4268 #ifdef CONFIG_RFS_ACCEL
4269 if (rmap
&& bp
->bnapi
[i
]->rx_ring
) {
4270 rc
= irq_cpu_rmap_add(rmap
, irq
->vector
);
4272 netdev_warn(bp
->dev
, "failed adding irq rmap for ring %d\n",
4277 rc
= request_irq(irq
->vector
, irq
->handler
, flags
, irq
->name
,
4287 static void bnxt_del_napi(struct bnxt
*bp
)
4294 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4295 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4297 napi_hash_del(&bnapi
->napi
);
4298 netif_napi_del(&bnapi
->napi
);
4302 static void bnxt_init_napi(struct bnxt
*bp
)
4305 struct bnxt_napi
*bnapi
;
4307 if (bp
->flags
& BNXT_FLAG_USING_MSIX
) {
4308 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4309 bnapi
= bp
->bnapi
[i
];
4310 netif_napi_add(bp
->dev
, &bnapi
->napi
,
4314 bnapi
= bp
->bnapi
[0];
4315 netif_napi_add(bp
->dev
, &bnapi
->napi
, bnxt_poll
, 64);
4319 static void bnxt_disable_napi(struct bnxt
*bp
)
4326 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4327 napi_disable(&bp
->bnapi
[i
]->napi
);
4328 bnxt_disable_poll(bp
->bnapi
[i
]);
4332 static void bnxt_enable_napi(struct bnxt
*bp
)
4336 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4337 bnxt_enable_poll(bp
->bnapi
[i
]);
4338 napi_enable(&bp
->bnapi
[i
]->napi
);
4342 static void bnxt_tx_disable(struct bnxt
*bp
)
4345 struct bnxt_tx_ring_info
*txr
;
4346 struct netdev_queue
*txq
;
4349 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
4350 txr
= &bp
->tx_ring
[i
];
4351 txq
= netdev_get_tx_queue(bp
->dev
, i
);
4352 __netif_tx_lock(txq
, smp_processor_id());
4353 txr
->dev_state
= BNXT_DEV_STATE_CLOSING
;
4354 __netif_tx_unlock(txq
);
4357 /* Stop all TX queues */
4358 netif_tx_disable(bp
->dev
);
4359 netif_carrier_off(bp
->dev
);
4362 static void bnxt_tx_enable(struct bnxt
*bp
)
4365 struct bnxt_tx_ring_info
*txr
;
4366 struct netdev_queue
*txq
;
4368 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
4369 txr
= &bp
->tx_ring
[i
];
4370 txq
= netdev_get_tx_queue(bp
->dev
, i
);
4373 netif_tx_wake_all_queues(bp
->dev
);
4374 if (bp
->link_info
.link_up
)
4375 netif_carrier_on(bp
->dev
);
4378 static void bnxt_report_link(struct bnxt
*bp
)
4380 if (bp
->link_info
.link_up
) {
4382 const char *flow_ctrl
;
4385 netif_carrier_on(bp
->dev
);
4386 if (bp
->link_info
.duplex
== BNXT_LINK_DUPLEX_FULL
)
4390 if (bp
->link_info
.pause
== BNXT_LINK_PAUSE_BOTH
)
4391 flow_ctrl
= "ON - receive & transmit";
4392 else if (bp
->link_info
.pause
== BNXT_LINK_PAUSE_TX
)
4393 flow_ctrl
= "ON - transmit";
4394 else if (bp
->link_info
.pause
== BNXT_LINK_PAUSE_RX
)
4395 flow_ctrl
= "ON - receive";
4398 speed
= bnxt_fw_to_ethtool_speed(bp
->link_info
.link_speed
);
4399 netdev_info(bp
->dev
, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
4400 speed
, duplex
, flow_ctrl
);
4402 netif_carrier_off(bp
->dev
);
4403 netdev_err(bp
->dev
, "NIC Link is Down\n");
4407 static int bnxt_update_link(struct bnxt
*bp
, bool chng_link_state
)
4410 struct bnxt_link_info
*link_info
= &bp
->link_info
;
4411 struct hwrm_port_phy_qcfg_input req
= {0};
4412 struct hwrm_port_phy_qcfg_output
*resp
= bp
->hwrm_cmd_resp_addr
;
4413 u8 link_up
= link_info
->link_up
;
4415 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_QCFG
, -1, -1);
4417 mutex_lock(&bp
->hwrm_cmd_lock
);
4418 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4420 mutex_unlock(&bp
->hwrm_cmd_lock
);
4424 memcpy(&link_info
->phy_qcfg_resp
, resp
, sizeof(*resp
));
4425 link_info
->phy_link_status
= resp
->link
;
4426 link_info
->duplex
= resp
->duplex
;
4427 link_info
->pause
= resp
->pause
;
4428 link_info
->auto_mode
= resp
->auto_mode
;
4429 link_info
->auto_pause_setting
= resp
->auto_pause
;
4430 link_info
->force_pause_setting
= resp
->force_pause
;
4431 link_info
->duplex_setting
= resp
->duplex
;
4432 if (link_info
->phy_link_status
== BNXT_LINK_LINK
)
4433 link_info
->link_speed
= le16_to_cpu(resp
->link_speed
);
4435 link_info
->link_speed
= 0;
4436 link_info
->force_link_speed
= le16_to_cpu(resp
->force_link_speed
);
4437 link_info
->auto_link_speed
= le16_to_cpu(resp
->auto_link_speed
);
4438 link_info
->support_speeds
= le16_to_cpu(resp
->support_speeds
);
4439 link_info
->auto_link_speeds
= le16_to_cpu(resp
->auto_link_speed_mask
);
4440 link_info
->preemphasis
= le32_to_cpu(resp
->preemphasis
);
4441 link_info
->phy_ver
[0] = resp
->phy_maj
;
4442 link_info
->phy_ver
[1] = resp
->phy_min
;
4443 link_info
->phy_ver
[2] = resp
->phy_bld
;
4444 link_info
->media_type
= resp
->media_type
;
4445 link_info
->transceiver
= resp
->transceiver_type
;
4446 link_info
->phy_addr
= resp
->phy_addr
;
4448 /* TODO: need to add more logic to report VF link */
4449 if (chng_link_state
) {
4450 if (link_info
->phy_link_status
== BNXT_LINK_LINK
)
4451 link_info
->link_up
= 1;
4453 link_info
->link_up
= 0;
4454 if (link_up
!= link_info
->link_up
)
4455 bnxt_report_link(bp
);
4457 /* alwasy link down if not require to update link state */
4458 link_info
->link_up
= 0;
4460 mutex_unlock(&bp
->hwrm_cmd_lock
);
4465 bnxt_hwrm_set_pause_common(struct bnxt
*bp
, struct hwrm_port_phy_cfg_input
*req
)
4467 if (bp
->link_info
.autoneg
& BNXT_AUTONEG_FLOW_CTRL
) {
4468 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_RX
)
4469 req
->auto_pause
|= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX
;
4470 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_TX
)
4471 req
->auto_pause
|= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX
;
4473 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE
);
4475 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_RX
)
4476 req
->force_pause
|= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX
;
4477 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_TX
)
4478 req
->force_pause
|= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX
;
4480 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE
);
4484 static void bnxt_hwrm_set_link_common(struct bnxt
*bp
,
4485 struct hwrm_port_phy_cfg_input
*req
)
4487 u8 autoneg
= bp
->link_info
.autoneg
;
4488 u16 fw_link_speed
= bp
->link_info
.req_link_speed
;
4489 u32 advertising
= bp
->link_info
.advertising
;
4491 if (autoneg
& BNXT_AUTONEG_SPEED
) {
4493 PORT_PHY_CFG_REQ_AUTO_MODE_MASK
;
4495 req
->enables
|= cpu_to_le32(
4496 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK
);
4497 req
->auto_link_speed_mask
= cpu_to_le16(advertising
);
4499 req
->enables
|= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE
);
4501 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG
);
4503 req
->force_link_speed
= cpu_to_le16(fw_link_speed
);
4504 req
->flags
|= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE
);
4507 /* currently don't support half duplex */
4508 req
->auto_duplex
= PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL
;
4509 req
->enables
|= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX
);
4510 /* tell chimp that the setting takes effect immediately */
4511 req
->flags
|= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY
);
4514 int bnxt_hwrm_set_pause(struct bnxt
*bp
)
4516 struct hwrm_port_phy_cfg_input req
= {0};
4519 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_CFG
, -1, -1);
4520 bnxt_hwrm_set_pause_common(bp
, &req
);
4522 if ((bp
->link_info
.autoneg
& BNXT_AUTONEG_FLOW_CTRL
) ||
4523 bp
->link_info
.force_link_chng
)
4524 bnxt_hwrm_set_link_common(bp
, &req
);
4526 mutex_lock(&bp
->hwrm_cmd_lock
);
4527 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4528 if (!rc
&& !(bp
->link_info
.autoneg
& BNXT_AUTONEG_FLOW_CTRL
)) {
4529 /* since changing of pause setting doesn't trigger any link
4530 * change event, the driver needs to update the current pause
4531 * result upon successfully return of the phy_cfg command
4533 bp
->link_info
.pause
=
4534 bp
->link_info
.force_pause_setting
= bp
->link_info
.req_flow_ctrl
;
4535 bp
->link_info
.auto_pause_setting
= 0;
4536 if (!bp
->link_info
.force_link_chng
)
4537 bnxt_report_link(bp
);
4539 bp
->link_info
.force_link_chng
= false;
4540 mutex_unlock(&bp
->hwrm_cmd_lock
);
4544 int bnxt_hwrm_set_link_setting(struct bnxt
*bp
, bool set_pause
)
4546 struct hwrm_port_phy_cfg_input req
= {0};
4548 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_CFG
, -1, -1);
4550 bnxt_hwrm_set_pause_common(bp
, &req
);
4552 bnxt_hwrm_set_link_common(bp
, &req
);
4553 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4556 static int bnxt_update_phy_setting(struct bnxt
*bp
)
4559 bool update_link
= false;
4560 bool update_pause
= false;
4561 struct bnxt_link_info
*link_info
= &bp
->link_info
;
4563 rc
= bnxt_update_link(bp
, true);
4565 netdev_err(bp
->dev
, "failed to update link (rc: %x)\n",
4569 if ((link_info
->autoneg
& BNXT_AUTONEG_FLOW_CTRL
) &&
4570 link_info
->auto_pause_setting
!= link_info
->req_flow_ctrl
)
4571 update_pause
= true;
4572 if (!(link_info
->autoneg
& BNXT_AUTONEG_FLOW_CTRL
) &&
4573 link_info
->force_pause_setting
!= link_info
->req_flow_ctrl
)
4574 update_pause
= true;
4575 if (!(link_info
->autoneg
& BNXT_AUTONEG_SPEED
)) {
4576 if (BNXT_AUTO_MODE(link_info
->auto_mode
))
4578 if (link_info
->req_link_speed
!= link_info
->force_link_speed
)
4580 if (link_info
->req_duplex
!= link_info
->duplex_setting
)
4583 if (link_info
->auto_mode
== BNXT_LINK_AUTO_NONE
)
4585 if (link_info
->advertising
!= link_info
->auto_link_speeds
)
4590 rc
= bnxt_hwrm_set_link_setting(bp
, update_pause
);
4591 else if (update_pause
)
4592 rc
= bnxt_hwrm_set_pause(bp
);
4594 netdev_err(bp
->dev
, "failed to update phy setting (rc: %x)\n",
4602 /* Common routine to pre-map certain register block to different GRC window.
4603 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
4604 * in PF and 3 windows in VF that can be customized to map in different
4607 static void bnxt_preset_reg_win(struct bnxt
*bp
)
4610 /* CAG registers map to GRC window #4 */
4611 writel(BNXT_CAG_REG_BASE
,
4612 bp
->bar0
+ BNXT_GRCPF_REG_WINDOW_BASE_OUT
+ 12);
4616 static int __bnxt_open_nic(struct bnxt
*bp
, bool irq_re_init
, bool link_re_init
)
4620 bnxt_preset_reg_win(bp
);
4621 netif_carrier_off(bp
->dev
);
4623 rc
= bnxt_setup_int_mode(bp
);
4625 netdev_err(bp
->dev
, "bnxt_setup_int_mode err: %x\n",
4630 if ((bp
->flags
& BNXT_FLAG_RFS
) &&
4631 !(bp
->flags
& BNXT_FLAG_USING_MSIX
)) {
4632 /* disable RFS if falling back to INTA */
4633 bp
->dev
->hw_features
&= ~NETIF_F_NTUPLE
;
4634 bp
->flags
&= ~BNXT_FLAG_RFS
;
4637 rc
= bnxt_alloc_mem(bp
, irq_re_init
);
4639 netdev_err(bp
->dev
, "bnxt_alloc_mem err: %x\n", rc
);
4640 goto open_err_free_mem
;
4645 rc
= bnxt_request_irq(bp
);
4647 netdev_err(bp
->dev
, "bnxt_request_irq err: %x\n", rc
);
4652 bnxt_enable_napi(bp
);
4654 rc
= bnxt_init_nic(bp
, irq_re_init
);
4656 netdev_err(bp
->dev
, "bnxt_init_nic err: %x\n", rc
);
4661 rc
= bnxt_update_phy_setting(bp
);
4663 netdev_warn(bp
->dev
, "failed to update phy settings\n");
4667 #if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE)
4668 vxlan_get_rx_port(bp
->dev
);
4670 if (!bnxt_hwrm_tunnel_dst_port_alloc(
4672 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
))
4673 bp
->nge_port_cnt
= 1;
4676 set_bit(BNXT_STATE_OPEN
, &bp
->state
);
4677 bnxt_enable_int(bp
);
4678 /* Enable TX queues */
4680 mod_timer(&bp
->timer
, jiffies
+ bp
->current_interval
);
4681 bnxt_update_link(bp
, true);
4686 bnxt_disable_napi(bp
);
4692 bnxt_free_mem(bp
, true);
4696 /* rtnl_lock held */
4697 int bnxt_open_nic(struct bnxt
*bp
, bool irq_re_init
, bool link_re_init
)
4701 rc
= __bnxt_open_nic(bp
, irq_re_init
, link_re_init
);
4703 netdev_err(bp
->dev
, "nic open fail (rc: %x)\n", rc
);
4709 static int bnxt_open(struct net_device
*dev
)
4711 struct bnxt
*bp
= netdev_priv(dev
);
4714 rc
= bnxt_hwrm_func_reset(bp
);
4716 netdev_err(bp
->dev
, "hwrm chip reset failure rc: %x\n",
4721 return __bnxt_open_nic(bp
, true, true);
4724 static void bnxt_disable_int_sync(struct bnxt
*bp
)
4728 atomic_inc(&bp
->intr_sem
);
4729 if (!netif_running(bp
->dev
))
4732 bnxt_disable_int(bp
);
4733 for (i
= 0; i
< bp
->cp_nr_rings
; i
++)
4734 synchronize_irq(bp
->irq_tbl
[i
].vector
);
4737 int bnxt_close_nic(struct bnxt
*bp
, bool irq_re_init
, bool link_re_init
)
4741 #ifdef CONFIG_BNXT_SRIOV
4742 if (bp
->sriov_cfg
) {
4743 rc
= wait_event_interruptible_timeout(bp
->sriov_cfg_wait
,
4745 BNXT_SRIOV_CFG_WAIT_TMO
);
4747 netdev_warn(bp
->dev
, "timeout waiting for SRIOV config operation to complete!\n");
4750 /* Change device state to avoid TX queue wake up's */
4751 bnxt_tx_disable(bp
);
4753 clear_bit(BNXT_STATE_OPEN
, &bp
->state
);
4754 smp_mb__after_atomic();
4755 while (test_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
))
4758 /* Flush rings before disabling interrupts */
4759 bnxt_shutdown_nic(bp
, irq_re_init
);
4761 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
4763 bnxt_disable_napi(bp
);
4764 bnxt_disable_int_sync(bp
);
4765 del_timer_sync(&bp
->timer
);
4772 bnxt_free_mem(bp
, irq_re_init
);
4776 static int bnxt_close(struct net_device
*dev
)
4778 struct bnxt
*bp
= netdev_priv(dev
);
4780 bnxt_close_nic(bp
, true, true);
4784 /* rtnl_lock held */
4785 static int bnxt_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
4791 if (!netif_running(dev
))
4798 if (!netif_running(dev
))
4810 static struct rtnl_link_stats64
*
4811 bnxt_get_stats64(struct net_device
*dev
, struct rtnl_link_stats64
*stats
)
4814 struct bnxt
*bp
= netdev_priv(dev
);
4816 memset(stats
, 0, sizeof(struct rtnl_link_stats64
));
4821 /* TODO check if we need to synchronize with bnxt_close path */
4822 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4823 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4824 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
4825 struct ctx_hw_stats
*hw_stats
= cpr
->hw_stats
;
4827 stats
->rx_packets
+= le64_to_cpu(hw_stats
->rx_ucast_pkts
);
4828 stats
->rx_packets
+= le64_to_cpu(hw_stats
->rx_mcast_pkts
);
4829 stats
->rx_packets
+= le64_to_cpu(hw_stats
->rx_bcast_pkts
);
4831 stats
->tx_packets
+= le64_to_cpu(hw_stats
->tx_ucast_pkts
);
4832 stats
->tx_packets
+= le64_to_cpu(hw_stats
->tx_mcast_pkts
);
4833 stats
->tx_packets
+= le64_to_cpu(hw_stats
->tx_bcast_pkts
);
4835 stats
->rx_bytes
+= le64_to_cpu(hw_stats
->rx_ucast_bytes
);
4836 stats
->rx_bytes
+= le64_to_cpu(hw_stats
->rx_mcast_bytes
);
4837 stats
->rx_bytes
+= le64_to_cpu(hw_stats
->rx_bcast_bytes
);
4839 stats
->tx_bytes
+= le64_to_cpu(hw_stats
->tx_ucast_bytes
);
4840 stats
->tx_bytes
+= le64_to_cpu(hw_stats
->tx_mcast_bytes
);
4841 stats
->tx_bytes
+= le64_to_cpu(hw_stats
->tx_bcast_bytes
);
4843 stats
->rx_missed_errors
+=
4844 le64_to_cpu(hw_stats
->rx_discard_pkts
);
4846 stats
->multicast
+= le64_to_cpu(hw_stats
->rx_mcast_pkts
);
4848 stats
->tx_dropped
+= le64_to_cpu(hw_stats
->tx_drop_pkts
);
4854 static bool bnxt_mc_list_updated(struct bnxt
*bp
, u32
*rx_mask
)
4856 struct net_device
*dev
= bp
->dev
;
4857 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
4858 struct netdev_hw_addr
*ha
;
4861 bool update
= false;
4864 netdev_for_each_mc_addr(ha
, dev
) {
4865 if (mc_count
>= BNXT_MAX_MC_ADDRS
) {
4866 *rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
;
4867 vnic
->mc_list_count
= 0;
4871 if (!ether_addr_equal(haddr
, vnic
->mc_list
+ off
)) {
4872 memcpy(vnic
->mc_list
+ off
, haddr
, ETH_ALEN
);
4879 *rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST
;
4881 if (mc_count
!= vnic
->mc_list_count
) {
4882 vnic
->mc_list_count
= mc_count
;
4888 static bool bnxt_uc_list_updated(struct bnxt
*bp
)
4890 struct net_device
*dev
= bp
->dev
;
4891 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
4892 struct netdev_hw_addr
*ha
;
4895 if (netdev_uc_count(dev
) != (vnic
->uc_filter_count
- 1))
4898 netdev_for_each_uc_addr(ha
, dev
) {
4899 if (!ether_addr_equal(ha
->addr
, vnic
->uc_list
+ off
))
4907 static void bnxt_set_rx_mode(struct net_device
*dev
)
4909 struct bnxt
*bp
= netdev_priv(dev
);
4910 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
4911 u32 mask
= vnic
->rx_mask
;
4912 bool mc_update
= false;
4915 if (!netif_running(dev
))
4918 mask
&= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
|
4919 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST
|
4920 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
);
4922 /* Only allow PF to be in promiscuous mode */
4923 if ((dev
->flags
& IFF_PROMISC
) && BNXT_PF(bp
))
4924 mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
;
4926 uc_update
= bnxt_uc_list_updated(bp
);
4928 if (dev
->flags
& IFF_ALLMULTI
) {
4929 mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
;
4930 vnic
->mc_list_count
= 0;
4932 mc_update
= bnxt_mc_list_updated(bp
, &mask
);
4935 if (mask
!= vnic
->rx_mask
|| uc_update
|| mc_update
) {
4936 vnic
->rx_mask
= mask
;
4938 set_bit(BNXT_RX_MASK_SP_EVENT
, &bp
->sp_event
);
4939 schedule_work(&bp
->sp_task
);
4943 static int bnxt_cfg_rx_mode(struct bnxt
*bp
)
4945 struct net_device
*dev
= bp
->dev
;
4946 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
4947 struct netdev_hw_addr
*ha
;
4951 netif_addr_lock_bh(dev
);
4952 uc_update
= bnxt_uc_list_updated(bp
);
4953 netif_addr_unlock_bh(dev
);
4958 mutex_lock(&bp
->hwrm_cmd_lock
);
4959 for (i
= 1; i
< vnic
->uc_filter_count
; i
++) {
4960 struct hwrm_cfa_l2_filter_free_input req
= {0};
4962 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_L2_FILTER_FREE
, -1,
4965 req
.l2_filter_id
= vnic
->fw_l2_filter_id
[i
];
4967 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
4970 mutex_unlock(&bp
->hwrm_cmd_lock
);
4972 vnic
->uc_filter_count
= 1;
4974 netif_addr_lock_bh(dev
);
4975 if (netdev_uc_count(dev
) > (BNXT_MAX_UC_ADDRS
- 1)) {
4976 vnic
->rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
;
4978 netdev_for_each_uc_addr(ha
, dev
) {
4979 memcpy(vnic
->uc_list
+ off
, ha
->addr
, ETH_ALEN
);
4981 vnic
->uc_filter_count
++;
4984 netif_addr_unlock_bh(dev
);
4986 for (i
= 1, off
= 0; i
< vnic
->uc_filter_count
; i
++, off
+= ETH_ALEN
) {
4987 rc
= bnxt_hwrm_set_vnic_filter(bp
, 0, i
, vnic
->uc_list
+ off
);
4989 netdev_err(bp
->dev
, "HWRM vnic filter failure rc: %x\n",
4991 vnic
->uc_filter_count
= i
;
4997 rc
= bnxt_hwrm_cfa_l2_set_rx_mask(bp
, 0);
4999 netdev_err(bp
->dev
, "HWRM cfa l2 rx mask failure rc: %x\n",
5005 static bool bnxt_rfs_capable(struct bnxt
*bp
)
5007 #ifdef CONFIG_RFS_ACCEL
5008 struct bnxt_pf_info
*pf
= &bp
->pf
;
5011 if (BNXT_VF(bp
) || !(bp
->flags
& BNXT_FLAG_MSIX_CAP
))
5014 vnics
= 1 + bp
->rx_nr_rings
;
5015 if (vnics
> pf
->max_rsscos_ctxs
|| vnics
> pf
->max_vnics
)
5024 static netdev_features_t
bnxt_fix_features(struct net_device
*dev
,
5025 netdev_features_t features
)
5027 struct bnxt
*bp
= netdev_priv(dev
);
5029 if (!bnxt_rfs_capable(bp
))
5030 features
&= ~NETIF_F_NTUPLE
;
5034 static int bnxt_set_features(struct net_device
*dev
, netdev_features_t features
)
5036 struct bnxt
*bp
= netdev_priv(dev
);
5037 u32 flags
= bp
->flags
;
5040 bool re_init
= false;
5041 bool update_tpa
= false;
5043 flags
&= ~BNXT_FLAG_ALL_CONFIG_FEATS
;
5044 if ((features
& NETIF_F_GRO
) && (bp
->pdev
->revision
> 0))
5045 flags
|= BNXT_FLAG_GRO
;
5046 if (features
& NETIF_F_LRO
)
5047 flags
|= BNXT_FLAG_LRO
;
5049 if (features
& NETIF_F_HW_VLAN_CTAG_RX
)
5050 flags
|= BNXT_FLAG_STRIP_VLAN
;
5052 if (features
& NETIF_F_NTUPLE
)
5053 flags
|= BNXT_FLAG_RFS
;
5055 changes
= flags
^ bp
->flags
;
5056 if (changes
& BNXT_FLAG_TPA
) {
5058 if ((bp
->flags
& BNXT_FLAG_TPA
) == 0 ||
5059 (flags
& BNXT_FLAG_TPA
) == 0)
5063 if (changes
& ~BNXT_FLAG_TPA
)
5066 if (flags
!= bp
->flags
) {
5067 u32 old_flags
= bp
->flags
;
5071 if (!test_bit(BNXT_STATE_OPEN
, &bp
->state
)) {
5073 bnxt_set_ring_params(bp
);
5078 bnxt_close_nic(bp
, false, false);
5080 bnxt_set_ring_params(bp
);
5082 return bnxt_open_nic(bp
, false, false);
5085 rc
= bnxt_set_tpa(bp
,
5086 (flags
& BNXT_FLAG_TPA
) ?
5089 bp
->flags
= old_flags
;
5095 static void bnxt_dump_tx_sw_state(struct bnxt_napi
*bnapi
)
5097 struct bnxt_tx_ring_info
*txr
= bnapi
->tx_ring
;
5098 int i
= bnapi
->index
;
5103 netdev_info(bnapi
->bp
->dev
, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
5104 i
, txr
->tx_ring_struct
.fw_ring_id
, txr
->tx_prod
,
5108 static void bnxt_dump_rx_sw_state(struct bnxt_napi
*bnapi
)
5110 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
5111 int i
= bnapi
->index
;
5116 netdev_info(bnapi
->bp
->dev
, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
5117 i
, rxr
->rx_ring_struct
.fw_ring_id
, rxr
->rx_prod
,
5118 rxr
->rx_agg_ring_struct
.fw_ring_id
, rxr
->rx_agg_prod
,
5119 rxr
->rx_sw_agg_prod
);
5122 static void bnxt_dump_cp_sw_state(struct bnxt_napi
*bnapi
)
5124 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
5125 int i
= bnapi
->index
;
5127 netdev_info(bnapi
->bp
->dev
, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
5128 i
, cpr
->cp_ring_struct
.fw_ring_id
, cpr
->cp_raw_cons
);
5131 static void bnxt_dbg_dump_states(struct bnxt
*bp
)
5134 struct bnxt_napi
*bnapi
;
5136 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
5137 bnapi
= bp
->bnapi
[i
];
5138 if (netif_msg_drv(bp
)) {
5139 bnxt_dump_tx_sw_state(bnapi
);
5140 bnxt_dump_rx_sw_state(bnapi
);
5141 bnxt_dump_cp_sw_state(bnapi
);
5146 static void bnxt_reset_task(struct bnxt
*bp
)
5148 bnxt_dbg_dump_states(bp
);
5149 if (netif_running(bp
->dev
)) {
5150 bnxt_close_nic(bp
, false, false);
5151 bnxt_open_nic(bp
, false, false);
5155 static void bnxt_tx_timeout(struct net_device
*dev
)
5157 struct bnxt
*bp
= netdev_priv(dev
);
5159 netdev_err(bp
->dev
, "TX timeout detected, starting reset task!\n");
5160 set_bit(BNXT_RESET_TASK_SP_EVENT
, &bp
->sp_event
);
5161 schedule_work(&bp
->sp_task
);
5164 #ifdef CONFIG_NET_POLL_CONTROLLER
5165 static void bnxt_poll_controller(struct net_device
*dev
)
5167 struct bnxt
*bp
= netdev_priv(dev
);
5170 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
5171 struct bnxt_irq
*irq
= &bp
->irq_tbl
[i
];
5173 disable_irq(irq
->vector
);
5174 irq
->handler(irq
->vector
, bp
->bnapi
[i
]);
5175 enable_irq(irq
->vector
);
5180 static void bnxt_timer(unsigned long data
)
5182 struct bnxt
*bp
= (struct bnxt
*)data
;
5183 struct net_device
*dev
= bp
->dev
;
5185 if (!netif_running(dev
))
5188 if (atomic_read(&bp
->intr_sem
) != 0)
5189 goto bnxt_restart_timer
;
5192 mod_timer(&bp
->timer
, jiffies
+ bp
->current_interval
);
5195 static void bnxt_cfg_ntp_filters(struct bnxt
*);
5197 static void bnxt_sp_task(struct work_struct
*work
)
5199 struct bnxt
*bp
= container_of(work
, struct bnxt
, sp_task
);
5202 set_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
5203 smp_mb__after_atomic();
5204 if (!test_bit(BNXT_STATE_OPEN
, &bp
->state
)) {
5205 clear_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
5209 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT
, &bp
->sp_event
))
5210 bnxt_cfg_rx_mode(bp
);
5212 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT
, &bp
->sp_event
))
5213 bnxt_cfg_ntp_filters(bp
);
5214 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT
, &bp
->sp_event
)) {
5215 rc
= bnxt_update_link(bp
, true);
5217 netdev_err(bp
->dev
, "SP task can't update link (rc: %x)\n",
5220 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT
, &bp
->sp_event
))
5221 bnxt_hwrm_exec_fwd_req(bp
);
5222 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT
, &bp
->sp_event
)) {
5223 bnxt_hwrm_tunnel_dst_port_alloc(
5225 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
);
5227 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT
, &bp
->sp_event
)) {
5228 bnxt_hwrm_tunnel_dst_port_free(
5229 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
);
5231 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT
, &bp
->sp_event
)) {
5232 /* bnxt_reset_task() calls bnxt_close_nic() which waits
5233 * for BNXT_STATE_IN_SP_TASK to clear.
5235 clear_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
5237 bnxt_reset_task(bp
);
5238 set_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
5242 smp_mb__before_atomic();
5243 clear_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
5246 static int bnxt_init_board(struct pci_dev
*pdev
, struct net_device
*dev
)
5249 struct bnxt
*bp
= netdev_priv(dev
);
5251 SET_NETDEV_DEV(dev
, &pdev
->dev
);
5253 /* enable device (incl. PCI PM wakeup), and bus-mastering */
5254 rc
= pci_enable_device(pdev
);
5256 dev_err(&pdev
->dev
, "Cannot enable PCI device, aborting\n");
5260 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
5262 "Cannot find PCI device base address, aborting\n");
5264 goto init_err_disable
;
5267 rc
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
5269 dev_err(&pdev
->dev
, "Cannot obtain PCI resources, aborting\n");
5270 goto init_err_disable
;
5273 if (dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(64)) != 0 &&
5274 dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(32)) != 0) {
5275 dev_err(&pdev
->dev
, "System does not support DMA, aborting\n");
5276 goto init_err_disable
;
5279 pci_set_master(pdev
);
5284 bp
->bar0
= pci_ioremap_bar(pdev
, 0);
5286 dev_err(&pdev
->dev
, "Cannot map device registers, aborting\n");
5288 goto init_err_release
;
5291 bp
->bar1
= pci_ioremap_bar(pdev
, 2);
5293 dev_err(&pdev
->dev
, "Cannot map doorbell registers, aborting\n");
5295 goto init_err_release
;
5298 bp
->bar2
= pci_ioremap_bar(pdev
, 4);
5300 dev_err(&pdev
->dev
, "Cannot map bar4 registers, aborting\n");
5302 goto init_err_release
;
5305 INIT_WORK(&bp
->sp_task
, bnxt_sp_task
);
5307 spin_lock_init(&bp
->ntp_fltr_lock
);
5309 bp
->rx_ring_size
= BNXT_DEFAULT_RX_RING_SIZE
;
5310 bp
->tx_ring_size
= BNXT_DEFAULT_TX_RING_SIZE
;
5312 /* tick values in micro seconds */
5313 bp
->rx_coal_ticks
= 4;
5314 bp
->rx_coal_bufs
= 20;
5315 bp
->rx_coal_ticks_irq
= 1;
5316 bp
->rx_coal_bufs_irq
= 2;
5318 init_timer(&bp
->timer
);
5319 bp
->timer
.data
= (unsigned long)bp
;
5320 bp
->timer
.function
= bnxt_timer
;
5321 bp
->current_interval
= BNXT_TIMER_INTERVAL
;
5323 clear_bit(BNXT_STATE_OPEN
, &bp
->state
);
5329 pci_iounmap(pdev
, bp
->bar2
);
5334 pci_iounmap(pdev
, bp
->bar1
);
5339 pci_iounmap(pdev
, bp
->bar0
);
5343 pci_release_regions(pdev
);
5346 pci_disable_device(pdev
);
5352 /* rtnl_lock held */
5353 static int bnxt_change_mac_addr(struct net_device
*dev
, void *p
)
5355 struct sockaddr
*addr
= p
;
5356 struct bnxt
*bp
= netdev_priv(dev
);
5359 if (!is_valid_ether_addr(addr
->sa_data
))
5360 return -EADDRNOTAVAIL
;
5362 #ifdef CONFIG_BNXT_SRIOV
5363 if (BNXT_VF(bp
) && is_valid_ether_addr(bp
->vf
.mac_addr
))
5364 return -EADDRNOTAVAIL
;
5367 if (ether_addr_equal(addr
->sa_data
, dev
->dev_addr
))
5370 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
5371 if (netif_running(dev
)) {
5372 bnxt_close_nic(bp
, false, false);
5373 rc
= bnxt_open_nic(bp
, false, false);
5379 /* rtnl_lock held */
5380 static int bnxt_change_mtu(struct net_device
*dev
, int new_mtu
)
5382 struct bnxt
*bp
= netdev_priv(dev
);
5384 if (new_mtu
< 60 || new_mtu
> 9000)
5387 if (netif_running(dev
))
5388 bnxt_close_nic(bp
, false, false);
5391 bnxt_set_ring_params(bp
);
5393 if (netif_running(dev
))
5394 return bnxt_open_nic(bp
, false, false);
5399 static int bnxt_setup_tc(struct net_device
*dev
, u32 handle
, __be16 proto
,
5400 struct tc_to_netdev
*ntc
)
5402 struct bnxt
*bp
= netdev_priv(dev
);
5405 if (handle
!= TC_H_ROOT
|| ntc
->type
!= TC_SETUP_MQPRIO
)
5410 if (tc
> bp
->max_tc
) {
5411 netdev_err(dev
, "too many traffic classes requested: %d Max supported is %d\n",
5416 if (netdev_get_num_tc(dev
) == tc
)
5420 int max_rx_rings
, max_tx_rings
, rc
;
5423 if (bp
->flags
& BNXT_FLAG_SHARED_RINGS
)
5426 rc
= bnxt_get_max_rings(bp
, &max_rx_rings
, &max_tx_rings
, sh
);
5427 if (rc
|| bp
->tx_nr_rings_per_tc
* tc
> max_tx_rings
)
5431 /* Needs to close the device and do hw resource re-allocations */
5432 if (netif_running(bp
->dev
))
5433 bnxt_close_nic(bp
, true, false);
5436 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
* tc
;
5437 netdev_set_num_tc(dev
, tc
);
5439 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
;
5440 netdev_reset_tc(dev
);
5442 bp
->cp_nr_rings
= max_t(int, bp
->tx_nr_rings
, bp
->rx_nr_rings
);
5443 bp
->num_stat_ctxs
= bp
->cp_nr_rings
;
5445 if (netif_running(bp
->dev
))
5446 return bnxt_open_nic(bp
, true, false);
5451 #ifdef CONFIG_RFS_ACCEL
5452 static bool bnxt_fltr_match(struct bnxt_ntuple_filter
*f1
,
5453 struct bnxt_ntuple_filter
*f2
)
5455 struct flow_keys
*keys1
= &f1
->fkeys
;
5456 struct flow_keys
*keys2
= &f2
->fkeys
;
5458 if (keys1
->addrs
.v4addrs
.src
== keys2
->addrs
.v4addrs
.src
&&
5459 keys1
->addrs
.v4addrs
.dst
== keys2
->addrs
.v4addrs
.dst
&&
5460 keys1
->ports
.ports
== keys2
->ports
.ports
&&
5461 keys1
->basic
.ip_proto
== keys2
->basic
.ip_proto
&&
5462 keys1
->basic
.n_proto
== keys2
->basic
.n_proto
&&
5463 ether_addr_equal(f1
->src_mac_addr
, f2
->src_mac_addr
))
5469 static int bnxt_rx_flow_steer(struct net_device
*dev
, const struct sk_buff
*skb
,
5470 u16 rxq_index
, u32 flow_id
)
5472 struct bnxt
*bp
= netdev_priv(dev
);
5473 struct bnxt_ntuple_filter
*fltr
, *new_fltr
;
5474 struct flow_keys
*fkeys
;
5475 struct ethhdr
*eth
= (struct ethhdr
*)skb_mac_header(skb
);
5476 int rc
= 0, idx
, bit_id
;
5477 struct hlist_head
*head
;
5479 if (skb
->encapsulation
)
5480 return -EPROTONOSUPPORT
;
5482 new_fltr
= kzalloc(sizeof(*new_fltr
), GFP_ATOMIC
);
5486 fkeys
= &new_fltr
->fkeys
;
5487 if (!skb_flow_dissect_flow_keys(skb
, fkeys
, 0)) {
5488 rc
= -EPROTONOSUPPORT
;
5492 if ((fkeys
->basic
.n_proto
!= htons(ETH_P_IP
)) ||
5493 ((fkeys
->basic
.ip_proto
!= IPPROTO_TCP
) &&
5494 (fkeys
->basic
.ip_proto
!= IPPROTO_UDP
))) {
5495 rc
= -EPROTONOSUPPORT
;
5499 memcpy(new_fltr
->src_mac_addr
, eth
->h_source
, ETH_ALEN
);
5501 idx
= skb_get_hash_raw(skb
) & BNXT_NTP_FLTR_HASH_MASK
;
5502 head
= &bp
->ntp_fltr_hash_tbl
[idx
];
5504 hlist_for_each_entry_rcu(fltr
, head
, hash
) {
5505 if (bnxt_fltr_match(fltr
, new_fltr
)) {
5513 spin_lock_bh(&bp
->ntp_fltr_lock
);
5514 bit_id
= bitmap_find_free_region(bp
->ntp_fltr_bmap
,
5515 BNXT_NTP_FLTR_MAX_FLTR
, 0);
5517 spin_unlock_bh(&bp
->ntp_fltr_lock
);
5522 new_fltr
->sw_id
= (u16
)bit_id
;
5523 new_fltr
->flow_id
= flow_id
;
5524 new_fltr
->rxq
= rxq_index
;
5525 hlist_add_head_rcu(&new_fltr
->hash
, head
);
5526 bp
->ntp_fltr_count
++;
5527 spin_unlock_bh(&bp
->ntp_fltr_lock
);
5529 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT
, &bp
->sp_event
);
5530 schedule_work(&bp
->sp_task
);
5532 return new_fltr
->sw_id
;
5539 static void bnxt_cfg_ntp_filters(struct bnxt
*bp
)
5543 for (i
= 0; i
< BNXT_NTP_FLTR_HASH_SIZE
; i
++) {
5544 struct hlist_head
*head
;
5545 struct hlist_node
*tmp
;
5546 struct bnxt_ntuple_filter
*fltr
;
5549 head
= &bp
->ntp_fltr_hash_tbl
[i
];
5550 hlist_for_each_entry_safe(fltr
, tmp
, head
, hash
) {
5553 if (test_bit(BNXT_FLTR_VALID
, &fltr
->state
)) {
5554 if (rps_may_expire_flow(bp
->dev
, fltr
->rxq
,
5557 bnxt_hwrm_cfa_ntuple_filter_free(bp
,
5562 rc
= bnxt_hwrm_cfa_ntuple_filter_alloc(bp
,
5567 set_bit(BNXT_FLTR_VALID
, &fltr
->state
);
5571 spin_lock_bh(&bp
->ntp_fltr_lock
);
5572 hlist_del_rcu(&fltr
->hash
);
5573 bp
->ntp_fltr_count
--;
5574 spin_unlock_bh(&bp
->ntp_fltr_lock
);
5576 clear_bit(fltr
->sw_id
, bp
->ntp_fltr_bmap
);
5581 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT
, &bp
->sp_event
))
5582 netdev_info(bp
->dev
, "Receive PF driver unload event!");
5587 static void bnxt_cfg_ntp_filters(struct bnxt
*bp
)
5591 #endif /* CONFIG_RFS_ACCEL */
5593 static void bnxt_add_vxlan_port(struct net_device
*dev
, sa_family_t sa_family
,
5596 struct bnxt
*bp
= netdev_priv(dev
);
5598 if (!netif_running(dev
))
5601 if (sa_family
!= AF_INET6
&& sa_family
!= AF_INET
)
5604 if (bp
->vxlan_port_cnt
&& bp
->vxlan_port
!= port
)
5607 bp
->vxlan_port_cnt
++;
5608 if (bp
->vxlan_port_cnt
== 1) {
5609 bp
->vxlan_port
= port
;
5610 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT
, &bp
->sp_event
);
5611 schedule_work(&bp
->sp_task
);
5615 static void bnxt_del_vxlan_port(struct net_device
*dev
, sa_family_t sa_family
,
5618 struct bnxt
*bp
= netdev_priv(dev
);
5620 if (!netif_running(dev
))
5623 if (sa_family
!= AF_INET6
&& sa_family
!= AF_INET
)
5626 if (bp
->vxlan_port_cnt
&& bp
->vxlan_port
== port
) {
5627 bp
->vxlan_port_cnt
--;
5629 if (bp
->vxlan_port_cnt
== 0) {
5630 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT
, &bp
->sp_event
);
5631 schedule_work(&bp
->sp_task
);
5636 static const struct net_device_ops bnxt_netdev_ops
= {
5637 .ndo_open
= bnxt_open
,
5638 .ndo_start_xmit
= bnxt_start_xmit
,
5639 .ndo_stop
= bnxt_close
,
5640 .ndo_get_stats64
= bnxt_get_stats64
,
5641 .ndo_set_rx_mode
= bnxt_set_rx_mode
,
5642 .ndo_do_ioctl
= bnxt_ioctl
,
5643 .ndo_validate_addr
= eth_validate_addr
,
5644 .ndo_set_mac_address
= bnxt_change_mac_addr
,
5645 .ndo_change_mtu
= bnxt_change_mtu
,
5646 .ndo_fix_features
= bnxt_fix_features
,
5647 .ndo_set_features
= bnxt_set_features
,
5648 .ndo_tx_timeout
= bnxt_tx_timeout
,
5649 #ifdef CONFIG_BNXT_SRIOV
5650 .ndo_get_vf_config
= bnxt_get_vf_config
,
5651 .ndo_set_vf_mac
= bnxt_set_vf_mac
,
5652 .ndo_set_vf_vlan
= bnxt_set_vf_vlan
,
5653 .ndo_set_vf_rate
= bnxt_set_vf_bw
,
5654 .ndo_set_vf_link_state
= bnxt_set_vf_link_state
,
5655 .ndo_set_vf_spoofchk
= bnxt_set_vf_spoofchk
,
5657 #ifdef CONFIG_NET_POLL_CONTROLLER
5658 .ndo_poll_controller
= bnxt_poll_controller
,
5660 .ndo_setup_tc
= bnxt_setup_tc
,
5661 #ifdef CONFIG_RFS_ACCEL
5662 .ndo_rx_flow_steer
= bnxt_rx_flow_steer
,
5664 .ndo_add_vxlan_port
= bnxt_add_vxlan_port
,
5665 .ndo_del_vxlan_port
= bnxt_del_vxlan_port
,
5666 #ifdef CONFIG_NET_RX_BUSY_POLL
5667 .ndo_busy_poll
= bnxt_busy_poll
,
5671 static void bnxt_remove_one(struct pci_dev
*pdev
)
5673 struct net_device
*dev
= pci_get_drvdata(pdev
);
5674 struct bnxt
*bp
= netdev_priv(dev
);
5677 bnxt_sriov_disable(bp
);
5679 unregister_netdev(dev
);
5680 cancel_work_sync(&bp
->sp_task
);
5683 bnxt_hwrm_func_drv_unrgtr(bp
);
5684 bnxt_free_hwrm_resources(bp
);
5685 pci_iounmap(pdev
, bp
->bar2
);
5686 pci_iounmap(pdev
, bp
->bar1
);
5687 pci_iounmap(pdev
, bp
->bar0
);
5690 pci_release_regions(pdev
);
5691 pci_disable_device(pdev
);
5694 static int bnxt_probe_phy(struct bnxt
*bp
)
5697 struct bnxt_link_info
*link_info
= &bp
->link_info
;
5698 char phy_ver
[PHY_VER_STR_LEN
];
5700 rc
= bnxt_update_link(bp
, false);
5702 netdev_err(bp
->dev
, "Probe phy can't update link (rc: %x)\n",
5707 /*initialize the ethool setting copy with NVM settings */
5708 if (BNXT_AUTO_MODE(link_info
->auto_mode
)) {
5709 link_info
->autoneg
= BNXT_AUTONEG_SPEED
|
5710 BNXT_AUTONEG_FLOW_CTRL
;
5711 link_info
->advertising
= link_info
->auto_link_speeds
;
5712 link_info
->req_flow_ctrl
= link_info
->auto_pause_setting
;
5714 link_info
->req_link_speed
= link_info
->force_link_speed
;
5715 link_info
->req_duplex
= link_info
->duplex_setting
;
5716 link_info
->req_flow_ctrl
= link_info
->force_pause_setting
;
5718 snprintf(phy_ver
, PHY_VER_STR_LEN
, " ph %d.%d.%d",
5719 link_info
->phy_ver
[0],
5720 link_info
->phy_ver
[1],
5721 link_info
->phy_ver
[2]);
5722 strcat(bp
->fw_ver_str
, phy_ver
);
5726 static int bnxt_get_max_irq(struct pci_dev
*pdev
)
5730 if (!pdev
->msix_cap
)
5733 pci_read_config_word(pdev
, pdev
->msix_cap
+ PCI_MSIX_FLAGS
, &ctrl
);
5734 return (ctrl
& PCI_MSIX_FLAGS_QSIZE
) + 1;
5737 static void _bnxt_get_max_rings(struct bnxt
*bp
, int *max_rx
, int *max_tx
,
5740 int max_ring_grps
= 0;
5742 #ifdef CONFIG_BNXT_SRIOV
5744 *max_tx
= bp
->vf
.max_tx_rings
;
5745 *max_rx
= bp
->vf
.max_rx_rings
;
5746 *max_cp
= min_t(int, bp
->vf
.max_irqs
, bp
->vf
.max_cp_rings
);
5747 *max_cp
= min_t(int, *max_cp
, bp
->vf
.max_stat_ctxs
);
5748 max_ring_grps
= bp
->vf
.max_hw_ring_grps
;
5752 *max_tx
= bp
->pf
.max_tx_rings
;
5753 *max_rx
= bp
->pf
.max_rx_rings
;
5754 *max_cp
= min_t(int, bp
->pf
.max_irqs
, bp
->pf
.max_cp_rings
);
5755 *max_cp
= min_t(int, *max_cp
, bp
->pf
.max_stat_ctxs
);
5756 max_ring_grps
= bp
->pf
.max_hw_ring_grps
;
5759 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
)
5761 *max_rx
= min_t(int, *max_rx
, max_ring_grps
);
5764 int bnxt_get_max_rings(struct bnxt
*bp
, int *max_rx
, int *max_tx
, bool shared
)
5768 _bnxt_get_max_rings(bp
, &rx
, &tx
, &cp
);
5769 if (!rx
|| !tx
|| !cp
)
5774 return bnxt_trim_rings(bp
, max_rx
, max_tx
, cp
, shared
);
5777 static int bnxt_set_dflt_rings(struct bnxt
*bp
)
5779 int dflt_rings
, max_rx_rings
, max_tx_rings
, rc
;
5783 bp
->flags
|= BNXT_FLAG_SHARED_RINGS
;
5784 dflt_rings
= netif_get_num_default_rss_queues();
5785 rc
= bnxt_get_max_rings(bp
, &max_rx_rings
, &max_tx_rings
, sh
);
5788 bp
->rx_nr_rings
= min_t(int, dflt_rings
, max_rx_rings
);
5789 bp
->tx_nr_rings_per_tc
= min_t(int, dflt_rings
, max_tx_rings
);
5790 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
;
5791 bp
->cp_nr_rings
= sh
? max_t(int, bp
->tx_nr_rings
, bp
->rx_nr_rings
) :
5792 bp
->tx_nr_rings
+ bp
->rx_nr_rings
;
5793 bp
->num_stat_ctxs
= bp
->cp_nr_rings
;
5797 static int bnxt_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
5799 static int version_printed
;
5800 struct net_device
*dev
;
5804 if (version_printed
++ == 0)
5805 pr_info("%s", version
);
5807 max_irqs
= bnxt_get_max_irq(pdev
);
5808 dev
= alloc_etherdev_mq(sizeof(*bp
), max_irqs
);
5812 bp
= netdev_priv(dev
);
5814 if (bnxt_vf_pciid(ent
->driver_data
))
5815 bp
->flags
|= BNXT_FLAG_VF
;
5818 bp
->flags
|= BNXT_FLAG_MSIX_CAP
;
5820 rc
= bnxt_init_board(pdev
, dev
);
5824 dev
->netdev_ops
= &bnxt_netdev_ops
;
5825 dev
->watchdog_timeo
= BNXT_TX_TIMEOUT
;
5826 dev
->ethtool_ops
= &bnxt_ethtool_ops
;
5828 pci_set_drvdata(pdev
, dev
);
5830 dev
->hw_features
= NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
| NETIF_F_SG
|
5831 NETIF_F_TSO
| NETIF_F_TSO6
|
5832 NETIF_F_GSO_UDP_TUNNEL
| NETIF_F_GSO_GRE
|
5833 NETIF_F_GSO_IPIP
| NETIF_F_GSO_SIT
|
5835 NETIF_F_RXCSUM
| NETIF_F_LRO
| NETIF_F_GRO
;
5837 dev
->hw_enc_features
=
5838 NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
| NETIF_F_SG
|
5839 NETIF_F_TSO
| NETIF_F_TSO6
|
5840 NETIF_F_GSO_UDP_TUNNEL
| NETIF_F_GSO_GRE
|
5841 NETIF_F_GSO_IPIP
| NETIF_F_GSO_SIT
;
5842 dev
->vlan_features
= dev
->hw_features
| NETIF_F_HIGHDMA
;
5843 dev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_RX
| NETIF_F_HW_VLAN_CTAG_TX
|
5844 NETIF_F_HW_VLAN_STAG_RX
| NETIF_F_HW_VLAN_STAG_TX
;
5845 dev
->features
|= dev
->hw_features
| NETIF_F_HIGHDMA
;
5846 dev
->priv_flags
|= IFF_UNICAST_FLT
;
5848 #ifdef CONFIG_BNXT_SRIOV
5849 init_waitqueue_head(&bp
->sriov_cfg_wait
);
5851 rc
= bnxt_alloc_hwrm_resources(bp
);
5855 mutex_init(&bp
->hwrm_cmd_lock
);
5856 bnxt_hwrm_ver_get(bp
);
5858 rc
= bnxt_hwrm_func_drv_rgtr(bp
);
5862 /* Get the MAX capabilities for this function */
5863 rc
= bnxt_hwrm_func_qcaps(bp
);
5865 netdev_err(bp
->dev
, "hwrm query capability failure rc: %x\n",
5871 rc
= bnxt_hwrm_queue_qportcfg(bp
);
5873 netdev_err(bp
->dev
, "hwrm query qportcfg failure rc: %x\n",
5879 bnxt_set_tpa_flags(bp
);
5880 bnxt_set_ring_params(bp
);
5882 bp
->pf
.max_irqs
= max_irqs
;
5883 #if defined(CONFIG_BNXT_SRIOV)
5885 bp
->vf
.max_irqs
= max_irqs
;
5887 bnxt_set_dflt_rings(bp
);
5890 dev
->hw_features
|= NETIF_F_NTUPLE
;
5891 if (bnxt_rfs_capable(bp
)) {
5892 bp
->flags
|= BNXT_FLAG_RFS
;
5893 dev
->features
|= NETIF_F_NTUPLE
;
5897 if (dev
->hw_features
& NETIF_F_HW_VLAN_CTAG_RX
)
5898 bp
->flags
|= BNXT_FLAG_STRIP_VLAN
;
5900 rc
= bnxt_probe_phy(bp
);
5904 rc
= register_netdev(dev
);
5908 netdev_info(dev
, "%s found at mem %lx, node addr %pM\n",
5909 board_info
[ent
->driver_data
].name
,
5910 (long)pci_resource_start(pdev
, 0), dev
->dev_addr
);
5915 pci_iounmap(pdev
, bp
->bar0
);
5916 pci_release_regions(pdev
);
5917 pci_disable_device(pdev
);
5924 static struct pci_driver bnxt_pci_driver
= {
5925 .name
= DRV_MODULE_NAME
,
5926 .id_table
= bnxt_pci_tbl
,
5927 .probe
= bnxt_init_one
,
5928 .remove
= bnxt_remove_one
,
5929 #if defined(CONFIG_BNXT_SRIOV)
5930 .sriov_configure
= bnxt_sriov_configure
,
5934 module_pci_driver(bnxt_pci_driver
);