1 /* Broadcom NetXtreme-C/E network driver.
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2017 Broadcom Limited
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
11 #include <linux/module.h>
13 #include <linux/stringify.h>
14 #include <linux/kernel.h>
15 #include <linux/timer.h>
16 #include <linux/errno.h>
17 #include <linux/ioport.h>
18 #include <linux/slab.h>
19 #include <linux/vmalloc.h>
20 #include <linux/interrupt.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
23 #include <linux/etherdevice.h>
24 #include <linux/skbuff.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/bitops.h>
28 #include <linux/irq.h>
29 #include <linux/delay.h>
30 #include <asm/byteorder.h>
32 #include <linux/time.h>
33 #include <linux/mii.h>
35 #include <linux/if_vlan.h>
36 #include <linux/rtc.h>
37 #include <linux/bpf.h>
41 #include <net/checksum.h>
42 #include <net/ip6_checksum.h>
43 #include <net/udp_tunnel.h>
44 #include <linux/workqueue.h>
45 #include <linux/prefetch.h>
46 #include <linux/cache.h>
47 #include <linux/log2.h>
48 #include <linux/aer.h>
49 #include <linux/bitmap.h>
50 #include <linux/cpu_rmap.h>
55 #include "bnxt_sriov.h"
56 #include "bnxt_ethtool.h"
60 #define BNXT_TX_TIMEOUT (5 * HZ)
62 static const char version
[] =
63 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME
" v" DRV_MODULE_VERSION
"\n";
65 MODULE_LICENSE("GPL");
66 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
67 MODULE_VERSION(DRV_MODULE_VERSION
);
69 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
70 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
71 #define BNXT_RX_COPY_THRESH 256
73 #define BNXT_TX_PUSH_THRESH 164
108 /* indexed by enum above */
109 static const struct {
112 { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
113 { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
114 { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
115 { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
116 { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
117 { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
118 { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
119 { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
120 { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
121 { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
122 { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
123 { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
124 { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
125 { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
126 { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
127 { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
128 { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
129 { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
130 { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
131 { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
132 { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
133 { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
134 { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
135 { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
136 { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
137 { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
138 { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" },
139 { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
140 { "Broadcom NetXtreme-E Ethernet Virtual Function" },
141 { "Broadcom NetXtreme-C Ethernet Virtual Function" },
144 static const struct pci_device_id bnxt_pci_tbl
[] = {
145 { PCI_VDEVICE(BROADCOM
, 0x16c0), .driver_data
= BCM57417_NPAR
},
146 { PCI_VDEVICE(BROADCOM
, 0x16c8), .driver_data
= BCM57301
},
147 { PCI_VDEVICE(BROADCOM
, 0x16c9), .driver_data
= BCM57302
},
148 { PCI_VDEVICE(BROADCOM
, 0x16ca), .driver_data
= BCM57304
},
149 { PCI_VDEVICE(BROADCOM
, 0x16cc), .driver_data
= BCM57417_NPAR
},
150 { PCI_VDEVICE(BROADCOM
, 0x16cd), .driver_data
= BCM58700
},
151 { PCI_VDEVICE(BROADCOM
, 0x16ce), .driver_data
= BCM57311
},
152 { PCI_VDEVICE(BROADCOM
, 0x16cf), .driver_data
= BCM57312
},
153 { PCI_VDEVICE(BROADCOM
, 0x16d0), .driver_data
= BCM57402
},
154 { PCI_VDEVICE(BROADCOM
, 0x16d1), .driver_data
= BCM57404
},
155 { PCI_VDEVICE(BROADCOM
, 0x16d2), .driver_data
= BCM57406
},
156 { PCI_VDEVICE(BROADCOM
, 0x16d4), .driver_data
= BCM57402_NPAR
},
157 { PCI_VDEVICE(BROADCOM
, 0x16d5), .driver_data
= BCM57407
},
158 { PCI_VDEVICE(BROADCOM
, 0x16d6), .driver_data
= BCM57412
},
159 { PCI_VDEVICE(BROADCOM
, 0x16d7), .driver_data
= BCM57414
},
160 { PCI_VDEVICE(BROADCOM
, 0x16d8), .driver_data
= BCM57416
},
161 { PCI_VDEVICE(BROADCOM
, 0x16d9), .driver_data
= BCM57417
},
162 { PCI_VDEVICE(BROADCOM
, 0x16de), .driver_data
= BCM57412_NPAR
},
163 { PCI_VDEVICE(BROADCOM
, 0x16df), .driver_data
= BCM57314
},
164 { PCI_VDEVICE(BROADCOM
, 0x16e2), .driver_data
= BCM57417_SFP
},
165 { PCI_VDEVICE(BROADCOM
, 0x16e3), .driver_data
= BCM57416_SFP
},
166 { PCI_VDEVICE(BROADCOM
, 0x16e7), .driver_data
= BCM57404_NPAR
},
167 { PCI_VDEVICE(BROADCOM
, 0x16e8), .driver_data
= BCM57406_NPAR
},
168 { PCI_VDEVICE(BROADCOM
, 0x16e9), .driver_data
= BCM57407_SFP
},
169 { PCI_VDEVICE(BROADCOM
, 0x16ea), .driver_data
= BCM57407_NPAR
},
170 { PCI_VDEVICE(BROADCOM
, 0x16eb), .driver_data
= BCM57412_NPAR
},
171 { PCI_VDEVICE(BROADCOM
, 0x16ec), .driver_data
= BCM57414_NPAR
},
172 { PCI_VDEVICE(BROADCOM
, 0x16ed), .driver_data
= BCM57414_NPAR
},
173 { PCI_VDEVICE(BROADCOM
, 0x16ee), .driver_data
= BCM57416_NPAR
},
174 { PCI_VDEVICE(BROADCOM
, 0x16ef), .driver_data
= BCM57416_NPAR
},
175 { PCI_VDEVICE(BROADCOM
, 0x16f1), .driver_data
= BCM57452
},
176 { PCI_VDEVICE(BROADCOM
, 0x1614), .driver_data
= BCM57454
},
177 #ifdef CONFIG_BNXT_SRIOV
178 { PCI_VDEVICE(BROADCOM
, 0x16c1), .driver_data
= NETXTREME_E_VF
},
179 { PCI_VDEVICE(BROADCOM
, 0x16cb), .driver_data
= NETXTREME_C_VF
},
180 { PCI_VDEVICE(BROADCOM
, 0x16d3), .driver_data
= NETXTREME_E_VF
},
181 { PCI_VDEVICE(BROADCOM
, 0x16dc), .driver_data
= NETXTREME_E_VF
},
182 { PCI_VDEVICE(BROADCOM
, 0x16e1), .driver_data
= NETXTREME_C_VF
},
183 { PCI_VDEVICE(BROADCOM
, 0x16e5), .driver_data
= NETXTREME_C_VF
},
188 MODULE_DEVICE_TABLE(pci
, bnxt_pci_tbl
);
190 static const u16 bnxt_vf_req_snif
[] = {
193 HWRM_CFA_L2_FILTER_ALLOC
,
196 static const u16 bnxt_async_events_arr
[] = {
197 ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE
,
198 ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD
,
199 ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED
,
200 ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE
,
201 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE
,
204 static bool bnxt_vf_pciid(enum board_idx idx
)
206 return (idx
== NETXTREME_C_VF
|| idx
== NETXTREME_E_VF
);
209 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
210 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
211 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
213 #define BNXT_CP_DB_REARM(db, raw_cons) \
214 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
216 #define BNXT_CP_DB(db, raw_cons) \
217 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
219 #define BNXT_CP_DB_IRQ_DIS(db) \
220 writel(DB_CP_IRQ_DIS_FLAGS, db)
222 const u16 bnxt_lhint_arr
[] = {
223 TX_BD_FLAGS_LHINT_512_AND_SMALLER
,
224 TX_BD_FLAGS_LHINT_512_TO_1023
,
225 TX_BD_FLAGS_LHINT_1024_TO_2047
,
226 TX_BD_FLAGS_LHINT_1024_TO_2047
,
227 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
228 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
229 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
230 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
231 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
232 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
233 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
234 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
235 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
236 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
237 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
238 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
239 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
240 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
241 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
244 static netdev_tx_t
bnxt_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
246 struct bnxt
*bp
= netdev_priv(dev
);
248 struct tx_bd_ext
*txbd1
;
249 struct netdev_queue
*txq
;
252 unsigned int length
, pad
= 0;
253 u32 len
, free_size
, vlan_tag_flags
, cfa_action
, flags
;
255 struct pci_dev
*pdev
= bp
->pdev
;
256 struct bnxt_tx_ring_info
*txr
;
257 struct bnxt_sw_tx_bd
*tx_buf
;
259 i
= skb_get_queue_mapping(skb
);
260 if (unlikely(i
>= bp
->tx_nr_rings
)) {
261 dev_kfree_skb_any(skb
);
265 txq
= netdev_get_tx_queue(dev
, i
);
266 txr
= &bp
->tx_ring
[bp
->tx_ring_map
[i
]];
269 free_size
= bnxt_tx_avail(bp
, txr
);
270 if (unlikely(free_size
< skb_shinfo(skb
)->nr_frags
+ 2)) {
271 netif_tx_stop_queue(txq
);
272 return NETDEV_TX_BUSY
;
276 len
= skb_headlen(skb
);
277 last_frag
= skb_shinfo(skb
)->nr_frags
;
279 txbd
= &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
281 txbd
->tx_bd_opaque
= prod
;
283 tx_buf
= &txr
->tx_buf_ring
[prod
];
285 tx_buf
->nr_frags
= last_frag
;
289 if (skb_vlan_tag_present(skb
)) {
290 vlan_tag_flags
= TX_BD_CFA_META_KEY_VLAN
|
291 skb_vlan_tag_get(skb
);
292 /* Currently supports 8021Q, 8021AD vlan offloads
293 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
295 if (skb
->vlan_proto
== htons(ETH_P_8021Q
))
296 vlan_tag_flags
|= 1 << TX_BD_CFA_META_TPID_SHIFT
;
299 if (free_size
== bp
->tx_ring_size
&& length
<= bp
->tx_push_thresh
) {
300 struct tx_push_buffer
*tx_push_buf
= txr
->tx_push
;
301 struct tx_push_bd
*tx_push
= &tx_push_buf
->push_bd
;
302 struct tx_bd_ext
*tx_push1
= &tx_push
->txbd2
;
303 void *pdata
= tx_push_buf
->data
;
307 /* Set COAL_NOW to be ready quickly for the next push */
308 tx_push
->tx_bd_len_flags_type
=
309 cpu_to_le32((length
<< TX_BD_LEN_SHIFT
) |
310 TX_BD_TYPE_LONG_TX_BD
|
311 TX_BD_FLAGS_LHINT_512_AND_SMALLER
|
312 TX_BD_FLAGS_COAL_NOW
|
313 TX_BD_FLAGS_PACKET_END
|
314 (2 << TX_BD_FLAGS_BD_CNT_SHIFT
));
316 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
317 tx_push1
->tx_bd_hsize_lflags
=
318 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM
);
320 tx_push1
->tx_bd_hsize_lflags
= 0;
322 tx_push1
->tx_bd_cfa_meta
= cpu_to_le32(vlan_tag_flags
);
323 tx_push1
->tx_bd_cfa_action
= cpu_to_le32(cfa_action
);
325 end
= pdata
+ length
;
326 end
= PTR_ALIGN(end
, 8) - 1;
329 skb_copy_from_linear_data(skb
, pdata
, len
);
331 for (j
= 0; j
< last_frag
; j
++) {
332 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[j
];
335 fptr
= skb_frag_address_safe(frag
);
339 memcpy(pdata
, fptr
, skb_frag_size(frag
));
340 pdata
+= skb_frag_size(frag
);
343 txbd
->tx_bd_len_flags_type
= tx_push
->tx_bd_len_flags_type
;
344 txbd
->tx_bd_haddr
= txr
->data_mapping
;
345 prod
= NEXT_TX(prod
);
346 txbd
= &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
347 memcpy(txbd
, tx_push1
, sizeof(*txbd
));
348 prod
= NEXT_TX(prod
);
350 cpu_to_le32(DB_KEY_TX_PUSH
| DB_LONG_TX_PUSH
| prod
);
354 netdev_tx_sent_queue(txq
, skb
->len
);
355 wmb(); /* Sync is_push and byte queue before pushing data */
357 push_len
= (length
+ sizeof(*tx_push
) + 7) / 8;
359 __iowrite64_copy(txr
->tx_doorbell
, tx_push_buf
, 16);
360 __iowrite32_copy(txr
->tx_doorbell
+ 4, tx_push_buf
+ 1,
361 (push_len
- 16) << 1);
363 __iowrite64_copy(txr
->tx_doorbell
, tx_push_buf
,
371 if (length
< BNXT_MIN_PKT_SIZE
) {
372 pad
= BNXT_MIN_PKT_SIZE
- length
;
373 if (skb_pad(skb
, pad
)) {
374 /* SKB already freed. */
378 length
= BNXT_MIN_PKT_SIZE
;
381 mapping
= dma_map_single(&pdev
->dev
, skb
->data
, len
, DMA_TO_DEVICE
);
383 if (unlikely(dma_mapping_error(&pdev
->dev
, mapping
))) {
384 dev_kfree_skb_any(skb
);
389 dma_unmap_addr_set(tx_buf
, mapping
, mapping
);
390 flags
= (len
<< TX_BD_LEN_SHIFT
) | TX_BD_TYPE_LONG_TX_BD
|
391 ((last_frag
+ 2) << TX_BD_FLAGS_BD_CNT_SHIFT
);
393 txbd
->tx_bd_haddr
= cpu_to_le64(mapping
);
395 prod
= NEXT_TX(prod
);
396 txbd1
= (struct tx_bd_ext
*)
397 &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
399 txbd1
->tx_bd_hsize_lflags
= 0;
400 if (skb_is_gso(skb
)) {
403 if (skb
->encapsulation
)
404 hdr_len
= skb_inner_network_offset(skb
) +
405 skb_inner_network_header_len(skb
) +
406 inner_tcp_hdrlen(skb
);
408 hdr_len
= skb_transport_offset(skb
) +
411 txbd1
->tx_bd_hsize_lflags
= cpu_to_le32(TX_BD_FLAGS_LSO
|
413 (hdr_len
<< (TX_BD_HSIZE_SHIFT
- 1)));
414 length
= skb_shinfo(skb
)->gso_size
;
415 txbd1
->tx_bd_mss
= cpu_to_le32(length
);
417 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
418 txbd1
->tx_bd_hsize_lflags
=
419 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM
);
420 txbd1
->tx_bd_mss
= 0;
424 flags
|= bnxt_lhint_arr
[length
];
425 txbd
->tx_bd_len_flags_type
= cpu_to_le32(flags
);
427 txbd1
->tx_bd_cfa_meta
= cpu_to_le32(vlan_tag_flags
);
428 txbd1
->tx_bd_cfa_action
= cpu_to_le32(cfa_action
);
429 for (i
= 0; i
< last_frag
; i
++) {
430 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
432 prod
= NEXT_TX(prod
);
433 txbd
= &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
435 len
= skb_frag_size(frag
);
436 mapping
= skb_frag_dma_map(&pdev
->dev
, frag
, 0, len
,
439 if (unlikely(dma_mapping_error(&pdev
->dev
, mapping
)))
442 tx_buf
= &txr
->tx_buf_ring
[prod
];
443 dma_unmap_addr_set(tx_buf
, mapping
, mapping
);
445 txbd
->tx_bd_haddr
= cpu_to_le64(mapping
);
447 flags
= len
<< TX_BD_LEN_SHIFT
;
448 txbd
->tx_bd_len_flags_type
= cpu_to_le32(flags
);
452 txbd
->tx_bd_len_flags_type
=
453 cpu_to_le32(((len
+ pad
) << TX_BD_LEN_SHIFT
) | flags
|
454 TX_BD_FLAGS_PACKET_END
);
456 netdev_tx_sent_queue(txq
, skb
->len
);
458 /* Sync BD data before updating doorbell */
461 prod
= NEXT_TX(prod
);
464 writel(DB_KEY_TX
| prod
, txr
->tx_doorbell
);
465 writel(DB_KEY_TX
| prod
, txr
->tx_doorbell
);
471 if (unlikely(bnxt_tx_avail(bp
, txr
) <= MAX_SKB_FRAGS
+ 1)) {
472 netif_tx_stop_queue(txq
);
474 /* netif_tx_stop_queue() must be done before checking
475 * tx index in bnxt_tx_avail() below, because in
476 * bnxt_tx_int(), we update tx index before checking for
477 * netif_tx_queue_stopped().
480 if (bnxt_tx_avail(bp
, txr
) > bp
->tx_wake_thresh
)
481 netif_tx_wake_queue(txq
);
488 /* start back at beginning and unmap skb */
490 tx_buf
= &txr
->tx_buf_ring
[prod
];
492 dma_unmap_single(&pdev
->dev
, dma_unmap_addr(tx_buf
, mapping
),
493 skb_headlen(skb
), PCI_DMA_TODEVICE
);
494 prod
= NEXT_TX(prod
);
496 /* unmap remaining mapped pages */
497 for (i
= 0; i
< last_frag
; i
++) {
498 prod
= NEXT_TX(prod
);
499 tx_buf
= &txr
->tx_buf_ring
[prod
];
500 dma_unmap_page(&pdev
->dev
, dma_unmap_addr(tx_buf
, mapping
),
501 skb_frag_size(&skb_shinfo(skb
)->frags
[i
]),
505 dev_kfree_skb_any(skb
);
509 static void bnxt_tx_int(struct bnxt
*bp
, struct bnxt_napi
*bnapi
, int nr_pkts
)
511 struct bnxt_tx_ring_info
*txr
= bnapi
->tx_ring
;
512 struct netdev_queue
*txq
= netdev_get_tx_queue(bp
->dev
, txr
->txq_index
);
513 u16 cons
= txr
->tx_cons
;
514 struct pci_dev
*pdev
= bp
->pdev
;
516 unsigned int tx_bytes
= 0;
518 for (i
= 0; i
< nr_pkts
; i
++) {
519 struct bnxt_sw_tx_bd
*tx_buf
;
523 tx_buf
= &txr
->tx_buf_ring
[cons
];
524 cons
= NEXT_TX(cons
);
528 if (tx_buf
->is_push
) {
533 dma_unmap_single(&pdev
->dev
, dma_unmap_addr(tx_buf
, mapping
),
534 skb_headlen(skb
), PCI_DMA_TODEVICE
);
535 last
= tx_buf
->nr_frags
;
537 for (j
= 0; j
< last
; j
++) {
538 cons
= NEXT_TX(cons
);
539 tx_buf
= &txr
->tx_buf_ring
[cons
];
542 dma_unmap_addr(tx_buf
, mapping
),
543 skb_frag_size(&skb_shinfo(skb
)->frags
[j
]),
548 cons
= NEXT_TX(cons
);
550 tx_bytes
+= skb
->len
;
551 dev_kfree_skb_any(skb
);
554 netdev_tx_completed_queue(txq
, nr_pkts
, tx_bytes
);
557 /* Need to make the tx_cons update visible to bnxt_start_xmit()
558 * before checking for netif_tx_queue_stopped(). Without the
559 * memory barrier, there is a small possibility that bnxt_start_xmit()
560 * will miss it and cause the queue to be stopped forever.
564 if (unlikely(netif_tx_queue_stopped(txq
)) &&
565 (bnxt_tx_avail(bp
, txr
) > bp
->tx_wake_thresh
)) {
566 __netif_tx_lock(txq
, smp_processor_id());
567 if (netif_tx_queue_stopped(txq
) &&
568 bnxt_tx_avail(bp
, txr
) > bp
->tx_wake_thresh
&&
569 txr
->dev_state
!= BNXT_DEV_STATE_CLOSING
)
570 netif_tx_wake_queue(txq
);
571 __netif_tx_unlock(txq
);
575 static struct page
*__bnxt_alloc_rx_page(struct bnxt
*bp
, dma_addr_t
*mapping
,
578 struct device
*dev
= &bp
->pdev
->dev
;
581 page
= alloc_page(gfp
);
585 *mapping
= dma_map_page(dev
, page
, 0, PAGE_SIZE
, bp
->rx_dir
);
586 if (dma_mapping_error(dev
, *mapping
)) {
590 *mapping
+= bp
->rx_dma_offset
;
594 static inline u8
*__bnxt_alloc_rx_data(struct bnxt
*bp
, dma_addr_t
*mapping
,
598 struct pci_dev
*pdev
= bp
->pdev
;
600 data
= kmalloc(bp
->rx_buf_size
, gfp
);
604 *mapping
= dma_map_single(&pdev
->dev
, data
+ bp
->rx_dma_offset
,
605 bp
->rx_buf_use_size
, bp
->rx_dir
);
607 if (dma_mapping_error(&pdev
->dev
, *mapping
)) {
614 int bnxt_alloc_rx_data(struct bnxt
*bp
, struct bnxt_rx_ring_info
*rxr
,
617 struct rx_bd
*rxbd
= &rxr
->rx_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
618 struct bnxt_sw_rx_bd
*rx_buf
= &rxr
->rx_buf_ring
[prod
];
621 if (BNXT_RX_PAGE_MODE(bp
)) {
622 struct page
*page
= __bnxt_alloc_rx_page(bp
, &mapping
, gfp
);
628 rx_buf
->data_ptr
= page_address(page
) + bp
->rx_offset
;
630 u8
*data
= __bnxt_alloc_rx_data(bp
, &mapping
, gfp
);
636 rx_buf
->data_ptr
= data
+ bp
->rx_offset
;
638 rx_buf
->mapping
= mapping
;
640 rxbd
->rx_bd_haddr
= cpu_to_le64(mapping
);
644 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info
*rxr
, u16 cons
, void *data
)
646 u16 prod
= rxr
->rx_prod
;
647 struct bnxt_sw_rx_bd
*cons_rx_buf
, *prod_rx_buf
;
648 struct rx_bd
*cons_bd
, *prod_bd
;
650 prod_rx_buf
= &rxr
->rx_buf_ring
[prod
];
651 cons_rx_buf
= &rxr
->rx_buf_ring
[cons
];
653 prod_rx_buf
->data
= data
;
654 prod_rx_buf
->data_ptr
= cons_rx_buf
->data_ptr
;
656 prod_rx_buf
->mapping
= cons_rx_buf
->mapping
;
658 prod_bd
= &rxr
->rx_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
659 cons_bd
= &rxr
->rx_desc_ring
[RX_RING(cons
)][RX_IDX(cons
)];
661 prod_bd
->rx_bd_haddr
= cons_bd
->rx_bd_haddr
;
664 static inline u16
bnxt_find_next_agg_idx(struct bnxt_rx_ring_info
*rxr
, u16 idx
)
666 u16 next
, max
= rxr
->rx_agg_bmap_size
;
668 next
= find_next_zero_bit(rxr
->rx_agg_bmap
, max
, idx
);
670 next
= find_first_zero_bit(rxr
->rx_agg_bmap
, max
);
674 static inline int bnxt_alloc_rx_page(struct bnxt
*bp
,
675 struct bnxt_rx_ring_info
*rxr
,
679 &rxr
->rx_agg_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
680 struct bnxt_sw_rx_agg_bd
*rx_agg_buf
;
681 struct pci_dev
*pdev
= bp
->pdev
;
684 u16 sw_prod
= rxr
->rx_sw_agg_prod
;
685 unsigned int offset
= 0;
687 if (PAGE_SIZE
> BNXT_RX_PAGE_SIZE
) {
690 page
= alloc_page(gfp
);
694 rxr
->rx_page_offset
= 0;
696 offset
= rxr
->rx_page_offset
;
697 rxr
->rx_page_offset
+= BNXT_RX_PAGE_SIZE
;
698 if (rxr
->rx_page_offset
== PAGE_SIZE
)
703 page
= alloc_page(gfp
);
708 mapping
= dma_map_page(&pdev
->dev
, page
, offset
, BNXT_RX_PAGE_SIZE
,
710 if (dma_mapping_error(&pdev
->dev
, mapping
)) {
715 if (unlikely(test_bit(sw_prod
, rxr
->rx_agg_bmap
)))
716 sw_prod
= bnxt_find_next_agg_idx(rxr
, sw_prod
);
718 __set_bit(sw_prod
, rxr
->rx_agg_bmap
);
719 rx_agg_buf
= &rxr
->rx_agg_ring
[sw_prod
];
720 rxr
->rx_sw_agg_prod
= NEXT_RX_AGG(sw_prod
);
722 rx_agg_buf
->page
= page
;
723 rx_agg_buf
->offset
= offset
;
724 rx_agg_buf
->mapping
= mapping
;
725 rxbd
->rx_bd_haddr
= cpu_to_le64(mapping
);
726 rxbd
->rx_bd_opaque
= sw_prod
;
730 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi
*bnapi
, u16 cp_cons
,
733 struct bnxt
*bp
= bnapi
->bp
;
734 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
735 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
736 u16 prod
= rxr
->rx_agg_prod
;
737 u16 sw_prod
= rxr
->rx_sw_agg_prod
;
740 for (i
= 0; i
< agg_bufs
; i
++) {
742 struct rx_agg_cmp
*agg
;
743 struct bnxt_sw_rx_agg_bd
*cons_rx_buf
, *prod_rx_buf
;
744 struct rx_bd
*prod_bd
;
747 agg
= (struct rx_agg_cmp
*)
748 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
749 cons
= agg
->rx_agg_cmp_opaque
;
750 __clear_bit(cons
, rxr
->rx_agg_bmap
);
752 if (unlikely(test_bit(sw_prod
, rxr
->rx_agg_bmap
)))
753 sw_prod
= bnxt_find_next_agg_idx(rxr
, sw_prod
);
755 __set_bit(sw_prod
, rxr
->rx_agg_bmap
);
756 prod_rx_buf
= &rxr
->rx_agg_ring
[sw_prod
];
757 cons_rx_buf
= &rxr
->rx_agg_ring
[cons
];
759 /* It is possible for sw_prod to be equal to cons, so
760 * set cons_rx_buf->page to NULL first.
762 page
= cons_rx_buf
->page
;
763 cons_rx_buf
->page
= NULL
;
764 prod_rx_buf
->page
= page
;
765 prod_rx_buf
->offset
= cons_rx_buf
->offset
;
767 prod_rx_buf
->mapping
= cons_rx_buf
->mapping
;
769 prod_bd
= &rxr
->rx_agg_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
771 prod_bd
->rx_bd_haddr
= cpu_to_le64(cons_rx_buf
->mapping
);
772 prod_bd
->rx_bd_opaque
= sw_prod
;
774 prod
= NEXT_RX_AGG(prod
);
775 sw_prod
= NEXT_RX_AGG(sw_prod
);
776 cp_cons
= NEXT_CMP(cp_cons
);
778 rxr
->rx_agg_prod
= prod
;
779 rxr
->rx_sw_agg_prod
= sw_prod
;
782 static struct sk_buff
*bnxt_rx_page_skb(struct bnxt
*bp
,
783 struct bnxt_rx_ring_info
*rxr
,
784 u16 cons
, void *data
, u8
*data_ptr
,
786 unsigned int offset_and_len
)
788 unsigned int payload
= offset_and_len
>> 16;
789 unsigned int len
= offset_and_len
& 0xffff;
790 struct skb_frag_struct
*frag
;
791 struct page
*page
= data
;
792 u16 prod
= rxr
->rx_prod
;
796 err
= bnxt_alloc_rx_data(bp
, rxr
, prod
, GFP_ATOMIC
);
798 bnxt_reuse_rx_data(rxr
, cons
, data
);
801 dma_addr
-= bp
->rx_dma_offset
;
802 dma_unmap_page(&bp
->pdev
->dev
, dma_addr
, PAGE_SIZE
, bp
->rx_dir
);
804 if (unlikely(!payload
))
805 payload
= eth_get_headlen(data_ptr
, len
);
807 skb
= napi_alloc_skb(&rxr
->bnapi
->napi
, payload
);
813 off
= (void *)data_ptr
- page_address(page
);
814 skb_add_rx_frag(skb
, 0, page
, off
, len
, PAGE_SIZE
);
815 memcpy(skb
->data
- NET_IP_ALIGN
, data_ptr
- NET_IP_ALIGN
,
816 payload
+ NET_IP_ALIGN
);
818 frag
= &skb_shinfo(skb
)->frags
[0];
819 skb_frag_size_sub(frag
, payload
);
820 frag
->page_offset
+= payload
;
821 skb
->data_len
-= payload
;
822 skb
->tail
+= payload
;
827 static struct sk_buff
*bnxt_rx_skb(struct bnxt
*bp
,
828 struct bnxt_rx_ring_info
*rxr
, u16 cons
,
829 void *data
, u8
*data_ptr
,
831 unsigned int offset_and_len
)
833 u16 prod
= rxr
->rx_prod
;
837 err
= bnxt_alloc_rx_data(bp
, rxr
, prod
, GFP_ATOMIC
);
839 bnxt_reuse_rx_data(rxr
, cons
, data
);
843 skb
= build_skb(data
, 0);
844 dma_unmap_single(&bp
->pdev
->dev
, dma_addr
, bp
->rx_buf_use_size
,
851 skb_reserve(skb
, bp
->rx_offset
);
852 skb_put(skb
, offset_and_len
& 0xffff);
856 static struct sk_buff
*bnxt_rx_pages(struct bnxt
*bp
, struct bnxt_napi
*bnapi
,
857 struct sk_buff
*skb
, u16 cp_cons
,
860 struct pci_dev
*pdev
= bp
->pdev
;
861 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
862 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
863 u16 prod
= rxr
->rx_agg_prod
;
866 for (i
= 0; i
< agg_bufs
; i
++) {
868 struct rx_agg_cmp
*agg
;
869 struct bnxt_sw_rx_agg_bd
*cons_rx_buf
;
873 agg
= (struct rx_agg_cmp
*)
874 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
875 cons
= agg
->rx_agg_cmp_opaque
;
876 frag_len
= (le32_to_cpu(agg
->rx_agg_cmp_len_flags_type
) &
877 RX_AGG_CMP_LEN
) >> RX_AGG_CMP_LEN_SHIFT
;
879 cons_rx_buf
= &rxr
->rx_agg_ring
[cons
];
880 skb_fill_page_desc(skb
, i
, cons_rx_buf
->page
,
881 cons_rx_buf
->offset
, frag_len
);
882 __clear_bit(cons
, rxr
->rx_agg_bmap
);
884 /* It is possible for bnxt_alloc_rx_page() to allocate
885 * a sw_prod index that equals the cons index, so we
886 * need to clear the cons entry now.
888 mapping
= cons_rx_buf
->mapping
;
889 page
= cons_rx_buf
->page
;
890 cons_rx_buf
->page
= NULL
;
892 if (bnxt_alloc_rx_page(bp
, rxr
, prod
, GFP_ATOMIC
) != 0) {
893 struct skb_shared_info
*shinfo
;
894 unsigned int nr_frags
;
896 shinfo
= skb_shinfo(skb
);
897 nr_frags
= --shinfo
->nr_frags
;
898 __skb_frag_set_page(&shinfo
->frags
[nr_frags
], NULL
);
902 cons_rx_buf
->page
= page
;
904 /* Update prod since possibly some pages have been
907 rxr
->rx_agg_prod
= prod
;
908 bnxt_reuse_rx_agg_bufs(bnapi
, cp_cons
, agg_bufs
- i
);
912 dma_unmap_page(&pdev
->dev
, mapping
, BNXT_RX_PAGE_SIZE
,
915 skb
->data_len
+= frag_len
;
916 skb
->len
+= frag_len
;
917 skb
->truesize
+= PAGE_SIZE
;
919 prod
= NEXT_RX_AGG(prod
);
920 cp_cons
= NEXT_CMP(cp_cons
);
922 rxr
->rx_agg_prod
= prod
;
926 static int bnxt_agg_bufs_valid(struct bnxt
*bp
, struct bnxt_cp_ring_info
*cpr
,
927 u8 agg_bufs
, u32
*raw_cons
)
930 struct rx_agg_cmp
*agg
;
932 *raw_cons
= ADV_RAW_CMP(*raw_cons
, agg_bufs
);
933 last
= RING_CMP(*raw_cons
);
934 agg
= (struct rx_agg_cmp
*)
935 &cpr
->cp_desc_ring
[CP_RING(last
)][CP_IDX(last
)];
936 return RX_AGG_CMP_VALID(agg
, *raw_cons
);
939 static inline struct sk_buff
*bnxt_copy_skb(struct bnxt_napi
*bnapi
, u8
*data
,
943 struct bnxt
*bp
= bnapi
->bp
;
944 struct pci_dev
*pdev
= bp
->pdev
;
947 skb
= napi_alloc_skb(&bnapi
->napi
, len
);
951 dma_sync_single_for_cpu(&pdev
->dev
, mapping
, bp
->rx_copy_thresh
,
954 memcpy(skb
->data
- NET_IP_ALIGN
, data
- NET_IP_ALIGN
,
957 dma_sync_single_for_device(&pdev
->dev
, mapping
, bp
->rx_copy_thresh
,
964 static int bnxt_discard_rx(struct bnxt
*bp
, struct bnxt_napi
*bnapi
,
965 u32
*raw_cons
, void *cmp
)
967 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
968 struct rx_cmp
*rxcmp
= cmp
;
969 u32 tmp_raw_cons
= *raw_cons
;
970 u8 cmp_type
, agg_bufs
= 0;
972 cmp_type
= RX_CMP_TYPE(rxcmp
);
974 if (cmp_type
== CMP_TYPE_RX_L2_CMP
) {
975 agg_bufs
= (le32_to_cpu(rxcmp
->rx_cmp_misc_v1
) &
977 RX_CMP_AGG_BUFS_SHIFT
;
978 } else if (cmp_type
== CMP_TYPE_RX_L2_TPA_END_CMP
) {
979 struct rx_tpa_end_cmp
*tpa_end
= cmp
;
981 agg_bufs
= (le32_to_cpu(tpa_end
->rx_tpa_end_cmp_misc_v1
) &
982 RX_TPA_END_CMP_AGG_BUFS
) >>
983 RX_TPA_END_CMP_AGG_BUFS_SHIFT
;
987 if (!bnxt_agg_bufs_valid(bp
, cpr
, agg_bufs
, &tmp_raw_cons
))
990 *raw_cons
= tmp_raw_cons
;
994 static void bnxt_sched_reset(struct bnxt
*bp
, struct bnxt_rx_ring_info
*rxr
)
996 if (!rxr
->bnapi
->in_reset
) {
997 rxr
->bnapi
->in_reset
= true;
998 set_bit(BNXT_RESET_TASK_SP_EVENT
, &bp
->sp_event
);
999 schedule_work(&bp
->sp_task
);
1001 rxr
->rx_next_cons
= 0xffff;
1004 static void bnxt_tpa_start(struct bnxt
*bp
, struct bnxt_rx_ring_info
*rxr
,
1005 struct rx_tpa_start_cmp
*tpa_start
,
1006 struct rx_tpa_start_cmp_ext
*tpa_start1
)
1008 u8 agg_id
= TPA_START_AGG_ID(tpa_start
);
1010 struct bnxt_tpa_info
*tpa_info
;
1011 struct bnxt_sw_rx_bd
*cons_rx_buf
, *prod_rx_buf
;
1012 struct rx_bd
*prod_bd
;
1015 cons
= tpa_start
->rx_tpa_start_cmp_opaque
;
1016 prod
= rxr
->rx_prod
;
1017 cons_rx_buf
= &rxr
->rx_buf_ring
[cons
];
1018 prod_rx_buf
= &rxr
->rx_buf_ring
[prod
];
1019 tpa_info
= &rxr
->rx_tpa
[agg_id
];
1021 if (unlikely(cons
!= rxr
->rx_next_cons
)) {
1022 bnxt_sched_reset(bp
, rxr
);
1026 prod_rx_buf
->data
= tpa_info
->data
;
1027 prod_rx_buf
->data_ptr
= tpa_info
->data_ptr
;
1029 mapping
= tpa_info
->mapping
;
1030 prod_rx_buf
->mapping
= mapping
;
1032 prod_bd
= &rxr
->rx_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
1034 prod_bd
->rx_bd_haddr
= cpu_to_le64(mapping
);
1036 tpa_info
->data
= cons_rx_buf
->data
;
1037 tpa_info
->data_ptr
= cons_rx_buf
->data_ptr
;
1038 cons_rx_buf
->data
= NULL
;
1039 tpa_info
->mapping
= cons_rx_buf
->mapping
;
1042 le32_to_cpu(tpa_start
->rx_tpa_start_cmp_len_flags_type
) >>
1043 RX_TPA_START_CMP_LEN_SHIFT
;
1044 if (likely(TPA_START_HASH_VALID(tpa_start
))) {
1045 u32 hash_type
= TPA_START_HASH_TYPE(tpa_start
);
1047 tpa_info
->hash_type
= PKT_HASH_TYPE_L4
;
1048 tpa_info
->gso_type
= SKB_GSO_TCPV4
;
1049 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1051 tpa_info
->gso_type
= SKB_GSO_TCPV6
;
1052 tpa_info
->rss_hash
=
1053 le32_to_cpu(tpa_start
->rx_tpa_start_cmp_rss_hash
);
1055 tpa_info
->hash_type
= PKT_HASH_TYPE_NONE
;
1056 tpa_info
->gso_type
= 0;
1057 if (netif_msg_rx_err(bp
))
1058 netdev_warn(bp
->dev
, "TPA packet without valid hash\n");
1060 tpa_info
->flags2
= le32_to_cpu(tpa_start1
->rx_tpa_start_cmp_flags2
);
1061 tpa_info
->metadata
= le32_to_cpu(tpa_start1
->rx_tpa_start_cmp_metadata
);
1062 tpa_info
->hdr_info
= le32_to_cpu(tpa_start1
->rx_tpa_start_cmp_hdr_info
);
1064 rxr
->rx_prod
= NEXT_RX(prod
);
1065 cons
= NEXT_RX(cons
);
1066 rxr
->rx_next_cons
= NEXT_RX(cons
);
1067 cons_rx_buf
= &rxr
->rx_buf_ring
[cons
];
1069 bnxt_reuse_rx_data(rxr
, cons
, cons_rx_buf
->data
);
1070 rxr
->rx_prod
= NEXT_RX(rxr
->rx_prod
);
1071 cons_rx_buf
->data
= NULL
;
1074 static void bnxt_abort_tpa(struct bnxt
*bp
, struct bnxt_napi
*bnapi
,
1075 u16 cp_cons
, u32 agg_bufs
)
1078 bnxt_reuse_rx_agg_bufs(bnapi
, cp_cons
, agg_bufs
);
1081 static struct sk_buff
*bnxt_gro_func_5731x(struct bnxt_tpa_info
*tpa_info
,
1082 int payload_off
, int tcp_ts
,
1083 struct sk_buff
*skb
)
1088 u16 outer_ip_off
, inner_ip_off
, inner_mac_off
;
1089 u32 hdr_info
= tpa_info
->hdr_info
;
1090 bool loopback
= false;
1092 inner_ip_off
= BNXT_TPA_INNER_L3_OFF(hdr_info
);
1093 inner_mac_off
= BNXT_TPA_INNER_L2_OFF(hdr_info
);
1094 outer_ip_off
= BNXT_TPA_OUTER_L3_OFF(hdr_info
);
1096 /* If the packet is an internal loopback packet, the offsets will
1097 * have an extra 4 bytes.
1099 if (inner_mac_off
== 4) {
1101 } else if (inner_mac_off
> 4) {
1102 __be16 proto
= *((__be16
*)(skb
->data
+ inner_ip_off
-
1105 /* We only support inner iPv4/ipv6. If we don't see the
1106 * correct protocol ID, it must be a loopback packet where
1107 * the offsets are off by 4.
1109 if (proto
!= htons(ETH_P_IP
) && proto
!= htons(ETH_P_IPV6
))
1113 /* internal loopback packet, subtract all offsets by 4 */
1119 nw_off
= inner_ip_off
- ETH_HLEN
;
1120 skb_set_network_header(skb
, nw_off
);
1121 if (tpa_info
->flags2
& RX_TPA_START_CMP_FLAGS2_IP_TYPE
) {
1122 struct ipv6hdr
*iph
= ipv6_hdr(skb
);
1124 skb_set_transport_header(skb
, nw_off
+ sizeof(struct ipv6hdr
));
1125 len
= skb
->len
- skb_transport_offset(skb
);
1127 th
->check
= ~tcp_v6_check(len
, &iph
->saddr
, &iph
->daddr
, 0);
1129 struct iphdr
*iph
= ip_hdr(skb
);
1131 skb_set_transport_header(skb
, nw_off
+ sizeof(struct iphdr
));
1132 len
= skb
->len
- skb_transport_offset(skb
);
1134 th
->check
= ~tcp_v4_check(len
, iph
->saddr
, iph
->daddr
, 0);
1137 if (inner_mac_off
) { /* tunnel */
1138 struct udphdr
*uh
= NULL
;
1139 __be16 proto
= *((__be16
*)(skb
->data
+ outer_ip_off
-
1142 if (proto
== htons(ETH_P_IP
)) {
1143 struct iphdr
*iph
= (struct iphdr
*)skb
->data
;
1145 if (iph
->protocol
== IPPROTO_UDP
)
1146 uh
= (struct udphdr
*)(iph
+ 1);
1148 struct ipv6hdr
*iph
= (struct ipv6hdr
*)skb
->data
;
1150 if (iph
->nexthdr
== IPPROTO_UDP
)
1151 uh
= (struct udphdr
*)(iph
+ 1);
1155 skb_shinfo(skb
)->gso_type
|=
1156 SKB_GSO_UDP_TUNNEL_CSUM
;
1158 skb_shinfo(skb
)->gso_type
|= SKB_GSO_UDP_TUNNEL
;
1165 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
1166 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1168 static struct sk_buff
*bnxt_gro_func_5730x(struct bnxt_tpa_info
*tpa_info
,
1169 int payload_off
, int tcp_ts
,
1170 struct sk_buff
*skb
)
1174 int len
, nw_off
, tcp_opt_len
= 0;
1179 if (tpa_info
->gso_type
== SKB_GSO_TCPV4
) {
1182 nw_off
= payload_off
- BNXT_IPV4_HDR_SIZE
- tcp_opt_len
-
1184 skb_set_network_header(skb
, nw_off
);
1186 skb_set_transport_header(skb
, nw_off
+ sizeof(struct iphdr
));
1187 len
= skb
->len
- skb_transport_offset(skb
);
1189 th
->check
= ~tcp_v4_check(len
, iph
->saddr
, iph
->daddr
, 0);
1190 } else if (tpa_info
->gso_type
== SKB_GSO_TCPV6
) {
1191 struct ipv6hdr
*iph
;
1193 nw_off
= payload_off
- BNXT_IPV6_HDR_SIZE
- tcp_opt_len
-
1195 skb_set_network_header(skb
, nw_off
);
1196 iph
= ipv6_hdr(skb
);
1197 skb_set_transport_header(skb
, nw_off
+ sizeof(struct ipv6hdr
));
1198 len
= skb
->len
- skb_transport_offset(skb
);
1200 th
->check
= ~tcp_v6_check(len
, &iph
->saddr
, &iph
->daddr
, 0);
1202 dev_kfree_skb_any(skb
);
1206 if (nw_off
) { /* tunnel */
1207 struct udphdr
*uh
= NULL
;
1209 if (skb
->protocol
== htons(ETH_P_IP
)) {
1210 struct iphdr
*iph
= (struct iphdr
*)skb
->data
;
1212 if (iph
->protocol
== IPPROTO_UDP
)
1213 uh
= (struct udphdr
*)(iph
+ 1);
1215 struct ipv6hdr
*iph
= (struct ipv6hdr
*)skb
->data
;
1217 if (iph
->nexthdr
== IPPROTO_UDP
)
1218 uh
= (struct udphdr
*)(iph
+ 1);
1222 skb_shinfo(skb
)->gso_type
|=
1223 SKB_GSO_UDP_TUNNEL_CSUM
;
1225 skb_shinfo(skb
)->gso_type
|= SKB_GSO_UDP_TUNNEL
;
1232 static inline struct sk_buff
*bnxt_gro_skb(struct bnxt
*bp
,
1233 struct bnxt_tpa_info
*tpa_info
,
1234 struct rx_tpa_end_cmp
*tpa_end
,
1235 struct rx_tpa_end_cmp_ext
*tpa_end1
,
1236 struct sk_buff
*skb
)
1242 segs
= TPA_END_TPA_SEGS(tpa_end
);
1246 NAPI_GRO_CB(skb
)->count
= segs
;
1247 skb_shinfo(skb
)->gso_size
=
1248 le32_to_cpu(tpa_end1
->rx_tpa_end_cmp_seg_len
);
1249 skb_shinfo(skb
)->gso_type
= tpa_info
->gso_type
;
1250 payload_off
= (le32_to_cpu(tpa_end
->rx_tpa_end_cmp_misc_v1
) &
1251 RX_TPA_END_CMP_PAYLOAD_OFFSET
) >>
1252 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT
;
1253 skb
= bp
->gro_func(tpa_info
, payload_off
, TPA_END_GRO_TS(tpa_end
), skb
);
1255 tcp_gro_complete(skb
);
1260 static inline struct sk_buff
*bnxt_tpa_end(struct bnxt
*bp
,
1261 struct bnxt_napi
*bnapi
,
1263 struct rx_tpa_end_cmp
*tpa_end
,
1264 struct rx_tpa_end_cmp_ext
*tpa_end1
,
1267 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1268 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
1269 u8 agg_id
= TPA_END_AGG_ID(tpa_end
);
1270 u8
*data_ptr
, agg_bufs
;
1271 u16 cp_cons
= RING_CMP(*raw_cons
);
1273 struct bnxt_tpa_info
*tpa_info
;
1275 struct sk_buff
*skb
;
1278 if (unlikely(bnapi
->in_reset
)) {
1279 int rc
= bnxt_discard_rx(bp
, bnapi
, raw_cons
, tpa_end
);
1282 return ERR_PTR(-EBUSY
);
1286 tpa_info
= &rxr
->rx_tpa
[agg_id
];
1287 data
= tpa_info
->data
;
1288 data_ptr
= tpa_info
->data_ptr
;
1290 len
= tpa_info
->len
;
1291 mapping
= tpa_info
->mapping
;
1293 agg_bufs
= (le32_to_cpu(tpa_end
->rx_tpa_end_cmp_misc_v1
) &
1294 RX_TPA_END_CMP_AGG_BUFS
) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT
;
1297 if (!bnxt_agg_bufs_valid(bp
, cpr
, agg_bufs
, raw_cons
))
1298 return ERR_PTR(-EBUSY
);
1300 *event
|= BNXT_AGG_EVENT
;
1301 cp_cons
= NEXT_CMP(cp_cons
);
1304 if (unlikely(agg_bufs
> MAX_SKB_FRAGS
)) {
1305 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
1306 netdev_warn(bp
->dev
, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1307 agg_bufs
, (int)MAX_SKB_FRAGS
);
1311 if (len
<= bp
->rx_copy_thresh
) {
1312 skb
= bnxt_copy_skb(bnapi
, data_ptr
, len
, mapping
);
1314 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
1319 dma_addr_t new_mapping
;
1321 new_data
= __bnxt_alloc_rx_data(bp
, &new_mapping
, GFP_ATOMIC
);
1323 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
1327 tpa_info
->data
= new_data
;
1328 tpa_info
->data_ptr
= new_data
+ bp
->rx_offset
;
1329 tpa_info
->mapping
= new_mapping
;
1331 skb
= build_skb(data
, 0);
1332 dma_unmap_single(&bp
->pdev
->dev
, mapping
, bp
->rx_buf_use_size
,
1337 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
1340 skb_reserve(skb
, bp
->rx_offset
);
1345 skb
= bnxt_rx_pages(bp
, bnapi
, skb
, cp_cons
, agg_bufs
);
1347 /* Page reuse already handled by bnxt_rx_pages(). */
1351 skb
->protocol
= eth_type_trans(skb
, bp
->dev
);
1353 if (tpa_info
->hash_type
!= PKT_HASH_TYPE_NONE
)
1354 skb_set_hash(skb
, tpa_info
->rss_hash
, tpa_info
->hash_type
);
1356 if ((tpa_info
->flags2
& RX_CMP_FLAGS2_META_FORMAT_VLAN
) &&
1357 (skb
->dev
->features
& NETIF_F_HW_VLAN_CTAG_RX
)) {
1358 u16 vlan_proto
= tpa_info
->metadata
>>
1359 RX_CMP_FLAGS2_METADATA_TPID_SFT
;
1360 u16 vtag
= tpa_info
->metadata
& RX_CMP_FLAGS2_METADATA_VID_MASK
;
1362 __vlan_hwaccel_put_tag(skb
, htons(vlan_proto
), vtag
);
1365 skb_checksum_none_assert(skb
);
1366 if (likely(tpa_info
->flags2
& RX_TPA_START_CMP_FLAGS2_L4_CS_CALC
)) {
1367 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1369 (tpa_info
->flags2
& RX_CMP_FLAGS2_T_L4_CS_CALC
) >> 3;
1372 if (TPA_END_GRO(tpa_end
))
1373 skb
= bnxt_gro_skb(bp
, tpa_info
, tpa_end
, tpa_end1
, skb
);
1378 /* returns the following:
1379 * 1 - 1 packet successfully received
1380 * 0 - successful TPA_START, packet not completed yet
1381 * -EBUSY - completion ring does not have all the agg buffers yet
1382 * -ENOMEM - packet aborted due to out of memory
1383 * -EIO - packet aborted due to hw error indicated in BD
1385 static int bnxt_rx_pkt(struct bnxt
*bp
, struct bnxt_napi
*bnapi
, u32
*raw_cons
,
1388 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1389 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
1390 struct net_device
*dev
= bp
->dev
;
1391 struct rx_cmp
*rxcmp
;
1392 struct rx_cmp_ext
*rxcmp1
;
1393 u32 tmp_raw_cons
= *raw_cons
;
1394 u16 cons
, prod
, cp_cons
= RING_CMP(tmp_raw_cons
);
1395 struct bnxt_sw_rx_bd
*rx_buf
;
1397 u8
*data_ptr
, agg_bufs
, cmp_type
;
1398 dma_addr_t dma_addr
;
1399 struct sk_buff
*skb
;
1404 rxcmp
= (struct rx_cmp
*)
1405 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
1407 tmp_raw_cons
= NEXT_RAW_CMP(tmp_raw_cons
);
1408 cp_cons
= RING_CMP(tmp_raw_cons
);
1409 rxcmp1
= (struct rx_cmp_ext
*)
1410 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
1412 if (!RX_CMP_VALID(rxcmp1
, tmp_raw_cons
))
1415 cmp_type
= RX_CMP_TYPE(rxcmp
);
1417 prod
= rxr
->rx_prod
;
1419 if (cmp_type
== CMP_TYPE_RX_L2_TPA_START_CMP
) {
1420 bnxt_tpa_start(bp
, rxr
, (struct rx_tpa_start_cmp
*)rxcmp
,
1421 (struct rx_tpa_start_cmp_ext
*)rxcmp1
);
1423 *event
|= BNXT_RX_EVENT
;
1424 goto next_rx_no_prod
;
1426 } else if (cmp_type
== CMP_TYPE_RX_L2_TPA_END_CMP
) {
1427 skb
= bnxt_tpa_end(bp
, bnapi
, &tmp_raw_cons
,
1428 (struct rx_tpa_end_cmp
*)rxcmp
,
1429 (struct rx_tpa_end_cmp_ext
*)rxcmp1
, event
);
1431 if (unlikely(IS_ERR(skb
)))
1436 skb_record_rx_queue(skb
, bnapi
->index
);
1437 napi_gro_receive(&bnapi
->napi
, skb
);
1440 *event
|= BNXT_RX_EVENT
;
1441 goto next_rx_no_prod
;
1444 cons
= rxcmp
->rx_cmp_opaque
;
1445 rx_buf
= &rxr
->rx_buf_ring
[cons
];
1446 data
= rx_buf
->data
;
1447 data_ptr
= rx_buf
->data_ptr
;
1448 if (unlikely(cons
!= rxr
->rx_next_cons
)) {
1449 int rc1
= bnxt_discard_rx(bp
, bnapi
, raw_cons
, rxcmp
);
1451 bnxt_sched_reset(bp
, rxr
);
1456 misc
= le32_to_cpu(rxcmp
->rx_cmp_misc_v1
);
1457 agg_bufs
= (misc
& RX_CMP_AGG_BUFS
) >> RX_CMP_AGG_BUFS_SHIFT
;
1460 if (!bnxt_agg_bufs_valid(bp
, cpr
, agg_bufs
, &tmp_raw_cons
))
1463 cp_cons
= NEXT_CMP(cp_cons
);
1464 *event
|= BNXT_AGG_EVENT
;
1466 *event
|= BNXT_RX_EVENT
;
1468 rx_buf
->data
= NULL
;
1469 if (rxcmp1
->rx_cmp_cfa_code_errors_v2
& RX_CMP_L2_ERRORS
) {
1470 bnxt_reuse_rx_data(rxr
, cons
, data
);
1472 bnxt_reuse_rx_agg_bufs(bnapi
, cp_cons
, agg_bufs
);
1478 len
= le32_to_cpu(rxcmp
->rx_cmp_len_flags_type
) >> RX_CMP_LEN_SHIFT
;
1479 dma_addr
= rx_buf
->mapping
;
1481 if (bnxt_rx_xdp(bp
, rxr
, cons
, data
, &data_ptr
, &len
, event
)) {
1486 if (len
<= bp
->rx_copy_thresh
) {
1487 skb
= bnxt_copy_skb(bnapi
, data_ptr
, len
, dma_addr
);
1488 bnxt_reuse_rx_data(rxr
, cons
, data
);
1496 if (rx_buf
->data_ptr
== data_ptr
)
1497 payload
= misc
& RX_CMP_PAYLOAD_OFFSET
;
1500 skb
= bp
->rx_skb_func(bp
, rxr
, cons
, data
, data_ptr
, dma_addr
,
1509 skb
= bnxt_rx_pages(bp
, bnapi
, skb
, cp_cons
, agg_bufs
);
1516 if (RX_CMP_HASH_VALID(rxcmp
)) {
1517 u32 hash_type
= RX_CMP_HASH_TYPE(rxcmp
);
1518 enum pkt_hash_types type
= PKT_HASH_TYPE_L4
;
1520 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1521 if (hash_type
!= 1 && hash_type
!= 3)
1522 type
= PKT_HASH_TYPE_L3
;
1523 skb_set_hash(skb
, le32_to_cpu(rxcmp
->rx_cmp_rss_hash
), type
);
1526 skb
->protocol
= eth_type_trans(skb
, dev
);
1528 if ((rxcmp1
->rx_cmp_flags2
&
1529 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN
)) &&
1530 (skb
->dev
->features
& NETIF_F_HW_VLAN_CTAG_RX
)) {
1531 u32 meta_data
= le32_to_cpu(rxcmp1
->rx_cmp_meta_data
);
1532 u16 vtag
= meta_data
& RX_CMP_FLAGS2_METADATA_VID_MASK
;
1533 u16 vlan_proto
= meta_data
>> RX_CMP_FLAGS2_METADATA_TPID_SFT
;
1535 __vlan_hwaccel_put_tag(skb
, htons(vlan_proto
), vtag
);
1538 skb_checksum_none_assert(skb
);
1539 if (RX_CMP_L4_CS_OK(rxcmp1
)) {
1540 if (dev
->features
& NETIF_F_RXCSUM
) {
1541 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1542 skb
->csum_level
= RX_CMP_ENCAP(rxcmp1
);
1545 if (rxcmp1
->rx_cmp_cfa_code_errors_v2
& RX_CMP_L4_CS_ERR_BITS
) {
1546 if (dev
->features
& NETIF_F_RXCSUM
)
1547 cpr
->rx_l4_csum_errors
++;
1551 skb_record_rx_queue(skb
, bnapi
->index
);
1552 napi_gro_receive(&bnapi
->napi
, skb
);
1556 rxr
->rx_prod
= NEXT_RX(prod
);
1557 rxr
->rx_next_cons
= NEXT_RX(cons
);
1560 *raw_cons
= tmp_raw_cons
;
1565 #define BNXT_GET_EVENT_PORT(data) \
1567 ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
1569 static int bnxt_async_event_process(struct bnxt
*bp
,
1570 struct hwrm_async_event_cmpl
*cmpl
)
1572 u16 event_id
= le16_to_cpu(cmpl
->event_id
);
1574 /* TODO CHIMP_FW: Define event id's for link change, error etc */
1576 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE
: {
1577 u32 data1
= le32_to_cpu(cmpl
->event_data1
);
1578 struct bnxt_link_info
*link_info
= &bp
->link_info
;
1581 goto async_event_process_exit
;
1582 if (data1
& 0x20000) {
1583 u16 fw_speed
= link_info
->force_link_speed
;
1584 u32 speed
= bnxt_fw_to_ethtool_speed(fw_speed
);
1586 netdev_warn(bp
->dev
, "Link speed %d no longer supported\n",
1589 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT
, &bp
->sp_event
);
1592 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE
:
1593 set_bit(BNXT_LINK_CHNG_SP_EVENT
, &bp
->sp_event
);
1595 case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD
:
1596 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT
, &bp
->sp_event
);
1598 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED
: {
1599 u32 data1
= le32_to_cpu(cmpl
->event_data1
);
1600 u16 port_id
= BNXT_GET_EVENT_PORT(data1
);
1605 if (bp
->pf
.port_id
!= port_id
)
1608 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT
, &bp
->sp_event
);
1611 case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE
:
1613 goto async_event_process_exit
;
1614 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT
, &bp
->sp_event
);
1617 goto async_event_process_exit
;
1619 schedule_work(&bp
->sp_task
);
1620 async_event_process_exit
:
1621 bnxt_ulp_async_events(bp
, cmpl
);
1625 static int bnxt_hwrm_handler(struct bnxt
*bp
, struct tx_cmp
*txcmp
)
1627 u16 cmpl_type
= TX_CMP_TYPE(txcmp
), vf_id
, seq_id
;
1628 struct hwrm_cmpl
*h_cmpl
= (struct hwrm_cmpl
*)txcmp
;
1629 struct hwrm_fwd_req_cmpl
*fwd_req_cmpl
=
1630 (struct hwrm_fwd_req_cmpl
*)txcmp
;
1632 switch (cmpl_type
) {
1633 case CMPL_BASE_TYPE_HWRM_DONE
:
1634 seq_id
= le16_to_cpu(h_cmpl
->sequence_id
);
1635 if (seq_id
== bp
->hwrm_intr_seq_id
)
1636 bp
->hwrm_intr_seq_id
= HWRM_SEQ_ID_INVALID
;
1638 netdev_err(bp
->dev
, "Invalid hwrm seq id %d\n", seq_id
);
1641 case CMPL_BASE_TYPE_HWRM_FWD_REQ
:
1642 vf_id
= le16_to_cpu(fwd_req_cmpl
->source_id
);
1644 if ((vf_id
< bp
->pf
.first_vf_id
) ||
1645 (vf_id
>= bp
->pf
.first_vf_id
+ bp
->pf
.active_vfs
)) {
1646 netdev_err(bp
->dev
, "Msg contains invalid VF id %x\n",
1651 set_bit(vf_id
- bp
->pf
.first_vf_id
, bp
->pf
.vf_event_bmap
);
1652 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT
, &bp
->sp_event
);
1653 schedule_work(&bp
->sp_task
);
1656 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT
:
1657 bnxt_async_event_process(bp
,
1658 (struct hwrm_async_event_cmpl
*)txcmp
);
1667 static irqreturn_t
bnxt_msix(int irq
, void *dev_instance
)
1669 struct bnxt_napi
*bnapi
= dev_instance
;
1670 struct bnxt
*bp
= bnapi
->bp
;
1671 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1672 u32 cons
= RING_CMP(cpr
->cp_raw_cons
);
1674 prefetch(&cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)]);
1675 napi_schedule(&bnapi
->napi
);
1679 static inline int bnxt_has_work(struct bnxt
*bp
, struct bnxt_cp_ring_info
*cpr
)
1681 u32 raw_cons
= cpr
->cp_raw_cons
;
1682 u16 cons
= RING_CMP(raw_cons
);
1683 struct tx_cmp
*txcmp
;
1685 txcmp
= &cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)];
1687 return TX_CMP_VALID(txcmp
, raw_cons
);
1690 static irqreturn_t
bnxt_inta(int irq
, void *dev_instance
)
1692 struct bnxt_napi
*bnapi
= dev_instance
;
1693 struct bnxt
*bp
= bnapi
->bp
;
1694 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1695 u32 cons
= RING_CMP(cpr
->cp_raw_cons
);
1698 prefetch(&cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)]);
1700 if (!bnxt_has_work(bp
, cpr
)) {
1701 int_status
= readl(bp
->bar0
+ BNXT_CAG_REG_LEGACY_INT_STATUS
);
1702 /* return if erroneous interrupt */
1703 if (!(int_status
& (0x10000 << cpr
->cp_ring_struct
.fw_ring_id
)))
1707 /* disable ring IRQ */
1708 BNXT_CP_DB_IRQ_DIS(cpr
->cp_doorbell
);
1710 /* Return here if interrupt is shared and is disabled. */
1711 if (unlikely(atomic_read(&bp
->intr_sem
) != 0))
1714 napi_schedule(&bnapi
->napi
);
1718 static int bnxt_poll_work(struct bnxt
*bp
, struct bnxt_napi
*bnapi
, int budget
)
1720 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1721 u32 raw_cons
= cpr
->cp_raw_cons
;
1726 struct tx_cmp
*txcmp
;
1731 cons
= RING_CMP(raw_cons
);
1732 txcmp
= &cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)];
1734 if (!TX_CMP_VALID(txcmp
, raw_cons
))
1737 /* The valid test of the entry must be done first before
1738 * reading any further.
1741 if (TX_CMP_TYPE(txcmp
) == CMP_TYPE_TX_L2_CMP
) {
1743 /* return full budget so NAPI will complete. */
1744 if (unlikely(tx_pkts
> bp
->tx_wake_thresh
))
1746 } else if ((TX_CMP_TYPE(txcmp
) & 0x30) == 0x10) {
1747 rc
= bnxt_rx_pkt(bp
, bnapi
, &raw_cons
, &event
);
1748 if (likely(rc
>= 0))
1750 else if (rc
== -EBUSY
) /* partial completion */
1752 } else if (unlikely((TX_CMP_TYPE(txcmp
) ==
1753 CMPL_BASE_TYPE_HWRM_DONE
) ||
1754 (TX_CMP_TYPE(txcmp
) ==
1755 CMPL_BASE_TYPE_HWRM_FWD_REQ
) ||
1756 (TX_CMP_TYPE(txcmp
) ==
1757 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT
))) {
1758 bnxt_hwrm_handler(bp
, txcmp
);
1760 raw_cons
= NEXT_RAW_CMP(raw_cons
);
1762 if (rx_pkts
== budget
)
1766 if (event
& BNXT_TX_EVENT
) {
1767 struct bnxt_tx_ring_info
*txr
= bnapi
->tx_ring
;
1768 void __iomem
*db
= txr
->tx_doorbell
;
1769 u16 prod
= txr
->tx_prod
;
1771 /* Sync BD data before updating doorbell */
1774 writel(DB_KEY_TX
| prod
, db
);
1775 writel(DB_KEY_TX
| prod
, db
);
1778 cpr
->cp_raw_cons
= raw_cons
;
1779 /* ACK completion ring before freeing tx ring and producing new
1780 * buffers in rx/agg rings to prevent overflowing the completion
1783 BNXT_CP_DB(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
1786 bnapi
->tx_int(bp
, bnapi
, tx_pkts
);
1788 if (event
& BNXT_RX_EVENT
) {
1789 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
1791 writel(DB_KEY_RX
| rxr
->rx_prod
, rxr
->rx_doorbell
);
1792 writel(DB_KEY_RX
| rxr
->rx_prod
, rxr
->rx_doorbell
);
1793 if (event
& BNXT_AGG_EVENT
) {
1794 writel(DB_KEY_RX
| rxr
->rx_agg_prod
,
1795 rxr
->rx_agg_doorbell
);
1796 writel(DB_KEY_RX
| rxr
->rx_agg_prod
,
1797 rxr
->rx_agg_doorbell
);
1803 static int bnxt_poll_nitroa0(struct napi_struct
*napi
, int budget
)
1805 struct bnxt_napi
*bnapi
= container_of(napi
, struct bnxt_napi
, napi
);
1806 struct bnxt
*bp
= bnapi
->bp
;
1807 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1808 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
1809 struct tx_cmp
*txcmp
;
1810 struct rx_cmp_ext
*rxcmp1
;
1811 u32 cp_cons
, tmp_raw_cons
;
1812 u32 raw_cons
= cpr
->cp_raw_cons
;
1819 cp_cons
= RING_CMP(raw_cons
);
1820 txcmp
= &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
1822 if (!TX_CMP_VALID(txcmp
, raw_cons
))
1825 if ((TX_CMP_TYPE(txcmp
) & 0x30) == 0x10) {
1826 tmp_raw_cons
= NEXT_RAW_CMP(raw_cons
);
1827 cp_cons
= RING_CMP(tmp_raw_cons
);
1828 rxcmp1
= (struct rx_cmp_ext
*)
1829 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
1831 if (!RX_CMP_VALID(rxcmp1
, tmp_raw_cons
))
1834 /* force an error to recycle the buffer */
1835 rxcmp1
->rx_cmp_cfa_code_errors_v2
|=
1836 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR
);
1838 rc
= bnxt_rx_pkt(bp
, bnapi
, &raw_cons
, &event
);
1839 if (likely(rc
== -EIO
))
1841 else if (rc
== -EBUSY
) /* partial completion */
1843 } else if (unlikely(TX_CMP_TYPE(txcmp
) ==
1844 CMPL_BASE_TYPE_HWRM_DONE
)) {
1845 bnxt_hwrm_handler(bp
, txcmp
);
1848 "Invalid completion received on special ring\n");
1850 raw_cons
= NEXT_RAW_CMP(raw_cons
);
1852 if (rx_pkts
== budget
)
1856 cpr
->cp_raw_cons
= raw_cons
;
1857 BNXT_CP_DB(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
1858 writel(DB_KEY_RX
| rxr
->rx_prod
, rxr
->rx_doorbell
);
1859 writel(DB_KEY_RX
| rxr
->rx_prod
, rxr
->rx_doorbell
);
1861 if (event
& BNXT_AGG_EVENT
) {
1862 writel(DB_KEY_RX
| rxr
->rx_agg_prod
, rxr
->rx_agg_doorbell
);
1863 writel(DB_KEY_RX
| rxr
->rx_agg_prod
, rxr
->rx_agg_doorbell
);
1866 if (!bnxt_has_work(bp
, cpr
) && rx_pkts
< budget
) {
1867 napi_complete_done(napi
, rx_pkts
);
1868 BNXT_CP_DB_REARM(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
1873 static int bnxt_poll(struct napi_struct
*napi
, int budget
)
1875 struct bnxt_napi
*bnapi
= container_of(napi
, struct bnxt_napi
, napi
);
1876 struct bnxt
*bp
= bnapi
->bp
;
1877 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1881 work_done
+= bnxt_poll_work(bp
, bnapi
, budget
- work_done
);
1883 if (work_done
>= budget
)
1886 if (!bnxt_has_work(bp
, cpr
)) {
1887 if (napi_complete_done(napi
, work_done
))
1888 BNXT_CP_DB_REARM(cpr
->cp_doorbell
,
1897 static void bnxt_free_tx_skbs(struct bnxt
*bp
)
1900 struct pci_dev
*pdev
= bp
->pdev
;
1905 max_idx
= bp
->tx_nr_pages
* TX_DESC_CNT
;
1906 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
1907 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
1910 for (j
= 0; j
< max_idx
;) {
1911 struct bnxt_sw_tx_bd
*tx_buf
= &txr
->tx_buf_ring
[j
];
1912 struct sk_buff
*skb
= tx_buf
->skb
;
1922 if (tx_buf
->is_push
) {
1928 dma_unmap_single(&pdev
->dev
,
1929 dma_unmap_addr(tx_buf
, mapping
),
1933 last
= tx_buf
->nr_frags
;
1935 for (k
= 0; k
< last
; k
++, j
++) {
1936 int ring_idx
= j
& bp
->tx_ring_mask
;
1937 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[k
];
1939 tx_buf
= &txr
->tx_buf_ring
[ring_idx
];
1942 dma_unmap_addr(tx_buf
, mapping
),
1943 skb_frag_size(frag
), PCI_DMA_TODEVICE
);
1947 netdev_tx_reset_queue(netdev_get_tx_queue(bp
->dev
, i
));
1951 static void bnxt_free_rx_skbs(struct bnxt
*bp
)
1953 int i
, max_idx
, max_agg_idx
;
1954 struct pci_dev
*pdev
= bp
->pdev
;
1959 max_idx
= bp
->rx_nr_pages
* RX_DESC_CNT
;
1960 max_agg_idx
= bp
->rx_agg_nr_pages
* RX_DESC_CNT
;
1961 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
1962 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
1966 for (j
= 0; j
< MAX_TPA
; j
++) {
1967 struct bnxt_tpa_info
*tpa_info
=
1969 u8
*data
= tpa_info
->data
;
1974 dma_unmap_single(&pdev
->dev
, tpa_info
->mapping
,
1975 bp
->rx_buf_use_size
,
1978 tpa_info
->data
= NULL
;
1984 for (j
= 0; j
< max_idx
; j
++) {
1985 struct bnxt_sw_rx_bd
*rx_buf
= &rxr
->rx_buf_ring
[j
];
1986 dma_addr_t mapping
= rx_buf
->mapping
;
1987 void *data
= rx_buf
->data
;
1992 rx_buf
->data
= NULL
;
1994 if (BNXT_RX_PAGE_MODE(bp
)) {
1995 mapping
-= bp
->rx_dma_offset
;
1996 dma_unmap_page(&pdev
->dev
, mapping
,
1997 PAGE_SIZE
, bp
->rx_dir
);
2000 dma_unmap_single(&pdev
->dev
, mapping
,
2001 bp
->rx_buf_use_size
,
2007 for (j
= 0; j
< max_agg_idx
; j
++) {
2008 struct bnxt_sw_rx_agg_bd
*rx_agg_buf
=
2009 &rxr
->rx_agg_ring
[j
];
2010 struct page
*page
= rx_agg_buf
->page
;
2015 dma_unmap_page(&pdev
->dev
, rx_agg_buf
->mapping
,
2016 BNXT_RX_PAGE_SIZE
, PCI_DMA_FROMDEVICE
);
2018 rx_agg_buf
->page
= NULL
;
2019 __clear_bit(j
, rxr
->rx_agg_bmap
);
2024 __free_page(rxr
->rx_page
);
2025 rxr
->rx_page
= NULL
;
2030 static void bnxt_free_skbs(struct bnxt
*bp
)
2032 bnxt_free_tx_skbs(bp
);
2033 bnxt_free_rx_skbs(bp
);
2036 static void bnxt_free_ring(struct bnxt
*bp
, struct bnxt_ring_struct
*ring
)
2038 struct pci_dev
*pdev
= bp
->pdev
;
2041 for (i
= 0; i
< ring
->nr_pages
; i
++) {
2042 if (!ring
->pg_arr
[i
])
2045 dma_free_coherent(&pdev
->dev
, ring
->page_size
,
2046 ring
->pg_arr
[i
], ring
->dma_arr
[i
]);
2048 ring
->pg_arr
[i
] = NULL
;
2051 dma_free_coherent(&pdev
->dev
, ring
->nr_pages
* 8,
2052 ring
->pg_tbl
, ring
->pg_tbl_map
);
2053 ring
->pg_tbl
= NULL
;
2055 if (ring
->vmem_size
&& *ring
->vmem
) {
2061 static int bnxt_alloc_ring(struct bnxt
*bp
, struct bnxt_ring_struct
*ring
)
2064 struct pci_dev
*pdev
= bp
->pdev
;
2066 if (ring
->nr_pages
> 1) {
2067 ring
->pg_tbl
= dma_alloc_coherent(&pdev
->dev
,
2075 for (i
= 0; i
< ring
->nr_pages
; i
++) {
2076 ring
->pg_arr
[i
] = dma_alloc_coherent(&pdev
->dev
,
2080 if (!ring
->pg_arr
[i
])
2083 if (ring
->nr_pages
> 1)
2084 ring
->pg_tbl
[i
] = cpu_to_le64(ring
->dma_arr
[i
]);
2087 if (ring
->vmem_size
) {
2088 *ring
->vmem
= vzalloc(ring
->vmem_size
);
2095 static void bnxt_free_rx_rings(struct bnxt
*bp
)
2102 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
2103 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
2104 struct bnxt_ring_struct
*ring
;
2107 bpf_prog_put(rxr
->xdp_prog
);
2112 kfree(rxr
->rx_agg_bmap
);
2113 rxr
->rx_agg_bmap
= NULL
;
2115 ring
= &rxr
->rx_ring_struct
;
2116 bnxt_free_ring(bp
, ring
);
2118 ring
= &rxr
->rx_agg_ring_struct
;
2119 bnxt_free_ring(bp
, ring
);
2123 static int bnxt_alloc_rx_rings(struct bnxt
*bp
)
2125 int i
, rc
, agg_rings
= 0, tpa_rings
= 0;
2130 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
)
2133 if (bp
->flags
& BNXT_FLAG_TPA
)
2136 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
2137 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
2138 struct bnxt_ring_struct
*ring
;
2140 ring
= &rxr
->rx_ring_struct
;
2142 rc
= bnxt_alloc_ring(bp
, ring
);
2149 ring
= &rxr
->rx_agg_ring_struct
;
2150 rc
= bnxt_alloc_ring(bp
, ring
);
2154 rxr
->rx_agg_bmap_size
= bp
->rx_agg_ring_mask
+ 1;
2155 mem_size
= rxr
->rx_agg_bmap_size
/ 8;
2156 rxr
->rx_agg_bmap
= kzalloc(mem_size
, GFP_KERNEL
);
2157 if (!rxr
->rx_agg_bmap
)
2161 rxr
->rx_tpa
= kcalloc(MAX_TPA
,
2162 sizeof(struct bnxt_tpa_info
),
2172 static void bnxt_free_tx_rings(struct bnxt
*bp
)
2175 struct pci_dev
*pdev
= bp
->pdev
;
2180 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
2181 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
2182 struct bnxt_ring_struct
*ring
;
2185 dma_free_coherent(&pdev
->dev
, bp
->tx_push_size
,
2186 txr
->tx_push
, txr
->tx_push_mapping
);
2187 txr
->tx_push
= NULL
;
2190 ring
= &txr
->tx_ring_struct
;
2192 bnxt_free_ring(bp
, ring
);
2196 static int bnxt_alloc_tx_rings(struct bnxt
*bp
)
2199 struct pci_dev
*pdev
= bp
->pdev
;
2201 bp
->tx_push_size
= 0;
2202 if (bp
->tx_push_thresh
) {
2205 push_size
= L1_CACHE_ALIGN(sizeof(struct tx_push_bd
) +
2206 bp
->tx_push_thresh
);
2208 if (push_size
> 256) {
2210 bp
->tx_push_thresh
= 0;
2213 bp
->tx_push_size
= push_size
;
2216 for (i
= 0, j
= 0; i
< bp
->tx_nr_rings
; i
++) {
2217 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
2218 struct bnxt_ring_struct
*ring
;
2220 ring
= &txr
->tx_ring_struct
;
2222 rc
= bnxt_alloc_ring(bp
, ring
);
2226 if (bp
->tx_push_size
) {
2229 /* One pre-allocated DMA buffer to backup
2232 txr
->tx_push
= dma_alloc_coherent(&pdev
->dev
,
2234 &txr
->tx_push_mapping
,
2240 mapping
= txr
->tx_push_mapping
+
2241 sizeof(struct tx_push_bd
);
2242 txr
->data_mapping
= cpu_to_le64(mapping
);
2244 memset(txr
->tx_push
, 0, sizeof(struct tx_push_bd
));
2246 ring
->queue_id
= bp
->q_info
[j
].queue_id
;
2247 if (i
< bp
->tx_nr_rings_xdp
)
2249 if (i
% bp
->tx_nr_rings_per_tc
== (bp
->tx_nr_rings_per_tc
- 1))
2255 static void bnxt_free_cp_rings(struct bnxt
*bp
)
2262 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2263 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2264 struct bnxt_cp_ring_info
*cpr
;
2265 struct bnxt_ring_struct
*ring
;
2270 cpr
= &bnapi
->cp_ring
;
2271 ring
= &cpr
->cp_ring_struct
;
2273 bnxt_free_ring(bp
, ring
);
2277 static int bnxt_alloc_cp_rings(struct bnxt
*bp
)
2281 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2282 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2283 struct bnxt_cp_ring_info
*cpr
;
2284 struct bnxt_ring_struct
*ring
;
2289 cpr
= &bnapi
->cp_ring
;
2290 ring
= &cpr
->cp_ring_struct
;
2292 rc
= bnxt_alloc_ring(bp
, ring
);
2299 static void bnxt_init_ring_struct(struct bnxt
*bp
)
2303 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2304 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2305 struct bnxt_cp_ring_info
*cpr
;
2306 struct bnxt_rx_ring_info
*rxr
;
2307 struct bnxt_tx_ring_info
*txr
;
2308 struct bnxt_ring_struct
*ring
;
2313 cpr
= &bnapi
->cp_ring
;
2314 ring
= &cpr
->cp_ring_struct
;
2315 ring
->nr_pages
= bp
->cp_nr_pages
;
2316 ring
->page_size
= HW_CMPD_RING_SIZE
;
2317 ring
->pg_arr
= (void **)cpr
->cp_desc_ring
;
2318 ring
->dma_arr
= cpr
->cp_desc_mapping
;
2319 ring
->vmem_size
= 0;
2321 rxr
= bnapi
->rx_ring
;
2325 ring
= &rxr
->rx_ring_struct
;
2326 ring
->nr_pages
= bp
->rx_nr_pages
;
2327 ring
->page_size
= HW_RXBD_RING_SIZE
;
2328 ring
->pg_arr
= (void **)rxr
->rx_desc_ring
;
2329 ring
->dma_arr
= rxr
->rx_desc_mapping
;
2330 ring
->vmem_size
= SW_RXBD_RING_SIZE
* bp
->rx_nr_pages
;
2331 ring
->vmem
= (void **)&rxr
->rx_buf_ring
;
2333 ring
= &rxr
->rx_agg_ring_struct
;
2334 ring
->nr_pages
= bp
->rx_agg_nr_pages
;
2335 ring
->page_size
= HW_RXBD_RING_SIZE
;
2336 ring
->pg_arr
= (void **)rxr
->rx_agg_desc_ring
;
2337 ring
->dma_arr
= rxr
->rx_agg_desc_mapping
;
2338 ring
->vmem_size
= SW_RXBD_AGG_RING_SIZE
* bp
->rx_agg_nr_pages
;
2339 ring
->vmem
= (void **)&rxr
->rx_agg_ring
;
2342 txr
= bnapi
->tx_ring
;
2346 ring
= &txr
->tx_ring_struct
;
2347 ring
->nr_pages
= bp
->tx_nr_pages
;
2348 ring
->page_size
= HW_RXBD_RING_SIZE
;
2349 ring
->pg_arr
= (void **)txr
->tx_desc_ring
;
2350 ring
->dma_arr
= txr
->tx_desc_mapping
;
2351 ring
->vmem_size
= SW_TXBD_RING_SIZE
* bp
->tx_nr_pages
;
2352 ring
->vmem
= (void **)&txr
->tx_buf_ring
;
2356 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct
*ring
, u32 type
)
2360 struct rx_bd
**rx_buf_ring
;
2362 rx_buf_ring
= (struct rx_bd
**)ring
->pg_arr
;
2363 for (i
= 0, prod
= 0; i
< ring
->nr_pages
; i
++) {
2367 rxbd
= rx_buf_ring
[i
];
2371 for (j
= 0; j
< RX_DESC_CNT
; j
++, rxbd
++, prod
++) {
2372 rxbd
->rx_bd_len_flags_type
= cpu_to_le32(type
);
2373 rxbd
->rx_bd_opaque
= prod
;
2378 static int bnxt_init_one_rx_ring(struct bnxt
*bp
, int ring_nr
)
2380 struct net_device
*dev
= bp
->dev
;
2381 struct bnxt_rx_ring_info
*rxr
;
2382 struct bnxt_ring_struct
*ring
;
2386 type
= (bp
->rx_buf_use_size
<< RX_BD_LEN_SHIFT
) |
2387 RX_BD_TYPE_RX_PACKET_BD
| RX_BD_FLAGS_EOP
;
2389 if (NET_IP_ALIGN
== 2)
2390 type
|= RX_BD_FLAGS_SOP
;
2392 rxr
= &bp
->rx_ring
[ring_nr
];
2393 ring
= &rxr
->rx_ring_struct
;
2394 bnxt_init_rxbd_pages(ring
, type
);
2396 if (BNXT_RX_PAGE_MODE(bp
) && bp
->xdp_prog
) {
2397 rxr
->xdp_prog
= bpf_prog_add(bp
->xdp_prog
, 1);
2398 if (IS_ERR(rxr
->xdp_prog
)) {
2399 int rc
= PTR_ERR(rxr
->xdp_prog
);
2401 rxr
->xdp_prog
= NULL
;
2405 prod
= rxr
->rx_prod
;
2406 for (i
= 0; i
< bp
->rx_ring_size
; i
++) {
2407 if (bnxt_alloc_rx_data(bp
, rxr
, prod
, GFP_KERNEL
) != 0) {
2408 netdev_warn(dev
, "init'ed rx ring %d with %d/%d skbs only\n",
2409 ring_nr
, i
, bp
->rx_ring_size
);
2412 prod
= NEXT_RX(prod
);
2414 rxr
->rx_prod
= prod
;
2415 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
2417 ring
= &rxr
->rx_agg_ring_struct
;
2418 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
2420 if (!(bp
->flags
& BNXT_FLAG_AGG_RINGS
))
2423 type
= ((u32
)BNXT_RX_PAGE_SIZE
<< RX_BD_LEN_SHIFT
) |
2424 RX_BD_TYPE_RX_AGG_BD
| RX_BD_FLAGS_SOP
;
2426 bnxt_init_rxbd_pages(ring
, type
);
2428 prod
= rxr
->rx_agg_prod
;
2429 for (i
= 0; i
< bp
->rx_agg_ring_size
; i
++) {
2430 if (bnxt_alloc_rx_page(bp
, rxr
, prod
, GFP_KERNEL
) != 0) {
2431 netdev_warn(dev
, "init'ed rx ring %d with %d/%d pages only\n",
2432 ring_nr
, i
, bp
->rx_ring_size
);
2435 prod
= NEXT_RX_AGG(prod
);
2437 rxr
->rx_agg_prod
= prod
;
2439 if (bp
->flags
& BNXT_FLAG_TPA
) {
2444 for (i
= 0; i
< MAX_TPA
; i
++) {
2445 data
= __bnxt_alloc_rx_data(bp
, &mapping
,
2450 rxr
->rx_tpa
[i
].data
= data
;
2451 rxr
->rx_tpa
[i
].data_ptr
= data
+ bp
->rx_offset
;
2452 rxr
->rx_tpa
[i
].mapping
= mapping
;
2455 netdev_err(bp
->dev
, "No resource allocated for LRO/GRO\n");
2463 static void bnxt_init_cp_rings(struct bnxt
*bp
)
2467 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2468 struct bnxt_cp_ring_info
*cpr
= &bp
->bnapi
[i
]->cp_ring
;
2469 struct bnxt_ring_struct
*ring
= &cpr
->cp_ring_struct
;
2471 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
2475 static int bnxt_init_rx_rings(struct bnxt
*bp
)
2479 if (BNXT_RX_PAGE_MODE(bp
)) {
2480 bp
->rx_offset
= NET_IP_ALIGN
+ XDP_PACKET_HEADROOM
;
2481 bp
->rx_dma_offset
= XDP_PACKET_HEADROOM
;
2483 bp
->rx_offset
= BNXT_RX_OFFSET
;
2484 bp
->rx_dma_offset
= BNXT_RX_DMA_OFFSET
;
2487 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
2488 rc
= bnxt_init_one_rx_ring(bp
, i
);
2496 static int bnxt_init_tx_rings(struct bnxt
*bp
)
2500 bp
->tx_wake_thresh
= max_t(int, bp
->tx_ring_size
/ 2,
2503 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
2504 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
2505 struct bnxt_ring_struct
*ring
= &txr
->tx_ring_struct
;
2507 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
2513 static void bnxt_free_ring_grps(struct bnxt
*bp
)
2515 kfree(bp
->grp_info
);
2516 bp
->grp_info
= NULL
;
2519 static int bnxt_init_ring_grps(struct bnxt
*bp
, bool irq_re_init
)
2524 bp
->grp_info
= kcalloc(bp
->cp_nr_rings
,
2525 sizeof(struct bnxt_ring_grp_info
),
2530 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2532 bp
->grp_info
[i
].fw_stats_ctx
= INVALID_HW_RING_ID
;
2533 bp
->grp_info
[i
].fw_grp_id
= INVALID_HW_RING_ID
;
2534 bp
->grp_info
[i
].rx_fw_ring_id
= INVALID_HW_RING_ID
;
2535 bp
->grp_info
[i
].agg_fw_ring_id
= INVALID_HW_RING_ID
;
2536 bp
->grp_info
[i
].cp_fw_ring_id
= INVALID_HW_RING_ID
;
2541 static void bnxt_free_vnics(struct bnxt
*bp
)
2543 kfree(bp
->vnic_info
);
2544 bp
->vnic_info
= NULL
;
2548 static int bnxt_alloc_vnics(struct bnxt
*bp
)
2552 #ifdef CONFIG_RFS_ACCEL
2553 if (bp
->flags
& BNXT_FLAG_RFS
)
2554 num_vnics
+= bp
->rx_nr_rings
;
2557 if (BNXT_CHIP_TYPE_NITRO_A0(bp
))
2560 bp
->vnic_info
= kcalloc(num_vnics
, sizeof(struct bnxt_vnic_info
),
2565 bp
->nr_vnics
= num_vnics
;
2569 static void bnxt_init_vnics(struct bnxt
*bp
)
2573 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
2574 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[i
];
2576 vnic
->fw_vnic_id
= INVALID_HW_RING_ID
;
2577 vnic
->fw_rss_cos_lb_ctx
[0] = INVALID_HW_RING_ID
;
2578 vnic
->fw_rss_cos_lb_ctx
[1] = INVALID_HW_RING_ID
;
2579 vnic
->fw_l2_ctx_id
= INVALID_HW_RING_ID
;
2581 if (bp
->vnic_info
[i
].rss_hash_key
) {
2583 prandom_bytes(vnic
->rss_hash_key
,
2586 memcpy(vnic
->rss_hash_key
,
2587 bp
->vnic_info
[0].rss_hash_key
,
2593 static int bnxt_calc_nr_ring_pages(u32 ring_size
, int desc_per_pg
)
2597 pages
= ring_size
/ desc_per_pg
;
2604 while (pages
& (pages
- 1))
2610 void bnxt_set_tpa_flags(struct bnxt
*bp
)
2612 bp
->flags
&= ~BNXT_FLAG_TPA
;
2613 if (bp
->flags
& BNXT_FLAG_NO_AGG_RINGS
)
2615 if (bp
->dev
->features
& NETIF_F_LRO
)
2616 bp
->flags
|= BNXT_FLAG_LRO
;
2617 if (bp
->dev
->features
& NETIF_F_GRO
)
2618 bp
->flags
|= BNXT_FLAG_GRO
;
2621 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2624 void bnxt_set_ring_params(struct bnxt
*bp
)
2626 u32 ring_size
, rx_size
, rx_space
;
2627 u32 agg_factor
= 0, agg_ring_size
= 0;
2629 /* 8 for CRC and VLAN */
2630 rx_size
= SKB_DATA_ALIGN(bp
->dev
->mtu
+ ETH_HLEN
+ NET_IP_ALIGN
+ 8);
2632 rx_space
= rx_size
+ NET_SKB_PAD
+
2633 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
2635 bp
->rx_copy_thresh
= BNXT_RX_COPY_THRESH
;
2636 ring_size
= bp
->rx_ring_size
;
2637 bp
->rx_agg_ring_size
= 0;
2638 bp
->rx_agg_nr_pages
= 0;
2640 if (bp
->flags
& BNXT_FLAG_TPA
)
2641 agg_factor
= min_t(u32
, 4, 65536 / BNXT_RX_PAGE_SIZE
);
2643 bp
->flags
&= ~BNXT_FLAG_JUMBO
;
2644 if (rx_space
> PAGE_SIZE
&& !(bp
->flags
& BNXT_FLAG_NO_AGG_RINGS
)) {
2647 bp
->flags
|= BNXT_FLAG_JUMBO
;
2648 jumbo_factor
= PAGE_ALIGN(bp
->dev
->mtu
- 40) >> PAGE_SHIFT
;
2649 if (jumbo_factor
> agg_factor
)
2650 agg_factor
= jumbo_factor
;
2652 agg_ring_size
= ring_size
* agg_factor
;
2654 if (agg_ring_size
) {
2655 bp
->rx_agg_nr_pages
= bnxt_calc_nr_ring_pages(agg_ring_size
,
2657 if (bp
->rx_agg_nr_pages
> MAX_RX_AGG_PAGES
) {
2658 u32 tmp
= agg_ring_size
;
2660 bp
->rx_agg_nr_pages
= MAX_RX_AGG_PAGES
;
2661 agg_ring_size
= MAX_RX_AGG_PAGES
* RX_DESC_CNT
- 1;
2662 netdev_warn(bp
->dev
, "rx agg ring size %d reduced to %d.\n",
2663 tmp
, agg_ring_size
);
2665 bp
->rx_agg_ring_size
= agg_ring_size
;
2666 bp
->rx_agg_ring_mask
= (bp
->rx_agg_nr_pages
* RX_DESC_CNT
) - 1;
2667 rx_size
= SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH
+ NET_IP_ALIGN
);
2668 rx_space
= rx_size
+ NET_SKB_PAD
+
2669 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
2672 bp
->rx_buf_use_size
= rx_size
;
2673 bp
->rx_buf_size
= rx_space
;
2675 bp
->rx_nr_pages
= bnxt_calc_nr_ring_pages(ring_size
, RX_DESC_CNT
);
2676 bp
->rx_ring_mask
= (bp
->rx_nr_pages
* RX_DESC_CNT
) - 1;
2678 ring_size
= bp
->tx_ring_size
;
2679 bp
->tx_nr_pages
= bnxt_calc_nr_ring_pages(ring_size
, TX_DESC_CNT
);
2680 bp
->tx_ring_mask
= (bp
->tx_nr_pages
* TX_DESC_CNT
) - 1;
2682 ring_size
= bp
->rx_ring_size
* (2 + agg_factor
) + bp
->tx_ring_size
;
2683 bp
->cp_ring_size
= ring_size
;
2685 bp
->cp_nr_pages
= bnxt_calc_nr_ring_pages(ring_size
, CP_DESC_CNT
);
2686 if (bp
->cp_nr_pages
> MAX_CP_PAGES
) {
2687 bp
->cp_nr_pages
= MAX_CP_PAGES
;
2688 bp
->cp_ring_size
= MAX_CP_PAGES
* CP_DESC_CNT
- 1;
2689 netdev_warn(bp
->dev
, "completion ring size %d reduced to %d.\n",
2690 ring_size
, bp
->cp_ring_size
);
2692 bp
->cp_bit
= bp
->cp_nr_pages
* CP_DESC_CNT
;
2693 bp
->cp_ring_mask
= bp
->cp_bit
- 1;
2696 int bnxt_set_rx_skb_mode(struct bnxt
*bp
, bool page_mode
)
2699 if (bp
->dev
->mtu
> BNXT_MAX_PAGE_MODE_MTU
)
2701 bp
->dev
->max_mtu
= BNXT_MAX_PAGE_MODE_MTU
;
2702 bp
->flags
&= ~BNXT_FLAG_AGG_RINGS
;
2703 bp
->flags
|= BNXT_FLAG_NO_AGG_RINGS
| BNXT_FLAG_RX_PAGE_MODE
;
2704 bp
->dev
->hw_features
&= ~NETIF_F_LRO
;
2705 bp
->dev
->features
&= ~NETIF_F_LRO
;
2706 bp
->rx_dir
= DMA_BIDIRECTIONAL
;
2707 bp
->rx_skb_func
= bnxt_rx_page_skb
;
2709 bp
->dev
->max_mtu
= BNXT_MAX_MTU
;
2710 bp
->flags
&= ~BNXT_FLAG_RX_PAGE_MODE
;
2711 bp
->rx_dir
= DMA_FROM_DEVICE
;
2712 bp
->rx_skb_func
= bnxt_rx_skb
;
2717 static void bnxt_free_vnic_attributes(struct bnxt
*bp
)
2720 struct bnxt_vnic_info
*vnic
;
2721 struct pci_dev
*pdev
= bp
->pdev
;
2726 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
2727 vnic
= &bp
->vnic_info
[i
];
2729 kfree(vnic
->fw_grp_ids
);
2730 vnic
->fw_grp_ids
= NULL
;
2732 kfree(vnic
->uc_list
);
2733 vnic
->uc_list
= NULL
;
2735 if (vnic
->mc_list
) {
2736 dma_free_coherent(&pdev
->dev
, vnic
->mc_list_size
,
2737 vnic
->mc_list
, vnic
->mc_list_mapping
);
2738 vnic
->mc_list
= NULL
;
2741 if (vnic
->rss_table
) {
2742 dma_free_coherent(&pdev
->dev
, PAGE_SIZE
,
2744 vnic
->rss_table_dma_addr
);
2745 vnic
->rss_table
= NULL
;
2748 vnic
->rss_hash_key
= NULL
;
2753 static int bnxt_alloc_vnic_attributes(struct bnxt
*bp
)
2755 int i
, rc
= 0, size
;
2756 struct bnxt_vnic_info
*vnic
;
2757 struct pci_dev
*pdev
= bp
->pdev
;
2760 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
2761 vnic
= &bp
->vnic_info
[i
];
2763 if (vnic
->flags
& BNXT_VNIC_UCAST_FLAG
) {
2764 int mem_size
= (BNXT_MAX_UC_ADDRS
- 1) * ETH_ALEN
;
2767 vnic
->uc_list
= kmalloc(mem_size
, GFP_KERNEL
);
2768 if (!vnic
->uc_list
) {
2775 if (vnic
->flags
& BNXT_VNIC_MCAST_FLAG
) {
2776 vnic
->mc_list_size
= BNXT_MAX_MC_ADDRS
* ETH_ALEN
;
2778 dma_alloc_coherent(&pdev
->dev
,
2780 &vnic
->mc_list_mapping
,
2782 if (!vnic
->mc_list
) {
2788 if (vnic
->flags
& BNXT_VNIC_RSS_FLAG
)
2789 max_rings
= bp
->rx_nr_rings
;
2793 vnic
->fw_grp_ids
= kcalloc(max_rings
, sizeof(u16
), GFP_KERNEL
);
2794 if (!vnic
->fw_grp_ids
) {
2799 if ((bp
->flags
& BNXT_FLAG_NEW_RSS_CAP
) &&
2800 !(vnic
->flags
& BNXT_VNIC_RSS_FLAG
))
2803 /* Allocate rss table and hash key */
2804 vnic
->rss_table
= dma_alloc_coherent(&pdev
->dev
, PAGE_SIZE
,
2805 &vnic
->rss_table_dma_addr
,
2807 if (!vnic
->rss_table
) {
2812 size
= L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE
* sizeof(u16
));
2814 vnic
->rss_hash_key
= ((void *)vnic
->rss_table
) + size
;
2815 vnic
->rss_hash_key_dma_addr
= vnic
->rss_table_dma_addr
+ size
;
2823 static void bnxt_free_hwrm_resources(struct bnxt
*bp
)
2825 struct pci_dev
*pdev
= bp
->pdev
;
2827 dma_free_coherent(&pdev
->dev
, PAGE_SIZE
, bp
->hwrm_cmd_resp_addr
,
2828 bp
->hwrm_cmd_resp_dma_addr
);
2830 bp
->hwrm_cmd_resp_addr
= NULL
;
2831 if (bp
->hwrm_dbg_resp_addr
) {
2832 dma_free_coherent(&pdev
->dev
, HWRM_DBG_REG_BUF_SIZE
,
2833 bp
->hwrm_dbg_resp_addr
,
2834 bp
->hwrm_dbg_resp_dma_addr
);
2836 bp
->hwrm_dbg_resp_addr
= NULL
;
2840 static int bnxt_alloc_hwrm_resources(struct bnxt
*bp
)
2842 struct pci_dev
*pdev
= bp
->pdev
;
2844 bp
->hwrm_cmd_resp_addr
= dma_alloc_coherent(&pdev
->dev
, PAGE_SIZE
,
2845 &bp
->hwrm_cmd_resp_dma_addr
,
2847 if (!bp
->hwrm_cmd_resp_addr
)
2849 bp
->hwrm_dbg_resp_addr
= dma_alloc_coherent(&pdev
->dev
,
2850 HWRM_DBG_REG_BUF_SIZE
,
2851 &bp
->hwrm_dbg_resp_dma_addr
,
2853 if (!bp
->hwrm_dbg_resp_addr
)
2854 netdev_warn(bp
->dev
, "fail to alloc debug register dma mem\n");
2859 static void bnxt_free_stats(struct bnxt
*bp
)
2862 struct pci_dev
*pdev
= bp
->pdev
;
2864 if (bp
->hw_rx_port_stats
) {
2865 dma_free_coherent(&pdev
->dev
, bp
->hw_port_stats_size
,
2866 bp
->hw_rx_port_stats
,
2867 bp
->hw_rx_port_stats_map
);
2868 bp
->hw_rx_port_stats
= NULL
;
2869 bp
->flags
&= ~BNXT_FLAG_PORT_STATS
;
2875 size
= sizeof(struct ctx_hw_stats
);
2877 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2878 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2879 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
2881 if (cpr
->hw_stats
) {
2882 dma_free_coherent(&pdev
->dev
, size
, cpr
->hw_stats
,
2884 cpr
->hw_stats
= NULL
;
2889 static int bnxt_alloc_stats(struct bnxt
*bp
)
2892 struct pci_dev
*pdev
= bp
->pdev
;
2894 size
= sizeof(struct ctx_hw_stats
);
2896 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2897 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2898 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
2900 cpr
->hw_stats
= dma_alloc_coherent(&pdev
->dev
, size
,
2906 cpr
->hw_stats_ctx_id
= INVALID_STATS_CTX_ID
;
2909 if (BNXT_PF(bp
) && bp
->chip_num
!= CHIP_NUM_58700
) {
2910 bp
->hw_port_stats_size
= sizeof(struct rx_port_stats
) +
2911 sizeof(struct tx_port_stats
) + 1024;
2913 bp
->hw_rx_port_stats
=
2914 dma_alloc_coherent(&pdev
->dev
, bp
->hw_port_stats_size
,
2915 &bp
->hw_rx_port_stats_map
,
2917 if (!bp
->hw_rx_port_stats
)
2920 bp
->hw_tx_port_stats
= (void *)(bp
->hw_rx_port_stats
+ 1) +
2922 bp
->hw_tx_port_stats_map
= bp
->hw_rx_port_stats_map
+
2923 sizeof(struct rx_port_stats
) + 512;
2924 bp
->flags
|= BNXT_FLAG_PORT_STATS
;
2929 static void bnxt_clear_ring_indices(struct bnxt
*bp
)
2936 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2937 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2938 struct bnxt_cp_ring_info
*cpr
;
2939 struct bnxt_rx_ring_info
*rxr
;
2940 struct bnxt_tx_ring_info
*txr
;
2945 cpr
= &bnapi
->cp_ring
;
2946 cpr
->cp_raw_cons
= 0;
2948 txr
= bnapi
->tx_ring
;
2954 rxr
= bnapi
->rx_ring
;
2957 rxr
->rx_agg_prod
= 0;
2958 rxr
->rx_sw_agg_prod
= 0;
2959 rxr
->rx_next_cons
= 0;
2964 static void bnxt_free_ntp_fltrs(struct bnxt
*bp
, bool irq_reinit
)
2966 #ifdef CONFIG_RFS_ACCEL
2969 /* Under rtnl_lock and all our NAPIs have been disabled. It's
2970 * safe to delete the hash table.
2972 for (i
= 0; i
< BNXT_NTP_FLTR_HASH_SIZE
; i
++) {
2973 struct hlist_head
*head
;
2974 struct hlist_node
*tmp
;
2975 struct bnxt_ntuple_filter
*fltr
;
2977 head
= &bp
->ntp_fltr_hash_tbl
[i
];
2978 hlist_for_each_entry_safe(fltr
, tmp
, head
, hash
) {
2979 hlist_del(&fltr
->hash
);
2984 kfree(bp
->ntp_fltr_bmap
);
2985 bp
->ntp_fltr_bmap
= NULL
;
2987 bp
->ntp_fltr_count
= 0;
2991 static int bnxt_alloc_ntp_fltrs(struct bnxt
*bp
)
2993 #ifdef CONFIG_RFS_ACCEL
2996 if (!(bp
->flags
& BNXT_FLAG_RFS
))
2999 for (i
= 0; i
< BNXT_NTP_FLTR_HASH_SIZE
; i
++)
3000 INIT_HLIST_HEAD(&bp
->ntp_fltr_hash_tbl
[i
]);
3002 bp
->ntp_fltr_count
= 0;
3003 bp
->ntp_fltr_bmap
= kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR
),
3007 if (!bp
->ntp_fltr_bmap
)
3016 static void bnxt_free_mem(struct bnxt
*bp
, bool irq_re_init
)
3018 bnxt_free_vnic_attributes(bp
);
3019 bnxt_free_tx_rings(bp
);
3020 bnxt_free_rx_rings(bp
);
3021 bnxt_free_cp_rings(bp
);
3022 bnxt_free_ntp_fltrs(bp
, irq_re_init
);
3024 bnxt_free_stats(bp
);
3025 bnxt_free_ring_grps(bp
);
3026 bnxt_free_vnics(bp
);
3027 kfree(bp
->tx_ring_map
);
3028 bp
->tx_ring_map
= NULL
;
3036 bnxt_clear_ring_indices(bp
);
3040 static int bnxt_alloc_mem(struct bnxt
*bp
, bool irq_re_init
)
3042 int i
, j
, rc
, size
, arr_size
;
3046 /* Allocate bnapi mem pointer array and mem block for
3049 arr_size
= L1_CACHE_ALIGN(sizeof(struct bnxt_napi
*) *
3051 size
= L1_CACHE_ALIGN(sizeof(struct bnxt_napi
));
3052 bnapi
= kzalloc(arr_size
+ size
* bp
->cp_nr_rings
, GFP_KERNEL
);
3058 for (i
= 0; i
< bp
->cp_nr_rings
; i
++, bnapi
+= size
) {
3059 bp
->bnapi
[i
] = bnapi
;
3060 bp
->bnapi
[i
]->index
= i
;
3061 bp
->bnapi
[i
]->bp
= bp
;
3064 bp
->rx_ring
= kcalloc(bp
->rx_nr_rings
,
3065 sizeof(struct bnxt_rx_ring_info
),
3070 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3071 bp
->rx_ring
[i
].bnapi
= bp
->bnapi
[i
];
3072 bp
->bnapi
[i
]->rx_ring
= &bp
->rx_ring
[i
];
3075 bp
->tx_ring
= kcalloc(bp
->tx_nr_rings
,
3076 sizeof(struct bnxt_tx_ring_info
),
3081 bp
->tx_ring_map
= kcalloc(bp
->tx_nr_rings
, sizeof(u16
),
3084 if (!bp
->tx_ring_map
)
3087 if (bp
->flags
& BNXT_FLAG_SHARED_RINGS
)
3090 j
= bp
->rx_nr_rings
;
3092 for (i
= 0; i
< bp
->tx_nr_rings
; i
++, j
++) {
3093 bp
->tx_ring
[i
].bnapi
= bp
->bnapi
[j
];
3094 bp
->bnapi
[j
]->tx_ring
= &bp
->tx_ring
[i
];
3095 bp
->tx_ring_map
[i
] = bp
->tx_nr_rings_xdp
+ i
;
3096 if (i
>= bp
->tx_nr_rings_xdp
) {
3097 bp
->tx_ring
[i
].txq_index
= i
-
3098 bp
->tx_nr_rings_xdp
;
3099 bp
->bnapi
[j
]->tx_int
= bnxt_tx_int
;
3101 bp
->bnapi
[j
]->flags
|= BNXT_NAPI_FLAG_XDP
;
3102 bp
->bnapi
[j
]->tx_int
= bnxt_tx_int_xdp
;
3106 rc
= bnxt_alloc_stats(bp
);
3110 rc
= bnxt_alloc_ntp_fltrs(bp
);
3114 rc
= bnxt_alloc_vnics(bp
);
3119 bnxt_init_ring_struct(bp
);
3121 rc
= bnxt_alloc_rx_rings(bp
);
3125 rc
= bnxt_alloc_tx_rings(bp
);
3129 rc
= bnxt_alloc_cp_rings(bp
);
3133 bp
->vnic_info
[0].flags
|= BNXT_VNIC_RSS_FLAG
| BNXT_VNIC_MCAST_FLAG
|
3134 BNXT_VNIC_UCAST_FLAG
;
3135 rc
= bnxt_alloc_vnic_attributes(bp
);
3141 bnxt_free_mem(bp
, true);
3145 static void bnxt_disable_int(struct bnxt
*bp
)
3152 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3153 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3154 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3155 struct bnxt_ring_struct
*ring
= &cpr
->cp_ring_struct
;
3157 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
)
3158 BNXT_CP_DB(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
3162 static void bnxt_disable_int_sync(struct bnxt
*bp
)
3166 atomic_inc(&bp
->intr_sem
);
3168 bnxt_disable_int(bp
);
3169 for (i
= 0; i
< bp
->cp_nr_rings
; i
++)
3170 synchronize_irq(bp
->irq_tbl
[i
].vector
);
3173 static void bnxt_enable_int(struct bnxt
*bp
)
3177 atomic_set(&bp
->intr_sem
, 0);
3178 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3179 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3180 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3182 BNXT_CP_DB_REARM(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
3186 void bnxt_hwrm_cmd_hdr_init(struct bnxt
*bp
, void *request
, u16 req_type
,
3187 u16 cmpl_ring
, u16 target_id
)
3189 struct input
*req
= request
;
3191 req
->req_type
= cpu_to_le16(req_type
);
3192 req
->cmpl_ring
= cpu_to_le16(cmpl_ring
);
3193 req
->target_id
= cpu_to_le16(target_id
);
3194 req
->resp_addr
= cpu_to_le64(bp
->hwrm_cmd_resp_dma_addr
);
3197 static int bnxt_hwrm_do_send_msg(struct bnxt
*bp
, void *msg
, u32 msg_len
,
3198 int timeout
, bool silent
)
3200 int i
, intr_process
, rc
, tmo_count
;
3201 struct input
*req
= msg
;
3203 __le32
*resp_len
, *valid
;
3204 u16 cp_ring_id
, len
= 0;
3205 struct hwrm_err_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3207 req
->seq_id
= cpu_to_le16(bp
->hwrm_cmd_seq
++);
3208 memset(resp
, 0, PAGE_SIZE
);
3209 cp_ring_id
= le16_to_cpu(req
->cmpl_ring
);
3210 intr_process
= (cp_ring_id
== INVALID_HW_RING_ID
) ? 0 : 1;
3212 /* Write request msg to hwrm channel */
3213 __iowrite32_copy(bp
->bar0
, data
, msg_len
/ 4);
3215 for (i
= msg_len
; i
< BNXT_HWRM_MAX_REQ_LEN
; i
+= 4)
3216 writel(0, bp
->bar0
+ i
);
3218 /* currently supports only one outstanding message */
3220 bp
->hwrm_intr_seq_id
= le16_to_cpu(req
->seq_id
);
3222 /* Ring channel doorbell */
3223 writel(1, bp
->bar0
+ 0x100);
3226 timeout
= DFLT_HWRM_CMD_TIMEOUT
;
3229 tmo_count
= timeout
* 40;
3231 /* Wait until hwrm response cmpl interrupt is processed */
3232 while (bp
->hwrm_intr_seq_id
!= HWRM_SEQ_ID_INVALID
&&
3234 usleep_range(25, 40);
3237 if (bp
->hwrm_intr_seq_id
!= HWRM_SEQ_ID_INVALID
) {
3238 netdev_err(bp
->dev
, "Resp cmpl intr err msg: 0x%x\n",
3239 le16_to_cpu(req
->req_type
));
3243 /* Check if response len is updated */
3244 resp_len
= bp
->hwrm_cmd_resp_addr
+ HWRM_RESP_LEN_OFFSET
;
3245 for (i
= 0; i
< tmo_count
; i
++) {
3246 len
= (le32_to_cpu(*resp_len
) & HWRM_RESP_LEN_MASK
) >>
3250 usleep_range(25, 40);
3253 if (i
>= tmo_count
) {
3254 netdev_err(bp
->dev
, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
3255 timeout
, le16_to_cpu(req
->req_type
),
3256 le16_to_cpu(req
->seq_id
), len
);
3260 /* Last word of resp contains valid bit */
3261 valid
= bp
->hwrm_cmd_resp_addr
+ len
- 4;
3262 for (i
= 0; i
< 5; i
++) {
3263 if (le32_to_cpu(*valid
) & HWRM_RESP_VALID_MASK
)
3269 netdev_err(bp
->dev
, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
3270 timeout
, le16_to_cpu(req
->req_type
),
3271 le16_to_cpu(req
->seq_id
), len
, *valid
);
3276 rc
= le16_to_cpu(resp
->error_code
);
3278 netdev_err(bp
->dev
, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
3279 le16_to_cpu(resp
->req_type
),
3280 le16_to_cpu(resp
->seq_id
), rc
);
3284 int _hwrm_send_message(struct bnxt
*bp
, void *msg
, u32 msg_len
, int timeout
)
3286 return bnxt_hwrm_do_send_msg(bp
, msg
, msg_len
, timeout
, false);
3289 int hwrm_send_message(struct bnxt
*bp
, void *msg
, u32 msg_len
, int timeout
)
3293 mutex_lock(&bp
->hwrm_cmd_lock
);
3294 rc
= _hwrm_send_message(bp
, msg
, msg_len
, timeout
);
3295 mutex_unlock(&bp
->hwrm_cmd_lock
);
3299 int hwrm_send_message_silent(struct bnxt
*bp
, void *msg
, u32 msg_len
,
3304 mutex_lock(&bp
->hwrm_cmd_lock
);
3305 rc
= bnxt_hwrm_do_send_msg(bp
, msg
, msg_len
, timeout
, true);
3306 mutex_unlock(&bp
->hwrm_cmd_lock
);
3310 int bnxt_hwrm_func_rgtr_async_events(struct bnxt
*bp
, unsigned long *bmap
,
3313 struct hwrm_func_drv_rgtr_input req
= {0};
3314 DECLARE_BITMAP(async_events_bmap
, 256);
3315 u32
*events
= (u32
*)async_events_bmap
;
3318 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_DRV_RGTR
, -1, -1);
3321 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD
);
3323 memset(async_events_bmap
, 0, sizeof(async_events_bmap
));
3324 for (i
= 0; i
< ARRAY_SIZE(bnxt_async_events_arr
); i
++)
3325 __set_bit(bnxt_async_events_arr
[i
], async_events_bmap
);
3327 if (bmap
&& bmap_size
) {
3328 for (i
= 0; i
< bmap_size
; i
++) {
3329 if (test_bit(i
, bmap
))
3330 __set_bit(i
, async_events_bmap
);
3334 for (i
= 0; i
< 8; i
++)
3335 req
.async_event_fwd
[i
] |= cpu_to_le32(events
[i
]);
3337 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3340 static int bnxt_hwrm_func_drv_rgtr(struct bnxt
*bp
)
3342 struct hwrm_func_drv_rgtr_input req
= {0};
3344 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_DRV_RGTR
, -1, -1);
3347 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE
|
3348 FUNC_DRV_RGTR_REQ_ENABLES_VER
);
3350 req
.os_type
= cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX
);
3351 req
.ver_maj
= DRV_VER_MAJ
;
3352 req
.ver_min
= DRV_VER_MIN
;
3353 req
.ver_upd
= DRV_VER_UPD
;
3356 DECLARE_BITMAP(vf_req_snif_bmap
, 256);
3357 u32
*data
= (u32
*)vf_req_snif_bmap
;
3360 memset(vf_req_snif_bmap
, 0, sizeof(vf_req_snif_bmap
));
3361 for (i
= 0; i
< ARRAY_SIZE(bnxt_vf_req_snif
); i
++)
3362 __set_bit(bnxt_vf_req_snif
[i
], vf_req_snif_bmap
);
3364 for (i
= 0; i
< 8; i
++)
3365 req
.vf_req_fwd
[i
] = cpu_to_le32(data
[i
]);
3368 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD
);
3371 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3374 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt
*bp
)
3376 struct hwrm_func_drv_unrgtr_input req
= {0};
3378 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_DRV_UNRGTR
, -1, -1);
3379 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3382 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt
*bp
, u8 tunnel_type
)
3385 struct hwrm_tunnel_dst_port_free_input req
= {0};
3387 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_TUNNEL_DST_PORT_FREE
, -1, -1);
3388 req
.tunnel_type
= tunnel_type
;
3390 switch (tunnel_type
) {
3391 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
:
3392 req
.tunnel_dst_port_id
= bp
->vxlan_fw_dst_port_id
;
3394 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
:
3395 req
.tunnel_dst_port_id
= bp
->nge_fw_dst_port_id
;
3401 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3403 netdev_err(bp
->dev
, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
3408 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt
*bp
, __be16 port
,
3412 struct hwrm_tunnel_dst_port_alloc_input req
= {0};
3413 struct hwrm_tunnel_dst_port_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3415 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_TUNNEL_DST_PORT_ALLOC
, -1, -1);
3417 req
.tunnel_type
= tunnel_type
;
3418 req
.tunnel_dst_port_val
= port
;
3420 mutex_lock(&bp
->hwrm_cmd_lock
);
3421 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3423 netdev_err(bp
->dev
, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
3428 switch (tunnel_type
) {
3429 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN
:
3430 bp
->vxlan_fw_dst_port_id
= resp
->tunnel_dst_port_id
;
3432 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE
:
3433 bp
->nge_fw_dst_port_id
= resp
->tunnel_dst_port_id
;
3440 mutex_unlock(&bp
->hwrm_cmd_lock
);
3444 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt
*bp
, u16 vnic_id
)
3446 struct hwrm_cfa_l2_set_rx_mask_input req
= {0};
3447 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
3449 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_L2_SET_RX_MASK
, -1, -1);
3450 req
.vnic_id
= cpu_to_le32(vnic
->fw_vnic_id
);
3452 req
.num_mc_entries
= cpu_to_le32(vnic
->mc_list_count
);
3453 req
.mc_tbl_addr
= cpu_to_le64(vnic
->mc_list_mapping
);
3454 req
.mask
= cpu_to_le32(vnic
->rx_mask
);
3455 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3458 #ifdef CONFIG_RFS_ACCEL
3459 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt
*bp
,
3460 struct bnxt_ntuple_filter
*fltr
)
3462 struct hwrm_cfa_ntuple_filter_free_input req
= {0};
3464 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_NTUPLE_FILTER_FREE
, -1, -1);
3465 req
.ntuple_filter_id
= fltr
->filter_id
;
3466 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3469 #define BNXT_NTP_FLTR_FLAGS \
3470 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
3471 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
3472 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
3473 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
3474 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
3475 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
3476 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
3477 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
3478 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
3479 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
3480 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
3481 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
3482 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
3483 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
3485 #define BNXT_NTP_TUNNEL_FLTR_FLAG \
3486 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE
3488 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt
*bp
,
3489 struct bnxt_ntuple_filter
*fltr
)
3492 struct hwrm_cfa_ntuple_filter_alloc_input req
= {0};
3493 struct hwrm_cfa_ntuple_filter_alloc_output
*resp
=
3494 bp
->hwrm_cmd_resp_addr
;
3495 struct flow_keys
*keys
= &fltr
->fkeys
;
3496 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[fltr
->rxq
+ 1];
3498 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_NTUPLE_FILTER_ALLOC
, -1, -1);
3499 req
.l2_filter_id
= bp
->vnic_info
[0].fw_l2_filter_id
[fltr
->l2_fltr_idx
];
3501 req
.enables
= cpu_to_le32(BNXT_NTP_FLTR_FLAGS
);
3503 req
.ethertype
= htons(ETH_P_IP
);
3504 memcpy(req
.src_macaddr
, fltr
->src_mac_addr
, ETH_ALEN
);
3505 req
.ip_addr_type
= CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4
;
3506 req
.ip_protocol
= keys
->basic
.ip_proto
;
3508 if (keys
->basic
.n_proto
== htons(ETH_P_IPV6
)) {
3511 req
.ethertype
= htons(ETH_P_IPV6
);
3513 CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6
;
3514 *(struct in6_addr
*)&req
.src_ipaddr
[0] =
3515 keys
->addrs
.v6addrs
.src
;
3516 *(struct in6_addr
*)&req
.dst_ipaddr
[0] =
3517 keys
->addrs
.v6addrs
.dst
;
3518 for (i
= 0; i
< 4; i
++) {
3519 req
.src_ipaddr_mask
[i
] = cpu_to_be32(0xffffffff);
3520 req
.dst_ipaddr_mask
[i
] = cpu_to_be32(0xffffffff);
3523 req
.src_ipaddr
[0] = keys
->addrs
.v4addrs
.src
;
3524 req
.src_ipaddr_mask
[0] = cpu_to_be32(0xffffffff);
3525 req
.dst_ipaddr
[0] = keys
->addrs
.v4addrs
.dst
;
3526 req
.dst_ipaddr_mask
[0] = cpu_to_be32(0xffffffff);
3528 if (keys
->control
.flags
& FLOW_DIS_ENCAPSULATION
) {
3529 req
.enables
|= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG
);
3531 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
;
3534 req
.src_port
= keys
->ports
.src
;
3535 req
.src_port_mask
= cpu_to_be16(0xffff);
3536 req
.dst_port
= keys
->ports
.dst
;
3537 req
.dst_port_mask
= cpu_to_be16(0xffff);
3539 req
.dst_id
= cpu_to_le16(vnic
->fw_vnic_id
);
3540 mutex_lock(&bp
->hwrm_cmd_lock
);
3541 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3543 fltr
->filter_id
= resp
->ntuple_filter_id
;
3544 mutex_unlock(&bp
->hwrm_cmd_lock
);
3549 static int bnxt_hwrm_set_vnic_filter(struct bnxt
*bp
, u16 vnic_id
, u16 idx
,
3553 struct hwrm_cfa_l2_filter_alloc_input req
= {0};
3554 struct hwrm_cfa_l2_filter_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3556 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_L2_FILTER_ALLOC
, -1, -1);
3557 req
.flags
= cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX
);
3558 if (!BNXT_CHIP_TYPE_NITRO_A0(bp
))
3560 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST
);
3561 req
.dst_id
= cpu_to_le16(bp
->vnic_info
[vnic_id
].fw_vnic_id
);
3563 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR
|
3564 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID
|
3565 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK
);
3566 memcpy(req
.l2_addr
, mac_addr
, ETH_ALEN
);
3567 req
.l2_addr_mask
[0] = 0xff;
3568 req
.l2_addr_mask
[1] = 0xff;
3569 req
.l2_addr_mask
[2] = 0xff;
3570 req
.l2_addr_mask
[3] = 0xff;
3571 req
.l2_addr_mask
[4] = 0xff;
3572 req
.l2_addr_mask
[5] = 0xff;
3574 mutex_lock(&bp
->hwrm_cmd_lock
);
3575 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3577 bp
->vnic_info
[vnic_id
].fw_l2_filter_id
[idx
] =
3579 mutex_unlock(&bp
->hwrm_cmd_lock
);
3583 static int bnxt_hwrm_clear_vnic_filter(struct bnxt
*bp
)
3585 u16 i
, j
, num_of_vnics
= 1; /* only vnic 0 supported */
3588 /* Any associated ntuple filters will also be cleared by firmware. */
3589 mutex_lock(&bp
->hwrm_cmd_lock
);
3590 for (i
= 0; i
< num_of_vnics
; i
++) {
3591 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[i
];
3593 for (j
= 0; j
< vnic
->uc_filter_count
; j
++) {
3594 struct hwrm_cfa_l2_filter_free_input req
= {0};
3596 bnxt_hwrm_cmd_hdr_init(bp
, &req
,
3597 HWRM_CFA_L2_FILTER_FREE
, -1, -1);
3599 req
.l2_filter_id
= vnic
->fw_l2_filter_id
[j
];
3601 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3604 vnic
->uc_filter_count
= 0;
3606 mutex_unlock(&bp
->hwrm_cmd_lock
);
3611 static int bnxt_hwrm_vnic_set_tpa(struct bnxt
*bp
, u16 vnic_id
, u32 tpa_flags
)
3613 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
3614 struct hwrm_vnic_tpa_cfg_input req
= {0};
3616 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_TPA_CFG
, -1, -1);
3619 u16 mss
= bp
->dev
->mtu
- 40;
3620 u32 nsegs
, n
, segs
= 0, flags
;
3622 flags
= VNIC_TPA_CFG_REQ_FLAGS_TPA
|
3623 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA
|
3624 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE
|
3625 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN
|
3626 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ
;
3627 if (tpa_flags
& BNXT_FLAG_GRO
)
3628 flags
|= VNIC_TPA_CFG_REQ_FLAGS_GRO
;
3630 req
.flags
= cpu_to_le32(flags
);
3633 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS
|
3634 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS
|
3635 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN
);
3637 /* Number of segs are log2 units, and first packet is not
3638 * included as part of this units.
3640 if (mss
<= BNXT_RX_PAGE_SIZE
) {
3641 n
= BNXT_RX_PAGE_SIZE
/ mss
;
3642 nsegs
= (MAX_SKB_FRAGS
- 1) * n
;
3644 n
= mss
/ BNXT_RX_PAGE_SIZE
;
3645 if (mss
& (BNXT_RX_PAGE_SIZE
- 1))
3647 nsegs
= (MAX_SKB_FRAGS
- n
) / n
;
3650 segs
= ilog2(nsegs
);
3651 req
.max_agg_segs
= cpu_to_le16(segs
);
3652 req
.max_aggs
= cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX
);
3654 req
.min_agg_len
= cpu_to_le32(512);
3656 req
.vnic_id
= cpu_to_le16(vnic
->fw_vnic_id
);
3658 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3661 static int bnxt_hwrm_vnic_set_rss(struct bnxt
*bp
, u16 vnic_id
, bool set_rss
)
3663 u32 i
, j
, max_rings
;
3664 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
3665 struct hwrm_vnic_rss_cfg_input req
= {0};
3667 if (vnic
->fw_rss_cos_lb_ctx
[0] == INVALID_HW_RING_ID
)
3670 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_RSS_CFG
, -1, -1);
3672 req
.hash_type
= cpu_to_le32(bp
->rss_hash_cfg
);
3673 if (vnic
->flags
& BNXT_VNIC_RSS_FLAG
) {
3674 if (BNXT_CHIP_TYPE_NITRO_A0(bp
))
3675 max_rings
= bp
->rx_nr_rings
- 1;
3677 max_rings
= bp
->rx_nr_rings
;
3682 /* Fill the RSS indirection table with ring group ids */
3683 for (i
= 0, j
= 0; i
< HW_HASH_INDEX_SIZE
; i
++, j
++) {
3686 vnic
->rss_table
[i
] = cpu_to_le16(vnic
->fw_grp_ids
[j
]);
3689 req
.ring_grp_tbl_addr
= cpu_to_le64(vnic
->rss_table_dma_addr
);
3690 req
.hash_key_tbl_addr
=
3691 cpu_to_le64(vnic
->rss_hash_key_dma_addr
);
3693 req
.rss_ctx_idx
= cpu_to_le16(vnic
->fw_rss_cos_lb_ctx
[0]);
3694 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3697 static int bnxt_hwrm_vnic_set_hds(struct bnxt
*bp
, u16 vnic_id
)
3699 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
3700 struct hwrm_vnic_plcmodes_cfg_input req
= {0};
3702 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_PLCMODES_CFG
, -1, -1);
3703 req
.flags
= cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT
|
3704 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4
|
3705 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6
);
3707 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID
|
3708 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID
);
3709 /* thresholds not implemented in firmware yet */
3710 req
.jumbo_thresh
= cpu_to_le16(bp
->rx_copy_thresh
);
3711 req
.hds_threshold
= cpu_to_le16(bp
->rx_copy_thresh
);
3712 req
.vnic_id
= cpu_to_le32(vnic
->fw_vnic_id
);
3713 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3716 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt
*bp
, u16 vnic_id
,
3719 struct hwrm_vnic_rss_cos_lb_ctx_free_input req
= {0};
3721 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_RSS_COS_LB_CTX_FREE
, -1, -1);
3722 req
.rss_cos_lb_ctx_id
=
3723 cpu_to_le16(bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
[ctx_idx
]);
3725 hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3726 bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
[ctx_idx
] = INVALID_HW_RING_ID
;
3729 static void bnxt_hwrm_vnic_ctx_free(struct bnxt
*bp
)
3733 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
3734 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[i
];
3736 for (j
= 0; j
< BNXT_MAX_CTX_PER_VNIC
; j
++) {
3737 if (vnic
->fw_rss_cos_lb_ctx
[j
] != INVALID_HW_RING_ID
)
3738 bnxt_hwrm_vnic_ctx_free_one(bp
, i
, j
);
3741 bp
->rsscos_nr_ctxs
= 0;
3744 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt
*bp
, u16 vnic_id
, u16 ctx_idx
)
3747 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req
= {0};
3748 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output
*resp
=
3749 bp
->hwrm_cmd_resp_addr
;
3751 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC
, -1,
3754 mutex_lock(&bp
->hwrm_cmd_lock
);
3755 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3757 bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
[ctx_idx
] =
3758 le16_to_cpu(resp
->rss_cos_lb_ctx_id
);
3759 mutex_unlock(&bp
->hwrm_cmd_lock
);
3764 int bnxt_hwrm_vnic_cfg(struct bnxt
*bp
, u16 vnic_id
)
3766 unsigned int ring
= 0, grp_idx
;
3767 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
3768 struct hwrm_vnic_cfg_input req
= {0};
3771 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_CFG
, -1, -1);
3773 req
.enables
= cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP
);
3774 /* Only RSS support for now TBD: COS & LB */
3775 if (vnic
->fw_rss_cos_lb_ctx
[0] != INVALID_HW_RING_ID
) {
3776 req
.rss_rule
= cpu_to_le16(vnic
->fw_rss_cos_lb_ctx
[0]);
3777 req
.enables
|= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE
|
3778 VNIC_CFG_REQ_ENABLES_MRU
);
3779 } else if (vnic
->flags
& BNXT_VNIC_RFS_NEW_RSS_FLAG
) {
3781 cpu_to_le16(bp
->vnic_info
[0].fw_rss_cos_lb_ctx
[0]);
3782 req
.enables
|= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE
|
3783 VNIC_CFG_REQ_ENABLES_MRU
);
3784 req
.flags
|= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE
);
3786 req
.rss_rule
= cpu_to_le16(0xffff);
3789 if (BNXT_CHIP_TYPE_NITRO_A0(bp
) &&
3790 (vnic
->fw_rss_cos_lb_ctx
[0] != INVALID_HW_RING_ID
)) {
3791 req
.cos_rule
= cpu_to_le16(vnic
->fw_rss_cos_lb_ctx
[1]);
3792 req
.enables
|= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE
);
3794 req
.cos_rule
= cpu_to_le16(0xffff);
3797 if (vnic
->flags
& BNXT_VNIC_RSS_FLAG
)
3799 else if (vnic
->flags
& BNXT_VNIC_RFS_FLAG
)
3801 else if ((vnic_id
== 1) && BNXT_CHIP_TYPE_NITRO_A0(bp
))
3802 ring
= bp
->rx_nr_rings
- 1;
3804 grp_idx
= bp
->rx_ring
[ring
].bnapi
->index
;
3805 req
.vnic_id
= cpu_to_le16(vnic
->fw_vnic_id
);
3806 req
.dflt_ring_grp
= cpu_to_le16(bp
->grp_info
[grp_idx
].fw_grp_id
);
3808 req
.lb_rule
= cpu_to_le16(0xffff);
3809 req
.mru
= cpu_to_le16(bp
->dev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+
3812 #ifdef CONFIG_BNXT_SRIOV
3814 def_vlan
= bp
->vf
.vlan
;
3816 if ((bp
->flags
& BNXT_FLAG_STRIP_VLAN
) || def_vlan
)
3817 req
.flags
|= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE
);
3818 if (!vnic_id
&& bnxt_ulp_registered(bp
->edev
, BNXT_ROCE_ULP
))
3820 cpu_to_le32(VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE
);
3822 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3825 static int bnxt_hwrm_vnic_free_one(struct bnxt
*bp
, u16 vnic_id
)
3829 if (bp
->vnic_info
[vnic_id
].fw_vnic_id
!= INVALID_HW_RING_ID
) {
3830 struct hwrm_vnic_free_input req
= {0};
3832 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_FREE
, -1, -1);
3834 cpu_to_le32(bp
->vnic_info
[vnic_id
].fw_vnic_id
);
3836 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3839 bp
->vnic_info
[vnic_id
].fw_vnic_id
= INVALID_HW_RING_ID
;
3844 static void bnxt_hwrm_vnic_free(struct bnxt
*bp
)
3848 for (i
= 0; i
< bp
->nr_vnics
; i
++)
3849 bnxt_hwrm_vnic_free_one(bp
, i
);
3852 static int bnxt_hwrm_vnic_alloc(struct bnxt
*bp
, u16 vnic_id
,
3853 unsigned int start_rx_ring_idx
,
3854 unsigned int nr_rings
)
3857 unsigned int i
, j
, grp_idx
, end_idx
= start_rx_ring_idx
+ nr_rings
;
3858 struct hwrm_vnic_alloc_input req
= {0};
3859 struct hwrm_vnic_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3861 /* map ring groups to this vnic */
3862 for (i
= start_rx_ring_idx
, j
= 0; i
< end_idx
; i
++, j
++) {
3863 grp_idx
= bp
->rx_ring
[i
].bnapi
->index
;
3864 if (bp
->grp_info
[grp_idx
].fw_grp_id
== INVALID_HW_RING_ID
) {
3865 netdev_err(bp
->dev
, "Not enough ring groups avail:%x req:%x\n",
3869 bp
->vnic_info
[vnic_id
].fw_grp_ids
[j
] =
3870 bp
->grp_info
[grp_idx
].fw_grp_id
;
3873 bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
[0] = INVALID_HW_RING_ID
;
3874 bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
[1] = INVALID_HW_RING_ID
;
3876 req
.flags
= cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT
);
3878 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_ALLOC
, -1, -1);
3880 mutex_lock(&bp
->hwrm_cmd_lock
);
3881 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3883 bp
->vnic_info
[vnic_id
].fw_vnic_id
= le32_to_cpu(resp
->vnic_id
);
3884 mutex_unlock(&bp
->hwrm_cmd_lock
);
3888 static int bnxt_hwrm_vnic_qcaps(struct bnxt
*bp
)
3890 struct hwrm_vnic_qcaps_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3891 struct hwrm_vnic_qcaps_input req
= {0};
3894 if (bp
->hwrm_spec_code
< 0x10600)
3897 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_QCAPS
, -1, -1);
3898 mutex_lock(&bp
->hwrm_cmd_lock
);
3899 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3902 cpu_to_le32(VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP
))
3903 bp
->flags
|= BNXT_FLAG_NEW_RSS_CAP
;
3905 mutex_unlock(&bp
->hwrm_cmd_lock
);
3909 static int bnxt_hwrm_ring_grp_alloc(struct bnxt
*bp
)
3914 mutex_lock(&bp
->hwrm_cmd_lock
);
3915 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3916 struct hwrm_ring_grp_alloc_input req
= {0};
3917 struct hwrm_ring_grp_alloc_output
*resp
=
3918 bp
->hwrm_cmd_resp_addr
;
3919 unsigned int grp_idx
= bp
->rx_ring
[i
].bnapi
->index
;
3921 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_GRP_ALLOC
, -1, -1);
3923 req
.cr
= cpu_to_le16(bp
->grp_info
[grp_idx
].cp_fw_ring_id
);
3924 req
.rr
= cpu_to_le16(bp
->grp_info
[grp_idx
].rx_fw_ring_id
);
3925 req
.ar
= cpu_to_le16(bp
->grp_info
[grp_idx
].agg_fw_ring_id
);
3926 req
.sc
= cpu_to_le16(bp
->grp_info
[grp_idx
].fw_stats_ctx
);
3928 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3933 bp
->grp_info
[grp_idx
].fw_grp_id
=
3934 le32_to_cpu(resp
->ring_group_id
);
3936 mutex_unlock(&bp
->hwrm_cmd_lock
);
3940 static int bnxt_hwrm_ring_grp_free(struct bnxt
*bp
)
3944 struct hwrm_ring_grp_free_input req
= {0};
3949 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_GRP_FREE
, -1, -1);
3951 mutex_lock(&bp
->hwrm_cmd_lock
);
3952 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3953 if (bp
->grp_info
[i
].fw_grp_id
== INVALID_HW_RING_ID
)
3956 cpu_to_le32(bp
->grp_info
[i
].fw_grp_id
);
3958 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3962 bp
->grp_info
[i
].fw_grp_id
= INVALID_HW_RING_ID
;
3964 mutex_unlock(&bp
->hwrm_cmd_lock
);
3968 static int hwrm_ring_alloc_send_msg(struct bnxt
*bp
,
3969 struct bnxt_ring_struct
*ring
,
3970 u32 ring_type
, u32 map_index
,
3973 int rc
= 0, err
= 0;
3974 struct hwrm_ring_alloc_input req
= {0};
3975 struct hwrm_ring_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3978 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_ALLOC
, -1, -1);
3981 if (ring
->nr_pages
> 1) {
3982 req
.page_tbl_addr
= cpu_to_le64(ring
->pg_tbl_map
);
3983 /* Page size is in log2 units */
3984 req
.page_size
= BNXT_PAGE_SHIFT
;
3985 req
.page_tbl_depth
= 1;
3987 req
.page_tbl_addr
= cpu_to_le64(ring
->dma_arr
[0]);
3990 /* Association of ring index with doorbell index and MSIX number */
3991 req
.logical_id
= cpu_to_le16(map_index
);
3993 switch (ring_type
) {
3994 case HWRM_RING_ALLOC_TX
:
3995 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_TX
;
3996 /* Association of transmit ring with completion ring */
3998 cpu_to_le16(bp
->grp_info
[map_index
].cp_fw_ring_id
);
3999 req
.length
= cpu_to_le32(bp
->tx_ring_mask
+ 1);
4000 req
.stat_ctx_id
= cpu_to_le32(stats_ctx_id
);
4001 req
.queue_id
= cpu_to_le16(ring
->queue_id
);
4003 case HWRM_RING_ALLOC_RX
:
4004 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_RX
;
4005 req
.length
= cpu_to_le32(bp
->rx_ring_mask
+ 1);
4007 case HWRM_RING_ALLOC_AGG
:
4008 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_RX
;
4009 req
.length
= cpu_to_le32(bp
->rx_agg_ring_mask
+ 1);
4011 case HWRM_RING_ALLOC_CMPL
:
4012 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_L2_CMPL
;
4013 req
.length
= cpu_to_le32(bp
->cp_ring_mask
+ 1);
4014 if (bp
->flags
& BNXT_FLAG_USING_MSIX
)
4015 req
.int_mode
= RING_ALLOC_REQ_INT_MODE_MSIX
;
4018 netdev_err(bp
->dev
, "hwrm alloc invalid ring type %d\n",
4023 mutex_lock(&bp
->hwrm_cmd_lock
);
4024 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4025 err
= le16_to_cpu(resp
->error_code
);
4026 ring_id
= le16_to_cpu(resp
->ring_id
);
4027 mutex_unlock(&bp
->hwrm_cmd_lock
);
4030 switch (ring_type
) {
4031 case RING_FREE_REQ_RING_TYPE_L2_CMPL
:
4032 netdev_err(bp
->dev
, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
4036 case RING_FREE_REQ_RING_TYPE_RX
:
4037 netdev_err(bp
->dev
, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
4041 case RING_FREE_REQ_RING_TYPE_TX
:
4042 netdev_err(bp
->dev
, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
4047 netdev_err(bp
->dev
, "Invalid ring\n");
4051 ring
->fw_ring_id
= ring_id
;
4055 static int bnxt_hwrm_set_async_event_cr(struct bnxt
*bp
, int idx
)
4060 struct hwrm_func_cfg_input req
= {0};
4062 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_CFG
, -1, -1);
4063 req
.fid
= cpu_to_le16(0xffff);
4064 req
.enables
= cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR
);
4065 req
.async_event_cr
= cpu_to_le16(idx
);
4066 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4068 struct hwrm_func_vf_cfg_input req
= {0};
4070 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_VF_CFG
, -1, -1);
4072 cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR
);
4073 req
.async_event_cr
= cpu_to_le16(idx
);
4074 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4079 static int bnxt_hwrm_ring_alloc(struct bnxt
*bp
)
4083 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4084 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4085 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
4086 struct bnxt_ring_struct
*ring
= &cpr
->cp_ring_struct
;
4088 cpr
->cp_doorbell
= bp
->bar1
+ i
* 0x80;
4089 rc
= hwrm_ring_alloc_send_msg(bp
, ring
, HWRM_RING_ALLOC_CMPL
, i
,
4090 INVALID_STATS_CTX_ID
);
4093 BNXT_CP_DB(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
4094 bp
->grp_info
[i
].cp_fw_ring_id
= ring
->fw_ring_id
;
4097 rc
= bnxt_hwrm_set_async_event_cr(bp
, ring
->fw_ring_id
);
4099 netdev_warn(bp
->dev
, "Failed to set async event completion ring.\n");
4103 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
4104 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
4105 struct bnxt_ring_struct
*ring
= &txr
->tx_ring_struct
;
4106 u32 map_idx
= txr
->bnapi
->index
;
4107 u16 fw_stats_ctx
= bp
->grp_info
[map_idx
].fw_stats_ctx
;
4109 rc
= hwrm_ring_alloc_send_msg(bp
, ring
, HWRM_RING_ALLOC_TX
,
4110 map_idx
, fw_stats_ctx
);
4113 txr
->tx_doorbell
= bp
->bar1
+ map_idx
* 0x80;
4116 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
4117 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
4118 struct bnxt_ring_struct
*ring
= &rxr
->rx_ring_struct
;
4119 u32 map_idx
= rxr
->bnapi
->index
;
4121 rc
= hwrm_ring_alloc_send_msg(bp
, ring
, HWRM_RING_ALLOC_RX
,
4122 map_idx
, INVALID_STATS_CTX_ID
);
4125 rxr
->rx_doorbell
= bp
->bar1
+ map_idx
* 0x80;
4126 writel(DB_KEY_RX
| rxr
->rx_prod
, rxr
->rx_doorbell
);
4127 bp
->grp_info
[map_idx
].rx_fw_ring_id
= ring
->fw_ring_id
;
4130 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
) {
4131 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
4132 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
4133 struct bnxt_ring_struct
*ring
=
4134 &rxr
->rx_agg_ring_struct
;
4135 u32 grp_idx
= rxr
->bnapi
->index
;
4136 u32 map_idx
= grp_idx
+ bp
->rx_nr_rings
;
4138 rc
= hwrm_ring_alloc_send_msg(bp
, ring
,
4139 HWRM_RING_ALLOC_AGG
,
4141 INVALID_STATS_CTX_ID
);
4145 rxr
->rx_agg_doorbell
= bp
->bar1
+ map_idx
* 0x80;
4146 writel(DB_KEY_RX
| rxr
->rx_agg_prod
,
4147 rxr
->rx_agg_doorbell
);
4148 bp
->grp_info
[grp_idx
].agg_fw_ring_id
= ring
->fw_ring_id
;
4155 static int hwrm_ring_free_send_msg(struct bnxt
*bp
,
4156 struct bnxt_ring_struct
*ring
,
4157 u32 ring_type
, int cmpl_ring_id
)
4160 struct hwrm_ring_free_input req
= {0};
4161 struct hwrm_ring_free_output
*resp
= bp
->hwrm_cmd_resp_addr
;
4164 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_FREE
, cmpl_ring_id
, -1);
4165 req
.ring_type
= ring_type
;
4166 req
.ring_id
= cpu_to_le16(ring
->fw_ring_id
);
4168 mutex_lock(&bp
->hwrm_cmd_lock
);
4169 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4170 error_code
= le16_to_cpu(resp
->error_code
);
4171 mutex_unlock(&bp
->hwrm_cmd_lock
);
4173 if (rc
|| error_code
) {
4174 switch (ring_type
) {
4175 case RING_FREE_REQ_RING_TYPE_L2_CMPL
:
4176 netdev_err(bp
->dev
, "hwrm_ring_free cp failed. rc:%d\n",
4179 case RING_FREE_REQ_RING_TYPE_RX
:
4180 netdev_err(bp
->dev
, "hwrm_ring_free rx failed. rc:%d\n",
4183 case RING_FREE_REQ_RING_TYPE_TX
:
4184 netdev_err(bp
->dev
, "hwrm_ring_free tx failed. rc:%d\n",
4188 netdev_err(bp
->dev
, "Invalid ring\n");
4195 static void bnxt_hwrm_ring_free(struct bnxt
*bp
, bool close_path
)
4202 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
4203 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
4204 struct bnxt_ring_struct
*ring
= &txr
->tx_ring_struct
;
4205 u32 grp_idx
= txr
->bnapi
->index
;
4206 u32 cmpl_ring_id
= bp
->grp_info
[grp_idx
].cp_fw_ring_id
;
4208 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
4209 hwrm_ring_free_send_msg(bp
, ring
,
4210 RING_FREE_REQ_RING_TYPE_TX
,
4211 close_path
? cmpl_ring_id
:
4212 INVALID_HW_RING_ID
);
4213 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
4217 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
4218 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
4219 struct bnxt_ring_struct
*ring
= &rxr
->rx_ring_struct
;
4220 u32 grp_idx
= rxr
->bnapi
->index
;
4221 u32 cmpl_ring_id
= bp
->grp_info
[grp_idx
].cp_fw_ring_id
;
4223 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
4224 hwrm_ring_free_send_msg(bp
, ring
,
4225 RING_FREE_REQ_RING_TYPE_RX
,
4226 close_path
? cmpl_ring_id
:
4227 INVALID_HW_RING_ID
);
4228 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
4229 bp
->grp_info
[grp_idx
].rx_fw_ring_id
=
4234 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
4235 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
4236 struct bnxt_ring_struct
*ring
= &rxr
->rx_agg_ring_struct
;
4237 u32 grp_idx
= rxr
->bnapi
->index
;
4238 u32 cmpl_ring_id
= bp
->grp_info
[grp_idx
].cp_fw_ring_id
;
4240 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
4241 hwrm_ring_free_send_msg(bp
, ring
,
4242 RING_FREE_REQ_RING_TYPE_RX
,
4243 close_path
? cmpl_ring_id
:
4244 INVALID_HW_RING_ID
);
4245 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
4246 bp
->grp_info
[grp_idx
].agg_fw_ring_id
=
4251 /* The completion rings are about to be freed. After that the
4252 * IRQ doorbell will not work anymore. So we need to disable
4255 bnxt_disable_int_sync(bp
);
4257 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4258 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4259 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
4260 struct bnxt_ring_struct
*ring
= &cpr
->cp_ring_struct
;
4262 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
4263 hwrm_ring_free_send_msg(bp
, ring
,
4264 RING_FREE_REQ_RING_TYPE_L2_CMPL
,
4265 INVALID_HW_RING_ID
);
4266 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
4267 bp
->grp_info
[i
].cp_fw_ring_id
= INVALID_HW_RING_ID
;
4272 /* Caller must hold bp->hwrm_cmd_lock */
4273 int __bnxt_hwrm_get_tx_rings(struct bnxt
*bp
, u16 fid
, int *tx_rings
)
4275 struct hwrm_func_qcfg_output
*resp
= bp
->hwrm_cmd_resp_addr
;
4276 struct hwrm_func_qcfg_input req
= {0};
4279 if (bp
->hwrm_spec_code
< 0x10601)
4282 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_QCFG
, -1, -1);
4283 req
.fid
= cpu_to_le16(fid
);
4284 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4286 *tx_rings
= le16_to_cpu(resp
->alloc_tx_rings
);
4291 static int bnxt_hwrm_reserve_tx_rings(struct bnxt
*bp
, int *tx_rings
)
4293 struct hwrm_func_cfg_input req
= {0};
4296 if (bp
->hwrm_spec_code
< 0x10601)
4302 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_CFG
, -1, -1);
4303 req
.fid
= cpu_to_le16(0xffff);
4304 req
.enables
= cpu_to_le32(FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS
);
4305 req
.num_tx_rings
= cpu_to_le16(*tx_rings
);
4306 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4310 mutex_lock(&bp
->hwrm_cmd_lock
);
4311 rc
= __bnxt_hwrm_get_tx_rings(bp
, 0xffff, tx_rings
);
4312 mutex_unlock(&bp
->hwrm_cmd_lock
);
4316 static void bnxt_hwrm_set_coal_params(struct bnxt
*bp
, u32 max_bufs
,
4317 u32 buf_tmrs
, u16 flags
,
4318 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input
*req
)
4320 req
->flags
= cpu_to_le16(flags
);
4321 req
->num_cmpl_dma_aggr
= cpu_to_le16((u16
)max_bufs
);
4322 req
->num_cmpl_dma_aggr_during_int
= cpu_to_le16(max_bufs
>> 16);
4323 req
->cmpl_aggr_dma_tmr
= cpu_to_le16((u16
)buf_tmrs
);
4324 req
->cmpl_aggr_dma_tmr_during_int
= cpu_to_le16(buf_tmrs
>> 16);
4325 /* Minimum time between 2 interrupts set to buf_tmr x 2 */
4326 req
->int_lat_tmr_min
= cpu_to_le16((u16
)buf_tmrs
* 2);
4327 req
->int_lat_tmr_max
= cpu_to_le16((u16
)buf_tmrs
* 4);
4328 req
->num_cmpl_aggr_int
= cpu_to_le16((u16
)max_bufs
* 4);
4331 int bnxt_hwrm_set_coal(struct bnxt
*bp
)
4334 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx
= {0},
4336 u16 max_buf
, max_buf_irq
;
4337 u16 buf_tmr
, buf_tmr_irq
;
4340 bnxt_hwrm_cmd_hdr_init(bp
, &req_rx
,
4341 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS
, -1, -1);
4342 bnxt_hwrm_cmd_hdr_init(bp
, &req_tx
,
4343 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS
, -1, -1);
4345 /* Each rx completion (2 records) should be DMAed immediately.
4346 * DMA 1/4 of the completion buffers at a time.
4348 max_buf
= min_t(u16
, bp
->rx_coal_bufs
/ 4, 2);
4349 /* max_buf must not be zero */
4350 max_buf
= clamp_t(u16
, max_buf
, 1, 63);
4351 max_buf_irq
= clamp_t(u16
, bp
->rx_coal_bufs_irq
, 1, 63);
4352 buf_tmr
= BNXT_USEC_TO_COAL_TIMER(bp
->rx_coal_ticks
);
4353 /* buf timer set to 1/4 of interrupt timer */
4354 buf_tmr
= max_t(u16
, buf_tmr
/ 4, 1);
4355 buf_tmr_irq
= BNXT_USEC_TO_COAL_TIMER(bp
->rx_coal_ticks_irq
);
4356 buf_tmr_irq
= max_t(u16
, buf_tmr_irq
, 1);
4358 flags
= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET
;
4360 /* RING_IDLE generates more IRQs for lower latency. Enable it only
4361 * if coal_ticks is less than 25 us.
4363 if (bp
->rx_coal_ticks
< 25)
4364 flags
|= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE
;
4366 bnxt_hwrm_set_coal_params(bp
, max_buf_irq
<< 16 | max_buf
,
4367 buf_tmr_irq
<< 16 | buf_tmr
, flags
, &req_rx
);
4369 /* max_buf must not be zero */
4370 max_buf
= clamp_t(u16
, bp
->tx_coal_bufs
, 1, 63);
4371 max_buf_irq
= clamp_t(u16
, bp
->tx_coal_bufs_irq
, 1, 63);
4372 buf_tmr
= BNXT_USEC_TO_COAL_TIMER(bp
->tx_coal_ticks
);
4373 /* buf timer set to 1/4 of interrupt timer */
4374 buf_tmr
= max_t(u16
, buf_tmr
/ 4, 1);
4375 buf_tmr_irq
= BNXT_USEC_TO_COAL_TIMER(bp
->tx_coal_ticks_irq
);
4376 buf_tmr_irq
= max_t(u16
, buf_tmr_irq
, 1);
4378 flags
= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET
;
4379 bnxt_hwrm_set_coal_params(bp
, max_buf_irq
<< 16 | max_buf
,
4380 buf_tmr_irq
<< 16 | buf_tmr
, flags
, &req_tx
);
4382 mutex_lock(&bp
->hwrm_cmd_lock
);
4383 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4384 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4387 if (!bnapi
->rx_ring
)
4389 req
->ring_id
= cpu_to_le16(bp
->grp_info
[i
].cp_fw_ring_id
);
4391 rc
= _hwrm_send_message(bp
, req
, sizeof(*req
),
4396 mutex_unlock(&bp
->hwrm_cmd_lock
);
4400 static int bnxt_hwrm_stat_ctx_free(struct bnxt
*bp
)
4403 struct hwrm_stat_ctx_free_input req
= {0};
4408 if (BNXT_CHIP_TYPE_NITRO_A0(bp
))
4411 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_STAT_CTX_FREE
, -1, -1);
4413 mutex_lock(&bp
->hwrm_cmd_lock
);
4414 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4415 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4416 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
4418 if (cpr
->hw_stats_ctx_id
!= INVALID_STATS_CTX_ID
) {
4419 req
.stat_ctx_id
= cpu_to_le32(cpr
->hw_stats_ctx_id
);
4421 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
4426 cpr
->hw_stats_ctx_id
= INVALID_STATS_CTX_ID
;
4429 mutex_unlock(&bp
->hwrm_cmd_lock
);
4433 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt
*bp
)
4436 struct hwrm_stat_ctx_alloc_input req
= {0};
4437 struct hwrm_stat_ctx_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
4439 if (BNXT_CHIP_TYPE_NITRO_A0(bp
))
4442 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_STAT_CTX_ALLOC
, -1, -1);
4444 req
.update_period_ms
= cpu_to_le32(bp
->stats_coal_ticks
/ 1000);
4446 mutex_lock(&bp
->hwrm_cmd_lock
);
4447 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4448 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4449 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
4451 req
.stats_dma_addr
= cpu_to_le64(cpr
->hw_stats_map
);
4453 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
4458 cpr
->hw_stats_ctx_id
= le32_to_cpu(resp
->stat_ctx_id
);
4460 bp
->grp_info
[i
].fw_stats_ctx
= cpr
->hw_stats_ctx_id
;
4462 mutex_unlock(&bp
->hwrm_cmd_lock
);
4466 static int bnxt_hwrm_func_qcfg(struct bnxt
*bp
)
4468 struct hwrm_func_qcfg_input req
= {0};
4469 struct hwrm_func_qcfg_output
*resp
= bp
->hwrm_cmd_resp_addr
;
4472 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_QCFG
, -1, -1);
4473 req
.fid
= cpu_to_le16(0xffff);
4474 mutex_lock(&bp
->hwrm_cmd_lock
);
4475 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4477 goto func_qcfg_exit
;
4479 #ifdef CONFIG_BNXT_SRIOV
4481 struct bnxt_vf_info
*vf
= &bp
->vf
;
4483 vf
->vlan
= le16_to_cpu(resp
->vlan
) & VLAN_VID_MASK
;
4487 u16 flags
= le16_to_cpu(resp
->flags
);
4489 if (flags
& (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED
|
4490 FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED
))
4491 bp
->flags
|= BNXT_FLAG_FW_LLDP_AGENT
;
4492 if (flags
& FUNC_QCFG_RESP_FLAGS_MULTI_HOST
)
4493 bp
->flags
|= BNXT_FLAG_MULTI_HOST
;
4496 switch (resp
->port_partition_type
) {
4497 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0
:
4498 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5
:
4499 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0
:
4500 bp
->port_partition_type
= resp
->port_partition_type
;
4505 mutex_unlock(&bp
->hwrm_cmd_lock
);
4509 static int bnxt_hwrm_func_qcaps(struct bnxt
*bp
)
4512 struct hwrm_func_qcaps_input req
= {0};
4513 struct hwrm_func_qcaps_output
*resp
= bp
->hwrm_cmd_resp_addr
;
4515 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_QCAPS
, -1, -1);
4516 req
.fid
= cpu_to_le16(0xffff);
4518 mutex_lock(&bp
->hwrm_cmd_lock
);
4519 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4521 goto hwrm_func_qcaps_exit
;
4523 if (resp
->flags
& cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED
))
4524 bp
->flags
|= BNXT_FLAG_ROCEV1_CAP
;
4525 if (resp
->flags
& cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED
))
4526 bp
->flags
|= BNXT_FLAG_ROCEV2_CAP
;
4528 bp
->tx_push_thresh
= 0;
4530 cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED
))
4531 bp
->tx_push_thresh
= BNXT_TX_PUSH_THRESH
;
4534 struct bnxt_pf_info
*pf
= &bp
->pf
;
4536 pf
->fw_fid
= le16_to_cpu(resp
->fid
);
4537 pf
->port_id
= le16_to_cpu(resp
->port_id
);
4538 bp
->dev
->dev_port
= pf
->port_id
;
4539 memcpy(pf
->mac_addr
, resp
->mac_address
, ETH_ALEN
);
4540 memcpy(bp
->dev
->dev_addr
, pf
->mac_addr
, ETH_ALEN
);
4541 pf
->max_rsscos_ctxs
= le16_to_cpu(resp
->max_rsscos_ctx
);
4542 pf
->max_cp_rings
= le16_to_cpu(resp
->max_cmpl_rings
);
4543 pf
->max_tx_rings
= le16_to_cpu(resp
->max_tx_rings
);
4544 pf
->max_rx_rings
= le16_to_cpu(resp
->max_rx_rings
);
4545 pf
->max_hw_ring_grps
= le32_to_cpu(resp
->max_hw_ring_grps
);
4546 if (!pf
->max_hw_ring_grps
)
4547 pf
->max_hw_ring_grps
= pf
->max_tx_rings
;
4548 pf
->max_l2_ctxs
= le16_to_cpu(resp
->max_l2_ctxs
);
4549 pf
->max_vnics
= le16_to_cpu(resp
->max_vnics
);
4550 pf
->max_stat_ctxs
= le16_to_cpu(resp
->max_stat_ctx
);
4551 pf
->first_vf_id
= le16_to_cpu(resp
->first_vf_id
);
4552 pf
->max_vfs
= le16_to_cpu(resp
->max_vfs
);
4553 pf
->max_encap_records
= le32_to_cpu(resp
->max_encap_records
);
4554 pf
->max_decap_records
= le32_to_cpu(resp
->max_decap_records
);
4555 pf
->max_tx_em_flows
= le32_to_cpu(resp
->max_tx_em_flows
);
4556 pf
->max_tx_wm_flows
= le32_to_cpu(resp
->max_tx_wm_flows
);
4557 pf
->max_rx_em_flows
= le32_to_cpu(resp
->max_rx_em_flows
);
4558 pf
->max_rx_wm_flows
= le32_to_cpu(resp
->max_rx_wm_flows
);
4560 cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED
))
4561 bp
->flags
|= BNXT_FLAG_WOL_CAP
;
4563 #ifdef CONFIG_BNXT_SRIOV
4564 struct bnxt_vf_info
*vf
= &bp
->vf
;
4566 vf
->fw_fid
= le16_to_cpu(resp
->fid
);
4568 vf
->max_rsscos_ctxs
= le16_to_cpu(resp
->max_rsscos_ctx
);
4569 vf
->max_cp_rings
= le16_to_cpu(resp
->max_cmpl_rings
);
4570 vf
->max_tx_rings
= le16_to_cpu(resp
->max_tx_rings
);
4571 vf
->max_rx_rings
= le16_to_cpu(resp
->max_rx_rings
);
4572 vf
->max_hw_ring_grps
= le32_to_cpu(resp
->max_hw_ring_grps
);
4573 if (!vf
->max_hw_ring_grps
)
4574 vf
->max_hw_ring_grps
= vf
->max_tx_rings
;
4575 vf
->max_l2_ctxs
= le16_to_cpu(resp
->max_l2_ctxs
);
4576 vf
->max_vnics
= le16_to_cpu(resp
->max_vnics
);
4577 vf
->max_stat_ctxs
= le16_to_cpu(resp
->max_stat_ctx
);
4579 memcpy(vf
->mac_addr
, resp
->mac_address
, ETH_ALEN
);
4580 mutex_unlock(&bp
->hwrm_cmd_lock
);
4582 if (is_valid_ether_addr(vf
->mac_addr
)) {
4583 /* overwrite netdev dev_adr with admin VF MAC */
4584 memcpy(bp
->dev
->dev_addr
, vf
->mac_addr
, ETH_ALEN
);
4586 eth_hw_addr_random(bp
->dev
);
4587 rc
= bnxt_approve_mac(bp
, bp
->dev
->dev_addr
);
4593 hwrm_func_qcaps_exit
:
4594 mutex_unlock(&bp
->hwrm_cmd_lock
);
4598 static int bnxt_hwrm_func_reset(struct bnxt
*bp
)
4600 struct hwrm_func_reset_input req
= {0};
4602 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_RESET
, -1, -1);
4605 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_RESET_TIMEOUT
);
4608 static int bnxt_hwrm_queue_qportcfg(struct bnxt
*bp
)
4611 struct hwrm_queue_qportcfg_input req
= {0};
4612 struct hwrm_queue_qportcfg_output
*resp
= bp
->hwrm_cmd_resp_addr
;
4615 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_QUEUE_QPORTCFG
, -1, -1);
4617 mutex_lock(&bp
->hwrm_cmd_lock
);
4618 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4622 if (!resp
->max_configurable_queues
) {
4626 bp
->max_tc
= resp
->max_configurable_queues
;
4627 bp
->max_lltc
= resp
->max_configurable_lossless_queues
;
4628 if (bp
->max_tc
> BNXT_MAX_QUEUE
)
4629 bp
->max_tc
= BNXT_MAX_QUEUE
;
4631 if (resp
->queue_cfg_info
& QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG
)
4634 if (bp
->max_lltc
> bp
->max_tc
)
4635 bp
->max_lltc
= bp
->max_tc
;
4637 qptr
= &resp
->queue_id0
;
4638 for (i
= 0; i
< bp
->max_tc
; i
++) {
4639 bp
->q_info
[i
].queue_id
= *qptr
++;
4640 bp
->q_info
[i
].queue_profile
= *qptr
++;
4644 mutex_unlock(&bp
->hwrm_cmd_lock
);
4648 static int bnxt_hwrm_ver_get(struct bnxt
*bp
)
4651 struct hwrm_ver_get_input req
= {0};
4652 struct hwrm_ver_get_output
*resp
= bp
->hwrm_cmd_resp_addr
;
4654 bp
->hwrm_max_req_len
= HWRM_MAX_REQ_LEN
;
4655 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VER_GET
, -1, -1);
4656 req
.hwrm_intf_maj
= HWRM_VERSION_MAJOR
;
4657 req
.hwrm_intf_min
= HWRM_VERSION_MINOR
;
4658 req
.hwrm_intf_upd
= HWRM_VERSION_UPDATE
;
4659 mutex_lock(&bp
->hwrm_cmd_lock
);
4660 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4662 goto hwrm_ver_get_exit
;
4664 memcpy(&bp
->ver_resp
, resp
, sizeof(struct hwrm_ver_get_output
));
4666 bp
->hwrm_spec_code
= resp
->hwrm_intf_maj
<< 16 |
4667 resp
->hwrm_intf_min
<< 8 | resp
->hwrm_intf_upd
;
4668 if (resp
->hwrm_intf_maj
< 1) {
4669 netdev_warn(bp
->dev
, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
4670 resp
->hwrm_intf_maj
, resp
->hwrm_intf_min
,
4671 resp
->hwrm_intf_upd
);
4672 netdev_warn(bp
->dev
, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
4674 snprintf(bp
->fw_ver_str
, BC_HWRM_STR_LEN
, "%d.%d.%d/%d.%d.%d",
4675 resp
->hwrm_fw_maj
, resp
->hwrm_fw_min
, resp
->hwrm_fw_bld
,
4676 resp
->hwrm_intf_maj
, resp
->hwrm_intf_min
, resp
->hwrm_intf_upd
);
4678 bp
->hwrm_cmd_timeout
= le16_to_cpu(resp
->def_req_timeout
);
4679 if (!bp
->hwrm_cmd_timeout
)
4680 bp
->hwrm_cmd_timeout
= DFLT_HWRM_CMD_TIMEOUT
;
4682 if (resp
->hwrm_intf_maj
>= 1)
4683 bp
->hwrm_max_req_len
= le16_to_cpu(resp
->max_req_win_len
);
4685 bp
->chip_num
= le16_to_cpu(resp
->chip_num
);
4686 if (bp
->chip_num
== CHIP_NUM_58700
&& !resp
->chip_rev
&&
4688 bp
->flags
|= BNXT_FLAG_CHIP_NITRO_A0
;
4691 mutex_unlock(&bp
->hwrm_cmd_lock
);
4695 int bnxt_hwrm_fw_set_time(struct bnxt
*bp
)
4697 #if IS_ENABLED(CONFIG_RTC_LIB)
4698 struct hwrm_fw_set_time_input req
= {0};
4702 if (bp
->hwrm_spec_code
< 0x10400)
4705 do_gettimeofday(&tv
);
4706 rtc_time_to_tm(tv
.tv_sec
, &tm
);
4707 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FW_SET_TIME
, -1, -1);
4708 req
.year
= cpu_to_le16(1900 + tm
.tm_year
);
4709 req
.month
= 1 + tm
.tm_mon
;
4710 req
.day
= tm
.tm_mday
;
4711 req
.hour
= tm
.tm_hour
;
4712 req
.minute
= tm
.tm_min
;
4713 req
.second
= tm
.tm_sec
;
4714 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4720 static int bnxt_hwrm_port_qstats(struct bnxt
*bp
)
4723 struct bnxt_pf_info
*pf
= &bp
->pf
;
4724 struct hwrm_port_qstats_input req
= {0};
4726 if (!(bp
->flags
& BNXT_FLAG_PORT_STATS
))
4729 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_QSTATS
, -1, -1);
4730 req
.port_id
= cpu_to_le16(pf
->port_id
);
4731 req
.tx_stat_host_addr
= cpu_to_le64(bp
->hw_tx_port_stats_map
);
4732 req
.rx_stat_host_addr
= cpu_to_le64(bp
->hw_rx_port_stats_map
);
4733 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4737 static void bnxt_hwrm_free_tunnel_ports(struct bnxt
*bp
)
4739 if (bp
->vxlan_port_cnt
) {
4740 bnxt_hwrm_tunnel_dst_port_free(
4741 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
);
4743 bp
->vxlan_port_cnt
= 0;
4744 if (bp
->nge_port_cnt
) {
4745 bnxt_hwrm_tunnel_dst_port_free(
4746 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
);
4748 bp
->nge_port_cnt
= 0;
4751 static int bnxt_set_tpa(struct bnxt
*bp
, bool set_tpa
)
4757 tpa_flags
= bp
->flags
& BNXT_FLAG_TPA
;
4758 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
4759 rc
= bnxt_hwrm_vnic_set_tpa(bp
, i
, tpa_flags
);
4761 netdev_err(bp
->dev
, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
4769 static void bnxt_hwrm_clear_vnic_rss(struct bnxt
*bp
)
4773 for (i
= 0; i
< bp
->nr_vnics
; i
++)
4774 bnxt_hwrm_vnic_set_rss(bp
, i
, false);
4777 static void bnxt_hwrm_resource_free(struct bnxt
*bp
, bool close_path
,
4780 if (bp
->vnic_info
) {
4781 bnxt_hwrm_clear_vnic_filter(bp
);
4782 /* clear all RSS setting before free vnic ctx */
4783 bnxt_hwrm_clear_vnic_rss(bp
);
4784 bnxt_hwrm_vnic_ctx_free(bp
);
4785 /* before free the vnic, undo the vnic tpa settings */
4786 if (bp
->flags
& BNXT_FLAG_TPA
)
4787 bnxt_set_tpa(bp
, false);
4788 bnxt_hwrm_vnic_free(bp
);
4790 bnxt_hwrm_ring_free(bp
, close_path
);
4791 bnxt_hwrm_ring_grp_free(bp
);
4793 bnxt_hwrm_stat_ctx_free(bp
);
4794 bnxt_hwrm_free_tunnel_ports(bp
);
4798 static int bnxt_setup_vnic(struct bnxt
*bp
, u16 vnic_id
)
4800 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
4803 if (vnic
->flags
& BNXT_VNIC_RFS_NEW_RSS_FLAG
)
4806 /* allocate context for vnic */
4807 rc
= bnxt_hwrm_vnic_ctx_alloc(bp
, vnic_id
, 0);
4809 netdev_err(bp
->dev
, "hwrm vnic %d alloc failure rc: %x\n",
4811 goto vnic_setup_err
;
4813 bp
->rsscos_nr_ctxs
++;
4815 if (BNXT_CHIP_TYPE_NITRO_A0(bp
)) {
4816 rc
= bnxt_hwrm_vnic_ctx_alloc(bp
, vnic_id
, 1);
4818 netdev_err(bp
->dev
, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
4820 goto vnic_setup_err
;
4822 bp
->rsscos_nr_ctxs
++;
4826 /* configure default vnic, ring grp */
4827 rc
= bnxt_hwrm_vnic_cfg(bp
, vnic_id
);
4829 netdev_err(bp
->dev
, "hwrm vnic %d cfg failure rc: %x\n",
4831 goto vnic_setup_err
;
4834 /* Enable RSS hashing on vnic */
4835 rc
= bnxt_hwrm_vnic_set_rss(bp
, vnic_id
, true);
4837 netdev_err(bp
->dev
, "hwrm vnic %d set rss failure rc: %x\n",
4839 goto vnic_setup_err
;
4842 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
) {
4843 rc
= bnxt_hwrm_vnic_set_hds(bp
, vnic_id
);
4845 netdev_err(bp
->dev
, "hwrm vnic %d set hds failure rc: %x\n",
4854 static int bnxt_alloc_rfs_vnics(struct bnxt
*bp
)
4856 #ifdef CONFIG_RFS_ACCEL
4859 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
4860 struct bnxt_vnic_info
*vnic
;
4861 u16 vnic_id
= i
+ 1;
4864 if (vnic_id
>= bp
->nr_vnics
)
4867 vnic
= &bp
->vnic_info
[vnic_id
];
4868 vnic
->flags
|= BNXT_VNIC_RFS_FLAG
;
4869 if (bp
->flags
& BNXT_FLAG_NEW_RSS_CAP
)
4870 vnic
->flags
|= BNXT_VNIC_RFS_NEW_RSS_FLAG
;
4871 rc
= bnxt_hwrm_vnic_alloc(bp
, vnic_id
, ring_id
, 1);
4873 netdev_err(bp
->dev
, "hwrm vnic %d alloc failure rc: %x\n",
4877 rc
= bnxt_setup_vnic(bp
, vnic_id
);
4887 /* Allow PF and VF with default VLAN to be in promiscuous mode */
4888 static bool bnxt_promisc_ok(struct bnxt
*bp
)
4890 #ifdef CONFIG_BNXT_SRIOV
4891 if (BNXT_VF(bp
) && !bp
->vf
.vlan
)
4897 static int bnxt_setup_nitroa0_vnic(struct bnxt
*bp
)
4899 unsigned int rc
= 0;
4901 rc
= bnxt_hwrm_vnic_alloc(bp
, 1, bp
->rx_nr_rings
- 1, 1);
4903 netdev_err(bp
->dev
, "Cannot allocate special vnic for NS2 A0: %x\n",
4908 rc
= bnxt_hwrm_vnic_cfg(bp
, 1);
4910 netdev_err(bp
->dev
, "Cannot allocate special vnic for NS2 A0: %x\n",
4917 static int bnxt_cfg_rx_mode(struct bnxt
*);
4918 static bool bnxt_mc_list_updated(struct bnxt
*, u32
*);
4920 static int bnxt_init_chip(struct bnxt
*bp
, bool irq_re_init
)
4922 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
4924 unsigned int rx_nr_rings
= bp
->rx_nr_rings
;
4927 rc
= bnxt_hwrm_stat_ctx_alloc(bp
);
4929 netdev_err(bp
->dev
, "hwrm stat ctx alloc failure rc: %x\n",
4935 rc
= bnxt_hwrm_ring_alloc(bp
);
4937 netdev_err(bp
->dev
, "hwrm ring alloc failure rc: %x\n", rc
);
4941 rc
= bnxt_hwrm_ring_grp_alloc(bp
);
4943 netdev_err(bp
->dev
, "hwrm_ring_grp alloc failure: %x\n", rc
);
4947 if (BNXT_CHIP_TYPE_NITRO_A0(bp
))
4950 /* default vnic 0 */
4951 rc
= bnxt_hwrm_vnic_alloc(bp
, 0, 0, rx_nr_rings
);
4953 netdev_err(bp
->dev
, "hwrm vnic alloc failure rc: %x\n", rc
);
4957 rc
= bnxt_setup_vnic(bp
, 0);
4961 if (bp
->flags
& BNXT_FLAG_RFS
) {
4962 rc
= bnxt_alloc_rfs_vnics(bp
);
4967 if (bp
->flags
& BNXT_FLAG_TPA
) {
4968 rc
= bnxt_set_tpa(bp
, true);
4974 bnxt_update_vf_mac(bp
);
4976 /* Filter for default vnic 0 */
4977 rc
= bnxt_hwrm_set_vnic_filter(bp
, 0, 0, bp
->dev
->dev_addr
);
4979 netdev_err(bp
->dev
, "HWRM vnic filter failure rc: %x\n", rc
);
4982 vnic
->uc_filter_count
= 1;
4984 vnic
->rx_mask
= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST
;
4986 if ((bp
->dev
->flags
& IFF_PROMISC
) && bnxt_promisc_ok(bp
))
4987 vnic
->rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
;
4989 if (bp
->dev
->flags
& IFF_ALLMULTI
) {
4990 vnic
->rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
;
4991 vnic
->mc_list_count
= 0;
4995 bnxt_mc_list_updated(bp
, &mask
);
4996 vnic
->rx_mask
|= mask
;
4999 rc
= bnxt_cfg_rx_mode(bp
);
5003 rc
= bnxt_hwrm_set_coal(bp
);
5005 netdev_warn(bp
->dev
, "HWRM set coalescing failure rc: %x\n",
5008 if (BNXT_CHIP_TYPE_NITRO_A0(bp
)) {
5009 rc
= bnxt_setup_nitroa0_vnic(bp
);
5011 netdev_err(bp
->dev
, "Special vnic setup failure for NS2 A0 rc: %x\n",
5016 bnxt_hwrm_func_qcfg(bp
);
5017 netdev_update_features(bp
->dev
);
5023 bnxt_hwrm_resource_free(bp
, 0, true);
5028 static int bnxt_shutdown_nic(struct bnxt
*bp
, bool irq_re_init
)
5030 bnxt_hwrm_resource_free(bp
, 1, irq_re_init
);
5034 static int bnxt_init_nic(struct bnxt
*bp
, bool irq_re_init
)
5036 bnxt_init_cp_rings(bp
);
5037 bnxt_init_rx_rings(bp
);
5038 bnxt_init_tx_rings(bp
);
5039 bnxt_init_ring_grps(bp
, irq_re_init
);
5040 bnxt_init_vnics(bp
);
5042 return bnxt_init_chip(bp
, irq_re_init
);
5045 static int bnxt_set_real_num_queues(struct bnxt
*bp
)
5048 struct net_device
*dev
= bp
->dev
;
5050 rc
= netif_set_real_num_tx_queues(dev
, bp
->tx_nr_rings
-
5051 bp
->tx_nr_rings_xdp
);
5055 rc
= netif_set_real_num_rx_queues(dev
, bp
->rx_nr_rings
);
5059 #ifdef CONFIG_RFS_ACCEL
5060 if (bp
->flags
& BNXT_FLAG_RFS
)
5061 dev
->rx_cpu_rmap
= alloc_irq_cpu_rmap(bp
->rx_nr_rings
);
5067 static int bnxt_trim_rings(struct bnxt
*bp
, int *rx
, int *tx
, int max
,
5070 int _rx
= *rx
, _tx
= *tx
;
5073 *rx
= min_t(int, _rx
, max
);
5074 *tx
= min_t(int, _tx
, max
);
5079 while (_rx
+ _tx
> max
) {
5080 if (_rx
> _tx
&& _rx
> 1)
5091 static void bnxt_setup_msix(struct bnxt
*bp
)
5093 const int len
= sizeof(bp
->irq_tbl
[0].name
);
5094 struct net_device
*dev
= bp
->dev
;
5097 tcs
= netdev_get_num_tc(dev
);
5101 for (i
= 0; i
< tcs
; i
++) {
5102 count
= bp
->tx_nr_rings_per_tc
;
5104 netdev_set_tc_queue(dev
, i
, count
, off
);
5108 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
5111 if (bp
->flags
& BNXT_FLAG_SHARED_RINGS
)
5113 else if (i
< bp
->rx_nr_rings
)
5118 snprintf(bp
->irq_tbl
[i
].name
, len
, "%s-%s-%d", dev
->name
, attr
,
5120 bp
->irq_tbl
[i
].handler
= bnxt_msix
;
5124 static void bnxt_setup_inta(struct bnxt
*bp
)
5126 const int len
= sizeof(bp
->irq_tbl
[0].name
);
5128 if (netdev_get_num_tc(bp
->dev
))
5129 netdev_reset_tc(bp
->dev
);
5131 snprintf(bp
->irq_tbl
[0].name
, len
, "%s-%s-%d", bp
->dev
->name
, "TxRx",
5133 bp
->irq_tbl
[0].handler
= bnxt_inta
;
5136 static int bnxt_setup_int_mode(struct bnxt
*bp
)
5140 if (bp
->flags
& BNXT_FLAG_USING_MSIX
)
5141 bnxt_setup_msix(bp
);
5143 bnxt_setup_inta(bp
);
5145 rc
= bnxt_set_real_num_queues(bp
);
5149 #ifdef CONFIG_RFS_ACCEL
5150 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt
*bp
)
5152 #if defined(CONFIG_BNXT_SRIOV)
5154 return bp
->vf
.max_rsscos_ctxs
;
5156 return bp
->pf
.max_rsscos_ctxs
;
5159 static unsigned int bnxt_get_max_func_vnics(struct bnxt
*bp
)
5161 #if defined(CONFIG_BNXT_SRIOV)
5163 return bp
->vf
.max_vnics
;
5165 return bp
->pf
.max_vnics
;
5169 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt
*bp
)
5171 #if defined(CONFIG_BNXT_SRIOV)
5173 return bp
->vf
.max_stat_ctxs
;
5175 return bp
->pf
.max_stat_ctxs
;
5178 void bnxt_set_max_func_stat_ctxs(struct bnxt
*bp
, unsigned int max
)
5180 #if defined(CONFIG_BNXT_SRIOV)
5182 bp
->vf
.max_stat_ctxs
= max
;
5185 bp
->pf
.max_stat_ctxs
= max
;
5188 unsigned int bnxt_get_max_func_cp_rings(struct bnxt
*bp
)
5190 #if defined(CONFIG_BNXT_SRIOV)
5192 return bp
->vf
.max_cp_rings
;
5194 return bp
->pf
.max_cp_rings
;
5197 void bnxt_set_max_func_cp_rings(struct bnxt
*bp
, unsigned int max
)
5199 #if defined(CONFIG_BNXT_SRIOV)
5201 bp
->vf
.max_cp_rings
= max
;
5204 bp
->pf
.max_cp_rings
= max
;
5207 static unsigned int bnxt_get_max_func_irqs(struct bnxt
*bp
)
5209 #if defined(CONFIG_BNXT_SRIOV)
5211 return min_t(unsigned int, bp
->vf
.max_irqs
,
5212 bp
->vf
.max_cp_rings
);
5214 return min_t(unsigned int, bp
->pf
.max_irqs
, bp
->pf
.max_cp_rings
);
5217 void bnxt_set_max_func_irqs(struct bnxt
*bp
, unsigned int max_irqs
)
5219 #if defined(CONFIG_BNXT_SRIOV)
5221 bp
->vf
.max_irqs
= max_irqs
;
5224 bp
->pf
.max_irqs
= max_irqs
;
5227 static int bnxt_init_msix(struct bnxt
*bp
)
5229 int i
, total_vecs
, rc
= 0, min
= 1;
5230 struct msix_entry
*msix_ent
;
5232 total_vecs
= bnxt_get_max_func_irqs(bp
);
5233 msix_ent
= kcalloc(total_vecs
, sizeof(struct msix_entry
), GFP_KERNEL
);
5237 for (i
= 0; i
< total_vecs
; i
++) {
5238 msix_ent
[i
].entry
= i
;
5239 msix_ent
[i
].vector
= 0;
5242 if (!(bp
->flags
& BNXT_FLAG_SHARED_RINGS
))
5245 total_vecs
= pci_enable_msix_range(bp
->pdev
, msix_ent
, min
, total_vecs
);
5246 if (total_vecs
< 0) {
5248 goto msix_setup_exit
;
5251 bp
->irq_tbl
= kcalloc(total_vecs
, sizeof(struct bnxt_irq
), GFP_KERNEL
);
5253 for (i
= 0; i
< total_vecs
; i
++)
5254 bp
->irq_tbl
[i
].vector
= msix_ent
[i
].vector
;
5256 bp
->total_irqs
= total_vecs
;
5257 /* Trim rings based upon num of vectors allocated */
5258 rc
= bnxt_trim_rings(bp
, &bp
->rx_nr_rings
, &bp
->tx_nr_rings
,
5259 total_vecs
, min
== 1);
5261 goto msix_setup_exit
;
5263 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
;
5264 bp
->cp_nr_rings
= (min
== 1) ?
5265 max_t(int, bp
->tx_nr_rings
, bp
->rx_nr_rings
) :
5266 bp
->tx_nr_rings
+ bp
->rx_nr_rings
;
5270 goto msix_setup_exit
;
5272 bp
->flags
|= BNXT_FLAG_USING_MSIX
;
5277 netdev_err(bp
->dev
, "bnxt_init_msix err: %x\n", rc
);
5280 pci_disable_msix(bp
->pdev
);
5285 static int bnxt_init_inta(struct bnxt
*bp
)
5287 bp
->irq_tbl
= kcalloc(1, sizeof(struct bnxt_irq
), GFP_KERNEL
);
5292 bp
->rx_nr_rings
= 1;
5293 bp
->tx_nr_rings
= 1;
5294 bp
->cp_nr_rings
= 1;
5295 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
;
5296 bp
->flags
|= BNXT_FLAG_SHARED_RINGS
;
5297 bp
->irq_tbl
[0].vector
= bp
->pdev
->irq
;
5301 static int bnxt_init_int_mode(struct bnxt
*bp
)
5305 if (bp
->flags
& BNXT_FLAG_MSIX_CAP
)
5306 rc
= bnxt_init_msix(bp
);
5308 if (!(bp
->flags
& BNXT_FLAG_USING_MSIX
) && BNXT_PF(bp
)) {
5309 /* fallback to INTA */
5310 rc
= bnxt_init_inta(bp
);
5315 static void bnxt_clear_int_mode(struct bnxt
*bp
)
5317 if (bp
->flags
& BNXT_FLAG_USING_MSIX
)
5318 pci_disable_msix(bp
->pdev
);
5322 bp
->flags
&= ~BNXT_FLAG_USING_MSIX
;
5325 static void bnxt_free_irq(struct bnxt
*bp
)
5327 struct bnxt_irq
*irq
;
5330 #ifdef CONFIG_RFS_ACCEL
5331 free_irq_cpu_rmap(bp
->dev
->rx_cpu_rmap
);
5332 bp
->dev
->rx_cpu_rmap
= NULL
;
5337 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
5338 irq
= &bp
->irq_tbl
[i
];
5340 free_irq(irq
->vector
, bp
->bnapi
[i
]);
5345 static int bnxt_request_irq(struct bnxt
*bp
)
5348 unsigned long flags
= 0;
5349 #ifdef CONFIG_RFS_ACCEL
5350 struct cpu_rmap
*rmap
= bp
->dev
->rx_cpu_rmap
;
5353 if (!(bp
->flags
& BNXT_FLAG_USING_MSIX
))
5354 flags
= IRQF_SHARED
;
5356 for (i
= 0, j
= 0; i
< bp
->cp_nr_rings
; i
++) {
5357 struct bnxt_irq
*irq
= &bp
->irq_tbl
[i
];
5358 #ifdef CONFIG_RFS_ACCEL
5359 if (rmap
&& bp
->bnapi
[i
]->rx_ring
) {
5360 rc
= irq_cpu_rmap_add(rmap
, irq
->vector
);
5362 netdev_warn(bp
->dev
, "failed adding irq rmap for ring %d\n",
5367 rc
= request_irq(irq
->vector
, irq
->handler
, flags
, irq
->name
,
5377 static void bnxt_del_napi(struct bnxt
*bp
)
5384 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
5385 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
5387 napi_hash_del(&bnapi
->napi
);
5388 netif_napi_del(&bnapi
->napi
);
5390 /* We called napi_hash_del() before netif_napi_del(), we need
5391 * to respect an RCU grace period before freeing napi structures.
5396 static void bnxt_init_napi(struct bnxt
*bp
)
5399 unsigned int cp_nr_rings
= bp
->cp_nr_rings
;
5400 struct bnxt_napi
*bnapi
;
5402 if (bp
->flags
& BNXT_FLAG_USING_MSIX
) {
5403 if (BNXT_CHIP_TYPE_NITRO_A0(bp
))
5405 for (i
= 0; i
< cp_nr_rings
; i
++) {
5406 bnapi
= bp
->bnapi
[i
];
5407 netif_napi_add(bp
->dev
, &bnapi
->napi
,
5410 if (BNXT_CHIP_TYPE_NITRO_A0(bp
)) {
5411 bnapi
= bp
->bnapi
[cp_nr_rings
];
5412 netif_napi_add(bp
->dev
, &bnapi
->napi
,
5413 bnxt_poll_nitroa0
, 64);
5416 bnapi
= bp
->bnapi
[0];
5417 netif_napi_add(bp
->dev
, &bnapi
->napi
, bnxt_poll
, 64);
5421 static void bnxt_disable_napi(struct bnxt
*bp
)
5428 for (i
= 0; i
< bp
->cp_nr_rings
; i
++)
5429 napi_disable(&bp
->bnapi
[i
]->napi
);
5432 static void bnxt_enable_napi(struct bnxt
*bp
)
5436 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
5437 bp
->bnapi
[i
]->in_reset
= false;
5438 napi_enable(&bp
->bnapi
[i
]->napi
);
5442 void bnxt_tx_disable(struct bnxt
*bp
)
5445 struct bnxt_tx_ring_info
*txr
;
5446 struct netdev_queue
*txq
;
5449 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
5450 txr
= &bp
->tx_ring
[i
];
5451 txq
= netdev_get_tx_queue(bp
->dev
, i
);
5452 txr
->dev_state
= BNXT_DEV_STATE_CLOSING
;
5455 /* Stop all TX queues */
5456 netif_tx_disable(bp
->dev
);
5457 netif_carrier_off(bp
->dev
);
5460 void bnxt_tx_enable(struct bnxt
*bp
)
5463 struct bnxt_tx_ring_info
*txr
;
5464 struct netdev_queue
*txq
;
5466 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
5467 txr
= &bp
->tx_ring
[i
];
5468 txq
= netdev_get_tx_queue(bp
->dev
, i
);
5471 netif_tx_wake_all_queues(bp
->dev
);
5472 if (bp
->link_info
.link_up
)
5473 netif_carrier_on(bp
->dev
);
5476 static void bnxt_report_link(struct bnxt
*bp
)
5478 if (bp
->link_info
.link_up
) {
5480 const char *flow_ctrl
;
5484 netif_carrier_on(bp
->dev
);
5485 if (bp
->link_info
.duplex
== BNXT_LINK_DUPLEX_FULL
)
5489 if (bp
->link_info
.pause
== BNXT_LINK_PAUSE_BOTH
)
5490 flow_ctrl
= "ON - receive & transmit";
5491 else if (bp
->link_info
.pause
== BNXT_LINK_PAUSE_TX
)
5492 flow_ctrl
= "ON - transmit";
5493 else if (bp
->link_info
.pause
== BNXT_LINK_PAUSE_RX
)
5494 flow_ctrl
= "ON - receive";
5497 speed
= bnxt_fw_to_ethtool_speed(bp
->link_info
.link_speed
);
5498 netdev_info(bp
->dev
, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n",
5499 speed
, duplex
, flow_ctrl
);
5500 if (bp
->flags
& BNXT_FLAG_EEE_CAP
)
5501 netdev_info(bp
->dev
, "EEE is %s\n",
5502 bp
->eee
.eee_active
? "active" :
5504 fec
= bp
->link_info
.fec_cfg
;
5505 if (!(fec
& PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED
))
5506 netdev_info(bp
->dev
, "FEC autoneg %s encodings: %s\n",
5507 (fec
& BNXT_FEC_AUTONEG
) ? "on" : "off",
5508 (fec
& BNXT_FEC_ENC_BASE_R
) ? "BaseR" :
5509 (fec
& BNXT_FEC_ENC_RS
) ? "RS" : "None");
5511 netif_carrier_off(bp
->dev
);
5512 netdev_err(bp
->dev
, "NIC Link is Down\n");
5516 static int bnxt_hwrm_phy_qcaps(struct bnxt
*bp
)
5519 struct hwrm_port_phy_qcaps_input req
= {0};
5520 struct hwrm_port_phy_qcaps_output
*resp
= bp
->hwrm_cmd_resp_addr
;
5521 struct bnxt_link_info
*link_info
= &bp
->link_info
;
5523 if (bp
->hwrm_spec_code
< 0x10201)
5526 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_QCAPS
, -1, -1);
5528 mutex_lock(&bp
->hwrm_cmd_lock
);
5529 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
5531 goto hwrm_phy_qcaps_exit
;
5533 if (resp
->eee_supported
& PORT_PHY_QCAPS_RESP_EEE_SUPPORTED
) {
5534 struct ethtool_eee
*eee
= &bp
->eee
;
5535 u16 fw_speeds
= le16_to_cpu(resp
->supported_speeds_eee_mode
);
5537 bp
->flags
|= BNXT_FLAG_EEE_CAP
;
5538 eee
->supported
= _bnxt_fw_to_ethtool_adv_spds(fw_speeds
, 0);
5539 bp
->lpi_tmr_lo
= le32_to_cpu(resp
->tx_lpi_timer_low
) &
5540 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK
;
5541 bp
->lpi_tmr_hi
= le32_to_cpu(resp
->valid_tx_lpi_timer_high
) &
5542 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK
;
5544 if (resp
->supported_speeds_auto_mode
)
5545 link_info
->support_auto_speeds
=
5546 le16_to_cpu(resp
->supported_speeds_auto_mode
);
5548 hwrm_phy_qcaps_exit
:
5549 mutex_unlock(&bp
->hwrm_cmd_lock
);
5553 static int bnxt_update_link(struct bnxt
*bp
, bool chng_link_state
)
5556 struct bnxt_link_info
*link_info
= &bp
->link_info
;
5557 struct hwrm_port_phy_qcfg_input req
= {0};
5558 struct hwrm_port_phy_qcfg_output
*resp
= bp
->hwrm_cmd_resp_addr
;
5559 u8 link_up
= link_info
->link_up
;
5562 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_QCFG
, -1, -1);
5564 mutex_lock(&bp
->hwrm_cmd_lock
);
5565 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
5567 mutex_unlock(&bp
->hwrm_cmd_lock
);
5571 memcpy(&link_info
->phy_qcfg_resp
, resp
, sizeof(*resp
));
5572 link_info
->phy_link_status
= resp
->link
;
5573 link_info
->duplex
= resp
->duplex
;
5574 link_info
->pause
= resp
->pause
;
5575 link_info
->auto_mode
= resp
->auto_mode
;
5576 link_info
->auto_pause_setting
= resp
->auto_pause
;
5577 link_info
->lp_pause
= resp
->link_partner_adv_pause
;
5578 link_info
->force_pause_setting
= resp
->force_pause
;
5579 link_info
->duplex_setting
= resp
->duplex
;
5580 if (link_info
->phy_link_status
== BNXT_LINK_LINK
)
5581 link_info
->link_speed
= le16_to_cpu(resp
->link_speed
);
5583 link_info
->link_speed
= 0;
5584 link_info
->force_link_speed
= le16_to_cpu(resp
->force_link_speed
);
5585 link_info
->support_speeds
= le16_to_cpu(resp
->support_speeds
);
5586 link_info
->auto_link_speeds
= le16_to_cpu(resp
->auto_link_speed_mask
);
5587 link_info
->lp_auto_link_speeds
=
5588 le16_to_cpu(resp
->link_partner_adv_speeds
);
5589 link_info
->preemphasis
= le32_to_cpu(resp
->preemphasis
);
5590 link_info
->phy_ver
[0] = resp
->phy_maj
;
5591 link_info
->phy_ver
[1] = resp
->phy_min
;
5592 link_info
->phy_ver
[2] = resp
->phy_bld
;
5593 link_info
->media_type
= resp
->media_type
;
5594 link_info
->phy_type
= resp
->phy_type
;
5595 link_info
->transceiver
= resp
->xcvr_pkg_type
;
5596 link_info
->phy_addr
= resp
->eee_config_phy_addr
&
5597 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK
;
5598 link_info
->module_status
= resp
->module_status
;
5600 if (bp
->flags
& BNXT_FLAG_EEE_CAP
) {
5601 struct ethtool_eee
*eee
= &bp
->eee
;
5604 eee
->eee_active
= 0;
5605 if (resp
->eee_config_phy_addr
&
5606 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE
) {
5607 eee
->eee_active
= 1;
5608 fw_speeds
= le16_to_cpu(
5609 resp
->link_partner_adv_eee_link_speed_mask
);
5610 eee
->lp_advertised
=
5611 _bnxt_fw_to_ethtool_adv_spds(fw_speeds
, 0);
5614 /* Pull initial EEE config */
5615 if (!chng_link_state
) {
5616 if (resp
->eee_config_phy_addr
&
5617 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED
)
5618 eee
->eee_enabled
= 1;
5620 fw_speeds
= le16_to_cpu(resp
->adv_eee_link_speed_mask
);
5622 _bnxt_fw_to_ethtool_adv_spds(fw_speeds
, 0);
5624 if (resp
->eee_config_phy_addr
&
5625 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI
) {
5628 eee
->tx_lpi_enabled
= 1;
5629 tmr
= resp
->xcvr_identifier_type_tx_lpi_timer
;
5630 eee
->tx_lpi_timer
= le32_to_cpu(tmr
) &
5631 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK
;
5636 link_info
->fec_cfg
= PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED
;
5637 if (bp
->hwrm_spec_code
>= 0x10504)
5638 link_info
->fec_cfg
= le16_to_cpu(resp
->fec_cfg
);
5640 /* TODO: need to add more logic to report VF link */
5641 if (chng_link_state
) {
5642 if (link_info
->phy_link_status
== BNXT_LINK_LINK
)
5643 link_info
->link_up
= 1;
5645 link_info
->link_up
= 0;
5646 if (link_up
!= link_info
->link_up
)
5647 bnxt_report_link(bp
);
5649 /* alwasy link down if not require to update link state */
5650 link_info
->link_up
= 0;
5652 mutex_unlock(&bp
->hwrm_cmd_lock
);
5654 diff
= link_info
->support_auto_speeds
^ link_info
->advertising
;
5655 if ((link_info
->support_auto_speeds
| diff
) !=
5656 link_info
->support_auto_speeds
) {
5657 /* An advertised speed is no longer supported, so we need to
5658 * update the advertisement settings. Caller holds RTNL
5659 * so we can modify link settings.
5661 link_info
->advertising
= link_info
->support_auto_speeds
;
5662 if (link_info
->autoneg
& BNXT_AUTONEG_SPEED
)
5663 bnxt_hwrm_set_link_setting(bp
, true, false);
5668 static void bnxt_get_port_module_status(struct bnxt
*bp
)
5670 struct bnxt_link_info
*link_info
= &bp
->link_info
;
5671 struct hwrm_port_phy_qcfg_output
*resp
= &link_info
->phy_qcfg_resp
;
5674 if (bnxt_update_link(bp
, true))
5677 module_status
= link_info
->module_status
;
5678 switch (module_status
) {
5679 case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX
:
5680 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN
:
5681 case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG
:
5682 netdev_warn(bp
->dev
, "Unqualified SFP+ module detected on port %d\n",
5684 if (bp
->hwrm_spec_code
>= 0x10201) {
5685 netdev_warn(bp
->dev
, "Module part number %s\n",
5686 resp
->phy_vendor_partnumber
);
5688 if (module_status
== PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX
)
5689 netdev_warn(bp
->dev
, "TX is disabled\n");
5690 if (module_status
== PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN
)
5691 netdev_warn(bp
->dev
, "SFP+ module is shutdown\n");
5696 bnxt_hwrm_set_pause_common(struct bnxt
*bp
, struct hwrm_port_phy_cfg_input
*req
)
5698 if (bp
->link_info
.autoneg
& BNXT_AUTONEG_FLOW_CTRL
) {
5699 if (bp
->hwrm_spec_code
>= 0x10201)
5701 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE
;
5702 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_RX
)
5703 req
->auto_pause
|= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX
;
5704 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_TX
)
5705 req
->auto_pause
|= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX
;
5707 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE
);
5709 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_RX
)
5710 req
->force_pause
|= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX
;
5711 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_TX
)
5712 req
->force_pause
|= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX
;
5714 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE
);
5715 if (bp
->hwrm_spec_code
>= 0x10201) {
5716 req
->auto_pause
= req
->force_pause
;
5717 req
->enables
|= cpu_to_le32(
5718 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE
);
5723 static void bnxt_hwrm_set_link_common(struct bnxt
*bp
,
5724 struct hwrm_port_phy_cfg_input
*req
)
5726 u8 autoneg
= bp
->link_info
.autoneg
;
5727 u16 fw_link_speed
= bp
->link_info
.req_link_speed
;
5728 u16 advertising
= bp
->link_info
.advertising
;
5730 if (autoneg
& BNXT_AUTONEG_SPEED
) {
5732 PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK
;
5734 req
->enables
|= cpu_to_le32(
5735 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK
);
5736 req
->auto_link_speed_mask
= cpu_to_le16(advertising
);
5738 req
->enables
|= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE
);
5740 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG
);
5742 req
->force_link_speed
= cpu_to_le16(fw_link_speed
);
5743 req
->flags
|= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE
);
5746 /* tell chimp that the setting takes effect immediately */
5747 req
->flags
|= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY
);
5750 int bnxt_hwrm_set_pause(struct bnxt
*bp
)
5752 struct hwrm_port_phy_cfg_input req
= {0};
5755 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_CFG
, -1, -1);
5756 bnxt_hwrm_set_pause_common(bp
, &req
);
5758 if ((bp
->link_info
.autoneg
& BNXT_AUTONEG_FLOW_CTRL
) ||
5759 bp
->link_info
.force_link_chng
)
5760 bnxt_hwrm_set_link_common(bp
, &req
);
5762 mutex_lock(&bp
->hwrm_cmd_lock
);
5763 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
5764 if (!rc
&& !(bp
->link_info
.autoneg
& BNXT_AUTONEG_FLOW_CTRL
)) {
5765 /* since changing of pause setting doesn't trigger any link
5766 * change event, the driver needs to update the current pause
5767 * result upon successfully return of the phy_cfg command
5769 bp
->link_info
.pause
=
5770 bp
->link_info
.force_pause_setting
= bp
->link_info
.req_flow_ctrl
;
5771 bp
->link_info
.auto_pause_setting
= 0;
5772 if (!bp
->link_info
.force_link_chng
)
5773 bnxt_report_link(bp
);
5775 bp
->link_info
.force_link_chng
= false;
5776 mutex_unlock(&bp
->hwrm_cmd_lock
);
5780 static void bnxt_hwrm_set_eee(struct bnxt
*bp
,
5781 struct hwrm_port_phy_cfg_input
*req
)
5783 struct ethtool_eee
*eee
= &bp
->eee
;
5785 if (eee
->eee_enabled
) {
5787 u32 flags
= PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE
;
5789 if (eee
->tx_lpi_enabled
)
5790 flags
|= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE
;
5792 flags
|= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE
;
5794 req
->flags
|= cpu_to_le32(flags
);
5795 eee_speeds
= bnxt_get_fw_auto_link_speeds(eee
->advertised
);
5796 req
->eee_link_speed_mask
= cpu_to_le16(eee_speeds
);
5797 req
->tx_lpi_timer
= cpu_to_le32(eee
->tx_lpi_timer
);
5799 req
->flags
|= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE
);
5803 int bnxt_hwrm_set_link_setting(struct bnxt
*bp
, bool set_pause
, bool set_eee
)
5805 struct hwrm_port_phy_cfg_input req
= {0};
5807 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_CFG
, -1, -1);
5809 bnxt_hwrm_set_pause_common(bp
, &req
);
5811 bnxt_hwrm_set_link_common(bp
, &req
);
5814 bnxt_hwrm_set_eee(bp
, &req
);
5815 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
5818 static int bnxt_hwrm_shutdown_link(struct bnxt
*bp
)
5820 struct hwrm_port_phy_cfg_input req
= {0};
5822 if (!BNXT_SINGLE_PF(bp
))
5825 if (pci_num_vf(bp
->pdev
))
5828 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_CFG
, -1, -1);
5829 req
.flags
= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN
);
5830 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
5833 static int bnxt_hwrm_port_led_qcaps(struct bnxt
*bp
)
5835 struct hwrm_port_led_qcaps_output
*resp
= bp
->hwrm_cmd_resp_addr
;
5836 struct hwrm_port_led_qcaps_input req
= {0};
5837 struct bnxt_pf_info
*pf
= &bp
->pf
;
5840 if (BNXT_VF(bp
) || bp
->hwrm_spec_code
< 0x10601)
5843 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_LED_QCAPS
, -1, -1);
5844 req
.port_id
= cpu_to_le16(pf
->port_id
);
5845 mutex_lock(&bp
->hwrm_cmd_lock
);
5846 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
5848 mutex_unlock(&bp
->hwrm_cmd_lock
);
5851 if (resp
->num_leds
> 0 && resp
->num_leds
< BNXT_MAX_LED
) {
5854 bp
->num_leds
= resp
->num_leds
;
5855 memcpy(bp
->leds
, &resp
->led0_id
, sizeof(bp
->leds
[0]) *
5857 for (i
= 0; i
< bp
->num_leds
; i
++) {
5858 struct bnxt_led_info
*led
= &bp
->leds
[i
];
5859 __le16 caps
= led
->led_state_caps
;
5861 if (!led
->led_group_id
||
5862 !BNXT_LED_ALT_BLINK_CAP(caps
)) {
5868 mutex_unlock(&bp
->hwrm_cmd_lock
);
5872 int bnxt_hwrm_alloc_wol_fltr(struct bnxt
*bp
)
5874 struct hwrm_wol_filter_alloc_input req
= {0};
5875 struct hwrm_wol_filter_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
5878 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_WOL_FILTER_ALLOC
, -1, -1);
5879 req
.port_id
= cpu_to_le16(bp
->pf
.port_id
);
5880 req
.wol_type
= WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT
;
5881 req
.enables
= cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS
);
5882 memcpy(req
.mac_address
, bp
->dev
->dev_addr
, ETH_ALEN
);
5883 mutex_lock(&bp
->hwrm_cmd_lock
);
5884 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
5886 bp
->wol_filter_id
= resp
->wol_filter_id
;
5887 mutex_unlock(&bp
->hwrm_cmd_lock
);
5891 int bnxt_hwrm_free_wol_fltr(struct bnxt
*bp
)
5893 struct hwrm_wol_filter_free_input req
= {0};
5896 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_WOL_FILTER_FREE
, -1, -1);
5897 req
.port_id
= cpu_to_le16(bp
->pf
.port_id
);
5898 req
.enables
= cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID
);
5899 req
.wol_filter_id
= bp
->wol_filter_id
;
5900 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
5904 static u16
bnxt_hwrm_get_wol_fltrs(struct bnxt
*bp
, u16 handle
)
5906 struct hwrm_wol_filter_qcfg_input req
= {0};
5907 struct hwrm_wol_filter_qcfg_output
*resp
= bp
->hwrm_cmd_resp_addr
;
5908 u16 next_handle
= 0;
5911 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_WOL_FILTER_QCFG
, -1, -1);
5912 req
.port_id
= cpu_to_le16(bp
->pf
.port_id
);
5913 req
.handle
= cpu_to_le16(handle
);
5914 mutex_lock(&bp
->hwrm_cmd_lock
);
5915 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
5917 next_handle
= le16_to_cpu(resp
->next_handle
);
5918 if (next_handle
!= 0) {
5919 if (resp
->wol_type
==
5920 WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT
) {
5922 bp
->wol_filter_id
= resp
->wol_filter_id
;
5926 mutex_unlock(&bp
->hwrm_cmd_lock
);
5930 static void bnxt_get_wol_settings(struct bnxt
*bp
)
5934 if (!BNXT_PF(bp
) || !(bp
->flags
& BNXT_FLAG_WOL_CAP
))
5938 handle
= bnxt_hwrm_get_wol_fltrs(bp
, handle
);
5939 } while (handle
&& handle
!= 0xffff);
5942 static bool bnxt_eee_config_ok(struct bnxt
*bp
)
5944 struct ethtool_eee
*eee
= &bp
->eee
;
5945 struct bnxt_link_info
*link_info
= &bp
->link_info
;
5947 if (!(bp
->flags
& BNXT_FLAG_EEE_CAP
))
5950 if (eee
->eee_enabled
) {
5952 _bnxt_fw_to_ethtool_adv_spds(link_info
->advertising
, 0);
5954 if (!(link_info
->autoneg
& BNXT_AUTONEG_SPEED
)) {
5955 eee
->eee_enabled
= 0;
5958 if (eee
->advertised
& ~advertising
) {
5959 eee
->advertised
= advertising
& eee
->supported
;
5966 static int bnxt_update_phy_setting(struct bnxt
*bp
)
5969 bool update_link
= false;
5970 bool update_pause
= false;
5971 bool update_eee
= false;
5972 struct bnxt_link_info
*link_info
= &bp
->link_info
;
5974 rc
= bnxt_update_link(bp
, true);
5976 netdev_err(bp
->dev
, "failed to update link (rc: %x)\n",
5980 if (!BNXT_SINGLE_PF(bp
))
5983 if ((link_info
->autoneg
& BNXT_AUTONEG_FLOW_CTRL
) &&
5984 (link_info
->auto_pause_setting
& BNXT_LINK_PAUSE_BOTH
) !=
5985 link_info
->req_flow_ctrl
)
5986 update_pause
= true;
5987 if (!(link_info
->autoneg
& BNXT_AUTONEG_FLOW_CTRL
) &&
5988 link_info
->force_pause_setting
!= link_info
->req_flow_ctrl
)
5989 update_pause
= true;
5990 if (!(link_info
->autoneg
& BNXT_AUTONEG_SPEED
)) {
5991 if (BNXT_AUTO_MODE(link_info
->auto_mode
))
5993 if (link_info
->req_link_speed
!= link_info
->force_link_speed
)
5995 if (link_info
->req_duplex
!= link_info
->duplex_setting
)
5998 if (link_info
->auto_mode
== BNXT_LINK_AUTO_NONE
)
6000 if (link_info
->advertising
!= link_info
->auto_link_speeds
)
6004 /* The last close may have shutdown the link, so need to call
6005 * PHY_CFG to bring it back up.
6007 if (!netif_carrier_ok(bp
->dev
))
6010 if (!bnxt_eee_config_ok(bp
))
6014 rc
= bnxt_hwrm_set_link_setting(bp
, update_pause
, update_eee
);
6015 else if (update_pause
)
6016 rc
= bnxt_hwrm_set_pause(bp
);
6018 netdev_err(bp
->dev
, "failed to update phy setting (rc: %x)\n",
6026 /* Common routine to pre-map certain register block to different GRC window.
6027 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
6028 * in PF and 3 windows in VF that can be customized to map in different
6031 static void bnxt_preset_reg_win(struct bnxt
*bp
)
6034 /* CAG registers map to GRC window #4 */
6035 writel(BNXT_CAG_REG_BASE
,
6036 bp
->bar0
+ BNXT_GRCPF_REG_WINDOW_BASE_OUT
+ 12);
6040 static int __bnxt_open_nic(struct bnxt
*bp
, bool irq_re_init
, bool link_re_init
)
6044 bnxt_preset_reg_win(bp
);
6045 netif_carrier_off(bp
->dev
);
6047 rc
= bnxt_setup_int_mode(bp
);
6049 netdev_err(bp
->dev
, "bnxt_setup_int_mode err: %x\n",
6054 if ((bp
->flags
& BNXT_FLAG_RFS
) &&
6055 !(bp
->flags
& BNXT_FLAG_USING_MSIX
)) {
6056 /* disable RFS if falling back to INTA */
6057 bp
->dev
->hw_features
&= ~NETIF_F_NTUPLE
;
6058 bp
->flags
&= ~BNXT_FLAG_RFS
;
6061 rc
= bnxt_alloc_mem(bp
, irq_re_init
);
6063 netdev_err(bp
->dev
, "bnxt_alloc_mem err: %x\n", rc
);
6064 goto open_err_free_mem
;
6069 rc
= bnxt_request_irq(bp
);
6071 netdev_err(bp
->dev
, "bnxt_request_irq err: %x\n", rc
);
6076 bnxt_enable_napi(bp
);
6078 rc
= bnxt_init_nic(bp
, irq_re_init
);
6080 netdev_err(bp
->dev
, "bnxt_init_nic err: %x\n", rc
);
6085 rc
= bnxt_update_phy_setting(bp
);
6087 netdev_warn(bp
->dev
, "failed to update phy settings\n");
6091 udp_tunnel_get_rx_info(bp
->dev
);
6093 set_bit(BNXT_STATE_OPEN
, &bp
->state
);
6094 bnxt_enable_int(bp
);
6095 /* Enable TX queues */
6097 mod_timer(&bp
->timer
, jiffies
+ bp
->current_interval
);
6098 /* Poll link status and check for SFP+ module status */
6099 bnxt_get_port_module_status(bp
);
6104 bnxt_disable_napi(bp
);
6110 bnxt_free_mem(bp
, true);
6114 /* rtnl_lock held */
6115 int bnxt_open_nic(struct bnxt
*bp
, bool irq_re_init
, bool link_re_init
)
6119 rc
= __bnxt_open_nic(bp
, irq_re_init
, link_re_init
);
6121 netdev_err(bp
->dev
, "nic open fail (rc: %x)\n", rc
);
6127 /* rtnl_lock held, open the NIC half way by allocating all resources, but
6128 * NAPI, IRQ, and TX are not enabled. This is mainly used for offline
6131 int bnxt_half_open_nic(struct bnxt
*bp
)
6135 rc
= bnxt_alloc_mem(bp
, false);
6137 netdev_err(bp
->dev
, "bnxt_alloc_mem err: %x\n", rc
);
6140 rc
= bnxt_init_nic(bp
, false);
6142 netdev_err(bp
->dev
, "bnxt_init_nic err: %x\n", rc
);
6149 bnxt_free_mem(bp
, false);
6154 /* rtnl_lock held, this call can only be made after a previous successful
6155 * call to bnxt_half_open_nic().
6157 void bnxt_half_close_nic(struct bnxt
*bp
)
6159 bnxt_hwrm_resource_free(bp
, false, false);
6161 bnxt_free_mem(bp
, false);
6164 static int bnxt_open(struct net_device
*dev
)
6166 struct bnxt
*bp
= netdev_priv(dev
);
6168 return __bnxt_open_nic(bp
, true, true);
6171 int bnxt_close_nic(struct bnxt
*bp
, bool irq_re_init
, bool link_re_init
)
6175 #ifdef CONFIG_BNXT_SRIOV
6176 if (bp
->sriov_cfg
) {
6177 rc
= wait_event_interruptible_timeout(bp
->sriov_cfg_wait
,
6179 BNXT_SRIOV_CFG_WAIT_TMO
);
6181 netdev_warn(bp
->dev
, "timeout waiting for SRIOV config operation to complete!\n");
6184 /* Change device state to avoid TX queue wake up's */
6185 bnxt_tx_disable(bp
);
6187 clear_bit(BNXT_STATE_OPEN
, &bp
->state
);
6188 smp_mb__after_atomic();
6189 while (test_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
))
6192 /* Flush rings and and disable interrupts */
6193 bnxt_shutdown_nic(bp
, irq_re_init
);
6195 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
6197 bnxt_disable_napi(bp
);
6198 del_timer_sync(&bp
->timer
);
6205 bnxt_free_mem(bp
, irq_re_init
);
6209 static int bnxt_close(struct net_device
*dev
)
6211 struct bnxt
*bp
= netdev_priv(dev
);
6213 bnxt_close_nic(bp
, true, true);
6214 bnxt_hwrm_shutdown_link(bp
);
6218 /* rtnl_lock held */
6219 static int bnxt_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
6225 if (!netif_running(dev
))
6232 if (!netif_running(dev
))
6245 bnxt_get_stats64(struct net_device
*dev
, struct rtnl_link_stats64
*stats
)
6248 struct bnxt
*bp
= netdev_priv(dev
);
6253 /* TODO check if we need to synchronize with bnxt_close path */
6254 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
6255 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
6256 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
6257 struct ctx_hw_stats
*hw_stats
= cpr
->hw_stats
;
6259 stats
->rx_packets
+= le64_to_cpu(hw_stats
->rx_ucast_pkts
);
6260 stats
->rx_packets
+= le64_to_cpu(hw_stats
->rx_mcast_pkts
);
6261 stats
->rx_packets
+= le64_to_cpu(hw_stats
->rx_bcast_pkts
);
6263 stats
->tx_packets
+= le64_to_cpu(hw_stats
->tx_ucast_pkts
);
6264 stats
->tx_packets
+= le64_to_cpu(hw_stats
->tx_mcast_pkts
);
6265 stats
->tx_packets
+= le64_to_cpu(hw_stats
->tx_bcast_pkts
);
6267 stats
->rx_bytes
+= le64_to_cpu(hw_stats
->rx_ucast_bytes
);
6268 stats
->rx_bytes
+= le64_to_cpu(hw_stats
->rx_mcast_bytes
);
6269 stats
->rx_bytes
+= le64_to_cpu(hw_stats
->rx_bcast_bytes
);
6271 stats
->tx_bytes
+= le64_to_cpu(hw_stats
->tx_ucast_bytes
);
6272 stats
->tx_bytes
+= le64_to_cpu(hw_stats
->tx_mcast_bytes
);
6273 stats
->tx_bytes
+= le64_to_cpu(hw_stats
->tx_bcast_bytes
);
6275 stats
->rx_missed_errors
+=
6276 le64_to_cpu(hw_stats
->rx_discard_pkts
);
6278 stats
->multicast
+= le64_to_cpu(hw_stats
->rx_mcast_pkts
);
6280 stats
->tx_dropped
+= le64_to_cpu(hw_stats
->tx_drop_pkts
);
6283 if (bp
->flags
& BNXT_FLAG_PORT_STATS
) {
6284 struct rx_port_stats
*rx
= bp
->hw_rx_port_stats
;
6285 struct tx_port_stats
*tx
= bp
->hw_tx_port_stats
;
6287 stats
->rx_crc_errors
= le64_to_cpu(rx
->rx_fcs_err_frames
);
6288 stats
->rx_frame_errors
= le64_to_cpu(rx
->rx_align_err_frames
);
6289 stats
->rx_length_errors
= le64_to_cpu(rx
->rx_undrsz_frames
) +
6290 le64_to_cpu(rx
->rx_ovrsz_frames
) +
6291 le64_to_cpu(rx
->rx_runt_frames
);
6292 stats
->rx_errors
= le64_to_cpu(rx
->rx_false_carrier_frames
) +
6293 le64_to_cpu(rx
->rx_jbr_frames
);
6294 stats
->collisions
= le64_to_cpu(tx
->tx_total_collisions
);
6295 stats
->tx_fifo_errors
= le64_to_cpu(tx
->tx_fifo_underruns
);
6296 stats
->tx_errors
= le64_to_cpu(tx
->tx_err
);
6300 static bool bnxt_mc_list_updated(struct bnxt
*bp
, u32
*rx_mask
)
6302 struct net_device
*dev
= bp
->dev
;
6303 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
6304 struct netdev_hw_addr
*ha
;
6307 bool update
= false;
6310 netdev_for_each_mc_addr(ha
, dev
) {
6311 if (mc_count
>= BNXT_MAX_MC_ADDRS
) {
6312 *rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
;
6313 vnic
->mc_list_count
= 0;
6317 if (!ether_addr_equal(haddr
, vnic
->mc_list
+ off
)) {
6318 memcpy(vnic
->mc_list
+ off
, haddr
, ETH_ALEN
);
6325 *rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST
;
6327 if (mc_count
!= vnic
->mc_list_count
) {
6328 vnic
->mc_list_count
= mc_count
;
6334 static bool bnxt_uc_list_updated(struct bnxt
*bp
)
6336 struct net_device
*dev
= bp
->dev
;
6337 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
6338 struct netdev_hw_addr
*ha
;
6341 if (netdev_uc_count(dev
) != (vnic
->uc_filter_count
- 1))
6344 netdev_for_each_uc_addr(ha
, dev
) {
6345 if (!ether_addr_equal(ha
->addr
, vnic
->uc_list
+ off
))
6353 static void bnxt_set_rx_mode(struct net_device
*dev
)
6355 struct bnxt
*bp
= netdev_priv(dev
);
6356 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
6357 u32 mask
= vnic
->rx_mask
;
6358 bool mc_update
= false;
6361 if (!netif_running(dev
))
6364 mask
&= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
|
6365 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST
|
6366 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
);
6368 if ((dev
->flags
& IFF_PROMISC
) && bnxt_promisc_ok(bp
))
6369 mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
;
6371 uc_update
= bnxt_uc_list_updated(bp
);
6373 if (dev
->flags
& IFF_ALLMULTI
) {
6374 mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
;
6375 vnic
->mc_list_count
= 0;
6377 mc_update
= bnxt_mc_list_updated(bp
, &mask
);
6380 if (mask
!= vnic
->rx_mask
|| uc_update
|| mc_update
) {
6381 vnic
->rx_mask
= mask
;
6383 set_bit(BNXT_RX_MASK_SP_EVENT
, &bp
->sp_event
);
6384 schedule_work(&bp
->sp_task
);
6388 static int bnxt_cfg_rx_mode(struct bnxt
*bp
)
6390 struct net_device
*dev
= bp
->dev
;
6391 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
6392 struct netdev_hw_addr
*ha
;
6396 netif_addr_lock_bh(dev
);
6397 uc_update
= bnxt_uc_list_updated(bp
);
6398 netif_addr_unlock_bh(dev
);
6403 mutex_lock(&bp
->hwrm_cmd_lock
);
6404 for (i
= 1; i
< vnic
->uc_filter_count
; i
++) {
6405 struct hwrm_cfa_l2_filter_free_input req
= {0};
6407 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_L2_FILTER_FREE
, -1,
6410 req
.l2_filter_id
= vnic
->fw_l2_filter_id
[i
];
6412 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
6415 mutex_unlock(&bp
->hwrm_cmd_lock
);
6417 vnic
->uc_filter_count
= 1;
6419 netif_addr_lock_bh(dev
);
6420 if (netdev_uc_count(dev
) > (BNXT_MAX_UC_ADDRS
- 1)) {
6421 vnic
->rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
;
6423 netdev_for_each_uc_addr(ha
, dev
) {
6424 memcpy(vnic
->uc_list
+ off
, ha
->addr
, ETH_ALEN
);
6426 vnic
->uc_filter_count
++;
6429 netif_addr_unlock_bh(dev
);
6431 for (i
= 1, off
= 0; i
< vnic
->uc_filter_count
; i
++, off
+= ETH_ALEN
) {
6432 rc
= bnxt_hwrm_set_vnic_filter(bp
, 0, i
, vnic
->uc_list
+ off
);
6434 netdev_err(bp
->dev
, "HWRM vnic filter failure rc: %x\n",
6436 vnic
->uc_filter_count
= i
;
6442 rc
= bnxt_hwrm_cfa_l2_set_rx_mask(bp
, 0);
6444 netdev_err(bp
->dev
, "HWRM cfa l2 rx mask failure rc: %x\n",
6450 /* If the chip and firmware supports RFS */
6451 static bool bnxt_rfs_supported(struct bnxt
*bp
)
6453 if (BNXT_PF(bp
) && !BNXT_CHIP_TYPE_NITRO_A0(bp
))
6455 if (bp
->flags
& BNXT_FLAG_NEW_RSS_CAP
)
6460 /* If runtime conditions support RFS */
6461 static bool bnxt_rfs_capable(struct bnxt
*bp
)
6463 #ifdef CONFIG_RFS_ACCEL
6464 int vnics
, max_vnics
, max_rss_ctxs
;
6466 if (!(bp
->flags
& BNXT_FLAG_MSIX_CAP
))
6469 vnics
= 1 + bp
->rx_nr_rings
;
6470 max_vnics
= bnxt_get_max_func_vnics(bp
);
6471 max_rss_ctxs
= bnxt_get_max_func_rss_ctxs(bp
);
6473 /* RSS contexts not a limiting factor */
6474 if (bp
->flags
& BNXT_FLAG_NEW_RSS_CAP
)
6475 max_rss_ctxs
= max_vnics
;
6476 if (vnics
> max_vnics
|| vnics
> max_rss_ctxs
) {
6477 netdev_warn(bp
->dev
,
6478 "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
6479 min(max_rss_ctxs
- 1, max_vnics
- 1));
6489 static netdev_features_t
bnxt_fix_features(struct net_device
*dev
,
6490 netdev_features_t features
)
6492 struct bnxt
*bp
= netdev_priv(dev
);
6494 if ((features
& NETIF_F_NTUPLE
) && !bnxt_rfs_capable(bp
))
6495 features
&= ~NETIF_F_NTUPLE
;
6497 /* Both CTAG and STAG VLAN accelaration on the RX side have to be
6498 * turned on or off together.
6500 if ((features
& (NETIF_F_HW_VLAN_CTAG_RX
| NETIF_F_HW_VLAN_STAG_RX
)) !=
6501 (NETIF_F_HW_VLAN_CTAG_RX
| NETIF_F_HW_VLAN_STAG_RX
)) {
6502 if (dev
->features
& NETIF_F_HW_VLAN_CTAG_RX
)
6503 features
&= ~(NETIF_F_HW_VLAN_CTAG_RX
|
6504 NETIF_F_HW_VLAN_STAG_RX
);
6506 features
|= NETIF_F_HW_VLAN_CTAG_RX
|
6507 NETIF_F_HW_VLAN_STAG_RX
;
6509 #ifdef CONFIG_BNXT_SRIOV
6512 features
&= ~(NETIF_F_HW_VLAN_CTAG_RX
|
6513 NETIF_F_HW_VLAN_STAG_RX
);
6520 static int bnxt_set_features(struct net_device
*dev
, netdev_features_t features
)
6522 struct bnxt
*bp
= netdev_priv(dev
);
6523 u32 flags
= bp
->flags
;
6526 bool re_init
= false;
6527 bool update_tpa
= false;
6529 flags
&= ~BNXT_FLAG_ALL_CONFIG_FEATS
;
6530 if ((features
& NETIF_F_GRO
) && !BNXT_CHIP_TYPE_NITRO_A0(bp
))
6531 flags
|= BNXT_FLAG_GRO
;
6532 if (features
& NETIF_F_LRO
)
6533 flags
|= BNXT_FLAG_LRO
;
6535 if (bp
->flags
& BNXT_FLAG_NO_AGG_RINGS
)
6536 flags
&= ~BNXT_FLAG_TPA
;
6538 if (features
& NETIF_F_HW_VLAN_CTAG_RX
)
6539 flags
|= BNXT_FLAG_STRIP_VLAN
;
6541 if (features
& NETIF_F_NTUPLE
)
6542 flags
|= BNXT_FLAG_RFS
;
6544 changes
= flags
^ bp
->flags
;
6545 if (changes
& BNXT_FLAG_TPA
) {
6547 if ((bp
->flags
& BNXT_FLAG_TPA
) == 0 ||
6548 (flags
& BNXT_FLAG_TPA
) == 0)
6552 if (changes
& ~BNXT_FLAG_TPA
)
6555 if (flags
!= bp
->flags
) {
6556 u32 old_flags
= bp
->flags
;
6560 if (!test_bit(BNXT_STATE_OPEN
, &bp
->state
)) {
6562 bnxt_set_ring_params(bp
);
6567 bnxt_close_nic(bp
, false, false);
6569 bnxt_set_ring_params(bp
);
6571 return bnxt_open_nic(bp
, false, false);
6574 rc
= bnxt_set_tpa(bp
,
6575 (flags
& BNXT_FLAG_TPA
) ?
6578 bp
->flags
= old_flags
;
6584 static void bnxt_dump_tx_sw_state(struct bnxt_napi
*bnapi
)
6586 struct bnxt_tx_ring_info
*txr
= bnapi
->tx_ring
;
6587 int i
= bnapi
->index
;
6592 netdev_info(bnapi
->bp
->dev
, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
6593 i
, txr
->tx_ring_struct
.fw_ring_id
, txr
->tx_prod
,
6597 static void bnxt_dump_rx_sw_state(struct bnxt_napi
*bnapi
)
6599 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
6600 int i
= bnapi
->index
;
6605 netdev_info(bnapi
->bp
->dev
, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
6606 i
, rxr
->rx_ring_struct
.fw_ring_id
, rxr
->rx_prod
,
6607 rxr
->rx_agg_ring_struct
.fw_ring_id
, rxr
->rx_agg_prod
,
6608 rxr
->rx_sw_agg_prod
);
6611 static void bnxt_dump_cp_sw_state(struct bnxt_napi
*bnapi
)
6613 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
6614 int i
= bnapi
->index
;
6616 netdev_info(bnapi
->bp
->dev
, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
6617 i
, cpr
->cp_ring_struct
.fw_ring_id
, cpr
->cp_raw_cons
);
6620 static void bnxt_dbg_dump_states(struct bnxt
*bp
)
6623 struct bnxt_napi
*bnapi
;
6625 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
6626 bnapi
= bp
->bnapi
[i
];
6627 if (netif_msg_drv(bp
)) {
6628 bnxt_dump_tx_sw_state(bnapi
);
6629 bnxt_dump_rx_sw_state(bnapi
);
6630 bnxt_dump_cp_sw_state(bnapi
);
6635 static void bnxt_reset_task(struct bnxt
*bp
, bool silent
)
6638 bnxt_dbg_dump_states(bp
);
6639 if (netif_running(bp
->dev
)) {
6644 bnxt_close_nic(bp
, false, false);
6645 rc
= bnxt_open_nic(bp
, false, false);
6651 static void bnxt_tx_timeout(struct net_device
*dev
)
6653 struct bnxt
*bp
= netdev_priv(dev
);
6655 netdev_err(bp
->dev
, "TX timeout detected, starting reset task!\n");
6656 set_bit(BNXT_RESET_TASK_SP_EVENT
, &bp
->sp_event
);
6657 schedule_work(&bp
->sp_task
);
6660 #ifdef CONFIG_NET_POLL_CONTROLLER
6661 static void bnxt_poll_controller(struct net_device
*dev
)
6663 struct bnxt
*bp
= netdev_priv(dev
);
6666 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
6667 struct bnxt_irq
*irq
= &bp
->irq_tbl
[i
];
6669 disable_irq(irq
->vector
);
6670 irq
->handler(irq
->vector
, bp
->bnapi
[i
]);
6671 enable_irq(irq
->vector
);
6676 static void bnxt_timer(unsigned long data
)
6678 struct bnxt
*bp
= (struct bnxt
*)data
;
6679 struct net_device
*dev
= bp
->dev
;
6681 if (!netif_running(dev
))
6684 if (atomic_read(&bp
->intr_sem
) != 0)
6685 goto bnxt_restart_timer
;
6687 if (bp
->link_info
.link_up
&& (bp
->flags
& BNXT_FLAG_PORT_STATS
)) {
6688 set_bit(BNXT_PERIODIC_STATS_SP_EVENT
, &bp
->sp_event
);
6689 schedule_work(&bp
->sp_task
);
6692 mod_timer(&bp
->timer
, jiffies
+ bp
->current_interval
);
6695 static void bnxt_rtnl_lock_sp(struct bnxt
*bp
)
6697 /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK
6698 * set. If the device is being closed, bnxt_close() may be holding
6699 * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we
6700 * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
6702 clear_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
6706 static void bnxt_rtnl_unlock_sp(struct bnxt
*bp
)
6708 set_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
6712 /* Only called from bnxt_sp_task() */
6713 static void bnxt_reset(struct bnxt
*bp
, bool silent
)
6715 bnxt_rtnl_lock_sp(bp
);
6716 if (test_bit(BNXT_STATE_OPEN
, &bp
->state
))
6717 bnxt_reset_task(bp
, silent
);
6718 bnxt_rtnl_unlock_sp(bp
);
6721 static void bnxt_cfg_ntp_filters(struct bnxt
*);
6723 static void bnxt_sp_task(struct work_struct
*work
)
6725 struct bnxt
*bp
= container_of(work
, struct bnxt
, sp_task
);
6727 set_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
6728 smp_mb__after_atomic();
6729 if (!test_bit(BNXT_STATE_OPEN
, &bp
->state
)) {
6730 clear_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
6734 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT
, &bp
->sp_event
))
6735 bnxt_cfg_rx_mode(bp
);
6737 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT
, &bp
->sp_event
))
6738 bnxt_cfg_ntp_filters(bp
);
6739 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT
, &bp
->sp_event
))
6740 bnxt_hwrm_exec_fwd_req(bp
);
6741 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT
, &bp
->sp_event
)) {
6742 bnxt_hwrm_tunnel_dst_port_alloc(
6744 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
);
6746 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT
, &bp
->sp_event
)) {
6747 bnxt_hwrm_tunnel_dst_port_free(
6748 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
);
6750 if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT
, &bp
->sp_event
)) {
6751 bnxt_hwrm_tunnel_dst_port_alloc(
6753 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
);
6755 if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT
, &bp
->sp_event
)) {
6756 bnxt_hwrm_tunnel_dst_port_free(
6757 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
);
6759 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT
, &bp
->sp_event
))
6760 bnxt_hwrm_port_qstats(bp
);
6762 /* These functions below will clear BNXT_STATE_IN_SP_TASK. They
6763 * must be the last functions to be called before exiting.
6765 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT
, &bp
->sp_event
)) {
6768 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT
,
6770 bnxt_hwrm_phy_qcaps(bp
);
6772 bnxt_rtnl_lock_sp(bp
);
6773 if (test_bit(BNXT_STATE_OPEN
, &bp
->state
))
6774 rc
= bnxt_update_link(bp
, true);
6775 bnxt_rtnl_unlock_sp(bp
);
6777 netdev_err(bp
->dev
, "SP task can't update link (rc: %x)\n",
6780 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT
, &bp
->sp_event
)) {
6781 bnxt_rtnl_lock_sp(bp
);
6782 if (test_bit(BNXT_STATE_OPEN
, &bp
->state
))
6783 bnxt_get_port_module_status(bp
);
6784 bnxt_rtnl_unlock_sp(bp
);
6786 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT
, &bp
->sp_event
))
6787 bnxt_reset(bp
, false);
6789 if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT
, &bp
->sp_event
))
6790 bnxt_reset(bp
, true);
6792 smp_mb__before_atomic();
6793 clear_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
6796 /* Under rtnl_lock */
6797 int bnxt_reserve_rings(struct bnxt
*bp
, int tx
, int rx
, int tcs
, int tx_xdp
)
6799 int max_rx
, max_tx
, tx_sets
= 1;
6800 int tx_rings_needed
;
6804 if (!(bp
->flags
& BNXT_FLAG_SHARED_RINGS
))
6810 rc
= bnxt_get_max_rings(bp
, &max_rx
, &max_tx
, sh
);
6817 tx_rings_needed
= tx
* tx_sets
+ tx_xdp
;
6818 if (max_tx
< tx_rings_needed
)
6821 if (bnxt_hwrm_reserve_tx_rings(bp
, &tx_rings_needed
) ||
6822 tx_rings_needed
< (tx
* tx_sets
+ tx_xdp
))
6827 static void bnxt_unmap_bars(struct bnxt
*bp
, struct pci_dev
*pdev
)
6830 pci_iounmap(pdev
, bp
->bar2
);
6835 pci_iounmap(pdev
, bp
->bar1
);
6840 pci_iounmap(pdev
, bp
->bar0
);
6845 static void bnxt_cleanup_pci(struct bnxt
*bp
)
6847 bnxt_unmap_bars(bp
, bp
->pdev
);
6848 pci_release_regions(bp
->pdev
);
6849 pci_disable_device(bp
->pdev
);
6852 static int bnxt_init_board(struct pci_dev
*pdev
, struct net_device
*dev
)
6855 struct bnxt
*bp
= netdev_priv(dev
);
6857 SET_NETDEV_DEV(dev
, &pdev
->dev
);
6859 /* enable device (incl. PCI PM wakeup), and bus-mastering */
6860 rc
= pci_enable_device(pdev
);
6862 dev_err(&pdev
->dev
, "Cannot enable PCI device, aborting\n");
6866 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
6868 "Cannot find PCI device base address, aborting\n");
6870 goto init_err_disable
;
6873 rc
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
6875 dev_err(&pdev
->dev
, "Cannot obtain PCI resources, aborting\n");
6876 goto init_err_disable
;
6879 if (dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(64)) != 0 &&
6880 dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(32)) != 0) {
6881 dev_err(&pdev
->dev
, "System does not support DMA, aborting\n");
6882 goto init_err_disable
;
6885 pci_set_master(pdev
);
6890 bp
->bar0
= pci_ioremap_bar(pdev
, 0);
6892 dev_err(&pdev
->dev
, "Cannot map device registers, aborting\n");
6894 goto init_err_release
;
6897 bp
->bar1
= pci_ioremap_bar(pdev
, 2);
6899 dev_err(&pdev
->dev
, "Cannot map doorbell registers, aborting\n");
6901 goto init_err_release
;
6904 bp
->bar2
= pci_ioremap_bar(pdev
, 4);
6906 dev_err(&pdev
->dev
, "Cannot map bar4 registers, aborting\n");
6908 goto init_err_release
;
6911 pci_enable_pcie_error_reporting(pdev
);
6913 INIT_WORK(&bp
->sp_task
, bnxt_sp_task
);
6915 spin_lock_init(&bp
->ntp_fltr_lock
);
6917 bp
->rx_ring_size
= BNXT_DEFAULT_RX_RING_SIZE
;
6918 bp
->tx_ring_size
= BNXT_DEFAULT_TX_RING_SIZE
;
6920 /* tick values in micro seconds */
6921 bp
->rx_coal_ticks
= 12;
6922 bp
->rx_coal_bufs
= 30;
6923 bp
->rx_coal_ticks_irq
= 1;
6924 bp
->rx_coal_bufs_irq
= 2;
6926 bp
->tx_coal_ticks
= 25;
6927 bp
->tx_coal_bufs
= 30;
6928 bp
->tx_coal_ticks_irq
= 2;
6929 bp
->tx_coal_bufs_irq
= 2;
6931 bp
->stats_coal_ticks
= BNXT_DEF_STATS_COAL_TICKS
;
6933 init_timer(&bp
->timer
);
6934 bp
->timer
.data
= (unsigned long)bp
;
6935 bp
->timer
.function
= bnxt_timer
;
6936 bp
->current_interval
= BNXT_TIMER_INTERVAL
;
6938 clear_bit(BNXT_STATE_OPEN
, &bp
->state
);
6942 bnxt_unmap_bars(bp
, pdev
);
6943 pci_release_regions(pdev
);
6946 pci_disable_device(pdev
);
6952 /* rtnl_lock held */
6953 static int bnxt_change_mac_addr(struct net_device
*dev
, void *p
)
6955 struct sockaddr
*addr
= p
;
6956 struct bnxt
*bp
= netdev_priv(dev
);
6959 if (!is_valid_ether_addr(addr
->sa_data
))
6960 return -EADDRNOTAVAIL
;
6962 rc
= bnxt_approve_mac(bp
, addr
->sa_data
);
6966 if (ether_addr_equal(addr
->sa_data
, dev
->dev_addr
))
6969 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
6970 if (netif_running(dev
)) {
6971 bnxt_close_nic(bp
, false, false);
6972 rc
= bnxt_open_nic(bp
, false, false);
6978 /* rtnl_lock held */
6979 static int bnxt_change_mtu(struct net_device
*dev
, int new_mtu
)
6981 struct bnxt
*bp
= netdev_priv(dev
);
6983 if (netif_running(dev
))
6984 bnxt_close_nic(bp
, false, false);
6987 bnxt_set_ring_params(bp
);
6989 if (netif_running(dev
))
6990 return bnxt_open_nic(bp
, false, false);
6995 int bnxt_setup_mq_tc(struct net_device
*dev
, u8 tc
)
6997 struct bnxt
*bp
= netdev_priv(dev
);
7001 if (tc
> bp
->max_tc
) {
7002 netdev_err(dev
, "Too many traffic classes requested: %d. Max supported is %d.\n",
7007 if (netdev_get_num_tc(dev
) == tc
)
7010 if (bp
->flags
& BNXT_FLAG_SHARED_RINGS
)
7013 rc
= bnxt_reserve_rings(bp
, bp
->tx_nr_rings_per_tc
, bp
->rx_nr_rings
,
7014 tc
, bp
->tx_nr_rings_xdp
);
7018 /* Needs to close the device and do hw resource re-allocations */
7019 if (netif_running(bp
->dev
))
7020 bnxt_close_nic(bp
, true, false);
7023 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
* tc
;
7024 netdev_set_num_tc(dev
, tc
);
7026 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
;
7027 netdev_reset_tc(dev
);
7029 bp
->cp_nr_rings
= sh
? max_t(int, bp
->tx_nr_rings
, bp
->rx_nr_rings
) :
7030 bp
->tx_nr_rings
+ bp
->rx_nr_rings
;
7031 bp
->num_stat_ctxs
= bp
->cp_nr_rings
;
7033 if (netif_running(bp
->dev
))
7034 return bnxt_open_nic(bp
, true, false);
7039 static int bnxt_setup_tc(struct net_device
*dev
, u32 handle
, __be16 proto
,
7040 struct tc_to_netdev
*ntc
)
7042 if (ntc
->type
!= TC_SETUP_MQPRIO
)
7045 ntc
->mqprio
->hw
= TC_MQPRIO_HW_OFFLOAD_TCS
;
7047 return bnxt_setup_mq_tc(dev
, ntc
->mqprio
->num_tc
);
7050 #ifdef CONFIG_RFS_ACCEL
7051 static bool bnxt_fltr_match(struct bnxt_ntuple_filter
*f1
,
7052 struct bnxt_ntuple_filter
*f2
)
7054 struct flow_keys
*keys1
= &f1
->fkeys
;
7055 struct flow_keys
*keys2
= &f2
->fkeys
;
7057 if (keys1
->addrs
.v4addrs
.src
== keys2
->addrs
.v4addrs
.src
&&
7058 keys1
->addrs
.v4addrs
.dst
== keys2
->addrs
.v4addrs
.dst
&&
7059 keys1
->ports
.ports
== keys2
->ports
.ports
&&
7060 keys1
->basic
.ip_proto
== keys2
->basic
.ip_proto
&&
7061 keys1
->basic
.n_proto
== keys2
->basic
.n_proto
&&
7062 keys1
->control
.flags
== keys2
->control
.flags
&&
7063 ether_addr_equal(f1
->src_mac_addr
, f2
->src_mac_addr
) &&
7064 ether_addr_equal(f1
->dst_mac_addr
, f2
->dst_mac_addr
))
7070 static int bnxt_rx_flow_steer(struct net_device
*dev
, const struct sk_buff
*skb
,
7071 u16 rxq_index
, u32 flow_id
)
7073 struct bnxt
*bp
= netdev_priv(dev
);
7074 struct bnxt_ntuple_filter
*fltr
, *new_fltr
;
7075 struct flow_keys
*fkeys
;
7076 struct ethhdr
*eth
= (struct ethhdr
*)skb_mac_header(skb
);
7077 int rc
= 0, idx
, bit_id
, l2_idx
= 0;
7078 struct hlist_head
*head
;
7080 if (!ether_addr_equal(dev
->dev_addr
, eth
->h_dest
)) {
7081 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
7084 netif_addr_lock_bh(dev
);
7085 for (j
= 0; j
< vnic
->uc_filter_count
; j
++, off
+= ETH_ALEN
) {
7086 if (ether_addr_equal(eth
->h_dest
,
7087 vnic
->uc_list
+ off
)) {
7092 netif_addr_unlock_bh(dev
);
7096 new_fltr
= kzalloc(sizeof(*new_fltr
), GFP_ATOMIC
);
7100 fkeys
= &new_fltr
->fkeys
;
7101 if (!skb_flow_dissect_flow_keys(skb
, fkeys
, 0)) {
7102 rc
= -EPROTONOSUPPORT
;
7106 if ((fkeys
->basic
.n_proto
!= htons(ETH_P_IP
) &&
7107 fkeys
->basic
.n_proto
!= htons(ETH_P_IPV6
)) ||
7108 ((fkeys
->basic
.ip_proto
!= IPPROTO_TCP
) &&
7109 (fkeys
->basic
.ip_proto
!= IPPROTO_UDP
))) {
7110 rc
= -EPROTONOSUPPORT
;
7113 if (fkeys
->basic
.n_proto
== htons(ETH_P_IPV6
) &&
7114 bp
->hwrm_spec_code
< 0x10601) {
7115 rc
= -EPROTONOSUPPORT
;
7118 if ((fkeys
->control
.flags
& FLOW_DIS_ENCAPSULATION
) &&
7119 bp
->hwrm_spec_code
< 0x10601) {
7120 rc
= -EPROTONOSUPPORT
;
7124 memcpy(new_fltr
->dst_mac_addr
, eth
->h_dest
, ETH_ALEN
);
7125 memcpy(new_fltr
->src_mac_addr
, eth
->h_source
, ETH_ALEN
);
7127 idx
= skb_get_hash_raw(skb
) & BNXT_NTP_FLTR_HASH_MASK
;
7128 head
= &bp
->ntp_fltr_hash_tbl
[idx
];
7130 hlist_for_each_entry_rcu(fltr
, head
, hash
) {
7131 if (bnxt_fltr_match(fltr
, new_fltr
)) {
7139 spin_lock_bh(&bp
->ntp_fltr_lock
);
7140 bit_id
= bitmap_find_free_region(bp
->ntp_fltr_bmap
,
7141 BNXT_NTP_FLTR_MAX_FLTR
, 0);
7143 spin_unlock_bh(&bp
->ntp_fltr_lock
);
7148 new_fltr
->sw_id
= (u16
)bit_id
;
7149 new_fltr
->flow_id
= flow_id
;
7150 new_fltr
->l2_fltr_idx
= l2_idx
;
7151 new_fltr
->rxq
= rxq_index
;
7152 hlist_add_head_rcu(&new_fltr
->hash
, head
);
7153 bp
->ntp_fltr_count
++;
7154 spin_unlock_bh(&bp
->ntp_fltr_lock
);
7156 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT
, &bp
->sp_event
);
7157 schedule_work(&bp
->sp_task
);
7159 return new_fltr
->sw_id
;
7166 static void bnxt_cfg_ntp_filters(struct bnxt
*bp
)
7170 for (i
= 0; i
< BNXT_NTP_FLTR_HASH_SIZE
; i
++) {
7171 struct hlist_head
*head
;
7172 struct hlist_node
*tmp
;
7173 struct bnxt_ntuple_filter
*fltr
;
7176 head
= &bp
->ntp_fltr_hash_tbl
[i
];
7177 hlist_for_each_entry_safe(fltr
, tmp
, head
, hash
) {
7180 if (test_bit(BNXT_FLTR_VALID
, &fltr
->state
)) {
7181 if (rps_may_expire_flow(bp
->dev
, fltr
->rxq
,
7184 bnxt_hwrm_cfa_ntuple_filter_free(bp
,
7189 rc
= bnxt_hwrm_cfa_ntuple_filter_alloc(bp
,
7194 set_bit(BNXT_FLTR_VALID
, &fltr
->state
);
7198 spin_lock_bh(&bp
->ntp_fltr_lock
);
7199 hlist_del_rcu(&fltr
->hash
);
7200 bp
->ntp_fltr_count
--;
7201 spin_unlock_bh(&bp
->ntp_fltr_lock
);
7203 clear_bit(fltr
->sw_id
, bp
->ntp_fltr_bmap
);
7208 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT
, &bp
->sp_event
))
7209 netdev_info(bp
->dev
, "Receive PF driver unload event!");
7214 static void bnxt_cfg_ntp_filters(struct bnxt
*bp
)
7218 #endif /* CONFIG_RFS_ACCEL */
7220 static void bnxt_udp_tunnel_add(struct net_device
*dev
,
7221 struct udp_tunnel_info
*ti
)
7223 struct bnxt
*bp
= netdev_priv(dev
);
7225 if (ti
->sa_family
!= AF_INET6
&& ti
->sa_family
!= AF_INET
)
7228 if (!netif_running(dev
))
7232 case UDP_TUNNEL_TYPE_VXLAN
:
7233 if (bp
->vxlan_port_cnt
&& bp
->vxlan_port
!= ti
->port
)
7236 bp
->vxlan_port_cnt
++;
7237 if (bp
->vxlan_port_cnt
== 1) {
7238 bp
->vxlan_port
= ti
->port
;
7239 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT
, &bp
->sp_event
);
7240 schedule_work(&bp
->sp_task
);
7243 case UDP_TUNNEL_TYPE_GENEVE
:
7244 if (bp
->nge_port_cnt
&& bp
->nge_port
!= ti
->port
)
7248 if (bp
->nge_port_cnt
== 1) {
7249 bp
->nge_port
= ti
->port
;
7250 set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT
, &bp
->sp_event
);
7257 schedule_work(&bp
->sp_task
);
7260 static void bnxt_udp_tunnel_del(struct net_device
*dev
,
7261 struct udp_tunnel_info
*ti
)
7263 struct bnxt
*bp
= netdev_priv(dev
);
7265 if (ti
->sa_family
!= AF_INET6
&& ti
->sa_family
!= AF_INET
)
7268 if (!netif_running(dev
))
7272 case UDP_TUNNEL_TYPE_VXLAN
:
7273 if (!bp
->vxlan_port_cnt
|| bp
->vxlan_port
!= ti
->port
)
7275 bp
->vxlan_port_cnt
--;
7277 if (bp
->vxlan_port_cnt
!= 0)
7280 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT
, &bp
->sp_event
);
7282 case UDP_TUNNEL_TYPE_GENEVE
:
7283 if (!bp
->nge_port_cnt
|| bp
->nge_port
!= ti
->port
)
7287 if (bp
->nge_port_cnt
!= 0)
7290 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT
, &bp
->sp_event
);
7296 schedule_work(&bp
->sp_task
);
7299 static const struct net_device_ops bnxt_netdev_ops
= {
7300 .ndo_open
= bnxt_open
,
7301 .ndo_start_xmit
= bnxt_start_xmit
,
7302 .ndo_stop
= bnxt_close
,
7303 .ndo_get_stats64
= bnxt_get_stats64
,
7304 .ndo_set_rx_mode
= bnxt_set_rx_mode
,
7305 .ndo_do_ioctl
= bnxt_ioctl
,
7306 .ndo_validate_addr
= eth_validate_addr
,
7307 .ndo_set_mac_address
= bnxt_change_mac_addr
,
7308 .ndo_change_mtu
= bnxt_change_mtu
,
7309 .ndo_fix_features
= bnxt_fix_features
,
7310 .ndo_set_features
= bnxt_set_features
,
7311 .ndo_tx_timeout
= bnxt_tx_timeout
,
7312 #ifdef CONFIG_BNXT_SRIOV
7313 .ndo_get_vf_config
= bnxt_get_vf_config
,
7314 .ndo_set_vf_mac
= bnxt_set_vf_mac
,
7315 .ndo_set_vf_vlan
= bnxt_set_vf_vlan
,
7316 .ndo_set_vf_rate
= bnxt_set_vf_bw
,
7317 .ndo_set_vf_link_state
= bnxt_set_vf_link_state
,
7318 .ndo_set_vf_spoofchk
= bnxt_set_vf_spoofchk
,
7320 #ifdef CONFIG_NET_POLL_CONTROLLER
7321 .ndo_poll_controller
= bnxt_poll_controller
,
7323 .ndo_setup_tc
= bnxt_setup_tc
,
7324 #ifdef CONFIG_RFS_ACCEL
7325 .ndo_rx_flow_steer
= bnxt_rx_flow_steer
,
7327 .ndo_udp_tunnel_add
= bnxt_udp_tunnel_add
,
7328 .ndo_udp_tunnel_del
= bnxt_udp_tunnel_del
,
7329 .ndo_xdp
= bnxt_xdp
,
7332 static void bnxt_remove_one(struct pci_dev
*pdev
)
7334 struct net_device
*dev
= pci_get_drvdata(pdev
);
7335 struct bnxt
*bp
= netdev_priv(dev
);
7338 bnxt_sriov_disable(bp
);
7340 pci_disable_pcie_error_reporting(pdev
);
7341 unregister_netdev(dev
);
7342 cancel_work_sync(&bp
->sp_task
);
7345 bnxt_clear_int_mode(bp
);
7346 bnxt_hwrm_func_drv_unrgtr(bp
);
7347 bnxt_free_hwrm_resources(bp
);
7348 bnxt_ethtool_free(bp
);
7353 bpf_prog_put(bp
->xdp_prog
);
7354 bnxt_cleanup_pci(bp
);
7358 static int bnxt_probe_phy(struct bnxt
*bp
)
7361 struct bnxt_link_info
*link_info
= &bp
->link_info
;
7363 rc
= bnxt_hwrm_phy_qcaps(bp
);
7365 netdev_err(bp
->dev
, "Probe phy can't get phy capabilities (rc: %x)\n",
7370 rc
= bnxt_update_link(bp
, false);
7372 netdev_err(bp
->dev
, "Probe phy can't update link (rc: %x)\n",
7377 /* Older firmware does not have supported_auto_speeds, so assume
7378 * that all supported speeds can be autonegotiated.
7380 if (link_info
->auto_link_speeds
&& !link_info
->support_auto_speeds
)
7381 link_info
->support_auto_speeds
= link_info
->support_speeds
;
7383 /*initialize the ethool setting copy with NVM settings */
7384 if (BNXT_AUTO_MODE(link_info
->auto_mode
)) {
7385 link_info
->autoneg
= BNXT_AUTONEG_SPEED
;
7386 if (bp
->hwrm_spec_code
>= 0x10201) {
7387 if (link_info
->auto_pause_setting
&
7388 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE
)
7389 link_info
->autoneg
|= BNXT_AUTONEG_FLOW_CTRL
;
7391 link_info
->autoneg
|= BNXT_AUTONEG_FLOW_CTRL
;
7393 link_info
->advertising
= link_info
->auto_link_speeds
;
7395 link_info
->req_link_speed
= link_info
->force_link_speed
;
7396 link_info
->req_duplex
= link_info
->duplex_setting
;
7398 if (link_info
->autoneg
& BNXT_AUTONEG_FLOW_CTRL
)
7399 link_info
->req_flow_ctrl
=
7400 link_info
->auto_pause_setting
& BNXT_LINK_PAUSE_BOTH
;
7402 link_info
->req_flow_ctrl
= link_info
->force_pause_setting
;
7406 static int bnxt_get_max_irq(struct pci_dev
*pdev
)
7410 if (!pdev
->msix_cap
)
7413 pci_read_config_word(pdev
, pdev
->msix_cap
+ PCI_MSIX_FLAGS
, &ctrl
);
7414 return (ctrl
& PCI_MSIX_FLAGS_QSIZE
) + 1;
7417 static void _bnxt_get_max_rings(struct bnxt
*bp
, int *max_rx
, int *max_tx
,
7420 int max_ring_grps
= 0;
7422 #ifdef CONFIG_BNXT_SRIOV
7424 *max_tx
= bp
->vf
.max_tx_rings
;
7425 *max_rx
= bp
->vf
.max_rx_rings
;
7426 *max_cp
= min_t(int, bp
->vf
.max_irqs
, bp
->vf
.max_cp_rings
);
7427 *max_cp
= min_t(int, *max_cp
, bp
->vf
.max_stat_ctxs
);
7428 max_ring_grps
= bp
->vf
.max_hw_ring_grps
;
7432 *max_tx
= bp
->pf
.max_tx_rings
;
7433 *max_rx
= bp
->pf
.max_rx_rings
;
7434 *max_cp
= min_t(int, bp
->pf
.max_irqs
, bp
->pf
.max_cp_rings
);
7435 *max_cp
= min_t(int, *max_cp
, bp
->pf
.max_stat_ctxs
);
7436 max_ring_grps
= bp
->pf
.max_hw_ring_grps
;
7438 if (BNXT_CHIP_TYPE_NITRO_A0(bp
) && BNXT_PF(bp
)) {
7442 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
)
7444 *max_rx
= min_t(int, *max_rx
, max_ring_grps
);
7447 int bnxt_get_max_rings(struct bnxt
*bp
, int *max_rx
, int *max_tx
, bool shared
)
7451 _bnxt_get_max_rings(bp
, &rx
, &tx
, &cp
);
7452 if (!rx
|| !tx
|| !cp
)
7457 return bnxt_trim_rings(bp
, max_rx
, max_tx
, cp
, shared
);
7460 static int bnxt_get_dflt_rings(struct bnxt
*bp
, int *max_rx
, int *max_tx
,
7465 rc
= bnxt_get_max_rings(bp
, max_rx
, max_tx
, shared
);
7466 if (rc
&& (bp
->flags
& BNXT_FLAG_AGG_RINGS
)) {
7467 /* Not enough rings, try disabling agg rings. */
7468 bp
->flags
&= ~BNXT_FLAG_AGG_RINGS
;
7469 rc
= bnxt_get_max_rings(bp
, max_rx
, max_tx
, shared
);
7472 bp
->flags
|= BNXT_FLAG_NO_AGG_RINGS
;
7473 bp
->dev
->hw_features
&= ~NETIF_F_LRO
;
7474 bp
->dev
->features
&= ~NETIF_F_LRO
;
7475 bnxt_set_ring_params(bp
);
7478 if (bp
->flags
& BNXT_FLAG_ROCE_CAP
) {
7479 int max_cp
, max_stat
, max_irq
;
7481 /* Reserve minimum resources for RoCE */
7482 max_cp
= bnxt_get_max_func_cp_rings(bp
);
7483 max_stat
= bnxt_get_max_func_stat_ctxs(bp
);
7484 max_irq
= bnxt_get_max_func_irqs(bp
);
7485 if (max_cp
<= BNXT_MIN_ROCE_CP_RINGS
||
7486 max_irq
<= BNXT_MIN_ROCE_CP_RINGS
||
7487 max_stat
<= BNXT_MIN_ROCE_STAT_CTXS
)
7490 max_cp
-= BNXT_MIN_ROCE_CP_RINGS
;
7491 max_irq
-= BNXT_MIN_ROCE_CP_RINGS
;
7492 max_stat
-= BNXT_MIN_ROCE_STAT_CTXS
;
7493 max_cp
= min_t(int, max_cp
, max_irq
);
7494 max_cp
= min_t(int, max_cp
, max_stat
);
7495 rc
= bnxt_trim_rings(bp
, max_rx
, max_tx
, max_cp
, shared
);
7502 static int bnxt_set_dflt_rings(struct bnxt
*bp
)
7504 int dflt_rings
, max_rx_rings
, max_tx_rings
, rc
;
7508 bp
->flags
|= BNXT_FLAG_SHARED_RINGS
;
7509 dflt_rings
= netif_get_num_default_rss_queues();
7510 rc
= bnxt_get_dflt_rings(bp
, &max_rx_rings
, &max_tx_rings
, sh
);
7513 bp
->rx_nr_rings
= min_t(int, dflt_rings
, max_rx_rings
);
7514 bp
->tx_nr_rings_per_tc
= min_t(int, dflt_rings
, max_tx_rings
);
7516 rc
= bnxt_hwrm_reserve_tx_rings(bp
, &bp
->tx_nr_rings_per_tc
);
7518 netdev_warn(bp
->dev
, "Unable to reserve tx rings\n");
7520 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
;
7521 bp
->cp_nr_rings
= sh
? max_t(int, bp
->tx_nr_rings
, bp
->rx_nr_rings
) :
7522 bp
->tx_nr_rings
+ bp
->rx_nr_rings
;
7523 bp
->num_stat_ctxs
= bp
->cp_nr_rings
;
7524 if (BNXT_CHIP_TYPE_NITRO_A0(bp
)) {
7531 void bnxt_restore_pf_fw_resources(struct bnxt
*bp
)
7534 bnxt_hwrm_func_qcaps(bp
);
7535 bnxt_subtract_ulp_resources(bp
, BNXT_ROCE_ULP
);
7538 static void bnxt_parse_log_pcie_link(struct bnxt
*bp
)
7540 enum pcie_link_width width
= PCIE_LNK_WIDTH_UNKNOWN
;
7541 enum pci_bus_speed speed
= PCI_SPEED_UNKNOWN
;
7543 if (pcie_get_minimum_link(bp
->pdev
, &speed
, &width
) ||
7544 speed
== PCI_SPEED_UNKNOWN
|| width
== PCIE_LNK_WIDTH_UNKNOWN
)
7545 netdev_info(bp
->dev
, "Failed to determine PCIe Link Info\n");
7547 netdev_info(bp
->dev
, "PCIe: Speed %s Width x%d\n",
7548 speed
== PCIE_SPEED_2_5GT
? "2.5GT/s" :
7549 speed
== PCIE_SPEED_5_0GT
? "5.0GT/s" :
7550 speed
== PCIE_SPEED_8_0GT
? "8.0GT/s" :
7554 static int bnxt_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
7556 static int version_printed
;
7557 struct net_device
*dev
;
7561 if (pci_is_bridge(pdev
))
7564 if (version_printed
++ == 0)
7565 pr_info("%s", version
);
7567 max_irqs
= bnxt_get_max_irq(pdev
);
7568 dev
= alloc_etherdev_mq(sizeof(*bp
), max_irqs
);
7572 bp
= netdev_priv(dev
);
7574 if (bnxt_vf_pciid(ent
->driver_data
))
7575 bp
->flags
|= BNXT_FLAG_VF
;
7578 bp
->flags
|= BNXT_FLAG_MSIX_CAP
;
7580 rc
= bnxt_init_board(pdev
, dev
);
7584 dev
->netdev_ops
= &bnxt_netdev_ops
;
7585 dev
->watchdog_timeo
= BNXT_TX_TIMEOUT
;
7586 dev
->ethtool_ops
= &bnxt_ethtool_ops
;
7587 pci_set_drvdata(pdev
, dev
);
7589 rc
= bnxt_alloc_hwrm_resources(bp
);
7591 goto init_err_pci_clean
;
7593 mutex_init(&bp
->hwrm_cmd_lock
);
7594 rc
= bnxt_hwrm_ver_get(bp
);
7596 goto init_err_pci_clean
;
7598 rc
= bnxt_hwrm_func_reset(bp
);
7600 goto init_err_pci_clean
;
7602 bnxt_hwrm_fw_set_time(bp
);
7604 dev
->hw_features
= NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
| NETIF_F_SG
|
7605 NETIF_F_TSO
| NETIF_F_TSO6
|
7606 NETIF_F_GSO_UDP_TUNNEL
| NETIF_F_GSO_GRE
|
7607 NETIF_F_GSO_IPXIP4
|
7608 NETIF_F_GSO_UDP_TUNNEL_CSUM
| NETIF_F_GSO_GRE_CSUM
|
7609 NETIF_F_GSO_PARTIAL
| NETIF_F_RXHASH
|
7610 NETIF_F_RXCSUM
| NETIF_F_GRO
;
7612 if (!BNXT_CHIP_TYPE_NITRO_A0(bp
))
7613 dev
->hw_features
|= NETIF_F_LRO
;
7615 dev
->hw_enc_features
=
7616 NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
| NETIF_F_SG
|
7617 NETIF_F_TSO
| NETIF_F_TSO6
|
7618 NETIF_F_GSO_UDP_TUNNEL
| NETIF_F_GSO_GRE
|
7619 NETIF_F_GSO_UDP_TUNNEL_CSUM
| NETIF_F_GSO_GRE_CSUM
|
7620 NETIF_F_GSO_IPXIP4
| NETIF_F_GSO_PARTIAL
;
7621 dev
->gso_partial_features
= NETIF_F_GSO_UDP_TUNNEL_CSUM
|
7622 NETIF_F_GSO_GRE_CSUM
;
7623 dev
->vlan_features
= dev
->hw_features
| NETIF_F_HIGHDMA
;
7624 dev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_RX
| NETIF_F_HW_VLAN_CTAG_TX
|
7625 NETIF_F_HW_VLAN_STAG_RX
| NETIF_F_HW_VLAN_STAG_TX
;
7626 dev
->features
|= dev
->hw_features
| NETIF_F_HIGHDMA
;
7627 dev
->priv_flags
|= IFF_UNICAST_FLT
;
7629 /* MTU range: 60 - 9500 */
7630 dev
->min_mtu
= ETH_ZLEN
;
7631 dev
->max_mtu
= BNXT_MAX_MTU
;
7635 #ifdef CONFIG_BNXT_SRIOV
7636 init_waitqueue_head(&bp
->sriov_cfg_wait
);
7638 bp
->gro_func
= bnxt_gro_func_5730x
;
7639 if (BNXT_CHIP_NUM_57X1X(bp
->chip_num
))
7640 bp
->gro_func
= bnxt_gro_func_5731x
;
7642 rc
= bnxt_hwrm_func_drv_rgtr(bp
);
7644 goto init_err_pci_clean
;
7646 rc
= bnxt_hwrm_func_rgtr_async_events(bp
, NULL
, 0);
7648 goto init_err_pci_clean
;
7650 bp
->ulp_probe
= bnxt_ulp_probe
;
7652 /* Get the MAX capabilities for this function */
7653 rc
= bnxt_hwrm_func_qcaps(bp
);
7655 netdev_err(bp
->dev
, "hwrm query capability failure rc: %x\n",
7658 goto init_err_pci_clean
;
7661 rc
= bnxt_hwrm_queue_qportcfg(bp
);
7663 netdev_err(bp
->dev
, "hwrm query qportcfg failure rc: %x\n",
7666 goto init_err_pci_clean
;
7669 bnxt_hwrm_func_qcfg(bp
);
7670 bnxt_hwrm_port_led_qcaps(bp
);
7671 bnxt_ethtool_init(bp
);
7673 bnxt_set_rx_skb_mode(bp
, false);
7674 bnxt_set_tpa_flags(bp
);
7675 bnxt_set_ring_params(bp
);
7676 bnxt_set_max_func_irqs(bp
, max_irqs
);
7677 rc
= bnxt_set_dflt_rings(bp
);
7679 netdev_err(bp
->dev
, "Not enough rings available.\n");
7681 goto init_err_pci_clean
;
7684 /* Default RSS hash cfg. */
7685 bp
->rss_hash_cfg
= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4
|
7686 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4
|
7687 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6
|
7688 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6
;
7689 if (!BNXT_CHIP_NUM_57X0X(bp
->chip_num
) &&
7690 !BNXT_CHIP_TYPE_NITRO_A0(bp
) &&
7691 bp
->hwrm_spec_code
>= 0x10501) {
7692 bp
->flags
|= BNXT_FLAG_UDP_RSS_CAP
;
7693 bp
->rss_hash_cfg
|= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4
|
7694 VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6
;
7697 bnxt_hwrm_vnic_qcaps(bp
);
7698 if (bnxt_rfs_supported(bp
)) {
7699 dev
->hw_features
|= NETIF_F_NTUPLE
;
7700 if (bnxt_rfs_capable(bp
)) {
7701 bp
->flags
|= BNXT_FLAG_RFS
;
7702 dev
->features
|= NETIF_F_NTUPLE
;
7706 if (dev
->hw_features
& NETIF_F_HW_VLAN_CTAG_RX
)
7707 bp
->flags
|= BNXT_FLAG_STRIP_VLAN
;
7709 rc
= bnxt_probe_phy(bp
);
7711 goto init_err_pci_clean
;
7713 rc
= bnxt_init_int_mode(bp
);
7715 goto init_err_pci_clean
;
7717 bnxt_get_wol_settings(bp
);
7718 if (bp
->flags
& BNXT_FLAG_WOL_CAP
)
7719 device_set_wakeup_enable(&pdev
->dev
, bp
->wol
);
7721 device_set_wakeup_capable(&pdev
->dev
, false);
7723 rc
= register_netdev(dev
);
7725 goto init_err_clr_int
;
7727 netdev_info(dev
, "%s found at mem %lx, node addr %pM\n",
7728 board_info
[ent
->driver_data
].name
,
7729 (long)pci_resource_start(pdev
, 0), dev
->dev_addr
);
7731 bnxt_parse_log_pcie_link(bp
);
7736 bnxt_clear_int_mode(bp
);
7739 bnxt_cleanup_pci(bp
);
7746 static void bnxt_shutdown(struct pci_dev
*pdev
)
7748 struct net_device
*dev
= pci_get_drvdata(pdev
);
7755 bp
= netdev_priv(dev
);
7759 if (netif_running(dev
))
7762 if (system_state
== SYSTEM_POWER_OFF
) {
7763 bnxt_clear_int_mode(bp
);
7764 pci_wake_from_d3(pdev
, bp
->wol
);
7765 pci_set_power_state(pdev
, PCI_D3hot
);
7772 #ifdef CONFIG_PM_SLEEP
7773 static int bnxt_suspend(struct device
*device
)
7775 struct pci_dev
*pdev
= to_pci_dev(device
);
7776 struct net_device
*dev
= pci_get_drvdata(pdev
);
7777 struct bnxt
*bp
= netdev_priv(dev
);
7781 if (netif_running(dev
)) {
7782 netif_device_detach(dev
);
7783 rc
= bnxt_close(dev
);
7785 bnxt_hwrm_func_drv_unrgtr(bp
);
7790 static int bnxt_resume(struct device
*device
)
7792 struct pci_dev
*pdev
= to_pci_dev(device
);
7793 struct net_device
*dev
= pci_get_drvdata(pdev
);
7794 struct bnxt
*bp
= netdev_priv(dev
);
7798 if (bnxt_hwrm_ver_get(bp
) || bnxt_hwrm_func_drv_rgtr(bp
)) {
7802 rc
= bnxt_hwrm_func_reset(bp
);
7807 bnxt_get_wol_settings(bp
);
7808 if (netif_running(dev
)) {
7809 rc
= bnxt_open(dev
);
7811 netif_device_attach(dev
);
7819 static SIMPLE_DEV_PM_OPS(bnxt_pm_ops
, bnxt_suspend
, bnxt_resume
);
7820 #define BNXT_PM_OPS (&bnxt_pm_ops)
7824 #define BNXT_PM_OPS NULL
7826 #endif /* CONFIG_PM_SLEEP */
7829 * bnxt_io_error_detected - called when PCI error is detected
7830 * @pdev: Pointer to PCI device
7831 * @state: The current pci connection state
7833 * This function is called after a PCI bus error affecting
7834 * this device has been detected.
7836 static pci_ers_result_t
bnxt_io_error_detected(struct pci_dev
*pdev
,
7837 pci_channel_state_t state
)
7839 struct net_device
*netdev
= pci_get_drvdata(pdev
);
7840 struct bnxt
*bp
= netdev_priv(netdev
);
7842 netdev_info(netdev
, "PCI I/O error detected\n");
7845 netif_device_detach(netdev
);
7849 if (state
== pci_channel_io_perm_failure
) {
7851 return PCI_ERS_RESULT_DISCONNECT
;
7854 if (netif_running(netdev
))
7857 pci_disable_device(pdev
);
7860 /* Request a slot slot reset. */
7861 return PCI_ERS_RESULT_NEED_RESET
;
7865 * bnxt_io_slot_reset - called after the pci bus has been reset.
7866 * @pdev: Pointer to PCI device
7868 * Restart the card from scratch, as if from a cold-boot.
7869 * At this point, the card has exprienced a hard reset,
7870 * followed by fixups by BIOS, and has its config space
7871 * set up identically to what it was at cold boot.
7873 static pci_ers_result_t
bnxt_io_slot_reset(struct pci_dev
*pdev
)
7875 struct net_device
*netdev
= pci_get_drvdata(pdev
);
7876 struct bnxt
*bp
= netdev_priv(netdev
);
7878 pci_ers_result_t result
= PCI_ERS_RESULT_DISCONNECT
;
7880 netdev_info(bp
->dev
, "PCI Slot Reset\n");
7884 if (pci_enable_device(pdev
)) {
7886 "Cannot re-enable PCI device after reset.\n");
7888 pci_set_master(pdev
);
7890 err
= bnxt_hwrm_func_reset(bp
);
7891 if (!err
&& netif_running(netdev
))
7892 err
= bnxt_open(netdev
);
7895 result
= PCI_ERS_RESULT_RECOVERED
;
7900 if (result
!= PCI_ERS_RESULT_RECOVERED
&& netif_running(netdev
))
7905 err
= pci_cleanup_aer_uncorrect_error_status(pdev
);
7908 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7909 err
); /* non-fatal, continue */
7912 return PCI_ERS_RESULT_RECOVERED
;
7916 * bnxt_io_resume - called when traffic can start flowing again.
7917 * @pdev: Pointer to PCI device
7919 * This callback is called when the error recovery driver tells
7920 * us that its OK to resume normal operation.
7922 static void bnxt_io_resume(struct pci_dev
*pdev
)
7924 struct net_device
*netdev
= pci_get_drvdata(pdev
);
7928 netif_device_attach(netdev
);
7933 static const struct pci_error_handlers bnxt_err_handler
= {
7934 .error_detected
= bnxt_io_error_detected
,
7935 .slot_reset
= bnxt_io_slot_reset
,
7936 .resume
= bnxt_io_resume
7939 static struct pci_driver bnxt_pci_driver
= {
7940 .name
= DRV_MODULE_NAME
,
7941 .id_table
= bnxt_pci_tbl
,
7942 .probe
= bnxt_init_one
,
7943 .remove
= bnxt_remove_one
,
7944 .shutdown
= bnxt_shutdown
,
7945 .driver
.pm
= BNXT_PM_OPS
,
7946 .err_handler
= &bnxt_err_handler
,
7947 #if defined(CONFIG_BNXT_SRIOV)
7948 .sriov_configure
= bnxt_sriov_configure
,
7952 module_pci_driver(bnxt_pci_driver
);