1 /* Broadcom NetXtreme-C/E network driver.
3 * Copyright (c) 2014-2016 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
10 #include <linux/module.h>
12 #include <linux/stringify.h>
13 #include <linux/kernel.h>
14 #include <linux/timer.h>
15 #include <linux/errno.h>
16 #include <linux/ioport.h>
17 #include <linux/slab.h>
18 #include <linux/vmalloc.h>
19 #include <linux/interrupt.h>
20 #include <linux/pci.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23 #include <linux/skbuff.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/bitops.h>
27 #include <linux/irq.h>
28 #include <linux/delay.h>
29 #include <asm/byteorder.h>
31 #include <linux/time.h>
32 #include <linux/mii.h>
34 #include <linux/if_vlan.h>
38 #include <net/checksum.h>
39 #include <net/ip6_checksum.h>
40 #include <net/udp_tunnel.h>
41 #ifdef CONFIG_NET_RX_BUSY_POLL
42 #include <net/busy_poll.h>
44 #include <linux/workqueue.h>
45 #include <linux/prefetch.h>
46 #include <linux/cache.h>
47 #include <linux/log2.h>
48 #include <linux/aer.h>
49 #include <linux/bitmap.h>
50 #include <linux/cpu_rmap.h>
54 #include "bnxt_sriov.h"
55 #include "bnxt_ethtool.h"
57 #define BNXT_TX_TIMEOUT (5 * HZ)
59 static const char version
[] =
60 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME
" v" DRV_MODULE_VERSION
"\n";
62 MODULE_LICENSE("GPL");
63 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
64 MODULE_VERSION(DRV_MODULE_VERSION
);
66 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
67 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
68 #define BNXT_RX_COPY_THRESH 256
70 #define BNXT_TX_PUSH_THRESH 164
94 /* indexed by enum above */
98 { "Broadcom BCM57301 NetXtreme-C Single-port 10Gb Ethernet" },
99 { "Broadcom BCM57302 NetXtreme-C Dual-port 10Gb/25Gb Ethernet" },
100 { "Broadcom BCM57304 NetXtreme-C Dual-port 10Gb/25Gb/40Gb/50Gb Ethernet" },
101 { "Broadcom BCM57311 NetXtreme-C Single-port 10Gb Ethernet" },
102 { "Broadcom BCM57312 NetXtreme-C Dual-port 10Gb/25Gb Ethernet" },
103 { "Broadcom BCM57402 NetXtreme-E Dual-port 10Gb Ethernet" },
104 { "Broadcom BCM57404 NetXtreme-E Dual-port 10Gb/25Gb Ethernet" },
105 { "Broadcom BCM57406 NetXtreme-E Dual-port 10GBase-T Ethernet" },
106 { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
107 { "Broadcom BCM57412 NetXtreme-E Dual-port 10Gb Ethernet" },
108 { "Broadcom BCM57414 NetXtreme-E Dual-port 10Gb/25Gb Ethernet" },
109 { "Broadcom BCM57416 NetXtreme-E Dual-port 10GBase-T Ethernet" },
110 { "Broadcom BCM57417 NetXtreme-E Dual-port 10GBase-T Ethernet" },
111 { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
112 { "Broadcom BCM57314 NetXtreme-C Dual-port 10Gb/25Gb/40Gb/50Gb Ethernet" },
113 { "Broadcom BCM57304 NetXtreme-C Ethernet Virtual Function" },
114 { "Broadcom BCM57404 NetXtreme-E Ethernet Virtual Function" },
115 { "Broadcom BCM57414 NetXtreme-E Ethernet Virtual Function" },
116 { "Broadcom BCM57314 NetXtreme-E Ethernet Virtual Function" },
119 static const struct pci_device_id bnxt_pci_tbl
[] = {
120 { PCI_VDEVICE(BROADCOM
, 0x16c8), .driver_data
= BCM57301
},
121 { PCI_VDEVICE(BROADCOM
, 0x16c9), .driver_data
= BCM57302
},
122 { PCI_VDEVICE(BROADCOM
, 0x16ca), .driver_data
= BCM57304
},
123 { PCI_VDEVICE(BROADCOM
, 0x16ce), .driver_data
= BCM57311
},
124 { PCI_VDEVICE(BROADCOM
, 0x16cf), .driver_data
= BCM57312
},
125 { PCI_VDEVICE(BROADCOM
, 0x16d0), .driver_data
= BCM57402
},
126 { PCI_VDEVICE(BROADCOM
, 0x16d1), .driver_data
= BCM57404
},
127 { PCI_VDEVICE(BROADCOM
, 0x16d2), .driver_data
= BCM57406
},
128 { PCI_VDEVICE(BROADCOM
, 0x16d4), .driver_data
= BCM57404_NPAR
},
129 { PCI_VDEVICE(BROADCOM
, 0x16d6), .driver_data
= BCM57412
},
130 { PCI_VDEVICE(BROADCOM
, 0x16d7), .driver_data
= BCM57414
},
131 { PCI_VDEVICE(BROADCOM
, 0x16d8), .driver_data
= BCM57416
},
132 { PCI_VDEVICE(BROADCOM
, 0x16d9), .driver_data
= BCM57417
},
133 { PCI_VDEVICE(BROADCOM
, 0x16de), .driver_data
= BCM57414_NPAR
},
134 { PCI_VDEVICE(BROADCOM
, 0x16df), .driver_data
= BCM57314
},
135 #ifdef CONFIG_BNXT_SRIOV
136 { PCI_VDEVICE(BROADCOM
, 0x16cb), .driver_data
= BCM57304_VF
},
137 { PCI_VDEVICE(BROADCOM
, 0x16d3), .driver_data
= BCM57404_VF
},
138 { PCI_VDEVICE(BROADCOM
, 0x16dc), .driver_data
= BCM57414_VF
},
139 { PCI_VDEVICE(BROADCOM
, 0x16e1), .driver_data
= BCM57314_VF
},
144 MODULE_DEVICE_TABLE(pci
, bnxt_pci_tbl
);
146 static const u16 bnxt_vf_req_snif
[] = {
149 HWRM_CFA_L2_FILTER_ALLOC
,
152 static const u16 bnxt_async_events_arr
[] = {
153 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE
,
154 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD
,
155 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED
,
156 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE
,
157 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE
,
160 static bool bnxt_vf_pciid(enum board_idx idx
)
162 return (idx
== BCM57304_VF
|| idx
== BCM57404_VF
||
163 idx
== BCM57314_VF
|| idx
== BCM57414_VF
);
166 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
167 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
168 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
170 #define BNXT_CP_DB_REARM(db, raw_cons) \
171 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
173 #define BNXT_CP_DB(db, raw_cons) \
174 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
176 #define BNXT_CP_DB_IRQ_DIS(db) \
177 writel(DB_CP_IRQ_DIS_FLAGS, db)
179 static inline u32
bnxt_tx_avail(struct bnxt
*bp
, struct bnxt_tx_ring_info
*txr
)
181 /* Tell compiler to fetch tx indices from memory. */
184 return bp
->tx_ring_size
-
185 ((txr
->tx_prod
- txr
->tx_cons
) & bp
->tx_ring_mask
);
188 static const u16 bnxt_lhint_arr
[] = {
189 TX_BD_FLAGS_LHINT_512_AND_SMALLER
,
190 TX_BD_FLAGS_LHINT_512_TO_1023
,
191 TX_BD_FLAGS_LHINT_1024_TO_2047
,
192 TX_BD_FLAGS_LHINT_1024_TO_2047
,
193 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
194 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
195 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
196 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
197 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
198 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
199 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
200 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
201 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
202 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
203 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
204 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
205 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
206 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
207 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
210 static netdev_tx_t
bnxt_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
212 struct bnxt
*bp
= netdev_priv(dev
);
214 struct tx_bd_ext
*txbd1
;
215 struct netdev_queue
*txq
;
218 unsigned int length
, pad
= 0;
219 u32 len
, free_size
, vlan_tag_flags
, cfa_action
, flags
;
221 struct pci_dev
*pdev
= bp
->pdev
;
222 struct bnxt_tx_ring_info
*txr
;
223 struct bnxt_sw_tx_bd
*tx_buf
;
225 i
= skb_get_queue_mapping(skb
);
226 if (unlikely(i
>= bp
->tx_nr_rings
)) {
227 dev_kfree_skb_any(skb
);
231 txr
= &bp
->tx_ring
[i
];
232 txq
= netdev_get_tx_queue(dev
, i
);
235 free_size
= bnxt_tx_avail(bp
, txr
);
236 if (unlikely(free_size
< skb_shinfo(skb
)->nr_frags
+ 2)) {
237 netif_tx_stop_queue(txq
);
238 return NETDEV_TX_BUSY
;
242 len
= skb_headlen(skb
);
243 last_frag
= skb_shinfo(skb
)->nr_frags
;
245 txbd
= &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
247 txbd
->tx_bd_opaque
= prod
;
249 tx_buf
= &txr
->tx_buf_ring
[prod
];
251 tx_buf
->nr_frags
= last_frag
;
255 if (skb_vlan_tag_present(skb
)) {
256 vlan_tag_flags
= TX_BD_CFA_META_KEY_VLAN
|
257 skb_vlan_tag_get(skb
);
258 /* Currently supports 8021Q, 8021AD vlan offloads
259 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
261 if (skb
->vlan_proto
== htons(ETH_P_8021Q
))
262 vlan_tag_flags
|= 1 << TX_BD_CFA_META_TPID_SHIFT
;
265 if (free_size
== bp
->tx_ring_size
&& length
<= bp
->tx_push_thresh
) {
266 struct tx_push_buffer
*tx_push_buf
= txr
->tx_push
;
267 struct tx_push_bd
*tx_push
= &tx_push_buf
->push_bd
;
268 struct tx_bd_ext
*tx_push1
= &tx_push
->txbd2
;
269 void *pdata
= tx_push_buf
->data
;
273 /* Set COAL_NOW to be ready quickly for the next push */
274 tx_push
->tx_bd_len_flags_type
=
275 cpu_to_le32((length
<< TX_BD_LEN_SHIFT
) |
276 TX_BD_TYPE_LONG_TX_BD
|
277 TX_BD_FLAGS_LHINT_512_AND_SMALLER
|
278 TX_BD_FLAGS_COAL_NOW
|
279 TX_BD_FLAGS_PACKET_END
|
280 (2 << TX_BD_FLAGS_BD_CNT_SHIFT
));
282 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
283 tx_push1
->tx_bd_hsize_lflags
=
284 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM
);
286 tx_push1
->tx_bd_hsize_lflags
= 0;
288 tx_push1
->tx_bd_cfa_meta
= cpu_to_le32(vlan_tag_flags
);
289 tx_push1
->tx_bd_cfa_action
= cpu_to_le32(cfa_action
);
291 end
= pdata
+ length
;
292 end
= PTR_ALIGN(end
, 8) - 1;
295 skb_copy_from_linear_data(skb
, pdata
, len
);
297 for (j
= 0; j
< last_frag
; j
++) {
298 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[j
];
301 fptr
= skb_frag_address_safe(frag
);
305 memcpy(pdata
, fptr
, skb_frag_size(frag
));
306 pdata
+= skb_frag_size(frag
);
309 txbd
->tx_bd_len_flags_type
= tx_push
->tx_bd_len_flags_type
;
310 txbd
->tx_bd_haddr
= txr
->data_mapping
;
311 prod
= NEXT_TX(prod
);
312 txbd
= &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
313 memcpy(txbd
, tx_push1
, sizeof(*txbd
));
314 prod
= NEXT_TX(prod
);
316 cpu_to_le32(DB_KEY_TX_PUSH
| DB_LONG_TX_PUSH
| prod
);
320 netdev_tx_sent_queue(txq
, skb
->len
);
321 wmb(); /* Sync is_push and byte queue before pushing data */
323 push_len
= (length
+ sizeof(*tx_push
) + 7) / 8;
325 __iowrite64_copy(txr
->tx_doorbell
, tx_push_buf
, 16);
326 __iowrite64_copy(txr
->tx_doorbell
+ 4, tx_push_buf
+ 1,
329 __iowrite64_copy(txr
->tx_doorbell
, tx_push_buf
,
337 if (length
< BNXT_MIN_PKT_SIZE
) {
338 pad
= BNXT_MIN_PKT_SIZE
- length
;
339 if (skb_pad(skb
, pad
)) {
340 /* SKB already freed. */
344 length
= BNXT_MIN_PKT_SIZE
;
347 mapping
= dma_map_single(&pdev
->dev
, skb
->data
, len
, DMA_TO_DEVICE
);
349 if (unlikely(dma_mapping_error(&pdev
->dev
, mapping
))) {
350 dev_kfree_skb_any(skb
);
355 dma_unmap_addr_set(tx_buf
, mapping
, mapping
);
356 flags
= (len
<< TX_BD_LEN_SHIFT
) | TX_BD_TYPE_LONG_TX_BD
|
357 ((last_frag
+ 2) << TX_BD_FLAGS_BD_CNT_SHIFT
);
359 txbd
->tx_bd_haddr
= cpu_to_le64(mapping
);
361 prod
= NEXT_TX(prod
);
362 txbd1
= (struct tx_bd_ext
*)
363 &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
365 txbd1
->tx_bd_hsize_lflags
= 0;
366 if (skb_is_gso(skb
)) {
369 if (skb
->encapsulation
)
370 hdr_len
= skb_inner_network_offset(skb
) +
371 skb_inner_network_header_len(skb
) +
372 inner_tcp_hdrlen(skb
);
374 hdr_len
= skb_transport_offset(skb
) +
377 txbd1
->tx_bd_hsize_lflags
= cpu_to_le32(TX_BD_FLAGS_LSO
|
379 (hdr_len
<< (TX_BD_HSIZE_SHIFT
- 1)));
380 length
= skb_shinfo(skb
)->gso_size
;
381 txbd1
->tx_bd_mss
= cpu_to_le32(length
);
383 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
384 txbd1
->tx_bd_hsize_lflags
=
385 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM
);
386 txbd1
->tx_bd_mss
= 0;
390 flags
|= bnxt_lhint_arr
[length
];
391 txbd
->tx_bd_len_flags_type
= cpu_to_le32(flags
);
393 txbd1
->tx_bd_cfa_meta
= cpu_to_le32(vlan_tag_flags
);
394 txbd1
->tx_bd_cfa_action
= cpu_to_le32(cfa_action
);
395 for (i
= 0; i
< last_frag
; i
++) {
396 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
398 prod
= NEXT_TX(prod
);
399 txbd
= &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
401 len
= skb_frag_size(frag
);
402 mapping
= skb_frag_dma_map(&pdev
->dev
, frag
, 0, len
,
405 if (unlikely(dma_mapping_error(&pdev
->dev
, mapping
)))
408 tx_buf
= &txr
->tx_buf_ring
[prod
];
409 dma_unmap_addr_set(tx_buf
, mapping
, mapping
);
411 txbd
->tx_bd_haddr
= cpu_to_le64(mapping
);
413 flags
= len
<< TX_BD_LEN_SHIFT
;
414 txbd
->tx_bd_len_flags_type
= cpu_to_le32(flags
);
418 txbd
->tx_bd_len_flags_type
=
419 cpu_to_le32(((len
+ pad
) << TX_BD_LEN_SHIFT
) | flags
|
420 TX_BD_FLAGS_PACKET_END
);
422 netdev_tx_sent_queue(txq
, skb
->len
);
424 /* Sync BD data before updating doorbell */
427 prod
= NEXT_TX(prod
);
430 writel(DB_KEY_TX
| prod
, txr
->tx_doorbell
);
431 writel(DB_KEY_TX
| prod
, txr
->tx_doorbell
);
437 if (unlikely(bnxt_tx_avail(bp
, txr
) <= MAX_SKB_FRAGS
+ 1)) {
438 netif_tx_stop_queue(txq
);
440 /* netif_tx_stop_queue() must be done before checking
441 * tx index in bnxt_tx_avail() below, because in
442 * bnxt_tx_int(), we update tx index before checking for
443 * netif_tx_queue_stopped().
446 if (bnxt_tx_avail(bp
, txr
) > bp
->tx_wake_thresh
)
447 netif_tx_wake_queue(txq
);
454 /* start back at beginning and unmap skb */
456 tx_buf
= &txr
->tx_buf_ring
[prod
];
458 dma_unmap_single(&pdev
->dev
, dma_unmap_addr(tx_buf
, mapping
),
459 skb_headlen(skb
), PCI_DMA_TODEVICE
);
460 prod
= NEXT_TX(prod
);
462 /* unmap remaining mapped pages */
463 for (i
= 0; i
< last_frag
; i
++) {
464 prod
= NEXT_TX(prod
);
465 tx_buf
= &txr
->tx_buf_ring
[prod
];
466 dma_unmap_page(&pdev
->dev
, dma_unmap_addr(tx_buf
, mapping
),
467 skb_frag_size(&skb_shinfo(skb
)->frags
[i
]),
471 dev_kfree_skb_any(skb
);
475 static void bnxt_tx_int(struct bnxt
*bp
, struct bnxt_napi
*bnapi
, int nr_pkts
)
477 struct bnxt_tx_ring_info
*txr
= bnapi
->tx_ring
;
478 int index
= txr
- &bp
->tx_ring
[0];
479 struct netdev_queue
*txq
= netdev_get_tx_queue(bp
->dev
, index
);
480 u16 cons
= txr
->tx_cons
;
481 struct pci_dev
*pdev
= bp
->pdev
;
483 unsigned int tx_bytes
= 0;
485 for (i
= 0; i
< nr_pkts
; i
++) {
486 struct bnxt_sw_tx_bd
*tx_buf
;
490 tx_buf
= &txr
->tx_buf_ring
[cons
];
491 cons
= NEXT_TX(cons
);
495 if (tx_buf
->is_push
) {
500 dma_unmap_single(&pdev
->dev
, dma_unmap_addr(tx_buf
, mapping
),
501 skb_headlen(skb
), PCI_DMA_TODEVICE
);
502 last
= tx_buf
->nr_frags
;
504 for (j
= 0; j
< last
; j
++) {
505 cons
= NEXT_TX(cons
);
506 tx_buf
= &txr
->tx_buf_ring
[cons
];
509 dma_unmap_addr(tx_buf
, mapping
),
510 skb_frag_size(&skb_shinfo(skb
)->frags
[j
]),
515 cons
= NEXT_TX(cons
);
517 tx_bytes
+= skb
->len
;
518 dev_kfree_skb_any(skb
);
521 netdev_tx_completed_queue(txq
, nr_pkts
, tx_bytes
);
524 /* Need to make the tx_cons update visible to bnxt_start_xmit()
525 * before checking for netif_tx_queue_stopped(). Without the
526 * memory barrier, there is a small possibility that bnxt_start_xmit()
527 * will miss it and cause the queue to be stopped forever.
531 if (unlikely(netif_tx_queue_stopped(txq
)) &&
532 (bnxt_tx_avail(bp
, txr
) > bp
->tx_wake_thresh
)) {
533 __netif_tx_lock(txq
, smp_processor_id());
534 if (netif_tx_queue_stopped(txq
) &&
535 bnxt_tx_avail(bp
, txr
) > bp
->tx_wake_thresh
&&
536 txr
->dev_state
!= BNXT_DEV_STATE_CLOSING
)
537 netif_tx_wake_queue(txq
);
538 __netif_tx_unlock(txq
);
542 static inline u8
*__bnxt_alloc_rx_data(struct bnxt
*bp
, dma_addr_t
*mapping
,
546 struct pci_dev
*pdev
= bp
->pdev
;
548 data
= kmalloc(bp
->rx_buf_size
, gfp
);
552 *mapping
= dma_map_single(&pdev
->dev
, data
+ BNXT_RX_DMA_OFFSET
,
553 bp
->rx_buf_use_size
, PCI_DMA_FROMDEVICE
);
555 if (dma_mapping_error(&pdev
->dev
, *mapping
)) {
562 static inline int bnxt_alloc_rx_data(struct bnxt
*bp
,
563 struct bnxt_rx_ring_info
*rxr
,
566 struct rx_bd
*rxbd
= &rxr
->rx_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
567 struct bnxt_sw_rx_bd
*rx_buf
= &rxr
->rx_buf_ring
[prod
];
571 data
= __bnxt_alloc_rx_data(bp
, &mapping
, gfp
);
576 dma_unmap_addr_set(rx_buf
, mapping
, mapping
);
578 rxbd
->rx_bd_haddr
= cpu_to_le64(mapping
);
583 static void bnxt_reuse_rx_data(struct bnxt_rx_ring_info
*rxr
, u16 cons
,
586 u16 prod
= rxr
->rx_prod
;
587 struct bnxt_sw_rx_bd
*cons_rx_buf
, *prod_rx_buf
;
588 struct rx_bd
*cons_bd
, *prod_bd
;
590 prod_rx_buf
= &rxr
->rx_buf_ring
[prod
];
591 cons_rx_buf
= &rxr
->rx_buf_ring
[cons
];
593 prod_rx_buf
->data
= data
;
595 dma_unmap_addr_set(prod_rx_buf
, mapping
,
596 dma_unmap_addr(cons_rx_buf
, mapping
));
598 prod_bd
= &rxr
->rx_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
599 cons_bd
= &rxr
->rx_desc_ring
[RX_RING(cons
)][RX_IDX(cons
)];
601 prod_bd
->rx_bd_haddr
= cons_bd
->rx_bd_haddr
;
604 static inline u16
bnxt_find_next_agg_idx(struct bnxt_rx_ring_info
*rxr
, u16 idx
)
606 u16 next
, max
= rxr
->rx_agg_bmap_size
;
608 next
= find_next_zero_bit(rxr
->rx_agg_bmap
, max
, idx
);
610 next
= find_first_zero_bit(rxr
->rx_agg_bmap
, max
);
614 static inline int bnxt_alloc_rx_page(struct bnxt
*bp
,
615 struct bnxt_rx_ring_info
*rxr
,
619 &rxr
->rx_agg_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
620 struct bnxt_sw_rx_agg_bd
*rx_agg_buf
;
621 struct pci_dev
*pdev
= bp
->pdev
;
624 u16 sw_prod
= rxr
->rx_sw_agg_prod
;
625 unsigned int offset
= 0;
627 if (PAGE_SIZE
> BNXT_RX_PAGE_SIZE
) {
630 page
= alloc_page(gfp
);
634 rxr
->rx_page_offset
= 0;
636 offset
= rxr
->rx_page_offset
;
637 rxr
->rx_page_offset
+= BNXT_RX_PAGE_SIZE
;
638 if (rxr
->rx_page_offset
== PAGE_SIZE
)
643 page
= alloc_page(gfp
);
648 mapping
= dma_map_page(&pdev
->dev
, page
, offset
, BNXT_RX_PAGE_SIZE
,
650 if (dma_mapping_error(&pdev
->dev
, mapping
)) {
655 if (unlikely(test_bit(sw_prod
, rxr
->rx_agg_bmap
)))
656 sw_prod
= bnxt_find_next_agg_idx(rxr
, sw_prod
);
658 __set_bit(sw_prod
, rxr
->rx_agg_bmap
);
659 rx_agg_buf
= &rxr
->rx_agg_ring
[sw_prod
];
660 rxr
->rx_sw_agg_prod
= NEXT_RX_AGG(sw_prod
);
662 rx_agg_buf
->page
= page
;
663 rx_agg_buf
->offset
= offset
;
664 rx_agg_buf
->mapping
= mapping
;
665 rxbd
->rx_bd_haddr
= cpu_to_le64(mapping
);
666 rxbd
->rx_bd_opaque
= sw_prod
;
670 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi
*bnapi
, u16 cp_cons
,
673 struct bnxt
*bp
= bnapi
->bp
;
674 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
675 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
676 u16 prod
= rxr
->rx_agg_prod
;
677 u16 sw_prod
= rxr
->rx_sw_agg_prod
;
680 for (i
= 0; i
< agg_bufs
; i
++) {
682 struct rx_agg_cmp
*agg
;
683 struct bnxt_sw_rx_agg_bd
*cons_rx_buf
, *prod_rx_buf
;
684 struct rx_bd
*prod_bd
;
687 agg
= (struct rx_agg_cmp
*)
688 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
689 cons
= agg
->rx_agg_cmp_opaque
;
690 __clear_bit(cons
, rxr
->rx_agg_bmap
);
692 if (unlikely(test_bit(sw_prod
, rxr
->rx_agg_bmap
)))
693 sw_prod
= bnxt_find_next_agg_idx(rxr
, sw_prod
);
695 __set_bit(sw_prod
, rxr
->rx_agg_bmap
);
696 prod_rx_buf
= &rxr
->rx_agg_ring
[sw_prod
];
697 cons_rx_buf
= &rxr
->rx_agg_ring
[cons
];
699 /* It is possible for sw_prod to be equal to cons, so
700 * set cons_rx_buf->page to NULL first.
702 page
= cons_rx_buf
->page
;
703 cons_rx_buf
->page
= NULL
;
704 prod_rx_buf
->page
= page
;
705 prod_rx_buf
->offset
= cons_rx_buf
->offset
;
707 prod_rx_buf
->mapping
= cons_rx_buf
->mapping
;
709 prod_bd
= &rxr
->rx_agg_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
711 prod_bd
->rx_bd_haddr
= cpu_to_le64(cons_rx_buf
->mapping
);
712 prod_bd
->rx_bd_opaque
= sw_prod
;
714 prod
= NEXT_RX_AGG(prod
);
715 sw_prod
= NEXT_RX_AGG(sw_prod
);
716 cp_cons
= NEXT_CMP(cp_cons
);
718 rxr
->rx_agg_prod
= prod
;
719 rxr
->rx_sw_agg_prod
= sw_prod
;
722 static struct sk_buff
*bnxt_rx_skb(struct bnxt
*bp
,
723 struct bnxt_rx_ring_info
*rxr
, u16 cons
,
724 u16 prod
, u8
*data
, dma_addr_t dma_addr
,
730 err
= bnxt_alloc_rx_data(bp
, rxr
, prod
, GFP_ATOMIC
);
732 bnxt_reuse_rx_data(rxr
, cons
, data
);
736 skb
= build_skb(data
, 0);
737 dma_unmap_single(&bp
->pdev
->dev
, dma_addr
, bp
->rx_buf_use_size
,
744 skb_reserve(skb
, BNXT_RX_OFFSET
);
749 static struct sk_buff
*bnxt_rx_pages(struct bnxt
*bp
, struct bnxt_napi
*bnapi
,
750 struct sk_buff
*skb
, u16 cp_cons
,
753 struct pci_dev
*pdev
= bp
->pdev
;
754 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
755 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
756 u16 prod
= rxr
->rx_agg_prod
;
759 for (i
= 0; i
< agg_bufs
; i
++) {
761 struct rx_agg_cmp
*agg
;
762 struct bnxt_sw_rx_agg_bd
*cons_rx_buf
;
766 agg
= (struct rx_agg_cmp
*)
767 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
768 cons
= agg
->rx_agg_cmp_opaque
;
769 frag_len
= (le32_to_cpu(agg
->rx_agg_cmp_len_flags_type
) &
770 RX_AGG_CMP_LEN
) >> RX_AGG_CMP_LEN_SHIFT
;
772 cons_rx_buf
= &rxr
->rx_agg_ring
[cons
];
773 skb_fill_page_desc(skb
, i
, cons_rx_buf
->page
,
774 cons_rx_buf
->offset
, frag_len
);
775 __clear_bit(cons
, rxr
->rx_agg_bmap
);
777 /* It is possible for bnxt_alloc_rx_page() to allocate
778 * a sw_prod index that equals the cons index, so we
779 * need to clear the cons entry now.
781 mapping
= dma_unmap_addr(cons_rx_buf
, mapping
);
782 page
= cons_rx_buf
->page
;
783 cons_rx_buf
->page
= NULL
;
785 if (bnxt_alloc_rx_page(bp
, rxr
, prod
, GFP_ATOMIC
) != 0) {
786 struct skb_shared_info
*shinfo
;
787 unsigned int nr_frags
;
789 shinfo
= skb_shinfo(skb
);
790 nr_frags
= --shinfo
->nr_frags
;
791 __skb_frag_set_page(&shinfo
->frags
[nr_frags
], NULL
);
795 cons_rx_buf
->page
= page
;
797 /* Update prod since possibly some pages have been
800 rxr
->rx_agg_prod
= prod
;
801 bnxt_reuse_rx_agg_bufs(bnapi
, cp_cons
, agg_bufs
- i
);
805 dma_unmap_page(&pdev
->dev
, mapping
, BNXT_RX_PAGE_SIZE
,
808 skb
->data_len
+= frag_len
;
809 skb
->len
+= frag_len
;
810 skb
->truesize
+= PAGE_SIZE
;
812 prod
= NEXT_RX_AGG(prod
);
813 cp_cons
= NEXT_CMP(cp_cons
);
815 rxr
->rx_agg_prod
= prod
;
819 static int bnxt_agg_bufs_valid(struct bnxt
*bp
, struct bnxt_cp_ring_info
*cpr
,
820 u8 agg_bufs
, u32
*raw_cons
)
823 struct rx_agg_cmp
*agg
;
825 *raw_cons
= ADV_RAW_CMP(*raw_cons
, agg_bufs
);
826 last
= RING_CMP(*raw_cons
);
827 agg
= (struct rx_agg_cmp
*)
828 &cpr
->cp_desc_ring
[CP_RING(last
)][CP_IDX(last
)];
829 return RX_AGG_CMP_VALID(agg
, *raw_cons
);
832 static inline struct sk_buff
*bnxt_copy_skb(struct bnxt_napi
*bnapi
, u8
*data
,
836 struct bnxt
*bp
= bnapi
->bp
;
837 struct pci_dev
*pdev
= bp
->pdev
;
840 skb
= napi_alloc_skb(&bnapi
->napi
, len
);
844 dma_sync_single_for_cpu(&pdev
->dev
, mapping
,
845 bp
->rx_copy_thresh
, PCI_DMA_FROMDEVICE
);
847 memcpy(skb
->data
- BNXT_RX_OFFSET
, data
, len
+ BNXT_RX_OFFSET
);
849 dma_sync_single_for_device(&pdev
->dev
, mapping
,
857 static int bnxt_discard_rx(struct bnxt
*bp
, struct bnxt_napi
*bnapi
,
858 u32
*raw_cons
, void *cmp
)
860 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
861 struct rx_cmp
*rxcmp
= cmp
;
862 u32 tmp_raw_cons
= *raw_cons
;
863 u8 cmp_type
, agg_bufs
= 0;
865 cmp_type
= RX_CMP_TYPE(rxcmp
);
867 if (cmp_type
== CMP_TYPE_RX_L2_CMP
) {
868 agg_bufs
= (le32_to_cpu(rxcmp
->rx_cmp_misc_v1
) &
870 RX_CMP_AGG_BUFS_SHIFT
;
871 } else if (cmp_type
== CMP_TYPE_RX_L2_TPA_END_CMP
) {
872 struct rx_tpa_end_cmp
*tpa_end
= cmp
;
874 agg_bufs
= (le32_to_cpu(tpa_end
->rx_tpa_end_cmp_misc_v1
) &
875 RX_TPA_END_CMP_AGG_BUFS
) >>
876 RX_TPA_END_CMP_AGG_BUFS_SHIFT
;
880 if (!bnxt_agg_bufs_valid(bp
, cpr
, agg_bufs
, &tmp_raw_cons
))
883 *raw_cons
= tmp_raw_cons
;
887 static void bnxt_sched_reset(struct bnxt
*bp
, struct bnxt_rx_ring_info
*rxr
)
889 if (!rxr
->bnapi
->in_reset
) {
890 rxr
->bnapi
->in_reset
= true;
891 set_bit(BNXT_RESET_TASK_SP_EVENT
, &bp
->sp_event
);
892 schedule_work(&bp
->sp_task
);
894 rxr
->rx_next_cons
= 0xffff;
897 static void bnxt_tpa_start(struct bnxt
*bp
, struct bnxt_rx_ring_info
*rxr
,
898 struct rx_tpa_start_cmp
*tpa_start
,
899 struct rx_tpa_start_cmp_ext
*tpa_start1
)
901 u8 agg_id
= TPA_START_AGG_ID(tpa_start
);
903 struct bnxt_tpa_info
*tpa_info
;
904 struct bnxt_sw_rx_bd
*cons_rx_buf
, *prod_rx_buf
;
905 struct rx_bd
*prod_bd
;
908 cons
= tpa_start
->rx_tpa_start_cmp_opaque
;
910 cons_rx_buf
= &rxr
->rx_buf_ring
[cons
];
911 prod_rx_buf
= &rxr
->rx_buf_ring
[prod
];
912 tpa_info
= &rxr
->rx_tpa
[agg_id
];
914 if (unlikely(cons
!= rxr
->rx_next_cons
)) {
915 bnxt_sched_reset(bp
, rxr
);
919 prod_rx_buf
->data
= tpa_info
->data
;
921 mapping
= tpa_info
->mapping
;
922 dma_unmap_addr_set(prod_rx_buf
, mapping
, mapping
);
924 prod_bd
= &rxr
->rx_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
926 prod_bd
->rx_bd_haddr
= cpu_to_le64(mapping
);
928 tpa_info
->data
= cons_rx_buf
->data
;
929 cons_rx_buf
->data
= NULL
;
930 tpa_info
->mapping
= dma_unmap_addr(cons_rx_buf
, mapping
);
933 le32_to_cpu(tpa_start
->rx_tpa_start_cmp_len_flags_type
) >>
934 RX_TPA_START_CMP_LEN_SHIFT
;
935 if (likely(TPA_START_HASH_VALID(tpa_start
))) {
936 u32 hash_type
= TPA_START_HASH_TYPE(tpa_start
);
938 tpa_info
->hash_type
= PKT_HASH_TYPE_L4
;
939 tpa_info
->gso_type
= SKB_GSO_TCPV4
;
940 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
942 tpa_info
->gso_type
= SKB_GSO_TCPV6
;
944 le32_to_cpu(tpa_start
->rx_tpa_start_cmp_rss_hash
);
946 tpa_info
->hash_type
= PKT_HASH_TYPE_NONE
;
947 tpa_info
->gso_type
= 0;
948 if (netif_msg_rx_err(bp
))
949 netdev_warn(bp
->dev
, "TPA packet without valid hash\n");
951 tpa_info
->flags2
= le32_to_cpu(tpa_start1
->rx_tpa_start_cmp_flags2
);
952 tpa_info
->metadata
= le32_to_cpu(tpa_start1
->rx_tpa_start_cmp_metadata
);
953 tpa_info
->hdr_info
= le32_to_cpu(tpa_start1
->rx_tpa_start_cmp_hdr_info
);
955 rxr
->rx_prod
= NEXT_RX(prod
);
956 cons
= NEXT_RX(cons
);
957 rxr
->rx_next_cons
= NEXT_RX(cons
);
958 cons_rx_buf
= &rxr
->rx_buf_ring
[cons
];
960 bnxt_reuse_rx_data(rxr
, cons
, cons_rx_buf
->data
);
961 rxr
->rx_prod
= NEXT_RX(rxr
->rx_prod
);
962 cons_rx_buf
->data
= NULL
;
965 static void bnxt_abort_tpa(struct bnxt
*bp
, struct bnxt_napi
*bnapi
,
966 u16 cp_cons
, u32 agg_bufs
)
969 bnxt_reuse_rx_agg_bufs(bnapi
, cp_cons
, agg_bufs
);
972 static struct sk_buff
*bnxt_gro_func_5731x(struct bnxt_tpa_info
*tpa_info
,
973 int payload_off
, int tcp_ts
,
979 u16 outer_ip_off
, inner_ip_off
, inner_mac_off
;
980 u32 hdr_info
= tpa_info
->hdr_info
;
981 bool loopback
= false;
983 inner_ip_off
= BNXT_TPA_INNER_L3_OFF(hdr_info
);
984 inner_mac_off
= BNXT_TPA_INNER_L2_OFF(hdr_info
);
985 outer_ip_off
= BNXT_TPA_OUTER_L3_OFF(hdr_info
);
987 /* If the packet is an internal loopback packet, the offsets will
988 * have an extra 4 bytes.
990 if (inner_mac_off
== 4) {
992 } else if (inner_mac_off
> 4) {
993 __be16 proto
= *((__be16
*)(skb
->data
+ inner_ip_off
-
996 /* We only support inner iPv4/ipv6. If we don't see the
997 * correct protocol ID, it must be a loopback packet where
998 * the offsets are off by 4.
1000 if (proto
!= htons(ETH_P_IP
) && proto
!= htons(ETH_P_IPV6
))
1004 /* internal loopback packet, subtract all offsets by 4 */
1010 nw_off
= inner_ip_off
- ETH_HLEN
;
1011 skb_set_network_header(skb
, nw_off
);
1012 if (tpa_info
->flags2
& RX_TPA_START_CMP_FLAGS2_IP_TYPE
) {
1013 struct ipv6hdr
*iph
= ipv6_hdr(skb
);
1015 skb_set_transport_header(skb
, nw_off
+ sizeof(struct ipv6hdr
));
1016 len
= skb
->len
- skb_transport_offset(skb
);
1018 th
->check
= ~tcp_v6_check(len
, &iph
->saddr
, &iph
->daddr
, 0);
1020 struct iphdr
*iph
= ip_hdr(skb
);
1022 skb_set_transport_header(skb
, nw_off
+ sizeof(struct iphdr
));
1023 len
= skb
->len
- skb_transport_offset(skb
);
1025 th
->check
= ~tcp_v4_check(len
, iph
->saddr
, iph
->daddr
, 0);
1028 if (inner_mac_off
) { /* tunnel */
1029 struct udphdr
*uh
= NULL
;
1030 __be16 proto
= *((__be16
*)(skb
->data
+ outer_ip_off
-
1033 if (proto
== htons(ETH_P_IP
)) {
1034 struct iphdr
*iph
= (struct iphdr
*)skb
->data
;
1036 if (iph
->protocol
== IPPROTO_UDP
)
1037 uh
= (struct udphdr
*)(iph
+ 1);
1039 struct ipv6hdr
*iph
= (struct ipv6hdr
*)skb
->data
;
1041 if (iph
->nexthdr
== IPPROTO_UDP
)
1042 uh
= (struct udphdr
*)(iph
+ 1);
1046 skb_shinfo(skb
)->gso_type
|=
1047 SKB_GSO_UDP_TUNNEL_CSUM
;
1049 skb_shinfo(skb
)->gso_type
|= SKB_GSO_UDP_TUNNEL
;
1056 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
1057 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1059 static struct sk_buff
*bnxt_gro_func_5730x(struct bnxt_tpa_info
*tpa_info
,
1060 int payload_off
, int tcp_ts
,
1061 struct sk_buff
*skb
)
1065 int len
, nw_off
, tcp_opt_len
;
1070 if (tpa_info
->gso_type
== SKB_GSO_TCPV4
) {
1073 nw_off
= payload_off
- BNXT_IPV4_HDR_SIZE
- tcp_opt_len
-
1075 skb_set_network_header(skb
, nw_off
);
1077 skb_set_transport_header(skb
, nw_off
+ sizeof(struct iphdr
));
1078 len
= skb
->len
- skb_transport_offset(skb
);
1080 th
->check
= ~tcp_v4_check(len
, iph
->saddr
, iph
->daddr
, 0);
1081 } else if (tpa_info
->gso_type
== SKB_GSO_TCPV6
) {
1082 struct ipv6hdr
*iph
;
1084 nw_off
= payload_off
- BNXT_IPV6_HDR_SIZE
- tcp_opt_len
-
1086 skb_set_network_header(skb
, nw_off
);
1087 iph
= ipv6_hdr(skb
);
1088 skb_set_transport_header(skb
, nw_off
+ sizeof(struct ipv6hdr
));
1089 len
= skb
->len
- skb_transport_offset(skb
);
1091 th
->check
= ~tcp_v6_check(len
, &iph
->saddr
, &iph
->daddr
, 0);
1093 dev_kfree_skb_any(skb
);
1096 tcp_gro_complete(skb
);
1098 if (nw_off
) { /* tunnel */
1099 struct udphdr
*uh
= NULL
;
1101 if (skb
->protocol
== htons(ETH_P_IP
)) {
1102 struct iphdr
*iph
= (struct iphdr
*)skb
->data
;
1104 if (iph
->protocol
== IPPROTO_UDP
)
1105 uh
= (struct udphdr
*)(iph
+ 1);
1107 struct ipv6hdr
*iph
= (struct ipv6hdr
*)skb
->data
;
1109 if (iph
->nexthdr
== IPPROTO_UDP
)
1110 uh
= (struct udphdr
*)(iph
+ 1);
1114 skb_shinfo(skb
)->gso_type
|=
1115 SKB_GSO_UDP_TUNNEL_CSUM
;
1117 skb_shinfo(skb
)->gso_type
|= SKB_GSO_UDP_TUNNEL
;
1124 static inline struct sk_buff
*bnxt_gro_skb(struct bnxt
*bp
,
1125 struct bnxt_tpa_info
*tpa_info
,
1126 struct rx_tpa_end_cmp
*tpa_end
,
1127 struct rx_tpa_end_cmp_ext
*tpa_end1
,
1128 struct sk_buff
*skb
)
1134 segs
= TPA_END_TPA_SEGS(tpa_end
);
1138 NAPI_GRO_CB(skb
)->count
= segs
;
1139 skb_shinfo(skb
)->gso_size
=
1140 le32_to_cpu(tpa_end1
->rx_tpa_end_cmp_seg_len
);
1141 skb_shinfo(skb
)->gso_type
= tpa_info
->gso_type
;
1142 payload_off
= (le32_to_cpu(tpa_end
->rx_tpa_end_cmp_misc_v1
) &
1143 RX_TPA_END_CMP_PAYLOAD_OFFSET
) >>
1144 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT
;
1145 skb
= bp
->gro_func(tpa_info
, payload_off
, TPA_END_GRO_TS(tpa_end
), skb
);
1150 static inline struct sk_buff
*bnxt_tpa_end(struct bnxt
*bp
,
1151 struct bnxt_napi
*bnapi
,
1153 struct rx_tpa_end_cmp
*tpa_end
,
1154 struct rx_tpa_end_cmp_ext
*tpa_end1
,
1157 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1158 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
1159 u8 agg_id
= TPA_END_AGG_ID(tpa_end
);
1161 u16 cp_cons
= RING_CMP(*raw_cons
);
1163 struct bnxt_tpa_info
*tpa_info
;
1165 struct sk_buff
*skb
;
1167 if (unlikely(bnapi
->in_reset
)) {
1168 int rc
= bnxt_discard_rx(bp
, bnapi
, raw_cons
, tpa_end
);
1171 return ERR_PTR(-EBUSY
);
1175 tpa_info
= &rxr
->rx_tpa
[agg_id
];
1176 data
= tpa_info
->data
;
1178 len
= tpa_info
->len
;
1179 mapping
= tpa_info
->mapping
;
1181 agg_bufs
= (le32_to_cpu(tpa_end
->rx_tpa_end_cmp_misc_v1
) &
1182 RX_TPA_END_CMP_AGG_BUFS
) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT
;
1185 if (!bnxt_agg_bufs_valid(bp
, cpr
, agg_bufs
, raw_cons
))
1186 return ERR_PTR(-EBUSY
);
1189 cp_cons
= NEXT_CMP(cp_cons
);
1192 if (unlikely(agg_bufs
> MAX_SKB_FRAGS
)) {
1193 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
1194 netdev_warn(bp
->dev
, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1195 agg_bufs
, (int)MAX_SKB_FRAGS
);
1199 if (len
<= bp
->rx_copy_thresh
) {
1200 skb
= bnxt_copy_skb(bnapi
, data
, len
, mapping
);
1202 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
1207 dma_addr_t new_mapping
;
1209 new_data
= __bnxt_alloc_rx_data(bp
, &new_mapping
, GFP_ATOMIC
);
1211 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
1215 tpa_info
->data
= new_data
;
1216 tpa_info
->mapping
= new_mapping
;
1218 skb
= build_skb(data
, 0);
1219 dma_unmap_single(&bp
->pdev
->dev
, mapping
, bp
->rx_buf_use_size
,
1220 PCI_DMA_FROMDEVICE
);
1224 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
1227 skb_reserve(skb
, BNXT_RX_OFFSET
);
1232 skb
= bnxt_rx_pages(bp
, bnapi
, skb
, cp_cons
, agg_bufs
);
1234 /* Page reuse already handled by bnxt_rx_pages(). */
1238 skb
->protocol
= eth_type_trans(skb
, bp
->dev
);
1240 if (tpa_info
->hash_type
!= PKT_HASH_TYPE_NONE
)
1241 skb_set_hash(skb
, tpa_info
->rss_hash
, tpa_info
->hash_type
);
1243 if ((tpa_info
->flags2
& RX_CMP_FLAGS2_META_FORMAT_VLAN
) &&
1244 (skb
->dev
->features
& NETIF_F_HW_VLAN_CTAG_RX
)) {
1245 u16 vlan_proto
= tpa_info
->metadata
>>
1246 RX_CMP_FLAGS2_METADATA_TPID_SFT
;
1247 u16 vtag
= tpa_info
->metadata
& RX_CMP_FLAGS2_METADATA_VID_MASK
;
1249 __vlan_hwaccel_put_tag(skb
, htons(vlan_proto
), vtag
);
1252 skb_checksum_none_assert(skb
);
1253 if (likely(tpa_info
->flags2
& RX_TPA_START_CMP_FLAGS2_L4_CS_CALC
)) {
1254 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1256 (tpa_info
->flags2
& RX_CMP_FLAGS2_T_L4_CS_CALC
) >> 3;
1259 if (TPA_END_GRO(tpa_end
))
1260 skb
= bnxt_gro_skb(bp
, tpa_info
, tpa_end
, tpa_end1
, skb
);
1265 /* returns the following:
1266 * 1 - 1 packet successfully received
1267 * 0 - successful TPA_START, packet not completed yet
1268 * -EBUSY - completion ring does not have all the agg buffers yet
1269 * -ENOMEM - packet aborted due to out of memory
1270 * -EIO - packet aborted due to hw error indicated in BD
1272 static int bnxt_rx_pkt(struct bnxt
*bp
, struct bnxt_napi
*bnapi
, u32
*raw_cons
,
1275 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1276 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
1277 struct net_device
*dev
= bp
->dev
;
1278 struct rx_cmp
*rxcmp
;
1279 struct rx_cmp_ext
*rxcmp1
;
1280 u32 tmp_raw_cons
= *raw_cons
;
1281 u16 cons
, prod
, cp_cons
= RING_CMP(tmp_raw_cons
);
1282 struct bnxt_sw_rx_bd
*rx_buf
;
1284 u8
*data
, agg_bufs
, cmp_type
;
1285 dma_addr_t dma_addr
;
1286 struct sk_buff
*skb
;
1289 rxcmp
= (struct rx_cmp
*)
1290 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
1292 tmp_raw_cons
= NEXT_RAW_CMP(tmp_raw_cons
);
1293 cp_cons
= RING_CMP(tmp_raw_cons
);
1294 rxcmp1
= (struct rx_cmp_ext
*)
1295 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
1297 if (!RX_CMP_VALID(rxcmp1
, tmp_raw_cons
))
1300 cmp_type
= RX_CMP_TYPE(rxcmp
);
1302 prod
= rxr
->rx_prod
;
1304 if (cmp_type
== CMP_TYPE_RX_L2_TPA_START_CMP
) {
1305 bnxt_tpa_start(bp
, rxr
, (struct rx_tpa_start_cmp
*)rxcmp
,
1306 (struct rx_tpa_start_cmp_ext
*)rxcmp1
);
1308 goto next_rx_no_prod
;
1310 } else if (cmp_type
== CMP_TYPE_RX_L2_TPA_END_CMP
) {
1311 skb
= bnxt_tpa_end(bp
, bnapi
, &tmp_raw_cons
,
1312 (struct rx_tpa_end_cmp
*)rxcmp
,
1313 (struct rx_tpa_end_cmp_ext
*)rxcmp1
,
1316 if (unlikely(IS_ERR(skb
)))
1321 skb_record_rx_queue(skb
, bnapi
->index
);
1322 skb_mark_napi_id(skb
, &bnapi
->napi
);
1323 if (bnxt_busy_polling(bnapi
))
1324 netif_receive_skb(skb
);
1326 napi_gro_receive(&bnapi
->napi
, skb
);
1329 goto next_rx_no_prod
;
1332 cons
= rxcmp
->rx_cmp_opaque
;
1333 rx_buf
= &rxr
->rx_buf_ring
[cons
];
1334 data
= rx_buf
->data
;
1335 if (unlikely(cons
!= rxr
->rx_next_cons
)) {
1336 int rc1
= bnxt_discard_rx(bp
, bnapi
, raw_cons
, rxcmp
);
1338 bnxt_sched_reset(bp
, rxr
);
1343 agg_bufs
= (le32_to_cpu(rxcmp
->rx_cmp_misc_v1
) & RX_CMP_AGG_BUFS
) >>
1344 RX_CMP_AGG_BUFS_SHIFT
;
1347 if (!bnxt_agg_bufs_valid(bp
, cpr
, agg_bufs
, &tmp_raw_cons
))
1350 cp_cons
= NEXT_CMP(cp_cons
);
1354 rx_buf
->data
= NULL
;
1355 if (rxcmp1
->rx_cmp_cfa_code_errors_v2
& RX_CMP_L2_ERRORS
) {
1356 bnxt_reuse_rx_data(rxr
, cons
, data
);
1358 bnxt_reuse_rx_agg_bufs(bnapi
, cp_cons
, agg_bufs
);
1364 len
= le32_to_cpu(rxcmp
->rx_cmp_len_flags_type
) >> RX_CMP_LEN_SHIFT
;
1365 dma_addr
= dma_unmap_addr(rx_buf
, mapping
);
1367 if (len
<= bp
->rx_copy_thresh
) {
1368 skb
= bnxt_copy_skb(bnapi
, data
, len
, dma_addr
);
1369 bnxt_reuse_rx_data(rxr
, cons
, data
);
1375 skb
= bnxt_rx_skb(bp
, rxr
, cons
, prod
, data
, dma_addr
, len
);
1383 skb
= bnxt_rx_pages(bp
, bnapi
, skb
, cp_cons
, agg_bufs
);
1390 if (RX_CMP_HASH_VALID(rxcmp
)) {
1391 u32 hash_type
= RX_CMP_HASH_TYPE(rxcmp
);
1392 enum pkt_hash_types type
= PKT_HASH_TYPE_L4
;
1394 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1395 if (hash_type
!= 1 && hash_type
!= 3)
1396 type
= PKT_HASH_TYPE_L3
;
1397 skb_set_hash(skb
, le32_to_cpu(rxcmp
->rx_cmp_rss_hash
), type
);
1400 skb
->protocol
= eth_type_trans(skb
, dev
);
1402 if ((rxcmp1
->rx_cmp_flags2
&
1403 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN
)) &&
1404 (skb
->dev
->features
& NETIF_F_HW_VLAN_CTAG_RX
)) {
1405 u32 meta_data
= le32_to_cpu(rxcmp1
->rx_cmp_meta_data
);
1406 u16 vtag
= meta_data
& RX_CMP_FLAGS2_METADATA_VID_MASK
;
1407 u16 vlan_proto
= meta_data
>> RX_CMP_FLAGS2_METADATA_TPID_SFT
;
1409 __vlan_hwaccel_put_tag(skb
, htons(vlan_proto
), vtag
);
1412 skb_checksum_none_assert(skb
);
1413 if (RX_CMP_L4_CS_OK(rxcmp1
)) {
1414 if (dev
->features
& NETIF_F_RXCSUM
) {
1415 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1416 skb
->csum_level
= RX_CMP_ENCAP(rxcmp1
);
1419 if (rxcmp1
->rx_cmp_cfa_code_errors_v2
& RX_CMP_L4_CS_ERR_BITS
) {
1420 if (dev
->features
& NETIF_F_RXCSUM
)
1421 cpr
->rx_l4_csum_errors
++;
1425 skb_record_rx_queue(skb
, bnapi
->index
);
1426 skb_mark_napi_id(skb
, &bnapi
->napi
);
1427 if (bnxt_busy_polling(bnapi
))
1428 netif_receive_skb(skb
);
1430 napi_gro_receive(&bnapi
->napi
, skb
);
1434 rxr
->rx_prod
= NEXT_RX(prod
);
1435 rxr
->rx_next_cons
= NEXT_RX(cons
);
1438 *raw_cons
= tmp_raw_cons
;
1443 #define BNXT_GET_EVENT_PORT(data) \
1445 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
1447 static int bnxt_async_event_process(struct bnxt
*bp
,
1448 struct hwrm_async_event_cmpl
*cmpl
)
1450 u16 event_id
= le16_to_cpu(cmpl
->event_id
);
1452 /* TODO CHIMP_FW: Define event id's for link change, error etc */
1454 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE
: {
1455 u32 data1
= le32_to_cpu(cmpl
->event_data1
);
1456 struct bnxt_link_info
*link_info
= &bp
->link_info
;
1459 goto async_event_process_exit
;
1460 if (data1
& 0x20000) {
1461 u16 fw_speed
= link_info
->force_link_speed
;
1462 u32 speed
= bnxt_fw_to_ethtool_speed(fw_speed
);
1464 netdev_warn(bp
->dev
, "Link speed %d no longer supported\n",
1469 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE
:
1470 set_bit(BNXT_LINK_CHNG_SP_EVENT
, &bp
->sp_event
);
1472 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD
:
1473 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT
, &bp
->sp_event
);
1475 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED
: {
1476 u32 data1
= le32_to_cpu(cmpl
->event_data1
);
1477 u16 port_id
= BNXT_GET_EVENT_PORT(data1
);
1482 if (bp
->pf
.port_id
!= port_id
)
1485 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT
, &bp
->sp_event
);
1488 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE
:
1490 goto async_event_process_exit
;
1491 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT
, &bp
->sp_event
);
1494 netdev_err(bp
->dev
, "unhandled ASYNC event (id 0x%x)\n",
1496 goto async_event_process_exit
;
1498 schedule_work(&bp
->sp_task
);
1499 async_event_process_exit
:
1503 static int bnxt_hwrm_handler(struct bnxt
*bp
, struct tx_cmp
*txcmp
)
1505 u16 cmpl_type
= TX_CMP_TYPE(txcmp
), vf_id
, seq_id
;
1506 struct hwrm_cmpl
*h_cmpl
= (struct hwrm_cmpl
*)txcmp
;
1507 struct hwrm_fwd_req_cmpl
*fwd_req_cmpl
=
1508 (struct hwrm_fwd_req_cmpl
*)txcmp
;
1510 switch (cmpl_type
) {
1511 case CMPL_BASE_TYPE_HWRM_DONE
:
1512 seq_id
= le16_to_cpu(h_cmpl
->sequence_id
);
1513 if (seq_id
== bp
->hwrm_intr_seq_id
)
1514 bp
->hwrm_intr_seq_id
= HWRM_SEQ_ID_INVALID
;
1516 netdev_err(bp
->dev
, "Invalid hwrm seq id %d\n", seq_id
);
1519 case CMPL_BASE_TYPE_HWRM_FWD_REQ
:
1520 vf_id
= le16_to_cpu(fwd_req_cmpl
->source_id
);
1522 if ((vf_id
< bp
->pf
.first_vf_id
) ||
1523 (vf_id
>= bp
->pf
.first_vf_id
+ bp
->pf
.active_vfs
)) {
1524 netdev_err(bp
->dev
, "Msg contains invalid VF id %x\n",
1529 set_bit(vf_id
- bp
->pf
.first_vf_id
, bp
->pf
.vf_event_bmap
);
1530 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT
, &bp
->sp_event
);
1531 schedule_work(&bp
->sp_task
);
1534 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT
:
1535 bnxt_async_event_process(bp
,
1536 (struct hwrm_async_event_cmpl
*)txcmp
);
1545 static irqreturn_t
bnxt_msix(int irq
, void *dev_instance
)
1547 struct bnxt_napi
*bnapi
= dev_instance
;
1548 struct bnxt
*bp
= bnapi
->bp
;
1549 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1550 u32 cons
= RING_CMP(cpr
->cp_raw_cons
);
1552 prefetch(&cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)]);
1553 napi_schedule(&bnapi
->napi
);
1557 static inline int bnxt_has_work(struct bnxt
*bp
, struct bnxt_cp_ring_info
*cpr
)
1559 u32 raw_cons
= cpr
->cp_raw_cons
;
1560 u16 cons
= RING_CMP(raw_cons
);
1561 struct tx_cmp
*txcmp
;
1563 txcmp
= &cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)];
1565 return TX_CMP_VALID(txcmp
, raw_cons
);
1568 static irqreturn_t
bnxt_inta(int irq
, void *dev_instance
)
1570 struct bnxt_napi
*bnapi
= dev_instance
;
1571 struct bnxt
*bp
= bnapi
->bp
;
1572 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1573 u32 cons
= RING_CMP(cpr
->cp_raw_cons
);
1576 prefetch(&cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)]);
1578 if (!bnxt_has_work(bp
, cpr
)) {
1579 int_status
= readl(bp
->bar0
+ BNXT_CAG_REG_LEGACY_INT_STATUS
);
1580 /* return if erroneous interrupt */
1581 if (!(int_status
& (0x10000 << cpr
->cp_ring_struct
.fw_ring_id
)))
1585 /* disable ring IRQ */
1586 BNXT_CP_DB_IRQ_DIS(cpr
->cp_doorbell
);
1588 /* Return here if interrupt is shared and is disabled. */
1589 if (unlikely(atomic_read(&bp
->intr_sem
) != 0))
1592 napi_schedule(&bnapi
->napi
);
1596 static int bnxt_poll_work(struct bnxt
*bp
, struct bnxt_napi
*bnapi
, int budget
)
1598 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1599 u32 raw_cons
= cpr
->cp_raw_cons
;
1603 bool rx_event
= false;
1604 bool agg_event
= false;
1605 struct tx_cmp
*txcmp
;
1610 cons
= RING_CMP(raw_cons
);
1611 txcmp
= &cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)];
1613 if (!TX_CMP_VALID(txcmp
, raw_cons
))
1616 /* The valid test of the entry must be done first before
1617 * reading any further.
1620 if (TX_CMP_TYPE(txcmp
) == CMP_TYPE_TX_L2_CMP
) {
1622 /* return full budget so NAPI will complete. */
1623 if (unlikely(tx_pkts
> bp
->tx_wake_thresh
))
1625 } else if ((TX_CMP_TYPE(txcmp
) & 0x30) == 0x10) {
1626 rc
= bnxt_rx_pkt(bp
, bnapi
, &raw_cons
, &agg_event
);
1627 if (likely(rc
>= 0))
1629 else if (rc
== -EBUSY
) /* partial completion */
1632 } else if (unlikely((TX_CMP_TYPE(txcmp
) ==
1633 CMPL_BASE_TYPE_HWRM_DONE
) ||
1634 (TX_CMP_TYPE(txcmp
) ==
1635 CMPL_BASE_TYPE_HWRM_FWD_REQ
) ||
1636 (TX_CMP_TYPE(txcmp
) ==
1637 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT
))) {
1638 bnxt_hwrm_handler(bp
, txcmp
);
1640 raw_cons
= NEXT_RAW_CMP(raw_cons
);
1642 if (rx_pkts
== budget
)
1646 cpr
->cp_raw_cons
= raw_cons
;
1647 /* ACK completion ring before freeing tx ring and producing new
1648 * buffers in rx/agg rings to prevent overflowing the completion
1651 BNXT_CP_DB(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
1654 bnxt_tx_int(bp
, bnapi
, tx_pkts
);
1657 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
1659 writel(DB_KEY_RX
| rxr
->rx_prod
, rxr
->rx_doorbell
);
1660 writel(DB_KEY_RX
| rxr
->rx_prod
, rxr
->rx_doorbell
);
1662 writel(DB_KEY_RX
| rxr
->rx_agg_prod
,
1663 rxr
->rx_agg_doorbell
);
1664 writel(DB_KEY_RX
| rxr
->rx_agg_prod
,
1665 rxr
->rx_agg_doorbell
);
1671 static int bnxt_poll(struct napi_struct
*napi
, int budget
)
1673 struct bnxt_napi
*bnapi
= container_of(napi
, struct bnxt_napi
, napi
);
1674 struct bnxt
*bp
= bnapi
->bp
;
1675 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1678 if (!bnxt_lock_napi(bnapi
))
1682 work_done
+= bnxt_poll_work(bp
, bnapi
, budget
- work_done
);
1684 if (work_done
>= budget
)
1687 if (!bnxt_has_work(bp
, cpr
)) {
1688 napi_complete(napi
);
1689 BNXT_CP_DB_REARM(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
1694 bnxt_unlock_napi(bnapi
);
1698 #ifdef CONFIG_NET_RX_BUSY_POLL
1699 static int bnxt_busy_poll(struct napi_struct
*napi
)
1701 struct bnxt_napi
*bnapi
= container_of(napi
, struct bnxt_napi
, napi
);
1702 struct bnxt
*bp
= bnapi
->bp
;
1703 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1704 int rx_work
, budget
= 4;
1706 if (atomic_read(&bp
->intr_sem
) != 0)
1707 return LL_FLUSH_FAILED
;
1709 if (!bnxt_lock_poll(bnapi
))
1710 return LL_FLUSH_BUSY
;
1712 rx_work
= bnxt_poll_work(bp
, bnapi
, budget
);
1714 BNXT_CP_DB_REARM(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
1716 bnxt_unlock_poll(bnapi
);
1721 static void bnxt_free_tx_skbs(struct bnxt
*bp
)
1724 struct pci_dev
*pdev
= bp
->pdev
;
1729 max_idx
= bp
->tx_nr_pages
* TX_DESC_CNT
;
1730 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
1731 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
1734 for (j
= 0; j
< max_idx
;) {
1735 struct bnxt_sw_tx_bd
*tx_buf
= &txr
->tx_buf_ring
[j
];
1736 struct sk_buff
*skb
= tx_buf
->skb
;
1746 if (tx_buf
->is_push
) {
1752 dma_unmap_single(&pdev
->dev
,
1753 dma_unmap_addr(tx_buf
, mapping
),
1757 last
= tx_buf
->nr_frags
;
1759 for (k
= 0; k
< last
; k
++, j
++) {
1760 int ring_idx
= j
& bp
->tx_ring_mask
;
1761 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[k
];
1763 tx_buf
= &txr
->tx_buf_ring
[ring_idx
];
1766 dma_unmap_addr(tx_buf
, mapping
),
1767 skb_frag_size(frag
), PCI_DMA_TODEVICE
);
1771 netdev_tx_reset_queue(netdev_get_tx_queue(bp
->dev
, i
));
1775 static void bnxt_free_rx_skbs(struct bnxt
*bp
)
1777 int i
, max_idx
, max_agg_idx
;
1778 struct pci_dev
*pdev
= bp
->pdev
;
1783 max_idx
= bp
->rx_nr_pages
* RX_DESC_CNT
;
1784 max_agg_idx
= bp
->rx_agg_nr_pages
* RX_DESC_CNT
;
1785 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
1786 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
1790 for (j
= 0; j
< MAX_TPA
; j
++) {
1791 struct bnxt_tpa_info
*tpa_info
=
1793 u8
*data
= tpa_info
->data
;
1800 dma_unmap_addr(tpa_info
, mapping
),
1801 bp
->rx_buf_use_size
,
1802 PCI_DMA_FROMDEVICE
);
1804 tpa_info
->data
= NULL
;
1810 for (j
= 0; j
< max_idx
; j
++) {
1811 struct bnxt_sw_rx_bd
*rx_buf
= &rxr
->rx_buf_ring
[j
];
1812 u8
*data
= rx_buf
->data
;
1817 dma_unmap_single(&pdev
->dev
,
1818 dma_unmap_addr(rx_buf
, mapping
),
1819 bp
->rx_buf_use_size
,
1820 PCI_DMA_FROMDEVICE
);
1822 rx_buf
->data
= NULL
;
1827 for (j
= 0; j
< max_agg_idx
; j
++) {
1828 struct bnxt_sw_rx_agg_bd
*rx_agg_buf
=
1829 &rxr
->rx_agg_ring
[j
];
1830 struct page
*page
= rx_agg_buf
->page
;
1835 dma_unmap_page(&pdev
->dev
,
1836 dma_unmap_addr(rx_agg_buf
, mapping
),
1837 BNXT_RX_PAGE_SIZE
, PCI_DMA_FROMDEVICE
);
1839 rx_agg_buf
->page
= NULL
;
1840 __clear_bit(j
, rxr
->rx_agg_bmap
);
1845 __free_page(rxr
->rx_page
);
1846 rxr
->rx_page
= NULL
;
1851 static void bnxt_free_skbs(struct bnxt
*bp
)
1853 bnxt_free_tx_skbs(bp
);
1854 bnxt_free_rx_skbs(bp
);
1857 static void bnxt_free_ring(struct bnxt
*bp
, struct bnxt_ring_struct
*ring
)
1859 struct pci_dev
*pdev
= bp
->pdev
;
1862 for (i
= 0; i
< ring
->nr_pages
; i
++) {
1863 if (!ring
->pg_arr
[i
])
1866 dma_free_coherent(&pdev
->dev
, ring
->page_size
,
1867 ring
->pg_arr
[i
], ring
->dma_arr
[i
]);
1869 ring
->pg_arr
[i
] = NULL
;
1872 dma_free_coherent(&pdev
->dev
, ring
->nr_pages
* 8,
1873 ring
->pg_tbl
, ring
->pg_tbl_map
);
1874 ring
->pg_tbl
= NULL
;
1876 if (ring
->vmem_size
&& *ring
->vmem
) {
1882 static int bnxt_alloc_ring(struct bnxt
*bp
, struct bnxt_ring_struct
*ring
)
1885 struct pci_dev
*pdev
= bp
->pdev
;
1887 if (ring
->nr_pages
> 1) {
1888 ring
->pg_tbl
= dma_alloc_coherent(&pdev
->dev
,
1896 for (i
= 0; i
< ring
->nr_pages
; i
++) {
1897 ring
->pg_arr
[i
] = dma_alloc_coherent(&pdev
->dev
,
1901 if (!ring
->pg_arr
[i
])
1904 if (ring
->nr_pages
> 1)
1905 ring
->pg_tbl
[i
] = cpu_to_le64(ring
->dma_arr
[i
]);
1908 if (ring
->vmem_size
) {
1909 *ring
->vmem
= vzalloc(ring
->vmem_size
);
1916 static void bnxt_free_rx_rings(struct bnxt
*bp
)
1923 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
1924 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
1925 struct bnxt_ring_struct
*ring
;
1930 kfree(rxr
->rx_agg_bmap
);
1931 rxr
->rx_agg_bmap
= NULL
;
1933 ring
= &rxr
->rx_ring_struct
;
1934 bnxt_free_ring(bp
, ring
);
1936 ring
= &rxr
->rx_agg_ring_struct
;
1937 bnxt_free_ring(bp
, ring
);
1941 static int bnxt_alloc_rx_rings(struct bnxt
*bp
)
1943 int i
, rc
, agg_rings
= 0, tpa_rings
= 0;
1948 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
)
1951 if (bp
->flags
& BNXT_FLAG_TPA
)
1954 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
1955 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
1956 struct bnxt_ring_struct
*ring
;
1958 ring
= &rxr
->rx_ring_struct
;
1960 rc
= bnxt_alloc_ring(bp
, ring
);
1967 ring
= &rxr
->rx_agg_ring_struct
;
1968 rc
= bnxt_alloc_ring(bp
, ring
);
1972 rxr
->rx_agg_bmap_size
= bp
->rx_agg_ring_mask
+ 1;
1973 mem_size
= rxr
->rx_agg_bmap_size
/ 8;
1974 rxr
->rx_agg_bmap
= kzalloc(mem_size
, GFP_KERNEL
);
1975 if (!rxr
->rx_agg_bmap
)
1979 rxr
->rx_tpa
= kcalloc(MAX_TPA
,
1980 sizeof(struct bnxt_tpa_info
),
1990 static void bnxt_free_tx_rings(struct bnxt
*bp
)
1993 struct pci_dev
*pdev
= bp
->pdev
;
1998 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
1999 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
2000 struct bnxt_ring_struct
*ring
;
2003 dma_free_coherent(&pdev
->dev
, bp
->tx_push_size
,
2004 txr
->tx_push
, txr
->tx_push_mapping
);
2005 txr
->tx_push
= NULL
;
2008 ring
= &txr
->tx_ring_struct
;
2010 bnxt_free_ring(bp
, ring
);
2014 static int bnxt_alloc_tx_rings(struct bnxt
*bp
)
2017 struct pci_dev
*pdev
= bp
->pdev
;
2019 bp
->tx_push_size
= 0;
2020 if (bp
->tx_push_thresh
) {
2023 push_size
= L1_CACHE_ALIGN(sizeof(struct tx_push_bd
) +
2024 bp
->tx_push_thresh
);
2026 if (push_size
> 256) {
2028 bp
->tx_push_thresh
= 0;
2031 bp
->tx_push_size
= push_size
;
2034 for (i
= 0, j
= 0; i
< bp
->tx_nr_rings
; i
++) {
2035 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
2036 struct bnxt_ring_struct
*ring
;
2038 ring
= &txr
->tx_ring_struct
;
2040 rc
= bnxt_alloc_ring(bp
, ring
);
2044 if (bp
->tx_push_size
) {
2047 /* One pre-allocated DMA buffer to backup
2050 txr
->tx_push
= dma_alloc_coherent(&pdev
->dev
,
2052 &txr
->tx_push_mapping
,
2058 mapping
= txr
->tx_push_mapping
+
2059 sizeof(struct tx_push_bd
);
2060 txr
->data_mapping
= cpu_to_le64(mapping
);
2062 memset(txr
->tx_push
, 0, sizeof(struct tx_push_bd
));
2064 ring
->queue_id
= bp
->q_info
[j
].queue_id
;
2065 if (i
% bp
->tx_nr_rings_per_tc
== (bp
->tx_nr_rings_per_tc
- 1))
2071 static void bnxt_free_cp_rings(struct bnxt
*bp
)
2078 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2079 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2080 struct bnxt_cp_ring_info
*cpr
;
2081 struct bnxt_ring_struct
*ring
;
2086 cpr
= &bnapi
->cp_ring
;
2087 ring
= &cpr
->cp_ring_struct
;
2089 bnxt_free_ring(bp
, ring
);
2093 static int bnxt_alloc_cp_rings(struct bnxt
*bp
)
2097 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2098 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2099 struct bnxt_cp_ring_info
*cpr
;
2100 struct bnxt_ring_struct
*ring
;
2105 cpr
= &bnapi
->cp_ring
;
2106 ring
= &cpr
->cp_ring_struct
;
2108 rc
= bnxt_alloc_ring(bp
, ring
);
2115 static void bnxt_init_ring_struct(struct bnxt
*bp
)
2119 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2120 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2121 struct bnxt_cp_ring_info
*cpr
;
2122 struct bnxt_rx_ring_info
*rxr
;
2123 struct bnxt_tx_ring_info
*txr
;
2124 struct bnxt_ring_struct
*ring
;
2129 cpr
= &bnapi
->cp_ring
;
2130 ring
= &cpr
->cp_ring_struct
;
2131 ring
->nr_pages
= bp
->cp_nr_pages
;
2132 ring
->page_size
= HW_CMPD_RING_SIZE
;
2133 ring
->pg_arr
= (void **)cpr
->cp_desc_ring
;
2134 ring
->dma_arr
= cpr
->cp_desc_mapping
;
2135 ring
->vmem_size
= 0;
2137 rxr
= bnapi
->rx_ring
;
2141 ring
= &rxr
->rx_ring_struct
;
2142 ring
->nr_pages
= bp
->rx_nr_pages
;
2143 ring
->page_size
= HW_RXBD_RING_SIZE
;
2144 ring
->pg_arr
= (void **)rxr
->rx_desc_ring
;
2145 ring
->dma_arr
= rxr
->rx_desc_mapping
;
2146 ring
->vmem_size
= SW_RXBD_RING_SIZE
* bp
->rx_nr_pages
;
2147 ring
->vmem
= (void **)&rxr
->rx_buf_ring
;
2149 ring
= &rxr
->rx_agg_ring_struct
;
2150 ring
->nr_pages
= bp
->rx_agg_nr_pages
;
2151 ring
->page_size
= HW_RXBD_RING_SIZE
;
2152 ring
->pg_arr
= (void **)rxr
->rx_agg_desc_ring
;
2153 ring
->dma_arr
= rxr
->rx_agg_desc_mapping
;
2154 ring
->vmem_size
= SW_RXBD_AGG_RING_SIZE
* bp
->rx_agg_nr_pages
;
2155 ring
->vmem
= (void **)&rxr
->rx_agg_ring
;
2158 txr
= bnapi
->tx_ring
;
2162 ring
= &txr
->tx_ring_struct
;
2163 ring
->nr_pages
= bp
->tx_nr_pages
;
2164 ring
->page_size
= HW_RXBD_RING_SIZE
;
2165 ring
->pg_arr
= (void **)txr
->tx_desc_ring
;
2166 ring
->dma_arr
= txr
->tx_desc_mapping
;
2167 ring
->vmem_size
= SW_TXBD_RING_SIZE
* bp
->tx_nr_pages
;
2168 ring
->vmem
= (void **)&txr
->tx_buf_ring
;
2172 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct
*ring
, u32 type
)
2176 struct rx_bd
**rx_buf_ring
;
2178 rx_buf_ring
= (struct rx_bd
**)ring
->pg_arr
;
2179 for (i
= 0, prod
= 0; i
< ring
->nr_pages
; i
++) {
2183 rxbd
= rx_buf_ring
[i
];
2187 for (j
= 0; j
< RX_DESC_CNT
; j
++, rxbd
++, prod
++) {
2188 rxbd
->rx_bd_len_flags_type
= cpu_to_le32(type
);
2189 rxbd
->rx_bd_opaque
= prod
;
2194 static int bnxt_init_one_rx_ring(struct bnxt
*bp
, int ring_nr
)
2196 struct net_device
*dev
= bp
->dev
;
2197 struct bnxt_rx_ring_info
*rxr
;
2198 struct bnxt_ring_struct
*ring
;
2202 type
= (bp
->rx_buf_use_size
<< RX_BD_LEN_SHIFT
) |
2203 RX_BD_TYPE_RX_PACKET_BD
| RX_BD_FLAGS_EOP
;
2205 if (NET_IP_ALIGN
== 2)
2206 type
|= RX_BD_FLAGS_SOP
;
2208 rxr
= &bp
->rx_ring
[ring_nr
];
2209 ring
= &rxr
->rx_ring_struct
;
2210 bnxt_init_rxbd_pages(ring
, type
);
2212 prod
= rxr
->rx_prod
;
2213 for (i
= 0; i
< bp
->rx_ring_size
; i
++) {
2214 if (bnxt_alloc_rx_data(bp
, rxr
, prod
, GFP_KERNEL
) != 0) {
2215 netdev_warn(dev
, "init'ed rx ring %d with %d/%d skbs only\n",
2216 ring_nr
, i
, bp
->rx_ring_size
);
2219 prod
= NEXT_RX(prod
);
2221 rxr
->rx_prod
= prod
;
2222 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
2224 ring
= &rxr
->rx_agg_ring_struct
;
2225 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
2227 if (!(bp
->flags
& BNXT_FLAG_AGG_RINGS
))
2230 type
= ((u32
)BNXT_RX_PAGE_SIZE
<< RX_BD_LEN_SHIFT
) |
2231 RX_BD_TYPE_RX_AGG_BD
| RX_BD_FLAGS_SOP
;
2233 bnxt_init_rxbd_pages(ring
, type
);
2235 prod
= rxr
->rx_agg_prod
;
2236 for (i
= 0; i
< bp
->rx_agg_ring_size
; i
++) {
2237 if (bnxt_alloc_rx_page(bp
, rxr
, prod
, GFP_KERNEL
) != 0) {
2238 netdev_warn(dev
, "init'ed rx ring %d with %d/%d pages only\n",
2239 ring_nr
, i
, bp
->rx_ring_size
);
2242 prod
= NEXT_RX_AGG(prod
);
2244 rxr
->rx_agg_prod
= prod
;
2246 if (bp
->flags
& BNXT_FLAG_TPA
) {
2251 for (i
= 0; i
< MAX_TPA
; i
++) {
2252 data
= __bnxt_alloc_rx_data(bp
, &mapping
,
2257 rxr
->rx_tpa
[i
].data
= data
;
2258 rxr
->rx_tpa
[i
].mapping
= mapping
;
2261 netdev_err(bp
->dev
, "No resource allocated for LRO/GRO\n");
2269 static int bnxt_init_rx_rings(struct bnxt
*bp
)
2273 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
2274 rc
= bnxt_init_one_rx_ring(bp
, i
);
2282 static int bnxt_init_tx_rings(struct bnxt
*bp
)
2286 bp
->tx_wake_thresh
= max_t(int, bp
->tx_ring_size
/ 2,
2289 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
2290 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
2291 struct bnxt_ring_struct
*ring
= &txr
->tx_ring_struct
;
2293 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
2299 static void bnxt_free_ring_grps(struct bnxt
*bp
)
2301 kfree(bp
->grp_info
);
2302 bp
->grp_info
= NULL
;
2305 static int bnxt_init_ring_grps(struct bnxt
*bp
, bool irq_re_init
)
2310 bp
->grp_info
= kcalloc(bp
->cp_nr_rings
,
2311 sizeof(struct bnxt_ring_grp_info
),
2316 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2318 bp
->grp_info
[i
].fw_stats_ctx
= INVALID_HW_RING_ID
;
2319 bp
->grp_info
[i
].fw_grp_id
= INVALID_HW_RING_ID
;
2320 bp
->grp_info
[i
].rx_fw_ring_id
= INVALID_HW_RING_ID
;
2321 bp
->grp_info
[i
].agg_fw_ring_id
= INVALID_HW_RING_ID
;
2322 bp
->grp_info
[i
].cp_fw_ring_id
= INVALID_HW_RING_ID
;
2327 static void bnxt_free_vnics(struct bnxt
*bp
)
2329 kfree(bp
->vnic_info
);
2330 bp
->vnic_info
= NULL
;
2334 static int bnxt_alloc_vnics(struct bnxt
*bp
)
2338 #ifdef CONFIG_RFS_ACCEL
2339 if (bp
->flags
& BNXT_FLAG_RFS
)
2340 num_vnics
+= bp
->rx_nr_rings
;
2343 bp
->vnic_info
= kcalloc(num_vnics
, sizeof(struct bnxt_vnic_info
),
2348 bp
->nr_vnics
= num_vnics
;
2352 static void bnxt_init_vnics(struct bnxt
*bp
)
2356 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
2357 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[i
];
2359 vnic
->fw_vnic_id
= INVALID_HW_RING_ID
;
2360 vnic
->fw_rss_cos_lb_ctx
= INVALID_HW_RING_ID
;
2361 vnic
->fw_l2_ctx_id
= INVALID_HW_RING_ID
;
2363 if (bp
->vnic_info
[i
].rss_hash_key
) {
2365 prandom_bytes(vnic
->rss_hash_key
,
2368 memcpy(vnic
->rss_hash_key
,
2369 bp
->vnic_info
[0].rss_hash_key
,
2375 static int bnxt_calc_nr_ring_pages(u32 ring_size
, int desc_per_pg
)
2379 pages
= ring_size
/ desc_per_pg
;
2386 while (pages
& (pages
- 1))
2392 static void bnxt_set_tpa_flags(struct bnxt
*bp
)
2394 bp
->flags
&= ~BNXT_FLAG_TPA
;
2395 if (bp
->dev
->features
& NETIF_F_LRO
)
2396 bp
->flags
|= BNXT_FLAG_LRO
;
2397 if (bp
->dev
->features
& NETIF_F_GRO
)
2398 bp
->flags
|= BNXT_FLAG_GRO
;
2401 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2404 void bnxt_set_ring_params(struct bnxt
*bp
)
2406 u32 ring_size
, rx_size
, rx_space
;
2407 u32 agg_factor
= 0, agg_ring_size
= 0;
2409 /* 8 for CRC and VLAN */
2410 rx_size
= SKB_DATA_ALIGN(bp
->dev
->mtu
+ ETH_HLEN
+ NET_IP_ALIGN
+ 8);
2412 rx_space
= rx_size
+ NET_SKB_PAD
+
2413 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
2415 bp
->rx_copy_thresh
= BNXT_RX_COPY_THRESH
;
2416 ring_size
= bp
->rx_ring_size
;
2417 bp
->rx_agg_ring_size
= 0;
2418 bp
->rx_agg_nr_pages
= 0;
2420 if (bp
->flags
& BNXT_FLAG_TPA
)
2421 agg_factor
= min_t(u32
, 4, 65536 / BNXT_RX_PAGE_SIZE
);
2423 bp
->flags
&= ~BNXT_FLAG_JUMBO
;
2424 if (rx_space
> PAGE_SIZE
) {
2427 bp
->flags
|= BNXT_FLAG_JUMBO
;
2428 jumbo_factor
= PAGE_ALIGN(bp
->dev
->mtu
- 40) >> PAGE_SHIFT
;
2429 if (jumbo_factor
> agg_factor
)
2430 agg_factor
= jumbo_factor
;
2432 agg_ring_size
= ring_size
* agg_factor
;
2434 if (agg_ring_size
) {
2435 bp
->rx_agg_nr_pages
= bnxt_calc_nr_ring_pages(agg_ring_size
,
2437 if (bp
->rx_agg_nr_pages
> MAX_RX_AGG_PAGES
) {
2438 u32 tmp
= agg_ring_size
;
2440 bp
->rx_agg_nr_pages
= MAX_RX_AGG_PAGES
;
2441 agg_ring_size
= MAX_RX_AGG_PAGES
* RX_DESC_CNT
- 1;
2442 netdev_warn(bp
->dev
, "rx agg ring size %d reduced to %d.\n",
2443 tmp
, agg_ring_size
);
2445 bp
->rx_agg_ring_size
= agg_ring_size
;
2446 bp
->rx_agg_ring_mask
= (bp
->rx_agg_nr_pages
* RX_DESC_CNT
) - 1;
2447 rx_size
= SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH
+ NET_IP_ALIGN
);
2448 rx_space
= rx_size
+ NET_SKB_PAD
+
2449 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
2452 bp
->rx_buf_use_size
= rx_size
;
2453 bp
->rx_buf_size
= rx_space
;
2455 bp
->rx_nr_pages
= bnxt_calc_nr_ring_pages(ring_size
, RX_DESC_CNT
);
2456 bp
->rx_ring_mask
= (bp
->rx_nr_pages
* RX_DESC_CNT
) - 1;
2458 ring_size
= bp
->tx_ring_size
;
2459 bp
->tx_nr_pages
= bnxt_calc_nr_ring_pages(ring_size
, TX_DESC_CNT
);
2460 bp
->tx_ring_mask
= (bp
->tx_nr_pages
* TX_DESC_CNT
) - 1;
2462 ring_size
= bp
->rx_ring_size
* (2 + agg_factor
) + bp
->tx_ring_size
;
2463 bp
->cp_ring_size
= ring_size
;
2465 bp
->cp_nr_pages
= bnxt_calc_nr_ring_pages(ring_size
, CP_DESC_CNT
);
2466 if (bp
->cp_nr_pages
> MAX_CP_PAGES
) {
2467 bp
->cp_nr_pages
= MAX_CP_PAGES
;
2468 bp
->cp_ring_size
= MAX_CP_PAGES
* CP_DESC_CNT
- 1;
2469 netdev_warn(bp
->dev
, "completion ring size %d reduced to %d.\n",
2470 ring_size
, bp
->cp_ring_size
);
2472 bp
->cp_bit
= bp
->cp_nr_pages
* CP_DESC_CNT
;
2473 bp
->cp_ring_mask
= bp
->cp_bit
- 1;
2476 static void bnxt_free_vnic_attributes(struct bnxt
*bp
)
2479 struct bnxt_vnic_info
*vnic
;
2480 struct pci_dev
*pdev
= bp
->pdev
;
2485 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
2486 vnic
= &bp
->vnic_info
[i
];
2488 kfree(vnic
->fw_grp_ids
);
2489 vnic
->fw_grp_ids
= NULL
;
2491 kfree(vnic
->uc_list
);
2492 vnic
->uc_list
= NULL
;
2494 if (vnic
->mc_list
) {
2495 dma_free_coherent(&pdev
->dev
, vnic
->mc_list_size
,
2496 vnic
->mc_list
, vnic
->mc_list_mapping
);
2497 vnic
->mc_list
= NULL
;
2500 if (vnic
->rss_table
) {
2501 dma_free_coherent(&pdev
->dev
, PAGE_SIZE
,
2503 vnic
->rss_table_dma_addr
);
2504 vnic
->rss_table
= NULL
;
2507 vnic
->rss_hash_key
= NULL
;
2512 static int bnxt_alloc_vnic_attributes(struct bnxt
*bp
)
2514 int i
, rc
= 0, size
;
2515 struct bnxt_vnic_info
*vnic
;
2516 struct pci_dev
*pdev
= bp
->pdev
;
2519 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
2520 vnic
= &bp
->vnic_info
[i
];
2522 if (vnic
->flags
& BNXT_VNIC_UCAST_FLAG
) {
2523 int mem_size
= (BNXT_MAX_UC_ADDRS
- 1) * ETH_ALEN
;
2526 vnic
->uc_list
= kmalloc(mem_size
, GFP_KERNEL
);
2527 if (!vnic
->uc_list
) {
2534 if (vnic
->flags
& BNXT_VNIC_MCAST_FLAG
) {
2535 vnic
->mc_list_size
= BNXT_MAX_MC_ADDRS
* ETH_ALEN
;
2537 dma_alloc_coherent(&pdev
->dev
,
2539 &vnic
->mc_list_mapping
,
2541 if (!vnic
->mc_list
) {
2547 if (vnic
->flags
& BNXT_VNIC_RSS_FLAG
)
2548 max_rings
= bp
->rx_nr_rings
;
2552 vnic
->fw_grp_ids
= kcalloc(max_rings
, sizeof(u16
), GFP_KERNEL
);
2553 if (!vnic
->fw_grp_ids
) {
2558 /* Allocate rss table and hash key */
2559 vnic
->rss_table
= dma_alloc_coherent(&pdev
->dev
, PAGE_SIZE
,
2560 &vnic
->rss_table_dma_addr
,
2562 if (!vnic
->rss_table
) {
2567 size
= L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE
* sizeof(u16
));
2569 vnic
->rss_hash_key
= ((void *)vnic
->rss_table
) + size
;
2570 vnic
->rss_hash_key_dma_addr
= vnic
->rss_table_dma_addr
+ size
;
2578 static void bnxt_free_hwrm_resources(struct bnxt
*bp
)
2580 struct pci_dev
*pdev
= bp
->pdev
;
2582 dma_free_coherent(&pdev
->dev
, PAGE_SIZE
, bp
->hwrm_cmd_resp_addr
,
2583 bp
->hwrm_cmd_resp_dma_addr
);
2585 bp
->hwrm_cmd_resp_addr
= NULL
;
2586 if (bp
->hwrm_dbg_resp_addr
) {
2587 dma_free_coherent(&pdev
->dev
, HWRM_DBG_REG_BUF_SIZE
,
2588 bp
->hwrm_dbg_resp_addr
,
2589 bp
->hwrm_dbg_resp_dma_addr
);
2591 bp
->hwrm_dbg_resp_addr
= NULL
;
2595 static int bnxt_alloc_hwrm_resources(struct bnxt
*bp
)
2597 struct pci_dev
*pdev
= bp
->pdev
;
2599 bp
->hwrm_cmd_resp_addr
= dma_alloc_coherent(&pdev
->dev
, PAGE_SIZE
,
2600 &bp
->hwrm_cmd_resp_dma_addr
,
2602 if (!bp
->hwrm_cmd_resp_addr
)
2604 bp
->hwrm_dbg_resp_addr
= dma_alloc_coherent(&pdev
->dev
,
2605 HWRM_DBG_REG_BUF_SIZE
,
2606 &bp
->hwrm_dbg_resp_dma_addr
,
2608 if (!bp
->hwrm_dbg_resp_addr
)
2609 netdev_warn(bp
->dev
, "fail to alloc debug register dma mem\n");
2614 static void bnxt_free_stats(struct bnxt
*bp
)
2617 struct pci_dev
*pdev
= bp
->pdev
;
2619 if (bp
->hw_rx_port_stats
) {
2620 dma_free_coherent(&pdev
->dev
, bp
->hw_port_stats_size
,
2621 bp
->hw_rx_port_stats
,
2622 bp
->hw_rx_port_stats_map
);
2623 bp
->hw_rx_port_stats
= NULL
;
2624 bp
->flags
&= ~BNXT_FLAG_PORT_STATS
;
2630 size
= sizeof(struct ctx_hw_stats
);
2632 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2633 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2634 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
2636 if (cpr
->hw_stats
) {
2637 dma_free_coherent(&pdev
->dev
, size
, cpr
->hw_stats
,
2639 cpr
->hw_stats
= NULL
;
2644 static int bnxt_alloc_stats(struct bnxt
*bp
)
2647 struct pci_dev
*pdev
= bp
->pdev
;
2649 size
= sizeof(struct ctx_hw_stats
);
2651 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2652 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2653 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
2655 cpr
->hw_stats
= dma_alloc_coherent(&pdev
->dev
, size
,
2661 cpr
->hw_stats_ctx_id
= INVALID_STATS_CTX_ID
;
2665 bp
->hw_port_stats_size
= sizeof(struct rx_port_stats
) +
2666 sizeof(struct tx_port_stats
) + 1024;
2668 bp
->hw_rx_port_stats
=
2669 dma_alloc_coherent(&pdev
->dev
, bp
->hw_port_stats_size
,
2670 &bp
->hw_rx_port_stats_map
,
2672 if (!bp
->hw_rx_port_stats
)
2675 bp
->hw_tx_port_stats
= (void *)(bp
->hw_rx_port_stats
+ 1) +
2677 bp
->hw_tx_port_stats_map
= bp
->hw_rx_port_stats_map
+
2678 sizeof(struct rx_port_stats
) + 512;
2679 bp
->flags
|= BNXT_FLAG_PORT_STATS
;
2684 static void bnxt_clear_ring_indices(struct bnxt
*bp
)
2691 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2692 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2693 struct bnxt_cp_ring_info
*cpr
;
2694 struct bnxt_rx_ring_info
*rxr
;
2695 struct bnxt_tx_ring_info
*txr
;
2700 cpr
= &bnapi
->cp_ring
;
2701 cpr
->cp_raw_cons
= 0;
2703 txr
= bnapi
->tx_ring
;
2709 rxr
= bnapi
->rx_ring
;
2712 rxr
->rx_agg_prod
= 0;
2713 rxr
->rx_sw_agg_prod
= 0;
2714 rxr
->rx_next_cons
= 0;
2719 static void bnxt_free_ntp_fltrs(struct bnxt
*bp
, bool irq_reinit
)
2721 #ifdef CONFIG_RFS_ACCEL
2724 /* Under rtnl_lock and all our NAPIs have been disabled. It's
2725 * safe to delete the hash table.
2727 for (i
= 0; i
< BNXT_NTP_FLTR_HASH_SIZE
; i
++) {
2728 struct hlist_head
*head
;
2729 struct hlist_node
*tmp
;
2730 struct bnxt_ntuple_filter
*fltr
;
2732 head
= &bp
->ntp_fltr_hash_tbl
[i
];
2733 hlist_for_each_entry_safe(fltr
, tmp
, head
, hash
) {
2734 hlist_del(&fltr
->hash
);
2739 kfree(bp
->ntp_fltr_bmap
);
2740 bp
->ntp_fltr_bmap
= NULL
;
2742 bp
->ntp_fltr_count
= 0;
2746 static int bnxt_alloc_ntp_fltrs(struct bnxt
*bp
)
2748 #ifdef CONFIG_RFS_ACCEL
2751 if (!(bp
->flags
& BNXT_FLAG_RFS
))
2754 for (i
= 0; i
< BNXT_NTP_FLTR_HASH_SIZE
; i
++)
2755 INIT_HLIST_HEAD(&bp
->ntp_fltr_hash_tbl
[i
]);
2757 bp
->ntp_fltr_count
= 0;
2758 bp
->ntp_fltr_bmap
= kzalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR
),
2761 if (!bp
->ntp_fltr_bmap
)
2770 static void bnxt_free_mem(struct bnxt
*bp
, bool irq_re_init
)
2772 bnxt_free_vnic_attributes(bp
);
2773 bnxt_free_tx_rings(bp
);
2774 bnxt_free_rx_rings(bp
);
2775 bnxt_free_cp_rings(bp
);
2776 bnxt_free_ntp_fltrs(bp
, irq_re_init
);
2778 bnxt_free_stats(bp
);
2779 bnxt_free_ring_grps(bp
);
2780 bnxt_free_vnics(bp
);
2788 bnxt_clear_ring_indices(bp
);
2792 static int bnxt_alloc_mem(struct bnxt
*bp
, bool irq_re_init
)
2794 int i
, j
, rc
, size
, arr_size
;
2798 /* Allocate bnapi mem pointer array and mem block for
2801 arr_size
= L1_CACHE_ALIGN(sizeof(struct bnxt_napi
*) *
2803 size
= L1_CACHE_ALIGN(sizeof(struct bnxt_napi
));
2804 bnapi
= kzalloc(arr_size
+ size
* bp
->cp_nr_rings
, GFP_KERNEL
);
2810 for (i
= 0; i
< bp
->cp_nr_rings
; i
++, bnapi
+= size
) {
2811 bp
->bnapi
[i
] = bnapi
;
2812 bp
->bnapi
[i
]->index
= i
;
2813 bp
->bnapi
[i
]->bp
= bp
;
2816 bp
->rx_ring
= kcalloc(bp
->rx_nr_rings
,
2817 sizeof(struct bnxt_rx_ring_info
),
2822 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
2823 bp
->rx_ring
[i
].bnapi
= bp
->bnapi
[i
];
2824 bp
->bnapi
[i
]->rx_ring
= &bp
->rx_ring
[i
];
2827 bp
->tx_ring
= kcalloc(bp
->tx_nr_rings
,
2828 sizeof(struct bnxt_tx_ring_info
),
2833 if (bp
->flags
& BNXT_FLAG_SHARED_RINGS
)
2836 j
= bp
->rx_nr_rings
;
2838 for (i
= 0; i
< bp
->tx_nr_rings
; i
++, j
++) {
2839 bp
->tx_ring
[i
].bnapi
= bp
->bnapi
[j
];
2840 bp
->bnapi
[j
]->tx_ring
= &bp
->tx_ring
[i
];
2843 rc
= bnxt_alloc_stats(bp
);
2847 rc
= bnxt_alloc_ntp_fltrs(bp
);
2851 rc
= bnxt_alloc_vnics(bp
);
2856 bnxt_init_ring_struct(bp
);
2858 rc
= bnxt_alloc_rx_rings(bp
);
2862 rc
= bnxt_alloc_tx_rings(bp
);
2866 rc
= bnxt_alloc_cp_rings(bp
);
2870 bp
->vnic_info
[0].flags
|= BNXT_VNIC_RSS_FLAG
| BNXT_VNIC_MCAST_FLAG
|
2871 BNXT_VNIC_UCAST_FLAG
;
2872 rc
= bnxt_alloc_vnic_attributes(bp
);
2878 bnxt_free_mem(bp
, true);
2882 void bnxt_hwrm_cmd_hdr_init(struct bnxt
*bp
, void *request
, u16 req_type
,
2883 u16 cmpl_ring
, u16 target_id
)
2885 struct input
*req
= request
;
2887 req
->req_type
= cpu_to_le16(req_type
);
2888 req
->cmpl_ring
= cpu_to_le16(cmpl_ring
);
2889 req
->target_id
= cpu_to_le16(target_id
);
2890 req
->resp_addr
= cpu_to_le64(bp
->hwrm_cmd_resp_dma_addr
);
2893 static int bnxt_hwrm_do_send_msg(struct bnxt
*bp
, void *msg
, u32 msg_len
,
2894 int timeout
, bool silent
)
2896 int i
, intr_process
, rc
, tmo_count
;
2897 struct input
*req
= msg
;
2899 __le32
*resp_len
, *valid
;
2900 u16 cp_ring_id
, len
= 0;
2901 struct hwrm_err_output
*resp
= bp
->hwrm_cmd_resp_addr
;
2903 req
->seq_id
= cpu_to_le16(bp
->hwrm_cmd_seq
++);
2904 memset(resp
, 0, PAGE_SIZE
);
2905 cp_ring_id
= le16_to_cpu(req
->cmpl_ring
);
2906 intr_process
= (cp_ring_id
== INVALID_HW_RING_ID
) ? 0 : 1;
2908 /* Write request msg to hwrm channel */
2909 __iowrite32_copy(bp
->bar0
, data
, msg_len
/ 4);
2911 for (i
= msg_len
; i
< BNXT_HWRM_MAX_REQ_LEN
; i
+= 4)
2912 writel(0, bp
->bar0
+ i
);
2914 /* currently supports only one outstanding message */
2916 bp
->hwrm_intr_seq_id
= le16_to_cpu(req
->seq_id
);
2918 /* Ring channel doorbell */
2919 writel(1, bp
->bar0
+ 0x100);
2922 timeout
= DFLT_HWRM_CMD_TIMEOUT
;
2925 tmo_count
= timeout
* 40;
2927 /* Wait until hwrm response cmpl interrupt is processed */
2928 while (bp
->hwrm_intr_seq_id
!= HWRM_SEQ_ID_INVALID
&&
2930 usleep_range(25, 40);
2933 if (bp
->hwrm_intr_seq_id
!= HWRM_SEQ_ID_INVALID
) {
2934 netdev_err(bp
->dev
, "Resp cmpl intr err msg: 0x%x\n",
2935 le16_to_cpu(req
->req_type
));
2939 /* Check if response len is updated */
2940 resp_len
= bp
->hwrm_cmd_resp_addr
+ HWRM_RESP_LEN_OFFSET
;
2941 for (i
= 0; i
< tmo_count
; i
++) {
2942 len
= (le32_to_cpu(*resp_len
) & HWRM_RESP_LEN_MASK
) >>
2946 usleep_range(25, 40);
2949 if (i
>= tmo_count
) {
2950 netdev_err(bp
->dev
, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
2951 timeout
, le16_to_cpu(req
->req_type
),
2952 le16_to_cpu(req
->seq_id
), len
);
2956 /* Last word of resp contains valid bit */
2957 valid
= bp
->hwrm_cmd_resp_addr
+ len
- 4;
2958 for (i
= 0; i
< 5; i
++) {
2959 if (le32_to_cpu(*valid
) & HWRM_RESP_VALID_MASK
)
2965 netdev_err(bp
->dev
, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
2966 timeout
, le16_to_cpu(req
->req_type
),
2967 le16_to_cpu(req
->seq_id
), len
, *valid
);
2972 rc
= le16_to_cpu(resp
->error_code
);
2974 netdev_err(bp
->dev
, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
2975 le16_to_cpu(resp
->req_type
),
2976 le16_to_cpu(resp
->seq_id
), rc
);
2980 int _hwrm_send_message(struct bnxt
*bp
, void *msg
, u32 msg_len
, int timeout
)
2982 return bnxt_hwrm_do_send_msg(bp
, msg
, msg_len
, timeout
, false);
2985 int hwrm_send_message(struct bnxt
*bp
, void *msg
, u32 msg_len
, int timeout
)
2989 mutex_lock(&bp
->hwrm_cmd_lock
);
2990 rc
= _hwrm_send_message(bp
, msg
, msg_len
, timeout
);
2991 mutex_unlock(&bp
->hwrm_cmd_lock
);
2995 int hwrm_send_message_silent(struct bnxt
*bp
, void *msg
, u32 msg_len
,
3000 mutex_lock(&bp
->hwrm_cmd_lock
);
3001 rc
= bnxt_hwrm_do_send_msg(bp
, msg
, msg_len
, timeout
, true);
3002 mutex_unlock(&bp
->hwrm_cmd_lock
);
3006 static int bnxt_hwrm_func_drv_rgtr(struct bnxt
*bp
)
3008 struct hwrm_func_drv_rgtr_input req
= {0};
3010 DECLARE_BITMAP(async_events_bmap
, 256);
3011 u32
*events
= (u32
*)async_events_bmap
;
3013 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_DRV_RGTR
, -1, -1);
3016 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE
|
3017 FUNC_DRV_RGTR_REQ_ENABLES_VER
|
3018 FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD
);
3020 memset(async_events_bmap
, 0, sizeof(async_events_bmap
));
3021 for (i
= 0; i
< ARRAY_SIZE(bnxt_async_events_arr
); i
++)
3022 __set_bit(bnxt_async_events_arr
[i
], async_events_bmap
);
3024 for (i
= 0; i
< 8; i
++)
3025 req
.async_event_fwd
[i
] |= cpu_to_le32(events
[i
]);
3027 req
.os_type
= cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX
);
3028 req
.ver_maj
= DRV_VER_MAJ
;
3029 req
.ver_min
= DRV_VER_MIN
;
3030 req
.ver_upd
= DRV_VER_UPD
;
3033 DECLARE_BITMAP(vf_req_snif_bmap
, 256);
3034 u32
*data
= (u32
*)vf_req_snif_bmap
;
3036 memset(vf_req_snif_bmap
, 0, sizeof(vf_req_snif_bmap
));
3037 for (i
= 0; i
< ARRAY_SIZE(bnxt_vf_req_snif
); i
++)
3038 __set_bit(bnxt_vf_req_snif
[i
], vf_req_snif_bmap
);
3040 for (i
= 0; i
< 8; i
++)
3041 req
.vf_req_fwd
[i
] = cpu_to_le32(data
[i
]);
3044 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD
);
3047 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3050 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt
*bp
)
3052 struct hwrm_func_drv_unrgtr_input req
= {0};
3054 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_DRV_UNRGTR
, -1, -1);
3055 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3058 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt
*bp
, u8 tunnel_type
)
3061 struct hwrm_tunnel_dst_port_free_input req
= {0};
3063 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_TUNNEL_DST_PORT_FREE
, -1, -1);
3064 req
.tunnel_type
= tunnel_type
;
3066 switch (tunnel_type
) {
3067 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
:
3068 req
.tunnel_dst_port_id
= bp
->vxlan_fw_dst_port_id
;
3070 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
:
3071 req
.tunnel_dst_port_id
= bp
->nge_fw_dst_port_id
;
3077 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3079 netdev_err(bp
->dev
, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
3084 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt
*bp
, __be16 port
,
3088 struct hwrm_tunnel_dst_port_alloc_input req
= {0};
3089 struct hwrm_tunnel_dst_port_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3091 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_TUNNEL_DST_PORT_ALLOC
, -1, -1);
3093 req
.tunnel_type
= tunnel_type
;
3094 req
.tunnel_dst_port_val
= port
;
3096 mutex_lock(&bp
->hwrm_cmd_lock
);
3097 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3099 netdev_err(bp
->dev
, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
3104 if (tunnel_type
& TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN
)
3105 bp
->vxlan_fw_dst_port_id
= resp
->tunnel_dst_port_id
;
3107 else if (tunnel_type
& TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE
)
3108 bp
->nge_fw_dst_port_id
= resp
->tunnel_dst_port_id
;
3110 mutex_unlock(&bp
->hwrm_cmd_lock
);
3114 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt
*bp
, u16 vnic_id
)
3116 struct hwrm_cfa_l2_set_rx_mask_input req
= {0};
3117 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
3119 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_L2_SET_RX_MASK
, -1, -1);
3120 req
.vnic_id
= cpu_to_le32(vnic
->fw_vnic_id
);
3122 req
.num_mc_entries
= cpu_to_le32(vnic
->mc_list_count
);
3123 req
.mc_tbl_addr
= cpu_to_le64(vnic
->mc_list_mapping
);
3124 req
.mask
= cpu_to_le32(vnic
->rx_mask
);
3125 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3128 #ifdef CONFIG_RFS_ACCEL
3129 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt
*bp
,
3130 struct bnxt_ntuple_filter
*fltr
)
3132 struct hwrm_cfa_ntuple_filter_free_input req
= {0};
3134 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_NTUPLE_FILTER_FREE
, -1, -1);
3135 req
.ntuple_filter_id
= fltr
->filter_id
;
3136 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3139 #define BNXT_NTP_FLTR_FLAGS \
3140 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
3141 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
3142 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
3143 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
3144 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
3145 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
3146 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
3147 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
3148 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
3149 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
3150 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
3151 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
3152 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
3153 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
3155 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt
*bp
,
3156 struct bnxt_ntuple_filter
*fltr
)
3159 struct hwrm_cfa_ntuple_filter_alloc_input req
= {0};
3160 struct hwrm_cfa_ntuple_filter_alloc_output
*resp
=
3161 bp
->hwrm_cmd_resp_addr
;
3162 struct flow_keys
*keys
= &fltr
->fkeys
;
3163 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[fltr
->rxq
+ 1];
3165 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_NTUPLE_FILTER_ALLOC
, -1, -1);
3166 req
.l2_filter_id
= bp
->vnic_info
[0].fw_l2_filter_id
[0];
3168 req
.enables
= cpu_to_le32(BNXT_NTP_FLTR_FLAGS
);
3170 req
.ethertype
= htons(ETH_P_IP
);
3171 memcpy(req
.src_macaddr
, fltr
->src_mac_addr
, ETH_ALEN
);
3172 req
.ip_addr_type
= CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4
;
3173 req
.ip_protocol
= keys
->basic
.ip_proto
;
3175 req
.src_ipaddr
[0] = keys
->addrs
.v4addrs
.src
;
3176 req
.src_ipaddr_mask
[0] = cpu_to_be32(0xffffffff);
3177 req
.dst_ipaddr
[0] = keys
->addrs
.v4addrs
.dst
;
3178 req
.dst_ipaddr_mask
[0] = cpu_to_be32(0xffffffff);
3180 req
.src_port
= keys
->ports
.src
;
3181 req
.src_port_mask
= cpu_to_be16(0xffff);
3182 req
.dst_port
= keys
->ports
.dst
;
3183 req
.dst_port_mask
= cpu_to_be16(0xffff);
3185 req
.dst_id
= cpu_to_le16(vnic
->fw_vnic_id
);
3186 mutex_lock(&bp
->hwrm_cmd_lock
);
3187 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3189 fltr
->filter_id
= resp
->ntuple_filter_id
;
3190 mutex_unlock(&bp
->hwrm_cmd_lock
);
3195 static int bnxt_hwrm_set_vnic_filter(struct bnxt
*bp
, u16 vnic_id
, u16 idx
,
3199 struct hwrm_cfa_l2_filter_alloc_input req
= {0};
3200 struct hwrm_cfa_l2_filter_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3202 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_L2_FILTER_ALLOC
, -1, -1);
3203 req
.flags
= cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX
|
3204 CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST
);
3205 req
.dst_id
= cpu_to_le16(bp
->vnic_info
[vnic_id
].fw_vnic_id
);
3207 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR
|
3208 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID
|
3209 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK
);
3210 memcpy(req
.l2_addr
, mac_addr
, ETH_ALEN
);
3211 req
.l2_addr_mask
[0] = 0xff;
3212 req
.l2_addr_mask
[1] = 0xff;
3213 req
.l2_addr_mask
[2] = 0xff;
3214 req
.l2_addr_mask
[3] = 0xff;
3215 req
.l2_addr_mask
[4] = 0xff;
3216 req
.l2_addr_mask
[5] = 0xff;
3218 mutex_lock(&bp
->hwrm_cmd_lock
);
3219 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3221 bp
->vnic_info
[vnic_id
].fw_l2_filter_id
[idx
] =
3223 mutex_unlock(&bp
->hwrm_cmd_lock
);
3227 static int bnxt_hwrm_clear_vnic_filter(struct bnxt
*bp
)
3229 u16 i
, j
, num_of_vnics
= 1; /* only vnic 0 supported */
3232 /* Any associated ntuple filters will also be cleared by firmware. */
3233 mutex_lock(&bp
->hwrm_cmd_lock
);
3234 for (i
= 0; i
< num_of_vnics
; i
++) {
3235 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[i
];
3237 for (j
= 0; j
< vnic
->uc_filter_count
; j
++) {
3238 struct hwrm_cfa_l2_filter_free_input req
= {0};
3240 bnxt_hwrm_cmd_hdr_init(bp
, &req
,
3241 HWRM_CFA_L2_FILTER_FREE
, -1, -1);
3243 req
.l2_filter_id
= vnic
->fw_l2_filter_id
[j
];
3245 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3248 vnic
->uc_filter_count
= 0;
3250 mutex_unlock(&bp
->hwrm_cmd_lock
);
3255 static int bnxt_hwrm_vnic_set_tpa(struct bnxt
*bp
, u16 vnic_id
, u32 tpa_flags
)
3257 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
3258 struct hwrm_vnic_tpa_cfg_input req
= {0};
3260 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_TPA_CFG
, -1, -1);
3263 u16 mss
= bp
->dev
->mtu
- 40;
3264 u32 nsegs
, n
, segs
= 0, flags
;
3266 flags
= VNIC_TPA_CFG_REQ_FLAGS_TPA
|
3267 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA
|
3268 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE
|
3269 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN
|
3270 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ
;
3271 if (tpa_flags
& BNXT_FLAG_GRO
)
3272 flags
|= VNIC_TPA_CFG_REQ_FLAGS_GRO
;
3274 req
.flags
= cpu_to_le32(flags
);
3277 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS
|
3278 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS
|
3279 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN
);
3281 /* Number of segs are log2 units, and first packet is not
3282 * included as part of this units.
3284 if (mss
<= BNXT_RX_PAGE_SIZE
) {
3285 n
= BNXT_RX_PAGE_SIZE
/ mss
;
3286 nsegs
= (MAX_SKB_FRAGS
- 1) * n
;
3288 n
= mss
/ BNXT_RX_PAGE_SIZE
;
3289 if (mss
& (BNXT_RX_PAGE_SIZE
- 1))
3291 nsegs
= (MAX_SKB_FRAGS
- n
) / n
;
3294 segs
= ilog2(nsegs
);
3295 req
.max_agg_segs
= cpu_to_le16(segs
);
3296 req
.max_aggs
= cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX
);
3298 req
.min_agg_len
= cpu_to_le32(512);
3300 req
.vnic_id
= cpu_to_le16(vnic
->fw_vnic_id
);
3302 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3305 static int bnxt_hwrm_vnic_set_rss(struct bnxt
*bp
, u16 vnic_id
, bool set_rss
)
3307 u32 i
, j
, max_rings
;
3308 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
3309 struct hwrm_vnic_rss_cfg_input req
= {0};
3311 if (vnic
->fw_rss_cos_lb_ctx
== INVALID_HW_RING_ID
)
3314 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_RSS_CFG
, -1, -1);
3316 vnic
->hash_type
= BNXT_RSS_HASH_TYPE_FLAG_IPV4
|
3317 BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV4
|
3318 BNXT_RSS_HASH_TYPE_FLAG_IPV6
|
3319 BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV6
;
3321 req
.hash_type
= cpu_to_le32(vnic
->hash_type
);
3323 if (vnic
->flags
& BNXT_VNIC_RSS_FLAG
)
3324 max_rings
= bp
->rx_nr_rings
;
3328 /* Fill the RSS indirection table with ring group ids */
3329 for (i
= 0, j
= 0; i
< HW_HASH_INDEX_SIZE
; i
++, j
++) {
3332 vnic
->rss_table
[i
] = cpu_to_le16(vnic
->fw_grp_ids
[j
]);
3335 req
.ring_grp_tbl_addr
= cpu_to_le64(vnic
->rss_table_dma_addr
);
3336 req
.hash_key_tbl_addr
=
3337 cpu_to_le64(vnic
->rss_hash_key_dma_addr
);
3339 req
.rss_ctx_idx
= cpu_to_le16(vnic
->fw_rss_cos_lb_ctx
);
3340 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3343 static int bnxt_hwrm_vnic_set_hds(struct bnxt
*bp
, u16 vnic_id
)
3345 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
3346 struct hwrm_vnic_plcmodes_cfg_input req
= {0};
3348 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_PLCMODES_CFG
, -1, -1);
3349 req
.flags
= cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT
|
3350 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4
|
3351 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6
);
3353 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID
|
3354 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID
);
3355 /* thresholds not implemented in firmware yet */
3356 req
.jumbo_thresh
= cpu_to_le16(bp
->rx_copy_thresh
);
3357 req
.hds_threshold
= cpu_to_le16(bp
->rx_copy_thresh
);
3358 req
.vnic_id
= cpu_to_le32(vnic
->fw_vnic_id
);
3359 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3362 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt
*bp
, u16 vnic_id
)
3364 struct hwrm_vnic_rss_cos_lb_ctx_free_input req
= {0};
3366 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_RSS_COS_LB_CTX_FREE
, -1, -1);
3367 req
.rss_cos_lb_ctx_id
=
3368 cpu_to_le16(bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
);
3370 hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3371 bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
= INVALID_HW_RING_ID
;
3374 static void bnxt_hwrm_vnic_ctx_free(struct bnxt
*bp
)
3378 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
3379 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[i
];
3381 if (vnic
->fw_rss_cos_lb_ctx
!= INVALID_HW_RING_ID
)
3382 bnxt_hwrm_vnic_ctx_free_one(bp
, i
);
3384 bp
->rsscos_nr_ctxs
= 0;
3387 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt
*bp
, u16 vnic_id
)
3390 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req
= {0};
3391 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output
*resp
=
3392 bp
->hwrm_cmd_resp_addr
;
3394 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC
, -1,
3397 mutex_lock(&bp
->hwrm_cmd_lock
);
3398 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3400 bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
=
3401 le16_to_cpu(resp
->rss_cos_lb_ctx_id
);
3402 mutex_unlock(&bp
->hwrm_cmd_lock
);
3407 static int bnxt_hwrm_vnic_cfg(struct bnxt
*bp
, u16 vnic_id
)
3409 unsigned int ring
= 0, grp_idx
;
3410 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
3411 struct hwrm_vnic_cfg_input req
= {0};
3414 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_CFG
, -1, -1);
3415 /* Only RSS support for now TBD: COS & LB */
3416 req
.enables
= cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP
|
3417 VNIC_CFG_REQ_ENABLES_RSS_RULE
|
3418 VNIC_CFG_REQ_ENABLES_MRU
);
3419 req
.rss_rule
= cpu_to_le16(vnic
->fw_rss_cos_lb_ctx
);
3420 req
.cos_rule
= cpu_to_le16(0xffff);
3421 if (vnic
->flags
& BNXT_VNIC_RSS_FLAG
)
3423 else if (vnic
->flags
& BNXT_VNIC_RFS_FLAG
)
3426 grp_idx
= bp
->rx_ring
[ring
].bnapi
->index
;
3427 req
.vnic_id
= cpu_to_le16(vnic
->fw_vnic_id
);
3428 req
.dflt_ring_grp
= cpu_to_le16(bp
->grp_info
[grp_idx
].fw_grp_id
);
3430 req
.lb_rule
= cpu_to_le16(0xffff);
3431 req
.mru
= cpu_to_le16(bp
->dev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+
3434 #ifdef CONFIG_BNXT_SRIOV
3436 def_vlan
= bp
->vf
.vlan
;
3438 if ((bp
->flags
& BNXT_FLAG_STRIP_VLAN
) || def_vlan
)
3439 req
.flags
|= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE
);
3441 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3444 static int bnxt_hwrm_vnic_free_one(struct bnxt
*bp
, u16 vnic_id
)
3448 if (bp
->vnic_info
[vnic_id
].fw_vnic_id
!= INVALID_HW_RING_ID
) {
3449 struct hwrm_vnic_free_input req
= {0};
3451 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_FREE
, -1, -1);
3453 cpu_to_le32(bp
->vnic_info
[vnic_id
].fw_vnic_id
);
3455 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3458 bp
->vnic_info
[vnic_id
].fw_vnic_id
= INVALID_HW_RING_ID
;
3463 static void bnxt_hwrm_vnic_free(struct bnxt
*bp
)
3467 for (i
= 0; i
< bp
->nr_vnics
; i
++)
3468 bnxt_hwrm_vnic_free_one(bp
, i
);
3471 static int bnxt_hwrm_vnic_alloc(struct bnxt
*bp
, u16 vnic_id
,
3472 unsigned int start_rx_ring_idx
,
3473 unsigned int nr_rings
)
3476 unsigned int i
, j
, grp_idx
, end_idx
= start_rx_ring_idx
+ nr_rings
;
3477 struct hwrm_vnic_alloc_input req
= {0};
3478 struct hwrm_vnic_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3480 /* map ring groups to this vnic */
3481 for (i
= start_rx_ring_idx
, j
= 0; i
< end_idx
; i
++, j
++) {
3482 grp_idx
= bp
->rx_ring
[i
].bnapi
->index
;
3483 if (bp
->grp_info
[grp_idx
].fw_grp_id
== INVALID_HW_RING_ID
) {
3484 netdev_err(bp
->dev
, "Not enough ring groups avail:%x req:%x\n",
3488 bp
->vnic_info
[vnic_id
].fw_grp_ids
[j
] =
3489 bp
->grp_info
[grp_idx
].fw_grp_id
;
3492 bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
= INVALID_HW_RING_ID
;
3494 req
.flags
= cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT
);
3496 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_ALLOC
, -1, -1);
3498 mutex_lock(&bp
->hwrm_cmd_lock
);
3499 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3501 bp
->vnic_info
[vnic_id
].fw_vnic_id
= le32_to_cpu(resp
->vnic_id
);
3502 mutex_unlock(&bp
->hwrm_cmd_lock
);
3506 static int bnxt_hwrm_ring_grp_alloc(struct bnxt
*bp
)
3511 mutex_lock(&bp
->hwrm_cmd_lock
);
3512 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3513 struct hwrm_ring_grp_alloc_input req
= {0};
3514 struct hwrm_ring_grp_alloc_output
*resp
=
3515 bp
->hwrm_cmd_resp_addr
;
3516 unsigned int grp_idx
= bp
->rx_ring
[i
].bnapi
->index
;
3518 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_GRP_ALLOC
, -1, -1);
3520 req
.cr
= cpu_to_le16(bp
->grp_info
[grp_idx
].cp_fw_ring_id
);
3521 req
.rr
= cpu_to_le16(bp
->grp_info
[grp_idx
].rx_fw_ring_id
);
3522 req
.ar
= cpu_to_le16(bp
->grp_info
[grp_idx
].agg_fw_ring_id
);
3523 req
.sc
= cpu_to_le16(bp
->grp_info
[grp_idx
].fw_stats_ctx
);
3525 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3530 bp
->grp_info
[grp_idx
].fw_grp_id
=
3531 le32_to_cpu(resp
->ring_group_id
);
3533 mutex_unlock(&bp
->hwrm_cmd_lock
);
3537 static int bnxt_hwrm_ring_grp_free(struct bnxt
*bp
)
3541 struct hwrm_ring_grp_free_input req
= {0};
3546 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_GRP_FREE
, -1, -1);
3548 mutex_lock(&bp
->hwrm_cmd_lock
);
3549 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3550 if (bp
->grp_info
[i
].fw_grp_id
== INVALID_HW_RING_ID
)
3553 cpu_to_le32(bp
->grp_info
[i
].fw_grp_id
);
3555 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3559 bp
->grp_info
[i
].fw_grp_id
= INVALID_HW_RING_ID
;
3561 mutex_unlock(&bp
->hwrm_cmd_lock
);
3565 static int hwrm_ring_alloc_send_msg(struct bnxt
*bp
,
3566 struct bnxt_ring_struct
*ring
,
3567 u32 ring_type
, u32 map_index
,
3570 int rc
= 0, err
= 0;
3571 struct hwrm_ring_alloc_input req
= {0};
3572 struct hwrm_ring_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3575 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_ALLOC
, -1, -1);
3578 if (ring
->nr_pages
> 1) {
3579 req
.page_tbl_addr
= cpu_to_le64(ring
->pg_tbl_map
);
3580 /* Page size is in log2 units */
3581 req
.page_size
= BNXT_PAGE_SHIFT
;
3582 req
.page_tbl_depth
= 1;
3584 req
.page_tbl_addr
= cpu_to_le64(ring
->dma_arr
[0]);
3587 /* Association of ring index with doorbell index and MSIX number */
3588 req
.logical_id
= cpu_to_le16(map_index
);
3590 switch (ring_type
) {
3591 case HWRM_RING_ALLOC_TX
:
3592 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_TX
;
3593 /* Association of transmit ring with completion ring */
3595 cpu_to_le16(bp
->grp_info
[map_index
].cp_fw_ring_id
);
3596 req
.length
= cpu_to_le32(bp
->tx_ring_mask
+ 1);
3597 req
.stat_ctx_id
= cpu_to_le32(stats_ctx_id
);
3598 req
.queue_id
= cpu_to_le16(ring
->queue_id
);
3600 case HWRM_RING_ALLOC_RX
:
3601 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_RX
;
3602 req
.length
= cpu_to_le32(bp
->rx_ring_mask
+ 1);
3604 case HWRM_RING_ALLOC_AGG
:
3605 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_RX
;
3606 req
.length
= cpu_to_le32(bp
->rx_agg_ring_mask
+ 1);
3608 case HWRM_RING_ALLOC_CMPL
:
3609 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_CMPL
;
3610 req
.length
= cpu_to_le32(bp
->cp_ring_mask
+ 1);
3611 if (bp
->flags
& BNXT_FLAG_USING_MSIX
)
3612 req
.int_mode
= RING_ALLOC_REQ_INT_MODE_MSIX
;
3615 netdev_err(bp
->dev
, "hwrm alloc invalid ring type %d\n",
3620 mutex_lock(&bp
->hwrm_cmd_lock
);
3621 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3622 err
= le16_to_cpu(resp
->error_code
);
3623 ring_id
= le16_to_cpu(resp
->ring_id
);
3624 mutex_unlock(&bp
->hwrm_cmd_lock
);
3627 switch (ring_type
) {
3628 case RING_FREE_REQ_RING_TYPE_CMPL
:
3629 netdev_err(bp
->dev
, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
3633 case RING_FREE_REQ_RING_TYPE_RX
:
3634 netdev_err(bp
->dev
, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
3638 case RING_FREE_REQ_RING_TYPE_TX
:
3639 netdev_err(bp
->dev
, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
3644 netdev_err(bp
->dev
, "Invalid ring\n");
3648 ring
->fw_ring_id
= ring_id
;
3652 static int bnxt_hwrm_ring_alloc(struct bnxt
*bp
)
3656 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3657 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3658 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3659 struct bnxt_ring_struct
*ring
= &cpr
->cp_ring_struct
;
3661 cpr
->cp_doorbell
= bp
->bar1
+ i
* 0x80;
3662 rc
= hwrm_ring_alloc_send_msg(bp
, ring
, HWRM_RING_ALLOC_CMPL
, i
,
3663 INVALID_STATS_CTX_ID
);
3666 BNXT_CP_DB(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
3667 bp
->grp_info
[i
].cp_fw_ring_id
= ring
->fw_ring_id
;
3670 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
3671 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
3672 struct bnxt_ring_struct
*ring
= &txr
->tx_ring_struct
;
3673 u32 map_idx
= txr
->bnapi
->index
;
3674 u16 fw_stats_ctx
= bp
->grp_info
[map_idx
].fw_stats_ctx
;
3676 rc
= hwrm_ring_alloc_send_msg(bp
, ring
, HWRM_RING_ALLOC_TX
,
3677 map_idx
, fw_stats_ctx
);
3680 txr
->tx_doorbell
= bp
->bar1
+ map_idx
* 0x80;
3683 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3684 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
3685 struct bnxt_ring_struct
*ring
= &rxr
->rx_ring_struct
;
3686 u32 map_idx
= rxr
->bnapi
->index
;
3688 rc
= hwrm_ring_alloc_send_msg(bp
, ring
, HWRM_RING_ALLOC_RX
,
3689 map_idx
, INVALID_STATS_CTX_ID
);
3692 rxr
->rx_doorbell
= bp
->bar1
+ map_idx
* 0x80;
3693 writel(DB_KEY_RX
| rxr
->rx_prod
, rxr
->rx_doorbell
);
3694 bp
->grp_info
[map_idx
].rx_fw_ring_id
= ring
->fw_ring_id
;
3697 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
) {
3698 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3699 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
3700 struct bnxt_ring_struct
*ring
=
3701 &rxr
->rx_agg_ring_struct
;
3702 u32 grp_idx
= rxr
->bnapi
->index
;
3703 u32 map_idx
= grp_idx
+ bp
->rx_nr_rings
;
3705 rc
= hwrm_ring_alloc_send_msg(bp
, ring
,
3706 HWRM_RING_ALLOC_AGG
,
3708 INVALID_STATS_CTX_ID
);
3712 rxr
->rx_agg_doorbell
= bp
->bar1
+ map_idx
* 0x80;
3713 writel(DB_KEY_RX
| rxr
->rx_agg_prod
,
3714 rxr
->rx_agg_doorbell
);
3715 bp
->grp_info
[grp_idx
].agg_fw_ring_id
= ring
->fw_ring_id
;
3722 static int hwrm_ring_free_send_msg(struct bnxt
*bp
,
3723 struct bnxt_ring_struct
*ring
,
3724 u32 ring_type
, int cmpl_ring_id
)
3727 struct hwrm_ring_free_input req
= {0};
3728 struct hwrm_ring_free_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3731 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_FREE
, cmpl_ring_id
, -1);
3732 req
.ring_type
= ring_type
;
3733 req
.ring_id
= cpu_to_le16(ring
->fw_ring_id
);
3735 mutex_lock(&bp
->hwrm_cmd_lock
);
3736 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3737 error_code
= le16_to_cpu(resp
->error_code
);
3738 mutex_unlock(&bp
->hwrm_cmd_lock
);
3740 if (rc
|| error_code
) {
3741 switch (ring_type
) {
3742 case RING_FREE_REQ_RING_TYPE_CMPL
:
3743 netdev_err(bp
->dev
, "hwrm_ring_free cp failed. rc:%d\n",
3746 case RING_FREE_REQ_RING_TYPE_RX
:
3747 netdev_err(bp
->dev
, "hwrm_ring_free rx failed. rc:%d\n",
3750 case RING_FREE_REQ_RING_TYPE_TX
:
3751 netdev_err(bp
->dev
, "hwrm_ring_free tx failed. rc:%d\n",
3755 netdev_err(bp
->dev
, "Invalid ring\n");
3762 static void bnxt_hwrm_ring_free(struct bnxt
*bp
, bool close_path
)
3769 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
3770 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
3771 struct bnxt_ring_struct
*ring
= &txr
->tx_ring_struct
;
3772 u32 grp_idx
= txr
->bnapi
->index
;
3773 u32 cmpl_ring_id
= bp
->grp_info
[grp_idx
].cp_fw_ring_id
;
3775 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
3776 hwrm_ring_free_send_msg(bp
, ring
,
3777 RING_FREE_REQ_RING_TYPE_TX
,
3778 close_path
? cmpl_ring_id
:
3779 INVALID_HW_RING_ID
);
3780 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
3784 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3785 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
3786 struct bnxt_ring_struct
*ring
= &rxr
->rx_ring_struct
;
3787 u32 grp_idx
= rxr
->bnapi
->index
;
3788 u32 cmpl_ring_id
= bp
->grp_info
[grp_idx
].cp_fw_ring_id
;
3790 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
3791 hwrm_ring_free_send_msg(bp
, ring
,
3792 RING_FREE_REQ_RING_TYPE_RX
,
3793 close_path
? cmpl_ring_id
:
3794 INVALID_HW_RING_ID
);
3795 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
3796 bp
->grp_info
[grp_idx
].rx_fw_ring_id
=
3801 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3802 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
3803 struct bnxt_ring_struct
*ring
= &rxr
->rx_agg_ring_struct
;
3804 u32 grp_idx
= rxr
->bnapi
->index
;
3805 u32 cmpl_ring_id
= bp
->grp_info
[grp_idx
].cp_fw_ring_id
;
3807 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
3808 hwrm_ring_free_send_msg(bp
, ring
,
3809 RING_FREE_REQ_RING_TYPE_RX
,
3810 close_path
? cmpl_ring_id
:
3811 INVALID_HW_RING_ID
);
3812 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
3813 bp
->grp_info
[grp_idx
].agg_fw_ring_id
=
3818 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3819 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3820 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3821 struct bnxt_ring_struct
*ring
= &cpr
->cp_ring_struct
;
3823 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
3824 hwrm_ring_free_send_msg(bp
, ring
,
3825 RING_FREE_REQ_RING_TYPE_CMPL
,
3826 INVALID_HW_RING_ID
);
3827 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
3828 bp
->grp_info
[i
].cp_fw_ring_id
= INVALID_HW_RING_ID
;
3833 static void bnxt_hwrm_set_coal_params(struct bnxt
*bp
, u32 max_bufs
,
3834 u32 buf_tmrs
, u16 flags
,
3835 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input
*req
)
3837 req
->flags
= cpu_to_le16(flags
);
3838 req
->num_cmpl_dma_aggr
= cpu_to_le16((u16
)max_bufs
);
3839 req
->num_cmpl_dma_aggr_during_int
= cpu_to_le16(max_bufs
>> 16);
3840 req
->cmpl_aggr_dma_tmr
= cpu_to_le16((u16
)buf_tmrs
);
3841 req
->cmpl_aggr_dma_tmr_during_int
= cpu_to_le16(buf_tmrs
>> 16);
3842 /* Minimum time between 2 interrupts set to buf_tmr x 2 */
3843 req
->int_lat_tmr_min
= cpu_to_le16((u16
)buf_tmrs
* 2);
3844 req
->int_lat_tmr_max
= cpu_to_le16((u16
)buf_tmrs
* 4);
3845 req
->num_cmpl_aggr_int
= cpu_to_le16((u16
)max_bufs
* 4);
3848 int bnxt_hwrm_set_coal(struct bnxt
*bp
)
3851 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx
= {0},
3853 u16 max_buf
, max_buf_irq
;
3854 u16 buf_tmr
, buf_tmr_irq
;
3857 bnxt_hwrm_cmd_hdr_init(bp
, &req_rx
,
3858 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS
, -1, -1);
3859 bnxt_hwrm_cmd_hdr_init(bp
, &req_tx
,
3860 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS
, -1, -1);
3862 /* Each rx completion (2 records) should be DMAed immediately.
3863 * DMA 1/4 of the completion buffers at a time.
3865 max_buf
= min_t(u16
, bp
->rx_coal_bufs
/ 4, 2);
3866 /* max_buf must not be zero */
3867 max_buf
= clamp_t(u16
, max_buf
, 1, 63);
3868 max_buf_irq
= clamp_t(u16
, bp
->rx_coal_bufs_irq
, 1, 63);
3869 buf_tmr
= BNXT_USEC_TO_COAL_TIMER(bp
->rx_coal_ticks
);
3870 /* buf timer set to 1/4 of interrupt timer */
3871 buf_tmr
= max_t(u16
, buf_tmr
/ 4, 1);
3872 buf_tmr_irq
= BNXT_USEC_TO_COAL_TIMER(bp
->rx_coal_ticks_irq
);
3873 buf_tmr_irq
= max_t(u16
, buf_tmr_irq
, 1);
3875 flags
= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET
;
3877 /* RING_IDLE generates more IRQs for lower latency. Enable it only
3878 * if coal_ticks is less than 25 us.
3880 if (bp
->rx_coal_ticks
< 25)
3881 flags
|= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE
;
3883 bnxt_hwrm_set_coal_params(bp
, max_buf_irq
<< 16 | max_buf
,
3884 buf_tmr_irq
<< 16 | buf_tmr
, flags
, &req_rx
);
3886 /* max_buf must not be zero */
3887 max_buf
= clamp_t(u16
, bp
->tx_coal_bufs
, 1, 63);
3888 max_buf_irq
= clamp_t(u16
, bp
->tx_coal_bufs_irq
, 1, 63);
3889 buf_tmr
= BNXT_USEC_TO_COAL_TIMER(bp
->tx_coal_ticks
);
3890 /* buf timer set to 1/4 of interrupt timer */
3891 buf_tmr
= max_t(u16
, buf_tmr
/ 4, 1);
3892 buf_tmr_irq
= BNXT_USEC_TO_COAL_TIMER(bp
->tx_coal_ticks_irq
);
3893 buf_tmr_irq
= max_t(u16
, buf_tmr_irq
, 1);
3895 flags
= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET
;
3896 bnxt_hwrm_set_coal_params(bp
, max_buf_irq
<< 16 | max_buf
,
3897 buf_tmr_irq
<< 16 | buf_tmr
, flags
, &req_tx
);
3899 mutex_lock(&bp
->hwrm_cmd_lock
);
3900 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3901 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3904 if (!bnapi
->rx_ring
)
3906 req
->ring_id
= cpu_to_le16(bp
->grp_info
[i
].cp_fw_ring_id
);
3908 rc
= _hwrm_send_message(bp
, req
, sizeof(*req
),
3913 mutex_unlock(&bp
->hwrm_cmd_lock
);
3917 static int bnxt_hwrm_stat_ctx_free(struct bnxt
*bp
)
3920 struct hwrm_stat_ctx_free_input req
= {0};
3925 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_STAT_CTX_FREE
, -1, -1);
3927 mutex_lock(&bp
->hwrm_cmd_lock
);
3928 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3929 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3930 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3932 if (cpr
->hw_stats_ctx_id
!= INVALID_STATS_CTX_ID
) {
3933 req
.stat_ctx_id
= cpu_to_le32(cpr
->hw_stats_ctx_id
);
3935 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3940 cpr
->hw_stats_ctx_id
= INVALID_STATS_CTX_ID
;
3943 mutex_unlock(&bp
->hwrm_cmd_lock
);
3947 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt
*bp
)
3950 struct hwrm_stat_ctx_alloc_input req
= {0};
3951 struct hwrm_stat_ctx_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3953 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_STAT_CTX_ALLOC
, -1, -1);
3955 req
.update_period_ms
= cpu_to_le32(bp
->stats_coal_ticks
/ 1000);
3957 mutex_lock(&bp
->hwrm_cmd_lock
);
3958 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3959 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3960 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3962 req
.stats_dma_addr
= cpu_to_le64(cpr
->hw_stats_map
);
3964 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3969 cpr
->hw_stats_ctx_id
= le32_to_cpu(resp
->stat_ctx_id
);
3971 bp
->grp_info
[i
].fw_stats_ctx
= cpr
->hw_stats_ctx_id
;
3973 mutex_unlock(&bp
->hwrm_cmd_lock
);
3977 static int bnxt_hwrm_func_qcfg(struct bnxt
*bp
)
3979 struct hwrm_func_qcfg_input req
= {0};
3980 struct hwrm_func_qcfg_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3983 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_QCFG
, -1, -1);
3984 req
.fid
= cpu_to_le16(0xffff);
3985 mutex_lock(&bp
->hwrm_cmd_lock
);
3986 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3988 goto func_qcfg_exit
;
3990 #ifdef CONFIG_BNXT_SRIOV
3992 struct bnxt_vf_info
*vf
= &bp
->vf
;
3994 vf
->vlan
= le16_to_cpu(resp
->vlan
) & VLAN_VID_MASK
;
3997 switch (resp
->port_partition_type
) {
3998 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0
:
3999 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5
:
4000 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0
:
4001 bp
->port_partition_type
= resp
->port_partition_type
;
4006 mutex_unlock(&bp
->hwrm_cmd_lock
);
4010 int bnxt_hwrm_func_qcaps(struct bnxt
*bp
)
4013 struct hwrm_func_qcaps_input req
= {0};
4014 struct hwrm_func_qcaps_output
*resp
= bp
->hwrm_cmd_resp_addr
;
4016 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_QCAPS
, -1, -1);
4017 req
.fid
= cpu_to_le16(0xffff);
4019 mutex_lock(&bp
->hwrm_cmd_lock
);
4020 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4022 goto hwrm_func_qcaps_exit
;
4025 struct bnxt_pf_info
*pf
= &bp
->pf
;
4027 pf
->fw_fid
= le16_to_cpu(resp
->fid
);
4028 pf
->port_id
= le16_to_cpu(resp
->port_id
);
4029 bp
->dev
->dev_port
= pf
->port_id
;
4030 memcpy(pf
->mac_addr
, resp
->mac_address
, ETH_ALEN
);
4031 memcpy(bp
->dev
->dev_addr
, pf
->mac_addr
, ETH_ALEN
);
4032 pf
->max_rsscos_ctxs
= le16_to_cpu(resp
->max_rsscos_ctx
);
4033 pf
->max_cp_rings
= le16_to_cpu(resp
->max_cmpl_rings
);
4034 pf
->max_tx_rings
= le16_to_cpu(resp
->max_tx_rings
);
4035 pf
->max_rx_rings
= le16_to_cpu(resp
->max_rx_rings
);
4036 pf
->max_hw_ring_grps
= le32_to_cpu(resp
->max_hw_ring_grps
);
4037 if (!pf
->max_hw_ring_grps
)
4038 pf
->max_hw_ring_grps
= pf
->max_tx_rings
;
4039 pf
->max_l2_ctxs
= le16_to_cpu(resp
->max_l2_ctxs
);
4040 pf
->max_vnics
= le16_to_cpu(resp
->max_vnics
);
4041 pf
->max_stat_ctxs
= le16_to_cpu(resp
->max_stat_ctx
);
4042 pf
->first_vf_id
= le16_to_cpu(resp
->first_vf_id
);
4043 pf
->max_vfs
= le16_to_cpu(resp
->max_vfs
);
4044 pf
->max_encap_records
= le32_to_cpu(resp
->max_encap_records
);
4045 pf
->max_decap_records
= le32_to_cpu(resp
->max_decap_records
);
4046 pf
->max_tx_em_flows
= le32_to_cpu(resp
->max_tx_em_flows
);
4047 pf
->max_tx_wm_flows
= le32_to_cpu(resp
->max_tx_wm_flows
);
4048 pf
->max_rx_em_flows
= le32_to_cpu(resp
->max_rx_em_flows
);
4049 pf
->max_rx_wm_flows
= le32_to_cpu(resp
->max_rx_wm_flows
);
4051 #ifdef CONFIG_BNXT_SRIOV
4052 struct bnxt_vf_info
*vf
= &bp
->vf
;
4054 vf
->fw_fid
= le16_to_cpu(resp
->fid
);
4055 memcpy(vf
->mac_addr
, resp
->mac_address
, ETH_ALEN
);
4056 if (is_valid_ether_addr(vf
->mac_addr
))
4057 /* overwrite netdev dev_adr with admin VF MAC */
4058 memcpy(bp
->dev
->dev_addr
, vf
->mac_addr
, ETH_ALEN
);
4060 random_ether_addr(bp
->dev
->dev_addr
);
4062 vf
->max_rsscos_ctxs
= le16_to_cpu(resp
->max_rsscos_ctx
);
4063 vf
->max_cp_rings
= le16_to_cpu(resp
->max_cmpl_rings
);
4064 vf
->max_tx_rings
= le16_to_cpu(resp
->max_tx_rings
);
4065 vf
->max_rx_rings
= le16_to_cpu(resp
->max_rx_rings
);
4066 vf
->max_hw_ring_grps
= le32_to_cpu(resp
->max_hw_ring_grps
);
4067 if (!vf
->max_hw_ring_grps
)
4068 vf
->max_hw_ring_grps
= vf
->max_tx_rings
;
4069 vf
->max_l2_ctxs
= le16_to_cpu(resp
->max_l2_ctxs
);
4070 vf
->max_vnics
= le16_to_cpu(resp
->max_vnics
);
4071 vf
->max_stat_ctxs
= le16_to_cpu(resp
->max_stat_ctx
);
4075 bp
->tx_push_thresh
= 0;
4077 cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED
))
4078 bp
->tx_push_thresh
= BNXT_TX_PUSH_THRESH
;
4080 hwrm_func_qcaps_exit
:
4081 mutex_unlock(&bp
->hwrm_cmd_lock
);
4085 static int bnxt_hwrm_func_reset(struct bnxt
*bp
)
4087 struct hwrm_func_reset_input req
= {0};
4089 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_RESET
, -1, -1);
4092 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_RESET_TIMEOUT
);
4095 static int bnxt_hwrm_queue_qportcfg(struct bnxt
*bp
)
4098 struct hwrm_queue_qportcfg_input req
= {0};
4099 struct hwrm_queue_qportcfg_output
*resp
= bp
->hwrm_cmd_resp_addr
;
4102 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_QUEUE_QPORTCFG
, -1, -1);
4104 mutex_lock(&bp
->hwrm_cmd_lock
);
4105 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4109 if (!resp
->max_configurable_queues
) {
4113 bp
->max_tc
= resp
->max_configurable_queues
;
4114 if (bp
->max_tc
> BNXT_MAX_QUEUE
)
4115 bp
->max_tc
= BNXT_MAX_QUEUE
;
4117 qptr
= &resp
->queue_id0
;
4118 for (i
= 0; i
< bp
->max_tc
; i
++) {
4119 bp
->q_info
[i
].queue_id
= *qptr
++;
4120 bp
->q_info
[i
].queue_profile
= *qptr
++;
4124 mutex_unlock(&bp
->hwrm_cmd_lock
);
4128 static int bnxt_hwrm_ver_get(struct bnxt
*bp
)
4131 struct hwrm_ver_get_input req
= {0};
4132 struct hwrm_ver_get_output
*resp
= bp
->hwrm_cmd_resp_addr
;
4134 bp
->hwrm_max_req_len
= HWRM_MAX_REQ_LEN
;
4135 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VER_GET
, -1, -1);
4136 req
.hwrm_intf_maj
= HWRM_VERSION_MAJOR
;
4137 req
.hwrm_intf_min
= HWRM_VERSION_MINOR
;
4138 req
.hwrm_intf_upd
= HWRM_VERSION_UPDATE
;
4139 mutex_lock(&bp
->hwrm_cmd_lock
);
4140 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4142 goto hwrm_ver_get_exit
;
4144 memcpy(&bp
->ver_resp
, resp
, sizeof(struct hwrm_ver_get_output
));
4146 bp
->hwrm_spec_code
= resp
->hwrm_intf_maj
<< 16 |
4147 resp
->hwrm_intf_min
<< 8 | resp
->hwrm_intf_upd
;
4148 if (resp
->hwrm_intf_maj
< 1) {
4149 netdev_warn(bp
->dev
, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
4150 resp
->hwrm_intf_maj
, resp
->hwrm_intf_min
,
4151 resp
->hwrm_intf_upd
);
4152 netdev_warn(bp
->dev
, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
4154 snprintf(bp
->fw_ver_str
, BC_HWRM_STR_LEN
, "%d.%d.%d/%d.%d.%d",
4155 resp
->hwrm_fw_maj
, resp
->hwrm_fw_min
, resp
->hwrm_fw_bld
,
4156 resp
->hwrm_intf_maj
, resp
->hwrm_intf_min
, resp
->hwrm_intf_upd
);
4158 bp
->hwrm_cmd_timeout
= le16_to_cpu(resp
->def_req_timeout
);
4159 if (!bp
->hwrm_cmd_timeout
)
4160 bp
->hwrm_cmd_timeout
= DFLT_HWRM_CMD_TIMEOUT
;
4162 if (resp
->hwrm_intf_maj
>= 1)
4163 bp
->hwrm_max_req_len
= le16_to_cpu(resp
->max_req_win_len
);
4165 bp
->chip_num
= le16_to_cpu(resp
->chip_num
);
4168 mutex_unlock(&bp
->hwrm_cmd_lock
);
4172 static int bnxt_hwrm_port_qstats(struct bnxt
*bp
)
4175 struct bnxt_pf_info
*pf
= &bp
->pf
;
4176 struct hwrm_port_qstats_input req
= {0};
4178 if (!(bp
->flags
& BNXT_FLAG_PORT_STATS
))
4181 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_QSTATS
, -1, -1);
4182 req
.port_id
= cpu_to_le16(pf
->port_id
);
4183 req
.tx_stat_host_addr
= cpu_to_le64(bp
->hw_tx_port_stats_map
);
4184 req
.rx_stat_host_addr
= cpu_to_le64(bp
->hw_rx_port_stats_map
);
4185 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4189 static void bnxt_hwrm_free_tunnel_ports(struct bnxt
*bp
)
4191 if (bp
->vxlan_port_cnt
) {
4192 bnxt_hwrm_tunnel_dst_port_free(
4193 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
);
4195 bp
->vxlan_port_cnt
= 0;
4196 if (bp
->nge_port_cnt
) {
4197 bnxt_hwrm_tunnel_dst_port_free(
4198 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
);
4200 bp
->nge_port_cnt
= 0;
4203 static int bnxt_set_tpa(struct bnxt
*bp
, bool set_tpa
)
4209 tpa_flags
= bp
->flags
& BNXT_FLAG_TPA
;
4210 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
4211 rc
= bnxt_hwrm_vnic_set_tpa(bp
, i
, tpa_flags
);
4213 netdev_err(bp
->dev
, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
4221 static void bnxt_hwrm_clear_vnic_rss(struct bnxt
*bp
)
4225 for (i
= 0; i
< bp
->nr_vnics
; i
++)
4226 bnxt_hwrm_vnic_set_rss(bp
, i
, false);
4229 static void bnxt_hwrm_resource_free(struct bnxt
*bp
, bool close_path
,
4232 if (bp
->vnic_info
) {
4233 bnxt_hwrm_clear_vnic_filter(bp
);
4234 /* clear all RSS setting before free vnic ctx */
4235 bnxt_hwrm_clear_vnic_rss(bp
);
4236 bnxt_hwrm_vnic_ctx_free(bp
);
4237 /* before free the vnic, undo the vnic tpa settings */
4238 if (bp
->flags
& BNXT_FLAG_TPA
)
4239 bnxt_set_tpa(bp
, false);
4240 bnxt_hwrm_vnic_free(bp
);
4242 bnxt_hwrm_ring_free(bp
, close_path
);
4243 bnxt_hwrm_ring_grp_free(bp
);
4245 bnxt_hwrm_stat_ctx_free(bp
);
4246 bnxt_hwrm_free_tunnel_ports(bp
);
4250 static int bnxt_setup_vnic(struct bnxt
*bp
, u16 vnic_id
)
4254 /* allocate context for vnic */
4255 rc
= bnxt_hwrm_vnic_ctx_alloc(bp
, vnic_id
);
4257 netdev_err(bp
->dev
, "hwrm vnic %d alloc failure rc: %x\n",
4259 goto vnic_setup_err
;
4261 bp
->rsscos_nr_ctxs
++;
4263 /* configure default vnic, ring grp */
4264 rc
= bnxt_hwrm_vnic_cfg(bp
, vnic_id
);
4266 netdev_err(bp
->dev
, "hwrm vnic %d cfg failure rc: %x\n",
4268 goto vnic_setup_err
;
4271 /* Enable RSS hashing on vnic */
4272 rc
= bnxt_hwrm_vnic_set_rss(bp
, vnic_id
, true);
4274 netdev_err(bp
->dev
, "hwrm vnic %d set rss failure rc: %x\n",
4276 goto vnic_setup_err
;
4279 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
) {
4280 rc
= bnxt_hwrm_vnic_set_hds(bp
, vnic_id
);
4282 netdev_err(bp
->dev
, "hwrm vnic %d set hds failure rc: %x\n",
4291 static int bnxt_alloc_rfs_vnics(struct bnxt
*bp
)
4293 #ifdef CONFIG_RFS_ACCEL
4296 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
4297 u16 vnic_id
= i
+ 1;
4300 if (vnic_id
>= bp
->nr_vnics
)
4303 bp
->vnic_info
[vnic_id
].flags
|= BNXT_VNIC_RFS_FLAG
;
4304 rc
= bnxt_hwrm_vnic_alloc(bp
, vnic_id
, ring_id
, 1);
4306 netdev_err(bp
->dev
, "hwrm vnic %d alloc failure rc: %x\n",
4310 rc
= bnxt_setup_vnic(bp
, vnic_id
);
4320 /* Allow PF and VF with default VLAN to be in promiscuous mode */
4321 static bool bnxt_promisc_ok(struct bnxt
*bp
)
4323 #ifdef CONFIG_BNXT_SRIOV
4324 if (BNXT_VF(bp
) && !bp
->vf
.vlan
)
4330 static int bnxt_cfg_rx_mode(struct bnxt
*);
4331 static bool bnxt_mc_list_updated(struct bnxt
*, u32
*);
4333 static int bnxt_init_chip(struct bnxt
*bp
, bool irq_re_init
)
4335 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
4339 rc
= bnxt_hwrm_stat_ctx_alloc(bp
);
4341 netdev_err(bp
->dev
, "hwrm stat ctx alloc failure rc: %x\n",
4347 rc
= bnxt_hwrm_ring_alloc(bp
);
4349 netdev_err(bp
->dev
, "hwrm ring alloc failure rc: %x\n", rc
);
4353 rc
= bnxt_hwrm_ring_grp_alloc(bp
);
4355 netdev_err(bp
->dev
, "hwrm_ring_grp alloc failure: %x\n", rc
);
4359 /* default vnic 0 */
4360 rc
= bnxt_hwrm_vnic_alloc(bp
, 0, 0, bp
->rx_nr_rings
);
4362 netdev_err(bp
->dev
, "hwrm vnic alloc failure rc: %x\n", rc
);
4366 rc
= bnxt_setup_vnic(bp
, 0);
4370 if (bp
->flags
& BNXT_FLAG_RFS
) {
4371 rc
= bnxt_alloc_rfs_vnics(bp
);
4376 if (bp
->flags
& BNXT_FLAG_TPA
) {
4377 rc
= bnxt_set_tpa(bp
, true);
4383 bnxt_update_vf_mac(bp
);
4385 /* Filter for default vnic 0 */
4386 rc
= bnxt_hwrm_set_vnic_filter(bp
, 0, 0, bp
->dev
->dev_addr
);
4388 netdev_err(bp
->dev
, "HWRM vnic filter failure rc: %x\n", rc
);
4391 vnic
->uc_filter_count
= 1;
4393 vnic
->rx_mask
= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST
;
4395 if ((bp
->dev
->flags
& IFF_PROMISC
) && bnxt_promisc_ok(bp
))
4396 vnic
->rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
;
4398 if (bp
->dev
->flags
& IFF_ALLMULTI
) {
4399 vnic
->rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
;
4400 vnic
->mc_list_count
= 0;
4404 bnxt_mc_list_updated(bp
, &mask
);
4405 vnic
->rx_mask
|= mask
;
4408 rc
= bnxt_cfg_rx_mode(bp
);
4412 rc
= bnxt_hwrm_set_coal(bp
);
4414 netdev_warn(bp
->dev
, "HWRM set coalescing failure rc: %x\n",
4418 bnxt_hwrm_func_qcfg(bp
);
4419 netdev_update_features(bp
->dev
);
4425 bnxt_hwrm_resource_free(bp
, 0, true);
4430 static int bnxt_shutdown_nic(struct bnxt
*bp
, bool irq_re_init
)
4432 bnxt_hwrm_resource_free(bp
, 1, irq_re_init
);
4436 static int bnxt_init_nic(struct bnxt
*bp
, bool irq_re_init
)
4438 bnxt_init_rx_rings(bp
);
4439 bnxt_init_tx_rings(bp
);
4440 bnxt_init_ring_grps(bp
, irq_re_init
);
4441 bnxt_init_vnics(bp
);
4443 return bnxt_init_chip(bp
, irq_re_init
);
4446 static void bnxt_disable_int(struct bnxt
*bp
)
4453 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4454 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4455 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
4457 BNXT_CP_DB(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
4461 static void bnxt_enable_int(struct bnxt
*bp
)
4465 atomic_set(&bp
->intr_sem
, 0);
4466 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4467 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4468 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
4470 BNXT_CP_DB_REARM(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
4474 static int bnxt_set_real_num_queues(struct bnxt
*bp
)
4477 struct net_device
*dev
= bp
->dev
;
4479 rc
= netif_set_real_num_tx_queues(dev
, bp
->tx_nr_rings
);
4483 rc
= netif_set_real_num_rx_queues(dev
, bp
->rx_nr_rings
);
4487 #ifdef CONFIG_RFS_ACCEL
4488 if (bp
->flags
& BNXT_FLAG_RFS
)
4489 dev
->rx_cpu_rmap
= alloc_irq_cpu_rmap(bp
->rx_nr_rings
);
4495 static int bnxt_trim_rings(struct bnxt
*bp
, int *rx
, int *tx
, int max
,
4498 int _rx
= *rx
, _tx
= *tx
;
4501 *rx
= min_t(int, _rx
, max
);
4502 *tx
= min_t(int, _tx
, max
);
4507 while (_rx
+ _tx
> max
) {
4508 if (_rx
> _tx
&& _rx
> 1)
4519 static int bnxt_setup_msix(struct bnxt
*bp
)
4521 struct msix_entry
*msix_ent
;
4522 struct net_device
*dev
= bp
->dev
;
4523 int i
, total_vecs
, rc
= 0, min
= 1;
4524 const int len
= sizeof(bp
->irq_tbl
[0].name
);
4526 bp
->flags
&= ~BNXT_FLAG_USING_MSIX
;
4527 total_vecs
= bp
->cp_nr_rings
;
4529 msix_ent
= kcalloc(total_vecs
, sizeof(struct msix_entry
), GFP_KERNEL
);
4533 for (i
= 0; i
< total_vecs
; i
++) {
4534 msix_ent
[i
].entry
= i
;
4535 msix_ent
[i
].vector
= 0;
4538 if (!(bp
->flags
& BNXT_FLAG_SHARED_RINGS
))
4541 total_vecs
= pci_enable_msix_range(bp
->pdev
, msix_ent
, min
, total_vecs
);
4542 if (total_vecs
< 0) {
4544 goto msix_setup_exit
;
4547 bp
->irq_tbl
= kcalloc(total_vecs
, sizeof(struct bnxt_irq
), GFP_KERNEL
);
4551 /* Trim rings based upon num of vectors allocated */
4552 rc
= bnxt_trim_rings(bp
, &bp
->rx_nr_rings
, &bp
->tx_nr_rings
,
4553 total_vecs
, min
== 1);
4555 goto msix_setup_exit
;
4557 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
;
4558 tcs
= netdev_get_num_tc(dev
);
4560 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
/ tcs
;
4561 if (bp
->tx_nr_rings_per_tc
== 0) {
4562 netdev_reset_tc(dev
);
4563 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
;
4567 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
* tcs
;
4568 for (i
= 0; i
< tcs
; i
++) {
4569 count
= bp
->tx_nr_rings_per_tc
;
4571 netdev_set_tc_queue(dev
, i
, count
, off
);
4575 bp
->cp_nr_rings
= total_vecs
;
4577 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4580 bp
->irq_tbl
[i
].vector
= msix_ent
[i
].vector
;
4581 if (bp
->flags
& BNXT_FLAG_SHARED_RINGS
)
4583 else if (i
< bp
->rx_nr_rings
)
4588 snprintf(bp
->irq_tbl
[i
].name
, len
,
4589 "%s-%s-%d", dev
->name
, attr
, i
);
4590 bp
->irq_tbl
[i
].handler
= bnxt_msix
;
4592 rc
= bnxt_set_real_num_queues(bp
);
4594 goto msix_setup_exit
;
4597 goto msix_setup_exit
;
4599 bp
->flags
|= BNXT_FLAG_USING_MSIX
;
4604 netdev_err(bp
->dev
, "bnxt_setup_msix err: %x\n", rc
);
4605 pci_disable_msix(bp
->pdev
);
4610 static int bnxt_setup_inta(struct bnxt
*bp
)
4613 const int len
= sizeof(bp
->irq_tbl
[0].name
);
4615 if (netdev_get_num_tc(bp
->dev
))
4616 netdev_reset_tc(bp
->dev
);
4618 bp
->irq_tbl
= kcalloc(1, sizeof(struct bnxt_irq
), GFP_KERNEL
);
4623 bp
->rx_nr_rings
= 1;
4624 bp
->tx_nr_rings
= 1;
4625 bp
->cp_nr_rings
= 1;
4626 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
;
4627 bp
->flags
|= BNXT_FLAG_SHARED_RINGS
;
4628 bp
->irq_tbl
[0].vector
= bp
->pdev
->irq
;
4629 snprintf(bp
->irq_tbl
[0].name
, len
,
4630 "%s-%s-%d", bp
->dev
->name
, "TxRx", 0);
4631 bp
->irq_tbl
[0].handler
= bnxt_inta
;
4632 rc
= bnxt_set_real_num_queues(bp
);
4636 static int bnxt_setup_int_mode(struct bnxt
*bp
)
4640 if (bp
->flags
& BNXT_FLAG_MSIX_CAP
)
4641 rc
= bnxt_setup_msix(bp
);
4643 if (!(bp
->flags
& BNXT_FLAG_USING_MSIX
) && BNXT_PF(bp
)) {
4644 /* fallback to INTA */
4645 rc
= bnxt_setup_inta(bp
);
4650 static void bnxt_free_irq(struct bnxt
*bp
)
4652 struct bnxt_irq
*irq
;
4655 #ifdef CONFIG_RFS_ACCEL
4656 free_irq_cpu_rmap(bp
->dev
->rx_cpu_rmap
);
4657 bp
->dev
->rx_cpu_rmap
= NULL
;
4662 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4663 irq
= &bp
->irq_tbl
[i
];
4665 free_irq(irq
->vector
, bp
->bnapi
[i
]);
4668 if (bp
->flags
& BNXT_FLAG_USING_MSIX
)
4669 pci_disable_msix(bp
->pdev
);
4674 static int bnxt_request_irq(struct bnxt
*bp
)
4677 unsigned long flags
= 0;
4678 #ifdef CONFIG_RFS_ACCEL
4679 struct cpu_rmap
*rmap
= bp
->dev
->rx_cpu_rmap
;
4682 if (!(bp
->flags
& BNXT_FLAG_USING_MSIX
))
4683 flags
= IRQF_SHARED
;
4685 for (i
= 0, j
= 0; i
< bp
->cp_nr_rings
; i
++) {
4686 struct bnxt_irq
*irq
= &bp
->irq_tbl
[i
];
4687 #ifdef CONFIG_RFS_ACCEL
4688 if (rmap
&& bp
->bnapi
[i
]->rx_ring
) {
4689 rc
= irq_cpu_rmap_add(rmap
, irq
->vector
);
4691 netdev_warn(bp
->dev
, "failed adding irq rmap for ring %d\n",
4696 rc
= request_irq(irq
->vector
, irq
->handler
, flags
, irq
->name
,
4706 static void bnxt_del_napi(struct bnxt
*bp
)
4713 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4714 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4716 napi_hash_del(&bnapi
->napi
);
4717 netif_napi_del(&bnapi
->napi
);
4721 static void bnxt_init_napi(struct bnxt
*bp
)
4724 struct bnxt_napi
*bnapi
;
4726 if (bp
->flags
& BNXT_FLAG_USING_MSIX
) {
4727 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4728 bnapi
= bp
->bnapi
[i
];
4729 netif_napi_add(bp
->dev
, &bnapi
->napi
,
4733 bnapi
= bp
->bnapi
[0];
4734 netif_napi_add(bp
->dev
, &bnapi
->napi
, bnxt_poll
, 64);
4738 static void bnxt_disable_napi(struct bnxt
*bp
)
4745 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4746 napi_disable(&bp
->bnapi
[i
]->napi
);
4747 bnxt_disable_poll(bp
->bnapi
[i
]);
4751 static void bnxt_enable_napi(struct bnxt
*bp
)
4755 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4756 bp
->bnapi
[i
]->in_reset
= false;
4757 bnxt_enable_poll(bp
->bnapi
[i
]);
4758 napi_enable(&bp
->bnapi
[i
]->napi
);
4762 static void bnxt_tx_disable(struct bnxt
*bp
)
4765 struct bnxt_tx_ring_info
*txr
;
4766 struct netdev_queue
*txq
;
4769 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
4770 txr
= &bp
->tx_ring
[i
];
4771 txq
= netdev_get_tx_queue(bp
->dev
, i
);
4772 __netif_tx_lock(txq
, smp_processor_id());
4773 txr
->dev_state
= BNXT_DEV_STATE_CLOSING
;
4774 __netif_tx_unlock(txq
);
4777 /* Stop all TX queues */
4778 netif_tx_disable(bp
->dev
);
4779 netif_carrier_off(bp
->dev
);
4782 static void bnxt_tx_enable(struct bnxt
*bp
)
4785 struct bnxt_tx_ring_info
*txr
;
4786 struct netdev_queue
*txq
;
4788 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
4789 txr
= &bp
->tx_ring
[i
];
4790 txq
= netdev_get_tx_queue(bp
->dev
, i
);
4793 netif_tx_wake_all_queues(bp
->dev
);
4794 if (bp
->link_info
.link_up
)
4795 netif_carrier_on(bp
->dev
);
4798 static void bnxt_report_link(struct bnxt
*bp
)
4800 if (bp
->link_info
.link_up
) {
4802 const char *flow_ctrl
;
4805 netif_carrier_on(bp
->dev
);
4806 if (bp
->link_info
.duplex
== BNXT_LINK_DUPLEX_FULL
)
4810 if (bp
->link_info
.pause
== BNXT_LINK_PAUSE_BOTH
)
4811 flow_ctrl
= "ON - receive & transmit";
4812 else if (bp
->link_info
.pause
== BNXT_LINK_PAUSE_TX
)
4813 flow_ctrl
= "ON - transmit";
4814 else if (bp
->link_info
.pause
== BNXT_LINK_PAUSE_RX
)
4815 flow_ctrl
= "ON - receive";
4818 speed
= bnxt_fw_to_ethtool_speed(bp
->link_info
.link_speed
);
4819 netdev_info(bp
->dev
, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
4820 speed
, duplex
, flow_ctrl
);
4821 if (bp
->flags
& BNXT_FLAG_EEE_CAP
)
4822 netdev_info(bp
->dev
, "EEE is %s\n",
4823 bp
->eee
.eee_active
? "active" :
4826 netif_carrier_off(bp
->dev
);
4827 netdev_err(bp
->dev
, "NIC Link is Down\n");
4831 static int bnxt_hwrm_phy_qcaps(struct bnxt
*bp
)
4834 struct hwrm_port_phy_qcaps_input req
= {0};
4835 struct hwrm_port_phy_qcaps_output
*resp
= bp
->hwrm_cmd_resp_addr
;
4836 struct bnxt_link_info
*link_info
= &bp
->link_info
;
4838 if (bp
->hwrm_spec_code
< 0x10201)
4841 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_QCAPS
, -1, -1);
4843 mutex_lock(&bp
->hwrm_cmd_lock
);
4844 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4846 goto hwrm_phy_qcaps_exit
;
4848 if (resp
->eee_supported
& PORT_PHY_QCAPS_RESP_EEE_SUPPORTED
) {
4849 struct ethtool_eee
*eee
= &bp
->eee
;
4850 u16 fw_speeds
= le16_to_cpu(resp
->supported_speeds_eee_mode
);
4852 bp
->flags
|= BNXT_FLAG_EEE_CAP
;
4853 eee
->supported
= _bnxt_fw_to_ethtool_adv_spds(fw_speeds
, 0);
4854 bp
->lpi_tmr_lo
= le32_to_cpu(resp
->tx_lpi_timer_low
) &
4855 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK
;
4856 bp
->lpi_tmr_hi
= le32_to_cpu(resp
->valid_tx_lpi_timer_high
) &
4857 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK
;
4859 link_info
->support_auto_speeds
=
4860 le16_to_cpu(resp
->supported_speeds_auto_mode
);
4862 hwrm_phy_qcaps_exit
:
4863 mutex_unlock(&bp
->hwrm_cmd_lock
);
4867 static int bnxt_update_link(struct bnxt
*bp
, bool chng_link_state
)
4870 struct bnxt_link_info
*link_info
= &bp
->link_info
;
4871 struct hwrm_port_phy_qcfg_input req
= {0};
4872 struct hwrm_port_phy_qcfg_output
*resp
= bp
->hwrm_cmd_resp_addr
;
4873 u8 link_up
= link_info
->link_up
;
4875 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_QCFG
, -1, -1);
4877 mutex_lock(&bp
->hwrm_cmd_lock
);
4878 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4880 mutex_unlock(&bp
->hwrm_cmd_lock
);
4884 memcpy(&link_info
->phy_qcfg_resp
, resp
, sizeof(*resp
));
4885 link_info
->phy_link_status
= resp
->link
;
4886 link_info
->duplex
= resp
->duplex
;
4887 link_info
->pause
= resp
->pause
;
4888 link_info
->auto_mode
= resp
->auto_mode
;
4889 link_info
->auto_pause_setting
= resp
->auto_pause
;
4890 link_info
->lp_pause
= resp
->link_partner_adv_pause
;
4891 link_info
->force_pause_setting
= resp
->force_pause
;
4892 link_info
->duplex_setting
= resp
->duplex
;
4893 if (link_info
->phy_link_status
== BNXT_LINK_LINK
)
4894 link_info
->link_speed
= le16_to_cpu(resp
->link_speed
);
4896 link_info
->link_speed
= 0;
4897 link_info
->force_link_speed
= le16_to_cpu(resp
->force_link_speed
);
4898 link_info
->support_speeds
= le16_to_cpu(resp
->support_speeds
);
4899 link_info
->auto_link_speeds
= le16_to_cpu(resp
->auto_link_speed_mask
);
4900 link_info
->lp_auto_link_speeds
=
4901 le16_to_cpu(resp
->link_partner_adv_speeds
);
4902 link_info
->preemphasis
= le32_to_cpu(resp
->preemphasis
);
4903 link_info
->phy_ver
[0] = resp
->phy_maj
;
4904 link_info
->phy_ver
[1] = resp
->phy_min
;
4905 link_info
->phy_ver
[2] = resp
->phy_bld
;
4906 link_info
->media_type
= resp
->media_type
;
4907 link_info
->phy_type
= resp
->phy_type
;
4908 link_info
->transceiver
= resp
->xcvr_pkg_type
;
4909 link_info
->phy_addr
= resp
->eee_config_phy_addr
&
4910 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK
;
4911 link_info
->module_status
= resp
->module_status
;
4913 if (bp
->flags
& BNXT_FLAG_EEE_CAP
) {
4914 struct ethtool_eee
*eee
= &bp
->eee
;
4917 eee
->eee_active
= 0;
4918 if (resp
->eee_config_phy_addr
&
4919 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE
) {
4920 eee
->eee_active
= 1;
4921 fw_speeds
= le16_to_cpu(
4922 resp
->link_partner_adv_eee_link_speed_mask
);
4923 eee
->lp_advertised
=
4924 _bnxt_fw_to_ethtool_adv_spds(fw_speeds
, 0);
4927 /* Pull initial EEE config */
4928 if (!chng_link_state
) {
4929 if (resp
->eee_config_phy_addr
&
4930 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED
)
4931 eee
->eee_enabled
= 1;
4933 fw_speeds
= le16_to_cpu(resp
->adv_eee_link_speed_mask
);
4935 _bnxt_fw_to_ethtool_adv_spds(fw_speeds
, 0);
4937 if (resp
->eee_config_phy_addr
&
4938 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI
) {
4941 eee
->tx_lpi_enabled
= 1;
4942 tmr
= resp
->xcvr_identifier_type_tx_lpi_timer
;
4943 eee
->tx_lpi_timer
= le32_to_cpu(tmr
) &
4944 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK
;
4948 /* TODO: need to add more logic to report VF link */
4949 if (chng_link_state
) {
4950 if (link_info
->phy_link_status
== BNXT_LINK_LINK
)
4951 link_info
->link_up
= 1;
4953 link_info
->link_up
= 0;
4954 if (link_up
!= link_info
->link_up
)
4955 bnxt_report_link(bp
);
4957 /* alwasy link down if not require to update link state */
4958 link_info
->link_up
= 0;
4960 mutex_unlock(&bp
->hwrm_cmd_lock
);
4964 static void bnxt_get_port_module_status(struct bnxt
*bp
)
4966 struct bnxt_link_info
*link_info
= &bp
->link_info
;
4967 struct hwrm_port_phy_qcfg_output
*resp
= &link_info
->phy_qcfg_resp
;
4970 if (bnxt_update_link(bp
, true))
4973 module_status
= link_info
->module_status
;
4974 switch (module_status
) {
4975 case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX
:
4976 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN
:
4977 case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG
:
4978 netdev_warn(bp
->dev
, "Unqualified SFP+ module detected on port %d\n",
4980 if (bp
->hwrm_spec_code
>= 0x10201) {
4981 netdev_warn(bp
->dev
, "Module part number %s\n",
4982 resp
->phy_vendor_partnumber
);
4984 if (module_status
== PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX
)
4985 netdev_warn(bp
->dev
, "TX is disabled\n");
4986 if (module_status
== PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN
)
4987 netdev_warn(bp
->dev
, "SFP+ module is shutdown\n");
4992 bnxt_hwrm_set_pause_common(struct bnxt
*bp
, struct hwrm_port_phy_cfg_input
*req
)
4994 if (bp
->link_info
.autoneg
& BNXT_AUTONEG_FLOW_CTRL
) {
4995 if (bp
->hwrm_spec_code
>= 0x10201)
4997 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE
;
4998 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_RX
)
4999 req
->auto_pause
|= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX
;
5000 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_TX
)
5001 req
->auto_pause
|= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX
;
5003 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE
);
5005 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_RX
)
5006 req
->force_pause
|= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX
;
5007 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_TX
)
5008 req
->force_pause
|= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX
;
5010 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE
);
5011 if (bp
->hwrm_spec_code
>= 0x10201) {
5012 req
->auto_pause
= req
->force_pause
;
5013 req
->enables
|= cpu_to_le32(
5014 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE
);
5019 static void bnxt_hwrm_set_link_common(struct bnxt
*bp
,
5020 struct hwrm_port_phy_cfg_input
*req
)
5022 u8 autoneg
= bp
->link_info
.autoneg
;
5023 u16 fw_link_speed
= bp
->link_info
.req_link_speed
;
5024 u32 advertising
= bp
->link_info
.advertising
;
5026 if (autoneg
& BNXT_AUTONEG_SPEED
) {
5028 PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK
;
5030 req
->enables
|= cpu_to_le32(
5031 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK
);
5032 req
->auto_link_speed_mask
= cpu_to_le16(advertising
);
5034 req
->enables
|= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE
);
5036 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG
);
5038 req
->force_link_speed
= cpu_to_le16(fw_link_speed
);
5039 req
->flags
|= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE
);
5042 /* tell chimp that the setting takes effect immediately */
5043 req
->flags
|= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY
);
5046 int bnxt_hwrm_set_pause(struct bnxt
*bp
)
5048 struct hwrm_port_phy_cfg_input req
= {0};
5051 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_CFG
, -1, -1);
5052 bnxt_hwrm_set_pause_common(bp
, &req
);
5054 if ((bp
->link_info
.autoneg
& BNXT_AUTONEG_FLOW_CTRL
) ||
5055 bp
->link_info
.force_link_chng
)
5056 bnxt_hwrm_set_link_common(bp
, &req
);
5058 mutex_lock(&bp
->hwrm_cmd_lock
);
5059 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
5060 if (!rc
&& !(bp
->link_info
.autoneg
& BNXT_AUTONEG_FLOW_CTRL
)) {
5061 /* since changing of pause setting doesn't trigger any link
5062 * change event, the driver needs to update the current pause
5063 * result upon successfully return of the phy_cfg command
5065 bp
->link_info
.pause
=
5066 bp
->link_info
.force_pause_setting
= bp
->link_info
.req_flow_ctrl
;
5067 bp
->link_info
.auto_pause_setting
= 0;
5068 if (!bp
->link_info
.force_link_chng
)
5069 bnxt_report_link(bp
);
5071 bp
->link_info
.force_link_chng
= false;
5072 mutex_unlock(&bp
->hwrm_cmd_lock
);
5076 static void bnxt_hwrm_set_eee(struct bnxt
*bp
,
5077 struct hwrm_port_phy_cfg_input
*req
)
5079 struct ethtool_eee
*eee
= &bp
->eee
;
5081 if (eee
->eee_enabled
) {
5083 u32 flags
= PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE
;
5085 if (eee
->tx_lpi_enabled
)
5086 flags
|= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE
;
5088 flags
|= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE
;
5090 req
->flags
|= cpu_to_le32(flags
);
5091 eee_speeds
= bnxt_get_fw_auto_link_speeds(eee
->advertised
);
5092 req
->eee_link_speed_mask
= cpu_to_le16(eee_speeds
);
5093 req
->tx_lpi_timer
= cpu_to_le32(eee
->tx_lpi_timer
);
5095 req
->flags
|= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE
);
5099 int bnxt_hwrm_set_link_setting(struct bnxt
*bp
, bool set_pause
, bool set_eee
)
5101 struct hwrm_port_phy_cfg_input req
= {0};
5103 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_CFG
, -1, -1);
5105 bnxt_hwrm_set_pause_common(bp
, &req
);
5107 bnxt_hwrm_set_link_common(bp
, &req
);
5110 bnxt_hwrm_set_eee(bp
, &req
);
5111 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
5114 static int bnxt_hwrm_shutdown_link(struct bnxt
*bp
)
5116 struct hwrm_port_phy_cfg_input req
= {0};
5118 if (!BNXT_SINGLE_PF(bp
))
5121 if (pci_num_vf(bp
->pdev
))
5124 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_CFG
, -1, -1);
5125 req
.flags
= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DOWN
);
5126 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
5129 static bool bnxt_eee_config_ok(struct bnxt
*bp
)
5131 struct ethtool_eee
*eee
= &bp
->eee
;
5132 struct bnxt_link_info
*link_info
= &bp
->link_info
;
5134 if (!(bp
->flags
& BNXT_FLAG_EEE_CAP
))
5137 if (eee
->eee_enabled
) {
5139 _bnxt_fw_to_ethtool_adv_spds(link_info
->advertising
, 0);
5141 if (!(link_info
->autoneg
& BNXT_AUTONEG_SPEED
)) {
5142 eee
->eee_enabled
= 0;
5145 if (eee
->advertised
& ~advertising
) {
5146 eee
->advertised
= advertising
& eee
->supported
;
5153 static int bnxt_update_phy_setting(struct bnxt
*bp
)
5156 bool update_link
= false;
5157 bool update_pause
= false;
5158 bool update_eee
= false;
5159 struct bnxt_link_info
*link_info
= &bp
->link_info
;
5161 rc
= bnxt_update_link(bp
, true);
5163 netdev_err(bp
->dev
, "failed to update link (rc: %x)\n",
5167 if ((link_info
->autoneg
& BNXT_AUTONEG_FLOW_CTRL
) &&
5168 (link_info
->auto_pause_setting
& BNXT_LINK_PAUSE_BOTH
) !=
5169 link_info
->req_flow_ctrl
)
5170 update_pause
= true;
5171 if (!(link_info
->autoneg
& BNXT_AUTONEG_FLOW_CTRL
) &&
5172 link_info
->force_pause_setting
!= link_info
->req_flow_ctrl
)
5173 update_pause
= true;
5174 if (!(link_info
->autoneg
& BNXT_AUTONEG_SPEED
)) {
5175 if (BNXT_AUTO_MODE(link_info
->auto_mode
))
5177 if (link_info
->req_link_speed
!= link_info
->force_link_speed
)
5179 if (link_info
->req_duplex
!= link_info
->duplex_setting
)
5182 if (link_info
->auto_mode
== BNXT_LINK_AUTO_NONE
)
5184 if (link_info
->advertising
!= link_info
->auto_link_speeds
)
5188 if (!bnxt_eee_config_ok(bp
))
5192 rc
= bnxt_hwrm_set_link_setting(bp
, update_pause
, update_eee
);
5193 else if (update_pause
)
5194 rc
= bnxt_hwrm_set_pause(bp
);
5196 netdev_err(bp
->dev
, "failed to update phy setting (rc: %x)\n",
5204 /* Common routine to pre-map certain register block to different GRC window.
5205 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
5206 * in PF and 3 windows in VF that can be customized to map in different
5209 static void bnxt_preset_reg_win(struct bnxt
*bp
)
5212 /* CAG registers map to GRC window #4 */
5213 writel(BNXT_CAG_REG_BASE
,
5214 bp
->bar0
+ BNXT_GRCPF_REG_WINDOW_BASE_OUT
+ 12);
5218 static int __bnxt_open_nic(struct bnxt
*bp
, bool irq_re_init
, bool link_re_init
)
5222 bnxt_preset_reg_win(bp
);
5223 netif_carrier_off(bp
->dev
);
5225 rc
= bnxt_setup_int_mode(bp
);
5227 netdev_err(bp
->dev
, "bnxt_setup_int_mode err: %x\n",
5232 if ((bp
->flags
& BNXT_FLAG_RFS
) &&
5233 !(bp
->flags
& BNXT_FLAG_USING_MSIX
)) {
5234 /* disable RFS if falling back to INTA */
5235 bp
->dev
->hw_features
&= ~NETIF_F_NTUPLE
;
5236 bp
->flags
&= ~BNXT_FLAG_RFS
;
5239 rc
= bnxt_alloc_mem(bp
, irq_re_init
);
5241 netdev_err(bp
->dev
, "bnxt_alloc_mem err: %x\n", rc
);
5242 goto open_err_free_mem
;
5247 rc
= bnxt_request_irq(bp
);
5249 netdev_err(bp
->dev
, "bnxt_request_irq err: %x\n", rc
);
5254 bnxt_enable_napi(bp
);
5256 rc
= bnxt_init_nic(bp
, irq_re_init
);
5258 netdev_err(bp
->dev
, "bnxt_init_nic err: %x\n", rc
);
5263 rc
= bnxt_update_phy_setting(bp
);
5265 netdev_warn(bp
->dev
, "failed to update phy settings\n");
5269 udp_tunnel_get_rx_info(bp
->dev
);
5271 set_bit(BNXT_STATE_OPEN
, &bp
->state
);
5272 bnxt_enable_int(bp
);
5273 /* Enable TX queues */
5275 mod_timer(&bp
->timer
, jiffies
+ bp
->current_interval
);
5276 /* Poll link status and check for SFP+ module status */
5277 bnxt_get_port_module_status(bp
);
5282 bnxt_disable_napi(bp
);
5288 bnxt_free_mem(bp
, true);
5292 /* rtnl_lock held */
5293 int bnxt_open_nic(struct bnxt
*bp
, bool irq_re_init
, bool link_re_init
)
5297 rc
= __bnxt_open_nic(bp
, irq_re_init
, link_re_init
);
5299 netdev_err(bp
->dev
, "nic open fail (rc: %x)\n", rc
);
5305 static int bnxt_open(struct net_device
*dev
)
5307 struct bnxt
*bp
= netdev_priv(dev
);
5310 if (!test_bit(BNXT_STATE_FN_RST_DONE
, &bp
->state
)) {
5311 rc
= bnxt_hwrm_func_reset(bp
);
5313 netdev_err(bp
->dev
, "hwrm chip reset failure rc: %x\n",
5318 /* Do func_reset during the 1st PF open only to prevent killing
5319 * the VFs when the PF is brought down and up.
5322 set_bit(BNXT_STATE_FN_RST_DONE
, &bp
->state
);
5324 return __bnxt_open_nic(bp
, true, true);
5327 static void bnxt_disable_int_sync(struct bnxt
*bp
)
5331 atomic_inc(&bp
->intr_sem
);
5332 if (!netif_running(bp
->dev
))
5335 bnxt_disable_int(bp
);
5336 for (i
= 0; i
< bp
->cp_nr_rings
; i
++)
5337 synchronize_irq(bp
->irq_tbl
[i
].vector
);
5340 int bnxt_close_nic(struct bnxt
*bp
, bool irq_re_init
, bool link_re_init
)
5344 #ifdef CONFIG_BNXT_SRIOV
5345 if (bp
->sriov_cfg
) {
5346 rc
= wait_event_interruptible_timeout(bp
->sriov_cfg_wait
,
5348 BNXT_SRIOV_CFG_WAIT_TMO
);
5350 netdev_warn(bp
->dev
, "timeout waiting for SRIOV config operation to complete!\n");
5353 /* Change device state to avoid TX queue wake up's */
5354 bnxt_tx_disable(bp
);
5356 clear_bit(BNXT_STATE_OPEN
, &bp
->state
);
5357 smp_mb__after_atomic();
5358 while (test_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
))
5361 /* Flush rings before disabling interrupts */
5362 bnxt_shutdown_nic(bp
, irq_re_init
);
5364 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
5366 bnxt_disable_napi(bp
);
5367 bnxt_disable_int_sync(bp
);
5368 del_timer_sync(&bp
->timer
);
5375 bnxt_free_mem(bp
, irq_re_init
);
5379 static int bnxt_close(struct net_device
*dev
)
5381 struct bnxt
*bp
= netdev_priv(dev
);
5383 bnxt_close_nic(bp
, true, true);
5384 bnxt_hwrm_shutdown_link(bp
);
5388 /* rtnl_lock held */
5389 static int bnxt_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
5395 if (!netif_running(dev
))
5402 if (!netif_running(dev
))
5414 static struct rtnl_link_stats64
*
5415 bnxt_get_stats64(struct net_device
*dev
, struct rtnl_link_stats64
*stats
)
5418 struct bnxt
*bp
= netdev_priv(dev
);
5420 memset(stats
, 0, sizeof(struct rtnl_link_stats64
));
5425 /* TODO check if we need to synchronize with bnxt_close path */
5426 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
5427 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
5428 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
5429 struct ctx_hw_stats
*hw_stats
= cpr
->hw_stats
;
5431 stats
->rx_packets
+= le64_to_cpu(hw_stats
->rx_ucast_pkts
);
5432 stats
->rx_packets
+= le64_to_cpu(hw_stats
->rx_mcast_pkts
);
5433 stats
->rx_packets
+= le64_to_cpu(hw_stats
->rx_bcast_pkts
);
5435 stats
->tx_packets
+= le64_to_cpu(hw_stats
->tx_ucast_pkts
);
5436 stats
->tx_packets
+= le64_to_cpu(hw_stats
->tx_mcast_pkts
);
5437 stats
->tx_packets
+= le64_to_cpu(hw_stats
->tx_bcast_pkts
);
5439 stats
->rx_bytes
+= le64_to_cpu(hw_stats
->rx_ucast_bytes
);
5440 stats
->rx_bytes
+= le64_to_cpu(hw_stats
->rx_mcast_bytes
);
5441 stats
->rx_bytes
+= le64_to_cpu(hw_stats
->rx_bcast_bytes
);
5443 stats
->tx_bytes
+= le64_to_cpu(hw_stats
->tx_ucast_bytes
);
5444 stats
->tx_bytes
+= le64_to_cpu(hw_stats
->tx_mcast_bytes
);
5445 stats
->tx_bytes
+= le64_to_cpu(hw_stats
->tx_bcast_bytes
);
5447 stats
->rx_missed_errors
+=
5448 le64_to_cpu(hw_stats
->rx_discard_pkts
);
5450 stats
->multicast
+= le64_to_cpu(hw_stats
->rx_mcast_pkts
);
5452 stats
->tx_dropped
+= le64_to_cpu(hw_stats
->tx_drop_pkts
);
5455 if (bp
->flags
& BNXT_FLAG_PORT_STATS
) {
5456 struct rx_port_stats
*rx
= bp
->hw_rx_port_stats
;
5457 struct tx_port_stats
*tx
= bp
->hw_tx_port_stats
;
5459 stats
->rx_crc_errors
= le64_to_cpu(rx
->rx_fcs_err_frames
);
5460 stats
->rx_frame_errors
= le64_to_cpu(rx
->rx_align_err_frames
);
5461 stats
->rx_length_errors
= le64_to_cpu(rx
->rx_undrsz_frames
) +
5462 le64_to_cpu(rx
->rx_ovrsz_frames
) +
5463 le64_to_cpu(rx
->rx_runt_frames
);
5464 stats
->rx_errors
= le64_to_cpu(rx
->rx_false_carrier_frames
) +
5465 le64_to_cpu(rx
->rx_jbr_frames
);
5466 stats
->collisions
= le64_to_cpu(tx
->tx_total_collisions
);
5467 stats
->tx_fifo_errors
= le64_to_cpu(tx
->tx_fifo_underruns
);
5468 stats
->tx_errors
= le64_to_cpu(tx
->tx_err
);
5474 static bool bnxt_mc_list_updated(struct bnxt
*bp
, u32
*rx_mask
)
5476 struct net_device
*dev
= bp
->dev
;
5477 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
5478 struct netdev_hw_addr
*ha
;
5481 bool update
= false;
5484 netdev_for_each_mc_addr(ha
, dev
) {
5485 if (mc_count
>= BNXT_MAX_MC_ADDRS
) {
5486 *rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
;
5487 vnic
->mc_list_count
= 0;
5491 if (!ether_addr_equal(haddr
, vnic
->mc_list
+ off
)) {
5492 memcpy(vnic
->mc_list
+ off
, haddr
, ETH_ALEN
);
5499 *rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST
;
5501 if (mc_count
!= vnic
->mc_list_count
) {
5502 vnic
->mc_list_count
= mc_count
;
5508 static bool bnxt_uc_list_updated(struct bnxt
*bp
)
5510 struct net_device
*dev
= bp
->dev
;
5511 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
5512 struct netdev_hw_addr
*ha
;
5515 if (netdev_uc_count(dev
) != (vnic
->uc_filter_count
- 1))
5518 netdev_for_each_uc_addr(ha
, dev
) {
5519 if (!ether_addr_equal(ha
->addr
, vnic
->uc_list
+ off
))
5527 static void bnxt_set_rx_mode(struct net_device
*dev
)
5529 struct bnxt
*bp
= netdev_priv(dev
);
5530 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
5531 u32 mask
= vnic
->rx_mask
;
5532 bool mc_update
= false;
5535 if (!netif_running(dev
))
5538 mask
&= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
|
5539 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST
|
5540 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
);
5542 if ((dev
->flags
& IFF_PROMISC
) && bnxt_promisc_ok(bp
))
5543 mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
;
5545 uc_update
= bnxt_uc_list_updated(bp
);
5547 if (dev
->flags
& IFF_ALLMULTI
) {
5548 mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
;
5549 vnic
->mc_list_count
= 0;
5551 mc_update
= bnxt_mc_list_updated(bp
, &mask
);
5554 if (mask
!= vnic
->rx_mask
|| uc_update
|| mc_update
) {
5555 vnic
->rx_mask
= mask
;
5557 set_bit(BNXT_RX_MASK_SP_EVENT
, &bp
->sp_event
);
5558 schedule_work(&bp
->sp_task
);
5562 static int bnxt_cfg_rx_mode(struct bnxt
*bp
)
5564 struct net_device
*dev
= bp
->dev
;
5565 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
5566 struct netdev_hw_addr
*ha
;
5570 netif_addr_lock_bh(dev
);
5571 uc_update
= bnxt_uc_list_updated(bp
);
5572 netif_addr_unlock_bh(dev
);
5577 mutex_lock(&bp
->hwrm_cmd_lock
);
5578 for (i
= 1; i
< vnic
->uc_filter_count
; i
++) {
5579 struct hwrm_cfa_l2_filter_free_input req
= {0};
5581 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_L2_FILTER_FREE
, -1,
5584 req
.l2_filter_id
= vnic
->fw_l2_filter_id
[i
];
5586 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
5589 mutex_unlock(&bp
->hwrm_cmd_lock
);
5591 vnic
->uc_filter_count
= 1;
5593 netif_addr_lock_bh(dev
);
5594 if (netdev_uc_count(dev
) > (BNXT_MAX_UC_ADDRS
- 1)) {
5595 vnic
->rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
;
5597 netdev_for_each_uc_addr(ha
, dev
) {
5598 memcpy(vnic
->uc_list
+ off
, ha
->addr
, ETH_ALEN
);
5600 vnic
->uc_filter_count
++;
5603 netif_addr_unlock_bh(dev
);
5605 for (i
= 1, off
= 0; i
< vnic
->uc_filter_count
; i
++, off
+= ETH_ALEN
) {
5606 rc
= bnxt_hwrm_set_vnic_filter(bp
, 0, i
, vnic
->uc_list
+ off
);
5608 netdev_err(bp
->dev
, "HWRM vnic filter failure rc: %x\n",
5610 vnic
->uc_filter_count
= i
;
5616 rc
= bnxt_hwrm_cfa_l2_set_rx_mask(bp
, 0);
5618 netdev_err(bp
->dev
, "HWRM cfa l2 rx mask failure rc: %x\n",
5624 static bool bnxt_rfs_capable(struct bnxt
*bp
)
5626 #ifdef CONFIG_RFS_ACCEL
5627 struct bnxt_pf_info
*pf
= &bp
->pf
;
5630 if (BNXT_VF(bp
) || !(bp
->flags
& BNXT_FLAG_MSIX_CAP
))
5633 vnics
= 1 + bp
->rx_nr_rings
;
5634 if (vnics
> pf
->max_rsscos_ctxs
|| vnics
> pf
->max_vnics
)
5643 static netdev_features_t
bnxt_fix_features(struct net_device
*dev
,
5644 netdev_features_t features
)
5646 struct bnxt
*bp
= netdev_priv(dev
);
5648 if (!bnxt_rfs_capable(bp
))
5649 features
&= ~NETIF_F_NTUPLE
;
5651 /* Both CTAG and STAG VLAN accelaration on the RX side have to be
5652 * turned on or off together.
5654 if ((features
& (NETIF_F_HW_VLAN_CTAG_RX
| NETIF_F_HW_VLAN_STAG_RX
)) !=
5655 (NETIF_F_HW_VLAN_CTAG_RX
| NETIF_F_HW_VLAN_STAG_RX
)) {
5656 if (dev
->features
& NETIF_F_HW_VLAN_CTAG_RX
)
5657 features
&= ~(NETIF_F_HW_VLAN_CTAG_RX
|
5658 NETIF_F_HW_VLAN_STAG_RX
);
5660 features
|= NETIF_F_HW_VLAN_CTAG_RX
|
5661 NETIF_F_HW_VLAN_STAG_RX
;
5663 #ifdef CONFIG_BNXT_SRIOV
5666 features
&= ~(NETIF_F_HW_VLAN_CTAG_RX
|
5667 NETIF_F_HW_VLAN_STAG_RX
);
5674 static int bnxt_set_features(struct net_device
*dev
, netdev_features_t features
)
5676 struct bnxt
*bp
= netdev_priv(dev
);
5677 u32 flags
= bp
->flags
;
5680 bool re_init
= false;
5681 bool update_tpa
= false;
5683 flags
&= ~BNXT_FLAG_ALL_CONFIG_FEATS
;
5684 if ((features
& NETIF_F_GRO
) && (bp
->pdev
->revision
> 0))
5685 flags
|= BNXT_FLAG_GRO
;
5686 if (features
& NETIF_F_LRO
)
5687 flags
|= BNXT_FLAG_LRO
;
5689 if (features
& NETIF_F_HW_VLAN_CTAG_RX
)
5690 flags
|= BNXT_FLAG_STRIP_VLAN
;
5692 if (features
& NETIF_F_NTUPLE
)
5693 flags
|= BNXT_FLAG_RFS
;
5695 changes
= flags
^ bp
->flags
;
5696 if (changes
& BNXT_FLAG_TPA
) {
5698 if ((bp
->flags
& BNXT_FLAG_TPA
) == 0 ||
5699 (flags
& BNXT_FLAG_TPA
) == 0)
5703 if (changes
& ~BNXT_FLAG_TPA
)
5706 if (flags
!= bp
->flags
) {
5707 u32 old_flags
= bp
->flags
;
5711 if (!test_bit(BNXT_STATE_OPEN
, &bp
->state
)) {
5713 bnxt_set_ring_params(bp
);
5718 bnxt_close_nic(bp
, false, false);
5720 bnxt_set_ring_params(bp
);
5722 return bnxt_open_nic(bp
, false, false);
5725 rc
= bnxt_set_tpa(bp
,
5726 (flags
& BNXT_FLAG_TPA
) ?
5729 bp
->flags
= old_flags
;
5735 static void bnxt_dump_tx_sw_state(struct bnxt_napi
*bnapi
)
5737 struct bnxt_tx_ring_info
*txr
= bnapi
->tx_ring
;
5738 int i
= bnapi
->index
;
5743 netdev_info(bnapi
->bp
->dev
, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
5744 i
, txr
->tx_ring_struct
.fw_ring_id
, txr
->tx_prod
,
5748 static void bnxt_dump_rx_sw_state(struct bnxt_napi
*bnapi
)
5750 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
5751 int i
= bnapi
->index
;
5756 netdev_info(bnapi
->bp
->dev
, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
5757 i
, rxr
->rx_ring_struct
.fw_ring_id
, rxr
->rx_prod
,
5758 rxr
->rx_agg_ring_struct
.fw_ring_id
, rxr
->rx_agg_prod
,
5759 rxr
->rx_sw_agg_prod
);
5762 static void bnxt_dump_cp_sw_state(struct bnxt_napi
*bnapi
)
5764 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
5765 int i
= bnapi
->index
;
5767 netdev_info(bnapi
->bp
->dev
, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
5768 i
, cpr
->cp_ring_struct
.fw_ring_id
, cpr
->cp_raw_cons
);
5771 static void bnxt_dbg_dump_states(struct bnxt
*bp
)
5774 struct bnxt_napi
*bnapi
;
5776 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
5777 bnapi
= bp
->bnapi
[i
];
5778 if (netif_msg_drv(bp
)) {
5779 bnxt_dump_tx_sw_state(bnapi
);
5780 bnxt_dump_rx_sw_state(bnapi
);
5781 bnxt_dump_cp_sw_state(bnapi
);
5786 static void bnxt_reset_task(struct bnxt
*bp
, bool silent
)
5789 bnxt_dbg_dump_states(bp
);
5790 if (netif_running(bp
->dev
)) {
5791 bnxt_close_nic(bp
, false, false);
5792 bnxt_open_nic(bp
, false, false);
5796 static void bnxt_tx_timeout(struct net_device
*dev
)
5798 struct bnxt
*bp
= netdev_priv(dev
);
5800 netdev_err(bp
->dev
, "TX timeout detected, starting reset task!\n");
5801 set_bit(BNXT_RESET_TASK_SP_EVENT
, &bp
->sp_event
);
5802 schedule_work(&bp
->sp_task
);
5805 #ifdef CONFIG_NET_POLL_CONTROLLER
5806 static void bnxt_poll_controller(struct net_device
*dev
)
5808 struct bnxt
*bp
= netdev_priv(dev
);
5811 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
5812 struct bnxt_irq
*irq
= &bp
->irq_tbl
[i
];
5814 disable_irq(irq
->vector
);
5815 irq
->handler(irq
->vector
, bp
->bnapi
[i
]);
5816 enable_irq(irq
->vector
);
5821 static void bnxt_timer(unsigned long data
)
5823 struct bnxt
*bp
= (struct bnxt
*)data
;
5824 struct net_device
*dev
= bp
->dev
;
5826 if (!netif_running(dev
))
5829 if (atomic_read(&bp
->intr_sem
) != 0)
5830 goto bnxt_restart_timer
;
5832 if (bp
->link_info
.link_up
&& (bp
->flags
& BNXT_FLAG_PORT_STATS
)) {
5833 set_bit(BNXT_PERIODIC_STATS_SP_EVENT
, &bp
->sp_event
);
5834 schedule_work(&bp
->sp_task
);
5837 mod_timer(&bp
->timer
, jiffies
+ bp
->current_interval
);
5840 /* Only called from bnxt_sp_task() */
5841 static void bnxt_reset(struct bnxt
*bp
, bool silent
)
5843 /* bnxt_reset_task() calls bnxt_close_nic() which waits
5844 * for BNXT_STATE_IN_SP_TASK to clear.
5845 * If there is a parallel dev_close(), bnxt_close() may be holding
5846 * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we
5847 * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
5849 clear_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
5851 if (test_bit(BNXT_STATE_OPEN
, &bp
->state
))
5852 bnxt_reset_task(bp
, silent
);
5853 set_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
5857 static void bnxt_cfg_ntp_filters(struct bnxt
*);
5859 static void bnxt_sp_task(struct work_struct
*work
)
5861 struct bnxt
*bp
= container_of(work
, struct bnxt
, sp_task
);
5864 set_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
5865 smp_mb__after_atomic();
5866 if (!test_bit(BNXT_STATE_OPEN
, &bp
->state
)) {
5867 clear_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
5871 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT
, &bp
->sp_event
))
5872 bnxt_cfg_rx_mode(bp
);
5874 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT
, &bp
->sp_event
))
5875 bnxt_cfg_ntp_filters(bp
);
5876 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT
, &bp
->sp_event
)) {
5877 rc
= bnxt_update_link(bp
, true);
5879 netdev_err(bp
->dev
, "SP task can't update link (rc: %x)\n",
5882 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT
, &bp
->sp_event
))
5883 bnxt_hwrm_exec_fwd_req(bp
);
5884 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT
, &bp
->sp_event
)) {
5885 bnxt_hwrm_tunnel_dst_port_alloc(
5887 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
);
5889 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT
, &bp
->sp_event
)) {
5890 bnxt_hwrm_tunnel_dst_port_free(
5891 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
);
5893 if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT
, &bp
->sp_event
)) {
5894 bnxt_hwrm_tunnel_dst_port_alloc(
5896 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
);
5898 if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT
, &bp
->sp_event
)) {
5899 bnxt_hwrm_tunnel_dst_port_free(
5900 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
);
5902 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT
, &bp
->sp_event
))
5903 bnxt_reset(bp
, false);
5905 if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT
, &bp
->sp_event
))
5906 bnxt_reset(bp
, true);
5908 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT
, &bp
->sp_event
))
5909 bnxt_get_port_module_status(bp
);
5911 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT
, &bp
->sp_event
))
5912 bnxt_hwrm_port_qstats(bp
);
5914 smp_mb__before_atomic();
5915 clear_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
5918 static int bnxt_init_board(struct pci_dev
*pdev
, struct net_device
*dev
)
5921 struct bnxt
*bp
= netdev_priv(dev
);
5923 SET_NETDEV_DEV(dev
, &pdev
->dev
);
5925 /* enable device (incl. PCI PM wakeup), and bus-mastering */
5926 rc
= pci_enable_device(pdev
);
5928 dev_err(&pdev
->dev
, "Cannot enable PCI device, aborting\n");
5932 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
5934 "Cannot find PCI device base address, aborting\n");
5936 goto init_err_disable
;
5939 rc
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
5941 dev_err(&pdev
->dev
, "Cannot obtain PCI resources, aborting\n");
5942 goto init_err_disable
;
5945 if (dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(64)) != 0 &&
5946 dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(32)) != 0) {
5947 dev_err(&pdev
->dev
, "System does not support DMA, aborting\n");
5948 goto init_err_disable
;
5951 pci_set_master(pdev
);
5956 bp
->bar0
= pci_ioremap_bar(pdev
, 0);
5958 dev_err(&pdev
->dev
, "Cannot map device registers, aborting\n");
5960 goto init_err_release
;
5963 bp
->bar1
= pci_ioremap_bar(pdev
, 2);
5965 dev_err(&pdev
->dev
, "Cannot map doorbell registers, aborting\n");
5967 goto init_err_release
;
5970 bp
->bar2
= pci_ioremap_bar(pdev
, 4);
5972 dev_err(&pdev
->dev
, "Cannot map bar4 registers, aborting\n");
5974 goto init_err_release
;
5977 pci_enable_pcie_error_reporting(pdev
);
5979 INIT_WORK(&bp
->sp_task
, bnxt_sp_task
);
5981 spin_lock_init(&bp
->ntp_fltr_lock
);
5983 bp
->rx_ring_size
= BNXT_DEFAULT_RX_RING_SIZE
;
5984 bp
->tx_ring_size
= BNXT_DEFAULT_TX_RING_SIZE
;
5986 /* tick values in micro seconds */
5987 bp
->rx_coal_ticks
= 12;
5988 bp
->rx_coal_bufs
= 30;
5989 bp
->rx_coal_ticks_irq
= 1;
5990 bp
->rx_coal_bufs_irq
= 2;
5992 bp
->tx_coal_ticks
= 25;
5993 bp
->tx_coal_bufs
= 30;
5994 bp
->tx_coal_ticks_irq
= 2;
5995 bp
->tx_coal_bufs_irq
= 2;
5997 bp
->stats_coal_ticks
= BNXT_DEF_STATS_COAL_TICKS
;
5999 init_timer(&bp
->timer
);
6000 bp
->timer
.data
= (unsigned long)bp
;
6001 bp
->timer
.function
= bnxt_timer
;
6002 bp
->current_interval
= BNXT_TIMER_INTERVAL
;
6004 clear_bit(BNXT_STATE_OPEN
, &bp
->state
);
6010 pci_iounmap(pdev
, bp
->bar2
);
6015 pci_iounmap(pdev
, bp
->bar1
);
6020 pci_iounmap(pdev
, bp
->bar0
);
6024 pci_release_regions(pdev
);
6027 pci_disable_device(pdev
);
6033 /* rtnl_lock held */
6034 static int bnxt_change_mac_addr(struct net_device
*dev
, void *p
)
6036 struct sockaddr
*addr
= p
;
6037 struct bnxt
*bp
= netdev_priv(dev
);
6040 if (!is_valid_ether_addr(addr
->sa_data
))
6041 return -EADDRNOTAVAIL
;
6043 rc
= bnxt_approve_mac(bp
, addr
->sa_data
);
6047 if (ether_addr_equal(addr
->sa_data
, dev
->dev_addr
))
6050 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
6051 if (netif_running(dev
)) {
6052 bnxt_close_nic(bp
, false, false);
6053 rc
= bnxt_open_nic(bp
, false, false);
6059 /* rtnl_lock held */
6060 static int bnxt_change_mtu(struct net_device
*dev
, int new_mtu
)
6062 struct bnxt
*bp
= netdev_priv(dev
);
6064 if (new_mtu
< 60 || new_mtu
> 9500)
6067 if (netif_running(dev
))
6068 bnxt_close_nic(bp
, false, false);
6071 bnxt_set_ring_params(bp
);
6073 if (netif_running(dev
))
6074 return bnxt_open_nic(bp
, false, false);
6079 static int bnxt_setup_tc(struct net_device
*dev
, u32 handle
, __be16 proto
,
6080 struct tc_to_netdev
*ntc
)
6082 struct bnxt
*bp
= netdev_priv(dev
);
6085 if (ntc
->type
!= TC_SETUP_MQPRIO
)
6090 if (tc
> bp
->max_tc
) {
6091 netdev_err(dev
, "too many traffic classes requested: %d Max supported is %d\n",
6096 if (netdev_get_num_tc(dev
) == tc
)
6100 int max_rx_rings
, max_tx_rings
, rc
;
6103 if (bp
->flags
& BNXT_FLAG_SHARED_RINGS
)
6106 rc
= bnxt_get_max_rings(bp
, &max_rx_rings
, &max_tx_rings
, sh
);
6107 if (rc
|| bp
->tx_nr_rings_per_tc
* tc
> max_tx_rings
)
6111 /* Needs to close the device and do hw resource re-allocations */
6112 if (netif_running(bp
->dev
))
6113 bnxt_close_nic(bp
, true, false);
6116 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
* tc
;
6117 netdev_set_num_tc(dev
, tc
);
6119 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
;
6120 netdev_reset_tc(dev
);
6122 bp
->cp_nr_rings
= max_t(int, bp
->tx_nr_rings
, bp
->rx_nr_rings
);
6123 bp
->num_stat_ctxs
= bp
->cp_nr_rings
;
6125 if (netif_running(bp
->dev
))
6126 return bnxt_open_nic(bp
, true, false);
6131 #ifdef CONFIG_RFS_ACCEL
6132 static bool bnxt_fltr_match(struct bnxt_ntuple_filter
*f1
,
6133 struct bnxt_ntuple_filter
*f2
)
6135 struct flow_keys
*keys1
= &f1
->fkeys
;
6136 struct flow_keys
*keys2
= &f2
->fkeys
;
6138 if (keys1
->addrs
.v4addrs
.src
== keys2
->addrs
.v4addrs
.src
&&
6139 keys1
->addrs
.v4addrs
.dst
== keys2
->addrs
.v4addrs
.dst
&&
6140 keys1
->ports
.ports
== keys2
->ports
.ports
&&
6141 keys1
->basic
.ip_proto
== keys2
->basic
.ip_proto
&&
6142 keys1
->basic
.n_proto
== keys2
->basic
.n_proto
&&
6143 ether_addr_equal(f1
->src_mac_addr
, f2
->src_mac_addr
))
6149 static int bnxt_rx_flow_steer(struct net_device
*dev
, const struct sk_buff
*skb
,
6150 u16 rxq_index
, u32 flow_id
)
6152 struct bnxt
*bp
= netdev_priv(dev
);
6153 struct bnxt_ntuple_filter
*fltr
, *new_fltr
;
6154 struct flow_keys
*fkeys
;
6155 struct ethhdr
*eth
= (struct ethhdr
*)skb_mac_header(skb
);
6156 int rc
= 0, idx
, bit_id
;
6157 struct hlist_head
*head
;
6159 if (skb
->encapsulation
)
6160 return -EPROTONOSUPPORT
;
6162 new_fltr
= kzalloc(sizeof(*new_fltr
), GFP_ATOMIC
);
6166 fkeys
= &new_fltr
->fkeys
;
6167 if (!skb_flow_dissect_flow_keys(skb
, fkeys
, 0)) {
6168 rc
= -EPROTONOSUPPORT
;
6172 if ((fkeys
->basic
.n_proto
!= htons(ETH_P_IP
)) ||
6173 ((fkeys
->basic
.ip_proto
!= IPPROTO_TCP
) &&
6174 (fkeys
->basic
.ip_proto
!= IPPROTO_UDP
))) {
6175 rc
= -EPROTONOSUPPORT
;
6179 memcpy(new_fltr
->src_mac_addr
, eth
->h_source
, ETH_ALEN
);
6181 idx
= skb_get_hash_raw(skb
) & BNXT_NTP_FLTR_HASH_MASK
;
6182 head
= &bp
->ntp_fltr_hash_tbl
[idx
];
6184 hlist_for_each_entry_rcu(fltr
, head
, hash
) {
6185 if (bnxt_fltr_match(fltr
, new_fltr
)) {
6193 spin_lock_bh(&bp
->ntp_fltr_lock
);
6194 bit_id
= bitmap_find_free_region(bp
->ntp_fltr_bmap
,
6195 BNXT_NTP_FLTR_MAX_FLTR
, 0);
6197 spin_unlock_bh(&bp
->ntp_fltr_lock
);
6202 new_fltr
->sw_id
= (u16
)bit_id
;
6203 new_fltr
->flow_id
= flow_id
;
6204 new_fltr
->rxq
= rxq_index
;
6205 hlist_add_head_rcu(&new_fltr
->hash
, head
);
6206 bp
->ntp_fltr_count
++;
6207 spin_unlock_bh(&bp
->ntp_fltr_lock
);
6209 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT
, &bp
->sp_event
);
6210 schedule_work(&bp
->sp_task
);
6212 return new_fltr
->sw_id
;
6219 static void bnxt_cfg_ntp_filters(struct bnxt
*bp
)
6223 for (i
= 0; i
< BNXT_NTP_FLTR_HASH_SIZE
; i
++) {
6224 struct hlist_head
*head
;
6225 struct hlist_node
*tmp
;
6226 struct bnxt_ntuple_filter
*fltr
;
6229 head
= &bp
->ntp_fltr_hash_tbl
[i
];
6230 hlist_for_each_entry_safe(fltr
, tmp
, head
, hash
) {
6233 if (test_bit(BNXT_FLTR_VALID
, &fltr
->state
)) {
6234 if (rps_may_expire_flow(bp
->dev
, fltr
->rxq
,
6237 bnxt_hwrm_cfa_ntuple_filter_free(bp
,
6242 rc
= bnxt_hwrm_cfa_ntuple_filter_alloc(bp
,
6247 set_bit(BNXT_FLTR_VALID
, &fltr
->state
);
6251 spin_lock_bh(&bp
->ntp_fltr_lock
);
6252 hlist_del_rcu(&fltr
->hash
);
6253 bp
->ntp_fltr_count
--;
6254 spin_unlock_bh(&bp
->ntp_fltr_lock
);
6256 clear_bit(fltr
->sw_id
, bp
->ntp_fltr_bmap
);
6261 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT
, &bp
->sp_event
))
6262 netdev_info(bp
->dev
, "Receive PF driver unload event!");
6267 static void bnxt_cfg_ntp_filters(struct bnxt
*bp
)
6271 #endif /* CONFIG_RFS_ACCEL */
6273 static void bnxt_udp_tunnel_add(struct net_device
*dev
,
6274 struct udp_tunnel_info
*ti
)
6276 struct bnxt
*bp
= netdev_priv(dev
);
6278 if (ti
->sa_family
!= AF_INET6
&& ti
->sa_family
!= AF_INET
)
6281 if (!netif_running(dev
))
6285 case UDP_TUNNEL_TYPE_VXLAN
:
6286 if (bp
->vxlan_port_cnt
&& bp
->vxlan_port
!= ti
->port
)
6289 bp
->vxlan_port_cnt
++;
6290 if (bp
->vxlan_port_cnt
== 1) {
6291 bp
->vxlan_port
= ti
->port
;
6292 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT
, &bp
->sp_event
);
6293 schedule_work(&bp
->sp_task
);
6296 case UDP_TUNNEL_TYPE_GENEVE
:
6297 if (bp
->nge_port_cnt
&& bp
->nge_port
!= ti
->port
)
6301 if (bp
->nge_port_cnt
== 1) {
6302 bp
->nge_port
= ti
->port
;
6303 set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT
, &bp
->sp_event
);
6310 schedule_work(&bp
->sp_task
);
6313 static void bnxt_udp_tunnel_del(struct net_device
*dev
,
6314 struct udp_tunnel_info
*ti
)
6316 struct bnxt
*bp
= netdev_priv(dev
);
6318 if (ti
->sa_family
!= AF_INET6
&& ti
->sa_family
!= AF_INET
)
6321 if (!netif_running(dev
))
6325 case UDP_TUNNEL_TYPE_VXLAN
:
6326 if (!bp
->vxlan_port_cnt
|| bp
->vxlan_port
!= ti
->port
)
6328 bp
->vxlan_port_cnt
--;
6330 if (bp
->vxlan_port_cnt
!= 0)
6333 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT
, &bp
->sp_event
);
6335 case UDP_TUNNEL_TYPE_GENEVE
:
6336 if (!bp
->nge_port_cnt
|| bp
->nge_port
!= ti
->port
)
6340 if (bp
->nge_port_cnt
!= 0)
6343 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT
, &bp
->sp_event
);
6349 schedule_work(&bp
->sp_task
);
6352 static const struct net_device_ops bnxt_netdev_ops
= {
6353 .ndo_open
= bnxt_open
,
6354 .ndo_start_xmit
= bnxt_start_xmit
,
6355 .ndo_stop
= bnxt_close
,
6356 .ndo_get_stats64
= bnxt_get_stats64
,
6357 .ndo_set_rx_mode
= bnxt_set_rx_mode
,
6358 .ndo_do_ioctl
= bnxt_ioctl
,
6359 .ndo_validate_addr
= eth_validate_addr
,
6360 .ndo_set_mac_address
= bnxt_change_mac_addr
,
6361 .ndo_change_mtu
= bnxt_change_mtu
,
6362 .ndo_fix_features
= bnxt_fix_features
,
6363 .ndo_set_features
= bnxt_set_features
,
6364 .ndo_tx_timeout
= bnxt_tx_timeout
,
6365 #ifdef CONFIG_BNXT_SRIOV
6366 .ndo_get_vf_config
= bnxt_get_vf_config
,
6367 .ndo_set_vf_mac
= bnxt_set_vf_mac
,
6368 .ndo_set_vf_vlan
= bnxt_set_vf_vlan
,
6369 .ndo_set_vf_rate
= bnxt_set_vf_bw
,
6370 .ndo_set_vf_link_state
= bnxt_set_vf_link_state
,
6371 .ndo_set_vf_spoofchk
= bnxt_set_vf_spoofchk
,
6373 #ifdef CONFIG_NET_POLL_CONTROLLER
6374 .ndo_poll_controller
= bnxt_poll_controller
,
6376 .ndo_setup_tc
= bnxt_setup_tc
,
6377 #ifdef CONFIG_RFS_ACCEL
6378 .ndo_rx_flow_steer
= bnxt_rx_flow_steer
,
6380 .ndo_udp_tunnel_add
= bnxt_udp_tunnel_add
,
6381 .ndo_udp_tunnel_del
= bnxt_udp_tunnel_del
,
6382 #ifdef CONFIG_NET_RX_BUSY_POLL
6383 .ndo_busy_poll
= bnxt_busy_poll
,
6387 static void bnxt_remove_one(struct pci_dev
*pdev
)
6389 struct net_device
*dev
= pci_get_drvdata(pdev
);
6390 struct bnxt
*bp
= netdev_priv(dev
);
6393 bnxt_sriov_disable(bp
);
6395 pci_disable_pcie_error_reporting(pdev
);
6396 unregister_netdev(dev
);
6397 cancel_work_sync(&bp
->sp_task
);
6400 bnxt_hwrm_func_drv_unrgtr(bp
);
6401 bnxt_free_hwrm_resources(bp
);
6402 pci_iounmap(pdev
, bp
->bar2
);
6403 pci_iounmap(pdev
, bp
->bar1
);
6404 pci_iounmap(pdev
, bp
->bar0
);
6407 pci_release_regions(pdev
);
6408 pci_disable_device(pdev
);
6411 static int bnxt_probe_phy(struct bnxt
*bp
)
6414 struct bnxt_link_info
*link_info
= &bp
->link_info
;
6416 rc
= bnxt_hwrm_phy_qcaps(bp
);
6418 netdev_err(bp
->dev
, "Probe phy can't get phy capabilities (rc: %x)\n",
6423 rc
= bnxt_update_link(bp
, false);
6425 netdev_err(bp
->dev
, "Probe phy can't update link (rc: %x)\n",
6430 /* Older firmware does not have supported_auto_speeds, so assume
6431 * that all supported speeds can be autonegotiated.
6433 if (link_info
->auto_link_speeds
&& !link_info
->support_auto_speeds
)
6434 link_info
->support_auto_speeds
= link_info
->support_speeds
;
6436 /*initialize the ethool setting copy with NVM settings */
6437 if (BNXT_AUTO_MODE(link_info
->auto_mode
)) {
6438 link_info
->autoneg
= BNXT_AUTONEG_SPEED
;
6439 if (bp
->hwrm_spec_code
>= 0x10201) {
6440 if (link_info
->auto_pause_setting
&
6441 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE
)
6442 link_info
->autoneg
|= BNXT_AUTONEG_FLOW_CTRL
;
6444 link_info
->autoneg
|= BNXT_AUTONEG_FLOW_CTRL
;
6446 link_info
->advertising
= link_info
->auto_link_speeds
;
6448 link_info
->req_link_speed
= link_info
->force_link_speed
;
6449 link_info
->req_duplex
= link_info
->duplex_setting
;
6451 if (link_info
->autoneg
& BNXT_AUTONEG_FLOW_CTRL
)
6452 link_info
->req_flow_ctrl
=
6453 link_info
->auto_pause_setting
& BNXT_LINK_PAUSE_BOTH
;
6455 link_info
->req_flow_ctrl
= link_info
->force_pause_setting
;
6459 static int bnxt_get_max_irq(struct pci_dev
*pdev
)
6463 if (!pdev
->msix_cap
)
6466 pci_read_config_word(pdev
, pdev
->msix_cap
+ PCI_MSIX_FLAGS
, &ctrl
);
6467 return (ctrl
& PCI_MSIX_FLAGS_QSIZE
) + 1;
6470 static void _bnxt_get_max_rings(struct bnxt
*bp
, int *max_rx
, int *max_tx
,
6473 int max_ring_grps
= 0;
6475 #ifdef CONFIG_BNXT_SRIOV
6477 *max_tx
= bp
->vf
.max_tx_rings
;
6478 *max_rx
= bp
->vf
.max_rx_rings
;
6479 *max_cp
= min_t(int, bp
->vf
.max_irqs
, bp
->vf
.max_cp_rings
);
6480 *max_cp
= min_t(int, *max_cp
, bp
->vf
.max_stat_ctxs
);
6481 max_ring_grps
= bp
->vf
.max_hw_ring_grps
;
6485 *max_tx
= bp
->pf
.max_tx_rings
;
6486 *max_rx
= bp
->pf
.max_rx_rings
;
6487 *max_cp
= min_t(int, bp
->pf
.max_irqs
, bp
->pf
.max_cp_rings
);
6488 *max_cp
= min_t(int, *max_cp
, bp
->pf
.max_stat_ctxs
);
6489 max_ring_grps
= bp
->pf
.max_hw_ring_grps
;
6492 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
)
6494 *max_rx
= min_t(int, *max_rx
, max_ring_grps
);
6497 int bnxt_get_max_rings(struct bnxt
*bp
, int *max_rx
, int *max_tx
, bool shared
)
6501 _bnxt_get_max_rings(bp
, &rx
, &tx
, &cp
);
6502 if (!rx
|| !tx
|| !cp
)
6507 return bnxt_trim_rings(bp
, max_rx
, max_tx
, cp
, shared
);
6510 static int bnxt_set_dflt_rings(struct bnxt
*bp
)
6512 int dflt_rings
, max_rx_rings
, max_tx_rings
, rc
;
6516 bp
->flags
|= BNXT_FLAG_SHARED_RINGS
;
6517 dflt_rings
= netif_get_num_default_rss_queues();
6518 rc
= bnxt_get_max_rings(bp
, &max_rx_rings
, &max_tx_rings
, sh
);
6521 bp
->rx_nr_rings
= min_t(int, dflt_rings
, max_rx_rings
);
6522 bp
->tx_nr_rings_per_tc
= min_t(int, dflt_rings
, max_tx_rings
);
6523 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
;
6524 bp
->cp_nr_rings
= sh
? max_t(int, bp
->tx_nr_rings
, bp
->rx_nr_rings
) :
6525 bp
->tx_nr_rings
+ bp
->rx_nr_rings
;
6526 bp
->num_stat_ctxs
= bp
->cp_nr_rings
;
6530 static void bnxt_parse_log_pcie_link(struct bnxt
*bp
)
6532 enum pcie_link_width width
= PCIE_LNK_WIDTH_UNKNOWN
;
6533 enum pci_bus_speed speed
= PCI_SPEED_UNKNOWN
;
6535 if (pcie_get_minimum_link(bp
->pdev
, &speed
, &width
) ||
6536 speed
== PCI_SPEED_UNKNOWN
|| width
== PCIE_LNK_WIDTH_UNKNOWN
)
6537 netdev_info(bp
->dev
, "Failed to determine PCIe Link Info\n");
6539 netdev_info(bp
->dev
, "PCIe: Speed %s Width x%d\n",
6540 speed
== PCIE_SPEED_2_5GT
? "2.5GT/s" :
6541 speed
== PCIE_SPEED_5_0GT
? "5.0GT/s" :
6542 speed
== PCIE_SPEED_8_0GT
? "8.0GT/s" :
6546 static int bnxt_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
6548 static int version_printed
;
6549 struct net_device
*dev
;
6553 if (version_printed
++ == 0)
6554 pr_info("%s", version
);
6556 max_irqs
= bnxt_get_max_irq(pdev
);
6557 dev
= alloc_etherdev_mq(sizeof(*bp
), max_irqs
);
6561 bp
= netdev_priv(dev
);
6563 if (bnxt_vf_pciid(ent
->driver_data
))
6564 bp
->flags
|= BNXT_FLAG_VF
;
6567 bp
->flags
|= BNXT_FLAG_MSIX_CAP
;
6569 rc
= bnxt_init_board(pdev
, dev
);
6573 dev
->netdev_ops
= &bnxt_netdev_ops
;
6574 dev
->watchdog_timeo
= BNXT_TX_TIMEOUT
;
6575 dev
->ethtool_ops
= &bnxt_ethtool_ops
;
6577 pci_set_drvdata(pdev
, dev
);
6579 dev
->hw_features
= NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
| NETIF_F_SG
|
6580 NETIF_F_TSO
| NETIF_F_TSO6
|
6581 NETIF_F_GSO_UDP_TUNNEL
| NETIF_F_GSO_GRE
|
6582 NETIF_F_GSO_IPXIP4
|
6583 NETIF_F_GSO_UDP_TUNNEL_CSUM
| NETIF_F_GSO_GRE_CSUM
|
6584 NETIF_F_GSO_PARTIAL
| NETIF_F_RXHASH
|
6585 NETIF_F_RXCSUM
| NETIF_F_LRO
| NETIF_F_GRO
;
6587 dev
->hw_enc_features
=
6588 NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
| NETIF_F_SG
|
6589 NETIF_F_TSO
| NETIF_F_TSO6
|
6590 NETIF_F_GSO_UDP_TUNNEL
| NETIF_F_GSO_GRE
|
6591 NETIF_F_GSO_UDP_TUNNEL_CSUM
| NETIF_F_GSO_GRE_CSUM
|
6592 NETIF_F_GSO_IPXIP4
| NETIF_F_GSO_PARTIAL
;
6593 dev
->gso_partial_features
= NETIF_F_GSO_UDP_TUNNEL_CSUM
|
6594 NETIF_F_GSO_GRE_CSUM
;
6595 dev
->vlan_features
= dev
->hw_features
| NETIF_F_HIGHDMA
;
6596 dev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_RX
| NETIF_F_HW_VLAN_CTAG_TX
|
6597 NETIF_F_HW_VLAN_STAG_RX
| NETIF_F_HW_VLAN_STAG_TX
;
6598 dev
->features
|= dev
->hw_features
| NETIF_F_HIGHDMA
;
6599 dev
->priv_flags
|= IFF_UNICAST_FLT
;
6601 #ifdef CONFIG_BNXT_SRIOV
6602 init_waitqueue_head(&bp
->sriov_cfg_wait
);
6604 rc
= bnxt_alloc_hwrm_resources(bp
);
6608 mutex_init(&bp
->hwrm_cmd_lock
);
6609 rc
= bnxt_hwrm_ver_get(bp
);
6613 bp
->gro_func
= bnxt_gro_func_5730x
;
6614 if (BNXT_CHIP_NUM_57X1X(bp
->chip_num
))
6615 bp
->gro_func
= bnxt_gro_func_5731x
;
6617 rc
= bnxt_hwrm_func_drv_rgtr(bp
);
6621 /* Get the MAX capabilities for this function */
6622 rc
= bnxt_hwrm_func_qcaps(bp
);
6624 netdev_err(bp
->dev
, "hwrm query capability failure rc: %x\n",
6630 rc
= bnxt_hwrm_queue_qportcfg(bp
);
6632 netdev_err(bp
->dev
, "hwrm query qportcfg failure rc: %x\n",
6638 bnxt_hwrm_func_qcfg(bp
);
6640 bnxt_set_tpa_flags(bp
);
6641 bnxt_set_ring_params(bp
);
6643 bp
->pf
.max_irqs
= max_irqs
;
6644 #if defined(CONFIG_BNXT_SRIOV)
6646 bp
->vf
.max_irqs
= max_irqs
;
6648 bnxt_set_dflt_rings(bp
);
6651 dev
->hw_features
|= NETIF_F_NTUPLE
;
6652 if (bnxt_rfs_capable(bp
)) {
6653 bp
->flags
|= BNXT_FLAG_RFS
;
6654 dev
->features
|= NETIF_F_NTUPLE
;
6658 if (dev
->hw_features
& NETIF_F_HW_VLAN_CTAG_RX
)
6659 bp
->flags
|= BNXT_FLAG_STRIP_VLAN
;
6661 rc
= bnxt_probe_phy(bp
);
6665 rc
= register_netdev(dev
);
6669 netdev_info(dev
, "%s found at mem %lx, node addr %pM\n",
6670 board_info
[ent
->driver_data
].name
,
6671 (long)pci_resource_start(pdev
, 0), dev
->dev_addr
);
6673 bnxt_parse_log_pcie_link(bp
);
6678 pci_iounmap(pdev
, bp
->bar0
);
6679 pci_release_regions(pdev
);
6680 pci_disable_device(pdev
);
6688 * bnxt_io_error_detected - called when PCI error is detected
6689 * @pdev: Pointer to PCI device
6690 * @state: The current pci connection state
6692 * This function is called after a PCI bus error affecting
6693 * this device has been detected.
6695 static pci_ers_result_t
bnxt_io_error_detected(struct pci_dev
*pdev
,
6696 pci_channel_state_t state
)
6698 struct net_device
*netdev
= pci_get_drvdata(pdev
);
6699 struct bnxt
*bp
= netdev_priv(netdev
);
6701 netdev_info(netdev
, "PCI I/O error detected\n");
6704 netif_device_detach(netdev
);
6706 if (state
== pci_channel_io_perm_failure
) {
6708 return PCI_ERS_RESULT_DISCONNECT
;
6711 if (netif_running(netdev
))
6714 /* So that func_reset will be done during slot_reset */
6715 clear_bit(BNXT_STATE_FN_RST_DONE
, &bp
->state
);
6716 pci_disable_device(pdev
);
6719 /* Request a slot slot reset. */
6720 return PCI_ERS_RESULT_NEED_RESET
;
6724 * bnxt_io_slot_reset - called after the pci bus has been reset.
6725 * @pdev: Pointer to PCI device
6727 * Restart the card from scratch, as if from a cold-boot.
6728 * At this point, the card has exprienced a hard reset,
6729 * followed by fixups by BIOS, and has its config space
6730 * set up identically to what it was at cold boot.
6732 static pci_ers_result_t
bnxt_io_slot_reset(struct pci_dev
*pdev
)
6734 struct net_device
*netdev
= pci_get_drvdata(pdev
);
6735 struct bnxt
*bp
= netdev_priv(netdev
);
6737 pci_ers_result_t result
= PCI_ERS_RESULT_DISCONNECT
;
6739 netdev_info(bp
->dev
, "PCI Slot Reset\n");
6743 if (pci_enable_device(pdev
)) {
6745 "Cannot re-enable PCI device after reset.\n");
6747 pci_set_master(pdev
);
6749 if (netif_running(netdev
))
6750 err
= bnxt_open(netdev
);
6753 result
= PCI_ERS_RESULT_RECOVERED
;
6756 if (result
!= PCI_ERS_RESULT_RECOVERED
&& netif_running(netdev
))
6761 err
= pci_cleanup_aer_uncorrect_error_status(pdev
);
6764 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
6765 err
); /* non-fatal, continue */
6768 return PCI_ERS_RESULT_RECOVERED
;
6772 * bnxt_io_resume - called when traffic can start flowing again.
6773 * @pdev: Pointer to PCI device
6775 * This callback is called when the error recovery driver tells
6776 * us that its OK to resume normal operation.
6778 static void bnxt_io_resume(struct pci_dev
*pdev
)
6780 struct net_device
*netdev
= pci_get_drvdata(pdev
);
6784 netif_device_attach(netdev
);
6789 static const struct pci_error_handlers bnxt_err_handler
= {
6790 .error_detected
= bnxt_io_error_detected
,
6791 .slot_reset
= bnxt_io_slot_reset
,
6792 .resume
= bnxt_io_resume
6795 static struct pci_driver bnxt_pci_driver
= {
6796 .name
= DRV_MODULE_NAME
,
6797 .id_table
= bnxt_pci_tbl
,
6798 .probe
= bnxt_init_one
,
6799 .remove
= bnxt_remove_one
,
6800 .err_handler
= &bnxt_err_handler
,
6801 #if defined(CONFIG_BNXT_SRIOV)
6802 .sriov_configure
= bnxt_sriov_configure
,
6806 module_pci_driver(bnxt_pci_driver
);