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[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / broadcom / bnxt / bnxt.c
1 /* Broadcom NetXtreme-C/E network driver.
2 *
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 */
9
10 #include <linux/module.h>
11
12 #include <linux/stringify.h>
13 #include <linux/kernel.h>
14 #include <linux/timer.h>
15 #include <linux/errno.h>
16 #include <linux/ioport.h>
17 #include <linux/slab.h>
18 #include <linux/vmalloc.h>
19 #include <linux/interrupt.h>
20 #include <linux/pci.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23 #include <linux/skbuff.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/bitops.h>
26 #include <linux/io.h>
27 #include <linux/irq.h>
28 #include <linux/delay.h>
29 #include <asm/byteorder.h>
30 #include <asm/page.h>
31 #include <linux/time.h>
32 #include <linux/mii.h>
33 #include <linux/if.h>
34 #include <linux/if_vlan.h>
35 #include <net/ip.h>
36 #include <net/tcp.h>
37 #include <net/udp.h>
38 #include <net/checksum.h>
39 #include <net/ip6_checksum.h>
40 #if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE)
41 #include <net/vxlan.h>
42 #endif
43 #ifdef CONFIG_NET_RX_BUSY_POLL
44 #include <net/busy_poll.h>
45 #endif
46 #include <linux/workqueue.h>
47 #include <linux/prefetch.h>
48 #include <linux/cache.h>
49 #include <linux/log2.h>
50 #include <linux/aer.h>
51 #include <linux/bitmap.h>
52 #include <linux/cpu_rmap.h>
53
54 #include "bnxt_hsi.h"
55 #include "bnxt.h"
56 #include "bnxt_sriov.h"
57 #include "bnxt_ethtool.h"
58
59 #define BNXT_TX_TIMEOUT (5 * HZ)
60
61 static const char version[] =
62 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
63
64 MODULE_LICENSE("GPL");
65 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
66 MODULE_VERSION(DRV_MODULE_VERSION);
67
68 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
69 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
70 #define BNXT_RX_COPY_THRESH 256
71
72 #define BNXT_TX_PUSH_THRESH 164
73
74 enum board_idx {
75 BCM57301,
76 BCM57302,
77 BCM57304,
78 BCM57402,
79 BCM57404,
80 BCM57406,
81 BCM57304_VF,
82 BCM57404_VF,
83 };
84
85 /* indexed by enum above */
86 static const struct {
87 char *name;
88 } board_info[] = {
89 { "Broadcom BCM57301 NetXtreme-C Single-port 10Gb Ethernet" },
90 { "Broadcom BCM57302 NetXtreme-C Dual-port 10Gb/25Gb Ethernet" },
91 { "Broadcom BCM57304 NetXtreme-C Dual-port 10Gb/25Gb/40Gb/50Gb Ethernet" },
92 { "Broadcom BCM57402 NetXtreme-E Dual-port 10Gb Ethernet" },
93 { "Broadcom BCM57404 NetXtreme-E Dual-port 10Gb/25Gb Ethernet" },
94 { "Broadcom BCM57406 NetXtreme-E Dual-port 10GBase-T Ethernet" },
95 { "Broadcom BCM57304 NetXtreme-C Ethernet Virtual Function" },
96 { "Broadcom BCM57404 NetXtreme-E Ethernet Virtual Function" },
97 };
98
99 static const struct pci_device_id bnxt_pci_tbl[] = {
100 { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
101 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
102 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
103 { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
104 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
105 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
106 #ifdef CONFIG_BNXT_SRIOV
107 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = BCM57304_VF },
108 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = BCM57404_VF },
109 #endif
110 { 0 }
111 };
112
113 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
114
115 static const u16 bnxt_vf_req_snif[] = {
116 HWRM_FUNC_CFG,
117 HWRM_PORT_PHY_QCFG,
118 HWRM_CFA_L2_FILTER_ALLOC,
119 };
120
121 static const u16 bnxt_async_events_arr[] = {
122 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
123 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
124 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
125 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
126 };
127
128 static bool bnxt_vf_pciid(enum board_idx idx)
129 {
130 return (idx == BCM57304_VF || idx == BCM57404_VF);
131 }
132
133 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
134 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
135 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
136
137 #define BNXT_CP_DB_REARM(db, raw_cons) \
138 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
139
140 #define BNXT_CP_DB(db, raw_cons) \
141 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
142
143 #define BNXT_CP_DB_IRQ_DIS(db) \
144 writel(DB_CP_IRQ_DIS_FLAGS, db)
145
146 static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
147 {
148 /* Tell compiler to fetch tx indices from memory. */
149 barrier();
150
151 return bp->tx_ring_size -
152 ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask);
153 }
154
155 static const u16 bnxt_lhint_arr[] = {
156 TX_BD_FLAGS_LHINT_512_AND_SMALLER,
157 TX_BD_FLAGS_LHINT_512_TO_1023,
158 TX_BD_FLAGS_LHINT_1024_TO_2047,
159 TX_BD_FLAGS_LHINT_1024_TO_2047,
160 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
161 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
162 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
163 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
164 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
165 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
166 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
167 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
168 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
169 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
170 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
171 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
172 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
173 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
174 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
175 };
176
177 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
178 {
179 struct bnxt *bp = netdev_priv(dev);
180 struct tx_bd *txbd;
181 struct tx_bd_ext *txbd1;
182 struct netdev_queue *txq;
183 int i;
184 dma_addr_t mapping;
185 unsigned int length, pad = 0;
186 u32 len, free_size, vlan_tag_flags, cfa_action, flags;
187 u16 prod, last_frag;
188 struct pci_dev *pdev = bp->pdev;
189 struct bnxt_tx_ring_info *txr;
190 struct bnxt_sw_tx_bd *tx_buf;
191
192 i = skb_get_queue_mapping(skb);
193 if (unlikely(i >= bp->tx_nr_rings)) {
194 dev_kfree_skb_any(skb);
195 return NETDEV_TX_OK;
196 }
197
198 txr = &bp->tx_ring[i];
199 txq = netdev_get_tx_queue(dev, i);
200 prod = txr->tx_prod;
201
202 free_size = bnxt_tx_avail(bp, txr);
203 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
204 netif_tx_stop_queue(txq);
205 return NETDEV_TX_BUSY;
206 }
207
208 length = skb->len;
209 len = skb_headlen(skb);
210 last_frag = skb_shinfo(skb)->nr_frags;
211
212 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
213
214 txbd->tx_bd_opaque = prod;
215
216 tx_buf = &txr->tx_buf_ring[prod];
217 tx_buf->skb = skb;
218 tx_buf->nr_frags = last_frag;
219
220 vlan_tag_flags = 0;
221 cfa_action = 0;
222 if (skb_vlan_tag_present(skb)) {
223 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
224 skb_vlan_tag_get(skb);
225 /* Currently supports 8021Q, 8021AD vlan offloads
226 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
227 */
228 if (skb->vlan_proto == htons(ETH_P_8021Q))
229 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
230 }
231
232 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
233 struct tx_push_buffer *tx_push_buf = txr->tx_push;
234 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
235 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
236 void *pdata = tx_push_buf->data;
237 u64 *end;
238 int j, push_len;
239
240 /* Set COAL_NOW to be ready quickly for the next push */
241 tx_push->tx_bd_len_flags_type =
242 cpu_to_le32((length << TX_BD_LEN_SHIFT) |
243 TX_BD_TYPE_LONG_TX_BD |
244 TX_BD_FLAGS_LHINT_512_AND_SMALLER |
245 TX_BD_FLAGS_COAL_NOW |
246 TX_BD_FLAGS_PACKET_END |
247 (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
248
249 if (skb->ip_summed == CHECKSUM_PARTIAL)
250 tx_push1->tx_bd_hsize_lflags =
251 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
252 else
253 tx_push1->tx_bd_hsize_lflags = 0;
254
255 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
256 tx_push1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
257
258 end = pdata + length;
259 end = PTR_ALIGN(end, 8) - 1;
260 *end = 0;
261
262 skb_copy_from_linear_data(skb, pdata, len);
263 pdata += len;
264 for (j = 0; j < last_frag; j++) {
265 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
266 void *fptr;
267
268 fptr = skb_frag_address_safe(frag);
269 if (!fptr)
270 goto normal_tx;
271
272 memcpy(pdata, fptr, skb_frag_size(frag));
273 pdata += skb_frag_size(frag);
274 }
275
276 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
277 txbd->tx_bd_haddr = txr->data_mapping;
278 prod = NEXT_TX(prod);
279 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
280 memcpy(txbd, tx_push1, sizeof(*txbd));
281 prod = NEXT_TX(prod);
282 tx_push->doorbell =
283 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
284 txr->tx_prod = prod;
285
286 netdev_tx_sent_queue(txq, skb->len);
287
288 push_len = (length + sizeof(*tx_push) + 7) / 8;
289 if (push_len > 16) {
290 __iowrite64_copy(txr->tx_doorbell, tx_push_buf, 16);
291 __iowrite64_copy(txr->tx_doorbell + 4, tx_push_buf + 1,
292 push_len - 16);
293 } else {
294 __iowrite64_copy(txr->tx_doorbell, tx_push_buf,
295 push_len);
296 }
297
298 tx_buf->is_push = 1;
299 goto tx_done;
300 }
301
302 normal_tx:
303 if (length < BNXT_MIN_PKT_SIZE) {
304 pad = BNXT_MIN_PKT_SIZE - length;
305 if (skb_pad(skb, pad)) {
306 /* SKB already freed. */
307 tx_buf->skb = NULL;
308 return NETDEV_TX_OK;
309 }
310 length = BNXT_MIN_PKT_SIZE;
311 }
312
313 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
314
315 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
316 dev_kfree_skb_any(skb);
317 tx_buf->skb = NULL;
318 return NETDEV_TX_OK;
319 }
320
321 dma_unmap_addr_set(tx_buf, mapping, mapping);
322 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
323 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
324
325 txbd->tx_bd_haddr = cpu_to_le64(mapping);
326
327 prod = NEXT_TX(prod);
328 txbd1 = (struct tx_bd_ext *)
329 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
330
331 txbd1->tx_bd_hsize_lflags = 0;
332 if (skb_is_gso(skb)) {
333 u32 hdr_len;
334
335 if (skb->encapsulation)
336 hdr_len = skb_inner_network_offset(skb) +
337 skb_inner_network_header_len(skb) +
338 inner_tcp_hdrlen(skb);
339 else
340 hdr_len = skb_transport_offset(skb) +
341 tcp_hdrlen(skb);
342
343 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
344 TX_BD_FLAGS_T_IPID |
345 (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
346 length = skb_shinfo(skb)->gso_size;
347 txbd1->tx_bd_mss = cpu_to_le32(length);
348 length += hdr_len;
349 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
350 txbd1->tx_bd_hsize_lflags =
351 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
352 txbd1->tx_bd_mss = 0;
353 }
354
355 length >>= 9;
356 flags |= bnxt_lhint_arr[length];
357 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
358
359 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
360 txbd1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
361 for (i = 0; i < last_frag; i++) {
362 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
363
364 prod = NEXT_TX(prod);
365 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
366
367 len = skb_frag_size(frag);
368 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
369 DMA_TO_DEVICE);
370
371 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
372 goto tx_dma_error;
373
374 tx_buf = &txr->tx_buf_ring[prod];
375 dma_unmap_addr_set(tx_buf, mapping, mapping);
376
377 txbd->tx_bd_haddr = cpu_to_le64(mapping);
378
379 flags = len << TX_BD_LEN_SHIFT;
380 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
381 }
382
383 flags &= ~TX_BD_LEN;
384 txbd->tx_bd_len_flags_type =
385 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
386 TX_BD_FLAGS_PACKET_END);
387
388 netdev_tx_sent_queue(txq, skb->len);
389
390 /* Sync BD data before updating doorbell */
391 wmb();
392
393 prod = NEXT_TX(prod);
394 txr->tx_prod = prod;
395
396 writel(DB_KEY_TX | prod, txr->tx_doorbell);
397 writel(DB_KEY_TX | prod, txr->tx_doorbell);
398
399 tx_done:
400
401 mmiowb();
402
403 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
404 netif_tx_stop_queue(txq);
405
406 /* netif_tx_stop_queue() must be done before checking
407 * tx index in bnxt_tx_avail() below, because in
408 * bnxt_tx_int(), we update tx index before checking for
409 * netif_tx_queue_stopped().
410 */
411 smp_mb();
412 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
413 netif_tx_wake_queue(txq);
414 }
415 return NETDEV_TX_OK;
416
417 tx_dma_error:
418 last_frag = i;
419
420 /* start back at beginning and unmap skb */
421 prod = txr->tx_prod;
422 tx_buf = &txr->tx_buf_ring[prod];
423 tx_buf->skb = NULL;
424 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
425 skb_headlen(skb), PCI_DMA_TODEVICE);
426 prod = NEXT_TX(prod);
427
428 /* unmap remaining mapped pages */
429 for (i = 0; i < last_frag; i++) {
430 prod = NEXT_TX(prod);
431 tx_buf = &txr->tx_buf_ring[prod];
432 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
433 skb_frag_size(&skb_shinfo(skb)->frags[i]),
434 PCI_DMA_TODEVICE);
435 }
436
437 dev_kfree_skb_any(skb);
438 return NETDEV_TX_OK;
439 }
440
441 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
442 {
443 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
444 int index = txr - &bp->tx_ring[0];
445 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, index);
446 u16 cons = txr->tx_cons;
447 struct pci_dev *pdev = bp->pdev;
448 int i;
449 unsigned int tx_bytes = 0;
450
451 for (i = 0; i < nr_pkts; i++) {
452 struct bnxt_sw_tx_bd *tx_buf;
453 struct sk_buff *skb;
454 int j, last;
455
456 tx_buf = &txr->tx_buf_ring[cons];
457 cons = NEXT_TX(cons);
458 skb = tx_buf->skb;
459 tx_buf->skb = NULL;
460
461 if (tx_buf->is_push) {
462 tx_buf->is_push = 0;
463 goto next_tx_int;
464 }
465
466 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
467 skb_headlen(skb), PCI_DMA_TODEVICE);
468 last = tx_buf->nr_frags;
469
470 for (j = 0; j < last; j++) {
471 cons = NEXT_TX(cons);
472 tx_buf = &txr->tx_buf_ring[cons];
473 dma_unmap_page(
474 &pdev->dev,
475 dma_unmap_addr(tx_buf, mapping),
476 skb_frag_size(&skb_shinfo(skb)->frags[j]),
477 PCI_DMA_TODEVICE);
478 }
479
480 next_tx_int:
481 cons = NEXT_TX(cons);
482
483 tx_bytes += skb->len;
484 dev_kfree_skb_any(skb);
485 }
486
487 netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
488 txr->tx_cons = cons;
489
490 /* Need to make the tx_cons update visible to bnxt_start_xmit()
491 * before checking for netif_tx_queue_stopped(). Without the
492 * memory barrier, there is a small possibility that bnxt_start_xmit()
493 * will miss it and cause the queue to be stopped forever.
494 */
495 smp_mb();
496
497 if (unlikely(netif_tx_queue_stopped(txq)) &&
498 (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
499 __netif_tx_lock(txq, smp_processor_id());
500 if (netif_tx_queue_stopped(txq) &&
501 bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
502 txr->dev_state != BNXT_DEV_STATE_CLOSING)
503 netif_tx_wake_queue(txq);
504 __netif_tx_unlock(txq);
505 }
506 }
507
508 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
509 gfp_t gfp)
510 {
511 u8 *data;
512 struct pci_dev *pdev = bp->pdev;
513
514 data = kmalloc(bp->rx_buf_size, gfp);
515 if (!data)
516 return NULL;
517
518 *mapping = dma_map_single(&pdev->dev, data + BNXT_RX_DMA_OFFSET,
519 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
520
521 if (dma_mapping_error(&pdev->dev, *mapping)) {
522 kfree(data);
523 data = NULL;
524 }
525 return data;
526 }
527
528 static inline int bnxt_alloc_rx_data(struct bnxt *bp,
529 struct bnxt_rx_ring_info *rxr,
530 u16 prod, gfp_t gfp)
531 {
532 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
533 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
534 u8 *data;
535 dma_addr_t mapping;
536
537 data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
538 if (!data)
539 return -ENOMEM;
540
541 rx_buf->data = data;
542 dma_unmap_addr_set(rx_buf, mapping, mapping);
543
544 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
545
546 return 0;
547 }
548
549 static void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons,
550 u8 *data)
551 {
552 u16 prod = rxr->rx_prod;
553 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
554 struct rx_bd *cons_bd, *prod_bd;
555
556 prod_rx_buf = &rxr->rx_buf_ring[prod];
557 cons_rx_buf = &rxr->rx_buf_ring[cons];
558
559 prod_rx_buf->data = data;
560
561 dma_unmap_addr_set(prod_rx_buf, mapping,
562 dma_unmap_addr(cons_rx_buf, mapping));
563
564 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
565 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
566
567 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
568 }
569
570 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
571 {
572 u16 next, max = rxr->rx_agg_bmap_size;
573
574 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
575 if (next >= max)
576 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
577 return next;
578 }
579
580 static inline int bnxt_alloc_rx_page(struct bnxt *bp,
581 struct bnxt_rx_ring_info *rxr,
582 u16 prod, gfp_t gfp)
583 {
584 struct rx_bd *rxbd =
585 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
586 struct bnxt_sw_rx_agg_bd *rx_agg_buf;
587 struct pci_dev *pdev = bp->pdev;
588 struct page *page;
589 dma_addr_t mapping;
590 u16 sw_prod = rxr->rx_sw_agg_prod;
591
592 page = alloc_page(gfp);
593 if (!page)
594 return -ENOMEM;
595
596 mapping = dma_map_page(&pdev->dev, page, 0, PAGE_SIZE,
597 PCI_DMA_FROMDEVICE);
598 if (dma_mapping_error(&pdev->dev, mapping)) {
599 __free_page(page);
600 return -EIO;
601 }
602
603 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
604 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
605
606 __set_bit(sw_prod, rxr->rx_agg_bmap);
607 rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
608 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
609
610 rx_agg_buf->page = page;
611 rx_agg_buf->mapping = mapping;
612 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
613 rxbd->rx_bd_opaque = sw_prod;
614 return 0;
615 }
616
617 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons,
618 u32 agg_bufs)
619 {
620 struct bnxt *bp = bnapi->bp;
621 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
622 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
623 u16 prod = rxr->rx_agg_prod;
624 u16 sw_prod = rxr->rx_sw_agg_prod;
625 u32 i;
626
627 for (i = 0; i < agg_bufs; i++) {
628 u16 cons;
629 struct rx_agg_cmp *agg;
630 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
631 struct rx_bd *prod_bd;
632 struct page *page;
633
634 agg = (struct rx_agg_cmp *)
635 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
636 cons = agg->rx_agg_cmp_opaque;
637 __clear_bit(cons, rxr->rx_agg_bmap);
638
639 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
640 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
641
642 __set_bit(sw_prod, rxr->rx_agg_bmap);
643 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
644 cons_rx_buf = &rxr->rx_agg_ring[cons];
645
646 /* It is possible for sw_prod to be equal to cons, so
647 * set cons_rx_buf->page to NULL first.
648 */
649 page = cons_rx_buf->page;
650 cons_rx_buf->page = NULL;
651 prod_rx_buf->page = page;
652
653 prod_rx_buf->mapping = cons_rx_buf->mapping;
654
655 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
656
657 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
658 prod_bd->rx_bd_opaque = sw_prod;
659
660 prod = NEXT_RX_AGG(prod);
661 sw_prod = NEXT_RX_AGG(sw_prod);
662 cp_cons = NEXT_CMP(cp_cons);
663 }
664 rxr->rx_agg_prod = prod;
665 rxr->rx_sw_agg_prod = sw_prod;
666 }
667
668 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
669 struct bnxt_rx_ring_info *rxr, u16 cons,
670 u16 prod, u8 *data, dma_addr_t dma_addr,
671 unsigned int len)
672 {
673 int err;
674 struct sk_buff *skb;
675
676 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
677 if (unlikely(err)) {
678 bnxt_reuse_rx_data(rxr, cons, data);
679 return NULL;
680 }
681
682 skb = build_skb(data, 0);
683 dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
684 PCI_DMA_FROMDEVICE);
685 if (!skb) {
686 kfree(data);
687 return NULL;
688 }
689
690 skb_reserve(skb, BNXT_RX_OFFSET);
691 skb_put(skb, len);
692 return skb;
693 }
694
695 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi,
696 struct sk_buff *skb, u16 cp_cons,
697 u32 agg_bufs)
698 {
699 struct pci_dev *pdev = bp->pdev;
700 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
701 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
702 u16 prod = rxr->rx_agg_prod;
703 u32 i;
704
705 for (i = 0; i < agg_bufs; i++) {
706 u16 cons, frag_len;
707 struct rx_agg_cmp *agg;
708 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
709 struct page *page;
710 dma_addr_t mapping;
711
712 agg = (struct rx_agg_cmp *)
713 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
714 cons = agg->rx_agg_cmp_opaque;
715 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
716 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
717
718 cons_rx_buf = &rxr->rx_agg_ring[cons];
719 skb_fill_page_desc(skb, i, cons_rx_buf->page, 0, frag_len);
720 __clear_bit(cons, rxr->rx_agg_bmap);
721
722 /* It is possible for bnxt_alloc_rx_page() to allocate
723 * a sw_prod index that equals the cons index, so we
724 * need to clear the cons entry now.
725 */
726 mapping = dma_unmap_addr(cons_rx_buf, mapping);
727 page = cons_rx_buf->page;
728 cons_rx_buf->page = NULL;
729
730 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
731 struct skb_shared_info *shinfo;
732 unsigned int nr_frags;
733
734 shinfo = skb_shinfo(skb);
735 nr_frags = --shinfo->nr_frags;
736 __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
737
738 dev_kfree_skb(skb);
739
740 cons_rx_buf->page = page;
741
742 /* Update prod since possibly some pages have been
743 * allocated already.
744 */
745 rxr->rx_agg_prod = prod;
746 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i);
747 return NULL;
748 }
749
750 dma_unmap_page(&pdev->dev, mapping, PAGE_SIZE,
751 PCI_DMA_FROMDEVICE);
752
753 skb->data_len += frag_len;
754 skb->len += frag_len;
755 skb->truesize += PAGE_SIZE;
756
757 prod = NEXT_RX_AGG(prod);
758 cp_cons = NEXT_CMP(cp_cons);
759 }
760 rxr->rx_agg_prod = prod;
761 return skb;
762 }
763
764 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
765 u8 agg_bufs, u32 *raw_cons)
766 {
767 u16 last;
768 struct rx_agg_cmp *agg;
769
770 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
771 last = RING_CMP(*raw_cons);
772 agg = (struct rx_agg_cmp *)
773 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
774 return RX_AGG_CMP_VALID(agg, *raw_cons);
775 }
776
777 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
778 unsigned int len,
779 dma_addr_t mapping)
780 {
781 struct bnxt *bp = bnapi->bp;
782 struct pci_dev *pdev = bp->pdev;
783 struct sk_buff *skb;
784
785 skb = napi_alloc_skb(&bnapi->napi, len);
786 if (!skb)
787 return NULL;
788
789 dma_sync_single_for_cpu(&pdev->dev, mapping,
790 bp->rx_copy_thresh, PCI_DMA_FROMDEVICE);
791
792 memcpy(skb->data - BNXT_RX_OFFSET, data, len + BNXT_RX_OFFSET);
793
794 dma_sync_single_for_device(&pdev->dev, mapping,
795 bp->rx_copy_thresh,
796 PCI_DMA_FROMDEVICE);
797
798 skb_put(skb, len);
799 return skb;
800 }
801
802 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
803 struct rx_tpa_start_cmp *tpa_start,
804 struct rx_tpa_start_cmp_ext *tpa_start1)
805 {
806 u8 agg_id = TPA_START_AGG_ID(tpa_start);
807 u16 cons, prod;
808 struct bnxt_tpa_info *tpa_info;
809 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
810 struct rx_bd *prod_bd;
811 dma_addr_t mapping;
812
813 cons = tpa_start->rx_tpa_start_cmp_opaque;
814 prod = rxr->rx_prod;
815 cons_rx_buf = &rxr->rx_buf_ring[cons];
816 prod_rx_buf = &rxr->rx_buf_ring[prod];
817 tpa_info = &rxr->rx_tpa[agg_id];
818
819 prod_rx_buf->data = tpa_info->data;
820
821 mapping = tpa_info->mapping;
822 dma_unmap_addr_set(prod_rx_buf, mapping, mapping);
823
824 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
825
826 prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
827
828 tpa_info->data = cons_rx_buf->data;
829 cons_rx_buf->data = NULL;
830 tpa_info->mapping = dma_unmap_addr(cons_rx_buf, mapping);
831
832 tpa_info->len =
833 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
834 RX_TPA_START_CMP_LEN_SHIFT;
835 if (likely(TPA_START_HASH_VALID(tpa_start))) {
836 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
837
838 tpa_info->hash_type = PKT_HASH_TYPE_L4;
839 tpa_info->gso_type = SKB_GSO_TCPV4;
840 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
841 if (hash_type == 3)
842 tpa_info->gso_type = SKB_GSO_TCPV6;
843 tpa_info->rss_hash =
844 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
845 } else {
846 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
847 tpa_info->gso_type = 0;
848 if (netif_msg_rx_err(bp))
849 netdev_warn(bp->dev, "TPA packet without valid hash\n");
850 }
851 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
852 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
853
854 rxr->rx_prod = NEXT_RX(prod);
855 cons = NEXT_RX(cons);
856 cons_rx_buf = &rxr->rx_buf_ring[cons];
857
858 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
859 rxr->rx_prod = NEXT_RX(rxr->rx_prod);
860 cons_rx_buf->data = NULL;
861 }
862
863 static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi,
864 u16 cp_cons, u32 agg_bufs)
865 {
866 if (agg_bufs)
867 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
868 }
869
870 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
871 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
872
873 static inline struct sk_buff *bnxt_gro_skb(struct bnxt_tpa_info *tpa_info,
874 struct rx_tpa_end_cmp *tpa_end,
875 struct rx_tpa_end_cmp_ext *tpa_end1,
876 struct sk_buff *skb)
877 {
878 #ifdef CONFIG_INET
879 struct tcphdr *th;
880 int payload_off, tcp_opt_len = 0;
881 int len, nw_off;
882 u16 segs;
883
884 segs = TPA_END_TPA_SEGS(tpa_end);
885 if (segs == 1)
886 return skb;
887
888 NAPI_GRO_CB(skb)->count = segs;
889 skb_shinfo(skb)->gso_size =
890 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
891 skb_shinfo(skb)->gso_type = tpa_info->gso_type;
892 payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
893 RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
894 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
895 if (TPA_END_GRO_TS(tpa_end))
896 tcp_opt_len = 12;
897
898 if (tpa_info->gso_type == SKB_GSO_TCPV4) {
899 struct iphdr *iph;
900
901 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
902 ETH_HLEN;
903 skb_set_network_header(skb, nw_off);
904 iph = ip_hdr(skb);
905 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
906 len = skb->len - skb_transport_offset(skb);
907 th = tcp_hdr(skb);
908 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
909 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
910 struct ipv6hdr *iph;
911
912 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
913 ETH_HLEN;
914 skb_set_network_header(skb, nw_off);
915 iph = ipv6_hdr(skb);
916 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
917 len = skb->len - skb_transport_offset(skb);
918 th = tcp_hdr(skb);
919 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
920 } else {
921 dev_kfree_skb_any(skb);
922 return NULL;
923 }
924 tcp_gro_complete(skb);
925
926 if (nw_off) { /* tunnel */
927 struct udphdr *uh = NULL;
928
929 if (skb->protocol == htons(ETH_P_IP)) {
930 struct iphdr *iph = (struct iphdr *)skb->data;
931
932 if (iph->protocol == IPPROTO_UDP)
933 uh = (struct udphdr *)(iph + 1);
934 } else {
935 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
936
937 if (iph->nexthdr == IPPROTO_UDP)
938 uh = (struct udphdr *)(iph + 1);
939 }
940 if (uh) {
941 if (uh->check)
942 skb_shinfo(skb)->gso_type |=
943 SKB_GSO_UDP_TUNNEL_CSUM;
944 else
945 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
946 }
947 }
948 #endif
949 return skb;
950 }
951
952 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
953 struct bnxt_napi *bnapi,
954 u32 *raw_cons,
955 struct rx_tpa_end_cmp *tpa_end,
956 struct rx_tpa_end_cmp_ext *tpa_end1,
957 bool *agg_event)
958 {
959 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
960 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
961 u8 agg_id = TPA_END_AGG_ID(tpa_end);
962 u8 *data, agg_bufs;
963 u16 cp_cons = RING_CMP(*raw_cons);
964 unsigned int len;
965 struct bnxt_tpa_info *tpa_info;
966 dma_addr_t mapping;
967 struct sk_buff *skb;
968
969 tpa_info = &rxr->rx_tpa[agg_id];
970 data = tpa_info->data;
971 prefetch(data);
972 len = tpa_info->len;
973 mapping = tpa_info->mapping;
974
975 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
976 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
977
978 if (agg_bufs) {
979 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
980 return ERR_PTR(-EBUSY);
981
982 *agg_event = true;
983 cp_cons = NEXT_CMP(cp_cons);
984 }
985
986 if (unlikely(agg_bufs > MAX_SKB_FRAGS)) {
987 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
988 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
989 agg_bufs, (int)MAX_SKB_FRAGS);
990 return NULL;
991 }
992
993 if (len <= bp->rx_copy_thresh) {
994 skb = bnxt_copy_skb(bnapi, data, len, mapping);
995 if (!skb) {
996 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
997 return NULL;
998 }
999 } else {
1000 u8 *new_data;
1001 dma_addr_t new_mapping;
1002
1003 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1004 if (!new_data) {
1005 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1006 return NULL;
1007 }
1008
1009 tpa_info->data = new_data;
1010 tpa_info->mapping = new_mapping;
1011
1012 skb = build_skb(data, 0);
1013 dma_unmap_single(&bp->pdev->dev, mapping, bp->rx_buf_use_size,
1014 PCI_DMA_FROMDEVICE);
1015
1016 if (!skb) {
1017 kfree(data);
1018 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1019 return NULL;
1020 }
1021 skb_reserve(skb, BNXT_RX_OFFSET);
1022 skb_put(skb, len);
1023 }
1024
1025 if (agg_bufs) {
1026 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1027 if (!skb) {
1028 /* Page reuse already handled by bnxt_rx_pages(). */
1029 return NULL;
1030 }
1031 }
1032 skb->protocol = eth_type_trans(skb, bp->dev);
1033
1034 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1035 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1036
1037 if (tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) {
1038 netdev_features_t features = skb->dev->features;
1039 u16 vlan_proto = tpa_info->metadata >>
1040 RX_CMP_FLAGS2_METADATA_TPID_SFT;
1041
1042 if (((features & NETIF_F_HW_VLAN_CTAG_RX) &&
1043 vlan_proto == ETH_P_8021Q) ||
1044 ((features & NETIF_F_HW_VLAN_STAG_RX) &&
1045 vlan_proto == ETH_P_8021AD)) {
1046 __vlan_hwaccel_put_tag(skb, htons(vlan_proto),
1047 tpa_info->metadata &
1048 RX_CMP_FLAGS2_METADATA_VID_MASK);
1049 }
1050 }
1051
1052 skb_checksum_none_assert(skb);
1053 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1054 skb->ip_summed = CHECKSUM_UNNECESSARY;
1055 skb->csum_level =
1056 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1057 }
1058
1059 if (TPA_END_GRO(tpa_end))
1060 skb = bnxt_gro_skb(tpa_info, tpa_end, tpa_end1, skb);
1061
1062 return skb;
1063 }
1064
1065 /* returns the following:
1066 * 1 - 1 packet successfully received
1067 * 0 - successful TPA_START, packet not completed yet
1068 * -EBUSY - completion ring does not have all the agg buffers yet
1069 * -ENOMEM - packet aborted due to out of memory
1070 * -EIO - packet aborted due to hw error indicated in BD
1071 */
1072 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons,
1073 bool *agg_event)
1074 {
1075 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1076 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1077 struct net_device *dev = bp->dev;
1078 struct rx_cmp *rxcmp;
1079 struct rx_cmp_ext *rxcmp1;
1080 u32 tmp_raw_cons = *raw_cons;
1081 u16 cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1082 struct bnxt_sw_rx_bd *rx_buf;
1083 unsigned int len;
1084 u8 *data, agg_bufs, cmp_type;
1085 dma_addr_t dma_addr;
1086 struct sk_buff *skb;
1087 int rc = 0;
1088
1089 rxcmp = (struct rx_cmp *)
1090 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1091
1092 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1093 cp_cons = RING_CMP(tmp_raw_cons);
1094 rxcmp1 = (struct rx_cmp_ext *)
1095 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1096
1097 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1098 return -EBUSY;
1099
1100 cmp_type = RX_CMP_TYPE(rxcmp);
1101
1102 prod = rxr->rx_prod;
1103
1104 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1105 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1106 (struct rx_tpa_start_cmp_ext *)rxcmp1);
1107
1108 goto next_rx_no_prod;
1109
1110 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1111 skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons,
1112 (struct rx_tpa_end_cmp *)rxcmp,
1113 (struct rx_tpa_end_cmp_ext *)rxcmp1,
1114 agg_event);
1115
1116 if (unlikely(IS_ERR(skb)))
1117 return -EBUSY;
1118
1119 rc = -ENOMEM;
1120 if (likely(skb)) {
1121 skb_record_rx_queue(skb, bnapi->index);
1122 skb_mark_napi_id(skb, &bnapi->napi);
1123 if (bnxt_busy_polling(bnapi))
1124 netif_receive_skb(skb);
1125 else
1126 napi_gro_receive(&bnapi->napi, skb);
1127 rc = 1;
1128 }
1129 goto next_rx_no_prod;
1130 }
1131
1132 cons = rxcmp->rx_cmp_opaque;
1133 rx_buf = &rxr->rx_buf_ring[cons];
1134 data = rx_buf->data;
1135 prefetch(data);
1136
1137 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) & RX_CMP_AGG_BUFS) >>
1138 RX_CMP_AGG_BUFS_SHIFT;
1139
1140 if (agg_bufs) {
1141 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1142 return -EBUSY;
1143
1144 cp_cons = NEXT_CMP(cp_cons);
1145 *agg_event = true;
1146 }
1147
1148 rx_buf->data = NULL;
1149 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1150 bnxt_reuse_rx_data(rxr, cons, data);
1151 if (agg_bufs)
1152 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1153
1154 rc = -EIO;
1155 goto next_rx;
1156 }
1157
1158 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1159 dma_addr = dma_unmap_addr(rx_buf, mapping);
1160
1161 if (len <= bp->rx_copy_thresh) {
1162 skb = bnxt_copy_skb(bnapi, data, len, dma_addr);
1163 bnxt_reuse_rx_data(rxr, cons, data);
1164 if (!skb) {
1165 rc = -ENOMEM;
1166 goto next_rx;
1167 }
1168 } else {
1169 skb = bnxt_rx_skb(bp, rxr, cons, prod, data, dma_addr, len);
1170 if (!skb) {
1171 rc = -ENOMEM;
1172 goto next_rx;
1173 }
1174 }
1175
1176 if (agg_bufs) {
1177 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1178 if (!skb) {
1179 rc = -ENOMEM;
1180 goto next_rx;
1181 }
1182 }
1183
1184 if (RX_CMP_HASH_VALID(rxcmp)) {
1185 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1186 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1187
1188 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1189 if (hash_type != 1 && hash_type != 3)
1190 type = PKT_HASH_TYPE_L3;
1191 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1192 }
1193
1194 skb->protocol = eth_type_trans(skb, dev);
1195
1196 if (rxcmp1->rx_cmp_flags2 &
1197 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) {
1198 netdev_features_t features = skb->dev->features;
1199 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1200 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1201
1202 if (((features & NETIF_F_HW_VLAN_CTAG_RX) &&
1203 vlan_proto == ETH_P_8021Q) ||
1204 ((features & NETIF_F_HW_VLAN_STAG_RX) &&
1205 vlan_proto == ETH_P_8021AD))
1206 __vlan_hwaccel_put_tag(skb, htons(vlan_proto),
1207 meta_data &
1208 RX_CMP_FLAGS2_METADATA_VID_MASK);
1209 }
1210
1211 skb_checksum_none_assert(skb);
1212 if (RX_CMP_L4_CS_OK(rxcmp1)) {
1213 if (dev->features & NETIF_F_RXCSUM) {
1214 skb->ip_summed = CHECKSUM_UNNECESSARY;
1215 skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1216 }
1217 } else {
1218 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1219 if (dev->features & NETIF_F_RXCSUM)
1220 cpr->rx_l4_csum_errors++;
1221 }
1222 }
1223
1224 skb_record_rx_queue(skb, bnapi->index);
1225 skb_mark_napi_id(skb, &bnapi->napi);
1226 if (bnxt_busy_polling(bnapi))
1227 netif_receive_skb(skb);
1228 else
1229 napi_gro_receive(&bnapi->napi, skb);
1230 rc = 1;
1231
1232 next_rx:
1233 rxr->rx_prod = NEXT_RX(prod);
1234
1235 next_rx_no_prod:
1236 *raw_cons = tmp_raw_cons;
1237
1238 return rc;
1239 }
1240
1241 #define BNXT_GET_EVENT_PORT(data) \
1242 ((data) & \
1243 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
1244
1245 #define BNXT_EVENT_POLICY_MASK \
1246 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK
1247
1248 #define BNXT_EVENT_POLICY_SFT \
1249 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT
1250
1251 #define BNXT_GET_EVENT_POLICY(data) \
1252 (((data) & BNXT_EVENT_POLICY_MASK) >> BNXT_EVENT_POLICY_SFT)
1253
1254 static int bnxt_async_event_process(struct bnxt *bp,
1255 struct hwrm_async_event_cmpl *cmpl)
1256 {
1257 u16 event_id = le16_to_cpu(cmpl->event_id);
1258
1259 /* TODO CHIMP_FW: Define event id's for link change, error etc */
1260 switch (event_id) {
1261 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
1262 u32 data1 = le32_to_cpu(cmpl->event_data1);
1263 struct bnxt_link_info *link_info = &bp->link_info;
1264
1265 if (BNXT_VF(bp))
1266 goto async_event_process_exit;
1267 if (data1 & 0x20000) {
1268 u16 fw_speed = link_info->force_link_speed;
1269 u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
1270
1271 netdev_warn(bp->dev, "Link speed %d no longer supported\n",
1272 speed);
1273 }
1274 /* fall thru */
1275 }
1276 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
1277 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
1278 break;
1279 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
1280 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
1281 break;
1282 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
1283 u32 data1 = le32_to_cpu(cmpl->event_data1);
1284 u16 port_id = BNXT_GET_EVENT_PORT(data1);
1285
1286 if (BNXT_VF(bp))
1287 break;
1288
1289 if (bp->pf.port_id != port_id)
1290 break;
1291
1292 bp->link_info.last_port_module_event =
1293 BNXT_GET_EVENT_POLICY(data1);
1294
1295 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
1296 break;
1297 }
1298 default:
1299 netdev_err(bp->dev, "unhandled ASYNC event (id 0x%x)\n",
1300 event_id);
1301 goto async_event_process_exit;
1302 }
1303 schedule_work(&bp->sp_task);
1304 async_event_process_exit:
1305 return 0;
1306 }
1307
1308 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1309 {
1310 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1311 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1312 struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1313 (struct hwrm_fwd_req_cmpl *)txcmp;
1314
1315 switch (cmpl_type) {
1316 case CMPL_BASE_TYPE_HWRM_DONE:
1317 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1318 if (seq_id == bp->hwrm_intr_seq_id)
1319 bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID;
1320 else
1321 netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1322 break;
1323
1324 case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1325 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1326
1327 if ((vf_id < bp->pf.first_vf_id) ||
1328 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1329 netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1330 vf_id);
1331 return -EINVAL;
1332 }
1333
1334 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1335 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1336 schedule_work(&bp->sp_task);
1337 break;
1338
1339 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1340 bnxt_async_event_process(bp,
1341 (struct hwrm_async_event_cmpl *)txcmp);
1342
1343 default:
1344 break;
1345 }
1346
1347 return 0;
1348 }
1349
1350 static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1351 {
1352 struct bnxt_napi *bnapi = dev_instance;
1353 struct bnxt *bp = bnapi->bp;
1354 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1355 u32 cons = RING_CMP(cpr->cp_raw_cons);
1356
1357 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1358 napi_schedule(&bnapi->napi);
1359 return IRQ_HANDLED;
1360 }
1361
1362 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1363 {
1364 u32 raw_cons = cpr->cp_raw_cons;
1365 u16 cons = RING_CMP(raw_cons);
1366 struct tx_cmp *txcmp;
1367
1368 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1369
1370 return TX_CMP_VALID(txcmp, raw_cons);
1371 }
1372
1373 static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1374 {
1375 struct bnxt_napi *bnapi = dev_instance;
1376 struct bnxt *bp = bnapi->bp;
1377 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1378 u32 cons = RING_CMP(cpr->cp_raw_cons);
1379 u32 int_status;
1380
1381 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1382
1383 if (!bnxt_has_work(bp, cpr)) {
1384 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
1385 /* return if erroneous interrupt */
1386 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1387 return IRQ_NONE;
1388 }
1389
1390 /* disable ring IRQ */
1391 BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell);
1392
1393 /* Return here if interrupt is shared and is disabled. */
1394 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1395 return IRQ_HANDLED;
1396
1397 napi_schedule(&bnapi->napi);
1398 return IRQ_HANDLED;
1399 }
1400
1401 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
1402 {
1403 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1404 u32 raw_cons = cpr->cp_raw_cons;
1405 u32 cons;
1406 int tx_pkts = 0;
1407 int rx_pkts = 0;
1408 bool rx_event = false;
1409 bool agg_event = false;
1410 struct tx_cmp *txcmp;
1411
1412 while (1) {
1413 int rc;
1414
1415 cons = RING_CMP(raw_cons);
1416 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1417
1418 if (!TX_CMP_VALID(txcmp, raw_cons))
1419 break;
1420
1421 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1422 tx_pkts++;
1423 /* return full budget so NAPI will complete. */
1424 if (unlikely(tx_pkts > bp->tx_wake_thresh))
1425 rx_pkts = budget;
1426 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1427 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &agg_event);
1428 if (likely(rc >= 0))
1429 rx_pkts += rc;
1430 else if (rc == -EBUSY) /* partial completion */
1431 break;
1432 rx_event = true;
1433 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1434 CMPL_BASE_TYPE_HWRM_DONE) ||
1435 (TX_CMP_TYPE(txcmp) ==
1436 CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1437 (TX_CMP_TYPE(txcmp) ==
1438 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1439 bnxt_hwrm_handler(bp, txcmp);
1440 }
1441 raw_cons = NEXT_RAW_CMP(raw_cons);
1442
1443 if (rx_pkts == budget)
1444 break;
1445 }
1446
1447 cpr->cp_raw_cons = raw_cons;
1448 /* ACK completion ring before freeing tx ring and producing new
1449 * buffers in rx/agg rings to prevent overflowing the completion
1450 * ring.
1451 */
1452 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1453
1454 if (tx_pkts)
1455 bnxt_tx_int(bp, bnapi, tx_pkts);
1456
1457 if (rx_event) {
1458 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1459
1460 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1461 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1462 if (agg_event) {
1463 writel(DB_KEY_RX | rxr->rx_agg_prod,
1464 rxr->rx_agg_doorbell);
1465 writel(DB_KEY_RX | rxr->rx_agg_prod,
1466 rxr->rx_agg_doorbell);
1467 }
1468 }
1469 return rx_pkts;
1470 }
1471
1472 static int bnxt_poll(struct napi_struct *napi, int budget)
1473 {
1474 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1475 struct bnxt *bp = bnapi->bp;
1476 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1477 int work_done = 0;
1478
1479 if (!bnxt_lock_napi(bnapi))
1480 return budget;
1481
1482 while (1) {
1483 work_done += bnxt_poll_work(bp, bnapi, budget - work_done);
1484
1485 if (work_done >= budget)
1486 break;
1487
1488 if (!bnxt_has_work(bp, cpr)) {
1489 napi_complete(napi);
1490 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1491 break;
1492 }
1493 }
1494 mmiowb();
1495 bnxt_unlock_napi(bnapi);
1496 return work_done;
1497 }
1498
1499 #ifdef CONFIG_NET_RX_BUSY_POLL
1500 static int bnxt_busy_poll(struct napi_struct *napi)
1501 {
1502 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1503 struct bnxt *bp = bnapi->bp;
1504 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1505 int rx_work, budget = 4;
1506
1507 if (atomic_read(&bp->intr_sem) != 0)
1508 return LL_FLUSH_FAILED;
1509
1510 if (!bnxt_lock_poll(bnapi))
1511 return LL_FLUSH_BUSY;
1512
1513 rx_work = bnxt_poll_work(bp, bnapi, budget);
1514
1515 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1516
1517 bnxt_unlock_poll(bnapi);
1518 return rx_work;
1519 }
1520 #endif
1521
1522 static void bnxt_free_tx_skbs(struct bnxt *bp)
1523 {
1524 int i, max_idx;
1525 struct pci_dev *pdev = bp->pdev;
1526
1527 if (!bp->tx_ring)
1528 return;
1529
1530 max_idx = bp->tx_nr_pages * TX_DESC_CNT;
1531 for (i = 0; i < bp->tx_nr_rings; i++) {
1532 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
1533 int j;
1534
1535 for (j = 0; j < max_idx;) {
1536 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
1537 struct sk_buff *skb = tx_buf->skb;
1538 int k, last;
1539
1540 if (!skb) {
1541 j++;
1542 continue;
1543 }
1544
1545 tx_buf->skb = NULL;
1546
1547 if (tx_buf->is_push) {
1548 dev_kfree_skb(skb);
1549 j += 2;
1550 continue;
1551 }
1552
1553 dma_unmap_single(&pdev->dev,
1554 dma_unmap_addr(tx_buf, mapping),
1555 skb_headlen(skb),
1556 PCI_DMA_TODEVICE);
1557
1558 last = tx_buf->nr_frags;
1559 j += 2;
1560 for (k = 0; k < last; k++, j++) {
1561 int ring_idx = j & bp->tx_ring_mask;
1562 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
1563
1564 tx_buf = &txr->tx_buf_ring[ring_idx];
1565 dma_unmap_page(
1566 &pdev->dev,
1567 dma_unmap_addr(tx_buf, mapping),
1568 skb_frag_size(frag), PCI_DMA_TODEVICE);
1569 }
1570 dev_kfree_skb(skb);
1571 }
1572 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
1573 }
1574 }
1575
1576 static void bnxt_free_rx_skbs(struct bnxt *bp)
1577 {
1578 int i, max_idx, max_agg_idx;
1579 struct pci_dev *pdev = bp->pdev;
1580
1581 if (!bp->rx_ring)
1582 return;
1583
1584 max_idx = bp->rx_nr_pages * RX_DESC_CNT;
1585 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
1586 for (i = 0; i < bp->rx_nr_rings; i++) {
1587 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
1588 int j;
1589
1590 if (rxr->rx_tpa) {
1591 for (j = 0; j < MAX_TPA; j++) {
1592 struct bnxt_tpa_info *tpa_info =
1593 &rxr->rx_tpa[j];
1594 u8 *data = tpa_info->data;
1595
1596 if (!data)
1597 continue;
1598
1599 dma_unmap_single(
1600 &pdev->dev,
1601 dma_unmap_addr(tpa_info, mapping),
1602 bp->rx_buf_use_size,
1603 PCI_DMA_FROMDEVICE);
1604
1605 tpa_info->data = NULL;
1606
1607 kfree(data);
1608 }
1609 }
1610
1611 for (j = 0; j < max_idx; j++) {
1612 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
1613 u8 *data = rx_buf->data;
1614
1615 if (!data)
1616 continue;
1617
1618 dma_unmap_single(&pdev->dev,
1619 dma_unmap_addr(rx_buf, mapping),
1620 bp->rx_buf_use_size,
1621 PCI_DMA_FROMDEVICE);
1622
1623 rx_buf->data = NULL;
1624
1625 kfree(data);
1626 }
1627
1628 for (j = 0; j < max_agg_idx; j++) {
1629 struct bnxt_sw_rx_agg_bd *rx_agg_buf =
1630 &rxr->rx_agg_ring[j];
1631 struct page *page = rx_agg_buf->page;
1632
1633 if (!page)
1634 continue;
1635
1636 dma_unmap_page(&pdev->dev,
1637 dma_unmap_addr(rx_agg_buf, mapping),
1638 PAGE_SIZE, PCI_DMA_FROMDEVICE);
1639
1640 rx_agg_buf->page = NULL;
1641 __clear_bit(j, rxr->rx_agg_bmap);
1642
1643 __free_page(page);
1644 }
1645 }
1646 }
1647
1648 static void bnxt_free_skbs(struct bnxt *bp)
1649 {
1650 bnxt_free_tx_skbs(bp);
1651 bnxt_free_rx_skbs(bp);
1652 }
1653
1654 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
1655 {
1656 struct pci_dev *pdev = bp->pdev;
1657 int i;
1658
1659 for (i = 0; i < ring->nr_pages; i++) {
1660 if (!ring->pg_arr[i])
1661 continue;
1662
1663 dma_free_coherent(&pdev->dev, ring->page_size,
1664 ring->pg_arr[i], ring->dma_arr[i]);
1665
1666 ring->pg_arr[i] = NULL;
1667 }
1668 if (ring->pg_tbl) {
1669 dma_free_coherent(&pdev->dev, ring->nr_pages * 8,
1670 ring->pg_tbl, ring->pg_tbl_map);
1671 ring->pg_tbl = NULL;
1672 }
1673 if (ring->vmem_size && *ring->vmem) {
1674 vfree(*ring->vmem);
1675 *ring->vmem = NULL;
1676 }
1677 }
1678
1679 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
1680 {
1681 int i;
1682 struct pci_dev *pdev = bp->pdev;
1683
1684 if (ring->nr_pages > 1) {
1685 ring->pg_tbl = dma_alloc_coherent(&pdev->dev,
1686 ring->nr_pages * 8,
1687 &ring->pg_tbl_map,
1688 GFP_KERNEL);
1689 if (!ring->pg_tbl)
1690 return -ENOMEM;
1691 }
1692
1693 for (i = 0; i < ring->nr_pages; i++) {
1694 ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
1695 ring->page_size,
1696 &ring->dma_arr[i],
1697 GFP_KERNEL);
1698 if (!ring->pg_arr[i])
1699 return -ENOMEM;
1700
1701 if (ring->nr_pages > 1)
1702 ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]);
1703 }
1704
1705 if (ring->vmem_size) {
1706 *ring->vmem = vzalloc(ring->vmem_size);
1707 if (!(*ring->vmem))
1708 return -ENOMEM;
1709 }
1710 return 0;
1711 }
1712
1713 static void bnxt_free_rx_rings(struct bnxt *bp)
1714 {
1715 int i;
1716
1717 if (!bp->rx_ring)
1718 return;
1719
1720 for (i = 0; i < bp->rx_nr_rings; i++) {
1721 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
1722 struct bnxt_ring_struct *ring;
1723
1724 kfree(rxr->rx_tpa);
1725 rxr->rx_tpa = NULL;
1726
1727 kfree(rxr->rx_agg_bmap);
1728 rxr->rx_agg_bmap = NULL;
1729
1730 ring = &rxr->rx_ring_struct;
1731 bnxt_free_ring(bp, ring);
1732
1733 ring = &rxr->rx_agg_ring_struct;
1734 bnxt_free_ring(bp, ring);
1735 }
1736 }
1737
1738 static int bnxt_alloc_rx_rings(struct bnxt *bp)
1739 {
1740 int i, rc, agg_rings = 0, tpa_rings = 0;
1741
1742 if (!bp->rx_ring)
1743 return -ENOMEM;
1744
1745 if (bp->flags & BNXT_FLAG_AGG_RINGS)
1746 agg_rings = 1;
1747
1748 if (bp->flags & BNXT_FLAG_TPA)
1749 tpa_rings = 1;
1750
1751 for (i = 0; i < bp->rx_nr_rings; i++) {
1752 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
1753 struct bnxt_ring_struct *ring;
1754
1755 ring = &rxr->rx_ring_struct;
1756
1757 rc = bnxt_alloc_ring(bp, ring);
1758 if (rc)
1759 return rc;
1760
1761 if (agg_rings) {
1762 u16 mem_size;
1763
1764 ring = &rxr->rx_agg_ring_struct;
1765 rc = bnxt_alloc_ring(bp, ring);
1766 if (rc)
1767 return rc;
1768
1769 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
1770 mem_size = rxr->rx_agg_bmap_size / 8;
1771 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
1772 if (!rxr->rx_agg_bmap)
1773 return -ENOMEM;
1774
1775 if (tpa_rings) {
1776 rxr->rx_tpa = kcalloc(MAX_TPA,
1777 sizeof(struct bnxt_tpa_info),
1778 GFP_KERNEL);
1779 if (!rxr->rx_tpa)
1780 return -ENOMEM;
1781 }
1782 }
1783 }
1784 return 0;
1785 }
1786
1787 static void bnxt_free_tx_rings(struct bnxt *bp)
1788 {
1789 int i;
1790 struct pci_dev *pdev = bp->pdev;
1791
1792 if (!bp->tx_ring)
1793 return;
1794
1795 for (i = 0; i < bp->tx_nr_rings; i++) {
1796 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
1797 struct bnxt_ring_struct *ring;
1798
1799 if (txr->tx_push) {
1800 dma_free_coherent(&pdev->dev, bp->tx_push_size,
1801 txr->tx_push, txr->tx_push_mapping);
1802 txr->tx_push = NULL;
1803 }
1804
1805 ring = &txr->tx_ring_struct;
1806
1807 bnxt_free_ring(bp, ring);
1808 }
1809 }
1810
1811 static int bnxt_alloc_tx_rings(struct bnxt *bp)
1812 {
1813 int i, j, rc;
1814 struct pci_dev *pdev = bp->pdev;
1815
1816 bp->tx_push_size = 0;
1817 if (bp->tx_push_thresh) {
1818 int push_size;
1819
1820 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
1821 bp->tx_push_thresh);
1822
1823 if (push_size > 256) {
1824 push_size = 0;
1825 bp->tx_push_thresh = 0;
1826 }
1827
1828 bp->tx_push_size = push_size;
1829 }
1830
1831 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
1832 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
1833 struct bnxt_ring_struct *ring;
1834
1835 ring = &txr->tx_ring_struct;
1836
1837 rc = bnxt_alloc_ring(bp, ring);
1838 if (rc)
1839 return rc;
1840
1841 if (bp->tx_push_size) {
1842 dma_addr_t mapping;
1843
1844 /* One pre-allocated DMA buffer to backup
1845 * TX push operation
1846 */
1847 txr->tx_push = dma_alloc_coherent(&pdev->dev,
1848 bp->tx_push_size,
1849 &txr->tx_push_mapping,
1850 GFP_KERNEL);
1851
1852 if (!txr->tx_push)
1853 return -ENOMEM;
1854
1855 mapping = txr->tx_push_mapping +
1856 sizeof(struct tx_push_bd);
1857 txr->data_mapping = cpu_to_le64(mapping);
1858
1859 memset(txr->tx_push, 0, sizeof(struct tx_push_bd));
1860 }
1861 ring->queue_id = bp->q_info[j].queue_id;
1862 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
1863 j++;
1864 }
1865 return 0;
1866 }
1867
1868 static void bnxt_free_cp_rings(struct bnxt *bp)
1869 {
1870 int i;
1871
1872 if (!bp->bnapi)
1873 return;
1874
1875 for (i = 0; i < bp->cp_nr_rings; i++) {
1876 struct bnxt_napi *bnapi = bp->bnapi[i];
1877 struct bnxt_cp_ring_info *cpr;
1878 struct bnxt_ring_struct *ring;
1879
1880 if (!bnapi)
1881 continue;
1882
1883 cpr = &bnapi->cp_ring;
1884 ring = &cpr->cp_ring_struct;
1885
1886 bnxt_free_ring(bp, ring);
1887 }
1888 }
1889
1890 static int bnxt_alloc_cp_rings(struct bnxt *bp)
1891 {
1892 int i, rc;
1893
1894 for (i = 0; i < bp->cp_nr_rings; i++) {
1895 struct bnxt_napi *bnapi = bp->bnapi[i];
1896 struct bnxt_cp_ring_info *cpr;
1897 struct bnxt_ring_struct *ring;
1898
1899 if (!bnapi)
1900 continue;
1901
1902 cpr = &bnapi->cp_ring;
1903 ring = &cpr->cp_ring_struct;
1904
1905 rc = bnxt_alloc_ring(bp, ring);
1906 if (rc)
1907 return rc;
1908 }
1909 return 0;
1910 }
1911
1912 static void bnxt_init_ring_struct(struct bnxt *bp)
1913 {
1914 int i;
1915
1916 for (i = 0; i < bp->cp_nr_rings; i++) {
1917 struct bnxt_napi *bnapi = bp->bnapi[i];
1918 struct bnxt_cp_ring_info *cpr;
1919 struct bnxt_rx_ring_info *rxr;
1920 struct bnxt_tx_ring_info *txr;
1921 struct bnxt_ring_struct *ring;
1922
1923 if (!bnapi)
1924 continue;
1925
1926 cpr = &bnapi->cp_ring;
1927 ring = &cpr->cp_ring_struct;
1928 ring->nr_pages = bp->cp_nr_pages;
1929 ring->page_size = HW_CMPD_RING_SIZE;
1930 ring->pg_arr = (void **)cpr->cp_desc_ring;
1931 ring->dma_arr = cpr->cp_desc_mapping;
1932 ring->vmem_size = 0;
1933
1934 rxr = bnapi->rx_ring;
1935 if (!rxr)
1936 goto skip_rx;
1937
1938 ring = &rxr->rx_ring_struct;
1939 ring->nr_pages = bp->rx_nr_pages;
1940 ring->page_size = HW_RXBD_RING_SIZE;
1941 ring->pg_arr = (void **)rxr->rx_desc_ring;
1942 ring->dma_arr = rxr->rx_desc_mapping;
1943 ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
1944 ring->vmem = (void **)&rxr->rx_buf_ring;
1945
1946 ring = &rxr->rx_agg_ring_struct;
1947 ring->nr_pages = bp->rx_agg_nr_pages;
1948 ring->page_size = HW_RXBD_RING_SIZE;
1949 ring->pg_arr = (void **)rxr->rx_agg_desc_ring;
1950 ring->dma_arr = rxr->rx_agg_desc_mapping;
1951 ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
1952 ring->vmem = (void **)&rxr->rx_agg_ring;
1953
1954 skip_rx:
1955 txr = bnapi->tx_ring;
1956 if (!txr)
1957 continue;
1958
1959 ring = &txr->tx_ring_struct;
1960 ring->nr_pages = bp->tx_nr_pages;
1961 ring->page_size = HW_RXBD_RING_SIZE;
1962 ring->pg_arr = (void **)txr->tx_desc_ring;
1963 ring->dma_arr = txr->tx_desc_mapping;
1964 ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
1965 ring->vmem = (void **)&txr->tx_buf_ring;
1966 }
1967 }
1968
1969 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
1970 {
1971 int i;
1972 u32 prod;
1973 struct rx_bd **rx_buf_ring;
1974
1975 rx_buf_ring = (struct rx_bd **)ring->pg_arr;
1976 for (i = 0, prod = 0; i < ring->nr_pages; i++) {
1977 int j;
1978 struct rx_bd *rxbd;
1979
1980 rxbd = rx_buf_ring[i];
1981 if (!rxbd)
1982 continue;
1983
1984 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
1985 rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
1986 rxbd->rx_bd_opaque = prod;
1987 }
1988 }
1989 }
1990
1991 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
1992 {
1993 struct net_device *dev = bp->dev;
1994 struct bnxt_rx_ring_info *rxr;
1995 struct bnxt_ring_struct *ring;
1996 u32 prod, type;
1997 int i;
1998
1999 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
2000 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
2001
2002 if (NET_IP_ALIGN == 2)
2003 type |= RX_BD_FLAGS_SOP;
2004
2005 rxr = &bp->rx_ring[ring_nr];
2006 ring = &rxr->rx_ring_struct;
2007 bnxt_init_rxbd_pages(ring, type);
2008
2009 prod = rxr->rx_prod;
2010 for (i = 0; i < bp->rx_ring_size; i++) {
2011 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
2012 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
2013 ring_nr, i, bp->rx_ring_size);
2014 break;
2015 }
2016 prod = NEXT_RX(prod);
2017 }
2018 rxr->rx_prod = prod;
2019 ring->fw_ring_id = INVALID_HW_RING_ID;
2020
2021 ring = &rxr->rx_agg_ring_struct;
2022 ring->fw_ring_id = INVALID_HW_RING_ID;
2023
2024 if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
2025 return 0;
2026
2027 type = ((u32)PAGE_SIZE << RX_BD_LEN_SHIFT) |
2028 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
2029
2030 bnxt_init_rxbd_pages(ring, type);
2031
2032 prod = rxr->rx_agg_prod;
2033 for (i = 0; i < bp->rx_agg_ring_size; i++) {
2034 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
2035 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
2036 ring_nr, i, bp->rx_ring_size);
2037 break;
2038 }
2039 prod = NEXT_RX_AGG(prod);
2040 }
2041 rxr->rx_agg_prod = prod;
2042
2043 if (bp->flags & BNXT_FLAG_TPA) {
2044 if (rxr->rx_tpa) {
2045 u8 *data;
2046 dma_addr_t mapping;
2047
2048 for (i = 0; i < MAX_TPA; i++) {
2049 data = __bnxt_alloc_rx_data(bp, &mapping,
2050 GFP_KERNEL);
2051 if (!data)
2052 return -ENOMEM;
2053
2054 rxr->rx_tpa[i].data = data;
2055 rxr->rx_tpa[i].mapping = mapping;
2056 }
2057 } else {
2058 netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2059 return -ENOMEM;
2060 }
2061 }
2062
2063 return 0;
2064 }
2065
2066 static int bnxt_init_rx_rings(struct bnxt *bp)
2067 {
2068 int i, rc = 0;
2069
2070 for (i = 0; i < bp->rx_nr_rings; i++) {
2071 rc = bnxt_init_one_rx_ring(bp, i);
2072 if (rc)
2073 break;
2074 }
2075
2076 return rc;
2077 }
2078
2079 static int bnxt_init_tx_rings(struct bnxt *bp)
2080 {
2081 u16 i;
2082
2083 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2084 MAX_SKB_FRAGS + 1);
2085
2086 for (i = 0; i < bp->tx_nr_rings; i++) {
2087 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2088 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2089
2090 ring->fw_ring_id = INVALID_HW_RING_ID;
2091 }
2092
2093 return 0;
2094 }
2095
2096 static void bnxt_free_ring_grps(struct bnxt *bp)
2097 {
2098 kfree(bp->grp_info);
2099 bp->grp_info = NULL;
2100 }
2101
2102 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2103 {
2104 int i;
2105
2106 if (irq_re_init) {
2107 bp->grp_info = kcalloc(bp->cp_nr_rings,
2108 sizeof(struct bnxt_ring_grp_info),
2109 GFP_KERNEL);
2110 if (!bp->grp_info)
2111 return -ENOMEM;
2112 }
2113 for (i = 0; i < bp->cp_nr_rings; i++) {
2114 if (irq_re_init)
2115 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
2116 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
2117 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
2118 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
2119 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
2120 }
2121 return 0;
2122 }
2123
2124 static void bnxt_free_vnics(struct bnxt *bp)
2125 {
2126 kfree(bp->vnic_info);
2127 bp->vnic_info = NULL;
2128 bp->nr_vnics = 0;
2129 }
2130
2131 static int bnxt_alloc_vnics(struct bnxt *bp)
2132 {
2133 int num_vnics = 1;
2134
2135 #ifdef CONFIG_RFS_ACCEL
2136 if (bp->flags & BNXT_FLAG_RFS)
2137 num_vnics += bp->rx_nr_rings;
2138 #endif
2139
2140 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
2141 GFP_KERNEL);
2142 if (!bp->vnic_info)
2143 return -ENOMEM;
2144
2145 bp->nr_vnics = num_vnics;
2146 return 0;
2147 }
2148
2149 static void bnxt_init_vnics(struct bnxt *bp)
2150 {
2151 int i;
2152
2153 for (i = 0; i < bp->nr_vnics; i++) {
2154 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2155
2156 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2157 vnic->fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
2158 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
2159
2160 if (bp->vnic_info[i].rss_hash_key) {
2161 if (i == 0)
2162 prandom_bytes(vnic->rss_hash_key,
2163 HW_HASH_KEY_SIZE);
2164 else
2165 memcpy(vnic->rss_hash_key,
2166 bp->vnic_info[0].rss_hash_key,
2167 HW_HASH_KEY_SIZE);
2168 }
2169 }
2170 }
2171
2172 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
2173 {
2174 int pages;
2175
2176 pages = ring_size / desc_per_pg;
2177
2178 if (!pages)
2179 return 1;
2180
2181 pages++;
2182
2183 while (pages & (pages - 1))
2184 pages++;
2185
2186 return pages;
2187 }
2188
2189 static void bnxt_set_tpa_flags(struct bnxt *bp)
2190 {
2191 bp->flags &= ~BNXT_FLAG_TPA;
2192 if (bp->dev->features & NETIF_F_LRO)
2193 bp->flags |= BNXT_FLAG_LRO;
2194 if ((bp->dev->features & NETIF_F_GRO) && (bp->pdev->revision > 0))
2195 bp->flags |= BNXT_FLAG_GRO;
2196 }
2197
2198 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2199 * be set on entry.
2200 */
2201 void bnxt_set_ring_params(struct bnxt *bp)
2202 {
2203 u32 ring_size, rx_size, rx_space;
2204 u32 agg_factor = 0, agg_ring_size = 0;
2205
2206 /* 8 for CRC and VLAN */
2207 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
2208
2209 rx_space = rx_size + NET_SKB_PAD +
2210 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2211
2212 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
2213 ring_size = bp->rx_ring_size;
2214 bp->rx_agg_ring_size = 0;
2215 bp->rx_agg_nr_pages = 0;
2216
2217 if (bp->flags & BNXT_FLAG_TPA)
2218 agg_factor = 4;
2219
2220 bp->flags &= ~BNXT_FLAG_JUMBO;
2221 if (rx_space > PAGE_SIZE) {
2222 u32 jumbo_factor;
2223
2224 bp->flags |= BNXT_FLAG_JUMBO;
2225 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
2226 if (jumbo_factor > agg_factor)
2227 agg_factor = jumbo_factor;
2228 }
2229 agg_ring_size = ring_size * agg_factor;
2230
2231 if (agg_ring_size) {
2232 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
2233 RX_DESC_CNT);
2234 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
2235 u32 tmp = agg_ring_size;
2236
2237 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
2238 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
2239 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
2240 tmp, agg_ring_size);
2241 }
2242 bp->rx_agg_ring_size = agg_ring_size;
2243 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
2244 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
2245 rx_space = rx_size + NET_SKB_PAD +
2246 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2247 }
2248
2249 bp->rx_buf_use_size = rx_size;
2250 bp->rx_buf_size = rx_space;
2251
2252 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
2253 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
2254
2255 ring_size = bp->tx_ring_size;
2256 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
2257 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
2258
2259 ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
2260 bp->cp_ring_size = ring_size;
2261
2262 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
2263 if (bp->cp_nr_pages > MAX_CP_PAGES) {
2264 bp->cp_nr_pages = MAX_CP_PAGES;
2265 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
2266 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
2267 ring_size, bp->cp_ring_size);
2268 }
2269 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
2270 bp->cp_ring_mask = bp->cp_bit - 1;
2271 }
2272
2273 static void bnxt_free_vnic_attributes(struct bnxt *bp)
2274 {
2275 int i;
2276 struct bnxt_vnic_info *vnic;
2277 struct pci_dev *pdev = bp->pdev;
2278
2279 if (!bp->vnic_info)
2280 return;
2281
2282 for (i = 0; i < bp->nr_vnics; i++) {
2283 vnic = &bp->vnic_info[i];
2284
2285 kfree(vnic->fw_grp_ids);
2286 vnic->fw_grp_ids = NULL;
2287
2288 kfree(vnic->uc_list);
2289 vnic->uc_list = NULL;
2290
2291 if (vnic->mc_list) {
2292 dma_free_coherent(&pdev->dev, vnic->mc_list_size,
2293 vnic->mc_list, vnic->mc_list_mapping);
2294 vnic->mc_list = NULL;
2295 }
2296
2297 if (vnic->rss_table) {
2298 dma_free_coherent(&pdev->dev, PAGE_SIZE,
2299 vnic->rss_table,
2300 vnic->rss_table_dma_addr);
2301 vnic->rss_table = NULL;
2302 }
2303
2304 vnic->rss_hash_key = NULL;
2305 vnic->flags = 0;
2306 }
2307 }
2308
2309 static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
2310 {
2311 int i, rc = 0, size;
2312 struct bnxt_vnic_info *vnic;
2313 struct pci_dev *pdev = bp->pdev;
2314 int max_rings;
2315
2316 for (i = 0; i < bp->nr_vnics; i++) {
2317 vnic = &bp->vnic_info[i];
2318
2319 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
2320 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
2321
2322 if (mem_size > 0) {
2323 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
2324 if (!vnic->uc_list) {
2325 rc = -ENOMEM;
2326 goto out;
2327 }
2328 }
2329 }
2330
2331 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
2332 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
2333 vnic->mc_list =
2334 dma_alloc_coherent(&pdev->dev,
2335 vnic->mc_list_size,
2336 &vnic->mc_list_mapping,
2337 GFP_KERNEL);
2338 if (!vnic->mc_list) {
2339 rc = -ENOMEM;
2340 goto out;
2341 }
2342 }
2343
2344 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
2345 max_rings = bp->rx_nr_rings;
2346 else
2347 max_rings = 1;
2348
2349 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
2350 if (!vnic->fw_grp_ids) {
2351 rc = -ENOMEM;
2352 goto out;
2353 }
2354
2355 /* Allocate rss table and hash key */
2356 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2357 &vnic->rss_table_dma_addr,
2358 GFP_KERNEL);
2359 if (!vnic->rss_table) {
2360 rc = -ENOMEM;
2361 goto out;
2362 }
2363
2364 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
2365
2366 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
2367 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
2368 }
2369 return 0;
2370
2371 out:
2372 return rc;
2373 }
2374
2375 static void bnxt_free_hwrm_resources(struct bnxt *bp)
2376 {
2377 struct pci_dev *pdev = bp->pdev;
2378
2379 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
2380 bp->hwrm_cmd_resp_dma_addr);
2381
2382 bp->hwrm_cmd_resp_addr = NULL;
2383 if (bp->hwrm_dbg_resp_addr) {
2384 dma_free_coherent(&pdev->dev, HWRM_DBG_REG_BUF_SIZE,
2385 bp->hwrm_dbg_resp_addr,
2386 bp->hwrm_dbg_resp_dma_addr);
2387
2388 bp->hwrm_dbg_resp_addr = NULL;
2389 }
2390 }
2391
2392 static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2393 {
2394 struct pci_dev *pdev = bp->pdev;
2395
2396 bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2397 &bp->hwrm_cmd_resp_dma_addr,
2398 GFP_KERNEL);
2399 if (!bp->hwrm_cmd_resp_addr)
2400 return -ENOMEM;
2401 bp->hwrm_dbg_resp_addr = dma_alloc_coherent(&pdev->dev,
2402 HWRM_DBG_REG_BUF_SIZE,
2403 &bp->hwrm_dbg_resp_dma_addr,
2404 GFP_KERNEL);
2405 if (!bp->hwrm_dbg_resp_addr)
2406 netdev_warn(bp->dev, "fail to alloc debug register dma mem\n");
2407
2408 return 0;
2409 }
2410
2411 static void bnxt_free_stats(struct bnxt *bp)
2412 {
2413 u32 size, i;
2414 struct pci_dev *pdev = bp->pdev;
2415
2416 if (bp->hw_rx_port_stats) {
2417 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size,
2418 bp->hw_rx_port_stats,
2419 bp->hw_rx_port_stats_map);
2420 bp->hw_rx_port_stats = NULL;
2421 bp->flags &= ~BNXT_FLAG_PORT_STATS;
2422 }
2423
2424 if (!bp->bnapi)
2425 return;
2426
2427 size = sizeof(struct ctx_hw_stats);
2428
2429 for (i = 0; i < bp->cp_nr_rings; i++) {
2430 struct bnxt_napi *bnapi = bp->bnapi[i];
2431 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2432
2433 if (cpr->hw_stats) {
2434 dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
2435 cpr->hw_stats_map);
2436 cpr->hw_stats = NULL;
2437 }
2438 }
2439 }
2440
2441 static int bnxt_alloc_stats(struct bnxt *bp)
2442 {
2443 u32 size, i;
2444 struct pci_dev *pdev = bp->pdev;
2445
2446 size = sizeof(struct ctx_hw_stats);
2447
2448 for (i = 0; i < bp->cp_nr_rings; i++) {
2449 struct bnxt_napi *bnapi = bp->bnapi[i];
2450 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2451
2452 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
2453 &cpr->hw_stats_map,
2454 GFP_KERNEL);
2455 if (!cpr->hw_stats)
2456 return -ENOMEM;
2457
2458 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
2459 }
2460
2461 if (BNXT_PF(bp)) {
2462 bp->hw_port_stats_size = sizeof(struct rx_port_stats) +
2463 sizeof(struct tx_port_stats) + 1024;
2464
2465 bp->hw_rx_port_stats =
2466 dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size,
2467 &bp->hw_rx_port_stats_map,
2468 GFP_KERNEL);
2469 if (!bp->hw_rx_port_stats)
2470 return -ENOMEM;
2471
2472 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) +
2473 512;
2474 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map +
2475 sizeof(struct rx_port_stats) + 512;
2476 bp->flags |= BNXT_FLAG_PORT_STATS;
2477 }
2478 return 0;
2479 }
2480
2481 static void bnxt_clear_ring_indices(struct bnxt *bp)
2482 {
2483 int i;
2484
2485 if (!bp->bnapi)
2486 return;
2487
2488 for (i = 0; i < bp->cp_nr_rings; i++) {
2489 struct bnxt_napi *bnapi = bp->bnapi[i];
2490 struct bnxt_cp_ring_info *cpr;
2491 struct bnxt_rx_ring_info *rxr;
2492 struct bnxt_tx_ring_info *txr;
2493
2494 if (!bnapi)
2495 continue;
2496
2497 cpr = &bnapi->cp_ring;
2498 cpr->cp_raw_cons = 0;
2499
2500 txr = bnapi->tx_ring;
2501 if (txr) {
2502 txr->tx_prod = 0;
2503 txr->tx_cons = 0;
2504 }
2505
2506 rxr = bnapi->rx_ring;
2507 if (rxr) {
2508 rxr->rx_prod = 0;
2509 rxr->rx_agg_prod = 0;
2510 rxr->rx_sw_agg_prod = 0;
2511 }
2512 }
2513 }
2514
2515 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
2516 {
2517 #ifdef CONFIG_RFS_ACCEL
2518 int i;
2519
2520 /* Under rtnl_lock and all our NAPIs have been disabled. It's
2521 * safe to delete the hash table.
2522 */
2523 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
2524 struct hlist_head *head;
2525 struct hlist_node *tmp;
2526 struct bnxt_ntuple_filter *fltr;
2527
2528 head = &bp->ntp_fltr_hash_tbl[i];
2529 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
2530 hlist_del(&fltr->hash);
2531 kfree(fltr);
2532 }
2533 }
2534 if (irq_reinit) {
2535 kfree(bp->ntp_fltr_bmap);
2536 bp->ntp_fltr_bmap = NULL;
2537 }
2538 bp->ntp_fltr_count = 0;
2539 #endif
2540 }
2541
2542 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
2543 {
2544 #ifdef CONFIG_RFS_ACCEL
2545 int i, rc = 0;
2546
2547 if (!(bp->flags & BNXT_FLAG_RFS))
2548 return 0;
2549
2550 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
2551 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
2552
2553 bp->ntp_fltr_count = 0;
2554 bp->ntp_fltr_bmap = kzalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
2555 GFP_KERNEL);
2556
2557 if (!bp->ntp_fltr_bmap)
2558 rc = -ENOMEM;
2559
2560 return rc;
2561 #else
2562 return 0;
2563 #endif
2564 }
2565
2566 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
2567 {
2568 bnxt_free_vnic_attributes(bp);
2569 bnxt_free_tx_rings(bp);
2570 bnxt_free_rx_rings(bp);
2571 bnxt_free_cp_rings(bp);
2572 bnxt_free_ntp_fltrs(bp, irq_re_init);
2573 if (irq_re_init) {
2574 bnxt_free_stats(bp);
2575 bnxt_free_ring_grps(bp);
2576 bnxt_free_vnics(bp);
2577 kfree(bp->tx_ring);
2578 bp->tx_ring = NULL;
2579 kfree(bp->rx_ring);
2580 bp->rx_ring = NULL;
2581 kfree(bp->bnapi);
2582 bp->bnapi = NULL;
2583 } else {
2584 bnxt_clear_ring_indices(bp);
2585 }
2586 }
2587
2588 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
2589 {
2590 int i, j, rc, size, arr_size;
2591 void *bnapi;
2592
2593 if (irq_re_init) {
2594 /* Allocate bnapi mem pointer array and mem block for
2595 * all queues
2596 */
2597 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
2598 bp->cp_nr_rings);
2599 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
2600 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
2601 if (!bnapi)
2602 return -ENOMEM;
2603
2604 bp->bnapi = bnapi;
2605 bnapi += arr_size;
2606 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
2607 bp->bnapi[i] = bnapi;
2608 bp->bnapi[i]->index = i;
2609 bp->bnapi[i]->bp = bp;
2610 }
2611
2612 bp->rx_ring = kcalloc(bp->rx_nr_rings,
2613 sizeof(struct bnxt_rx_ring_info),
2614 GFP_KERNEL);
2615 if (!bp->rx_ring)
2616 return -ENOMEM;
2617
2618 for (i = 0; i < bp->rx_nr_rings; i++) {
2619 bp->rx_ring[i].bnapi = bp->bnapi[i];
2620 bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
2621 }
2622
2623 bp->tx_ring = kcalloc(bp->tx_nr_rings,
2624 sizeof(struct bnxt_tx_ring_info),
2625 GFP_KERNEL);
2626 if (!bp->tx_ring)
2627 return -ENOMEM;
2628
2629 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
2630 j = 0;
2631 else
2632 j = bp->rx_nr_rings;
2633
2634 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
2635 bp->tx_ring[i].bnapi = bp->bnapi[j];
2636 bp->bnapi[j]->tx_ring = &bp->tx_ring[i];
2637 }
2638
2639 rc = bnxt_alloc_stats(bp);
2640 if (rc)
2641 goto alloc_mem_err;
2642
2643 rc = bnxt_alloc_ntp_fltrs(bp);
2644 if (rc)
2645 goto alloc_mem_err;
2646
2647 rc = bnxt_alloc_vnics(bp);
2648 if (rc)
2649 goto alloc_mem_err;
2650 }
2651
2652 bnxt_init_ring_struct(bp);
2653
2654 rc = bnxt_alloc_rx_rings(bp);
2655 if (rc)
2656 goto alloc_mem_err;
2657
2658 rc = bnxt_alloc_tx_rings(bp);
2659 if (rc)
2660 goto alloc_mem_err;
2661
2662 rc = bnxt_alloc_cp_rings(bp);
2663 if (rc)
2664 goto alloc_mem_err;
2665
2666 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
2667 BNXT_VNIC_UCAST_FLAG;
2668 rc = bnxt_alloc_vnic_attributes(bp);
2669 if (rc)
2670 goto alloc_mem_err;
2671 return 0;
2672
2673 alloc_mem_err:
2674 bnxt_free_mem(bp, true);
2675 return rc;
2676 }
2677
2678 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
2679 u16 cmpl_ring, u16 target_id)
2680 {
2681 struct input *req = request;
2682
2683 req->req_type = cpu_to_le16(req_type);
2684 req->cmpl_ring = cpu_to_le16(cmpl_ring);
2685 req->target_id = cpu_to_le16(target_id);
2686 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
2687 }
2688
2689 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
2690 int timeout, bool silent)
2691 {
2692 int i, intr_process, rc;
2693 struct input *req = msg;
2694 u32 *data = msg;
2695 __le32 *resp_len, *valid;
2696 u16 cp_ring_id, len = 0;
2697 struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
2698
2699 req->seq_id = cpu_to_le16(bp->hwrm_cmd_seq++);
2700 memset(resp, 0, PAGE_SIZE);
2701 cp_ring_id = le16_to_cpu(req->cmpl_ring);
2702 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
2703
2704 /* Write request msg to hwrm channel */
2705 __iowrite32_copy(bp->bar0, data, msg_len / 4);
2706
2707 for (i = msg_len; i < BNXT_HWRM_MAX_REQ_LEN; i += 4)
2708 writel(0, bp->bar0 + i);
2709
2710 /* currently supports only one outstanding message */
2711 if (intr_process)
2712 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
2713
2714 /* Ring channel doorbell */
2715 writel(1, bp->bar0 + 0x100);
2716
2717 if (!timeout)
2718 timeout = DFLT_HWRM_CMD_TIMEOUT;
2719
2720 i = 0;
2721 if (intr_process) {
2722 /* Wait until hwrm response cmpl interrupt is processed */
2723 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID &&
2724 i++ < timeout) {
2725 usleep_range(600, 800);
2726 }
2727
2728 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) {
2729 netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
2730 le16_to_cpu(req->req_type));
2731 return -1;
2732 }
2733 } else {
2734 /* Check if response len is updated */
2735 resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET;
2736 for (i = 0; i < timeout; i++) {
2737 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
2738 HWRM_RESP_LEN_SFT;
2739 if (len)
2740 break;
2741 usleep_range(600, 800);
2742 }
2743
2744 if (i >= timeout) {
2745 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
2746 timeout, le16_to_cpu(req->req_type),
2747 le16_to_cpu(req->seq_id), *resp_len);
2748 return -1;
2749 }
2750
2751 /* Last word of resp contains valid bit */
2752 valid = bp->hwrm_cmd_resp_addr + len - 4;
2753 for (i = 0; i < timeout; i++) {
2754 if (le32_to_cpu(*valid) & HWRM_RESP_VALID_MASK)
2755 break;
2756 usleep_range(600, 800);
2757 }
2758
2759 if (i >= timeout) {
2760 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
2761 timeout, le16_to_cpu(req->req_type),
2762 le16_to_cpu(req->seq_id), len, *valid);
2763 return -1;
2764 }
2765 }
2766
2767 rc = le16_to_cpu(resp->error_code);
2768 if (rc && !silent)
2769 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
2770 le16_to_cpu(resp->req_type),
2771 le16_to_cpu(resp->seq_id), rc);
2772 return rc;
2773 }
2774
2775 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
2776 {
2777 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
2778 }
2779
2780 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
2781 {
2782 int rc;
2783
2784 mutex_lock(&bp->hwrm_cmd_lock);
2785 rc = _hwrm_send_message(bp, msg, msg_len, timeout);
2786 mutex_unlock(&bp->hwrm_cmd_lock);
2787 return rc;
2788 }
2789
2790 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
2791 int timeout)
2792 {
2793 int rc;
2794
2795 mutex_lock(&bp->hwrm_cmd_lock);
2796 rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
2797 mutex_unlock(&bp->hwrm_cmd_lock);
2798 return rc;
2799 }
2800
2801 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
2802 {
2803 struct hwrm_func_drv_rgtr_input req = {0};
2804 int i;
2805 DECLARE_BITMAP(async_events_bmap, 256);
2806 u32 *events = (u32 *)async_events_bmap;
2807
2808 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
2809
2810 req.enables =
2811 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
2812 FUNC_DRV_RGTR_REQ_ENABLES_VER |
2813 FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
2814
2815 memset(async_events_bmap, 0, sizeof(async_events_bmap));
2816 for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++)
2817 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
2818
2819 for (i = 0; i < 8; i++)
2820 req.async_event_fwd[i] |= cpu_to_le32(events[i]);
2821
2822 req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
2823 req.ver_maj = DRV_VER_MAJ;
2824 req.ver_min = DRV_VER_MIN;
2825 req.ver_upd = DRV_VER_UPD;
2826
2827 if (BNXT_PF(bp)) {
2828 DECLARE_BITMAP(vf_req_snif_bmap, 256);
2829 u32 *data = (u32 *)vf_req_snif_bmap;
2830
2831 memset(vf_req_snif_bmap, 0, sizeof(vf_req_snif_bmap));
2832 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++)
2833 __set_bit(bnxt_vf_req_snif[i], vf_req_snif_bmap);
2834
2835 for (i = 0; i < 8; i++)
2836 req.vf_req_fwd[i] = cpu_to_le32(data[i]);
2837
2838 req.enables |=
2839 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
2840 }
2841
2842 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2843 }
2844
2845 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
2846 {
2847 struct hwrm_func_drv_unrgtr_input req = {0};
2848
2849 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
2850 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2851 }
2852
2853 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
2854 {
2855 u32 rc = 0;
2856 struct hwrm_tunnel_dst_port_free_input req = {0};
2857
2858 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
2859 req.tunnel_type = tunnel_type;
2860
2861 switch (tunnel_type) {
2862 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
2863 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
2864 break;
2865 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
2866 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
2867 break;
2868 default:
2869 break;
2870 }
2871
2872 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2873 if (rc)
2874 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
2875 rc);
2876 return rc;
2877 }
2878
2879 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
2880 u8 tunnel_type)
2881 {
2882 u32 rc = 0;
2883 struct hwrm_tunnel_dst_port_alloc_input req = {0};
2884 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2885
2886 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
2887
2888 req.tunnel_type = tunnel_type;
2889 req.tunnel_dst_port_val = port;
2890
2891 mutex_lock(&bp->hwrm_cmd_lock);
2892 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2893 if (rc) {
2894 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
2895 rc);
2896 goto err_out;
2897 }
2898
2899 if (tunnel_type & TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN)
2900 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
2901
2902 else if (tunnel_type & TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE)
2903 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
2904 err_out:
2905 mutex_unlock(&bp->hwrm_cmd_lock);
2906 return rc;
2907 }
2908
2909 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
2910 {
2911 struct hwrm_cfa_l2_set_rx_mask_input req = {0};
2912 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2913
2914 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
2915 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
2916
2917 req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
2918 req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
2919 req.mask = cpu_to_le32(vnic->rx_mask);
2920 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2921 }
2922
2923 #ifdef CONFIG_RFS_ACCEL
2924 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
2925 struct bnxt_ntuple_filter *fltr)
2926 {
2927 struct hwrm_cfa_ntuple_filter_free_input req = {0};
2928
2929 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
2930 req.ntuple_filter_id = fltr->filter_id;
2931 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2932 }
2933
2934 #define BNXT_NTP_FLTR_FLAGS \
2935 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
2936 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
2937 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
2938 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
2939 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
2940 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
2941 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
2942 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
2943 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
2944 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
2945 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
2946 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
2947 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
2948 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
2949
2950 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
2951 struct bnxt_ntuple_filter *fltr)
2952 {
2953 int rc = 0;
2954 struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
2955 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
2956 bp->hwrm_cmd_resp_addr;
2957 struct flow_keys *keys = &fltr->fkeys;
2958 struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1];
2959
2960 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
2961 req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[0];
2962
2963 req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
2964
2965 req.ethertype = htons(ETH_P_IP);
2966 memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
2967 req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
2968 req.ip_protocol = keys->basic.ip_proto;
2969
2970 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
2971 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
2972 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
2973 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
2974
2975 req.src_port = keys->ports.src;
2976 req.src_port_mask = cpu_to_be16(0xffff);
2977 req.dst_port = keys->ports.dst;
2978 req.dst_port_mask = cpu_to_be16(0xffff);
2979
2980 req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
2981 mutex_lock(&bp->hwrm_cmd_lock);
2982 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2983 if (!rc)
2984 fltr->filter_id = resp->ntuple_filter_id;
2985 mutex_unlock(&bp->hwrm_cmd_lock);
2986 return rc;
2987 }
2988 #endif
2989
2990 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
2991 u8 *mac_addr)
2992 {
2993 u32 rc = 0;
2994 struct hwrm_cfa_l2_filter_alloc_input req = {0};
2995 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2996
2997 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
2998 req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX |
2999 CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
3000 req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
3001 req.enables =
3002 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
3003 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
3004 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
3005 memcpy(req.l2_addr, mac_addr, ETH_ALEN);
3006 req.l2_addr_mask[0] = 0xff;
3007 req.l2_addr_mask[1] = 0xff;
3008 req.l2_addr_mask[2] = 0xff;
3009 req.l2_addr_mask[3] = 0xff;
3010 req.l2_addr_mask[4] = 0xff;
3011 req.l2_addr_mask[5] = 0xff;
3012
3013 mutex_lock(&bp->hwrm_cmd_lock);
3014 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3015 if (!rc)
3016 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
3017 resp->l2_filter_id;
3018 mutex_unlock(&bp->hwrm_cmd_lock);
3019 return rc;
3020 }
3021
3022 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
3023 {
3024 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
3025 int rc = 0;
3026
3027 /* Any associated ntuple filters will also be cleared by firmware. */
3028 mutex_lock(&bp->hwrm_cmd_lock);
3029 for (i = 0; i < num_of_vnics; i++) {
3030 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3031
3032 for (j = 0; j < vnic->uc_filter_count; j++) {
3033 struct hwrm_cfa_l2_filter_free_input req = {0};
3034
3035 bnxt_hwrm_cmd_hdr_init(bp, &req,
3036 HWRM_CFA_L2_FILTER_FREE, -1, -1);
3037
3038 req.l2_filter_id = vnic->fw_l2_filter_id[j];
3039
3040 rc = _hwrm_send_message(bp, &req, sizeof(req),
3041 HWRM_CMD_TIMEOUT);
3042 }
3043 vnic->uc_filter_count = 0;
3044 }
3045 mutex_unlock(&bp->hwrm_cmd_lock);
3046
3047 return rc;
3048 }
3049
3050 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
3051 {
3052 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3053 struct hwrm_vnic_tpa_cfg_input req = {0};
3054
3055 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
3056
3057 if (tpa_flags) {
3058 u16 mss = bp->dev->mtu - 40;
3059 u32 nsegs, n, segs = 0, flags;
3060
3061 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
3062 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
3063 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
3064 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
3065 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
3066 if (tpa_flags & BNXT_FLAG_GRO)
3067 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
3068
3069 req.flags = cpu_to_le32(flags);
3070
3071 req.enables =
3072 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
3073 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
3074 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
3075
3076 /* Number of segs are log2 units, and first packet is not
3077 * included as part of this units.
3078 */
3079 if (mss <= PAGE_SIZE) {
3080 n = PAGE_SIZE / mss;
3081 nsegs = (MAX_SKB_FRAGS - 1) * n;
3082 } else {
3083 n = mss / PAGE_SIZE;
3084 if (mss & (PAGE_SIZE - 1))
3085 n++;
3086 nsegs = (MAX_SKB_FRAGS - n) / n;
3087 }
3088
3089 segs = ilog2(nsegs);
3090 req.max_agg_segs = cpu_to_le16(segs);
3091 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
3092
3093 req.min_agg_len = cpu_to_le32(512);
3094 }
3095 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3096
3097 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3098 }
3099
3100 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
3101 {
3102 u32 i, j, max_rings;
3103 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3104 struct hwrm_vnic_rss_cfg_input req = {0};
3105
3106 if (vnic->fw_rss_cos_lb_ctx == INVALID_HW_RING_ID)
3107 return 0;
3108
3109 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
3110 if (set_rss) {
3111 vnic->hash_type = BNXT_RSS_HASH_TYPE_FLAG_IPV4 |
3112 BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV4 |
3113 BNXT_RSS_HASH_TYPE_FLAG_IPV6 |
3114 BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV6;
3115
3116 req.hash_type = cpu_to_le32(vnic->hash_type);
3117
3118 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3119 max_rings = bp->rx_nr_rings;
3120 else
3121 max_rings = 1;
3122
3123 /* Fill the RSS indirection table with ring group ids */
3124 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
3125 if (j == max_rings)
3126 j = 0;
3127 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
3128 }
3129
3130 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
3131 req.hash_key_tbl_addr =
3132 cpu_to_le64(vnic->rss_hash_key_dma_addr);
3133 }
3134 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx);
3135 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3136 }
3137
3138 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
3139 {
3140 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3141 struct hwrm_vnic_plcmodes_cfg_input req = {0};
3142
3143 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
3144 req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
3145 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
3146 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
3147 req.enables =
3148 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
3149 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
3150 /* thresholds not implemented in firmware yet */
3151 req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
3152 req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
3153 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3154 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3155 }
3156
3157 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id)
3158 {
3159 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
3160
3161 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
3162 req.rss_cos_lb_ctx_id =
3163 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx);
3164
3165 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3166 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
3167 }
3168
3169 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
3170 {
3171 int i;
3172
3173 for (i = 0; i < bp->nr_vnics; i++) {
3174 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3175
3176 if (vnic->fw_rss_cos_lb_ctx != INVALID_HW_RING_ID)
3177 bnxt_hwrm_vnic_ctx_free_one(bp, i);
3178 }
3179 bp->rsscos_nr_ctxs = 0;
3180 }
3181
3182 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id)
3183 {
3184 int rc;
3185 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
3186 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
3187 bp->hwrm_cmd_resp_addr;
3188
3189 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
3190 -1);
3191
3192 mutex_lock(&bp->hwrm_cmd_lock);
3193 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3194 if (!rc)
3195 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx =
3196 le16_to_cpu(resp->rss_cos_lb_ctx_id);
3197 mutex_unlock(&bp->hwrm_cmd_lock);
3198
3199 return rc;
3200 }
3201
3202 static int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
3203 {
3204 unsigned int ring = 0, grp_idx;
3205 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3206 struct hwrm_vnic_cfg_input req = {0};
3207
3208 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
3209 /* Only RSS support for now TBD: COS & LB */
3210 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP |
3211 VNIC_CFG_REQ_ENABLES_RSS_RULE);
3212 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx);
3213 req.cos_rule = cpu_to_le16(0xffff);
3214 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3215 ring = 0;
3216 else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
3217 ring = vnic_id - 1;
3218
3219 grp_idx = bp->rx_ring[ring].bnapi->index;
3220 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3221 req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
3222
3223 req.lb_rule = cpu_to_le16(0xffff);
3224 req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
3225 VLAN_HLEN);
3226
3227 if (bp->flags & BNXT_FLAG_STRIP_VLAN)
3228 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
3229
3230 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3231 }
3232
3233 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
3234 {
3235 u32 rc = 0;
3236
3237 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
3238 struct hwrm_vnic_free_input req = {0};
3239
3240 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
3241 req.vnic_id =
3242 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
3243
3244 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3245 if (rc)
3246 return rc;
3247 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
3248 }
3249 return rc;
3250 }
3251
3252 static void bnxt_hwrm_vnic_free(struct bnxt *bp)
3253 {
3254 u16 i;
3255
3256 for (i = 0; i < bp->nr_vnics; i++)
3257 bnxt_hwrm_vnic_free_one(bp, i);
3258 }
3259
3260 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
3261 unsigned int start_rx_ring_idx,
3262 unsigned int nr_rings)
3263 {
3264 int rc = 0;
3265 unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
3266 struct hwrm_vnic_alloc_input req = {0};
3267 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3268
3269 /* map ring groups to this vnic */
3270 for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
3271 grp_idx = bp->rx_ring[i].bnapi->index;
3272 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
3273 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
3274 j, nr_rings);
3275 break;
3276 }
3277 bp->vnic_info[vnic_id].fw_grp_ids[j] =
3278 bp->grp_info[grp_idx].fw_grp_id;
3279 }
3280
3281 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
3282 if (vnic_id == 0)
3283 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
3284
3285 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
3286
3287 mutex_lock(&bp->hwrm_cmd_lock);
3288 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3289 if (!rc)
3290 bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id);
3291 mutex_unlock(&bp->hwrm_cmd_lock);
3292 return rc;
3293 }
3294
3295 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
3296 {
3297 u16 i;
3298 u32 rc = 0;
3299
3300 mutex_lock(&bp->hwrm_cmd_lock);
3301 for (i = 0; i < bp->rx_nr_rings; i++) {
3302 struct hwrm_ring_grp_alloc_input req = {0};
3303 struct hwrm_ring_grp_alloc_output *resp =
3304 bp->hwrm_cmd_resp_addr;
3305 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
3306
3307 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
3308
3309 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
3310 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
3311 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
3312 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
3313
3314 rc = _hwrm_send_message(bp, &req, sizeof(req),
3315 HWRM_CMD_TIMEOUT);
3316 if (rc)
3317 break;
3318
3319 bp->grp_info[grp_idx].fw_grp_id =
3320 le32_to_cpu(resp->ring_group_id);
3321 }
3322 mutex_unlock(&bp->hwrm_cmd_lock);
3323 return rc;
3324 }
3325
3326 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
3327 {
3328 u16 i;
3329 u32 rc = 0;
3330 struct hwrm_ring_grp_free_input req = {0};
3331
3332 if (!bp->grp_info)
3333 return 0;
3334
3335 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
3336
3337 mutex_lock(&bp->hwrm_cmd_lock);
3338 for (i = 0; i < bp->cp_nr_rings; i++) {
3339 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
3340 continue;
3341 req.ring_group_id =
3342 cpu_to_le32(bp->grp_info[i].fw_grp_id);
3343
3344 rc = _hwrm_send_message(bp, &req, sizeof(req),
3345 HWRM_CMD_TIMEOUT);
3346 if (rc)
3347 break;
3348 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
3349 }
3350 mutex_unlock(&bp->hwrm_cmd_lock);
3351 return rc;
3352 }
3353
3354 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
3355 struct bnxt_ring_struct *ring,
3356 u32 ring_type, u32 map_index,
3357 u32 stats_ctx_id)
3358 {
3359 int rc = 0, err = 0;
3360 struct hwrm_ring_alloc_input req = {0};
3361 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3362 u16 ring_id;
3363
3364 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
3365
3366 req.enables = 0;
3367 if (ring->nr_pages > 1) {
3368 req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map);
3369 /* Page size is in log2 units */
3370 req.page_size = BNXT_PAGE_SHIFT;
3371 req.page_tbl_depth = 1;
3372 } else {
3373 req.page_tbl_addr = cpu_to_le64(ring->dma_arr[0]);
3374 }
3375 req.fbo = 0;
3376 /* Association of ring index with doorbell index and MSIX number */
3377 req.logical_id = cpu_to_le16(map_index);
3378
3379 switch (ring_type) {
3380 case HWRM_RING_ALLOC_TX:
3381 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
3382 /* Association of transmit ring with completion ring */
3383 req.cmpl_ring_id =
3384 cpu_to_le16(bp->grp_info[map_index].cp_fw_ring_id);
3385 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
3386 req.stat_ctx_id = cpu_to_le32(stats_ctx_id);
3387 req.queue_id = cpu_to_le16(ring->queue_id);
3388 break;
3389 case HWRM_RING_ALLOC_RX:
3390 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3391 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
3392 break;
3393 case HWRM_RING_ALLOC_AGG:
3394 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3395 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
3396 break;
3397 case HWRM_RING_ALLOC_CMPL:
3398 req.ring_type = RING_ALLOC_REQ_RING_TYPE_CMPL;
3399 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
3400 if (bp->flags & BNXT_FLAG_USING_MSIX)
3401 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
3402 break;
3403 default:
3404 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
3405 ring_type);
3406 return -1;
3407 }
3408
3409 mutex_lock(&bp->hwrm_cmd_lock);
3410 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3411 err = le16_to_cpu(resp->error_code);
3412 ring_id = le16_to_cpu(resp->ring_id);
3413 mutex_unlock(&bp->hwrm_cmd_lock);
3414
3415 if (rc || err) {
3416 switch (ring_type) {
3417 case RING_FREE_REQ_RING_TYPE_CMPL:
3418 netdev_err(bp->dev, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
3419 rc, err);
3420 return -1;
3421
3422 case RING_FREE_REQ_RING_TYPE_RX:
3423 netdev_err(bp->dev, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
3424 rc, err);
3425 return -1;
3426
3427 case RING_FREE_REQ_RING_TYPE_TX:
3428 netdev_err(bp->dev, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
3429 rc, err);
3430 return -1;
3431
3432 default:
3433 netdev_err(bp->dev, "Invalid ring\n");
3434 return -1;
3435 }
3436 }
3437 ring->fw_ring_id = ring_id;
3438 return rc;
3439 }
3440
3441 static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
3442 {
3443 int i, rc = 0;
3444
3445 for (i = 0; i < bp->cp_nr_rings; i++) {
3446 struct bnxt_napi *bnapi = bp->bnapi[i];
3447 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3448 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3449
3450 cpr->cp_doorbell = bp->bar1 + i * 0x80;
3451 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL, i,
3452 INVALID_STATS_CTX_ID);
3453 if (rc)
3454 goto err_out;
3455 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
3456 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
3457 }
3458
3459 for (i = 0; i < bp->tx_nr_rings; i++) {
3460 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3461 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
3462 u32 map_idx = txr->bnapi->index;
3463 u16 fw_stats_ctx = bp->grp_info[map_idx].fw_stats_ctx;
3464
3465 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_TX,
3466 map_idx, fw_stats_ctx);
3467 if (rc)
3468 goto err_out;
3469 txr->tx_doorbell = bp->bar1 + map_idx * 0x80;
3470 }
3471
3472 for (i = 0; i < bp->rx_nr_rings; i++) {
3473 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3474 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
3475 u32 map_idx = rxr->bnapi->index;
3476
3477 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_RX,
3478 map_idx, INVALID_STATS_CTX_ID);
3479 if (rc)
3480 goto err_out;
3481 rxr->rx_doorbell = bp->bar1 + map_idx * 0x80;
3482 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
3483 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
3484 }
3485
3486 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
3487 for (i = 0; i < bp->rx_nr_rings; i++) {
3488 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3489 struct bnxt_ring_struct *ring =
3490 &rxr->rx_agg_ring_struct;
3491 u32 grp_idx = rxr->bnapi->index;
3492 u32 map_idx = grp_idx + bp->rx_nr_rings;
3493
3494 rc = hwrm_ring_alloc_send_msg(bp, ring,
3495 HWRM_RING_ALLOC_AGG,
3496 map_idx,
3497 INVALID_STATS_CTX_ID);
3498 if (rc)
3499 goto err_out;
3500
3501 rxr->rx_agg_doorbell = bp->bar1 + map_idx * 0x80;
3502 writel(DB_KEY_RX | rxr->rx_agg_prod,
3503 rxr->rx_agg_doorbell);
3504 bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
3505 }
3506 }
3507 err_out:
3508 return rc;
3509 }
3510
3511 static int hwrm_ring_free_send_msg(struct bnxt *bp,
3512 struct bnxt_ring_struct *ring,
3513 u32 ring_type, int cmpl_ring_id)
3514 {
3515 int rc;
3516 struct hwrm_ring_free_input req = {0};
3517 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
3518 u16 error_code;
3519
3520 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
3521 req.ring_type = ring_type;
3522 req.ring_id = cpu_to_le16(ring->fw_ring_id);
3523
3524 mutex_lock(&bp->hwrm_cmd_lock);
3525 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3526 error_code = le16_to_cpu(resp->error_code);
3527 mutex_unlock(&bp->hwrm_cmd_lock);
3528
3529 if (rc || error_code) {
3530 switch (ring_type) {
3531 case RING_FREE_REQ_RING_TYPE_CMPL:
3532 netdev_err(bp->dev, "hwrm_ring_free cp failed. rc:%d\n",
3533 rc);
3534 return rc;
3535 case RING_FREE_REQ_RING_TYPE_RX:
3536 netdev_err(bp->dev, "hwrm_ring_free rx failed. rc:%d\n",
3537 rc);
3538 return rc;
3539 case RING_FREE_REQ_RING_TYPE_TX:
3540 netdev_err(bp->dev, "hwrm_ring_free tx failed. rc:%d\n",
3541 rc);
3542 return rc;
3543 default:
3544 netdev_err(bp->dev, "Invalid ring\n");
3545 return -1;
3546 }
3547 }
3548 return 0;
3549 }
3550
3551 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
3552 {
3553 int i;
3554
3555 if (!bp->bnapi)
3556 return;
3557
3558 for (i = 0; i < bp->tx_nr_rings; i++) {
3559 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3560 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
3561 u32 grp_idx = txr->bnapi->index;
3562 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
3563
3564 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3565 hwrm_ring_free_send_msg(bp, ring,
3566 RING_FREE_REQ_RING_TYPE_TX,
3567 close_path ? cmpl_ring_id :
3568 INVALID_HW_RING_ID);
3569 ring->fw_ring_id = INVALID_HW_RING_ID;
3570 }
3571 }
3572
3573 for (i = 0; i < bp->rx_nr_rings; i++) {
3574 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3575 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
3576 u32 grp_idx = rxr->bnapi->index;
3577 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
3578
3579 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3580 hwrm_ring_free_send_msg(bp, ring,
3581 RING_FREE_REQ_RING_TYPE_RX,
3582 close_path ? cmpl_ring_id :
3583 INVALID_HW_RING_ID);
3584 ring->fw_ring_id = INVALID_HW_RING_ID;
3585 bp->grp_info[grp_idx].rx_fw_ring_id =
3586 INVALID_HW_RING_ID;
3587 }
3588 }
3589
3590 for (i = 0; i < bp->rx_nr_rings; i++) {
3591 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3592 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
3593 u32 grp_idx = rxr->bnapi->index;
3594 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
3595
3596 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3597 hwrm_ring_free_send_msg(bp, ring,
3598 RING_FREE_REQ_RING_TYPE_RX,
3599 close_path ? cmpl_ring_id :
3600 INVALID_HW_RING_ID);
3601 ring->fw_ring_id = INVALID_HW_RING_ID;
3602 bp->grp_info[grp_idx].agg_fw_ring_id =
3603 INVALID_HW_RING_ID;
3604 }
3605 }
3606
3607 for (i = 0; i < bp->cp_nr_rings; i++) {
3608 struct bnxt_napi *bnapi = bp->bnapi[i];
3609 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3610 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3611
3612 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3613 hwrm_ring_free_send_msg(bp, ring,
3614 RING_FREE_REQ_RING_TYPE_CMPL,
3615 INVALID_HW_RING_ID);
3616 ring->fw_ring_id = INVALID_HW_RING_ID;
3617 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
3618 }
3619 }
3620 }
3621
3622 static void bnxt_hwrm_set_coal_params(struct bnxt *bp, u32 max_bufs,
3623 u32 buf_tmrs, u16 flags,
3624 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
3625 {
3626 req->flags = cpu_to_le16(flags);
3627 req->num_cmpl_dma_aggr = cpu_to_le16((u16)max_bufs);
3628 req->num_cmpl_dma_aggr_during_int = cpu_to_le16(max_bufs >> 16);
3629 req->cmpl_aggr_dma_tmr = cpu_to_le16((u16)buf_tmrs);
3630 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(buf_tmrs >> 16);
3631 /* Minimum time between 2 interrupts set to buf_tmr x 2 */
3632 req->int_lat_tmr_min = cpu_to_le16((u16)buf_tmrs * 2);
3633 req->int_lat_tmr_max = cpu_to_le16((u16)buf_tmrs * 4);
3634 req->num_cmpl_aggr_int = cpu_to_le16((u16)max_bufs * 4);
3635 }
3636
3637 int bnxt_hwrm_set_coal(struct bnxt *bp)
3638 {
3639 int i, rc = 0;
3640 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
3641 req_tx = {0}, *req;
3642 u16 max_buf, max_buf_irq;
3643 u16 buf_tmr, buf_tmr_irq;
3644 u32 flags;
3645
3646 bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
3647 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
3648 bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
3649 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
3650
3651 /* Each rx completion (2 records) should be DMAed immediately.
3652 * DMA 1/4 of the completion buffers at a time.
3653 */
3654 max_buf = min_t(u16, bp->rx_coal_bufs / 4, 2);
3655 /* max_buf must not be zero */
3656 max_buf = clamp_t(u16, max_buf, 1, 63);
3657 max_buf_irq = clamp_t(u16, bp->rx_coal_bufs_irq, 1, 63);
3658 buf_tmr = BNXT_USEC_TO_COAL_TIMER(bp->rx_coal_ticks);
3659 /* buf timer set to 1/4 of interrupt timer */
3660 buf_tmr = max_t(u16, buf_tmr / 4, 1);
3661 buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(bp->rx_coal_ticks_irq);
3662 buf_tmr_irq = max_t(u16, buf_tmr_irq, 1);
3663
3664 flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
3665
3666 /* RING_IDLE generates more IRQs for lower latency. Enable it only
3667 * if coal_ticks is less than 25 us.
3668 */
3669 if (bp->rx_coal_ticks < 25)
3670 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
3671
3672 bnxt_hwrm_set_coal_params(bp, max_buf_irq << 16 | max_buf,
3673 buf_tmr_irq << 16 | buf_tmr, flags, &req_rx);
3674
3675 /* max_buf must not be zero */
3676 max_buf = clamp_t(u16, bp->tx_coal_bufs, 1, 63);
3677 max_buf_irq = clamp_t(u16, bp->tx_coal_bufs_irq, 1, 63);
3678 buf_tmr = BNXT_USEC_TO_COAL_TIMER(bp->tx_coal_ticks);
3679 /* buf timer set to 1/4 of interrupt timer */
3680 buf_tmr = max_t(u16, buf_tmr / 4, 1);
3681 buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(bp->tx_coal_ticks_irq);
3682 buf_tmr_irq = max_t(u16, buf_tmr_irq, 1);
3683
3684 flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
3685 bnxt_hwrm_set_coal_params(bp, max_buf_irq << 16 | max_buf,
3686 buf_tmr_irq << 16 | buf_tmr, flags, &req_tx);
3687
3688 mutex_lock(&bp->hwrm_cmd_lock);
3689 for (i = 0; i < bp->cp_nr_rings; i++) {
3690 struct bnxt_napi *bnapi = bp->bnapi[i];
3691
3692 req = &req_rx;
3693 if (!bnapi->rx_ring)
3694 req = &req_tx;
3695 req->ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id);
3696
3697 rc = _hwrm_send_message(bp, req, sizeof(*req),
3698 HWRM_CMD_TIMEOUT);
3699 if (rc)
3700 break;
3701 }
3702 mutex_unlock(&bp->hwrm_cmd_lock);
3703 return rc;
3704 }
3705
3706 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
3707 {
3708 int rc = 0, i;
3709 struct hwrm_stat_ctx_free_input req = {0};
3710
3711 if (!bp->bnapi)
3712 return 0;
3713
3714 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
3715
3716 mutex_lock(&bp->hwrm_cmd_lock);
3717 for (i = 0; i < bp->cp_nr_rings; i++) {
3718 struct bnxt_napi *bnapi = bp->bnapi[i];
3719 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3720
3721 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
3722 req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
3723
3724 rc = _hwrm_send_message(bp, &req, sizeof(req),
3725 HWRM_CMD_TIMEOUT);
3726 if (rc)
3727 break;
3728
3729 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
3730 }
3731 }
3732 mutex_unlock(&bp->hwrm_cmd_lock);
3733 return rc;
3734 }
3735
3736 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
3737 {
3738 int rc = 0, i;
3739 struct hwrm_stat_ctx_alloc_input req = {0};
3740 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3741
3742 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
3743
3744 req.update_period_ms = cpu_to_le32(1000);
3745
3746 mutex_lock(&bp->hwrm_cmd_lock);
3747 for (i = 0; i < bp->cp_nr_rings; i++) {
3748 struct bnxt_napi *bnapi = bp->bnapi[i];
3749 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3750
3751 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
3752
3753 rc = _hwrm_send_message(bp, &req, sizeof(req),
3754 HWRM_CMD_TIMEOUT);
3755 if (rc)
3756 break;
3757
3758 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
3759
3760 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
3761 }
3762 mutex_unlock(&bp->hwrm_cmd_lock);
3763 return 0;
3764 }
3765
3766 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
3767 {
3768 int rc = 0;
3769 struct hwrm_func_qcaps_input req = {0};
3770 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3771
3772 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
3773 req.fid = cpu_to_le16(0xffff);
3774
3775 mutex_lock(&bp->hwrm_cmd_lock);
3776 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3777 if (rc)
3778 goto hwrm_func_qcaps_exit;
3779
3780 if (BNXT_PF(bp)) {
3781 struct bnxt_pf_info *pf = &bp->pf;
3782
3783 pf->fw_fid = le16_to_cpu(resp->fid);
3784 pf->port_id = le16_to_cpu(resp->port_id);
3785 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
3786 memcpy(bp->dev->dev_addr, pf->mac_addr, ETH_ALEN);
3787 pf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
3788 pf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
3789 pf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
3790 pf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
3791 pf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
3792 if (!pf->max_hw_ring_grps)
3793 pf->max_hw_ring_grps = pf->max_tx_rings;
3794 pf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
3795 pf->max_vnics = le16_to_cpu(resp->max_vnics);
3796 pf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
3797 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
3798 pf->max_vfs = le16_to_cpu(resp->max_vfs);
3799 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
3800 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
3801 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
3802 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
3803 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
3804 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
3805 } else {
3806 #ifdef CONFIG_BNXT_SRIOV
3807 struct bnxt_vf_info *vf = &bp->vf;
3808
3809 vf->fw_fid = le16_to_cpu(resp->fid);
3810 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
3811 if (is_valid_ether_addr(vf->mac_addr))
3812 /* overwrite netdev dev_adr with admin VF MAC */
3813 memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
3814 else
3815 random_ether_addr(bp->dev->dev_addr);
3816
3817 vf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
3818 vf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
3819 vf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
3820 vf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
3821 vf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
3822 if (!vf->max_hw_ring_grps)
3823 vf->max_hw_ring_grps = vf->max_tx_rings;
3824 vf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
3825 vf->max_vnics = le16_to_cpu(resp->max_vnics);
3826 vf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
3827 #endif
3828 }
3829
3830 bp->tx_push_thresh = 0;
3831 if (resp->flags &
3832 cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED))
3833 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
3834
3835 hwrm_func_qcaps_exit:
3836 mutex_unlock(&bp->hwrm_cmd_lock);
3837 return rc;
3838 }
3839
3840 static int bnxt_hwrm_func_reset(struct bnxt *bp)
3841 {
3842 struct hwrm_func_reset_input req = {0};
3843
3844 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
3845 req.enables = 0;
3846
3847 return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
3848 }
3849
3850 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
3851 {
3852 int rc = 0;
3853 struct hwrm_queue_qportcfg_input req = {0};
3854 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
3855 u8 i, *qptr;
3856
3857 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
3858
3859 mutex_lock(&bp->hwrm_cmd_lock);
3860 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3861 if (rc)
3862 goto qportcfg_exit;
3863
3864 if (!resp->max_configurable_queues) {
3865 rc = -EINVAL;
3866 goto qportcfg_exit;
3867 }
3868 bp->max_tc = resp->max_configurable_queues;
3869 if (bp->max_tc > BNXT_MAX_QUEUE)
3870 bp->max_tc = BNXT_MAX_QUEUE;
3871
3872 qptr = &resp->queue_id0;
3873 for (i = 0; i < bp->max_tc; i++) {
3874 bp->q_info[i].queue_id = *qptr++;
3875 bp->q_info[i].queue_profile = *qptr++;
3876 }
3877
3878 qportcfg_exit:
3879 mutex_unlock(&bp->hwrm_cmd_lock);
3880 return rc;
3881 }
3882
3883 static int bnxt_hwrm_ver_get(struct bnxt *bp)
3884 {
3885 int rc;
3886 struct hwrm_ver_get_input req = {0};
3887 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
3888
3889 bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
3890 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
3891 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
3892 req.hwrm_intf_min = HWRM_VERSION_MINOR;
3893 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
3894 mutex_lock(&bp->hwrm_cmd_lock);
3895 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3896 if (rc)
3897 goto hwrm_ver_get_exit;
3898
3899 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
3900
3901 bp->hwrm_spec_code = resp->hwrm_intf_maj << 16 |
3902 resp->hwrm_intf_min << 8 | resp->hwrm_intf_upd;
3903 if (resp->hwrm_intf_maj < 1) {
3904 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
3905 resp->hwrm_intf_maj, resp->hwrm_intf_min,
3906 resp->hwrm_intf_upd);
3907 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
3908 }
3909 snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d/%d.%d.%d",
3910 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld,
3911 resp->hwrm_intf_maj, resp->hwrm_intf_min, resp->hwrm_intf_upd);
3912
3913 bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
3914 if (!bp->hwrm_cmd_timeout)
3915 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
3916
3917 if (resp->hwrm_intf_maj >= 1)
3918 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
3919
3920 hwrm_ver_get_exit:
3921 mutex_unlock(&bp->hwrm_cmd_lock);
3922 return rc;
3923 }
3924
3925 static int bnxt_hwrm_port_qstats(struct bnxt *bp)
3926 {
3927 int rc;
3928 struct bnxt_pf_info *pf = &bp->pf;
3929 struct hwrm_port_qstats_input req = {0};
3930
3931 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
3932 return 0;
3933
3934 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
3935 req.port_id = cpu_to_le16(pf->port_id);
3936 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map);
3937 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map);
3938 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3939 return rc;
3940 }
3941
3942 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
3943 {
3944 if (bp->vxlan_port_cnt) {
3945 bnxt_hwrm_tunnel_dst_port_free(
3946 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
3947 }
3948 bp->vxlan_port_cnt = 0;
3949 if (bp->nge_port_cnt) {
3950 bnxt_hwrm_tunnel_dst_port_free(
3951 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
3952 }
3953 bp->nge_port_cnt = 0;
3954 }
3955
3956 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
3957 {
3958 int rc, i;
3959 u32 tpa_flags = 0;
3960
3961 if (set_tpa)
3962 tpa_flags = bp->flags & BNXT_FLAG_TPA;
3963 for (i = 0; i < bp->nr_vnics; i++) {
3964 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
3965 if (rc) {
3966 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
3967 rc, i);
3968 return rc;
3969 }
3970 }
3971 return 0;
3972 }
3973
3974 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
3975 {
3976 int i;
3977
3978 for (i = 0; i < bp->nr_vnics; i++)
3979 bnxt_hwrm_vnic_set_rss(bp, i, false);
3980 }
3981
3982 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
3983 bool irq_re_init)
3984 {
3985 if (bp->vnic_info) {
3986 bnxt_hwrm_clear_vnic_filter(bp);
3987 /* clear all RSS setting before free vnic ctx */
3988 bnxt_hwrm_clear_vnic_rss(bp);
3989 bnxt_hwrm_vnic_ctx_free(bp);
3990 /* before free the vnic, undo the vnic tpa settings */
3991 if (bp->flags & BNXT_FLAG_TPA)
3992 bnxt_set_tpa(bp, false);
3993 bnxt_hwrm_vnic_free(bp);
3994 }
3995 bnxt_hwrm_ring_free(bp, close_path);
3996 bnxt_hwrm_ring_grp_free(bp);
3997 if (irq_re_init) {
3998 bnxt_hwrm_stat_ctx_free(bp);
3999 bnxt_hwrm_free_tunnel_ports(bp);
4000 }
4001 }
4002
4003 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
4004 {
4005 int rc;
4006
4007 /* allocate context for vnic */
4008 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id);
4009 if (rc) {
4010 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
4011 vnic_id, rc);
4012 goto vnic_setup_err;
4013 }
4014 bp->rsscos_nr_ctxs++;
4015
4016 /* configure default vnic, ring grp */
4017 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
4018 if (rc) {
4019 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
4020 vnic_id, rc);
4021 goto vnic_setup_err;
4022 }
4023
4024 /* Enable RSS hashing on vnic */
4025 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
4026 if (rc) {
4027 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
4028 vnic_id, rc);
4029 goto vnic_setup_err;
4030 }
4031
4032 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
4033 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
4034 if (rc) {
4035 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
4036 vnic_id, rc);
4037 }
4038 }
4039
4040 vnic_setup_err:
4041 return rc;
4042 }
4043
4044 static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
4045 {
4046 #ifdef CONFIG_RFS_ACCEL
4047 int i, rc = 0;
4048
4049 for (i = 0; i < bp->rx_nr_rings; i++) {
4050 u16 vnic_id = i + 1;
4051 u16 ring_id = i;
4052
4053 if (vnic_id >= bp->nr_vnics)
4054 break;
4055
4056 bp->vnic_info[vnic_id].flags |= BNXT_VNIC_RFS_FLAG;
4057 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
4058 if (rc) {
4059 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
4060 vnic_id, rc);
4061 break;
4062 }
4063 rc = bnxt_setup_vnic(bp, vnic_id);
4064 if (rc)
4065 break;
4066 }
4067 return rc;
4068 #else
4069 return 0;
4070 #endif
4071 }
4072
4073 static int bnxt_cfg_rx_mode(struct bnxt *);
4074
4075 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
4076 {
4077 int rc = 0;
4078
4079 if (irq_re_init) {
4080 rc = bnxt_hwrm_stat_ctx_alloc(bp);
4081 if (rc) {
4082 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
4083 rc);
4084 goto err_out;
4085 }
4086 }
4087
4088 rc = bnxt_hwrm_ring_alloc(bp);
4089 if (rc) {
4090 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
4091 goto err_out;
4092 }
4093
4094 rc = bnxt_hwrm_ring_grp_alloc(bp);
4095 if (rc) {
4096 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
4097 goto err_out;
4098 }
4099
4100 /* default vnic 0 */
4101 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, bp->rx_nr_rings);
4102 if (rc) {
4103 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
4104 goto err_out;
4105 }
4106
4107 rc = bnxt_setup_vnic(bp, 0);
4108 if (rc)
4109 goto err_out;
4110
4111 if (bp->flags & BNXT_FLAG_RFS) {
4112 rc = bnxt_alloc_rfs_vnics(bp);
4113 if (rc)
4114 goto err_out;
4115 }
4116
4117 if (bp->flags & BNXT_FLAG_TPA) {
4118 rc = bnxt_set_tpa(bp, true);
4119 if (rc)
4120 goto err_out;
4121 }
4122
4123 if (BNXT_VF(bp))
4124 bnxt_update_vf_mac(bp);
4125
4126 /* Filter for default vnic 0 */
4127 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
4128 if (rc) {
4129 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
4130 goto err_out;
4131 }
4132 bp->vnic_info[0].uc_filter_count = 1;
4133
4134 bp->vnic_info[0].rx_mask = CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
4135
4136 if ((bp->dev->flags & IFF_PROMISC) && BNXT_PF(bp))
4137 bp->vnic_info[0].rx_mask |=
4138 CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
4139
4140 rc = bnxt_cfg_rx_mode(bp);
4141 if (rc)
4142 goto err_out;
4143
4144 rc = bnxt_hwrm_set_coal(bp);
4145 if (rc)
4146 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
4147 rc);
4148
4149 return 0;
4150
4151 err_out:
4152 bnxt_hwrm_resource_free(bp, 0, true);
4153
4154 return rc;
4155 }
4156
4157 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
4158 {
4159 bnxt_hwrm_resource_free(bp, 1, irq_re_init);
4160 return 0;
4161 }
4162
4163 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
4164 {
4165 bnxt_init_rx_rings(bp);
4166 bnxt_init_tx_rings(bp);
4167 bnxt_init_ring_grps(bp, irq_re_init);
4168 bnxt_init_vnics(bp);
4169
4170 return bnxt_init_chip(bp, irq_re_init);
4171 }
4172
4173 static void bnxt_disable_int(struct bnxt *bp)
4174 {
4175 int i;
4176
4177 if (!bp->bnapi)
4178 return;
4179
4180 for (i = 0; i < bp->cp_nr_rings; i++) {
4181 struct bnxt_napi *bnapi = bp->bnapi[i];
4182 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4183
4184 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
4185 }
4186 }
4187
4188 static void bnxt_enable_int(struct bnxt *bp)
4189 {
4190 int i;
4191
4192 atomic_set(&bp->intr_sem, 0);
4193 for (i = 0; i < bp->cp_nr_rings; i++) {
4194 struct bnxt_napi *bnapi = bp->bnapi[i];
4195 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4196
4197 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
4198 }
4199 }
4200
4201 static int bnxt_set_real_num_queues(struct bnxt *bp)
4202 {
4203 int rc;
4204 struct net_device *dev = bp->dev;
4205
4206 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings);
4207 if (rc)
4208 return rc;
4209
4210 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
4211 if (rc)
4212 return rc;
4213
4214 #ifdef CONFIG_RFS_ACCEL
4215 if (bp->flags & BNXT_FLAG_RFS)
4216 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
4217 #endif
4218
4219 return rc;
4220 }
4221
4222 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
4223 bool shared)
4224 {
4225 int _rx = *rx, _tx = *tx;
4226
4227 if (shared) {
4228 *rx = min_t(int, _rx, max);
4229 *tx = min_t(int, _tx, max);
4230 } else {
4231 if (max < 2)
4232 return -ENOMEM;
4233
4234 while (_rx + _tx > max) {
4235 if (_rx > _tx && _rx > 1)
4236 _rx--;
4237 else if (_tx > 1)
4238 _tx--;
4239 }
4240 *rx = _rx;
4241 *tx = _tx;
4242 }
4243 return 0;
4244 }
4245
4246 static int bnxt_setup_msix(struct bnxt *bp)
4247 {
4248 struct msix_entry *msix_ent;
4249 struct net_device *dev = bp->dev;
4250 int i, total_vecs, rc = 0, min = 1;
4251 const int len = sizeof(bp->irq_tbl[0].name);
4252
4253 bp->flags &= ~BNXT_FLAG_USING_MSIX;
4254 total_vecs = bp->cp_nr_rings;
4255
4256 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
4257 if (!msix_ent)
4258 return -ENOMEM;
4259
4260 for (i = 0; i < total_vecs; i++) {
4261 msix_ent[i].entry = i;
4262 msix_ent[i].vector = 0;
4263 }
4264
4265 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
4266 min = 2;
4267
4268 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
4269 if (total_vecs < 0) {
4270 rc = -ENODEV;
4271 goto msix_setup_exit;
4272 }
4273
4274 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
4275 if (bp->irq_tbl) {
4276 int tcs;
4277
4278 /* Trim rings based upon num of vectors allocated */
4279 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
4280 total_vecs, min == 1);
4281 if (rc)
4282 goto msix_setup_exit;
4283
4284 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4285 tcs = netdev_get_num_tc(dev);
4286 if (tcs > 1) {
4287 bp->tx_nr_rings_per_tc = bp->tx_nr_rings / tcs;
4288 if (bp->tx_nr_rings_per_tc == 0) {
4289 netdev_reset_tc(dev);
4290 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4291 } else {
4292 int i, off, count;
4293
4294 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs;
4295 for (i = 0; i < tcs; i++) {
4296 count = bp->tx_nr_rings_per_tc;
4297 off = i * count;
4298 netdev_set_tc_queue(dev, i, count, off);
4299 }
4300 }
4301 }
4302 bp->cp_nr_rings = total_vecs;
4303
4304 for (i = 0; i < bp->cp_nr_rings; i++) {
4305 char *attr;
4306
4307 bp->irq_tbl[i].vector = msix_ent[i].vector;
4308 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
4309 attr = "TxRx";
4310 else if (i < bp->rx_nr_rings)
4311 attr = "rx";
4312 else
4313 attr = "tx";
4314
4315 snprintf(bp->irq_tbl[i].name, len,
4316 "%s-%s-%d", dev->name, attr, i);
4317 bp->irq_tbl[i].handler = bnxt_msix;
4318 }
4319 rc = bnxt_set_real_num_queues(bp);
4320 if (rc)
4321 goto msix_setup_exit;
4322 } else {
4323 rc = -ENOMEM;
4324 goto msix_setup_exit;
4325 }
4326 bp->flags |= BNXT_FLAG_USING_MSIX;
4327 kfree(msix_ent);
4328 return 0;
4329
4330 msix_setup_exit:
4331 netdev_err(bp->dev, "bnxt_setup_msix err: %x\n", rc);
4332 pci_disable_msix(bp->pdev);
4333 kfree(msix_ent);
4334 return rc;
4335 }
4336
4337 static int bnxt_setup_inta(struct bnxt *bp)
4338 {
4339 int rc;
4340 const int len = sizeof(bp->irq_tbl[0].name);
4341
4342 if (netdev_get_num_tc(bp->dev))
4343 netdev_reset_tc(bp->dev);
4344
4345 bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
4346 if (!bp->irq_tbl) {
4347 rc = -ENOMEM;
4348 return rc;
4349 }
4350 bp->rx_nr_rings = 1;
4351 bp->tx_nr_rings = 1;
4352 bp->cp_nr_rings = 1;
4353 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4354 bp->flags |= BNXT_FLAG_SHARED_RINGS;
4355 bp->irq_tbl[0].vector = bp->pdev->irq;
4356 snprintf(bp->irq_tbl[0].name, len,
4357 "%s-%s-%d", bp->dev->name, "TxRx", 0);
4358 bp->irq_tbl[0].handler = bnxt_inta;
4359 rc = bnxt_set_real_num_queues(bp);
4360 return rc;
4361 }
4362
4363 static int bnxt_setup_int_mode(struct bnxt *bp)
4364 {
4365 int rc = 0;
4366
4367 if (bp->flags & BNXT_FLAG_MSIX_CAP)
4368 rc = bnxt_setup_msix(bp);
4369
4370 if (!(bp->flags & BNXT_FLAG_USING_MSIX)) {
4371 /* fallback to INTA */
4372 rc = bnxt_setup_inta(bp);
4373 }
4374 return rc;
4375 }
4376
4377 static void bnxt_free_irq(struct bnxt *bp)
4378 {
4379 struct bnxt_irq *irq;
4380 int i;
4381
4382 #ifdef CONFIG_RFS_ACCEL
4383 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
4384 bp->dev->rx_cpu_rmap = NULL;
4385 #endif
4386 if (!bp->irq_tbl)
4387 return;
4388
4389 for (i = 0; i < bp->cp_nr_rings; i++) {
4390 irq = &bp->irq_tbl[i];
4391 if (irq->requested)
4392 free_irq(irq->vector, bp->bnapi[i]);
4393 irq->requested = 0;
4394 }
4395 if (bp->flags & BNXT_FLAG_USING_MSIX)
4396 pci_disable_msix(bp->pdev);
4397 kfree(bp->irq_tbl);
4398 bp->irq_tbl = NULL;
4399 }
4400
4401 static int bnxt_request_irq(struct bnxt *bp)
4402 {
4403 int i, j, rc = 0;
4404 unsigned long flags = 0;
4405 #ifdef CONFIG_RFS_ACCEL
4406 struct cpu_rmap *rmap = bp->dev->rx_cpu_rmap;
4407 #endif
4408
4409 if (!(bp->flags & BNXT_FLAG_USING_MSIX))
4410 flags = IRQF_SHARED;
4411
4412 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
4413 struct bnxt_irq *irq = &bp->irq_tbl[i];
4414 #ifdef CONFIG_RFS_ACCEL
4415 if (rmap && bp->bnapi[i]->rx_ring) {
4416 rc = irq_cpu_rmap_add(rmap, irq->vector);
4417 if (rc)
4418 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
4419 j);
4420 j++;
4421 }
4422 #endif
4423 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
4424 bp->bnapi[i]);
4425 if (rc)
4426 break;
4427
4428 irq->requested = 1;
4429 }
4430 return rc;
4431 }
4432
4433 static void bnxt_del_napi(struct bnxt *bp)
4434 {
4435 int i;
4436
4437 if (!bp->bnapi)
4438 return;
4439
4440 for (i = 0; i < bp->cp_nr_rings; i++) {
4441 struct bnxt_napi *bnapi = bp->bnapi[i];
4442
4443 napi_hash_del(&bnapi->napi);
4444 netif_napi_del(&bnapi->napi);
4445 }
4446 }
4447
4448 static void bnxt_init_napi(struct bnxt *bp)
4449 {
4450 int i;
4451 struct bnxt_napi *bnapi;
4452
4453 if (bp->flags & BNXT_FLAG_USING_MSIX) {
4454 for (i = 0; i < bp->cp_nr_rings; i++) {
4455 bnapi = bp->bnapi[i];
4456 netif_napi_add(bp->dev, &bnapi->napi,
4457 bnxt_poll, 64);
4458 }
4459 } else {
4460 bnapi = bp->bnapi[0];
4461 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
4462 }
4463 }
4464
4465 static void bnxt_disable_napi(struct bnxt *bp)
4466 {
4467 int i;
4468
4469 if (!bp->bnapi)
4470 return;
4471
4472 for (i = 0; i < bp->cp_nr_rings; i++) {
4473 napi_disable(&bp->bnapi[i]->napi);
4474 bnxt_disable_poll(bp->bnapi[i]);
4475 }
4476 }
4477
4478 static void bnxt_enable_napi(struct bnxt *bp)
4479 {
4480 int i;
4481
4482 for (i = 0; i < bp->cp_nr_rings; i++) {
4483 bnxt_enable_poll(bp->bnapi[i]);
4484 napi_enable(&bp->bnapi[i]->napi);
4485 }
4486 }
4487
4488 static void bnxt_tx_disable(struct bnxt *bp)
4489 {
4490 int i;
4491 struct bnxt_tx_ring_info *txr;
4492 struct netdev_queue *txq;
4493
4494 if (bp->tx_ring) {
4495 for (i = 0; i < bp->tx_nr_rings; i++) {
4496 txr = &bp->tx_ring[i];
4497 txq = netdev_get_tx_queue(bp->dev, i);
4498 __netif_tx_lock(txq, smp_processor_id());
4499 txr->dev_state = BNXT_DEV_STATE_CLOSING;
4500 __netif_tx_unlock(txq);
4501 }
4502 }
4503 /* Stop all TX queues */
4504 netif_tx_disable(bp->dev);
4505 netif_carrier_off(bp->dev);
4506 }
4507
4508 static void bnxt_tx_enable(struct bnxt *bp)
4509 {
4510 int i;
4511 struct bnxt_tx_ring_info *txr;
4512 struct netdev_queue *txq;
4513
4514 for (i = 0; i < bp->tx_nr_rings; i++) {
4515 txr = &bp->tx_ring[i];
4516 txq = netdev_get_tx_queue(bp->dev, i);
4517 txr->dev_state = 0;
4518 }
4519 netif_tx_wake_all_queues(bp->dev);
4520 if (bp->link_info.link_up)
4521 netif_carrier_on(bp->dev);
4522 }
4523
4524 static void bnxt_report_link(struct bnxt *bp)
4525 {
4526 if (bp->link_info.link_up) {
4527 const char *duplex;
4528 const char *flow_ctrl;
4529 u16 speed;
4530
4531 netif_carrier_on(bp->dev);
4532 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
4533 duplex = "full";
4534 else
4535 duplex = "half";
4536 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
4537 flow_ctrl = "ON - receive & transmit";
4538 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
4539 flow_ctrl = "ON - transmit";
4540 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
4541 flow_ctrl = "ON - receive";
4542 else
4543 flow_ctrl = "none";
4544 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
4545 netdev_info(bp->dev, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
4546 speed, duplex, flow_ctrl);
4547 if (bp->flags & BNXT_FLAG_EEE_CAP)
4548 netdev_info(bp->dev, "EEE is %s\n",
4549 bp->eee.eee_active ? "active" :
4550 "not active");
4551 } else {
4552 netif_carrier_off(bp->dev);
4553 netdev_err(bp->dev, "NIC Link is Down\n");
4554 }
4555 }
4556
4557 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
4558 {
4559 int rc = 0;
4560 struct hwrm_port_phy_qcaps_input req = {0};
4561 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4562
4563 if (bp->hwrm_spec_code < 0x10201)
4564 return 0;
4565
4566 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
4567
4568 mutex_lock(&bp->hwrm_cmd_lock);
4569 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4570 if (rc)
4571 goto hwrm_phy_qcaps_exit;
4572
4573 if (resp->eee_supported & PORT_PHY_QCAPS_RESP_EEE_SUPPORTED) {
4574 struct ethtool_eee *eee = &bp->eee;
4575 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
4576
4577 bp->flags |= BNXT_FLAG_EEE_CAP;
4578 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
4579 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
4580 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
4581 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
4582 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
4583 }
4584
4585 hwrm_phy_qcaps_exit:
4586 mutex_unlock(&bp->hwrm_cmd_lock);
4587 return rc;
4588 }
4589
4590 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
4591 {
4592 int rc = 0;
4593 struct bnxt_link_info *link_info = &bp->link_info;
4594 struct hwrm_port_phy_qcfg_input req = {0};
4595 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4596 u8 link_up = link_info->link_up;
4597
4598 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
4599
4600 mutex_lock(&bp->hwrm_cmd_lock);
4601 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4602 if (rc) {
4603 mutex_unlock(&bp->hwrm_cmd_lock);
4604 return rc;
4605 }
4606
4607 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
4608 link_info->phy_link_status = resp->link;
4609 link_info->duplex = resp->duplex;
4610 link_info->pause = resp->pause;
4611 link_info->auto_mode = resp->auto_mode;
4612 link_info->auto_pause_setting = resp->auto_pause;
4613 link_info->lp_pause = resp->link_partner_adv_pause;
4614 link_info->force_pause_setting = resp->force_pause;
4615 link_info->duplex_setting = resp->duplex;
4616 if (link_info->phy_link_status == BNXT_LINK_LINK)
4617 link_info->link_speed = le16_to_cpu(resp->link_speed);
4618 else
4619 link_info->link_speed = 0;
4620 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
4621 link_info->support_speeds = le16_to_cpu(resp->support_speeds);
4622 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
4623 link_info->lp_auto_link_speeds =
4624 le16_to_cpu(resp->link_partner_adv_speeds);
4625 link_info->preemphasis = le32_to_cpu(resp->preemphasis);
4626 link_info->phy_ver[0] = resp->phy_maj;
4627 link_info->phy_ver[1] = resp->phy_min;
4628 link_info->phy_ver[2] = resp->phy_bld;
4629 link_info->media_type = resp->media_type;
4630 link_info->phy_type = resp->phy_type;
4631 link_info->transceiver = resp->xcvr_pkg_type;
4632 link_info->phy_addr = resp->eee_config_phy_addr &
4633 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
4634
4635 if (bp->flags & BNXT_FLAG_EEE_CAP) {
4636 struct ethtool_eee *eee = &bp->eee;
4637 u16 fw_speeds;
4638
4639 eee->eee_active = 0;
4640 if (resp->eee_config_phy_addr &
4641 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
4642 eee->eee_active = 1;
4643 fw_speeds = le16_to_cpu(
4644 resp->link_partner_adv_eee_link_speed_mask);
4645 eee->lp_advertised =
4646 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
4647 }
4648
4649 /* Pull initial EEE config */
4650 if (!chng_link_state) {
4651 if (resp->eee_config_phy_addr &
4652 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
4653 eee->eee_enabled = 1;
4654
4655 fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
4656 eee->advertised =
4657 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
4658
4659 if (resp->eee_config_phy_addr &
4660 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
4661 __le32 tmr;
4662
4663 eee->tx_lpi_enabled = 1;
4664 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
4665 eee->tx_lpi_timer = le32_to_cpu(tmr) &
4666 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
4667 }
4668 }
4669 }
4670 /* TODO: need to add more logic to report VF link */
4671 if (chng_link_state) {
4672 if (link_info->phy_link_status == BNXT_LINK_LINK)
4673 link_info->link_up = 1;
4674 else
4675 link_info->link_up = 0;
4676 if (link_up != link_info->link_up)
4677 bnxt_report_link(bp);
4678 } else {
4679 /* alwasy link down if not require to update link state */
4680 link_info->link_up = 0;
4681 }
4682 mutex_unlock(&bp->hwrm_cmd_lock);
4683 return 0;
4684 }
4685
4686 static void
4687 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
4688 {
4689 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
4690 if (bp->hwrm_spec_code >= 0x10201)
4691 req->auto_pause =
4692 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
4693 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
4694 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
4695 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
4696 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
4697 req->enables |=
4698 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
4699 } else {
4700 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
4701 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
4702 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
4703 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
4704 req->enables |=
4705 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
4706 if (bp->hwrm_spec_code >= 0x10201) {
4707 req->auto_pause = req->force_pause;
4708 req->enables |= cpu_to_le32(
4709 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
4710 }
4711 }
4712 }
4713
4714 static void bnxt_hwrm_set_link_common(struct bnxt *bp,
4715 struct hwrm_port_phy_cfg_input *req)
4716 {
4717 u8 autoneg = bp->link_info.autoneg;
4718 u16 fw_link_speed = bp->link_info.req_link_speed;
4719 u32 advertising = bp->link_info.advertising;
4720
4721 if (autoneg & BNXT_AUTONEG_SPEED) {
4722 req->auto_mode |=
4723 PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
4724
4725 req->enables |= cpu_to_le32(
4726 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
4727 req->auto_link_speed_mask = cpu_to_le16(advertising);
4728
4729 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
4730 req->flags |=
4731 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
4732 } else {
4733 req->force_link_speed = cpu_to_le16(fw_link_speed);
4734 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
4735 }
4736
4737 /* tell chimp that the setting takes effect immediately */
4738 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
4739 }
4740
4741 int bnxt_hwrm_set_pause(struct bnxt *bp)
4742 {
4743 struct hwrm_port_phy_cfg_input req = {0};
4744 int rc;
4745
4746 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
4747 bnxt_hwrm_set_pause_common(bp, &req);
4748
4749 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
4750 bp->link_info.force_link_chng)
4751 bnxt_hwrm_set_link_common(bp, &req);
4752
4753 mutex_lock(&bp->hwrm_cmd_lock);
4754 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4755 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
4756 /* since changing of pause setting doesn't trigger any link
4757 * change event, the driver needs to update the current pause
4758 * result upon successfully return of the phy_cfg command
4759 */
4760 bp->link_info.pause =
4761 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
4762 bp->link_info.auto_pause_setting = 0;
4763 if (!bp->link_info.force_link_chng)
4764 bnxt_report_link(bp);
4765 }
4766 bp->link_info.force_link_chng = false;
4767 mutex_unlock(&bp->hwrm_cmd_lock);
4768 return rc;
4769 }
4770
4771 static void bnxt_hwrm_set_eee(struct bnxt *bp,
4772 struct hwrm_port_phy_cfg_input *req)
4773 {
4774 struct ethtool_eee *eee = &bp->eee;
4775
4776 if (eee->eee_enabled) {
4777 u16 eee_speeds;
4778 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
4779
4780 if (eee->tx_lpi_enabled)
4781 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
4782 else
4783 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
4784
4785 req->flags |= cpu_to_le32(flags);
4786 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
4787 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
4788 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
4789 } else {
4790 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
4791 }
4792 }
4793
4794 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
4795 {
4796 struct hwrm_port_phy_cfg_input req = {0};
4797
4798 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
4799 if (set_pause)
4800 bnxt_hwrm_set_pause_common(bp, &req);
4801
4802 bnxt_hwrm_set_link_common(bp, &req);
4803
4804 if (set_eee)
4805 bnxt_hwrm_set_eee(bp, &req);
4806 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4807 }
4808
4809 static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
4810 {
4811 struct hwrm_port_phy_cfg_input req = {0};
4812
4813 if (BNXT_VF(bp))
4814 return 0;
4815
4816 if (pci_num_vf(bp->pdev))
4817 return 0;
4818
4819 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
4820 req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DOWN);
4821 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4822 }
4823
4824 static bool bnxt_eee_config_ok(struct bnxt *bp)
4825 {
4826 struct ethtool_eee *eee = &bp->eee;
4827 struct bnxt_link_info *link_info = &bp->link_info;
4828
4829 if (!(bp->flags & BNXT_FLAG_EEE_CAP))
4830 return true;
4831
4832 if (eee->eee_enabled) {
4833 u32 advertising =
4834 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
4835
4836 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
4837 eee->eee_enabled = 0;
4838 return false;
4839 }
4840 if (eee->advertised & ~advertising) {
4841 eee->advertised = advertising & eee->supported;
4842 return false;
4843 }
4844 }
4845 return true;
4846 }
4847
4848 static int bnxt_update_phy_setting(struct bnxt *bp)
4849 {
4850 int rc;
4851 bool update_link = false;
4852 bool update_pause = false;
4853 bool update_eee = false;
4854 struct bnxt_link_info *link_info = &bp->link_info;
4855
4856 rc = bnxt_update_link(bp, true);
4857 if (rc) {
4858 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
4859 rc);
4860 return rc;
4861 }
4862 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
4863 (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
4864 link_info->req_flow_ctrl)
4865 update_pause = true;
4866 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
4867 link_info->force_pause_setting != link_info->req_flow_ctrl)
4868 update_pause = true;
4869 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
4870 if (BNXT_AUTO_MODE(link_info->auto_mode))
4871 update_link = true;
4872 if (link_info->req_link_speed != link_info->force_link_speed)
4873 update_link = true;
4874 if (link_info->req_duplex != link_info->duplex_setting)
4875 update_link = true;
4876 } else {
4877 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
4878 update_link = true;
4879 if (link_info->advertising != link_info->auto_link_speeds)
4880 update_link = true;
4881 }
4882
4883 if (!bnxt_eee_config_ok(bp))
4884 update_eee = true;
4885
4886 if (update_link)
4887 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
4888 else if (update_pause)
4889 rc = bnxt_hwrm_set_pause(bp);
4890 if (rc) {
4891 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
4892 rc);
4893 return rc;
4894 }
4895
4896 return rc;
4897 }
4898
4899 /* Common routine to pre-map certain register block to different GRC window.
4900 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
4901 * in PF and 3 windows in VF that can be customized to map in different
4902 * register blocks.
4903 */
4904 static void bnxt_preset_reg_win(struct bnxt *bp)
4905 {
4906 if (BNXT_PF(bp)) {
4907 /* CAG registers map to GRC window #4 */
4908 writel(BNXT_CAG_REG_BASE,
4909 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
4910 }
4911 }
4912
4913 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
4914 {
4915 int rc = 0;
4916
4917 bnxt_preset_reg_win(bp);
4918 netif_carrier_off(bp->dev);
4919 if (irq_re_init) {
4920 rc = bnxt_setup_int_mode(bp);
4921 if (rc) {
4922 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
4923 rc);
4924 return rc;
4925 }
4926 }
4927 if ((bp->flags & BNXT_FLAG_RFS) &&
4928 !(bp->flags & BNXT_FLAG_USING_MSIX)) {
4929 /* disable RFS if falling back to INTA */
4930 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
4931 bp->flags &= ~BNXT_FLAG_RFS;
4932 }
4933
4934 rc = bnxt_alloc_mem(bp, irq_re_init);
4935 if (rc) {
4936 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
4937 goto open_err_free_mem;
4938 }
4939
4940 if (irq_re_init) {
4941 bnxt_init_napi(bp);
4942 rc = bnxt_request_irq(bp);
4943 if (rc) {
4944 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
4945 goto open_err;
4946 }
4947 }
4948
4949 bnxt_enable_napi(bp);
4950
4951 rc = bnxt_init_nic(bp, irq_re_init);
4952 if (rc) {
4953 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
4954 goto open_err;
4955 }
4956
4957 if (link_re_init) {
4958 rc = bnxt_update_phy_setting(bp);
4959 if (rc)
4960 netdev_warn(bp->dev, "failed to update phy settings\n");
4961 }
4962
4963 if (irq_re_init) {
4964 #if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE)
4965 vxlan_get_rx_port(bp->dev);
4966 #endif
4967 if (!bnxt_hwrm_tunnel_dst_port_alloc(
4968 bp, htons(0x17c1),
4969 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE))
4970 bp->nge_port_cnt = 1;
4971 }
4972
4973 set_bit(BNXT_STATE_OPEN, &bp->state);
4974 bnxt_enable_int(bp);
4975 /* Enable TX queues */
4976 bnxt_tx_enable(bp);
4977 mod_timer(&bp->timer, jiffies + bp->current_interval);
4978 bnxt_update_link(bp, true);
4979
4980 return 0;
4981
4982 open_err:
4983 bnxt_disable_napi(bp);
4984 bnxt_del_napi(bp);
4985
4986 open_err_free_mem:
4987 bnxt_free_skbs(bp);
4988 bnxt_free_irq(bp);
4989 bnxt_free_mem(bp, true);
4990 return rc;
4991 }
4992
4993 /* rtnl_lock held */
4994 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
4995 {
4996 int rc = 0;
4997
4998 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
4999 if (rc) {
5000 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
5001 dev_close(bp->dev);
5002 }
5003 return rc;
5004 }
5005
5006 static int bnxt_open(struct net_device *dev)
5007 {
5008 struct bnxt *bp = netdev_priv(dev);
5009 int rc = 0;
5010
5011 rc = bnxt_hwrm_func_reset(bp);
5012 if (rc) {
5013 netdev_err(bp->dev, "hwrm chip reset failure rc: %x\n",
5014 rc);
5015 rc = -1;
5016 return rc;
5017 }
5018 return __bnxt_open_nic(bp, true, true);
5019 }
5020
5021 static void bnxt_disable_int_sync(struct bnxt *bp)
5022 {
5023 int i;
5024
5025 atomic_inc(&bp->intr_sem);
5026 if (!netif_running(bp->dev))
5027 return;
5028
5029 bnxt_disable_int(bp);
5030 for (i = 0; i < bp->cp_nr_rings; i++)
5031 synchronize_irq(bp->irq_tbl[i].vector);
5032 }
5033
5034 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
5035 {
5036 int rc = 0;
5037
5038 #ifdef CONFIG_BNXT_SRIOV
5039 if (bp->sriov_cfg) {
5040 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
5041 !bp->sriov_cfg,
5042 BNXT_SRIOV_CFG_WAIT_TMO);
5043 if (rc)
5044 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
5045 }
5046 #endif
5047 /* Change device state to avoid TX queue wake up's */
5048 bnxt_tx_disable(bp);
5049
5050 clear_bit(BNXT_STATE_OPEN, &bp->state);
5051 smp_mb__after_atomic();
5052 while (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state))
5053 msleep(20);
5054
5055 /* Flush rings before disabling interrupts */
5056 bnxt_shutdown_nic(bp, irq_re_init);
5057
5058 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
5059
5060 bnxt_disable_napi(bp);
5061 bnxt_disable_int_sync(bp);
5062 del_timer_sync(&bp->timer);
5063 bnxt_free_skbs(bp);
5064
5065 if (irq_re_init) {
5066 bnxt_free_irq(bp);
5067 bnxt_del_napi(bp);
5068 }
5069 bnxt_free_mem(bp, irq_re_init);
5070 return rc;
5071 }
5072
5073 static int bnxt_close(struct net_device *dev)
5074 {
5075 struct bnxt *bp = netdev_priv(dev);
5076
5077 bnxt_close_nic(bp, true, true);
5078 bnxt_hwrm_shutdown_link(bp);
5079 return 0;
5080 }
5081
5082 /* rtnl_lock held */
5083 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5084 {
5085 switch (cmd) {
5086 case SIOCGMIIPHY:
5087 /* fallthru */
5088 case SIOCGMIIREG: {
5089 if (!netif_running(dev))
5090 return -EAGAIN;
5091
5092 return 0;
5093 }
5094
5095 case SIOCSMIIREG:
5096 if (!netif_running(dev))
5097 return -EAGAIN;
5098
5099 return 0;
5100
5101 default:
5102 /* do nothing */
5103 break;
5104 }
5105 return -EOPNOTSUPP;
5106 }
5107
5108 static struct rtnl_link_stats64 *
5109 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
5110 {
5111 u32 i;
5112 struct bnxt *bp = netdev_priv(dev);
5113
5114 memset(stats, 0, sizeof(struct rtnl_link_stats64));
5115
5116 if (!bp->bnapi)
5117 return stats;
5118
5119 /* TODO check if we need to synchronize with bnxt_close path */
5120 for (i = 0; i < bp->cp_nr_rings; i++) {
5121 struct bnxt_napi *bnapi = bp->bnapi[i];
5122 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5123 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
5124
5125 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
5126 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
5127 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
5128
5129 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
5130 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
5131 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
5132
5133 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
5134 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
5135 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
5136
5137 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
5138 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
5139 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
5140
5141 stats->rx_missed_errors +=
5142 le64_to_cpu(hw_stats->rx_discard_pkts);
5143
5144 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
5145
5146 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
5147 }
5148
5149 if (bp->flags & BNXT_FLAG_PORT_STATS) {
5150 struct rx_port_stats *rx = bp->hw_rx_port_stats;
5151 struct tx_port_stats *tx = bp->hw_tx_port_stats;
5152
5153 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames);
5154 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames);
5155 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) +
5156 le64_to_cpu(rx->rx_ovrsz_frames) +
5157 le64_to_cpu(rx->rx_runt_frames);
5158 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) +
5159 le64_to_cpu(rx->rx_jbr_frames);
5160 stats->collisions = le64_to_cpu(tx->tx_total_collisions);
5161 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns);
5162 stats->tx_errors = le64_to_cpu(tx->tx_err);
5163 }
5164
5165 return stats;
5166 }
5167
5168 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
5169 {
5170 struct net_device *dev = bp->dev;
5171 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5172 struct netdev_hw_addr *ha;
5173 u8 *haddr;
5174 int mc_count = 0;
5175 bool update = false;
5176 int off = 0;
5177
5178 netdev_for_each_mc_addr(ha, dev) {
5179 if (mc_count >= BNXT_MAX_MC_ADDRS) {
5180 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
5181 vnic->mc_list_count = 0;
5182 return false;
5183 }
5184 haddr = ha->addr;
5185 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
5186 memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
5187 update = true;
5188 }
5189 off += ETH_ALEN;
5190 mc_count++;
5191 }
5192 if (mc_count)
5193 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
5194
5195 if (mc_count != vnic->mc_list_count) {
5196 vnic->mc_list_count = mc_count;
5197 update = true;
5198 }
5199 return update;
5200 }
5201
5202 static bool bnxt_uc_list_updated(struct bnxt *bp)
5203 {
5204 struct net_device *dev = bp->dev;
5205 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5206 struct netdev_hw_addr *ha;
5207 int off = 0;
5208
5209 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
5210 return true;
5211
5212 netdev_for_each_uc_addr(ha, dev) {
5213 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
5214 return true;
5215
5216 off += ETH_ALEN;
5217 }
5218 return false;
5219 }
5220
5221 static void bnxt_set_rx_mode(struct net_device *dev)
5222 {
5223 struct bnxt *bp = netdev_priv(dev);
5224 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5225 u32 mask = vnic->rx_mask;
5226 bool mc_update = false;
5227 bool uc_update;
5228
5229 if (!netif_running(dev))
5230 return;
5231
5232 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
5233 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
5234 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST);
5235
5236 /* Only allow PF to be in promiscuous mode */
5237 if ((dev->flags & IFF_PROMISC) && BNXT_PF(bp))
5238 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
5239
5240 uc_update = bnxt_uc_list_updated(bp);
5241
5242 if (dev->flags & IFF_ALLMULTI) {
5243 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
5244 vnic->mc_list_count = 0;
5245 } else {
5246 mc_update = bnxt_mc_list_updated(bp, &mask);
5247 }
5248
5249 if (mask != vnic->rx_mask || uc_update || mc_update) {
5250 vnic->rx_mask = mask;
5251
5252 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
5253 schedule_work(&bp->sp_task);
5254 }
5255 }
5256
5257 static int bnxt_cfg_rx_mode(struct bnxt *bp)
5258 {
5259 struct net_device *dev = bp->dev;
5260 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5261 struct netdev_hw_addr *ha;
5262 int i, off = 0, rc;
5263 bool uc_update;
5264
5265 netif_addr_lock_bh(dev);
5266 uc_update = bnxt_uc_list_updated(bp);
5267 netif_addr_unlock_bh(dev);
5268
5269 if (!uc_update)
5270 goto skip_uc;
5271
5272 mutex_lock(&bp->hwrm_cmd_lock);
5273 for (i = 1; i < vnic->uc_filter_count; i++) {
5274 struct hwrm_cfa_l2_filter_free_input req = {0};
5275
5276 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
5277 -1);
5278
5279 req.l2_filter_id = vnic->fw_l2_filter_id[i];
5280
5281 rc = _hwrm_send_message(bp, &req, sizeof(req),
5282 HWRM_CMD_TIMEOUT);
5283 }
5284 mutex_unlock(&bp->hwrm_cmd_lock);
5285
5286 vnic->uc_filter_count = 1;
5287
5288 netif_addr_lock_bh(dev);
5289 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
5290 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
5291 } else {
5292 netdev_for_each_uc_addr(ha, dev) {
5293 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
5294 off += ETH_ALEN;
5295 vnic->uc_filter_count++;
5296 }
5297 }
5298 netif_addr_unlock_bh(dev);
5299
5300 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
5301 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
5302 if (rc) {
5303 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
5304 rc);
5305 vnic->uc_filter_count = i;
5306 return rc;
5307 }
5308 }
5309
5310 skip_uc:
5311 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
5312 if (rc)
5313 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n",
5314 rc);
5315
5316 return rc;
5317 }
5318
5319 static bool bnxt_rfs_capable(struct bnxt *bp)
5320 {
5321 #ifdef CONFIG_RFS_ACCEL
5322 struct bnxt_pf_info *pf = &bp->pf;
5323 int vnics;
5324
5325 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_MSIX_CAP))
5326 return false;
5327
5328 vnics = 1 + bp->rx_nr_rings;
5329 if (vnics > pf->max_rsscos_ctxs || vnics > pf->max_vnics)
5330 return false;
5331
5332 return true;
5333 #else
5334 return false;
5335 #endif
5336 }
5337
5338 static netdev_features_t bnxt_fix_features(struct net_device *dev,
5339 netdev_features_t features)
5340 {
5341 struct bnxt *bp = netdev_priv(dev);
5342
5343 if (!bnxt_rfs_capable(bp))
5344 features &= ~NETIF_F_NTUPLE;
5345 return features;
5346 }
5347
5348 static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
5349 {
5350 struct bnxt *bp = netdev_priv(dev);
5351 u32 flags = bp->flags;
5352 u32 changes;
5353 int rc = 0;
5354 bool re_init = false;
5355 bool update_tpa = false;
5356
5357 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
5358 if ((features & NETIF_F_GRO) && (bp->pdev->revision > 0))
5359 flags |= BNXT_FLAG_GRO;
5360 if (features & NETIF_F_LRO)
5361 flags |= BNXT_FLAG_LRO;
5362
5363 if (features & NETIF_F_HW_VLAN_CTAG_RX)
5364 flags |= BNXT_FLAG_STRIP_VLAN;
5365
5366 if (features & NETIF_F_NTUPLE)
5367 flags |= BNXT_FLAG_RFS;
5368
5369 changes = flags ^ bp->flags;
5370 if (changes & BNXT_FLAG_TPA) {
5371 update_tpa = true;
5372 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
5373 (flags & BNXT_FLAG_TPA) == 0)
5374 re_init = true;
5375 }
5376
5377 if (changes & ~BNXT_FLAG_TPA)
5378 re_init = true;
5379
5380 if (flags != bp->flags) {
5381 u32 old_flags = bp->flags;
5382
5383 bp->flags = flags;
5384
5385 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
5386 if (update_tpa)
5387 bnxt_set_ring_params(bp);
5388 return rc;
5389 }
5390
5391 if (re_init) {
5392 bnxt_close_nic(bp, false, false);
5393 if (update_tpa)
5394 bnxt_set_ring_params(bp);
5395
5396 return bnxt_open_nic(bp, false, false);
5397 }
5398 if (update_tpa) {
5399 rc = bnxt_set_tpa(bp,
5400 (flags & BNXT_FLAG_TPA) ?
5401 true : false);
5402 if (rc)
5403 bp->flags = old_flags;
5404 }
5405 }
5406 return rc;
5407 }
5408
5409 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
5410 {
5411 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
5412 int i = bnapi->index;
5413
5414 if (!txr)
5415 return;
5416
5417 netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
5418 i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
5419 txr->tx_cons);
5420 }
5421
5422 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
5423 {
5424 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
5425 int i = bnapi->index;
5426
5427 if (!rxr)
5428 return;
5429
5430 netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
5431 i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
5432 rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
5433 rxr->rx_sw_agg_prod);
5434 }
5435
5436 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
5437 {
5438 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5439 int i = bnapi->index;
5440
5441 netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
5442 i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
5443 }
5444
5445 static void bnxt_dbg_dump_states(struct bnxt *bp)
5446 {
5447 int i;
5448 struct bnxt_napi *bnapi;
5449
5450 for (i = 0; i < bp->cp_nr_rings; i++) {
5451 bnapi = bp->bnapi[i];
5452 if (netif_msg_drv(bp)) {
5453 bnxt_dump_tx_sw_state(bnapi);
5454 bnxt_dump_rx_sw_state(bnapi);
5455 bnxt_dump_cp_sw_state(bnapi);
5456 }
5457 }
5458 }
5459
5460 static void bnxt_reset_task(struct bnxt *bp)
5461 {
5462 bnxt_dbg_dump_states(bp);
5463 if (netif_running(bp->dev)) {
5464 bnxt_close_nic(bp, false, false);
5465 bnxt_open_nic(bp, false, false);
5466 }
5467 }
5468
5469 static void bnxt_tx_timeout(struct net_device *dev)
5470 {
5471 struct bnxt *bp = netdev_priv(dev);
5472
5473 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n");
5474 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
5475 schedule_work(&bp->sp_task);
5476 }
5477
5478 #ifdef CONFIG_NET_POLL_CONTROLLER
5479 static void bnxt_poll_controller(struct net_device *dev)
5480 {
5481 struct bnxt *bp = netdev_priv(dev);
5482 int i;
5483
5484 for (i = 0; i < bp->cp_nr_rings; i++) {
5485 struct bnxt_irq *irq = &bp->irq_tbl[i];
5486
5487 disable_irq(irq->vector);
5488 irq->handler(irq->vector, bp->bnapi[i]);
5489 enable_irq(irq->vector);
5490 }
5491 }
5492 #endif
5493
5494 static void bnxt_timer(unsigned long data)
5495 {
5496 struct bnxt *bp = (struct bnxt *)data;
5497 struct net_device *dev = bp->dev;
5498
5499 if (!netif_running(dev))
5500 return;
5501
5502 if (atomic_read(&bp->intr_sem) != 0)
5503 goto bnxt_restart_timer;
5504
5505 if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS)) {
5506 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
5507 schedule_work(&bp->sp_task);
5508 }
5509 bnxt_restart_timer:
5510 mod_timer(&bp->timer, jiffies + bp->current_interval);
5511 }
5512
5513 static void bnxt_port_module_event(struct bnxt *bp)
5514 {
5515 struct bnxt_link_info *link_info = &bp->link_info;
5516 struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
5517
5518 if (bnxt_update_link(bp, true))
5519 return;
5520
5521 if (link_info->last_port_module_event != 0) {
5522 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
5523 bp->pf.port_id);
5524 if (bp->hwrm_spec_code >= 0x10201) {
5525 netdev_warn(bp->dev, "Module part number %s\n",
5526 resp->phy_vendor_partnumber);
5527 }
5528 }
5529 if (link_info->last_port_module_event == 1)
5530 netdev_warn(bp->dev, "TX is disabled\n");
5531 if (link_info->last_port_module_event == 3)
5532 netdev_warn(bp->dev, "Shutdown SFP+ module\n");
5533 }
5534
5535 static void bnxt_cfg_ntp_filters(struct bnxt *);
5536
5537 static void bnxt_sp_task(struct work_struct *work)
5538 {
5539 struct bnxt *bp = container_of(work, struct bnxt, sp_task);
5540 int rc;
5541
5542 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5543 smp_mb__after_atomic();
5544 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
5545 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5546 return;
5547 }
5548
5549 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
5550 bnxt_cfg_rx_mode(bp);
5551
5552 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
5553 bnxt_cfg_ntp_filters(bp);
5554 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
5555 rc = bnxt_update_link(bp, true);
5556 if (rc)
5557 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
5558 rc);
5559 }
5560 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
5561 bnxt_hwrm_exec_fwd_req(bp);
5562 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
5563 bnxt_hwrm_tunnel_dst_port_alloc(
5564 bp, bp->vxlan_port,
5565 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
5566 }
5567 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
5568 bnxt_hwrm_tunnel_dst_port_free(
5569 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
5570 }
5571 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event)) {
5572 /* bnxt_reset_task() calls bnxt_close_nic() which waits
5573 * for BNXT_STATE_IN_SP_TASK to clear.
5574 */
5575 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5576 rtnl_lock();
5577 bnxt_reset_task(bp);
5578 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5579 rtnl_unlock();
5580 }
5581
5582 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event))
5583 bnxt_port_module_event(bp);
5584
5585 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event))
5586 bnxt_hwrm_port_qstats(bp);
5587
5588 smp_mb__before_atomic();
5589 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5590 }
5591
5592 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
5593 {
5594 int rc;
5595 struct bnxt *bp = netdev_priv(dev);
5596
5597 SET_NETDEV_DEV(dev, &pdev->dev);
5598
5599 /* enable device (incl. PCI PM wakeup), and bus-mastering */
5600 rc = pci_enable_device(pdev);
5601 if (rc) {
5602 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
5603 goto init_err;
5604 }
5605
5606 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
5607 dev_err(&pdev->dev,
5608 "Cannot find PCI device base address, aborting\n");
5609 rc = -ENODEV;
5610 goto init_err_disable;
5611 }
5612
5613 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
5614 if (rc) {
5615 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
5616 goto init_err_disable;
5617 }
5618
5619 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
5620 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
5621 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
5622 goto init_err_disable;
5623 }
5624
5625 pci_set_master(pdev);
5626
5627 bp->dev = dev;
5628 bp->pdev = pdev;
5629
5630 bp->bar0 = pci_ioremap_bar(pdev, 0);
5631 if (!bp->bar0) {
5632 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
5633 rc = -ENOMEM;
5634 goto init_err_release;
5635 }
5636
5637 bp->bar1 = pci_ioremap_bar(pdev, 2);
5638 if (!bp->bar1) {
5639 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
5640 rc = -ENOMEM;
5641 goto init_err_release;
5642 }
5643
5644 bp->bar2 = pci_ioremap_bar(pdev, 4);
5645 if (!bp->bar2) {
5646 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
5647 rc = -ENOMEM;
5648 goto init_err_release;
5649 }
5650
5651 pci_enable_pcie_error_reporting(pdev);
5652
5653 INIT_WORK(&bp->sp_task, bnxt_sp_task);
5654
5655 spin_lock_init(&bp->ntp_fltr_lock);
5656
5657 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
5658 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
5659
5660 /* tick values in micro seconds */
5661 bp->rx_coal_ticks = 12;
5662 bp->rx_coal_bufs = 30;
5663 bp->rx_coal_ticks_irq = 1;
5664 bp->rx_coal_bufs_irq = 2;
5665
5666 bp->tx_coal_ticks = 25;
5667 bp->tx_coal_bufs = 30;
5668 bp->tx_coal_ticks_irq = 2;
5669 bp->tx_coal_bufs_irq = 2;
5670
5671 init_timer(&bp->timer);
5672 bp->timer.data = (unsigned long)bp;
5673 bp->timer.function = bnxt_timer;
5674 bp->current_interval = BNXT_TIMER_INTERVAL;
5675
5676 clear_bit(BNXT_STATE_OPEN, &bp->state);
5677
5678 return 0;
5679
5680 init_err_release:
5681 if (bp->bar2) {
5682 pci_iounmap(pdev, bp->bar2);
5683 bp->bar2 = NULL;
5684 }
5685
5686 if (bp->bar1) {
5687 pci_iounmap(pdev, bp->bar1);
5688 bp->bar1 = NULL;
5689 }
5690
5691 if (bp->bar0) {
5692 pci_iounmap(pdev, bp->bar0);
5693 bp->bar0 = NULL;
5694 }
5695
5696 pci_release_regions(pdev);
5697
5698 init_err_disable:
5699 pci_disable_device(pdev);
5700
5701 init_err:
5702 return rc;
5703 }
5704
5705 /* rtnl_lock held */
5706 static int bnxt_change_mac_addr(struct net_device *dev, void *p)
5707 {
5708 struct sockaddr *addr = p;
5709 struct bnxt *bp = netdev_priv(dev);
5710 int rc = 0;
5711
5712 if (!is_valid_ether_addr(addr->sa_data))
5713 return -EADDRNOTAVAIL;
5714
5715 rc = bnxt_approve_mac(bp, addr->sa_data);
5716 if (rc)
5717 return rc;
5718
5719 if (ether_addr_equal(addr->sa_data, dev->dev_addr))
5720 return 0;
5721
5722 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5723 if (netif_running(dev)) {
5724 bnxt_close_nic(bp, false, false);
5725 rc = bnxt_open_nic(bp, false, false);
5726 }
5727
5728 return rc;
5729 }
5730
5731 /* rtnl_lock held */
5732 static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
5733 {
5734 struct bnxt *bp = netdev_priv(dev);
5735
5736 if (new_mtu < 60 || new_mtu > 9000)
5737 return -EINVAL;
5738
5739 if (netif_running(dev))
5740 bnxt_close_nic(bp, false, false);
5741
5742 dev->mtu = new_mtu;
5743 bnxt_set_ring_params(bp);
5744
5745 if (netif_running(dev))
5746 return bnxt_open_nic(bp, false, false);
5747
5748 return 0;
5749 }
5750
5751 static int bnxt_setup_tc(struct net_device *dev, u32 handle, __be16 proto,
5752 struct tc_to_netdev *ntc)
5753 {
5754 struct bnxt *bp = netdev_priv(dev);
5755 u8 tc;
5756
5757 if (ntc->type != TC_SETUP_MQPRIO)
5758 return -EINVAL;
5759
5760 tc = ntc->tc;
5761
5762 if (tc > bp->max_tc) {
5763 netdev_err(dev, "too many traffic classes requested: %d Max supported is %d\n",
5764 tc, bp->max_tc);
5765 return -EINVAL;
5766 }
5767
5768 if (netdev_get_num_tc(dev) == tc)
5769 return 0;
5770
5771 if (tc) {
5772 int max_rx_rings, max_tx_rings, rc;
5773 bool sh = false;
5774
5775 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
5776 sh = true;
5777
5778 rc = bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, sh);
5779 if (rc || bp->tx_nr_rings_per_tc * tc > max_tx_rings)
5780 return -ENOMEM;
5781 }
5782
5783 /* Needs to close the device and do hw resource re-allocations */
5784 if (netif_running(bp->dev))
5785 bnxt_close_nic(bp, true, false);
5786
5787 if (tc) {
5788 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
5789 netdev_set_num_tc(dev, tc);
5790 } else {
5791 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
5792 netdev_reset_tc(dev);
5793 }
5794 bp->cp_nr_rings = max_t(int, bp->tx_nr_rings, bp->rx_nr_rings);
5795 bp->num_stat_ctxs = bp->cp_nr_rings;
5796
5797 if (netif_running(bp->dev))
5798 return bnxt_open_nic(bp, true, false);
5799
5800 return 0;
5801 }
5802
5803 #ifdef CONFIG_RFS_ACCEL
5804 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
5805 struct bnxt_ntuple_filter *f2)
5806 {
5807 struct flow_keys *keys1 = &f1->fkeys;
5808 struct flow_keys *keys2 = &f2->fkeys;
5809
5810 if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
5811 keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
5812 keys1->ports.ports == keys2->ports.ports &&
5813 keys1->basic.ip_proto == keys2->basic.ip_proto &&
5814 keys1->basic.n_proto == keys2->basic.n_proto &&
5815 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr))
5816 return true;
5817
5818 return false;
5819 }
5820
5821 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
5822 u16 rxq_index, u32 flow_id)
5823 {
5824 struct bnxt *bp = netdev_priv(dev);
5825 struct bnxt_ntuple_filter *fltr, *new_fltr;
5826 struct flow_keys *fkeys;
5827 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
5828 int rc = 0, idx, bit_id;
5829 struct hlist_head *head;
5830
5831 if (skb->encapsulation)
5832 return -EPROTONOSUPPORT;
5833
5834 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
5835 if (!new_fltr)
5836 return -ENOMEM;
5837
5838 fkeys = &new_fltr->fkeys;
5839 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
5840 rc = -EPROTONOSUPPORT;
5841 goto err_free;
5842 }
5843
5844 if ((fkeys->basic.n_proto != htons(ETH_P_IP)) ||
5845 ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
5846 (fkeys->basic.ip_proto != IPPROTO_UDP))) {
5847 rc = -EPROTONOSUPPORT;
5848 goto err_free;
5849 }
5850
5851 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
5852
5853 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
5854 head = &bp->ntp_fltr_hash_tbl[idx];
5855 rcu_read_lock();
5856 hlist_for_each_entry_rcu(fltr, head, hash) {
5857 if (bnxt_fltr_match(fltr, new_fltr)) {
5858 rcu_read_unlock();
5859 rc = 0;
5860 goto err_free;
5861 }
5862 }
5863 rcu_read_unlock();
5864
5865 spin_lock_bh(&bp->ntp_fltr_lock);
5866 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
5867 BNXT_NTP_FLTR_MAX_FLTR, 0);
5868 if (bit_id < 0) {
5869 spin_unlock_bh(&bp->ntp_fltr_lock);
5870 rc = -ENOMEM;
5871 goto err_free;
5872 }
5873
5874 new_fltr->sw_id = (u16)bit_id;
5875 new_fltr->flow_id = flow_id;
5876 new_fltr->rxq = rxq_index;
5877 hlist_add_head_rcu(&new_fltr->hash, head);
5878 bp->ntp_fltr_count++;
5879 spin_unlock_bh(&bp->ntp_fltr_lock);
5880
5881 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
5882 schedule_work(&bp->sp_task);
5883
5884 return new_fltr->sw_id;
5885
5886 err_free:
5887 kfree(new_fltr);
5888 return rc;
5889 }
5890
5891 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
5892 {
5893 int i;
5894
5895 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
5896 struct hlist_head *head;
5897 struct hlist_node *tmp;
5898 struct bnxt_ntuple_filter *fltr;
5899 int rc;
5900
5901 head = &bp->ntp_fltr_hash_tbl[i];
5902 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
5903 bool del = false;
5904
5905 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
5906 if (rps_may_expire_flow(bp->dev, fltr->rxq,
5907 fltr->flow_id,
5908 fltr->sw_id)) {
5909 bnxt_hwrm_cfa_ntuple_filter_free(bp,
5910 fltr);
5911 del = true;
5912 }
5913 } else {
5914 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
5915 fltr);
5916 if (rc)
5917 del = true;
5918 else
5919 set_bit(BNXT_FLTR_VALID, &fltr->state);
5920 }
5921
5922 if (del) {
5923 spin_lock_bh(&bp->ntp_fltr_lock);
5924 hlist_del_rcu(&fltr->hash);
5925 bp->ntp_fltr_count--;
5926 spin_unlock_bh(&bp->ntp_fltr_lock);
5927 synchronize_rcu();
5928 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
5929 kfree(fltr);
5930 }
5931 }
5932 }
5933 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
5934 netdev_info(bp->dev, "Receive PF driver unload event!");
5935 }
5936
5937 #else
5938
5939 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
5940 {
5941 }
5942
5943 #endif /* CONFIG_RFS_ACCEL */
5944
5945 static void bnxt_add_vxlan_port(struct net_device *dev, sa_family_t sa_family,
5946 __be16 port)
5947 {
5948 struct bnxt *bp = netdev_priv(dev);
5949
5950 if (!netif_running(dev))
5951 return;
5952
5953 if (sa_family != AF_INET6 && sa_family != AF_INET)
5954 return;
5955
5956 if (bp->vxlan_port_cnt && bp->vxlan_port != port)
5957 return;
5958
5959 bp->vxlan_port_cnt++;
5960 if (bp->vxlan_port_cnt == 1) {
5961 bp->vxlan_port = port;
5962 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
5963 schedule_work(&bp->sp_task);
5964 }
5965 }
5966
5967 static void bnxt_del_vxlan_port(struct net_device *dev, sa_family_t sa_family,
5968 __be16 port)
5969 {
5970 struct bnxt *bp = netdev_priv(dev);
5971
5972 if (!netif_running(dev))
5973 return;
5974
5975 if (sa_family != AF_INET6 && sa_family != AF_INET)
5976 return;
5977
5978 if (bp->vxlan_port_cnt && bp->vxlan_port == port) {
5979 bp->vxlan_port_cnt--;
5980
5981 if (bp->vxlan_port_cnt == 0) {
5982 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
5983 schedule_work(&bp->sp_task);
5984 }
5985 }
5986 }
5987
5988 static const struct net_device_ops bnxt_netdev_ops = {
5989 .ndo_open = bnxt_open,
5990 .ndo_start_xmit = bnxt_start_xmit,
5991 .ndo_stop = bnxt_close,
5992 .ndo_get_stats64 = bnxt_get_stats64,
5993 .ndo_set_rx_mode = bnxt_set_rx_mode,
5994 .ndo_do_ioctl = bnxt_ioctl,
5995 .ndo_validate_addr = eth_validate_addr,
5996 .ndo_set_mac_address = bnxt_change_mac_addr,
5997 .ndo_change_mtu = bnxt_change_mtu,
5998 .ndo_fix_features = bnxt_fix_features,
5999 .ndo_set_features = bnxt_set_features,
6000 .ndo_tx_timeout = bnxt_tx_timeout,
6001 #ifdef CONFIG_BNXT_SRIOV
6002 .ndo_get_vf_config = bnxt_get_vf_config,
6003 .ndo_set_vf_mac = bnxt_set_vf_mac,
6004 .ndo_set_vf_vlan = bnxt_set_vf_vlan,
6005 .ndo_set_vf_rate = bnxt_set_vf_bw,
6006 .ndo_set_vf_link_state = bnxt_set_vf_link_state,
6007 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk,
6008 #endif
6009 #ifdef CONFIG_NET_POLL_CONTROLLER
6010 .ndo_poll_controller = bnxt_poll_controller,
6011 #endif
6012 .ndo_setup_tc = bnxt_setup_tc,
6013 #ifdef CONFIG_RFS_ACCEL
6014 .ndo_rx_flow_steer = bnxt_rx_flow_steer,
6015 #endif
6016 .ndo_add_vxlan_port = bnxt_add_vxlan_port,
6017 .ndo_del_vxlan_port = bnxt_del_vxlan_port,
6018 #ifdef CONFIG_NET_RX_BUSY_POLL
6019 .ndo_busy_poll = bnxt_busy_poll,
6020 #endif
6021 };
6022
6023 static void bnxt_remove_one(struct pci_dev *pdev)
6024 {
6025 struct net_device *dev = pci_get_drvdata(pdev);
6026 struct bnxt *bp = netdev_priv(dev);
6027
6028 if (BNXT_PF(bp))
6029 bnxt_sriov_disable(bp);
6030
6031 pci_disable_pcie_error_reporting(pdev);
6032 unregister_netdev(dev);
6033 cancel_work_sync(&bp->sp_task);
6034 bp->sp_event = 0;
6035
6036 bnxt_hwrm_func_drv_unrgtr(bp);
6037 bnxt_free_hwrm_resources(bp);
6038 pci_iounmap(pdev, bp->bar2);
6039 pci_iounmap(pdev, bp->bar1);
6040 pci_iounmap(pdev, bp->bar0);
6041 free_netdev(dev);
6042
6043 pci_release_regions(pdev);
6044 pci_disable_device(pdev);
6045 }
6046
6047 static int bnxt_probe_phy(struct bnxt *bp)
6048 {
6049 int rc = 0;
6050 struct bnxt_link_info *link_info = &bp->link_info;
6051
6052 rc = bnxt_hwrm_phy_qcaps(bp);
6053 if (rc) {
6054 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
6055 rc);
6056 return rc;
6057 }
6058
6059 rc = bnxt_update_link(bp, false);
6060 if (rc) {
6061 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
6062 rc);
6063 return rc;
6064 }
6065
6066 /*initialize the ethool setting copy with NVM settings */
6067 if (BNXT_AUTO_MODE(link_info->auto_mode)) {
6068 link_info->autoneg = BNXT_AUTONEG_SPEED;
6069 if (bp->hwrm_spec_code >= 0x10201) {
6070 if (link_info->auto_pause_setting &
6071 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
6072 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
6073 } else {
6074 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
6075 }
6076 link_info->advertising = link_info->auto_link_speeds;
6077 } else {
6078 link_info->req_link_speed = link_info->force_link_speed;
6079 link_info->req_duplex = link_info->duplex_setting;
6080 }
6081 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
6082 link_info->req_flow_ctrl =
6083 link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
6084 else
6085 link_info->req_flow_ctrl = link_info->force_pause_setting;
6086 return rc;
6087 }
6088
6089 static int bnxt_get_max_irq(struct pci_dev *pdev)
6090 {
6091 u16 ctrl;
6092
6093 if (!pdev->msix_cap)
6094 return 1;
6095
6096 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
6097 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
6098 }
6099
6100 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
6101 int *max_cp)
6102 {
6103 int max_ring_grps = 0;
6104
6105 #ifdef CONFIG_BNXT_SRIOV
6106 if (!BNXT_PF(bp)) {
6107 *max_tx = bp->vf.max_tx_rings;
6108 *max_rx = bp->vf.max_rx_rings;
6109 *max_cp = min_t(int, bp->vf.max_irqs, bp->vf.max_cp_rings);
6110 *max_cp = min_t(int, *max_cp, bp->vf.max_stat_ctxs);
6111 max_ring_grps = bp->vf.max_hw_ring_grps;
6112 } else
6113 #endif
6114 {
6115 *max_tx = bp->pf.max_tx_rings;
6116 *max_rx = bp->pf.max_rx_rings;
6117 *max_cp = min_t(int, bp->pf.max_irqs, bp->pf.max_cp_rings);
6118 *max_cp = min_t(int, *max_cp, bp->pf.max_stat_ctxs);
6119 max_ring_grps = bp->pf.max_hw_ring_grps;
6120 }
6121
6122 if (bp->flags & BNXT_FLAG_AGG_RINGS)
6123 *max_rx >>= 1;
6124 *max_rx = min_t(int, *max_rx, max_ring_grps);
6125 }
6126
6127 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
6128 {
6129 int rx, tx, cp;
6130
6131 _bnxt_get_max_rings(bp, &rx, &tx, &cp);
6132 if (!rx || !tx || !cp)
6133 return -ENOMEM;
6134
6135 *max_rx = rx;
6136 *max_tx = tx;
6137 return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
6138 }
6139
6140 static int bnxt_set_dflt_rings(struct bnxt *bp)
6141 {
6142 int dflt_rings, max_rx_rings, max_tx_rings, rc;
6143 bool sh = true;
6144
6145 if (sh)
6146 bp->flags |= BNXT_FLAG_SHARED_RINGS;
6147 dflt_rings = netif_get_num_default_rss_queues();
6148 rc = bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, sh);
6149 if (rc)
6150 return rc;
6151 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
6152 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
6153 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
6154 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
6155 bp->tx_nr_rings + bp->rx_nr_rings;
6156 bp->num_stat_ctxs = bp->cp_nr_rings;
6157 return rc;
6158 }
6159
6160 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6161 {
6162 static int version_printed;
6163 struct net_device *dev;
6164 struct bnxt *bp;
6165 int rc, max_irqs;
6166
6167 if (version_printed++ == 0)
6168 pr_info("%s", version);
6169
6170 max_irqs = bnxt_get_max_irq(pdev);
6171 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
6172 if (!dev)
6173 return -ENOMEM;
6174
6175 bp = netdev_priv(dev);
6176
6177 if (bnxt_vf_pciid(ent->driver_data))
6178 bp->flags |= BNXT_FLAG_VF;
6179
6180 if (pdev->msix_cap)
6181 bp->flags |= BNXT_FLAG_MSIX_CAP;
6182
6183 rc = bnxt_init_board(pdev, dev);
6184 if (rc < 0)
6185 goto init_err_free;
6186
6187 dev->netdev_ops = &bnxt_netdev_ops;
6188 dev->watchdog_timeo = BNXT_TX_TIMEOUT;
6189 dev->ethtool_ops = &bnxt_ethtool_ops;
6190
6191 pci_set_drvdata(pdev, dev);
6192
6193 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
6194 NETIF_F_TSO | NETIF_F_TSO6 |
6195 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
6196 NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT |
6197 NETIF_F_RXHASH |
6198 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO;
6199
6200 dev->hw_enc_features =
6201 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
6202 NETIF_F_TSO | NETIF_F_TSO6 |
6203 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
6204 NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT;
6205 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
6206 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
6207 NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
6208 dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
6209 dev->priv_flags |= IFF_UNICAST_FLT;
6210
6211 #ifdef CONFIG_BNXT_SRIOV
6212 init_waitqueue_head(&bp->sriov_cfg_wait);
6213 #endif
6214 rc = bnxt_alloc_hwrm_resources(bp);
6215 if (rc)
6216 goto init_err;
6217
6218 mutex_init(&bp->hwrm_cmd_lock);
6219 bnxt_hwrm_ver_get(bp);
6220
6221 rc = bnxt_hwrm_func_drv_rgtr(bp);
6222 if (rc)
6223 goto init_err;
6224
6225 /* Get the MAX capabilities for this function */
6226 rc = bnxt_hwrm_func_qcaps(bp);
6227 if (rc) {
6228 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
6229 rc);
6230 rc = -1;
6231 goto init_err;
6232 }
6233
6234 rc = bnxt_hwrm_queue_qportcfg(bp);
6235 if (rc) {
6236 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
6237 rc);
6238 rc = -1;
6239 goto init_err;
6240 }
6241
6242 bnxt_set_tpa_flags(bp);
6243 bnxt_set_ring_params(bp);
6244 if (BNXT_PF(bp))
6245 bp->pf.max_irqs = max_irqs;
6246 #if defined(CONFIG_BNXT_SRIOV)
6247 else
6248 bp->vf.max_irqs = max_irqs;
6249 #endif
6250 bnxt_set_dflt_rings(bp);
6251
6252 if (BNXT_PF(bp)) {
6253 dev->hw_features |= NETIF_F_NTUPLE;
6254 if (bnxt_rfs_capable(bp)) {
6255 bp->flags |= BNXT_FLAG_RFS;
6256 dev->features |= NETIF_F_NTUPLE;
6257 }
6258 }
6259
6260 if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
6261 bp->flags |= BNXT_FLAG_STRIP_VLAN;
6262
6263 rc = bnxt_probe_phy(bp);
6264 if (rc)
6265 goto init_err;
6266
6267 rc = register_netdev(dev);
6268 if (rc)
6269 goto init_err;
6270
6271 netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
6272 board_info[ent->driver_data].name,
6273 (long)pci_resource_start(pdev, 0), dev->dev_addr);
6274
6275 return 0;
6276
6277 init_err:
6278 pci_iounmap(pdev, bp->bar0);
6279 pci_release_regions(pdev);
6280 pci_disable_device(pdev);
6281
6282 init_err_free:
6283 free_netdev(dev);
6284 return rc;
6285 }
6286
6287 /**
6288 * bnxt_io_error_detected - called when PCI error is detected
6289 * @pdev: Pointer to PCI device
6290 * @state: The current pci connection state
6291 *
6292 * This function is called after a PCI bus error affecting
6293 * this device has been detected.
6294 */
6295 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
6296 pci_channel_state_t state)
6297 {
6298 struct net_device *netdev = pci_get_drvdata(pdev);
6299
6300 netdev_info(netdev, "PCI I/O error detected\n");
6301
6302 rtnl_lock();
6303 netif_device_detach(netdev);
6304
6305 if (state == pci_channel_io_perm_failure) {
6306 rtnl_unlock();
6307 return PCI_ERS_RESULT_DISCONNECT;
6308 }
6309
6310 if (netif_running(netdev))
6311 bnxt_close(netdev);
6312
6313 pci_disable_device(pdev);
6314 rtnl_unlock();
6315
6316 /* Request a slot slot reset. */
6317 return PCI_ERS_RESULT_NEED_RESET;
6318 }
6319
6320 /**
6321 * bnxt_io_slot_reset - called after the pci bus has been reset.
6322 * @pdev: Pointer to PCI device
6323 *
6324 * Restart the card from scratch, as if from a cold-boot.
6325 * At this point, the card has exprienced a hard reset,
6326 * followed by fixups by BIOS, and has its config space
6327 * set up identically to what it was at cold boot.
6328 */
6329 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
6330 {
6331 struct net_device *netdev = pci_get_drvdata(pdev);
6332 struct bnxt *bp = netdev_priv(netdev);
6333 int err = 0;
6334 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
6335
6336 netdev_info(bp->dev, "PCI Slot Reset\n");
6337
6338 rtnl_lock();
6339
6340 if (pci_enable_device(pdev)) {
6341 dev_err(&pdev->dev,
6342 "Cannot re-enable PCI device after reset.\n");
6343 } else {
6344 pci_set_master(pdev);
6345
6346 if (netif_running(netdev))
6347 err = bnxt_open(netdev);
6348
6349 if (!err)
6350 result = PCI_ERS_RESULT_RECOVERED;
6351 }
6352
6353 if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev))
6354 dev_close(netdev);
6355
6356 rtnl_unlock();
6357
6358 err = pci_cleanup_aer_uncorrect_error_status(pdev);
6359 if (err) {
6360 dev_err(&pdev->dev,
6361 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
6362 err); /* non-fatal, continue */
6363 }
6364
6365 return PCI_ERS_RESULT_RECOVERED;
6366 }
6367
6368 /**
6369 * bnxt_io_resume - called when traffic can start flowing again.
6370 * @pdev: Pointer to PCI device
6371 *
6372 * This callback is called when the error recovery driver tells
6373 * us that its OK to resume normal operation.
6374 */
6375 static void bnxt_io_resume(struct pci_dev *pdev)
6376 {
6377 struct net_device *netdev = pci_get_drvdata(pdev);
6378
6379 rtnl_lock();
6380
6381 netif_device_attach(netdev);
6382
6383 rtnl_unlock();
6384 }
6385
6386 static const struct pci_error_handlers bnxt_err_handler = {
6387 .error_detected = bnxt_io_error_detected,
6388 .slot_reset = bnxt_io_slot_reset,
6389 .resume = bnxt_io_resume
6390 };
6391
6392 static struct pci_driver bnxt_pci_driver = {
6393 .name = DRV_MODULE_NAME,
6394 .id_table = bnxt_pci_tbl,
6395 .probe = bnxt_init_one,
6396 .remove = bnxt_remove_one,
6397 .err_handler = &bnxt_err_handler,
6398 #if defined(CONFIG_BNXT_SRIOV)
6399 .sriov_configure = bnxt_sriov_configure,
6400 #endif
6401 };
6402
6403 module_pci_driver(bnxt_pci_driver);
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