1 /* Broadcom NetXtreme-C/E network driver.
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2017 Broadcom Limited
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
11 #include <linux/module.h>
13 #include <linux/stringify.h>
14 #include <linux/kernel.h>
15 #include <linux/timer.h>
16 #include <linux/errno.h>
17 #include <linux/ioport.h>
18 #include <linux/slab.h>
19 #include <linux/vmalloc.h>
20 #include <linux/interrupt.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
23 #include <linux/etherdevice.h>
24 #include <linux/skbuff.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/bitops.h>
28 #include <linux/irq.h>
29 #include <linux/delay.h>
30 #include <asm/byteorder.h>
32 #include <linux/time.h>
33 #include <linux/mii.h>
35 #include <linux/if_vlan.h>
36 #include <linux/rtc.h>
37 #include <linux/bpf.h>
41 #include <net/checksum.h>
42 #include <net/ip6_checksum.h>
43 #include <net/udp_tunnel.h>
44 #include <linux/workqueue.h>
45 #include <linux/prefetch.h>
46 #include <linux/cache.h>
47 #include <linux/log2.h>
48 #include <linux/aer.h>
49 #include <linux/bitmap.h>
50 #include <linux/cpu_rmap.h>
55 #include "bnxt_sriov.h"
56 #include "bnxt_ethtool.h"
60 #define BNXT_TX_TIMEOUT (5 * HZ)
62 static const char version
[] =
63 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME
" v" DRV_MODULE_VERSION
"\n";
65 MODULE_LICENSE("GPL");
66 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
67 MODULE_VERSION(DRV_MODULE_VERSION
);
69 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
70 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
71 #define BNXT_RX_COPY_THRESH 256
73 #define BNXT_TX_PUSH_THRESH 164
108 /* indexed by enum above */
109 static const struct {
112 { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
113 { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
114 { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
115 { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
116 { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
117 { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
118 { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
119 { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
120 { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
121 { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
122 { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
123 { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
124 { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
125 { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
126 { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
127 { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
128 { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
129 { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
130 { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
131 { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
132 { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
133 { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
134 { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
135 { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
136 { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
137 { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
138 { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" },
139 { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
140 { "Broadcom NetXtreme-E Ethernet Virtual Function" },
141 { "Broadcom NetXtreme-C Ethernet Virtual Function" },
144 static const struct pci_device_id bnxt_pci_tbl
[] = {
145 { PCI_VDEVICE(BROADCOM
, 0x16c0), .driver_data
= BCM57417_NPAR
},
146 { PCI_VDEVICE(BROADCOM
, 0x16c8), .driver_data
= BCM57301
},
147 { PCI_VDEVICE(BROADCOM
, 0x16c9), .driver_data
= BCM57302
},
148 { PCI_VDEVICE(BROADCOM
, 0x16ca), .driver_data
= BCM57304
},
149 { PCI_VDEVICE(BROADCOM
, 0x16cc), .driver_data
= BCM57417_NPAR
},
150 { PCI_VDEVICE(BROADCOM
, 0x16cd), .driver_data
= BCM58700
},
151 { PCI_VDEVICE(BROADCOM
, 0x16ce), .driver_data
= BCM57311
},
152 { PCI_VDEVICE(BROADCOM
, 0x16cf), .driver_data
= BCM57312
},
153 { PCI_VDEVICE(BROADCOM
, 0x16d0), .driver_data
= BCM57402
},
154 { PCI_VDEVICE(BROADCOM
, 0x16d1), .driver_data
= BCM57404
},
155 { PCI_VDEVICE(BROADCOM
, 0x16d2), .driver_data
= BCM57406
},
156 { PCI_VDEVICE(BROADCOM
, 0x16d4), .driver_data
= BCM57402_NPAR
},
157 { PCI_VDEVICE(BROADCOM
, 0x16d5), .driver_data
= BCM57407
},
158 { PCI_VDEVICE(BROADCOM
, 0x16d6), .driver_data
= BCM57412
},
159 { PCI_VDEVICE(BROADCOM
, 0x16d7), .driver_data
= BCM57414
},
160 { PCI_VDEVICE(BROADCOM
, 0x16d8), .driver_data
= BCM57416
},
161 { PCI_VDEVICE(BROADCOM
, 0x16d9), .driver_data
= BCM57417
},
162 { PCI_VDEVICE(BROADCOM
, 0x16de), .driver_data
= BCM57412_NPAR
},
163 { PCI_VDEVICE(BROADCOM
, 0x16df), .driver_data
= BCM57314
},
164 { PCI_VDEVICE(BROADCOM
, 0x16e2), .driver_data
= BCM57417_SFP
},
165 { PCI_VDEVICE(BROADCOM
, 0x16e3), .driver_data
= BCM57416_SFP
},
166 { PCI_VDEVICE(BROADCOM
, 0x16e7), .driver_data
= BCM57404_NPAR
},
167 { PCI_VDEVICE(BROADCOM
, 0x16e8), .driver_data
= BCM57406_NPAR
},
168 { PCI_VDEVICE(BROADCOM
, 0x16e9), .driver_data
= BCM57407_SFP
},
169 { PCI_VDEVICE(BROADCOM
, 0x16ea), .driver_data
= BCM57407_NPAR
},
170 { PCI_VDEVICE(BROADCOM
, 0x16eb), .driver_data
= BCM57412_NPAR
},
171 { PCI_VDEVICE(BROADCOM
, 0x16ec), .driver_data
= BCM57414_NPAR
},
172 { PCI_VDEVICE(BROADCOM
, 0x16ed), .driver_data
= BCM57414_NPAR
},
173 { PCI_VDEVICE(BROADCOM
, 0x16ee), .driver_data
= BCM57416_NPAR
},
174 { PCI_VDEVICE(BROADCOM
, 0x16ef), .driver_data
= BCM57416_NPAR
},
175 { PCI_VDEVICE(BROADCOM
, 0x16f1), .driver_data
= BCM57452
},
176 { PCI_VDEVICE(BROADCOM
, 0x1614), .driver_data
= BCM57454
},
177 #ifdef CONFIG_BNXT_SRIOV
178 { PCI_VDEVICE(BROADCOM
, 0x16c1), .driver_data
= NETXTREME_E_VF
},
179 { PCI_VDEVICE(BROADCOM
, 0x16cb), .driver_data
= NETXTREME_C_VF
},
180 { PCI_VDEVICE(BROADCOM
, 0x16d3), .driver_data
= NETXTREME_E_VF
},
181 { PCI_VDEVICE(BROADCOM
, 0x16dc), .driver_data
= NETXTREME_E_VF
},
182 { PCI_VDEVICE(BROADCOM
, 0x16e1), .driver_data
= NETXTREME_C_VF
},
183 { PCI_VDEVICE(BROADCOM
, 0x16e5), .driver_data
= NETXTREME_C_VF
},
188 MODULE_DEVICE_TABLE(pci
, bnxt_pci_tbl
);
190 static const u16 bnxt_vf_req_snif
[] = {
193 HWRM_CFA_L2_FILTER_ALLOC
,
196 static const u16 bnxt_async_events_arr
[] = {
197 ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE
,
198 ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD
,
199 ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED
,
200 ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE
,
201 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE
,
204 static bool bnxt_vf_pciid(enum board_idx idx
)
206 return (idx
== NETXTREME_C_VF
|| idx
== NETXTREME_E_VF
);
209 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
210 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
211 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
213 #define BNXT_CP_DB_REARM(db, raw_cons) \
214 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
216 #define BNXT_CP_DB(db, raw_cons) \
217 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
219 #define BNXT_CP_DB_IRQ_DIS(db) \
220 writel(DB_CP_IRQ_DIS_FLAGS, db)
222 const u16 bnxt_lhint_arr
[] = {
223 TX_BD_FLAGS_LHINT_512_AND_SMALLER
,
224 TX_BD_FLAGS_LHINT_512_TO_1023
,
225 TX_BD_FLAGS_LHINT_1024_TO_2047
,
226 TX_BD_FLAGS_LHINT_1024_TO_2047
,
227 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
228 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
229 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
230 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
231 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
232 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
233 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
234 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
235 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
236 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
237 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
238 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
239 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
240 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
241 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
244 static netdev_tx_t
bnxt_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
246 struct bnxt
*bp
= netdev_priv(dev
);
248 struct tx_bd_ext
*txbd1
;
249 struct netdev_queue
*txq
;
252 unsigned int length
, pad
= 0;
253 u32 len
, free_size
, vlan_tag_flags
, cfa_action
, flags
;
255 struct pci_dev
*pdev
= bp
->pdev
;
256 struct bnxt_tx_ring_info
*txr
;
257 struct bnxt_sw_tx_bd
*tx_buf
;
259 i
= skb_get_queue_mapping(skb
);
260 if (unlikely(i
>= bp
->tx_nr_rings
)) {
261 dev_kfree_skb_any(skb
);
265 txq
= netdev_get_tx_queue(dev
, i
);
266 txr
= &bp
->tx_ring
[bp
->tx_ring_map
[i
]];
269 free_size
= bnxt_tx_avail(bp
, txr
);
270 if (unlikely(free_size
< skb_shinfo(skb
)->nr_frags
+ 2)) {
271 netif_tx_stop_queue(txq
);
272 return NETDEV_TX_BUSY
;
276 len
= skb_headlen(skb
);
277 last_frag
= skb_shinfo(skb
)->nr_frags
;
279 txbd
= &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
281 txbd
->tx_bd_opaque
= prod
;
283 tx_buf
= &txr
->tx_buf_ring
[prod
];
285 tx_buf
->nr_frags
= last_frag
;
289 if (skb_vlan_tag_present(skb
)) {
290 vlan_tag_flags
= TX_BD_CFA_META_KEY_VLAN
|
291 skb_vlan_tag_get(skb
);
292 /* Currently supports 8021Q, 8021AD vlan offloads
293 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
295 if (skb
->vlan_proto
== htons(ETH_P_8021Q
))
296 vlan_tag_flags
|= 1 << TX_BD_CFA_META_TPID_SHIFT
;
299 if (free_size
== bp
->tx_ring_size
&& length
<= bp
->tx_push_thresh
) {
300 struct tx_push_buffer
*tx_push_buf
= txr
->tx_push
;
301 struct tx_push_bd
*tx_push
= &tx_push_buf
->push_bd
;
302 struct tx_bd_ext
*tx_push1
= &tx_push
->txbd2
;
303 void *pdata
= tx_push_buf
->data
;
307 /* Set COAL_NOW to be ready quickly for the next push */
308 tx_push
->tx_bd_len_flags_type
=
309 cpu_to_le32((length
<< TX_BD_LEN_SHIFT
) |
310 TX_BD_TYPE_LONG_TX_BD
|
311 TX_BD_FLAGS_LHINT_512_AND_SMALLER
|
312 TX_BD_FLAGS_COAL_NOW
|
313 TX_BD_FLAGS_PACKET_END
|
314 (2 << TX_BD_FLAGS_BD_CNT_SHIFT
));
316 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
317 tx_push1
->tx_bd_hsize_lflags
=
318 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM
);
320 tx_push1
->tx_bd_hsize_lflags
= 0;
322 tx_push1
->tx_bd_cfa_meta
= cpu_to_le32(vlan_tag_flags
);
323 tx_push1
->tx_bd_cfa_action
= cpu_to_le32(cfa_action
);
325 end
= pdata
+ length
;
326 end
= PTR_ALIGN(end
, 8) - 1;
329 skb_copy_from_linear_data(skb
, pdata
, len
);
331 for (j
= 0; j
< last_frag
; j
++) {
332 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[j
];
335 fptr
= skb_frag_address_safe(frag
);
339 memcpy(pdata
, fptr
, skb_frag_size(frag
));
340 pdata
+= skb_frag_size(frag
);
343 txbd
->tx_bd_len_flags_type
= tx_push
->tx_bd_len_flags_type
;
344 txbd
->tx_bd_haddr
= txr
->data_mapping
;
345 prod
= NEXT_TX(prod
);
346 txbd
= &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
347 memcpy(txbd
, tx_push1
, sizeof(*txbd
));
348 prod
= NEXT_TX(prod
);
350 cpu_to_le32(DB_KEY_TX_PUSH
| DB_LONG_TX_PUSH
| prod
);
354 netdev_tx_sent_queue(txq
, skb
->len
);
355 wmb(); /* Sync is_push and byte queue before pushing data */
357 push_len
= (length
+ sizeof(*tx_push
) + 7) / 8;
359 __iowrite64_copy(txr
->tx_doorbell
, tx_push_buf
, 16);
360 __iowrite32_copy(txr
->tx_doorbell
+ 4, tx_push_buf
+ 1,
361 (push_len
- 16) << 1);
363 __iowrite64_copy(txr
->tx_doorbell
, tx_push_buf
,
371 if (length
< BNXT_MIN_PKT_SIZE
) {
372 pad
= BNXT_MIN_PKT_SIZE
- length
;
373 if (skb_pad(skb
, pad
)) {
374 /* SKB already freed. */
378 length
= BNXT_MIN_PKT_SIZE
;
381 mapping
= dma_map_single(&pdev
->dev
, skb
->data
, len
, DMA_TO_DEVICE
);
383 if (unlikely(dma_mapping_error(&pdev
->dev
, mapping
))) {
384 dev_kfree_skb_any(skb
);
389 dma_unmap_addr_set(tx_buf
, mapping
, mapping
);
390 flags
= (len
<< TX_BD_LEN_SHIFT
) | TX_BD_TYPE_LONG_TX_BD
|
391 ((last_frag
+ 2) << TX_BD_FLAGS_BD_CNT_SHIFT
);
393 txbd
->tx_bd_haddr
= cpu_to_le64(mapping
);
395 prod
= NEXT_TX(prod
);
396 txbd1
= (struct tx_bd_ext
*)
397 &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
399 txbd1
->tx_bd_hsize_lflags
= 0;
400 if (skb_is_gso(skb
)) {
403 if (skb
->encapsulation
)
404 hdr_len
= skb_inner_network_offset(skb
) +
405 skb_inner_network_header_len(skb
) +
406 inner_tcp_hdrlen(skb
);
408 hdr_len
= skb_transport_offset(skb
) +
411 txbd1
->tx_bd_hsize_lflags
= cpu_to_le32(TX_BD_FLAGS_LSO
|
413 (hdr_len
<< (TX_BD_HSIZE_SHIFT
- 1)));
414 length
= skb_shinfo(skb
)->gso_size
;
415 txbd1
->tx_bd_mss
= cpu_to_le32(length
);
417 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
418 txbd1
->tx_bd_hsize_lflags
=
419 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM
);
420 txbd1
->tx_bd_mss
= 0;
424 flags
|= bnxt_lhint_arr
[length
];
425 txbd
->tx_bd_len_flags_type
= cpu_to_le32(flags
);
427 txbd1
->tx_bd_cfa_meta
= cpu_to_le32(vlan_tag_flags
);
428 txbd1
->tx_bd_cfa_action
= cpu_to_le32(cfa_action
);
429 for (i
= 0; i
< last_frag
; i
++) {
430 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
432 prod
= NEXT_TX(prod
);
433 txbd
= &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
435 len
= skb_frag_size(frag
);
436 mapping
= skb_frag_dma_map(&pdev
->dev
, frag
, 0, len
,
439 if (unlikely(dma_mapping_error(&pdev
->dev
, mapping
)))
442 tx_buf
= &txr
->tx_buf_ring
[prod
];
443 dma_unmap_addr_set(tx_buf
, mapping
, mapping
);
445 txbd
->tx_bd_haddr
= cpu_to_le64(mapping
);
447 flags
= len
<< TX_BD_LEN_SHIFT
;
448 txbd
->tx_bd_len_flags_type
= cpu_to_le32(flags
);
452 txbd
->tx_bd_len_flags_type
=
453 cpu_to_le32(((len
+ pad
) << TX_BD_LEN_SHIFT
) | flags
|
454 TX_BD_FLAGS_PACKET_END
);
456 netdev_tx_sent_queue(txq
, skb
->len
);
458 /* Sync BD data before updating doorbell */
461 prod
= NEXT_TX(prod
);
464 writel(DB_KEY_TX
| prod
, txr
->tx_doorbell
);
465 writel(DB_KEY_TX
| prod
, txr
->tx_doorbell
);
471 if (unlikely(bnxt_tx_avail(bp
, txr
) <= MAX_SKB_FRAGS
+ 1)) {
472 netif_tx_stop_queue(txq
);
474 /* netif_tx_stop_queue() must be done before checking
475 * tx index in bnxt_tx_avail() below, because in
476 * bnxt_tx_int(), we update tx index before checking for
477 * netif_tx_queue_stopped().
480 if (bnxt_tx_avail(bp
, txr
) > bp
->tx_wake_thresh
)
481 netif_tx_wake_queue(txq
);
488 /* start back at beginning and unmap skb */
490 tx_buf
= &txr
->tx_buf_ring
[prod
];
492 dma_unmap_single(&pdev
->dev
, dma_unmap_addr(tx_buf
, mapping
),
493 skb_headlen(skb
), PCI_DMA_TODEVICE
);
494 prod
= NEXT_TX(prod
);
496 /* unmap remaining mapped pages */
497 for (i
= 0; i
< last_frag
; i
++) {
498 prod
= NEXT_TX(prod
);
499 tx_buf
= &txr
->tx_buf_ring
[prod
];
500 dma_unmap_page(&pdev
->dev
, dma_unmap_addr(tx_buf
, mapping
),
501 skb_frag_size(&skb_shinfo(skb
)->frags
[i
]),
505 dev_kfree_skb_any(skb
);
509 static void bnxt_tx_int(struct bnxt
*bp
, struct bnxt_napi
*bnapi
, int nr_pkts
)
511 struct bnxt_tx_ring_info
*txr
= bnapi
->tx_ring
;
512 struct netdev_queue
*txq
= netdev_get_tx_queue(bp
->dev
, txr
->txq_index
);
513 u16 cons
= txr
->tx_cons
;
514 struct pci_dev
*pdev
= bp
->pdev
;
516 unsigned int tx_bytes
= 0;
518 for (i
= 0; i
< nr_pkts
; i
++) {
519 struct bnxt_sw_tx_bd
*tx_buf
;
523 tx_buf
= &txr
->tx_buf_ring
[cons
];
524 cons
= NEXT_TX(cons
);
528 if (tx_buf
->is_push
) {
533 dma_unmap_single(&pdev
->dev
, dma_unmap_addr(tx_buf
, mapping
),
534 skb_headlen(skb
), PCI_DMA_TODEVICE
);
535 last
= tx_buf
->nr_frags
;
537 for (j
= 0; j
< last
; j
++) {
538 cons
= NEXT_TX(cons
);
539 tx_buf
= &txr
->tx_buf_ring
[cons
];
542 dma_unmap_addr(tx_buf
, mapping
),
543 skb_frag_size(&skb_shinfo(skb
)->frags
[j
]),
548 cons
= NEXT_TX(cons
);
550 tx_bytes
+= skb
->len
;
551 dev_kfree_skb_any(skb
);
554 netdev_tx_completed_queue(txq
, nr_pkts
, tx_bytes
);
557 /* Need to make the tx_cons update visible to bnxt_start_xmit()
558 * before checking for netif_tx_queue_stopped(). Without the
559 * memory barrier, there is a small possibility that bnxt_start_xmit()
560 * will miss it and cause the queue to be stopped forever.
564 if (unlikely(netif_tx_queue_stopped(txq
)) &&
565 (bnxt_tx_avail(bp
, txr
) > bp
->tx_wake_thresh
)) {
566 __netif_tx_lock(txq
, smp_processor_id());
567 if (netif_tx_queue_stopped(txq
) &&
568 bnxt_tx_avail(bp
, txr
) > bp
->tx_wake_thresh
&&
569 txr
->dev_state
!= BNXT_DEV_STATE_CLOSING
)
570 netif_tx_wake_queue(txq
);
571 __netif_tx_unlock(txq
);
575 static struct page
*__bnxt_alloc_rx_page(struct bnxt
*bp
, dma_addr_t
*mapping
,
578 struct device
*dev
= &bp
->pdev
->dev
;
581 page
= alloc_page(gfp
);
585 *mapping
= dma_map_page(dev
, page
, 0, PAGE_SIZE
, bp
->rx_dir
);
586 if (dma_mapping_error(dev
, *mapping
)) {
590 *mapping
+= bp
->rx_dma_offset
;
594 static inline u8
*__bnxt_alloc_rx_data(struct bnxt
*bp
, dma_addr_t
*mapping
,
598 struct pci_dev
*pdev
= bp
->pdev
;
600 data
= kmalloc(bp
->rx_buf_size
, gfp
);
604 *mapping
= dma_map_single(&pdev
->dev
, data
+ bp
->rx_dma_offset
,
605 bp
->rx_buf_use_size
, bp
->rx_dir
);
607 if (dma_mapping_error(&pdev
->dev
, *mapping
)) {
614 int bnxt_alloc_rx_data(struct bnxt
*bp
, struct bnxt_rx_ring_info
*rxr
,
617 struct rx_bd
*rxbd
= &rxr
->rx_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
618 struct bnxt_sw_rx_bd
*rx_buf
= &rxr
->rx_buf_ring
[prod
];
621 if (BNXT_RX_PAGE_MODE(bp
)) {
622 struct page
*page
= __bnxt_alloc_rx_page(bp
, &mapping
, gfp
);
628 rx_buf
->data_ptr
= page_address(page
) + bp
->rx_offset
;
630 u8
*data
= __bnxt_alloc_rx_data(bp
, &mapping
, gfp
);
636 rx_buf
->data_ptr
= data
+ bp
->rx_offset
;
638 rx_buf
->mapping
= mapping
;
640 rxbd
->rx_bd_haddr
= cpu_to_le64(mapping
);
644 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info
*rxr
, u16 cons
, void *data
)
646 u16 prod
= rxr
->rx_prod
;
647 struct bnxt_sw_rx_bd
*cons_rx_buf
, *prod_rx_buf
;
648 struct rx_bd
*cons_bd
, *prod_bd
;
650 prod_rx_buf
= &rxr
->rx_buf_ring
[prod
];
651 cons_rx_buf
= &rxr
->rx_buf_ring
[cons
];
653 prod_rx_buf
->data
= data
;
654 prod_rx_buf
->data_ptr
= cons_rx_buf
->data_ptr
;
656 prod_rx_buf
->mapping
= cons_rx_buf
->mapping
;
658 prod_bd
= &rxr
->rx_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
659 cons_bd
= &rxr
->rx_desc_ring
[RX_RING(cons
)][RX_IDX(cons
)];
661 prod_bd
->rx_bd_haddr
= cons_bd
->rx_bd_haddr
;
664 static inline u16
bnxt_find_next_agg_idx(struct bnxt_rx_ring_info
*rxr
, u16 idx
)
666 u16 next
, max
= rxr
->rx_agg_bmap_size
;
668 next
= find_next_zero_bit(rxr
->rx_agg_bmap
, max
, idx
);
670 next
= find_first_zero_bit(rxr
->rx_agg_bmap
, max
);
674 static inline int bnxt_alloc_rx_page(struct bnxt
*bp
,
675 struct bnxt_rx_ring_info
*rxr
,
679 &rxr
->rx_agg_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
680 struct bnxt_sw_rx_agg_bd
*rx_agg_buf
;
681 struct pci_dev
*pdev
= bp
->pdev
;
684 u16 sw_prod
= rxr
->rx_sw_agg_prod
;
685 unsigned int offset
= 0;
687 if (PAGE_SIZE
> BNXT_RX_PAGE_SIZE
) {
690 page
= alloc_page(gfp
);
694 rxr
->rx_page_offset
= 0;
696 offset
= rxr
->rx_page_offset
;
697 rxr
->rx_page_offset
+= BNXT_RX_PAGE_SIZE
;
698 if (rxr
->rx_page_offset
== PAGE_SIZE
)
703 page
= alloc_page(gfp
);
708 mapping
= dma_map_page(&pdev
->dev
, page
, offset
, BNXT_RX_PAGE_SIZE
,
710 if (dma_mapping_error(&pdev
->dev
, mapping
)) {
715 if (unlikely(test_bit(sw_prod
, rxr
->rx_agg_bmap
)))
716 sw_prod
= bnxt_find_next_agg_idx(rxr
, sw_prod
);
718 __set_bit(sw_prod
, rxr
->rx_agg_bmap
);
719 rx_agg_buf
= &rxr
->rx_agg_ring
[sw_prod
];
720 rxr
->rx_sw_agg_prod
= NEXT_RX_AGG(sw_prod
);
722 rx_agg_buf
->page
= page
;
723 rx_agg_buf
->offset
= offset
;
724 rx_agg_buf
->mapping
= mapping
;
725 rxbd
->rx_bd_haddr
= cpu_to_le64(mapping
);
726 rxbd
->rx_bd_opaque
= sw_prod
;
730 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi
*bnapi
, u16 cp_cons
,
733 struct bnxt
*bp
= bnapi
->bp
;
734 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
735 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
736 u16 prod
= rxr
->rx_agg_prod
;
737 u16 sw_prod
= rxr
->rx_sw_agg_prod
;
740 for (i
= 0; i
< agg_bufs
; i
++) {
742 struct rx_agg_cmp
*agg
;
743 struct bnxt_sw_rx_agg_bd
*cons_rx_buf
, *prod_rx_buf
;
744 struct rx_bd
*prod_bd
;
747 agg
= (struct rx_agg_cmp
*)
748 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
749 cons
= agg
->rx_agg_cmp_opaque
;
750 __clear_bit(cons
, rxr
->rx_agg_bmap
);
752 if (unlikely(test_bit(sw_prod
, rxr
->rx_agg_bmap
)))
753 sw_prod
= bnxt_find_next_agg_idx(rxr
, sw_prod
);
755 __set_bit(sw_prod
, rxr
->rx_agg_bmap
);
756 prod_rx_buf
= &rxr
->rx_agg_ring
[sw_prod
];
757 cons_rx_buf
= &rxr
->rx_agg_ring
[cons
];
759 /* It is possible for sw_prod to be equal to cons, so
760 * set cons_rx_buf->page to NULL first.
762 page
= cons_rx_buf
->page
;
763 cons_rx_buf
->page
= NULL
;
764 prod_rx_buf
->page
= page
;
765 prod_rx_buf
->offset
= cons_rx_buf
->offset
;
767 prod_rx_buf
->mapping
= cons_rx_buf
->mapping
;
769 prod_bd
= &rxr
->rx_agg_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
771 prod_bd
->rx_bd_haddr
= cpu_to_le64(cons_rx_buf
->mapping
);
772 prod_bd
->rx_bd_opaque
= sw_prod
;
774 prod
= NEXT_RX_AGG(prod
);
775 sw_prod
= NEXT_RX_AGG(sw_prod
);
776 cp_cons
= NEXT_CMP(cp_cons
);
778 rxr
->rx_agg_prod
= prod
;
779 rxr
->rx_sw_agg_prod
= sw_prod
;
782 static struct sk_buff
*bnxt_rx_page_skb(struct bnxt
*bp
,
783 struct bnxt_rx_ring_info
*rxr
,
784 u16 cons
, void *data
, u8
*data_ptr
,
786 unsigned int offset_and_len
)
788 unsigned int payload
= offset_and_len
>> 16;
789 unsigned int len
= offset_and_len
& 0xffff;
790 struct skb_frag_struct
*frag
;
791 struct page
*page
= data
;
792 u16 prod
= rxr
->rx_prod
;
796 err
= bnxt_alloc_rx_data(bp
, rxr
, prod
, GFP_ATOMIC
);
798 bnxt_reuse_rx_data(rxr
, cons
, data
);
801 dma_addr
-= bp
->rx_dma_offset
;
802 dma_unmap_page(&bp
->pdev
->dev
, dma_addr
, PAGE_SIZE
, bp
->rx_dir
);
804 if (unlikely(!payload
))
805 payload
= eth_get_headlen(data_ptr
, len
);
807 skb
= napi_alloc_skb(&rxr
->bnapi
->napi
, payload
);
813 off
= (void *)data_ptr
- page_address(page
);
814 skb_add_rx_frag(skb
, 0, page
, off
, len
, PAGE_SIZE
);
815 memcpy(skb
->data
- NET_IP_ALIGN
, data_ptr
- NET_IP_ALIGN
,
816 payload
+ NET_IP_ALIGN
);
818 frag
= &skb_shinfo(skb
)->frags
[0];
819 skb_frag_size_sub(frag
, payload
);
820 frag
->page_offset
+= payload
;
821 skb
->data_len
-= payload
;
822 skb
->tail
+= payload
;
827 static struct sk_buff
*bnxt_rx_skb(struct bnxt
*bp
,
828 struct bnxt_rx_ring_info
*rxr
, u16 cons
,
829 void *data
, u8
*data_ptr
,
831 unsigned int offset_and_len
)
833 u16 prod
= rxr
->rx_prod
;
837 err
= bnxt_alloc_rx_data(bp
, rxr
, prod
, GFP_ATOMIC
);
839 bnxt_reuse_rx_data(rxr
, cons
, data
);
843 skb
= build_skb(data
, 0);
844 dma_unmap_single(&bp
->pdev
->dev
, dma_addr
, bp
->rx_buf_use_size
,
851 skb_reserve(skb
, bp
->rx_offset
);
852 skb_put(skb
, offset_and_len
& 0xffff);
856 static struct sk_buff
*bnxt_rx_pages(struct bnxt
*bp
, struct bnxt_napi
*bnapi
,
857 struct sk_buff
*skb
, u16 cp_cons
,
860 struct pci_dev
*pdev
= bp
->pdev
;
861 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
862 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
863 u16 prod
= rxr
->rx_agg_prod
;
866 for (i
= 0; i
< agg_bufs
; i
++) {
868 struct rx_agg_cmp
*agg
;
869 struct bnxt_sw_rx_agg_bd
*cons_rx_buf
;
873 agg
= (struct rx_agg_cmp
*)
874 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
875 cons
= agg
->rx_agg_cmp_opaque
;
876 frag_len
= (le32_to_cpu(agg
->rx_agg_cmp_len_flags_type
) &
877 RX_AGG_CMP_LEN
) >> RX_AGG_CMP_LEN_SHIFT
;
879 cons_rx_buf
= &rxr
->rx_agg_ring
[cons
];
880 skb_fill_page_desc(skb
, i
, cons_rx_buf
->page
,
881 cons_rx_buf
->offset
, frag_len
);
882 __clear_bit(cons
, rxr
->rx_agg_bmap
);
884 /* It is possible for bnxt_alloc_rx_page() to allocate
885 * a sw_prod index that equals the cons index, so we
886 * need to clear the cons entry now.
888 mapping
= cons_rx_buf
->mapping
;
889 page
= cons_rx_buf
->page
;
890 cons_rx_buf
->page
= NULL
;
892 if (bnxt_alloc_rx_page(bp
, rxr
, prod
, GFP_ATOMIC
) != 0) {
893 struct skb_shared_info
*shinfo
;
894 unsigned int nr_frags
;
896 shinfo
= skb_shinfo(skb
);
897 nr_frags
= --shinfo
->nr_frags
;
898 __skb_frag_set_page(&shinfo
->frags
[nr_frags
], NULL
);
902 cons_rx_buf
->page
= page
;
904 /* Update prod since possibly some pages have been
907 rxr
->rx_agg_prod
= prod
;
908 bnxt_reuse_rx_agg_bufs(bnapi
, cp_cons
, agg_bufs
- i
);
912 dma_unmap_page(&pdev
->dev
, mapping
, BNXT_RX_PAGE_SIZE
,
915 skb
->data_len
+= frag_len
;
916 skb
->len
+= frag_len
;
917 skb
->truesize
+= PAGE_SIZE
;
919 prod
= NEXT_RX_AGG(prod
);
920 cp_cons
= NEXT_CMP(cp_cons
);
922 rxr
->rx_agg_prod
= prod
;
926 static int bnxt_agg_bufs_valid(struct bnxt
*bp
, struct bnxt_cp_ring_info
*cpr
,
927 u8 agg_bufs
, u32
*raw_cons
)
930 struct rx_agg_cmp
*agg
;
932 *raw_cons
= ADV_RAW_CMP(*raw_cons
, agg_bufs
);
933 last
= RING_CMP(*raw_cons
);
934 agg
= (struct rx_agg_cmp
*)
935 &cpr
->cp_desc_ring
[CP_RING(last
)][CP_IDX(last
)];
936 return RX_AGG_CMP_VALID(agg
, *raw_cons
);
939 static inline struct sk_buff
*bnxt_copy_skb(struct bnxt_napi
*bnapi
, u8
*data
,
943 struct bnxt
*bp
= bnapi
->bp
;
944 struct pci_dev
*pdev
= bp
->pdev
;
947 skb
= napi_alloc_skb(&bnapi
->napi
, len
);
951 dma_sync_single_for_cpu(&pdev
->dev
, mapping
, bp
->rx_copy_thresh
,
954 memcpy(skb
->data
- NET_IP_ALIGN
, data
- NET_IP_ALIGN
,
957 dma_sync_single_for_device(&pdev
->dev
, mapping
, bp
->rx_copy_thresh
,
964 static int bnxt_discard_rx(struct bnxt
*bp
, struct bnxt_napi
*bnapi
,
965 u32
*raw_cons
, void *cmp
)
967 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
968 struct rx_cmp
*rxcmp
= cmp
;
969 u32 tmp_raw_cons
= *raw_cons
;
970 u8 cmp_type
, agg_bufs
= 0;
972 cmp_type
= RX_CMP_TYPE(rxcmp
);
974 if (cmp_type
== CMP_TYPE_RX_L2_CMP
) {
975 agg_bufs
= (le32_to_cpu(rxcmp
->rx_cmp_misc_v1
) &
977 RX_CMP_AGG_BUFS_SHIFT
;
978 } else if (cmp_type
== CMP_TYPE_RX_L2_TPA_END_CMP
) {
979 struct rx_tpa_end_cmp
*tpa_end
= cmp
;
981 agg_bufs
= (le32_to_cpu(tpa_end
->rx_tpa_end_cmp_misc_v1
) &
982 RX_TPA_END_CMP_AGG_BUFS
) >>
983 RX_TPA_END_CMP_AGG_BUFS_SHIFT
;
987 if (!bnxt_agg_bufs_valid(bp
, cpr
, agg_bufs
, &tmp_raw_cons
))
990 *raw_cons
= tmp_raw_cons
;
994 static void bnxt_sched_reset(struct bnxt
*bp
, struct bnxt_rx_ring_info
*rxr
)
996 if (!rxr
->bnapi
->in_reset
) {
997 rxr
->bnapi
->in_reset
= true;
998 set_bit(BNXT_RESET_TASK_SP_EVENT
, &bp
->sp_event
);
999 schedule_work(&bp
->sp_task
);
1001 rxr
->rx_next_cons
= 0xffff;
1004 static void bnxt_tpa_start(struct bnxt
*bp
, struct bnxt_rx_ring_info
*rxr
,
1005 struct rx_tpa_start_cmp
*tpa_start
,
1006 struct rx_tpa_start_cmp_ext
*tpa_start1
)
1008 u8 agg_id
= TPA_START_AGG_ID(tpa_start
);
1010 struct bnxt_tpa_info
*tpa_info
;
1011 struct bnxt_sw_rx_bd
*cons_rx_buf
, *prod_rx_buf
;
1012 struct rx_bd
*prod_bd
;
1015 cons
= tpa_start
->rx_tpa_start_cmp_opaque
;
1016 prod
= rxr
->rx_prod
;
1017 cons_rx_buf
= &rxr
->rx_buf_ring
[cons
];
1018 prod_rx_buf
= &rxr
->rx_buf_ring
[prod
];
1019 tpa_info
= &rxr
->rx_tpa
[agg_id
];
1021 if (unlikely(cons
!= rxr
->rx_next_cons
)) {
1022 bnxt_sched_reset(bp
, rxr
);
1026 prod_rx_buf
->data
= tpa_info
->data
;
1027 prod_rx_buf
->data_ptr
= tpa_info
->data_ptr
;
1029 mapping
= tpa_info
->mapping
;
1030 prod_rx_buf
->mapping
= mapping
;
1032 prod_bd
= &rxr
->rx_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
1034 prod_bd
->rx_bd_haddr
= cpu_to_le64(mapping
);
1036 tpa_info
->data
= cons_rx_buf
->data
;
1037 tpa_info
->data_ptr
= cons_rx_buf
->data_ptr
;
1038 cons_rx_buf
->data
= NULL
;
1039 tpa_info
->mapping
= cons_rx_buf
->mapping
;
1042 le32_to_cpu(tpa_start
->rx_tpa_start_cmp_len_flags_type
) >>
1043 RX_TPA_START_CMP_LEN_SHIFT
;
1044 if (likely(TPA_START_HASH_VALID(tpa_start
))) {
1045 u32 hash_type
= TPA_START_HASH_TYPE(tpa_start
);
1047 tpa_info
->hash_type
= PKT_HASH_TYPE_L4
;
1048 tpa_info
->gso_type
= SKB_GSO_TCPV4
;
1049 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1051 tpa_info
->gso_type
= SKB_GSO_TCPV6
;
1052 tpa_info
->rss_hash
=
1053 le32_to_cpu(tpa_start
->rx_tpa_start_cmp_rss_hash
);
1055 tpa_info
->hash_type
= PKT_HASH_TYPE_NONE
;
1056 tpa_info
->gso_type
= 0;
1057 if (netif_msg_rx_err(bp
))
1058 netdev_warn(bp
->dev
, "TPA packet without valid hash\n");
1060 tpa_info
->flags2
= le32_to_cpu(tpa_start1
->rx_tpa_start_cmp_flags2
);
1061 tpa_info
->metadata
= le32_to_cpu(tpa_start1
->rx_tpa_start_cmp_metadata
);
1062 tpa_info
->hdr_info
= le32_to_cpu(tpa_start1
->rx_tpa_start_cmp_hdr_info
);
1064 rxr
->rx_prod
= NEXT_RX(prod
);
1065 cons
= NEXT_RX(cons
);
1066 rxr
->rx_next_cons
= NEXT_RX(cons
);
1067 cons_rx_buf
= &rxr
->rx_buf_ring
[cons
];
1069 bnxt_reuse_rx_data(rxr
, cons
, cons_rx_buf
->data
);
1070 rxr
->rx_prod
= NEXT_RX(rxr
->rx_prod
);
1071 cons_rx_buf
->data
= NULL
;
1074 static void bnxt_abort_tpa(struct bnxt
*bp
, struct bnxt_napi
*bnapi
,
1075 u16 cp_cons
, u32 agg_bufs
)
1078 bnxt_reuse_rx_agg_bufs(bnapi
, cp_cons
, agg_bufs
);
1081 static struct sk_buff
*bnxt_gro_func_5731x(struct bnxt_tpa_info
*tpa_info
,
1082 int payload_off
, int tcp_ts
,
1083 struct sk_buff
*skb
)
1088 u16 outer_ip_off
, inner_ip_off
, inner_mac_off
;
1089 u32 hdr_info
= tpa_info
->hdr_info
;
1090 bool loopback
= false;
1092 inner_ip_off
= BNXT_TPA_INNER_L3_OFF(hdr_info
);
1093 inner_mac_off
= BNXT_TPA_INNER_L2_OFF(hdr_info
);
1094 outer_ip_off
= BNXT_TPA_OUTER_L3_OFF(hdr_info
);
1096 /* If the packet is an internal loopback packet, the offsets will
1097 * have an extra 4 bytes.
1099 if (inner_mac_off
== 4) {
1101 } else if (inner_mac_off
> 4) {
1102 __be16 proto
= *((__be16
*)(skb
->data
+ inner_ip_off
-
1105 /* We only support inner iPv4/ipv6. If we don't see the
1106 * correct protocol ID, it must be a loopback packet where
1107 * the offsets are off by 4.
1109 if (proto
!= htons(ETH_P_IP
) && proto
!= htons(ETH_P_IPV6
))
1113 /* internal loopback packet, subtract all offsets by 4 */
1119 nw_off
= inner_ip_off
- ETH_HLEN
;
1120 skb_set_network_header(skb
, nw_off
);
1121 if (tpa_info
->flags2
& RX_TPA_START_CMP_FLAGS2_IP_TYPE
) {
1122 struct ipv6hdr
*iph
= ipv6_hdr(skb
);
1124 skb_set_transport_header(skb
, nw_off
+ sizeof(struct ipv6hdr
));
1125 len
= skb
->len
- skb_transport_offset(skb
);
1127 th
->check
= ~tcp_v6_check(len
, &iph
->saddr
, &iph
->daddr
, 0);
1129 struct iphdr
*iph
= ip_hdr(skb
);
1131 skb_set_transport_header(skb
, nw_off
+ sizeof(struct iphdr
));
1132 len
= skb
->len
- skb_transport_offset(skb
);
1134 th
->check
= ~tcp_v4_check(len
, iph
->saddr
, iph
->daddr
, 0);
1137 if (inner_mac_off
) { /* tunnel */
1138 struct udphdr
*uh
= NULL
;
1139 __be16 proto
= *((__be16
*)(skb
->data
+ outer_ip_off
-
1142 if (proto
== htons(ETH_P_IP
)) {
1143 struct iphdr
*iph
= (struct iphdr
*)skb
->data
;
1145 if (iph
->protocol
== IPPROTO_UDP
)
1146 uh
= (struct udphdr
*)(iph
+ 1);
1148 struct ipv6hdr
*iph
= (struct ipv6hdr
*)skb
->data
;
1150 if (iph
->nexthdr
== IPPROTO_UDP
)
1151 uh
= (struct udphdr
*)(iph
+ 1);
1155 skb_shinfo(skb
)->gso_type
|=
1156 SKB_GSO_UDP_TUNNEL_CSUM
;
1158 skb_shinfo(skb
)->gso_type
|= SKB_GSO_UDP_TUNNEL
;
1165 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
1166 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1168 static struct sk_buff
*bnxt_gro_func_5730x(struct bnxt_tpa_info
*tpa_info
,
1169 int payload_off
, int tcp_ts
,
1170 struct sk_buff
*skb
)
1174 int len
, nw_off
, tcp_opt_len
= 0;
1179 if (tpa_info
->gso_type
== SKB_GSO_TCPV4
) {
1182 nw_off
= payload_off
- BNXT_IPV4_HDR_SIZE
- tcp_opt_len
-
1184 skb_set_network_header(skb
, nw_off
);
1186 skb_set_transport_header(skb
, nw_off
+ sizeof(struct iphdr
));
1187 len
= skb
->len
- skb_transport_offset(skb
);
1189 th
->check
= ~tcp_v4_check(len
, iph
->saddr
, iph
->daddr
, 0);
1190 } else if (tpa_info
->gso_type
== SKB_GSO_TCPV6
) {
1191 struct ipv6hdr
*iph
;
1193 nw_off
= payload_off
- BNXT_IPV6_HDR_SIZE
- tcp_opt_len
-
1195 skb_set_network_header(skb
, nw_off
);
1196 iph
= ipv6_hdr(skb
);
1197 skb_set_transport_header(skb
, nw_off
+ sizeof(struct ipv6hdr
));
1198 len
= skb
->len
- skb_transport_offset(skb
);
1200 th
->check
= ~tcp_v6_check(len
, &iph
->saddr
, &iph
->daddr
, 0);
1202 dev_kfree_skb_any(skb
);
1206 if (nw_off
) { /* tunnel */
1207 struct udphdr
*uh
= NULL
;
1209 if (skb
->protocol
== htons(ETH_P_IP
)) {
1210 struct iphdr
*iph
= (struct iphdr
*)skb
->data
;
1212 if (iph
->protocol
== IPPROTO_UDP
)
1213 uh
= (struct udphdr
*)(iph
+ 1);
1215 struct ipv6hdr
*iph
= (struct ipv6hdr
*)skb
->data
;
1217 if (iph
->nexthdr
== IPPROTO_UDP
)
1218 uh
= (struct udphdr
*)(iph
+ 1);
1222 skb_shinfo(skb
)->gso_type
|=
1223 SKB_GSO_UDP_TUNNEL_CSUM
;
1225 skb_shinfo(skb
)->gso_type
|= SKB_GSO_UDP_TUNNEL
;
1232 static inline struct sk_buff
*bnxt_gro_skb(struct bnxt
*bp
,
1233 struct bnxt_tpa_info
*tpa_info
,
1234 struct rx_tpa_end_cmp
*tpa_end
,
1235 struct rx_tpa_end_cmp_ext
*tpa_end1
,
1236 struct sk_buff
*skb
)
1242 segs
= TPA_END_TPA_SEGS(tpa_end
);
1246 NAPI_GRO_CB(skb
)->count
= segs
;
1247 skb_shinfo(skb
)->gso_size
=
1248 le32_to_cpu(tpa_end1
->rx_tpa_end_cmp_seg_len
);
1249 skb_shinfo(skb
)->gso_type
= tpa_info
->gso_type
;
1250 payload_off
= (le32_to_cpu(tpa_end
->rx_tpa_end_cmp_misc_v1
) &
1251 RX_TPA_END_CMP_PAYLOAD_OFFSET
) >>
1252 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT
;
1253 skb
= bp
->gro_func(tpa_info
, payload_off
, TPA_END_GRO_TS(tpa_end
), skb
);
1255 tcp_gro_complete(skb
);
1260 static inline struct sk_buff
*bnxt_tpa_end(struct bnxt
*bp
,
1261 struct bnxt_napi
*bnapi
,
1263 struct rx_tpa_end_cmp
*tpa_end
,
1264 struct rx_tpa_end_cmp_ext
*tpa_end1
,
1267 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1268 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
1269 u8 agg_id
= TPA_END_AGG_ID(tpa_end
);
1270 u8
*data_ptr
, agg_bufs
;
1271 u16 cp_cons
= RING_CMP(*raw_cons
);
1273 struct bnxt_tpa_info
*tpa_info
;
1275 struct sk_buff
*skb
;
1278 if (unlikely(bnapi
->in_reset
)) {
1279 int rc
= bnxt_discard_rx(bp
, bnapi
, raw_cons
, tpa_end
);
1282 return ERR_PTR(-EBUSY
);
1286 tpa_info
= &rxr
->rx_tpa
[agg_id
];
1287 data
= tpa_info
->data
;
1288 data_ptr
= tpa_info
->data_ptr
;
1290 len
= tpa_info
->len
;
1291 mapping
= tpa_info
->mapping
;
1293 agg_bufs
= (le32_to_cpu(tpa_end
->rx_tpa_end_cmp_misc_v1
) &
1294 RX_TPA_END_CMP_AGG_BUFS
) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT
;
1297 if (!bnxt_agg_bufs_valid(bp
, cpr
, agg_bufs
, raw_cons
))
1298 return ERR_PTR(-EBUSY
);
1300 *event
|= BNXT_AGG_EVENT
;
1301 cp_cons
= NEXT_CMP(cp_cons
);
1304 if (unlikely(agg_bufs
> MAX_SKB_FRAGS
)) {
1305 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
1306 netdev_warn(bp
->dev
, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1307 agg_bufs
, (int)MAX_SKB_FRAGS
);
1311 if (len
<= bp
->rx_copy_thresh
) {
1312 skb
= bnxt_copy_skb(bnapi
, data_ptr
, len
, mapping
);
1314 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
1319 dma_addr_t new_mapping
;
1321 new_data
= __bnxt_alloc_rx_data(bp
, &new_mapping
, GFP_ATOMIC
);
1323 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
1327 tpa_info
->data
= new_data
;
1328 tpa_info
->data_ptr
= new_data
+ bp
->rx_offset
;
1329 tpa_info
->mapping
= new_mapping
;
1331 skb
= build_skb(data
, 0);
1332 dma_unmap_single(&bp
->pdev
->dev
, mapping
, bp
->rx_buf_use_size
,
1337 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
1340 skb_reserve(skb
, bp
->rx_offset
);
1345 skb
= bnxt_rx_pages(bp
, bnapi
, skb
, cp_cons
, agg_bufs
);
1347 /* Page reuse already handled by bnxt_rx_pages(). */
1351 skb
->protocol
= eth_type_trans(skb
, bp
->dev
);
1353 if (tpa_info
->hash_type
!= PKT_HASH_TYPE_NONE
)
1354 skb_set_hash(skb
, tpa_info
->rss_hash
, tpa_info
->hash_type
);
1356 if ((tpa_info
->flags2
& RX_CMP_FLAGS2_META_FORMAT_VLAN
) &&
1357 (skb
->dev
->features
& NETIF_F_HW_VLAN_CTAG_RX
)) {
1358 u16 vlan_proto
= tpa_info
->metadata
>>
1359 RX_CMP_FLAGS2_METADATA_TPID_SFT
;
1360 u16 vtag
= tpa_info
->metadata
& RX_CMP_FLAGS2_METADATA_VID_MASK
;
1362 __vlan_hwaccel_put_tag(skb
, htons(vlan_proto
), vtag
);
1365 skb_checksum_none_assert(skb
);
1366 if (likely(tpa_info
->flags2
& RX_TPA_START_CMP_FLAGS2_L4_CS_CALC
)) {
1367 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1369 (tpa_info
->flags2
& RX_CMP_FLAGS2_T_L4_CS_CALC
) >> 3;
1372 if (TPA_END_GRO(tpa_end
))
1373 skb
= bnxt_gro_skb(bp
, tpa_info
, tpa_end
, tpa_end1
, skb
);
1378 /* returns the following:
1379 * 1 - 1 packet successfully received
1380 * 0 - successful TPA_START, packet not completed yet
1381 * -EBUSY - completion ring does not have all the agg buffers yet
1382 * -ENOMEM - packet aborted due to out of memory
1383 * -EIO - packet aborted due to hw error indicated in BD
1385 static int bnxt_rx_pkt(struct bnxt
*bp
, struct bnxt_napi
*bnapi
, u32
*raw_cons
,
1388 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1389 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
1390 struct net_device
*dev
= bp
->dev
;
1391 struct rx_cmp
*rxcmp
;
1392 struct rx_cmp_ext
*rxcmp1
;
1393 u32 tmp_raw_cons
= *raw_cons
;
1394 u16 cons
, prod
, cp_cons
= RING_CMP(tmp_raw_cons
);
1395 struct bnxt_sw_rx_bd
*rx_buf
;
1397 u8
*data_ptr
, agg_bufs
, cmp_type
;
1398 dma_addr_t dma_addr
;
1399 struct sk_buff
*skb
;
1404 rxcmp
= (struct rx_cmp
*)
1405 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
1407 tmp_raw_cons
= NEXT_RAW_CMP(tmp_raw_cons
);
1408 cp_cons
= RING_CMP(tmp_raw_cons
);
1409 rxcmp1
= (struct rx_cmp_ext
*)
1410 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
1412 if (!RX_CMP_VALID(rxcmp1
, tmp_raw_cons
))
1415 cmp_type
= RX_CMP_TYPE(rxcmp
);
1417 prod
= rxr
->rx_prod
;
1419 if (cmp_type
== CMP_TYPE_RX_L2_TPA_START_CMP
) {
1420 bnxt_tpa_start(bp
, rxr
, (struct rx_tpa_start_cmp
*)rxcmp
,
1421 (struct rx_tpa_start_cmp_ext
*)rxcmp1
);
1423 *event
|= BNXT_RX_EVENT
;
1424 goto next_rx_no_prod
;
1426 } else if (cmp_type
== CMP_TYPE_RX_L2_TPA_END_CMP
) {
1427 skb
= bnxt_tpa_end(bp
, bnapi
, &tmp_raw_cons
,
1428 (struct rx_tpa_end_cmp
*)rxcmp
,
1429 (struct rx_tpa_end_cmp_ext
*)rxcmp1
, event
);
1431 if (unlikely(IS_ERR(skb
)))
1436 skb_record_rx_queue(skb
, bnapi
->index
);
1437 napi_gro_receive(&bnapi
->napi
, skb
);
1440 *event
|= BNXT_RX_EVENT
;
1441 goto next_rx_no_prod
;
1444 cons
= rxcmp
->rx_cmp_opaque
;
1445 rx_buf
= &rxr
->rx_buf_ring
[cons
];
1446 data
= rx_buf
->data
;
1447 data_ptr
= rx_buf
->data_ptr
;
1448 if (unlikely(cons
!= rxr
->rx_next_cons
)) {
1449 int rc1
= bnxt_discard_rx(bp
, bnapi
, raw_cons
, rxcmp
);
1451 bnxt_sched_reset(bp
, rxr
);
1456 misc
= le32_to_cpu(rxcmp
->rx_cmp_misc_v1
);
1457 agg_bufs
= (misc
& RX_CMP_AGG_BUFS
) >> RX_CMP_AGG_BUFS_SHIFT
;
1460 if (!bnxt_agg_bufs_valid(bp
, cpr
, agg_bufs
, &tmp_raw_cons
))
1463 cp_cons
= NEXT_CMP(cp_cons
);
1464 *event
|= BNXT_AGG_EVENT
;
1466 *event
|= BNXT_RX_EVENT
;
1468 rx_buf
->data
= NULL
;
1469 if (rxcmp1
->rx_cmp_cfa_code_errors_v2
& RX_CMP_L2_ERRORS
) {
1470 bnxt_reuse_rx_data(rxr
, cons
, data
);
1472 bnxt_reuse_rx_agg_bufs(bnapi
, cp_cons
, agg_bufs
);
1478 len
= le32_to_cpu(rxcmp
->rx_cmp_len_flags_type
) >> RX_CMP_LEN_SHIFT
;
1479 dma_addr
= rx_buf
->mapping
;
1481 if (bnxt_rx_xdp(bp
, rxr
, cons
, data
, &data_ptr
, &len
, event
)) {
1486 if (len
<= bp
->rx_copy_thresh
) {
1487 skb
= bnxt_copy_skb(bnapi
, data_ptr
, len
, dma_addr
);
1488 bnxt_reuse_rx_data(rxr
, cons
, data
);
1496 if (rx_buf
->data_ptr
== data_ptr
)
1497 payload
= misc
& RX_CMP_PAYLOAD_OFFSET
;
1500 skb
= bp
->rx_skb_func(bp
, rxr
, cons
, data
, data_ptr
, dma_addr
,
1509 skb
= bnxt_rx_pages(bp
, bnapi
, skb
, cp_cons
, agg_bufs
);
1516 if (RX_CMP_HASH_VALID(rxcmp
)) {
1517 u32 hash_type
= RX_CMP_HASH_TYPE(rxcmp
);
1518 enum pkt_hash_types type
= PKT_HASH_TYPE_L4
;
1520 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1521 if (hash_type
!= 1 && hash_type
!= 3)
1522 type
= PKT_HASH_TYPE_L3
;
1523 skb_set_hash(skb
, le32_to_cpu(rxcmp
->rx_cmp_rss_hash
), type
);
1526 skb
->protocol
= eth_type_trans(skb
, dev
);
1528 if ((rxcmp1
->rx_cmp_flags2
&
1529 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN
)) &&
1530 (skb
->dev
->features
& NETIF_F_HW_VLAN_CTAG_RX
)) {
1531 u32 meta_data
= le32_to_cpu(rxcmp1
->rx_cmp_meta_data
);
1532 u16 vtag
= meta_data
& RX_CMP_FLAGS2_METADATA_VID_MASK
;
1533 u16 vlan_proto
= meta_data
>> RX_CMP_FLAGS2_METADATA_TPID_SFT
;
1535 __vlan_hwaccel_put_tag(skb
, htons(vlan_proto
), vtag
);
1538 skb_checksum_none_assert(skb
);
1539 if (RX_CMP_L4_CS_OK(rxcmp1
)) {
1540 if (dev
->features
& NETIF_F_RXCSUM
) {
1541 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1542 skb
->csum_level
= RX_CMP_ENCAP(rxcmp1
);
1545 if (rxcmp1
->rx_cmp_cfa_code_errors_v2
& RX_CMP_L4_CS_ERR_BITS
) {
1546 if (dev
->features
& NETIF_F_RXCSUM
)
1547 cpr
->rx_l4_csum_errors
++;
1551 skb_record_rx_queue(skb
, bnapi
->index
);
1552 napi_gro_receive(&bnapi
->napi
, skb
);
1556 rxr
->rx_prod
= NEXT_RX(prod
);
1557 rxr
->rx_next_cons
= NEXT_RX(cons
);
1560 *raw_cons
= tmp_raw_cons
;
1565 #define BNXT_GET_EVENT_PORT(data) \
1567 ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
1569 static int bnxt_async_event_process(struct bnxt
*bp
,
1570 struct hwrm_async_event_cmpl
*cmpl
)
1572 u16 event_id
= le16_to_cpu(cmpl
->event_id
);
1574 /* TODO CHIMP_FW: Define event id's for link change, error etc */
1576 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE
: {
1577 u32 data1
= le32_to_cpu(cmpl
->event_data1
);
1578 struct bnxt_link_info
*link_info
= &bp
->link_info
;
1581 goto async_event_process_exit
;
1582 if (data1
& 0x20000) {
1583 u16 fw_speed
= link_info
->force_link_speed
;
1584 u32 speed
= bnxt_fw_to_ethtool_speed(fw_speed
);
1586 netdev_warn(bp
->dev
, "Link speed %d no longer supported\n",
1589 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT
, &bp
->sp_event
);
1592 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE
:
1593 set_bit(BNXT_LINK_CHNG_SP_EVENT
, &bp
->sp_event
);
1595 case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD
:
1596 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT
, &bp
->sp_event
);
1598 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED
: {
1599 u32 data1
= le32_to_cpu(cmpl
->event_data1
);
1600 u16 port_id
= BNXT_GET_EVENT_PORT(data1
);
1605 if (bp
->pf
.port_id
!= port_id
)
1608 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT
, &bp
->sp_event
);
1611 case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE
:
1613 goto async_event_process_exit
;
1614 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT
, &bp
->sp_event
);
1617 goto async_event_process_exit
;
1619 schedule_work(&bp
->sp_task
);
1620 async_event_process_exit
:
1621 bnxt_ulp_async_events(bp
, cmpl
);
1625 static int bnxt_hwrm_handler(struct bnxt
*bp
, struct tx_cmp
*txcmp
)
1627 u16 cmpl_type
= TX_CMP_TYPE(txcmp
), vf_id
, seq_id
;
1628 struct hwrm_cmpl
*h_cmpl
= (struct hwrm_cmpl
*)txcmp
;
1629 struct hwrm_fwd_req_cmpl
*fwd_req_cmpl
=
1630 (struct hwrm_fwd_req_cmpl
*)txcmp
;
1632 switch (cmpl_type
) {
1633 case CMPL_BASE_TYPE_HWRM_DONE
:
1634 seq_id
= le16_to_cpu(h_cmpl
->sequence_id
);
1635 if (seq_id
== bp
->hwrm_intr_seq_id
)
1636 bp
->hwrm_intr_seq_id
= HWRM_SEQ_ID_INVALID
;
1638 netdev_err(bp
->dev
, "Invalid hwrm seq id %d\n", seq_id
);
1641 case CMPL_BASE_TYPE_HWRM_FWD_REQ
:
1642 vf_id
= le16_to_cpu(fwd_req_cmpl
->source_id
);
1644 if ((vf_id
< bp
->pf
.first_vf_id
) ||
1645 (vf_id
>= bp
->pf
.first_vf_id
+ bp
->pf
.active_vfs
)) {
1646 netdev_err(bp
->dev
, "Msg contains invalid VF id %x\n",
1651 set_bit(vf_id
- bp
->pf
.first_vf_id
, bp
->pf
.vf_event_bmap
);
1652 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT
, &bp
->sp_event
);
1653 schedule_work(&bp
->sp_task
);
1656 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT
:
1657 bnxt_async_event_process(bp
,
1658 (struct hwrm_async_event_cmpl
*)txcmp
);
1667 static irqreturn_t
bnxt_msix(int irq
, void *dev_instance
)
1669 struct bnxt_napi
*bnapi
= dev_instance
;
1670 struct bnxt
*bp
= bnapi
->bp
;
1671 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1672 u32 cons
= RING_CMP(cpr
->cp_raw_cons
);
1674 prefetch(&cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)]);
1675 napi_schedule(&bnapi
->napi
);
1679 static inline int bnxt_has_work(struct bnxt
*bp
, struct bnxt_cp_ring_info
*cpr
)
1681 u32 raw_cons
= cpr
->cp_raw_cons
;
1682 u16 cons
= RING_CMP(raw_cons
);
1683 struct tx_cmp
*txcmp
;
1685 txcmp
= &cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)];
1687 return TX_CMP_VALID(txcmp
, raw_cons
);
1690 static irqreturn_t
bnxt_inta(int irq
, void *dev_instance
)
1692 struct bnxt_napi
*bnapi
= dev_instance
;
1693 struct bnxt
*bp
= bnapi
->bp
;
1694 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1695 u32 cons
= RING_CMP(cpr
->cp_raw_cons
);
1698 prefetch(&cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)]);
1700 if (!bnxt_has_work(bp
, cpr
)) {
1701 int_status
= readl(bp
->bar0
+ BNXT_CAG_REG_LEGACY_INT_STATUS
);
1702 /* return if erroneous interrupt */
1703 if (!(int_status
& (0x10000 << cpr
->cp_ring_struct
.fw_ring_id
)))
1707 /* disable ring IRQ */
1708 BNXT_CP_DB_IRQ_DIS(cpr
->cp_doorbell
);
1710 /* Return here if interrupt is shared and is disabled. */
1711 if (unlikely(atomic_read(&bp
->intr_sem
) != 0))
1714 napi_schedule(&bnapi
->napi
);
1718 static int bnxt_poll_work(struct bnxt
*bp
, struct bnxt_napi
*bnapi
, int budget
)
1720 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1721 u32 raw_cons
= cpr
->cp_raw_cons
;
1726 struct tx_cmp
*txcmp
;
1731 cons
= RING_CMP(raw_cons
);
1732 txcmp
= &cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)];
1734 if (!TX_CMP_VALID(txcmp
, raw_cons
))
1737 /* The valid test of the entry must be done first before
1738 * reading any further.
1741 if (TX_CMP_TYPE(txcmp
) == CMP_TYPE_TX_L2_CMP
) {
1743 /* return full budget so NAPI will complete. */
1744 if (unlikely(tx_pkts
> bp
->tx_wake_thresh
))
1746 } else if ((TX_CMP_TYPE(txcmp
) & 0x30) == 0x10) {
1747 rc
= bnxt_rx_pkt(bp
, bnapi
, &raw_cons
, &event
);
1748 if (likely(rc
>= 0))
1750 else if (rc
== -EBUSY
) /* partial completion */
1752 } else if (unlikely((TX_CMP_TYPE(txcmp
) ==
1753 CMPL_BASE_TYPE_HWRM_DONE
) ||
1754 (TX_CMP_TYPE(txcmp
) ==
1755 CMPL_BASE_TYPE_HWRM_FWD_REQ
) ||
1756 (TX_CMP_TYPE(txcmp
) ==
1757 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT
))) {
1758 bnxt_hwrm_handler(bp
, txcmp
);
1760 raw_cons
= NEXT_RAW_CMP(raw_cons
);
1762 if (rx_pkts
== budget
)
1766 if (event
& BNXT_TX_EVENT
) {
1767 struct bnxt_tx_ring_info
*txr
= bnapi
->tx_ring
;
1768 void __iomem
*db
= txr
->tx_doorbell
;
1769 u16 prod
= txr
->tx_prod
;
1771 /* Sync BD data before updating doorbell */
1774 writel(DB_KEY_TX
| prod
, db
);
1775 writel(DB_KEY_TX
| prod
, db
);
1778 cpr
->cp_raw_cons
= raw_cons
;
1779 /* ACK completion ring before freeing tx ring and producing new
1780 * buffers in rx/agg rings to prevent overflowing the completion
1783 BNXT_CP_DB(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
1786 bnapi
->tx_int(bp
, bnapi
, tx_pkts
);
1788 if (event
& BNXT_RX_EVENT
) {
1789 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
1791 writel(DB_KEY_RX
| rxr
->rx_prod
, rxr
->rx_doorbell
);
1792 writel(DB_KEY_RX
| rxr
->rx_prod
, rxr
->rx_doorbell
);
1793 if (event
& BNXT_AGG_EVENT
) {
1794 writel(DB_KEY_RX
| rxr
->rx_agg_prod
,
1795 rxr
->rx_agg_doorbell
);
1796 writel(DB_KEY_RX
| rxr
->rx_agg_prod
,
1797 rxr
->rx_agg_doorbell
);
1803 static int bnxt_poll_nitroa0(struct napi_struct
*napi
, int budget
)
1805 struct bnxt_napi
*bnapi
= container_of(napi
, struct bnxt_napi
, napi
);
1806 struct bnxt
*bp
= bnapi
->bp
;
1807 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1808 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
1809 struct tx_cmp
*txcmp
;
1810 struct rx_cmp_ext
*rxcmp1
;
1811 u32 cp_cons
, tmp_raw_cons
;
1812 u32 raw_cons
= cpr
->cp_raw_cons
;
1819 cp_cons
= RING_CMP(raw_cons
);
1820 txcmp
= &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
1822 if (!TX_CMP_VALID(txcmp
, raw_cons
))
1825 if ((TX_CMP_TYPE(txcmp
) & 0x30) == 0x10) {
1826 tmp_raw_cons
= NEXT_RAW_CMP(raw_cons
);
1827 cp_cons
= RING_CMP(tmp_raw_cons
);
1828 rxcmp1
= (struct rx_cmp_ext
*)
1829 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
1831 if (!RX_CMP_VALID(rxcmp1
, tmp_raw_cons
))
1834 /* force an error to recycle the buffer */
1835 rxcmp1
->rx_cmp_cfa_code_errors_v2
|=
1836 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR
);
1838 rc
= bnxt_rx_pkt(bp
, bnapi
, &raw_cons
, &event
);
1839 if (likely(rc
== -EIO
))
1841 else if (rc
== -EBUSY
) /* partial completion */
1843 } else if (unlikely(TX_CMP_TYPE(txcmp
) ==
1844 CMPL_BASE_TYPE_HWRM_DONE
)) {
1845 bnxt_hwrm_handler(bp
, txcmp
);
1848 "Invalid completion received on special ring\n");
1850 raw_cons
= NEXT_RAW_CMP(raw_cons
);
1852 if (rx_pkts
== budget
)
1856 cpr
->cp_raw_cons
= raw_cons
;
1857 BNXT_CP_DB(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
1858 writel(DB_KEY_RX
| rxr
->rx_prod
, rxr
->rx_doorbell
);
1859 writel(DB_KEY_RX
| rxr
->rx_prod
, rxr
->rx_doorbell
);
1861 if (event
& BNXT_AGG_EVENT
) {
1862 writel(DB_KEY_RX
| rxr
->rx_agg_prod
, rxr
->rx_agg_doorbell
);
1863 writel(DB_KEY_RX
| rxr
->rx_agg_prod
, rxr
->rx_agg_doorbell
);
1866 if (!bnxt_has_work(bp
, cpr
) && rx_pkts
< budget
) {
1867 napi_complete_done(napi
, rx_pkts
);
1868 BNXT_CP_DB_REARM(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
1873 static int bnxt_poll(struct napi_struct
*napi
, int budget
)
1875 struct bnxt_napi
*bnapi
= container_of(napi
, struct bnxt_napi
, napi
);
1876 struct bnxt
*bp
= bnapi
->bp
;
1877 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1881 work_done
+= bnxt_poll_work(bp
, bnapi
, budget
- work_done
);
1883 if (work_done
>= budget
)
1886 if (!bnxt_has_work(bp
, cpr
)) {
1887 if (napi_complete_done(napi
, work_done
))
1888 BNXT_CP_DB_REARM(cpr
->cp_doorbell
,
1897 static void bnxt_free_tx_skbs(struct bnxt
*bp
)
1900 struct pci_dev
*pdev
= bp
->pdev
;
1905 max_idx
= bp
->tx_nr_pages
* TX_DESC_CNT
;
1906 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
1907 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
1910 for (j
= 0; j
< max_idx
;) {
1911 struct bnxt_sw_tx_bd
*tx_buf
= &txr
->tx_buf_ring
[j
];
1912 struct sk_buff
*skb
= tx_buf
->skb
;
1922 if (tx_buf
->is_push
) {
1928 dma_unmap_single(&pdev
->dev
,
1929 dma_unmap_addr(tx_buf
, mapping
),
1933 last
= tx_buf
->nr_frags
;
1935 for (k
= 0; k
< last
; k
++, j
++) {
1936 int ring_idx
= j
& bp
->tx_ring_mask
;
1937 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[k
];
1939 tx_buf
= &txr
->tx_buf_ring
[ring_idx
];
1942 dma_unmap_addr(tx_buf
, mapping
),
1943 skb_frag_size(frag
), PCI_DMA_TODEVICE
);
1947 netdev_tx_reset_queue(netdev_get_tx_queue(bp
->dev
, i
));
1951 static void bnxt_free_rx_skbs(struct bnxt
*bp
)
1953 int i
, max_idx
, max_agg_idx
;
1954 struct pci_dev
*pdev
= bp
->pdev
;
1959 max_idx
= bp
->rx_nr_pages
* RX_DESC_CNT
;
1960 max_agg_idx
= bp
->rx_agg_nr_pages
* RX_DESC_CNT
;
1961 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
1962 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
1966 for (j
= 0; j
< MAX_TPA
; j
++) {
1967 struct bnxt_tpa_info
*tpa_info
=
1969 u8
*data
= tpa_info
->data
;
1974 dma_unmap_single(&pdev
->dev
, tpa_info
->mapping
,
1975 bp
->rx_buf_use_size
,
1978 tpa_info
->data
= NULL
;
1984 for (j
= 0; j
< max_idx
; j
++) {
1985 struct bnxt_sw_rx_bd
*rx_buf
= &rxr
->rx_buf_ring
[j
];
1986 dma_addr_t mapping
= rx_buf
->mapping
;
1987 void *data
= rx_buf
->data
;
1992 rx_buf
->data
= NULL
;
1994 if (BNXT_RX_PAGE_MODE(bp
)) {
1995 mapping
-= bp
->rx_dma_offset
;
1996 dma_unmap_page(&pdev
->dev
, mapping
,
1997 PAGE_SIZE
, bp
->rx_dir
);
2000 dma_unmap_single(&pdev
->dev
, mapping
,
2001 bp
->rx_buf_use_size
,
2007 for (j
= 0; j
< max_agg_idx
; j
++) {
2008 struct bnxt_sw_rx_agg_bd
*rx_agg_buf
=
2009 &rxr
->rx_agg_ring
[j
];
2010 struct page
*page
= rx_agg_buf
->page
;
2015 dma_unmap_page(&pdev
->dev
, rx_agg_buf
->mapping
,
2016 BNXT_RX_PAGE_SIZE
, PCI_DMA_FROMDEVICE
);
2018 rx_agg_buf
->page
= NULL
;
2019 __clear_bit(j
, rxr
->rx_agg_bmap
);
2024 __free_page(rxr
->rx_page
);
2025 rxr
->rx_page
= NULL
;
2030 static void bnxt_free_skbs(struct bnxt
*bp
)
2032 bnxt_free_tx_skbs(bp
);
2033 bnxt_free_rx_skbs(bp
);
2036 static void bnxt_free_ring(struct bnxt
*bp
, struct bnxt_ring_struct
*ring
)
2038 struct pci_dev
*pdev
= bp
->pdev
;
2041 for (i
= 0; i
< ring
->nr_pages
; i
++) {
2042 if (!ring
->pg_arr
[i
])
2045 dma_free_coherent(&pdev
->dev
, ring
->page_size
,
2046 ring
->pg_arr
[i
], ring
->dma_arr
[i
]);
2048 ring
->pg_arr
[i
] = NULL
;
2051 dma_free_coherent(&pdev
->dev
, ring
->nr_pages
* 8,
2052 ring
->pg_tbl
, ring
->pg_tbl_map
);
2053 ring
->pg_tbl
= NULL
;
2055 if (ring
->vmem_size
&& *ring
->vmem
) {
2061 static int bnxt_alloc_ring(struct bnxt
*bp
, struct bnxt_ring_struct
*ring
)
2064 struct pci_dev
*pdev
= bp
->pdev
;
2066 if (ring
->nr_pages
> 1) {
2067 ring
->pg_tbl
= dma_alloc_coherent(&pdev
->dev
,
2075 for (i
= 0; i
< ring
->nr_pages
; i
++) {
2076 ring
->pg_arr
[i
] = dma_alloc_coherent(&pdev
->dev
,
2080 if (!ring
->pg_arr
[i
])
2083 if (ring
->nr_pages
> 1)
2084 ring
->pg_tbl
[i
] = cpu_to_le64(ring
->dma_arr
[i
]);
2087 if (ring
->vmem_size
) {
2088 *ring
->vmem
= vzalloc(ring
->vmem_size
);
2095 static void bnxt_free_rx_rings(struct bnxt
*bp
)
2102 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
2103 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
2104 struct bnxt_ring_struct
*ring
;
2107 bpf_prog_put(rxr
->xdp_prog
);
2112 kfree(rxr
->rx_agg_bmap
);
2113 rxr
->rx_agg_bmap
= NULL
;
2115 ring
= &rxr
->rx_ring_struct
;
2116 bnxt_free_ring(bp
, ring
);
2118 ring
= &rxr
->rx_agg_ring_struct
;
2119 bnxt_free_ring(bp
, ring
);
2123 static int bnxt_alloc_rx_rings(struct bnxt
*bp
)
2125 int i
, rc
, agg_rings
= 0, tpa_rings
= 0;
2130 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
)
2133 if (bp
->flags
& BNXT_FLAG_TPA
)
2136 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
2137 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
2138 struct bnxt_ring_struct
*ring
;
2140 ring
= &rxr
->rx_ring_struct
;
2142 rc
= bnxt_alloc_ring(bp
, ring
);
2149 ring
= &rxr
->rx_agg_ring_struct
;
2150 rc
= bnxt_alloc_ring(bp
, ring
);
2154 rxr
->rx_agg_bmap_size
= bp
->rx_agg_ring_mask
+ 1;
2155 mem_size
= rxr
->rx_agg_bmap_size
/ 8;
2156 rxr
->rx_agg_bmap
= kzalloc(mem_size
, GFP_KERNEL
);
2157 if (!rxr
->rx_agg_bmap
)
2161 rxr
->rx_tpa
= kcalloc(MAX_TPA
,
2162 sizeof(struct bnxt_tpa_info
),
2172 static void bnxt_free_tx_rings(struct bnxt
*bp
)
2175 struct pci_dev
*pdev
= bp
->pdev
;
2180 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
2181 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
2182 struct bnxt_ring_struct
*ring
;
2185 dma_free_coherent(&pdev
->dev
, bp
->tx_push_size
,
2186 txr
->tx_push
, txr
->tx_push_mapping
);
2187 txr
->tx_push
= NULL
;
2190 ring
= &txr
->tx_ring_struct
;
2192 bnxt_free_ring(bp
, ring
);
2196 static int bnxt_alloc_tx_rings(struct bnxt
*bp
)
2199 struct pci_dev
*pdev
= bp
->pdev
;
2201 bp
->tx_push_size
= 0;
2202 if (bp
->tx_push_thresh
) {
2205 push_size
= L1_CACHE_ALIGN(sizeof(struct tx_push_bd
) +
2206 bp
->tx_push_thresh
);
2208 if (push_size
> 256) {
2210 bp
->tx_push_thresh
= 0;
2213 bp
->tx_push_size
= push_size
;
2216 for (i
= 0, j
= 0; i
< bp
->tx_nr_rings
; i
++) {
2217 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
2218 struct bnxt_ring_struct
*ring
;
2220 ring
= &txr
->tx_ring_struct
;
2222 rc
= bnxt_alloc_ring(bp
, ring
);
2226 if (bp
->tx_push_size
) {
2229 /* One pre-allocated DMA buffer to backup
2232 txr
->tx_push
= dma_alloc_coherent(&pdev
->dev
,
2234 &txr
->tx_push_mapping
,
2240 mapping
= txr
->tx_push_mapping
+
2241 sizeof(struct tx_push_bd
);
2242 txr
->data_mapping
= cpu_to_le64(mapping
);
2244 memset(txr
->tx_push
, 0, sizeof(struct tx_push_bd
));
2246 ring
->queue_id
= bp
->q_info
[j
].queue_id
;
2247 if (i
< bp
->tx_nr_rings_xdp
)
2249 if (i
% bp
->tx_nr_rings_per_tc
== (bp
->tx_nr_rings_per_tc
- 1))
2255 static void bnxt_free_cp_rings(struct bnxt
*bp
)
2262 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2263 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2264 struct bnxt_cp_ring_info
*cpr
;
2265 struct bnxt_ring_struct
*ring
;
2270 cpr
= &bnapi
->cp_ring
;
2271 ring
= &cpr
->cp_ring_struct
;
2273 bnxt_free_ring(bp
, ring
);
2277 static int bnxt_alloc_cp_rings(struct bnxt
*bp
)
2281 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2282 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2283 struct bnxt_cp_ring_info
*cpr
;
2284 struct bnxt_ring_struct
*ring
;
2289 cpr
= &bnapi
->cp_ring
;
2290 ring
= &cpr
->cp_ring_struct
;
2292 rc
= bnxt_alloc_ring(bp
, ring
);
2299 static void bnxt_init_ring_struct(struct bnxt
*bp
)
2303 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2304 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2305 struct bnxt_cp_ring_info
*cpr
;
2306 struct bnxt_rx_ring_info
*rxr
;
2307 struct bnxt_tx_ring_info
*txr
;
2308 struct bnxt_ring_struct
*ring
;
2313 cpr
= &bnapi
->cp_ring
;
2314 ring
= &cpr
->cp_ring_struct
;
2315 ring
->nr_pages
= bp
->cp_nr_pages
;
2316 ring
->page_size
= HW_CMPD_RING_SIZE
;
2317 ring
->pg_arr
= (void **)cpr
->cp_desc_ring
;
2318 ring
->dma_arr
= cpr
->cp_desc_mapping
;
2319 ring
->vmem_size
= 0;
2321 rxr
= bnapi
->rx_ring
;
2325 ring
= &rxr
->rx_ring_struct
;
2326 ring
->nr_pages
= bp
->rx_nr_pages
;
2327 ring
->page_size
= HW_RXBD_RING_SIZE
;
2328 ring
->pg_arr
= (void **)rxr
->rx_desc_ring
;
2329 ring
->dma_arr
= rxr
->rx_desc_mapping
;
2330 ring
->vmem_size
= SW_RXBD_RING_SIZE
* bp
->rx_nr_pages
;
2331 ring
->vmem
= (void **)&rxr
->rx_buf_ring
;
2333 ring
= &rxr
->rx_agg_ring_struct
;
2334 ring
->nr_pages
= bp
->rx_agg_nr_pages
;
2335 ring
->page_size
= HW_RXBD_RING_SIZE
;
2336 ring
->pg_arr
= (void **)rxr
->rx_agg_desc_ring
;
2337 ring
->dma_arr
= rxr
->rx_agg_desc_mapping
;
2338 ring
->vmem_size
= SW_RXBD_AGG_RING_SIZE
* bp
->rx_agg_nr_pages
;
2339 ring
->vmem
= (void **)&rxr
->rx_agg_ring
;
2342 txr
= bnapi
->tx_ring
;
2346 ring
= &txr
->tx_ring_struct
;
2347 ring
->nr_pages
= bp
->tx_nr_pages
;
2348 ring
->page_size
= HW_RXBD_RING_SIZE
;
2349 ring
->pg_arr
= (void **)txr
->tx_desc_ring
;
2350 ring
->dma_arr
= txr
->tx_desc_mapping
;
2351 ring
->vmem_size
= SW_TXBD_RING_SIZE
* bp
->tx_nr_pages
;
2352 ring
->vmem
= (void **)&txr
->tx_buf_ring
;
2356 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct
*ring
, u32 type
)
2360 struct rx_bd
**rx_buf_ring
;
2362 rx_buf_ring
= (struct rx_bd
**)ring
->pg_arr
;
2363 for (i
= 0, prod
= 0; i
< ring
->nr_pages
; i
++) {
2367 rxbd
= rx_buf_ring
[i
];
2371 for (j
= 0; j
< RX_DESC_CNT
; j
++, rxbd
++, prod
++) {
2372 rxbd
->rx_bd_len_flags_type
= cpu_to_le32(type
);
2373 rxbd
->rx_bd_opaque
= prod
;
2378 static int bnxt_init_one_rx_ring(struct bnxt
*bp
, int ring_nr
)
2380 struct net_device
*dev
= bp
->dev
;
2381 struct bnxt_rx_ring_info
*rxr
;
2382 struct bnxt_ring_struct
*ring
;
2386 type
= (bp
->rx_buf_use_size
<< RX_BD_LEN_SHIFT
) |
2387 RX_BD_TYPE_RX_PACKET_BD
| RX_BD_FLAGS_EOP
;
2389 if (NET_IP_ALIGN
== 2)
2390 type
|= RX_BD_FLAGS_SOP
;
2392 rxr
= &bp
->rx_ring
[ring_nr
];
2393 ring
= &rxr
->rx_ring_struct
;
2394 bnxt_init_rxbd_pages(ring
, type
);
2396 if (BNXT_RX_PAGE_MODE(bp
) && bp
->xdp_prog
) {
2397 rxr
->xdp_prog
= bpf_prog_add(bp
->xdp_prog
, 1);
2398 if (IS_ERR(rxr
->xdp_prog
)) {
2399 int rc
= PTR_ERR(rxr
->xdp_prog
);
2401 rxr
->xdp_prog
= NULL
;
2405 prod
= rxr
->rx_prod
;
2406 for (i
= 0; i
< bp
->rx_ring_size
; i
++) {
2407 if (bnxt_alloc_rx_data(bp
, rxr
, prod
, GFP_KERNEL
) != 0) {
2408 netdev_warn(dev
, "init'ed rx ring %d with %d/%d skbs only\n",
2409 ring_nr
, i
, bp
->rx_ring_size
);
2412 prod
= NEXT_RX(prod
);
2414 rxr
->rx_prod
= prod
;
2415 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
2417 ring
= &rxr
->rx_agg_ring_struct
;
2418 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
2420 if (!(bp
->flags
& BNXT_FLAG_AGG_RINGS
))
2423 type
= ((u32
)BNXT_RX_PAGE_SIZE
<< RX_BD_LEN_SHIFT
) |
2424 RX_BD_TYPE_RX_AGG_BD
| RX_BD_FLAGS_SOP
;
2426 bnxt_init_rxbd_pages(ring
, type
);
2428 prod
= rxr
->rx_agg_prod
;
2429 for (i
= 0; i
< bp
->rx_agg_ring_size
; i
++) {
2430 if (bnxt_alloc_rx_page(bp
, rxr
, prod
, GFP_KERNEL
) != 0) {
2431 netdev_warn(dev
, "init'ed rx ring %d with %d/%d pages only\n",
2432 ring_nr
, i
, bp
->rx_ring_size
);
2435 prod
= NEXT_RX_AGG(prod
);
2437 rxr
->rx_agg_prod
= prod
;
2439 if (bp
->flags
& BNXT_FLAG_TPA
) {
2444 for (i
= 0; i
< MAX_TPA
; i
++) {
2445 data
= __bnxt_alloc_rx_data(bp
, &mapping
,
2450 rxr
->rx_tpa
[i
].data
= data
;
2451 rxr
->rx_tpa
[i
].data_ptr
= data
+ bp
->rx_offset
;
2452 rxr
->rx_tpa
[i
].mapping
= mapping
;
2455 netdev_err(bp
->dev
, "No resource allocated for LRO/GRO\n");
2463 static void bnxt_init_cp_rings(struct bnxt
*bp
)
2467 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2468 struct bnxt_cp_ring_info
*cpr
= &bp
->bnapi
[i
]->cp_ring
;
2469 struct bnxt_ring_struct
*ring
= &cpr
->cp_ring_struct
;
2471 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
2475 static int bnxt_init_rx_rings(struct bnxt
*bp
)
2479 if (BNXT_RX_PAGE_MODE(bp
)) {
2480 bp
->rx_offset
= NET_IP_ALIGN
+ XDP_PACKET_HEADROOM
;
2481 bp
->rx_dma_offset
= XDP_PACKET_HEADROOM
;
2483 bp
->rx_offset
= BNXT_RX_OFFSET
;
2484 bp
->rx_dma_offset
= BNXT_RX_DMA_OFFSET
;
2487 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
2488 rc
= bnxt_init_one_rx_ring(bp
, i
);
2496 static int bnxt_init_tx_rings(struct bnxt
*bp
)
2500 bp
->tx_wake_thresh
= max_t(int, bp
->tx_ring_size
/ 2,
2503 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
2504 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
2505 struct bnxt_ring_struct
*ring
= &txr
->tx_ring_struct
;
2507 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
2513 static void bnxt_free_ring_grps(struct bnxt
*bp
)
2515 kfree(bp
->grp_info
);
2516 bp
->grp_info
= NULL
;
2519 static int bnxt_init_ring_grps(struct bnxt
*bp
, bool irq_re_init
)
2524 bp
->grp_info
= kcalloc(bp
->cp_nr_rings
,
2525 sizeof(struct bnxt_ring_grp_info
),
2530 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2532 bp
->grp_info
[i
].fw_stats_ctx
= INVALID_HW_RING_ID
;
2533 bp
->grp_info
[i
].fw_grp_id
= INVALID_HW_RING_ID
;
2534 bp
->grp_info
[i
].rx_fw_ring_id
= INVALID_HW_RING_ID
;
2535 bp
->grp_info
[i
].agg_fw_ring_id
= INVALID_HW_RING_ID
;
2536 bp
->grp_info
[i
].cp_fw_ring_id
= INVALID_HW_RING_ID
;
2541 static void bnxt_free_vnics(struct bnxt
*bp
)
2543 kfree(bp
->vnic_info
);
2544 bp
->vnic_info
= NULL
;
2548 static int bnxt_alloc_vnics(struct bnxt
*bp
)
2552 #ifdef CONFIG_RFS_ACCEL
2553 if (bp
->flags
& BNXT_FLAG_RFS
)
2554 num_vnics
+= bp
->rx_nr_rings
;
2557 if (BNXT_CHIP_TYPE_NITRO_A0(bp
))
2560 bp
->vnic_info
= kcalloc(num_vnics
, sizeof(struct bnxt_vnic_info
),
2565 bp
->nr_vnics
= num_vnics
;
2569 static void bnxt_init_vnics(struct bnxt
*bp
)
2573 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
2574 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[i
];
2576 vnic
->fw_vnic_id
= INVALID_HW_RING_ID
;
2577 vnic
->fw_rss_cos_lb_ctx
[0] = INVALID_HW_RING_ID
;
2578 vnic
->fw_rss_cos_lb_ctx
[1] = INVALID_HW_RING_ID
;
2579 vnic
->fw_l2_ctx_id
= INVALID_HW_RING_ID
;
2581 if (bp
->vnic_info
[i
].rss_hash_key
) {
2583 prandom_bytes(vnic
->rss_hash_key
,
2586 memcpy(vnic
->rss_hash_key
,
2587 bp
->vnic_info
[0].rss_hash_key
,
2593 static int bnxt_calc_nr_ring_pages(u32 ring_size
, int desc_per_pg
)
2597 pages
= ring_size
/ desc_per_pg
;
2604 while (pages
& (pages
- 1))
2610 void bnxt_set_tpa_flags(struct bnxt
*bp
)
2612 bp
->flags
&= ~BNXT_FLAG_TPA
;
2613 if (bp
->flags
& BNXT_FLAG_NO_AGG_RINGS
)
2615 if (bp
->dev
->features
& NETIF_F_LRO
)
2616 bp
->flags
|= BNXT_FLAG_LRO
;
2617 if (bp
->dev
->features
& NETIF_F_GRO
)
2618 bp
->flags
|= BNXT_FLAG_GRO
;
2621 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2624 void bnxt_set_ring_params(struct bnxt
*bp
)
2626 u32 ring_size
, rx_size
, rx_space
;
2627 u32 agg_factor
= 0, agg_ring_size
= 0;
2629 /* 8 for CRC and VLAN */
2630 rx_size
= SKB_DATA_ALIGN(bp
->dev
->mtu
+ ETH_HLEN
+ NET_IP_ALIGN
+ 8);
2632 rx_space
= rx_size
+ NET_SKB_PAD
+
2633 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
2635 bp
->rx_copy_thresh
= BNXT_RX_COPY_THRESH
;
2636 ring_size
= bp
->rx_ring_size
;
2637 bp
->rx_agg_ring_size
= 0;
2638 bp
->rx_agg_nr_pages
= 0;
2640 if (bp
->flags
& BNXT_FLAG_TPA
)
2641 agg_factor
= min_t(u32
, 4, 65536 / BNXT_RX_PAGE_SIZE
);
2643 bp
->flags
&= ~BNXT_FLAG_JUMBO
;
2644 if (rx_space
> PAGE_SIZE
&& !(bp
->flags
& BNXT_FLAG_NO_AGG_RINGS
)) {
2647 bp
->flags
|= BNXT_FLAG_JUMBO
;
2648 jumbo_factor
= PAGE_ALIGN(bp
->dev
->mtu
- 40) >> PAGE_SHIFT
;
2649 if (jumbo_factor
> agg_factor
)
2650 agg_factor
= jumbo_factor
;
2652 agg_ring_size
= ring_size
* agg_factor
;
2654 if (agg_ring_size
) {
2655 bp
->rx_agg_nr_pages
= bnxt_calc_nr_ring_pages(agg_ring_size
,
2657 if (bp
->rx_agg_nr_pages
> MAX_RX_AGG_PAGES
) {
2658 u32 tmp
= agg_ring_size
;
2660 bp
->rx_agg_nr_pages
= MAX_RX_AGG_PAGES
;
2661 agg_ring_size
= MAX_RX_AGG_PAGES
* RX_DESC_CNT
- 1;
2662 netdev_warn(bp
->dev
, "rx agg ring size %d reduced to %d.\n",
2663 tmp
, agg_ring_size
);
2665 bp
->rx_agg_ring_size
= agg_ring_size
;
2666 bp
->rx_agg_ring_mask
= (bp
->rx_agg_nr_pages
* RX_DESC_CNT
) - 1;
2667 rx_size
= SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH
+ NET_IP_ALIGN
);
2668 rx_space
= rx_size
+ NET_SKB_PAD
+
2669 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
2672 bp
->rx_buf_use_size
= rx_size
;
2673 bp
->rx_buf_size
= rx_space
;
2675 bp
->rx_nr_pages
= bnxt_calc_nr_ring_pages(ring_size
, RX_DESC_CNT
);
2676 bp
->rx_ring_mask
= (bp
->rx_nr_pages
* RX_DESC_CNT
) - 1;
2678 ring_size
= bp
->tx_ring_size
;
2679 bp
->tx_nr_pages
= bnxt_calc_nr_ring_pages(ring_size
, TX_DESC_CNT
);
2680 bp
->tx_ring_mask
= (bp
->tx_nr_pages
* TX_DESC_CNT
) - 1;
2682 ring_size
= bp
->rx_ring_size
* (2 + agg_factor
) + bp
->tx_ring_size
;
2683 bp
->cp_ring_size
= ring_size
;
2685 bp
->cp_nr_pages
= bnxt_calc_nr_ring_pages(ring_size
, CP_DESC_CNT
);
2686 if (bp
->cp_nr_pages
> MAX_CP_PAGES
) {
2687 bp
->cp_nr_pages
= MAX_CP_PAGES
;
2688 bp
->cp_ring_size
= MAX_CP_PAGES
* CP_DESC_CNT
- 1;
2689 netdev_warn(bp
->dev
, "completion ring size %d reduced to %d.\n",
2690 ring_size
, bp
->cp_ring_size
);
2692 bp
->cp_bit
= bp
->cp_nr_pages
* CP_DESC_CNT
;
2693 bp
->cp_ring_mask
= bp
->cp_bit
- 1;
2696 int bnxt_set_rx_skb_mode(struct bnxt
*bp
, bool page_mode
)
2699 if (bp
->dev
->mtu
> BNXT_MAX_PAGE_MODE_MTU
)
2701 bp
->dev
->max_mtu
= BNXT_MAX_PAGE_MODE_MTU
;
2702 bp
->flags
&= ~BNXT_FLAG_AGG_RINGS
;
2703 bp
->flags
|= BNXT_FLAG_NO_AGG_RINGS
| BNXT_FLAG_RX_PAGE_MODE
;
2704 bp
->dev
->hw_features
&= ~NETIF_F_LRO
;
2705 bp
->dev
->features
&= ~NETIF_F_LRO
;
2706 bp
->rx_dir
= DMA_BIDIRECTIONAL
;
2707 bp
->rx_skb_func
= bnxt_rx_page_skb
;
2709 bp
->dev
->max_mtu
= BNXT_MAX_MTU
;
2710 bp
->flags
&= ~BNXT_FLAG_RX_PAGE_MODE
;
2711 bp
->rx_dir
= DMA_FROM_DEVICE
;
2712 bp
->rx_skb_func
= bnxt_rx_skb
;
2717 static void bnxt_free_vnic_attributes(struct bnxt
*bp
)
2720 struct bnxt_vnic_info
*vnic
;
2721 struct pci_dev
*pdev
= bp
->pdev
;
2726 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
2727 vnic
= &bp
->vnic_info
[i
];
2729 kfree(vnic
->fw_grp_ids
);
2730 vnic
->fw_grp_ids
= NULL
;
2732 kfree(vnic
->uc_list
);
2733 vnic
->uc_list
= NULL
;
2735 if (vnic
->mc_list
) {
2736 dma_free_coherent(&pdev
->dev
, vnic
->mc_list_size
,
2737 vnic
->mc_list
, vnic
->mc_list_mapping
);
2738 vnic
->mc_list
= NULL
;
2741 if (vnic
->rss_table
) {
2742 dma_free_coherent(&pdev
->dev
, PAGE_SIZE
,
2744 vnic
->rss_table_dma_addr
);
2745 vnic
->rss_table
= NULL
;
2748 vnic
->rss_hash_key
= NULL
;
2753 static int bnxt_alloc_vnic_attributes(struct bnxt
*bp
)
2755 int i
, rc
= 0, size
;
2756 struct bnxt_vnic_info
*vnic
;
2757 struct pci_dev
*pdev
= bp
->pdev
;
2760 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
2761 vnic
= &bp
->vnic_info
[i
];
2763 if (vnic
->flags
& BNXT_VNIC_UCAST_FLAG
) {
2764 int mem_size
= (BNXT_MAX_UC_ADDRS
- 1) * ETH_ALEN
;
2767 vnic
->uc_list
= kmalloc(mem_size
, GFP_KERNEL
);
2768 if (!vnic
->uc_list
) {
2775 if (vnic
->flags
& BNXT_VNIC_MCAST_FLAG
) {
2776 vnic
->mc_list_size
= BNXT_MAX_MC_ADDRS
* ETH_ALEN
;
2778 dma_alloc_coherent(&pdev
->dev
,
2780 &vnic
->mc_list_mapping
,
2782 if (!vnic
->mc_list
) {
2788 if (vnic
->flags
& BNXT_VNIC_RSS_FLAG
)
2789 max_rings
= bp
->rx_nr_rings
;
2793 vnic
->fw_grp_ids
= kcalloc(max_rings
, sizeof(u16
), GFP_KERNEL
);
2794 if (!vnic
->fw_grp_ids
) {
2799 if ((bp
->flags
& BNXT_FLAG_NEW_RSS_CAP
) &&
2800 !(vnic
->flags
& BNXT_VNIC_RSS_FLAG
))
2803 /* Allocate rss table and hash key */
2804 vnic
->rss_table
= dma_alloc_coherent(&pdev
->dev
, PAGE_SIZE
,
2805 &vnic
->rss_table_dma_addr
,
2807 if (!vnic
->rss_table
) {
2812 size
= L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE
* sizeof(u16
));
2814 vnic
->rss_hash_key
= ((void *)vnic
->rss_table
) + size
;
2815 vnic
->rss_hash_key_dma_addr
= vnic
->rss_table_dma_addr
+ size
;
2823 static void bnxt_free_hwrm_resources(struct bnxt
*bp
)
2825 struct pci_dev
*pdev
= bp
->pdev
;
2827 dma_free_coherent(&pdev
->dev
, PAGE_SIZE
, bp
->hwrm_cmd_resp_addr
,
2828 bp
->hwrm_cmd_resp_dma_addr
);
2830 bp
->hwrm_cmd_resp_addr
= NULL
;
2831 if (bp
->hwrm_dbg_resp_addr
) {
2832 dma_free_coherent(&pdev
->dev
, HWRM_DBG_REG_BUF_SIZE
,
2833 bp
->hwrm_dbg_resp_addr
,
2834 bp
->hwrm_dbg_resp_dma_addr
);
2836 bp
->hwrm_dbg_resp_addr
= NULL
;
2840 static int bnxt_alloc_hwrm_resources(struct bnxt
*bp
)
2842 struct pci_dev
*pdev
= bp
->pdev
;
2844 bp
->hwrm_cmd_resp_addr
= dma_alloc_coherent(&pdev
->dev
, PAGE_SIZE
,
2845 &bp
->hwrm_cmd_resp_dma_addr
,
2847 if (!bp
->hwrm_cmd_resp_addr
)
2849 bp
->hwrm_dbg_resp_addr
= dma_alloc_coherent(&pdev
->dev
,
2850 HWRM_DBG_REG_BUF_SIZE
,
2851 &bp
->hwrm_dbg_resp_dma_addr
,
2853 if (!bp
->hwrm_dbg_resp_addr
)
2854 netdev_warn(bp
->dev
, "fail to alloc debug register dma mem\n");
2859 static void bnxt_free_stats(struct bnxt
*bp
)
2862 struct pci_dev
*pdev
= bp
->pdev
;
2864 if (bp
->hw_rx_port_stats
) {
2865 dma_free_coherent(&pdev
->dev
, bp
->hw_port_stats_size
,
2866 bp
->hw_rx_port_stats
,
2867 bp
->hw_rx_port_stats_map
);
2868 bp
->hw_rx_port_stats
= NULL
;
2869 bp
->flags
&= ~BNXT_FLAG_PORT_STATS
;
2875 size
= sizeof(struct ctx_hw_stats
);
2877 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2878 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2879 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
2881 if (cpr
->hw_stats
) {
2882 dma_free_coherent(&pdev
->dev
, size
, cpr
->hw_stats
,
2884 cpr
->hw_stats
= NULL
;
2889 static int bnxt_alloc_stats(struct bnxt
*bp
)
2892 struct pci_dev
*pdev
= bp
->pdev
;
2894 size
= sizeof(struct ctx_hw_stats
);
2896 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2897 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2898 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
2900 cpr
->hw_stats
= dma_alloc_coherent(&pdev
->dev
, size
,
2906 cpr
->hw_stats_ctx_id
= INVALID_STATS_CTX_ID
;
2909 if (BNXT_PF(bp
) && bp
->chip_num
!= CHIP_NUM_58700
) {
2910 bp
->hw_port_stats_size
= sizeof(struct rx_port_stats
) +
2911 sizeof(struct tx_port_stats
) + 1024;
2913 bp
->hw_rx_port_stats
=
2914 dma_alloc_coherent(&pdev
->dev
, bp
->hw_port_stats_size
,
2915 &bp
->hw_rx_port_stats_map
,
2917 if (!bp
->hw_rx_port_stats
)
2920 bp
->hw_tx_port_stats
= (void *)(bp
->hw_rx_port_stats
+ 1) +
2922 bp
->hw_tx_port_stats_map
= bp
->hw_rx_port_stats_map
+
2923 sizeof(struct rx_port_stats
) + 512;
2924 bp
->flags
|= BNXT_FLAG_PORT_STATS
;
2929 static void bnxt_clear_ring_indices(struct bnxt
*bp
)
2936 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2937 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2938 struct bnxt_cp_ring_info
*cpr
;
2939 struct bnxt_rx_ring_info
*rxr
;
2940 struct bnxt_tx_ring_info
*txr
;
2945 cpr
= &bnapi
->cp_ring
;
2946 cpr
->cp_raw_cons
= 0;
2948 txr
= bnapi
->tx_ring
;
2954 rxr
= bnapi
->rx_ring
;
2957 rxr
->rx_agg_prod
= 0;
2958 rxr
->rx_sw_agg_prod
= 0;
2959 rxr
->rx_next_cons
= 0;
2964 static void bnxt_free_ntp_fltrs(struct bnxt
*bp
, bool irq_reinit
)
2966 #ifdef CONFIG_RFS_ACCEL
2969 /* Under rtnl_lock and all our NAPIs have been disabled. It's
2970 * safe to delete the hash table.
2972 for (i
= 0; i
< BNXT_NTP_FLTR_HASH_SIZE
; i
++) {
2973 struct hlist_head
*head
;
2974 struct hlist_node
*tmp
;
2975 struct bnxt_ntuple_filter
*fltr
;
2977 head
= &bp
->ntp_fltr_hash_tbl
[i
];
2978 hlist_for_each_entry_safe(fltr
, tmp
, head
, hash
) {
2979 hlist_del(&fltr
->hash
);
2984 kfree(bp
->ntp_fltr_bmap
);
2985 bp
->ntp_fltr_bmap
= NULL
;
2987 bp
->ntp_fltr_count
= 0;
2991 static int bnxt_alloc_ntp_fltrs(struct bnxt
*bp
)
2993 #ifdef CONFIG_RFS_ACCEL
2996 if (!(bp
->flags
& BNXT_FLAG_RFS
))
2999 for (i
= 0; i
< BNXT_NTP_FLTR_HASH_SIZE
; i
++)
3000 INIT_HLIST_HEAD(&bp
->ntp_fltr_hash_tbl
[i
]);
3002 bp
->ntp_fltr_count
= 0;
3003 bp
->ntp_fltr_bmap
= kzalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR
),
3006 if (!bp
->ntp_fltr_bmap
)
3015 static void bnxt_free_mem(struct bnxt
*bp
, bool irq_re_init
)
3017 bnxt_free_vnic_attributes(bp
);
3018 bnxt_free_tx_rings(bp
);
3019 bnxt_free_rx_rings(bp
);
3020 bnxt_free_cp_rings(bp
);
3021 bnxt_free_ntp_fltrs(bp
, irq_re_init
);
3023 bnxt_free_stats(bp
);
3024 bnxt_free_ring_grps(bp
);
3025 bnxt_free_vnics(bp
);
3026 kfree(bp
->tx_ring_map
);
3027 bp
->tx_ring_map
= NULL
;
3035 bnxt_clear_ring_indices(bp
);
3039 static int bnxt_alloc_mem(struct bnxt
*bp
, bool irq_re_init
)
3041 int i
, j
, rc
, size
, arr_size
;
3045 /* Allocate bnapi mem pointer array and mem block for
3048 arr_size
= L1_CACHE_ALIGN(sizeof(struct bnxt_napi
*) *
3050 size
= L1_CACHE_ALIGN(sizeof(struct bnxt_napi
));
3051 bnapi
= kzalloc(arr_size
+ size
* bp
->cp_nr_rings
, GFP_KERNEL
);
3057 for (i
= 0; i
< bp
->cp_nr_rings
; i
++, bnapi
+= size
) {
3058 bp
->bnapi
[i
] = bnapi
;
3059 bp
->bnapi
[i
]->index
= i
;
3060 bp
->bnapi
[i
]->bp
= bp
;
3063 bp
->rx_ring
= kcalloc(bp
->rx_nr_rings
,
3064 sizeof(struct bnxt_rx_ring_info
),
3069 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3070 bp
->rx_ring
[i
].bnapi
= bp
->bnapi
[i
];
3071 bp
->bnapi
[i
]->rx_ring
= &bp
->rx_ring
[i
];
3074 bp
->tx_ring
= kcalloc(bp
->tx_nr_rings
,
3075 sizeof(struct bnxt_tx_ring_info
),
3080 bp
->tx_ring_map
= kcalloc(bp
->tx_nr_rings
, sizeof(u16
),
3083 if (!bp
->tx_ring_map
)
3086 if (bp
->flags
& BNXT_FLAG_SHARED_RINGS
)
3089 j
= bp
->rx_nr_rings
;
3091 for (i
= 0; i
< bp
->tx_nr_rings
; i
++, j
++) {
3092 bp
->tx_ring
[i
].bnapi
= bp
->bnapi
[j
];
3093 bp
->bnapi
[j
]->tx_ring
= &bp
->tx_ring
[i
];
3094 bp
->tx_ring_map
[i
] = bp
->tx_nr_rings_xdp
+ i
;
3095 if (i
>= bp
->tx_nr_rings_xdp
) {
3096 bp
->tx_ring
[i
].txq_index
= i
-
3097 bp
->tx_nr_rings_xdp
;
3098 bp
->bnapi
[j
]->tx_int
= bnxt_tx_int
;
3100 bp
->bnapi
[j
]->flags
|= BNXT_NAPI_FLAG_XDP
;
3101 bp
->bnapi
[j
]->tx_int
= bnxt_tx_int_xdp
;
3105 rc
= bnxt_alloc_stats(bp
);
3109 rc
= bnxt_alloc_ntp_fltrs(bp
);
3113 rc
= bnxt_alloc_vnics(bp
);
3118 bnxt_init_ring_struct(bp
);
3120 rc
= bnxt_alloc_rx_rings(bp
);
3124 rc
= bnxt_alloc_tx_rings(bp
);
3128 rc
= bnxt_alloc_cp_rings(bp
);
3132 bp
->vnic_info
[0].flags
|= BNXT_VNIC_RSS_FLAG
| BNXT_VNIC_MCAST_FLAG
|
3133 BNXT_VNIC_UCAST_FLAG
;
3134 rc
= bnxt_alloc_vnic_attributes(bp
);
3140 bnxt_free_mem(bp
, true);
3144 static void bnxt_disable_int(struct bnxt
*bp
)
3151 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3152 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3153 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3154 struct bnxt_ring_struct
*ring
= &cpr
->cp_ring_struct
;
3156 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
)
3157 BNXT_CP_DB(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
3161 static void bnxt_disable_int_sync(struct bnxt
*bp
)
3165 atomic_inc(&bp
->intr_sem
);
3167 bnxt_disable_int(bp
);
3168 for (i
= 0; i
< bp
->cp_nr_rings
; i
++)
3169 synchronize_irq(bp
->irq_tbl
[i
].vector
);
3172 static void bnxt_enable_int(struct bnxt
*bp
)
3176 atomic_set(&bp
->intr_sem
, 0);
3177 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3178 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3179 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3181 BNXT_CP_DB_REARM(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
3185 void bnxt_hwrm_cmd_hdr_init(struct bnxt
*bp
, void *request
, u16 req_type
,
3186 u16 cmpl_ring
, u16 target_id
)
3188 struct input
*req
= request
;
3190 req
->req_type
= cpu_to_le16(req_type
);
3191 req
->cmpl_ring
= cpu_to_le16(cmpl_ring
);
3192 req
->target_id
= cpu_to_le16(target_id
);
3193 req
->resp_addr
= cpu_to_le64(bp
->hwrm_cmd_resp_dma_addr
);
3196 static int bnxt_hwrm_do_send_msg(struct bnxt
*bp
, void *msg
, u32 msg_len
,
3197 int timeout
, bool silent
)
3199 int i
, intr_process
, rc
, tmo_count
;
3200 struct input
*req
= msg
;
3202 __le32
*resp_len
, *valid
;
3203 u16 cp_ring_id
, len
= 0;
3204 struct hwrm_err_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3206 req
->seq_id
= cpu_to_le16(bp
->hwrm_cmd_seq
++);
3207 memset(resp
, 0, PAGE_SIZE
);
3208 cp_ring_id
= le16_to_cpu(req
->cmpl_ring
);
3209 intr_process
= (cp_ring_id
== INVALID_HW_RING_ID
) ? 0 : 1;
3211 /* Write request msg to hwrm channel */
3212 __iowrite32_copy(bp
->bar0
, data
, msg_len
/ 4);
3214 for (i
= msg_len
; i
< BNXT_HWRM_MAX_REQ_LEN
; i
+= 4)
3215 writel(0, bp
->bar0
+ i
);
3217 /* currently supports only one outstanding message */
3219 bp
->hwrm_intr_seq_id
= le16_to_cpu(req
->seq_id
);
3221 /* Ring channel doorbell */
3222 writel(1, bp
->bar0
+ 0x100);
3225 timeout
= DFLT_HWRM_CMD_TIMEOUT
;
3228 tmo_count
= timeout
* 40;
3230 /* Wait until hwrm response cmpl interrupt is processed */
3231 while (bp
->hwrm_intr_seq_id
!= HWRM_SEQ_ID_INVALID
&&
3233 usleep_range(25, 40);
3236 if (bp
->hwrm_intr_seq_id
!= HWRM_SEQ_ID_INVALID
) {
3237 netdev_err(bp
->dev
, "Resp cmpl intr err msg: 0x%x\n",
3238 le16_to_cpu(req
->req_type
));
3242 /* Check if response len is updated */
3243 resp_len
= bp
->hwrm_cmd_resp_addr
+ HWRM_RESP_LEN_OFFSET
;
3244 for (i
= 0; i
< tmo_count
; i
++) {
3245 len
= (le32_to_cpu(*resp_len
) & HWRM_RESP_LEN_MASK
) >>
3249 usleep_range(25, 40);
3252 if (i
>= tmo_count
) {
3253 netdev_err(bp
->dev
, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
3254 timeout
, le16_to_cpu(req
->req_type
),
3255 le16_to_cpu(req
->seq_id
), len
);
3259 /* Last word of resp contains valid bit */
3260 valid
= bp
->hwrm_cmd_resp_addr
+ len
- 4;
3261 for (i
= 0; i
< 5; i
++) {
3262 if (le32_to_cpu(*valid
) & HWRM_RESP_VALID_MASK
)
3268 netdev_err(bp
->dev
, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
3269 timeout
, le16_to_cpu(req
->req_type
),
3270 le16_to_cpu(req
->seq_id
), len
, *valid
);
3275 rc
= le16_to_cpu(resp
->error_code
);
3277 netdev_err(bp
->dev
, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
3278 le16_to_cpu(resp
->req_type
),
3279 le16_to_cpu(resp
->seq_id
), rc
);
3283 int _hwrm_send_message(struct bnxt
*bp
, void *msg
, u32 msg_len
, int timeout
)
3285 return bnxt_hwrm_do_send_msg(bp
, msg
, msg_len
, timeout
, false);
3288 int hwrm_send_message(struct bnxt
*bp
, void *msg
, u32 msg_len
, int timeout
)
3292 mutex_lock(&bp
->hwrm_cmd_lock
);
3293 rc
= _hwrm_send_message(bp
, msg
, msg_len
, timeout
);
3294 mutex_unlock(&bp
->hwrm_cmd_lock
);
3298 int hwrm_send_message_silent(struct bnxt
*bp
, void *msg
, u32 msg_len
,
3303 mutex_lock(&bp
->hwrm_cmd_lock
);
3304 rc
= bnxt_hwrm_do_send_msg(bp
, msg
, msg_len
, timeout
, true);
3305 mutex_unlock(&bp
->hwrm_cmd_lock
);
3309 int bnxt_hwrm_func_rgtr_async_events(struct bnxt
*bp
, unsigned long *bmap
,
3312 struct hwrm_func_drv_rgtr_input req
= {0};
3313 DECLARE_BITMAP(async_events_bmap
, 256);
3314 u32
*events
= (u32
*)async_events_bmap
;
3317 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_DRV_RGTR
, -1, -1);
3320 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD
);
3322 memset(async_events_bmap
, 0, sizeof(async_events_bmap
));
3323 for (i
= 0; i
< ARRAY_SIZE(bnxt_async_events_arr
); i
++)
3324 __set_bit(bnxt_async_events_arr
[i
], async_events_bmap
);
3326 if (bmap
&& bmap_size
) {
3327 for (i
= 0; i
< bmap_size
; i
++) {
3328 if (test_bit(i
, bmap
))
3329 __set_bit(i
, async_events_bmap
);
3333 for (i
= 0; i
< 8; i
++)
3334 req
.async_event_fwd
[i
] |= cpu_to_le32(events
[i
]);
3336 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3339 static int bnxt_hwrm_func_drv_rgtr(struct bnxt
*bp
)
3341 struct hwrm_func_drv_rgtr_input req
= {0};
3343 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_DRV_RGTR
, -1, -1);
3346 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE
|
3347 FUNC_DRV_RGTR_REQ_ENABLES_VER
);
3349 req
.os_type
= cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX
);
3350 req
.ver_maj
= DRV_VER_MAJ
;
3351 req
.ver_min
= DRV_VER_MIN
;
3352 req
.ver_upd
= DRV_VER_UPD
;
3355 DECLARE_BITMAP(vf_req_snif_bmap
, 256);
3356 u32
*data
= (u32
*)vf_req_snif_bmap
;
3359 memset(vf_req_snif_bmap
, 0, sizeof(vf_req_snif_bmap
));
3360 for (i
= 0; i
< ARRAY_SIZE(bnxt_vf_req_snif
); i
++)
3361 __set_bit(bnxt_vf_req_snif
[i
], vf_req_snif_bmap
);
3363 for (i
= 0; i
< 8; i
++)
3364 req
.vf_req_fwd
[i
] = cpu_to_le32(data
[i
]);
3367 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD
);
3370 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3373 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt
*bp
)
3375 struct hwrm_func_drv_unrgtr_input req
= {0};
3377 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_DRV_UNRGTR
, -1, -1);
3378 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3381 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt
*bp
, u8 tunnel_type
)
3384 struct hwrm_tunnel_dst_port_free_input req
= {0};
3386 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_TUNNEL_DST_PORT_FREE
, -1, -1);
3387 req
.tunnel_type
= tunnel_type
;
3389 switch (tunnel_type
) {
3390 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
:
3391 req
.tunnel_dst_port_id
= bp
->vxlan_fw_dst_port_id
;
3393 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
:
3394 req
.tunnel_dst_port_id
= bp
->nge_fw_dst_port_id
;
3400 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3402 netdev_err(bp
->dev
, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
3407 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt
*bp
, __be16 port
,
3411 struct hwrm_tunnel_dst_port_alloc_input req
= {0};
3412 struct hwrm_tunnel_dst_port_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3414 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_TUNNEL_DST_PORT_ALLOC
, -1, -1);
3416 req
.tunnel_type
= tunnel_type
;
3417 req
.tunnel_dst_port_val
= port
;
3419 mutex_lock(&bp
->hwrm_cmd_lock
);
3420 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3422 netdev_err(bp
->dev
, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
3427 switch (tunnel_type
) {
3428 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN
:
3429 bp
->vxlan_fw_dst_port_id
= resp
->tunnel_dst_port_id
;
3431 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE
:
3432 bp
->nge_fw_dst_port_id
= resp
->tunnel_dst_port_id
;
3439 mutex_unlock(&bp
->hwrm_cmd_lock
);
3443 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt
*bp
, u16 vnic_id
)
3445 struct hwrm_cfa_l2_set_rx_mask_input req
= {0};
3446 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
3448 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_L2_SET_RX_MASK
, -1, -1);
3449 req
.vnic_id
= cpu_to_le32(vnic
->fw_vnic_id
);
3451 req
.num_mc_entries
= cpu_to_le32(vnic
->mc_list_count
);
3452 req
.mc_tbl_addr
= cpu_to_le64(vnic
->mc_list_mapping
);
3453 req
.mask
= cpu_to_le32(vnic
->rx_mask
);
3454 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3457 #ifdef CONFIG_RFS_ACCEL
3458 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt
*bp
,
3459 struct bnxt_ntuple_filter
*fltr
)
3461 struct hwrm_cfa_ntuple_filter_free_input req
= {0};
3463 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_NTUPLE_FILTER_FREE
, -1, -1);
3464 req
.ntuple_filter_id
= fltr
->filter_id
;
3465 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3468 #define BNXT_NTP_FLTR_FLAGS \
3469 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
3470 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
3471 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
3472 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
3473 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
3474 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
3475 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
3476 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
3477 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
3478 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
3479 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
3480 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
3481 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
3482 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
3484 #define BNXT_NTP_TUNNEL_FLTR_FLAG \
3485 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE
3487 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt
*bp
,
3488 struct bnxt_ntuple_filter
*fltr
)
3491 struct hwrm_cfa_ntuple_filter_alloc_input req
= {0};
3492 struct hwrm_cfa_ntuple_filter_alloc_output
*resp
=
3493 bp
->hwrm_cmd_resp_addr
;
3494 struct flow_keys
*keys
= &fltr
->fkeys
;
3495 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[fltr
->rxq
+ 1];
3497 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_NTUPLE_FILTER_ALLOC
, -1, -1);
3498 req
.l2_filter_id
= bp
->vnic_info
[0].fw_l2_filter_id
[fltr
->l2_fltr_idx
];
3500 req
.enables
= cpu_to_le32(BNXT_NTP_FLTR_FLAGS
);
3502 req
.ethertype
= htons(ETH_P_IP
);
3503 memcpy(req
.src_macaddr
, fltr
->src_mac_addr
, ETH_ALEN
);
3504 req
.ip_addr_type
= CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4
;
3505 req
.ip_protocol
= keys
->basic
.ip_proto
;
3507 if (keys
->basic
.n_proto
== htons(ETH_P_IPV6
)) {
3510 req
.ethertype
= htons(ETH_P_IPV6
);
3512 CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6
;
3513 *(struct in6_addr
*)&req
.src_ipaddr
[0] =
3514 keys
->addrs
.v6addrs
.src
;
3515 *(struct in6_addr
*)&req
.dst_ipaddr
[0] =
3516 keys
->addrs
.v6addrs
.dst
;
3517 for (i
= 0; i
< 4; i
++) {
3518 req
.src_ipaddr_mask
[i
] = cpu_to_be32(0xffffffff);
3519 req
.dst_ipaddr_mask
[i
] = cpu_to_be32(0xffffffff);
3522 req
.src_ipaddr
[0] = keys
->addrs
.v4addrs
.src
;
3523 req
.src_ipaddr_mask
[0] = cpu_to_be32(0xffffffff);
3524 req
.dst_ipaddr
[0] = keys
->addrs
.v4addrs
.dst
;
3525 req
.dst_ipaddr_mask
[0] = cpu_to_be32(0xffffffff);
3527 if (keys
->control
.flags
& FLOW_DIS_ENCAPSULATION
) {
3528 req
.enables
|= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG
);
3530 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
;
3533 req
.src_port
= keys
->ports
.src
;
3534 req
.src_port_mask
= cpu_to_be16(0xffff);
3535 req
.dst_port
= keys
->ports
.dst
;
3536 req
.dst_port_mask
= cpu_to_be16(0xffff);
3538 req
.dst_id
= cpu_to_le16(vnic
->fw_vnic_id
);
3539 mutex_lock(&bp
->hwrm_cmd_lock
);
3540 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3542 fltr
->filter_id
= resp
->ntuple_filter_id
;
3543 mutex_unlock(&bp
->hwrm_cmd_lock
);
3548 static int bnxt_hwrm_set_vnic_filter(struct bnxt
*bp
, u16 vnic_id
, u16 idx
,
3552 struct hwrm_cfa_l2_filter_alloc_input req
= {0};
3553 struct hwrm_cfa_l2_filter_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3555 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_L2_FILTER_ALLOC
, -1, -1);
3556 req
.flags
= cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX
);
3557 if (!BNXT_CHIP_TYPE_NITRO_A0(bp
))
3559 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST
);
3560 req
.dst_id
= cpu_to_le16(bp
->vnic_info
[vnic_id
].fw_vnic_id
);
3562 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR
|
3563 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID
|
3564 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK
);
3565 memcpy(req
.l2_addr
, mac_addr
, ETH_ALEN
);
3566 req
.l2_addr_mask
[0] = 0xff;
3567 req
.l2_addr_mask
[1] = 0xff;
3568 req
.l2_addr_mask
[2] = 0xff;
3569 req
.l2_addr_mask
[3] = 0xff;
3570 req
.l2_addr_mask
[4] = 0xff;
3571 req
.l2_addr_mask
[5] = 0xff;
3573 mutex_lock(&bp
->hwrm_cmd_lock
);
3574 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3576 bp
->vnic_info
[vnic_id
].fw_l2_filter_id
[idx
] =
3578 mutex_unlock(&bp
->hwrm_cmd_lock
);
3582 static int bnxt_hwrm_clear_vnic_filter(struct bnxt
*bp
)
3584 u16 i
, j
, num_of_vnics
= 1; /* only vnic 0 supported */
3587 /* Any associated ntuple filters will also be cleared by firmware. */
3588 mutex_lock(&bp
->hwrm_cmd_lock
);
3589 for (i
= 0; i
< num_of_vnics
; i
++) {
3590 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[i
];
3592 for (j
= 0; j
< vnic
->uc_filter_count
; j
++) {
3593 struct hwrm_cfa_l2_filter_free_input req
= {0};
3595 bnxt_hwrm_cmd_hdr_init(bp
, &req
,
3596 HWRM_CFA_L2_FILTER_FREE
, -1, -1);
3598 req
.l2_filter_id
= vnic
->fw_l2_filter_id
[j
];
3600 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3603 vnic
->uc_filter_count
= 0;
3605 mutex_unlock(&bp
->hwrm_cmd_lock
);
3610 static int bnxt_hwrm_vnic_set_tpa(struct bnxt
*bp
, u16 vnic_id
, u32 tpa_flags
)
3612 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
3613 struct hwrm_vnic_tpa_cfg_input req
= {0};
3615 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_TPA_CFG
, -1, -1);
3618 u16 mss
= bp
->dev
->mtu
- 40;
3619 u32 nsegs
, n
, segs
= 0, flags
;
3621 flags
= VNIC_TPA_CFG_REQ_FLAGS_TPA
|
3622 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA
|
3623 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE
|
3624 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN
|
3625 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ
;
3626 if (tpa_flags
& BNXT_FLAG_GRO
)
3627 flags
|= VNIC_TPA_CFG_REQ_FLAGS_GRO
;
3629 req
.flags
= cpu_to_le32(flags
);
3632 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS
|
3633 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS
|
3634 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN
);
3636 /* Number of segs are log2 units, and first packet is not
3637 * included as part of this units.
3639 if (mss
<= BNXT_RX_PAGE_SIZE
) {
3640 n
= BNXT_RX_PAGE_SIZE
/ mss
;
3641 nsegs
= (MAX_SKB_FRAGS
- 1) * n
;
3643 n
= mss
/ BNXT_RX_PAGE_SIZE
;
3644 if (mss
& (BNXT_RX_PAGE_SIZE
- 1))
3646 nsegs
= (MAX_SKB_FRAGS
- n
) / n
;
3649 segs
= ilog2(nsegs
);
3650 req
.max_agg_segs
= cpu_to_le16(segs
);
3651 req
.max_aggs
= cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX
);
3653 req
.min_agg_len
= cpu_to_le32(512);
3655 req
.vnic_id
= cpu_to_le16(vnic
->fw_vnic_id
);
3657 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3660 static int bnxt_hwrm_vnic_set_rss(struct bnxt
*bp
, u16 vnic_id
, bool set_rss
)
3662 u32 i
, j
, max_rings
;
3663 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
3664 struct hwrm_vnic_rss_cfg_input req
= {0};
3666 if (vnic
->fw_rss_cos_lb_ctx
[0] == INVALID_HW_RING_ID
)
3669 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_RSS_CFG
, -1, -1);
3671 req
.hash_type
= cpu_to_le32(bp
->rss_hash_cfg
);
3672 if (vnic
->flags
& BNXT_VNIC_RSS_FLAG
) {
3673 if (BNXT_CHIP_TYPE_NITRO_A0(bp
))
3674 max_rings
= bp
->rx_nr_rings
- 1;
3676 max_rings
= bp
->rx_nr_rings
;
3681 /* Fill the RSS indirection table with ring group ids */
3682 for (i
= 0, j
= 0; i
< HW_HASH_INDEX_SIZE
; i
++, j
++) {
3685 vnic
->rss_table
[i
] = cpu_to_le16(vnic
->fw_grp_ids
[j
]);
3688 req
.ring_grp_tbl_addr
= cpu_to_le64(vnic
->rss_table_dma_addr
);
3689 req
.hash_key_tbl_addr
=
3690 cpu_to_le64(vnic
->rss_hash_key_dma_addr
);
3692 req
.rss_ctx_idx
= cpu_to_le16(vnic
->fw_rss_cos_lb_ctx
[0]);
3693 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3696 static int bnxt_hwrm_vnic_set_hds(struct bnxt
*bp
, u16 vnic_id
)
3698 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
3699 struct hwrm_vnic_plcmodes_cfg_input req
= {0};
3701 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_PLCMODES_CFG
, -1, -1);
3702 req
.flags
= cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT
|
3703 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4
|
3704 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6
);
3706 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID
|
3707 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID
);
3708 /* thresholds not implemented in firmware yet */
3709 req
.jumbo_thresh
= cpu_to_le16(bp
->rx_copy_thresh
);
3710 req
.hds_threshold
= cpu_to_le16(bp
->rx_copy_thresh
);
3711 req
.vnic_id
= cpu_to_le32(vnic
->fw_vnic_id
);
3712 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3715 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt
*bp
, u16 vnic_id
,
3718 struct hwrm_vnic_rss_cos_lb_ctx_free_input req
= {0};
3720 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_RSS_COS_LB_CTX_FREE
, -1, -1);
3721 req
.rss_cos_lb_ctx_id
=
3722 cpu_to_le16(bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
[ctx_idx
]);
3724 hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3725 bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
[ctx_idx
] = INVALID_HW_RING_ID
;
3728 static void bnxt_hwrm_vnic_ctx_free(struct bnxt
*bp
)
3732 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
3733 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[i
];
3735 for (j
= 0; j
< BNXT_MAX_CTX_PER_VNIC
; j
++) {
3736 if (vnic
->fw_rss_cos_lb_ctx
[j
] != INVALID_HW_RING_ID
)
3737 bnxt_hwrm_vnic_ctx_free_one(bp
, i
, j
);
3740 bp
->rsscos_nr_ctxs
= 0;
3743 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt
*bp
, u16 vnic_id
, u16 ctx_idx
)
3746 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req
= {0};
3747 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output
*resp
=
3748 bp
->hwrm_cmd_resp_addr
;
3750 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC
, -1,
3753 mutex_lock(&bp
->hwrm_cmd_lock
);
3754 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3756 bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
[ctx_idx
] =
3757 le16_to_cpu(resp
->rss_cos_lb_ctx_id
);
3758 mutex_unlock(&bp
->hwrm_cmd_lock
);
3763 int bnxt_hwrm_vnic_cfg(struct bnxt
*bp
, u16 vnic_id
)
3765 unsigned int ring
= 0, grp_idx
;
3766 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
3767 struct hwrm_vnic_cfg_input req
= {0};
3770 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_CFG
, -1, -1);
3772 req
.enables
= cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP
);
3773 /* Only RSS support for now TBD: COS & LB */
3774 if (vnic
->fw_rss_cos_lb_ctx
[0] != INVALID_HW_RING_ID
) {
3775 req
.rss_rule
= cpu_to_le16(vnic
->fw_rss_cos_lb_ctx
[0]);
3776 req
.enables
|= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE
|
3777 VNIC_CFG_REQ_ENABLES_MRU
);
3778 } else if (vnic
->flags
& BNXT_VNIC_RFS_NEW_RSS_FLAG
) {
3780 cpu_to_le16(bp
->vnic_info
[0].fw_rss_cos_lb_ctx
[0]);
3781 req
.enables
|= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE
|
3782 VNIC_CFG_REQ_ENABLES_MRU
);
3783 req
.flags
|= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE
);
3785 req
.rss_rule
= cpu_to_le16(0xffff);
3788 if (BNXT_CHIP_TYPE_NITRO_A0(bp
) &&
3789 (vnic
->fw_rss_cos_lb_ctx
[0] != INVALID_HW_RING_ID
)) {
3790 req
.cos_rule
= cpu_to_le16(vnic
->fw_rss_cos_lb_ctx
[1]);
3791 req
.enables
|= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE
);
3793 req
.cos_rule
= cpu_to_le16(0xffff);
3796 if (vnic
->flags
& BNXT_VNIC_RSS_FLAG
)
3798 else if (vnic
->flags
& BNXT_VNIC_RFS_FLAG
)
3800 else if ((vnic_id
== 1) && BNXT_CHIP_TYPE_NITRO_A0(bp
))
3801 ring
= bp
->rx_nr_rings
- 1;
3803 grp_idx
= bp
->rx_ring
[ring
].bnapi
->index
;
3804 req
.vnic_id
= cpu_to_le16(vnic
->fw_vnic_id
);
3805 req
.dflt_ring_grp
= cpu_to_le16(bp
->grp_info
[grp_idx
].fw_grp_id
);
3807 req
.lb_rule
= cpu_to_le16(0xffff);
3808 req
.mru
= cpu_to_le16(bp
->dev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+
3811 #ifdef CONFIG_BNXT_SRIOV
3813 def_vlan
= bp
->vf
.vlan
;
3815 if ((bp
->flags
& BNXT_FLAG_STRIP_VLAN
) || def_vlan
)
3816 req
.flags
|= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE
);
3817 if (!vnic_id
&& bnxt_ulp_registered(bp
->edev
, BNXT_ROCE_ULP
))
3819 cpu_to_le32(VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE
);
3821 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3824 static int bnxt_hwrm_vnic_free_one(struct bnxt
*bp
, u16 vnic_id
)
3828 if (bp
->vnic_info
[vnic_id
].fw_vnic_id
!= INVALID_HW_RING_ID
) {
3829 struct hwrm_vnic_free_input req
= {0};
3831 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_FREE
, -1, -1);
3833 cpu_to_le32(bp
->vnic_info
[vnic_id
].fw_vnic_id
);
3835 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3838 bp
->vnic_info
[vnic_id
].fw_vnic_id
= INVALID_HW_RING_ID
;
3843 static void bnxt_hwrm_vnic_free(struct bnxt
*bp
)
3847 for (i
= 0; i
< bp
->nr_vnics
; i
++)
3848 bnxt_hwrm_vnic_free_one(bp
, i
);
3851 static int bnxt_hwrm_vnic_alloc(struct bnxt
*bp
, u16 vnic_id
,
3852 unsigned int start_rx_ring_idx
,
3853 unsigned int nr_rings
)
3856 unsigned int i
, j
, grp_idx
, end_idx
= start_rx_ring_idx
+ nr_rings
;
3857 struct hwrm_vnic_alloc_input req
= {0};
3858 struct hwrm_vnic_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3860 /* map ring groups to this vnic */
3861 for (i
= start_rx_ring_idx
, j
= 0; i
< end_idx
; i
++, j
++) {
3862 grp_idx
= bp
->rx_ring
[i
].bnapi
->index
;
3863 if (bp
->grp_info
[grp_idx
].fw_grp_id
== INVALID_HW_RING_ID
) {
3864 netdev_err(bp
->dev
, "Not enough ring groups avail:%x req:%x\n",
3868 bp
->vnic_info
[vnic_id
].fw_grp_ids
[j
] =
3869 bp
->grp_info
[grp_idx
].fw_grp_id
;
3872 bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
[0] = INVALID_HW_RING_ID
;
3873 bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
[1] = INVALID_HW_RING_ID
;
3875 req
.flags
= cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT
);
3877 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_ALLOC
, -1, -1);
3879 mutex_lock(&bp
->hwrm_cmd_lock
);
3880 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3882 bp
->vnic_info
[vnic_id
].fw_vnic_id
= le32_to_cpu(resp
->vnic_id
);
3883 mutex_unlock(&bp
->hwrm_cmd_lock
);
3887 static int bnxt_hwrm_vnic_qcaps(struct bnxt
*bp
)
3889 struct hwrm_vnic_qcaps_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3890 struct hwrm_vnic_qcaps_input req
= {0};
3893 if (bp
->hwrm_spec_code
< 0x10600)
3896 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_QCAPS
, -1, -1);
3897 mutex_lock(&bp
->hwrm_cmd_lock
);
3898 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3901 cpu_to_le32(VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP
))
3902 bp
->flags
|= BNXT_FLAG_NEW_RSS_CAP
;
3904 mutex_unlock(&bp
->hwrm_cmd_lock
);
3908 static int bnxt_hwrm_ring_grp_alloc(struct bnxt
*bp
)
3913 mutex_lock(&bp
->hwrm_cmd_lock
);
3914 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3915 struct hwrm_ring_grp_alloc_input req
= {0};
3916 struct hwrm_ring_grp_alloc_output
*resp
=
3917 bp
->hwrm_cmd_resp_addr
;
3918 unsigned int grp_idx
= bp
->rx_ring
[i
].bnapi
->index
;
3920 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_GRP_ALLOC
, -1, -1);
3922 req
.cr
= cpu_to_le16(bp
->grp_info
[grp_idx
].cp_fw_ring_id
);
3923 req
.rr
= cpu_to_le16(bp
->grp_info
[grp_idx
].rx_fw_ring_id
);
3924 req
.ar
= cpu_to_le16(bp
->grp_info
[grp_idx
].agg_fw_ring_id
);
3925 req
.sc
= cpu_to_le16(bp
->grp_info
[grp_idx
].fw_stats_ctx
);
3927 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3932 bp
->grp_info
[grp_idx
].fw_grp_id
=
3933 le32_to_cpu(resp
->ring_group_id
);
3935 mutex_unlock(&bp
->hwrm_cmd_lock
);
3939 static int bnxt_hwrm_ring_grp_free(struct bnxt
*bp
)
3943 struct hwrm_ring_grp_free_input req
= {0};
3948 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_GRP_FREE
, -1, -1);
3950 mutex_lock(&bp
->hwrm_cmd_lock
);
3951 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3952 if (bp
->grp_info
[i
].fw_grp_id
== INVALID_HW_RING_ID
)
3955 cpu_to_le32(bp
->grp_info
[i
].fw_grp_id
);
3957 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3961 bp
->grp_info
[i
].fw_grp_id
= INVALID_HW_RING_ID
;
3963 mutex_unlock(&bp
->hwrm_cmd_lock
);
3967 static int hwrm_ring_alloc_send_msg(struct bnxt
*bp
,
3968 struct bnxt_ring_struct
*ring
,
3969 u32 ring_type
, u32 map_index
,
3972 int rc
= 0, err
= 0;
3973 struct hwrm_ring_alloc_input req
= {0};
3974 struct hwrm_ring_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3977 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_ALLOC
, -1, -1);
3980 if (ring
->nr_pages
> 1) {
3981 req
.page_tbl_addr
= cpu_to_le64(ring
->pg_tbl_map
);
3982 /* Page size is in log2 units */
3983 req
.page_size
= BNXT_PAGE_SHIFT
;
3984 req
.page_tbl_depth
= 1;
3986 req
.page_tbl_addr
= cpu_to_le64(ring
->dma_arr
[0]);
3989 /* Association of ring index with doorbell index and MSIX number */
3990 req
.logical_id
= cpu_to_le16(map_index
);
3992 switch (ring_type
) {
3993 case HWRM_RING_ALLOC_TX
:
3994 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_TX
;
3995 /* Association of transmit ring with completion ring */
3997 cpu_to_le16(bp
->grp_info
[map_index
].cp_fw_ring_id
);
3998 req
.length
= cpu_to_le32(bp
->tx_ring_mask
+ 1);
3999 req
.stat_ctx_id
= cpu_to_le32(stats_ctx_id
);
4000 req
.queue_id
= cpu_to_le16(ring
->queue_id
);
4002 case HWRM_RING_ALLOC_RX
:
4003 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_RX
;
4004 req
.length
= cpu_to_le32(bp
->rx_ring_mask
+ 1);
4006 case HWRM_RING_ALLOC_AGG
:
4007 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_RX
;
4008 req
.length
= cpu_to_le32(bp
->rx_agg_ring_mask
+ 1);
4010 case HWRM_RING_ALLOC_CMPL
:
4011 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_L2_CMPL
;
4012 req
.length
= cpu_to_le32(bp
->cp_ring_mask
+ 1);
4013 if (bp
->flags
& BNXT_FLAG_USING_MSIX
)
4014 req
.int_mode
= RING_ALLOC_REQ_INT_MODE_MSIX
;
4017 netdev_err(bp
->dev
, "hwrm alloc invalid ring type %d\n",
4022 mutex_lock(&bp
->hwrm_cmd_lock
);
4023 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4024 err
= le16_to_cpu(resp
->error_code
);
4025 ring_id
= le16_to_cpu(resp
->ring_id
);
4026 mutex_unlock(&bp
->hwrm_cmd_lock
);
4029 switch (ring_type
) {
4030 case RING_FREE_REQ_RING_TYPE_L2_CMPL
:
4031 netdev_err(bp
->dev
, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
4035 case RING_FREE_REQ_RING_TYPE_RX
:
4036 netdev_err(bp
->dev
, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
4040 case RING_FREE_REQ_RING_TYPE_TX
:
4041 netdev_err(bp
->dev
, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
4046 netdev_err(bp
->dev
, "Invalid ring\n");
4050 ring
->fw_ring_id
= ring_id
;
4054 static int bnxt_hwrm_set_async_event_cr(struct bnxt
*bp
, int idx
)
4059 struct hwrm_func_cfg_input req
= {0};
4061 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_CFG
, -1, -1);
4062 req
.fid
= cpu_to_le16(0xffff);
4063 req
.enables
= cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR
);
4064 req
.async_event_cr
= cpu_to_le16(idx
);
4065 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4067 struct hwrm_func_vf_cfg_input req
= {0};
4069 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_VF_CFG
, -1, -1);
4071 cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR
);
4072 req
.async_event_cr
= cpu_to_le16(idx
);
4073 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4078 static int bnxt_hwrm_ring_alloc(struct bnxt
*bp
)
4082 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4083 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4084 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
4085 struct bnxt_ring_struct
*ring
= &cpr
->cp_ring_struct
;
4087 cpr
->cp_doorbell
= bp
->bar1
+ i
* 0x80;
4088 rc
= hwrm_ring_alloc_send_msg(bp
, ring
, HWRM_RING_ALLOC_CMPL
, i
,
4089 INVALID_STATS_CTX_ID
);
4092 BNXT_CP_DB(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
4093 bp
->grp_info
[i
].cp_fw_ring_id
= ring
->fw_ring_id
;
4096 rc
= bnxt_hwrm_set_async_event_cr(bp
, ring
->fw_ring_id
);
4098 netdev_warn(bp
->dev
, "Failed to set async event completion ring.\n");
4102 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
4103 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
4104 struct bnxt_ring_struct
*ring
= &txr
->tx_ring_struct
;
4105 u32 map_idx
= txr
->bnapi
->index
;
4106 u16 fw_stats_ctx
= bp
->grp_info
[map_idx
].fw_stats_ctx
;
4108 rc
= hwrm_ring_alloc_send_msg(bp
, ring
, HWRM_RING_ALLOC_TX
,
4109 map_idx
, fw_stats_ctx
);
4112 txr
->tx_doorbell
= bp
->bar1
+ map_idx
* 0x80;
4115 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
4116 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
4117 struct bnxt_ring_struct
*ring
= &rxr
->rx_ring_struct
;
4118 u32 map_idx
= rxr
->bnapi
->index
;
4120 rc
= hwrm_ring_alloc_send_msg(bp
, ring
, HWRM_RING_ALLOC_RX
,
4121 map_idx
, INVALID_STATS_CTX_ID
);
4124 rxr
->rx_doorbell
= bp
->bar1
+ map_idx
* 0x80;
4125 writel(DB_KEY_RX
| rxr
->rx_prod
, rxr
->rx_doorbell
);
4126 bp
->grp_info
[map_idx
].rx_fw_ring_id
= ring
->fw_ring_id
;
4129 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
) {
4130 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
4131 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
4132 struct bnxt_ring_struct
*ring
=
4133 &rxr
->rx_agg_ring_struct
;
4134 u32 grp_idx
= rxr
->bnapi
->index
;
4135 u32 map_idx
= grp_idx
+ bp
->rx_nr_rings
;
4137 rc
= hwrm_ring_alloc_send_msg(bp
, ring
,
4138 HWRM_RING_ALLOC_AGG
,
4140 INVALID_STATS_CTX_ID
);
4144 rxr
->rx_agg_doorbell
= bp
->bar1
+ map_idx
* 0x80;
4145 writel(DB_KEY_RX
| rxr
->rx_agg_prod
,
4146 rxr
->rx_agg_doorbell
);
4147 bp
->grp_info
[grp_idx
].agg_fw_ring_id
= ring
->fw_ring_id
;
4154 static int hwrm_ring_free_send_msg(struct bnxt
*bp
,
4155 struct bnxt_ring_struct
*ring
,
4156 u32 ring_type
, int cmpl_ring_id
)
4159 struct hwrm_ring_free_input req
= {0};
4160 struct hwrm_ring_free_output
*resp
= bp
->hwrm_cmd_resp_addr
;
4163 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_FREE
, cmpl_ring_id
, -1);
4164 req
.ring_type
= ring_type
;
4165 req
.ring_id
= cpu_to_le16(ring
->fw_ring_id
);
4167 mutex_lock(&bp
->hwrm_cmd_lock
);
4168 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4169 error_code
= le16_to_cpu(resp
->error_code
);
4170 mutex_unlock(&bp
->hwrm_cmd_lock
);
4172 if (rc
|| error_code
) {
4173 switch (ring_type
) {
4174 case RING_FREE_REQ_RING_TYPE_L2_CMPL
:
4175 netdev_err(bp
->dev
, "hwrm_ring_free cp failed. rc:%d\n",
4178 case RING_FREE_REQ_RING_TYPE_RX
:
4179 netdev_err(bp
->dev
, "hwrm_ring_free rx failed. rc:%d\n",
4182 case RING_FREE_REQ_RING_TYPE_TX
:
4183 netdev_err(bp
->dev
, "hwrm_ring_free tx failed. rc:%d\n",
4187 netdev_err(bp
->dev
, "Invalid ring\n");
4194 static void bnxt_hwrm_ring_free(struct bnxt
*bp
, bool close_path
)
4201 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
4202 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
4203 struct bnxt_ring_struct
*ring
= &txr
->tx_ring_struct
;
4204 u32 grp_idx
= txr
->bnapi
->index
;
4205 u32 cmpl_ring_id
= bp
->grp_info
[grp_idx
].cp_fw_ring_id
;
4207 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
4208 hwrm_ring_free_send_msg(bp
, ring
,
4209 RING_FREE_REQ_RING_TYPE_TX
,
4210 close_path
? cmpl_ring_id
:
4211 INVALID_HW_RING_ID
);
4212 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
4216 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
4217 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
4218 struct bnxt_ring_struct
*ring
= &rxr
->rx_ring_struct
;
4219 u32 grp_idx
= rxr
->bnapi
->index
;
4220 u32 cmpl_ring_id
= bp
->grp_info
[grp_idx
].cp_fw_ring_id
;
4222 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
4223 hwrm_ring_free_send_msg(bp
, ring
,
4224 RING_FREE_REQ_RING_TYPE_RX
,
4225 close_path
? cmpl_ring_id
:
4226 INVALID_HW_RING_ID
);
4227 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
4228 bp
->grp_info
[grp_idx
].rx_fw_ring_id
=
4233 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
4234 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
4235 struct bnxt_ring_struct
*ring
= &rxr
->rx_agg_ring_struct
;
4236 u32 grp_idx
= rxr
->bnapi
->index
;
4237 u32 cmpl_ring_id
= bp
->grp_info
[grp_idx
].cp_fw_ring_id
;
4239 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
4240 hwrm_ring_free_send_msg(bp
, ring
,
4241 RING_FREE_REQ_RING_TYPE_RX
,
4242 close_path
? cmpl_ring_id
:
4243 INVALID_HW_RING_ID
);
4244 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
4245 bp
->grp_info
[grp_idx
].agg_fw_ring_id
=
4250 /* The completion rings are about to be freed. After that the
4251 * IRQ doorbell will not work anymore. So we need to disable
4254 bnxt_disable_int_sync(bp
);
4256 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4257 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4258 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
4259 struct bnxt_ring_struct
*ring
= &cpr
->cp_ring_struct
;
4261 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
4262 hwrm_ring_free_send_msg(bp
, ring
,
4263 RING_FREE_REQ_RING_TYPE_L2_CMPL
,
4264 INVALID_HW_RING_ID
);
4265 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
4266 bp
->grp_info
[i
].cp_fw_ring_id
= INVALID_HW_RING_ID
;
4271 /* Caller must hold bp->hwrm_cmd_lock */
4272 int __bnxt_hwrm_get_tx_rings(struct bnxt
*bp
, u16 fid
, int *tx_rings
)
4274 struct hwrm_func_qcfg_output
*resp
= bp
->hwrm_cmd_resp_addr
;
4275 struct hwrm_func_qcfg_input req
= {0};
4278 if (bp
->hwrm_spec_code
< 0x10601)
4281 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_QCFG
, -1, -1);
4282 req
.fid
= cpu_to_le16(fid
);
4283 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4285 *tx_rings
= le16_to_cpu(resp
->alloc_tx_rings
);
4290 static int bnxt_hwrm_reserve_tx_rings(struct bnxt
*bp
, int *tx_rings
)
4292 struct hwrm_func_cfg_input req
= {0};
4295 if (bp
->hwrm_spec_code
< 0x10601)
4301 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_CFG
, -1, -1);
4302 req
.fid
= cpu_to_le16(0xffff);
4303 req
.enables
= cpu_to_le32(FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS
);
4304 req
.num_tx_rings
= cpu_to_le16(*tx_rings
);
4305 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4309 mutex_lock(&bp
->hwrm_cmd_lock
);
4310 rc
= __bnxt_hwrm_get_tx_rings(bp
, 0xffff, tx_rings
);
4311 mutex_unlock(&bp
->hwrm_cmd_lock
);
4315 static void bnxt_hwrm_set_coal_params(struct bnxt
*bp
, u32 max_bufs
,
4316 u32 buf_tmrs
, u16 flags
,
4317 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input
*req
)
4319 req
->flags
= cpu_to_le16(flags
);
4320 req
->num_cmpl_dma_aggr
= cpu_to_le16((u16
)max_bufs
);
4321 req
->num_cmpl_dma_aggr_during_int
= cpu_to_le16(max_bufs
>> 16);
4322 req
->cmpl_aggr_dma_tmr
= cpu_to_le16((u16
)buf_tmrs
);
4323 req
->cmpl_aggr_dma_tmr_during_int
= cpu_to_le16(buf_tmrs
>> 16);
4324 /* Minimum time between 2 interrupts set to buf_tmr x 2 */
4325 req
->int_lat_tmr_min
= cpu_to_le16((u16
)buf_tmrs
* 2);
4326 req
->int_lat_tmr_max
= cpu_to_le16((u16
)buf_tmrs
* 4);
4327 req
->num_cmpl_aggr_int
= cpu_to_le16((u16
)max_bufs
* 4);
4330 int bnxt_hwrm_set_coal(struct bnxt
*bp
)
4333 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx
= {0},
4335 u16 max_buf
, max_buf_irq
;
4336 u16 buf_tmr
, buf_tmr_irq
;
4339 bnxt_hwrm_cmd_hdr_init(bp
, &req_rx
,
4340 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS
, -1, -1);
4341 bnxt_hwrm_cmd_hdr_init(bp
, &req_tx
,
4342 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS
, -1, -1);
4344 /* Each rx completion (2 records) should be DMAed immediately.
4345 * DMA 1/4 of the completion buffers at a time.
4347 max_buf
= min_t(u16
, bp
->rx_coal_bufs
/ 4, 2);
4348 /* max_buf must not be zero */
4349 max_buf
= clamp_t(u16
, max_buf
, 1, 63);
4350 max_buf_irq
= clamp_t(u16
, bp
->rx_coal_bufs_irq
, 1, 63);
4351 buf_tmr
= BNXT_USEC_TO_COAL_TIMER(bp
->rx_coal_ticks
);
4352 /* buf timer set to 1/4 of interrupt timer */
4353 buf_tmr
= max_t(u16
, buf_tmr
/ 4, 1);
4354 buf_tmr_irq
= BNXT_USEC_TO_COAL_TIMER(bp
->rx_coal_ticks_irq
);
4355 buf_tmr_irq
= max_t(u16
, buf_tmr_irq
, 1);
4357 flags
= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET
;
4359 /* RING_IDLE generates more IRQs for lower latency. Enable it only
4360 * if coal_ticks is less than 25 us.
4362 if (bp
->rx_coal_ticks
< 25)
4363 flags
|= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE
;
4365 bnxt_hwrm_set_coal_params(bp
, max_buf_irq
<< 16 | max_buf
,
4366 buf_tmr_irq
<< 16 | buf_tmr
, flags
, &req_rx
);
4368 /* max_buf must not be zero */
4369 max_buf
= clamp_t(u16
, bp
->tx_coal_bufs
, 1, 63);
4370 max_buf_irq
= clamp_t(u16
, bp
->tx_coal_bufs_irq
, 1, 63);
4371 buf_tmr
= BNXT_USEC_TO_COAL_TIMER(bp
->tx_coal_ticks
);
4372 /* buf timer set to 1/4 of interrupt timer */
4373 buf_tmr
= max_t(u16
, buf_tmr
/ 4, 1);
4374 buf_tmr_irq
= BNXT_USEC_TO_COAL_TIMER(bp
->tx_coal_ticks_irq
);
4375 buf_tmr_irq
= max_t(u16
, buf_tmr_irq
, 1);
4377 flags
= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET
;
4378 bnxt_hwrm_set_coal_params(bp
, max_buf_irq
<< 16 | max_buf
,
4379 buf_tmr_irq
<< 16 | buf_tmr
, flags
, &req_tx
);
4381 mutex_lock(&bp
->hwrm_cmd_lock
);
4382 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4383 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4386 if (!bnapi
->rx_ring
)
4388 req
->ring_id
= cpu_to_le16(bp
->grp_info
[i
].cp_fw_ring_id
);
4390 rc
= _hwrm_send_message(bp
, req
, sizeof(*req
),
4395 mutex_unlock(&bp
->hwrm_cmd_lock
);
4399 static int bnxt_hwrm_stat_ctx_free(struct bnxt
*bp
)
4402 struct hwrm_stat_ctx_free_input req
= {0};
4407 if (BNXT_CHIP_TYPE_NITRO_A0(bp
))
4410 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_STAT_CTX_FREE
, -1, -1);
4412 mutex_lock(&bp
->hwrm_cmd_lock
);
4413 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4414 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4415 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
4417 if (cpr
->hw_stats_ctx_id
!= INVALID_STATS_CTX_ID
) {
4418 req
.stat_ctx_id
= cpu_to_le32(cpr
->hw_stats_ctx_id
);
4420 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
4425 cpr
->hw_stats_ctx_id
= INVALID_STATS_CTX_ID
;
4428 mutex_unlock(&bp
->hwrm_cmd_lock
);
4432 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt
*bp
)
4435 struct hwrm_stat_ctx_alloc_input req
= {0};
4436 struct hwrm_stat_ctx_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
4438 if (BNXT_CHIP_TYPE_NITRO_A0(bp
))
4441 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_STAT_CTX_ALLOC
, -1, -1);
4443 req
.update_period_ms
= cpu_to_le32(bp
->stats_coal_ticks
/ 1000);
4445 mutex_lock(&bp
->hwrm_cmd_lock
);
4446 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4447 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4448 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
4450 req
.stats_dma_addr
= cpu_to_le64(cpr
->hw_stats_map
);
4452 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
4457 cpr
->hw_stats_ctx_id
= le32_to_cpu(resp
->stat_ctx_id
);
4459 bp
->grp_info
[i
].fw_stats_ctx
= cpr
->hw_stats_ctx_id
;
4461 mutex_unlock(&bp
->hwrm_cmd_lock
);
4465 static int bnxt_hwrm_func_qcfg(struct bnxt
*bp
)
4467 struct hwrm_func_qcfg_input req
= {0};
4468 struct hwrm_func_qcfg_output
*resp
= bp
->hwrm_cmd_resp_addr
;
4471 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_QCFG
, -1, -1);
4472 req
.fid
= cpu_to_le16(0xffff);
4473 mutex_lock(&bp
->hwrm_cmd_lock
);
4474 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4476 goto func_qcfg_exit
;
4478 #ifdef CONFIG_BNXT_SRIOV
4480 struct bnxt_vf_info
*vf
= &bp
->vf
;
4482 vf
->vlan
= le16_to_cpu(resp
->vlan
) & VLAN_VID_MASK
;
4485 if (BNXT_PF(bp
) && (le16_to_cpu(resp
->flags
) &
4486 FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED
))
4487 bp
->flags
|= BNXT_FLAG_FW_LLDP_AGENT
;
4489 switch (resp
->port_partition_type
) {
4490 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0
:
4491 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5
:
4492 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0
:
4493 bp
->port_partition_type
= resp
->port_partition_type
;
4498 mutex_unlock(&bp
->hwrm_cmd_lock
);
4502 static int bnxt_hwrm_func_qcaps(struct bnxt
*bp
)
4505 struct hwrm_func_qcaps_input req
= {0};
4506 struct hwrm_func_qcaps_output
*resp
= bp
->hwrm_cmd_resp_addr
;
4508 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_QCAPS
, -1, -1);
4509 req
.fid
= cpu_to_le16(0xffff);
4511 mutex_lock(&bp
->hwrm_cmd_lock
);
4512 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4514 goto hwrm_func_qcaps_exit
;
4516 if (resp
->flags
& cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED
))
4517 bp
->flags
|= BNXT_FLAG_ROCEV1_CAP
;
4518 if (resp
->flags
& cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED
))
4519 bp
->flags
|= BNXT_FLAG_ROCEV2_CAP
;
4521 bp
->tx_push_thresh
= 0;
4523 cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED
))
4524 bp
->tx_push_thresh
= BNXT_TX_PUSH_THRESH
;
4527 struct bnxt_pf_info
*pf
= &bp
->pf
;
4529 pf
->fw_fid
= le16_to_cpu(resp
->fid
);
4530 pf
->port_id
= le16_to_cpu(resp
->port_id
);
4531 bp
->dev
->dev_port
= pf
->port_id
;
4532 memcpy(pf
->mac_addr
, resp
->mac_address
, ETH_ALEN
);
4533 memcpy(bp
->dev
->dev_addr
, pf
->mac_addr
, ETH_ALEN
);
4534 pf
->max_rsscos_ctxs
= le16_to_cpu(resp
->max_rsscos_ctx
);
4535 pf
->max_cp_rings
= le16_to_cpu(resp
->max_cmpl_rings
);
4536 pf
->max_tx_rings
= le16_to_cpu(resp
->max_tx_rings
);
4537 pf
->max_rx_rings
= le16_to_cpu(resp
->max_rx_rings
);
4538 pf
->max_hw_ring_grps
= le32_to_cpu(resp
->max_hw_ring_grps
);
4539 if (!pf
->max_hw_ring_grps
)
4540 pf
->max_hw_ring_grps
= pf
->max_tx_rings
;
4541 pf
->max_l2_ctxs
= le16_to_cpu(resp
->max_l2_ctxs
);
4542 pf
->max_vnics
= le16_to_cpu(resp
->max_vnics
);
4543 pf
->max_stat_ctxs
= le16_to_cpu(resp
->max_stat_ctx
);
4544 pf
->first_vf_id
= le16_to_cpu(resp
->first_vf_id
);
4545 pf
->max_vfs
= le16_to_cpu(resp
->max_vfs
);
4546 pf
->max_encap_records
= le32_to_cpu(resp
->max_encap_records
);
4547 pf
->max_decap_records
= le32_to_cpu(resp
->max_decap_records
);
4548 pf
->max_tx_em_flows
= le32_to_cpu(resp
->max_tx_em_flows
);
4549 pf
->max_tx_wm_flows
= le32_to_cpu(resp
->max_tx_wm_flows
);
4550 pf
->max_rx_em_flows
= le32_to_cpu(resp
->max_rx_em_flows
);
4551 pf
->max_rx_wm_flows
= le32_to_cpu(resp
->max_rx_wm_flows
);
4553 #ifdef CONFIG_BNXT_SRIOV
4554 struct bnxt_vf_info
*vf
= &bp
->vf
;
4556 vf
->fw_fid
= le16_to_cpu(resp
->fid
);
4558 vf
->max_rsscos_ctxs
= le16_to_cpu(resp
->max_rsscos_ctx
);
4559 vf
->max_cp_rings
= le16_to_cpu(resp
->max_cmpl_rings
);
4560 vf
->max_tx_rings
= le16_to_cpu(resp
->max_tx_rings
);
4561 vf
->max_rx_rings
= le16_to_cpu(resp
->max_rx_rings
);
4562 vf
->max_hw_ring_grps
= le32_to_cpu(resp
->max_hw_ring_grps
);
4563 if (!vf
->max_hw_ring_grps
)
4564 vf
->max_hw_ring_grps
= vf
->max_tx_rings
;
4565 vf
->max_l2_ctxs
= le16_to_cpu(resp
->max_l2_ctxs
);
4566 vf
->max_vnics
= le16_to_cpu(resp
->max_vnics
);
4567 vf
->max_stat_ctxs
= le16_to_cpu(resp
->max_stat_ctx
);
4569 memcpy(vf
->mac_addr
, resp
->mac_address
, ETH_ALEN
);
4570 mutex_unlock(&bp
->hwrm_cmd_lock
);
4572 if (is_valid_ether_addr(vf
->mac_addr
)) {
4573 /* overwrite netdev dev_adr with admin VF MAC */
4574 memcpy(bp
->dev
->dev_addr
, vf
->mac_addr
, ETH_ALEN
);
4576 eth_hw_addr_random(bp
->dev
);
4577 rc
= bnxt_approve_mac(bp
, bp
->dev
->dev_addr
);
4583 hwrm_func_qcaps_exit
:
4584 mutex_unlock(&bp
->hwrm_cmd_lock
);
4588 static int bnxt_hwrm_func_reset(struct bnxt
*bp
)
4590 struct hwrm_func_reset_input req
= {0};
4592 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_RESET
, -1, -1);
4595 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_RESET_TIMEOUT
);
4598 static int bnxt_hwrm_queue_qportcfg(struct bnxt
*bp
)
4601 struct hwrm_queue_qportcfg_input req
= {0};
4602 struct hwrm_queue_qportcfg_output
*resp
= bp
->hwrm_cmd_resp_addr
;
4605 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_QUEUE_QPORTCFG
, -1, -1);
4607 mutex_lock(&bp
->hwrm_cmd_lock
);
4608 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4612 if (!resp
->max_configurable_queues
) {
4616 bp
->max_tc
= resp
->max_configurable_queues
;
4617 bp
->max_lltc
= resp
->max_configurable_lossless_queues
;
4618 if (bp
->max_tc
> BNXT_MAX_QUEUE
)
4619 bp
->max_tc
= BNXT_MAX_QUEUE
;
4621 if (resp
->queue_cfg_info
& QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG
)
4624 if (bp
->max_lltc
> bp
->max_tc
)
4625 bp
->max_lltc
= bp
->max_tc
;
4627 qptr
= &resp
->queue_id0
;
4628 for (i
= 0; i
< bp
->max_tc
; i
++) {
4629 bp
->q_info
[i
].queue_id
= *qptr
++;
4630 bp
->q_info
[i
].queue_profile
= *qptr
++;
4634 mutex_unlock(&bp
->hwrm_cmd_lock
);
4638 static int bnxt_hwrm_ver_get(struct bnxt
*bp
)
4641 struct hwrm_ver_get_input req
= {0};
4642 struct hwrm_ver_get_output
*resp
= bp
->hwrm_cmd_resp_addr
;
4644 bp
->hwrm_max_req_len
= HWRM_MAX_REQ_LEN
;
4645 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VER_GET
, -1, -1);
4646 req
.hwrm_intf_maj
= HWRM_VERSION_MAJOR
;
4647 req
.hwrm_intf_min
= HWRM_VERSION_MINOR
;
4648 req
.hwrm_intf_upd
= HWRM_VERSION_UPDATE
;
4649 mutex_lock(&bp
->hwrm_cmd_lock
);
4650 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4652 goto hwrm_ver_get_exit
;
4654 memcpy(&bp
->ver_resp
, resp
, sizeof(struct hwrm_ver_get_output
));
4656 bp
->hwrm_spec_code
= resp
->hwrm_intf_maj
<< 16 |
4657 resp
->hwrm_intf_min
<< 8 | resp
->hwrm_intf_upd
;
4658 if (resp
->hwrm_intf_maj
< 1) {
4659 netdev_warn(bp
->dev
, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
4660 resp
->hwrm_intf_maj
, resp
->hwrm_intf_min
,
4661 resp
->hwrm_intf_upd
);
4662 netdev_warn(bp
->dev
, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
4664 snprintf(bp
->fw_ver_str
, BC_HWRM_STR_LEN
, "%d.%d.%d/%d.%d.%d",
4665 resp
->hwrm_fw_maj
, resp
->hwrm_fw_min
, resp
->hwrm_fw_bld
,
4666 resp
->hwrm_intf_maj
, resp
->hwrm_intf_min
, resp
->hwrm_intf_upd
);
4668 bp
->hwrm_cmd_timeout
= le16_to_cpu(resp
->def_req_timeout
);
4669 if (!bp
->hwrm_cmd_timeout
)
4670 bp
->hwrm_cmd_timeout
= DFLT_HWRM_CMD_TIMEOUT
;
4672 if (resp
->hwrm_intf_maj
>= 1)
4673 bp
->hwrm_max_req_len
= le16_to_cpu(resp
->max_req_win_len
);
4675 bp
->chip_num
= le16_to_cpu(resp
->chip_num
);
4676 if (bp
->chip_num
== CHIP_NUM_58700
&& !resp
->chip_rev
&&
4678 bp
->flags
|= BNXT_FLAG_CHIP_NITRO_A0
;
4681 mutex_unlock(&bp
->hwrm_cmd_lock
);
4685 int bnxt_hwrm_fw_set_time(struct bnxt
*bp
)
4687 #if IS_ENABLED(CONFIG_RTC_LIB)
4688 struct hwrm_fw_set_time_input req
= {0};
4692 if (bp
->hwrm_spec_code
< 0x10400)
4695 do_gettimeofday(&tv
);
4696 rtc_time_to_tm(tv
.tv_sec
, &tm
);
4697 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FW_SET_TIME
, -1, -1);
4698 req
.year
= cpu_to_le16(1900 + tm
.tm_year
);
4699 req
.month
= 1 + tm
.tm_mon
;
4700 req
.day
= tm
.tm_mday
;
4701 req
.hour
= tm
.tm_hour
;
4702 req
.minute
= tm
.tm_min
;
4703 req
.second
= tm
.tm_sec
;
4704 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4710 static int bnxt_hwrm_port_qstats(struct bnxt
*bp
)
4713 struct bnxt_pf_info
*pf
= &bp
->pf
;
4714 struct hwrm_port_qstats_input req
= {0};
4716 if (!(bp
->flags
& BNXT_FLAG_PORT_STATS
))
4719 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_QSTATS
, -1, -1);
4720 req
.port_id
= cpu_to_le16(pf
->port_id
);
4721 req
.tx_stat_host_addr
= cpu_to_le64(bp
->hw_tx_port_stats_map
);
4722 req
.rx_stat_host_addr
= cpu_to_le64(bp
->hw_rx_port_stats_map
);
4723 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4727 static void bnxt_hwrm_free_tunnel_ports(struct bnxt
*bp
)
4729 if (bp
->vxlan_port_cnt
) {
4730 bnxt_hwrm_tunnel_dst_port_free(
4731 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
);
4733 bp
->vxlan_port_cnt
= 0;
4734 if (bp
->nge_port_cnt
) {
4735 bnxt_hwrm_tunnel_dst_port_free(
4736 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
);
4738 bp
->nge_port_cnt
= 0;
4741 static int bnxt_set_tpa(struct bnxt
*bp
, bool set_tpa
)
4747 tpa_flags
= bp
->flags
& BNXT_FLAG_TPA
;
4748 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
4749 rc
= bnxt_hwrm_vnic_set_tpa(bp
, i
, tpa_flags
);
4751 netdev_err(bp
->dev
, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
4759 static void bnxt_hwrm_clear_vnic_rss(struct bnxt
*bp
)
4763 for (i
= 0; i
< bp
->nr_vnics
; i
++)
4764 bnxt_hwrm_vnic_set_rss(bp
, i
, false);
4767 static void bnxt_hwrm_resource_free(struct bnxt
*bp
, bool close_path
,
4770 if (bp
->vnic_info
) {
4771 bnxt_hwrm_clear_vnic_filter(bp
);
4772 /* clear all RSS setting before free vnic ctx */
4773 bnxt_hwrm_clear_vnic_rss(bp
);
4774 bnxt_hwrm_vnic_ctx_free(bp
);
4775 /* before free the vnic, undo the vnic tpa settings */
4776 if (bp
->flags
& BNXT_FLAG_TPA
)
4777 bnxt_set_tpa(bp
, false);
4778 bnxt_hwrm_vnic_free(bp
);
4780 bnxt_hwrm_ring_free(bp
, close_path
);
4781 bnxt_hwrm_ring_grp_free(bp
);
4783 bnxt_hwrm_stat_ctx_free(bp
);
4784 bnxt_hwrm_free_tunnel_ports(bp
);
4788 static int bnxt_setup_vnic(struct bnxt
*bp
, u16 vnic_id
)
4790 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
4793 if (vnic
->flags
& BNXT_VNIC_RFS_NEW_RSS_FLAG
)
4796 /* allocate context for vnic */
4797 rc
= bnxt_hwrm_vnic_ctx_alloc(bp
, vnic_id
, 0);
4799 netdev_err(bp
->dev
, "hwrm vnic %d alloc failure rc: %x\n",
4801 goto vnic_setup_err
;
4803 bp
->rsscos_nr_ctxs
++;
4805 if (BNXT_CHIP_TYPE_NITRO_A0(bp
)) {
4806 rc
= bnxt_hwrm_vnic_ctx_alloc(bp
, vnic_id
, 1);
4808 netdev_err(bp
->dev
, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
4810 goto vnic_setup_err
;
4812 bp
->rsscos_nr_ctxs
++;
4816 /* configure default vnic, ring grp */
4817 rc
= bnxt_hwrm_vnic_cfg(bp
, vnic_id
);
4819 netdev_err(bp
->dev
, "hwrm vnic %d cfg failure rc: %x\n",
4821 goto vnic_setup_err
;
4824 /* Enable RSS hashing on vnic */
4825 rc
= bnxt_hwrm_vnic_set_rss(bp
, vnic_id
, true);
4827 netdev_err(bp
->dev
, "hwrm vnic %d set rss failure rc: %x\n",
4829 goto vnic_setup_err
;
4832 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
) {
4833 rc
= bnxt_hwrm_vnic_set_hds(bp
, vnic_id
);
4835 netdev_err(bp
->dev
, "hwrm vnic %d set hds failure rc: %x\n",
4844 static int bnxt_alloc_rfs_vnics(struct bnxt
*bp
)
4846 #ifdef CONFIG_RFS_ACCEL
4849 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
4850 struct bnxt_vnic_info
*vnic
;
4851 u16 vnic_id
= i
+ 1;
4854 if (vnic_id
>= bp
->nr_vnics
)
4857 vnic
= &bp
->vnic_info
[vnic_id
];
4858 vnic
->flags
|= BNXT_VNIC_RFS_FLAG
;
4859 if (bp
->flags
& BNXT_FLAG_NEW_RSS_CAP
)
4860 vnic
->flags
|= BNXT_VNIC_RFS_NEW_RSS_FLAG
;
4861 rc
= bnxt_hwrm_vnic_alloc(bp
, vnic_id
, ring_id
, 1);
4863 netdev_err(bp
->dev
, "hwrm vnic %d alloc failure rc: %x\n",
4867 rc
= bnxt_setup_vnic(bp
, vnic_id
);
4877 /* Allow PF and VF with default VLAN to be in promiscuous mode */
4878 static bool bnxt_promisc_ok(struct bnxt
*bp
)
4880 #ifdef CONFIG_BNXT_SRIOV
4881 if (BNXT_VF(bp
) && !bp
->vf
.vlan
)
4887 static int bnxt_setup_nitroa0_vnic(struct bnxt
*bp
)
4889 unsigned int rc
= 0;
4891 rc
= bnxt_hwrm_vnic_alloc(bp
, 1, bp
->rx_nr_rings
- 1, 1);
4893 netdev_err(bp
->dev
, "Cannot allocate special vnic for NS2 A0: %x\n",
4898 rc
= bnxt_hwrm_vnic_cfg(bp
, 1);
4900 netdev_err(bp
->dev
, "Cannot allocate special vnic for NS2 A0: %x\n",
4907 static int bnxt_cfg_rx_mode(struct bnxt
*);
4908 static bool bnxt_mc_list_updated(struct bnxt
*, u32
*);
4910 static int bnxt_init_chip(struct bnxt
*bp
, bool irq_re_init
)
4912 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
4914 unsigned int rx_nr_rings
= bp
->rx_nr_rings
;
4917 rc
= bnxt_hwrm_stat_ctx_alloc(bp
);
4919 netdev_err(bp
->dev
, "hwrm stat ctx alloc failure rc: %x\n",
4925 rc
= bnxt_hwrm_ring_alloc(bp
);
4927 netdev_err(bp
->dev
, "hwrm ring alloc failure rc: %x\n", rc
);
4931 rc
= bnxt_hwrm_ring_grp_alloc(bp
);
4933 netdev_err(bp
->dev
, "hwrm_ring_grp alloc failure: %x\n", rc
);
4937 if (BNXT_CHIP_TYPE_NITRO_A0(bp
))
4940 /* default vnic 0 */
4941 rc
= bnxt_hwrm_vnic_alloc(bp
, 0, 0, rx_nr_rings
);
4943 netdev_err(bp
->dev
, "hwrm vnic alloc failure rc: %x\n", rc
);
4947 rc
= bnxt_setup_vnic(bp
, 0);
4951 if (bp
->flags
& BNXT_FLAG_RFS
) {
4952 rc
= bnxt_alloc_rfs_vnics(bp
);
4957 if (bp
->flags
& BNXT_FLAG_TPA
) {
4958 rc
= bnxt_set_tpa(bp
, true);
4964 bnxt_update_vf_mac(bp
);
4966 /* Filter for default vnic 0 */
4967 rc
= bnxt_hwrm_set_vnic_filter(bp
, 0, 0, bp
->dev
->dev_addr
);
4969 netdev_err(bp
->dev
, "HWRM vnic filter failure rc: %x\n", rc
);
4972 vnic
->uc_filter_count
= 1;
4974 vnic
->rx_mask
= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST
;
4976 if ((bp
->dev
->flags
& IFF_PROMISC
) && bnxt_promisc_ok(bp
))
4977 vnic
->rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
;
4979 if (bp
->dev
->flags
& IFF_ALLMULTI
) {
4980 vnic
->rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
;
4981 vnic
->mc_list_count
= 0;
4985 bnxt_mc_list_updated(bp
, &mask
);
4986 vnic
->rx_mask
|= mask
;
4989 rc
= bnxt_cfg_rx_mode(bp
);
4993 rc
= bnxt_hwrm_set_coal(bp
);
4995 netdev_warn(bp
->dev
, "HWRM set coalescing failure rc: %x\n",
4998 if (BNXT_CHIP_TYPE_NITRO_A0(bp
)) {
4999 rc
= bnxt_setup_nitroa0_vnic(bp
);
5001 netdev_err(bp
->dev
, "Special vnic setup failure for NS2 A0 rc: %x\n",
5006 bnxt_hwrm_func_qcfg(bp
);
5007 netdev_update_features(bp
->dev
);
5013 bnxt_hwrm_resource_free(bp
, 0, true);
5018 static int bnxt_shutdown_nic(struct bnxt
*bp
, bool irq_re_init
)
5020 bnxt_hwrm_resource_free(bp
, 1, irq_re_init
);
5024 static int bnxt_init_nic(struct bnxt
*bp
, bool irq_re_init
)
5026 bnxt_init_cp_rings(bp
);
5027 bnxt_init_rx_rings(bp
);
5028 bnxt_init_tx_rings(bp
);
5029 bnxt_init_ring_grps(bp
, irq_re_init
);
5030 bnxt_init_vnics(bp
);
5032 return bnxt_init_chip(bp
, irq_re_init
);
5035 static int bnxt_set_real_num_queues(struct bnxt
*bp
)
5038 struct net_device
*dev
= bp
->dev
;
5040 rc
= netif_set_real_num_tx_queues(dev
, bp
->tx_nr_rings
-
5041 bp
->tx_nr_rings_xdp
);
5045 rc
= netif_set_real_num_rx_queues(dev
, bp
->rx_nr_rings
);
5049 #ifdef CONFIG_RFS_ACCEL
5050 if (bp
->flags
& BNXT_FLAG_RFS
)
5051 dev
->rx_cpu_rmap
= alloc_irq_cpu_rmap(bp
->rx_nr_rings
);
5057 static int bnxt_trim_rings(struct bnxt
*bp
, int *rx
, int *tx
, int max
,
5060 int _rx
= *rx
, _tx
= *tx
;
5063 *rx
= min_t(int, _rx
, max
);
5064 *tx
= min_t(int, _tx
, max
);
5069 while (_rx
+ _tx
> max
) {
5070 if (_rx
> _tx
&& _rx
> 1)
5081 static void bnxt_setup_msix(struct bnxt
*bp
)
5083 const int len
= sizeof(bp
->irq_tbl
[0].name
);
5084 struct net_device
*dev
= bp
->dev
;
5087 tcs
= netdev_get_num_tc(dev
);
5091 for (i
= 0; i
< tcs
; i
++) {
5092 count
= bp
->tx_nr_rings_per_tc
;
5094 netdev_set_tc_queue(dev
, i
, count
, off
);
5098 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
5101 if (bp
->flags
& BNXT_FLAG_SHARED_RINGS
)
5103 else if (i
< bp
->rx_nr_rings
)
5108 snprintf(bp
->irq_tbl
[i
].name
, len
, "%s-%s-%d", dev
->name
, attr
,
5110 bp
->irq_tbl
[i
].handler
= bnxt_msix
;
5114 static void bnxt_setup_inta(struct bnxt
*bp
)
5116 const int len
= sizeof(bp
->irq_tbl
[0].name
);
5118 if (netdev_get_num_tc(bp
->dev
))
5119 netdev_reset_tc(bp
->dev
);
5121 snprintf(bp
->irq_tbl
[0].name
, len
, "%s-%s-%d", bp
->dev
->name
, "TxRx",
5123 bp
->irq_tbl
[0].handler
= bnxt_inta
;
5126 static int bnxt_setup_int_mode(struct bnxt
*bp
)
5130 if (bp
->flags
& BNXT_FLAG_USING_MSIX
)
5131 bnxt_setup_msix(bp
);
5133 bnxt_setup_inta(bp
);
5135 rc
= bnxt_set_real_num_queues(bp
);
5139 #ifdef CONFIG_RFS_ACCEL
5140 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt
*bp
)
5142 #if defined(CONFIG_BNXT_SRIOV)
5144 return bp
->vf
.max_rsscos_ctxs
;
5146 return bp
->pf
.max_rsscos_ctxs
;
5149 static unsigned int bnxt_get_max_func_vnics(struct bnxt
*bp
)
5151 #if defined(CONFIG_BNXT_SRIOV)
5153 return bp
->vf
.max_vnics
;
5155 return bp
->pf
.max_vnics
;
5159 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt
*bp
)
5161 #if defined(CONFIG_BNXT_SRIOV)
5163 return bp
->vf
.max_stat_ctxs
;
5165 return bp
->pf
.max_stat_ctxs
;
5168 void bnxt_set_max_func_stat_ctxs(struct bnxt
*bp
, unsigned int max
)
5170 #if defined(CONFIG_BNXT_SRIOV)
5172 bp
->vf
.max_stat_ctxs
= max
;
5175 bp
->pf
.max_stat_ctxs
= max
;
5178 unsigned int bnxt_get_max_func_cp_rings(struct bnxt
*bp
)
5180 #if defined(CONFIG_BNXT_SRIOV)
5182 return bp
->vf
.max_cp_rings
;
5184 return bp
->pf
.max_cp_rings
;
5187 void bnxt_set_max_func_cp_rings(struct bnxt
*bp
, unsigned int max
)
5189 #if defined(CONFIG_BNXT_SRIOV)
5191 bp
->vf
.max_cp_rings
= max
;
5194 bp
->pf
.max_cp_rings
= max
;
5197 static unsigned int bnxt_get_max_func_irqs(struct bnxt
*bp
)
5199 #if defined(CONFIG_BNXT_SRIOV)
5201 return bp
->vf
.max_irqs
;
5203 return bp
->pf
.max_irqs
;
5206 void bnxt_set_max_func_irqs(struct bnxt
*bp
, unsigned int max_irqs
)
5208 #if defined(CONFIG_BNXT_SRIOV)
5210 bp
->vf
.max_irqs
= max_irqs
;
5213 bp
->pf
.max_irqs
= max_irqs
;
5216 static int bnxt_init_msix(struct bnxt
*bp
)
5218 int i
, total_vecs
, rc
= 0, min
= 1;
5219 struct msix_entry
*msix_ent
;
5221 total_vecs
= bnxt_get_max_func_irqs(bp
);
5222 msix_ent
= kcalloc(total_vecs
, sizeof(struct msix_entry
), GFP_KERNEL
);
5226 for (i
= 0; i
< total_vecs
; i
++) {
5227 msix_ent
[i
].entry
= i
;
5228 msix_ent
[i
].vector
= 0;
5231 if (!(bp
->flags
& BNXT_FLAG_SHARED_RINGS
))
5234 total_vecs
= pci_enable_msix_range(bp
->pdev
, msix_ent
, min
, total_vecs
);
5235 if (total_vecs
< 0) {
5237 goto msix_setup_exit
;
5240 bp
->irq_tbl
= kcalloc(total_vecs
, sizeof(struct bnxt_irq
), GFP_KERNEL
);
5242 for (i
= 0; i
< total_vecs
; i
++)
5243 bp
->irq_tbl
[i
].vector
= msix_ent
[i
].vector
;
5245 bp
->total_irqs
= total_vecs
;
5246 /* Trim rings based upon num of vectors allocated */
5247 rc
= bnxt_trim_rings(bp
, &bp
->rx_nr_rings
, &bp
->tx_nr_rings
,
5248 total_vecs
, min
== 1);
5250 goto msix_setup_exit
;
5252 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
;
5253 bp
->cp_nr_rings
= (min
== 1) ?
5254 max_t(int, bp
->tx_nr_rings
, bp
->rx_nr_rings
) :
5255 bp
->tx_nr_rings
+ bp
->rx_nr_rings
;
5259 goto msix_setup_exit
;
5261 bp
->flags
|= BNXT_FLAG_USING_MSIX
;
5266 netdev_err(bp
->dev
, "bnxt_init_msix err: %x\n", rc
);
5269 pci_disable_msix(bp
->pdev
);
5274 static int bnxt_init_inta(struct bnxt
*bp
)
5276 bp
->irq_tbl
= kcalloc(1, sizeof(struct bnxt_irq
), GFP_KERNEL
);
5281 bp
->rx_nr_rings
= 1;
5282 bp
->tx_nr_rings
= 1;
5283 bp
->cp_nr_rings
= 1;
5284 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
;
5285 bp
->flags
|= BNXT_FLAG_SHARED_RINGS
;
5286 bp
->irq_tbl
[0].vector
= bp
->pdev
->irq
;
5290 static int bnxt_init_int_mode(struct bnxt
*bp
)
5294 if (bp
->flags
& BNXT_FLAG_MSIX_CAP
)
5295 rc
= bnxt_init_msix(bp
);
5297 if (!(bp
->flags
& BNXT_FLAG_USING_MSIX
) && BNXT_PF(bp
)) {
5298 /* fallback to INTA */
5299 rc
= bnxt_init_inta(bp
);
5304 static void bnxt_clear_int_mode(struct bnxt
*bp
)
5306 if (bp
->flags
& BNXT_FLAG_USING_MSIX
)
5307 pci_disable_msix(bp
->pdev
);
5311 bp
->flags
&= ~BNXT_FLAG_USING_MSIX
;
5314 static void bnxt_free_irq(struct bnxt
*bp
)
5316 struct bnxt_irq
*irq
;
5319 #ifdef CONFIG_RFS_ACCEL
5320 free_irq_cpu_rmap(bp
->dev
->rx_cpu_rmap
);
5321 bp
->dev
->rx_cpu_rmap
= NULL
;
5326 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
5327 irq
= &bp
->irq_tbl
[i
];
5329 free_irq(irq
->vector
, bp
->bnapi
[i
]);
5334 static int bnxt_request_irq(struct bnxt
*bp
)
5337 unsigned long flags
= 0;
5338 #ifdef CONFIG_RFS_ACCEL
5339 struct cpu_rmap
*rmap
= bp
->dev
->rx_cpu_rmap
;
5342 if (!(bp
->flags
& BNXT_FLAG_USING_MSIX
))
5343 flags
= IRQF_SHARED
;
5345 for (i
= 0, j
= 0; i
< bp
->cp_nr_rings
; i
++) {
5346 struct bnxt_irq
*irq
= &bp
->irq_tbl
[i
];
5347 #ifdef CONFIG_RFS_ACCEL
5348 if (rmap
&& bp
->bnapi
[i
]->rx_ring
) {
5349 rc
= irq_cpu_rmap_add(rmap
, irq
->vector
);
5351 netdev_warn(bp
->dev
, "failed adding irq rmap for ring %d\n",
5356 rc
= request_irq(irq
->vector
, irq
->handler
, flags
, irq
->name
,
5366 static void bnxt_del_napi(struct bnxt
*bp
)
5373 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
5374 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
5376 napi_hash_del(&bnapi
->napi
);
5377 netif_napi_del(&bnapi
->napi
);
5379 /* We called napi_hash_del() before netif_napi_del(), we need
5380 * to respect an RCU grace period before freeing napi structures.
5385 static void bnxt_init_napi(struct bnxt
*bp
)
5388 unsigned int cp_nr_rings
= bp
->cp_nr_rings
;
5389 struct bnxt_napi
*bnapi
;
5391 if (bp
->flags
& BNXT_FLAG_USING_MSIX
) {
5392 if (BNXT_CHIP_TYPE_NITRO_A0(bp
))
5394 for (i
= 0; i
< cp_nr_rings
; i
++) {
5395 bnapi
= bp
->bnapi
[i
];
5396 netif_napi_add(bp
->dev
, &bnapi
->napi
,
5399 if (BNXT_CHIP_TYPE_NITRO_A0(bp
)) {
5400 bnapi
= bp
->bnapi
[cp_nr_rings
];
5401 netif_napi_add(bp
->dev
, &bnapi
->napi
,
5402 bnxt_poll_nitroa0
, 64);
5405 bnapi
= bp
->bnapi
[0];
5406 netif_napi_add(bp
->dev
, &bnapi
->napi
, bnxt_poll
, 64);
5410 static void bnxt_disable_napi(struct bnxt
*bp
)
5417 for (i
= 0; i
< bp
->cp_nr_rings
; i
++)
5418 napi_disable(&bp
->bnapi
[i
]->napi
);
5421 static void bnxt_enable_napi(struct bnxt
*bp
)
5425 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
5426 bp
->bnapi
[i
]->in_reset
= false;
5427 napi_enable(&bp
->bnapi
[i
]->napi
);
5431 void bnxt_tx_disable(struct bnxt
*bp
)
5434 struct bnxt_tx_ring_info
*txr
;
5435 struct netdev_queue
*txq
;
5438 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
5439 txr
= &bp
->tx_ring
[i
];
5440 txq
= netdev_get_tx_queue(bp
->dev
, i
);
5441 txr
->dev_state
= BNXT_DEV_STATE_CLOSING
;
5444 /* Stop all TX queues */
5445 netif_tx_disable(bp
->dev
);
5446 netif_carrier_off(bp
->dev
);
5449 void bnxt_tx_enable(struct bnxt
*bp
)
5452 struct bnxt_tx_ring_info
*txr
;
5453 struct netdev_queue
*txq
;
5455 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
5456 txr
= &bp
->tx_ring
[i
];
5457 txq
= netdev_get_tx_queue(bp
->dev
, i
);
5460 netif_tx_wake_all_queues(bp
->dev
);
5461 if (bp
->link_info
.link_up
)
5462 netif_carrier_on(bp
->dev
);
5465 static void bnxt_report_link(struct bnxt
*bp
)
5467 if (bp
->link_info
.link_up
) {
5469 const char *flow_ctrl
;
5472 netif_carrier_on(bp
->dev
);
5473 if (bp
->link_info
.duplex
== BNXT_LINK_DUPLEX_FULL
)
5477 if (bp
->link_info
.pause
== BNXT_LINK_PAUSE_BOTH
)
5478 flow_ctrl
= "ON - receive & transmit";
5479 else if (bp
->link_info
.pause
== BNXT_LINK_PAUSE_TX
)
5480 flow_ctrl
= "ON - transmit";
5481 else if (bp
->link_info
.pause
== BNXT_LINK_PAUSE_RX
)
5482 flow_ctrl
= "ON - receive";
5485 speed
= bnxt_fw_to_ethtool_speed(bp
->link_info
.link_speed
);
5486 netdev_info(bp
->dev
, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
5487 speed
, duplex
, flow_ctrl
);
5488 if (bp
->flags
& BNXT_FLAG_EEE_CAP
)
5489 netdev_info(bp
->dev
, "EEE is %s\n",
5490 bp
->eee
.eee_active
? "active" :
5492 fec
= bp
->link_info
.fec_cfg
;
5493 if (!(fec
& PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED
))
5494 netdev_info(bp
->dev
, "FEC autoneg %s encodings: %s\n",
5495 (fec
& BNXT_FEC_AUTONEG
) ? "on" : "off",
5496 (fec
& BNXT_FEC_ENC_BASE_R
) ? "BaseR" :
5497 (fec
& BNXT_FEC_ENC_RS
) ? "RS" : "None");
5499 netif_carrier_off(bp
->dev
);
5500 netdev_err(bp
->dev
, "NIC Link is Down\n");
5504 static int bnxt_hwrm_phy_qcaps(struct bnxt
*bp
)
5507 struct hwrm_port_phy_qcaps_input req
= {0};
5508 struct hwrm_port_phy_qcaps_output
*resp
= bp
->hwrm_cmd_resp_addr
;
5509 struct bnxt_link_info
*link_info
= &bp
->link_info
;
5511 if (bp
->hwrm_spec_code
< 0x10201)
5514 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_QCAPS
, -1, -1);
5516 mutex_lock(&bp
->hwrm_cmd_lock
);
5517 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
5519 goto hwrm_phy_qcaps_exit
;
5521 if (resp
->eee_supported
& PORT_PHY_QCAPS_RESP_EEE_SUPPORTED
) {
5522 struct ethtool_eee
*eee
= &bp
->eee
;
5523 u16 fw_speeds
= le16_to_cpu(resp
->supported_speeds_eee_mode
);
5525 bp
->flags
|= BNXT_FLAG_EEE_CAP
;
5526 eee
->supported
= _bnxt_fw_to_ethtool_adv_spds(fw_speeds
, 0);
5527 bp
->lpi_tmr_lo
= le32_to_cpu(resp
->tx_lpi_timer_low
) &
5528 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK
;
5529 bp
->lpi_tmr_hi
= le32_to_cpu(resp
->valid_tx_lpi_timer_high
) &
5530 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK
;
5532 if (resp
->supported_speeds_auto_mode
)
5533 link_info
->support_auto_speeds
=
5534 le16_to_cpu(resp
->supported_speeds_auto_mode
);
5536 hwrm_phy_qcaps_exit
:
5537 mutex_unlock(&bp
->hwrm_cmd_lock
);
5541 static int bnxt_update_link(struct bnxt
*bp
, bool chng_link_state
)
5544 struct bnxt_link_info
*link_info
= &bp
->link_info
;
5545 struct hwrm_port_phy_qcfg_input req
= {0};
5546 struct hwrm_port_phy_qcfg_output
*resp
= bp
->hwrm_cmd_resp_addr
;
5547 u8 link_up
= link_info
->link_up
;
5550 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_QCFG
, -1, -1);
5552 mutex_lock(&bp
->hwrm_cmd_lock
);
5553 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
5555 mutex_unlock(&bp
->hwrm_cmd_lock
);
5559 memcpy(&link_info
->phy_qcfg_resp
, resp
, sizeof(*resp
));
5560 link_info
->phy_link_status
= resp
->link
;
5561 link_info
->duplex
= resp
->duplex
;
5562 link_info
->pause
= resp
->pause
;
5563 link_info
->auto_mode
= resp
->auto_mode
;
5564 link_info
->auto_pause_setting
= resp
->auto_pause
;
5565 link_info
->lp_pause
= resp
->link_partner_adv_pause
;
5566 link_info
->force_pause_setting
= resp
->force_pause
;
5567 link_info
->duplex_setting
= resp
->duplex
;
5568 if (link_info
->phy_link_status
== BNXT_LINK_LINK
)
5569 link_info
->link_speed
= le16_to_cpu(resp
->link_speed
);
5571 link_info
->link_speed
= 0;
5572 link_info
->force_link_speed
= le16_to_cpu(resp
->force_link_speed
);
5573 link_info
->support_speeds
= le16_to_cpu(resp
->support_speeds
);
5574 link_info
->auto_link_speeds
= le16_to_cpu(resp
->auto_link_speed_mask
);
5575 link_info
->lp_auto_link_speeds
=
5576 le16_to_cpu(resp
->link_partner_adv_speeds
);
5577 link_info
->preemphasis
= le32_to_cpu(resp
->preemphasis
);
5578 link_info
->phy_ver
[0] = resp
->phy_maj
;
5579 link_info
->phy_ver
[1] = resp
->phy_min
;
5580 link_info
->phy_ver
[2] = resp
->phy_bld
;
5581 link_info
->media_type
= resp
->media_type
;
5582 link_info
->phy_type
= resp
->phy_type
;
5583 link_info
->transceiver
= resp
->xcvr_pkg_type
;
5584 link_info
->phy_addr
= resp
->eee_config_phy_addr
&
5585 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK
;
5586 link_info
->module_status
= resp
->module_status
;
5588 if (bp
->flags
& BNXT_FLAG_EEE_CAP
) {
5589 struct ethtool_eee
*eee
= &bp
->eee
;
5592 eee
->eee_active
= 0;
5593 if (resp
->eee_config_phy_addr
&
5594 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE
) {
5595 eee
->eee_active
= 1;
5596 fw_speeds
= le16_to_cpu(
5597 resp
->link_partner_adv_eee_link_speed_mask
);
5598 eee
->lp_advertised
=
5599 _bnxt_fw_to_ethtool_adv_spds(fw_speeds
, 0);
5602 /* Pull initial EEE config */
5603 if (!chng_link_state
) {
5604 if (resp
->eee_config_phy_addr
&
5605 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED
)
5606 eee
->eee_enabled
= 1;
5608 fw_speeds
= le16_to_cpu(resp
->adv_eee_link_speed_mask
);
5610 _bnxt_fw_to_ethtool_adv_spds(fw_speeds
, 0);
5612 if (resp
->eee_config_phy_addr
&
5613 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI
) {
5616 eee
->tx_lpi_enabled
= 1;
5617 tmr
= resp
->xcvr_identifier_type_tx_lpi_timer
;
5618 eee
->tx_lpi_timer
= le32_to_cpu(tmr
) &
5619 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK
;
5624 link_info
->fec_cfg
= PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED
;
5625 if (bp
->hwrm_spec_code
>= 0x10504)
5626 link_info
->fec_cfg
= le16_to_cpu(resp
->fec_cfg
);
5628 /* TODO: need to add more logic to report VF link */
5629 if (chng_link_state
) {
5630 if (link_info
->phy_link_status
== BNXT_LINK_LINK
)
5631 link_info
->link_up
= 1;
5633 link_info
->link_up
= 0;
5634 if (link_up
!= link_info
->link_up
)
5635 bnxt_report_link(bp
);
5637 /* alwasy link down if not require to update link state */
5638 link_info
->link_up
= 0;
5640 mutex_unlock(&bp
->hwrm_cmd_lock
);
5642 diff
= link_info
->support_auto_speeds
^ link_info
->advertising
;
5643 if ((link_info
->support_auto_speeds
| diff
) !=
5644 link_info
->support_auto_speeds
) {
5645 /* An advertised speed is no longer supported, so we need to
5646 * update the advertisement settings. Caller holds RTNL
5647 * so we can modify link settings.
5649 link_info
->advertising
= link_info
->support_auto_speeds
;
5650 if (link_info
->autoneg
& BNXT_AUTONEG_SPEED
)
5651 bnxt_hwrm_set_link_setting(bp
, true, false);
5656 static void bnxt_get_port_module_status(struct bnxt
*bp
)
5658 struct bnxt_link_info
*link_info
= &bp
->link_info
;
5659 struct hwrm_port_phy_qcfg_output
*resp
= &link_info
->phy_qcfg_resp
;
5662 if (bnxt_update_link(bp
, true))
5665 module_status
= link_info
->module_status
;
5666 switch (module_status
) {
5667 case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX
:
5668 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN
:
5669 case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG
:
5670 netdev_warn(bp
->dev
, "Unqualified SFP+ module detected on port %d\n",
5672 if (bp
->hwrm_spec_code
>= 0x10201) {
5673 netdev_warn(bp
->dev
, "Module part number %s\n",
5674 resp
->phy_vendor_partnumber
);
5676 if (module_status
== PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX
)
5677 netdev_warn(bp
->dev
, "TX is disabled\n");
5678 if (module_status
== PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN
)
5679 netdev_warn(bp
->dev
, "SFP+ module is shutdown\n");
5684 bnxt_hwrm_set_pause_common(struct bnxt
*bp
, struct hwrm_port_phy_cfg_input
*req
)
5686 if (bp
->link_info
.autoneg
& BNXT_AUTONEG_FLOW_CTRL
) {
5687 if (bp
->hwrm_spec_code
>= 0x10201)
5689 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE
;
5690 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_RX
)
5691 req
->auto_pause
|= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX
;
5692 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_TX
)
5693 req
->auto_pause
|= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX
;
5695 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE
);
5697 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_RX
)
5698 req
->force_pause
|= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX
;
5699 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_TX
)
5700 req
->force_pause
|= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX
;
5702 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE
);
5703 if (bp
->hwrm_spec_code
>= 0x10201) {
5704 req
->auto_pause
= req
->force_pause
;
5705 req
->enables
|= cpu_to_le32(
5706 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE
);
5711 static void bnxt_hwrm_set_link_common(struct bnxt
*bp
,
5712 struct hwrm_port_phy_cfg_input
*req
)
5714 u8 autoneg
= bp
->link_info
.autoneg
;
5715 u16 fw_link_speed
= bp
->link_info
.req_link_speed
;
5716 u16 advertising
= bp
->link_info
.advertising
;
5718 if (autoneg
& BNXT_AUTONEG_SPEED
) {
5720 PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK
;
5722 req
->enables
|= cpu_to_le32(
5723 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK
);
5724 req
->auto_link_speed_mask
= cpu_to_le16(advertising
);
5726 req
->enables
|= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE
);
5728 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG
);
5730 req
->force_link_speed
= cpu_to_le16(fw_link_speed
);
5731 req
->flags
|= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE
);
5734 /* tell chimp that the setting takes effect immediately */
5735 req
->flags
|= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY
);
5738 int bnxt_hwrm_set_pause(struct bnxt
*bp
)
5740 struct hwrm_port_phy_cfg_input req
= {0};
5743 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_CFG
, -1, -1);
5744 bnxt_hwrm_set_pause_common(bp
, &req
);
5746 if ((bp
->link_info
.autoneg
& BNXT_AUTONEG_FLOW_CTRL
) ||
5747 bp
->link_info
.force_link_chng
)
5748 bnxt_hwrm_set_link_common(bp
, &req
);
5750 mutex_lock(&bp
->hwrm_cmd_lock
);
5751 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
5752 if (!rc
&& !(bp
->link_info
.autoneg
& BNXT_AUTONEG_FLOW_CTRL
)) {
5753 /* since changing of pause setting doesn't trigger any link
5754 * change event, the driver needs to update the current pause
5755 * result upon successfully return of the phy_cfg command
5757 bp
->link_info
.pause
=
5758 bp
->link_info
.force_pause_setting
= bp
->link_info
.req_flow_ctrl
;
5759 bp
->link_info
.auto_pause_setting
= 0;
5760 if (!bp
->link_info
.force_link_chng
)
5761 bnxt_report_link(bp
);
5763 bp
->link_info
.force_link_chng
= false;
5764 mutex_unlock(&bp
->hwrm_cmd_lock
);
5768 static void bnxt_hwrm_set_eee(struct bnxt
*bp
,
5769 struct hwrm_port_phy_cfg_input
*req
)
5771 struct ethtool_eee
*eee
= &bp
->eee
;
5773 if (eee
->eee_enabled
) {
5775 u32 flags
= PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE
;
5777 if (eee
->tx_lpi_enabled
)
5778 flags
|= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE
;
5780 flags
|= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE
;
5782 req
->flags
|= cpu_to_le32(flags
);
5783 eee_speeds
= bnxt_get_fw_auto_link_speeds(eee
->advertised
);
5784 req
->eee_link_speed_mask
= cpu_to_le16(eee_speeds
);
5785 req
->tx_lpi_timer
= cpu_to_le32(eee
->tx_lpi_timer
);
5787 req
->flags
|= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE
);
5791 int bnxt_hwrm_set_link_setting(struct bnxt
*bp
, bool set_pause
, bool set_eee
)
5793 struct hwrm_port_phy_cfg_input req
= {0};
5795 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_CFG
, -1, -1);
5797 bnxt_hwrm_set_pause_common(bp
, &req
);
5799 bnxt_hwrm_set_link_common(bp
, &req
);
5802 bnxt_hwrm_set_eee(bp
, &req
);
5803 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
5806 static int bnxt_hwrm_shutdown_link(struct bnxt
*bp
)
5808 struct hwrm_port_phy_cfg_input req
= {0};
5810 if (!BNXT_SINGLE_PF(bp
))
5813 if (pci_num_vf(bp
->pdev
))
5816 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_CFG
, -1, -1);
5817 req
.flags
= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN
);
5818 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
5821 static int bnxt_hwrm_port_led_qcaps(struct bnxt
*bp
)
5823 struct hwrm_port_led_qcaps_output
*resp
= bp
->hwrm_cmd_resp_addr
;
5824 struct hwrm_port_led_qcaps_input req
= {0};
5825 struct bnxt_pf_info
*pf
= &bp
->pf
;
5828 if (BNXT_VF(bp
) || bp
->hwrm_spec_code
< 0x10601)
5831 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_LED_QCAPS
, -1, -1);
5832 req
.port_id
= cpu_to_le16(pf
->port_id
);
5833 mutex_lock(&bp
->hwrm_cmd_lock
);
5834 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
5836 mutex_unlock(&bp
->hwrm_cmd_lock
);
5839 if (resp
->num_leds
> 0 && resp
->num_leds
< BNXT_MAX_LED
) {
5842 bp
->num_leds
= resp
->num_leds
;
5843 memcpy(bp
->leds
, &resp
->led0_id
, sizeof(bp
->leds
[0]) *
5845 for (i
= 0; i
< bp
->num_leds
; i
++) {
5846 struct bnxt_led_info
*led
= &bp
->leds
[i
];
5847 __le16 caps
= led
->led_state_caps
;
5849 if (!led
->led_group_id
||
5850 !BNXT_LED_ALT_BLINK_CAP(caps
)) {
5856 mutex_unlock(&bp
->hwrm_cmd_lock
);
5860 static bool bnxt_eee_config_ok(struct bnxt
*bp
)
5862 struct ethtool_eee
*eee
= &bp
->eee
;
5863 struct bnxt_link_info
*link_info
= &bp
->link_info
;
5865 if (!(bp
->flags
& BNXT_FLAG_EEE_CAP
))
5868 if (eee
->eee_enabled
) {
5870 _bnxt_fw_to_ethtool_adv_spds(link_info
->advertising
, 0);
5872 if (!(link_info
->autoneg
& BNXT_AUTONEG_SPEED
)) {
5873 eee
->eee_enabled
= 0;
5876 if (eee
->advertised
& ~advertising
) {
5877 eee
->advertised
= advertising
& eee
->supported
;
5884 static int bnxt_update_phy_setting(struct bnxt
*bp
)
5887 bool update_link
= false;
5888 bool update_pause
= false;
5889 bool update_eee
= false;
5890 struct bnxt_link_info
*link_info
= &bp
->link_info
;
5892 rc
= bnxt_update_link(bp
, true);
5894 netdev_err(bp
->dev
, "failed to update link (rc: %x)\n",
5898 if (!BNXT_SINGLE_PF(bp
))
5901 if ((link_info
->autoneg
& BNXT_AUTONEG_FLOW_CTRL
) &&
5902 (link_info
->auto_pause_setting
& BNXT_LINK_PAUSE_BOTH
) !=
5903 link_info
->req_flow_ctrl
)
5904 update_pause
= true;
5905 if (!(link_info
->autoneg
& BNXT_AUTONEG_FLOW_CTRL
) &&
5906 link_info
->force_pause_setting
!= link_info
->req_flow_ctrl
)
5907 update_pause
= true;
5908 if (!(link_info
->autoneg
& BNXT_AUTONEG_SPEED
)) {
5909 if (BNXT_AUTO_MODE(link_info
->auto_mode
))
5911 if (link_info
->req_link_speed
!= link_info
->force_link_speed
)
5913 if (link_info
->req_duplex
!= link_info
->duplex_setting
)
5916 if (link_info
->auto_mode
== BNXT_LINK_AUTO_NONE
)
5918 if (link_info
->advertising
!= link_info
->auto_link_speeds
)
5922 /* The last close may have shutdown the link, so need to call
5923 * PHY_CFG to bring it back up.
5925 if (!netif_carrier_ok(bp
->dev
))
5928 if (!bnxt_eee_config_ok(bp
))
5932 rc
= bnxt_hwrm_set_link_setting(bp
, update_pause
, update_eee
);
5933 else if (update_pause
)
5934 rc
= bnxt_hwrm_set_pause(bp
);
5936 netdev_err(bp
->dev
, "failed to update phy setting (rc: %x)\n",
5944 /* Common routine to pre-map certain register block to different GRC window.
5945 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
5946 * in PF and 3 windows in VF that can be customized to map in different
5949 static void bnxt_preset_reg_win(struct bnxt
*bp
)
5952 /* CAG registers map to GRC window #4 */
5953 writel(BNXT_CAG_REG_BASE
,
5954 bp
->bar0
+ BNXT_GRCPF_REG_WINDOW_BASE_OUT
+ 12);
5958 static int __bnxt_open_nic(struct bnxt
*bp
, bool irq_re_init
, bool link_re_init
)
5962 bnxt_preset_reg_win(bp
);
5963 netif_carrier_off(bp
->dev
);
5965 rc
= bnxt_setup_int_mode(bp
);
5967 netdev_err(bp
->dev
, "bnxt_setup_int_mode err: %x\n",
5972 if ((bp
->flags
& BNXT_FLAG_RFS
) &&
5973 !(bp
->flags
& BNXT_FLAG_USING_MSIX
)) {
5974 /* disable RFS if falling back to INTA */
5975 bp
->dev
->hw_features
&= ~NETIF_F_NTUPLE
;
5976 bp
->flags
&= ~BNXT_FLAG_RFS
;
5979 rc
= bnxt_alloc_mem(bp
, irq_re_init
);
5981 netdev_err(bp
->dev
, "bnxt_alloc_mem err: %x\n", rc
);
5982 goto open_err_free_mem
;
5987 rc
= bnxt_request_irq(bp
);
5989 netdev_err(bp
->dev
, "bnxt_request_irq err: %x\n", rc
);
5994 bnxt_enable_napi(bp
);
5996 rc
= bnxt_init_nic(bp
, irq_re_init
);
5998 netdev_err(bp
->dev
, "bnxt_init_nic err: %x\n", rc
);
6003 rc
= bnxt_update_phy_setting(bp
);
6005 netdev_warn(bp
->dev
, "failed to update phy settings\n");
6009 udp_tunnel_get_rx_info(bp
->dev
);
6011 set_bit(BNXT_STATE_OPEN
, &bp
->state
);
6012 bnxt_enable_int(bp
);
6013 /* Enable TX queues */
6015 mod_timer(&bp
->timer
, jiffies
+ bp
->current_interval
);
6016 /* Poll link status and check for SFP+ module status */
6017 bnxt_get_port_module_status(bp
);
6022 bnxt_disable_napi(bp
);
6028 bnxt_free_mem(bp
, true);
6032 /* rtnl_lock held */
6033 int bnxt_open_nic(struct bnxt
*bp
, bool irq_re_init
, bool link_re_init
)
6037 rc
= __bnxt_open_nic(bp
, irq_re_init
, link_re_init
);
6039 netdev_err(bp
->dev
, "nic open fail (rc: %x)\n", rc
);
6045 static int bnxt_open(struct net_device
*dev
)
6047 struct bnxt
*bp
= netdev_priv(dev
);
6049 return __bnxt_open_nic(bp
, true, true);
6052 int bnxt_close_nic(struct bnxt
*bp
, bool irq_re_init
, bool link_re_init
)
6056 #ifdef CONFIG_BNXT_SRIOV
6057 if (bp
->sriov_cfg
) {
6058 rc
= wait_event_interruptible_timeout(bp
->sriov_cfg_wait
,
6060 BNXT_SRIOV_CFG_WAIT_TMO
);
6062 netdev_warn(bp
->dev
, "timeout waiting for SRIOV config operation to complete!\n");
6065 /* Change device state to avoid TX queue wake up's */
6066 bnxt_tx_disable(bp
);
6068 clear_bit(BNXT_STATE_OPEN
, &bp
->state
);
6069 smp_mb__after_atomic();
6070 while (test_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
))
6073 /* Flush rings and and disable interrupts */
6074 bnxt_shutdown_nic(bp
, irq_re_init
);
6076 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
6078 bnxt_disable_napi(bp
);
6079 del_timer_sync(&bp
->timer
);
6086 bnxt_free_mem(bp
, irq_re_init
);
6090 static int bnxt_close(struct net_device
*dev
)
6092 struct bnxt
*bp
= netdev_priv(dev
);
6094 bnxt_close_nic(bp
, true, true);
6095 bnxt_hwrm_shutdown_link(bp
);
6099 /* rtnl_lock held */
6100 static int bnxt_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
6106 if (!netif_running(dev
))
6113 if (!netif_running(dev
))
6126 bnxt_get_stats64(struct net_device
*dev
, struct rtnl_link_stats64
*stats
)
6129 struct bnxt
*bp
= netdev_priv(dev
);
6134 /* TODO check if we need to synchronize with bnxt_close path */
6135 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
6136 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
6137 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
6138 struct ctx_hw_stats
*hw_stats
= cpr
->hw_stats
;
6140 stats
->rx_packets
+= le64_to_cpu(hw_stats
->rx_ucast_pkts
);
6141 stats
->rx_packets
+= le64_to_cpu(hw_stats
->rx_mcast_pkts
);
6142 stats
->rx_packets
+= le64_to_cpu(hw_stats
->rx_bcast_pkts
);
6144 stats
->tx_packets
+= le64_to_cpu(hw_stats
->tx_ucast_pkts
);
6145 stats
->tx_packets
+= le64_to_cpu(hw_stats
->tx_mcast_pkts
);
6146 stats
->tx_packets
+= le64_to_cpu(hw_stats
->tx_bcast_pkts
);
6148 stats
->rx_bytes
+= le64_to_cpu(hw_stats
->rx_ucast_bytes
);
6149 stats
->rx_bytes
+= le64_to_cpu(hw_stats
->rx_mcast_bytes
);
6150 stats
->rx_bytes
+= le64_to_cpu(hw_stats
->rx_bcast_bytes
);
6152 stats
->tx_bytes
+= le64_to_cpu(hw_stats
->tx_ucast_bytes
);
6153 stats
->tx_bytes
+= le64_to_cpu(hw_stats
->tx_mcast_bytes
);
6154 stats
->tx_bytes
+= le64_to_cpu(hw_stats
->tx_bcast_bytes
);
6156 stats
->rx_missed_errors
+=
6157 le64_to_cpu(hw_stats
->rx_discard_pkts
);
6159 stats
->multicast
+= le64_to_cpu(hw_stats
->rx_mcast_pkts
);
6161 stats
->tx_dropped
+= le64_to_cpu(hw_stats
->tx_drop_pkts
);
6164 if (bp
->flags
& BNXT_FLAG_PORT_STATS
) {
6165 struct rx_port_stats
*rx
= bp
->hw_rx_port_stats
;
6166 struct tx_port_stats
*tx
= bp
->hw_tx_port_stats
;
6168 stats
->rx_crc_errors
= le64_to_cpu(rx
->rx_fcs_err_frames
);
6169 stats
->rx_frame_errors
= le64_to_cpu(rx
->rx_align_err_frames
);
6170 stats
->rx_length_errors
= le64_to_cpu(rx
->rx_undrsz_frames
) +
6171 le64_to_cpu(rx
->rx_ovrsz_frames
) +
6172 le64_to_cpu(rx
->rx_runt_frames
);
6173 stats
->rx_errors
= le64_to_cpu(rx
->rx_false_carrier_frames
) +
6174 le64_to_cpu(rx
->rx_jbr_frames
);
6175 stats
->collisions
= le64_to_cpu(tx
->tx_total_collisions
);
6176 stats
->tx_fifo_errors
= le64_to_cpu(tx
->tx_fifo_underruns
);
6177 stats
->tx_errors
= le64_to_cpu(tx
->tx_err
);
6181 static bool bnxt_mc_list_updated(struct bnxt
*bp
, u32
*rx_mask
)
6183 struct net_device
*dev
= bp
->dev
;
6184 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
6185 struct netdev_hw_addr
*ha
;
6188 bool update
= false;
6191 netdev_for_each_mc_addr(ha
, dev
) {
6192 if (mc_count
>= BNXT_MAX_MC_ADDRS
) {
6193 *rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
;
6194 vnic
->mc_list_count
= 0;
6198 if (!ether_addr_equal(haddr
, vnic
->mc_list
+ off
)) {
6199 memcpy(vnic
->mc_list
+ off
, haddr
, ETH_ALEN
);
6206 *rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST
;
6208 if (mc_count
!= vnic
->mc_list_count
) {
6209 vnic
->mc_list_count
= mc_count
;
6215 static bool bnxt_uc_list_updated(struct bnxt
*bp
)
6217 struct net_device
*dev
= bp
->dev
;
6218 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
6219 struct netdev_hw_addr
*ha
;
6222 if (netdev_uc_count(dev
) != (vnic
->uc_filter_count
- 1))
6225 netdev_for_each_uc_addr(ha
, dev
) {
6226 if (!ether_addr_equal(ha
->addr
, vnic
->uc_list
+ off
))
6234 static void bnxt_set_rx_mode(struct net_device
*dev
)
6236 struct bnxt
*bp
= netdev_priv(dev
);
6237 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
6238 u32 mask
= vnic
->rx_mask
;
6239 bool mc_update
= false;
6242 if (!netif_running(dev
))
6245 mask
&= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
|
6246 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST
|
6247 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
);
6249 if ((dev
->flags
& IFF_PROMISC
) && bnxt_promisc_ok(bp
))
6250 mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
;
6252 uc_update
= bnxt_uc_list_updated(bp
);
6254 if (dev
->flags
& IFF_ALLMULTI
) {
6255 mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
;
6256 vnic
->mc_list_count
= 0;
6258 mc_update
= bnxt_mc_list_updated(bp
, &mask
);
6261 if (mask
!= vnic
->rx_mask
|| uc_update
|| mc_update
) {
6262 vnic
->rx_mask
= mask
;
6264 set_bit(BNXT_RX_MASK_SP_EVENT
, &bp
->sp_event
);
6265 schedule_work(&bp
->sp_task
);
6269 static int bnxt_cfg_rx_mode(struct bnxt
*bp
)
6271 struct net_device
*dev
= bp
->dev
;
6272 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
6273 struct netdev_hw_addr
*ha
;
6277 netif_addr_lock_bh(dev
);
6278 uc_update
= bnxt_uc_list_updated(bp
);
6279 netif_addr_unlock_bh(dev
);
6284 mutex_lock(&bp
->hwrm_cmd_lock
);
6285 for (i
= 1; i
< vnic
->uc_filter_count
; i
++) {
6286 struct hwrm_cfa_l2_filter_free_input req
= {0};
6288 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_L2_FILTER_FREE
, -1,
6291 req
.l2_filter_id
= vnic
->fw_l2_filter_id
[i
];
6293 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
6296 mutex_unlock(&bp
->hwrm_cmd_lock
);
6298 vnic
->uc_filter_count
= 1;
6300 netif_addr_lock_bh(dev
);
6301 if (netdev_uc_count(dev
) > (BNXT_MAX_UC_ADDRS
- 1)) {
6302 vnic
->rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
;
6304 netdev_for_each_uc_addr(ha
, dev
) {
6305 memcpy(vnic
->uc_list
+ off
, ha
->addr
, ETH_ALEN
);
6307 vnic
->uc_filter_count
++;
6310 netif_addr_unlock_bh(dev
);
6312 for (i
= 1, off
= 0; i
< vnic
->uc_filter_count
; i
++, off
+= ETH_ALEN
) {
6313 rc
= bnxt_hwrm_set_vnic_filter(bp
, 0, i
, vnic
->uc_list
+ off
);
6315 netdev_err(bp
->dev
, "HWRM vnic filter failure rc: %x\n",
6317 vnic
->uc_filter_count
= i
;
6323 rc
= bnxt_hwrm_cfa_l2_set_rx_mask(bp
, 0);
6325 netdev_err(bp
->dev
, "HWRM cfa l2 rx mask failure rc: %x\n",
6331 /* If the chip and firmware supports RFS */
6332 static bool bnxt_rfs_supported(struct bnxt
*bp
)
6334 if (BNXT_PF(bp
) && !BNXT_CHIP_TYPE_NITRO_A0(bp
))
6336 if (bp
->flags
& BNXT_FLAG_NEW_RSS_CAP
)
6341 /* If runtime conditions support RFS */
6342 static bool bnxt_rfs_capable(struct bnxt
*bp
)
6344 #ifdef CONFIG_RFS_ACCEL
6345 int vnics
, max_vnics
, max_rss_ctxs
;
6347 if (!(bp
->flags
& BNXT_FLAG_MSIX_CAP
))
6350 vnics
= 1 + bp
->rx_nr_rings
;
6351 max_vnics
= bnxt_get_max_func_vnics(bp
);
6352 max_rss_ctxs
= bnxt_get_max_func_rss_ctxs(bp
);
6354 /* RSS contexts not a limiting factor */
6355 if (bp
->flags
& BNXT_FLAG_NEW_RSS_CAP
)
6356 max_rss_ctxs
= max_vnics
;
6357 if (vnics
> max_vnics
|| vnics
> max_rss_ctxs
) {
6358 netdev_warn(bp
->dev
,
6359 "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
6360 min(max_rss_ctxs
- 1, max_vnics
- 1));
6370 static netdev_features_t
bnxt_fix_features(struct net_device
*dev
,
6371 netdev_features_t features
)
6373 struct bnxt
*bp
= netdev_priv(dev
);
6375 if ((features
& NETIF_F_NTUPLE
) && !bnxt_rfs_capable(bp
))
6376 features
&= ~NETIF_F_NTUPLE
;
6378 /* Both CTAG and STAG VLAN accelaration on the RX side have to be
6379 * turned on or off together.
6381 if ((features
& (NETIF_F_HW_VLAN_CTAG_RX
| NETIF_F_HW_VLAN_STAG_RX
)) !=
6382 (NETIF_F_HW_VLAN_CTAG_RX
| NETIF_F_HW_VLAN_STAG_RX
)) {
6383 if (dev
->features
& NETIF_F_HW_VLAN_CTAG_RX
)
6384 features
&= ~(NETIF_F_HW_VLAN_CTAG_RX
|
6385 NETIF_F_HW_VLAN_STAG_RX
);
6387 features
|= NETIF_F_HW_VLAN_CTAG_RX
|
6388 NETIF_F_HW_VLAN_STAG_RX
;
6390 #ifdef CONFIG_BNXT_SRIOV
6393 features
&= ~(NETIF_F_HW_VLAN_CTAG_RX
|
6394 NETIF_F_HW_VLAN_STAG_RX
);
6401 static int bnxt_set_features(struct net_device
*dev
, netdev_features_t features
)
6403 struct bnxt
*bp
= netdev_priv(dev
);
6404 u32 flags
= bp
->flags
;
6407 bool re_init
= false;
6408 bool update_tpa
= false;
6410 flags
&= ~BNXT_FLAG_ALL_CONFIG_FEATS
;
6411 if ((features
& NETIF_F_GRO
) && !BNXT_CHIP_TYPE_NITRO_A0(bp
))
6412 flags
|= BNXT_FLAG_GRO
;
6413 if (features
& NETIF_F_LRO
)
6414 flags
|= BNXT_FLAG_LRO
;
6416 if (bp
->flags
& BNXT_FLAG_NO_AGG_RINGS
)
6417 flags
&= ~BNXT_FLAG_TPA
;
6419 if (features
& NETIF_F_HW_VLAN_CTAG_RX
)
6420 flags
|= BNXT_FLAG_STRIP_VLAN
;
6422 if (features
& NETIF_F_NTUPLE
)
6423 flags
|= BNXT_FLAG_RFS
;
6425 changes
= flags
^ bp
->flags
;
6426 if (changes
& BNXT_FLAG_TPA
) {
6428 if ((bp
->flags
& BNXT_FLAG_TPA
) == 0 ||
6429 (flags
& BNXT_FLAG_TPA
) == 0)
6433 if (changes
& ~BNXT_FLAG_TPA
)
6436 if (flags
!= bp
->flags
) {
6437 u32 old_flags
= bp
->flags
;
6441 if (!test_bit(BNXT_STATE_OPEN
, &bp
->state
)) {
6443 bnxt_set_ring_params(bp
);
6448 bnxt_close_nic(bp
, false, false);
6450 bnxt_set_ring_params(bp
);
6452 return bnxt_open_nic(bp
, false, false);
6455 rc
= bnxt_set_tpa(bp
,
6456 (flags
& BNXT_FLAG_TPA
) ?
6459 bp
->flags
= old_flags
;
6465 static void bnxt_dump_tx_sw_state(struct bnxt_napi
*bnapi
)
6467 struct bnxt_tx_ring_info
*txr
= bnapi
->tx_ring
;
6468 int i
= bnapi
->index
;
6473 netdev_info(bnapi
->bp
->dev
, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
6474 i
, txr
->tx_ring_struct
.fw_ring_id
, txr
->tx_prod
,
6478 static void bnxt_dump_rx_sw_state(struct bnxt_napi
*bnapi
)
6480 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
6481 int i
= bnapi
->index
;
6486 netdev_info(bnapi
->bp
->dev
, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
6487 i
, rxr
->rx_ring_struct
.fw_ring_id
, rxr
->rx_prod
,
6488 rxr
->rx_agg_ring_struct
.fw_ring_id
, rxr
->rx_agg_prod
,
6489 rxr
->rx_sw_agg_prod
);
6492 static void bnxt_dump_cp_sw_state(struct bnxt_napi
*bnapi
)
6494 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
6495 int i
= bnapi
->index
;
6497 netdev_info(bnapi
->bp
->dev
, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
6498 i
, cpr
->cp_ring_struct
.fw_ring_id
, cpr
->cp_raw_cons
);
6501 static void bnxt_dbg_dump_states(struct bnxt
*bp
)
6504 struct bnxt_napi
*bnapi
;
6506 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
6507 bnapi
= bp
->bnapi
[i
];
6508 if (netif_msg_drv(bp
)) {
6509 bnxt_dump_tx_sw_state(bnapi
);
6510 bnxt_dump_rx_sw_state(bnapi
);
6511 bnxt_dump_cp_sw_state(bnapi
);
6516 static void bnxt_reset_task(struct bnxt
*bp
, bool silent
)
6519 bnxt_dbg_dump_states(bp
);
6520 if (netif_running(bp
->dev
)) {
6525 bnxt_close_nic(bp
, false, false);
6526 rc
= bnxt_open_nic(bp
, false, false);
6532 static void bnxt_tx_timeout(struct net_device
*dev
)
6534 struct bnxt
*bp
= netdev_priv(dev
);
6536 netdev_err(bp
->dev
, "TX timeout detected, starting reset task!\n");
6537 set_bit(BNXT_RESET_TASK_SP_EVENT
, &bp
->sp_event
);
6538 schedule_work(&bp
->sp_task
);
6541 #ifdef CONFIG_NET_POLL_CONTROLLER
6542 static void bnxt_poll_controller(struct net_device
*dev
)
6544 struct bnxt
*bp
= netdev_priv(dev
);
6547 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
6548 struct bnxt_irq
*irq
= &bp
->irq_tbl
[i
];
6550 disable_irq(irq
->vector
);
6551 irq
->handler(irq
->vector
, bp
->bnapi
[i
]);
6552 enable_irq(irq
->vector
);
6557 static void bnxt_timer(unsigned long data
)
6559 struct bnxt
*bp
= (struct bnxt
*)data
;
6560 struct net_device
*dev
= bp
->dev
;
6562 if (!netif_running(dev
))
6565 if (atomic_read(&bp
->intr_sem
) != 0)
6566 goto bnxt_restart_timer
;
6568 if (bp
->link_info
.link_up
&& (bp
->flags
& BNXT_FLAG_PORT_STATS
)) {
6569 set_bit(BNXT_PERIODIC_STATS_SP_EVENT
, &bp
->sp_event
);
6570 schedule_work(&bp
->sp_task
);
6573 mod_timer(&bp
->timer
, jiffies
+ bp
->current_interval
);
6576 static void bnxt_rtnl_lock_sp(struct bnxt
*bp
)
6578 /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK
6579 * set. If the device is being closed, bnxt_close() may be holding
6580 * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we
6581 * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
6583 clear_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
6587 static void bnxt_rtnl_unlock_sp(struct bnxt
*bp
)
6589 set_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
6593 /* Only called from bnxt_sp_task() */
6594 static void bnxt_reset(struct bnxt
*bp
, bool silent
)
6596 bnxt_rtnl_lock_sp(bp
);
6597 if (test_bit(BNXT_STATE_OPEN
, &bp
->state
))
6598 bnxt_reset_task(bp
, silent
);
6599 bnxt_rtnl_unlock_sp(bp
);
6602 static void bnxt_cfg_ntp_filters(struct bnxt
*);
6604 static void bnxt_sp_task(struct work_struct
*work
)
6606 struct bnxt
*bp
= container_of(work
, struct bnxt
, sp_task
);
6608 set_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
6609 smp_mb__after_atomic();
6610 if (!test_bit(BNXT_STATE_OPEN
, &bp
->state
)) {
6611 clear_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
6615 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT
, &bp
->sp_event
))
6616 bnxt_cfg_rx_mode(bp
);
6618 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT
, &bp
->sp_event
))
6619 bnxt_cfg_ntp_filters(bp
);
6620 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT
, &bp
->sp_event
))
6621 bnxt_hwrm_exec_fwd_req(bp
);
6622 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT
, &bp
->sp_event
)) {
6623 bnxt_hwrm_tunnel_dst_port_alloc(
6625 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
);
6627 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT
, &bp
->sp_event
)) {
6628 bnxt_hwrm_tunnel_dst_port_free(
6629 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
);
6631 if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT
, &bp
->sp_event
)) {
6632 bnxt_hwrm_tunnel_dst_port_alloc(
6634 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
);
6636 if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT
, &bp
->sp_event
)) {
6637 bnxt_hwrm_tunnel_dst_port_free(
6638 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
);
6640 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT
, &bp
->sp_event
))
6641 bnxt_hwrm_port_qstats(bp
);
6643 /* These functions below will clear BNXT_STATE_IN_SP_TASK. They
6644 * must be the last functions to be called before exiting.
6646 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT
, &bp
->sp_event
)) {
6649 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT
,
6651 bnxt_hwrm_phy_qcaps(bp
);
6653 bnxt_rtnl_lock_sp(bp
);
6654 if (test_bit(BNXT_STATE_OPEN
, &bp
->state
))
6655 rc
= bnxt_update_link(bp
, true);
6656 bnxt_rtnl_unlock_sp(bp
);
6658 netdev_err(bp
->dev
, "SP task can't update link (rc: %x)\n",
6661 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT
, &bp
->sp_event
)) {
6662 bnxt_rtnl_lock_sp(bp
);
6663 if (test_bit(BNXT_STATE_OPEN
, &bp
->state
))
6664 bnxt_get_port_module_status(bp
);
6665 bnxt_rtnl_unlock_sp(bp
);
6667 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT
, &bp
->sp_event
))
6668 bnxt_reset(bp
, false);
6670 if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT
, &bp
->sp_event
))
6671 bnxt_reset(bp
, true);
6673 smp_mb__before_atomic();
6674 clear_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
6677 /* Under rtnl_lock */
6678 int bnxt_reserve_rings(struct bnxt
*bp
, int tx
, int rx
, int tcs
, int tx_xdp
)
6680 int max_rx
, max_tx
, tx_sets
= 1;
6681 int tx_rings_needed
;
6685 if (!(bp
->flags
& BNXT_FLAG_SHARED_RINGS
))
6691 rc
= bnxt_get_max_rings(bp
, &max_rx
, &max_tx
, sh
);
6698 tx_rings_needed
= tx
* tx_sets
+ tx_xdp
;
6699 if (max_tx
< tx_rings_needed
)
6702 if (bnxt_hwrm_reserve_tx_rings(bp
, &tx_rings_needed
) ||
6703 tx_rings_needed
< (tx
* tx_sets
+ tx_xdp
))
6708 static void bnxt_unmap_bars(struct bnxt
*bp
, struct pci_dev
*pdev
)
6711 pci_iounmap(pdev
, bp
->bar2
);
6716 pci_iounmap(pdev
, bp
->bar1
);
6721 pci_iounmap(pdev
, bp
->bar0
);
6726 static void bnxt_cleanup_pci(struct bnxt
*bp
)
6728 bnxt_unmap_bars(bp
, bp
->pdev
);
6729 pci_release_regions(bp
->pdev
);
6730 pci_disable_device(bp
->pdev
);
6733 static int bnxt_init_board(struct pci_dev
*pdev
, struct net_device
*dev
)
6736 struct bnxt
*bp
= netdev_priv(dev
);
6738 SET_NETDEV_DEV(dev
, &pdev
->dev
);
6740 /* enable device (incl. PCI PM wakeup), and bus-mastering */
6741 rc
= pci_enable_device(pdev
);
6743 dev_err(&pdev
->dev
, "Cannot enable PCI device, aborting\n");
6747 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
6749 "Cannot find PCI device base address, aborting\n");
6751 goto init_err_disable
;
6754 rc
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
6756 dev_err(&pdev
->dev
, "Cannot obtain PCI resources, aborting\n");
6757 goto init_err_disable
;
6760 if (dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(64)) != 0 &&
6761 dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(32)) != 0) {
6762 dev_err(&pdev
->dev
, "System does not support DMA, aborting\n");
6763 goto init_err_disable
;
6766 pci_set_master(pdev
);
6771 bp
->bar0
= pci_ioremap_bar(pdev
, 0);
6773 dev_err(&pdev
->dev
, "Cannot map device registers, aborting\n");
6775 goto init_err_release
;
6778 bp
->bar1
= pci_ioremap_bar(pdev
, 2);
6780 dev_err(&pdev
->dev
, "Cannot map doorbell registers, aborting\n");
6782 goto init_err_release
;
6785 bp
->bar2
= pci_ioremap_bar(pdev
, 4);
6787 dev_err(&pdev
->dev
, "Cannot map bar4 registers, aborting\n");
6789 goto init_err_release
;
6792 pci_enable_pcie_error_reporting(pdev
);
6794 INIT_WORK(&bp
->sp_task
, bnxt_sp_task
);
6796 spin_lock_init(&bp
->ntp_fltr_lock
);
6798 bp
->rx_ring_size
= BNXT_DEFAULT_RX_RING_SIZE
;
6799 bp
->tx_ring_size
= BNXT_DEFAULT_TX_RING_SIZE
;
6801 /* tick values in micro seconds */
6802 bp
->rx_coal_ticks
= 12;
6803 bp
->rx_coal_bufs
= 30;
6804 bp
->rx_coal_ticks_irq
= 1;
6805 bp
->rx_coal_bufs_irq
= 2;
6807 bp
->tx_coal_ticks
= 25;
6808 bp
->tx_coal_bufs
= 30;
6809 bp
->tx_coal_ticks_irq
= 2;
6810 bp
->tx_coal_bufs_irq
= 2;
6812 bp
->stats_coal_ticks
= BNXT_DEF_STATS_COAL_TICKS
;
6814 init_timer(&bp
->timer
);
6815 bp
->timer
.data
= (unsigned long)bp
;
6816 bp
->timer
.function
= bnxt_timer
;
6817 bp
->current_interval
= BNXT_TIMER_INTERVAL
;
6819 clear_bit(BNXT_STATE_OPEN
, &bp
->state
);
6823 bnxt_unmap_bars(bp
, pdev
);
6824 pci_release_regions(pdev
);
6827 pci_disable_device(pdev
);
6833 /* rtnl_lock held */
6834 static int bnxt_change_mac_addr(struct net_device
*dev
, void *p
)
6836 struct sockaddr
*addr
= p
;
6837 struct bnxt
*bp
= netdev_priv(dev
);
6840 if (!is_valid_ether_addr(addr
->sa_data
))
6841 return -EADDRNOTAVAIL
;
6843 rc
= bnxt_approve_mac(bp
, addr
->sa_data
);
6847 if (ether_addr_equal(addr
->sa_data
, dev
->dev_addr
))
6850 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
6851 if (netif_running(dev
)) {
6852 bnxt_close_nic(bp
, false, false);
6853 rc
= bnxt_open_nic(bp
, false, false);
6859 /* rtnl_lock held */
6860 static int bnxt_change_mtu(struct net_device
*dev
, int new_mtu
)
6862 struct bnxt
*bp
= netdev_priv(dev
);
6864 if (netif_running(dev
))
6865 bnxt_close_nic(bp
, false, false);
6868 bnxt_set_ring_params(bp
);
6870 if (netif_running(dev
))
6871 return bnxt_open_nic(bp
, false, false);
6876 int bnxt_setup_mq_tc(struct net_device
*dev
, u8 tc
)
6878 struct bnxt
*bp
= netdev_priv(dev
);
6882 if (tc
> bp
->max_tc
) {
6883 netdev_err(dev
, "Too many traffic classes requested: %d. Max supported is %d.\n",
6888 if (netdev_get_num_tc(dev
) == tc
)
6891 if (bp
->flags
& BNXT_FLAG_SHARED_RINGS
)
6894 rc
= bnxt_reserve_rings(bp
, bp
->tx_nr_rings_per_tc
, bp
->rx_nr_rings
,
6895 tc
, bp
->tx_nr_rings_xdp
);
6899 /* Needs to close the device and do hw resource re-allocations */
6900 if (netif_running(bp
->dev
))
6901 bnxt_close_nic(bp
, true, false);
6904 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
* tc
;
6905 netdev_set_num_tc(dev
, tc
);
6907 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
;
6908 netdev_reset_tc(dev
);
6910 bp
->cp_nr_rings
= sh
? max_t(int, bp
->tx_nr_rings
, bp
->rx_nr_rings
) :
6911 bp
->tx_nr_rings
+ bp
->rx_nr_rings
;
6912 bp
->num_stat_ctxs
= bp
->cp_nr_rings
;
6914 if (netif_running(bp
->dev
))
6915 return bnxt_open_nic(bp
, true, false);
6920 static int bnxt_setup_tc(struct net_device
*dev
, u32 handle
, __be16 proto
,
6921 struct tc_to_netdev
*ntc
)
6923 if (ntc
->type
!= TC_SETUP_MQPRIO
)
6926 return bnxt_setup_mq_tc(dev
, ntc
->tc
);
6929 #ifdef CONFIG_RFS_ACCEL
6930 static bool bnxt_fltr_match(struct bnxt_ntuple_filter
*f1
,
6931 struct bnxt_ntuple_filter
*f2
)
6933 struct flow_keys
*keys1
= &f1
->fkeys
;
6934 struct flow_keys
*keys2
= &f2
->fkeys
;
6936 if (keys1
->addrs
.v4addrs
.src
== keys2
->addrs
.v4addrs
.src
&&
6937 keys1
->addrs
.v4addrs
.dst
== keys2
->addrs
.v4addrs
.dst
&&
6938 keys1
->ports
.ports
== keys2
->ports
.ports
&&
6939 keys1
->basic
.ip_proto
== keys2
->basic
.ip_proto
&&
6940 keys1
->basic
.n_proto
== keys2
->basic
.n_proto
&&
6941 keys1
->control
.flags
== keys2
->control
.flags
&&
6942 ether_addr_equal(f1
->src_mac_addr
, f2
->src_mac_addr
) &&
6943 ether_addr_equal(f1
->dst_mac_addr
, f2
->dst_mac_addr
))
6949 static int bnxt_rx_flow_steer(struct net_device
*dev
, const struct sk_buff
*skb
,
6950 u16 rxq_index
, u32 flow_id
)
6952 struct bnxt
*bp
= netdev_priv(dev
);
6953 struct bnxt_ntuple_filter
*fltr
, *new_fltr
;
6954 struct flow_keys
*fkeys
;
6955 struct ethhdr
*eth
= (struct ethhdr
*)skb_mac_header(skb
);
6956 int rc
= 0, idx
, bit_id
, l2_idx
= 0;
6957 struct hlist_head
*head
;
6959 if (!ether_addr_equal(dev
->dev_addr
, eth
->h_dest
)) {
6960 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
6963 netif_addr_lock_bh(dev
);
6964 for (j
= 0; j
< vnic
->uc_filter_count
; j
++, off
+= ETH_ALEN
) {
6965 if (ether_addr_equal(eth
->h_dest
,
6966 vnic
->uc_list
+ off
)) {
6971 netif_addr_unlock_bh(dev
);
6975 new_fltr
= kzalloc(sizeof(*new_fltr
), GFP_ATOMIC
);
6979 fkeys
= &new_fltr
->fkeys
;
6980 if (!skb_flow_dissect_flow_keys(skb
, fkeys
, 0)) {
6981 rc
= -EPROTONOSUPPORT
;
6985 if ((fkeys
->basic
.n_proto
!= htons(ETH_P_IP
) &&
6986 fkeys
->basic
.n_proto
!= htons(ETH_P_IPV6
)) ||
6987 ((fkeys
->basic
.ip_proto
!= IPPROTO_TCP
) &&
6988 (fkeys
->basic
.ip_proto
!= IPPROTO_UDP
))) {
6989 rc
= -EPROTONOSUPPORT
;
6992 if (fkeys
->basic
.n_proto
== htons(ETH_P_IPV6
) &&
6993 bp
->hwrm_spec_code
< 0x10601) {
6994 rc
= -EPROTONOSUPPORT
;
6997 if ((fkeys
->control
.flags
& FLOW_DIS_ENCAPSULATION
) &&
6998 bp
->hwrm_spec_code
< 0x10601) {
6999 rc
= -EPROTONOSUPPORT
;
7003 memcpy(new_fltr
->dst_mac_addr
, eth
->h_dest
, ETH_ALEN
);
7004 memcpy(new_fltr
->src_mac_addr
, eth
->h_source
, ETH_ALEN
);
7006 idx
= skb_get_hash_raw(skb
) & BNXT_NTP_FLTR_HASH_MASK
;
7007 head
= &bp
->ntp_fltr_hash_tbl
[idx
];
7009 hlist_for_each_entry_rcu(fltr
, head
, hash
) {
7010 if (bnxt_fltr_match(fltr
, new_fltr
)) {
7018 spin_lock_bh(&bp
->ntp_fltr_lock
);
7019 bit_id
= bitmap_find_free_region(bp
->ntp_fltr_bmap
,
7020 BNXT_NTP_FLTR_MAX_FLTR
, 0);
7022 spin_unlock_bh(&bp
->ntp_fltr_lock
);
7027 new_fltr
->sw_id
= (u16
)bit_id
;
7028 new_fltr
->flow_id
= flow_id
;
7029 new_fltr
->l2_fltr_idx
= l2_idx
;
7030 new_fltr
->rxq
= rxq_index
;
7031 hlist_add_head_rcu(&new_fltr
->hash
, head
);
7032 bp
->ntp_fltr_count
++;
7033 spin_unlock_bh(&bp
->ntp_fltr_lock
);
7035 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT
, &bp
->sp_event
);
7036 schedule_work(&bp
->sp_task
);
7038 return new_fltr
->sw_id
;
7045 static void bnxt_cfg_ntp_filters(struct bnxt
*bp
)
7049 for (i
= 0; i
< BNXT_NTP_FLTR_HASH_SIZE
; i
++) {
7050 struct hlist_head
*head
;
7051 struct hlist_node
*tmp
;
7052 struct bnxt_ntuple_filter
*fltr
;
7055 head
= &bp
->ntp_fltr_hash_tbl
[i
];
7056 hlist_for_each_entry_safe(fltr
, tmp
, head
, hash
) {
7059 if (test_bit(BNXT_FLTR_VALID
, &fltr
->state
)) {
7060 if (rps_may_expire_flow(bp
->dev
, fltr
->rxq
,
7063 bnxt_hwrm_cfa_ntuple_filter_free(bp
,
7068 rc
= bnxt_hwrm_cfa_ntuple_filter_alloc(bp
,
7073 set_bit(BNXT_FLTR_VALID
, &fltr
->state
);
7077 spin_lock_bh(&bp
->ntp_fltr_lock
);
7078 hlist_del_rcu(&fltr
->hash
);
7079 bp
->ntp_fltr_count
--;
7080 spin_unlock_bh(&bp
->ntp_fltr_lock
);
7082 clear_bit(fltr
->sw_id
, bp
->ntp_fltr_bmap
);
7087 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT
, &bp
->sp_event
))
7088 netdev_info(bp
->dev
, "Receive PF driver unload event!");
7093 static void bnxt_cfg_ntp_filters(struct bnxt
*bp
)
7097 #endif /* CONFIG_RFS_ACCEL */
7099 static void bnxt_udp_tunnel_add(struct net_device
*dev
,
7100 struct udp_tunnel_info
*ti
)
7102 struct bnxt
*bp
= netdev_priv(dev
);
7104 if (ti
->sa_family
!= AF_INET6
&& ti
->sa_family
!= AF_INET
)
7107 if (!netif_running(dev
))
7111 case UDP_TUNNEL_TYPE_VXLAN
:
7112 if (bp
->vxlan_port_cnt
&& bp
->vxlan_port
!= ti
->port
)
7115 bp
->vxlan_port_cnt
++;
7116 if (bp
->vxlan_port_cnt
== 1) {
7117 bp
->vxlan_port
= ti
->port
;
7118 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT
, &bp
->sp_event
);
7119 schedule_work(&bp
->sp_task
);
7122 case UDP_TUNNEL_TYPE_GENEVE
:
7123 if (bp
->nge_port_cnt
&& bp
->nge_port
!= ti
->port
)
7127 if (bp
->nge_port_cnt
== 1) {
7128 bp
->nge_port
= ti
->port
;
7129 set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT
, &bp
->sp_event
);
7136 schedule_work(&bp
->sp_task
);
7139 static void bnxt_udp_tunnel_del(struct net_device
*dev
,
7140 struct udp_tunnel_info
*ti
)
7142 struct bnxt
*bp
= netdev_priv(dev
);
7144 if (ti
->sa_family
!= AF_INET6
&& ti
->sa_family
!= AF_INET
)
7147 if (!netif_running(dev
))
7151 case UDP_TUNNEL_TYPE_VXLAN
:
7152 if (!bp
->vxlan_port_cnt
|| bp
->vxlan_port
!= ti
->port
)
7154 bp
->vxlan_port_cnt
--;
7156 if (bp
->vxlan_port_cnt
!= 0)
7159 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT
, &bp
->sp_event
);
7161 case UDP_TUNNEL_TYPE_GENEVE
:
7162 if (!bp
->nge_port_cnt
|| bp
->nge_port
!= ti
->port
)
7166 if (bp
->nge_port_cnt
!= 0)
7169 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT
, &bp
->sp_event
);
7175 schedule_work(&bp
->sp_task
);
7178 static const struct net_device_ops bnxt_netdev_ops
= {
7179 .ndo_open
= bnxt_open
,
7180 .ndo_start_xmit
= bnxt_start_xmit
,
7181 .ndo_stop
= bnxt_close
,
7182 .ndo_get_stats64
= bnxt_get_stats64
,
7183 .ndo_set_rx_mode
= bnxt_set_rx_mode
,
7184 .ndo_do_ioctl
= bnxt_ioctl
,
7185 .ndo_validate_addr
= eth_validate_addr
,
7186 .ndo_set_mac_address
= bnxt_change_mac_addr
,
7187 .ndo_change_mtu
= bnxt_change_mtu
,
7188 .ndo_fix_features
= bnxt_fix_features
,
7189 .ndo_set_features
= bnxt_set_features
,
7190 .ndo_tx_timeout
= bnxt_tx_timeout
,
7191 #ifdef CONFIG_BNXT_SRIOV
7192 .ndo_get_vf_config
= bnxt_get_vf_config
,
7193 .ndo_set_vf_mac
= bnxt_set_vf_mac
,
7194 .ndo_set_vf_vlan
= bnxt_set_vf_vlan
,
7195 .ndo_set_vf_rate
= bnxt_set_vf_bw
,
7196 .ndo_set_vf_link_state
= bnxt_set_vf_link_state
,
7197 .ndo_set_vf_spoofchk
= bnxt_set_vf_spoofchk
,
7199 #ifdef CONFIG_NET_POLL_CONTROLLER
7200 .ndo_poll_controller
= bnxt_poll_controller
,
7202 .ndo_setup_tc
= bnxt_setup_tc
,
7203 #ifdef CONFIG_RFS_ACCEL
7204 .ndo_rx_flow_steer
= bnxt_rx_flow_steer
,
7206 .ndo_udp_tunnel_add
= bnxt_udp_tunnel_add
,
7207 .ndo_udp_tunnel_del
= bnxt_udp_tunnel_del
,
7208 .ndo_xdp
= bnxt_xdp
,
7211 static void bnxt_remove_one(struct pci_dev
*pdev
)
7213 struct net_device
*dev
= pci_get_drvdata(pdev
);
7214 struct bnxt
*bp
= netdev_priv(dev
);
7217 bnxt_sriov_disable(bp
);
7219 pci_disable_pcie_error_reporting(pdev
);
7220 unregister_netdev(dev
);
7221 cancel_work_sync(&bp
->sp_task
);
7224 bnxt_clear_int_mode(bp
);
7225 bnxt_hwrm_func_drv_unrgtr(bp
);
7226 bnxt_free_hwrm_resources(bp
);
7231 bpf_prog_put(bp
->xdp_prog
);
7232 bnxt_cleanup_pci(bp
);
7236 static int bnxt_probe_phy(struct bnxt
*bp
)
7239 struct bnxt_link_info
*link_info
= &bp
->link_info
;
7241 rc
= bnxt_hwrm_phy_qcaps(bp
);
7243 netdev_err(bp
->dev
, "Probe phy can't get phy capabilities (rc: %x)\n",
7248 rc
= bnxt_update_link(bp
, false);
7250 netdev_err(bp
->dev
, "Probe phy can't update link (rc: %x)\n",
7255 /* Older firmware does not have supported_auto_speeds, so assume
7256 * that all supported speeds can be autonegotiated.
7258 if (link_info
->auto_link_speeds
&& !link_info
->support_auto_speeds
)
7259 link_info
->support_auto_speeds
= link_info
->support_speeds
;
7261 /*initialize the ethool setting copy with NVM settings */
7262 if (BNXT_AUTO_MODE(link_info
->auto_mode
)) {
7263 link_info
->autoneg
= BNXT_AUTONEG_SPEED
;
7264 if (bp
->hwrm_spec_code
>= 0x10201) {
7265 if (link_info
->auto_pause_setting
&
7266 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE
)
7267 link_info
->autoneg
|= BNXT_AUTONEG_FLOW_CTRL
;
7269 link_info
->autoneg
|= BNXT_AUTONEG_FLOW_CTRL
;
7271 link_info
->advertising
= link_info
->auto_link_speeds
;
7273 link_info
->req_link_speed
= link_info
->force_link_speed
;
7274 link_info
->req_duplex
= link_info
->duplex_setting
;
7276 if (link_info
->autoneg
& BNXT_AUTONEG_FLOW_CTRL
)
7277 link_info
->req_flow_ctrl
=
7278 link_info
->auto_pause_setting
& BNXT_LINK_PAUSE_BOTH
;
7280 link_info
->req_flow_ctrl
= link_info
->force_pause_setting
;
7284 static int bnxt_get_max_irq(struct pci_dev
*pdev
)
7288 if (!pdev
->msix_cap
)
7291 pci_read_config_word(pdev
, pdev
->msix_cap
+ PCI_MSIX_FLAGS
, &ctrl
);
7292 return (ctrl
& PCI_MSIX_FLAGS_QSIZE
) + 1;
7295 static void _bnxt_get_max_rings(struct bnxt
*bp
, int *max_rx
, int *max_tx
,
7298 int max_ring_grps
= 0;
7300 #ifdef CONFIG_BNXT_SRIOV
7302 *max_tx
= bp
->vf
.max_tx_rings
;
7303 *max_rx
= bp
->vf
.max_rx_rings
;
7304 *max_cp
= min_t(int, bp
->vf
.max_irqs
, bp
->vf
.max_cp_rings
);
7305 *max_cp
= min_t(int, *max_cp
, bp
->vf
.max_stat_ctxs
);
7306 max_ring_grps
= bp
->vf
.max_hw_ring_grps
;
7310 *max_tx
= bp
->pf
.max_tx_rings
;
7311 *max_rx
= bp
->pf
.max_rx_rings
;
7312 *max_cp
= min_t(int, bp
->pf
.max_irqs
, bp
->pf
.max_cp_rings
);
7313 *max_cp
= min_t(int, *max_cp
, bp
->pf
.max_stat_ctxs
);
7314 max_ring_grps
= bp
->pf
.max_hw_ring_grps
;
7316 if (BNXT_CHIP_TYPE_NITRO_A0(bp
) && BNXT_PF(bp
)) {
7320 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
)
7322 *max_rx
= min_t(int, *max_rx
, max_ring_grps
);
7325 int bnxt_get_max_rings(struct bnxt
*bp
, int *max_rx
, int *max_tx
, bool shared
)
7329 _bnxt_get_max_rings(bp
, &rx
, &tx
, &cp
);
7330 if (!rx
|| !tx
|| !cp
)
7335 return bnxt_trim_rings(bp
, max_rx
, max_tx
, cp
, shared
);
7338 static int bnxt_get_dflt_rings(struct bnxt
*bp
, int *max_rx
, int *max_tx
,
7343 rc
= bnxt_get_max_rings(bp
, max_rx
, max_tx
, shared
);
7344 if (rc
&& (bp
->flags
& BNXT_FLAG_AGG_RINGS
)) {
7345 /* Not enough rings, try disabling agg rings. */
7346 bp
->flags
&= ~BNXT_FLAG_AGG_RINGS
;
7347 rc
= bnxt_get_max_rings(bp
, max_rx
, max_tx
, shared
);
7350 bp
->flags
|= BNXT_FLAG_NO_AGG_RINGS
;
7351 bp
->dev
->hw_features
&= ~NETIF_F_LRO
;
7352 bp
->dev
->features
&= ~NETIF_F_LRO
;
7353 bnxt_set_ring_params(bp
);
7356 if (bp
->flags
& BNXT_FLAG_ROCE_CAP
) {
7357 int max_cp
, max_stat
, max_irq
;
7359 /* Reserve minimum resources for RoCE */
7360 max_cp
= bnxt_get_max_func_cp_rings(bp
);
7361 max_stat
= bnxt_get_max_func_stat_ctxs(bp
);
7362 max_irq
= bnxt_get_max_func_irqs(bp
);
7363 if (max_cp
<= BNXT_MIN_ROCE_CP_RINGS
||
7364 max_irq
<= BNXT_MIN_ROCE_CP_RINGS
||
7365 max_stat
<= BNXT_MIN_ROCE_STAT_CTXS
)
7368 max_cp
-= BNXT_MIN_ROCE_CP_RINGS
;
7369 max_irq
-= BNXT_MIN_ROCE_CP_RINGS
;
7370 max_stat
-= BNXT_MIN_ROCE_STAT_CTXS
;
7371 max_cp
= min_t(int, max_cp
, max_irq
);
7372 max_cp
= min_t(int, max_cp
, max_stat
);
7373 rc
= bnxt_trim_rings(bp
, max_rx
, max_tx
, max_cp
, shared
);
7380 static int bnxt_set_dflt_rings(struct bnxt
*bp
)
7382 int dflt_rings
, max_rx_rings
, max_tx_rings
, rc
;
7386 bp
->flags
|= BNXT_FLAG_SHARED_RINGS
;
7387 dflt_rings
= netif_get_num_default_rss_queues();
7388 rc
= bnxt_get_dflt_rings(bp
, &max_rx_rings
, &max_tx_rings
, sh
);
7391 bp
->rx_nr_rings
= min_t(int, dflt_rings
, max_rx_rings
);
7392 bp
->tx_nr_rings_per_tc
= min_t(int, dflt_rings
, max_tx_rings
);
7394 rc
= bnxt_hwrm_reserve_tx_rings(bp
, &bp
->tx_nr_rings_per_tc
);
7396 netdev_warn(bp
->dev
, "Unable to reserve tx rings\n");
7398 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
;
7399 bp
->cp_nr_rings
= sh
? max_t(int, bp
->tx_nr_rings
, bp
->rx_nr_rings
) :
7400 bp
->tx_nr_rings
+ bp
->rx_nr_rings
;
7401 bp
->num_stat_ctxs
= bp
->cp_nr_rings
;
7402 if (BNXT_CHIP_TYPE_NITRO_A0(bp
)) {
7409 void bnxt_restore_pf_fw_resources(struct bnxt
*bp
)
7412 bnxt_hwrm_func_qcaps(bp
);
7413 bnxt_subtract_ulp_resources(bp
, BNXT_ROCE_ULP
);
7416 static void bnxt_parse_log_pcie_link(struct bnxt
*bp
)
7418 enum pcie_link_width width
= PCIE_LNK_WIDTH_UNKNOWN
;
7419 enum pci_bus_speed speed
= PCI_SPEED_UNKNOWN
;
7421 if (pcie_get_minimum_link(bp
->pdev
, &speed
, &width
) ||
7422 speed
== PCI_SPEED_UNKNOWN
|| width
== PCIE_LNK_WIDTH_UNKNOWN
)
7423 netdev_info(bp
->dev
, "Failed to determine PCIe Link Info\n");
7425 netdev_info(bp
->dev
, "PCIe: Speed %s Width x%d\n",
7426 speed
== PCIE_SPEED_2_5GT
? "2.5GT/s" :
7427 speed
== PCIE_SPEED_5_0GT
? "5.0GT/s" :
7428 speed
== PCIE_SPEED_8_0GT
? "8.0GT/s" :
7432 static int bnxt_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
7434 static int version_printed
;
7435 struct net_device
*dev
;
7439 if (pci_is_bridge(pdev
))
7442 if (version_printed
++ == 0)
7443 pr_info("%s", version
);
7445 max_irqs
= bnxt_get_max_irq(pdev
);
7446 dev
= alloc_etherdev_mq(sizeof(*bp
), max_irqs
);
7450 bp
= netdev_priv(dev
);
7452 if (bnxt_vf_pciid(ent
->driver_data
))
7453 bp
->flags
|= BNXT_FLAG_VF
;
7456 bp
->flags
|= BNXT_FLAG_MSIX_CAP
;
7458 rc
= bnxt_init_board(pdev
, dev
);
7462 dev
->netdev_ops
= &bnxt_netdev_ops
;
7463 dev
->watchdog_timeo
= BNXT_TX_TIMEOUT
;
7464 dev
->ethtool_ops
= &bnxt_ethtool_ops
;
7465 pci_set_drvdata(pdev
, dev
);
7467 rc
= bnxt_alloc_hwrm_resources(bp
);
7469 goto init_err_pci_clean
;
7471 mutex_init(&bp
->hwrm_cmd_lock
);
7472 rc
= bnxt_hwrm_ver_get(bp
);
7474 goto init_err_pci_clean
;
7476 rc
= bnxt_hwrm_func_reset(bp
);
7478 goto init_err_pci_clean
;
7480 bnxt_hwrm_fw_set_time(bp
);
7482 dev
->hw_features
= NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
| NETIF_F_SG
|
7483 NETIF_F_TSO
| NETIF_F_TSO6
|
7484 NETIF_F_GSO_UDP_TUNNEL
| NETIF_F_GSO_GRE
|
7485 NETIF_F_GSO_IPXIP4
|
7486 NETIF_F_GSO_UDP_TUNNEL_CSUM
| NETIF_F_GSO_GRE_CSUM
|
7487 NETIF_F_GSO_PARTIAL
| NETIF_F_RXHASH
|
7488 NETIF_F_RXCSUM
| NETIF_F_GRO
;
7490 if (!BNXT_CHIP_TYPE_NITRO_A0(bp
))
7491 dev
->hw_features
|= NETIF_F_LRO
;
7493 dev
->hw_enc_features
=
7494 NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
| NETIF_F_SG
|
7495 NETIF_F_TSO
| NETIF_F_TSO6
|
7496 NETIF_F_GSO_UDP_TUNNEL
| NETIF_F_GSO_GRE
|
7497 NETIF_F_GSO_UDP_TUNNEL_CSUM
| NETIF_F_GSO_GRE_CSUM
|
7498 NETIF_F_GSO_IPXIP4
| NETIF_F_GSO_PARTIAL
;
7499 dev
->gso_partial_features
= NETIF_F_GSO_UDP_TUNNEL_CSUM
|
7500 NETIF_F_GSO_GRE_CSUM
;
7501 dev
->vlan_features
= dev
->hw_features
| NETIF_F_HIGHDMA
;
7502 dev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_RX
| NETIF_F_HW_VLAN_CTAG_TX
|
7503 NETIF_F_HW_VLAN_STAG_RX
| NETIF_F_HW_VLAN_STAG_TX
;
7504 dev
->features
|= dev
->hw_features
| NETIF_F_HIGHDMA
;
7505 dev
->priv_flags
|= IFF_UNICAST_FLT
;
7507 /* MTU range: 60 - 9500 */
7508 dev
->min_mtu
= ETH_ZLEN
;
7509 dev
->max_mtu
= BNXT_MAX_MTU
;
7513 #ifdef CONFIG_BNXT_SRIOV
7514 init_waitqueue_head(&bp
->sriov_cfg_wait
);
7516 bp
->gro_func
= bnxt_gro_func_5730x
;
7517 if (BNXT_CHIP_NUM_57X1X(bp
->chip_num
))
7518 bp
->gro_func
= bnxt_gro_func_5731x
;
7520 rc
= bnxt_hwrm_func_drv_rgtr(bp
);
7522 goto init_err_pci_clean
;
7524 rc
= bnxt_hwrm_func_rgtr_async_events(bp
, NULL
, 0);
7526 goto init_err_pci_clean
;
7528 bp
->ulp_probe
= bnxt_ulp_probe
;
7530 /* Get the MAX capabilities for this function */
7531 rc
= bnxt_hwrm_func_qcaps(bp
);
7533 netdev_err(bp
->dev
, "hwrm query capability failure rc: %x\n",
7536 goto init_err_pci_clean
;
7539 rc
= bnxt_hwrm_queue_qportcfg(bp
);
7541 netdev_err(bp
->dev
, "hwrm query qportcfg failure rc: %x\n",
7544 goto init_err_pci_clean
;
7547 bnxt_hwrm_func_qcfg(bp
);
7548 bnxt_hwrm_port_led_qcaps(bp
);
7550 bnxt_set_rx_skb_mode(bp
, false);
7551 bnxt_set_tpa_flags(bp
);
7552 bnxt_set_ring_params(bp
);
7553 bnxt_set_max_func_irqs(bp
, max_irqs
);
7554 rc
= bnxt_set_dflt_rings(bp
);
7556 netdev_err(bp
->dev
, "Not enough rings available.\n");
7558 goto init_err_pci_clean
;
7561 /* Default RSS hash cfg. */
7562 bp
->rss_hash_cfg
= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4
|
7563 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4
|
7564 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6
|
7565 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6
;
7566 if (!BNXT_CHIP_NUM_57X0X(bp
->chip_num
) &&
7567 !BNXT_CHIP_TYPE_NITRO_A0(bp
) &&
7568 bp
->hwrm_spec_code
>= 0x10501) {
7569 bp
->flags
|= BNXT_FLAG_UDP_RSS_CAP
;
7570 bp
->rss_hash_cfg
|= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4
|
7571 VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6
;
7574 bnxt_hwrm_vnic_qcaps(bp
);
7575 if (bnxt_rfs_supported(bp
)) {
7576 dev
->hw_features
|= NETIF_F_NTUPLE
;
7577 if (bnxt_rfs_capable(bp
)) {
7578 bp
->flags
|= BNXT_FLAG_RFS
;
7579 dev
->features
|= NETIF_F_NTUPLE
;
7583 if (dev
->hw_features
& NETIF_F_HW_VLAN_CTAG_RX
)
7584 bp
->flags
|= BNXT_FLAG_STRIP_VLAN
;
7586 rc
= bnxt_probe_phy(bp
);
7588 goto init_err_pci_clean
;
7590 rc
= bnxt_init_int_mode(bp
);
7592 goto init_err_pci_clean
;
7594 rc
= register_netdev(dev
);
7596 goto init_err_clr_int
;
7598 netdev_info(dev
, "%s found at mem %lx, node addr %pM\n",
7599 board_info
[ent
->driver_data
].name
,
7600 (long)pci_resource_start(pdev
, 0), dev
->dev_addr
);
7602 bnxt_parse_log_pcie_link(bp
);
7607 bnxt_clear_int_mode(bp
);
7610 bnxt_cleanup_pci(bp
);
7618 * bnxt_io_error_detected - called when PCI error is detected
7619 * @pdev: Pointer to PCI device
7620 * @state: The current pci connection state
7622 * This function is called after a PCI bus error affecting
7623 * this device has been detected.
7625 static pci_ers_result_t
bnxt_io_error_detected(struct pci_dev
*pdev
,
7626 pci_channel_state_t state
)
7628 struct net_device
*netdev
= pci_get_drvdata(pdev
);
7629 struct bnxt
*bp
= netdev_priv(netdev
);
7631 netdev_info(netdev
, "PCI I/O error detected\n");
7634 netif_device_detach(netdev
);
7638 if (state
== pci_channel_io_perm_failure
) {
7640 return PCI_ERS_RESULT_DISCONNECT
;
7643 if (netif_running(netdev
))
7646 pci_disable_device(pdev
);
7649 /* Request a slot slot reset. */
7650 return PCI_ERS_RESULT_NEED_RESET
;
7654 * bnxt_io_slot_reset - called after the pci bus has been reset.
7655 * @pdev: Pointer to PCI device
7657 * Restart the card from scratch, as if from a cold-boot.
7658 * At this point, the card has exprienced a hard reset,
7659 * followed by fixups by BIOS, and has its config space
7660 * set up identically to what it was at cold boot.
7662 static pci_ers_result_t
bnxt_io_slot_reset(struct pci_dev
*pdev
)
7664 struct net_device
*netdev
= pci_get_drvdata(pdev
);
7665 struct bnxt
*bp
= netdev_priv(netdev
);
7667 pci_ers_result_t result
= PCI_ERS_RESULT_DISCONNECT
;
7669 netdev_info(bp
->dev
, "PCI Slot Reset\n");
7673 if (pci_enable_device(pdev
)) {
7675 "Cannot re-enable PCI device after reset.\n");
7677 pci_set_master(pdev
);
7679 err
= bnxt_hwrm_func_reset(bp
);
7680 if (!err
&& netif_running(netdev
))
7681 err
= bnxt_open(netdev
);
7684 result
= PCI_ERS_RESULT_RECOVERED
;
7689 if (result
!= PCI_ERS_RESULT_RECOVERED
&& netif_running(netdev
))
7694 err
= pci_cleanup_aer_uncorrect_error_status(pdev
);
7697 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7698 err
); /* non-fatal, continue */
7701 return PCI_ERS_RESULT_RECOVERED
;
7705 * bnxt_io_resume - called when traffic can start flowing again.
7706 * @pdev: Pointer to PCI device
7708 * This callback is called when the error recovery driver tells
7709 * us that its OK to resume normal operation.
7711 static void bnxt_io_resume(struct pci_dev
*pdev
)
7713 struct net_device
*netdev
= pci_get_drvdata(pdev
);
7717 netif_device_attach(netdev
);
7722 static const struct pci_error_handlers bnxt_err_handler
= {
7723 .error_detected
= bnxt_io_error_detected
,
7724 .slot_reset
= bnxt_io_slot_reset
,
7725 .resume
= bnxt_io_resume
7728 static struct pci_driver bnxt_pci_driver
= {
7729 .name
= DRV_MODULE_NAME
,
7730 .id_table
= bnxt_pci_tbl
,
7731 .probe
= bnxt_init_one
,
7732 .remove
= bnxt_remove_one
,
7733 .err_handler
= &bnxt_err_handler
,
7734 #if defined(CONFIG_BNXT_SRIOV)
7735 .sriov_configure
= bnxt_sriov_configure
,
7739 module_pci_driver(bnxt_pci_driver
);