1 /* Broadcom NetXtreme-C/E network driver.
3 * Copyright (c) 2014-2015 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
10 #include <linux/module.h>
12 #include <linux/stringify.h>
13 #include <linux/kernel.h>
14 #include <linux/timer.h>
15 #include <linux/errno.h>
16 #include <linux/ioport.h>
17 #include <linux/slab.h>
18 #include <linux/vmalloc.h>
19 #include <linux/interrupt.h>
20 #include <linux/pci.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23 #include <linux/skbuff.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/bitops.h>
27 #include <linux/irq.h>
28 #include <linux/delay.h>
29 #include <asm/byteorder.h>
31 #include <linux/time.h>
32 #include <linux/mii.h>
34 #include <linux/if_vlan.h>
38 #include <net/checksum.h>
39 #include <net/ip6_checksum.h>
40 #if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE)
41 #include <net/vxlan.h>
43 #ifdef CONFIG_NET_RX_BUSY_POLL
44 #include <net/busy_poll.h>
46 #include <linux/workqueue.h>
47 #include <linux/prefetch.h>
48 #include <linux/cache.h>
49 #include <linux/log2.h>
50 #include <linux/aer.h>
51 #include <linux/bitmap.h>
52 #include <linux/cpu_rmap.h>
56 #include "bnxt_sriov.h"
57 #include "bnxt_ethtool.h"
59 #define BNXT_TX_TIMEOUT (5 * HZ)
61 static const char version
[] =
62 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME
" v" DRV_MODULE_VERSION
"\n";
64 MODULE_LICENSE("GPL");
65 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
66 MODULE_VERSION(DRV_MODULE_VERSION
);
68 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
69 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
70 #define BNXT_RX_COPY_THRESH 256
72 #define BNXT_TX_PUSH_THRESH 92
83 /* indexed by enum above */
87 { "Broadcom BCM57302 NetXtreme-C Single-port 10Gb/25Gb/40Gb/50Gb Ethernet" },
88 { "Broadcom BCM57304 NetXtreme-C Dual-port 10Gb/25Gb/40Gb/50Gb Ethernet" },
89 { "Broadcom BCM57404 NetXtreme-E Dual-port 10Gb/25Gb Ethernet" },
90 { "Broadcom BCM57406 NetXtreme-E Dual-port 10Gb Ethernet" },
91 { "Broadcom BCM57304 NetXtreme-C Ethernet Virtual Function" },
92 { "Broadcom BCM57404 NetXtreme-E Ethernet Virtual Function" },
95 static const struct pci_device_id bnxt_pci_tbl
[] = {
96 { PCI_VDEVICE(BROADCOM
, 0x16c9), .driver_data
= BCM57302
},
97 { PCI_VDEVICE(BROADCOM
, 0x16ca), .driver_data
= BCM57304
},
98 { PCI_VDEVICE(BROADCOM
, 0x16d1), .driver_data
= BCM57404
},
99 { PCI_VDEVICE(BROADCOM
, 0x16d2), .driver_data
= BCM57406
},
100 #ifdef CONFIG_BNXT_SRIOV
101 { PCI_VDEVICE(BROADCOM
, 0x16cb), .driver_data
= BCM57304_VF
},
102 { PCI_VDEVICE(BROADCOM
, 0x16d3), .driver_data
= BCM57404_VF
},
107 MODULE_DEVICE_TABLE(pci
, bnxt_pci_tbl
);
109 static const u16 bnxt_vf_req_snif
[] = {
112 HWRM_CFA_L2_FILTER_ALLOC
,
115 static bool bnxt_vf_pciid(enum board_idx idx
)
117 return (idx
== BCM57304_VF
|| idx
== BCM57404_VF
);
120 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
121 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
122 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
124 #define BNXT_CP_DB_REARM(db, raw_cons) \
125 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
127 #define BNXT_CP_DB(db, raw_cons) \
128 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
130 #define BNXT_CP_DB_IRQ_DIS(db) \
131 writel(DB_CP_IRQ_DIS_FLAGS, db)
133 static inline u32
bnxt_tx_avail(struct bnxt
*bp
, struct bnxt_tx_ring_info
*txr
)
135 /* Tell compiler to fetch tx indices from memory. */
138 return bp
->tx_ring_size
-
139 ((txr
->tx_prod
- txr
->tx_cons
) & bp
->tx_ring_mask
);
142 static const u16 bnxt_lhint_arr
[] = {
143 TX_BD_FLAGS_LHINT_512_AND_SMALLER
,
144 TX_BD_FLAGS_LHINT_512_TO_1023
,
145 TX_BD_FLAGS_LHINT_1024_TO_2047
,
146 TX_BD_FLAGS_LHINT_1024_TO_2047
,
147 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
148 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
149 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
150 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
151 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
152 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
153 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
154 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
155 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
156 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
157 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
158 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
159 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
160 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
161 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
164 static netdev_tx_t
bnxt_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
166 struct bnxt
*bp
= netdev_priv(dev
);
168 struct tx_bd_ext
*txbd1
;
169 struct netdev_queue
*txq
;
172 unsigned int length
, pad
= 0;
173 u32 len
, free_size
, vlan_tag_flags
, cfa_action
, flags
;
175 struct pci_dev
*pdev
= bp
->pdev
;
176 struct bnxt_napi
*bnapi
;
177 struct bnxt_tx_ring_info
*txr
;
178 struct bnxt_sw_tx_bd
*tx_buf
;
180 i
= skb_get_queue_mapping(skb
);
181 if (unlikely(i
>= bp
->tx_nr_rings
)) {
182 dev_kfree_skb_any(skb
);
186 bnapi
= bp
->bnapi
[i
];
187 txr
= &bnapi
->tx_ring
;
188 txq
= netdev_get_tx_queue(dev
, i
);
191 free_size
= bnxt_tx_avail(bp
, txr
);
192 if (unlikely(free_size
< skb_shinfo(skb
)->nr_frags
+ 2)) {
193 netif_tx_stop_queue(txq
);
194 return NETDEV_TX_BUSY
;
198 len
= skb_headlen(skb
);
199 last_frag
= skb_shinfo(skb
)->nr_frags
;
201 txbd
= &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
203 txbd
->tx_bd_opaque
= prod
;
205 tx_buf
= &txr
->tx_buf_ring
[prod
];
207 tx_buf
->nr_frags
= last_frag
;
211 if (skb_vlan_tag_present(skb
)) {
212 vlan_tag_flags
= TX_BD_CFA_META_KEY_VLAN
|
213 skb_vlan_tag_get(skb
);
214 /* Currently supports 8021Q, 8021AD vlan offloads
215 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
217 if (skb
->vlan_proto
== htons(ETH_P_8021Q
))
218 vlan_tag_flags
|= 1 << TX_BD_CFA_META_TPID_SHIFT
;
221 if (free_size
== bp
->tx_ring_size
&& length
<= bp
->tx_push_thresh
) {
222 struct tx_push_bd
*push
= txr
->tx_push
;
223 struct tx_bd
*tx_push
= &push
->txbd1
;
224 struct tx_bd_ext
*tx_push1
= &push
->txbd2
;
225 void *pdata
= tx_push1
+ 1;
228 /* Set COAL_NOW to be ready quickly for the next push */
229 tx_push
->tx_bd_len_flags_type
=
230 cpu_to_le32((length
<< TX_BD_LEN_SHIFT
) |
231 TX_BD_TYPE_LONG_TX_BD
|
232 TX_BD_FLAGS_LHINT_512_AND_SMALLER
|
233 TX_BD_FLAGS_COAL_NOW
|
234 TX_BD_FLAGS_PACKET_END
|
235 (2 << TX_BD_FLAGS_BD_CNT_SHIFT
));
237 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
238 tx_push1
->tx_bd_hsize_lflags
=
239 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM
);
241 tx_push1
->tx_bd_hsize_lflags
= 0;
243 tx_push1
->tx_bd_cfa_meta
= cpu_to_le32(vlan_tag_flags
);
244 tx_push1
->tx_bd_cfa_action
= cpu_to_le32(cfa_action
);
246 skb_copy_from_linear_data(skb
, pdata
, len
);
248 for (j
= 0; j
< last_frag
; j
++) {
249 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[j
];
252 fptr
= skb_frag_address_safe(frag
);
256 memcpy(pdata
, fptr
, skb_frag_size(frag
));
257 pdata
+= skb_frag_size(frag
);
260 memcpy(txbd
, tx_push
, sizeof(*txbd
));
261 prod
= NEXT_TX(prod
);
262 txbd
= &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
263 memcpy(txbd
, tx_push1
, sizeof(*txbd
));
264 prod
= NEXT_TX(prod
);
266 cpu_to_le32(DB_KEY_TX_PUSH
| DB_LONG_TX_PUSH
| prod
);
269 netdev_tx_sent_queue(txq
, skb
->len
);
271 __iowrite64_copy(txr
->tx_doorbell
, push
,
272 (length
+ sizeof(*push
) + 8) / 8);
280 if (length
< BNXT_MIN_PKT_SIZE
) {
281 pad
= BNXT_MIN_PKT_SIZE
- length
;
282 if (skb_pad(skb
, pad
)) {
283 /* SKB already freed. */
287 length
= BNXT_MIN_PKT_SIZE
;
290 mapping
= dma_map_single(&pdev
->dev
, skb
->data
, len
, DMA_TO_DEVICE
);
292 if (unlikely(dma_mapping_error(&pdev
->dev
, mapping
))) {
293 dev_kfree_skb_any(skb
);
298 dma_unmap_addr_set(tx_buf
, mapping
, mapping
);
299 flags
= (len
<< TX_BD_LEN_SHIFT
) | TX_BD_TYPE_LONG_TX_BD
|
300 ((last_frag
+ 2) << TX_BD_FLAGS_BD_CNT_SHIFT
);
302 txbd
->tx_bd_haddr
= cpu_to_le64(mapping
);
304 prod
= NEXT_TX(prod
);
305 txbd1
= (struct tx_bd_ext
*)
306 &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
308 txbd1
->tx_bd_hsize_lflags
= 0;
309 if (skb_is_gso(skb
)) {
312 if (skb
->encapsulation
)
313 hdr_len
= skb_inner_network_offset(skb
) +
314 skb_inner_network_header_len(skb
) +
315 inner_tcp_hdrlen(skb
);
317 hdr_len
= skb_transport_offset(skb
) +
320 txbd1
->tx_bd_hsize_lflags
= cpu_to_le32(TX_BD_FLAGS_LSO
|
322 (hdr_len
<< (TX_BD_HSIZE_SHIFT
- 1)));
323 length
= skb_shinfo(skb
)->gso_size
;
324 txbd1
->tx_bd_mss
= cpu_to_le32(length
);
326 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
327 txbd1
->tx_bd_hsize_lflags
=
328 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM
);
329 txbd1
->tx_bd_mss
= 0;
333 flags
|= bnxt_lhint_arr
[length
];
334 txbd
->tx_bd_len_flags_type
= cpu_to_le32(flags
);
336 txbd1
->tx_bd_cfa_meta
= cpu_to_le32(vlan_tag_flags
);
337 txbd1
->tx_bd_cfa_action
= cpu_to_le32(cfa_action
);
338 for (i
= 0; i
< last_frag
; i
++) {
339 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
341 prod
= NEXT_TX(prod
);
342 txbd
= &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
344 len
= skb_frag_size(frag
);
345 mapping
= skb_frag_dma_map(&pdev
->dev
, frag
, 0, len
,
348 if (unlikely(dma_mapping_error(&pdev
->dev
, mapping
)))
351 tx_buf
= &txr
->tx_buf_ring
[prod
];
352 dma_unmap_addr_set(tx_buf
, mapping
, mapping
);
354 txbd
->tx_bd_haddr
= cpu_to_le64(mapping
);
356 flags
= len
<< TX_BD_LEN_SHIFT
;
357 txbd
->tx_bd_len_flags_type
= cpu_to_le32(flags
);
361 txbd
->tx_bd_len_flags_type
=
362 cpu_to_le32(((len
+ pad
) << TX_BD_LEN_SHIFT
) | flags
|
363 TX_BD_FLAGS_PACKET_END
);
365 netdev_tx_sent_queue(txq
, skb
->len
);
367 /* Sync BD data before updating doorbell */
370 prod
= NEXT_TX(prod
);
373 writel(DB_KEY_TX
| prod
, txr
->tx_doorbell
);
374 writel(DB_KEY_TX
| prod
, txr
->tx_doorbell
);
380 if (unlikely(bnxt_tx_avail(bp
, txr
) <= MAX_SKB_FRAGS
+ 1)) {
381 netif_tx_stop_queue(txq
);
383 /* netif_tx_stop_queue() must be done before checking
384 * tx index in bnxt_tx_avail() below, because in
385 * bnxt_tx_int(), we update tx index before checking for
386 * netif_tx_queue_stopped().
389 if (bnxt_tx_avail(bp
, txr
) > bp
->tx_wake_thresh
)
390 netif_tx_wake_queue(txq
);
397 /* start back at beginning and unmap skb */
399 tx_buf
= &txr
->tx_buf_ring
[prod
];
401 dma_unmap_single(&pdev
->dev
, dma_unmap_addr(tx_buf
, mapping
),
402 skb_headlen(skb
), PCI_DMA_TODEVICE
);
403 prod
= NEXT_TX(prod
);
405 /* unmap remaining mapped pages */
406 for (i
= 0; i
< last_frag
; i
++) {
407 prod
= NEXT_TX(prod
);
408 tx_buf
= &txr
->tx_buf_ring
[prod
];
409 dma_unmap_page(&pdev
->dev
, dma_unmap_addr(tx_buf
, mapping
),
410 skb_frag_size(&skb_shinfo(skb
)->frags
[i
]),
414 dev_kfree_skb_any(skb
);
418 static void bnxt_tx_int(struct bnxt
*bp
, struct bnxt_napi
*bnapi
, int nr_pkts
)
420 struct bnxt_tx_ring_info
*txr
= &bnapi
->tx_ring
;
421 int index
= bnapi
->index
;
422 struct netdev_queue
*txq
= netdev_get_tx_queue(bp
->dev
, index
);
423 u16 cons
= txr
->tx_cons
;
424 struct pci_dev
*pdev
= bp
->pdev
;
426 unsigned int tx_bytes
= 0;
428 for (i
= 0; i
< nr_pkts
; i
++) {
429 struct bnxt_sw_tx_bd
*tx_buf
;
433 tx_buf
= &txr
->tx_buf_ring
[cons
];
434 cons
= NEXT_TX(cons
);
438 if (tx_buf
->is_push
) {
443 dma_unmap_single(&pdev
->dev
, dma_unmap_addr(tx_buf
, mapping
),
444 skb_headlen(skb
), PCI_DMA_TODEVICE
);
445 last
= tx_buf
->nr_frags
;
447 for (j
= 0; j
< last
; j
++) {
448 cons
= NEXT_TX(cons
);
449 tx_buf
= &txr
->tx_buf_ring
[cons
];
452 dma_unmap_addr(tx_buf
, mapping
),
453 skb_frag_size(&skb_shinfo(skb
)->frags
[j
]),
458 cons
= NEXT_TX(cons
);
460 tx_bytes
+= skb
->len
;
461 dev_kfree_skb_any(skb
);
464 netdev_tx_completed_queue(txq
, nr_pkts
, tx_bytes
);
467 /* Need to make the tx_cons update visible to bnxt_start_xmit()
468 * before checking for netif_tx_queue_stopped(). Without the
469 * memory barrier, there is a small possibility that bnxt_start_xmit()
470 * will miss it and cause the queue to be stopped forever.
474 if (unlikely(netif_tx_queue_stopped(txq
)) &&
475 (bnxt_tx_avail(bp
, txr
) > bp
->tx_wake_thresh
)) {
476 __netif_tx_lock(txq
, smp_processor_id());
477 if (netif_tx_queue_stopped(txq
) &&
478 bnxt_tx_avail(bp
, txr
) > bp
->tx_wake_thresh
&&
479 txr
->dev_state
!= BNXT_DEV_STATE_CLOSING
)
480 netif_tx_wake_queue(txq
);
481 __netif_tx_unlock(txq
);
485 static inline u8
*__bnxt_alloc_rx_data(struct bnxt
*bp
, dma_addr_t
*mapping
,
489 struct pci_dev
*pdev
= bp
->pdev
;
491 data
= kmalloc(bp
->rx_buf_size
, gfp
);
495 *mapping
= dma_map_single(&pdev
->dev
, data
+ BNXT_RX_DMA_OFFSET
,
496 bp
->rx_buf_use_size
, PCI_DMA_FROMDEVICE
);
498 if (dma_mapping_error(&pdev
->dev
, *mapping
)) {
505 static inline int bnxt_alloc_rx_data(struct bnxt
*bp
,
506 struct bnxt_rx_ring_info
*rxr
,
509 struct rx_bd
*rxbd
= &rxr
->rx_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
510 struct bnxt_sw_rx_bd
*rx_buf
= &rxr
->rx_buf_ring
[prod
];
514 data
= __bnxt_alloc_rx_data(bp
, &mapping
, gfp
);
519 dma_unmap_addr_set(rx_buf
, mapping
, mapping
);
521 rxbd
->rx_bd_haddr
= cpu_to_le64(mapping
);
526 static void bnxt_reuse_rx_data(struct bnxt_rx_ring_info
*rxr
, u16 cons
,
529 u16 prod
= rxr
->rx_prod
;
530 struct bnxt_sw_rx_bd
*cons_rx_buf
, *prod_rx_buf
;
531 struct rx_bd
*cons_bd
, *prod_bd
;
533 prod_rx_buf
= &rxr
->rx_buf_ring
[prod
];
534 cons_rx_buf
= &rxr
->rx_buf_ring
[cons
];
536 prod_rx_buf
->data
= data
;
538 dma_unmap_addr_set(prod_rx_buf
, mapping
,
539 dma_unmap_addr(cons_rx_buf
, mapping
));
541 prod_bd
= &rxr
->rx_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
542 cons_bd
= &rxr
->rx_desc_ring
[RX_RING(cons
)][RX_IDX(cons
)];
544 prod_bd
->rx_bd_haddr
= cons_bd
->rx_bd_haddr
;
547 static inline u16
bnxt_find_next_agg_idx(struct bnxt_rx_ring_info
*rxr
, u16 idx
)
549 u16 next
, max
= rxr
->rx_agg_bmap_size
;
551 next
= find_next_zero_bit(rxr
->rx_agg_bmap
, max
, idx
);
553 next
= find_first_zero_bit(rxr
->rx_agg_bmap
, max
);
557 static inline int bnxt_alloc_rx_page(struct bnxt
*bp
,
558 struct bnxt_rx_ring_info
*rxr
,
562 &rxr
->rx_agg_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
563 struct bnxt_sw_rx_agg_bd
*rx_agg_buf
;
564 struct pci_dev
*pdev
= bp
->pdev
;
567 u16 sw_prod
= rxr
->rx_sw_agg_prod
;
569 page
= alloc_page(gfp
);
573 mapping
= dma_map_page(&pdev
->dev
, page
, 0, PAGE_SIZE
,
575 if (dma_mapping_error(&pdev
->dev
, mapping
)) {
580 if (unlikely(test_bit(sw_prod
, rxr
->rx_agg_bmap
)))
581 sw_prod
= bnxt_find_next_agg_idx(rxr
, sw_prod
);
583 __set_bit(sw_prod
, rxr
->rx_agg_bmap
);
584 rx_agg_buf
= &rxr
->rx_agg_ring
[sw_prod
];
585 rxr
->rx_sw_agg_prod
= NEXT_RX_AGG(sw_prod
);
587 rx_agg_buf
->page
= page
;
588 rx_agg_buf
->mapping
= mapping
;
589 rxbd
->rx_bd_haddr
= cpu_to_le64(mapping
);
590 rxbd
->rx_bd_opaque
= sw_prod
;
594 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi
*bnapi
, u16 cp_cons
,
597 struct bnxt
*bp
= bnapi
->bp
;
598 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
599 struct bnxt_rx_ring_info
*rxr
= &bnapi
->rx_ring
;
600 u16 prod
= rxr
->rx_agg_prod
;
601 u16 sw_prod
= rxr
->rx_sw_agg_prod
;
604 for (i
= 0; i
< agg_bufs
; i
++) {
606 struct rx_agg_cmp
*agg
;
607 struct bnxt_sw_rx_agg_bd
*cons_rx_buf
, *prod_rx_buf
;
608 struct rx_bd
*prod_bd
;
611 agg
= (struct rx_agg_cmp
*)
612 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
613 cons
= agg
->rx_agg_cmp_opaque
;
614 __clear_bit(cons
, rxr
->rx_agg_bmap
);
616 if (unlikely(test_bit(sw_prod
, rxr
->rx_agg_bmap
)))
617 sw_prod
= bnxt_find_next_agg_idx(rxr
, sw_prod
);
619 __set_bit(sw_prod
, rxr
->rx_agg_bmap
);
620 prod_rx_buf
= &rxr
->rx_agg_ring
[sw_prod
];
621 cons_rx_buf
= &rxr
->rx_agg_ring
[cons
];
623 /* It is possible for sw_prod to be equal to cons, so
624 * set cons_rx_buf->page to NULL first.
626 page
= cons_rx_buf
->page
;
627 cons_rx_buf
->page
= NULL
;
628 prod_rx_buf
->page
= page
;
630 prod_rx_buf
->mapping
= cons_rx_buf
->mapping
;
632 prod_bd
= &rxr
->rx_agg_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
634 prod_bd
->rx_bd_haddr
= cpu_to_le64(cons_rx_buf
->mapping
);
635 prod_bd
->rx_bd_opaque
= sw_prod
;
637 prod
= NEXT_RX_AGG(prod
);
638 sw_prod
= NEXT_RX_AGG(sw_prod
);
639 cp_cons
= NEXT_CMP(cp_cons
);
641 rxr
->rx_agg_prod
= prod
;
642 rxr
->rx_sw_agg_prod
= sw_prod
;
645 static struct sk_buff
*bnxt_rx_skb(struct bnxt
*bp
,
646 struct bnxt_rx_ring_info
*rxr
, u16 cons
,
647 u16 prod
, u8
*data
, dma_addr_t dma_addr
,
653 err
= bnxt_alloc_rx_data(bp
, rxr
, prod
, GFP_ATOMIC
);
655 bnxt_reuse_rx_data(rxr
, cons
, data
);
659 skb
= build_skb(data
, 0);
660 dma_unmap_single(&bp
->pdev
->dev
, dma_addr
, bp
->rx_buf_use_size
,
667 skb_reserve(skb
, BNXT_RX_OFFSET
);
672 static struct sk_buff
*bnxt_rx_pages(struct bnxt
*bp
, struct bnxt_napi
*bnapi
,
673 struct sk_buff
*skb
, u16 cp_cons
,
676 struct pci_dev
*pdev
= bp
->pdev
;
677 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
678 struct bnxt_rx_ring_info
*rxr
= &bnapi
->rx_ring
;
679 u16 prod
= rxr
->rx_agg_prod
;
682 for (i
= 0; i
< agg_bufs
; i
++) {
684 struct rx_agg_cmp
*agg
;
685 struct bnxt_sw_rx_agg_bd
*cons_rx_buf
;
689 agg
= (struct rx_agg_cmp
*)
690 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
691 cons
= agg
->rx_agg_cmp_opaque
;
692 frag_len
= (le32_to_cpu(agg
->rx_agg_cmp_len_flags_type
) &
693 RX_AGG_CMP_LEN
) >> RX_AGG_CMP_LEN_SHIFT
;
695 cons_rx_buf
= &rxr
->rx_agg_ring
[cons
];
696 skb_fill_page_desc(skb
, i
, cons_rx_buf
->page
, 0, frag_len
);
697 __clear_bit(cons
, rxr
->rx_agg_bmap
);
699 /* It is possible for bnxt_alloc_rx_page() to allocate
700 * a sw_prod index that equals the cons index, so we
701 * need to clear the cons entry now.
703 mapping
= dma_unmap_addr(cons_rx_buf
, mapping
);
704 page
= cons_rx_buf
->page
;
705 cons_rx_buf
->page
= NULL
;
707 if (bnxt_alloc_rx_page(bp
, rxr
, prod
, GFP_ATOMIC
) != 0) {
708 struct skb_shared_info
*shinfo
;
709 unsigned int nr_frags
;
711 shinfo
= skb_shinfo(skb
);
712 nr_frags
= --shinfo
->nr_frags
;
713 __skb_frag_set_page(&shinfo
->frags
[nr_frags
], NULL
);
717 cons_rx_buf
->page
= page
;
719 /* Update prod since possibly some pages have been
722 rxr
->rx_agg_prod
= prod
;
723 bnxt_reuse_rx_agg_bufs(bnapi
, cp_cons
, agg_bufs
- i
);
727 dma_unmap_page(&pdev
->dev
, mapping
, PAGE_SIZE
,
730 skb
->data_len
+= frag_len
;
731 skb
->len
+= frag_len
;
732 skb
->truesize
+= PAGE_SIZE
;
734 prod
= NEXT_RX_AGG(prod
);
735 cp_cons
= NEXT_CMP(cp_cons
);
737 rxr
->rx_agg_prod
= prod
;
741 static int bnxt_agg_bufs_valid(struct bnxt
*bp
, struct bnxt_cp_ring_info
*cpr
,
742 u8 agg_bufs
, u32
*raw_cons
)
745 struct rx_agg_cmp
*agg
;
747 *raw_cons
= ADV_RAW_CMP(*raw_cons
, agg_bufs
);
748 last
= RING_CMP(*raw_cons
);
749 agg
= (struct rx_agg_cmp
*)
750 &cpr
->cp_desc_ring
[CP_RING(last
)][CP_IDX(last
)];
751 return RX_AGG_CMP_VALID(agg
, *raw_cons
);
754 static inline struct sk_buff
*bnxt_copy_skb(struct bnxt_napi
*bnapi
, u8
*data
,
758 struct bnxt
*bp
= bnapi
->bp
;
759 struct pci_dev
*pdev
= bp
->pdev
;
762 skb
= napi_alloc_skb(&bnapi
->napi
, len
);
766 dma_sync_single_for_cpu(&pdev
->dev
, mapping
,
767 bp
->rx_copy_thresh
, PCI_DMA_FROMDEVICE
);
769 memcpy(skb
->data
- BNXT_RX_OFFSET
, data
, len
+ BNXT_RX_OFFSET
);
771 dma_sync_single_for_device(&pdev
->dev
, mapping
,
779 static void bnxt_tpa_start(struct bnxt
*bp
, struct bnxt_rx_ring_info
*rxr
,
780 struct rx_tpa_start_cmp
*tpa_start
,
781 struct rx_tpa_start_cmp_ext
*tpa_start1
)
783 u8 agg_id
= TPA_START_AGG_ID(tpa_start
);
785 struct bnxt_tpa_info
*tpa_info
;
786 struct bnxt_sw_rx_bd
*cons_rx_buf
, *prod_rx_buf
;
787 struct rx_bd
*prod_bd
;
790 cons
= tpa_start
->rx_tpa_start_cmp_opaque
;
792 cons_rx_buf
= &rxr
->rx_buf_ring
[cons
];
793 prod_rx_buf
= &rxr
->rx_buf_ring
[prod
];
794 tpa_info
= &rxr
->rx_tpa
[agg_id
];
796 prod_rx_buf
->data
= tpa_info
->data
;
798 mapping
= tpa_info
->mapping
;
799 dma_unmap_addr_set(prod_rx_buf
, mapping
, mapping
);
801 prod_bd
= &rxr
->rx_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
803 prod_bd
->rx_bd_haddr
= cpu_to_le64(mapping
);
805 tpa_info
->data
= cons_rx_buf
->data
;
806 cons_rx_buf
->data
= NULL
;
807 tpa_info
->mapping
= dma_unmap_addr(cons_rx_buf
, mapping
);
810 le32_to_cpu(tpa_start
->rx_tpa_start_cmp_len_flags_type
) >>
811 RX_TPA_START_CMP_LEN_SHIFT
;
812 if (likely(TPA_START_HASH_VALID(tpa_start
))) {
813 u32 hash_type
= TPA_START_HASH_TYPE(tpa_start
);
815 tpa_info
->hash_type
= PKT_HASH_TYPE_L4
;
816 tpa_info
->gso_type
= SKB_GSO_TCPV4
;
817 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
819 tpa_info
->gso_type
= SKB_GSO_TCPV6
;
821 le32_to_cpu(tpa_start
->rx_tpa_start_cmp_rss_hash
);
823 tpa_info
->hash_type
= PKT_HASH_TYPE_NONE
;
824 tpa_info
->gso_type
= 0;
825 if (netif_msg_rx_err(bp
))
826 netdev_warn(bp
->dev
, "TPA packet without valid hash\n");
828 tpa_info
->flags2
= le32_to_cpu(tpa_start1
->rx_tpa_start_cmp_flags2
);
829 tpa_info
->metadata
= le32_to_cpu(tpa_start1
->rx_tpa_start_cmp_metadata
);
831 rxr
->rx_prod
= NEXT_RX(prod
);
832 cons
= NEXT_RX(cons
);
833 cons_rx_buf
= &rxr
->rx_buf_ring
[cons
];
835 bnxt_reuse_rx_data(rxr
, cons
, cons_rx_buf
->data
);
836 rxr
->rx_prod
= NEXT_RX(rxr
->rx_prod
);
837 cons_rx_buf
->data
= NULL
;
840 static void bnxt_abort_tpa(struct bnxt
*bp
, struct bnxt_napi
*bnapi
,
841 u16 cp_cons
, u32 agg_bufs
)
844 bnxt_reuse_rx_agg_bufs(bnapi
, cp_cons
, agg_bufs
);
847 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
848 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
850 static inline struct sk_buff
*bnxt_gro_skb(struct bnxt_tpa_info
*tpa_info
,
851 struct rx_tpa_end_cmp
*tpa_end
,
852 struct rx_tpa_end_cmp_ext
*tpa_end1
,
857 int payload_off
, tcp_opt_len
= 0;
860 NAPI_GRO_CB(skb
)->count
= TPA_END_TPA_SEGS(tpa_end
);
861 skb_shinfo(skb
)->gso_size
=
862 le32_to_cpu(tpa_end1
->rx_tpa_end_cmp_seg_len
);
863 skb_shinfo(skb
)->gso_type
= tpa_info
->gso_type
;
864 payload_off
= (le32_to_cpu(tpa_end
->rx_tpa_end_cmp_misc_v1
) &
865 RX_TPA_END_CMP_PAYLOAD_OFFSET
) >>
866 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT
;
867 if (TPA_END_GRO_TS(tpa_end
))
870 if (tpa_info
->gso_type
== SKB_GSO_TCPV4
) {
873 nw_off
= payload_off
- BNXT_IPV4_HDR_SIZE
- tcp_opt_len
-
875 skb_set_network_header(skb
, nw_off
);
877 skb_set_transport_header(skb
, nw_off
+ sizeof(struct iphdr
));
878 len
= skb
->len
- skb_transport_offset(skb
);
880 th
->check
= ~tcp_v4_check(len
, iph
->saddr
, iph
->daddr
, 0);
881 } else if (tpa_info
->gso_type
== SKB_GSO_TCPV6
) {
884 nw_off
= payload_off
- BNXT_IPV6_HDR_SIZE
- tcp_opt_len
-
886 skb_set_network_header(skb
, nw_off
);
888 skb_set_transport_header(skb
, nw_off
+ sizeof(struct ipv6hdr
));
889 len
= skb
->len
- skb_transport_offset(skb
);
891 th
->check
= ~tcp_v6_check(len
, &iph
->saddr
, &iph
->daddr
, 0);
893 dev_kfree_skb_any(skb
);
896 tcp_gro_complete(skb
);
898 if (nw_off
) { /* tunnel */
899 struct udphdr
*uh
= NULL
;
901 if (skb
->protocol
== htons(ETH_P_IP
)) {
902 struct iphdr
*iph
= (struct iphdr
*)skb
->data
;
904 if (iph
->protocol
== IPPROTO_UDP
)
905 uh
= (struct udphdr
*)(iph
+ 1);
907 struct ipv6hdr
*iph
= (struct ipv6hdr
*)skb
->data
;
909 if (iph
->nexthdr
== IPPROTO_UDP
)
910 uh
= (struct udphdr
*)(iph
+ 1);
914 skb_shinfo(skb
)->gso_type
|=
915 SKB_GSO_UDP_TUNNEL_CSUM
;
917 skb_shinfo(skb
)->gso_type
|= SKB_GSO_UDP_TUNNEL
;
924 static inline struct sk_buff
*bnxt_tpa_end(struct bnxt
*bp
,
925 struct bnxt_napi
*bnapi
,
927 struct rx_tpa_end_cmp
*tpa_end
,
928 struct rx_tpa_end_cmp_ext
*tpa_end1
,
931 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
932 struct bnxt_rx_ring_info
*rxr
= &bnapi
->rx_ring
;
933 u8 agg_id
= TPA_END_AGG_ID(tpa_end
);
935 u16 cp_cons
= RING_CMP(*raw_cons
);
937 struct bnxt_tpa_info
*tpa_info
;
941 tpa_info
= &rxr
->rx_tpa
[agg_id
];
942 data
= tpa_info
->data
;
945 mapping
= tpa_info
->mapping
;
947 agg_bufs
= (le32_to_cpu(tpa_end
->rx_tpa_end_cmp_misc_v1
) &
948 RX_TPA_END_CMP_AGG_BUFS
) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT
;
951 if (!bnxt_agg_bufs_valid(bp
, cpr
, agg_bufs
, raw_cons
))
952 return ERR_PTR(-EBUSY
);
955 cp_cons
= NEXT_CMP(cp_cons
);
958 if (unlikely(agg_bufs
> MAX_SKB_FRAGS
)) {
959 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
960 netdev_warn(bp
->dev
, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
961 agg_bufs
, (int)MAX_SKB_FRAGS
);
965 if (len
<= bp
->rx_copy_thresh
) {
966 skb
= bnxt_copy_skb(bnapi
, data
, len
, mapping
);
968 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
973 dma_addr_t new_mapping
;
975 new_data
= __bnxt_alloc_rx_data(bp
, &new_mapping
, GFP_ATOMIC
);
977 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
981 tpa_info
->data
= new_data
;
982 tpa_info
->mapping
= new_mapping
;
984 skb
= build_skb(data
, 0);
985 dma_unmap_single(&bp
->pdev
->dev
, mapping
, bp
->rx_buf_use_size
,
990 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
993 skb_reserve(skb
, BNXT_RX_OFFSET
);
998 skb
= bnxt_rx_pages(bp
, bnapi
, skb
, cp_cons
, agg_bufs
);
1000 /* Page reuse already handled by bnxt_rx_pages(). */
1004 skb
->protocol
= eth_type_trans(skb
, bp
->dev
);
1006 if (tpa_info
->hash_type
!= PKT_HASH_TYPE_NONE
)
1007 skb_set_hash(skb
, tpa_info
->rss_hash
, tpa_info
->hash_type
);
1009 if (tpa_info
->flags2
& RX_CMP_FLAGS2_META_FORMAT_VLAN
) {
1010 netdev_features_t features
= skb
->dev
->features
;
1011 u16 vlan_proto
= tpa_info
->metadata
>>
1012 RX_CMP_FLAGS2_METADATA_TPID_SFT
;
1014 if (((features
& NETIF_F_HW_VLAN_CTAG_RX
) &&
1015 vlan_proto
== ETH_P_8021Q
) ||
1016 ((features
& NETIF_F_HW_VLAN_STAG_RX
) &&
1017 vlan_proto
== ETH_P_8021AD
)) {
1018 __vlan_hwaccel_put_tag(skb
, htons(vlan_proto
),
1019 tpa_info
->metadata
&
1020 RX_CMP_FLAGS2_METADATA_VID_MASK
);
1024 skb_checksum_none_assert(skb
);
1025 if (likely(tpa_info
->flags2
& RX_TPA_START_CMP_FLAGS2_L4_CS_CALC
)) {
1026 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1028 (tpa_info
->flags2
& RX_CMP_FLAGS2_T_L4_CS_CALC
) >> 3;
1031 if (TPA_END_GRO(tpa_end
))
1032 skb
= bnxt_gro_skb(tpa_info
, tpa_end
, tpa_end1
, skb
);
1037 /* returns the following:
1038 * 1 - 1 packet successfully received
1039 * 0 - successful TPA_START, packet not completed yet
1040 * -EBUSY - completion ring does not have all the agg buffers yet
1041 * -ENOMEM - packet aborted due to out of memory
1042 * -EIO - packet aborted due to hw error indicated in BD
1044 static int bnxt_rx_pkt(struct bnxt
*bp
, struct bnxt_napi
*bnapi
, u32
*raw_cons
,
1047 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1048 struct bnxt_rx_ring_info
*rxr
= &bnapi
->rx_ring
;
1049 struct net_device
*dev
= bp
->dev
;
1050 struct rx_cmp
*rxcmp
;
1051 struct rx_cmp_ext
*rxcmp1
;
1052 u32 tmp_raw_cons
= *raw_cons
;
1053 u16 cons
, prod
, cp_cons
= RING_CMP(tmp_raw_cons
);
1054 struct bnxt_sw_rx_bd
*rx_buf
;
1056 u8
*data
, agg_bufs
, cmp_type
;
1057 dma_addr_t dma_addr
;
1058 struct sk_buff
*skb
;
1061 rxcmp
= (struct rx_cmp
*)
1062 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
1064 tmp_raw_cons
= NEXT_RAW_CMP(tmp_raw_cons
);
1065 cp_cons
= RING_CMP(tmp_raw_cons
);
1066 rxcmp1
= (struct rx_cmp_ext
*)
1067 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
1069 if (!RX_CMP_VALID(rxcmp1
, tmp_raw_cons
))
1072 cmp_type
= RX_CMP_TYPE(rxcmp
);
1074 prod
= rxr
->rx_prod
;
1076 if (cmp_type
== CMP_TYPE_RX_L2_TPA_START_CMP
) {
1077 bnxt_tpa_start(bp
, rxr
, (struct rx_tpa_start_cmp
*)rxcmp
,
1078 (struct rx_tpa_start_cmp_ext
*)rxcmp1
);
1080 goto next_rx_no_prod
;
1082 } else if (cmp_type
== CMP_TYPE_RX_L2_TPA_END_CMP
) {
1083 skb
= bnxt_tpa_end(bp
, bnapi
, &tmp_raw_cons
,
1084 (struct rx_tpa_end_cmp
*)rxcmp
,
1085 (struct rx_tpa_end_cmp_ext
*)rxcmp1
,
1088 if (unlikely(IS_ERR(skb
)))
1093 skb_record_rx_queue(skb
, bnapi
->index
);
1094 skb_mark_napi_id(skb
, &bnapi
->napi
);
1095 if (bnxt_busy_polling(bnapi
))
1096 netif_receive_skb(skb
);
1098 napi_gro_receive(&bnapi
->napi
, skb
);
1101 goto next_rx_no_prod
;
1104 cons
= rxcmp
->rx_cmp_opaque
;
1105 rx_buf
= &rxr
->rx_buf_ring
[cons
];
1106 data
= rx_buf
->data
;
1109 agg_bufs
= (le32_to_cpu(rxcmp
->rx_cmp_misc_v1
) & RX_CMP_AGG_BUFS
) >>
1110 RX_CMP_AGG_BUFS_SHIFT
;
1113 if (!bnxt_agg_bufs_valid(bp
, cpr
, agg_bufs
, &tmp_raw_cons
))
1116 cp_cons
= NEXT_CMP(cp_cons
);
1120 rx_buf
->data
= NULL
;
1121 if (rxcmp1
->rx_cmp_cfa_code_errors_v2
& RX_CMP_L2_ERRORS
) {
1122 bnxt_reuse_rx_data(rxr
, cons
, data
);
1124 bnxt_reuse_rx_agg_bufs(bnapi
, cp_cons
, agg_bufs
);
1130 len
= le32_to_cpu(rxcmp
->rx_cmp_len_flags_type
) >> RX_CMP_LEN_SHIFT
;
1131 dma_addr
= dma_unmap_addr(rx_buf
, mapping
);
1133 if (len
<= bp
->rx_copy_thresh
) {
1134 skb
= bnxt_copy_skb(bnapi
, data
, len
, dma_addr
);
1135 bnxt_reuse_rx_data(rxr
, cons
, data
);
1141 skb
= bnxt_rx_skb(bp
, rxr
, cons
, prod
, data
, dma_addr
, len
);
1149 skb
= bnxt_rx_pages(bp
, bnapi
, skb
, cp_cons
, agg_bufs
);
1156 if (RX_CMP_HASH_VALID(rxcmp
)) {
1157 u32 hash_type
= RX_CMP_HASH_TYPE(rxcmp
);
1158 enum pkt_hash_types type
= PKT_HASH_TYPE_L4
;
1160 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1161 if (hash_type
!= 1 && hash_type
!= 3)
1162 type
= PKT_HASH_TYPE_L3
;
1163 skb_set_hash(skb
, le32_to_cpu(rxcmp
->rx_cmp_rss_hash
), type
);
1166 skb
->protocol
= eth_type_trans(skb
, dev
);
1168 if (rxcmp1
->rx_cmp_flags2
&
1169 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN
)) {
1170 netdev_features_t features
= skb
->dev
->features
;
1171 u32 meta_data
= le32_to_cpu(rxcmp1
->rx_cmp_meta_data
);
1172 u16 vlan_proto
= meta_data
>> RX_CMP_FLAGS2_METADATA_TPID_SFT
;
1174 if (((features
& NETIF_F_HW_VLAN_CTAG_RX
) &&
1175 vlan_proto
== ETH_P_8021Q
) ||
1176 ((features
& NETIF_F_HW_VLAN_STAG_RX
) &&
1177 vlan_proto
== ETH_P_8021AD
))
1178 __vlan_hwaccel_put_tag(skb
, htons(vlan_proto
),
1180 RX_CMP_FLAGS2_METADATA_VID_MASK
);
1183 skb_checksum_none_assert(skb
);
1184 if (RX_CMP_L4_CS_OK(rxcmp1
)) {
1185 if (dev
->features
& NETIF_F_RXCSUM
) {
1186 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1187 skb
->csum_level
= RX_CMP_ENCAP(rxcmp1
);
1190 if (rxcmp1
->rx_cmp_cfa_code_errors_v2
& RX_CMP_L4_CS_ERR_BITS
)
1191 cpr
->rx_l4_csum_errors
++;
1194 skb_record_rx_queue(skb
, bnapi
->index
);
1195 skb_mark_napi_id(skb
, &bnapi
->napi
);
1196 if (bnxt_busy_polling(bnapi
))
1197 netif_receive_skb(skb
);
1199 napi_gro_receive(&bnapi
->napi
, skb
);
1203 rxr
->rx_prod
= NEXT_RX(prod
);
1206 *raw_cons
= tmp_raw_cons
;
1211 static int bnxt_async_event_process(struct bnxt
*bp
,
1212 struct hwrm_async_event_cmpl
*cmpl
)
1214 u16 event_id
= le16_to_cpu(cmpl
->event_id
);
1216 /* TODO CHIMP_FW: Define event id's for link change, error etc */
1218 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE
:
1219 set_bit(BNXT_LINK_CHNG_SP_EVENT
, &bp
->sp_event
);
1220 schedule_work(&bp
->sp_task
);
1223 netdev_err(bp
->dev
, "unhandled ASYNC event (id 0x%x)\n",
1230 static int bnxt_hwrm_handler(struct bnxt
*bp
, struct tx_cmp
*txcmp
)
1232 u16 cmpl_type
= TX_CMP_TYPE(txcmp
), vf_id
, seq_id
;
1233 struct hwrm_cmpl
*h_cmpl
= (struct hwrm_cmpl
*)txcmp
;
1234 struct hwrm_fwd_req_cmpl
*fwd_req_cmpl
=
1235 (struct hwrm_fwd_req_cmpl
*)txcmp
;
1237 switch (cmpl_type
) {
1238 case CMPL_BASE_TYPE_HWRM_DONE
:
1239 seq_id
= le16_to_cpu(h_cmpl
->sequence_id
);
1240 if (seq_id
== bp
->hwrm_intr_seq_id
)
1241 bp
->hwrm_intr_seq_id
= HWRM_SEQ_ID_INVALID
;
1243 netdev_err(bp
->dev
, "Invalid hwrm seq id %d\n", seq_id
);
1246 case CMPL_BASE_TYPE_HWRM_FWD_REQ
:
1247 vf_id
= le16_to_cpu(fwd_req_cmpl
->source_id
);
1249 if ((vf_id
< bp
->pf
.first_vf_id
) ||
1250 (vf_id
>= bp
->pf
.first_vf_id
+ bp
->pf
.active_vfs
)) {
1251 netdev_err(bp
->dev
, "Msg contains invalid VF id %x\n",
1256 set_bit(vf_id
- bp
->pf
.first_vf_id
, bp
->pf
.vf_event_bmap
);
1257 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT
, &bp
->sp_event
);
1258 schedule_work(&bp
->sp_task
);
1261 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT
:
1262 bnxt_async_event_process(bp
,
1263 (struct hwrm_async_event_cmpl
*)txcmp
);
1272 static irqreturn_t
bnxt_msix(int irq
, void *dev_instance
)
1274 struct bnxt_napi
*bnapi
= dev_instance
;
1275 struct bnxt
*bp
= bnapi
->bp
;
1276 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1277 u32 cons
= RING_CMP(cpr
->cp_raw_cons
);
1279 prefetch(&cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)]);
1280 napi_schedule(&bnapi
->napi
);
1284 static inline int bnxt_has_work(struct bnxt
*bp
, struct bnxt_cp_ring_info
*cpr
)
1286 u32 raw_cons
= cpr
->cp_raw_cons
;
1287 u16 cons
= RING_CMP(raw_cons
);
1288 struct tx_cmp
*txcmp
;
1290 txcmp
= &cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)];
1292 return TX_CMP_VALID(txcmp
, raw_cons
);
1295 static irqreturn_t
bnxt_inta(int irq
, void *dev_instance
)
1297 struct bnxt_napi
*bnapi
= dev_instance
;
1298 struct bnxt
*bp
= bnapi
->bp
;
1299 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1300 u32 cons
= RING_CMP(cpr
->cp_raw_cons
);
1303 prefetch(&cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)]);
1305 if (!bnxt_has_work(bp
, cpr
)) {
1306 int_status
= readl(bp
->bar0
+ BNXT_CAG_REG_LEGACY_INT_STATUS
);
1307 /* return if erroneous interrupt */
1308 if (!(int_status
& (0x10000 << cpr
->cp_ring_struct
.fw_ring_id
)))
1312 /* disable ring IRQ */
1313 BNXT_CP_DB_IRQ_DIS(cpr
->cp_doorbell
);
1315 /* Return here if interrupt is shared and is disabled. */
1316 if (unlikely(atomic_read(&bp
->intr_sem
) != 0))
1319 napi_schedule(&bnapi
->napi
);
1323 static int bnxt_poll_work(struct bnxt
*bp
, struct bnxt_napi
*bnapi
, int budget
)
1325 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1326 u32 raw_cons
= cpr
->cp_raw_cons
;
1330 bool rx_event
= false;
1331 bool agg_event
= false;
1332 struct tx_cmp
*txcmp
;
1337 cons
= RING_CMP(raw_cons
);
1338 txcmp
= &cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)];
1340 if (!TX_CMP_VALID(txcmp
, raw_cons
))
1343 if (TX_CMP_TYPE(txcmp
) == CMP_TYPE_TX_L2_CMP
) {
1345 /* return full budget so NAPI will complete. */
1346 if (unlikely(tx_pkts
> bp
->tx_wake_thresh
))
1348 } else if ((TX_CMP_TYPE(txcmp
) & 0x30) == 0x10) {
1349 rc
= bnxt_rx_pkt(bp
, bnapi
, &raw_cons
, &agg_event
);
1350 if (likely(rc
>= 0))
1352 else if (rc
== -EBUSY
) /* partial completion */
1355 } else if (unlikely((TX_CMP_TYPE(txcmp
) ==
1356 CMPL_BASE_TYPE_HWRM_DONE
) ||
1357 (TX_CMP_TYPE(txcmp
) ==
1358 CMPL_BASE_TYPE_HWRM_FWD_REQ
) ||
1359 (TX_CMP_TYPE(txcmp
) ==
1360 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT
))) {
1361 bnxt_hwrm_handler(bp
, txcmp
);
1363 raw_cons
= NEXT_RAW_CMP(raw_cons
);
1365 if (rx_pkts
== budget
)
1369 cpr
->cp_raw_cons
= raw_cons
;
1370 /* ACK completion ring before freeing tx ring and producing new
1371 * buffers in rx/agg rings to prevent overflowing the completion
1374 BNXT_CP_DB(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
1377 bnxt_tx_int(bp
, bnapi
, tx_pkts
);
1380 struct bnxt_rx_ring_info
*rxr
= &bnapi
->rx_ring
;
1382 writel(DB_KEY_RX
| rxr
->rx_prod
, rxr
->rx_doorbell
);
1383 writel(DB_KEY_RX
| rxr
->rx_prod
, rxr
->rx_doorbell
);
1385 writel(DB_KEY_RX
| rxr
->rx_agg_prod
,
1386 rxr
->rx_agg_doorbell
);
1387 writel(DB_KEY_RX
| rxr
->rx_agg_prod
,
1388 rxr
->rx_agg_doorbell
);
1394 static int bnxt_poll(struct napi_struct
*napi
, int budget
)
1396 struct bnxt_napi
*bnapi
= container_of(napi
, struct bnxt_napi
, napi
);
1397 struct bnxt
*bp
= bnapi
->bp
;
1398 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1401 if (!bnxt_lock_napi(bnapi
))
1405 work_done
+= bnxt_poll_work(bp
, bnapi
, budget
- work_done
);
1407 if (work_done
>= budget
)
1410 if (!bnxt_has_work(bp
, cpr
)) {
1411 napi_complete(napi
);
1412 BNXT_CP_DB_REARM(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
1417 bnxt_unlock_napi(bnapi
);
1421 #ifdef CONFIG_NET_RX_BUSY_POLL
1422 static int bnxt_busy_poll(struct napi_struct
*napi
)
1424 struct bnxt_napi
*bnapi
= container_of(napi
, struct bnxt_napi
, napi
);
1425 struct bnxt
*bp
= bnapi
->bp
;
1426 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1427 int rx_work
, budget
= 4;
1429 if (atomic_read(&bp
->intr_sem
) != 0)
1430 return LL_FLUSH_FAILED
;
1432 if (!bnxt_lock_poll(bnapi
))
1433 return LL_FLUSH_BUSY
;
1435 rx_work
= bnxt_poll_work(bp
, bnapi
, budget
);
1437 BNXT_CP_DB_REARM(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
1439 bnxt_unlock_poll(bnapi
);
1444 static void bnxt_free_tx_skbs(struct bnxt
*bp
)
1447 struct pci_dev
*pdev
= bp
->pdev
;
1452 max_idx
= bp
->tx_nr_pages
* TX_DESC_CNT
;
1453 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
1454 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
1455 struct bnxt_tx_ring_info
*txr
;
1461 txr
= &bnapi
->tx_ring
;
1462 for (j
= 0; j
< max_idx
;) {
1463 struct bnxt_sw_tx_bd
*tx_buf
= &txr
->tx_buf_ring
[j
];
1464 struct sk_buff
*skb
= tx_buf
->skb
;
1474 if (tx_buf
->is_push
) {
1480 dma_unmap_single(&pdev
->dev
,
1481 dma_unmap_addr(tx_buf
, mapping
),
1485 last
= tx_buf
->nr_frags
;
1487 for (k
= 0; k
< last
; k
++, j
= NEXT_TX(j
)) {
1488 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[k
];
1490 tx_buf
= &txr
->tx_buf_ring
[j
];
1493 dma_unmap_addr(tx_buf
, mapping
),
1494 skb_frag_size(frag
), PCI_DMA_TODEVICE
);
1498 netdev_tx_reset_queue(netdev_get_tx_queue(bp
->dev
, i
));
1502 static void bnxt_free_rx_skbs(struct bnxt
*bp
)
1504 int i
, max_idx
, max_agg_idx
;
1505 struct pci_dev
*pdev
= bp
->pdev
;
1510 max_idx
= bp
->rx_nr_pages
* RX_DESC_CNT
;
1511 max_agg_idx
= bp
->rx_agg_nr_pages
* RX_DESC_CNT
;
1512 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
1513 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
1514 struct bnxt_rx_ring_info
*rxr
;
1520 rxr
= &bnapi
->rx_ring
;
1523 for (j
= 0; j
< MAX_TPA
; j
++) {
1524 struct bnxt_tpa_info
*tpa_info
=
1526 u8
*data
= tpa_info
->data
;
1533 dma_unmap_addr(tpa_info
, mapping
),
1534 bp
->rx_buf_use_size
,
1535 PCI_DMA_FROMDEVICE
);
1537 tpa_info
->data
= NULL
;
1543 for (j
= 0; j
< max_idx
; j
++) {
1544 struct bnxt_sw_rx_bd
*rx_buf
= &rxr
->rx_buf_ring
[j
];
1545 u8
*data
= rx_buf
->data
;
1550 dma_unmap_single(&pdev
->dev
,
1551 dma_unmap_addr(rx_buf
, mapping
),
1552 bp
->rx_buf_use_size
,
1553 PCI_DMA_FROMDEVICE
);
1555 rx_buf
->data
= NULL
;
1560 for (j
= 0; j
< max_agg_idx
; j
++) {
1561 struct bnxt_sw_rx_agg_bd
*rx_agg_buf
=
1562 &rxr
->rx_agg_ring
[j
];
1563 struct page
*page
= rx_agg_buf
->page
;
1568 dma_unmap_page(&pdev
->dev
,
1569 dma_unmap_addr(rx_agg_buf
, mapping
),
1570 PAGE_SIZE
, PCI_DMA_FROMDEVICE
);
1572 rx_agg_buf
->page
= NULL
;
1573 __clear_bit(j
, rxr
->rx_agg_bmap
);
1580 static void bnxt_free_skbs(struct bnxt
*bp
)
1582 bnxt_free_tx_skbs(bp
);
1583 bnxt_free_rx_skbs(bp
);
1586 static void bnxt_free_ring(struct bnxt
*bp
, struct bnxt_ring_struct
*ring
)
1588 struct pci_dev
*pdev
= bp
->pdev
;
1591 for (i
= 0; i
< ring
->nr_pages
; i
++) {
1592 if (!ring
->pg_arr
[i
])
1595 dma_free_coherent(&pdev
->dev
, ring
->page_size
,
1596 ring
->pg_arr
[i
], ring
->dma_arr
[i
]);
1598 ring
->pg_arr
[i
] = NULL
;
1601 dma_free_coherent(&pdev
->dev
, ring
->nr_pages
* 8,
1602 ring
->pg_tbl
, ring
->pg_tbl_map
);
1603 ring
->pg_tbl
= NULL
;
1605 if (ring
->vmem_size
&& *ring
->vmem
) {
1611 static int bnxt_alloc_ring(struct bnxt
*bp
, struct bnxt_ring_struct
*ring
)
1614 struct pci_dev
*pdev
= bp
->pdev
;
1616 if (ring
->nr_pages
> 1) {
1617 ring
->pg_tbl
= dma_alloc_coherent(&pdev
->dev
,
1625 for (i
= 0; i
< ring
->nr_pages
; i
++) {
1626 ring
->pg_arr
[i
] = dma_alloc_coherent(&pdev
->dev
,
1630 if (!ring
->pg_arr
[i
])
1633 if (ring
->nr_pages
> 1)
1634 ring
->pg_tbl
[i
] = cpu_to_le64(ring
->dma_arr
[i
]);
1637 if (ring
->vmem_size
) {
1638 *ring
->vmem
= vzalloc(ring
->vmem_size
);
1645 static void bnxt_free_rx_rings(struct bnxt
*bp
)
1652 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
1653 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
1654 struct bnxt_rx_ring_info
*rxr
;
1655 struct bnxt_ring_struct
*ring
;
1660 rxr
= &bnapi
->rx_ring
;
1665 kfree(rxr
->rx_agg_bmap
);
1666 rxr
->rx_agg_bmap
= NULL
;
1668 ring
= &rxr
->rx_ring_struct
;
1669 bnxt_free_ring(bp
, ring
);
1671 ring
= &rxr
->rx_agg_ring_struct
;
1672 bnxt_free_ring(bp
, ring
);
1676 static int bnxt_alloc_rx_rings(struct bnxt
*bp
)
1678 int i
, rc
, agg_rings
= 0, tpa_rings
= 0;
1680 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
)
1683 if (bp
->flags
& BNXT_FLAG_TPA
)
1686 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
1687 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
1688 struct bnxt_rx_ring_info
*rxr
;
1689 struct bnxt_ring_struct
*ring
;
1694 rxr
= &bnapi
->rx_ring
;
1695 ring
= &rxr
->rx_ring_struct
;
1697 rc
= bnxt_alloc_ring(bp
, ring
);
1704 ring
= &rxr
->rx_agg_ring_struct
;
1705 rc
= bnxt_alloc_ring(bp
, ring
);
1709 rxr
->rx_agg_bmap_size
= bp
->rx_agg_ring_mask
+ 1;
1710 mem_size
= rxr
->rx_agg_bmap_size
/ 8;
1711 rxr
->rx_agg_bmap
= kzalloc(mem_size
, GFP_KERNEL
);
1712 if (!rxr
->rx_agg_bmap
)
1716 rxr
->rx_tpa
= kcalloc(MAX_TPA
,
1717 sizeof(struct bnxt_tpa_info
),
1727 static void bnxt_free_tx_rings(struct bnxt
*bp
)
1730 struct pci_dev
*pdev
= bp
->pdev
;
1735 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
1736 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
1737 struct bnxt_tx_ring_info
*txr
;
1738 struct bnxt_ring_struct
*ring
;
1743 txr
= &bnapi
->tx_ring
;
1746 dma_free_coherent(&pdev
->dev
, bp
->tx_push_size
,
1747 txr
->tx_push
, txr
->tx_push_mapping
);
1748 txr
->tx_push
= NULL
;
1751 ring
= &txr
->tx_ring_struct
;
1753 bnxt_free_ring(bp
, ring
);
1757 static int bnxt_alloc_tx_rings(struct bnxt
*bp
)
1760 struct pci_dev
*pdev
= bp
->pdev
;
1762 bp
->tx_push_size
= 0;
1763 if (bp
->tx_push_thresh
) {
1766 push_size
= L1_CACHE_ALIGN(sizeof(struct tx_push_bd
) +
1767 bp
->tx_push_thresh
);
1769 if (push_size
> 128) {
1771 bp
->tx_push_thresh
= 0;
1774 bp
->tx_push_size
= push_size
;
1777 for (i
= 0, j
= 0; i
< bp
->tx_nr_rings
; i
++) {
1778 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
1779 struct bnxt_tx_ring_info
*txr
;
1780 struct bnxt_ring_struct
*ring
;
1785 txr
= &bnapi
->tx_ring
;
1786 ring
= &txr
->tx_ring_struct
;
1788 rc
= bnxt_alloc_ring(bp
, ring
);
1792 if (bp
->tx_push_size
) {
1796 /* One pre-allocated DMA buffer to backup
1799 txr
->tx_push
= dma_alloc_coherent(&pdev
->dev
,
1801 &txr
->tx_push_mapping
,
1807 txbd
= &txr
->tx_push
->txbd1
;
1809 mapping
= txr
->tx_push_mapping
+
1810 sizeof(struct tx_push_bd
);
1811 txbd
->tx_bd_haddr
= cpu_to_le64(mapping
);
1813 memset(txbd
+ 1, 0, sizeof(struct tx_bd_ext
));
1815 ring
->queue_id
= bp
->q_info
[j
].queue_id
;
1816 if (i
% bp
->tx_nr_rings_per_tc
== (bp
->tx_nr_rings_per_tc
- 1))
1822 static void bnxt_free_cp_rings(struct bnxt
*bp
)
1829 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
1830 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
1831 struct bnxt_cp_ring_info
*cpr
;
1832 struct bnxt_ring_struct
*ring
;
1837 cpr
= &bnapi
->cp_ring
;
1838 ring
= &cpr
->cp_ring_struct
;
1840 bnxt_free_ring(bp
, ring
);
1844 static int bnxt_alloc_cp_rings(struct bnxt
*bp
)
1848 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
1849 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
1850 struct bnxt_cp_ring_info
*cpr
;
1851 struct bnxt_ring_struct
*ring
;
1856 cpr
= &bnapi
->cp_ring
;
1857 ring
= &cpr
->cp_ring_struct
;
1859 rc
= bnxt_alloc_ring(bp
, ring
);
1866 static void bnxt_init_ring_struct(struct bnxt
*bp
)
1870 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
1871 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
1872 struct bnxt_cp_ring_info
*cpr
;
1873 struct bnxt_rx_ring_info
*rxr
;
1874 struct bnxt_tx_ring_info
*txr
;
1875 struct bnxt_ring_struct
*ring
;
1880 cpr
= &bnapi
->cp_ring
;
1881 ring
= &cpr
->cp_ring_struct
;
1882 ring
->nr_pages
= bp
->cp_nr_pages
;
1883 ring
->page_size
= HW_CMPD_RING_SIZE
;
1884 ring
->pg_arr
= (void **)cpr
->cp_desc_ring
;
1885 ring
->dma_arr
= cpr
->cp_desc_mapping
;
1886 ring
->vmem_size
= 0;
1888 rxr
= &bnapi
->rx_ring
;
1889 ring
= &rxr
->rx_ring_struct
;
1890 ring
->nr_pages
= bp
->rx_nr_pages
;
1891 ring
->page_size
= HW_RXBD_RING_SIZE
;
1892 ring
->pg_arr
= (void **)rxr
->rx_desc_ring
;
1893 ring
->dma_arr
= rxr
->rx_desc_mapping
;
1894 ring
->vmem_size
= SW_RXBD_RING_SIZE
* bp
->rx_nr_pages
;
1895 ring
->vmem
= (void **)&rxr
->rx_buf_ring
;
1897 ring
= &rxr
->rx_agg_ring_struct
;
1898 ring
->nr_pages
= bp
->rx_agg_nr_pages
;
1899 ring
->page_size
= HW_RXBD_RING_SIZE
;
1900 ring
->pg_arr
= (void **)rxr
->rx_agg_desc_ring
;
1901 ring
->dma_arr
= rxr
->rx_agg_desc_mapping
;
1902 ring
->vmem_size
= SW_RXBD_AGG_RING_SIZE
* bp
->rx_agg_nr_pages
;
1903 ring
->vmem
= (void **)&rxr
->rx_agg_ring
;
1905 txr
= &bnapi
->tx_ring
;
1906 ring
= &txr
->tx_ring_struct
;
1907 ring
->nr_pages
= bp
->tx_nr_pages
;
1908 ring
->page_size
= HW_RXBD_RING_SIZE
;
1909 ring
->pg_arr
= (void **)txr
->tx_desc_ring
;
1910 ring
->dma_arr
= txr
->tx_desc_mapping
;
1911 ring
->vmem_size
= SW_TXBD_RING_SIZE
* bp
->tx_nr_pages
;
1912 ring
->vmem
= (void **)&txr
->tx_buf_ring
;
1916 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct
*ring
, u32 type
)
1920 struct rx_bd
**rx_buf_ring
;
1922 rx_buf_ring
= (struct rx_bd
**)ring
->pg_arr
;
1923 for (i
= 0, prod
= 0; i
< ring
->nr_pages
; i
++) {
1927 rxbd
= rx_buf_ring
[i
];
1931 for (j
= 0; j
< RX_DESC_CNT
; j
++, rxbd
++, prod
++) {
1932 rxbd
->rx_bd_len_flags_type
= cpu_to_le32(type
);
1933 rxbd
->rx_bd_opaque
= prod
;
1938 static int bnxt_init_one_rx_ring(struct bnxt
*bp
, int ring_nr
)
1940 struct net_device
*dev
= bp
->dev
;
1941 struct bnxt_napi
*bnapi
= bp
->bnapi
[ring_nr
];
1942 struct bnxt_rx_ring_info
*rxr
;
1943 struct bnxt_ring_struct
*ring
;
1950 type
= (bp
->rx_buf_use_size
<< RX_BD_LEN_SHIFT
) |
1951 RX_BD_TYPE_RX_PACKET_BD
| RX_BD_FLAGS_EOP
;
1953 if (NET_IP_ALIGN
== 2)
1954 type
|= RX_BD_FLAGS_SOP
;
1956 rxr
= &bnapi
->rx_ring
;
1957 ring
= &rxr
->rx_ring_struct
;
1958 bnxt_init_rxbd_pages(ring
, type
);
1960 prod
= rxr
->rx_prod
;
1961 for (i
= 0; i
< bp
->rx_ring_size
; i
++) {
1962 if (bnxt_alloc_rx_data(bp
, rxr
, prod
, GFP_KERNEL
) != 0) {
1963 netdev_warn(dev
, "init'ed rx ring %d with %d/%d skbs only\n",
1964 ring_nr
, i
, bp
->rx_ring_size
);
1967 prod
= NEXT_RX(prod
);
1969 rxr
->rx_prod
= prod
;
1970 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
1972 if (!(bp
->flags
& BNXT_FLAG_AGG_RINGS
))
1975 ring
= &rxr
->rx_agg_ring_struct
;
1977 type
= ((u32
)PAGE_SIZE
<< RX_BD_LEN_SHIFT
) |
1978 RX_BD_TYPE_RX_AGG_BD
| RX_BD_FLAGS_SOP
;
1980 bnxt_init_rxbd_pages(ring
, type
);
1982 prod
= rxr
->rx_agg_prod
;
1983 for (i
= 0; i
< bp
->rx_agg_ring_size
; i
++) {
1984 if (bnxt_alloc_rx_page(bp
, rxr
, prod
, GFP_KERNEL
) != 0) {
1985 netdev_warn(dev
, "init'ed rx ring %d with %d/%d pages only\n",
1986 ring_nr
, i
, bp
->rx_ring_size
);
1989 prod
= NEXT_RX_AGG(prod
);
1991 rxr
->rx_agg_prod
= prod
;
1992 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
1994 if (bp
->flags
& BNXT_FLAG_TPA
) {
1999 for (i
= 0; i
< MAX_TPA
; i
++) {
2000 data
= __bnxt_alloc_rx_data(bp
, &mapping
,
2005 rxr
->rx_tpa
[i
].data
= data
;
2006 rxr
->rx_tpa
[i
].mapping
= mapping
;
2009 netdev_err(bp
->dev
, "No resource allocated for LRO/GRO\n");
2017 static int bnxt_init_rx_rings(struct bnxt
*bp
)
2021 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
2022 rc
= bnxt_init_one_rx_ring(bp
, i
);
2030 static int bnxt_init_tx_rings(struct bnxt
*bp
)
2034 bp
->tx_wake_thresh
= max_t(int, bp
->tx_ring_size
/ 2,
2037 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
2038 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2039 struct bnxt_tx_ring_info
*txr
= &bnapi
->tx_ring
;
2040 struct bnxt_ring_struct
*ring
= &txr
->tx_ring_struct
;
2042 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
2048 static void bnxt_free_ring_grps(struct bnxt
*bp
)
2050 kfree(bp
->grp_info
);
2051 bp
->grp_info
= NULL
;
2054 static int bnxt_init_ring_grps(struct bnxt
*bp
, bool irq_re_init
)
2059 bp
->grp_info
= kcalloc(bp
->cp_nr_rings
,
2060 sizeof(struct bnxt_ring_grp_info
),
2065 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2067 bp
->grp_info
[i
].fw_stats_ctx
= INVALID_HW_RING_ID
;
2068 bp
->grp_info
[i
].fw_grp_id
= INVALID_HW_RING_ID
;
2069 bp
->grp_info
[i
].rx_fw_ring_id
= INVALID_HW_RING_ID
;
2070 bp
->grp_info
[i
].agg_fw_ring_id
= INVALID_HW_RING_ID
;
2071 bp
->grp_info
[i
].cp_fw_ring_id
= INVALID_HW_RING_ID
;
2076 static void bnxt_free_vnics(struct bnxt
*bp
)
2078 kfree(bp
->vnic_info
);
2079 bp
->vnic_info
= NULL
;
2083 static int bnxt_alloc_vnics(struct bnxt
*bp
)
2087 #ifdef CONFIG_RFS_ACCEL
2088 if (bp
->flags
& BNXT_FLAG_RFS
)
2089 num_vnics
+= bp
->rx_nr_rings
;
2092 bp
->vnic_info
= kcalloc(num_vnics
, sizeof(struct bnxt_vnic_info
),
2097 bp
->nr_vnics
= num_vnics
;
2101 static void bnxt_init_vnics(struct bnxt
*bp
)
2105 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
2106 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[i
];
2108 vnic
->fw_vnic_id
= INVALID_HW_RING_ID
;
2109 vnic
->fw_rss_cos_lb_ctx
= INVALID_HW_RING_ID
;
2110 vnic
->fw_l2_ctx_id
= INVALID_HW_RING_ID
;
2112 if (bp
->vnic_info
[i
].rss_hash_key
) {
2114 prandom_bytes(vnic
->rss_hash_key
,
2117 memcpy(vnic
->rss_hash_key
,
2118 bp
->vnic_info
[0].rss_hash_key
,
2124 static int bnxt_calc_nr_ring_pages(u32 ring_size
, int desc_per_pg
)
2128 pages
= ring_size
/ desc_per_pg
;
2135 while (pages
& (pages
- 1))
2141 static void bnxt_set_tpa_flags(struct bnxt
*bp
)
2143 bp
->flags
&= ~BNXT_FLAG_TPA
;
2144 if (bp
->dev
->features
& NETIF_F_LRO
)
2145 bp
->flags
|= BNXT_FLAG_LRO
;
2146 if ((bp
->dev
->features
& NETIF_F_GRO
) && (bp
->pdev
->revision
> 0))
2147 bp
->flags
|= BNXT_FLAG_GRO
;
2150 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2153 void bnxt_set_ring_params(struct bnxt
*bp
)
2155 u32 ring_size
, rx_size
, rx_space
;
2156 u32 agg_factor
= 0, agg_ring_size
= 0;
2158 /* 8 for CRC and VLAN */
2159 rx_size
= SKB_DATA_ALIGN(bp
->dev
->mtu
+ ETH_HLEN
+ NET_IP_ALIGN
+ 8);
2161 rx_space
= rx_size
+ NET_SKB_PAD
+
2162 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
2164 bp
->rx_copy_thresh
= BNXT_RX_COPY_THRESH
;
2165 ring_size
= bp
->rx_ring_size
;
2166 bp
->rx_agg_ring_size
= 0;
2167 bp
->rx_agg_nr_pages
= 0;
2169 if (bp
->flags
& BNXT_FLAG_TPA
)
2172 bp
->flags
&= ~BNXT_FLAG_JUMBO
;
2173 if (rx_space
> PAGE_SIZE
) {
2176 bp
->flags
|= BNXT_FLAG_JUMBO
;
2177 jumbo_factor
= PAGE_ALIGN(bp
->dev
->mtu
- 40) >> PAGE_SHIFT
;
2178 if (jumbo_factor
> agg_factor
)
2179 agg_factor
= jumbo_factor
;
2181 agg_ring_size
= ring_size
* agg_factor
;
2183 if (agg_ring_size
) {
2184 bp
->rx_agg_nr_pages
= bnxt_calc_nr_ring_pages(agg_ring_size
,
2186 if (bp
->rx_agg_nr_pages
> MAX_RX_AGG_PAGES
) {
2187 u32 tmp
= agg_ring_size
;
2189 bp
->rx_agg_nr_pages
= MAX_RX_AGG_PAGES
;
2190 agg_ring_size
= MAX_RX_AGG_PAGES
* RX_DESC_CNT
- 1;
2191 netdev_warn(bp
->dev
, "rx agg ring size %d reduced to %d.\n",
2192 tmp
, agg_ring_size
);
2194 bp
->rx_agg_ring_size
= agg_ring_size
;
2195 bp
->rx_agg_ring_mask
= (bp
->rx_agg_nr_pages
* RX_DESC_CNT
) - 1;
2196 rx_size
= SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH
+ NET_IP_ALIGN
);
2197 rx_space
= rx_size
+ NET_SKB_PAD
+
2198 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
2201 bp
->rx_buf_use_size
= rx_size
;
2202 bp
->rx_buf_size
= rx_space
;
2204 bp
->rx_nr_pages
= bnxt_calc_nr_ring_pages(ring_size
, RX_DESC_CNT
);
2205 bp
->rx_ring_mask
= (bp
->rx_nr_pages
* RX_DESC_CNT
) - 1;
2207 ring_size
= bp
->tx_ring_size
;
2208 bp
->tx_nr_pages
= bnxt_calc_nr_ring_pages(ring_size
, TX_DESC_CNT
);
2209 bp
->tx_ring_mask
= (bp
->tx_nr_pages
* TX_DESC_CNT
) - 1;
2211 ring_size
= bp
->rx_ring_size
* (2 + agg_factor
) + bp
->tx_ring_size
;
2212 bp
->cp_ring_size
= ring_size
;
2214 bp
->cp_nr_pages
= bnxt_calc_nr_ring_pages(ring_size
, CP_DESC_CNT
);
2215 if (bp
->cp_nr_pages
> MAX_CP_PAGES
) {
2216 bp
->cp_nr_pages
= MAX_CP_PAGES
;
2217 bp
->cp_ring_size
= MAX_CP_PAGES
* CP_DESC_CNT
- 1;
2218 netdev_warn(bp
->dev
, "completion ring size %d reduced to %d.\n",
2219 ring_size
, bp
->cp_ring_size
);
2221 bp
->cp_bit
= bp
->cp_nr_pages
* CP_DESC_CNT
;
2222 bp
->cp_ring_mask
= bp
->cp_bit
- 1;
2225 static void bnxt_free_vnic_attributes(struct bnxt
*bp
)
2228 struct bnxt_vnic_info
*vnic
;
2229 struct pci_dev
*pdev
= bp
->pdev
;
2234 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
2235 vnic
= &bp
->vnic_info
[i
];
2237 kfree(vnic
->fw_grp_ids
);
2238 vnic
->fw_grp_ids
= NULL
;
2240 kfree(vnic
->uc_list
);
2241 vnic
->uc_list
= NULL
;
2243 if (vnic
->mc_list
) {
2244 dma_free_coherent(&pdev
->dev
, vnic
->mc_list_size
,
2245 vnic
->mc_list
, vnic
->mc_list_mapping
);
2246 vnic
->mc_list
= NULL
;
2249 if (vnic
->rss_table
) {
2250 dma_free_coherent(&pdev
->dev
, PAGE_SIZE
,
2252 vnic
->rss_table_dma_addr
);
2253 vnic
->rss_table
= NULL
;
2256 vnic
->rss_hash_key
= NULL
;
2261 static int bnxt_alloc_vnic_attributes(struct bnxt
*bp
)
2263 int i
, rc
= 0, size
;
2264 struct bnxt_vnic_info
*vnic
;
2265 struct pci_dev
*pdev
= bp
->pdev
;
2268 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
2269 vnic
= &bp
->vnic_info
[i
];
2271 if (vnic
->flags
& BNXT_VNIC_UCAST_FLAG
) {
2272 int mem_size
= (BNXT_MAX_UC_ADDRS
- 1) * ETH_ALEN
;
2275 vnic
->uc_list
= kmalloc(mem_size
, GFP_KERNEL
);
2276 if (!vnic
->uc_list
) {
2283 if (vnic
->flags
& BNXT_VNIC_MCAST_FLAG
) {
2284 vnic
->mc_list_size
= BNXT_MAX_MC_ADDRS
* ETH_ALEN
;
2286 dma_alloc_coherent(&pdev
->dev
,
2288 &vnic
->mc_list_mapping
,
2290 if (!vnic
->mc_list
) {
2296 if (vnic
->flags
& BNXT_VNIC_RSS_FLAG
)
2297 max_rings
= bp
->rx_nr_rings
;
2301 vnic
->fw_grp_ids
= kcalloc(max_rings
, sizeof(u16
), GFP_KERNEL
);
2302 if (!vnic
->fw_grp_ids
) {
2307 /* Allocate rss table and hash key */
2308 vnic
->rss_table
= dma_alloc_coherent(&pdev
->dev
, PAGE_SIZE
,
2309 &vnic
->rss_table_dma_addr
,
2311 if (!vnic
->rss_table
) {
2316 size
= L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE
* sizeof(u16
));
2318 vnic
->rss_hash_key
= ((void *)vnic
->rss_table
) + size
;
2319 vnic
->rss_hash_key_dma_addr
= vnic
->rss_table_dma_addr
+ size
;
2327 static void bnxt_free_hwrm_resources(struct bnxt
*bp
)
2329 struct pci_dev
*pdev
= bp
->pdev
;
2331 dma_free_coherent(&pdev
->dev
, PAGE_SIZE
, bp
->hwrm_cmd_resp_addr
,
2332 bp
->hwrm_cmd_resp_dma_addr
);
2334 bp
->hwrm_cmd_resp_addr
= NULL
;
2335 if (bp
->hwrm_dbg_resp_addr
) {
2336 dma_free_coherent(&pdev
->dev
, HWRM_DBG_REG_BUF_SIZE
,
2337 bp
->hwrm_dbg_resp_addr
,
2338 bp
->hwrm_dbg_resp_dma_addr
);
2340 bp
->hwrm_dbg_resp_addr
= NULL
;
2344 static int bnxt_alloc_hwrm_resources(struct bnxt
*bp
)
2346 struct pci_dev
*pdev
= bp
->pdev
;
2348 bp
->hwrm_cmd_resp_addr
= dma_alloc_coherent(&pdev
->dev
, PAGE_SIZE
,
2349 &bp
->hwrm_cmd_resp_dma_addr
,
2351 if (!bp
->hwrm_cmd_resp_addr
)
2353 bp
->hwrm_dbg_resp_addr
= dma_alloc_coherent(&pdev
->dev
,
2354 HWRM_DBG_REG_BUF_SIZE
,
2355 &bp
->hwrm_dbg_resp_dma_addr
,
2357 if (!bp
->hwrm_dbg_resp_addr
)
2358 netdev_warn(bp
->dev
, "fail to alloc debug register dma mem\n");
2363 static void bnxt_free_stats(struct bnxt
*bp
)
2366 struct pci_dev
*pdev
= bp
->pdev
;
2371 size
= sizeof(struct ctx_hw_stats
);
2373 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2374 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2375 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
2377 if (cpr
->hw_stats
) {
2378 dma_free_coherent(&pdev
->dev
, size
, cpr
->hw_stats
,
2380 cpr
->hw_stats
= NULL
;
2385 static int bnxt_alloc_stats(struct bnxt
*bp
)
2388 struct pci_dev
*pdev
= bp
->pdev
;
2390 size
= sizeof(struct ctx_hw_stats
);
2392 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2393 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2394 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
2396 cpr
->hw_stats
= dma_alloc_coherent(&pdev
->dev
, size
,
2402 cpr
->hw_stats_ctx_id
= INVALID_STATS_CTX_ID
;
2407 static void bnxt_clear_ring_indices(struct bnxt
*bp
)
2414 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2415 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2416 struct bnxt_cp_ring_info
*cpr
;
2417 struct bnxt_rx_ring_info
*rxr
;
2418 struct bnxt_tx_ring_info
*txr
;
2423 cpr
= &bnapi
->cp_ring
;
2424 cpr
->cp_raw_cons
= 0;
2426 txr
= &bnapi
->tx_ring
;
2430 rxr
= &bnapi
->rx_ring
;
2432 rxr
->rx_agg_prod
= 0;
2433 rxr
->rx_sw_agg_prod
= 0;
2437 static void bnxt_free_ntp_fltrs(struct bnxt
*bp
, bool irq_reinit
)
2439 #ifdef CONFIG_RFS_ACCEL
2442 /* Under rtnl_lock and all our NAPIs have been disabled. It's
2443 * safe to delete the hash table.
2445 for (i
= 0; i
< BNXT_NTP_FLTR_HASH_SIZE
; i
++) {
2446 struct hlist_head
*head
;
2447 struct hlist_node
*tmp
;
2448 struct bnxt_ntuple_filter
*fltr
;
2450 head
= &bp
->ntp_fltr_hash_tbl
[i
];
2451 hlist_for_each_entry_safe(fltr
, tmp
, head
, hash
) {
2452 hlist_del(&fltr
->hash
);
2457 kfree(bp
->ntp_fltr_bmap
);
2458 bp
->ntp_fltr_bmap
= NULL
;
2460 bp
->ntp_fltr_count
= 0;
2464 static int bnxt_alloc_ntp_fltrs(struct bnxt
*bp
)
2466 #ifdef CONFIG_RFS_ACCEL
2469 if (!(bp
->flags
& BNXT_FLAG_RFS
))
2472 for (i
= 0; i
< BNXT_NTP_FLTR_HASH_SIZE
; i
++)
2473 INIT_HLIST_HEAD(&bp
->ntp_fltr_hash_tbl
[i
]);
2475 bp
->ntp_fltr_count
= 0;
2476 bp
->ntp_fltr_bmap
= kzalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR
),
2479 if (!bp
->ntp_fltr_bmap
)
2488 static void bnxt_free_mem(struct bnxt
*bp
, bool irq_re_init
)
2490 bnxt_free_vnic_attributes(bp
);
2491 bnxt_free_tx_rings(bp
);
2492 bnxt_free_rx_rings(bp
);
2493 bnxt_free_cp_rings(bp
);
2494 bnxt_free_ntp_fltrs(bp
, irq_re_init
);
2496 bnxt_free_stats(bp
);
2497 bnxt_free_ring_grps(bp
);
2498 bnxt_free_vnics(bp
);
2502 bnxt_clear_ring_indices(bp
);
2506 static int bnxt_alloc_mem(struct bnxt
*bp
, bool irq_re_init
)
2508 int i
, rc
, size
, arr_size
;
2512 /* Allocate bnapi mem pointer array and mem block for
2515 arr_size
= L1_CACHE_ALIGN(sizeof(struct bnxt_napi
*) *
2517 size
= L1_CACHE_ALIGN(sizeof(struct bnxt_napi
));
2518 bnapi
= kzalloc(arr_size
+ size
* bp
->cp_nr_rings
, GFP_KERNEL
);
2524 for (i
= 0; i
< bp
->cp_nr_rings
; i
++, bnapi
+= size
) {
2525 bp
->bnapi
[i
] = bnapi
;
2526 bp
->bnapi
[i
]->index
= i
;
2527 bp
->bnapi
[i
]->bp
= bp
;
2530 rc
= bnxt_alloc_stats(bp
);
2534 rc
= bnxt_alloc_ntp_fltrs(bp
);
2538 rc
= bnxt_alloc_vnics(bp
);
2543 bnxt_init_ring_struct(bp
);
2545 rc
= bnxt_alloc_rx_rings(bp
);
2549 rc
= bnxt_alloc_tx_rings(bp
);
2553 rc
= bnxt_alloc_cp_rings(bp
);
2557 bp
->vnic_info
[0].flags
|= BNXT_VNIC_RSS_FLAG
| BNXT_VNIC_MCAST_FLAG
|
2558 BNXT_VNIC_UCAST_FLAG
;
2559 rc
= bnxt_alloc_vnic_attributes(bp
);
2565 bnxt_free_mem(bp
, true);
2569 void bnxt_hwrm_cmd_hdr_init(struct bnxt
*bp
, void *request
, u16 req_type
,
2570 u16 cmpl_ring
, u16 target_id
)
2572 struct hwrm_cmd_req_hdr
*req
= request
;
2574 req
->cmpl_ring_req_type
=
2575 cpu_to_le32(req_type
| (cmpl_ring
<< HWRM_CMPL_RING_SFT
));
2576 req
->target_id_seq_id
= cpu_to_le32(target_id
<< HWRM_TARGET_FID_SFT
);
2577 req
->resp_addr
= cpu_to_le64(bp
->hwrm_cmd_resp_dma_addr
);
2580 int _hwrm_send_message(struct bnxt
*bp
, void *msg
, u32 msg_len
, int timeout
)
2582 int i
, intr_process
, rc
;
2583 struct hwrm_cmd_req_hdr
*req
= msg
;
2585 __le32
*resp_len
, *valid
;
2586 u16 cp_ring_id
, len
= 0;
2587 struct hwrm_err_output
*resp
= bp
->hwrm_cmd_resp_addr
;
2589 req
->target_id_seq_id
|= cpu_to_le32(bp
->hwrm_cmd_seq
++);
2590 memset(resp
, 0, PAGE_SIZE
);
2591 cp_ring_id
= (le32_to_cpu(req
->cmpl_ring_req_type
) &
2592 HWRM_CMPL_RING_MASK
) >>
2594 intr_process
= (cp_ring_id
== INVALID_HW_RING_ID
) ? 0 : 1;
2596 /* Write request msg to hwrm channel */
2597 __iowrite32_copy(bp
->bar0
, data
, msg_len
/ 4);
2599 /* currently supports only one outstanding message */
2601 bp
->hwrm_intr_seq_id
= le32_to_cpu(req
->target_id_seq_id
) &
2604 /* Ring channel doorbell */
2605 writel(1, bp
->bar0
+ 0x100);
2609 /* Wait until hwrm response cmpl interrupt is processed */
2610 while (bp
->hwrm_intr_seq_id
!= HWRM_SEQ_ID_INVALID
&&
2612 usleep_range(600, 800);
2615 if (bp
->hwrm_intr_seq_id
!= HWRM_SEQ_ID_INVALID
) {
2616 netdev_err(bp
->dev
, "Resp cmpl intr err msg: 0x%x\n",
2617 req
->cmpl_ring_req_type
);
2621 /* Check if response len is updated */
2622 resp_len
= bp
->hwrm_cmd_resp_addr
+ HWRM_RESP_LEN_OFFSET
;
2623 for (i
= 0; i
< timeout
; i
++) {
2624 len
= (le32_to_cpu(*resp_len
) & HWRM_RESP_LEN_MASK
) >>
2628 usleep_range(600, 800);
2632 netdev_err(bp
->dev
, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
2633 timeout
, req
->cmpl_ring_req_type
,
2634 req
->target_id_seq_id
, *resp_len
);
2638 /* Last word of resp contains valid bit */
2639 valid
= bp
->hwrm_cmd_resp_addr
+ len
- 4;
2640 for (i
= 0; i
< timeout
; i
++) {
2641 if (le32_to_cpu(*valid
) & HWRM_RESP_VALID_MASK
)
2643 usleep_range(600, 800);
2647 netdev_err(bp
->dev
, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
2648 timeout
, req
->cmpl_ring_req_type
,
2649 req
->target_id_seq_id
, len
, *valid
);
2654 rc
= le16_to_cpu(resp
->error_code
);
2656 netdev_err(bp
->dev
, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
2657 le16_to_cpu(resp
->req_type
),
2658 le16_to_cpu(resp
->seq_id
), rc
);
2664 int hwrm_send_message(struct bnxt
*bp
, void *msg
, u32 msg_len
, int timeout
)
2668 mutex_lock(&bp
->hwrm_cmd_lock
);
2669 rc
= _hwrm_send_message(bp
, msg
, msg_len
, timeout
);
2670 mutex_unlock(&bp
->hwrm_cmd_lock
);
2674 static int bnxt_hwrm_func_drv_rgtr(struct bnxt
*bp
)
2676 struct hwrm_func_drv_rgtr_input req
= {0};
2679 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_DRV_RGTR
, -1, -1);
2682 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE
|
2683 FUNC_DRV_RGTR_REQ_ENABLES_VER
|
2684 FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD
);
2686 /* TODO: current async event fwd bits are not defined and the firmware
2687 * only checks if it is non-zero to enable async event forwarding
2689 req
.async_event_fwd
[0] |= cpu_to_le32(1);
2690 req
.os_type
= cpu_to_le16(1);
2691 req
.ver_maj
= DRV_VER_MAJ
;
2692 req
.ver_min
= DRV_VER_MIN
;
2693 req
.ver_upd
= DRV_VER_UPD
;
2696 unsigned long vf_req_snif_bmap
[4];
2697 u32
*data
= (u32
*)vf_req_snif_bmap
;
2699 memset(vf_req_snif_bmap
, 0, 32);
2700 for (i
= 0; i
< ARRAY_SIZE(bnxt_vf_req_snif
); i
++)
2701 __set_bit(bnxt_vf_req_snif
[i
], vf_req_snif_bmap
);
2703 for (i
= 0; i
< 8; i
++) {
2704 req
.vf_req_fwd
[i
] = cpu_to_le32(*data
);
2708 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD
);
2711 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2714 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt
*bp
, u8 tunnel_type
)
2717 struct hwrm_tunnel_dst_port_free_input req
= {0};
2719 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_TUNNEL_DST_PORT_FREE
, -1, -1);
2720 req
.tunnel_type
= tunnel_type
;
2722 switch (tunnel_type
) {
2723 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
:
2724 req
.tunnel_dst_port_id
= bp
->vxlan_fw_dst_port_id
;
2726 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
:
2727 req
.tunnel_dst_port_id
= bp
->nge_fw_dst_port_id
;
2733 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2735 netdev_err(bp
->dev
, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
2740 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt
*bp
, __be16 port
,
2744 struct hwrm_tunnel_dst_port_alloc_input req
= {0};
2745 struct hwrm_tunnel_dst_port_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
2747 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_TUNNEL_DST_PORT_ALLOC
, -1, -1);
2749 req
.tunnel_type
= tunnel_type
;
2750 req
.tunnel_dst_port_val
= port
;
2752 mutex_lock(&bp
->hwrm_cmd_lock
);
2753 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2755 netdev_err(bp
->dev
, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
2760 if (tunnel_type
& TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN
)
2761 bp
->vxlan_fw_dst_port_id
= resp
->tunnel_dst_port_id
;
2763 else if (tunnel_type
& TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE
)
2764 bp
->nge_fw_dst_port_id
= resp
->tunnel_dst_port_id
;
2766 mutex_unlock(&bp
->hwrm_cmd_lock
);
2770 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt
*bp
, u16 vnic_id
)
2772 struct hwrm_cfa_l2_set_rx_mask_input req
= {0};
2773 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
2775 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_L2_SET_RX_MASK
, -1, -1);
2776 req
.dflt_vnic_id
= cpu_to_le32(vnic
->fw_vnic_id
);
2778 req
.num_mc_entries
= cpu_to_le32(vnic
->mc_list_count
);
2779 req
.mc_tbl_addr
= cpu_to_le64(vnic
->mc_list_mapping
);
2780 req
.mask
= cpu_to_le32(vnic
->rx_mask
);
2781 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2784 #ifdef CONFIG_RFS_ACCEL
2785 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt
*bp
,
2786 struct bnxt_ntuple_filter
*fltr
)
2788 struct hwrm_cfa_ntuple_filter_free_input req
= {0};
2790 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_NTUPLE_FILTER_FREE
, -1, -1);
2791 req
.ntuple_filter_id
= fltr
->filter_id
;
2792 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2795 #define BNXT_NTP_FLTR_FLAGS \
2796 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
2797 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
2798 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
2799 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
2800 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
2801 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
2802 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
2803 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
2804 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
2805 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
2806 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
2807 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
2808 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
2809 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID)
2811 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt
*bp
,
2812 struct bnxt_ntuple_filter
*fltr
)
2815 struct hwrm_cfa_ntuple_filter_alloc_input req
= {0};
2816 struct hwrm_cfa_ntuple_filter_alloc_output
*resp
=
2817 bp
->hwrm_cmd_resp_addr
;
2818 struct flow_keys
*keys
= &fltr
->fkeys
;
2819 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[fltr
->rxq
+ 1];
2821 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_NTUPLE_FILTER_ALLOC
, -1, -1);
2822 req
.l2_filter_id
= bp
->vnic_info
[0].fw_l2_filter_id
[0];
2824 req
.enables
= cpu_to_le32(BNXT_NTP_FLTR_FLAGS
);
2826 req
.ethertype
= htons(ETH_P_IP
);
2827 memcpy(req
.src_macaddr
, fltr
->src_mac_addr
, ETH_ALEN
);
2828 req
.ipaddr_type
= 4;
2829 req
.ip_protocol
= keys
->basic
.ip_proto
;
2831 req
.src_ipaddr
[0] = keys
->addrs
.v4addrs
.src
;
2832 req
.src_ipaddr_mask
[0] = cpu_to_be32(0xffffffff);
2833 req
.dst_ipaddr
[0] = keys
->addrs
.v4addrs
.dst
;
2834 req
.dst_ipaddr_mask
[0] = cpu_to_be32(0xffffffff);
2836 req
.src_port
= keys
->ports
.src
;
2837 req
.src_port_mask
= cpu_to_be16(0xffff);
2838 req
.dst_port
= keys
->ports
.dst
;
2839 req
.dst_port_mask
= cpu_to_be16(0xffff);
2841 req
.dst_vnic_id
= cpu_to_le16(vnic
->fw_vnic_id
);
2842 mutex_lock(&bp
->hwrm_cmd_lock
);
2843 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2845 fltr
->filter_id
= resp
->ntuple_filter_id
;
2846 mutex_unlock(&bp
->hwrm_cmd_lock
);
2851 static int bnxt_hwrm_set_vnic_filter(struct bnxt
*bp
, u16 vnic_id
, u16 idx
,
2855 struct hwrm_cfa_l2_filter_alloc_input req
= {0};
2856 struct hwrm_cfa_l2_filter_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
2858 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_L2_FILTER_ALLOC
, -1, -1);
2859 req
.flags
= cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX
|
2860 CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST
);
2861 req
.dst_vnic_id
= cpu_to_le16(bp
->vnic_info
[vnic_id
].fw_vnic_id
);
2863 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR
|
2864 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID
|
2865 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK
);
2866 memcpy(req
.l2_addr
, mac_addr
, ETH_ALEN
);
2867 req
.l2_addr_mask
[0] = 0xff;
2868 req
.l2_addr_mask
[1] = 0xff;
2869 req
.l2_addr_mask
[2] = 0xff;
2870 req
.l2_addr_mask
[3] = 0xff;
2871 req
.l2_addr_mask
[4] = 0xff;
2872 req
.l2_addr_mask
[5] = 0xff;
2874 mutex_lock(&bp
->hwrm_cmd_lock
);
2875 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2877 bp
->vnic_info
[vnic_id
].fw_l2_filter_id
[idx
] =
2879 mutex_unlock(&bp
->hwrm_cmd_lock
);
2883 static int bnxt_hwrm_clear_vnic_filter(struct bnxt
*bp
)
2885 u16 i
, j
, num_of_vnics
= 1; /* only vnic 0 supported */
2888 /* Any associated ntuple filters will also be cleared by firmware. */
2889 mutex_lock(&bp
->hwrm_cmd_lock
);
2890 for (i
= 0; i
< num_of_vnics
; i
++) {
2891 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[i
];
2893 for (j
= 0; j
< vnic
->uc_filter_count
; j
++) {
2894 struct hwrm_cfa_l2_filter_free_input req
= {0};
2896 bnxt_hwrm_cmd_hdr_init(bp
, &req
,
2897 HWRM_CFA_L2_FILTER_FREE
, -1, -1);
2899 req
.l2_filter_id
= vnic
->fw_l2_filter_id
[j
];
2901 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
2904 vnic
->uc_filter_count
= 0;
2906 mutex_unlock(&bp
->hwrm_cmd_lock
);
2911 static int bnxt_hwrm_vnic_set_tpa(struct bnxt
*bp
, u16 vnic_id
, u32 tpa_flags
)
2913 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
2914 struct hwrm_vnic_tpa_cfg_input req
= {0};
2916 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_TPA_CFG
, -1, -1);
2919 u16 mss
= bp
->dev
->mtu
- 40;
2920 u32 nsegs
, n
, segs
= 0, flags
;
2922 flags
= VNIC_TPA_CFG_REQ_FLAGS_TPA
|
2923 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA
|
2924 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE
|
2925 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN
|
2926 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ
;
2927 if (tpa_flags
& BNXT_FLAG_GRO
)
2928 flags
|= VNIC_TPA_CFG_REQ_FLAGS_GRO
;
2930 req
.flags
= cpu_to_le32(flags
);
2933 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS
|
2934 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS
);
2936 /* Number of segs are log2 units, and first packet is not
2937 * included as part of this units.
2939 if (mss
<= PAGE_SIZE
) {
2940 n
= PAGE_SIZE
/ mss
;
2941 nsegs
= (MAX_SKB_FRAGS
- 1) * n
;
2943 n
= mss
/ PAGE_SIZE
;
2944 if (mss
& (PAGE_SIZE
- 1))
2946 nsegs
= (MAX_SKB_FRAGS
- n
) / n
;
2949 segs
= ilog2(nsegs
);
2950 req
.max_agg_segs
= cpu_to_le16(segs
);
2951 req
.max_aggs
= cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX
);
2953 req
.vnic_id
= cpu_to_le16(vnic
->fw_vnic_id
);
2955 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2958 static int bnxt_hwrm_vnic_set_rss(struct bnxt
*bp
, u16 vnic_id
, bool set_rss
)
2960 u32 i
, j
, max_rings
;
2961 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
2962 struct hwrm_vnic_rss_cfg_input req
= {0};
2964 if (vnic
->fw_rss_cos_lb_ctx
== INVALID_HW_RING_ID
)
2967 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_RSS_CFG
, -1, -1);
2969 vnic
->hash_type
= BNXT_RSS_HASH_TYPE_FLAG_IPV4
|
2970 BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV4
|
2971 BNXT_RSS_HASH_TYPE_FLAG_IPV6
|
2972 BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV6
;
2974 req
.hash_type
= cpu_to_le32(vnic
->hash_type
);
2976 if (vnic
->flags
& BNXT_VNIC_RSS_FLAG
)
2977 max_rings
= bp
->rx_nr_rings
;
2981 /* Fill the RSS indirection table with ring group ids */
2982 for (i
= 0, j
= 0; i
< HW_HASH_INDEX_SIZE
; i
++, j
++) {
2985 vnic
->rss_table
[i
] = cpu_to_le16(vnic
->fw_grp_ids
[j
]);
2988 req
.ring_grp_tbl_addr
= cpu_to_le64(vnic
->rss_table_dma_addr
);
2989 req
.hash_key_tbl_addr
=
2990 cpu_to_le64(vnic
->rss_hash_key_dma_addr
);
2992 req
.rss_ctx_idx
= cpu_to_le16(vnic
->fw_rss_cos_lb_ctx
);
2993 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2996 static int bnxt_hwrm_vnic_set_hds(struct bnxt
*bp
, u16 vnic_id
)
2998 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
2999 struct hwrm_vnic_plcmodes_cfg_input req
= {0};
3001 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_PLCMODES_CFG
, -1, -1);
3002 req
.flags
= cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT
|
3003 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4
|
3004 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6
);
3006 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID
|
3007 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID
);
3008 /* thresholds not implemented in firmware yet */
3009 req
.jumbo_thresh
= cpu_to_le16(bp
->rx_copy_thresh
);
3010 req
.hds_threshold
= cpu_to_le16(bp
->rx_copy_thresh
);
3011 req
.vnic_id
= cpu_to_le32(vnic
->fw_vnic_id
);
3012 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3015 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt
*bp
, u16 vnic_id
)
3017 struct hwrm_vnic_rss_cos_lb_ctx_free_input req
= {0};
3019 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_RSS_COS_LB_CTX_FREE
, -1, -1);
3020 req
.rss_cos_lb_ctx_id
=
3021 cpu_to_le16(bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
);
3023 hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3024 bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
= INVALID_HW_RING_ID
;
3027 static void bnxt_hwrm_vnic_ctx_free(struct bnxt
*bp
)
3031 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
3032 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[i
];
3034 if (vnic
->fw_rss_cos_lb_ctx
!= INVALID_HW_RING_ID
)
3035 bnxt_hwrm_vnic_ctx_free_one(bp
, i
);
3037 bp
->rsscos_nr_ctxs
= 0;
3040 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt
*bp
, u16 vnic_id
)
3043 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req
= {0};
3044 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output
*resp
=
3045 bp
->hwrm_cmd_resp_addr
;
3047 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC
, -1,
3050 mutex_lock(&bp
->hwrm_cmd_lock
);
3051 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3053 bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
=
3054 le16_to_cpu(resp
->rss_cos_lb_ctx_id
);
3055 mutex_unlock(&bp
->hwrm_cmd_lock
);
3060 static int bnxt_hwrm_vnic_cfg(struct bnxt
*bp
, u16 vnic_id
)
3063 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
3064 struct hwrm_vnic_cfg_input req
= {0};
3066 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_CFG
, -1, -1);
3067 /* Only RSS support for now TBD: COS & LB */
3068 req
.enables
= cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP
|
3069 VNIC_CFG_REQ_ENABLES_RSS_RULE
);
3070 req
.rss_rule
= cpu_to_le16(vnic
->fw_rss_cos_lb_ctx
);
3071 req
.cos_rule
= cpu_to_le16(0xffff);
3072 if (vnic
->flags
& BNXT_VNIC_RSS_FLAG
)
3074 else if (vnic
->flags
& BNXT_VNIC_RFS_FLAG
)
3075 grp_idx
= vnic_id
- 1;
3077 req
.vnic_id
= cpu_to_le16(vnic
->fw_vnic_id
);
3078 req
.dflt_ring_grp
= cpu_to_le16(bp
->grp_info
[grp_idx
].fw_grp_id
);
3080 req
.lb_rule
= cpu_to_le16(0xffff);
3081 req
.mru
= cpu_to_le16(bp
->dev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+
3084 if (bp
->flags
& BNXT_FLAG_STRIP_VLAN
)
3085 req
.flags
|= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE
);
3087 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3090 static int bnxt_hwrm_vnic_free_one(struct bnxt
*bp
, u16 vnic_id
)
3094 if (bp
->vnic_info
[vnic_id
].fw_vnic_id
!= INVALID_HW_RING_ID
) {
3095 struct hwrm_vnic_free_input req
= {0};
3097 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_FREE
, -1, -1);
3099 cpu_to_le32(bp
->vnic_info
[vnic_id
].fw_vnic_id
);
3101 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3104 bp
->vnic_info
[vnic_id
].fw_vnic_id
= INVALID_HW_RING_ID
;
3109 static void bnxt_hwrm_vnic_free(struct bnxt
*bp
)
3113 for (i
= 0; i
< bp
->nr_vnics
; i
++)
3114 bnxt_hwrm_vnic_free_one(bp
, i
);
3117 static int bnxt_hwrm_vnic_alloc(struct bnxt
*bp
, u16 vnic_id
, u16 start_grp_id
,
3121 struct hwrm_vnic_alloc_input req
= {0};
3122 struct hwrm_vnic_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3124 /* map ring groups to this vnic */
3125 for (i
= start_grp_id
, j
= 0; i
< end_grp_id
; i
++, j
++) {
3126 if (bp
->grp_info
[i
].fw_grp_id
== INVALID_HW_RING_ID
) {
3127 netdev_err(bp
->dev
, "Not enough ring groups avail:%x req:%x\n",
3128 j
, (end_grp_id
- start_grp_id
));
3131 bp
->vnic_info
[vnic_id
].fw_grp_ids
[j
] =
3132 bp
->grp_info
[i
].fw_grp_id
;
3135 bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
= INVALID_HW_RING_ID
;
3137 req
.flags
= cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT
);
3139 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_ALLOC
, -1, -1);
3141 mutex_lock(&bp
->hwrm_cmd_lock
);
3142 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3144 bp
->vnic_info
[vnic_id
].fw_vnic_id
= le32_to_cpu(resp
->vnic_id
);
3145 mutex_unlock(&bp
->hwrm_cmd_lock
);
3149 static int bnxt_hwrm_ring_grp_alloc(struct bnxt
*bp
)
3154 mutex_lock(&bp
->hwrm_cmd_lock
);
3155 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3156 struct hwrm_ring_grp_alloc_input req
= {0};
3157 struct hwrm_ring_grp_alloc_output
*resp
=
3158 bp
->hwrm_cmd_resp_addr
;
3160 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_GRP_ALLOC
, -1, -1);
3162 req
.cr
= cpu_to_le16(bp
->grp_info
[i
].cp_fw_ring_id
);
3163 req
.rr
= cpu_to_le16(bp
->grp_info
[i
].rx_fw_ring_id
);
3164 req
.ar
= cpu_to_le16(bp
->grp_info
[i
].agg_fw_ring_id
);
3165 req
.sc
= cpu_to_le16(bp
->grp_info
[i
].fw_stats_ctx
);
3167 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3172 bp
->grp_info
[i
].fw_grp_id
= le32_to_cpu(resp
->ring_group_id
);
3174 mutex_unlock(&bp
->hwrm_cmd_lock
);
3178 static int bnxt_hwrm_ring_grp_free(struct bnxt
*bp
)
3182 struct hwrm_ring_grp_free_input req
= {0};
3187 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_GRP_FREE
, -1, -1);
3189 mutex_lock(&bp
->hwrm_cmd_lock
);
3190 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3191 if (bp
->grp_info
[i
].fw_grp_id
== INVALID_HW_RING_ID
)
3194 cpu_to_le32(bp
->grp_info
[i
].fw_grp_id
);
3196 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3200 bp
->grp_info
[i
].fw_grp_id
= INVALID_HW_RING_ID
;
3202 mutex_unlock(&bp
->hwrm_cmd_lock
);
3206 static int hwrm_ring_alloc_send_msg(struct bnxt
*bp
,
3207 struct bnxt_ring_struct
*ring
,
3208 u32 ring_type
, u32 map_index
,
3211 int rc
= 0, err
= 0;
3212 struct hwrm_ring_alloc_input req
= {0};
3213 struct hwrm_ring_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3216 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_ALLOC
, -1, -1);
3219 if (ring
->nr_pages
> 1) {
3220 req
.page_tbl_addr
= cpu_to_le64(ring
->pg_tbl_map
);
3221 /* Page size is in log2 units */
3222 req
.page_size
= BNXT_PAGE_SHIFT
;
3223 req
.page_tbl_depth
= 1;
3225 req
.page_tbl_addr
= cpu_to_le64(ring
->dma_arr
[0]);
3228 /* Association of ring index with doorbell index and MSIX number */
3229 req
.logical_id
= cpu_to_le16(map_index
);
3231 switch (ring_type
) {
3232 case HWRM_RING_ALLOC_TX
:
3233 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_TX
;
3234 /* Association of transmit ring with completion ring */
3236 cpu_to_le16(bp
->grp_info
[map_index
].cp_fw_ring_id
);
3237 req
.length
= cpu_to_le32(bp
->tx_ring_mask
+ 1);
3238 req
.stat_ctx_id
= cpu_to_le32(stats_ctx_id
);
3239 req
.queue_id
= cpu_to_le16(ring
->queue_id
);
3241 case HWRM_RING_ALLOC_RX
:
3242 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_RX
;
3243 req
.length
= cpu_to_le32(bp
->rx_ring_mask
+ 1);
3245 case HWRM_RING_ALLOC_AGG
:
3246 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_RX
;
3247 req
.length
= cpu_to_le32(bp
->rx_agg_ring_mask
+ 1);
3249 case HWRM_RING_ALLOC_CMPL
:
3250 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_CMPL
;
3251 req
.length
= cpu_to_le32(bp
->cp_ring_mask
+ 1);
3252 if (bp
->flags
& BNXT_FLAG_USING_MSIX
)
3253 req
.int_mode
= RING_ALLOC_REQ_INT_MODE_MSIX
;
3256 netdev_err(bp
->dev
, "hwrm alloc invalid ring type %d\n",
3261 mutex_lock(&bp
->hwrm_cmd_lock
);
3262 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3263 err
= le16_to_cpu(resp
->error_code
);
3264 ring_id
= le16_to_cpu(resp
->ring_id
);
3265 mutex_unlock(&bp
->hwrm_cmd_lock
);
3268 switch (ring_type
) {
3269 case RING_FREE_REQ_RING_TYPE_CMPL
:
3270 netdev_err(bp
->dev
, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
3274 case RING_FREE_REQ_RING_TYPE_RX
:
3275 netdev_err(bp
->dev
, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
3279 case RING_FREE_REQ_RING_TYPE_TX
:
3280 netdev_err(bp
->dev
, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
3285 netdev_err(bp
->dev
, "Invalid ring\n");
3289 ring
->fw_ring_id
= ring_id
;
3293 static int bnxt_hwrm_ring_alloc(struct bnxt
*bp
)
3297 if (bp
->cp_nr_rings
) {
3298 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3299 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3300 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3301 struct bnxt_ring_struct
*ring
= &cpr
->cp_ring_struct
;
3303 rc
= hwrm_ring_alloc_send_msg(bp
, ring
,
3304 HWRM_RING_ALLOC_CMPL
, i
,
3305 INVALID_STATS_CTX_ID
);
3308 cpr
->cp_doorbell
= bp
->bar1
+ i
* 0x80;
3309 BNXT_CP_DB(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
3310 bp
->grp_info
[i
].cp_fw_ring_id
= ring
->fw_ring_id
;
3314 if (bp
->tx_nr_rings
) {
3315 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
3316 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3317 struct bnxt_tx_ring_info
*txr
= &bnapi
->tx_ring
;
3318 struct bnxt_ring_struct
*ring
= &txr
->tx_ring_struct
;
3319 u16 fw_stats_ctx
= bp
->grp_info
[i
].fw_stats_ctx
;
3321 rc
= hwrm_ring_alloc_send_msg(bp
, ring
,
3322 HWRM_RING_ALLOC_TX
, i
,
3326 txr
->tx_doorbell
= bp
->bar1
+ i
* 0x80;
3330 if (bp
->rx_nr_rings
) {
3331 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3332 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3333 struct bnxt_rx_ring_info
*rxr
= &bnapi
->rx_ring
;
3334 struct bnxt_ring_struct
*ring
= &rxr
->rx_ring_struct
;
3336 rc
= hwrm_ring_alloc_send_msg(bp
, ring
,
3337 HWRM_RING_ALLOC_RX
, i
,
3338 INVALID_STATS_CTX_ID
);
3341 rxr
->rx_doorbell
= bp
->bar1
+ i
* 0x80;
3342 writel(DB_KEY_RX
| rxr
->rx_prod
, rxr
->rx_doorbell
);
3343 bp
->grp_info
[i
].rx_fw_ring_id
= ring
->fw_ring_id
;
3347 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
) {
3348 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3349 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3350 struct bnxt_rx_ring_info
*rxr
= &bnapi
->rx_ring
;
3351 struct bnxt_ring_struct
*ring
=
3352 &rxr
->rx_agg_ring_struct
;
3354 rc
= hwrm_ring_alloc_send_msg(bp
, ring
,
3355 HWRM_RING_ALLOC_AGG
,
3356 bp
->rx_nr_rings
+ i
,
3357 INVALID_STATS_CTX_ID
);
3361 rxr
->rx_agg_doorbell
=
3362 bp
->bar1
+ (bp
->rx_nr_rings
+ i
) * 0x80;
3363 writel(DB_KEY_RX
| rxr
->rx_agg_prod
,
3364 rxr
->rx_agg_doorbell
);
3365 bp
->grp_info
[i
].agg_fw_ring_id
= ring
->fw_ring_id
;
3372 static int hwrm_ring_free_send_msg(struct bnxt
*bp
,
3373 struct bnxt_ring_struct
*ring
,
3374 u32 ring_type
, int cmpl_ring_id
)
3377 struct hwrm_ring_free_input req
= {0};
3378 struct hwrm_ring_free_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3381 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_FREE
, -1, -1);
3382 req
.ring_type
= ring_type
;
3383 req
.ring_id
= cpu_to_le16(ring
->fw_ring_id
);
3385 mutex_lock(&bp
->hwrm_cmd_lock
);
3386 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3387 error_code
= le16_to_cpu(resp
->error_code
);
3388 mutex_unlock(&bp
->hwrm_cmd_lock
);
3390 if (rc
|| error_code
) {
3391 switch (ring_type
) {
3392 case RING_FREE_REQ_RING_TYPE_CMPL
:
3393 netdev_err(bp
->dev
, "hwrm_ring_free cp failed. rc:%d\n",
3396 case RING_FREE_REQ_RING_TYPE_RX
:
3397 netdev_err(bp
->dev
, "hwrm_ring_free rx failed. rc:%d\n",
3400 case RING_FREE_REQ_RING_TYPE_TX
:
3401 netdev_err(bp
->dev
, "hwrm_ring_free tx failed. rc:%d\n",
3405 netdev_err(bp
->dev
, "Invalid ring\n");
3412 static int bnxt_hwrm_ring_free(struct bnxt
*bp
, bool close_path
)
3419 if (bp
->tx_nr_rings
) {
3420 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
3421 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3422 struct bnxt_tx_ring_info
*txr
= &bnapi
->tx_ring
;
3423 struct bnxt_ring_struct
*ring
= &txr
->tx_ring_struct
;
3424 u32 cmpl_ring_id
= bp
->grp_info
[i
].cp_fw_ring_id
;
3426 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
3427 hwrm_ring_free_send_msg(
3429 RING_FREE_REQ_RING_TYPE_TX
,
3430 close_path
? cmpl_ring_id
:
3431 INVALID_HW_RING_ID
);
3432 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
3437 if (bp
->rx_nr_rings
) {
3438 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3439 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3440 struct bnxt_rx_ring_info
*rxr
= &bnapi
->rx_ring
;
3441 struct bnxt_ring_struct
*ring
= &rxr
->rx_ring_struct
;
3442 u32 cmpl_ring_id
= bp
->grp_info
[i
].cp_fw_ring_id
;
3444 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
3445 hwrm_ring_free_send_msg(
3447 RING_FREE_REQ_RING_TYPE_RX
,
3448 close_path
? cmpl_ring_id
:
3449 INVALID_HW_RING_ID
);
3450 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
3451 bp
->grp_info
[i
].rx_fw_ring_id
=
3457 if (bp
->rx_agg_nr_pages
) {
3458 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3459 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3460 struct bnxt_rx_ring_info
*rxr
= &bnapi
->rx_ring
;
3461 struct bnxt_ring_struct
*ring
=
3462 &rxr
->rx_agg_ring_struct
;
3463 u32 cmpl_ring_id
= bp
->grp_info
[i
].cp_fw_ring_id
;
3465 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
3466 hwrm_ring_free_send_msg(
3468 RING_FREE_REQ_RING_TYPE_RX
,
3469 close_path
? cmpl_ring_id
:
3470 INVALID_HW_RING_ID
);
3471 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
3472 bp
->grp_info
[i
].agg_fw_ring_id
=
3478 if (bp
->cp_nr_rings
) {
3479 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3480 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3481 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3482 struct bnxt_ring_struct
*ring
= &cpr
->cp_ring_struct
;
3484 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
3485 hwrm_ring_free_send_msg(
3487 RING_FREE_REQ_RING_TYPE_CMPL
,
3488 INVALID_HW_RING_ID
);
3489 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
3490 bp
->grp_info
[i
].cp_fw_ring_id
=
3499 int bnxt_hwrm_set_coal(struct bnxt
*bp
)
3502 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req
= {0};
3503 u16 max_buf
, max_buf_irq
;
3504 u16 buf_tmr
, buf_tmr_irq
;
3507 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS
,
3510 /* Each rx completion (2 records) should be DMAed immediately */
3511 max_buf
= min_t(u16
, bp
->coal_bufs
/ 4, 2);
3512 /* max_buf must not be zero */
3513 max_buf
= clamp_t(u16
, max_buf
, 1, 63);
3514 max_buf_irq
= clamp_t(u16
, bp
->coal_bufs_irq
, 1, 63);
3515 buf_tmr
= max_t(u16
, bp
->coal_ticks
/ 4, 1);
3516 buf_tmr_irq
= max_t(u16
, bp
->coal_ticks_irq
, 1);
3518 flags
= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET
;
3520 /* RING_IDLE generates more IRQs for lower latency. Enable it only
3521 * if coal_ticks is less than 25 us.
3523 if (BNXT_COAL_TIMER_TO_USEC(bp
->coal_ticks
) < 25)
3524 flags
|= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE
;
3526 req
.flags
= cpu_to_le16(flags
);
3527 req
.num_cmpl_dma_aggr
= cpu_to_le16(max_buf
);
3528 req
.num_cmpl_dma_aggr_during_int
= cpu_to_le16(max_buf_irq
);
3529 req
.cmpl_aggr_dma_tmr
= cpu_to_le16(buf_tmr
);
3530 req
.cmpl_aggr_dma_tmr_during_int
= cpu_to_le16(buf_tmr_irq
);
3531 req
.int_lat_tmr_min
= cpu_to_le16(buf_tmr
);
3532 req
.int_lat_tmr_max
= cpu_to_le16(bp
->coal_ticks
);
3533 req
.num_cmpl_aggr_int
= cpu_to_le16(bp
->coal_bufs
);
3535 mutex_lock(&bp
->hwrm_cmd_lock
);
3536 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3537 req
.ring_id
= cpu_to_le16(bp
->grp_info
[i
].cp_fw_ring_id
);
3539 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3544 mutex_unlock(&bp
->hwrm_cmd_lock
);
3548 static int bnxt_hwrm_stat_ctx_free(struct bnxt
*bp
)
3551 struct hwrm_stat_ctx_free_input req
= {0};
3556 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_STAT_CTX_FREE
, -1, -1);
3558 mutex_lock(&bp
->hwrm_cmd_lock
);
3559 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3560 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3561 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3563 if (cpr
->hw_stats_ctx_id
!= INVALID_STATS_CTX_ID
) {
3564 req
.stat_ctx_id
= cpu_to_le32(cpr
->hw_stats_ctx_id
);
3566 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3571 cpr
->hw_stats_ctx_id
= INVALID_STATS_CTX_ID
;
3574 mutex_unlock(&bp
->hwrm_cmd_lock
);
3578 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt
*bp
)
3581 struct hwrm_stat_ctx_alloc_input req
= {0};
3582 struct hwrm_stat_ctx_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3584 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_STAT_CTX_ALLOC
, -1, -1);
3586 req
.update_period_ms
= cpu_to_le32(1000);
3588 mutex_lock(&bp
->hwrm_cmd_lock
);
3589 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3590 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3591 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3593 req
.stats_dma_addr
= cpu_to_le64(cpr
->hw_stats_map
);
3595 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3600 cpr
->hw_stats_ctx_id
= le32_to_cpu(resp
->stat_ctx_id
);
3602 bp
->grp_info
[i
].fw_stats_ctx
= cpr
->hw_stats_ctx_id
;
3604 mutex_unlock(&bp
->hwrm_cmd_lock
);
3608 static int bnxt_hwrm_func_qcaps(struct bnxt
*bp
)
3611 struct hwrm_func_qcaps_input req
= {0};
3612 struct hwrm_func_qcaps_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3614 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_QCAPS
, -1, -1);
3615 req
.fid
= cpu_to_le16(0xffff);
3617 mutex_lock(&bp
->hwrm_cmd_lock
);
3618 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3620 goto hwrm_func_qcaps_exit
;
3623 struct bnxt_pf_info
*pf
= &bp
->pf
;
3625 pf
->fw_fid
= le16_to_cpu(resp
->fid
);
3626 pf
->port_id
= le16_to_cpu(resp
->port_id
);
3627 memcpy(pf
->mac_addr
, resp
->perm_mac_address
, ETH_ALEN
);
3628 pf
->max_rsscos_ctxs
= le16_to_cpu(resp
->max_rsscos_ctx
);
3629 pf
->max_cp_rings
= le16_to_cpu(resp
->max_cmpl_rings
);
3630 pf
->max_tx_rings
= le16_to_cpu(resp
->max_tx_rings
);
3631 pf
->max_pf_tx_rings
= pf
->max_tx_rings
;
3632 pf
->max_rx_rings
= le16_to_cpu(resp
->max_rx_rings
);
3633 pf
->max_pf_rx_rings
= pf
->max_rx_rings
;
3634 pf
->max_l2_ctxs
= le16_to_cpu(resp
->max_l2_ctxs
);
3635 pf
->max_vnics
= le16_to_cpu(resp
->max_vnics
);
3636 pf
->max_stat_ctxs
= le16_to_cpu(resp
->max_stat_ctx
);
3637 pf
->first_vf_id
= le16_to_cpu(resp
->first_vf_id
);
3638 pf
->max_vfs
= le16_to_cpu(resp
->max_vfs
);
3639 pf
->max_encap_records
= le32_to_cpu(resp
->max_encap_records
);
3640 pf
->max_decap_records
= le32_to_cpu(resp
->max_decap_records
);
3641 pf
->max_tx_em_flows
= le32_to_cpu(resp
->max_tx_em_flows
);
3642 pf
->max_tx_wm_flows
= le32_to_cpu(resp
->max_tx_wm_flows
);
3643 pf
->max_rx_em_flows
= le32_to_cpu(resp
->max_rx_em_flows
);
3644 pf
->max_rx_wm_flows
= le32_to_cpu(resp
->max_rx_wm_flows
);
3646 #ifdef CONFIG_BNXT_SRIOV
3647 struct bnxt_vf_info
*vf
= &bp
->vf
;
3649 vf
->fw_fid
= le16_to_cpu(resp
->fid
);
3650 memcpy(vf
->mac_addr
, resp
->perm_mac_address
, ETH_ALEN
);
3651 if (!is_valid_ether_addr(vf
->mac_addr
))
3652 random_ether_addr(vf
->mac_addr
);
3654 vf
->max_rsscos_ctxs
= le16_to_cpu(resp
->max_rsscos_ctx
);
3655 vf
->max_cp_rings
= le16_to_cpu(resp
->max_cmpl_rings
);
3656 vf
->max_tx_rings
= le16_to_cpu(resp
->max_tx_rings
);
3657 vf
->max_rx_rings
= le16_to_cpu(resp
->max_rx_rings
);
3658 vf
->max_l2_ctxs
= le16_to_cpu(resp
->max_l2_ctxs
);
3659 vf
->max_vnics
= le16_to_cpu(resp
->max_vnics
);
3660 vf
->max_stat_ctxs
= le16_to_cpu(resp
->max_stat_ctx
);
3664 bp
->tx_push_thresh
= 0;
3666 cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED
))
3667 bp
->tx_push_thresh
= BNXT_TX_PUSH_THRESH
;
3669 hwrm_func_qcaps_exit
:
3670 mutex_unlock(&bp
->hwrm_cmd_lock
);
3674 static int bnxt_hwrm_func_reset(struct bnxt
*bp
)
3676 struct hwrm_func_reset_input req
= {0};
3678 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_RESET
, -1, -1);
3681 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_RESET_TIMEOUT
);
3684 static int bnxt_hwrm_queue_qportcfg(struct bnxt
*bp
)
3687 struct hwrm_queue_qportcfg_input req
= {0};
3688 struct hwrm_queue_qportcfg_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3691 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_QUEUE_QPORTCFG
, -1, -1);
3693 mutex_lock(&bp
->hwrm_cmd_lock
);
3694 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3698 if (!resp
->max_configurable_queues
) {
3702 bp
->max_tc
= resp
->max_configurable_queues
;
3703 if (bp
->max_tc
> BNXT_MAX_QUEUE
)
3704 bp
->max_tc
= BNXT_MAX_QUEUE
;
3706 qptr
= &resp
->queue_id0
;
3707 for (i
= 0; i
< bp
->max_tc
; i
++) {
3708 bp
->q_info
[i
].queue_id
= *qptr
++;
3709 bp
->q_info
[i
].queue_profile
= *qptr
++;
3713 mutex_unlock(&bp
->hwrm_cmd_lock
);
3717 static int bnxt_hwrm_ver_get(struct bnxt
*bp
)
3720 struct hwrm_ver_get_input req
= {0};
3721 struct hwrm_ver_get_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3723 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VER_GET
, -1, -1);
3724 req
.hwrm_intf_maj
= HWRM_VERSION_MAJOR
;
3725 req
.hwrm_intf_min
= HWRM_VERSION_MINOR
;
3726 req
.hwrm_intf_upd
= HWRM_VERSION_UPDATE
;
3727 mutex_lock(&bp
->hwrm_cmd_lock
);
3728 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3730 goto hwrm_ver_get_exit
;
3732 memcpy(&bp
->ver_resp
, resp
, sizeof(struct hwrm_ver_get_output
));
3734 if (req
.hwrm_intf_maj
!= resp
->hwrm_intf_maj
||
3735 req
.hwrm_intf_min
!= resp
->hwrm_intf_min
||
3736 req
.hwrm_intf_upd
!= resp
->hwrm_intf_upd
) {
3737 netdev_warn(bp
->dev
, "HWRM interface %d.%d.%d does not match driver interface %d.%d.%d.\n",
3738 resp
->hwrm_intf_maj
, resp
->hwrm_intf_min
,
3739 resp
->hwrm_intf_upd
, req
.hwrm_intf_maj
,
3740 req
.hwrm_intf_min
, req
.hwrm_intf_upd
);
3741 netdev_warn(bp
->dev
, "Please update driver or firmware with matching interface versions.\n");
3743 snprintf(bp
->fw_ver_str
, BC_HWRM_STR_LEN
, "bc %d.%d.%d rm %d.%d.%d",
3744 resp
->hwrm_fw_maj
, resp
->hwrm_fw_min
, resp
->hwrm_fw_bld
,
3745 resp
->hwrm_intf_maj
, resp
->hwrm_intf_min
, resp
->hwrm_intf_upd
);
3748 mutex_unlock(&bp
->hwrm_cmd_lock
);
3752 static void bnxt_hwrm_free_tunnel_ports(struct bnxt
*bp
)
3754 if (bp
->vxlan_port_cnt
) {
3755 bnxt_hwrm_tunnel_dst_port_free(
3756 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
);
3758 bp
->vxlan_port_cnt
= 0;
3759 if (bp
->nge_port_cnt
) {
3760 bnxt_hwrm_tunnel_dst_port_free(
3761 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
);
3763 bp
->nge_port_cnt
= 0;
3766 static int bnxt_set_tpa(struct bnxt
*bp
, bool set_tpa
)
3772 tpa_flags
= bp
->flags
& BNXT_FLAG_TPA
;
3773 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
3774 rc
= bnxt_hwrm_vnic_set_tpa(bp
, i
, tpa_flags
);
3776 netdev_err(bp
->dev
, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
3784 static void bnxt_hwrm_clear_vnic_rss(struct bnxt
*bp
)
3788 for (i
= 0; i
< bp
->nr_vnics
; i
++)
3789 bnxt_hwrm_vnic_set_rss(bp
, i
, false);
3792 static void bnxt_hwrm_resource_free(struct bnxt
*bp
, bool close_path
,
3795 if (bp
->vnic_info
) {
3796 bnxt_hwrm_clear_vnic_filter(bp
);
3797 /* clear all RSS setting before free vnic ctx */
3798 bnxt_hwrm_clear_vnic_rss(bp
);
3799 bnxt_hwrm_vnic_ctx_free(bp
);
3800 /* before free the vnic, undo the vnic tpa settings */
3801 if (bp
->flags
& BNXT_FLAG_TPA
)
3802 bnxt_set_tpa(bp
, false);
3803 bnxt_hwrm_vnic_free(bp
);
3805 bnxt_hwrm_ring_free(bp
, close_path
);
3806 bnxt_hwrm_ring_grp_free(bp
);
3808 bnxt_hwrm_stat_ctx_free(bp
);
3809 bnxt_hwrm_free_tunnel_ports(bp
);
3813 static int bnxt_setup_vnic(struct bnxt
*bp
, u16 vnic_id
)
3817 /* allocate context for vnic */
3818 rc
= bnxt_hwrm_vnic_ctx_alloc(bp
, vnic_id
);
3820 netdev_err(bp
->dev
, "hwrm vnic %d alloc failure rc: %x\n",
3822 goto vnic_setup_err
;
3824 bp
->rsscos_nr_ctxs
++;
3826 /* configure default vnic, ring grp */
3827 rc
= bnxt_hwrm_vnic_cfg(bp
, vnic_id
);
3829 netdev_err(bp
->dev
, "hwrm vnic %d cfg failure rc: %x\n",
3831 goto vnic_setup_err
;
3834 /* Enable RSS hashing on vnic */
3835 rc
= bnxt_hwrm_vnic_set_rss(bp
, vnic_id
, true);
3837 netdev_err(bp
->dev
, "hwrm vnic %d set rss failure rc: %x\n",
3839 goto vnic_setup_err
;
3842 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
) {
3843 rc
= bnxt_hwrm_vnic_set_hds(bp
, vnic_id
);
3845 netdev_err(bp
->dev
, "hwrm vnic %d set hds failure rc: %x\n",
3854 static int bnxt_alloc_rfs_vnics(struct bnxt
*bp
)
3856 #ifdef CONFIG_RFS_ACCEL
3859 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3860 u16 vnic_id
= i
+ 1;
3863 if (vnic_id
>= bp
->nr_vnics
)
3866 bp
->vnic_info
[vnic_id
].flags
|= BNXT_VNIC_RFS_FLAG
;
3867 rc
= bnxt_hwrm_vnic_alloc(bp
, vnic_id
, ring_id
, ring_id
+ 1);
3869 netdev_err(bp
->dev
, "hwrm vnic %d alloc failure rc: %x\n",
3873 rc
= bnxt_setup_vnic(bp
, vnic_id
);
3883 static int bnxt_init_chip(struct bnxt
*bp
, bool irq_re_init
)
3888 rc
= bnxt_hwrm_stat_ctx_alloc(bp
);
3890 netdev_err(bp
->dev
, "hwrm stat ctx alloc failure rc: %x\n",
3896 rc
= bnxt_hwrm_ring_alloc(bp
);
3898 netdev_err(bp
->dev
, "hwrm ring alloc failure rc: %x\n", rc
);
3902 rc
= bnxt_hwrm_ring_grp_alloc(bp
);
3904 netdev_err(bp
->dev
, "hwrm_ring_grp alloc failure: %x\n", rc
);
3908 /* default vnic 0 */
3909 rc
= bnxt_hwrm_vnic_alloc(bp
, 0, 0, bp
->rx_nr_rings
);
3911 netdev_err(bp
->dev
, "hwrm vnic alloc failure rc: %x\n", rc
);
3915 rc
= bnxt_setup_vnic(bp
, 0);
3919 if (bp
->flags
& BNXT_FLAG_RFS
) {
3920 rc
= bnxt_alloc_rfs_vnics(bp
);
3925 if (bp
->flags
& BNXT_FLAG_TPA
) {
3926 rc
= bnxt_set_tpa(bp
, true);
3932 bnxt_update_vf_mac(bp
);
3934 /* Filter for default vnic 0 */
3935 rc
= bnxt_hwrm_set_vnic_filter(bp
, 0, 0, bp
->dev
->dev_addr
);
3937 netdev_err(bp
->dev
, "HWRM vnic filter failure rc: %x\n", rc
);
3940 bp
->vnic_info
[0].uc_filter_count
= 1;
3942 bp
->vnic_info
[0].rx_mask
= CFA_L2_SET_RX_MASK_REQ_MASK_UNICAST
|
3943 CFA_L2_SET_RX_MASK_REQ_MASK_BCAST
;
3945 if ((bp
->dev
->flags
& IFF_PROMISC
) && BNXT_PF(bp
))
3946 bp
->vnic_info
[0].rx_mask
|=
3947 CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
;
3949 rc
= bnxt_hwrm_cfa_l2_set_rx_mask(bp
, 0);
3951 netdev_err(bp
->dev
, "HWRM cfa l2 rx mask failure rc: %x\n", rc
);
3955 rc
= bnxt_hwrm_set_coal(bp
);
3957 netdev_warn(bp
->dev
, "HWRM set coalescing failure rc: %x\n",
3963 bnxt_hwrm_resource_free(bp
, 0, true);
3968 static int bnxt_shutdown_nic(struct bnxt
*bp
, bool irq_re_init
)
3970 bnxt_hwrm_resource_free(bp
, 1, irq_re_init
);
3974 static int bnxt_init_nic(struct bnxt
*bp
, bool irq_re_init
)
3976 bnxt_init_rx_rings(bp
);
3977 bnxt_init_tx_rings(bp
);
3978 bnxt_init_ring_grps(bp
, irq_re_init
);
3979 bnxt_init_vnics(bp
);
3981 return bnxt_init_chip(bp
, irq_re_init
);
3984 static void bnxt_disable_int(struct bnxt
*bp
)
3991 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3992 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3993 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3995 BNXT_CP_DB(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
3999 static void bnxt_enable_int(struct bnxt
*bp
)
4003 atomic_set(&bp
->intr_sem
, 0);
4004 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4005 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4006 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
4008 BNXT_CP_DB_REARM(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
4012 static int bnxt_set_real_num_queues(struct bnxt
*bp
)
4015 struct net_device
*dev
= bp
->dev
;
4017 rc
= netif_set_real_num_tx_queues(dev
, bp
->tx_nr_rings
);
4021 rc
= netif_set_real_num_rx_queues(dev
, bp
->rx_nr_rings
);
4025 #ifdef CONFIG_RFS_ACCEL
4026 if (bp
->rx_nr_rings
)
4027 dev
->rx_cpu_rmap
= alloc_irq_cpu_rmap(bp
->rx_nr_rings
);
4028 if (!dev
->rx_cpu_rmap
)
4035 static int bnxt_setup_msix(struct bnxt
*bp
)
4037 struct msix_entry
*msix_ent
;
4038 struct net_device
*dev
= bp
->dev
;
4039 int i
, total_vecs
, rc
= 0;
4040 const int len
= sizeof(bp
->irq_tbl
[0].name
);
4042 bp
->flags
&= ~BNXT_FLAG_USING_MSIX
;
4043 total_vecs
= bp
->cp_nr_rings
;
4045 msix_ent
= kcalloc(total_vecs
, sizeof(struct msix_entry
), GFP_KERNEL
);
4049 for (i
= 0; i
< total_vecs
; i
++) {
4050 msix_ent
[i
].entry
= i
;
4051 msix_ent
[i
].vector
= 0;
4054 total_vecs
= pci_enable_msix_range(bp
->pdev
, msix_ent
, 1, total_vecs
);
4055 if (total_vecs
< 0) {
4057 goto msix_setup_exit
;
4060 bp
->irq_tbl
= kcalloc(total_vecs
, sizeof(struct bnxt_irq
), GFP_KERNEL
);
4064 /* Trim rings based upon num of vectors allocated */
4065 bp
->rx_nr_rings
= min_t(int, total_vecs
, bp
->rx_nr_rings
);
4066 bp
->tx_nr_rings
= min_t(int, total_vecs
, bp
->tx_nr_rings
);
4067 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
;
4068 tcs
= netdev_get_num_tc(dev
);
4070 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
/ tcs
;
4071 if (bp
->tx_nr_rings_per_tc
== 0) {
4072 netdev_reset_tc(dev
);
4073 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
;
4077 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
* tcs
;
4078 for (i
= 0; i
< tcs
; i
++) {
4079 count
= bp
->tx_nr_rings_per_tc
;
4081 netdev_set_tc_queue(dev
, i
, count
, off
);
4085 bp
->cp_nr_rings
= max_t(int, bp
->rx_nr_rings
, bp
->tx_nr_rings
);
4087 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4088 bp
->irq_tbl
[i
].vector
= msix_ent
[i
].vector
;
4089 snprintf(bp
->irq_tbl
[i
].name
, len
,
4090 "%s-%s-%d", dev
->name
, "TxRx", i
);
4091 bp
->irq_tbl
[i
].handler
= bnxt_msix
;
4093 rc
= bnxt_set_real_num_queues(bp
);
4095 goto msix_setup_exit
;
4098 goto msix_setup_exit
;
4100 bp
->flags
|= BNXT_FLAG_USING_MSIX
;
4105 netdev_err(bp
->dev
, "bnxt_setup_msix err: %x\n", rc
);
4106 pci_disable_msix(bp
->pdev
);
4111 static int bnxt_setup_inta(struct bnxt
*bp
)
4114 const int len
= sizeof(bp
->irq_tbl
[0].name
);
4116 if (netdev_get_num_tc(bp
->dev
))
4117 netdev_reset_tc(bp
->dev
);
4119 bp
->irq_tbl
= kcalloc(1, sizeof(struct bnxt_irq
), GFP_KERNEL
);
4124 bp
->rx_nr_rings
= 1;
4125 bp
->tx_nr_rings
= 1;
4126 bp
->cp_nr_rings
= 1;
4127 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
;
4128 bp
->irq_tbl
[0].vector
= bp
->pdev
->irq
;
4129 snprintf(bp
->irq_tbl
[0].name
, len
,
4130 "%s-%s-%d", bp
->dev
->name
, "TxRx", 0);
4131 bp
->irq_tbl
[0].handler
= bnxt_inta
;
4132 rc
= bnxt_set_real_num_queues(bp
);
4136 static int bnxt_setup_int_mode(struct bnxt
*bp
)
4140 if (bp
->flags
& BNXT_FLAG_MSIX_CAP
)
4141 rc
= bnxt_setup_msix(bp
);
4143 if (!(bp
->flags
& BNXT_FLAG_USING_MSIX
)) {
4144 /* fallback to INTA */
4145 rc
= bnxt_setup_inta(bp
);
4150 static void bnxt_free_irq(struct bnxt
*bp
)
4152 struct bnxt_irq
*irq
;
4155 #ifdef CONFIG_RFS_ACCEL
4156 free_irq_cpu_rmap(bp
->dev
->rx_cpu_rmap
);
4157 bp
->dev
->rx_cpu_rmap
= NULL
;
4162 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4163 irq
= &bp
->irq_tbl
[i
];
4165 free_irq(irq
->vector
, bp
->bnapi
[i
]);
4168 if (bp
->flags
& BNXT_FLAG_USING_MSIX
)
4169 pci_disable_msix(bp
->pdev
);
4174 static int bnxt_request_irq(struct bnxt
*bp
)
4177 unsigned long flags
= 0;
4178 #ifdef CONFIG_RFS_ACCEL
4179 struct cpu_rmap
*rmap
= bp
->dev
->rx_cpu_rmap
;
4182 if (!(bp
->flags
& BNXT_FLAG_USING_MSIX
))
4183 flags
= IRQF_SHARED
;
4185 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4186 struct bnxt_irq
*irq
= &bp
->irq_tbl
[i
];
4187 #ifdef CONFIG_RFS_ACCEL
4188 if (rmap
&& (i
< bp
->rx_nr_rings
)) {
4189 rc
= irq_cpu_rmap_add(rmap
, irq
->vector
);
4191 netdev_warn(bp
->dev
, "failed adding irq rmap for ring %d\n",
4195 rc
= request_irq(irq
->vector
, irq
->handler
, flags
, irq
->name
,
4205 static void bnxt_del_napi(struct bnxt
*bp
)
4212 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4213 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4215 napi_hash_del(&bnapi
->napi
);
4216 netif_napi_del(&bnapi
->napi
);
4220 static void bnxt_init_napi(struct bnxt
*bp
)
4223 struct bnxt_napi
*bnapi
;
4225 if (bp
->flags
& BNXT_FLAG_USING_MSIX
) {
4226 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4227 bnapi
= bp
->bnapi
[i
];
4228 netif_napi_add(bp
->dev
, &bnapi
->napi
,
4230 napi_hash_add(&bnapi
->napi
);
4233 bnapi
= bp
->bnapi
[0];
4234 netif_napi_add(bp
->dev
, &bnapi
->napi
, bnxt_poll
, 64);
4235 napi_hash_add(&bnapi
->napi
);
4239 static void bnxt_disable_napi(struct bnxt
*bp
)
4246 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4247 napi_disable(&bp
->bnapi
[i
]->napi
);
4248 bnxt_disable_poll(bp
->bnapi
[i
]);
4252 static void bnxt_enable_napi(struct bnxt
*bp
)
4256 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4257 bnxt_enable_poll(bp
->bnapi
[i
]);
4258 napi_enable(&bp
->bnapi
[i
]->napi
);
4262 static void bnxt_tx_disable(struct bnxt
*bp
)
4265 struct bnxt_napi
*bnapi
;
4266 struct bnxt_tx_ring_info
*txr
;
4267 struct netdev_queue
*txq
;
4270 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
4271 bnapi
= bp
->bnapi
[i
];
4272 txr
= &bnapi
->tx_ring
;
4273 txq
= netdev_get_tx_queue(bp
->dev
, i
);
4274 __netif_tx_lock(txq
, smp_processor_id());
4275 txr
->dev_state
= BNXT_DEV_STATE_CLOSING
;
4276 __netif_tx_unlock(txq
);
4279 /* Stop all TX queues */
4280 netif_tx_disable(bp
->dev
);
4281 netif_carrier_off(bp
->dev
);
4284 static void bnxt_tx_enable(struct bnxt
*bp
)
4287 struct bnxt_napi
*bnapi
;
4288 struct bnxt_tx_ring_info
*txr
;
4289 struct netdev_queue
*txq
;
4291 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
4292 bnapi
= bp
->bnapi
[i
];
4293 txr
= &bnapi
->tx_ring
;
4294 txq
= netdev_get_tx_queue(bp
->dev
, i
);
4297 netif_tx_wake_all_queues(bp
->dev
);
4298 if (bp
->link_info
.link_up
)
4299 netif_carrier_on(bp
->dev
);
4302 static void bnxt_report_link(struct bnxt
*bp
)
4304 if (bp
->link_info
.link_up
) {
4306 const char *flow_ctrl
;
4309 netif_carrier_on(bp
->dev
);
4310 if (bp
->link_info
.duplex
== BNXT_LINK_DUPLEX_FULL
)
4314 if (bp
->link_info
.pause
== BNXT_LINK_PAUSE_BOTH
)
4315 flow_ctrl
= "ON - receive & transmit";
4316 else if (bp
->link_info
.pause
== BNXT_LINK_PAUSE_TX
)
4317 flow_ctrl
= "ON - transmit";
4318 else if (bp
->link_info
.pause
== BNXT_LINK_PAUSE_RX
)
4319 flow_ctrl
= "ON - receive";
4322 speed
= bnxt_fw_to_ethtool_speed(bp
->link_info
.link_speed
);
4323 netdev_info(bp
->dev
, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
4324 speed
, duplex
, flow_ctrl
);
4326 netif_carrier_off(bp
->dev
);
4327 netdev_err(bp
->dev
, "NIC Link is Down\n");
4331 static int bnxt_update_link(struct bnxt
*bp
, bool chng_link_state
)
4334 struct bnxt_link_info
*link_info
= &bp
->link_info
;
4335 struct hwrm_port_phy_qcfg_input req
= {0};
4336 struct hwrm_port_phy_qcfg_output
*resp
= bp
->hwrm_cmd_resp_addr
;
4337 u8 link_up
= link_info
->link_up
;
4339 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_QCFG
, -1, -1);
4341 mutex_lock(&bp
->hwrm_cmd_lock
);
4342 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4344 mutex_unlock(&bp
->hwrm_cmd_lock
);
4348 memcpy(&link_info
->phy_qcfg_resp
, resp
, sizeof(*resp
));
4349 link_info
->phy_link_status
= resp
->link
;
4350 link_info
->duplex
= resp
->duplex
;
4351 link_info
->pause
= resp
->pause
;
4352 link_info
->auto_mode
= resp
->auto_mode
;
4353 link_info
->auto_pause_setting
= resp
->auto_pause
;
4354 link_info
->force_pause_setting
= resp
->force_pause
;
4355 link_info
->duplex_setting
= resp
->duplex_setting
;
4356 if (link_info
->phy_link_status
== BNXT_LINK_LINK
)
4357 link_info
->link_speed
= le16_to_cpu(resp
->link_speed
);
4359 link_info
->link_speed
= 0;
4360 link_info
->force_link_speed
= le16_to_cpu(resp
->force_link_speed
);
4361 link_info
->auto_link_speed
= le16_to_cpu(resp
->auto_link_speed
);
4362 link_info
->support_speeds
= le16_to_cpu(resp
->support_speeds
);
4363 link_info
->auto_link_speeds
= le16_to_cpu(resp
->auto_link_speed_mask
);
4364 link_info
->preemphasis
= le32_to_cpu(resp
->preemphasis
);
4365 link_info
->phy_ver
[0] = resp
->phy_maj
;
4366 link_info
->phy_ver
[1] = resp
->phy_min
;
4367 link_info
->phy_ver
[2] = resp
->phy_bld
;
4368 link_info
->media_type
= resp
->media_type
;
4369 link_info
->transceiver
= resp
->transceiver_type
;
4370 link_info
->phy_addr
= resp
->phy_addr
;
4372 /* TODO: need to add more logic to report VF link */
4373 if (chng_link_state
) {
4374 if (link_info
->phy_link_status
== BNXT_LINK_LINK
)
4375 link_info
->link_up
= 1;
4377 link_info
->link_up
= 0;
4378 if (link_up
!= link_info
->link_up
)
4379 bnxt_report_link(bp
);
4381 /* alwasy link down if not require to update link state */
4382 link_info
->link_up
= 0;
4384 mutex_unlock(&bp
->hwrm_cmd_lock
);
4389 bnxt_hwrm_set_pause_common(struct bnxt
*bp
, struct hwrm_port_phy_cfg_input
*req
)
4391 if (bp
->link_info
.autoneg
& BNXT_AUTONEG_FLOW_CTRL
) {
4392 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_RX
)
4393 req
->auto_pause
|= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX
;
4394 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_TX
)
4395 req
->auto_pause
|= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX
;
4397 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE
);
4399 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_RX
)
4400 req
->force_pause
|= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX
;
4401 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_TX
)
4402 req
->force_pause
|= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX
;
4404 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE
);
4408 static void bnxt_hwrm_set_link_common(struct bnxt
*bp
,
4409 struct hwrm_port_phy_cfg_input
*req
)
4411 u8 autoneg
= bp
->link_info
.autoneg
;
4412 u16 fw_link_speed
= bp
->link_info
.req_link_speed
;
4413 u32 advertising
= bp
->link_info
.advertising
;
4415 if (autoneg
& BNXT_AUTONEG_SPEED
) {
4417 PORT_PHY_CFG_REQ_AUTO_MODE_MASK
;
4419 req
->enables
|= cpu_to_le32(
4420 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK
);
4421 req
->auto_link_speed_mask
= cpu_to_le16(advertising
);
4423 req
->enables
|= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE
);
4425 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG
);
4427 req
->force_link_speed
= cpu_to_le16(fw_link_speed
);
4428 req
->flags
|= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE
);
4431 /* currently don't support half duplex */
4432 req
->auto_duplex
= PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL
;
4433 req
->enables
|= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX
);
4434 /* tell chimp that the setting takes effect immediately */
4435 req
->flags
|= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY
);
4438 int bnxt_hwrm_set_pause(struct bnxt
*bp
)
4440 struct hwrm_port_phy_cfg_input req
= {0};
4443 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_CFG
, -1, -1);
4444 bnxt_hwrm_set_pause_common(bp
, &req
);
4446 if ((bp
->link_info
.autoneg
& BNXT_AUTONEG_FLOW_CTRL
) ||
4447 bp
->link_info
.force_link_chng
)
4448 bnxt_hwrm_set_link_common(bp
, &req
);
4450 mutex_lock(&bp
->hwrm_cmd_lock
);
4451 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4452 if (!rc
&& !(bp
->link_info
.autoneg
& BNXT_AUTONEG_FLOW_CTRL
)) {
4453 /* since changing of pause setting doesn't trigger any link
4454 * change event, the driver needs to update the current pause
4455 * result upon successfully return of the phy_cfg command
4457 bp
->link_info
.pause
=
4458 bp
->link_info
.force_pause_setting
= bp
->link_info
.req_flow_ctrl
;
4459 bp
->link_info
.auto_pause_setting
= 0;
4460 if (!bp
->link_info
.force_link_chng
)
4461 bnxt_report_link(bp
);
4463 bp
->link_info
.force_link_chng
= false;
4464 mutex_unlock(&bp
->hwrm_cmd_lock
);
4468 int bnxt_hwrm_set_link_setting(struct bnxt
*bp
, bool set_pause
)
4470 struct hwrm_port_phy_cfg_input req
= {0};
4472 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_CFG
, -1, -1);
4474 bnxt_hwrm_set_pause_common(bp
, &req
);
4476 bnxt_hwrm_set_link_common(bp
, &req
);
4477 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4480 static int bnxt_update_phy_setting(struct bnxt
*bp
)
4483 bool update_link
= false;
4484 bool update_pause
= false;
4485 struct bnxt_link_info
*link_info
= &bp
->link_info
;
4487 rc
= bnxt_update_link(bp
, true);
4489 netdev_err(bp
->dev
, "failed to update link (rc: %x)\n",
4493 if ((link_info
->autoneg
& BNXT_AUTONEG_FLOW_CTRL
) &&
4494 link_info
->auto_pause_setting
!= link_info
->req_flow_ctrl
)
4495 update_pause
= true;
4496 if (!(link_info
->autoneg
& BNXT_AUTONEG_FLOW_CTRL
) &&
4497 link_info
->force_pause_setting
!= link_info
->req_flow_ctrl
)
4498 update_pause
= true;
4499 if (link_info
->req_duplex
!= link_info
->duplex_setting
)
4501 if (!(link_info
->autoneg
& BNXT_AUTONEG_SPEED
)) {
4502 if (BNXT_AUTO_MODE(link_info
->auto_mode
))
4504 if (link_info
->req_link_speed
!= link_info
->force_link_speed
)
4507 if (link_info
->auto_mode
== BNXT_LINK_AUTO_NONE
)
4509 if (link_info
->advertising
!= link_info
->auto_link_speeds
)
4511 if (link_info
->req_link_speed
!= link_info
->auto_link_speed
)
4516 rc
= bnxt_hwrm_set_link_setting(bp
, update_pause
);
4517 else if (update_pause
)
4518 rc
= bnxt_hwrm_set_pause(bp
);
4520 netdev_err(bp
->dev
, "failed to update phy setting (rc: %x)\n",
4528 /* Common routine to pre-map certain register block to different GRC window.
4529 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
4530 * in PF and 3 windows in VF that can be customized to map in different
4533 static void bnxt_preset_reg_win(struct bnxt
*bp
)
4536 /* CAG registers map to GRC window #4 */
4537 writel(BNXT_CAG_REG_BASE
,
4538 bp
->bar0
+ BNXT_GRCPF_REG_WINDOW_BASE_OUT
+ 12);
4542 static int __bnxt_open_nic(struct bnxt
*bp
, bool irq_re_init
, bool link_re_init
)
4546 bnxt_preset_reg_win(bp
);
4547 netif_carrier_off(bp
->dev
);
4549 rc
= bnxt_setup_int_mode(bp
);
4551 netdev_err(bp
->dev
, "bnxt_setup_int_mode err: %x\n",
4556 if ((bp
->flags
& BNXT_FLAG_RFS
) &&
4557 !(bp
->flags
& BNXT_FLAG_USING_MSIX
)) {
4558 /* disable RFS if falling back to INTA */
4559 bp
->dev
->hw_features
&= ~NETIF_F_NTUPLE
;
4560 bp
->flags
&= ~BNXT_FLAG_RFS
;
4563 rc
= bnxt_alloc_mem(bp
, irq_re_init
);
4565 netdev_err(bp
->dev
, "bnxt_alloc_mem err: %x\n", rc
);
4566 goto open_err_free_mem
;
4571 rc
= bnxt_request_irq(bp
);
4573 netdev_err(bp
->dev
, "bnxt_request_irq err: %x\n", rc
);
4578 bnxt_enable_napi(bp
);
4580 rc
= bnxt_init_nic(bp
, irq_re_init
);
4582 netdev_err(bp
->dev
, "bnxt_init_nic err: %x\n", rc
);
4587 rc
= bnxt_update_phy_setting(bp
);
4593 #if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE)
4594 vxlan_get_rx_port(bp
->dev
);
4596 if (!bnxt_hwrm_tunnel_dst_port_alloc(
4598 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
))
4599 bp
->nge_port_cnt
= 1;
4602 bp
->state
= BNXT_STATE_OPEN
;
4603 bnxt_enable_int(bp
);
4604 /* Enable TX queues */
4606 mod_timer(&bp
->timer
, jiffies
+ bp
->current_interval
);
4611 bnxt_disable_napi(bp
);
4617 bnxt_free_mem(bp
, true);
4621 /* rtnl_lock held */
4622 int bnxt_open_nic(struct bnxt
*bp
, bool irq_re_init
, bool link_re_init
)
4626 rc
= __bnxt_open_nic(bp
, irq_re_init
, link_re_init
);
4628 netdev_err(bp
->dev
, "nic open fail (rc: %x)\n", rc
);
4634 static int bnxt_open(struct net_device
*dev
)
4636 struct bnxt
*bp
= netdev_priv(dev
);
4639 rc
= bnxt_hwrm_func_reset(bp
);
4641 netdev_err(bp
->dev
, "hwrm chip reset failure rc: %x\n",
4646 return __bnxt_open_nic(bp
, true, true);
4649 static void bnxt_disable_int_sync(struct bnxt
*bp
)
4653 atomic_inc(&bp
->intr_sem
);
4654 if (!netif_running(bp
->dev
))
4657 bnxt_disable_int(bp
);
4658 for (i
= 0; i
< bp
->cp_nr_rings
; i
++)
4659 synchronize_irq(bp
->irq_tbl
[i
].vector
);
4662 int bnxt_close_nic(struct bnxt
*bp
, bool irq_re_init
, bool link_re_init
)
4666 #ifdef CONFIG_BNXT_SRIOV
4667 if (bp
->sriov_cfg
) {
4668 rc
= wait_event_interruptible_timeout(bp
->sriov_cfg_wait
,
4670 BNXT_SRIOV_CFG_WAIT_TMO
);
4672 netdev_warn(bp
->dev
, "timeout waiting for SRIOV config operation to complete!\n");
4675 /* Change device state to avoid TX queue wake up's */
4676 bnxt_tx_disable(bp
);
4678 bp
->state
= BNXT_STATE_CLOSED
;
4679 cancel_work_sync(&bp
->sp_task
);
4681 /* Flush rings before disabling interrupts */
4682 bnxt_shutdown_nic(bp
, irq_re_init
);
4684 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
4686 bnxt_disable_napi(bp
);
4687 bnxt_disable_int_sync(bp
);
4688 del_timer_sync(&bp
->timer
);
4695 bnxt_free_mem(bp
, irq_re_init
);
4699 static int bnxt_close(struct net_device
*dev
)
4701 struct bnxt
*bp
= netdev_priv(dev
);
4703 bnxt_close_nic(bp
, true, true);
4707 /* rtnl_lock held */
4708 static int bnxt_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
4714 if (!netif_running(dev
))
4721 if (!netif_running(dev
))
4733 static struct rtnl_link_stats64
*
4734 bnxt_get_stats64(struct net_device
*dev
, struct rtnl_link_stats64
*stats
)
4737 struct bnxt
*bp
= netdev_priv(dev
);
4739 memset(stats
, 0, sizeof(struct rtnl_link_stats64
));
4744 /* TODO check if we need to synchronize with bnxt_close path */
4745 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4746 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4747 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
4748 struct ctx_hw_stats
*hw_stats
= cpr
->hw_stats
;
4750 stats
->rx_packets
+= le64_to_cpu(hw_stats
->rx_ucast_pkts
);
4751 stats
->rx_packets
+= le64_to_cpu(hw_stats
->rx_mcast_pkts
);
4752 stats
->rx_packets
+= le64_to_cpu(hw_stats
->rx_bcast_pkts
);
4754 stats
->tx_packets
+= le64_to_cpu(hw_stats
->tx_ucast_pkts
);
4755 stats
->tx_packets
+= le64_to_cpu(hw_stats
->tx_mcast_pkts
);
4756 stats
->tx_packets
+= le64_to_cpu(hw_stats
->tx_bcast_pkts
);
4758 stats
->rx_bytes
+= le64_to_cpu(hw_stats
->rx_ucast_bytes
);
4759 stats
->rx_bytes
+= le64_to_cpu(hw_stats
->rx_mcast_bytes
);
4760 stats
->rx_bytes
+= le64_to_cpu(hw_stats
->rx_bcast_bytes
);
4762 stats
->tx_bytes
+= le64_to_cpu(hw_stats
->tx_ucast_bytes
);
4763 stats
->tx_bytes
+= le64_to_cpu(hw_stats
->tx_mcast_bytes
);
4764 stats
->tx_bytes
+= le64_to_cpu(hw_stats
->tx_bcast_bytes
);
4766 stats
->rx_missed_errors
+=
4767 le64_to_cpu(hw_stats
->rx_discard_pkts
);
4769 stats
->multicast
+= le64_to_cpu(hw_stats
->rx_mcast_pkts
);
4771 stats
->rx_dropped
+= le64_to_cpu(hw_stats
->rx_drop_pkts
);
4773 stats
->tx_dropped
+= le64_to_cpu(hw_stats
->tx_drop_pkts
);
4779 static bool bnxt_mc_list_updated(struct bnxt
*bp
, u32
*rx_mask
)
4781 struct net_device
*dev
= bp
->dev
;
4782 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
4783 struct netdev_hw_addr
*ha
;
4786 bool update
= false;
4789 netdev_for_each_mc_addr(ha
, dev
) {
4790 if (mc_count
>= BNXT_MAX_MC_ADDRS
) {
4791 *rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
;
4792 vnic
->mc_list_count
= 0;
4796 if (!ether_addr_equal(haddr
, vnic
->mc_list
+ off
)) {
4797 memcpy(vnic
->mc_list
+ off
, haddr
, ETH_ALEN
);
4804 *rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST
;
4806 if (mc_count
!= vnic
->mc_list_count
) {
4807 vnic
->mc_list_count
= mc_count
;
4813 static bool bnxt_uc_list_updated(struct bnxt
*bp
)
4815 struct net_device
*dev
= bp
->dev
;
4816 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
4817 struct netdev_hw_addr
*ha
;
4820 if (netdev_uc_count(dev
) != (vnic
->uc_filter_count
- 1))
4823 netdev_for_each_uc_addr(ha
, dev
) {
4824 if (!ether_addr_equal(ha
->addr
, vnic
->uc_list
+ off
))
4832 static void bnxt_set_rx_mode(struct net_device
*dev
)
4834 struct bnxt
*bp
= netdev_priv(dev
);
4835 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
4836 u32 mask
= vnic
->rx_mask
;
4837 bool mc_update
= false;
4840 if (!netif_running(dev
))
4843 mask
&= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
|
4844 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST
|
4845 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
);
4847 /* Only allow PF to be in promiscuous mode */
4848 if ((dev
->flags
& IFF_PROMISC
) && BNXT_PF(bp
))
4849 mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
;
4851 uc_update
= bnxt_uc_list_updated(bp
);
4853 if (dev
->flags
& IFF_ALLMULTI
) {
4854 mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
;
4855 vnic
->mc_list_count
= 0;
4857 mc_update
= bnxt_mc_list_updated(bp
, &mask
);
4860 if (mask
!= vnic
->rx_mask
|| uc_update
|| mc_update
) {
4861 vnic
->rx_mask
= mask
;
4863 set_bit(BNXT_RX_MASK_SP_EVENT
, &bp
->sp_event
);
4864 schedule_work(&bp
->sp_task
);
4868 static void bnxt_cfg_rx_mode(struct bnxt
*bp
)
4870 struct net_device
*dev
= bp
->dev
;
4871 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
4872 struct netdev_hw_addr
*ha
;
4876 netif_addr_lock_bh(dev
);
4877 uc_update
= bnxt_uc_list_updated(bp
);
4878 netif_addr_unlock_bh(dev
);
4883 mutex_lock(&bp
->hwrm_cmd_lock
);
4884 for (i
= 1; i
< vnic
->uc_filter_count
; i
++) {
4885 struct hwrm_cfa_l2_filter_free_input req
= {0};
4887 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_L2_FILTER_FREE
, -1,
4890 req
.l2_filter_id
= vnic
->fw_l2_filter_id
[i
];
4892 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
4895 mutex_unlock(&bp
->hwrm_cmd_lock
);
4897 vnic
->uc_filter_count
= 1;
4899 netif_addr_lock_bh(dev
);
4900 if (netdev_uc_count(dev
) > (BNXT_MAX_UC_ADDRS
- 1)) {
4901 vnic
->rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
;
4903 netdev_for_each_uc_addr(ha
, dev
) {
4904 memcpy(vnic
->uc_list
+ off
, ha
->addr
, ETH_ALEN
);
4906 vnic
->uc_filter_count
++;
4909 netif_addr_unlock_bh(dev
);
4911 for (i
= 1, off
= 0; i
< vnic
->uc_filter_count
; i
++, off
+= ETH_ALEN
) {
4912 rc
= bnxt_hwrm_set_vnic_filter(bp
, 0, i
, vnic
->uc_list
+ off
);
4914 netdev_err(bp
->dev
, "HWRM vnic filter failure rc: %x\n",
4916 vnic
->uc_filter_count
= i
;
4921 rc
= bnxt_hwrm_cfa_l2_set_rx_mask(bp
, 0);
4923 netdev_err(bp
->dev
, "HWRM cfa l2 rx mask failure rc: %x\n",
4927 static netdev_features_t
bnxt_fix_features(struct net_device
*dev
,
4928 netdev_features_t features
)
4933 static int bnxt_set_features(struct net_device
*dev
, netdev_features_t features
)
4935 struct bnxt
*bp
= netdev_priv(dev
);
4936 u32 flags
= bp
->flags
;
4939 bool re_init
= false;
4940 bool update_tpa
= false;
4942 flags
&= ~BNXT_FLAG_ALL_CONFIG_FEATS
;
4943 if ((features
& NETIF_F_GRO
) && (bp
->pdev
->revision
> 0))
4944 flags
|= BNXT_FLAG_GRO
;
4945 if (features
& NETIF_F_LRO
)
4946 flags
|= BNXT_FLAG_LRO
;
4948 if (features
& NETIF_F_HW_VLAN_CTAG_RX
)
4949 flags
|= BNXT_FLAG_STRIP_VLAN
;
4951 if (features
& NETIF_F_NTUPLE
)
4952 flags
|= BNXT_FLAG_RFS
;
4954 changes
= flags
^ bp
->flags
;
4955 if (changes
& BNXT_FLAG_TPA
) {
4957 if ((bp
->flags
& BNXT_FLAG_TPA
) == 0 ||
4958 (flags
& BNXT_FLAG_TPA
) == 0)
4962 if (changes
& ~BNXT_FLAG_TPA
)
4965 if (flags
!= bp
->flags
) {
4966 u32 old_flags
= bp
->flags
;
4970 if (!netif_running(dev
)) {
4972 bnxt_set_ring_params(bp
);
4977 bnxt_close_nic(bp
, false, false);
4979 bnxt_set_ring_params(bp
);
4981 return bnxt_open_nic(bp
, false, false);
4984 rc
= bnxt_set_tpa(bp
,
4985 (flags
& BNXT_FLAG_TPA
) ?
4988 bp
->flags
= old_flags
;
4994 static void bnxt_dbg_dump_states(struct bnxt
*bp
)
4997 struct bnxt_napi
*bnapi
;
4998 struct bnxt_tx_ring_info
*txr
;
4999 struct bnxt_rx_ring_info
*rxr
;
5000 struct bnxt_cp_ring_info
*cpr
;
5002 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
5003 bnapi
= bp
->bnapi
[i
];
5004 txr
= &bnapi
->tx_ring
;
5005 rxr
= &bnapi
->rx_ring
;
5006 cpr
= &bnapi
->cp_ring
;
5007 if (netif_msg_drv(bp
)) {
5008 netdev_info(bp
->dev
, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
5009 i
, txr
->tx_ring_struct
.fw_ring_id
,
5010 txr
->tx_prod
, txr
->tx_cons
);
5011 netdev_info(bp
->dev
, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
5012 i
, rxr
->rx_ring_struct
.fw_ring_id
,
5014 rxr
->rx_agg_ring_struct
.fw_ring_id
,
5015 rxr
->rx_agg_prod
, rxr
->rx_sw_agg_prod
);
5016 netdev_info(bp
->dev
, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
5017 i
, cpr
->cp_ring_struct
.fw_ring_id
,
5023 static void bnxt_reset_task(struct bnxt
*bp
)
5025 bnxt_dbg_dump_states(bp
);
5026 if (netif_running(bp
->dev
))
5027 bnxt_tx_disable(bp
); /* prevent tx timout again */
5030 static void bnxt_tx_timeout(struct net_device
*dev
)
5032 struct bnxt
*bp
= netdev_priv(dev
);
5034 netdev_err(bp
->dev
, "TX timeout detected, starting reset task!\n");
5035 set_bit(BNXT_RESET_TASK_SP_EVENT
, &bp
->sp_event
);
5036 schedule_work(&bp
->sp_task
);
5039 #ifdef CONFIG_NET_POLL_CONTROLLER
5040 static void bnxt_poll_controller(struct net_device
*dev
)
5042 struct bnxt
*bp
= netdev_priv(dev
);
5045 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
5046 struct bnxt_irq
*irq
= &bp
->irq_tbl
[i
];
5048 disable_irq(irq
->vector
);
5049 irq
->handler(irq
->vector
, bp
->bnapi
[i
]);
5050 enable_irq(irq
->vector
);
5055 static void bnxt_timer(unsigned long data
)
5057 struct bnxt
*bp
= (struct bnxt
*)data
;
5058 struct net_device
*dev
= bp
->dev
;
5060 if (!netif_running(dev
))
5063 if (atomic_read(&bp
->intr_sem
) != 0)
5064 goto bnxt_restart_timer
;
5067 mod_timer(&bp
->timer
, jiffies
+ bp
->current_interval
);
5070 static void bnxt_cfg_ntp_filters(struct bnxt
*);
5072 static void bnxt_sp_task(struct work_struct
*work
)
5074 struct bnxt
*bp
= container_of(work
, struct bnxt
, sp_task
);
5077 if (bp
->state
!= BNXT_STATE_OPEN
)
5080 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT
, &bp
->sp_event
))
5081 bnxt_cfg_rx_mode(bp
);
5083 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT
, &bp
->sp_event
))
5084 bnxt_cfg_ntp_filters(bp
);
5085 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT
, &bp
->sp_event
)) {
5086 rc
= bnxt_update_link(bp
, true);
5088 netdev_err(bp
->dev
, "SP task can't update link (rc: %x)\n",
5091 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT
, &bp
->sp_event
))
5092 bnxt_hwrm_exec_fwd_req(bp
);
5093 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT
, &bp
->sp_event
)) {
5094 bnxt_hwrm_tunnel_dst_port_alloc(
5096 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
);
5098 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT
, &bp
->sp_event
)) {
5099 bnxt_hwrm_tunnel_dst_port_free(
5100 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
);
5102 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT
, &bp
->sp_event
))
5103 bnxt_reset_task(bp
);
5106 static int bnxt_init_board(struct pci_dev
*pdev
, struct net_device
*dev
)
5109 struct bnxt
*bp
= netdev_priv(dev
);
5111 SET_NETDEV_DEV(dev
, &pdev
->dev
);
5113 /* enable device (incl. PCI PM wakeup), and bus-mastering */
5114 rc
= pci_enable_device(pdev
);
5116 dev_err(&pdev
->dev
, "Cannot enable PCI device, aborting\n");
5120 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
5122 "Cannot find PCI device base address, aborting\n");
5124 goto init_err_disable
;
5127 rc
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
5129 dev_err(&pdev
->dev
, "Cannot obtain PCI resources, aborting\n");
5130 goto init_err_disable
;
5133 if (dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(64)) != 0 &&
5134 dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(32)) != 0) {
5135 dev_err(&pdev
->dev
, "System does not support DMA, aborting\n");
5136 goto init_err_disable
;
5139 pci_set_master(pdev
);
5144 bp
->bar0
= pci_ioremap_bar(pdev
, 0);
5146 dev_err(&pdev
->dev
, "Cannot map device registers, aborting\n");
5148 goto init_err_release
;
5151 bp
->bar1
= pci_ioremap_bar(pdev
, 2);
5153 dev_err(&pdev
->dev
, "Cannot map doorbell registers, aborting\n");
5155 goto init_err_release
;
5158 bp
->bar2
= pci_ioremap_bar(pdev
, 4);
5160 dev_err(&pdev
->dev
, "Cannot map bar4 registers, aborting\n");
5162 goto init_err_release
;
5165 INIT_WORK(&bp
->sp_task
, bnxt_sp_task
);
5167 spin_lock_init(&bp
->ntp_fltr_lock
);
5169 bp
->rx_ring_size
= BNXT_DEFAULT_RX_RING_SIZE
;
5170 bp
->tx_ring_size
= BNXT_DEFAULT_TX_RING_SIZE
;
5172 bp
->coal_ticks
= BNXT_USEC_TO_COAL_TIMER(4);
5174 bp
->coal_ticks_irq
= BNXT_USEC_TO_COAL_TIMER(1);
5175 bp
->coal_bufs_irq
= 2;
5177 init_timer(&bp
->timer
);
5178 bp
->timer
.data
= (unsigned long)bp
;
5179 bp
->timer
.function
= bnxt_timer
;
5180 bp
->current_interval
= BNXT_TIMER_INTERVAL
;
5182 bp
->state
= BNXT_STATE_CLOSED
;
5188 pci_iounmap(pdev
, bp
->bar2
);
5193 pci_iounmap(pdev
, bp
->bar1
);
5198 pci_iounmap(pdev
, bp
->bar0
);
5202 pci_release_regions(pdev
);
5205 pci_disable_device(pdev
);
5211 /* rtnl_lock held */
5212 static int bnxt_change_mac_addr(struct net_device
*dev
, void *p
)
5214 struct sockaddr
*addr
= p
;
5216 if (!is_valid_ether_addr(addr
->sa_data
))
5217 return -EADDRNOTAVAIL
;
5219 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
5224 /* rtnl_lock held */
5225 static int bnxt_change_mtu(struct net_device
*dev
, int new_mtu
)
5227 struct bnxt
*bp
= netdev_priv(dev
);
5229 if (new_mtu
< 60 || new_mtu
> 9000)
5232 if (netif_running(dev
))
5233 bnxt_close_nic(bp
, false, false);
5236 bnxt_set_ring_params(bp
);
5238 if (netif_running(dev
))
5239 return bnxt_open_nic(bp
, false, false);
5244 static int bnxt_setup_tc(struct net_device
*dev
, u8 tc
)
5246 struct bnxt
*bp
= netdev_priv(dev
);
5248 if (tc
> bp
->max_tc
) {
5249 netdev_err(dev
, "too many traffic classes requested: %d Max supported is %d\n",
5254 if (netdev_get_num_tc(dev
) == tc
)
5258 int max_rx_rings
, max_tx_rings
;
5260 bnxt_get_max_rings(bp
, &max_rx_rings
, &max_tx_rings
);
5261 if (bp
->tx_nr_rings_per_tc
* tc
> max_tx_rings
)
5265 /* Needs to close the device and do hw resource re-allocations */
5266 if (netif_running(bp
->dev
))
5267 bnxt_close_nic(bp
, true, false);
5270 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
* tc
;
5271 netdev_set_num_tc(dev
, tc
);
5273 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
;
5274 netdev_reset_tc(dev
);
5276 bp
->cp_nr_rings
= max_t(int, bp
->tx_nr_rings
, bp
->rx_nr_rings
);
5277 bp
->num_stat_ctxs
= bp
->cp_nr_rings
;
5279 if (netif_running(bp
->dev
))
5280 return bnxt_open_nic(bp
, true, false);
5285 #ifdef CONFIG_RFS_ACCEL
5286 static bool bnxt_fltr_match(struct bnxt_ntuple_filter
*f1
,
5287 struct bnxt_ntuple_filter
*f2
)
5289 struct flow_keys
*keys1
= &f1
->fkeys
;
5290 struct flow_keys
*keys2
= &f2
->fkeys
;
5292 if (keys1
->addrs
.v4addrs
.src
== keys2
->addrs
.v4addrs
.src
&&
5293 keys1
->addrs
.v4addrs
.dst
== keys2
->addrs
.v4addrs
.dst
&&
5294 keys1
->ports
.ports
== keys2
->ports
.ports
&&
5295 keys1
->basic
.ip_proto
== keys2
->basic
.ip_proto
&&
5296 keys1
->basic
.n_proto
== keys2
->basic
.n_proto
&&
5297 ether_addr_equal(f1
->src_mac_addr
, f2
->src_mac_addr
))
5303 static int bnxt_rx_flow_steer(struct net_device
*dev
, const struct sk_buff
*skb
,
5304 u16 rxq_index
, u32 flow_id
)
5306 struct bnxt
*bp
= netdev_priv(dev
);
5307 struct bnxt_ntuple_filter
*fltr
, *new_fltr
;
5308 struct flow_keys
*fkeys
;
5309 struct ethhdr
*eth
= (struct ethhdr
*)skb_mac_header(skb
);
5310 int rc
= 0, idx
, bit_id
;
5311 struct hlist_head
*head
;
5313 if (skb
->encapsulation
)
5314 return -EPROTONOSUPPORT
;
5316 new_fltr
= kzalloc(sizeof(*new_fltr
), GFP_ATOMIC
);
5320 fkeys
= &new_fltr
->fkeys
;
5321 if (!skb_flow_dissect_flow_keys(skb
, fkeys
, 0)) {
5322 rc
= -EPROTONOSUPPORT
;
5326 if ((fkeys
->basic
.n_proto
!= htons(ETH_P_IP
)) ||
5327 ((fkeys
->basic
.ip_proto
!= IPPROTO_TCP
) &&
5328 (fkeys
->basic
.ip_proto
!= IPPROTO_UDP
))) {
5329 rc
= -EPROTONOSUPPORT
;
5333 memcpy(new_fltr
->src_mac_addr
, eth
->h_source
, ETH_ALEN
);
5335 idx
= skb_get_hash_raw(skb
) & BNXT_NTP_FLTR_HASH_MASK
;
5336 head
= &bp
->ntp_fltr_hash_tbl
[idx
];
5338 hlist_for_each_entry_rcu(fltr
, head
, hash
) {
5339 if (bnxt_fltr_match(fltr
, new_fltr
)) {
5347 spin_lock_bh(&bp
->ntp_fltr_lock
);
5348 bit_id
= bitmap_find_free_region(bp
->ntp_fltr_bmap
,
5349 BNXT_NTP_FLTR_MAX_FLTR
, 0);
5351 spin_unlock_bh(&bp
->ntp_fltr_lock
);
5356 new_fltr
->sw_id
= (u16
)bit_id
;
5357 new_fltr
->flow_id
= flow_id
;
5358 new_fltr
->rxq
= rxq_index
;
5359 hlist_add_head_rcu(&new_fltr
->hash
, head
);
5360 bp
->ntp_fltr_count
++;
5361 spin_unlock_bh(&bp
->ntp_fltr_lock
);
5363 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT
, &bp
->sp_event
);
5364 schedule_work(&bp
->sp_task
);
5366 return new_fltr
->sw_id
;
5373 static void bnxt_cfg_ntp_filters(struct bnxt
*bp
)
5377 for (i
= 0; i
< BNXT_NTP_FLTR_HASH_SIZE
; i
++) {
5378 struct hlist_head
*head
;
5379 struct hlist_node
*tmp
;
5380 struct bnxt_ntuple_filter
*fltr
;
5383 head
= &bp
->ntp_fltr_hash_tbl
[i
];
5384 hlist_for_each_entry_safe(fltr
, tmp
, head
, hash
) {
5387 if (test_bit(BNXT_FLTR_VALID
, &fltr
->state
)) {
5388 if (rps_may_expire_flow(bp
->dev
, fltr
->rxq
,
5391 bnxt_hwrm_cfa_ntuple_filter_free(bp
,
5396 rc
= bnxt_hwrm_cfa_ntuple_filter_alloc(bp
,
5401 set_bit(BNXT_FLTR_VALID
, &fltr
->state
);
5405 spin_lock_bh(&bp
->ntp_fltr_lock
);
5406 hlist_del_rcu(&fltr
->hash
);
5407 bp
->ntp_fltr_count
--;
5408 spin_unlock_bh(&bp
->ntp_fltr_lock
);
5410 clear_bit(fltr
->sw_id
, bp
->ntp_fltr_bmap
);
5419 static void bnxt_cfg_ntp_filters(struct bnxt
*bp
)
5423 #endif /* CONFIG_RFS_ACCEL */
5425 static void bnxt_add_vxlan_port(struct net_device
*dev
, sa_family_t sa_family
,
5428 struct bnxt
*bp
= netdev_priv(dev
);
5430 if (!netif_running(dev
))
5433 if (sa_family
!= AF_INET6
&& sa_family
!= AF_INET
)
5436 if (bp
->vxlan_port_cnt
&& bp
->vxlan_port
!= port
)
5439 bp
->vxlan_port_cnt
++;
5440 if (bp
->vxlan_port_cnt
== 1) {
5441 bp
->vxlan_port
= port
;
5442 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT
, &bp
->sp_event
);
5443 schedule_work(&bp
->sp_task
);
5447 static void bnxt_del_vxlan_port(struct net_device
*dev
, sa_family_t sa_family
,
5450 struct bnxt
*bp
= netdev_priv(dev
);
5452 if (!netif_running(dev
))
5455 if (sa_family
!= AF_INET6
&& sa_family
!= AF_INET
)
5458 if (bp
->vxlan_port_cnt
&& bp
->vxlan_port
== port
) {
5459 bp
->vxlan_port_cnt
--;
5461 if (bp
->vxlan_port_cnt
== 0) {
5462 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT
, &bp
->sp_event
);
5463 schedule_work(&bp
->sp_task
);
5468 static const struct net_device_ops bnxt_netdev_ops
= {
5469 .ndo_open
= bnxt_open
,
5470 .ndo_start_xmit
= bnxt_start_xmit
,
5471 .ndo_stop
= bnxt_close
,
5472 .ndo_get_stats64
= bnxt_get_stats64
,
5473 .ndo_set_rx_mode
= bnxt_set_rx_mode
,
5474 .ndo_do_ioctl
= bnxt_ioctl
,
5475 .ndo_validate_addr
= eth_validate_addr
,
5476 .ndo_set_mac_address
= bnxt_change_mac_addr
,
5477 .ndo_change_mtu
= bnxt_change_mtu
,
5478 .ndo_fix_features
= bnxt_fix_features
,
5479 .ndo_set_features
= bnxt_set_features
,
5480 .ndo_tx_timeout
= bnxt_tx_timeout
,
5481 #ifdef CONFIG_BNXT_SRIOV
5482 .ndo_get_vf_config
= bnxt_get_vf_config
,
5483 .ndo_set_vf_mac
= bnxt_set_vf_mac
,
5484 .ndo_set_vf_vlan
= bnxt_set_vf_vlan
,
5485 .ndo_set_vf_rate
= bnxt_set_vf_bw
,
5486 .ndo_set_vf_link_state
= bnxt_set_vf_link_state
,
5487 .ndo_set_vf_spoofchk
= bnxt_set_vf_spoofchk
,
5489 #ifdef CONFIG_NET_POLL_CONTROLLER
5490 .ndo_poll_controller
= bnxt_poll_controller
,
5492 .ndo_setup_tc
= bnxt_setup_tc
,
5493 #ifdef CONFIG_RFS_ACCEL
5494 .ndo_rx_flow_steer
= bnxt_rx_flow_steer
,
5496 .ndo_add_vxlan_port
= bnxt_add_vxlan_port
,
5497 .ndo_del_vxlan_port
= bnxt_del_vxlan_port
,
5498 #ifdef CONFIG_NET_RX_BUSY_POLL
5499 .ndo_busy_poll
= bnxt_busy_poll
,
5503 static void bnxt_remove_one(struct pci_dev
*pdev
)
5505 struct net_device
*dev
= pci_get_drvdata(pdev
);
5506 struct bnxt
*bp
= netdev_priv(dev
);
5509 bnxt_sriov_disable(bp
);
5511 unregister_netdev(dev
);
5512 cancel_work_sync(&bp
->sp_task
);
5515 bnxt_free_hwrm_resources(bp
);
5516 pci_iounmap(pdev
, bp
->bar2
);
5517 pci_iounmap(pdev
, bp
->bar1
);
5518 pci_iounmap(pdev
, bp
->bar0
);
5521 pci_release_regions(pdev
);
5522 pci_disable_device(pdev
);
5525 static int bnxt_probe_phy(struct bnxt
*bp
)
5528 struct bnxt_link_info
*link_info
= &bp
->link_info
;
5529 char phy_ver
[PHY_VER_STR_LEN
];
5531 rc
= bnxt_update_link(bp
, false);
5533 netdev_err(bp
->dev
, "Probe phy can't update link (rc: %x)\n",
5538 /*initialize the ethool setting copy with NVM settings */
5539 if (BNXT_AUTO_MODE(link_info
->auto_mode
))
5540 link_info
->autoneg
|= BNXT_AUTONEG_SPEED
;
5542 if (link_info
->auto_pause_setting
& BNXT_LINK_PAUSE_BOTH
) {
5543 if (link_info
->auto_pause_setting
== BNXT_LINK_PAUSE_BOTH
)
5544 link_info
->autoneg
|= BNXT_AUTONEG_FLOW_CTRL
;
5545 link_info
->req_flow_ctrl
= link_info
->auto_pause_setting
;
5546 } else if (link_info
->force_pause_setting
& BNXT_LINK_PAUSE_BOTH
) {
5547 link_info
->req_flow_ctrl
= link_info
->force_pause_setting
;
5549 link_info
->req_duplex
= link_info
->duplex_setting
;
5550 if (link_info
->autoneg
& BNXT_AUTONEG_SPEED
)
5551 link_info
->req_link_speed
= link_info
->auto_link_speed
;
5553 link_info
->req_link_speed
= link_info
->force_link_speed
;
5554 link_info
->advertising
= link_info
->auto_link_speeds
;
5555 snprintf(phy_ver
, PHY_VER_STR_LEN
, " ph %d.%d.%d",
5556 link_info
->phy_ver
[0],
5557 link_info
->phy_ver
[1],
5558 link_info
->phy_ver
[2]);
5559 strcat(bp
->fw_ver_str
, phy_ver
);
5563 static int bnxt_get_max_irq(struct pci_dev
*pdev
)
5567 if (!pdev
->msix_cap
)
5570 pci_read_config_word(pdev
, pdev
->msix_cap
+ PCI_MSIX_FLAGS
, &ctrl
);
5571 return (ctrl
& PCI_MSIX_FLAGS_QSIZE
) + 1;
5574 void bnxt_get_max_rings(struct bnxt
*bp
, int *max_rx
, int *max_tx
)
5579 *max_tx
= bp
->pf
.max_pf_tx_rings
;
5580 *max_rx
= bp
->pf
.max_pf_rx_rings
;
5581 max_rings
= min_t(int, bp
->pf
.max_irqs
, bp
->pf
.max_cp_rings
);
5582 max_rings
= min_t(int, max_rings
, bp
->pf
.max_stat_ctxs
);
5584 #ifdef CONFIG_BNXT_SRIOV
5585 *max_tx
= bp
->vf
.max_tx_rings
;
5586 *max_rx
= bp
->vf
.max_rx_rings
;
5587 max_rings
= min_t(int, bp
->vf
.max_irqs
, bp
->vf
.max_cp_rings
);
5588 max_rings
= min_t(int, max_rings
, bp
->vf
.max_stat_ctxs
);
5591 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
)
5594 *max_rx
= min_t(int, *max_rx
, max_rings
);
5595 *max_tx
= min_t(int, *max_tx
, max_rings
);
5598 static int bnxt_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
5600 static int version_printed
;
5601 struct net_device
*dev
;
5603 int rc
, max_rx_rings
, max_tx_rings
, max_irqs
, dflt_rings
;
5605 if (version_printed
++ == 0)
5606 pr_info("%s", version
);
5608 max_irqs
= bnxt_get_max_irq(pdev
);
5609 dev
= alloc_etherdev_mq(sizeof(*bp
), max_irqs
);
5613 bp
= netdev_priv(dev
);
5615 if (bnxt_vf_pciid(ent
->driver_data
))
5616 bp
->flags
|= BNXT_FLAG_VF
;
5618 if (pdev
->msix_cap
) {
5619 bp
->flags
|= BNXT_FLAG_MSIX_CAP
;
5621 bp
->flags
|= BNXT_FLAG_RFS
;
5624 rc
= bnxt_init_board(pdev
, dev
);
5628 dev
->netdev_ops
= &bnxt_netdev_ops
;
5629 dev
->watchdog_timeo
= BNXT_TX_TIMEOUT
;
5630 dev
->ethtool_ops
= &bnxt_ethtool_ops
;
5632 pci_set_drvdata(pdev
, dev
);
5634 dev
->hw_features
= NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
| NETIF_F_SG
|
5635 NETIF_F_TSO
| NETIF_F_TSO6
|
5636 NETIF_F_GSO_UDP_TUNNEL
| NETIF_F_GSO_GRE
|
5637 NETIF_F_GSO_IPIP
| NETIF_F_GSO_SIT
|
5639 NETIF_F_RXCSUM
| NETIF_F_LRO
| NETIF_F_GRO
;
5641 if (bp
->flags
& BNXT_FLAG_RFS
)
5642 dev
->hw_features
|= NETIF_F_NTUPLE
;
5644 dev
->hw_enc_features
=
5645 NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
| NETIF_F_SG
|
5646 NETIF_F_TSO
| NETIF_F_TSO6
|
5647 NETIF_F_GSO_UDP_TUNNEL
| NETIF_F_GSO_GRE
|
5648 NETIF_F_GSO_IPIP
| NETIF_F_GSO_SIT
;
5649 dev
->vlan_features
= dev
->hw_features
| NETIF_F_HIGHDMA
;
5650 dev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_RX
| NETIF_F_HW_VLAN_CTAG_TX
|
5651 NETIF_F_HW_VLAN_STAG_RX
| NETIF_F_HW_VLAN_STAG_TX
;
5652 dev
->features
|= dev
->hw_features
| NETIF_F_HIGHDMA
;
5653 dev
->priv_flags
|= IFF_UNICAST_FLT
;
5655 #ifdef CONFIG_BNXT_SRIOV
5656 init_waitqueue_head(&bp
->sriov_cfg_wait
);
5658 rc
= bnxt_alloc_hwrm_resources(bp
);
5662 mutex_init(&bp
->hwrm_cmd_lock
);
5663 bnxt_hwrm_ver_get(bp
);
5665 rc
= bnxt_hwrm_func_drv_rgtr(bp
);
5669 /* Get the MAX capabilities for this function */
5670 rc
= bnxt_hwrm_func_qcaps(bp
);
5672 netdev_err(bp
->dev
, "hwrm query capability failure rc: %x\n",
5678 rc
= bnxt_hwrm_queue_qportcfg(bp
);
5680 netdev_err(bp
->dev
, "hwrm query qportcfg failure rc: %x\n",
5686 bnxt_set_tpa_flags(bp
);
5687 bnxt_set_ring_params(bp
);
5688 dflt_rings
= netif_get_num_default_rss_queues();
5690 memcpy(dev
->dev_addr
, bp
->pf
.mac_addr
, ETH_ALEN
);
5691 bp
->pf
.max_irqs
= max_irqs
;
5693 #if defined(CONFIG_BNXT_SRIOV)
5694 memcpy(dev
->dev_addr
, bp
->vf
.mac_addr
, ETH_ALEN
);
5695 bp
->vf
.max_irqs
= max_irqs
;
5698 bnxt_get_max_rings(bp
, &max_rx_rings
, &max_tx_rings
);
5699 bp
->rx_nr_rings
= min_t(int, dflt_rings
, max_rx_rings
);
5700 bp
->tx_nr_rings_per_tc
= min_t(int, dflt_rings
, max_tx_rings
);
5701 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
;
5702 bp
->cp_nr_rings
= max_t(int, bp
->rx_nr_rings
, bp
->tx_nr_rings
);
5703 bp
->num_stat_ctxs
= bp
->cp_nr_rings
;
5705 if (dev
->hw_features
& NETIF_F_HW_VLAN_CTAG_RX
)
5706 bp
->flags
|= BNXT_FLAG_STRIP_VLAN
;
5708 rc
= bnxt_probe_phy(bp
);
5712 rc
= register_netdev(dev
);
5716 netdev_info(dev
, "%s found at mem %lx, node addr %pM\n",
5717 board_info
[ent
->driver_data
].name
,
5718 (long)pci_resource_start(pdev
, 0), dev
->dev_addr
);
5723 pci_iounmap(pdev
, bp
->bar0
);
5724 pci_release_regions(pdev
);
5725 pci_disable_device(pdev
);
5732 static struct pci_driver bnxt_pci_driver
= {
5733 .name
= DRV_MODULE_NAME
,
5734 .id_table
= bnxt_pci_tbl
,
5735 .probe
= bnxt_init_one
,
5736 .remove
= bnxt_remove_one
,
5737 #if defined(CONFIG_BNXT_SRIOV)
5738 .sriov_configure
= bnxt_sriov_configure
,
5742 module_pci_driver(bnxt_pci_driver
);