]> git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blob - drivers/net/ethernet/broadcom/bnxt/bnxt.c
projects / mirror_ubuntu-jammy-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge tag 'mac80211-next-for-net-next-2021-08-20' of git://git.kernel.org/pub/scm...
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / broadcom / bnxt / bnxt.c
1 /* Broadcom NetXtreme-C/E network driver.
2 *
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2019 Broadcom Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
9 */
10
11 #include <linux/module.h>
12
13 #include <linux/stringify.h>
14 #include <linux/kernel.h>
15 #include <linux/timer.h>
16 #include <linux/errno.h>
17 #include <linux/ioport.h>
18 #include <linux/slab.h>
19 #include <linux/vmalloc.h>
20 #include <linux/interrupt.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
23 #include <linux/etherdevice.h>
24 #include <linux/skbuff.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/bitops.h>
27 #include <linux/io.h>
28 #include <linux/irq.h>
29 #include <linux/delay.h>
30 #include <asm/byteorder.h>
31 #include <asm/page.h>
32 #include <linux/time.h>
33 #include <linux/mii.h>
34 #include <linux/mdio.h>
35 #include <linux/if.h>
36 #include <linux/if_vlan.h>
37 #include <linux/if_bridge.h>
38 #include <linux/rtc.h>
39 #include <linux/bpf.h>
40 #include <net/ip.h>
41 #include <net/tcp.h>
42 #include <net/udp.h>
43 #include <net/checksum.h>
44 #include <net/ip6_checksum.h>
45 #include <net/udp_tunnel.h>
46 #include <linux/workqueue.h>
47 #include <linux/prefetch.h>
48 #include <linux/cache.h>
49 #include <linux/log2.h>
50 #include <linux/aer.h>
51 #include <linux/bitmap.h>
52 #include <linux/ptp_clock_kernel.h>
53 #include <linux/timecounter.h>
54 #include <linux/cpu_rmap.h>
55 #include <linux/cpumask.h>
56 #include <net/pkt_cls.h>
57 #include <linux/hwmon.h>
58 #include <linux/hwmon-sysfs.h>
59 #include <net/page_pool.h>
60
61 #include "bnxt_hsi.h"
62 #include "bnxt.h"
63 #include "bnxt_ulp.h"
64 #include "bnxt_sriov.h"
65 #include "bnxt_ethtool.h"
66 #include "bnxt_dcb.h"
67 #include "bnxt_xdp.h"
68 #include "bnxt_ptp.h"
69 #include "bnxt_vfr.h"
70 #include "bnxt_tc.h"
71 #include "bnxt_devlink.h"
72 #include "bnxt_debugfs.h"
73
74 #define BNXT_TX_TIMEOUT (5 * HZ)
75 #define BNXT_DEF_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_HW | \
76 NETIF_MSG_TX_ERR)
77
78 MODULE_LICENSE("GPL");
79 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
80
81 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
82 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
83 #define BNXT_RX_COPY_THRESH 256
84
85 #define BNXT_TX_PUSH_THRESH 164
86
87 enum board_idx {
88 BCM57301,
89 BCM57302,
90 BCM57304,
91 BCM57417_NPAR,
92 BCM58700,
93 BCM57311,
94 BCM57312,
95 BCM57402,
96 BCM57404,
97 BCM57406,
98 BCM57402_NPAR,
99 BCM57407,
100 BCM57412,
101 BCM57414,
102 BCM57416,
103 BCM57417,
104 BCM57412_NPAR,
105 BCM57314,
106 BCM57417_SFP,
107 BCM57416_SFP,
108 BCM57404_NPAR,
109 BCM57406_NPAR,
110 BCM57407_SFP,
111 BCM57407_NPAR,
112 BCM57414_NPAR,
113 BCM57416_NPAR,
114 BCM57452,
115 BCM57454,
116 BCM5745x_NPAR,
117 BCM57508,
118 BCM57504,
119 BCM57502,
120 BCM57508_NPAR,
121 BCM57504_NPAR,
122 BCM57502_NPAR,
123 BCM58802,
124 BCM58804,
125 BCM58808,
126 NETXTREME_E_VF,
127 NETXTREME_C_VF,
128 NETXTREME_S_VF,
129 NETXTREME_C_VF_HV,
130 NETXTREME_E_VF_HV,
131 NETXTREME_E_P5_VF,
132 NETXTREME_E_P5_VF_HV,
133 };
134
135 /* indexed by enum above */
136 static const struct {
137 char *name;
138 } board_info[] = {
139 [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
140 [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
141 [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
142 [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
143 [BCM58700] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
144 [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
145 [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
146 [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
147 [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
148 [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
149 [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
150 [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
151 [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
152 [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
153 [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
154 [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
155 [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
156 [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
157 [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
158 [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
159 [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
160 [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
161 [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
162 [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
163 [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
164 [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
165 [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" },
166 [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
167 [BCM5745x_NPAR] = { "Broadcom BCM5745x NetXtreme-E Ethernet Partition" },
168 [BCM57508] = { "Broadcom BCM57508 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" },
169 [BCM57504] = { "Broadcom BCM57504 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" },
170 [BCM57502] = { "Broadcom BCM57502 NetXtreme-E 10Gb/25Gb/50Gb Ethernet" },
171 [BCM57508_NPAR] = { "Broadcom BCM57508 NetXtreme-E Ethernet Partition" },
172 [BCM57504_NPAR] = { "Broadcom BCM57504 NetXtreme-E Ethernet Partition" },
173 [BCM57502_NPAR] = { "Broadcom BCM57502 NetXtreme-E Ethernet Partition" },
174 [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" },
175 [BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
176 [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
177 [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" },
178 [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" },
179 [NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" },
180 [NETXTREME_C_VF_HV] = { "Broadcom NetXtreme-C Virtual Function for Hyper-V" },
181 [NETXTREME_E_VF_HV] = { "Broadcom NetXtreme-E Virtual Function for Hyper-V" },
182 [NETXTREME_E_P5_VF] = { "Broadcom BCM5750X NetXtreme-E Ethernet Virtual Function" },
183 [NETXTREME_E_P5_VF_HV] = { "Broadcom BCM5750X NetXtreme-E Virtual Function for Hyper-V" },
184 };
185
186 static const struct pci_device_id bnxt_pci_tbl[] = {
187 { PCI_VDEVICE(BROADCOM, 0x1604), .driver_data = BCM5745x_NPAR },
188 { PCI_VDEVICE(BROADCOM, 0x1605), .driver_data = BCM5745x_NPAR },
189 { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 },
190 { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR },
191 { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
192 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
193 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
194 { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR },
195 { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 },
196 { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 },
197 { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 },
198 { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
199 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
200 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
201 { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR },
202 { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 },
203 { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 },
204 { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 },
205 { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 },
206 { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 },
207 { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR },
208 { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
209 { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP },
210 { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP },
211 { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR },
212 { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR },
213 { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP },
214 { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR },
215 { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR },
216 { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR },
217 { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR },
218 { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR },
219 { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR },
220 { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 },
221 { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 },
222 { PCI_VDEVICE(BROADCOM, 0x1750), .driver_data = BCM57508 },
223 { PCI_VDEVICE(BROADCOM, 0x1751), .driver_data = BCM57504 },
224 { PCI_VDEVICE(BROADCOM, 0x1752), .driver_data = BCM57502 },
225 { PCI_VDEVICE(BROADCOM, 0x1800), .driver_data = BCM57508_NPAR },
226 { PCI_VDEVICE(BROADCOM, 0x1801), .driver_data = BCM57504_NPAR },
227 { PCI_VDEVICE(BROADCOM, 0x1802), .driver_data = BCM57502_NPAR },
228 { PCI_VDEVICE(BROADCOM, 0x1803), .driver_data = BCM57508_NPAR },
229 { PCI_VDEVICE(BROADCOM, 0x1804), .driver_data = BCM57504_NPAR },
230 { PCI_VDEVICE(BROADCOM, 0x1805), .driver_data = BCM57502_NPAR },
231 { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 },
232 { PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 },
233 #ifdef CONFIG_BNXT_SRIOV
234 { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF },
235 { PCI_VDEVICE(BROADCOM, 0x1607), .driver_data = NETXTREME_E_VF_HV },
236 { PCI_VDEVICE(BROADCOM, 0x1608), .driver_data = NETXTREME_E_VF_HV },
237 { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF },
238 { PCI_VDEVICE(BROADCOM, 0x16bd), .driver_data = NETXTREME_E_VF_HV },
239 { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF },
240 { PCI_VDEVICE(BROADCOM, 0x16c2), .driver_data = NETXTREME_C_VF_HV },
241 { PCI_VDEVICE(BROADCOM, 0x16c3), .driver_data = NETXTREME_C_VF_HV },
242 { PCI_VDEVICE(BROADCOM, 0x16c4), .driver_data = NETXTREME_E_VF_HV },
243 { PCI_VDEVICE(BROADCOM, 0x16c5), .driver_data = NETXTREME_E_VF_HV },
244 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF },
245 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF },
246 { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF },
247 { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF },
248 { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF },
249 { PCI_VDEVICE(BROADCOM, 0x16e6), .driver_data = NETXTREME_C_VF_HV },
250 { PCI_VDEVICE(BROADCOM, 0x1806), .driver_data = NETXTREME_E_P5_VF },
251 { PCI_VDEVICE(BROADCOM, 0x1807), .driver_data = NETXTREME_E_P5_VF },
252 { PCI_VDEVICE(BROADCOM, 0x1808), .driver_data = NETXTREME_E_P5_VF_HV },
253 { PCI_VDEVICE(BROADCOM, 0x1809), .driver_data = NETXTREME_E_P5_VF_HV },
254 { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF },
255 #endif
256 { 0 }
257 };
258
259 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
260
261 static const u16 bnxt_vf_req_snif[] = {
262 HWRM_FUNC_CFG,
263 HWRM_FUNC_VF_CFG,
264 HWRM_PORT_PHY_QCFG,
265 HWRM_CFA_L2_FILTER_ALLOC,
266 };
267
268 static const u16 bnxt_async_events_arr[] = {
269 ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
270 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE,
271 ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
272 ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
273 ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
274 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
275 ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE,
276 ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY,
277 ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY,
278 ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION,
279 ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG,
280 ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST,
281 ASYNC_EVENT_CMPL_EVENT_ID_PPS_TIMESTAMP,
282 ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT,
283 };
284
285 static struct workqueue_struct *bnxt_pf_wq;
286
287 static bool bnxt_vf_pciid(enum board_idx idx)
288 {
289 return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF ||
290 idx == NETXTREME_S_VF || idx == NETXTREME_C_VF_HV ||
291 idx == NETXTREME_E_VF_HV || idx == NETXTREME_E_P5_VF ||
292 idx == NETXTREME_E_P5_VF_HV);
293 }
294
295 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
296 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
297 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
298
299 #define BNXT_CP_DB_IRQ_DIS(db) \
300 writel(DB_CP_IRQ_DIS_FLAGS, db)
301
302 #define BNXT_DB_CQ(db, idx) \
303 writel(DB_CP_FLAGS | RING_CMP(idx), (db)->doorbell)
304
305 #define BNXT_DB_NQ_P5(db, idx) \
306 writeq((db)->db_key64 | DBR_TYPE_NQ | RING_CMP(idx), (db)->doorbell)
307
308 #define BNXT_DB_CQ_ARM(db, idx) \
309 writel(DB_CP_REARM_FLAGS | RING_CMP(idx), (db)->doorbell)
310
311 #define BNXT_DB_NQ_ARM_P5(db, idx) \
312 writeq((db)->db_key64 | DBR_TYPE_NQ_ARM | RING_CMP(idx), (db)->doorbell)
313
314 static void bnxt_db_nq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
315 {
316 if (bp->flags & BNXT_FLAG_CHIP_P5)
317 BNXT_DB_NQ_P5(db, idx);
318 else
319 BNXT_DB_CQ(db, idx);
320 }
321
322 static void bnxt_db_nq_arm(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
323 {
324 if (bp->flags & BNXT_FLAG_CHIP_P5)
325 BNXT_DB_NQ_ARM_P5(db, idx);
326 else
327 BNXT_DB_CQ_ARM(db, idx);
328 }
329
330 static void bnxt_db_cq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
331 {
332 if (bp->flags & BNXT_FLAG_CHIP_P5)
333 writeq(db->db_key64 | DBR_TYPE_CQ_ARMALL | RING_CMP(idx),
334 db->doorbell);
335 else
336 BNXT_DB_CQ(db, idx);
337 }
338
339 const u16 bnxt_lhint_arr[] = {
340 TX_BD_FLAGS_LHINT_512_AND_SMALLER,
341 TX_BD_FLAGS_LHINT_512_TO_1023,
342 TX_BD_FLAGS_LHINT_1024_TO_2047,
343 TX_BD_FLAGS_LHINT_1024_TO_2047,
344 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
345 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
346 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
347 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
348 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
349 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
350 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
351 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
352 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
353 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
354 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
355 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
356 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
357 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
358 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
359 };
360
361 static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb)
362 {
363 struct metadata_dst *md_dst = skb_metadata_dst(skb);
364
365 if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX)
366 return 0;
367
368 return md_dst->u.port_info.port_id;
369 }
370
371 static void bnxt_txr_db_kick(struct bnxt *bp, struct bnxt_tx_ring_info *txr,
372 u16 prod)
373 {
374 bnxt_db_write(bp, &txr->tx_db, prod);
375 txr->kick_pending = 0;
376 }
377
378 static bool bnxt_txr_netif_try_stop_queue(struct bnxt *bp,
379 struct bnxt_tx_ring_info *txr,
380 struct netdev_queue *txq)
381 {
382 netif_tx_stop_queue(txq);
383
384 /* netif_tx_stop_queue() must be done before checking
385 * tx index in bnxt_tx_avail() below, because in
386 * bnxt_tx_int(), we update tx index before checking for
387 * netif_tx_queue_stopped().
388 */
389 smp_mb();
390 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh) {
391 netif_tx_wake_queue(txq);
392 return false;
393 }
394
395 return true;
396 }
397
398 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
399 {
400 struct bnxt *bp = netdev_priv(dev);
401 struct tx_bd *txbd;
402 struct tx_bd_ext *txbd1;
403 struct netdev_queue *txq;
404 int i;
405 dma_addr_t mapping;
406 unsigned int length, pad = 0;
407 u32 len, free_size, vlan_tag_flags, cfa_action, flags;
408 u16 prod, last_frag;
409 struct pci_dev *pdev = bp->pdev;
410 struct bnxt_tx_ring_info *txr;
411 struct bnxt_sw_tx_bd *tx_buf;
412 __le32 lflags = 0;
413
414 i = skb_get_queue_mapping(skb);
415 if (unlikely(i >= bp->tx_nr_rings)) {
416 dev_kfree_skb_any(skb);
417 atomic_long_inc(&dev->tx_dropped);
418 return NETDEV_TX_OK;
419 }
420
421 txq = netdev_get_tx_queue(dev, i);
422 txr = &bp->tx_ring[bp->tx_ring_map[i]];
423 prod = txr->tx_prod;
424
425 free_size = bnxt_tx_avail(bp, txr);
426 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
427 /* We must have raced with NAPI cleanup */
428 if (net_ratelimit() && txr->kick_pending)
429 netif_warn(bp, tx_err, dev,
430 "bnxt: ring busy w/ flush pending!\n");
431 if (bnxt_txr_netif_try_stop_queue(bp, txr, txq))
432 return NETDEV_TX_BUSY;
433 }
434
435 length = skb->len;
436 len = skb_headlen(skb);
437 last_frag = skb_shinfo(skb)->nr_frags;
438
439 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
440
441 txbd->tx_bd_opaque = prod;
442
443 tx_buf = &txr->tx_buf_ring[prod];
444 tx_buf->skb = skb;
445 tx_buf->nr_frags = last_frag;
446
447 vlan_tag_flags = 0;
448 cfa_action = bnxt_xmit_get_cfa_action(skb);
449 if (skb_vlan_tag_present(skb)) {
450 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
451 skb_vlan_tag_get(skb);
452 /* Currently supports 8021Q, 8021AD vlan offloads
453 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
454 */
455 if (skb->vlan_proto == htons(ETH_P_8021Q))
456 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
457 }
458
459 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
460 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
461
462 if (ptp && ptp->tx_tstamp_en && !skb_is_gso(skb) &&
463 atomic_dec_if_positive(&ptp->tx_avail) >= 0) {
464 if (!bnxt_ptp_parse(skb, &ptp->tx_seqid,
465 &ptp->tx_hdr_off)) {
466 if (vlan_tag_flags)
467 ptp->tx_hdr_off += VLAN_HLEN;
468 lflags |= cpu_to_le32(TX_BD_FLAGS_STAMP);
469 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
470 } else {
471 atomic_inc(&bp->ptp_cfg->tx_avail);
472 }
473 }
474 }
475
476 if (unlikely(skb->no_fcs))
477 lflags |= cpu_to_le32(TX_BD_FLAGS_NO_CRC);
478
479 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh &&
480 !lflags) {
481 struct tx_push_buffer *tx_push_buf = txr->tx_push;
482 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
483 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
484 void __iomem *db = txr->tx_db.doorbell;
485 void *pdata = tx_push_buf->data;
486 u64 *end;
487 int j, push_len;
488
489 /* Set COAL_NOW to be ready quickly for the next push */
490 tx_push->tx_bd_len_flags_type =
491 cpu_to_le32((length << TX_BD_LEN_SHIFT) |
492 TX_BD_TYPE_LONG_TX_BD |
493 TX_BD_FLAGS_LHINT_512_AND_SMALLER |
494 TX_BD_FLAGS_COAL_NOW |
495 TX_BD_FLAGS_PACKET_END |
496 (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
497
498 if (skb->ip_summed == CHECKSUM_PARTIAL)
499 tx_push1->tx_bd_hsize_lflags =
500 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
501 else
502 tx_push1->tx_bd_hsize_lflags = 0;
503
504 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
505 tx_push1->tx_bd_cfa_action =
506 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
507
508 end = pdata + length;
509 end = PTR_ALIGN(end, 8) - 1;
510 *end = 0;
511
512 skb_copy_from_linear_data(skb, pdata, len);
513 pdata += len;
514 for (j = 0; j < last_frag; j++) {
515 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
516 void *fptr;
517
518 fptr = skb_frag_address_safe(frag);
519 if (!fptr)
520 goto normal_tx;
521
522 memcpy(pdata, fptr, skb_frag_size(frag));
523 pdata += skb_frag_size(frag);
524 }
525
526 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
527 txbd->tx_bd_haddr = txr->data_mapping;
528 prod = NEXT_TX(prod);
529 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
530 memcpy(txbd, tx_push1, sizeof(*txbd));
531 prod = NEXT_TX(prod);
532 tx_push->doorbell =
533 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
534 txr->tx_prod = prod;
535
536 tx_buf->is_push = 1;
537 netdev_tx_sent_queue(txq, skb->len);
538 wmb(); /* Sync is_push and byte queue before pushing data */
539
540 push_len = (length + sizeof(*tx_push) + 7) / 8;
541 if (push_len > 16) {
542 __iowrite64_copy(db, tx_push_buf, 16);
543 __iowrite32_copy(db + 4, tx_push_buf + 1,
544 (push_len - 16) << 1);
545 } else {
546 __iowrite64_copy(db, tx_push_buf, push_len);
547 }
548
549 goto tx_done;
550 }
551
552 normal_tx:
553 if (length < BNXT_MIN_PKT_SIZE) {
554 pad = BNXT_MIN_PKT_SIZE - length;
555 if (skb_pad(skb, pad))
556 /* SKB already freed. */
557 goto tx_kick_pending;
558 length = BNXT_MIN_PKT_SIZE;
559 }
560
561 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
562
563 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
564 goto tx_free;
565
566 dma_unmap_addr_set(tx_buf, mapping, mapping);
567 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
568 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
569
570 txbd->tx_bd_haddr = cpu_to_le64(mapping);
571
572 prod = NEXT_TX(prod);
573 txbd1 = (struct tx_bd_ext *)
574 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
575
576 txbd1->tx_bd_hsize_lflags = lflags;
577 if (skb_is_gso(skb)) {
578 u32 hdr_len;
579
580 if (skb->encapsulation)
581 hdr_len = skb_inner_network_offset(skb) +
582 skb_inner_network_header_len(skb) +
583 inner_tcp_hdrlen(skb);
584 else
585 hdr_len = skb_transport_offset(skb) +
586 tcp_hdrlen(skb);
587
588 txbd1->tx_bd_hsize_lflags |= cpu_to_le32(TX_BD_FLAGS_LSO |
589 TX_BD_FLAGS_T_IPID |
590 (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
591 length = skb_shinfo(skb)->gso_size;
592 txbd1->tx_bd_mss = cpu_to_le32(length);
593 length += hdr_len;
594 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
595 txbd1->tx_bd_hsize_lflags |=
596 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
597 txbd1->tx_bd_mss = 0;
598 }
599
600 length >>= 9;
601 if (unlikely(length >= ARRAY_SIZE(bnxt_lhint_arr))) {
602 dev_warn_ratelimited(&pdev->dev, "Dropped oversize %d bytes TX packet.\n",
603 skb->len);
604 i = 0;
605 goto tx_dma_error;
606 }
607 flags |= bnxt_lhint_arr[length];
608 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
609
610 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
611 txbd1->tx_bd_cfa_action =
612 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
613 for (i = 0; i < last_frag; i++) {
614 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
615
616 prod = NEXT_TX(prod);
617 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
618
619 len = skb_frag_size(frag);
620 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
621 DMA_TO_DEVICE);
622
623 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
624 goto tx_dma_error;
625
626 tx_buf = &txr->tx_buf_ring[prod];
627 dma_unmap_addr_set(tx_buf, mapping, mapping);
628
629 txbd->tx_bd_haddr = cpu_to_le64(mapping);
630
631 flags = len << TX_BD_LEN_SHIFT;
632 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
633 }
634
635 flags &= ~TX_BD_LEN;
636 txbd->tx_bd_len_flags_type =
637 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
638 TX_BD_FLAGS_PACKET_END);
639
640 netdev_tx_sent_queue(txq, skb->len);
641
642 skb_tx_timestamp(skb);
643
644 /* Sync BD data before updating doorbell */
645 wmb();
646
647 prod = NEXT_TX(prod);
648 txr->tx_prod = prod;
649
650 if (!netdev_xmit_more() || netif_xmit_stopped(txq))
651 bnxt_txr_db_kick(bp, txr, prod);
652 else
653 txr->kick_pending = 1;
654
655 tx_done:
656
657 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
658 if (netdev_xmit_more() && !tx_buf->is_push)
659 bnxt_txr_db_kick(bp, txr, prod);
660
661 bnxt_txr_netif_try_stop_queue(bp, txr, txq);
662 }
663 return NETDEV_TX_OK;
664
665 tx_dma_error:
666 if (BNXT_TX_PTP_IS_SET(lflags))
667 atomic_inc(&bp->ptp_cfg->tx_avail);
668
669 last_frag = i;
670
671 /* start back at beginning and unmap skb */
672 prod = txr->tx_prod;
673 tx_buf = &txr->tx_buf_ring[prod];
674 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
675 skb_headlen(skb), PCI_DMA_TODEVICE);
676 prod = NEXT_TX(prod);
677
678 /* unmap remaining mapped pages */
679 for (i = 0; i < last_frag; i++) {
680 prod = NEXT_TX(prod);
681 tx_buf = &txr->tx_buf_ring[prod];
682 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
683 skb_frag_size(&skb_shinfo(skb)->frags[i]),
684 PCI_DMA_TODEVICE);
685 }
686
687 tx_free:
688 dev_kfree_skb_any(skb);
689 tx_kick_pending:
690 if (txr->kick_pending)
691 bnxt_txr_db_kick(bp, txr, txr->tx_prod);
692 txr->tx_buf_ring[txr->tx_prod].skb = NULL;
693 atomic_long_inc(&dev->tx_dropped);
694 return NETDEV_TX_OK;
695 }
696
697 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
698 {
699 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
700 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index);
701 u16 cons = txr->tx_cons;
702 struct pci_dev *pdev = bp->pdev;
703 int i;
704 unsigned int tx_bytes = 0;
705
706 for (i = 0; i < nr_pkts; i++) {
707 struct bnxt_sw_tx_bd *tx_buf;
708 bool compl_deferred = false;
709 struct sk_buff *skb;
710 int j, last;
711
712 tx_buf = &txr->tx_buf_ring[cons];
713 cons = NEXT_TX(cons);
714 skb = tx_buf->skb;
715 tx_buf->skb = NULL;
716
717 if (tx_buf->is_push) {
718 tx_buf->is_push = 0;
719 goto next_tx_int;
720 }
721
722 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
723 skb_headlen(skb), PCI_DMA_TODEVICE);
724 last = tx_buf->nr_frags;
725
726 for (j = 0; j < last; j++) {
727 cons = NEXT_TX(cons);
728 tx_buf = &txr->tx_buf_ring[cons];
729 dma_unmap_page(
730 &pdev->dev,
731 dma_unmap_addr(tx_buf, mapping),
732 skb_frag_size(&skb_shinfo(skb)->frags[j]),
733 PCI_DMA_TODEVICE);
734 }
735 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
736 if (bp->flags & BNXT_FLAG_CHIP_P5) {
737 if (!bnxt_get_tx_ts_p5(bp, skb))
738 compl_deferred = true;
739 else
740 atomic_inc(&bp->ptp_cfg->tx_avail);
741 }
742 }
743
744 next_tx_int:
745 cons = NEXT_TX(cons);
746
747 tx_bytes += skb->len;
748 if (!compl_deferred)
749 dev_kfree_skb_any(skb);
750 }
751
752 netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
753 txr->tx_cons = cons;
754
755 /* Need to make the tx_cons update visible to bnxt_start_xmit()
756 * before checking for netif_tx_queue_stopped(). Without the
757 * memory barrier, there is a small possibility that bnxt_start_xmit()
758 * will miss it and cause the queue to be stopped forever.
759 */
760 smp_mb();
761
762 if (unlikely(netif_tx_queue_stopped(txq)) &&
763 bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
764 READ_ONCE(txr->dev_state) != BNXT_DEV_STATE_CLOSING)
765 netif_tx_wake_queue(txq);
766 }
767
768 static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping,
769 struct bnxt_rx_ring_info *rxr,
770 gfp_t gfp)
771 {
772 struct device *dev = &bp->pdev->dev;
773 struct page *page;
774
775 page = page_pool_dev_alloc_pages(rxr->page_pool);
776 if (!page)
777 return NULL;
778
779 *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir,
780 DMA_ATTR_WEAK_ORDERING);
781 if (dma_mapping_error(dev, *mapping)) {
782 page_pool_recycle_direct(rxr->page_pool, page);
783 return NULL;
784 }
785 *mapping += bp->rx_dma_offset;
786 return page;
787 }
788
789 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
790 gfp_t gfp)
791 {
792 u8 *data;
793 struct pci_dev *pdev = bp->pdev;
794
795 data = kmalloc(bp->rx_buf_size, gfp);
796 if (!data)
797 return NULL;
798
799 *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset,
800 bp->rx_buf_use_size, bp->rx_dir,
801 DMA_ATTR_WEAK_ORDERING);
802
803 if (dma_mapping_error(&pdev->dev, *mapping)) {
804 kfree(data);
805 data = NULL;
806 }
807 return data;
808 }
809
810 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
811 u16 prod, gfp_t gfp)
812 {
813 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
814 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
815 dma_addr_t mapping;
816
817 if (BNXT_RX_PAGE_MODE(bp)) {
818 struct page *page =
819 __bnxt_alloc_rx_page(bp, &mapping, rxr, gfp);
820
821 if (!page)
822 return -ENOMEM;
823
824 rx_buf->data = page;
825 rx_buf->data_ptr = page_address(page) + bp->rx_offset;
826 } else {
827 u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
828
829 if (!data)
830 return -ENOMEM;
831
832 rx_buf->data = data;
833 rx_buf->data_ptr = data + bp->rx_offset;
834 }
835 rx_buf->mapping = mapping;
836
837 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
838 return 0;
839 }
840
841 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data)
842 {
843 u16 prod = rxr->rx_prod;
844 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
845 struct rx_bd *cons_bd, *prod_bd;
846
847 prod_rx_buf = &rxr->rx_buf_ring[prod];
848 cons_rx_buf = &rxr->rx_buf_ring[cons];
849
850 prod_rx_buf->data = data;
851 prod_rx_buf->data_ptr = cons_rx_buf->data_ptr;
852
853 prod_rx_buf->mapping = cons_rx_buf->mapping;
854
855 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
856 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
857
858 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
859 }
860
861 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
862 {
863 u16 next, max = rxr->rx_agg_bmap_size;
864
865 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
866 if (next >= max)
867 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
868 return next;
869 }
870
871 static inline int bnxt_alloc_rx_page(struct bnxt *bp,
872 struct bnxt_rx_ring_info *rxr,
873 u16 prod, gfp_t gfp)
874 {
875 struct rx_bd *rxbd =
876 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
877 struct bnxt_sw_rx_agg_bd *rx_agg_buf;
878 struct pci_dev *pdev = bp->pdev;
879 struct page *page;
880 dma_addr_t mapping;
881 u16 sw_prod = rxr->rx_sw_agg_prod;
882 unsigned int offset = 0;
883
884 if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
885 page = rxr->rx_page;
886 if (!page) {
887 page = alloc_page(gfp);
888 if (!page)
889 return -ENOMEM;
890 rxr->rx_page = page;
891 rxr->rx_page_offset = 0;
892 }
893 offset = rxr->rx_page_offset;
894 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
895 if (rxr->rx_page_offset == PAGE_SIZE)
896 rxr->rx_page = NULL;
897 else
898 get_page(page);
899 } else {
900 page = alloc_page(gfp);
901 if (!page)
902 return -ENOMEM;
903 }
904
905 mapping = dma_map_page_attrs(&pdev->dev, page, offset,
906 BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE,
907 DMA_ATTR_WEAK_ORDERING);
908 if (dma_mapping_error(&pdev->dev, mapping)) {
909 __free_page(page);
910 return -EIO;
911 }
912
913 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
914 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
915
916 __set_bit(sw_prod, rxr->rx_agg_bmap);
917 rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
918 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
919
920 rx_agg_buf->page = page;
921 rx_agg_buf->offset = offset;
922 rx_agg_buf->mapping = mapping;
923 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
924 rxbd->rx_bd_opaque = sw_prod;
925 return 0;
926 }
927
928 static struct rx_agg_cmp *bnxt_get_agg(struct bnxt *bp,
929 struct bnxt_cp_ring_info *cpr,
930 u16 cp_cons, u16 curr)
931 {
932 struct rx_agg_cmp *agg;
933
934 cp_cons = RING_CMP(ADV_RAW_CMP(cp_cons, curr));
935 agg = (struct rx_agg_cmp *)
936 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
937 return agg;
938 }
939
940 static struct rx_agg_cmp *bnxt_get_tpa_agg_p5(struct bnxt *bp,
941 struct bnxt_rx_ring_info *rxr,
942 u16 agg_id, u16 curr)
943 {
944 struct bnxt_tpa_info *tpa_info = &rxr->rx_tpa[agg_id];
945
946 return &tpa_info->agg_arr[curr];
947 }
948
949 static void bnxt_reuse_rx_agg_bufs(struct bnxt_cp_ring_info *cpr, u16 idx,
950 u16 start, u32 agg_bufs, bool tpa)
951 {
952 struct bnxt_napi *bnapi = cpr->bnapi;
953 struct bnxt *bp = bnapi->bp;
954 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
955 u16 prod = rxr->rx_agg_prod;
956 u16 sw_prod = rxr->rx_sw_agg_prod;
957 bool p5_tpa = false;
958 u32 i;
959
960 if ((bp->flags & BNXT_FLAG_CHIP_P5) && tpa)
961 p5_tpa = true;
962
963 for (i = 0; i < agg_bufs; i++) {
964 u16 cons;
965 struct rx_agg_cmp *agg;
966 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
967 struct rx_bd *prod_bd;
968 struct page *page;
969
970 if (p5_tpa)
971 agg = bnxt_get_tpa_agg_p5(bp, rxr, idx, start + i);
972 else
973 agg = bnxt_get_agg(bp, cpr, idx, start + i);
974 cons = agg->rx_agg_cmp_opaque;
975 __clear_bit(cons, rxr->rx_agg_bmap);
976
977 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
978 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
979
980 __set_bit(sw_prod, rxr->rx_agg_bmap);
981 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
982 cons_rx_buf = &rxr->rx_agg_ring[cons];
983
984 /* It is possible for sw_prod to be equal to cons, so
985 * set cons_rx_buf->page to NULL first.
986 */
987 page = cons_rx_buf->page;
988 cons_rx_buf->page = NULL;
989 prod_rx_buf->page = page;
990 prod_rx_buf->offset = cons_rx_buf->offset;
991
992 prod_rx_buf->mapping = cons_rx_buf->mapping;
993
994 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
995
996 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
997 prod_bd->rx_bd_opaque = sw_prod;
998
999 prod = NEXT_RX_AGG(prod);
1000 sw_prod = NEXT_RX_AGG(sw_prod);
1001 }
1002 rxr->rx_agg_prod = prod;
1003 rxr->rx_sw_agg_prod = sw_prod;
1004 }
1005
1006 static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp,
1007 struct bnxt_rx_ring_info *rxr,
1008 u16 cons, void *data, u8 *data_ptr,
1009 dma_addr_t dma_addr,
1010 unsigned int offset_and_len)
1011 {
1012 unsigned int payload = offset_and_len >> 16;
1013 unsigned int len = offset_and_len & 0xffff;
1014 skb_frag_t *frag;
1015 struct page *page = data;
1016 u16 prod = rxr->rx_prod;
1017 struct sk_buff *skb;
1018 int off, err;
1019
1020 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
1021 if (unlikely(err)) {
1022 bnxt_reuse_rx_data(rxr, cons, data);
1023 return NULL;
1024 }
1025 dma_addr -= bp->rx_dma_offset;
1026 dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir,
1027 DMA_ATTR_WEAK_ORDERING);
1028 page_pool_release_page(rxr->page_pool, page);
1029
1030 if (unlikely(!payload))
1031 payload = eth_get_headlen(bp->dev, data_ptr, len);
1032
1033 skb = napi_alloc_skb(&rxr->bnapi->napi, payload);
1034 if (!skb) {
1035 __free_page(page);
1036 return NULL;
1037 }
1038
1039 off = (void *)data_ptr - page_address(page);
1040 skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE);
1041 memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN,
1042 payload + NET_IP_ALIGN);
1043
1044 frag = &skb_shinfo(skb)->frags[0];
1045 skb_frag_size_sub(frag, payload);
1046 skb_frag_off_add(frag, payload);
1047 skb->data_len -= payload;
1048 skb->tail += payload;
1049
1050 return skb;
1051 }
1052
1053 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
1054 struct bnxt_rx_ring_info *rxr, u16 cons,
1055 void *data, u8 *data_ptr,
1056 dma_addr_t dma_addr,
1057 unsigned int offset_and_len)
1058 {
1059 u16 prod = rxr->rx_prod;
1060 struct sk_buff *skb;
1061 int err;
1062
1063 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
1064 if (unlikely(err)) {
1065 bnxt_reuse_rx_data(rxr, cons, data);
1066 return NULL;
1067 }
1068
1069 skb = build_skb(data, 0);
1070 dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
1071 bp->rx_dir, DMA_ATTR_WEAK_ORDERING);
1072 if (!skb) {
1073 kfree(data);
1074 return NULL;
1075 }
1076
1077 skb_reserve(skb, bp->rx_offset);
1078 skb_put(skb, offset_and_len & 0xffff);
1079 return skb;
1080 }
1081
1082 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp,
1083 struct bnxt_cp_ring_info *cpr,
1084 struct sk_buff *skb, u16 idx,
1085 u32 agg_bufs, bool tpa)
1086 {
1087 struct bnxt_napi *bnapi = cpr->bnapi;
1088 struct pci_dev *pdev = bp->pdev;
1089 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1090 u16 prod = rxr->rx_agg_prod;
1091 bool p5_tpa = false;
1092 u32 i;
1093
1094 if ((bp->flags & BNXT_FLAG_CHIP_P5) && tpa)
1095 p5_tpa = true;
1096
1097 for (i = 0; i < agg_bufs; i++) {
1098 u16 cons, frag_len;
1099 struct rx_agg_cmp *agg;
1100 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
1101 struct page *page;
1102 dma_addr_t mapping;
1103
1104 if (p5_tpa)
1105 agg = bnxt_get_tpa_agg_p5(bp, rxr, idx, i);
1106 else
1107 agg = bnxt_get_agg(bp, cpr, idx, i);
1108 cons = agg->rx_agg_cmp_opaque;
1109 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
1110 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
1111
1112 cons_rx_buf = &rxr->rx_agg_ring[cons];
1113 skb_fill_page_desc(skb, i, cons_rx_buf->page,
1114 cons_rx_buf->offset, frag_len);
1115 __clear_bit(cons, rxr->rx_agg_bmap);
1116
1117 /* It is possible for bnxt_alloc_rx_page() to allocate
1118 * a sw_prod index that equals the cons index, so we
1119 * need to clear the cons entry now.
1120 */
1121 mapping = cons_rx_buf->mapping;
1122 page = cons_rx_buf->page;
1123 cons_rx_buf->page = NULL;
1124
1125 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
1126 struct skb_shared_info *shinfo;
1127 unsigned int nr_frags;
1128
1129 shinfo = skb_shinfo(skb);
1130 nr_frags = --shinfo->nr_frags;
1131 __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
1132
1133 dev_kfree_skb(skb);
1134
1135 cons_rx_buf->page = page;
1136
1137 /* Update prod since possibly some pages have been
1138 * allocated already.
1139 */
1140 rxr->rx_agg_prod = prod;
1141 bnxt_reuse_rx_agg_bufs(cpr, idx, i, agg_bufs - i, tpa);
1142 return NULL;
1143 }
1144
1145 dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
1146 PCI_DMA_FROMDEVICE,
1147 DMA_ATTR_WEAK_ORDERING);
1148
1149 skb->data_len += frag_len;
1150 skb->len += frag_len;
1151 skb->truesize += PAGE_SIZE;
1152
1153 prod = NEXT_RX_AGG(prod);
1154 }
1155 rxr->rx_agg_prod = prod;
1156 return skb;
1157 }
1158
1159 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1160 u8 agg_bufs, u32 *raw_cons)
1161 {
1162 u16 last;
1163 struct rx_agg_cmp *agg;
1164
1165 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
1166 last = RING_CMP(*raw_cons);
1167 agg = (struct rx_agg_cmp *)
1168 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
1169 return RX_AGG_CMP_VALID(agg, *raw_cons);
1170 }
1171
1172 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
1173 unsigned int len,
1174 dma_addr_t mapping)
1175 {
1176 struct bnxt *bp = bnapi->bp;
1177 struct pci_dev *pdev = bp->pdev;
1178 struct sk_buff *skb;
1179
1180 skb = napi_alloc_skb(&bnapi->napi, len);
1181 if (!skb)
1182 return NULL;
1183
1184 dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh,
1185 bp->rx_dir);
1186
1187 memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN,
1188 len + NET_IP_ALIGN);
1189
1190 dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh,
1191 bp->rx_dir);
1192
1193 skb_put(skb, len);
1194 return skb;
1195 }
1196
1197 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1198 u32 *raw_cons, void *cmp)
1199 {
1200 struct rx_cmp *rxcmp = cmp;
1201 u32 tmp_raw_cons = *raw_cons;
1202 u8 cmp_type, agg_bufs = 0;
1203
1204 cmp_type = RX_CMP_TYPE(rxcmp);
1205
1206 if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1207 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
1208 RX_CMP_AGG_BUFS) >>
1209 RX_CMP_AGG_BUFS_SHIFT;
1210 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1211 struct rx_tpa_end_cmp *tpa_end = cmp;
1212
1213 if (bp->flags & BNXT_FLAG_CHIP_P5)
1214 return 0;
1215
1216 agg_bufs = TPA_END_AGG_BUFS(tpa_end);
1217 }
1218
1219 if (agg_bufs) {
1220 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1221 return -EBUSY;
1222 }
1223 *raw_cons = tmp_raw_cons;
1224 return 0;
1225 }
1226
1227 static void bnxt_queue_fw_reset_work(struct bnxt *bp, unsigned long delay)
1228 {
1229 if (!(test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)))
1230 return;
1231
1232 if (BNXT_PF(bp))
1233 queue_delayed_work(bnxt_pf_wq, &bp->fw_reset_task, delay);
1234 else
1235 schedule_delayed_work(&bp->fw_reset_task, delay);
1236 }
1237
1238 static void bnxt_queue_sp_work(struct bnxt *bp)
1239 {
1240 if (BNXT_PF(bp))
1241 queue_work(bnxt_pf_wq, &bp->sp_task);
1242 else
1243 schedule_work(&bp->sp_task);
1244 }
1245
1246 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
1247 {
1248 if (!rxr->bnapi->in_reset) {
1249 rxr->bnapi->in_reset = true;
1250 if (bp->flags & BNXT_FLAG_CHIP_P5)
1251 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
1252 else
1253 set_bit(BNXT_RST_RING_SP_EVENT, &bp->sp_event);
1254 bnxt_queue_sp_work(bp);
1255 }
1256 rxr->rx_next_cons = 0xffff;
1257 }
1258
1259 static u16 bnxt_alloc_agg_idx(struct bnxt_rx_ring_info *rxr, u16 agg_id)
1260 {
1261 struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map;
1262 u16 idx = agg_id & MAX_TPA_P5_MASK;
1263
1264 if (test_bit(idx, map->agg_idx_bmap))
1265 idx = find_first_zero_bit(map->agg_idx_bmap,
1266 BNXT_AGG_IDX_BMAP_SIZE);
1267 __set_bit(idx, map->agg_idx_bmap);
1268 map->agg_id_tbl[agg_id] = idx;
1269 return idx;
1270 }
1271
1272 static void bnxt_free_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
1273 {
1274 struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map;
1275
1276 __clear_bit(idx, map->agg_idx_bmap);
1277 }
1278
1279 static u16 bnxt_lookup_agg_idx(struct bnxt_rx_ring_info *rxr, u16 agg_id)
1280 {
1281 struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map;
1282
1283 return map->agg_id_tbl[agg_id];
1284 }
1285
1286 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1287 struct rx_tpa_start_cmp *tpa_start,
1288 struct rx_tpa_start_cmp_ext *tpa_start1)
1289 {
1290 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
1291 struct bnxt_tpa_info *tpa_info;
1292 u16 cons, prod, agg_id;
1293 struct rx_bd *prod_bd;
1294 dma_addr_t mapping;
1295
1296 if (bp->flags & BNXT_FLAG_CHIP_P5) {
1297 agg_id = TPA_START_AGG_ID_P5(tpa_start);
1298 agg_id = bnxt_alloc_agg_idx(rxr, agg_id);
1299 } else {
1300 agg_id = TPA_START_AGG_ID(tpa_start);
1301 }
1302 cons = tpa_start->rx_tpa_start_cmp_opaque;
1303 prod = rxr->rx_prod;
1304 cons_rx_buf = &rxr->rx_buf_ring[cons];
1305 prod_rx_buf = &rxr->rx_buf_ring[prod];
1306 tpa_info = &rxr->rx_tpa[agg_id];
1307
1308 if (unlikely(cons != rxr->rx_next_cons ||
1309 TPA_START_ERROR(tpa_start))) {
1310 netdev_warn(bp->dev, "TPA cons %x, expected cons %x, error code %x\n",
1311 cons, rxr->rx_next_cons,
1312 TPA_START_ERROR_CODE(tpa_start1));
1313 bnxt_sched_reset(bp, rxr);
1314 return;
1315 }
1316 /* Store cfa_code in tpa_info to use in tpa_end
1317 * completion processing.
1318 */
1319 tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1);
1320 prod_rx_buf->data = tpa_info->data;
1321 prod_rx_buf->data_ptr = tpa_info->data_ptr;
1322
1323 mapping = tpa_info->mapping;
1324 prod_rx_buf->mapping = mapping;
1325
1326 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1327
1328 prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
1329
1330 tpa_info->data = cons_rx_buf->data;
1331 tpa_info->data_ptr = cons_rx_buf->data_ptr;
1332 cons_rx_buf->data = NULL;
1333 tpa_info->mapping = cons_rx_buf->mapping;
1334
1335 tpa_info->len =
1336 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
1337 RX_TPA_START_CMP_LEN_SHIFT;
1338 if (likely(TPA_START_HASH_VALID(tpa_start))) {
1339 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
1340
1341 tpa_info->hash_type = PKT_HASH_TYPE_L4;
1342 tpa_info->gso_type = SKB_GSO_TCPV4;
1343 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1344 if (hash_type == 3 || TPA_START_IS_IPV6(tpa_start1))
1345 tpa_info->gso_type = SKB_GSO_TCPV6;
1346 tpa_info->rss_hash =
1347 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
1348 } else {
1349 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
1350 tpa_info->gso_type = 0;
1351 netif_warn(bp, rx_err, bp->dev, "TPA packet without valid hash\n");
1352 }
1353 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
1354 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
1355 tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
1356 tpa_info->agg_count = 0;
1357
1358 rxr->rx_prod = NEXT_RX(prod);
1359 cons = NEXT_RX(cons);
1360 rxr->rx_next_cons = NEXT_RX(cons);
1361 cons_rx_buf = &rxr->rx_buf_ring[cons];
1362
1363 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
1364 rxr->rx_prod = NEXT_RX(rxr->rx_prod);
1365 cons_rx_buf->data = NULL;
1366 }
1367
1368 static void bnxt_abort_tpa(struct bnxt_cp_ring_info *cpr, u16 idx, u32 agg_bufs)
1369 {
1370 if (agg_bufs)
1371 bnxt_reuse_rx_agg_bufs(cpr, idx, 0, agg_bufs, true);
1372 }
1373
1374 #ifdef CONFIG_INET
1375 static void bnxt_gro_tunnel(struct sk_buff *skb, __be16 ip_proto)
1376 {
1377 struct udphdr *uh = NULL;
1378
1379 if (ip_proto == htons(ETH_P_IP)) {
1380 struct iphdr *iph = (struct iphdr *)skb->data;
1381
1382 if (iph->protocol == IPPROTO_UDP)
1383 uh = (struct udphdr *)(iph + 1);
1384 } else {
1385 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1386
1387 if (iph->nexthdr == IPPROTO_UDP)
1388 uh = (struct udphdr *)(iph + 1);
1389 }
1390 if (uh) {
1391 if (uh->check)
1392 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL_CSUM;
1393 else
1394 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1395 }
1396 }
1397 #endif
1398
1399 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info,
1400 int payload_off, int tcp_ts,
1401 struct sk_buff *skb)
1402 {
1403 #ifdef CONFIG_INET
1404 struct tcphdr *th;
1405 int len, nw_off;
1406 u16 outer_ip_off, inner_ip_off, inner_mac_off;
1407 u32 hdr_info = tpa_info->hdr_info;
1408 bool loopback = false;
1409
1410 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1411 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1412 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1413
1414 /* If the packet is an internal loopback packet, the offsets will
1415 * have an extra 4 bytes.
1416 */
1417 if (inner_mac_off == 4) {
1418 loopback = true;
1419 } else if (inner_mac_off > 4) {
1420 __be16 proto = *((__be16 *)(skb->data + inner_ip_off -
1421 ETH_HLEN - 2));
1422
1423 /* We only support inner iPv4/ipv6. If we don't see the
1424 * correct protocol ID, it must be a loopback packet where
1425 * the offsets are off by 4.
1426 */
1427 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6))
1428 loopback = true;
1429 }
1430 if (loopback) {
1431 /* internal loopback packet, subtract all offsets by 4 */
1432 inner_ip_off -= 4;
1433 inner_mac_off -= 4;
1434 outer_ip_off -= 4;
1435 }
1436
1437 nw_off = inner_ip_off - ETH_HLEN;
1438 skb_set_network_header(skb, nw_off);
1439 if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) {
1440 struct ipv6hdr *iph = ipv6_hdr(skb);
1441
1442 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1443 len = skb->len - skb_transport_offset(skb);
1444 th = tcp_hdr(skb);
1445 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1446 } else {
1447 struct iphdr *iph = ip_hdr(skb);
1448
1449 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1450 len = skb->len - skb_transport_offset(skb);
1451 th = tcp_hdr(skb);
1452 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1453 }
1454
1455 if (inner_mac_off) { /* tunnel */
1456 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1457 ETH_HLEN - 2));
1458
1459 bnxt_gro_tunnel(skb, proto);
1460 }
1461 #endif
1462 return skb;
1463 }
1464
1465 static struct sk_buff *bnxt_gro_func_5750x(struct bnxt_tpa_info *tpa_info,
1466 int payload_off, int tcp_ts,
1467 struct sk_buff *skb)
1468 {
1469 #ifdef CONFIG_INET
1470 u16 outer_ip_off, inner_ip_off, inner_mac_off;
1471 u32 hdr_info = tpa_info->hdr_info;
1472 int iphdr_len, nw_off;
1473
1474 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1475 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1476 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1477
1478 nw_off = inner_ip_off - ETH_HLEN;
1479 skb_set_network_header(skb, nw_off);
1480 iphdr_len = (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) ?
1481 sizeof(struct ipv6hdr) : sizeof(struct iphdr);
1482 skb_set_transport_header(skb, nw_off + iphdr_len);
1483
1484 if (inner_mac_off) { /* tunnel */
1485 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1486 ETH_HLEN - 2));
1487
1488 bnxt_gro_tunnel(skb, proto);
1489 }
1490 #endif
1491 return skb;
1492 }
1493
1494 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
1495 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1496
1497 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info,
1498 int payload_off, int tcp_ts,
1499 struct sk_buff *skb)
1500 {
1501 #ifdef CONFIG_INET
1502 struct tcphdr *th;
1503 int len, nw_off, tcp_opt_len = 0;
1504
1505 if (tcp_ts)
1506 tcp_opt_len = 12;
1507
1508 if (tpa_info->gso_type == SKB_GSO_TCPV4) {
1509 struct iphdr *iph;
1510
1511 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
1512 ETH_HLEN;
1513 skb_set_network_header(skb, nw_off);
1514 iph = ip_hdr(skb);
1515 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1516 len = skb->len - skb_transport_offset(skb);
1517 th = tcp_hdr(skb);
1518 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1519 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
1520 struct ipv6hdr *iph;
1521
1522 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
1523 ETH_HLEN;
1524 skb_set_network_header(skb, nw_off);
1525 iph = ipv6_hdr(skb);
1526 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1527 len = skb->len - skb_transport_offset(skb);
1528 th = tcp_hdr(skb);
1529 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1530 } else {
1531 dev_kfree_skb_any(skb);
1532 return NULL;
1533 }
1534
1535 if (nw_off) /* tunnel */
1536 bnxt_gro_tunnel(skb, skb->protocol);
1537 #endif
1538 return skb;
1539 }
1540
1541 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp,
1542 struct bnxt_tpa_info *tpa_info,
1543 struct rx_tpa_end_cmp *tpa_end,
1544 struct rx_tpa_end_cmp_ext *tpa_end1,
1545 struct sk_buff *skb)
1546 {
1547 #ifdef CONFIG_INET
1548 int payload_off;
1549 u16 segs;
1550
1551 segs = TPA_END_TPA_SEGS(tpa_end);
1552 if (segs == 1)
1553 return skb;
1554
1555 NAPI_GRO_CB(skb)->count = segs;
1556 skb_shinfo(skb)->gso_size =
1557 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1558 skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1559 if (bp->flags & BNXT_FLAG_CHIP_P5)
1560 payload_off = TPA_END_PAYLOAD_OFF_P5(tpa_end1);
1561 else
1562 payload_off = TPA_END_PAYLOAD_OFF(tpa_end);
1563 skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
1564 if (likely(skb))
1565 tcp_gro_complete(skb);
1566 #endif
1567 return skb;
1568 }
1569
1570 /* Given the cfa_code of a received packet determine which
1571 * netdev (vf-rep or PF) the packet is destined to.
1572 */
1573 static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code)
1574 {
1575 struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code);
1576
1577 /* if vf-rep dev is NULL, the must belongs to the PF */
1578 return dev ? dev : bp->dev;
1579 }
1580
1581 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
1582 struct bnxt_cp_ring_info *cpr,
1583 u32 *raw_cons,
1584 struct rx_tpa_end_cmp *tpa_end,
1585 struct rx_tpa_end_cmp_ext *tpa_end1,
1586 u8 *event)
1587 {
1588 struct bnxt_napi *bnapi = cpr->bnapi;
1589 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1590 u8 *data_ptr, agg_bufs;
1591 unsigned int len;
1592 struct bnxt_tpa_info *tpa_info;
1593 dma_addr_t mapping;
1594 struct sk_buff *skb;
1595 u16 idx = 0, agg_id;
1596 void *data;
1597 bool gro;
1598
1599 if (unlikely(bnapi->in_reset)) {
1600 int rc = bnxt_discard_rx(bp, cpr, raw_cons, tpa_end);
1601
1602 if (rc < 0)
1603 return ERR_PTR(-EBUSY);
1604 return NULL;
1605 }
1606
1607 if (bp->flags & BNXT_FLAG_CHIP_P5) {
1608 agg_id = TPA_END_AGG_ID_P5(tpa_end);
1609 agg_id = bnxt_lookup_agg_idx(rxr, agg_id);
1610 agg_bufs = TPA_END_AGG_BUFS_P5(tpa_end1);
1611 tpa_info = &rxr->rx_tpa[agg_id];
1612 if (unlikely(agg_bufs != tpa_info->agg_count)) {
1613 netdev_warn(bp->dev, "TPA end agg_buf %d != expected agg_bufs %d\n",
1614 agg_bufs, tpa_info->agg_count);
1615 agg_bufs = tpa_info->agg_count;
1616 }
1617 tpa_info->agg_count = 0;
1618 *event |= BNXT_AGG_EVENT;
1619 bnxt_free_agg_idx(rxr, agg_id);
1620 idx = agg_id;
1621 gro = !!(bp->flags & BNXT_FLAG_GRO);
1622 } else {
1623 agg_id = TPA_END_AGG_ID(tpa_end);
1624 agg_bufs = TPA_END_AGG_BUFS(tpa_end);
1625 tpa_info = &rxr->rx_tpa[agg_id];
1626 idx = RING_CMP(*raw_cons);
1627 if (agg_bufs) {
1628 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1629 return ERR_PTR(-EBUSY);
1630
1631 *event |= BNXT_AGG_EVENT;
1632 idx = NEXT_CMP(idx);
1633 }
1634 gro = !!TPA_END_GRO(tpa_end);
1635 }
1636 data = tpa_info->data;
1637 data_ptr = tpa_info->data_ptr;
1638 prefetch(data_ptr);
1639 len = tpa_info->len;
1640 mapping = tpa_info->mapping;
1641
1642 if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) {
1643 bnxt_abort_tpa(cpr, idx, agg_bufs);
1644 if (agg_bufs > MAX_SKB_FRAGS)
1645 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1646 agg_bufs, (int)MAX_SKB_FRAGS);
1647 return NULL;
1648 }
1649
1650 if (len <= bp->rx_copy_thresh) {
1651 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping);
1652 if (!skb) {
1653 bnxt_abort_tpa(cpr, idx, agg_bufs);
1654 return NULL;
1655 }
1656 } else {
1657 u8 *new_data;
1658 dma_addr_t new_mapping;
1659
1660 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1661 if (!new_data) {
1662 bnxt_abort_tpa(cpr, idx, agg_bufs);
1663 return NULL;
1664 }
1665
1666 tpa_info->data = new_data;
1667 tpa_info->data_ptr = new_data + bp->rx_offset;
1668 tpa_info->mapping = new_mapping;
1669
1670 skb = build_skb(data, 0);
1671 dma_unmap_single_attrs(&bp->pdev->dev, mapping,
1672 bp->rx_buf_use_size, bp->rx_dir,
1673 DMA_ATTR_WEAK_ORDERING);
1674
1675 if (!skb) {
1676 kfree(data);
1677 bnxt_abort_tpa(cpr, idx, agg_bufs);
1678 return NULL;
1679 }
1680 skb_reserve(skb, bp->rx_offset);
1681 skb_put(skb, len);
1682 }
1683
1684 if (agg_bufs) {
1685 skb = bnxt_rx_pages(bp, cpr, skb, idx, agg_bufs, true);
1686 if (!skb) {
1687 /* Page reuse already handled by bnxt_rx_pages(). */
1688 return NULL;
1689 }
1690 }
1691
1692 skb->protocol =
1693 eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code));
1694
1695 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1696 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1697
1698 if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1699 (skb->dev->features & BNXT_HW_FEATURE_VLAN_ALL_RX)) {
1700 __be16 vlan_proto = htons(tpa_info->metadata >>
1701 RX_CMP_FLAGS2_METADATA_TPID_SFT);
1702 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1703
1704 if (eth_type_vlan(vlan_proto)) {
1705 __vlan_hwaccel_put_tag(skb, vlan_proto, vtag);
1706 } else {
1707 dev_kfree_skb(skb);
1708 return NULL;
1709 }
1710 }
1711
1712 skb_checksum_none_assert(skb);
1713 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1714 skb->ip_summed = CHECKSUM_UNNECESSARY;
1715 skb->csum_level =
1716 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1717 }
1718
1719 if (gro)
1720 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb);
1721
1722 return skb;
1723 }
1724
1725 static void bnxt_tpa_agg(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1726 struct rx_agg_cmp *rx_agg)
1727 {
1728 u16 agg_id = TPA_AGG_AGG_ID(rx_agg);
1729 struct bnxt_tpa_info *tpa_info;
1730
1731 agg_id = bnxt_lookup_agg_idx(rxr, agg_id);
1732 tpa_info = &rxr->rx_tpa[agg_id];
1733 BUG_ON(tpa_info->agg_count >= MAX_SKB_FRAGS);
1734 tpa_info->agg_arr[tpa_info->agg_count++] = *rx_agg;
1735 }
1736
1737 static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi,
1738 struct sk_buff *skb)
1739 {
1740 if (skb->dev != bp->dev) {
1741 /* this packet belongs to a vf-rep */
1742 bnxt_vf_rep_rx(bp, skb);
1743 return;
1744 }
1745 skb_record_rx_queue(skb, bnapi->index);
1746 napi_gro_receive(&bnapi->napi, skb);
1747 }
1748
1749 /* returns the following:
1750 * 1 - 1 packet successfully received
1751 * 0 - successful TPA_START, packet not completed yet
1752 * -EBUSY - completion ring does not have all the agg buffers yet
1753 * -ENOMEM - packet aborted due to out of memory
1754 * -EIO - packet aborted due to hw error indicated in BD
1755 */
1756 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1757 u32 *raw_cons, u8 *event)
1758 {
1759 struct bnxt_napi *bnapi = cpr->bnapi;
1760 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1761 struct net_device *dev = bp->dev;
1762 struct rx_cmp *rxcmp;
1763 struct rx_cmp_ext *rxcmp1;
1764 u32 tmp_raw_cons = *raw_cons;
1765 u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1766 struct bnxt_sw_rx_bd *rx_buf;
1767 unsigned int len;
1768 u8 *data_ptr, agg_bufs, cmp_type;
1769 dma_addr_t dma_addr;
1770 struct sk_buff *skb;
1771 u32 flags, misc;
1772 void *data;
1773 int rc = 0;
1774
1775 rxcmp = (struct rx_cmp *)
1776 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1777
1778 cmp_type = RX_CMP_TYPE(rxcmp);
1779
1780 if (cmp_type == CMP_TYPE_RX_TPA_AGG_CMP) {
1781 bnxt_tpa_agg(bp, rxr, (struct rx_agg_cmp *)rxcmp);
1782 goto next_rx_no_prod_no_len;
1783 }
1784
1785 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1786 cp_cons = RING_CMP(tmp_raw_cons);
1787 rxcmp1 = (struct rx_cmp_ext *)
1788 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1789
1790 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1791 return -EBUSY;
1792
1793 /* The valid test of the entry must be done first before
1794 * reading any further.
1795 */
1796 dma_rmb();
1797 prod = rxr->rx_prod;
1798
1799 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1800 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1801 (struct rx_tpa_start_cmp_ext *)rxcmp1);
1802
1803 *event |= BNXT_RX_EVENT;
1804 goto next_rx_no_prod_no_len;
1805
1806 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1807 skb = bnxt_tpa_end(bp, cpr, &tmp_raw_cons,
1808 (struct rx_tpa_end_cmp *)rxcmp,
1809 (struct rx_tpa_end_cmp_ext *)rxcmp1, event);
1810
1811 if (IS_ERR(skb))
1812 return -EBUSY;
1813
1814 rc = -ENOMEM;
1815 if (likely(skb)) {
1816 bnxt_deliver_skb(bp, bnapi, skb);
1817 rc = 1;
1818 }
1819 *event |= BNXT_RX_EVENT;
1820 goto next_rx_no_prod_no_len;
1821 }
1822
1823 cons = rxcmp->rx_cmp_opaque;
1824 if (unlikely(cons != rxr->rx_next_cons)) {
1825 int rc1 = bnxt_discard_rx(bp, cpr, &tmp_raw_cons, rxcmp);
1826
1827 /* 0xffff is forced error, don't print it */
1828 if (rxr->rx_next_cons != 0xffff)
1829 netdev_warn(bp->dev, "RX cons %x != expected cons %x\n",
1830 cons, rxr->rx_next_cons);
1831 bnxt_sched_reset(bp, rxr);
1832 if (rc1)
1833 return rc1;
1834 goto next_rx_no_prod_no_len;
1835 }
1836 rx_buf = &rxr->rx_buf_ring[cons];
1837 data = rx_buf->data;
1838 data_ptr = rx_buf->data_ptr;
1839 prefetch(data_ptr);
1840
1841 misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1);
1842 agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT;
1843
1844 if (agg_bufs) {
1845 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1846 return -EBUSY;
1847
1848 cp_cons = NEXT_CMP(cp_cons);
1849 *event |= BNXT_AGG_EVENT;
1850 }
1851 *event |= BNXT_RX_EVENT;
1852
1853 rx_buf->data = NULL;
1854 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1855 u32 rx_err = le32_to_cpu(rxcmp1->rx_cmp_cfa_code_errors_v2);
1856
1857 bnxt_reuse_rx_data(rxr, cons, data);
1858 if (agg_bufs)
1859 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, 0, agg_bufs,
1860 false);
1861
1862 rc = -EIO;
1863 if (rx_err & RX_CMPL_ERRORS_BUFFER_ERROR_MASK) {
1864 bnapi->cp_ring.sw_stats.rx.rx_buf_errors++;
1865 if (!(bp->flags & BNXT_FLAG_CHIP_P5) &&
1866 !(bp->fw_cap & BNXT_FW_CAP_RING_MONITOR)) {
1867 netdev_warn_once(bp->dev, "RX buffer error %x\n",
1868 rx_err);
1869 bnxt_sched_reset(bp, rxr);
1870 }
1871 }
1872 goto next_rx_no_len;
1873 }
1874
1875 flags = le32_to_cpu(rxcmp->rx_cmp_len_flags_type);
1876 len = flags >> RX_CMP_LEN_SHIFT;
1877 dma_addr = rx_buf->mapping;
1878
1879 if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) {
1880 rc = 1;
1881 goto next_rx;
1882 }
1883
1884 if (len <= bp->rx_copy_thresh) {
1885 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr);
1886 bnxt_reuse_rx_data(rxr, cons, data);
1887 if (!skb) {
1888 if (agg_bufs)
1889 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, 0,
1890 agg_bufs, false);
1891 rc = -ENOMEM;
1892 goto next_rx;
1893 }
1894 } else {
1895 u32 payload;
1896
1897 if (rx_buf->data_ptr == data_ptr)
1898 payload = misc & RX_CMP_PAYLOAD_OFFSET;
1899 else
1900 payload = 0;
1901 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr,
1902 payload | len);
1903 if (!skb) {
1904 rc = -ENOMEM;
1905 goto next_rx;
1906 }
1907 }
1908
1909 if (agg_bufs) {
1910 skb = bnxt_rx_pages(bp, cpr, skb, cp_cons, agg_bufs, false);
1911 if (!skb) {
1912 rc = -ENOMEM;
1913 goto next_rx;
1914 }
1915 }
1916
1917 if (RX_CMP_HASH_VALID(rxcmp)) {
1918 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1919 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1920
1921 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1922 if (hash_type != 1 && hash_type != 3)
1923 type = PKT_HASH_TYPE_L3;
1924 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1925 }
1926
1927 cfa_code = RX_CMP_CFA_CODE(rxcmp1);
1928 skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code));
1929
1930 if ((rxcmp1->rx_cmp_flags2 &
1931 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
1932 (skb->dev->features & BNXT_HW_FEATURE_VLAN_ALL_RX)) {
1933 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1934 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1935 __be16 vlan_proto = htons(meta_data >>
1936 RX_CMP_FLAGS2_METADATA_TPID_SFT);
1937
1938 if (eth_type_vlan(vlan_proto)) {
1939 __vlan_hwaccel_put_tag(skb, vlan_proto, vtag);
1940 } else {
1941 dev_kfree_skb(skb);
1942 goto next_rx;
1943 }
1944 }
1945
1946 skb_checksum_none_assert(skb);
1947 if (RX_CMP_L4_CS_OK(rxcmp1)) {
1948 if (dev->features & NETIF_F_RXCSUM) {
1949 skb->ip_summed = CHECKSUM_UNNECESSARY;
1950 skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1951 }
1952 } else {
1953 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1954 if (dev->features & NETIF_F_RXCSUM)
1955 bnapi->cp_ring.sw_stats.rx.rx_l4_csum_errors++;
1956 }
1957 }
1958
1959 if (unlikely((flags & RX_CMP_FLAGS_ITYPES_MASK) ==
1960 RX_CMP_FLAGS_ITYPE_PTP_W_TS)) {
1961 if (bp->flags & BNXT_FLAG_CHIP_P5) {
1962 u32 cmpl_ts = le32_to_cpu(rxcmp1->rx_cmp_timestamp);
1963 u64 ns, ts;
1964
1965 if (!bnxt_get_rx_ts_p5(bp, &ts, cmpl_ts)) {
1966 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1967
1968 spin_lock_bh(&ptp->ptp_lock);
1969 ns = timecounter_cyc2time(&ptp->tc, ts);
1970 spin_unlock_bh(&ptp->ptp_lock);
1971 memset(skb_hwtstamps(skb), 0,
1972 sizeof(*skb_hwtstamps(skb)));
1973 skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns);
1974 }
1975 }
1976 }
1977 bnxt_deliver_skb(bp, bnapi, skb);
1978 rc = 1;
1979
1980 next_rx:
1981 cpr->rx_packets += 1;
1982 cpr->rx_bytes += len;
1983
1984 next_rx_no_len:
1985 rxr->rx_prod = NEXT_RX(prod);
1986 rxr->rx_next_cons = NEXT_RX(cons);
1987
1988 next_rx_no_prod_no_len:
1989 *raw_cons = tmp_raw_cons;
1990
1991 return rc;
1992 }
1993
1994 /* In netpoll mode, if we are using a combined completion ring, we need to
1995 * discard the rx packets and recycle the buffers.
1996 */
1997 static int bnxt_force_rx_discard(struct bnxt *bp,
1998 struct bnxt_cp_ring_info *cpr,
1999 u32 *raw_cons, u8 *event)
2000 {
2001 u32 tmp_raw_cons = *raw_cons;
2002 struct rx_cmp_ext *rxcmp1;
2003 struct rx_cmp *rxcmp;
2004 u16 cp_cons;
2005 u8 cmp_type;
2006
2007 cp_cons = RING_CMP(tmp_raw_cons);
2008 rxcmp = (struct rx_cmp *)
2009 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2010
2011 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
2012 cp_cons = RING_CMP(tmp_raw_cons);
2013 rxcmp1 = (struct rx_cmp_ext *)
2014 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2015
2016 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
2017 return -EBUSY;
2018
2019 /* The valid test of the entry must be done first before
2020 * reading any further.
2021 */
2022 dma_rmb();
2023 cmp_type = RX_CMP_TYPE(rxcmp);
2024 if (cmp_type == CMP_TYPE_RX_L2_CMP) {
2025 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
2026 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
2027 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
2028 struct rx_tpa_end_cmp_ext *tpa_end1;
2029
2030 tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1;
2031 tpa_end1->rx_tpa_end_cmp_errors_v2 |=
2032 cpu_to_le32(RX_TPA_END_CMP_ERRORS);
2033 }
2034 return bnxt_rx_pkt(bp, cpr, raw_cons, event);
2035 }
2036
2037 u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx)
2038 {
2039 struct bnxt_fw_health *fw_health = bp->fw_health;
2040 u32 reg = fw_health->regs[reg_idx];
2041 u32 reg_type, reg_off, val = 0;
2042
2043 reg_type = BNXT_FW_HEALTH_REG_TYPE(reg);
2044 reg_off = BNXT_FW_HEALTH_REG_OFF(reg);
2045 switch (reg_type) {
2046 case BNXT_FW_HEALTH_REG_TYPE_CFG:
2047 pci_read_config_dword(bp->pdev, reg_off, &val);
2048 break;
2049 case BNXT_FW_HEALTH_REG_TYPE_GRC:
2050 reg_off = fw_health->mapped_regs[reg_idx];
2051 fallthrough;
2052 case BNXT_FW_HEALTH_REG_TYPE_BAR0:
2053 val = readl(bp->bar0 + reg_off);
2054 break;
2055 case BNXT_FW_HEALTH_REG_TYPE_BAR1:
2056 val = readl(bp->bar1 + reg_off);
2057 break;
2058 }
2059 if (reg_idx == BNXT_FW_RESET_INPROG_REG)
2060 val &= fw_health->fw_reset_inprog_reg_mask;
2061 return val;
2062 }
2063
2064 static u16 bnxt_agg_ring_id_to_grp_idx(struct bnxt *bp, u16 ring_id)
2065 {
2066 int i;
2067
2068 for (i = 0; i < bp->rx_nr_rings; i++) {
2069 u16 grp_idx = bp->rx_ring[i].bnapi->index;
2070 struct bnxt_ring_grp_info *grp_info;
2071
2072 grp_info = &bp->grp_info[grp_idx];
2073 if (grp_info->agg_fw_ring_id == ring_id)
2074 return grp_idx;
2075 }
2076 return INVALID_HW_RING_ID;
2077 }
2078
2079 static void bnxt_event_error_report(struct bnxt *bp, u32 data1, u32 data2)
2080 {
2081 switch (BNXT_EVENT_ERROR_REPORT_TYPE(data1)) {
2082 case ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL:
2083 netdev_err(bp->dev, "1PPS: Received invalid signal on pin%lu from the external source. Please fix the signal and reconfigure the pin\n",
2084 BNXT_EVENT_INVALID_SIGNAL_DATA(data2));
2085 break;
2086 default:
2087 netdev_err(bp->dev, "FW reported unknown error type\n");
2088 break;
2089 }
2090 }
2091
2092 #define BNXT_GET_EVENT_PORT(data) \
2093 ((data) & \
2094 ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
2095
2096 #define BNXT_EVENT_RING_TYPE(data2) \
2097 ((data2) & \
2098 ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK)
2099
2100 #define BNXT_EVENT_RING_TYPE_RX(data2) \
2101 (BNXT_EVENT_RING_TYPE(data2) == \
2102 ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX)
2103
2104 static int bnxt_async_event_process(struct bnxt *bp,
2105 struct hwrm_async_event_cmpl *cmpl)
2106 {
2107 u16 event_id = le16_to_cpu(cmpl->event_id);
2108 u32 data1 = le32_to_cpu(cmpl->event_data1);
2109 u32 data2 = le32_to_cpu(cmpl->event_data2);
2110
2111 /* TODO CHIMP_FW: Define event id's for link change, error etc */
2112 switch (event_id) {
2113 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
2114 struct bnxt_link_info *link_info = &bp->link_info;
2115
2116 if (BNXT_VF(bp))
2117 goto async_event_process_exit;
2118
2119 /* print unsupported speed warning in forced speed mode only */
2120 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED) &&
2121 (data1 & 0x20000)) {
2122 u16 fw_speed = link_info->force_link_speed;
2123 u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
2124
2125 if (speed != SPEED_UNKNOWN)
2126 netdev_warn(bp->dev, "Link speed %d no longer supported\n",
2127 speed);
2128 }
2129 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event);
2130 }
2131 fallthrough;
2132 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE:
2133 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE:
2134 set_bit(BNXT_LINK_CFG_CHANGE_SP_EVENT, &bp->sp_event);
2135 fallthrough;
2136 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
2137 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
2138 break;
2139 case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
2140 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
2141 break;
2142 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
2143 u16 port_id = BNXT_GET_EVENT_PORT(data1);
2144
2145 if (BNXT_VF(bp))
2146 break;
2147
2148 if (bp->pf.port_id != port_id)
2149 break;
2150
2151 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
2152 break;
2153 }
2154 case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE:
2155 if (BNXT_PF(bp))
2156 goto async_event_process_exit;
2157 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
2158 break;
2159 case ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY: {
2160 char *fatal_str = "non-fatal";
2161
2162 if (!bp->fw_health)
2163 goto async_event_process_exit;
2164
2165 bp->fw_reset_timestamp = jiffies;
2166 bp->fw_reset_min_dsecs = cmpl->timestamp_lo;
2167 if (!bp->fw_reset_min_dsecs)
2168 bp->fw_reset_min_dsecs = BNXT_DFLT_FW_RST_MIN_DSECS;
2169 bp->fw_reset_max_dsecs = le16_to_cpu(cmpl->timestamp_hi);
2170 if (!bp->fw_reset_max_dsecs)
2171 bp->fw_reset_max_dsecs = BNXT_DFLT_FW_RST_MAX_DSECS;
2172 if (EVENT_DATA1_RESET_NOTIFY_FATAL(data1)) {
2173 fatal_str = "fatal";
2174 set_bit(BNXT_STATE_FW_FATAL_COND, &bp->state);
2175 }
2176 netif_warn(bp, hw, bp->dev,
2177 "Firmware %s reset event, data1: 0x%x, data2: 0x%x, min wait %u ms, max wait %u ms\n",
2178 fatal_str, data1, data2,
2179 bp->fw_reset_min_dsecs * 100,
2180 bp->fw_reset_max_dsecs * 100);
2181 set_bit(BNXT_FW_RESET_NOTIFY_SP_EVENT, &bp->sp_event);
2182 break;
2183 }
2184 case ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY: {
2185 struct bnxt_fw_health *fw_health = bp->fw_health;
2186
2187 if (!fw_health)
2188 goto async_event_process_exit;
2189
2190 fw_health->enabled = EVENT_DATA1_RECOVERY_ENABLED(data1);
2191 fw_health->master = EVENT_DATA1_RECOVERY_MASTER_FUNC(data1);
2192 if (!fw_health->enabled) {
2193 netif_info(bp, drv, bp->dev,
2194 "Error recovery info: error recovery[0]\n");
2195 break;
2196 }
2197 fw_health->tmr_multiplier =
2198 DIV_ROUND_UP(fw_health->polling_dsecs * HZ,
2199 bp->current_interval * 10);
2200 fw_health->tmr_counter = fw_health->tmr_multiplier;
2201 fw_health->last_fw_heartbeat =
2202 bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG);
2203 fw_health->last_fw_reset_cnt =
2204 bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG);
2205 netif_info(bp, drv, bp->dev,
2206 "Error recovery info: error recovery[1], master[%d], reset count[%u], health status: 0x%x\n",
2207 fw_health->master, fw_health->last_fw_reset_cnt,
2208 bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG));
2209 goto async_event_process_exit;
2210 }
2211 case ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION:
2212 netif_notice(bp, hw, bp->dev,
2213 "Received firmware debug notification, data1: 0x%x, data2: 0x%x\n",
2214 data1, data2);
2215 goto async_event_process_exit;
2216 case ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG: {
2217 struct bnxt_rx_ring_info *rxr;
2218 u16 grp_idx;
2219
2220 if (bp->flags & BNXT_FLAG_CHIP_P5)
2221 goto async_event_process_exit;
2222
2223 netdev_warn(bp->dev, "Ring monitor event, ring type %lu id 0x%x\n",
2224 BNXT_EVENT_RING_TYPE(data2), data1);
2225 if (!BNXT_EVENT_RING_TYPE_RX(data2))
2226 goto async_event_process_exit;
2227
2228 grp_idx = bnxt_agg_ring_id_to_grp_idx(bp, data1);
2229 if (grp_idx == INVALID_HW_RING_ID) {
2230 netdev_warn(bp->dev, "Unknown RX agg ring id 0x%x\n",
2231 data1);
2232 goto async_event_process_exit;
2233 }
2234 rxr = bp->bnapi[grp_idx]->rx_ring;
2235 bnxt_sched_reset(bp, rxr);
2236 goto async_event_process_exit;
2237 }
2238 case ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST: {
2239 struct bnxt_fw_health *fw_health = bp->fw_health;
2240
2241 netif_notice(bp, hw, bp->dev,
2242 "Received firmware echo request, data1: 0x%x, data2: 0x%x\n",
2243 data1, data2);
2244 if (fw_health) {
2245 fw_health->echo_req_data1 = data1;
2246 fw_health->echo_req_data2 = data2;
2247 set_bit(BNXT_FW_ECHO_REQUEST_SP_EVENT, &bp->sp_event);
2248 break;
2249 }
2250 goto async_event_process_exit;
2251 }
2252 case ASYNC_EVENT_CMPL_EVENT_ID_PPS_TIMESTAMP: {
2253 bnxt_ptp_pps_event(bp, data1, data2);
2254 goto async_event_process_exit;
2255 }
2256 case ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT: {
2257 bnxt_event_error_report(bp, data1, data2);
2258 goto async_event_process_exit;
2259 }
2260 default:
2261 goto async_event_process_exit;
2262 }
2263 bnxt_queue_sp_work(bp);
2264 async_event_process_exit:
2265 bnxt_ulp_async_events(bp, cmpl);
2266 return 0;
2267 }
2268
2269 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
2270 {
2271 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
2272 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
2273 struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
2274 (struct hwrm_fwd_req_cmpl *)txcmp;
2275
2276 switch (cmpl_type) {
2277 case CMPL_BASE_TYPE_HWRM_DONE:
2278 seq_id = le16_to_cpu(h_cmpl->sequence_id);
2279 if (seq_id == bp->hwrm_intr_seq_id)
2280 bp->hwrm_intr_seq_id = (u16)~bp->hwrm_intr_seq_id;
2281 else
2282 netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
2283 break;
2284
2285 case CMPL_BASE_TYPE_HWRM_FWD_REQ:
2286 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
2287
2288 if ((vf_id < bp->pf.first_vf_id) ||
2289 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
2290 netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
2291 vf_id);
2292 return -EINVAL;
2293 }
2294
2295 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
2296 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
2297 bnxt_queue_sp_work(bp);
2298 break;
2299
2300 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
2301 bnxt_async_event_process(bp,
2302 (struct hwrm_async_event_cmpl *)txcmp);
2303 break;
2304
2305 default:
2306 break;
2307 }
2308
2309 return 0;
2310 }
2311
2312 static irqreturn_t bnxt_msix(int irq, void *dev_instance)
2313 {
2314 struct bnxt_napi *bnapi = dev_instance;
2315 struct bnxt *bp = bnapi->bp;
2316 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2317 u32 cons = RING_CMP(cpr->cp_raw_cons);
2318
2319 cpr->event_ctr++;
2320 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
2321 napi_schedule(&bnapi->napi);
2322 return IRQ_HANDLED;
2323 }
2324
2325 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2326 {
2327 u32 raw_cons = cpr->cp_raw_cons;
2328 u16 cons = RING_CMP(raw_cons);
2329 struct tx_cmp *txcmp;
2330
2331 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
2332
2333 return TX_CMP_VALID(txcmp, raw_cons);
2334 }
2335
2336 static irqreturn_t bnxt_inta(int irq, void *dev_instance)
2337 {
2338 struct bnxt_napi *bnapi = dev_instance;
2339 struct bnxt *bp = bnapi->bp;
2340 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2341 u32 cons = RING_CMP(cpr->cp_raw_cons);
2342 u32 int_status;
2343
2344 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
2345
2346 if (!bnxt_has_work(bp, cpr)) {
2347 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
2348 /* return if erroneous interrupt */
2349 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
2350 return IRQ_NONE;
2351 }
2352
2353 /* disable ring IRQ */
2354 BNXT_CP_DB_IRQ_DIS(cpr->cp_db.doorbell);
2355
2356 /* Return here if interrupt is shared and is disabled. */
2357 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2358 return IRQ_HANDLED;
2359
2360 napi_schedule(&bnapi->napi);
2361 return IRQ_HANDLED;
2362 }
2363
2364 static int __bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
2365 int budget)
2366 {
2367 struct bnxt_napi *bnapi = cpr->bnapi;
2368 u32 raw_cons = cpr->cp_raw_cons;
2369 u32 cons;
2370 int tx_pkts = 0;
2371 int rx_pkts = 0;
2372 u8 event = 0;
2373 struct tx_cmp *txcmp;
2374
2375 cpr->has_more_work = 0;
2376 cpr->had_work_done = 1;
2377 while (1) {
2378 int rc;
2379
2380 cons = RING_CMP(raw_cons);
2381 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
2382
2383 if (!TX_CMP_VALID(txcmp, raw_cons))
2384 break;
2385
2386 /* The valid test of the entry must be done first before
2387 * reading any further.
2388 */
2389 dma_rmb();
2390 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
2391 tx_pkts++;
2392 /* return full budget so NAPI will complete. */
2393 if (unlikely(tx_pkts > bp->tx_wake_thresh)) {
2394 rx_pkts = budget;
2395 raw_cons = NEXT_RAW_CMP(raw_cons);
2396 if (budget)
2397 cpr->has_more_work = 1;
2398 break;
2399 }
2400 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
2401 if (likely(budget))
2402 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event);
2403 else
2404 rc = bnxt_force_rx_discard(bp, cpr, &raw_cons,
2405 &event);
2406 if (likely(rc >= 0))
2407 rx_pkts += rc;
2408 /* Increment rx_pkts when rc is -ENOMEM to count towards
2409 * the NAPI budget. Otherwise, we may potentially loop
2410 * here forever if we consistently cannot allocate
2411 * buffers.
2412 */
2413 else if (rc == -ENOMEM && budget)
2414 rx_pkts++;
2415 else if (rc == -EBUSY) /* partial completion */
2416 break;
2417 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
2418 CMPL_BASE_TYPE_HWRM_DONE) ||
2419 (TX_CMP_TYPE(txcmp) ==
2420 CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
2421 (TX_CMP_TYPE(txcmp) ==
2422 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
2423 bnxt_hwrm_handler(bp, txcmp);
2424 }
2425 raw_cons = NEXT_RAW_CMP(raw_cons);
2426
2427 if (rx_pkts && rx_pkts == budget) {
2428 cpr->has_more_work = 1;
2429 break;
2430 }
2431 }
2432
2433 if (event & BNXT_REDIRECT_EVENT)
2434 xdp_do_flush_map();
2435
2436 if (event & BNXT_TX_EVENT) {
2437 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
2438 u16 prod = txr->tx_prod;
2439
2440 /* Sync BD data before updating doorbell */
2441 wmb();
2442
2443 bnxt_db_write_relaxed(bp, &txr->tx_db, prod);
2444 }
2445
2446 cpr->cp_raw_cons = raw_cons;
2447 bnapi->tx_pkts += tx_pkts;
2448 bnapi->events |= event;
2449 return rx_pkts;
2450 }
2451
2452 static void __bnxt_poll_work_done(struct bnxt *bp, struct bnxt_napi *bnapi)
2453 {
2454 if (bnapi->tx_pkts) {
2455 bnapi->tx_int(bp, bnapi, bnapi->tx_pkts);
2456 bnapi->tx_pkts = 0;
2457 }
2458
2459 if ((bnapi->events & BNXT_RX_EVENT) && !(bnapi->in_reset)) {
2460 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
2461
2462 if (bnapi->events & BNXT_AGG_EVENT)
2463 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
2464 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
2465 }
2466 bnapi->events = 0;
2467 }
2468
2469 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
2470 int budget)
2471 {
2472 struct bnxt_napi *bnapi = cpr->bnapi;
2473 int rx_pkts;
2474
2475 rx_pkts = __bnxt_poll_work(bp, cpr, budget);
2476
2477 /* ACK completion ring before freeing tx ring and producing new
2478 * buffers in rx/agg rings to prevent overflowing the completion
2479 * ring.
2480 */
2481 bnxt_db_cq(bp, &cpr->cp_db, cpr->cp_raw_cons);
2482
2483 __bnxt_poll_work_done(bp, bnapi);
2484 return rx_pkts;
2485 }
2486
2487 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget)
2488 {
2489 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2490 struct bnxt *bp = bnapi->bp;
2491 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2492 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
2493 struct tx_cmp *txcmp;
2494 struct rx_cmp_ext *rxcmp1;
2495 u32 cp_cons, tmp_raw_cons;
2496 u32 raw_cons = cpr->cp_raw_cons;
2497 u32 rx_pkts = 0;
2498 u8 event = 0;
2499
2500 while (1) {
2501 int rc;
2502
2503 cp_cons = RING_CMP(raw_cons);
2504 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2505
2506 if (!TX_CMP_VALID(txcmp, raw_cons))
2507 break;
2508
2509 /* The valid test of the entry must be done first before
2510 * reading any further.
2511 */
2512 dma_rmb();
2513 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
2514 tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
2515 cp_cons = RING_CMP(tmp_raw_cons);
2516 rxcmp1 = (struct rx_cmp_ext *)
2517 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2518
2519 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
2520 break;
2521
2522 /* force an error to recycle the buffer */
2523 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
2524 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
2525
2526 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event);
2527 if (likely(rc == -EIO) && budget)
2528 rx_pkts++;
2529 else if (rc == -EBUSY) /* partial completion */
2530 break;
2531 } else if (unlikely(TX_CMP_TYPE(txcmp) ==
2532 CMPL_BASE_TYPE_HWRM_DONE)) {
2533 bnxt_hwrm_handler(bp, txcmp);
2534 } else {
2535 netdev_err(bp->dev,
2536 "Invalid completion received on special ring\n");
2537 }
2538 raw_cons = NEXT_RAW_CMP(raw_cons);
2539
2540 if (rx_pkts == budget)
2541 break;
2542 }
2543
2544 cpr->cp_raw_cons = raw_cons;
2545 BNXT_DB_CQ(&cpr->cp_db, cpr->cp_raw_cons);
2546 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
2547
2548 if (event & BNXT_AGG_EVENT)
2549 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
2550
2551 if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) {
2552 napi_complete_done(napi, rx_pkts);
2553 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2554 }
2555 return rx_pkts;
2556 }
2557
2558 static int bnxt_poll(struct napi_struct *napi, int budget)
2559 {
2560 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2561 struct bnxt *bp = bnapi->bp;
2562 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2563 int work_done = 0;
2564
2565 if (unlikely(test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))) {
2566 napi_complete(napi);
2567 return 0;
2568 }
2569 while (1) {
2570 work_done += bnxt_poll_work(bp, cpr, budget - work_done);
2571
2572 if (work_done >= budget) {
2573 if (!budget)
2574 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2575 break;
2576 }
2577
2578 if (!bnxt_has_work(bp, cpr)) {
2579 if (napi_complete_done(napi, work_done))
2580 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2581 break;
2582 }
2583 }
2584 if (bp->flags & BNXT_FLAG_DIM) {
2585 struct dim_sample dim_sample = {};
2586
2587 dim_update_sample(cpr->event_ctr,
2588 cpr->rx_packets,
2589 cpr->rx_bytes,
2590 &dim_sample);
2591 net_dim(&cpr->dim, dim_sample);
2592 }
2593 return work_done;
2594 }
2595
2596 static int __bnxt_poll_cqs(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
2597 {
2598 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2599 int i, work_done = 0;
2600
2601 for (i = 0; i < 2; i++) {
2602 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i];
2603
2604 if (cpr2) {
2605 work_done += __bnxt_poll_work(bp, cpr2,
2606 budget - work_done);
2607 cpr->has_more_work |= cpr2->has_more_work;
2608 }
2609 }
2610 return work_done;
2611 }
2612
2613 static void __bnxt_poll_cqs_done(struct bnxt *bp, struct bnxt_napi *bnapi,
2614 u64 dbr_type)
2615 {
2616 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2617 int i;
2618
2619 for (i = 0; i < 2; i++) {
2620 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i];
2621 struct bnxt_db_info *db;
2622
2623 if (cpr2 && cpr2->had_work_done) {
2624 db = &cpr2->cp_db;
2625 writeq(db->db_key64 | dbr_type |
2626 RING_CMP(cpr2->cp_raw_cons), db->doorbell);
2627 cpr2->had_work_done = 0;
2628 }
2629 }
2630 __bnxt_poll_work_done(bp, bnapi);
2631 }
2632
2633 static int bnxt_poll_p5(struct napi_struct *napi, int budget)
2634 {
2635 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2636 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2637 u32 raw_cons = cpr->cp_raw_cons;
2638 struct bnxt *bp = bnapi->bp;
2639 struct nqe_cn *nqcmp;
2640 int work_done = 0;
2641 u32 cons;
2642
2643 if (unlikely(test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))) {
2644 napi_complete(napi);
2645 return 0;
2646 }
2647 if (cpr->has_more_work) {
2648 cpr->has_more_work = 0;
2649 work_done = __bnxt_poll_cqs(bp, bnapi, budget);
2650 }
2651 while (1) {
2652 cons = RING_CMP(raw_cons);
2653 nqcmp = &cpr->nq_desc_ring[CP_RING(cons)][CP_IDX(cons)];
2654
2655 if (!NQ_CMP_VALID(nqcmp, raw_cons)) {
2656 if (cpr->has_more_work)
2657 break;
2658
2659 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL);
2660 cpr->cp_raw_cons = raw_cons;
2661 if (napi_complete_done(napi, work_done))
2662 BNXT_DB_NQ_ARM_P5(&cpr->cp_db,
2663 cpr->cp_raw_cons);
2664 return work_done;
2665 }
2666
2667 /* The valid test of the entry must be done first before
2668 * reading any further.
2669 */
2670 dma_rmb();
2671
2672 if (nqcmp->type == cpu_to_le16(NQ_CN_TYPE_CQ_NOTIFICATION)) {
2673 u32 idx = le32_to_cpu(nqcmp->cq_handle_low);
2674 struct bnxt_cp_ring_info *cpr2;
2675
2676 cpr2 = cpr->cp_ring_arr[idx];
2677 work_done += __bnxt_poll_work(bp, cpr2,
2678 budget - work_done);
2679 cpr->has_more_work |= cpr2->has_more_work;
2680 } else {
2681 bnxt_hwrm_handler(bp, (struct tx_cmp *)nqcmp);
2682 }
2683 raw_cons = NEXT_RAW_CMP(raw_cons);
2684 }
2685 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ);
2686 if (raw_cons != cpr->cp_raw_cons) {
2687 cpr->cp_raw_cons = raw_cons;
2688 BNXT_DB_NQ_P5(&cpr->cp_db, raw_cons);
2689 }
2690 return work_done;
2691 }
2692
2693 static void bnxt_free_tx_skbs(struct bnxt *bp)
2694 {
2695 int i, max_idx;
2696 struct pci_dev *pdev = bp->pdev;
2697
2698 if (!bp->tx_ring)
2699 return;
2700
2701 max_idx = bp->tx_nr_pages * TX_DESC_CNT;
2702 for (i = 0; i < bp->tx_nr_rings; i++) {
2703 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2704 int j;
2705
2706 for (j = 0; j < max_idx;) {
2707 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
2708 struct sk_buff *skb;
2709 int k, last;
2710
2711 if (i < bp->tx_nr_rings_xdp &&
2712 tx_buf->action == XDP_REDIRECT) {
2713 dma_unmap_single(&pdev->dev,
2714 dma_unmap_addr(tx_buf, mapping),
2715 dma_unmap_len(tx_buf, len),
2716 PCI_DMA_TODEVICE);
2717 xdp_return_frame(tx_buf->xdpf);
2718 tx_buf->action = 0;
2719 tx_buf->xdpf = NULL;
2720 j++;
2721 continue;
2722 }
2723
2724 skb = tx_buf->skb;
2725 if (!skb) {
2726 j++;
2727 continue;
2728 }
2729
2730 tx_buf->skb = NULL;
2731
2732 if (tx_buf->is_push) {
2733 dev_kfree_skb(skb);
2734 j += 2;
2735 continue;
2736 }
2737
2738 dma_unmap_single(&pdev->dev,
2739 dma_unmap_addr(tx_buf, mapping),
2740 skb_headlen(skb),
2741 PCI_DMA_TODEVICE);
2742
2743 last = tx_buf->nr_frags;
2744 j += 2;
2745 for (k = 0; k < last; k++, j++) {
2746 int ring_idx = j & bp->tx_ring_mask;
2747 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
2748
2749 tx_buf = &txr->tx_buf_ring[ring_idx];
2750 dma_unmap_page(
2751 &pdev->dev,
2752 dma_unmap_addr(tx_buf, mapping),
2753 skb_frag_size(frag), PCI_DMA_TODEVICE);
2754 }
2755 dev_kfree_skb(skb);
2756 }
2757 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
2758 }
2759 }
2760
2761 static void bnxt_free_one_rx_ring_skbs(struct bnxt *bp, int ring_nr)
2762 {
2763 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[ring_nr];
2764 struct pci_dev *pdev = bp->pdev;
2765 struct bnxt_tpa_idx_map *map;
2766 int i, max_idx, max_agg_idx;
2767
2768 max_idx = bp->rx_nr_pages * RX_DESC_CNT;
2769 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
2770 if (!rxr->rx_tpa)
2771 goto skip_rx_tpa_free;
2772
2773 for (i = 0; i < bp->max_tpa; i++) {
2774 struct bnxt_tpa_info *tpa_info = &rxr->rx_tpa[i];
2775 u8 *data = tpa_info->data;
2776
2777 if (!data)
2778 continue;
2779
2780 dma_unmap_single_attrs(&pdev->dev, tpa_info->mapping,
2781 bp->rx_buf_use_size, bp->rx_dir,
2782 DMA_ATTR_WEAK_ORDERING);
2783
2784 tpa_info->data = NULL;
2785
2786 kfree(data);
2787 }
2788
2789 skip_rx_tpa_free:
2790 for (i = 0; i < max_idx; i++) {
2791 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[i];
2792 dma_addr_t mapping = rx_buf->mapping;
2793 void *data = rx_buf->data;
2794
2795 if (!data)
2796 continue;
2797
2798 rx_buf->data = NULL;
2799 if (BNXT_RX_PAGE_MODE(bp)) {
2800 mapping -= bp->rx_dma_offset;
2801 dma_unmap_page_attrs(&pdev->dev, mapping, PAGE_SIZE,
2802 bp->rx_dir,
2803 DMA_ATTR_WEAK_ORDERING);
2804 page_pool_recycle_direct(rxr->page_pool, data);
2805 } else {
2806 dma_unmap_single_attrs(&pdev->dev, mapping,
2807 bp->rx_buf_use_size, bp->rx_dir,
2808 DMA_ATTR_WEAK_ORDERING);
2809 kfree(data);
2810 }
2811 }
2812 for (i = 0; i < max_agg_idx; i++) {
2813 struct bnxt_sw_rx_agg_bd *rx_agg_buf = &rxr->rx_agg_ring[i];
2814 struct page *page = rx_agg_buf->page;
2815
2816 if (!page)
2817 continue;
2818
2819 dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping,
2820 BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE,
2821 DMA_ATTR_WEAK_ORDERING);
2822
2823 rx_agg_buf->page = NULL;
2824 __clear_bit(i, rxr->rx_agg_bmap);
2825
2826 __free_page(page);
2827 }
2828 if (rxr->rx_page) {
2829 __free_page(rxr->rx_page);
2830 rxr->rx_page = NULL;
2831 }
2832 map = rxr->rx_tpa_idx_map;
2833 if (map)
2834 memset(map->agg_idx_bmap, 0, sizeof(map->agg_idx_bmap));
2835 }
2836
2837 static void bnxt_free_rx_skbs(struct bnxt *bp)
2838 {
2839 int i;
2840
2841 if (!bp->rx_ring)
2842 return;
2843
2844 for (i = 0; i < bp->rx_nr_rings; i++)
2845 bnxt_free_one_rx_ring_skbs(bp, i);
2846 }
2847
2848 static void bnxt_free_skbs(struct bnxt *bp)
2849 {
2850 bnxt_free_tx_skbs(bp);
2851 bnxt_free_rx_skbs(bp);
2852 }
2853
2854 static void bnxt_init_ctx_mem(struct bnxt_mem_init *mem_init, void *p, int len)
2855 {
2856 u8 init_val = mem_init->init_val;
2857 u16 offset = mem_init->offset;
2858 u8 *p2 = p;
2859 int i;
2860
2861 if (!init_val)
2862 return;
2863 if (offset == BNXT_MEM_INVALID_OFFSET) {
2864 memset(p, init_val, len);
2865 return;
2866 }
2867 for (i = 0; i < len; i += mem_init->size)
2868 *(p2 + i + offset) = init_val;
2869 }
2870
2871 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem)
2872 {
2873 struct pci_dev *pdev = bp->pdev;
2874 int i;
2875
2876 for (i = 0; i < rmem->nr_pages; i++) {
2877 if (!rmem->pg_arr[i])
2878 continue;
2879
2880 dma_free_coherent(&pdev->dev, rmem->page_size,
2881 rmem->pg_arr[i], rmem->dma_arr[i]);
2882
2883 rmem->pg_arr[i] = NULL;
2884 }
2885 if (rmem->pg_tbl) {
2886 size_t pg_tbl_size = rmem->nr_pages * 8;
2887
2888 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG)
2889 pg_tbl_size = rmem->page_size;
2890 dma_free_coherent(&pdev->dev, pg_tbl_size,
2891 rmem->pg_tbl, rmem->pg_tbl_map);
2892 rmem->pg_tbl = NULL;
2893 }
2894 if (rmem->vmem_size && *rmem->vmem) {
2895 vfree(*rmem->vmem);
2896 *rmem->vmem = NULL;
2897 }
2898 }
2899
2900 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem)
2901 {
2902 struct pci_dev *pdev = bp->pdev;
2903 u64 valid_bit = 0;
2904 int i;
2905
2906 if (rmem->flags & (BNXT_RMEM_VALID_PTE_FLAG | BNXT_RMEM_RING_PTE_FLAG))
2907 valid_bit = PTU_PTE_VALID;
2908 if ((rmem->nr_pages > 1 || rmem->depth > 0) && !rmem->pg_tbl) {
2909 size_t pg_tbl_size = rmem->nr_pages * 8;
2910
2911 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG)
2912 pg_tbl_size = rmem->page_size;
2913 rmem->pg_tbl = dma_alloc_coherent(&pdev->dev, pg_tbl_size,
2914 &rmem->pg_tbl_map,
2915 GFP_KERNEL);
2916 if (!rmem->pg_tbl)
2917 return -ENOMEM;
2918 }
2919
2920 for (i = 0; i < rmem->nr_pages; i++) {
2921 u64 extra_bits = valid_bit;
2922
2923 rmem->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
2924 rmem->page_size,
2925 &rmem->dma_arr[i],
2926 GFP_KERNEL);
2927 if (!rmem->pg_arr[i])
2928 return -ENOMEM;
2929
2930 if (rmem->mem_init)
2931 bnxt_init_ctx_mem(rmem->mem_init, rmem->pg_arr[i],
2932 rmem->page_size);
2933 if (rmem->nr_pages > 1 || rmem->depth > 0) {
2934 if (i == rmem->nr_pages - 2 &&
2935 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
2936 extra_bits |= PTU_PTE_NEXT_TO_LAST;
2937 else if (i == rmem->nr_pages - 1 &&
2938 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
2939 extra_bits |= PTU_PTE_LAST;
2940 rmem->pg_tbl[i] =
2941 cpu_to_le64(rmem->dma_arr[i] | extra_bits);
2942 }
2943 }
2944
2945 if (rmem->vmem_size) {
2946 *rmem->vmem = vzalloc(rmem->vmem_size);
2947 if (!(*rmem->vmem))
2948 return -ENOMEM;
2949 }
2950 return 0;
2951 }
2952
2953 static void bnxt_free_tpa_info(struct bnxt *bp)
2954 {
2955 int i;
2956
2957 for (i = 0; i < bp->rx_nr_rings; i++) {
2958 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2959
2960 kfree(rxr->rx_tpa_idx_map);
2961 rxr->rx_tpa_idx_map = NULL;
2962 if (rxr->rx_tpa) {
2963 kfree(rxr->rx_tpa[0].agg_arr);
2964 rxr->rx_tpa[0].agg_arr = NULL;
2965 }
2966 kfree(rxr->rx_tpa);
2967 rxr->rx_tpa = NULL;
2968 }
2969 }
2970
2971 static int bnxt_alloc_tpa_info(struct bnxt *bp)
2972 {
2973 int i, j, total_aggs = 0;
2974
2975 bp->max_tpa = MAX_TPA;
2976 if (bp->flags & BNXT_FLAG_CHIP_P5) {
2977 if (!bp->max_tpa_v2)
2978 return 0;
2979 bp->max_tpa = max_t(u16, bp->max_tpa_v2, MAX_TPA_P5);
2980 total_aggs = bp->max_tpa * MAX_SKB_FRAGS;
2981 }
2982
2983 for (i = 0; i < bp->rx_nr_rings; i++) {
2984 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2985 struct rx_agg_cmp *agg;
2986
2987 rxr->rx_tpa = kcalloc(bp->max_tpa, sizeof(struct bnxt_tpa_info),
2988 GFP_KERNEL);
2989 if (!rxr->rx_tpa)
2990 return -ENOMEM;
2991
2992 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
2993 continue;
2994 agg = kcalloc(total_aggs, sizeof(*agg), GFP_KERNEL);
2995 rxr->rx_tpa[0].agg_arr = agg;
2996 if (!agg)
2997 return -ENOMEM;
2998 for (j = 1; j < bp->max_tpa; j++)
2999 rxr->rx_tpa[j].agg_arr = agg + j * MAX_SKB_FRAGS;
3000 rxr->rx_tpa_idx_map = kzalloc(sizeof(*rxr->rx_tpa_idx_map),
3001 GFP_KERNEL);
3002 if (!rxr->rx_tpa_idx_map)
3003 return -ENOMEM;
3004 }
3005 return 0;
3006 }
3007
3008 static void bnxt_free_rx_rings(struct bnxt *bp)
3009 {
3010 int i;
3011
3012 if (!bp->rx_ring)
3013 return;
3014
3015 bnxt_free_tpa_info(bp);
3016 for (i = 0; i < bp->rx_nr_rings; i++) {
3017 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3018 struct bnxt_ring_struct *ring;
3019
3020 if (rxr->xdp_prog)
3021 bpf_prog_put(rxr->xdp_prog);
3022
3023 if (xdp_rxq_info_is_reg(&rxr->xdp_rxq))
3024 xdp_rxq_info_unreg(&rxr->xdp_rxq);
3025
3026 page_pool_destroy(rxr->page_pool);
3027 rxr->page_pool = NULL;
3028
3029 kfree(rxr->rx_agg_bmap);
3030 rxr->rx_agg_bmap = NULL;
3031
3032 ring = &rxr->rx_ring_struct;
3033 bnxt_free_ring(bp, &ring->ring_mem);
3034
3035 ring = &rxr->rx_agg_ring_struct;
3036 bnxt_free_ring(bp, &ring->ring_mem);
3037 }
3038 }
3039
3040 static int bnxt_alloc_rx_page_pool(struct bnxt *bp,
3041 struct bnxt_rx_ring_info *rxr)
3042 {
3043 struct page_pool_params pp = { 0 };
3044
3045 pp.pool_size = bp->rx_ring_size;
3046 pp.nid = dev_to_node(&bp->pdev->dev);
3047 pp.dev = &bp->pdev->dev;
3048 pp.dma_dir = DMA_BIDIRECTIONAL;
3049
3050 rxr->page_pool = page_pool_create(&pp);
3051 if (IS_ERR(rxr->page_pool)) {
3052 int err = PTR_ERR(rxr->page_pool);
3053
3054 rxr->page_pool = NULL;
3055 return err;
3056 }
3057 return 0;
3058 }
3059
3060 static int bnxt_alloc_rx_rings(struct bnxt *bp)
3061 {
3062 int i, rc = 0, agg_rings = 0;
3063
3064 if (!bp->rx_ring)
3065 return -ENOMEM;
3066
3067 if (bp->flags & BNXT_FLAG_AGG_RINGS)
3068 agg_rings = 1;
3069
3070 for (i = 0; i < bp->rx_nr_rings; i++) {
3071 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3072 struct bnxt_ring_struct *ring;
3073
3074 ring = &rxr->rx_ring_struct;
3075
3076 rc = bnxt_alloc_rx_page_pool(bp, rxr);
3077 if (rc)
3078 return rc;
3079
3080 rc = xdp_rxq_info_reg(&rxr->xdp_rxq, bp->dev, i, 0);
3081 if (rc < 0)
3082 return rc;
3083
3084 rc = xdp_rxq_info_reg_mem_model(&rxr->xdp_rxq,
3085 MEM_TYPE_PAGE_POOL,
3086 rxr->page_pool);
3087 if (rc) {
3088 xdp_rxq_info_unreg(&rxr->xdp_rxq);
3089 return rc;
3090 }
3091
3092 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
3093 if (rc)
3094 return rc;
3095
3096 ring->grp_idx = i;
3097 if (agg_rings) {
3098 u16 mem_size;
3099
3100 ring = &rxr->rx_agg_ring_struct;
3101 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
3102 if (rc)
3103 return rc;
3104
3105 ring->grp_idx = i;
3106 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
3107 mem_size = rxr->rx_agg_bmap_size / 8;
3108 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
3109 if (!rxr->rx_agg_bmap)
3110 return -ENOMEM;
3111 }
3112 }
3113 if (bp->flags & BNXT_FLAG_TPA)
3114 rc = bnxt_alloc_tpa_info(bp);
3115 return rc;
3116 }
3117
3118 static void bnxt_free_tx_rings(struct bnxt *bp)
3119 {
3120 int i;
3121 struct pci_dev *pdev = bp->pdev;
3122
3123 if (!bp->tx_ring)
3124 return;
3125
3126 for (i = 0; i < bp->tx_nr_rings; i++) {
3127 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3128 struct bnxt_ring_struct *ring;
3129
3130 if (txr->tx_push) {
3131 dma_free_coherent(&pdev->dev, bp->tx_push_size,
3132 txr->tx_push, txr->tx_push_mapping);
3133 txr->tx_push = NULL;
3134 }
3135
3136 ring = &txr->tx_ring_struct;
3137
3138 bnxt_free_ring(bp, &ring->ring_mem);
3139 }
3140 }
3141
3142 static int bnxt_alloc_tx_rings(struct bnxt *bp)
3143 {
3144 int i, j, rc;
3145 struct pci_dev *pdev = bp->pdev;
3146
3147 bp->tx_push_size = 0;
3148 if (bp->tx_push_thresh) {
3149 int push_size;
3150
3151 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
3152 bp->tx_push_thresh);
3153
3154 if (push_size > 256) {
3155 push_size = 0;
3156 bp->tx_push_thresh = 0;
3157 }
3158
3159 bp->tx_push_size = push_size;
3160 }
3161
3162 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
3163 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3164 struct bnxt_ring_struct *ring;
3165 u8 qidx;
3166
3167 ring = &txr->tx_ring_struct;
3168
3169 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
3170 if (rc)
3171 return rc;
3172
3173 ring->grp_idx = txr->bnapi->index;
3174 if (bp->tx_push_size) {
3175 dma_addr_t mapping;
3176
3177 /* One pre-allocated DMA buffer to backup
3178 * TX push operation
3179 */
3180 txr->tx_push = dma_alloc_coherent(&pdev->dev,
3181 bp->tx_push_size,
3182 &txr->tx_push_mapping,
3183 GFP_KERNEL);
3184
3185 if (!txr->tx_push)
3186 return -ENOMEM;
3187
3188 mapping = txr->tx_push_mapping +
3189 sizeof(struct tx_push_bd);
3190 txr->data_mapping = cpu_to_le64(mapping);
3191 }
3192 qidx = bp->tc_to_qidx[j];
3193 ring->queue_id = bp->q_info[qidx].queue_id;
3194 if (i < bp->tx_nr_rings_xdp)
3195 continue;
3196 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
3197 j++;
3198 }
3199 return 0;
3200 }
3201
3202 static void bnxt_free_cp_arrays(struct bnxt_cp_ring_info *cpr)
3203 {
3204 kfree(cpr->cp_desc_ring);
3205 cpr->cp_desc_ring = NULL;
3206 kfree(cpr->cp_desc_mapping);
3207 cpr->cp_desc_mapping = NULL;
3208 }
3209
3210 static int bnxt_alloc_cp_arrays(struct bnxt_cp_ring_info *cpr, int n)
3211 {
3212 cpr->cp_desc_ring = kcalloc(n, sizeof(*cpr->cp_desc_ring), GFP_KERNEL);
3213 if (!cpr->cp_desc_ring)
3214 return -ENOMEM;
3215 cpr->cp_desc_mapping = kcalloc(n, sizeof(*cpr->cp_desc_mapping),
3216 GFP_KERNEL);
3217 if (!cpr->cp_desc_mapping)
3218 return -ENOMEM;
3219 return 0;
3220 }
3221
3222 static void bnxt_free_all_cp_arrays(struct bnxt *bp)
3223 {
3224 int i;
3225
3226 if (!bp->bnapi)
3227 return;
3228 for (i = 0; i < bp->cp_nr_rings; i++) {
3229 struct bnxt_napi *bnapi = bp->bnapi[i];
3230
3231 if (!bnapi)
3232 continue;
3233 bnxt_free_cp_arrays(&bnapi->cp_ring);
3234 }
3235 }
3236
3237 static int bnxt_alloc_all_cp_arrays(struct bnxt *bp)
3238 {
3239 int i, n = bp->cp_nr_pages;
3240
3241 for (i = 0; i < bp->cp_nr_rings; i++) {
3242 struct bnxt_napi *bnapi = bp->bnapi[i];
3243 int rc;
3244
3245 if (!bnapi)
3246 continue;
3247 rc = bnxt_alloc_cp_arrays(&bnapi->cp_ring, n);
3248 if (rc)
3249 return rc;
3250 }
3251 return 0;
3252 }
3253
3254 static void bnxt_free_cp_rings(struct bnxt *bp)
3255 {
3256 int i;
3257
3258 if (!bp->bnapi)
3259 return;
3260
3261 for (i = 0; i < bp->cp_nr_rings; i++) {
3262 struct bnxt_napi *bnapi = bp->bnapi[i];
3263 struct bnxt_cp_ring_info *cpr;
3264 struct bnxt_ring_struct *ring;
3265 int j;
3266
3267 if (!bnapi)
3268 continue;
3269
3270 cpr = &bnapi->cp_ring;
3271 ring = &cpr->cp_ring_struct;
3272
3273 bnxt_free_ring(bp, &ring->ring_mem);
3274
3275 for (j = 0; j < 2; j++) {
3276 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
3277
3278 if (cpr2) {
3279 ring = &cpr2->cp_ring_struct;
3280 bnxt_free_ring(bp, &ring->ring_mem);
3281 bnxt_free_cp_arrays(cpr2);
3282 kfree(cpr2);
3283 cpr->cp_ring_arr[j] = NULL;
3284 }
3285 }
3286 }
3287 }
3288
3289 static struct bnxt_cp_ring_info *bnxt_alloc_cp_sub_ring(struct bnxt *bp)
3290 {
3291 struct bnxt_ring_mem_info *rmem;
3292 struct bnxt_ring_struct *ring;
3293 struct bnxt_cp_ring_info *cpr;
3294 int rc;
3295
3296 cpr = kzalloc(sizeof(*cpr), GFP_KERNEL);
3297 if (!cpr)
3298 return NULL;
3299
3300 rc = bnxt_alloc_cp_arrays(cpr, bp->cp_nr_pages);
3301 if (rc) {
3302 bnxt_free_cp_arrays(cpr);
3303 kfree(cpr);
3304 return NULL;
3305 }
3306 ring = &cpr->cp_ring_struct;
3307 rmem = &ring->ring_mem;
3308 rmem->nr_pages = bp->cp_nr_pages;
3309 rmem->page_size = HW_CMPD_RING_SIZE;
3310 rmem->pg_arr = (void **)cpr->cp_desc_ring;
3311 rmem->dma_arr = cpr->cp_desc_mapping;
3312 rmem->flags = BNXT_RMEM_RING_PTE_FLAG;
3313 rc = bnxt_alloc_ring(bp, rmem);
3314 if (rc) {
3315 bnxt_free_ring(bp, rmem);
3316 bnxt_free_cp_arrays(cpr);
3317 kfree(cpr);
3318 cpr = NULL;
3319 }
3320 return cpr;
3321 }
3322
3323 static int bnxt_alloc_cp_rings(struct bnxt *bp)
3324 {
3325 bool sh = !!(bp->flags & BNXT_FLAG_SHARED_RINGS);
3326 int i, rc, ulp_base_vec, ulp_msix;
3327
3328 ulp_msix = bnxt_get_ulp_msix_num(bp);
3329 ulp_base_vec = bnxt_get_ulp_msix_base(bp);
3330 for (i = 0; i < bp->cp_nr_rings; i++) {
3331 struct bnxt_napi *bnapi = bp->bnapi[i];
3332 struct bnxt_cp_ring_info *cpr;
3333 struct bnxt_ring_struct *ring;
3334
3335 if (!bnapi)
3336 continue;
3337
3338 cpr = &bnapi->cp_ring;
3339 cpr->bnapi = bnapi;
3340 ring = &cpr->cp_ring_struct;
3341
3342 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
3343 if (rc)
3344 return rc;
3345
3346 if (ulp_msix && i >= ulp_base_vec)
3347 ring->map_idx = i + ulp_msix;
3348 else
3349 ring->map_idx = i;
3350
3351 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
3352 continue;
3353
3354 if (i < bp->rx_nr_rings) {
3355 struct bnxt_cp_ring_info *cpr2 =
3356 bnxt_alloc_cp_sub_ring(bp);
3357
3358 cpr->cp_ring_arr[BNXT_RX_HDL] = cpr2;
3359 if (!cpr2)
3360 return -ENOMEM;
3361 cpr2->bnapi = bnapi;
3362 }
3363 if ((sh && i < bp->tx_nr_rings) ||
3364 (!sh && i >= bp->rx_nr_rings)) {
3365 struct bnxt_cp_ring_info *cpr2 =
3366 bnxt_alloc_cp_sub_ring(bp);
3367
3368 cpr->cp_ring_arr[BNXT_TX_HDL] = cpr2;
3369 if (!cpr2)
3370 return -ENOMEM;
3371 cpr2->bnapi = bnapi;
3372 }
3373 }
3374 return 0;
3375 }
3376
3377 static void bnxt_init_ring_struct(struct bnxt *bp)
3378 {
3379 int i;
3380
3381 for (i = 0; i < bp->cp_nr_rings; i++) {
3382 struct bnxt_napi *bnapi = bp->bnapi[i];
3383 struct bnxt_ring_mem_info *rmem;
3384 struct bnxt_cp_ring_info *cpr;
3385 struct bnxt_rx_ring_info *rxr;
3386 struct bnxt_tx_ring_info *txr;
3387 struct bnxt_ring_struct *ring;
3388
3389 if (!bnapi)
3390 continue;
3391
3392 cpr = &bnapi->cp_ring;
3393 ring = &cpr->cp_ring_struct;
3394 rmem = &ring->ring_mem;
3395 rmem->nr_pages = bp->cp_nr_pages;
3396 rmem->page_size = HW_CMPD_RING_SIZE;
3397 rmem->pg_arr = (void **)cpr->cp_desc_ring;
3398 rmem->dma_arr = cpr->cp_desc_mapping;
3399 rmem->vmem_size = 0;
3400
3401 rxr = bnapi->rx_ring;
3402 if (!rxr)
3403 goto skip_rx;
3404
3405 ring = &rxr->rx_ring_struct;
3406 rmem = &ring->ring_mem;
3407 rmem->nr_pages = bp->rx_nr_pages;
3408 rmem->page_size = HW_RXBD_RING_SIZE;
3409 rmem->pg_arr = (void **)rxr->rx_desc_ring;
3410 rmem->dma_arr = rxr->rx_desc_mapping;
3411 rmem->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
3412 rmem->vmem = (void **)&rxr->rx_buf_ring;
3413
3414 ring = &rxr->rx_agg_ring_struct;
3415 rmem = &ring->ring_mem;
3416 rmem->nr_pages = bp->rx_agg_nr_pages;
3417 rmem->page_size = HW_RXBD_RING_SIZE;
3418 rmem->pg_arr = (void **)rxr->rx_agg_desc_ring;
3419 rmem->dma_arr = rxr->rx_agg_desc_mapping;
3420 rmem->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
3421 rmem->vmem = (void **)&rxr->rx_agg_ring;
3422
3423 skip_rx:
3424 txr = bnapi->tx_ring;
3425 if (!txr)
3426 continue;
3427
3428 ring = &txr->tx_ring_struct;
3429 rmem = &ring->ring_mem;
3430 rmem->nr_pages = bp->tx_nr_pages;
3431 rmem->page_size = HW_RXBD_RING_SIZE;
3432 rmem->pg_arr = (void **)txr->tx_desc_ring;
3433 rmem->dma_arr = txr->tx_desc_mapping;
3434 rmem->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
3435 rmem->vmem = (void **)&txr->tx_buf_ring;
3436 }
3437 }
3438
3439 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
3440 {
3441 int i;
3442 u32 prod;
3443 struct rx_bd **rx_buf_ring;
3444
3445 rx_buf_ring = (struct rx_bd **)ring->ring_mem.pg_arr;
3446 for (i = 0, prod = 0; i < ring->ring_mem.nr_pages; i++) {
3447 int j;
3448 struct rx_bd *rxbd;
3449
3450 rxbd = rx_buf_ring[i];
3451 if (!rxbd)
3452 continue;
3453
3454 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
3455 rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
3456 rxbd->rx_bd_opaque = prod;
3457 }
3458 }
3459 }
3460
3461 static int bnxt_alloc_one_rx_ring(struct bnxt *bp, int ring_nr)
3462 {
3463 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[ring_nr];
3464 struct net_device *dev = bp->dev;
3465 u32 prod;
3466 int i;
3467
3468 prod = rxr->rx_prod;
3469 for (i = 0; i < bp->rx_ring_size; i++) {
3470 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL)) {
3471 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
3472 ring_nr, i, bp->rx_ring_size);
3473 break;
3474 }
3475 prod = NEXT_RX(prod);
3476 }
3477 rxr->rx_prod = prod;
3478
3479 if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
3480 return 0;
3481
3482 prod = rxr->rx_agg_prod;
3483 for (i = 0; i < bp->rx_agg_ring_size; i++) {
3484 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL)) {
3485 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
3486 ring_nr, i, bp->rx_ring_size);
3487 break;
3488 }
3489 prod = NEXT_RX_AGG(prod);
3490 }
3491 rxr->rx_agg_prod = prod;
3492
3493 if (rxr->rx_tpa) {
3494 dma_addr_t mapping;
3495 u8 *data;
3496
3497 for (i = 0; i < bp->max_tpa; i++) {
3498 data = __bnxt_alloc_rx_data(bp, &mapping, GFP_KERNEL);
3499 if (!data)
3500 return -ENOMEM;
3501
3502 rxr->rx_tpa[i].data = data;
3503 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset;
3504 rxr->rx_tpa[i].mapping = mapping;
3505 }
3506 }
3507 return 0;
3508 }
3509
3510 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
3511 {
3512 struct bnxt_rx_ring_info *rxr;
3513 struct bnxt_ring_struct *ring;
3514 u32 type;
3515
3516 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
3517 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
3518
3519 if (NET_IP_ALIGN == 2)
3520 type |= RX_BD_FLAGS_SOP;
3521
3522 rxr = &bp->rx_ring[ring_nr];
3523 ring = &rxr->rx_ring_struct;
3524 bnxt_init_rxbd_pages(ring, type);
3525
3526 if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) {
3527 bpf_prog_add(bp->xdp_prog, 1);
3528 rxr->xdp_prog = bp->xdp_prog;
3529 }
3530 ring->fw_ring_id = INVALID_HW_RING_ID;
3531
3532 ring = &rxr->rx_agg_ring_struct;
3533 ring->fw_ring_id = INVALID_HW_RING_ID;
3534
3535 if ((bp->flags & BNXT_FLAG_AGG_RINGS)) {
3536 type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
3537 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
3538
3539 bnxt_init_rxbd_pages(ring, type);
3540 }
3541
3542 return bnxt_alloc_one_rx_ring(bp, ring_nr);
3543 }
3544
3545 static void bnxt_init_cp_rings(struct bnxt *bp)
3546 {
3547 int i, j;
3548
3549 for (i = 0; i < bp->cp_nr_rings; i++) {
3550 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
3551 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3552
3553 ring->fw_ring_id = INVALID_HW_RING_ID;
3554 cpr->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
3555 cpr->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
3556 for (j = 0; j < 2; j++) {
3557 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
3558
3559 if (!cpr2)
3560 continue;
3561
3562 ring = &cpr2->cp_ring_struct;
3563 ring->fw_ring_id = INVALID_HW_RING_ID;
3564 cpr2->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
3565 cpr2->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
3566 }
3567 }
3568 }
3569
3570 static int bnxt_init_rx_rings(struct bnxt *bp)
3571 {
3572 int i, rc = 0;
3573
3574 if (BNXT_RX_PAGE_MODE(bp)) {
3575 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM;
3576 bp->rx_dma_offset = XDP_PACKET_HEADROOM;
3577 } else {
3578 bp->rx_offset = BNXT_RX_OFFSET;
3579 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET;
3580 }
3581
3582 for (i = 0; i < bp->rx_nr_rings; i++) {
3583 rc = bnxt_init_one_rx_ring(bp, i);
3584 if (rc)
3585 break;
3586 }
3587
3588 return rc;
3589 }
3590
3591 static int bnxt_init_tx_rings(struct bnxt *bp)
3592 {
3593 u16 i;
3594
3595 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
3596 MAX_SKB_FRAGS + 1);
3597
3598 for (i = 0; i < bp->tx_nr_rings; i++) {
3599 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3600 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
3601
3602 ring->fw_ring_id = INVALID_HW_RING_ID;
3603 }
3604
3605 return 0;
3606 }
3607
3608 static void bnxt_free_ring_grps(struct bnxt *bp)
3609 {
3610 kfree(bp->grp_info);
3611 bp->grp_info = NULL;
3612 }
3613
3614 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
3615 {
3616 int i;
3617
3618 if (irq_re_init) {
3619 bp->grp_info = kcalloc(bp->cp_nr_rings,
3620 sizeof(struct bnxt_ring_grp_info),
3621 GFP_KERNEL);
3622 if (!bp->grp_info)
3623 return -ENOMEM;
3624 }
3625 for (i = 0; i < bp->cp_nr_rings; i++) {
3626 if (irq_re_init)
3627 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
3628 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
3629 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
3630 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
3631 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
3632 }
3633 return 0;
3634 }
3635
3636 static void bnxt_free_vnics(struct bnxt *bp)
3637 {
3638 kfree(bp->vnic_info);
3639 bp->vnic_info = NULL;
3640 bp->nr_vnics = 0;
3641 }
3642
3643 static int bnxt_alloc_vnics(struct bnxt *bp)
3644 {
3645 int num_vnics = 1;
3646
3647 #ifdef CONFIG_RFS_ACCEL
3648 if ((bp->flags & (BNXT_FLAG_RFS | BNXT_FLAG_CHIP_P5)) == BNXT_FLAG_RFS)
3649 num_vnics += bp->rx_nr_rings;
3650 #endif
3651
3652 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
3653 num_vnics++;
3654
3655 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
3656 GFP_KERNEL);
3657 if (!bp->vnic_info)
3658 return -ENOMEM;
3659
3660 bp->nr_vnics = num_vnics;
3661 return 0;
3662 }
3663
3664 static void bnxt_init_vnics(struct bnxt *bp)
3665 {
3666 int i;
3667
3668 for (i = 0; i < bp->nr_vnics; i++) {
3669 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3670 int j;
3671
3672 vnic->fw_vnic_id = INVALID_HW_RING_ID;
3673 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++)
3674 vnic->fw_rss_cos_lb_ctx[j] = INVALID_HW_RING_ID;
3675
3676 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
3677
3678 if (bp->vnic_info[i].rss_hash_key) {
3679 if (i == 0)
3680 prandom_bytes(vnic->rss_hash_key,
3681 HW_HASH_KEY_SIZE);
3682 else
3683 memcpy(vnic->rss_hash_key,
3684 bp->vnic_info[0].rss_hash_key,
3685 HW_HASH_KEY_SIZE);
3686 }
3687 }
3688 }
3689
3690 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
3691 {
3692 int pages;
3693
3694 pages = ring_size / desc_per_pg;
3695
3696 if (!pages)
3697 return 1;
3698
3699 pages++;
3700
3701 while (pages & (pages - 1))
3702 pages++;
3703
3704 return pages;
3705 }
3706
3707 void bnxt_set_tpa_flags(struct bnxt *bp)
3708 {
3709 bp->flags &= ~BNXT_FLAG_TPA;
3710 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
3711 return;
3712 if (bp->dev->features & NETIF_F_LRO)
3713 bp->flags |= BNXT_FLAG_LRO;
3714 else if (bp->dev->features & NETIF_F_GRO_HW)
3715 bp->flags |= BNXT_FLAG_GRO;
3716 }
3717
3718 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
3719 * be set on entry.
3720 */
3721 void bnxt_set_ring_params(struct bnxt *bp)
3722 {
3723 u32 ring_size, rx_size, rx_space, max_rx_cmpl;
3724 u32 agg_factor = 0, agg_ring_size = 0;
3725
3726 /* 8 for CRC and VLAN */
3727 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
3728
3729 rx_space = rx_size + NET_SKB_PAD +
3730 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3731
3732 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
3733 ring_size = bp->rx_ring_size;
3734 bp->rx_agg_ring_size = 0;
3735 bp->rx_agg_nr_pages = 0;
3736
3737 if (bp->flags & BNXT_FLAG_TPA)
3738 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
3739
3740 bp->flags &= ~BNXT_FLAG_JUMBO;
3741 if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) {
3742 u32 jumbo_factor;
3743
3744 bp->flags |= BNXT_FLAG_JUMBO;
3745 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
3746 if (jumbo_factor > agg_factor)
3747 agg_factor = jumbo_factor;
3748 }
3749 if (agg_factor) {
3750 if (ring_size > BNXT_MAX_RX_DESC_CNT_JUM_ENA) {
3751 ring_size = BNXT_MAX_RX_DESC_CNT_JUM_ENA;
3752 netdev_warn(bp->dev, "RX ring size reduced from %d to %d because the jumbo ring is now enabled\n",
3753 bp->rx_ring_size, ring_size);
3754 bp->rx_ring_size = ring_size;
3755 }
3756 agg_ring_size = ring_size * agg_factor;
3757
3758 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
3759 RX_DESC_CNT);
3760 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
3761 u32 tmp = agg_ring_size;
3762
3763 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
3764 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
3765 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
3766 tmp, agg_ring_size);
3767 }
3768 bp->rx_agg_ring_size = agg_ring_size;
3769 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
3770 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
3771 rx_space = rx_size + NET_SKB_PAD +
3772 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3773 }
3774
3775 bp->rx_buf_use_size = rx_size;
3776 bp->rx_buf_size = rx_space;
3777
3778 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
3779 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
3780
3781 ring_size = bp->tx_ring_size;
3782 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
3783 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
3784
3785 max_rx_cmpl = bp->rx_ring_size;
3786 /* MAX TPA needs to be added because TPA_START completions are
3787 * immediately recycled, so the TPA completions are not bound by
3788 * the RX ring size.
3789 */
3790 if (bp->flags & BNXT_FLAG_TPA)
3791 max_rx_cmpl += bp->max_tpa;
3792 /* RX and TPA completions are 32-byte, all others are 16-byte */
3793 ring_size = max_rx_cmpl * 2 + agg_ring_size + bp->tx_ring_size;
3794 bp->cp_ring_size = ring_size;
3795
3796 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
3797 if (bp->cp_nr_pages > MAX_CP_PAGES) {
3798 bp->cp_nr_pages = MAX_CP_PAGES;
3799 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
3800 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
3801 ring_size, bp->cp_ring_size);
3802 }
3803 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
3804 bp->cp_ring_mask = bp->cp_bit - 1;
3805 }
3806
3807 /* Changing allocation mode of RX rings.
3808 * TODO: Update when extending xdp_rxq_info to support allocation modes.
3809 */
3810 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode)
3811 {
3812 if (page_mode) {
3813 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU)
3814 return -EOPNOTSUPP;
3815 bp->dev->max_mtu =
3816 min_t(u16, bp->max_mtu, BNXT_MAX_PAGE_MODE_MTU);
3817 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
3818 bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE;
3819 bp->rx_dir = DMA_BIDIRECTIONAL;
3820 bp->rx_skb_func = bnxt_rx_page_skb;
3821 /* Disable LRO or GRO_HW */
3822 netdev_update_features(bp->dev);
3823 } else {
3824 bp->dev->max_mtu = bp->max_mtu;
3825 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE;
3826 bp->rx_dir = DMA_FROM_DEVICE;
3827 bp->rx_skb_func = bnxt_rx_skb;
3828 }
3829 return 0;
3830 }
3831
3832 static void bnxt_free_vnic_attributes(struct bnxt *bp)
3833 {
3834 int i;
3835 struct bnxt_vnic_info *vnic;
3836 struct pci_dev *pdev = bp->pdev;
3837
3838 if (!bp->vnic_info)
3839 return;
3840
3841 for (i = 0; i < bp->nr_vnics; i++) {
3842 vnic = &bp->vnic_info[i];
3843
3844 kfree(vnic->fw_grp_ids);
3845 vnic->fw_grp_ids = NULL;
3846
3847 kfree(vnic->uc_list);
3848 vnic->uc_list = NULL;
3849
3850 if (vnic->mc_list) {
3851 dma_free_coherent(&pdev->dev, vnic->mc_list_size,
3852 vnic->mc_list, vnic->mc_list_mapping);
3853 vnic->mc_list = NULL;
3854 }
3855
3856 if (vnic->rss_table) {
3857 dma_free_coherent(&pdev->dev, vnic->rss_table_size,
3858 vnic->rss_table,
3859 vnic->rss_table_dma_addr);
3860 vnic->rss_table = NULL;
3861 }
3862
3863 vnic->rss_hash_key = NULL;
3864 vnic->flags = 0;
3865 }
3866 }
3867
3868 static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
3869 {
3870 int i, rc = 0, size;
3871 struct bnxt_vnic_info *vnic;
3872 struct pci_dev *pdev = bp->pdev;
3873 int max_rings;
3874
3875 for (i = 0; i < bp->nr_vnics; i++) {
3876 vnic = &bp->vnic_info[i];
3877
3878 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
3879 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
3880
3881 if (mem_size > 0) {
3882 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
3883 if (!vnic->uc_list) {
3884 rc = -ENOMEM;
3885 goto out;
3886 }
3887 }
3888 }
3889
3890 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
3891 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
3892 vnic->mc_list =
3893 dma_alloc_coherent(&pdev->dev,
3894 vnic->mc_list_size,
3895 &vnic->mc_list_mapping,
3896 GFP_KERNEL);
3897 if (!vnic->mc_list) {
3898 rc = -ENOMEM;
3899 goto out;
3900 }
3901 }
3902
3903 if (bp->flags & BNXT_FLAG_CHIP_P5)
3904 goto vnic_skip_grps;
3905
3906 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3907 max_rings = bp->rx_nr_rings;
3908 else
3909 max_rings = 1;
3910
3911 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
3912 if (!vnic->fw_grp_ids) {
3913 rc = -ENOMEM;
3914 goto out;
3915 }
3916 vnic_skip_grps:
3917 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
3918 !(vnic->flags & BNXT_VNIC_RSS_FLAG))
3919 continue;
3920
3921 /* Allocate rss table and hash key */
3922 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
3923 if (bp->flags & BNXT_FLAG_CHIP_P5)
3924 size = L1_CACHE_ALIGN(BNXT_MAX_RSS_TABLE_SIZE_P5);
3925
3926 vnic->rss_table_size = size + HW_HASH_KEY_SIZE;
3927 vnic->rss_table = dma_alloc_coherent(&pdev->dev,
3928 vnic->rss_table_size,
3929 &vnic->rss_table_dma_addr,
3930 GFP_KERNEL);
3931 if (!vnic->rss_table) {
3932 rc = -ENOMEM;
3933 goto out;
3934 }
3935
3936 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
3937 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
3938 }
3939 return 0;
3940
3941 out:
3942 return rc;
3943 }
3944
3945 static void bnxt_free_hwrm_resources(struct bnxt *bp)
3946 {
3947 struct pci_dev *pdev = bp->pdev;
3948
3949 if (bp->hwrm_cmd_resp_addr) {
3950 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
3951 bp->hwrm_cmd_resp_dma_addr);
3952 bp->hwrm_cmd_resp_addr = NULL;
3953 }
3954
3955 if (bp->hwrm_cmd_kong_resp_addr) {
3956 dma_free_coherent(&pdev->dev, PAGE_SIZE,
3957 bp->hwrm_cmd_kong_resp_addr,
3958 bp->hwrm_cmd_kong_resp_dma_addr);
3959 bp->hwrm_cmd_kong_resp_addr = NULL;
3960 }
3961 }
3962
3963 static int bnxt_alloc_kong_hwrm_resources(struct bnxt *bp)
3964 {
3965 struct pci_dev *pdev = bp->pdev;
3966
3967 if (bp->hwrm_cmd_kong_resp_addr)
3968 return 0;
3969
3970 bp->hwrm_cmd_kong_resp_addr =
3971 dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3972 &bp->hwrm_cmd_kong_resp_dma_addr,
3973 GFP_KERNEL);
3974 if (!bp->hwrm_cmd_kong_resp_addr)
3975 return -ENOMEM;
3976
3977 return 0;
3978 }
3979
3980 static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
3981 {
3982 struct pci_dev *pdev = bp->pdev;
3983
3984 bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3985 &bp->hwrm_cmd_resp_dma_addr,
3986 GFP_KERNEL);
3987 if (!bp->hwrm_cmd_resp_addr)
3988 return -ENOMEM;
3989
3990 return 0;
3991 }
3992
3993 static void bnxt_free_hwrm_short_cmd_req(struct bnxt *bp)
3994 {
3995 if (bp->hwrm_short_cmd_req_addr) {
3996 struct pci_dev *pdev = bp->pdev;
3997
3998 dma_free_coherent(&pdev->dev, bp->hwrm_max_ext_req_len,
3999 bp->hwrm_short_cmd_req_addr,
4000 bp->hwrm_short_cmd_req_dma_addr);
4001 bp->hwrm_short_cmd_req_addr = NULL;
4002 }
4003 }
4004
4005 static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt *bp)
4006 {
4007 struct pci_dev *pdev = bp->pdev;
4008
4009 if (bp->hwrm_short_cmd_req_addr)
4010 return 0;
4011
4012 bp->hwrm_short_cmd_req_addr =
4013 dma_alloc_coherent(&pdev->dev, bp->hwrm_max_ext_req_len,
4014 &bp->hwrm_short_cmd_req_dma_addr,
4015 GFP_KERNEL);
4016 if (!bp->hwrm_short_cmd_req_addr)
4017 return -ENOMEM;
4018
4019 return 0;
4020 }
4021
4022 static void bnxt_free_stats_mem(struct bnxt *bp, struct bnxt_stats_mem *stats)
4023 {
4024 kfree(stats->hw_masks);
4025 stats->hw_masks = NULL;
4026 kfree(stats->sw_stats);
4027 stats->sw_stats = NULL;
4028 if (stats->hw_stats) {
4029 dma_free_coherent(&bp->pdev->dev, stats->len, stats->hw_stats,
4030 stats->hw_stats_map);
4031 stats->hw_stats = NULL;
4032 }
4033 }
4034
4035 static int bnxt_alloc_stats_mem(struct bnxt *bp, struct bnxt_stats_mem *stats,
4036 bool alloc_masks)
4037 {
4038 stats->hw_stats = dma_alloc_coherent(&bp->pdev->dev, stats->len,
4039 &stats->hw_stats_map, GFP_KERNEL);
4040 if (!stats->hw_stats)
4041 return -ENOMEM;
4042
4043 stats->sw_stats = kzalloc(stats->len, GFP_KERNEL);
4044 if (!stats->sw_stats)
4045 goto stats_mem_err;
4046
4047 if (alloc_masks) {
4048 stats->hw_masks = kzalloc(stats->len, GFP_KERNEL);
4049 if (!stats->hw_masks)
4050 goto stats_mem_err;
4051 }
4052 return 0;
4053
4054 stats_mem_err:
4055 bnxt_free_stats_mem(bp, stats);
4056 return -ENOMEM;
4057 }
4058
4059 static void bnxt_fill_masks(u64 *mask_arr, u64 mask, int count)
4060 {
4061 int i;
4062
4063 for (i = 0; i < count; i++)
4064 mask_arr[i] = mask;
4065 }
4066
4067 static void bnxt_copy_hw_masks(u64 *mask_arr, __le64 *hw_mask_arr, int count)
4068 {
4069 int i;
4070
4071 for (i = 0; i < count; i++)
4072 mask_arr[i] = le64_to_cpu(hw_mask_arr[i]);
4073 }
4074
4075 static int bnxt_hwrm_func_qstat_ext(struct bnxt *bp,
4076 struct bnxt_stats_mem *stats)
4077 {
4078 struct hwrm_func_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4079 struct hwrm_func_qstats_ext_input req = {0};
4080 __le64 *hw_masks;
4081 int rc;
4082
4083 if (!(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED) ||
4084 !(bp->flags & BNXT_FLAG_CHIP_P5))
4085 return -EOPNOTSUPP;
4086
4087 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QSTATS_EXT, -1, -1);
4088 req.fid = cpu_to_le16(0xffff);
4089 req.flags = FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK;
4090 mutex_lock(&bp->hwrm_cmd_lock);
4091 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4092 if (rc)
4093 goto qstat_exit;
4094
4095 hw_masks = &resp->rx_ucast_pkts;
4096 bnxt_copy_hw_masks(stats->hw_masks, hw_masks, stats->len / 8);
4097
4098 qstat_exit:
4099 mutex_unlock(&bp->hwrm_cmd_lock);
4100 return rc;
4101 }
4102
4103 static int bnxt_hwrm_port_qstats(struct bnxt *bp, u8 flags);
4104 static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp, u8 flags);
4105
4106 static void bnxt_init_stats(struct bnxt *bp)
4107 {
4108 struct bnxt_napi *bnapi = bp->bnapi[0];
4109 struct bnxt_cp_ring_info *cpr;
4110 struct bnxt_stats_mem *stats;
4111 __le64 *rx_stats, *tx_stats;
4112 int rc, rx_count, tx_count;
4113 u64 *rx_masks, *tx_masks;
4114 u64 mask;
4115 u8 flags;
4116
4117 cpr = &bnapi->cp_ring;
4118 stats = &cpr->stats;
4119 rc = bnxt_hwrm_func_qstat_ext(bp, stats);
4120 if (rc) {
4121 if (bp->flags & BNXT_FLAG_CHIP_P5)
4122 mask = (1ULL << 48) - 1;
4123 else
4124 mask = -1ULL;
4125 bnxt_fill_masks(stats->hw_masks, mask, stats->len / 8);
4126 }
4127 if (bp->flags & BNXT_FLAG_PORT_STATS) {
4128 stats = &bp->port_stats;
4129 rx_stats = stats->hw_stats;
4130 rx_masks = stats->hw_masks;
4131 rx_count = sizeof(struct rx_port_stats) / 8;
4132 tx_stats = rx_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
4133 tx_masks = rx_masks + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
4134 tx_count = sizeof(struct tx_port_stats) / 8;
4135
4136 flags = PORT_QSTATS_REQ_FLAGS_COUNTER_MASK;
4137 rc = bnxt_hwrm_port_qstats(bp, flags);
4138 if (rc) {
4139 mask = (1ULL << 40) - 1;
4140
4141 bnxt_fill_masks(rx_masks, mask, rx_count);
4142 bnxt_fill_masks(tx_masks, mask, tx_count);
4143 } else {
4144 bnxt_copy_hw_masks(rx_masks, rx_stats, rx_count);
4145 bnxt_copy_hw_masks(tx_masks, tx_stats, tx_count);
4146 bnxt_hwrm_port_qstats(bp, 0);
4147 }
4148 }
4149 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
4150 stats = &bp->rx_port_stats_ext;
4151 rx_stats = stats->hw_stats;
4152 rx_masks = stats->hw_masks;
4153 rx_count = sizeof(struct rx_port_stats_ext) / 8;
4154 stats = &bp->tx_port_stats_ext;
4155 tx_stats = stats->hw_stats;
4156 tx_masks = stats->hw_masks;
4157 tx_count = sizeof(struct tx_port_stats_ext) / 8;
4158
4159 flags = PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK;
4160 rc = bnxt_hwrm_port_qstats_ext(bp, flags);
4161 if (rc) {
4162 mask = (1ULL << 40) - 1;
4163
4164 bnxt_fill_masks(rx_masks, mask, rx_count);
4165 if (tx_stats)
4166 bnxt_fill_masks(tx_masks, mask, tx_count);
4167 } else {
4168 bnxt_copy_hw_masks(rx_masks, rx_stats, rx_count);
4169 if (tx_stats)
4170 bnxt_copy_hw_masks(tx_masks, tx_stats,
4171 tx_count);
4172 bnxt_hwrm_port_qstats_ext(bp, 0);
4173 }
4174 }
4175 }
4176
4177 static void bnxt_free_port_stats(struct bnxt *bp)
4178 {
4179 bp->flags &= ~BNXT_FLAG_PORT_STATS;
4180 bp->flags &= ~BNXT_FLAG_PORT_STATS_EXT;
4181
4182 bnxt_free_stats_mem(bp, &bp->port_stats);
4183 bnxt_free_stats_mem(bp, &bp->rx_port_stats_ext);
4184 bnxt_free_stats_mem(bp, &bp->tx_port_stats_ext);
4185 }
4186
4187 static void bnxt_free_ring_stats(struct bnxt *bp)
4188 {
4189 int i;
4190
4191 if (!bp->bnapi)
4192 return;
4193
4194 for (i = 0; i < bp->cp_nr_rings; i++) {
4195 struct bnxt_napi *bnapi = bp->bnapi[i];
4196 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4197
4198 bnxt_free_stats_mem(bp, &cpr->stats);
4199 }
4200 }
4201
4202 static int bnxt_alloc_stats(struct bnxt *bp)
4203 {
4204 u32 size, i;
4205 int rc;
4206
4207 size = bp->hw_ring_stats_size;
4208
4209 for (i = 0; i < bp->cp_nr_rings; i++) {
4210 struct bnxt_napi *bnapi = bp->bnapi[i];
4211 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4212
4213 cpr->stats.len = size;
4214 rc = bnxt_alloc_stats_mem(bp, &cpr->stats, !i);
4215 if (rc)
4216 return rc;
4217
4218 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
4219 }
4220
4221 if (BNXT_VF(bp) || bp->chip_num == CHIP_NUM_58700)
4222 return 0;
4223
4224 if (bp->port_stats.hw_stats)
4225 goto alloc_ext_stats;
4226
4227 bp->port_stats.len = BNXT_PORT_STATS_SIZE;
4228 rc = bnxt_alloc_stats_mem(bp, &bp->port_stats, true);
4229 if (rc)
4230 return rc;
4231
4232 bp->flags |= BNXT_FLAG_PORT_STATS;
4233
4234 alloc_ext_stats:
4235 /* Display extended statistics only if FW supports it */
4236 if (bp->hwrm_spec_code < 0x10804 || bp->hwrm_spec_code == 0x10900)
4237 if (!(bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED))
4238 return 0;
4239
4240 if (bp->rx_port_stats_ext.hw_stats)
4241 goto alloc_tx_ext_stats;
4242
4243 bp->rx_port_stats_ext.len = sizeof(struct rx_port_stats_ext);
4244 rc = bnxt_alloc_stats_mem(bp, &bp->rx_port_stats_ext, true);
4245 /* Extended stats are optional */
4246 if (rc)
4247 return 0;
4248
4249 alloc_tx_ext_stats:
4250 if (bp->tx_port_stats_ext.hw_stats)
4251 return 0;
4252
4253 if (bp->hwrm_spec_code >= 0x10902 ||
4254 (bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED)) {
4255 bp->tx_port_stats_ext.len = sizeof(struct tx_port_stats_ext);
4256 rc = bnxt_alloc_stats_mem(bp, &bp->tx_port_stats_ext, true);
4257 /* Extended stats are optional */
4258 if (rc)
4259 return 0;
4260 }
4261 bp->flags |= BNXT_FLAG_PORT_STATS_EXT;
4262 return 0;
4263 }
4264
4265 static void bnxt_clear_ring_indices(struct bnxt *bp)
4266 {
4267 int i;
4268
4269 if (!bp->bnapi)
4270 return;
4271
4272 for (i = 0; i < bp->cp_nr_rings; i++) {
4273 struct bnxt_napi *bnapi = bp->bnapi[i];
4274 struct bnxt_cp_ring_info *cpr;
4275 struct bnxt_rx_ring_info *rxr;
4276 struct bnxt_tx_ring_info *txr;
4277
4278 if (!bnapi)
4279 continue;
4280
4281 cpr = &bnapi->cp_ring;
4282 cpr->cp_raw_cons = 0;
4283
4284 txr = bnapi->tx_ring;
4285 if (txr) {
4286 txr->tx_prod = 0;
4287 txr->tx_cons = 0;
4288 }
4289
4290 rxr = bnapi->rx_ring;
4291 if (rxr) {
4292 rxr->rx_prod = 0;
4293 rxr->rx_agg_prod = 0;
4294 rxr->rx_sw_agg_prod = 0;
4295 rxr->rx_next_cons = 0;
4296 }
4297 }
4298 }
4299
4300 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
4301 {
4302 #ifdef CONFIG_RFS_ACCEL
4303 int i;
4304
4305 /* Under rtnl_lock and all our NAPIs have been disabled. It's
4306 * safe to delete the hash table.
4307 */
4308 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
4309 struct hlist_head *head;
4310 struct hlist_node *tmp;
4311 struct bnxt_ntuple_filter *fltr;
4312
4313 head = &bp->ntp_fltr_hash_tbl[i];
4314 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
4315 hlist_del(&fltr->hash);
4316 kfree(fltr);
4317 }
4318 }
4319 if (irq_reinit) {
4320 kfree(bp->ntp_fltr_bmap);
4321 bp->ntp_fltr_bmap = NULL;
4322 }
4323 bp->ntp_fltr_count = 0;
4324 #endif
4325 }
4326
4327 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
4328 {
4329 #ifdef CONFIG_RFS_ACCEL
4330 int i, rc = 0;
4331
4332 if (!(bp->flags & BNXT_FLAG_RFS))
4333 return 0;
4334
4335 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
4336 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
4337
4338 bp->ntp_fltr_count = 0;
4339 bp->ntp_fltr_bmap = kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
4340 sizeof(long),
4341 GFP_KERNEL);
4342
4343 if (!bp->ntp_fltr_bmap)
4344 rc = -ENOMEM;
4345
4346 return rc;
4347 #else
4348 return 0;
4349 #endif
4350 }
4351
4352 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
4353 {
4354 bnxt_free_vnic_attributes(bp);
4355 bnxt_free_tx_rings(bp);
4356 bnxt_free_rx_rings(bp);
4357 bnxt_free_cp_rings(bp);
4358 bnxt_free_all_cp_arrays(bp);
4359 bnxt_free_ntp_fltrs(bp, irq_re_init);
4360 if (irq_re_init) {
4361 bnxt_free_ring_stats(bp);
4362 if (!(bp->phy_flags & BNXT_PHY_FL_PORT_STATS_NO_RESET) ||
4363 test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
4364 bnxt_free_port_stats(bp);
4365 bnxt_free_ring_grps(bp);
4366 bnxt_free_vnics(bp);
4367 kfree(bp->tx_ring_map);
4368 bp->tx_ring_map = NULL;
4369 kfree(bp->tx_ring);
4370 bp->tx_ring = NULL;
4371 kfree(bp->rx_ring);
4372 bp->rx_ring = NULL;
4373 kfree(bp->bnapi);
4374 bp->bnapi = NULL;
4375 } else {
4376 bnxt_clear_ring_indices(bp);
4377 }
4378 }
4379
4380 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
4381 {
4382 int i, j, rc, size, arr_size;
4383 void *bnapi;
4384
4385 if (irq_re_init) {
4386 /* Allocate bnapi mem pointer array and mem block for
4387 * all queues
4388 */
4389 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
4390 bp->cp_nr_rings);
4391 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
4392 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
4393 if (!bnapi)
4394 return -ENOMEM;
4395
4396 bp->bnapi = bnapi;
4397 bnapi += arr_size;
4398 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
4399 bp->bnapi[i] = bnapi;
4400 bp->bnapi[i]->index = i;
4401 bp->bnapi[i]->bp = bp;
4402 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4403 struct bnxt_cp_ring_info *cpr =
4404 &bp->bnapi[i]->cp_ring;
4405
4406 cpr->cp_ring_struct.ring_mem.flags =
4407 BNXT_RMEM_RING_PTE_FLAG;
4408 }
4409 }
4410
4411 bp->rx_ring = kcalloc(bp->rx_nr_rings,
4412 sizeof(struct bnxt_rx_ring_info),
4413 GFP_KERNEL);
4414 if (!bp->rx_ring)
4415 return -ENOMEM;
4416
4417 for (i = 0; i < bp->rx_nr_rings; i++) {
4418 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4419
4420 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4421 rxr->rx_ring_struct.ring_mem.flags =
4422 BNXT_RMEM_RING_PTE_FLAG;
4423 rxr->rx_agg_ring_struct.ring_mem.flags =
4424 BNXT_RMEM_RING_PTE_FLAG;
4425 }
4426 rxr->bnapi = bp->bnapi[i];
4427 bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
4428 }
4429
4430 bp->tx_ring = kcalloc(bp->tx_nr_rings,
4431 sizeof(struct bnxt_tx_ring_info),
4432 GFP_KERNEL);
4433 if (!bp->tx_ring)
4434 return -ENOMEM;
4435
4436 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16),
4437 GFP_KERNEL);
4438
4439 if (!bp->tx_ring_map)
4440 return -ENOMEM;
4441
4442 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
4443 j = 0;
4444 else
4445 j = bp->rx_nr_rings;
4446
4447 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
4448 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
4449
4450 if (bp->flags & BNXT_FLAG_CHIP_P5)
4451 txr->tx_ring_struct.ring_mem.flags =
4452 BNXT_RMEM_RING_PTE_FLAG;
4453 txr->bnapi = bp->bnapi[j];
4454 bp->bnapi[j]->tx_ring = txr;
4455 bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i;
4456 if (i >= bp->tx_nr_rings_xdp) {
4457 txr->txq_index = i - bp->tx_nr_rings_xdp;
4458 bp->bnapi[j]->tx_int = bnxt_tx_int;
4459 } else {
4460 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP;
4461 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp;
4462 }
4463 }
4464
4465 rc = bnxt_alloc_stats(bp);
4466 if (rc)
4467 goto alloc_mem_err;
4468 bnxt_init_stats(bp);
4469
4470 rc = bnxt_alloc_ntp_fltrs(bp);
4471 if (rc)
4472 goto alloc_mem_err;
4473
4474 rc = bnxt_alloc_vnics(bp);
4475 if (rc)
4476 goto alloc_mem_err;
4477 }
4478
4479 rc = bnxt_alloc_all_cp_arrays(bp);
4480 if (rc)
4481 goto alloc_mem_err;
4482
4483 bnxt_init_ring_struct(bp);
4484
4485 rc = bnxt_alloc_rx_rings(bp);
4486 if (rc)
4487 goto alloc_mem_err;
4488
4489 rc = bnxt_alloc_tx_rings(bp);
4490 if (rc)
4491 goto alloc_mem_err;
4492
4493 rc = bnxt_alloc_cp_rings(bp);
4494 if (rc)
4495 goto alloc_mem_err;
4496
4497 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
4498 BNXT_VNIC_UCAST_FLAG;
4499 rc = bnxt_alloc_vnic_attributes(bp);
4500 if (rc)
4501 goto alloc_mem_err;
4502 return 0;
4503
4504 alloc_mem_err:
4505 bnxt_free_mem(bp, true);
4506 return rc;
4507 }
4508
4509 static void bnxt_disable_int(struct bnxt *bp)
4510 {
4511 int i;
4512
4513 if (!bp->bnapi)
4514 return;
4515
4516 for (i = 0; i < bp->cp_nr_rings; i++) {
4517 struct bnxt_napi *bnapi = bp->bnapi[i];
4518 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4519 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4520
4521 if (ring->fw_ring_id != INVALID_HW_RING_ID)
4522 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons);
4523 }
4524 }
4525
4526 static int bnxt_cp_num_to_irq_num(struct bnxt *bp, int n)
4527 {
4528 struct bnxt_napi *bnapi = bp->bnapi[n];
4529 struct bnxt_cp_ring_info *cpr;
4530
4531 cpr = &bnapi->cp_ring;
4532 return cpr->cp_ring_struct.map_idx;
4533 }
4534
4535 static void bnxt_disable_int_sync(struct bnxt *bp)
4536 {
4537 int i;
4538
4539 if (!bp->irq_tbl)
4540 return;
4541
4542 atomic_inc(&bp->intr_sem);
4543
4544 bnxt_disable_int(bp);
4545 for (i = 0; i < bp->cp_nr_rings; i++) {
4546 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
4547
4548 synchronize_irq(bp->irq_tbl[map_idx].vector);
4549 }
4550 }
4551
4552 static void bnxt_enable_int(struct bnxt *bp)
4553 {
4554 int i;
4555
4556 atomic_set(&bp->intr_sem, 0);
4557 for (i = 0; i < bp->cp_nr_rings; i++) {
4558 struct bnxt_napi *bnapi = bp->bnapi[i];
4559 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4560
4561 bnxt_db_nq_arm(bp, &cpr->cp_db, cpr->cp_raw_cons);
4562 }
4563 }
4564
4565 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
4566 u16 cmpl_ring, u16 target_id)
4567 {
4568 struct input *req = request;
4569
4570 req->req_type = cpu_to_le16(req_type);
4571 req->cmpl_ring = cpu_to_le16(cmpl_ring);
4572 req->target_id = cpu_to_le16(target_id);
4573 if (bnxt_kong_hwrm_message(bp, req))
4574 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr);
4575 else
4576 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
4577 }
4578
4579 static int bnxt_hwrm_to_stderr(u32 hwrm_err)
4580 {
4581 switch (hwrm_err) {
4582 case HWRM_ERR_CODE_SUCCESS:
4583 return 0;
4584 case HWRM_ERR_CODE_RESOURCE_LOCKED:
4585 return -EROFS;
4586 case HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED:
4587 return -EACCES;
4588 case HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR:
4589 return -ENOSPC;
4590 case HWRM_ERR_CODE_INVALID_PARAMS:
4591 case HWRM_ERR_CODE_INVALID_FLAGS:
4592 case HWRM_ERR_CODE_INVALID_ENABLES:
4593 case HWRM_ERR_CODE_UNSUPPORTED_TLV:
4594 case HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR:
4595 return -EINVAL;
4596 case HWRM_ERR_CODE_NO_BUFFER:
4597 return -ENOMEM;
4598 case HWRM_ERR_CODE_HOT_RESET_PROGRESS:
4599 case HWRM_ERR_CODE_BUSY:
4600 return -EAGAIN;
4601 case HWRM_ERR_CODE_CMD_NOT_SUPPORTED:
4602 return -EOPNOTSUPP;
4603 default:
4604 return -EIO;
4605 }
4606 }
4607
4608 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
4609 int timeout, bool silent)
4610 {
4611 int i, intr_process, rc, tmo_count;
4612 struct input *req = msg;
4613 u32 *data = msg;
4614 u8 *valid;
4615 u16 cp_ring_id, len = 0;
4616 struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
4617 u16 max_req_len = BNXT_HWRM_MAX_REQ_LEN;
4618 struct hwrm_short_input short_input = {0};
4619 u32 doorbell_offset = BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER;
4620 u32 bar_offset = BNXT_GRCPF_REG_CHIMP_COMM;
4621 u16 dst = BNXT_HWRM_CHNL_CHIMP;
4622
4623 if (BNXT_NO_FW_ACCESS(bp) &&
4624 le16_to_cpu(req->req_type) != HWRM_FUNC_RESET)
4625 return -EBUSY;
4626
4627 if (msg_len > BNXT_HWRM_MAX_REQ_LEN) {
4628 if (msg_len > bp->hwrm_max_ext_req_len ||
4629 !bp->hwrm_short_cmd_req_addr)
4630 return -EINVAL;
4631 }
4632
4633 if (bnxt_hwrm_kong_chnl(bp, req)) {
4634 dst = BNXT_HWRM_CHNL_KONG;
4635 bar_offset = BNXT_GRCPF_REG_KONG_COMM;
4636 doorbell_offset = BNXT_GRCPF_REG_KONG_COMM_TRIGGER;
4637 resp = bp->hwrm_cmd_kong_resp_addr;
4638 }
4639
4640 memset(resp, 0, PAGE_SIZE);
4641 cp_ring_id = le16_to_cpu(req->cmpl_ring);
4642 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
4643
4644 req->seq_id = cpu_to_le16(bnxt_get_hwrm_seq_id(bp, dst));
4645 /* currently supports only one outstanding message */
4646 if (intr_process)
4647 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
4648
4649 if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) ||
4650 msg_len > BNXT_HWRM_MAX_REQ_LEN) {
4651 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
4652 u16 max_msg_len;
4653
4654 /* Set boundary for maximum extended request length for short
4655 * cmd format. If passed up from device use the max supported
4656 * internal req length.
4657 */
4658 max_msg_len = bp->hwrm_max_ext_req_len;
4659
4660 memcpy(short_cmd_req, req, msg_len);
4661 if (msg_len < max_msg_len)
4662 memset(short_cmd_req + msg_len, 0,
4663 max_msg_len - msg_len);
4664
4665 short_input.req_type = req->req_type;
4666 short_input.signature =
4667 cpu_to_le16(SHORT_REQ_SIGNATURE_SHORT_CMD);
4668 short_input.size = cpu_to_le16(msg_len);
4669 short_input.req_addr =
4670 cpu_to_le64(bp->hwrm_short_cmd_req_dma_addr);
4671
4672 data = (u32 *)&short_input;
4673 msg_len = sizeof(short_input);
4674
4675 /* Sync memory write before updating doorbell */
4676 wmb();
4677
4678 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
4679 }
4680
4681 /* Write request msg to hwrm channel */
4682 __iowrite32_copy(bp->bar0 + bar_offset, data, msg_len / 4);
4683
4684 for (i = msg_len; i < max_req_len; i += 4)
4685 writel(0, bp->bar0 + bar_offset + i);
4686
4687 /* Ring channel doorbell */
4688 writel(1, bp->bar0 + doorbell_offset);
4689
4690 if (!pci_is_enabled(bp->pdev))
4691 return -ENODEV;
4692
4693 if (!timeout)
4694 timeout = DFLT_HWRM_CMD_TIMEOUT;
4695 /* Limit timeout to an upper limit */
4696 timeout = min(timeout, HWRM_CMD_MAX_TIMEOUT);
4697 /* convert timeout to usec */
4698 timeout *= 1000;
4699
4700 i = 0;
4701 /* Short timeout for the first few iterations:
4702 * number of loops = number of loops for short timeout +
4703 * number of loops for standard timeout.
4704 */
4705 tmo_count = HWRM_SHORT_TIMEOUT_COUNTER;
4706 timeout = timeout - HWRM_SHORT_MIN_TIMEOUT * HWRM_SHORT_TIMEOUT_COUNTER;
4707 tmo_count += DIV_ROUND_UP(timeout, HWRM_MIN_TIMEOUT);
4708
4709 if (intr_process) {
4710 u16 seq_id = bp->hwrm_intr_seq_id;
4711
4712 /* Wait until hwrm response cmpl interrupt is processed */
4713 while (bp->hwrm_intr_seq_id != (u16)~seq_id &&
4714 i++ < tmo_count) {
4715 /* Abort the wait for completion if the FW health
4716 * check has failed.
4717 */
4718 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))
4719 return -EBUSY;
4720 /* on first few passes, just barely sleep */
4721 if (i < HWRM_SHORT_TIMEOUT_COUNTER) {
4722 usleep_range(HWRM_SHORT_MIN_TIMEOUT,
4723 HWRM_SHORT_MAX_TIMEOUT);
4724 } else {
4725 if (HWRM_WAIT_MUST_ABORT(bp, req))
4726 break;
4727 usleep_range(HWRM_MIN_TIMEOUT,
4728 HWRM_MAX_TIMEOUT);
4729 }
4730 }
4731
4732 if (bp->hwrm_intr_seq_id != (u16)~seq_id) {
4733 if (!silent)
4734 netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
4735 le16_to_cpu(req->req_type));
4736 return -EBUSY;
4737 }
4738 len = le16_to_cpu(resp->resp_len);
4739 valid = ((u8 *)resp) + len - 1;
4740 } else {
4741 int j;
4742
4743 /* Check if response len is updated */
4744 for (i = 0; i < tmo_count; i++) {
4745 /* Abort the wait for completion if the FW health
4746 * check has failed.
4747 */
4748 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))
4749 return -EBUSY;
4750 len = le16_to_cpu(resp->resp_len);
4751 if (len)
4752 break;
4753 /* on first few passes, just barely sleep */
4754 if (i < HWRM_SHORT_TIMEOUT_COUNTER) {
4755 usleep_range(HWRM_SHORT_MIN_TIMEOUT,
4756 HWRM_SHORT_MAX_TIMEOUT);
4757 } else {
4758 if (HWRM_WAIT_MUST_ABORT(bp, req))
4759 goto timeout_abort;
4760 usleep_range(HWRM_MIN_TIMEOUT,
4761 HWRM_MAX_TIMEOUT);
4762 }
4763 }
4764
4765 if (i >= tmo_count) {
4766 timeout_abort:
4767 if (!silent)
4768 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
4769 HWRM_TOTAL_TIMEOUT(i),
4770 le16_to_cpu(req->req_type),
4771 le16_to_cpu(req->seq_id), len);
4772 return -EBUSY;
4773 }
4774
4775 /* Last byte of resp contains valid bit */
4776 valid = ((u8 *)resp) + len - 1;
4777 for (j = 0; j < HWRM_VALID_BIT_DELAY_USEC; j++) {
4778 /* make sure we read from updated DMA memory */
4779 dma_rmb();
4780 if (*valid)
4781 break;
4782 usleep_range(1, 5);
4783 }
4784
4785 if (j >= HWRM_VALID_BIT_DELAY_USEC) {
4786 if (!silent)
4787 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
4788 HWRM_TOTAL_TIMEOUT(i),
4789 le16_to_cpu(req->req_type),
4790 le16_to_cpu(req->seq_id), len,
4791 *valid);
4792 return -EBUSY;
4793 }
4794 }
4795
4796 /* Zero valid bit for compatibility. Valid bit in an older spec
4797 * may become a new field in a newer spec. We must make sure that
4798 * a new field not implemented by old spec will read zero.
4799 */
4800 *valid = 0;
4801 rc = le16_to_cpu(resp->error_code);
4802 if (rc && !silent)
4803 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
4804 le16_to_cpu(resp->req_type),
4805 le16_to_cpu(resp->seq_id), rc);
4806 return bnxt_hwrm_to_stderr(rc);
4807 }
4808
4809 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
4810 {
4811 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
4812 }
4813
4814 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
4815 int timeout)
4816 {
4817 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
4818 }
4819
4820 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
4821 {
4822 int rc;
4823
4824 mutex_lock(&bp->hwrm_cmd_lock);
4825 rc = _hwrm_send_message(bp, msg, msg_len, timeout);
4826 mutex_unlock(&bp->hwrm_cmd_lock);
4827 return rc;
4828 }
4829
4830 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
4831 int timeout)
4832 {
4833 int rc;
4834
4835 mutex_lock(&bp->hwrm_cmd_lock);
4836 rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
4837 mutex_unlock(&bp->hwrm_cmd_lock);
4838 return rc;
4839 }
4840
4841 int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp, unsigned long *bmap, int bmap_size,
4842 bool async_only)
4843 {
4844 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
4845 struct hwrm_func_drv_rgtr_input req = {0};
4846 DECLARE_BITMAP(async_events_bmap, 256);
4847 u32 *events = (u32 *)async_events_bmap;
4848 u32 flags;
4849 int rc, i;
4850
4851 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
4852
4853 req.enables =
4854 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
4855 FUNC_DRV_RGTR_REQ_ENABLES_VER |
4856 FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
4857
4858 req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
4859 flags = FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE;
4860 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
4861 flags |= FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT;
4862 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
4863 flags |= FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT |
4864 FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT;
4865 req.flags = cpu_to_le32(flags);
4866 req.ver_maj_8b = DRV_VER_MAJ;
4867 req.ver_min_8b = DRV_VER_MIN;
4868 req.ver_upd_8b = DRV_VER_UPD;
4869 req.ver_maj = cpu_to_le16(DRV_VER_MAJ);
4870 req.ver_min = cpu_to_le16(DRV_VER_MIN);
4871 req.ver_upd = cpu_to_le16(DRV_VER_UPD);
4872
4873 if (BNXT_PF(bp)) {
4874 u32 data[8];
4875 int i;
4876
4877 memset(data, 0, sizeof(data));
4878 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) {
4879 u16 cmd = bnxt_vf_req_snif[i];
4880 unsigned int bit, idx;
4881
4882 idx = cmd / 32;
4883 bit = cmd % 32;
4884 data[idx] |= 1 << bit;
4885 }
4886
4887 for (i = 0; i < 8; i++)
4888 req.vf_req_fwd[i] = cpu_to_le32(data[i]);
4889
4890 req.enables |=
4891 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
4892 }
4893
4894 if (bp->fw_cap & BNXT_FW_CAP_OVS_64BIT_HANDLE)
4895 req.flags |= cpu_to_le32(
4896 FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE);
4897
4898 memset(async_events_bmap, 0, sizeof(async_events_bmap));
4899 for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++) {
4900 u16 event_id = bnxt_async_events_arr[i];
4901
4902 if (event_id == ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY &&
4903 !(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4904 continue;
4905 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
4906 }
4907 if (bmap && bmap_size) {
4908 for (i = 0; i < bmap_size; i++) {
4909 if (test_bit(i, bmap))
4910 __set_bit(i, async_events_bmap);
4911 }
4912 }
4913 for (i = 0; i < 8; i++)
4914 req.async_event_fwd[i] |= cpu_to_le32(events[i]);
4915
4916 if (async_only)
4917 req.enables =
4918 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
4919
4920 mutex_lock(&bp->hwrm_cmd_lock);
4921 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4922 if (!rc) {
4923 set_bit(BNXT_STATE_DRV_REGISTERED, &bp->state);
4924 if (resp->flags &
4925 cpu_to_le32(FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED))
4926 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
4927 }
4928 mutex_unlock(&bp->hwrm_cmd_lock);
4929 return rc;
4930 }
4931
4932 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
4933 {
4934 struct hwrm_func_drv_unrgtr_input req = {0};
4935
4936 if (!test_and_clear_bit(BNXT_STATE_DRV_REGISTERED, &bp->state))
4937 return 0;
4938
4939 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
4940 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4941 }
4942
4943 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
4944 {
4945 u32 rc = 0;
4946 struct hwrm_tunnel_dst_port_free_input req = {0};
4947
4948 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
4949 req.tunnel_type = tunnel_type;
4950
4951 switch (tunnel_type) {
4952 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
4953 req.tunnel_dst_port_id = cpu_to_le16(bp->vxlan_fw_dst_port_id);
4954 bp->vxlan_fw_dst_port_id = INVALID_HW_RING_ID;
4955 break;
4956 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
4957 req.tunnel_dst_port_id = cpu_to_le16(bp->nge_fw_dst_port_id);
4958 bp->nge_fw_dst_port_id = INVALID_HW_RING_ID;
4959 break;
4960 default:
4961 break;
4962 }
4963
4964 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4965 if (rc)
4966 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
4967 rc);
4968 return rc;
4969 }
4970
4971 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
4972 u8 tunnel_type)
4973 {
4974 u32 rc = 0;
4975 struct hwrm_tunnel_dst_port_alloc_input req = {0};
4976 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4977
4978 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
4979
4980 req.tunnel_type = tunnel_type;
4981 req.tunnel_dst_port_val = port;
4982
4983 mutex_lock(&bp->hwrm_cmd_lock);
4984 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4985 if (rc) {
4986 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
4987 rc);
4988 goto err_out;
4989 }
4990
4991 switch (tunnel_type) {
4992 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN:
4993 bp->vxlan_fw_dst_port_id =
4994 le16_to_cpu(resp->tunnel_dst_port_id);
4995 break;
4996 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE:
4997 bp->nge_fw_dst_port_id = le16_to_cpu(resp->tunnel_dst_port_id);
4998 break;
4999 default:
5000 break;
5001 }
5002
5003 err_out:
5004 mutex_unlock(&bp->hwrm_cmd_lock);
5005 return rc;
5006 }
5007
5008 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
5009 {
5010 struct hwrm_cfa_l2_set_rx_mask_input req = {0};
5011 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5012
5013 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
5014 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
5015
5016 req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
5017 req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
5018 req.mask = cpu_to_le32(vnic->rx_mask);
5019 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5020 }
5021
5022 #ifdef CONFIG_RFS_ACCEL
5023 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
5024 struct bnxt_ntuple_filter *fltr)
5025 {
5026 struct hwrm_cfa_ntuple_filter_free_input req = {0};
5027
5028 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
5029 req.ntuple_filter_id = fltr->filter_id;
5030 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5031 }
5032
5033 #define BNXT_NTP_FLTR_FLAGS \
5034 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
5035 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
5036 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
5037 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
5038 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
5039 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
5040 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
5041 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
5042 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
5043 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
5044 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
5045 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
5046 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
5047 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
5048
5049 #define BNXT_NTP_TUNNEL_FLTR_FLAG \
5050 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE
5051
5052 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
5053 struct bnxt_ntuple_filter *fltr)
5054 {
5055 struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
5056 struct hwrm_cfa_ntuple_filter_alloc_output *resp;
5057 struct flow_keys *keys = &fltr->fkeys;
5058 struct bnxt_vnic_info *vnic;
5059 u32 flags = 0;
5060 int rc = 0;
5061
5062 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
5063 req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx];
5064
5065 if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2) {
5066 flags = CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_RFS_RING_IDX;
5067 req.dst_id = cpu_to_le16(fltr->rxq);
5068 } else {
5069 vnic = &bp->vnic_info[fltr->rxq + 1];
5070 req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
5071 }
5072 req.flags = cpu_to_le32(flags);
5073 req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
5074
5075 req.ethertype = htons(ETH_P_IP);
5076 memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
5077 req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
5078 req.ip_protocol = keys->basic.ip_proto;
5079
5080 if (keys->basic.n_proto == htons(ETH_P_IPV6)) {
5081 int i;
5082
5083 req.ethertype = htons(ETH_P_IPV6);
5084 req.ip_addr_type =
5085 CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6;
5086 *(struct in6_addr *)&req.src_ipaddr[0] =
5087 keys->addrs.v6addrs.src;
5088 *(struct in6_addr *)&req.dst_ipaddr[0] =
5089 keys->addrs.v6addrs.dst;
5090 for (i = 0; i < 4; i++) {
5091 req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
5092 req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
5093 }
5094 } else {
5095 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
5096 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
5097 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
5098 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
5099 }
5100 if (keys->control.flags & FLOW_DIS_ENCAPSULATION) {
5101 req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG);
5102 req.tunnel_type =
5103 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL;
5104 }
5105
5106 req.src_port = keys->ports.src;
5107 req.src_port_mask = cpu_to_be16(0xffff);
5108 req.dst_port = keys->ports.dst;
5109 req.dst_port_mask = cpu_to_be16(0xffff);
5110
5111 mutex_lock(&bp->hwrm_cmd_lock);
5112 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5113 if (!rc) {
5114 resp = bnxt_get_hwrm_resp_addr(bp, &req);
5115 fltr->filter_id = resp->ntuple_filter_id;
5116 }
5117 mutex_unlock(&bp->hwrm_cmd_lock);
5118 return rc;
5119 }
5120 #endif
5121
5122 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
5123 u8 *mac_addr)
5124 {
5125 u32 rc = 0;
5126 struct hwrm_cfa_l2_filter_alloc_input req = {0};
5127 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5128
5129 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
5130 req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX);
5131 if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
5132 req.flags |=
5133 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
5134 req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
5135 req.enables =
5136 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
5137 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
5138 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
5139 memcpy(req.l2_addr, mac_addr, ETH_ALEN);
5140 req.l2_addr_mask[0] = 0xff;
5141 req.l2_addr_mask[1] = 0xff;
5142 req.l2_addr_mask[2] = 0xff;
5143 req.l2_addr_mask[3] = 0xff;
5144 req.l2_addr_mask[4] = 0xff;
5145 req.l2_addr_mask[5] = 0xff;
5146
5147 mutex_lock(&bp->hwrm_cmd_lock);
5148 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5149 if (!rc)
5150 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
5151 resp->l2_filter_id;
5152 mutex_unlock(&bp->hwrm_cmd_lock);
5153 return rc;
5154 }
5155
5156 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
5157 {
5158 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
5159 int rc = 0;
5160
5161 /* Any associated ntuple filters will also be cleared by firmware. */
5162 mutex_lock(&bp->hwrm_cmd_lock);
5163 for (i = 0; i < num_of_vnics; i++) {
5164 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
5165
5166 for (j = 0; j < vnic->uc_filter_count; j++) {
5167 struct hwrm_cfa_l2_filter_free_input req = {0};
5168
5169 bnxt_hwrm_cmd_hdr_init(bp, &req,
5170 HWRM_CFA_L2_FILTER_FREE, -1, -1);
5171
5172 req.l2_filter_id = vnic->fw_l2_filter_id[j];
5173
5174 rc = _hwrm_send_message(bp, &req, sizeof(req),
5175 HWRM_CMD_TIMEOUT);
5176 }
5177 vnic->uc_filter_count = 0;
5178 }
5179 mutex_unlock(&bp->hwrm_cmd_lock);
5180
5181 return rc;
5182 }
5183
5184 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
5185 {
5186 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5187 u16 max_aggs = VNIC_TPA_CFG_REQ_MAX_AGGS_MAX;
5188 struct hwrm_vnic_tpa_cfg_input req = {0};
5189
5190 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
5191 return 0;
5192
5193 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
5194
5195 if (tpa_flags) {
5196 u16 mss = bp->dev->mtu - 40;
5197 u32 nsegs, n, segs = 0, flags;
5198
5199 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
5200 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
5201 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
5202 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
5203 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
5204 if (tpa_flags & BNXT_FLAG_GRO)
5205 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
5206
5207 req.flags = cpu_to_le32(flags);
5208
5209 req.enables =
5210 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
5211 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
5212 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
5213
5214 /* Number of segs are log2 units, and first packet is not
5215 * included as part of this units.
5216 */
5217 if (mss <= BNXT_RX_PAGE_SIZE) {
5218 n = BNXT_RX_PAGE_SIZE / mss;
5219 nsegs = (MAX_SKB_FRAGS - 1) * n;
5220 } else {
5221 n = mss / BNXT_RX_PAGE_SIZE;
5222 if (mss & (BNXT_RX_PAGE_SIZE - 1))
5223 n++;
5224 nsegs = (MAX_SKB_FRAGS - n) / n;
5225 }
5226
5227 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5228 segs = MAX_TPA_SEGS_P5;
5229 max_aggs = bp->max_tpa;
5230 } else {
5231 segs = ilog2(nsegs);
5232 }
5233 req.max_agg_segs = cpu_to_le16(segs);
5234 req.max_aggs = cpu_to_le16(max_aggs);
5235
5236 req.min_agg_len = cpu_to_le32(512);
5237 }
5238 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
5239
5240 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5241 }
5242
5243 static u16 bnxt_cp_ring_from_grp(struct bnxt *bp, struct bnxt_ring_struct *ring)
5244 {
5245 struct bnxt_ring_grp_info *grp_info;
5246
5247 grp_info = &bp->grp_info[ring->grp_idx];
5248 return grp_info->cp_fw_ring_id;
5249 }
5250
5251 static u16 bnxt_cp_ring_for_rx(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
5252 {
5253 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5254 struct bnxt_napi *bnapi = rxr->bnapi;
5255 struct bnxt_cp_ring_info *cpr;
5256
5257 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_RX_HDL];
5258 return cpr->cp_ring_struct.fw_ring_id;
5259 } else {
5260 return bnxt_cp_ring_from_grp(bp, &rxr->rx_ring_struct);
5261 }
5262 }
5263
5264 static u16 bnxt_cp_ring_for_tx(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
5265 {
5266 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5267 struct bnxt_napi *bnapi = txr->bnapi;
5268 struct bnxt_cp_ring_info *cpr;
5269
5270 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_TX_HDL];
5271 return cpr->cp_ring_struct.fw_ring_id;
5272 } else {
5273 return bnxt_cp_ring_from_grp(bp, &txr->tx_ring_struct);
5274 }
5275 }
5276
5277 static int bnxt_alloc_rss_indir_tbl(struct bnxt *bp)
5278 {
5279 int entries;
5280
5281 if (bp->flags & BNXT_FLAG_CHIP_P5)
5282 entries = BNXT_MAX_RSS_TABLE_ENTRIES_P5;
5283 else
5284 entries = HW_HASH_INDEX_SIZE;
5285
5286 bp->rss_indir_tbl_entries = entries;
5287 bp->rss_indir_tbl = kmalloc_array(entries, sizeof(*bp->rss_indir_tbl),
5288 GFP_KERNEL);
5289 if (!bp->rss_indir_tbl)
5290 return -ENOMEM;
5291 return 0;
5292 }
5293
5294 static void bnxt_set_dflt_rss_indir_tbl(struct bnxt *bp)
5295 {
5296 u16 max_rings, max_entries, pad, i;
5297
5298 if (!bp->rx_nr_rings)
5299 return;
5300
5301 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5302 max_rings = bp->rx_nr_rings - 1;
5303 else
5304 max_rings = bp->rx_nr_rings;
5305
5306 max_entries = bnxt_get_rxfh_indir_size(bp->dev);
5307
5308 for (i = 0; i < max_entries; i++)
5309 bp->rss_indir_tbl[i] = ethtool_rxfh_indir_default(i, max_rings);
5310
5311 pad = bp->rss_indir_tbl_entries - max_entries;
5312 if (pad)
5313 memset(&bp->rss_indir_tbl[i], 0, pad * sizeof(u16));
5314 }
5315
5316 static u16 bnxt_get_max_rss_ring(struct bnxt *bp)
5317 {
5318 u16 i, tbl_size, max_ring = 0;
5319
5320 if (!bp->rss_indir_tbl)
5321 return 0;
5322
5323 tbl_size = bnxt_get_rxfh_indir_size(bp->dev);
5324 for (i = 0; i < tbl_size; i++)
5325 max_ring = max(max_ring, bp->rss_indir_tbl[i]);
5326 return max_ring;
5327 }
5328
5329 int bnxt_get_nr_rss_ctxs(struct bnxt *bp, int rx_rings)
5330 {
5331 if (bp->flags & BNXT_FLAG_CHIP_P5)
5332 return DIV_ROUND_UP(rx_rings, BNXT_RSS_TABLE_ENTRIES_P5);
5333 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5334 return 2;
5335 return 1;
5336 }
5337
5338 static void __bnxt_fill_hw_rss_tbl(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5339 {
5340 bool no_rss = !(vnic->flags & BNXT_VNIC_RSS_FLAG);
5341 u16 i, j;
5342
5343 /* Fill the RSS indirection table with ring group ids */
5344 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++) {
5345 if (!no_rss)
5346 j = bp->rss_indir_tbl[i];
5347 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
5348 }
5349 }
5350
5351 static void __bnxt_fill_hw_rss_tbl_p5(struct bnxt *bp,
5352 struct bnxt_vnic_info *vnic)
5353 {
5354 __le16 *ring_tbl = vnic->rss_table;
5355 struct bnxt_rx_ring_info *rxr;
5356 u16 tbl_size, i;
5357
5358 tbl_size = bnxt_get_rxfh_indir_size(bp->dev);
5359
5360 for (i = 0; i < tbl_size; i++) {
5361 u16 ring_id, j;
5362
5363 j = bp->rss_indir_tbl[i];
5364 rxr = &bp->rx_ring[j];
5365
5366 ring_id = rxr->rx_ring_struct.fw_ring_id;
5367 *ring_tbl++ = cpu_to_le16(ring_id);
5368 ring_id = bnxt_cp_ring_for_rx(bp, rxr);
5369 *ring_tbl++ = cpu_to_le16(ring_id);
5370 }
5371 }
5372
5373 static void bnxt_fill_hw_rss_tbl(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5374 {
5375 if (bp->flags & BNXT_FLAG_CHIP_P5)
5376 __bnxt_fill_hw_rss_tbl_p5(bp, vnic);
5377 else
5378 __bnxt_fill_hw_rss_tbl(bp, vnic);
5379 }
5380
5381 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
5382 {
5383 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5384 struct hwrm_vnic_rss_cfg_input req = {0};
5385
5386 if ((bp->flags & BNXT_FLAG_CHIP_P5) ||
5387 vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)
5388 return 0;
5389
5390 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
5391 if (set_rss) {
5392 bnxt_fill_hw_rss_tbl(bp, vnic);
5393 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
5394 req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT;
5395 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
5396 req.hash_key_tbl_addr =
5397 cpu_to_le64(vnic->rss_hash_key_dma_addr);
5398 }
5399 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
5400 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5401 }
5402
5403 static int bnxt_hwrm_vnic_set_rss_p5(struct bnxt *bp, u16 vnic_id, bool set_rss)
5404 {
5405 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5406 struct hwrm_vnic_rss_cfg_input req = {0};
5407 dma_addr_t ring_tbl_map;
5408 u32 i, nr_ctxs;
5409
5410 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
5411 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
5412 if (!set_rss) {
5413 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5414 return 0;
5415 }
5416 bnxt_fill_hw_rss_tbl(bp, vnic);
5417 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
5418 req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT;
5419 req.hash_key_tbl_addr = cpu_to_le64(vnic->rss_hash_key_dma_addr);
5420 ring_tbl_map = vnic->rss_table_dma_addr;
5421 nr_ctxs = bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings);
5422 for (i = 0; i < nr_ctxs; ring_tbl_map += BNXT_RSS_TABLE_SIZE_P5, i++) {
5423 int rc;
5424
5425 req.ring_grp_tbl_addr = cpu_to_le64(ring_tbl_map);
5426 req.ring_table_pair_index = i;
5427 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[i]);
5428 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5429 if (rc)
5430 return rc;
5431 }
5432 return 0;
5433 }
5434
5435 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
5436 {
5437 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5438 struct hwrm_vnic_plcmodes_cfg_input req = {0};
5439
5440 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
5441 req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
5442 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
5443 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
5444 req.enables =
5445 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
5446 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
5447 /* thresholds not implemented in firmware yet */
5448 req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
5449 req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
5450 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
5451 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5452 }
5453
5454 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id,
5455 u16 ctx_idx)
5456 {
5457 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
5458
5459 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
5460 req.rss_cos_lb_ctx_id =
5461 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]);
5462
5463 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5464 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID;
5465 }
5466
5467 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
5468 {
5469 int i, j;
5470
5471 for (i = 0; i < bp->nr_vnics; i++) {
5472 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
5473
5474 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) {
5475 if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID)
5476 bnxt_hwrm_vnic_ctx_free_one(bp, i, j);
5477 }
5478 }
5479 bp->rsscos_nr_ctxs = 0;
5480 }
5481
5482 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx)
5483 {
5484 int rc;
5485 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
5486 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
5487 bp->hwrm_cmd_resp_addr;
5488
5489 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
5490 -1);
5491
5492 mutex_lock(&bp->hwrm_cmd_lock);
5493 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5494 if (!rc)
5495 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] =
5496 le16_to_cpu(resp->rss_cos_lb_ctx_id);
5497 mutex_unlock(&bp->hwrm_cmd_lock);
5498
5499 return rc;
5500 }
5501
5502 static u32 bnxt_get_roce_vnic_mode(struct bnxt *bp)
5503 {
5504 if (bp->flags & BNXT_FLAG_ROCE_MIRROR_CAP)
5505 return VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE;
5506 return VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE;
5507 }
5508
5509 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
5510 {
5511 unsigned int ring = 0, grp_idx;
5512 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5513 struct hwrm_vnic_cfg_input req = {0};
5514 u16 def_vlan = 0;
5515
5516 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
5517
5518 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5519 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0];
5520
5521 req.default_rx_ring_id =
5522 cpu_to_le16(rxr->rx_ring_struct.fw_ring_id);
5523 req.default_cmpl_ring_id =
5524 cpu_to_le16(bnxt_cp_ring_for_rx(bp, rxr));
5525 req.enables =
5526 cpu_to_le32(VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID |
5527 VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID);
5528 goto vnic_mru;
5529 }
5530 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP);
5531 /* Only RSS support for now TBD: COS & LB */
5532 if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) {
5533 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
5534 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
5535 VNIC_CFG_REQ_ENABLES_MRU);
5536 } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) {
5537 req.rss_rule =
5538 cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]);
5539 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
5540 VNIC_CFG_REQ_ENABLES_MRU);
5541 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE);
5542 } else {
5543 req.rss_rule = cpu_to_le16(0xffff);
5544 }
5545
5546 if (BNXT_CHIP_TYPE_NITRO_A0(bp) &&
5547 (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) {
5548 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]);
5549 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE);
5550 } else {
5551 req.cos_rule = cpu_to_le16(0xffff);
5552 }
5553
5554 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
5555 ring = 0;
5556 else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
5557 ring = vnic_id - 1;
5558 else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp))
5559 ring = bp->rx_nr_rings - 1;
5560
5561 grp_idx = bp->rx_ring[ring].bnapi->index;
5562 req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
5563 req.lb_rule = cpu_to_le16(0xffff);
5564 vnic_mru:
5565 req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + VLAN_HLEN);
5566
5567 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
5568 #ifdef CONFIG_BNXT_SRIOV
5569 if (BNXT_VF(bp))
5570 def_vlan = bp->vf.vlan;
5571 #endif
5572 if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
5573 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
5574 if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP))
5575 req.flags |= cpu_to_le32(bnxt_get_roce_vnic_mode(bp));
5576
5577 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5578 }
5579
5580 static void bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
5581 {
5582 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
5583 struct hwrm_vnic_free_input req = {0};
5584
5585 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
5586 req.vnic_id =
5587 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
5588
5589 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5590 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
5591 }
5592 }
5593
5594 static void bnxt_hwrm_vnic_free(struct bnxt *bp)
5595 {
5596 u16 i;
5597
5598 for (i = 0; i < bp->nr_vnics; i++)
5599 bnxt_hwrm_vnic_free_one(bp, i);
5600 }
5601
5602 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
5603 unsigned int start_rx_ring_idx,
5604 unsigned int nr_rings)
5605 {
5606 int rc = 0;
5607 unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
5608 struct hwrm_vnic_alloc_input req = {0};
5609 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5610 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5611
5612 if (bp->flags & BNXT_FLAG_CHIP_P5)
5613 goto vnic_no_ring_grps;
5614
5615 /* map ring groups to this vnic */
5616 for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
5617 grp_idx = bp->rx_ring[i].bnapi->index;
5618 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
5619 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
5620 j, nr_rings);
5621 break;
5622 }
5623 vnic->fw_grp_ids[j] = bp->grp_info[grp_idx].fw_grp_id;
5624 }
5625
5626 vnic_no_ring_grps:
5627 for (i = 0; i < BNXT_MAX_CTX_PER_VNIC; i++)
5628 vnic->fw_rss_cos_lb_ctx[i] = INVALID_HW_RING_ID;
5629 if (vnic_id == 0)
5630 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
5631
5632 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
5633
5634 mutex_lock(&bp->hwrm_cmd_lock);
5635 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5636 if (!rc)
5637 vnic->fw_vnic_id = le32_to_cpu(resp->vnic_id);
5638 mutex_unlock(&bp->hwrm_cmd_lock);
5639 return rc;
5640 }
5641
5642 static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
5643 {
5644 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5645 struct hwrm_vnic_qcaps_input req = {0};
5646 int rc;
5647
5648 bp->hw_ring_stats_size = sizeof(struct ctx_hw_stats);
5649 bp->flags &= ~(BNXT_FLAG_NEW_RSS_CAP | BNXT_FLAG_ROCE_MIRROR_CAP);
5650 if (bp->hwrm_spec_code < 0x10600)
5651 return 0;
5652
5653 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1);
5654 mutex_lock(&bp->hwrm_cmd_lock);
5655 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5656 if (!rc) {
5657 u32 flags = le32_to_cpu(resp->flags);
5658
5659 if (!(bp->flags & BNXT_FLAG_CHIP_P5) &&
5660 (flags & VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP))
5661 bp->flags |= BNXT_FLAG_NEW_RSS_CAP;
5662 if (flags &
5663 VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP)
5664 bp->flags |= BNXT_FLAG_ROCE_MIRROR_CAP;
5665
5666 /* Older P5 fw before EXT_HW_STATS support did not set
5667 * VLAN_STRIP_CAP properly.
5668 */
5669 if ((flags & VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP) ||
5670 (BNXT_CHIP_P5_THOR(bp) &&
5671 !(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED)))
5672 bp->fw_cap |= BNXT_FW_CAP_VLAN_RX_STRIP;
5673 bp->max_tpa_v2 = le16_to_cpu(resp->max_aggs_supported);
5674 if (bp->max_tpa_v2) {
5675 if (BNXT_CHIP_P5_THOR(bp))
5676 bp->hw_ring_stats_size = BNXT_RING_STATS_SIZE_P5;
5677 else
5678 bp->hw_ring_stats_size = BNXT_RING_STATS_SIZE_P5_SR2;
5679 }
5680 }
5681 mutex_unlock(&bp->hwrm_cmd_lock);
5682 return rc;
5683 }
5684
5685 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
5686 {
5687 u16 i;
5688 u32 rc = 0;
5689
5690 if (bp->flags & BNXT_FLAG_CHIP_P5)
5691 return 0;
5692
5693 mutex_lock(&bp->hwrm_cmd_lock);
5694 for (i = 0; i < bp->rx_nr_rings; i++) {
5695 struct hwrm_ring_grp_alloc_input req = {0};
5696 struct hwrm_ring_grp_alloc_output *resp =
5697 bp->hwrm_cmd_resp_addr;
5698 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
5699
5700 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
5701
5702 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
5703 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
5704 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
5705 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
5706
5707 rc = _hwrm_send_message(bp, &req, sizeof(req),
5708 HWRM_CMD_TIMEOUT);
5709 if (rc)
5710 break;
5711
5712 bp->grp_info[grp_idx].fw_grp_id =
5713 le32_to_cpu(resp->ring_group_id);
5714 }
5715 mutex_unlock(&bp->hwrm_cmd_lock);
5716 return rc;
5717 }
5718
5719 static void bnxt_hwrm_ring_grp_free(struct bnxt *bp)
5720 {
5721 u16 i;
5722 struct hwrm_ring_grp_free_input req = {0};
5723
5724 if (!bp->grp_info || (bp->flags & BNXT_FLAG_CHIP_P5))
5725 return;
5726
5727 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
5728
5729 mutex_lock(&bp->hwrm_cmd_lock);
5730 for (i = 0; i < bp->cp_nr_rings; i++) {
5731 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
5732 continue;
5733 req.ring_group_id =
5734 cpu_to_le32(bp->grp_info[i].fw_grp_id);
5735
5736 _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5737 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
5738 }
5739 mutex_unlock(&bp->hwrm_cmd_lock);
5740 }
5741
5742 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
5743 struct bnxt_ring_struct *ring,
5744 u32 ring_type, u32 map_index)
5745 {
5746 int rc = 0, err = 0;
5747 struct hwrm_ring_alloc_input req = {0};
5748 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5749 struct bnxt_ring_mem_info *rmem = &ring->ring_mem;
5750 struct bnxt_ring_grp_info *grp_info;
5751 u16 ring_id;
5752
5753 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
5754
5755 req.enables = 0;
5756 if (rmem->nr_pages > 1) {
5757 req.page_tbl_addr = cpu_to_le64(rmem->pg_tbl_map);
5758 /* Page size is in log2 units */
5759 req.page_size = BNXT_PAGE_SHIFT;
5760 req.page_tbl_depth = 1;
5761 } else {
5762 req.page_tbl_addr = cpu_to_le64(rmem->dma_arr[0]);
5763 }
5764 req.fbo = 0;
5765 /* Association of ring index with doorbell index and MSIX number */
5766 req.logical_id = cpu_to_le16(map_index);
5767
5768 switch (ring_type) {
5769 case HWRM_RING_ALLOC_TX: {
5770 struct bnxt_tx_ring_info *txr;
5771
5772 txr = container_of(ring, struct bnxt_tx_ring_info,
5773 tx_ring_struct);
5774 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
5775 /* Association of transmit ring with completion ring */
5776 grp_info = &bp->grp_info[ring->grp_idx];
5777 req.cmpl_ring_id = cpu_to_le16(bnxt_cp_ring_for_tx(bp, txr));
5778 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
5779 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
5780 req.queue_id = cpu_to_le16(ring->queue_id);
5781 break;
5782 }
5783 case HWRM_RING_ALLOC_RX:
5784 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
5785 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
5786 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5787 u16 flags = 0;
5788
5789 /* Association of rx ring with stats context */
5790 grp_info = &bp->grp_info[ring->grp_idx];
5791 req.rx_buf_size = cpu_to_le16(bp->rx_buf_use_size);
5792 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
5793 req.enables |= cpu_to_le32(
5794 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID);
5795 if (NET_IP_ALIGN == 2)
5796 flags = RING_ALLOC_REQ_FLAGS_RX_SOP_PAD;
5797 req.flags = cpu_to_le16(flags);
5798 }
5799 break;
5800 case HWRM_RING_ALLOC_AGG:
5801 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5802 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX_AGG;
5803 /* Association of agg ring with rx ring */
5804 grp_info = &bp->grp_info[ring->grp_idx];
5805 req.rx_ring_id = cpu_to_le16(grp_info->rx_fw_ring_id);
5806 req.rx_buf_size = cpu_to_le16(BNXT_RX_PAGE_SIZE);
5807 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
5808 req.enables |= cpu_to_le32(
5809 RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID |
5810 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID);
5811 } else {
5812 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
5813 }
5814 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
5815 break;
5816 case HWRM_RING_ALLOC_CMPL:
5817 req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL;
5818 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
5819 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5820 /* Association of cp ring with nq */
5821 grp_info = &bp->grp_info[map_index];
5822 req.nq_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id);
5823 req.cq_handle = cpu_to_le64(ring->handle);
5824 req.enables |= cpu_to_le32(
5825 RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID);
5826 } else if (bp->flags & BNXT_FLAG_USING_MSIX) {
5827 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
5828 }
5829 break;
5830 case HWRM_RING_ALLOC_NQ:
5831 req.ring_type = RING_ALLOC_REQ_RING_TYPE_NQ;
5832 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
5833 if (bp->flags & BNXT_FLAG_USING_MSIX)
5834 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
5835 break;
5836 default:
5837 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
5838 ring_type);
5839 return -1;
5840 }
5841
5842 mutex_lock(&bp->hwrm_cmd_lock);
5843 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5844 err = le16_to_cpu(resp->error_code);
5845 ring_id = le16_to_cpu(resp->ring_id);
5846 mutex_unlock(&bp->hwrm_cmd_lock);
5847
5848 if (rc || err) {
5849 netdev_err(bp->dev, "hwrm_ring_alloc type %d failed. rc:%x err:%x\n",
5850 ring_type, rc, err);
5851 return -EIO;
5852 }
5853 ring->fw_ring_id = ring_id;
5854 return rc;
5855 }
5856
5857 static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx)
5858 {
5859 int rc;
5860
5861 if (BNXT_PF(bp)) {
5862 struct hwrm_func_cfg_input req = {0};
5863
5864 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
5865 req.fid = cpu_to_le16(0xffff);
5866 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
5867 req.async_event_cr = cpu_to_le16(idx);
5868 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5869 } else {
5870 struct hwrm_func_vf_cfg_input req = {0};
5871
5872 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1);
5873 req.enables =
5874 cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
5875 req.async_event_cr = cpu_to_le16(idx);
5876 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5877 }
5878 return rc;
5879 }
5880
5881 static void bnxt_set_db(struct bnxt *bp, struct bnxt_db_info *db, u32 ring_type,
5882 u32 map_idx, u32 xid)
5883 {
5884 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5885 if (BNXT_PF(bp))
5886 db->doorbell = bp->bar1 + DB_PF_OFFSET_P5;
5887 else
5888 db->doorbell = bp->bar1 + DB_VF_OFFSET_P5;
5889 switch (ring_type) {
5890 case HWRM_RING_ALLOC_TX:
5891 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SQ;
5892 break;
5893 case HWRM_RING_ALLOC_RX:
5894 case HWRM_RING_ALLOC_AGG:
5895 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SRQ;
5896 break;
5897 case HWRM_RING_ALLOC_CMPL:
5898 db->db_key64 = DBR_PATH_L2;
5899 break;
5900 case HWRM_RING_ALLOC_NQ:
5901 db->db_key64 = DBR_PATH_L2;
5902 break;
5903 }
5904 db->db_key64 |= (u64)xid << DBR_XID_SFT;
5905 } else {
5906 db->doorbell = bp->bar1 + map_idx * 0x80;
5907 switch (ring_type) {
5908 case HWRM_RING_ALLOC_TX:
5909 db->db_key32 = DB_KEY_TX;
5910 break;
5911 case HWRM_RING_ALLOC_RX:
5912 case HWRM_RING_ALLOC_AGG:
5913 db->db_key32 = DB_KEY_RX;
5914 break;
5915 case HWRM_RING_ALLOC_CMPL:
5916 db->db_key32 = DB_KEY_CP;
5917 break;
5918 }
5919 }
5920 }
5921
5922 static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
5923 {
5924 bool agg_rings = !!(bp->flags & BNXT_FLAG_AGG_RINGS);
5925 int i, rc = 0;
5926 u32 type;
5927
5928 if (bp->flags & BNXT_FLAG_CHIP_P5)
5929 type = HWRM_RING_ALLOC_NQ;
5930 else
5931 type = HWRM_RING_ALLOC_CMPL;
5932 for (i = 0; i < bp->cp_nr_rings; i++) {
5933 struct bnxt_napi *bnapi = bp->bnapi[i];
5934 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5935 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
5936 u32 map_idx = ring->map_idx;
5937 unsigned int vector;
5938
5939 vector = bp->irq_tbl[map_idx].vector;
5940 disable_irq_nosync(vector);
5941 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5942 if (rc) {
5943 enable_irq(vector);
5944 goto err_out;
5945 }
5946 bnxt_set_db(bp, &cpr->cp_db, type, map_idx, ring->fw_ring_id);
5947 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons);
5948 enable_irq(vector);
5949 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
5950
5951 if (!i) {
5952 rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id);
5953 if (rc)
5954 netdev_warn(bp->dev, "Failed to set async event completion ring.\n");
5955 }
5956 }
5957
5958 type = HWRM_RING_ALLOC_TX;
5959 for (i = 0; i < bp->tx_nr_rings; i++) {
5960 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
5961 struct bnxt_ring_struct *ring;
5962 u32 map_idx;
5963
5964 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5965 struct bnxt_napi *bnapi = txr->bnapi;
5966 struct bnxt_cp_ring_info *cpr, *cpr2;
5967 u32 type2 = HWRM_RING_ALLOC_CMPL;
5968
5969 cpr = &bnapi->cp_ring;
5970 cpr2 = cpr->cp_ring_arr[BNXT_TX_HDL];
5971 ring = &cpr2->cp_ring_struct;
5972 ring->handle = BNXT_TX_HDL;
5973 map_idx = bnapi->index;
5974 rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx);
5975 if (rc)
5976 goto err_out;
5977 bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx,
5978 ring->fw_ring_id);
5979 bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons);
5980 }
5981 ring = &txr->tx_ring_struct;
5982 map_idx = i;
5983 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5984 if (rc)
5985 goto err_out;
5986 bnxt_set_db(bp, &txr->tx_db, type, map_idx, ring->fw_ring_id);
5987 }
5988
5989 type = HWRM_RING_ALLOC_RX;
5990 for (i = 0; i < bp->rx_nr_rings; i++) {
5991 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5992 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
5993 struct bnxt_napi *bnapi = rxr->bnapi;
5994 u32 map_idx = bnapi->index;
5995
5996 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5997 if (rc)
5998 goto err_out;
5999 bnxt_set_db(bp, &rxr->rx_db, type, map_idx, ring->fw_ring_id);
6000 /* If we have agg rings, post agg buffers first. */
6001 if (!agg_rings)
6002 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
6003 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
6004 if (bp->flags & BNXT_FLAG_CHIP_P5) {
6005 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6006 u32 type2 = HWRM_RING_ALLOC_CMPL;
6007 struct bnxt_cp_ring_info *cpr2;
6008
6009 cpr2 = cpr->cp_ring_arr[BNXT_RX_HDL];
6010 ring = &cpr2->cp_ring_struct;
6011 ring->handle = BNXT_RX_HDL;
6012 rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx);
6013 if (rc)
6014 goto err_out;
6015 bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx,
6016 ring->fw_ring_id);
6017 bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons);
6018 }
6019 }
6020
6021 if (agg_rings) {
6022 type = HWRM_RING_ALLOC_AGG;
6023 for (i = 0; i < bp->rx_nr_rings; i++) {
6024 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
6025 struct bnxt_ring_struct *ring =
6026 &rxr->rx_agg_ring_struct;
6027 u32 grp_idx = ring->grp_idx;
6028 u32 map_idx = grp_idx + bp->rx_nr_rings;
6029
6030 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
6031 if (rc)
6032 goto err_out;
6033
6034 bnxt_set_db(bp, &rxr->rx_agg_db, type, map_idx,
6035 ring->fw_ring_id);
6036 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
6037 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
6038 bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
6039 }
6040 }
6041 err_out:
6042 return rc;
6043 }
6044
6045 static int hwrm_ring_free_send_msg(struct bnxt *bp,
6046 struct bnxt_ring_struct *ring,
6047 u32 ring_type, int cmpl_ring_id)
6048 {
6049 int rc;
6050 struct hwrm_ring_free_input req = {0};
6051 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
6052 u16 error_code;
6053
6054 if (BNXT_NO_FW_ACCESS(bp))
6055 return 0;
6056
6057 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
6058 req.ring_type = ring_type;
6059 req.ring_id = cpu_to_le16(ring->fw_ring_id);
6060
6061 mutex_lock(&bp->hwrm_cmd_lock);
6062 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6063 error_code = le16_to_cpu(resp->error_code);
6064 mutex_unlock(&bp->hwrm_cmd_lock);
6065
6066 if (rc || error_code) {
6067 netdev_err(bp->dev, "hwrm_ring_free type %d failed. rc:%x err:%x\n",
6068 ring_type, rc, error_code);
6069 return -EIO;
6070 }
6071 return 0;
6072 }
6073
6074 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
6075 {
6076 u32 type;
6077 int i;
6078
6079 if (!bp->bnapi)
6080 return;
6081
6082 for (i = 0; i < bp->tx_nr_rings; i++) {
6083 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
6084 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
6085
6086 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
6087 u32 cmpl_ring_id = bnxt_cp_ring_for_tx(bp, txr);
6088
6089 hwrm_ring_free_send_msg(bp, ring,
6090 RING_FREE_REQ_RING_TYPE_TX,
6091 close_path ? cmpl_ring_id :
6092 INVALID_HW_RING_ID);
6093 ring->fw_ring_id = INVALID_HW_RING_ID;
6094 }
6095 }
6096
6097 for (i = 0; i < bp->rx_nr_rings; i++) {
6098 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
6099 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
6100 u32 grp_idx = rxr->bnapi->index;
6101
6102 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
6103 u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr);
6104
6105 hwrm_ring_free_send_msg(bp, ring,
6106 RING_FREE_REQ_RING_TYPE_RX,
6107 close_path ? cmpl_ring_id :
6108 INVALID_HW_RING_ID);
6109 ring->fw_ring_id = INVALID_HW_RING_ID;
6110 bp->grp_info[grp_idx].rx_fw_ring_id =
6111 INVALID_HW_RING_ID;
6112 }
6113 }
6114
6115 if (bp->flags & BNXT_FLAG_CHIP_P5)
6116 type = RING_FREE_REQ_RING_TYPE_RX_AGG;
6117 else
6118 type = RING_FREE_REQ_RING_TYPE_RX;
6119 for (i = 0; i < bp->rx_nr_rings; i++) {
6120 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
6121 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
6122 u32 grp_idx = rxr->bnapi->index;
6123
6124 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
6125 u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr);
6126
6127 hwrm_ring_free_send_msg(bp, ring, type,
6128 close_path ? cmpl_ring_id :
6129 INVALID_HW_RING_ID);
6130 ring->fw_ring_id = INVALID_HW_RING_ID;
6131 bp->grp_info[grp_idx].agg_fw_ring_id =
6132 INVALID_HW_RING_ID;
6133 }
6134 }
6135
6136 /* The completion rings are about to be freed. After that the
6137 * IRQ doorbell will not work anymore. So we need to disable
6138 * IRQ here.
6139 */
6140 bnxt_disable_int_sync(bp);
6141
6142 if (bp->flags & BNXT_FLAG_CHIP_P5)
6143 type = RING_FREE_REQ_RING_TYPE_NQ;
6144 else
6145 type = RING_FREE_REQ_RING_TYPE_L2_CMPL;
6146 for (i = 0; i < bp->cp_nr_rings; i++) {
6147 struct bnxt_napi *bnapi = bp->bnapi[i];
6148 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6149 struct bnxt_ring_struct *ring;
6150 int j;
6151
6152 for (j = 0; j < 2; j++) {
6153 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
6154
6155 if (cpr2) {
6156 ring = &cpr2->cp_ring_struct;
6157 if (ring->fw_ring_id == INVALID_HW_RING_ID)
6158 continue;
6159 hwrm_ring_free_send_msg(bp, ring,
6160 RING_FREE_REQ_RING_TYPE_L2_CMPL,
6161 INVALID_HW_RING_ID);
6162 ring->fw_ring_id = INVALID_HW_RING_ID;
6163 }
6164 }
6165 ring = &cpr->cp_ring_struct;
6166 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
6167 hwrm_ring_free_send_msg(bp, ring, type,
6168 INVALID_HW_RING_ID);
6169 ring->fw_ring_id = INVALID_HW_RING_ID;
6170 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
6171 }
6172 }
6173 }
6174
6175 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
6176 bool shared);
6177
6178 static int bnxt_hwrm_get_rings(struct bnxt *bp)
6179 {
6180 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
6181 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6182 struct hwrm_func_qcfg_input req = {0};
6183 int rc;
6184
6185 if (bp->hwrm_spec_code < 0x10601)
6186 return 0;
6187
6188 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
6189 req.fid = cpu_to_le16(0xffff);
6190 mutex_lock(&bp->hwrm_cmd_lock);
6191 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6192 if (rc) {
6193 mutex_unlock(&bp->hwrm_cmd_lock);
6194 return rc;
6195 }
6196
6197 hw_resc->resv_tx_rings = le16_to_cpu(resp->alloc_tx_rings);
6198 if (BNXT_NEW_RM(bp)) {
6199 u16 cp, stats;
6200
6201 hw_resc->resv_rx_rings = le16_to_cpu(resp->alloc_rx_rings);
6202 hw_resc->resv_hw_ring_grps =
6203 le32_to_cpu(resp->alloc_hw_ring_grps);
6204 hw_resc->resv_vnics = le16_to_cpu(resp->alloc_vnics);
6205 cp = le16_to_cpu(resp->alloc_cmpl_rings);
6206 stats = le16_to_cpu(resp->alloc_stat_ctx);
6207 hw_resc->resv_irqs = cp;
6208 if (bp->flags & BNXT_FLAG_CHIP_P5) {
6209 int rx = hw_resc->resv_rx_rings;
6210 int tx = hw_resc->resv_tx_rings;
6211
6212 if (bp->flags & BNXT_FLAG_AGG_RINGS)
6213 rx >>= 1;
6214 if (cp < (rx + tx)) {
6215 bnxt_trim_rings(bp, &rx, &tx, cp, false);
6216 if (bp->flags & BNXT_FLAG_AGG_RINGS)
6217 rx <<= 1;
6218 hw_resc->resv_rx_rings = rx;
6219 hw_resc->resv_tx_rings = tx;
6220 }
6221 hw_resc->resv_irqs = le16_to_cpu(resp->alloc_msix);
6222 hw_resc->resv_hw_ring_grps = rx;
6223 }
6224 hw_resc->resv_cp_rings = cp;
6225 hw_resc->resv_stat_ctxs = stats;
6226 }
6227 mutex_unlock(&bp->hwrm_cmd_lock);
6228 return 0;
6229 }
6230
6231 /* Caller must hold bp->hwrm_cmd_lock */
6232 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings)
6233 {
6234 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
6235 struct hwrm_func_qcfg_input req = {0};
6236 int rc;
6237
6238 if (bp->hwrm_spec_code < 0x10601)
6239 return 0;
6240
6241 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
6242 req.fid = cpu_to_le16(fid);
6243 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6244 if (!rc)
6245 *tx_rings = le16_to_cpu(resp->alloc_tx_rings);
6246
6247 return rc;
6248 }
6249
6250 static bool bnxt_rfs_supported(struct bnxt *bp);
6251
6252 static void
6253 __bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, struct hwrm_func_cfg_input *req,
6254 int tx_rings, int rx_rings, int ring_grps,
6255 int cp_rings, int stats, int vnics)
6256 {
6257 u32 enables = 0;
6258
6259 bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_CFG, -1, -1);
6260 req->fid = cpu_to_le16(0xffff);
6261 enables |= tx_rings ? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
6262 req->num_tx_rings = cpu_to_le16(tx_rings);
6263 if (BNXT_NEW_RM(bp)) {
6264 enables |= rx_rings ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0;
6265 enables |= stats ? FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
6266 if (bp->flags & BNXT_FLAG_CHIP_P5) {
6267 enables |= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_MSIX : 0;
6268 enables |= tx_rings + ring_grps ?
6269 FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
6270 enables |= rx_rings ?
6271 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
6272 } else {
6273 enables |= cp_rings ?
6274 FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
6275 enables |= ring_grps ?
6276 FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS |
6277 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
6278 }
6279 enables |= vnics ? FUNC_CFG_REQ_ENABLES_NUM_VNICS : 0;
6280
6281 req->num_rx_rings = cpu_to_le16(rx_rings);
6282 if (bp->flags & BNXT_FLAG_CHIP_P5) {
6283 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps);
6284 req->num_msix = cpu_to_le16(cp_rings);
6285 req->num_rsscos_ctxs =
6286 cpu_to_le16(DIV_ROUND_UP(ring_grps, 64));
6287 } else {
6288 req->num_cmpl_rings = cpu_to_le16(cp_rings);
6289 req->num_hw_ring_grps = cpu_to_le16(ring_grps);
6290 req->num_rsscos_ctxs = cpu_to_le16(1);
6291 if (!(bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
6292 bnxt_rfs_supported(bp))
6293 req->num_rsscos_ctxs =
6294 cpu_to_le16(ring_grps + 1);
6295 }
6296 req->num_stat_ctxs = cpu_to_le16(stats);
6297 req->num_vnics = cpu_to_le16(vnics);
6298 }
6299 req->enables = cpu_to_le32(enables);
6300 }
6301
6302 static void
6303 __bnxt_hwrm_reserve_vf_rings(struct bnxt *bp,
6304 struct hwrm_func_vf_cfg_input *req, int tx_rings,
6305 int rx_rings, int ring_grps, int cp_rings,
6306 int stats, int vnics)
6307 {
6308 u32 enables = 0;
6309
6310 bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_VF_CFG, -1, -1);
6311 enables |= tx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
6312 enables |= rx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS |
6313 FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
6314 enables |= stats ? FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
6315 if (bp->flags & BNXT_FLAG_CHIP_P5) {
6316 enables |= tx_rings + ring_grps ?
6317 FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
6318 } else {
6319 enables |= cp_rings ?
6320 FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
6321 enables |= ring_grps ?
6322 FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0;
6323 }
6324 enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0;
6325 enables |= FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS;
6326
6327 req->num_l2_ctxs = cpu_to_le16(BNXT_VF_MAX_L2_CTX);
6328 req->num_tx_rings = cpu_to_le16(tx_rings);
6329 req->num_rx_rings = cpu_to_le16(rx_rings);
6330 if (bp->flags & BNXT_FLAG_CHIP_P5) {
6331 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps);
6332 req->num_rsscos_ctxs = cpu_to_le16(DIV_ROUND_UP(ring_grps, 64));
6333 } else {
6334 req->num_cmpl_rings = cpu_to_le16(cp_rings);
6335 req->num_hw_ring_grps = cpu_to_le16(ring_grps);
6336 req->num_rsscos_ctxs = cpu_to_le16(BNXT_VF_MAX_RSS_CTX);
6337 }
6338 req->num_stat_ctxs = cpu_to_le16(stats);
6339 req->num_vnics = cpu_to_le16(vnics);
6340
6341 req->enables = cpu_to_le32(enables);
6342 }
6343
6344 static int
6345 bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
6346 int ring_grps, int cp_rings, int stats, int vnics)
6347 {
6348 struct hwrm_func_cfg_input req = {0};
6349 int rc;
6350
6351 __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
6352 cp_rings, stats, vnics);
6353 if (!req.enables)
6354 return 0;
6355
6356 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6357 if (rc)
6358 return rc;
6359
6360 if (bp->hwrm_spec_code < 0x10601)
6361 bp->hw_resc.resv_tx_rings = tx_rings;
6362
6363 return bnxt_hwrm_get_rings(bp);
6364 }
6365
6366 static int
6367 bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
6368 int ring_grps, int cp_rings, int stats, int vnics)
6369 {
6370 struct hwrm_func_vf_cfg_input req = {0};
6371 int rc;
6372
6373 if (!BNXT_NEW_RM(bp)) {
6374 bp->hw_resc.resv_tx_rings = tx_rings;
6375 return 0;
6376 }
6377
6378 __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
6379 cp_rings, stats, vnics);
6380 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6381 if (rc)
6382 return rc;
6383
6384 return bnxt_hwrm_get_rings(bp);
6385 }
6386
6387 static int bnxt_hwrm_reserve_rings(struct bnxt *bp, int tx, int rx, int grp,
6388 int cp, int stat, int vnic)
6389 {
6390 if (BNXT_PF(bp))
6391 return bnxt_hwrm_reserve_pf_rings(bp, tx, rx, grp, cp, stat,
6392 vnic);
6393 else
6394 return bnxt_hwrm_reserve_vf_rings(bp, tx, rx, grp, cp, stat,
6395 vnic);
6396 }
6397
6398 int bnxt_nq_rings_in_use(struct bnxt *bp)
6399 {
6400 int cp = bp->cp_nr_rings;
6401 int ulp_msix, ulp_base;
6402
6403 ulp_msix = bnxt_get_ulp_msix_num(bp);
6404 if (ulp_msix) {
6405 ulp_base = bnxt_get_ulp_msix_base(bp);
6406 cp += ulp_msix;
6407 if ((ulp_base + ulp_msix) > cp)
6408 cp = ulp_base + ulp_msix;
6409 }
6410 return cp;
6411 }
6412
6413 static int bnxt_cp_rings_in_use(struct bnxt *bp)
6414 {
6415 int cp;
6416
6417 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
6418 return bnxt_nq_rings_in_use(bp);
6419
6420 cp = bp->tx_nr_rings + bp->rx_nr_rings;
6421 return cp;
6422 }
6423
6424 static int bnxt_get_func_stat_ctxs(struct bnxt *bp)
6425 {
6426 int ulp_stat = bnxt_get_ulp_stat_ctxs(bp);
6427 int cp = bp->cp_nr_rings;
6428
6429 if (!ulp_stat)
6430 return cp;
6431
6432 if (bnxt_nq_rings_in_use(bp) > cp + bnxt_get_ulp_msix_num(bp))
6433 return bnxt_get_ulp_msix_base(bp) + ulp_stat;
6434
6435 return cp + ulp_stat;
6436 }
6437
6438 /* Check if a default RSS map needs to be setup. This function is only
6439 * used on older firmware that does not require reserving RX rings.
6440 */
6441 static void bnxt_check_rss_tbl_no_rmgr(struct bnxt *bp)
6442 {
6443 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6444
6445 /* The RSS map is valid for RX rings set to resv_rx_rings */
6446 if (hw_resc->resv_rx_rings != bp->rx_nr_rings) {
6447 hw_resc->resv_rx_rings = bp->rx_nr_rings;
6448 if (!netif_is_rxfh_configured(bp->dev))
6449 bnxt_set_dflt_rss_indir_tbl(bp);
6450 }
6451 }
6452
6453 static bool bnxt_need_reserve_rings(struct bnxt *bp)
6454 {
6455 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6456 int cp = bnxt_cp_rings_in_use(bp);
6457 int nq = bnxt_nq_rings_in_use(bp);
6458 int rx = bp->rx_nr_rings, stat;
6459 int vnic = 1, grp = rx;
6460
6461 if (hw_resc->resv_tx_rings != bp->tx_nr_rings &&
6462 bp->hwrm_spec_code >= 0x10601)
6463 return true;
6464
6465 /* Old firmware does not need RX ring reservations but we still
6466 * need to setup a default RSS map when needed. With new firmware
6467 * we go through RX ring reservations first and then set up the
6468 * RSS map for the successfully reserved RX rings when needed.
6469 */
6470 if (!BNXT_NEW_RM(bp)) {
6471 bnxt_check_rss_tbl_no_rmgr(bp);
6472 return false;
6473 }
6474 if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5))
6475 vnic = rx + 1;
6476 if (bp->flags & BNXT_FLAG_AGG_RINGS)
6477 rx <<= 1;
6478 stat = bnxt_get_func_stat_ctxs(bp);
6479 if (hw_resc->resv_rx_rings != rx || hw_resc->resv_cp_rings != cp ||
6480 hw_resc->resv_vnics != vnic || hw_resc->resv_stat_ctxs != stat ||
6481 (hw_resc->resv_hw_ring_grps != grp &&
6482 !(bp->flags & BNXT_FLAG_CHIP_P5)))
6483 return true;
6484 if ((bp->flags & BNXT_FLAG_CHIP_P5) && BNXT_PF(bp) &&
6485 hw_resc->resv_irqs != nq)
6486 return true;
6487 return false;
6488 }
6489
6490 static int __bnxt_reserve_rings(struct bnxt *bp)
6491 {
6492 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6493 int cp = bnxt_nq_rings_in_use(bp);
6494 int tx = bp->tx_nr_rings;
6495 int rx = bp->rx_nr_rings;
6496 int grp, rx_rings, rc;
6497 int vnic = 1, stat;
6498 bool sh = false;
6499
6500 if (!bnxt_need_reserve_rings(bp))
6501 return 0;
6502
6503 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
6504 sh = true;
6505 if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5))
6506 vnic = rx + 1;
6507 if (bp->flags & BNXT_FLAG_AGG_RINGS)
6508 rx <<= 1;
6509 grp = bp->rx_nr_rings;
6510 stat = bnxt_get_func_stat_ctxs(bp);
6511
6512 rc = bnxt_hwrm_reserve_rings(bp, tx, rx, grp, cp, stat, vnic);
6513 if (rc)
6514 return rc;
6515
6516 tx = hw_resc->resv_tx_rings;
6517 if (BNXT_NEW_RM(bp)) {
6518 rx = hw_resc->resv_rx_rings;
6519 cp = hw_resc->resv_irqs;
6520 grp = hw_resc->resv_hw_ring_grps;
6521 vnic = hw_resc->resv_vnics;
6522 stat = hw_resc->resv_stat_ctxs;
6523 }
6524
6525 rx_rings = rx;
6526 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
6527 if (rx >= 2) {
6528 rx_rings = rx >> 1;
6529 } else {
6530 if (netif_running(bp->dev))
6531 return -ENOMEM;
6532
6533 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
6534 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
6535 bp->dev->hw_features &= ~NETIF_F_LRO;
6536 bp->dev->features &= ~NETIF_F_LRO;
6537 bnxt_set_ring_params(bp);
6538 }
6539 }
6540 rx_rings = min_t(int, rx_rings, grp);
6541 cp = min_t(int, cp, bp->cp_nr_rings);
6542 if (stat > bnxt_get_ulp_stat_ctxs(bp))
6543 stat -= bnxt_get_ulp_stat_ctxs(bp);
6544 cp = min_t(int, cp, stat);
6545 rc = bnxt_trim_rings(bp, &rx_rings, &tx, cp, sh);
6546 if (bp->flags & BNXT_FLAG_AGG_RINGS)
6547 rx = rx_rings << 1;
6548 cp = sh ? max_t(int, tx, rx_rings) : tx + rx_rings;
6549 bp->tx_nr_rings = tx;
6550
6551 /* If we cannot reserve all the RX rings, reset the RSS map only
6552 * if absolutely necessary
6553 */
6554 if (rx_rings != bp->rx_nr_rings) {
6555 netdev_warn(bp->dev, "Able to reserve only %d out of %d requested RX rings\n",
6556 rx_rings, bp->rx_nr_rings);
6557 if ((bp->dev->priv_flags & IFF_RXFH_CONFIGURED) &&
6558 (bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) !=
6559 bnxt_get_nr_rss_ctxs(bp, rx_rings) ||
6560 bnxt_get_max_rss_ring(bp) >= rx_rings)) {
6561 netdev_warn(bp->dev, "RSS table entries reverting to default\n");
6562 bp->dev->priv_flags &= ~IFF_RXFH_CONFIGURED;
6563 }
6564 }
6565 bp->rx_nr_rings = rx_rings;
6566 bp->cp_nr_rings = cp;
6567
6568 if (!tx || !rx || !cp || !grp || !vnic || !stat)
6569 return -ENOMEM;
6570
6571 if (!netif_is_rxfh_configured(bp->dev))
6572 bnxt_set_dflt_rss_indir_tbl(bp);
6573
6574 return rc;
6575 }
6576
6577 static int bnxt_hwrm_check_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
6578 int ring_grps, int cp_rings, int stats,
6579 int vnics)
6580 {
6581 struct hwrm_func_vf_cfg_input req = {0};
6582 u32 flags;
6583
6584 if (!BNXT_NEW_RM(bp))
6585 return 0;
6586
6587 __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
6588 cp_rings, stats, vnics);
6589 flags = FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST |
6590 FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST |
6591 FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
6592 FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
6593 FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST |
6594 FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST;
6595 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
6596 flags |= FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST;
6597
6598 req.flags = cpu_to_le32(flags);
6599 return hwrm_send_message_silent(bp, &req, sizeof(req),
6600 HWRM_CMD_TIMEOUT);
6601 }
6602
6603 static int bnxt_hwrm_check_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
6604 int ring_grps, int cp_rings, int stats,
6605 int vnics)
6606 {
6607 struct hwrm_func_cfg_input req = {0};
6608 u32 flags;
6609
6610 __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
6611 cp_rings, stats, vnics);
6612 flags = FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST;
6613 if (BNXT_NEW_RM(bp)) {
6614 flags |= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST |
6615 FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
6616 FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
6617 FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST;
6618 if (bp->flags & BNXT_FLAG_CHIP_P5)
6619 flags |= FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST |
6620 FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST;
6621 else
6622 flags |= FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST;
6623 }
6624
6625 req.flags = cpu_to_le32(flags);
6626 return hwrm_send_message_silent(bp, &req, sizeof(req),
6627 HWRM_CMD_TIMEOUT);
6628 }
6629
6630 static int bnxt_hwrm_check_rings(struct bnxt *bp, int tx_rings, int rx_rings,
6631 int ring_grps, int cp_rings, int stats,
6632 int vnics)
6633 {
6634 if (bp->hwrm_spec_code < 0x10801)
6635 return 0;
6636
6637 if (BNXT_PF(bp))
6638 return bnxt_hwrm_check_pf_rings(bp, tx_rings, rx_rings,
6639 ring_grps, cp_rings, stats,
6640 vnics);
6641
6642 return bnxt_hwrm_check_vf_rings(bp, tx_rings, rx_rings, ring_grps,
6643 cp_rings, stats, vnics);
6644 }
6645
6646 static void bnxt_hwrm_coal_params_qcaps(struct bnxt *bp)
6647 {
6648 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6649 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
6650 struct hwrm_ring_aggint_qcaps_input req = {0};
6651 int rc;
6652
6653 coal_cap->cmpl_params = BNXT_LEGACY_COAL_CMPL_PARAMS;
6654 coal_cap->num_cmpl_dma_aggr_max = 63;
6655 coal_cap->num_cmpl_dma_aggr_during_int_max = 63;
6656 coal_cap->cmpl_aggr_dma_tmr_max = 65535;
6657 coal_cap->cmpl_aggr_dma_tmr_during_int_max = 65535;
6658 coal_cap->int_lat_tmr_min_max = 65535;
6659 coal_cap->int_lat_tmr_max_max = 65535;
6660 coal_cap->num_cmpl_aggr_int_max = 65535;
6661 coal_cap->timer_units = 80;
6662
6663 if (bp->hwrm_spec_code < 0x10902)
6664 return;
6665
6666 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_AGGINT_QCAPS, -1, -1);
6667 mutex_lock(&bp->hwrm_cmd_lock);
6668 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6669 if (!rc) {
6670 coal_cap->cmpl_params = le32_to_cpu(resp->cmpl_params);
6671 coal_cap->nq_params = le32_to_cpu(resp->nq_params);
6672 coal_cap->num_cmpl_dma_aggr_max =
6673 le16_to_cpu(resp->num_cmpl_dma_aggr_max);
6674 coal_cap->num_cmpl_dma_aggr_during_int_max =
6675 le16_to_cpu(resp->num_cmpl_dma_aggr_during_int_max);
6676 coal_cap->cmpl_aggr_dma_tmr_max =
6677 le16_to_cpu(resp->cmpl_aggr_dma_tmr_max);
6678 coal_cap->cmpl_aggr_dma_tmr_during_int_max =
6679 le16_to_cpu(resp->cmpl_aggr_dma_tmr_during_int_max);
6680 coal_cap->int_lat_tmr_min_max =
6681 le16_to_cpu(resp->int_lat_tmr_min_max);
6682 coal_cap->int_lat_tmr_max_max =
6683 le16_to_cpu(resp->int_lat_tmr_max_max);
6684 coal_cap->num_cmpl_aggr_int_max =
6685 le16_to_cpu(resp->num_cmpl_aggr_int_max);
6686 coal_cap->timer_units = le16_to_cpu(resp->timer_units);
6687 }
6688 mutex_unlock(&bp->hwrm_cmd_lock);
6689 }
6690
6691 static u16 bnxt_usec_to_coal_tmr(struct bnxt *bp, u16 usec)
6692 {
6693 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
6694
6695 return usec * 1000 / coal_cap->timer_units;
6696 }
6697
6698 static void bnxt_hwrm_set_coal_params(struct bnxt *bp,
6699 struct bnxt_coal *hw_coal,
6700 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
6701 {
6702 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
6703 u32 cmpl_params = coal_cap->cmpl_params;
6704 u16 val, tmr, max, flags = 0;
6705
6706 max = hw_coal->bufs_per_record * 128;
6707 if (hw_coal->budget)
6708 max = hw_coal->bufs_per_record * hw_coal->budget;
6709 max = min_t(u16, max, coal_cap->num_cmpl_aggr_int_max);
6710
6711 val = clamp_t(u16, hw_coal->coal_bufs, 1, max);
6712 req->num_cmpl_aggr_int = cpu_to_le16(val);
6713
6714 val = min_t(u16, val, coal_cap->num_cmpl_dma_aggr_max);
6715 req->num_cmpl_dma_aggr = cpu_to_le16(val);
6716
6717 val = clamp_t(u16, hw_coal->coal_bufs_irq, 1,
6718 coal_cap->num_cmpl_dma_aggr_during_int_max);
6719 req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val);
6720
6721 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks);
6722 tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_max_max);
6723 req->int_lat_tmr_max = cpu_to_le16(tmr);
6724
6725 /* min timer set to 1/2 of interrupt timer */
6726 if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN) {
6727 val = tmr / 2;
6728 val = clamp_t(u16, val, 1, coal_cap->int_lat_tmr_min_max);
6729 req->int_lat_tmr_min = cpu_to_le16(val);
6730 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE);
6731 }
6732
6733 /* buf timer set to 1/4 of interrupt timer */
6734 val = clamp_t(u16, tmr / 4, 1, coal_cap->cmpl_aggr_dma_tmr_max);
6735 req->cmpl_aggr_dma_tmr = cpu_to_le16(val);
6736
6737 if (cmpl_params &
6738 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT) {
6739 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks_irq);
6740 val = clamp_t(u16, tmr, 1,
6741 coal_cap->cmpl_aggr_dma_tmr_during_int_max);
6742 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(val);
6743 req->enables |=
6744 cpu_to_le16(BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE);
6745 }
6746
6747 if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET)
6748 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
6749 if ((cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE) &&
6750 hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh)
6751 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
6752 req->flags = cpu_to_le16(flags);
6753 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_ENABLES);
6754 }
6755
6756 /* Caller holds bp->hwrm_cmd_lock */
6757 static int __bnxt_hwrm_set_coal_nq(struct bnxt *bp, struct bnxt_napi *bnapi,
6758 struct bnxt_coal *hw_coal)
6759 {
6760 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
6761 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6762 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
6763 u32 nq_params = coal_cap->nq_params;
6764 u16 tmr;
6765
6766 if (!(nq_params & RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN))
6767 return 0;
6768
6769 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
6770 -1, -1);
6771 req.ring_id = cpu_to_le16(cpr->cp_ring_struct.fw_ring_id);
6772 req.flags =
6773 cpu_to_le16(RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ);
6774
6775 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks) / 2;
6776 tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_min_max);
6777 req.int_lat_tmr_min = cpu_to_le16(tmr);
6778 req.enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE);
6779 return _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6780 }
6781
6782 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi)
6783 {
6784 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0};
6785 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6786 struct bnxt_coal coal;
6787
6788 /* Tick values in micro seconds.
6789 * 1 coal_buf x bufs_per_record = 1 completion record.
6790 */
6791 memcpy(&coal, &bp->rx_coal, sizeof(struct bnxt_coal));
6792
6793 coal.coal_ticks = cpr->rx_ring_coal.coal_ticks;
6794 coal.coal_bufs = cpr->rx_ring_coal.coal_bufs;
6795
6796 if (!bnapi->rx_ring)
6797 return -ENODEV;
6798
6799 bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
6800 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
6801
6802 bnxt_hwrm_set_coal_params(bp, &coal, &req_rx);
6803
6804 req_rx.ring_id = cpu_to_le16(bnxt_cp_ring_for_rx(bp, bnapi->rx_ring));
6805
6806 return hwrm_send_message(bp, &req_rx, sizeof(req_rx),
6807 HWRM_CMD_TIMEOUT);
6808 }
6809
6810 int bnxt_hwrm_set_coal(struct bnxt *bp)
6811 {
6812 int i, rc = 0;
6813 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
6814 req_tx = {0}, *req;
6815
6816 bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
6817 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
6818 bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
6819 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
6820
6821 bnxt_hwrm_set_coal_params(bp, &bp->rx_coal, &req_rx);
6822 bnxt_hwrm_set_coal_params(bp, &bp->tx_coal, &req_tx);
6823
6824 mutex_lock(&bp->hwrm_cmd_lock);
6825 for (i = 0; i < bp->cp_nr_rings; i++) {
6826 struct bnxt_napi *bnapi = bp->bnapi[i];
6827 struct bnxt_coal *hw_coal;
6828 u16 ring_id;
6829
6830 req = &req_rx;
6831 if (!bnapi->rx_ring) {
6832 ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring);
6833 req = &req_tx;
6834 } else {
6835 ring_id = bnxt_cp_ring_for_rx(bp, bnapi->rx_ring);
6836 }
6837 req->ring_id = cpu_to_le16(ring_id);
6838
6839 rc = _hwrm_send_message(bp, req, sizeof(*req),
6840 HWRM_CMD_TIMEOUT);
6841 if (rc)
6842 break;
6843
6844 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
6845 continue;
6846
6847 if (bnapi->rx_ring && bnapi->tx_ring) {
6848 req = &req_tx;
6849 ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring);
6850 req->ring_id = cpu_to_le16(ring_id);
6851 rc = _hwrm_send_message(bp, req, sizeof(*req),
6852 HWRM_CMD_TIMEOUT);
6853 if (rc)
6854 break;
6855 }
6856 if (bnapi->rx_ring)
6857 hw_coal = &bp->rx_coal;
6858 else
6859 hw_coal = &bp->tx_coal;
6860 __bnxt_hwrm_set_coal_nq(bp, bnapi, hw_coal);
6861 }
6862 mutex_unlock(&bp->hwrm_cmd_lock);
6863 return rc;
6864 }
6865
6866 static void bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
6867 {
6868 struct hwrm_stat_ctx_clr_stats_input req0 = {0};
6869 struct hwrm_stat_ctx_free_input req = {0};
6870 int i;
6871
6872 if (!bp->bnapi)
6873 return;
6874
6875 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
6876 return;
6877
6878 bnxt_hwrm_cmd_hdr_init(bp, &req0, HWRM_STAT_CTX_CLR_STATS, -1, -1);
6879 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
6880
6881 mutex_lock(&bp->hwrm_cmd_lock);
6882 for (i = 0; i < bp->cp_nr_rings; i++) {
6883 struct bnxt_napi *bnapi = bp->bnapi[i];
6884 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6885
6886 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
6887 req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
6888 if (BNXT_FW_MAJ(bp) <= 20) {
6889 req0.stat_ctx_id = req.stat_ctx_id;
6890 _hwrm_send_message(bp, &req0, sizeof(req0),
6891 HWRM_CMD_TIMEOUT);
6892 }
6893 _hwrm_send_message(bp, &req, sizeof(req),
6894 HWRM_CMD_TIMEOUT);
6895
6896 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
6897 }
6898 }
6899 mutex_unlock(&bp->hwrm_cmd_lock);
6900 }
6901
6902 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
6903 {
6904 int rc = 0, i;
6905 struct hwrm_stat_ctx_alloc_input req = {0};
6906 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
6907
6908 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
6909 return 0;
6910
6911 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
6912
6913 req.stats_dma_length = cpu_to_le16(bp->hw_ring_stats_size);
6914 req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000);
6915
6916 mutex_lock(&bp->hwrm_cmd_lock);
6917 for (i = 0; i < bp->cp_nr_rings; i++) {
6918 struct bnxt_napi *bnapi = bp->bnapi[i];
6919 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6920
6921 req.stats_dma_addr = cpu_to_le64(cpr->stats.hw_stats_map);
6922
6923 rc = _hwrm_send_message(bp, &req, sizeof(req),
6924 HWRM_CMD_TIMEOUT);
6925 if (rc)
6926 break;
6927
6928 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
6929
6930 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
6931 }
6932 mutex_unlock(&bp->hwrm_cmd_lock);
6933 return rc;
6934 }
6935
6936 static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
6937 {
6938 struct hwrm_func_qcfg_input req = {0};
6939 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
6940 u32 min_db_offset = 0;
6941 u16 flags;
6942 int rc;
6943
6944 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
6945 req.fid = cpu_to_le16(0xffff);
6946 mutex_lock(&bp->hwrm_cmd_lock);
6947 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6948 if (rc)
6949 goto func_qcfg_exit;
6950
6951 #ifdef CONFIG_BNXT_SRIOV
6952 if (BNXT_VF(bp)) {
6953 struct bnxt_vf_info *vf = &bp->vf;
6954
6955 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
6956 } else {
6957 bp->pf.registered_vfs = le16_to_cpu(resp->registered_vfs);
6958 }
6959 #endif
6960 flags = le16_to_cpu(resp->flags);
6961 if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED |
6962 FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) {
6963 bp->fw_cap |= BNXT_FW_CAP_LLDP_AGENT;
6964 if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED)
6965 bp->fw_cap |= BNXT_FW_CAP_DCBX_AGENT;
6966 }
6967 if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST))
6968 bp->flags |= BNXT_FLAG_MULTI_HOST;
6969 if (flags & FUNC_QCFG_RESP_FLAGS_RING_MONITOR_ENABLED)
6970 bp->fw_cap |= BNXT_FW_CAP_RING_MONITOR;
6971
6972 switch (resp->port_partition_type) {
6973 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
6974 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
6975 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0:
6976 bp->port_partition_type = resp->port_partition_type;
6977 break;
6978 }
6979 if (bp->hwrm_spec_code < 0x10707 ||
6980 resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB)
6981 bp->br_mode = BRIDGE_MODE_VEB;
6982 else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA)
6983 bp->br_mode = BRIDGE_MODE_VEPA;
6984 else
6985 bp->br_mode = BRIDGE_MODE_UNDEF;
6986
6987 bp->max_mtu = le16_to_cpu(resp->max_mtu_configured);
6988 if (!bp->max_mtu)
6989 bp->max_mtu = BNXT_MAX_MTU;
6990
6991 if (bp->db_size)
6992 goto func_qcfg_exit;
6993
6994 if (bp->flags & BNXT_FLAG_CHIP_P5) {
6995 if (BNXT_PF(bp))
6996 min_db_offset = DB_PF_OFFSET_P5;
6997 else
6998 min_db_offset = DB_VF_OFFSET_P5;
6999 }
7000 bp->db_size = PAGE_ALIGN(le16_to_cpu(resp->l2_doorbell_bar_size_kb) *
7001 1024);
7002 if (!bp->db_size || bp->db_size > pci_resource_len(bp->pdev, 2) ||
7003 bp->db_size <= min_db_offset)
7004 bp->db_size = pci_resource_len(bp->pdev, 2);
7005
7006 func_qcfg_exit:
7007 mutex_unlock(&bp->hwrm_cmd_lock);
7008 return rc;
7009 }
7010
7011 static void bnxt_init_ctx_initializer(struct bnxt_ctx_mem_info *ctx,
7012 struct hwrm_func_backing_store_qcaps_output *resp)
7013 {
7014 struct bnxt_mem_init *mem_init;
7015 u16 init_mask;
7016 u8 init_val;
7017 u8 *offset;
7018 int i;
7019
7020 init_val = resp->ctx_kind_initializer;
7021 init_mask = le16_to_cpu(resp->ctx_init_mask);
7022 offset = &resp->qp_init_offset;
7023 mem_init = &ctx->mem_init[BNXT_CTX_MEM_INIT_QP];
7024 for (i = 0; i < BNXT_CTX_MEM_INIT_MAX; i++, mem_init++, offset++) {
7025 mem_init->init_val = init_val;
7026 mem_init->offset = BNXT_MEM_INVALID_OFFSET;
7027 if (!init_mask)
7028 continue;
7029 if (i == BNXT_CTX_MEM_INIT_STAT)
7030 offset = &resp->stat_init_offset;
7031 if (init_mask & (1 << i))
7032 mem_init->offset = *offset * 4;
7033 else
7034 mem_init->init_val = 0;
7035 }
7036 ctx->mem_init[BNXT_CTX_MEM_INIT_QP].size = ctx->qp_entry_size;
7037 ctx->mem_init[BNXT_CTX_MEM_INIT_SRQ].size = ctx->srq_entry_size;
7038 ctx->mem_init[BNXT_CTX_MEM_INIT_CQ].size = ctx->cq_entry_size;
7039 ctx->mem_init[BNXT_CTX_MEM_INIT_VNIC].size = ctx->vnic_entry_size;
7040 ctx->mem_init[BNXT_CTX_MEM_INIT_STAT].size = ctx->stat_entry_size;
7041 ctx->mem_init[BNXT_CTX_MEM_INIT_MRAV].size = ctx->mrav_entry_size;
7042 }
7043
7044 static int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
7045 {
7046 struct hwrm_func_backing_store_qcaps_input req = {0};
7047 struct hwrm_func_backing_store_qcaps_output *resp =
7048 bp->hwrm_cmd_resp_addr;
7049 int rc;
7050
7051 if (bp->hwrm_spec_code < 0x10902 || BNXT_VF(bp) || bp->ctx)
7052 return 0;
7053
7054 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_QCAPS, -1, -1);
7055 mutex_lock(&bp->hwrm_cmd_lock);
7056 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7057 if (!rc) {
7058 struct bnxt_ctx_pg_info *ctx_pg;
7059 struct bnxt_ctx_mem_info *ctx;
7060 int i, tqm_rings;
7061
7062 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
7063 if (!ctx) {
7064 rc = -ENOMEM;
7065 goto ctx_err;
7066 }
7067 ctx->qp_max_entries = le32_to_cpu(resp->qp_max_entries);
7068 ctx->qp_min_qp1_entries = le16_to_cpu(resp->qp_min_qp1_entries);
7069 ctx->qp_max_l2_entries = le16_to_cpu(resp->qp_max_l2_entries);
7070 ctx->qp_entry_size = le16_to_cpu(resp->qp_entry_size);
7071 ctx->srq_max_l2_entries = le16_to_cpu(resp->srq_max_l2_entries);
7072 ctx->srq_max_entries = le32_to_cpu(resp->srq_max_entries);
7073 ctx->srq_entry_size = le16_to_cpu(resp->srq_entry_size);
7074 ctx->cq_max_l2_entries = le16_to_cpu(resp->cq_max_l2_entries);
7075 ctx->cq_max_entries = le32_to_cpu(resp->cq_max_entries);
7076 ctx->cq_entry_size = le16_to_cpu(resp->cq_entry_size);
7077 ctx->vnic_max_vnic_entries =
7078 le16_to_cpu(resp->vnic_max_vnic_entries);
7079 ctx->vnic_max_ring_table_entries =
7080 le16_to_cpu(resp->vnic_max_ring_table_entries);
7081 ctx->vnic_entry_size = le16_to_cpu(resp->vnic_entry_size);
7082 ctx->stat_max_entries = le32_to_cpu(resp->stat_max_entries);
7083 ctx->stat_entry_size = le16_to_cpu(resp->stat_entry_size);
7084 ctx->tqm_entry_size = le16_to_cpu(resp->tqm_entry_size);
7085 ctx->tqm_min_entries_per_ring =
7086 le32_to_cpu(resp->tqm_min_entries_per_ring);
7087 ctx->tqm_max_entries_per_ring =
7088 le32_to_cpu(resp->tqm_max_entries_per_ring);
7089 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
7090 if (!ctx->tqm_entries_multiple)
7091 ctx->tqm_entries_multiple = 1;
7092 ctx->mrav_max_entries = le32_to_cpu(resp->mrav_max_entries);
7093 ctx->mrav_entry_size = le16_to_cpu(resp->mrav_entry_size);
7094 ctx->mrav_num_entries_units =
7095 le16_to_cpu(resp->mrav_num_entries_units);
7096 ctx->tim_entry_size = le16_to_cpu(resp->tim_entry_size);
7097 ctx->tim_max_entries = le32_to_cpu(resp->tim_max_entries);
7098
7099 bnxt_init_ctx_initializer(ctx, resp);
7100
7101 ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
7102 if (!ctx->tqm_fp_rings_count)
7103 ctx->tqm_fp_rings_count = bp->max_q;
7104 else if (ctx->tqm_fp_rings_count > BNXT_MAX_TQM_FP_RINGS)
7105 ctx->tqm_fp_rings_count = BNXT_MAX_TQM_FP_RINGS;
7106
7107 tqm_rings = ctx->tqm_fp_rings_count + BNXT_MAX_TQM_SP_RINGS;
7108 ctx_pg = kcalloc(tqm_rings, sizeof(*ctx_pg), GFP_KERNEL);
7109 if (!ctx_pg) {
7110 kfree(ctx);
7111 rc = -ENOMEM;
7112 goto ctx_err;
7113 }
7114 for (i = 0; i < tqm_rings; i++, ctx_pg++)
7115 ctx->tqm_mem[i] = ctx_pg;
7116 bp->ctx = ctx;
7117 } else {
7118 rc = 0;
7119 }
7120 ctx_err:
7121 mutex_unlock(&bp->hwrm_cmd_lock);
7122 return rc;
7123 }
7124
7125 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem, u8 *pg_attr,
7126 __le64 *pg_dir)
7127 {
7128 if (!rmem->nr_pages)
7129 return;
7130
7131 BNXT_SET_CTX_PAGE_ATTR(*pg_attr);
7132 if (rmem->depth >= 1) {
7133 if (rmem->depth == 2)
7134 *pg_attr |= 2;
7135 else
7136 *pg_attr |= 1;
7137 *pg_dir = cpu_to_le64(rmem->pg_tbl_map);
7138 } else {
7139 *pg_dir = cpu_to_le64(rmem->dma_arr[0]);
7140 }
7141 }
7142
7143 #define FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES \
7144 (FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP | \
7145 FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ | \
7146 FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ | \
7147 FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC | \
7148 FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT)
7149
7150 static int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, u32 enables)
7151 {
7152 struct hwrm_func_backing_store_cfg_input req = {0};
7153 struct bnxt_ctx_mem_info *ctx = bp->ctx;
7154 struct bnxt_ctx_pg_info *ctx_pg;
7155 u32 req_len = sizeof(req);
7156 __le32 *num_entries;
7157 __le64 *pg_dir;
7158 u32 flags = 0;
7159 u8 *pg_attr;
7160 u32 ena;
7161 int i;
7162
7163 if (!ctx)
7164 return 0;
7165
7166 if (req_len > bp->hwrm_max_ext_req_len)
7167 req_len = BNXT_BACKING_STORE_CFG_LEGACY_LEN;
7168 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_CFG, -1, -1);
7169 req.enables = cpu_to_le32(enables);
7170
7171 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP) {
7172 ctx_pg = &ctx->qp_mem;
7173 req.qp_num_entries = cpu_to_le32(ctx_pg->entries);
7174 req.qp_num_qp1_entries = cpu_to_le16(ctx->qp_min_qp1_entries);
7175 req.qp_num_l2_entries = cpu_to_le16(ctx->qp_max_l2_entries);
7176 req.qp_entry_size = cpu_to_le16(ctx->qp_entry_size);
7177 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
7178 &req.qpc_pg_size_qpc_lvl,
7179 &req.qpc_page_dir);
7180 }
7181 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ) {
7182 ctx_pg = &ctx->srq_mem;
7183 req.srq_num_entries = cpu_to_le32(ctx_pg->entries);
7184 req.srq_num_l2_entries = cpu_to_le16(ctx->srq_max_l2_entries);
7185 req.srq_entry_size = cpu_to_le16(ctx->srq_entry_size);
7186 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
7187 &req.srq_pg_size_srq_lvl,
7188 &req.srq_page_dir);
7189 }
7190 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ) {
7191 ctx_pg = &ctx->cq_mem;
7192 req.cq_num_entries = cpu_to_le32(ctx_pg->entries);
7193 req.cq_num_l2_entries = cpu_to_le16(ctx->cq_max_l2_entries);
7194 req.cq_entry_size = cpu_to_le16(ctx->cq_entry_size);
7195 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, &req.cq_pg_size_cq_lvl,
7196 &req.cq_page_dir);
7197 }
7198 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC) {
7199 ctx_pg = &ctx->vnic_mem;
7200 req.vnic_num_vnic_entries =
7201 cpu_to_le16(ctx->vnic_max_vnic_entries);
7202 req.vnic_num_ring_table_entries =
7203 cpu_to_le16(ctx->vnic_max_ring_table_entries);
7204 req.vnic_entry_size = cpu_to_le16(ctx->vnic_entry_size);
7205 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
7206 &req.vnic_pg_size_vnic_lvl,
7207 &req.vnic_page_dir);
7208 }
7209 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) {
7210 ctx_pg = &ctx->stat_mem;
7211 req.stat_num_entries = cpu_to_le32(ctx->stat_max_entries);
7212 req.stat_entry_size = cpu_to_le16(ctx->stat_entry_size);
7213 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
7214 &req.stat_pg_size_stat_lvl,
7215 &req.stat_page_dir);
7216 }
7217 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV) {
7218 ctx_pg = &ctx->mrav_mem;
7219 req.mrav_num_entries = cpu_to_le32(ctx_pg->entries);
7220 if (ctx->mrav_num_entries_units)
7221 flags |=
7222 FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT;
7223 req.mrav_entry_size = cpu_to_le16(ctx->mrav_entry_size);
7224 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
7225 &req.mrav_pg_size_mrav_lvl,
7226 &req.mrav_page_dir);
7227 }
7228 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM) {
7229 ctx_pg = &ctx->tim_mem;
7230 req.tim_num_entries = cpu_to_le32(ctx_pg->entries);
7231 req.tim_entry_size = cpu_to_le16(ctx->tim_entry_size);
7232 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
7233 &req.tim_pg_size_tim_lvl,
7234 &req.tim_page_dir);
7235 }
7236 for (i = 0, num_entries = &req.tqm_sp_num_entries,
7237 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl,
7238 pg_dir = &req.tqm_sp_page_dir,
7239 ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP;
7240 i < BNXT_MAX_TQM_RINGS;
7241 i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
7242 if (!(enables & ena))
7243 continue;
7244
7245 req.tqm_entry_size = cpu_to_le16(ctx->tqm_entry_size);
7246 ctx_pg = ctx->tqm_mem[i];
7247 *num_entries = cpu_to_le32(ctx_pg->entries);
7248 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
7249 }
7250 req.flags = cpu_to_le32(flags);
7251 return hwrm_send_message(bp, &req, req_len, HWRM_CMD_TIMEOUT);
7252 }
7253
7254 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
7255 struct bnxt_ctx_pg_info *ctx_pg)
7256 {
7257 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
7258
7259 rmem->page_size = BNXT_PAGE_SIZE;
7260 rmem->pg_arr = ctx_pg->ctx_pg_arr;
7261 rmem->dma_arr = ctx_pg->ctx_dma_arr;
7262 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
7263 if (rmem->depth >= 1)
7264 rmem->flags |= BNXT_RMEM_USE_FULL_PAGE_FLAG;
7265 return bnxt_alloc_ring(bp, rmem);
7266 }
7267
7268 static int bnxt_alloc_ctx_pg_tbls(struct bnxt *bp,
7269 struct bnxt_ctx_pg_info *ctx_pg, u32 mem_size,
7270 u8 depth, struct bnxt_mem_init *mem_init)
7271 {
7272 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
7273 int rc;
7274
7275 if (!mem_size)
7276 return -EINVAL;
7277
7278 ctx_pg->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE);
7279 if (ctx_pg->nr_pages > MAX_CTX_TOTAL_PAGES) {
7280 ctx_pg->nr_pages = 0;
7281 return -EINVAL;
7282 }
7283 if (ctx_pg->nr_pages > MAX_CTX_PAGES || depth > 1) {
7284 int nr_tbls, i;
7285
7286 rmem->depth = 2;
7287 ctx_pg->ctx_pg_tbl = kcalloc(MAX_CTX_PAGES, sizeof(ctx_pg),
7288 GFP_KERNEL);
7289 if (!ctx_pg->ctx_pg_tbl)
7290 return -ENOMEM;
7291 nr_tbls = DIV_ROUND_UP(ctx_pg->nr_pages, MAX_CTX_PAGES);
7292 rmem->nr_pages = nr_tbls;
7293 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg);
7294 if (rc)
7295 return rc;
7296 for (i = 0; i < nr_tbls; i++) {
7297 struct bnxt_ctx_pg_info *pg_tbl;
7298
7299 pg_tbl = kzalloc(sizeof(*pg_tbl), GFP_KERNEL);
7300 if (!pg_tbl)
7301 return -ENOMEM;
7302 ctx_pg->ctx_pg_tbl[i] = pg_tbl;
7303 rmem = &pg_tbl->ring_mem;
7304 rmem->pg_tbl = ctx_pg->ctx_pg_arr[i];
7305 rmem->pg_tbl_map = ctx_pg->ctx_dma_arr[i];
7306 rmem->depth = 1;
7307 rmem->nr_pages = MAX_CTX_PAGES;
7308 rmem->mem_init = mem_init;
7309 if (i == (nr_tbls - 1)) {
7310 int rem = ctx_pg->nr_pages % MAX_CTX_PAGES;
7311
7312 if (rem)
7313 rmem->nr_pages = rem;
7314 }
7315 rc = bnxt_alloc_ctx_mem_blk(bp, pg_tbl);
7316 if (rc)
7317 break;
7318 }
7319 } else {
7320 rmem->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE);
7321 if (rmem->nr_pages > 1 || depth)
7322 rmem->depth = 1;
7323 rmem->mem_init = mem_init;
7324 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg);
7325 }
7326 return rc;
7327 }
7328
7329 static void bnxt_free_ctx_pg_tbls(struct bnxt *bp,
7330 struct bnxt_ctx_pg_info *ctx_pg)
7331 {
7332 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
7333
7334 if (rmem->depth > 1 || ctx_pg->nr_pages > MAX_CTX_PAGES ||
7335 ctx_pg->ctx_pg_tbl) {
7336 int i, nr_tbls = rmem->nr_pages;
7337
7338 for (i = 0; i < nr_tbls; i++) {
7339 struct bnxt_ctx_pg_info *pg_tbl;
7340 struct bnxt_ring_mem_info *rmem2;
7341
7342 pg_tbl = ctx_pg->ctx_pg_tbl[i];
7343 if (!pg_tbl)
7344 continue;
7345 rmem2 = &pg_tbl->ring_mem;
7346 bnxt_free_ring(bp, rmem2);
7347 ctx_pg->ctx_pg_arr[i] = NULL;
7348 kfree(pg_tbl);
7349 ctx_pg->ctx_pg_tbl[i] = NULL;
7350 }
7351 kfree(ctx_pg->ctx_pg_tbl);
7352 ctx_pg->ctx_pg_tbl = NULL;
7353 }
7354 bnxt_free_ring(bp, rmem);
7355 ctx_pg->nr_pages = 0;
7356 }
7357
7358 static void bnxt_free_ctx_mem(struct bnxt *bp)
7359 {
7360 struct bnxt_ctx_mem_info *ctx = bp->ctx;
7361 int i;
7362
7363 if (!ctx)
7364 return;
7365
7366 if (ctx->tqm_mem[0]) {
7367 for (i = 0; i < ctx->tqm_fp_rings_count + 1; i++)
7368 bnxt_free_ctx_pg_tbls(bp, ctx->tqm_mem[i]);
7369 kfree(ctx->tqm_mem[0]);
7370 ctx->tqm_mem[0] = NULL;
7371 }
7372
7373 bnxt_free_ctx_pg_tbls(bp, &ctx->tim_mem);
7374 bnxt_free_ctx_pg_tbls(bp, &ctx->mrav_mem);
7375 bnxt_free_ctx_pg_tbls(bp, &ctx->stat_mem);
7376 bnxt_free_ctx_pg_tbls(bp, &ctx->vnic_mem);
7377 bnxt_free_ctx_pg_tbls(bp, &ctx->cq_mem);
7378 bnxt_free_ctx_pg_tbls(bp, &ctx->srq_mem);
7379 bnxt_free_ctx_pg_tbls(bp, &ctx->qp_mem);
7380 ctx->flags &= ~BNXT_CTX_FLAG_INITED;
7381 }
7382
7383 static int bnxt_alloc_ctx_mem(struct bnxt *bp)
7384 {
7385 struct bnxt_ctx_pg_info *ctx_pg;
7386 struct bnxt_ctx_mem_info *ctx;
7387 struct bnxt_mem_init *init;
7388 u32 mem_size, ena, entries;
7389 u32 entries_sp, min;
7390 u32 num_mr, num_ah;
7391 u32 extra_srqs = 0;
7392 u32 extra_qps = 0;
7393 u8 pg_lvl = 1;
7394 int i, rc;
7395
7396 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
7397 if (rc) {
7398 netdev_err(bp->dev, "Failed querying context mem capability, rc = %d.\n",
7399 rc);
7400 return rc;
7401 }
7402 ctx = bp->ctx;
7403 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
7404 return 0;
7405
7406 if ((bp->flags & BNXT_FLAG_ROCE_CAP) && !is_kdump_kernel()) {
7407 pg_lvl = 2;
7408 extra_qps = 65536;
7409 extra_srqs = 8192;
7410 }
7411
7412 ctx_pg = &ctx->qp_mem;
7413 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries +
7414 extra_qps;
7415 if (ctx->qp_entry_size) {
7416 mem_size = ctx->qp_entry_size * ctx_pg->entries;
7417 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_QP];
7418 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, init);
7419 if (rc)
7420 return rc;
7421 }
7422
7423 ctx_pg = &ctx->srq_mem;
7424 ctx_pg->entries = ctx->srq_max_l2_entries + extra_srqs;
7425 if (ctx->srq_entry_size) {
7426 mem_size = ctx->srq_entry_size * ctx_pg->entries;
7427 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_SRQ];
7428 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, init);
7429 if (rc)
7430 return rc;
7431 }
7432
7433 ctx_pg = &ctx->cq_mem;
7434 ctx_pg->entries = ctx->cq_max_l2_entries + extra_qps * 2;
7435 if (ctx->cq_entry_size) {
7436 mem_size = ctx->cq_entry_size * ctx_pg->entries;
7437 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_CQ];
7438 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, init);
7439 if (rc)
7440 return rc;
7441 }
7442
7443 ctx_pg = &ctx->vnic_mem;
7444 ctx_pg->entries = ctx->vnic_max_vnic_entries +
7445 ctx->vnic_max_ring_table_entries;
7446 if (ctx->vnic_entry_size) {
7447 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
7448 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_VNIC];
7449 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, init);
7450 if (rc)
7451 return rc;
7452 }
7453
7454 ctx_pg = &ctx->stat_mem;
7455 ctx_pg->entries = ctx->stat_max_entries;
7456 if (ctx->stat_entry_size) {
7457 mem_size = ctx->stat_entry_size * ctx_pg->entries;
7458 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_STAT];
7459 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, init);
7460 if (rc)
7461 return rc;
7462 }
7463
7464 ena = 0;
7465 if (!(bp->flags & BNXT_FLAG_ROCE_CAP))
7466 goto skip_rdma;
7467
7468 ctx_pg = &ctx->mrav_mem;
7469 /* 128K extra is needed to accommodate static AH context
7470 * allocation by f/w.
7471 */
7472 num_mr = 1024 * 256;
7473 num_ah = 1024 * 128;
7474 ctx_pg->entries = num_mr + num_ah;
7475 if (ctx->mrav_entry_size) {
7476 mem_size = ctx->mrav_entry_size * ctx_pg->entries;
7477 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_MRAV];
7478 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 2, init);
7479 if (rc)
7480 return rc;
7481 }
7482 ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV;
7483 if (ctx->mrav_num_entries_units)
7484 ctx_pg->entries =
7485 ((num_mr / ctx->mrav_num_entries_units) << 16) |
7486 (num_ah / ctx->mrav_num_entries_units);
7487
7488 ctx_pg = &ctx->tim_mem;
7489 ctx_pg->entries = ctx->qp_mem.entries;
7490 if (ctx->tim_entry_size) {
7491 mem_size = ctx->tim_entry_size * ctx_pg->entries;
7492 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, NULL);
7493 if (rc)
7494 return rc;
7495 }
7496 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM;
7497
7498 skip_rdma:
7499 min = ctx->tqm_min_entries_per_ring;
7500 entries_sp = ctx->vnic_max_vnic_entries + ctx->qp_max_l2_entries +
7501 2 * (extra_qps + ctx->qp_min_qp1_entries) + min;
7502 entries_sp = roundup(entries_sp, ctx->tqm_entries_multiple);
7503 entries = ctx->qp_max_l2_entries + 2 * (extra_qps + ctx->qp_min_qp1_entries);
7504 entries = roundup(entries, ctx->tqm_entries_multiple);
7505 entries = clamp_t(u32, entries, min, ctx->tqm_max_entries_per_ring);
7506 for (i = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
7507 ctx_pg = ctx->tqm_mem[i];
7508 ctx_pg->entries = i ? entries : entries_sp;
7509 if (ctx->tqm_entry_size) {
7510 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
7511 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1,
7512 NULL);
7513 if (rc)
7514 return rc;
7515 }
7516 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP << i;
7517 }
7518 ena |= FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES;
7519 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
7520 if (rc) {
7521 netdev_err(bp->dev, "Failed configuring context mem, rc = %d.\n",
7522 rc);
7523 return rc;
7524 }
7525 ctx->flags |= BNXT_CTX_FLAG_INITED;
7526 return 0;
7527 }
7528
7529 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all)
7530 {
7531 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
7532 struct hwrm_func_resource_qcaps_input req = {0};
7533 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
7534 int rc;
7535
7536 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESOURCE_QCAPS, -1, -1);
7537 req.fid = cpu_to_le16(0xffff);
7538
7539 mutex_lock(&bp->hwrm_cmd_lock);
7540 rc = _hwrm_send_message_silent(bp, &req, sizeof(req),
7541 HWRM_CMD_TIMEOUT);
7542 if (rc)
7543 goto hwrm_func_resc_qcaps_exit;
7544
7545 hw_resc->max_tx_sch_inputs = le16_to_cpu(resp->max_tx_scheduler_inputs);
7546 if (!all)
7547 goto hwrm_func_resc_qcaps_exit;
7548
7549 hw_resc->min_rsscos_ctxs = le16_to_cpu(resp->min_rsscos_ctx);
7550 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
7551 hw_resc->min_cp_rings = le16_to_cpu(resp->min_cmpl_rings);
7552 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
7553 hw_resc->min_tx_rings = le16_to_cpu(resp->min_tx_rings);
7554 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
7555 hw_resc->min_rx_rings = le16_to_cpu(resp->min_rx_rings);
7556 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
7557 hw_resc->min_hw_ring_grps = le16_to_cpu(resp->min_hw_ring_grps);
7558 hw_resc->max_hw_ring_grps = le16_to_cpu(resp->max_hw_ring_grps);
7559 hw_resc->min_l2_ctxs = le16_to_cpu(resp->min_l2_ctxs);
7560 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
7561 hw_resc->min_vnics = le16_to_cpu(resp->min_vnics);
7562 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
7563 hw_resc->min_stat_ctxs = le16_to_cpu(resp->min_stat_ctx);
7564 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
7565
7566 if (bp->flags & BNXT_FLAG_CHIP_P5) {
7567 u16 max_msix = le16_to_cpu(resp->max_msix);
7568
7569 hw_resc->max_nqs = max_msix;
7570 hw_resc->max_hw_ring_grps = hw_resc->max_rx_rings;
7571 }
7572
7573 if (BNXT_PF(bp)) {
7574 struct bnxt_pf_info *pf = &bp->pf;
7575
7576 pf->vf_resv_strategy =
7577 le16_to_cpu(resp->vf_reservation_strategy);
7578 if (pf->vf_resv_strategy > BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC)
7579 pf->vf_resv_strategy = BNXT_VF_RESV_STRATEGY_MAXIMAL;
7580 }
7581 hwrm_func_resc_qcaps_exit:
7582 mutex_unlock(&bp->hwrm_cmd_lock);
7583 return rc;
7584 }
7585
7586 /* bp->hwrm_cmd_lock already held. */
7587 static int __bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
7588 {
7589 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
7590 struct hwrm_port_mac_ptp_qcfg_input req = {0};
7591 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
7592 u8 flags;
7593 int rc;
7594
7595 if (bp->hwrm_spec_code < 0x10801) {
7596 rc = -ENODEV;
7597 goto no_ptp;
7598 }
7599
7600 req.port_id = cpu_to_le16(bp->pf.port_id);
7601 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_MAC_PTP_QCFG, -1, -1);
7602 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7603 if (rc)
7604 goto no_ptp;
7605
7606 flags = resp->flags;
7607 if (!(flags & PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS)) {
7608 rc = -ENODEV;
7609 goto no_ptp;
7610 }
7611 if (!ptp) {
7612 ptp = kzalloc(sizeof(*ptp), GFP_KERNEL);
7613 if (!ptp)
7614 return -ENOMEM;
7615 ptp->bp = bp;
7616 bp->ptp_cfg = ptp;
7617 }
7618 if (flags & PORT_MAC_PTP_QCFG_RESP_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK) {
7619 ptp->refclk_regs[0] = le32_to_cpu(resp->ts_ref_clock_reg_lower);
7620 ptp->refclk_regs[1] = le32_to_cpu(resp->ts_ref_clock_reg_upper);
7621 } else if (bp->flags & BNXT_FLAG_CHIP_P5) {
7622 ptp->refclk_regs[0] = BNXT_TS_REG_TIMESYNC_TS0_LOWER;
7623 ptp->refclk_regs[1] = BNXT_TS_REG_TIMESYNC_TS0_UPPER;
7624 } else {
7625 rc = -ENODEV;
7626 goto no_ptp;
7627 }
7628 rc = bnxt_ptp_init(bp);
7629 if (!rc)
7630 return 0;
7631
7632 netdev_warn(bp->dev, "PTP initialization failed.\n");
7633
7634 no_ptp:
7635 bnxt_ptp_clear(bp);
7636 kfree(ptp);
7637 bp->ptp_cfg = NULL;
7638 return rc;
7639 }
7640
7641 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
7642 {
7643 int rc = 0;
7644 struct hwrm_func_qcaps_input req = {0};
7645 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
7646 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
7647 u32 flags, flags_ext;
7648
7649 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
7650 req.fid = cpu_to_le16(0xffff);
7651
7652 mutex_lock(&bp->hwrm_cmd_lock);
7653 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7654 if (rc)
7655 goto hwrm_func_qcaps_exit;
7656
7657 flags = le32_to_cpu(resp->flags);
7658 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED)
7659 bp->flags |= BNXT_FLAG_ROCEV1_CAP;
7660 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED)
7661 bp->flags |= BNXT_FLAG_ROCEV2_CAP;
7662 if (flags & FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED)
7663 bp->fw_cap |= BNXT_FW_CAP_PCIE_STATS_SUPPORTED;
7664 if (flags & FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE)
7665 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
7666 if (flags & FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED)
7667 bp->fw_cap |= BNXT_FW_CAP_EXT_STATS_SUPPORTED;
7668 if (flags & FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE)
7669 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
7670 if (flags & FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD)
7671 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
7672 if (!(flags & FUNC_QCAPS_RESP_FLAGS_VLAN_ACCELERATION_TX_DISABLED))
7673 bp->fw_cap |= BNXT_FW_CAP_VLAN_TX_INSERT;
7674
7675 flags_ext = le32_to_cpu(resp->flags_ext);
7676 if (flags_ext & FUNC_QCAPS_RESP_FLAGS_EXT_EXT_HW_STATS_SUPPORTED)
7677 bp->fw_cap |= BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED;
7678 if (BNXT_PF(bp) && (flags_ext & FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PPS_SUPPORTED))
7679 bp->fw_cap |= BNXT_FW_CAP_PTP_PPS;
7680
7681 bp->tx_push_thresh = 0;
7682 if ((flags & FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED) &&
7683 BNXT_FW_MAJ(bp) > 217)
7684 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
7685
7686 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
7687 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
7688 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
7689 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
7690 hw_resc->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
7691 if (!hw_resc->max_hw_ring_grps)
7692 hw_resc->max_hw_ring_grps = hw_resc->max_tx_rings;
7693 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
7694 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
7695 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
7696
7697 if (BNXT_PF(bp)) {
7698 struct bnxt_pf_info *pf = &bp->pf;
7699
7700 pf->fw_fid = le16_to_cpu(resp->fid);
7701 pf->port_id = le16_to_cpu(resp->port_id);
7702 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
7703 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
7704 pf->max_vfs = le16_to_cpu(resp->max_vfs);
7705 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
7706 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
7707 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
7708 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
7709 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
7710 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
7711 bp->flags &= ~BNXT_FLAG_WOL_CAP;
7712 if (flags & FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED)
7713 bp->flags |= BNXT_FLAG_WOL_CAP;
7714 if (flags & FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED) {
7715 __bnxt_hwrm_ptp_qcfg(bp);
7716 } else {
7717 bnxt_ptp_clear(bp);
7718 kfree(bp->ptp_cfg);
7719 bp->ptp_cfg = NULL;
7720 }
7721 } else {
7722 #ifdef CONFIG_BNXT_SRIOV
7723 struct bnxt_vf_info *vf = &bp->vf;
7724
7725 vf->fw_fid = le16_to_cpu(resp->fid);
7726 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
7727 #endif
7728 }
7729
7730 hwrm_func_qcaps_exit:
7731 mutex_unlock(&bp->hwrm_cmd_lock);
7732 return rc;
7733 }
7734
7735 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp);
7736
7737 static int bnxt_hwrm_func_qcaps(struct bnxt *bp)
7738 {
7739 int rc;
7740
7741 rc = __bnxt_hwrm_func_qcaps(bp);
7742 if (rc)
7743 return rc;
7744 rc = bnxt_hwrm_queue_qportcfg(bp);
7745 if (rc) {
7746 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %d\n", rc);
7747 return rc;
7748 }
7749 if (bp->hwrm_spec_code >= 0x10803) {
7750 rc = bnxt_alloc_ctx_mem(bp);
7751 if (rc)
7752 return rc;
7753 rc = bnxt_hwrm_func_resc_qcaps(bp, true);
7754 if (!rc)
7755 bp->fw_cap |= BNXT_FW_CAP_NEW_RM;
7756 }
7757 return 0;
7758 }
7759
7760 static int bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(struct bnxt *bp)
7761 {
7762 struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
7763 struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp;
7764 int rc = 0;
7765 u32 flags;
7766
7767 if (!(bp->fw_cap & BNXT_FW_CAP_CFA_ADV_FLOW))
7768 return 0;
7769
7770 resp = bp->hwrm_cmd_resp_addr;
7771 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, -1, -1);
7772
7773 mutex_lock(&bp->hwrm_cmd_lock);
7774 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7775 if (rc)
7776 goto hwrm_cfa_adv_qcaps_exit;
7777
7778 flags = le32_to_cpu(resp->flags);
7779 if (flags &
7780 CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED)
7781 bp->fw_cap |= BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2;
7782
7783 hwrm_cfa_adv_qcaps_exit:
7784 mutex_unlock(&bp->hwrm_cmd_lock);
7785 return rc;
7786 }
7787
7788 static int __bnxt_alloc_fw_health(struct bnxt *bp)
7789 {
7790 if (bp->fw_health)
7791 return 0;
7792
7793 bp->fw_health = kzalloc(sizeof(*bp->fw_health), GFP_KERNEL);
7794 if (!bp->fw_health)
7795 return -ENOMEM;
7796
7797 return 0;
7798 }
7799
7800 static int bnxt_alloc_fw_health(struct bnxt *bp)
7801 {
7802 int rc;
7803
7804 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET) &&
7805 !(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
7806 return 0;
7807
7808 rc = __bnxt_alloc_fw_health(bp);
7809 if (rc) {
7810 bp->fw_cap &= ~BNXT_FW_CAP_HOT_RESET;
7811 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
7812 return rc;
7813 }
7814
7815 return 0;
7816 }
7817
7818 static void __bnxt_map_fw_health_reg(struct bnxt *bp, u32 reg)
7819 {
7820 writel(reg & BNXT_GRC_BASE_MASK, bp->bar0 +
7821 BNXT_GRCPF_REG_WINDOW_BASE_OUT +
7822 BNXT_FW_HEALTH_WIN_MAP_OFF);
7823 }
7824
7825 bool bnxt_is_fw_healthy(struct bnxt *bp)
7826 {
7827 if (bp->fw_health && bp->fw_health->status_reliable) {
7828 u32 fw_status;
7829
7830 fw_status = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG);
7831 if (fw_status && !BNXT_FW_IS_HEALTHY(fw_status))
7832 return false;
7833 }
7834
7835 return true;
7836 }
7837
7838 static void bnxt_inv_fw_health_reg(struct bnxt *bp)
7839 {
7840 struct bnxt_fw_health *fw_health = bp->fw_health;
7841 u32 reg_type;
7842
7843 if (!fw_health || !fw_health->status_reliable)
7844 return;
7845
7846 reg_type = BNXT_FW_HEALTH_REG_TYPE(fw_health->regs[BNXT_FW_HEALTH_REG]);
7847 if (reg_type == BNXT_FW_HEALTH_REG_TYPE_GRC)
7848 fw_health->status_reliable = false;
7849 }
7850
7851 static void bnxt_try_map_fw_health_reg(struct bnxt *bp)
7852 {
7853 void __iomem *hs;
7854 u32 status_loc;
7855 u32 reg_type;
7856 u32 sig;
7857
7858 if (bp->fw_health)
7859 bp->fw_health->status_reliable = false;
7860
7861 __bnxt_map_fw_health_reg(bp, HCOMM_STATUS_STRUCT_LOC);
7862 hs = bp->bar0 + BNXT_FW_HEALTH_WIN_OFF(HCOMM_STATUS_STRUCT_LOC);
7863
7864 sig = readl(hs + offsetof(struct hcomm_status, sig_ver));
7865 if ((sig & HCOMM_STATUS_SIGNATURE_MASK) != HCOMM_STATUS_SIGNATURE_VAL) {
7866 if (!bp->chip_num) {
7867 __bnxt_map_fw_health_reg(bp, BNXT_GRC_REG_BASE);
7868 bp->chip_num = readl(bp->bar0 +
7869 BNXT_FW_HEALTH_WIN_BASE +
7870 BNXT_GRC_REG_CHIP_NUM);
7871 }
7872 if (!BNXT_CHIP_P5(bp))
7873 return;
7874
7875 status_loc = BNXT_GRC_REG_STATUS_P5 |
7876 BNXT_FW_HEALTH_REG_TYPE_BAR0;
7877 } else {
7878 status_loc = readl(hs + offsetof(struct hcomm_status,
7879 fw_status_loc));
7880 }
7881
7882 if (__bnxt_alloc_fw_health(bp)) {
7883 netdev_warn(bp->dev, "no memory for firmware status checks\n");
7884 return;
7885 }
7886
7887 bp->fw_health->regs[BNXT_FW_HEALTH_REG] = status_loc;
7888 reg_type = BNXT_FW_HEALTH_REG_TYPE(status_loc);
7889 if (reg_type == BNXT_FW_HEALTH_REG_TYPE_GRC) {
7890 __bnxt_map_fw_health_reg(bp, status_loc);
7891 bp->fw_health->mapped_regs[BNXT_FW_HEALTH_REG] =
7892 BNXT_FW_HEALTH_WIN_OFF(status_loc);
7893 }
7894
7895 bp->fw_health->status_reliable = true;
7896 }
7897
7898 static int bnxt_map_fw_health_regs(struct bnxt *bp)
7899 {
7900 struct bnxt_fw_health *fw_health = bp->fw_health;
7901 u32 reg_base = 0xffffffff;
7902 int i;
7903
7904 bp->fw_health->status_reliable = false;
7905 /* Only pre-map the monitoring GRC registers using window 3 */
7906 for (i = 0; i < 4; i++) {
7907 u32 reg = fw_health->regs[i];
7908
7909 if (BNXT_FW_HEALTH_REG_TYPE(reg) != BNXT_FW_HEALTH_REG_TYPE_GRC)
7910 continue;
7911 if (reg_base == 0xffffffff)
7912 reg_base = reg & BNXT_GRC_BASE_MASK;
7913 if ((reg & BNXT_GRC_BASE_MASK) != reg_base)
7914 return -ERANGE;
7915 fw_health->mapped_regs[i] = BNXT_FW_HEALTH_WIN_OFF(reg);
7916 }
7917 bp->fw_health->status_reliable = true;
7918 if (reg_base == 0xffffffff)
7919 return 0;
7920
7921 __bnxt_map_fw_health_reg(bp, reg_base);
7922 return 0;
7923 }
7924
7925 static int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
7926 {
7927 struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
7928 struct bnxt_fw_health *fw_health = bp->fw_health;
7929 struct hwrm_error_recovery_qcfg_input req = {0};
7930 int rc, i;
7931
7932 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
7933 return 0;
7934
7935 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_ERROR_RECOVERY_QCFG, -1, -1);
7936 mutex_lock(&bp->hwrm_cmd_lock);
7937 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7938 if (rc)
7939 goto err_recovery_out;
7940 fw_health->flags = le32_to_cpu(resp->flags);
7941 if ((fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) &&
7942 !(bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL)) {
7943 rc = -EINVAL;
7944 goto err_recovery_out;
7945 }
7946 fw_health->polling_dsecs = le32_to_cpu(resp->driver_polling_freq);
7947 fw_health->master_func_wait_dsecs =
7948 le32_to_cpu(resp->master_func_wait_period);
7949 fw_health->normal_func_wait_dsecs =
7950 le32_to_cpu(resp->normal_func_wait_period);
7951 fw_health->post_reset_wait_dsecs =
7952 le32_to_cpu(resp->master_func_wait_period_after_reset);
7953 fw_health->post_reset_max_wait_dsecs =
7954 le32_to_cpu(resp->max_bailout_time_after_reset);
7955 fw_health->regs[BNXT_FW_HEALTH_REG] =
7956 le32_to_cpu(resp->fw_health_status_reg);
7957 fw_health->regs[BNXT_FW_HEARTBEAT_REG] =
7958 le32_to_cpu(resp->fw_heartbeat_reg);
7959 fw_health->regs[BNXT_FW_RESET_CNT_REG] =
7960 le32_to_cpu(resp->fw_reset_cnt_reg);
7961 fw_health->regs[BNXT_FW_RESET_INPROG_REG] =
7962 le32_to_cpu(resp->reset_inprogress_reg);
7963 fw_health->fw_reset_inprog_reg_mask =
7964 le32_to_cpu(resp->reset_inprogress_reg_mask);
7965 fw_health->fw_reset_seq_cnt = resp->reg_array_cnt;
7966 if (fw_health->fw_reset_seq_cnt >= 16) {
7967 rc = -EINVAL;
7968 goto err_recovery_out;
7969 }
7970 for (i = 0; i < fw_health->fw_reset_seq_cnt; i++) {
7971 fw_health->fw_reset_seq_regs[i] =
7972 le32_to_cpu(resp->reset_reg[i]);
7973 fw_health->fw_reset_seq_vals[i] =
7974 le32_to_cpu(resp->reset_reg_val[i]);
7975 fw_health->fw_reset_seq_delay_msec[i] =
7976 resp->delay_after_reset[i];
7977 }
7978 err_recovery_out:
7979 mutex_unlock(&bp->hwrm_cmd_lock);
7980 if (!rc)
7981 rc = bnxt_map_fw_health_regs(bp);
7982 if (rc)
7983 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
7984 return rc;
7985 }
7986
7987 static int bnxt_hwrm_func_reset(struct bnxt *bp)
7988 {
7989 struct hwrm_func_reset_input req = {0};
7990
7991 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
7992 req.enables = 0;
7993
7994 return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
7995 }
7996
7997 static void bnxt_nvm_cfg_ver_get(struct bnxt *bp)
7998 {
7999 struct hwrm_nvm_get_dev_info_output nvm_info;
8000
8001 if (!bnxt_hwrm_nvm_get_dev_info(bp, &nvm_info))
8002 snprintf(bp->nvm_cfg_ver, FW_VER_STR_LEN, "%d.%d.%d",
8003 nvm_info.nvm_cfg_ver_maj, nvm_info.nvm_cfg_ver_min,
8004 nvm_info.nvm_cfg_ver_upd);
8005 }
8006
8007 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
8008 {
8009 int rc = 0;
8010 struct hwrm_queue_qportcfg_input req = {0};
8011 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
8012 u8 i, j, *qptr;
8013 bool no_rdma;
8014
8015 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
8016
8017 mutex_lock(&bp->hwrm_cmd_lock);
8018 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8019 if (rc)
8020 goto qportcfg_exit;
8021
8022 if (!resp->max_configurable_queues) {
8023 rc = -EINVAL;
8024 goto qportcfg_exit;
8025 }
8026 bp->max_tc = resp->max_configurable_queues;
8027 bp->max_lltc = resp->max_configurable_lossless_queues;
8028 if (bp->max_tc > BNXT_MAX_QUEUE)
8029 bp->max_tc = BNXT_MAX_QUEUE;
8030
8031 no_rdma = !(bp->flags & BNXT_FLAG_ROCE_CAP);
8032 qptr = &resp->queue_id0;
8033 for (i = 0, j = 0; i < bp->max_tc; i++) {
8034 bp->q_info[j].queue_id = *qptr;
8035 bp->q_ids[i] = *qptr++;
8036 bp->q_info[j].queue_profile = *qptr++;
8037 bp->tc_to_qidx[j] = j;
8038 if (!BNXT_CNPQ(bp->q_info[j].queue_profile) ||
8039 (no_rdma && BNXT_PF(bp)))
8040 j++;
8041 }
8042 bp->max_q = bp->max_tc;
8043 bp->max_tc = max_t(u8, j, 1);
8044
8045 if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG)
8046 bp->max_tc = 1;
8047
8048 if (bp->max_lltc > bp->max_tc)
8049 bp->max_lltc = bp->max_tc;
8050
8051 qportcfg_exit:
8052 mutex_unlock(&bp->hwrm_cmd_lock);
8053 return rc;
8054 }
8055
8056 static int __bnxt_hwrm_ver_get(struct bnxt *bp, bool silent)
8057 {
8058 struct hwrm_ver_get_input req = {0};
8059 int rc;
8060
8061 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
8062 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
8063 req.hwrm_intf_min = HWRM_VERSION_MINOR;
8064 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
8065
8066 rc = bnxt_hwrm_do_send_msg(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT,
8067 silent);
8068 return rc;
8069 }
8070
8071 static int bnxt_hwrm_ver_get(struct bnxt *bp)
8072 {
8073 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
8074 u16 fw_maj, fw_min, fw_bld, fw_rsv;
8075 u32 dev_caps_cfg, hwrm_ver;
8076 int rc, len;
8077
8078 bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
8079 mutex_lock(&bp->hwrm_cmd_lock);
8080 rc = __bnxt_hwrm_ver_get(bp, false);
8081 if (rc)
8082 goto hwrm_ver_get_exit;
8083
8084 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
8085
8086 bp->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 |
8087 resp->hwrm_intf_min_8b << 8 |
8088 resp->hwrm_intf_upd_8b;
8089 if (resp->hwrm_intf_maj_8b < 1) {
8090 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
8091 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
8092 resp->hwrm_intf_upd_8b);
8093 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
8094 }
8095
8096 hwrm_ver = HWRM_VERSION_MAJOR << 16 | HWRM_VERSION_MINOR << 8 |
8097 HWRM_VERSION_UPDATE;
8098
8099 if (bp->hwrm_spec_code > hwrm_ver)
8100 snprintf(bp->hwrm_ver_supp, FW_VER_STR_LEN, "%d.%d.%d",
8101 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR,
8102 HWRM_VERSION_UPDATE);
8103 else
8104 snprintf(bp->hwrm_ver_supp, FW_VER_STR_LEN, "%d.%d.%d",
8105 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
8106 resp->hwrm_intf_upd_8b);
8107
8108 fw_maj = le16_to_cpu(resp->hwrm_fw_major);
8109 if (bp->hwrm_spec_code > 0x10803 && fw_maj) {
8110 fw_min = le16_to_cpu(resp->hwrm_fw_minor);
8111 fw_bld = le16_to_cpu(resp->hwrm_fw_build);
8112 fw_rsv = le16_to_cpu(resp->hwrm_fw_patch);
8113 len = FW_VER_STR_LEN;
8114 } else {
8115 fw_maj = resp->hwrm_fw_maj_8b;
8116 fw_min = resp->hwrm_fw_min_8b;
8117 fw_bld = resp->hwrm_fw_bld_8b;
8118 fw_rsv = resp->hwrm_fw_rsvd_8b;
8119 len = BC_HWRM_STR_LEN;
8120 }
8121 bp->fw_ver_code = BNXT_FW_VER_CODE(fw_maj, fw_min, fw_bld, fw_rsv);
8122 snprintf(bp->fw_ver_str, len, "%d.%d.%d.%d", fw_maj, fw_min, fw_bld,
8123 fw_rsv);
8124
8125 if (strlen(resp->active_pkg_name)) {
8126 int fw_ver_len = strlen(bp->fw_ver_str);
8127
8128 snprintf(bp->fw_ver_str + fw_ver_len,
8129 FW_VER_STR_LEN - fw_ver_len - 1, "/pkg %s",
8130 resp->active_pkg_name);
8131 bp->fw_cap |= BNXT_FW_CAP_PKG_VER;
8132 }
8133
8134 bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
8135 if (!bp->hwrm_cmd_timeout)
8136 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
8137
8138 if (resp->hwrm_intf_maj_8b >= 1) {
8139 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
8140 bp->hwrm_max_ext_req_len = le16_to_cpu(resp->max_ext_req_len);
8141 }
8142 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
8143 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
8144
8145 bp->chip_num = le16_to_cpu(resp->chip_num);
8146 bp->chip_rev = resp->chip_rev;
8147 if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev &&
8148 !resp->chip_metal)
8149 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0;
8150
8151 dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg);
8152 if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
8153 (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED))
8154 bp->fw_cap |= BNXT_FW_CAP_SHORT_CMD;
8155
8156 if (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED)
8157 bp->fw_cap |= BNXT_FW_CAP_KONG_MB_CHNL;
8158
8159 if (dev_caps_cfg &
8160 VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED)
8161 bp->fw_cap |= BNXT_FW_CAP_OVS_64BIT_HANDLE;
8162
8163 if (dev_caps_cfg &
8164 VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
8165 bp->fw_cap |= BNXT_FW_CAP_TRUSTED_VF;
8166
8167 if (dev_caps_cfg &
8168 VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED)
8169 bp->fw_cap |= BNXT_FW_CAP_CFA_ADV_FLOW;
8170
8171 hwrm_ver_get_exit:
8172 mutex_unlock(&bp->hwrm_cmd_lock);
8173 return rc;
8174 }
8175
8176 int bnxt_hwrm_fw_set_time(struct bnxt *bp)
8177 {
8178 struct hwrm_fw_set_time_input req = {0};
8179 struct tm tm;
8180 time64_t now = ktime_get_real_seconds();
8181
8182 if ((BNXT_VF(bp) && bp->hwrm_spec_code < 0x10901) ||
8183 bp->hwrm_spec_code < 0x10400)
8184 return -EOPNOTSUPP;
8185
8186 time64_to_tm(now, 0, &tm);
8187 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1);
8188 req.year = cpu_to_le16(1900 + tm.tm_year);
8189 req.month = 1 + tm.tm_mon;
8190 req.day = tm.tm_mday;
8191 req.hour = tm.tm_hour;
8192 req.minute = tm.tm_min;
8193 req.second = tm.tm_sec;
8194 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8195 }
8196
8197 static void bnxt_add_one_ctr(u64 hw, u64 *sw, u64 mask)
8198 {
8199 u64 sw_tmp;
8200
8201 hw &= mask;
8202 sw_tmp = (*sw & ~mask) | hw;
8203 if (hw < (*sw & mask))
8204 sw_tmp += mask + 1;
8205 WRITE_ONCE(*sw, sw_tmp);
8206 }
8207
8208 static void __bnxt_accumulate_stats(__le64 *hw_stats, u64 *sw_stats, u64 *masks,
8209 int count, bool ignore_zero)
8210 {
8211 int i;
8212
8213 for (i = 0; i < count; i++) {
8214 u64 hw = le64_to_cpu(READ_ONCE(hw_stats[i]));
8215
8216 if (ignore_zero && !hw)
8217 continue;
8218
8219 if (masks[i] == -1ULL)
8220 sw_stats[i] = hw;
8221 else
8222 bnxt_add_one_ctr(hw, &sw_stats[i], masks[i]);
8223 }
8224 }
8225
8226 static void bnxt_accumulate_stats(struct bnxt_stats_mem *stats)
8227 {
8228 if (!stats->hw_stats)
8229 return;
8230
8231 __bnxt_accumulate_stats(stats->hw_stats, stats->sw_stats,
8232 stats->hw_masks, stats->len / 8, false);
8233 }
8234
8235 static void bnxt_accumulate_all_stats(struct bnxt *bp)
8236 {
8237 struct bnxt_stats_mem *ring0_stats;
8238 bool ignore_zero = false;
8239 int i;
8240
8241 /* Chip bug. Counter intermittently becomes 0. */
8242 if (bp->flags & BNXT_FLAG_CHIP_P5)
8243 ignore_zero = true;
8244
8245 for (i = 0; i < bp->cp_nr_rings; i++) {
8246 struct bnxt_napi *bnapi = bp->bnapi[i];
8247 struct bnxt_cp_ring_info *cpr;
8248 struct bnxt_stats_mem *stats;
8249
8250 cpr = &bnapi->cp_ring;
8251 stats = &cpr->stats;
8252 if (!i)
8253 ring0_stats = stats;
8254 __bnxt_accumulate_stats(stats->hw_stats, stats->sw_stats,
8255 ring0_stats->hw_masks,
8256 ring0_stats->len / 8, ignore_zero);
8257 }
8258 if (bp->flags & BNXT_FLAG_PORT_STATS) {
8259 struct bnxt_stats_mem *stats = &bp->port_stats;
8260 __le64 *hw_stats = stats->hw_stats;
8261 u64 *sw_stats = stats->sw_stats;
8262 u64 *masks = stats->hw_masks;
8263 int cnt;
8264
8265 cnt = sizeof(struct rx_port_stats) / 8;
8266 __bnxt_accumulate_stats(hw_stats, sw_stats, masks, cnt, false);
8267
8268 hw_stats += BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
8269 sw_stats += BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
8270 masks += BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
8271 cnt = sizeof(struct tx_port_stats) / 8;
8272 __bnxt_accumulate_stats(hw_stats, sw_stats, masks, cnt, false);
8273 }
8274 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
8275 bnxt_accumulate_stats(&bp->rx_port_stats_ext);
8276 bnxt_accumulate_stats(&bp->tx_port_stats_ext);
8277 }
8278 }
8279
8280 static int bnxt_hwrm_port_qstats(struct bnxt *bp, u8 flags)
8281 {
8282 struct bnxt_pf_info *pf = &bp->pf;
8283 struct hwrm_port_qstats_input req = {0};
8284
8285 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
8286 return 0;
8287
8288 if (flags && !(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED))
8289 return -EOPNOTSUPP;
8290
8291 req.flags = flags;
8292 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
8293 req.port_id = cpu_to_le16(pf->port_id);
8294 req.tx_stat_host_addr = cpu_to_le64(bp->port_stats.hw_stats_map +
8295 BNXT_TX_PORT_STATS_BYTE_OFFSET);
8296 req.rx_stat_host_addr = cpu_to_le64(bp->port_stats.hw_stats_map);
8297 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8298 }
8299
8300 static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp, u8 flags)
8301 {
8302 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
8303 struct hwrm_queue_pri2cos_qcfg_input req2 = {0};
8304 struct hwrm_port_qstats_ext_input req = {0};
8305 struct bnxt_pf_info *pf = &bp->pf;
8306 u32 tx_stat_size;
8307 int rc;
8308
8309 if (!(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
8310 return 0;
8311
8312 if (flags && !(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED))
8313 return -EOPNOTSUPP;
8314
8315 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS_EXT, -1, -1);
8316 req.flags = flags;
8317 req.port_id = cpu_to_le16(pf->port_id);
8318 req.rx_stat_size = cpu_to_le16(sizeof(struct rx_port_stats_ext));
8319 req.rx_stat_host_addr = cpu_to_le64(bp->rx_port_stats_ext.hw_stats_map);
8320 tx_stat_size = bp->tx_port_stats_ext.hw_stats ?
8321 sizeof(struct tx_port_stats_ext) : 0;
8322 req.tx_stat_size = cpu_to_le16(tx_stat_size);
8323 req.tx_stat_host_addr = cpu_to_le64(bp->tx_port_stats_ext.hw_stats_map);
8324 mutex_lock(&bp->hwrm_cmd_lock);
8325 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8326 if (!rc) {
8327 bp->fw_rx_stats_ext_size = le16_to_cpu(resp->rx_stat_size) / 8;
8328 bp->fw_tx_stats_ext_size = tx_stat_size ?
8329 le16_to_cpu(resp->tx_stat_size) / 8 : 0;
8330 } else {
8331 bp->fw_rx_stats_ext_size = 0;
8332 bp->fw_tx_stats_ext_size = 0;
8333 }
8334 if (flags)
8335 goto qstats_done;
8336
8337 if (bp->fw_tx_stats_ext_size <=
8338 offsetof(struct tx_port_stats_ext, pfc_pri0_tx_duration_us) / 8) {
8339 mutex_unlock(&bp->hwrm_cmd_lock);
8340 bp->pri2cos_valid = 0;
8341 return rc;
8342 }
8343
8344 bnxt_hwrm_cmd_hdr_init(bp, &req2, HWRM_QUEUE_PRI2COS_QCFG, -1, -1);
8345 req2.flags = cpu_to_le32(QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN);
8346
8347 rc = _hwrm_send_message(bp, &req2, sizeof(req2), HWRM_CMD_TIMEOUT);
8348 if (!rc) {
8349 struct hwrm_queue_pri2cos_qcfg_output *resp2;
8350 u8 *pri2cos;
8351 int i, j;
8352
8353 resp2 = bp->hwrm_cmd_resp_addr;
8354 pri2cos = &resp2->pri0_cos_queue_id;
8355 for (i = 0; i < 8; i++) {
8356 u8 queue_id = pri2cos[i];
8357 u8 queue_idx;
8358
8359 /* Per port queue IDs start from 0, 10, 20, etc */
8360 queue_idx = queue_id % 10;
8361 if (queue_idx > BNXT_MAX_QUEUE) {
8362 bp->pri2cos_valid = false;
8363 goto qstats_done;
8364 }
8365 for (j = 0; j < bp->max_q; j++) {
8366 if (bp->q_ids[j] == queue_id)
8367 bp->pri2cos_idx[i] = queue_idx;
8368 }
8369 }
8370 bp->pri2cos_valid = 1;
8371 }
8372 qstats_done:
8373 mutex_unlock(&bp->hwrm_cmd_lock);
8374 return rc;
8375 }
8376
8377 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
8378 {
8379 if (bp->vxlan_fw_dst_port_id != INVALID_HW_RING_ID)
8380 bnxt_hwrm_tunnel_dst_port_free(
8381 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
8382 if (bp->nge_fw_dst_port_id != INVALID_HW_RING_ID)
8383 bnxt_hwrm_tunnel_dst_port_free(
8384 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
8385 }
8386
8387 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
8388 {
8389 int rc, i;
8390 u32 tpa_flags = 0;
8391
8392 if (set_tpa)
8393 tpa_flags = bp->flags & BNXT_FLAG_TPA;
8394 else if (BNXT_NO_FW_ACCESS(bp))
8395 return 0;
8396 for (i = 0; i < bp->nr_vnics; i++) {
8397 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
8398 if (rc) {
8399 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
8400 i, rc);
8401 return rc;
8402 }
8403 }
8404 return 0;
8405 }
8406
8407 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
8408 {
8409 int i;
8410
8411 for (i = 0; i < bp->nr_vnics; i++)
8412 bnxt_hwrm_vnic_set_rss(bp, i, false);
8413 }
8414
8415 static void bnxt_clear_vnic(struct bnxt *bp)
8416 {
8417 if (!bp->vnic_info)
8418 return;
8419
8420 bnxt_hwrm_clear_vnic_filter(bp);
8421 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) {
8422 /* clear all RSS setting before free vnic ctx */
8423 bnxt_hwrm_clear_vnic_rss(bp);
8424 bnxt_hwrm_vnic_ctx_free(bp);
8425 }
8426 /* before free the vnic, undo the vnic tpa settings */
8427 if (bp->flags & BNXT_FLAG_TPA)
8428 bnxt_set_tpa(bp, false);
8429 bnxt_hwrm_vnic_free(bp);
8430 if (bp->flags & BNXT_FLAG_CHIP_P5)
8431 bnxt_hwrm_vnic_ctx_free(bp);
8432 }
8433
8434 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
8435 bool irq_re_init)
8436 {
8437 bnxt_clear_vnic(bp);
8438 bnxt_hwrm_ring_free(bp, close_path);
8439 bnxt_hwrm_ring_grp_free(bp);
8440 if (irq_re_init) {
8441 bnxt_hwrm_stat_ctx_free(bp);
8442 bnxt_hwrm_free_tunnel_ports(bp);
8443 }
8444 }
8445
8446 static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode)
8447 {
8448 struct hwrm_func_cfg_input req = {0};
8449
8450 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
8451 req.fid = cpu_to_le16(0xffff);
8452 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE);
8453 if (br_mode == BRIDGE_MODE_VEB)
8454 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB;
8455 else if (br_mode == BRIDGE_MODE_VEPA)
8456 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA;
8457 else
8458 return -EINVAL;
8459 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8460 }
8461
8462 static int bnxt_hwrm_set_cache_line_size(struct bnxt *bp, int size)
8463 {
8464 struct hwrm_func_cfg_input req = {0};
8465
8466 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10803)
8467 return 0;
8468
8469 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
8470 req.fid = cpu_to_le16(0xffff);
8471 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE);
8472 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64;
8473 if (size == 128)
8474 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128;
8475
8476 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8477 }
8478
8479 static int __bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
8480 {
8481 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
8482 int rc;
8483
8484 if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG)
8485 goto skip_rss_ctx;
8486
8487 /* allocate context for vnic */
8488 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0);
8489 if (rc) {
8490 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
8491 vnic_id, rc);
8492 goto vnic_setup_err;
8493 }
8494 bp->rsscos_nr_ctxs++;
8495
8496 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
8497 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1);
8498 if (rc) {
8499 netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
8500 vnic_id, rc);
8501 goto vnic_setup_err;
8502 }
8503 bp->rsscos_nr_ctxs++;
8504 }
8505
8506 skip_rss_ctx:
8507 /* configure default vnic, ring grp */
8508 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
8509 if (rc) {
8510 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
8511 vnic_id, rc);
8512 goto vnic_setup_err;
8513 }
8514
8515 /* Enable RSS hashing on vnic */
8516 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
8517 if (rc) {
8518 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
8519 vnic_id, rc);
8520 goto vnic_setup_err;
8521 }
8522
8523 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
8524 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
8525 if (rc) {
8526 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
8527 vnic_id, rc);
8528 }
8529 }
8530
8531 vnic_setup_err:
8532 return rc;
8533 }
8534
8535 static int __bnxt_setup_vnic_p5(struct bnxt *bp, u16 vnic_id)
8536 {
8537 int rc, i, nr_ctxs;
8538
8539 nr_ctxs = bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings);
8540 for (i = 0; i < nr_ctxs; i++) {
8541 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, i);
8542 if (rc) {
8543 netdev_err(bp->dev, "hwrm vnic %d ctx %d alloc failure rc: %x\n",
8544 vnic_id, i, rc);
8545 break;
8546 }
8547 bp->rsscos_nr_ctxs++;
8548 }
8549 if (i < nr_ctxs)
8550 return -ENOMEM;
8551
8552 rc = bnxt_hwrm_vnic_set_rss_p5(bp, vnic_id, true);
8553 if (rc) {
8554 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %d\n",
8555 vnic_id, rc);
8556 return rc;
8557 }
8558 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
8559 if (rc) {
8560 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
8561 vnic_id, rc);
8562 return rc;
8563 }
8564 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
8565 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
8566 if (rc) {
8567 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
8568 vnic_id, rc);
8569 }
8570 }
8571 return rc;
8572 }
8573
8574 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
8575 {
8576 if (bp->flags & BNXT_FLAG_CHIP_P5)
8577 return __bnxt_setup_vnic_p5(bp, vnic_id);
8578 else
8579 return __bnxt_setup_vnic(bp, vnic_id);
8580 }
8581
8582 static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
8583 {
8584 #ifdef CONFIG_RFS_ACCEL
8585 int i, rc = 0;
8586
8587 if (bp->flags & BNXT_FLAG_CHIP_P5)
8588 return 0;
8589
8590 for (i = 0; i < bp->rx_nr_rings; i++) {
8591 struct bnxt_vnic_info *vnic;
8592 u16 vnic_id = i + 1;
8593 u16 ring_id = i;
8594
8595 if (vnic_id >= bp->nr_vnics)
8596 break;
8597
8598 vnic = &bp->vnic_info[vnic_id];
8599 vnic->flags |= BNXT_VNIC_RFS_FLAG;
8600 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
8601 vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG;
8602 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
8603 if (rc) {
8604 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
8605 vnic_id, rc);
8606 break;
8607 }
8608 rc = bnxt_setup_vnic(bp, vnic_id);
8609 if (rc)
8610 break;
8611 }
8612 return rc;
8613 #else
8614 return 0;
8615 #endif
8616 }
8617
8618 /* Allow PF, trusted VFs and VFs with default VLAN to be in promiscuous mode */
8619 static bool bnxt_promisc_ok(struct bnxt *bp)
8620 {
8621 #ifdef CONFIG_BNXT_SRIOV
8622 if (BNXT_VF(bp) && !bp->vf.vlan && !bnxt_is_trusted_vf(bp, &bp->vf))
8623 return false;
8624 #endif
8625 return true;
8626 }
8627
8628 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp)
8629 {
8630 unsigned int rc = 0;
8631
8632 rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1);
8633 if (rc) {
8634 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
8635 rc);
8636 return rc;
8637 }
8638
8639 rc = bnxt_hwrm_vnic_cfg(bp, 1);
8640 if (rc) {
8641 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
8642 rc);
8643 return rc;
8644 }
8645 return rc;
8646 }
8647
8648 static int bnxt_cfg_rx_mode(struct bnxt *);
8649 static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
8650
8651 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
8652 {
8653 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
8654 int rc = 0;
8655 unsigned int rx_nr_rings = bp->rx_nr_rings;
8656
8657 if (irq_re_init) {
8658 rc = bnxt_hwrm_stat_ctx_alloc(bp);
8659 if (rc) {
8660 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
8661 rc);
8662 goto err_out;
8663 }
8664 }
8665
8666 rc = bnxt_hwrm_ring_alloc(bp);
8667 if (rc) {
8668 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
8669 goto err_out;
8670 }
8671
8672 rc = bnxt_hwrm_ring_grp_alloc(bp);
8673 if (rc) {
8674 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
8675 goto err_out;
8676 }
8677
8678 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
8679 rx_nr_rings--;
8680
8681 /* default vnic 0 */
8682 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings);
8683 if (rc) {
8684 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
8685 goto err_out;
8686 }
8687
8688 rc = bnxt_setup_vnic(bp, 0);
8689 if (rc)
8690 goto err_out;
8691
8692 if (bp->flags & BNXT_FLAG_RFS) {
8693 rc = bnxt_alloc_rfs_vnics(bp);
8694 if (rc)
8695 goto err_out;
8696 }
8697
8698 if (bp->flags & BNXT_FLAG_TPA) {
8699 rc = bnxt_set_tpa(bp, true);
8700 if (rc)
8701 goto err_out;
8702 }
8703
8704 if (BNXT_VF(bp))
8705 bnxt_update_vf_mac(bp);
8706
8707 /* Filter for default vnic 0 */
8708 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
8709 if (rc) {
8710 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
8711 goto err_out;
8712 }
8713 vnic->uc_filter_count = 1;
8714
8715 vnic->rx_mask = 0;
8716 if (bp->dev->flags & IFF_BROADCAST)
8717 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
8718
8719 if (bp->dev->flags & IFF_PROMISC)
8720 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
8721
8722 if (bp->dev->flags & IFF_ALLMULTI) {
8723 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
8724 vnic->mc_list_count = 0;
8725 } else {
8726 u32 mask = 0;
8727
8728 bnxt_mc_list_updated(bp, &mask);
8729 vnic->rx_mask |= mask;
8730 }
8731
8732 rc = bnxt_cfg_rx_mode(bp);
8733 if (rc)
8734 goto err_out;
8735
8736 rc = bnxt_hwrm_set_coal(bp);
8737 if (rc)
8738 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
8739 rc);
8740
8741 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
8742 rc = bnxt_setup_nitroa0_vnic(bp);
8743 if (rc)
8744 netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n",
8745 rc);
8746 }
8747
8748 if (BNXT_VF(bp)) {
8749 bnxt_hwrm_func_qcfg(bp);
8750 netdev_update_features(bp->dev);
8751 }
8752
8753 return 0;
8754
8755 err_out:
8756 bnxt_hwrm_resource_free(bp, 0, true);
8757
8758 return rc;
8759 }
8760
8761 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
8762 {
8763 bnxt_hwrm_resource_free(bp, 1, irq_re_init);
8764 return 0;
8765 }
8766
8767 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
8768 {
8769 bnxt_init_cp_rings(bp);
8770 bnxt_init_rx_rings(bp);
8771 bnxt_init_tx_rings(bp);
8772 bnxt_init_ring_grps(bp, irq_re_init);
8773 bnxt_init_vnics(bp);
8774
8775 return bnxt_init_chip(bp, irq_re_init);
8776 }
8777
8778 static int bnxt_set_real_num_queues(struct bnxt *bp)
8779 {
8780 int rc;
8781 struct net_device *dev = bp->dev;
8782
8783 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings -
8784 bp->tx_nr_rings_xdp);
8785 if (rc)
8786 return rc;
8787
8788 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
8789 if (rc)
8790 return rc;
8791
8792 #ifdef CONFIG_RFS_ACCEL
8793 if (bp->flags & BNXT_FLAG_RFS)
8794 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
8795 #endif
8796
8797 return rc;
8798 }
8799
8800 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
8801 bool shared)
8802 {
8803 int _rx = *rx, _tx = *tx;
8804
8805 if (shared) {
8806 *rx = min_t(int, _rx, max);
8807 *tx = min_t(int, _tx, max);
8808 } else {
8809 if (max < 2)
8810 return -ENOMEM;
8811
8812 while (_rx + _tx > max) {
8813 if (_rx > _tx && _rx > 1)
8814 _rx--;
8815 else if (_tx > 1)
8816 _tx--;
8817 }
8818 *rx = _rx;
8819 *tx = _tx;
8820 }
8821 return 0;
8822 }
8823
8824 static void bnxt_setup_msix(struct bnxt *bp)
8825 {
8826 const int len = sizeof(bp->irq_tbl[0].name);
8827 struct net_device *dev = bp->dev;
8828 int tcs, i;
8829
8830 tcs = netdev_get_num_tc(dev);
8831 if (tcs) {
8832 int i, off, count;
8833
8834 for (i = 0; i < tcs; i++) {
8835 count = bp->tx_nr_rings_per_tc;
8836 off = i * count;
8837 netdev_set_tc_queue(dev, i, count, off);
8838 }
8839 }
8840
8841 for (i = 0; i < bp->cp_nr_rings; i++) {
8842 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
8843 char *attr;
8844
8845 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
8846 attr = "TxRx";
8847 else if (i < bp->rx_nr_rings)
8848 attr = "rx";
8849 else
8850 attr = "tx";
8851
8852 snprintf(bp->irq_tbl[map_idx].name, len, "%s-%s-%d", dev->name,
8853 attr, i);
8854 bp->irq_tbl[map_idx].handler = bnxt_msix;
8855 }
8856 }
8857
8858 static void bnxt_setup_inta(struct bnxt *bp)
8859 {
8860 const int len = sizeof(bp->irq_tbl[0].name);
8861
8862 if (netdev_get_num_tc(bp->dev))
8863 netdev_reset_tc(bp->dev);
8864
8865 snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx",
8866 0);
8867 bp->irq_tbl[0].handler = bnxt_inta;
8868 }
8869
8870 static int bnxt_init_int_mode(struct bnxt *bp);
8871
8872 static int bnxt_setup_int_mode(struct bnxt *bp)
8873 {
8874 int rc;
8875
8876 if (!bp->irq_tbl) {
8877 rc = bnxt_init_int_mode(bp);
8878 if (rc || !bp->irq_tbl)
8879 return rc ?: -ENODEV;
8880 }
8881
8882 if (bp->flags & BNXT_FLAG_USING_MSIX)
8883 bnxt_setup_msix(bp);
8884 else
8885 bnxt_setup_inta(bp);
8886
8887 rc = bnxt_set_real_num_queues(bp);
8888 return rc;
8889 }
8890
8891 #ifdef CONFIG_RFS_ACCEL
8892 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp)
8893 {
8894 return bp->hw_resc.max_rsscos_ctxs;
8895 }
8896
8897 static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp)
8898 {
8899 return bp->hw_resc.max_vnics;
8900 }
8901 #endif
8902
8903 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp)
8904 {
8905 return bp->hw_resc.max_stat_ctxs;
8906 }
8907
8908 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp)
8909 {
8910 return bp->hw_resc.max_cp_rings;
8911 }
8912
8913 static unsigned int bnxt_get_max_func_cp_rings_for_en(struct bnxt *bp)
8914 {
8915 unsigned int cp = bp->hw_resc.max_cp_rings;
8916
8917 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
8918 cp -= bnxt_get_ulp_msix_num(bp);
8919
8920 return cp;
8921 }
8922
8923 static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp)
8924 {
8925 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
8926
8927 if (bp->flags & BNXT_FLAG_CHIP_P5)
8928 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_nqs);
8929
8930 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_cp_rings);
8931 }
8932
8933 static void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs)
8934 {
8935 bp->hw_resc.max_irqs = max_irqs;
8936 }
8937
8938 unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp)
8939 {
8940 unsigned int cp;
8941
8942 cp = bnxt_get_max_func_cp_rings_for_en(bp);
8943 if (bp->flags & BNXT_FLAG_CHIP_P5)
8944 return cp - bp->rx_nr_rings - bp->tx_nr_rings;
8945 else
8946 return cp - bp->cp_nr_rings;
8947 }
8948
8949 unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp)
8950 {
8951 return bnxt_get_max_func_stat_ctxs(bp) - bnxt_get_func_stat_ctxs(bp);
8952 }
8953
8954 int bnxt_get_avail_msix(struct bnxt *bp, int num)
8955 {
8956 int max_cp = bnxt_get_max_func_cp_rings(bp);
8957 int max_irq = bnxt_get_max_func_irqs(bp);
8958 int total_req = bp->cp_nr_rings + num;
8959 int max_idx, avail_msix;
8960
8961 max_idx = bp->total_irqs;
8962 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
8963 max_idx = min_t(int, bp->total_irqs, max_cp);
8964 avail_msix = max_idx - bp->cp_nr_rings;
8965 if (!BNXT_NEW_RM(bp) || avail_msix >= num)
8966 return avail_msix;
8967
8968 if (max_irq < total_req) {
8969 num = max_irq - bp->cp_nr_rings;
8970 if (num <= 0)
8971 return 0;
8972 }
8973 return num;
8974 }
8975
8976 static int bnxt_get_num_msix(struct bnxt *bp)
8977 {
8978 if (!BNXT_NEW_RM(bp))
8979 return bnxt_get_max_func_irqs(bp);
8980
8981 return bnxt_nq_rings_in_use(bp);
8982 }
8983
8984 static int bnxt_init_msix(struct bnxt *bp)
8985 {
8986 int i, total_vecs, max, rc = 0, min = 1, ulp_msix;
8987 struct msix_entry *msix_ent;
8988
8989 total_vecs = bnxt_get_num_msix(bp);
8990 max = bnxt_get_max_func_irqs(bp);
8991 if (total_vecs > max)
8992 total_vecs = max;
8993
8994 if (!total_vecs)
8995 return 0;
8996
8997 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
8998 if (!msix_ent)
8999 return -ENOMEM;
9000
9001 for (i = 0; i < total_vecs; i++) {
9002 msix_ent[i].entry = i;
9003 msix_ent[i].vector = 0;
9004 }
9005
9006 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
9007 min = 2;
9008
9009 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
9010 ulp_msix = bnxt_get_ulp_msix_num(bp);
9011 if (total_vecs < 0 || total_vecs < ulp_msix) {
9012 rc = -ENODEV;
9013 goto msix_setup_exit;
9014 }
9015
9016 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
9017 if (bp->irq_tbl) {
9018 for (i = 0; i < total_vecs; i++)
9019 bp->irq_tbl[i].vector = msix_ent[i].vector;
9020
9021 bp->total_irqs = total_vecs;
9022 /* Trim rings based upon num of vectors allocated */
9023 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
9024 total_vecs - ulp_msix, min == 1);
9025 if (rc)
9026 goto msix_setup_exit;
9027
9028 bp->cp_nr_rings = (min == 1) ?
9029 max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
9030 bp->tx_nr_rings + bp->rx_nr_rings;
9031
9032 } else {
9033 rc = -ENOMEM;
9034 goto msix_setup_exit;
9035 }
9036 bp->flags |= BNXT_FLAG_USING_MSIX;
9037 kfree(msix_ent);
9038 return 0;
9039
9040 msix_setup_exit:
9041 netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc);
9042 kfree(bp->irq_tbl);
9043 bp->irq_tbl = NULL;
9044 pci_disable_msix(bp->pdev);
9045 kfree(msix_ent);
9046 return rc;
9047 }
9048
9049 static int bnxt_init_inta(struct bnxt *bp)
9050 {
9051 bp->irq_tbl = kzalloc(sizeof(struct bnxt_irq), GFP_KERNEL);
9052 if (!bp->irq_tbl)
9053 return -ENOMEM;
9054
9055 bp->total_irqs = 1;
9056 bp->rx_nr_rings = 1;
9057 bp->tx_nr_rings = 1;
9058 bp->cp_nr_rings = 1;
9059 bp->flags |= BNXT_FLAG_SHARED_RINGS;
9060 bp->irq_tbl[0].vector = bp->pdev->irq;
9061 return 0;
9062 }
9063
9064 static int bnxt_init_int_mode(struct bnxt *bp)
9065 {
9066 int rc = -ENODEV;
9067
9068 if (bp->flags & BNXT_FLAG_MSIX_CAP)
9069 rc = bnxt_init_msix(bp);
9070
9071 if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
9072 /* fallback to INTA */
9073 rc = bnxt_init_inta(bp);
9074 }
9075 return rc;
9076 }
9077
9078 static void bnxt_clear_int_mode(struct bnxt *bp)
9079 {
9080 if (bp->flags & BNXT_FLAG_USING_MSIX)
9081 pci_disable_msix(bp->pdev);
9082
9083 kfree(bp->irq_tbl);
9084 bp->irq_tbl = NULL;
9085 bp->flags &= ~BNXT_FLAG_USING_MSIX;
9086 }
9087
9088 int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init)
9089 {
9090 int tcs = netdev_get_num_tc(bp->dev);
9091 bool irq_cleared = false;
9092 int rc;
9093
9094 if (!bnxt_need_reserve_rings(bp))
9095 return 0;
9096
9097 if (irq_re_init && BNXT_NEW_RM(bp) &&
9098 bnxt_get_num_msix(bp) != bp->total_irqs) {
9099 bnxt_ulp_irq_stop(bp);
9100 bnxt_clear_int_mode(bp);
9101 irq_cleared = true;
9102 }
9103 rc = __bnxt_reserve_rings(bp);
9104 if (irq_cleared) {
9105 if (!rc)
9106 rc = bnxt_init_int_mode(bp);
9107 bnxt_ulp_irq_restart(bp, rc);
9108 }
9109 if (rc) {
9110 netdev_err(bp->dev, "ring reservation/IRQ init failure rc: %d\n", rc);
9111 return rc;
9112 }
9113 if (tcs && (bp->tx_nr_rings_per_tc * tcs != bp->tx_nr_rings)) {
9114 netdev_err(bp->dev, "tx ring reservation failure\n");
9115 netdev_reset_tc(bp->dev);
9116 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
9117 return -ENOMEM;
9118 }
9119 return 0;
9120 }
9121
9122 static void bnxt_free_irq(struct bnxt *bp)
9123 {
9124 struct bnxt_irq *irq;
9125 int i;
9126
9127 #ifdef CONFIG_RFS_ACCEL
9128 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
9129 bp->dev->rx_cpu_rmap = NULL;
9130 #endif
9131 if (!bp->irq_tbl || !bp->bnapi)
9132 return;
9133
9134 for (i = 0; i < bp->cp_nr_rings; i++) {
9135 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
9136
9137 irq = &bp->irq_tbl[map_idx];
9138 if (irq->requested) {
9139 if (irq->have_cpumask) {
9140 irq_set_affinity_hint(irq->vector, NULL);
9141 free_cpumask_var(irq->cpu_mask);
9142 irq->have_cpumask = 0;
9143 }
9144 free_irq(irq->vector, bp->bnapi[i]);
9145 }
9146
9147 irq->requested = 0;
9148 }
9149 }
9150
9151 static int bnxt_request_irq(struct bnxt *bp)
9152 {
9153 int i, j, rc = 0;
9154 unsigned long flags = 0;
9155 #ifdef CONFIG_RFS_ACCEL
9156 struct cpu_rmap *rmap;
9157 #endif
9158
9159 rc = bnxt_setup_int_mode(bp);
9160 if (rc) {
9161 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
9162 rc);
9163 return rc;
9164 }
9165 #ifdef CONFIG_RFS_ACCEL
9166 rmap = bp->dev->rx_cpu_rmap;
9167 #endif
9168 if (!(bp->flags & BNXT_FLAG_USING_MSIX))
9169 flags = IRQF_SHARED;
9170
9171 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
9172 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
9173 struct bnxt_irq *irq = &bp->irq_tbl[map_idx];
9174
9175 #ifdef CONFIG_RFS_ACCEL
9176 if (rmap && bp->bnapi[i]->rx_ring) {
9177 rc = irq_cpu_rmap_add(rmap, irq->vector);
9178 if (rc)
9179 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
9180 j);
9181 j++;
9182 }
9183 #endif
9184 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
9185 bp->bnapi[i]);
9186 if (rc)
9187 break;
9188
9189 irq->requested = 1;
9190
9191 if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) {
9192 int numa_node = dev_to_node(&bp->pdev->dev);
9193
9194 irq->have_cpumask = 1;
9195 cpumask_set_cpu(cpumask_local_spread(i, numa_node),
9196 irq->cpu_mask);
9197 rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask);
9198 if (rc) {
9199 netdev_warn(bp->dev,
9200 "Set affinity failed, IRQ = %d\n",
9201 irq->vector);
9202 break;
9203 }
9204 }
9205 }
9206 return rc;
9207 }
9208
9209 static void bnxt_del_napi(struct bnxt *bp)
9210 {
9211 int i;
9212
9213 if (!bp->bnapi)
9214 return;
9215
9216 for (i = 0; i < bp->cp_nr_rings; i++) {
9217 struct bnxt_napi *bnapi = bp->bnapi[i];
9218
9219 __netif_napi_del(&bnapi->napi);
9220 }
9221 /* We called __netif_napi_del(), we need
9222 * to respect an RCU grace period before freeing napi structures.
9223 */
9224 synchronize_net();
9225 }
9226
9227 static void bnxt_init_napi(struct bnxt *bp)
9228 {
9229 int i;
9230 unsigned int cp_nr_rings = bp->cp_nr_rings;
9231 struct bnxt_napi *bnapi;
9232
9233 if (bp->flags & BNXT_FLAG_USING_MSIX) {
9234 int (*poll_fn)(struct napi_struct *, int) = bnxt_poll;
9235
9236 if (bp->flags & BNXT_FLAG_CHIP_P5)
9237 poll_fn = bnxt_poll_p5;
9238 else if (BNXT_CHIP_TYPE_NITRO_A0(bp))
9239 cp_nr_rings--;
9240 for (i = 0; i < cp_nr_rings; i++) {
9241 bnapi = bp->bnapi[i];
9242 netif_napi_add(bp->dev, &bnapi->napi, poll_fn, 64);
9243 }
9244 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
9245 bnapi = bp->bnapi[cp_nr_rings];
9246 netif_napi_add(bp->dev, &bnapi->napi,
9247 bnxt_poll_nitroa0, 64);
9248 }
9249 } else {
9250 bnapi = bp->bnapi[0];
9251 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
9252 }
9253 }
9254
9255 static void bnxt_disable_napi(struct bnxt *bp)
9256 {
9257 int i;
9258
9259 if (!bp->bnapi ||
9260 test_and_set_bit(BNXT_STATE_NAPI_DISABLED, &bp->state))
9261 return;
9262
9263 for (i = 0; i < bp->cp_nr_rings; i++) {
9264 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
9265
9266 napi_disable(&bp->bnapi[i]->napi);
9267 if (bp->bnapi[i]->rx_ring)
9268 cancel_work_sync(&cpr->dim.work);
9269 }
9270 }
9271
9272 static void bnxt_enable_napi(struct bnxt *bp)
9273 {
9274 int i;
9275
9276 clear_bit(BNXT_STATE_NAPI_DISABLED, &bp->state);
9277 for (i = 0; i < bp->cp_nr_rings; i++) {
9278 struct bnxt_napi *bnapi = bp->bnapi[i];
9279 struct bnxt_cp_ring_info *cpr;
9280
9281 cpr = &bnapi->cp_ring;
9282 if (bnapi->in_reset)
9283 cpr->sw_stats.rx.rx_resets++;
9284 bnapi->in_reset = false;
9285
9286 if (bnapi->rx_ring) {
9287 INIT_WORK(&cpr->dim.work, bnxt_dim_work);
9288 cpr->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
9289 }
9290 napi_enable(&bnapi->napi);
9291 }
9292 }
9293
9294 void bnxt_tx_disable(struct bnxt *bp)
9295 {
9296 int i;
9297 struct bnxt_tx_ring_info *txr;
9298
9299 if (bp->tx_ring) {
9300 for (i = 0; i < bp->tx_nr_rings; i++) {
9301 txr = &bp->tx_ring[i];
9302 WRITE_ONCE(txr->dev_state, BNXT_DEV_STATE_CLOSING);
9303 }
9304 }
9305 /* Make sure napi polls see @dev_state change */
9306 synchronize_net();
9307 /* Drop carrier first to prevent TX timeout */
9308 netif_carrier_off(bp->dev);
9309 /* Stop all TX queues */
9310 netif_tx_disable(bp->dev);
9311 }
9312
9313 void bnxt_tx_enable(struct bnxt *bp)
9314 {
9315 int i;
9316 struct bnxt_tx_ring_info *txr;
9317
9318 for (i = 0; i < bp->tx_nr_rings; i++) {
9319 txr = &bp->tx_ring[i];
9320 WRITE_ONCE(txr->dev_state, 0);
9321 }
9322 /* Make sure napi polls see @dev_state change */
9323 synchronize_net();
9324 netif_tx_wake_all_queues(bp->dev);
9325 if (bp->link_info.link_up)
9326 netif_carrier_on(bp->dev);
9327 }
9328
9329 static char *bnxt_report_fec(struct bnxt_link_info *link_info)
9330 {
9331 u8 active_fec = link_info->active_fec_sig_mode &
9332 PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK;
9333
9334 switch (active_fec) {
9335 default:
9336 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE:
9337 return "None";
9338 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE:
9339 return "Clause 74 BaseR";
9340 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE:
9341 return "Clause 91 RS(528,514)";
9342 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE:
9343 return "Clause 91 RS544_1XN";
9344 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE:
9345 return "Clause 91 RS(544,514)";
9346 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE:
9347 return "Clause 91 RS272_1XN";
9348 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE:
9349 return "Clause 91 RS(272,257)";
9350 }
9351 }
9352
9353 static void bnxt_report_link(struct bnxt *bp)
9354 {
9355 if (bp->link_info.link_up) {
9356 const char *signal = "";
9357 const char *flow_ctrl;
9358 const char *duplex;
9359 u32 speed;
9360 u16 fec;
9361
9362 netif_carrier_on(bp->dev);
9363 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
9364 if (speed == SPEED_UNKNOWN) {
9365 netdev_info(bp->dev, "NIC Link is Up, speed unknown\n");
9366 return;
9367 }
9368 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
9369 duplex = "full";
9370 else
9371 duplex = "half";
9372 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
9373 flow_ctrl = "ON - receive & transmit";
9374 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
9375 flow_ctrl = "ON - transmit";
9376 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
9377 flow_ctrl = "ON - receive";
9378 else
9379 flow_ctrl = "none";
9380 if (bp->link_info.phy_qcfg_resp.option_flags &
9381 PORT_PHY_QCFG_RESP_OPTION_FLAGS_SIGNAL_MODE_KNOWN) {
9382 u8 sig_mode = bp->link_info.active_fec_sig_mode &
9383 PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK;
9384 switch (sig_mode) {
9385 case PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ:
9386 signal = "(NRZ) ";
9387 break;
9388 case PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4:
9389 signal = "(PAM4) ";
9390 break;
9391 default:
9392 break;
9393 }
9394 }
9395 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s%s duplex, Flow control: %s\n",
9396 speed, signal, duplex, flow_ctrl);
9397 if (bp->phy_flags & BNXT_PHY_FL_EEE_CAP)
9398 netdev_info(bp->dev, "EEE is %s\n",
9399 bp->eee.eee_active ? "active" :
9400 "not active");
9401 fec = bp->link_info.fec_cfg;
9402 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED))
9403 netdev_info(bp->dev, "FEC autoneg %s encoding: %s\n",
9404 (fec & BNXT_FEC_AUTONEG) ? "on" : "off",
9405 bnxt_report_fec(&bp->link_info));
9406 } else {
9407 netif_carrier_off(bp->dev);
9408 netdev_err(bp->dev, "NIC Link is Down\n");
9409 }
9410 }
9411
9412 static bool bnxt_phy_qcaps_no_speed(struct hwrm_port_phy_qcaps_output *resp)
9413 {
9414 if (!resp->supported_speeds_auto_mode &&
9415 !resp->supported_speeds_force_mode &&
9416 !resp->supported_pam4_speeds_auto_mode &&
9417 !resp->supported_pam4_speeds_force_mode)
9418 return true;
9419 return false;
9420 }
9421
9422 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
9423 {
9424 int rc = 0;
9425 struct hwrm_port_phy_qcaps_input req = {0};
9426 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
9427 struct bnxt_link_info *link_info = &bp->link_info;
9428
9429 if (bp->hwrm_spec_code < 0x10201)
9430 return 0;
9431
9432 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
9433
9434 mutex_lock(&bp->hwrm_cmd_lock);
9435 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9436 if (rc)
9437 goto hwrm_phy_qcaps_exit;
9438
9439 bp->phy_flags = resp->flags;
9440 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) {
9441 struct ethtool_eee *eee = &bp->eee;
9442 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
9443
9444 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
9445 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
9446 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
9447 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
9448 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
9449 }
9450
9451 if (bp->hwrm_spec_code >= 0x10a01) {
9452 if (bnxt_phy_qcaps_no_speed(resp)) {
9453 link_info->phy_state = BNXT_PHY_STATE_DISABLED;
9454 netdev_warn(bp->dev, "Ethernet link disabled\n");
9455 } else if (link_info->phy_state == BNXT_PHY_STATE_DISABLED) {
9456 link_info->phy_state = BNXT_PHY_STATE_ENABLED;
9457 netdev_info(bp->dev, "Ethernet link enabled\n");
9458 /* Phy re-enabled, reprobe the speeds */
9459 link_info->support_auto_speeds = 0;
9460 link_info->support_pam4_auto_speeds = 0;
9461 }
9462 }
9463 if (resp->supported_speeds_auto_mode)
9464 link_info->support_auto_speeds =
9465 le16_to_cpu(resp->supported_speeds_auto_mode);
9466 if (resp->supported_pam4_speeds_auto_mode)
9467 link_info->support_pam4_auto_speeds =
9468 le16_to_cpu(resp->supported_pam4_speeds_auto_mode);
9469
9470 bp->port_count = resp->port_cnt;
9471
9472 hwrm_phy_qcaps_exit:
9473 mutex_unlock(&bp->hwrm_cmd_lock);
9474 return rc;
9475 }
9476
9477 static bool bnxt_support_dropped(u16 advertising, u16 supported)
9478 {
9479 u16 diff = advertising ^ supported;
9480
9481 return ((supported | diff) != supported);
9482 }
9483
9484 int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
9485 {
9486 int rc = 0;
9487 struct bnxt_link_info *link_info = &bp->link_info;
9488 struct hwrm_port_phy_qcfg_input req = {0};
9489 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
9490 u8 link_up = link_info->link_up;
9491 bool support_changed = false;
9492
9493 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
9494
9495 mutex_lock(&bp->hwrm_cmd_lock);
9496 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9497 if (rc) {
9498 mutex_unlock(&bp->hwrm_cmd_lock);
9499 return rc;
9500 }
9501
9502 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
9503 link_info->phy_link_status = resp->link;
9504 link_info->duplex = resp->duplex_cfg;
9505 if (bp->hwrm_spec_code >= 0x10800)
9506 link_info->duplex = resp->duplex_state;
9507 link_info->pause = resp->pause;
9508 link_info->auto_mode = resp->auto_mode;
9509 link_info->auto_pause_setting = resp->auto_pause;
9510 link_info->lp_pause = resp->link_partner_adv_pause;
9511 link_info->force_pause_setting = resp->force_pause;
9512 link_info->duplex_setting = resp->duplex_cfg;
9513 if (link_info->phy_link_status == BNXT_LINK_LINK)
9514 link_info->link_speed = le16_to_cpu(resp->link_speed);
9515 else
9516 link_info->link_speed = 0;
9517 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
9518 link_info->force_pam4_link_speed =
9519 le16_to_cpu(resp->force_pam4_link_speed);
9520 link_info->support_speeds = le16_to_cpu(resp->support_speeds);
9521 link_info->support_pam4_speeds = le16_to_cpu(resp->support_pam4_speeds);
9522 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
9523 link_info->auto_pam4_link_speeds =
9524 le16_to_cpu(resp->auto_pam4_link_speed_mask);
9525 link_info->lp_auto_link_speeds =
9526 le16_to_cpu(resp->link_partner_adv_speeds);
9527 link_info->lp_auto_pam4_link_speeds =
9528 resp->link_partner_pam4_adv_speeds;
9529 link_info->preemphasis = le32_to_cpu(resp->preemphasis);
9530 link_info->phy_ver[0] = resp->phy_maj;
9531 link_info->phy_ver[1] = resp->phy_min;
9532 link_info->phy_ver[2] = resp->phy_bld;
9533 link_info->media_type = resp->media_type;
9534 link_info->phy_type = resp->phy_type;
9535 link_info->transceiver = resp->xcvr_pkg_type;
9536 link_info->phy_addr = resp->eee_config_phy_addr &
9537 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
9538 link_info->module_status = resp->module_status;
9539
9540 if (bp->phy_flags & BNXT_PHY_FL_EEE_CAP) {
9541 struct ethtool_eee *eee = &bp->eee;
9542 u16 fw_speeds;
9543
9544 eee->eee_active = 0;
9545 if (resp->eee_config_phy_addr &
9546 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
9547 eee->eee_active = 1;
9548 fw_speeds = le16_to_cpu(
9549 resp->link_partner_adv_eee_link_speed_mask);
9550 eee->lp_advertised =
9551 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
9552 }
9553
9554 /* Pull initial EEE config */
9555 if (!chng_link_state) {
9556 if (resp->eee_config_phy_addr &
9557 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
9558 eee->eee_enabled = 1;
9559
9560 fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
9561 eee->advertised =
9562 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
9563
9564 if (resp->eee_config_phy_addr &
9565 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
9566 __le32 tmr;
9567
9568 eee->tx_lpi_enabled = 1;
9569 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
9570 eee->tx_lpi_timer = le32_to_cpu(tmr) &
9571 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
9572 }
9573 }
9574 }
9575
9576 link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED;
9577 if (bp->hwrm_spec_code >= 0x10504) {
9578 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg);
9579 link_info->active_fec_sig_mode = resp->active_fec_signal_mode;
9580 }
9581 /* TODO: need to add more logic to report VF link */
9582 if (chng_link_state) {
9583 if (link_info->phy_link_status == BNXT_LINK_LINK)
9584 link_info->link_up = 1;
9585 else
9586 link_info->link_up = 0;
9587 if (link_up != link_info->link_up)
9588 bnxt_report_link(bp);
9589 } else {
9590 /* alwasy link down if not require to update link state */
9591 link_info->link_up = 0;
9592 }
9593 mutex_unlock(&bp->hwrm_cmd_lock);
9594
9595 if (!BNXT_PHY_CFG_ABLE(bp))
9596 return 0;
9597
9598 /* Check if any advertised speeds are no longer supported. The caller
9599 * holds the link_lock mutex, so we can modify link_info settings.
9600 */
9601 if (bnxt_support_dropped(link_info->advertising,
9602 link_info->support_auto_speeds)) {
9603 link_info->advertising = link_info->support_auto_speeds;
9604 support_changed = true;
9605 }
9606 if (bnxt_support_dropped(link_info->advertising_pam4,
9607 link_info->support_pam4_auto_speeds)) {
9608 link_info->advertising_pam4 = link_info->support_pam4_auto_speeds;
9609 support_changed = true;
9610 }
9611 if (support_changed && (link_info->autoneg & BNXT_AUTONEG_SPEED))
9612 bnxt_hwrm_set_link_setting(bp, true, false);
9613 return 0;
9614 }
9615
9616 static void bnxt_get_port_module_status(struct bnxt *bp)
9617 {
9618 struct bnxt_link_info *link_info = &bp->link_info;
9619 struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
9620 u8 module_status;
9621
9622 if (bnxt_update_link(bp, true))
9623 return;
9624
9625 module_status = link_info->module_status;
9626 switch (module_status) {
9627 case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX:
9628 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
9629 case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG:
9630 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
9631 bp->pf.port_id);
9632 if (bp->hwrm_spec_code >= 0x10201) {
9633 netdev_warn(bp->dev, "Module part number %s\n",
9634 resp->phy_vendor_partnumber);
9635 }
9636 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX)
9637 netdev_warn(bp->dev, "TX is disabled\n");
9638 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN)
9639 netdev_warn(bp->dev, "SFP+ module is shutdown\n");
9640 }
9641 }
9642
9643 static void
9644 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
9645 {
9646 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
9647 if (bp->hwrm_spec_code >= 0x10201)
9648 req->auto_pause =
9649 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
9650 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
9651 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
9652 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
9653 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
9654 req->enables |=
9655 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
9656 } else {
9657 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
9658 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
9659 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
9660 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
9661 req->enables |=
9662 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
9663 if (bp->hwrm_spec_code >= 0x10201) {
9664 req->auto_pause = req->force_pause;
9665 req->enables |= cpu_to_le32(
9666 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
9667 }
9668 }
9669 }
9670
9671 static void bnxt_hwrm_set_link_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
9672 {
9673 if (bp->link_info.autoneg & BNXT_AUTONEG_SPEED) {
9674 req->auto_mode |= PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
9675 if (bp->link_info.advertising) {
9676 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
9677 req->auto_link_speed_mask = cpu_to_le16(bp->link_info.advertising);
9678 }
9679 if (bp->link_info.advertising_pam4) {
9680 req->enables |=
9681 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAM4_LINK_SPEED_MASK);
9682 req->auto_link_pam4_speed_mask =
9683 cpu_to_le16(bp->link_info.advertising_pam4);
9684 }
9685 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
9686 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
9687 } else {
9688 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
9689 if (bp->link_info.req_signal_mode == BNXT_SIG_MODE_PAM4) {
9690 req->force_pam4_link_speed = cpu_to_le16(bp->link_info.req_link_speed);
9691 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED);
9692 } else {
9693 req->force_link_speed = cpu_to_le16(bp->link_info.req_link_speed);
9694 }
9695 }
9696
9697 /* tell chimp that the setting takes effect immediately */
9698 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
9699 }
9700
9701 int bnxt_hwrm_set_pause(struct bnxt *bp)
9702 {
9703 struct hwrm_port_phy_cfg_input req = {0};
9704 int rc;
9705
9706 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
9707 bnxt_hwrm_set_pause_common(bp, &req);
9708
9709 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
9710 bp->link_info.force_link_chng)
9711 bnxt_hwrm_set_link_common(bp, &req);
9712
9713 mutex_lock(&bp->hwrm_cmd_lock);
9714 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9715 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
9716 /* since changing of pause setting doesn't trigger any link
9717 * change event, the driver needs to update the current pause
9718 * result upon successfully return of the phy_cfg command
9719 */
9720 bp->link_info.pause =
9721 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
9722 bp->link_info.auto_pause_setting = 0;
9723 if (!bp->link_info.force_link_chng)
9724 bnxt_report_link(bp);
9725 }
9726 bp->link_info.force_link_chng = false;
9727 mutex_unlock(&bp->hwrm_cmd_lock);
9728 return rc;
9729 }
9730
9731 static void bnxt_hwrm_set_eee(struct bnxt *bp,
9732 struct hwrm_port_phy_cfg_input *req)
9733 {
9734 struct ethtool_eee *eee = &bp->eee;
9735
9736 if (eee->eee_enabled) {
9737 u16 eee_speeds;
9738 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
9739
9740 if (eee->tx_lpi_enabled)
9741 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
9742 else
9743 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
9744
9745 req->flags |= cpu_to_le32(flags);
9746 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
9747 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
9748 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
9749 } else {
9750 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
9751 }
9752 }
9753
9754 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
9755 {
9756 struct hwrm_port_phy_cfg_input req = {0};
9757
9758 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
9759 if (set_pause)
9760 bnxt_hwrm_set_pause_common(bp, &req);
9761
9762 bnxt_hwrm_set_link_common(bp, &req);
9763
9764 if (set_eee)
9765 bnxt_hwrm_set_eee(bp, &req);
9766 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9767 }
9768
9769 static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
9770 {
9771 struct hwrm_port_phy_cfg_input req = {0};
9772
9773 if (!BNXT_SINGLE_PF(bp))
9774 return 0;
9775
9776 if (pci_num_vf(bp->pdev) &&
9777 !(bp->phy_flags & BNXT_PHY_FL_FW_MANAGED_LKDN))
9778 return 0;
9779
9780 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
9781 req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN);
9782 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9783 }
9784
9785 static int bnxt_fw_init_one(struct bnxt *bp);
9786
9787 static int bnxt_fw_reset_via_optee(struct bnxt *bp)
9788 {
9789 #ifdef CONFIG_TEE_BNXT_FW
9790 int rc = tee_bnxt_fw_load();
9791
9792 if (rc)
9793 netdev_err(bp->dev, "Failed FW reset via OP-TEE, rc=%d\n", rc);
9794
9795 return rc;
9796 #else
9797 netdev_err(bp->dev, "OP-TEE not supported\n");
9798 return -ENODEV;
9799 #endif
9800 }
9801
9802 static int bnxt_try_recover_fw(struct bnxt *bp)
9803 {
9804 if (bp->fw_health && bp->fw_health->status_reliable) {
9805 int retry = 0, rc;
9806 u32 sts;
9807
9808 mutex_lock(&bp->hwrm_cmd_lock);
9809 do {
9810 sts = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG);
9811 rc = __bnxt_hwrm_ver_get(bp, true);
9812 if (!BNXT_FW_IS_BOOTING(sts) &&
9813 !BNXT_FW_IS_RECOVERING(sts))
9814 break;
9815 retry++;
9816 } while (rc == -EBUSY && retry < BNXT_FW_RETRY);
9817 mutex_unlock(&bp->hwrm_cmd_lock);
9818
9819 if (!BNXT_FW_IS_HEALTHY(sts)) {
9820 netdev_err(bp->dev,
9821 "Firmware not responding, status: 0x%x\n",
9822 sts);
9823 rc = -ENODEV;
9824 }
9825 if (sts & FW_STATUS_REG_CRASHED_NO_MASTER) {
9826 netdev_warn(bp->dev, "Firmware recover via OP-TEE requested\n");
9827 return bnxt_fw_reset_via_optee(bp);
9828 }
9829 return rc;
9830 }
9831
9832 return -ENODEV;
9833 }
9834
9835 static int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
9836 {
9837 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
9838 struct hwrm_func_drv_if_change_input req = {0};
9839 bool fw_reset = !bp->irq_tbl;
9840 bool resc_reinit = false;
9841 int rc, retry = 0;
9842 u32 flags = 0;
9843
9844 if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
9845 return 0;
9846
9847 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_IF_CHANGE, -1, -1);
9848 if (up)
9849 req.flags = cpu_to_le32(FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP);
9850 mutex_lock(&bp->hwrm_cmd_lock);
9851 while (retry < BNXT_FW_IF_RETRY) {
9852 rc = _hwrm_send_message(bp, &req, sizeof(req),
9853 HWRM_CMD_TIMEOUT);
9854 if (rc != -EAGAIN)
9855 break;
9856
9857 msleep(50);
9858 retry++;
9859 }
9860 if (!rc)
9861 flags = le32_to_cpu(resp->flags);
9862 mutex_unlock(&bp->hwrm_cmd_lock);
9863
9864 if (rc == -EAGAIN)
9865 return rc;
9866 if (rc && up) {
9867 rc = bnxt_try_recover_fw(bp);
9868 fw_reset = true;
9869 }
9870 if (rc)
9871 return rc;
9872
9873 if (!up) {
9874 bnxt_inv_fw_health_reg(bp);
9875 return 0;
9876 }
9877
9878 if (flags & FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE)
9879 resc_reinit = true;
9880 if (flags & FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE)
9881 fw_reset = true;
9882 else if (bp->fw_health && !bp->fw_health->status_reliable)
9883 bnxt_try_map_fw_health_reg(bp);
9884
9885 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state) && !fw_reset) {
9886 netdev_err(bp->dev, "RESET_DONE not set during FW reset.\n");
9887 set_bit(BNXT_STATE_ABORT_ERR, &bp->state);
9888 return -ENODEV;
9889 }
9890 if (resc_reinit || fw_reset) {
9891 if (fw_reset) {
9892 set_bit(BNXT_STATE_FW_RESET_DET, &bp->state);
9893 if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
9894 bnxt_ulp_stop(bp);
9895 bnxt_free_ctx_mem(bp);
9896 kfree(bp->ctx);
9897 bp->ctx = NULL;
9898 bnxt_dcb_free(bp);
9899 rc = bnxt_fw_init_one(bp);
9900 if (rc) {
9901 clear_bit(BNXT_STATE_FW_RESET_DET, &bp->state);
9902 set_bit(BNXT_STATE_ABORT_ERR, &bp->state);
9903 return rc;
9904 }
9905 bnxt_clear_int_mode(bp);
9906 rc = bnxt_init_int_mode(bp);
9907 if (rc) {
9908 clear_bit(BNXT_STATE_FW_RESET_DET, &bp->state);
9909 netdev_err(bp->dev, "init int mode failed\n");
9910 return rc;
9911 }
9912 }
9913 if (BNXT_NEW_RM(bp)) {
9914 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
9915
9916 rc = bnxt_hwrm_func_resc_qcaps(bp, true);
9917 if (rc)
9918 netdev_err(bp->dev, "resc_qcaps failed\n");
9919
9920 hw_resc->resv_cp_rings = 0;
9921 hw_resc->resv_stat_ctxs = 0;
9922 hw_resc->resv_irqs = 0;
9923 hw_resc->resv_tx_rings = 0;
9924 hw_resc->resv_rx_rings = 0;
9925 hw_resc->resv_hw_ring_grps = 0;
9926 hw_resc->resv_vnics = 0;
9927 if (!fw_reset) {
9928 bp->tx_nr_rings = 0;
9929 bp->rx_nr_rings = 0;
9930 }
9931 }
9932 }
9933 return rc;
9934 }
9935
9936 static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
9937 {
9938 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
9939 struct hwrm_port_led_qcaps_input req = {0};
9940 struct bnxt_pf_info *pf = &bp->pf;
9941 int rc;
9942
9943 bp->num_leds = 0;
9944 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601)
9945 return 0;
9946
9947 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1);
9948 req.port_id = cpu_to_le16(pf->port_id);
9949 mutex_lock(&bp->hwrm_cmd_lock);
9950 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9951 if (rc) {
9952 mutex_unlock(&bp->hwrm_cmd_lock);
9953 return rc;
9954 }
9955 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
9956 int i;
9957
9958 bp->num_leds = resp->num_leds;
9959 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) *
9960 bp->num_leds);
9961 for (i = 0; i < bp->num_leds; i++) {
9962 struct bnxt_led_info *led = &bp->leds[i];
9963 __le16 caps = led->led_state_caps;
9964
9965 if (!led->led_group_id ||
9966 !BNXT_LED_ALT_BLINK_CAP(caps)) {
9967 bp->num_leds = 0;
9968 break;
9969 }
9970 }
9971 }
9972 mutex_unlock(&bp->hwrm_cmd_lock);
9973 return 0;
9974 }
9975
9976 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp)
9977 {
9978 struct hwrm_wol_filter_alloc_input req = {0};
9979 struct hwrm_wol_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
9980 int rc;
9981
9982 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_ALLOC, -1, -1);
9983 req.port_id = cpu_to_le16(bp->pf.port_id);
9984 req.wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT;
9985 req.enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS);
9986 memcpy(req.mac_address, bp->dev->dev_addr, ETH_ALEN);
9987 mutex_lock(&bp->hwrm_cmd_lock);
9988 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9989 if (!rc)
9990 bp->wol_filter_id = resp->wol_filter_id;
9991 mutex_unlock(&bp->hwrm_cmd_lock);
9992 return rc;
9993 }
9994
9995 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp)
9996 {
9997 struct hwrm_wol_filter_free_input req = {0};
9998
9999 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1);
10000 req.port_id = cpu_to_le16(bp->pf.port_id);
10001 req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID);
10002 req.wol_filter_id = bp->wol_filter_id;
10003 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
10004 }
10005
10006 static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle)
10007 {
10008 struct hwrm_wol_filter_qcfg_input req = {0};
10009 struct hwrm_wol_filter_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
10010 u16 next_handle = 0;
10011 int rc;
10012
10013 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_QCFG, -1, -1);
10014 req.port_id = cpu_to_le16(bp->pf.port_id);
10015 req.handle = cpu_to_le16(handle);
10016 mutex_lock(&bp->hwrm_cmd_lock);
10017 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
10018 if (!rc) {
10019 next_handle = le16_to_cpu(resp->next_handle);
10020 if (next_handle != 0) {
10021 if (resp->wol_type ==
10022 WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) {
10023 bp->wol = 1;
10024 bp->wol_filter_id = resp->wol_filter_id;
10025 }
10026 }
10027 }
10028 mutex_unlock(&bp->hwrm_cmd_lock);
10029 return next_handle;
10030 }
10031
10032 static void bnxt_get_wol_settings(struct bnxt *bp)
10033 {
10034 u16 handle = 0;
10035
10036 bp->wol = 0;
10037 if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP))
10038 return;
10039
10040 do {
10041 handle = bnxt_hwrm_get_wol_fltrs(bp, handle);
10042 } while (handle && handle != 0xffff);
10043 }
10044
10045 #ifdef CONFIG_BNXT_HWMON
10046 static ssize_t bnxt_show_temp(struct device *dev,
10047 struct device_attribute *devattr, char *buf)
10048 {
10049 struct hwrm_temp_monitor_query_input req = {0};
10050 struct hwrm_temp_monitor_query_output *resp;
10051 struct bnxt *bp = dev_get_drvdata(dev);
10052 u32 len = 0;
10053 int rc;
10054
10055 resp = bp->hwrm_cmd_resp_addr;
10056 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TEMP_MONITOR_QUERY, -1, -1);
10057 mutex_lock(&bp->hwrm_cmd_lock);
10058 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
10059 if (!rc)
10060 len = sprintf(buf, "%u\n", resp->temp * 1000); /* display millidegree */
10061 mutex_unlock(&bp->hwrm_cmd_lock);
10062 if (rc)
10063 return rc;
10064 return len;
10065 }
10066 static SENSOR_DEVICE_ATTR(temp1_input, 0444, bnxt_show_temp, NULL, 0);
10067
10068 static struct attribute *bnxt_attrs[] = {
10069 &sensor_dev_attr_temp1_input.dev_attr.attr,
10070 NULL
10071 };
10072 ATTRIBUTE_GROUPS(bnxt);
10073
10074 static void bnxt_hwmon_close(struct bnxt *bp)
10075 {
10076 if (bp->hwmon_dev) {
10077 hwmon_device_unregister(bp->hwmon_dev);
10078 bp->hwmon_dev = NULL;
10079 }
10080 }
10081
10082 static void bnxt_hwmon_open(struct bnxt *bp)
10083 {
10084 struct hwrm_temp_monitor_query_input req = {0};
10085 struct pci_dev *pdev = bp->pdev;
10086 int rc;
10087
10088 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TEMP_MONITOR_QUERY, -1, -1);
10089 rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
10090 if (rc == -EACCES || rc == -EOPNOTSUPP) {
10091 bnxt_hwmon_close(bp);
10092 return;
10093 }
10094
10095 if (bp->hwmon_dev)
10096 return;
10097
10098 bp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev,
10099 DRV_MODULE_NAME, bp,
10100 bnxt_groups);
10101 if (IS_ERR(bp->hwmon_dev)) {
10102 bp->hwmon_dev = NULL;
10103 dev_warn(&pdev->dev, "Cannot register hwmon device\n");
10104 }
10105 }
10106 #else
10107 static void bnxt_hwmon_close(struct bnxt *bp)
10108 {
10109 }
10110
10111 static void bnxt_hwmon_open(struct bnxt *bp)
10112 {
10113 }
10114 #endif
10115
10116 static bool bnxt_eee_config_ok(struct bnxt *bp)
10117 {
10118 struct ethtool_eee *eee = &bp->eee;
10119 struct bnxt_link_info *link_info = &bp->link_info;
10120
10121 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP))
10122 return true;
10123
10124 if (eee->eee_enabled) {
10125 u32 advertising =
10126 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
10127
10128 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
10129 eee->eee_enabled = 0;
10130 return false;
10131 }
10132 if (eee->advertised & ~advertising) {
10133 eee->advertised = advertising & eee->supported;
10134 return false;
10135 }
10136 }
10137 return true;
10138 }
10139
10140 static int bnxt_update_phy_setting(struct bnxt *bp)
10141 {
10142 int rc;
10143 bool update_link = false;
10144 bool update_pause = false;
10145 bool update_eee = false;
10146 struct bnxt_link_info *link_info = &bp->link_info;
10147
10148 rc = bnxt_update_link(bp, true);
10149 if (rc) {
10150 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
10151 rc);
10152 return rc;
10153 }
10154 if (!BNXT_SINGLE_PF(bp))
10155 return 0;
10156
10157 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
10158 (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
10159 link_info->req_flow_ctrl)
10160 update_pause = true;
10161 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
10162 link_info->force_pause_setting != link_info->req_flow_ctrl)
10163 update_pause = true;
10164 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
10165 if (BNXT_AUTO_MODE(link_info->auto_mode))
10166 update_link = true;
10167 if (link_info->req_signal_mode == BNXT_SIG_MODE_NRZ &&
10168 link_info->req_link_speed != link_info->force_link_speed)
10169 update_link = true;
10170 else if (link_info->req_signal_mode == BNXT_SIG_MODE_PAM4 &&
10171 link_info->req_link_speed != link_info->force_pam4_link_speed)
10172 update_link = true;
10173 if (link_info->req_duplex != link_info->duplex_setting)
10174 update_link = true;
10175 } else {
10176 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
10177 update_link = true;
10178 if (link_info->advertising != link_info->auto_link_speeds ||
10179 link_info->advertising_pam4 != link_info->auto_pam4_link_speeds)
10180 update_link = true;
10181 }
10182
10183 /* The last close may have shutdown the link, so need to call
10184 * PHY_CFG to bring it back up.
10185 */
10186 if (!bp->link_info.link_up)
10187 update_link = true;
10188
10189 if (!bnxt_eee_config_ok(bp))
10190 update_eee = true;
10191
10192 if (update_link)
10193 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
10194 else if (update_pause)
10195 rc = bnxt_hwrm_set_pause(bp);
10196 if (rc) {
10197 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
10198 rc);
10199 return rc;
10200 }
10201
10202 return rc;
10203 }
10204
10205 /* Common routine to pre-map certain register block to different GRC window.
10206 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
10207 * in PF and 3 windows in VF that can be customized to map in different
10208 * register blocks.
10209 */
10210 static void bnxt_preset_reg_win(struct bnxt *bp)
10211 {
10212 if (BNXT_PF(bp)) {
10213 /* CAG registers map to GRC window #4 */
10214 writel(BNXT_CAG_REG_BASE,
10215 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
10216 }
10217 }
10218
10219 static int bnxt_init_dflt_ring_mode(struct bnxt *bp);
10220
10221 static int bnxt_reinit_after_abort(struct bnxt *bp)
10222 {
10223 int rc;
10224
10225 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
10226 return -EBUSY;
10227
10228 if (bp->dev->reg_state == NETREG_UNREGISTERED)
10229 return -ENODEV;
10230
10231 rc = bnxt_fw_init_one(bp);
10232 if (!rc) {
10233 bnxt_clear_int_mode(bp);
10234 rc = bnxt_init_int_mode(bp);
10235 if (!rc) {
10236 clear_bit(BNXT_STATE_ABORT_ERR, &bp->state);
10237 set_bit(BNXT_STATE_FW_RESET_DET, &bp->state);
10238 }
10239 }
10240 return rc;
10241 }
10242
10243 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
10244 {
10245 int rc = 0;
10246
10247 bnxt_preset_reg_win(bp);
10248 netif_carrier_off(bp->dev);
10249 if (irq_re_init) {
10250 /* Reserve rings now if none were reserved at driver probe. */
10251 rc = bnxt_init_dflt_ring_mode(bp);
10252 if (rc) {
10253 netdev_err(bp->dev, "Failed to reserve default rings at open\n");
10254 return rc;
10255 }
10256 }
10257 rc = bnxt_reserve_rings(bp, irq_re_init);
10258 if (rc)
10259 return rc;
10260 if ((bp->flags & BNXT_FLAG_RFS) &&
10261 !(bp->flags & BNXT_FLAG_USING_MSIX)) {
10262 /* disable RFS if falling back to INTA */
10263 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
10264 bp->flags &= ~BNXT_FLAG_RFS;
10265 }
10266
10267 rc = bnxt_alloc_mem(bp, irq_re_init);
10268 if (rc) {
10269 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
10270 goto open_err_free_mem;
10271 }
10272
10273 if (irq_re_init) {
10274 bnxt_init_napi(bp);
10275 rc = bnxt_request_irq(bp);
10276 if (rc) {
10277 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
10278 goto open_err_irq;
10279 }
10280 }
10281
10282 rc = bnxt_init_nic(bp, irq_re_init);
10283 if (rc) {
10284 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
10285 goto open_err_irq;
10286 }
10287
10288 bnxt_enable_napi(bp);
10289 bnxt_debug_dev_init(bp);
10290
10291 if (link_re_init) {
10292 mutex_lock(&bp->link_lock);
10293 rc = bnxt_update_phy_setting(bp);
10294 mutex_unlock(&bp->link_lock);
10295 if (rc) {
10296 netdev_warn(bp->dev, "failed to update phy settings\n");
10297 if (BNXT_SINGLE_PF(bp)) {
10298 bp->link_info.phy_retry = true;
10299 bp->link_info.phy_retry_expires =
10300 jiffies + 5 * HZ;
10301 }
10302 }
10303 }
10304
10305 if (irq_re_init)
10306 udp_tunnel_nic_reset_ntf(bp->dev);
10307
10308 set_bit(BNXT_STATE_OPEN, &bp->state);
10309 bnxt_enable_int(bp);
10310 /* Enable TX queues */
10311 bnxt_tx_enable(bp);
10312 mod_timer(&bp->timer, jiffies + bp->current_interval);
10313 /* Poll link status and check for SFP+ module status */
10314 bnxt_get_port_module_status(bp);
10315
10316 /* VF-reps may need to be re-opened after the PF is re-opened */
10317 if (BNXT_PF(bp))
10318 bnxt_vf_reps_open(bp);
10319 return 0;
10320
10321 open_err_irq:
10322 bnxt_del_napi(bp);
10323
10324 open_err_free_mem:
10325 bnxt_free_skbs(bp);
10326 bnxt_free_irq(bp);
10327 bnxt_free_mem(bp, true);
10328 return rc;
10329 }
10330
10331 /* rtnl_lock held */
10332 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
10333 {
10334 int rc = 0;
10335
10336 if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state))
10337 rc = -EIO;
10338 if (!rc)
10339 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
10340 if (rc) {
10341 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
10342 dev_close(bp->dev);
10343 }
10344 return rc;
10345 }
10346
10347 /* rtnl_lock held, open the NIC half way by allocating all resources, but
10348 * NAPI, IRQ, and TX are not enabled. This is mainly used for offline
10349 * self tests.
10350 */
10351 int bnxt_half_open_nic(struct bnxt *bp)
10352 {
10353 int rc = 0;
10354
10355 if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state)) {
10356 netdev_err(bp->dev, "A previous firmware reset has not completed, aborting half open\n");
10357 rc = -ENODEV;
10358 goto half_open_err;
10359 }
10360
10361 rc = bnxt_alloc_mem(bp, false);
10362 if (rc) {
10363 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
10364 goto half_open_err;
10365 }
10366 rc = bnxt_init_nic(bp, false);
10367 if (rc) {
10368 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
10369 goto half_open_err;
10370 }
10371 return 0;
10372
10373 half_open_err:
10374 bnxt_free_skbs(bp);
10375 bnxt_free_mem(bp, false);
10376 dev_close(bp->dev);
10377 return rc;
10378 }
10379
10380 /* rtnl_lock held, this call can only be made after a previous successful
10381 * call to bnxt_half_open_nic().
10382 */
10383 void bnxt_half_close_nic(struct bnxt *bp)
10384 {
10385 bnxt_hwrm_resource_free(bp, false, false);
10386 bnxt_free_skbs(bp);
10387 bnxt_free_mem(bp, false);
10388 }
10389
10390 static void bnxt_reenable_sriov(struct bnxt *bp)
10391 {
10392 if (BNXT_PF(bp)) {
10393 struct bnxt_pf_info *pf = &bp->pf;
10394 int n = pf->active_vfs;
10395
10396 if (n)
10397 bnxt_cfg_hw_sriov(bp, &n, true);
10398 }
10399 }
10400
10401 static int bnxt_open(struct net_device *dev)
10402 {
10403 struct bnxt *bp = netdev_priv(dev);
10404 int rc;
10405
10406 if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state)) {
10407 rc = bnxt_reinit_after_abort(bp);
10408 if (rc) {
10409 if (rc == -EBUSY)
10410 netdev_err(bp->dev, "A previous firmware reset has not completed, aborting\n");
10411 else
10412 netdev_err(bp->dev, "Failed to reinitialize after aborted firmware reset\n");
10413 return -ENODEV;
10414 }
10415 }
10416
10417 rc = bnxt_hwrm_if_change(bp, true);
10418 if (rc)
10419 return rc;
10420
10421 rc = __bnxt_open_nic(bp, true, true);
10422 if (rc) {
10423 bnxt_hwrm_if_change(bp, false);
10424 } else {
10425 if (test_and_clear_bit(BNXT_STATE_FW_RESET_DET, &bp->state)) {
10426 if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) {
10427 bnxt_ulp_start(bp, 0);
10428 bnxt_reenable_sriov(bp);
10429 }
10430 }
10431 bnxt_hwmon_open(bp);
10432 }
10433
10434 return rc;
10435 }
10436
10437 static bool bnxt_drv_busy(struct bnxt *bp)
10438 {
10439 return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) ||
10440 test_bit(BNXT_STATE_READ_STATS, &bp->state));
10441 }
10442
10443 static void bnxt_get_ring_stats(struct bnxt *bp,
10444 struct rtnl_link_stats64 *stats);
10445
10446 static void __bnxt_close_nic(struct bnxt *bp, bool irq_re_init,
10447 bool link_re_init)
10448 {
10449 /* Close the VF-reps before closing PF */
10450 if (BNXT_PF(bp))
10451 bnxt_vf_reps_close(bp);
10452
10453 /* Change device state to avoid TX queue wake up's */
10454 bnxt_tx_disable(bp);
10455
10456 clear_bit(BNXT_STATE_OPEN, &bp->state);
10457 smp_mb__after_atomic();
10458 while (bnxt_drv_busy(bp))
10459 msleep(20);
10460
10461 /* Flush rings and and disable interrupts */
10462 bnxt_shutdown_nic(bp, irq_re_init);
10463
10464 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
10465
10466 bnxt_debug_dev_exit(bp);
10467 bnxt_disable_napi(bp);
10468 del_timer_sync(&bp->timer);
10469 bnxt_free_skbs(bp);
10470
10471 /* Save ring stats before shutdown */
10472 if (bp->bnapi && irq_re_init)
10473 bnxt_get_ring_stats(bp, &bp->net_stats_prev);
10474 if (irq_re_init) {
10475 bnxt_free_irq(bp);
10476 bnxt_del_napi(bp);
10477 }
10478 bnxt_free_mem(bp, irq_re_init);
10479 }
10480
10481 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
10482 {
10483 int rc = 0;
10484
10485 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) {
10486 /* If we get here, it means firmware reset is in progress
10487 * while we are trying to close. We can safely proceed with
10488 * the close because we are holding rtnl_lock(). Some firmware
10489 * messages may fail as we proceed to close. We set the
10490 * ABORT_ERR flag here so that the FW reset thread will later
10491 * abort when it gets the rtnl_lock() and sees the flag.
10492 */
10493 netdev_warn(bp->dev, "FW reset in progress during close, FW reset will be aborted\n");
10494 set_bit(BNXT_STATE_ABORT_ERR, &bp->state);
10495 }
10496
10497 #ifdef CONFIG_BNXT_SRIOV
10498 if (bp->sriov_cfg) {
10499 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
10500 !bp->sriov_cfg,
10501 BNXT_SRIOV_CFG_WAIT_TMO);
10502 if (rc)
10503 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
10504 }
10505 #endif
10506 __bnxt_close_nic(bp, irq_re_init, link_re_init);
10507 return rc;
10508 }
10509
10510 static int bnxt_close(struct net_device *dev)
10511 {
10512 struct bnxt *bp = netdev_priv(dev);
10513
10514 bnxt_hwmon_close(bp);
10515 bnxt_close_nic(bp, true, true);
10516 bnxt_hwrm_shutdown_link(bp);
10517 bnxt_hwrm_if_change(bp, false);
10518 return 0;
10519 }
10520
10521 static int bnxt_hwrm_port_phy_read(struct bnxt *bp, u16 phy_addr, u16 reg,
10522 u16 *val)
10523 {
10524 struct hwrm_port_phy_mdio_read_output *resp = bp->hwrm_cmd_resp_addr;
10525 struct hwrm_port_phy_mdio_read_input req = {0};
10526 int rc;
10527
10528 if (bp->hwrm_spec_code < 0x10a00)
10529 return -EOPNOTSUPP;
10530
10531 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_READ, -1, -1);
10532 req.port_id = cpu_to_le16(bp->pf.port_id);
10533 req.phy_addr = phy_addr;
10534 req.reg_addr = cpu_to_le16(reg & 0x1f);
10535 if (mdio_phy_id_is_c45(phy_addr)) {
10536 req.cl45_mdio = 1;
10537 req.phy_addr = mdio_phy_id_prtad(phy_addr);
10538 req.dev_addr = mdio_phy_id_devad(phy_addr);
10539 req.reg_addr = cpu_to_le16(reg);
10540 }
10541
10542 mutex_lock(&bp->hwrm_cmd_lock);
10543 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
10544 if (!rc)
10545 *val = le16_to_cpu(resp->reg_data);
10546 mutex_unlock(&bp->hwrm_cmd_lock);
10547 return rc;
10548 }
10549
10550 static int bnxt_hwrm_port_phy_write(struct bnxt *bp, u16 phy_addr, u16 reg,
10551 u16 val)
10552 {
10553 struct hwrm_port_phy_mdio_write_input req = {0};
10554
10555 if (bp->hwrm_spec_code < 0x10a00)
10556 return -EOPNOTSUPP;
10557
10558 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_WRITE, -1, -1);
10559 req.port_id = cpu_to_le16(bp->pf.port_id);
10560 req.phy_addr = phy_addr;
10561 req.reg_addr = cpu_to_le16(reg & 0x1f);
10562 if (mdio_phy_id_is_c45(phy_addr)) {
10563 req.cl45_mdio = 1;
10564 req.phy_addr = mdio_phy_id_prtad(phy_addr);
10565 req.dev_addr = mdio_phy_id_devad(phy_addr);
10566 req.reg_addr = cpu_to_le16(reg);
10567 }
10568 req.reg_data = cpu_to_le16(val);
10569
10570 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
10571 }
10572
10573 /* rtnl_lock held */
10574 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10575 {
10576 struct mii_ioctl_data *mdio = if_mii(ifr);
10577 struct bnxt *bp = netdev_priv(dev);
10578 int rc;
10579
10580 switch (cmd) {
10581 case SIOCGMIIPHY:
10582 mdio->phy_id = bp->link_info.phy_addr;
10583
10584 fallthrough;
10585 case SIOCGMIIREG: {
10586 u16 mii_regval = 0;
10587
10588 if (!netif_running(dev))
10589 return -EAGAIN;
10590
10591 rc = bnxt_hwrm_port_phy_read(bp, mdio->phy_id, mdio->reg_num,
10592 &mii_regval);
10593 mdio->val_out = mii_regval;
10594 return rc;
10595 }
10596
10597 case SIOCSMIIREG:
10598 if (!netif_running(dev))
10599 return -EAGAIN;
10600
10601 return bnxt_hwrm_port_phy_write(bp, mdio->phy_id, mdio->reg_num,
10602 mdio->val_in);
10603
10604 case SIOCSHWTSTAMP:
10605 return bnxt_hwtstamp_set(dev, ifr);
10606
10607 case SIOCGHWTSTAMP:
10608 return bnxt_hwtstamp_get(dev, ifr);
10609
10610 default:
10611 /* do nothing */
10612 break;
10613 }
10614 return -EOPNOTSUPP;
10615 }
10616
10617 static void bnxt_get_ring_stats(struct bnxt *bp,
10618 struct rtnl_link_stats64 *stats)
10619 {
10620 int i;
10621
10622 for (i = 0; i < bp->cp_nr_rings; i++) {
10623 struct bnxt_napi *bnapi = bp->bnapi[i];
10624 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
10625 u64 *sw = cpr->stats.sw_stats;
10626
10627 stats->rx_packets += BNXT_GET_RING_STATS64(sw, rx_ucast_pkts);
10628 stats->rx_packets += BNXT_GET_RING_STATS64(sw, rx_mcast_pkts);
10629 stats->rx_packets += BNXT_GET_RING_STATS64(sw, rx_bcast_pkts);
10630
10631 stats->tx_packets += BNXT_GET_RING_STATS64(sw, tx_ucast_pkts);
10632 stats->tx_packets += BNXT_GET_RING_STATS64(sw, tx_mcast_pkts);
10633 stats->tx_packets += BNXT_GET_RING_STATS64(sw, tx_bcast_pkts);
10634
10635 stats->rx_bytes += BNXT_GET_RING_STATS64(sw, rx_ucast_bytes);
10636 stats->rx_bytes += BNXT_GET_RING_STATS64(sw, rx_mcast_bytes);
10637 stats->rx_bytes += BNXT_GET_RING_STATS64(sw, rx_bcast_bytes);
10638
10639 stats->tx_bytes += BNXT_GET_RING_STATS64(sw, tx_ucast_bytes);
10640 stats->tx_bytes += BNXT_GET_RING_STATS64(sw, tx_mcast_bytes);
10641 stats->tx_bytes += BNXT_GET_RING_STATS64(sw, tx_bcast_bytes);
10642
10643 stats->rx_missed_errors +=
10644 BNXT_GET_RING_STATS64(sw, rx_discard_pkts);
10645
10646 stats->multicast += BNXT_GET_RING_STATS64(sw, rx_mcast_pkts);
10647
10648 stats->tx_dropped += BNXT_GET_RING_STATS64(sw, tx_error_pkts);
10649 }
10650 }
10651
10652 static void bnxt_add_prev_stats(struct bnxt *bp,
10653 struct rtnl_link_stats64 *stats)
10654 {
10655 struct rtnl_link_stats64 *prev_stats = &bp->net_stats_prev;
10656
10657 stats->rx_packets += prev_stats->rx_packets;
10658 stats->tx_packets += prev_stats->tx_packets;
10659 stats->rx_bytes += prev_stats->rx_bytes;
10660 stats->tx_bytes += prev_stats->tx_bytes;
10661 stats->rx_missed_errors += prev_stats->rx_missed_errors;
10662 stats->multicast += prev_stats->multicast;
10663 stats->tx_dropped += prev_stats->tx_dropped;
10664 }
10665
10666 static void
10667 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
10668 {
10669 struct bnxt *bp = netdev_priv(dev);
10670
10671 set_bit(BNXT_STATE_READ_STATS, &bp->state);
10672 /* Make sure bnxt_close_nic() sees that we are reading stats before
10673 * we check the BNXT_STATE_OPEN flag.
10674 */
10675 smp_mb__after_atomic();
10676 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
10677 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
10678 *stats = bp->net_stats_prev;
10679 return;
10680 }
10681
10682 bnxt_get_ring_stats(bp, stats);
10683 bnxt_add_prev_stats(bp, stats);
10684
10685 if (bp->flags & BNXT_FLAG_PORT_STATS) {
10686 u64 *rx = bp->port_stats.sw_stats;
10687 u64 *tx = bp->port_stats.sw_stats +
10688 BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
10689
10690 stats->rx_crc_errors =
10691 BNXT_GET_RX_PORT_STATS64(rx, rx_fcs_err_frames);
10692 stats->rx_frame_errors =
10693 BNXT_GET_RX_PORT_STATS64(rx, rx_align_err_frames);
10694 stats->rx_length_errors =
10695 BNXT_GET_RX_PORT_STATS64(rx, rx_undrsz_frames) +
10696 BNXT_GET_RX_PORT_STATS64(rx, rx_ovrsz_frames) +
10697 BNXT_GET_RX_PORT_STATS64(rx, rx_runt_frames);
10698 stats->rx_errors =
10699 BNXT_GET_RX_PORT_STATS64(rx, rx_false_carrier_frames) +
10700 BNXT_GET_RX_PORT_STATS64(rx, rx_jbr_frames);
10701 stats->collisions =
10702 BNXT_GET_TX_PORT_STATS64(tx, tx_total_collisions);
10703 stats->tx_fifo_errors =
10704 BNXT_GET_TX_PORT_STATS64(tx, tx_fifo_underruns);
10705 stats->tx_errors = BNXT_GET_TX_PORT_STATS64(tx, tx_err);
10706 }
10707 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
10708 }
10709
10710 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
10711 {
10712 struct net_device *dev = bp->dev;
10713 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
10714 struct netdev_hw_addr *ha;
10715 u8 *haddr;
10716 int mc_count = 0;
10717 bool update = false;
10718 int off = 0;
10719
10720 netdev_for_each_mc_addr(ha, dev) {
10721 if (mc_count >= BNXT_MAX_MC_ADDRS) {
10722 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
10723 vnic->mc_list_count = 0;
10724 return false;
10725 }
10726 haddr = ha->addr;
10727 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
10728 memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
10729 update = true;
10730 }
10731 off += ETH_ALEN;
10732 mc_count++;
10733 }
10734 if (mc_count)
10735 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
10736
10737 if (mc_count != vnic->mc_list_count) {
10738 vnic->mc_list_count = mc_count;
10739 update = true;
10740 }
10741 return update;
10742 }
10743
10744 static bool bnxt_uc_list_updated(struct bnxt *bp)
10745 {
10746 struct net_device *dev = bp->dev;
10747 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
10748 struct netdev_hw_addr *ha;
10749 int off = 0;
10750
10751 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
10752 return true;
10753
10754 netdev_for_each_uc_addr(ha, dev) {
10755 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
10756 return true;
10757
10758 off += ETH_ALEN;
10759 }
10760 return false;
10761 }
10762
10763 static void bnxt_set_rx_mode(struct net_device *dev)
10764 {
10765 struct bnxt *bp = netdev_priv(dev);
10766 struct bnxt_vnic_info *vnic;
10767 bool mc_update = false;
10768 bool uc_update;
10769 u32 mask;
10770
10771 if (!test_bit(BNXT_STATE_OPEN, &bp->state))
10772 return;
10773
10774 vnic = &bp->vnic_info[0];
10775 mask = vnic->rx_mask;
10776 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
10777 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
10778 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST |
10779 CFA_L2_SET_RX_MASK_REQ_MASK_BCAST);
10780
10781 if (dev->flags & IFF_PROMISC)
10782 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
10783
10784 uc_update = bnxt_uc_list_updated(bp);
10785
10786 if (dev->flags & IFF_BROADCAST)
10787 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
10788 if (dev->flags & IFF_ALLMULTI) {
10789 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
10790 vnic->mc_list_count = 0;
10791 } else {
10792 mc_update = bnxt_mc_list_updated(bp, &mask);
10793 }
10794
10795 if (mask != vnic->rx_mask || uc_update || mc_update) {
10796 vnic->rx_mask = mask;
10797
10798 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
10799 bnxt_queue_sp_work(bp);
10800 }
10801 }
10802
10803 static int bnxt_cfg_rx_mode(struct bnxt *bp)
10804 {
10805 struct net_device *dev = bp->dev;
10806 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
10807 struct netdev_hw_addr *ha;
10808 int i, off = 0, rc;
10809 bool uc_update;
10810
10811 netif_addr_lock_bh(dev);
10812 uc_update = bnxt_uc_list_updated(bp);
10813 netif_addr_unlock_bh(dev);
10814
10815 if (!uc_update)
10816 goto skip_uc;
10817
10818 mutex_lock(&bp->hwrm_cmd_lock);
10819 for (i = 1; i < vnic->uc_filter_count; i++) {
10820 struct hwrm_cfa_l2_filter_free_input req = {0};
10821
10822 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
10823 -1);
10824
10825 req.l2_filter_id = vnic->fw_l2_filter_id[i];
10826
10827 rc = _hwrm_send_message(bp, &req, sizeof(req),
10828 HWRM_CMD_TIMEOUT);
10829 }
10830 mutex_unlock(&bp->hwrm_cmd_lock);
10831
10832 vnic->uc_filter_count = 1;
10833
10834 netif_addr_lock_bh(dev);
10835 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
10836 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
10837 } else {
10838 netdev_for_each_uc_addr(ha, dev) {
10839 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
10840 off += ETH_ALEN;
10841 vnic->uc_filter_count++;
10842 }
10843 }
10844 netif_addr_unlock_bh(dev);
10845
10846 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
10847 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
10848 if (rc) {
10849 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
10850 rc);
10851 vnic->uc_filter_count = i;
10852 return rc;
10853 }
10854 }
10855
10856 skip_uc:
10857 if ((vnic->rx_mask & CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS) &&
10858 !bnxt_promisc_ok(bp))
10859 vnic->rx_mask &= ~CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
10860 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
10861 if (rc && vnic->mc_list_count) {
10862 netdev_info(bp->dev, "Failed setting MC filters rc: %d, turning on ALL_MCAST mode\n",
10863 rc);
10864 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
10865 vnic->mc_list_count = 0;
10866 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
10867 }
10868 if (rc)
10869 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %d\n",
10870 rc);
10871
10872 return rc;
10873 }
10874
10875 static bool bnxt_can_reserve_rings(struct bnxt *bp)
10876 {
10877 #ifdef CONFIG_BNXT_SRIOV
10878 if (BNXT_NEW_RM(bp) && BNXT_VF(bp)) {
10879 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
10880
10881 /* No minimum rings were provisioned by the PF. Don't
10882 * reserve rings by default when device is down.
10883 */
10884 if (hw_resc->min_tx_rings || hw_resc->resv_tx_rings)
10885 return true;
10886
10887 if (!netif_running(bp->dev))
10888 return false;
10889 }
10890 #endif
10891 return true;
10892 }
10893
10894 /* If the chip and firmware supports RFS */
10895 static bool bnxt_rfs_supported(struct bnxt *bp)
10896 {
10897 if (bp->flags & BNXT_FLAG_CHIP_P5) {
10898 if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2)
10899 return true;
10900 return false;
10901 }
10902 /* 212 firmware is broken for aRFS */
10903 if (BNXT_FW_MAJ(bp) == 212)
10904 return false;
10905 if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
10906 return true;
10907 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
10908 return true;
10909 return false;
10910 }
10911
10912 /* If runtime conditions support RFS */
10913 static bool bnxt_rfs_capable(struct bnxt *bp)
10914 {
10915 #ifdef CONFIG_RFS_ACCEL
10916 int vnics, max_vnics, max_rss_ctxs;
10917
10918 if (bp->flags & BNXT_FLAG_CHIP_P5)
10919 return bnxt_rfs_supported(bp);
10920 if (!(bp->flags & BNXT_FLAG_MSIX_CAP) || !bnxt_can_reserve_rings(bp))
10921 return false;
10922
10923 vnics = 1 + bp->rx_nr_rings;
10924 max_vnics = bnxt_get_max_func_vnics(bp);
10925 max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp);
10926
10927 /* RSS contexts not a limiting factor */
10928 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
10929 max_rss_ctxs = max_vnics;
10930 if (vnics > max_vnics || vnics > max_rss_ctxs) {
10931 if (bp->rx_nr_rings > 1)
10932 netdev_warn(bp->dev,
10933 "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
10934 min(max_rss_ctxs - 1, max_vnics - 1));
10935 return false;
10936 }
10937
10938 if (!BNXT_NEW_RM(bp))
10939 return true;
10940
10941 if (vnics == bp->hw_resc.resv_vnics)
10942 return true;
10943
10944 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, vnics);
10945 if (vnics <= bp->hw_resc.resv_vnics)
10946 return true;
10947
10948 netdev_warn(bp->dev, "Unable to reserve resources to support NTUPLE filters.\n");
10949 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, 1);
10950 return false;
10951 #else
10952 return false;
10953 #endif
10954 }
10955
10956 static netdev_features_t bnxt_fix_features(struct net_device *dev,
10957 netdev_features_t features)
10958 {
10959 struct bnxt *bp = netdev_priv(dev);
10960 netdev_features_t vlan_features;
10961
10962 if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp))
10963 features &= ~NETIF_F_NTUPLE;
10964
10965 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
10966 features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
10967
10968 if (!(features & NETIF_F_GRO))
10969 features &= ~NETIF_F_GRO_HW;
10970
10971 if (features & NETIF_F_GRO_HW)
10972 features &= ~NETIF_F_LRO;
10973
10974 /* Both CTAG and STAG VLAN accelaration on the RX side have to be
10975 * turned on or off together.
10976 */
10977 vlan_features = features & BNXT_HW_FEATURE_VLAN_ALL_RX;
10978 if (vlan_features != BNXT_HW_FEATURE_VLAN_ALL_RX) {
10979 if (dev->features & BNXT_HW_FEATURE_VLAN_ALL_RX)
10980 features &= ~BNXT_HW_FEATURE_VLAN_ALL_RX;
10981 else if (vlan_features)
10982 features |= BNXT_HW_FEATURE_VLAN_ALL_RX;
10983 }
10984 #ifdef CONFIG_BNXT_SRIOV
10985 if (BNXT_VF(bp) && bp->vf.vlan)
10986 features &= ~BNXT_HW_FEATURE_VLAN_ALL_RX;
10987 #endif
10988 return features;
10989 }
10990
10991 static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
10992 {
10993 struct bnxt *bp = netdev_priv(dev);
10994 u32 flags = bp->flags;
10995 u32 changes;
10996 int rc = 0;
10997 bool re_init = false;
10998 bool update_tpa = false;
10999
11000 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
11001 if (features & NETIF_F_GRO_HW)
11002 flags |= BNXT_FLAG_GRO;
11003 else if (features & NETIF_F_LRO)
11004 flags |= BNXT_FLAG_LRO;
11005
11006 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
11007 flags &= ~BNXT_FLAG_TPA;
11008
11009 if (features & BNXT_HW_FEATURE_VLAN_ALL_RX)
11010 flags |= BNXT_FLAG_STRIP_VLAN;
11011
11012 if (features & NETIF_F_NTUPLE)
11013 flags |= BNXT_FLAG_RFS;
11014
11015 changes = flags ^ bp->flags;
11016 if (changes & BNXT_FLAG_TPA) {
11017 update_tpa = true;
11018 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
11019 (flags & BNXT_FLAG_TPA) == 0 ||
11020 (bp->flags & BNXT_FLAG_CHIP_P5))
11021 re_init = true;
11022 }
11023
11024 if (changes & ~BNXT_FLAG_TPA)
11025 re_init = true;
11026
11027 if (flags != bp->flags) {
11028 u32 old_flags = bp->flags;
11029
11030 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
11031 bp->flags = flags;
11032 if (update_tpa)
11033 bnxt_set_ring_params(bp);
11034 return rc;
11035 }
11036
11037 if (re_init) {
11038 bnxt_close_nic(bp, false, false);
11039 bp->flags = flags;
11040 if (update_tpa)
11041 bnxt_set_ring_params(bp);
11042
11043 return bnxt_open_nic(bp, false, false);
11044 }
11045 if (update_tpa) {
11046 bp->flags = flags;
11047 rc = bnxt_set_tpa(bp,
11048 (flags & BNXT_FLAG_TPA) ?
11049 true : false);
11050 if (rc)
11051 bp->flags = old_flags;
11052 }
11053 }
11054 return rc;
11055 }
11056
11057 static bool bnxt_exthdr_check(struct bnxt *bp, struct sk_buff *skb, int nw_off,
11058 u8 **nextp)
11059 {
11060 struct ipv6hdr *ip6h = (struct ipv6hdr *)(skb->data + nw_off);
11061 int hdr_count = 0;
11062 u8 *nexthdr;
11063 int start;
11064
11065 /* Check that there are at most 2 IPv6 extension headers, no
11066 * fragment header, and each is <= 64 bytes.
11067 */
11068 start = nw_off + sizeof(*ip6h);
11069 nexthdr = &ip6h->nexthdr;
11070 while (ipv6_ext_hdr(*nexthdr)) {
11071 struct ipv6_opt_hdr *hp;
11072 int hdrlen;
11073
11074 if (hdr_count >= 3 || *nexthdr == NEXTHDR_NONE ||
11075 *nexthdr == NEXTHDR_FRAGMENT)
11076 return false;
11077 hp = __skb_header_pointer(NULL, start, sizeof(*hp), skb->data,
11078 skb_headlen(skb), NULL);
11079 if (!hp)
11080 return false;
11081 if (*nexthdr == NEXTHDR_AUTH)
11082 hdrlen = ipv6_authlen(hp);
11083 else
11084 hdrlen = ipv6_optlen(hp);
11085
11086 if (hdrlen > 64)
11087 return false;
11088 nexthdr = &hp->nexthdr;
11089 start += hdrlen;
11090 hdr_count++;
11091 }
11092 if (nextp) {
11093 /* Caller will check inner protocol */
11094 if (skb->encapsulation) {
11095 *nextp = nexthdr;
11096 return true;
11097 }
11098 *nextp = NULL;
11099 }
11100 /* Only support TCP/UDP for non-tunneled ipv6 and inner ipv6 */
11101 return *nexthdr == IPPROTO_TCP || *nexthdr == IPPROTO_UDP;
11102 }
11103
11104 /* For UDP, we can only handle 1 Vxlan port and 1 Geneve port. */
11105 static bool bnxt_udp_tunl_check(struct bnxt *bp, struct sk_buff *skb)
11106 {
11107 struct udphdr *uh = udp_hdr(skb);
11108 __be16 udp_port = uh->dest;
11109
11110 if (udp_port != bp->vxlan_port && udp_port != bp->nge_port)
11111 return false;
11112 if (skb->inner_protocol_type == ENCAP_TYPE_ETHER) {
11113 struct ethhdr *eh = inner_eth_hdr(skb);
11114
11115 switch (eh->h_proto) {
11116 case htons(ETH_P_IP):
11117 return true;
11118 case htons(ETH_P_IPV6):
11119 return bnxt_exthdr_check(bp, skb,
11120 skb_inner_network_offset(skb),
11121 NULL);
11122 }
11123 }
11124 return false;
11125 }
11126
11127 static bool bnxt_tunl_check(struct bnxt *bp, struct sk_buff *skb, u8 l4_proto)
11128 {
11129 switch (l4_proto) {
11130 case IPPROTO_UDP:
11131 return bnxt_udp_tunl_check(bp, skb);
11132 case IPPROTO_IPIP:
11133 return true;
11134 case IPPROTO_GRE: {
11135 switch (skb->inner_protocol) {
11136 default:
11137 return false;
11138 case htons(ETH_P_IP):
11139 return true;
11140 case htons(ETH_P_IPV6):
11141 fallthrough;
11142 }
11143 }
11144 case IPPROTO_IPV6:
11145 /* Check ext headers of inner ipv6 */
11146 return bnxt_exthdr_check(bp, skb, skb_inner_network_offset(skb),
11147 NULL);
11148 }
11149 return false;
11150 }
11151
11152 static netdev_features_t bnxt_features_check(struct sk_buff *skb,
11153 struct net_device *dev,
11154 netdev_features_t features)
11155 {
11156 struct bnxt *bp = netdev_priv(dev);
11157 u8 *l4_proto;
11158
11159 features = vlan_features_check(skb, features);
11160 switch (vlan_get_protocol(skb)) {
11161 case htons(ETH_P_IP):
11162 if (!skb->encapsulation)
11163 return features;
11164 l4_proto = &ip_hdr(skb)->protocol;
11165 if (bnxt_tunl_check(bp, skb, *l4_proto))
11166 return features;
11167 break;
11168 case htons(ETH_P_IPV6):
11169 if (!bnxt_exthdr_check(bp, skb, skb_network_offset(skb),
11170 &l4_proto))
11171 break;
11172 if (!l4_proto || bnxt_tunl_check(bp, skb, *l4_proto))
11173 return features;
11174 break;
11175 }
11176 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
11177 }
11178
11179 int bnxt_dbg_hwrm_rd_reg(struct bnxt *bp, u32 reg_off, u16 num_words,
11180 u32 *reg_buf)
11181 {
11182 struct hwrm_dbg_read_direct_output *resp = bp->hwrm_cmd_resp_addr;
11183 struct hwrm_dbg_read_direct_input req = {0};
11184 __le32 *dbg_reg_buf;
11185 dma_addr_t mapping;
11186 int rc, i;
11187
11188 dbg_reg_buf = dma_alloc_coherent(&bp->pdev->dev, num_words * 4,
11189 &mapping, GFP_KERNEL);
11190 if (!dbg_reg_buf)
11191 return -ENOMEM;
11192 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_READ_DIRECT, -1, -1);
11193 req.host_dest_addr = cpu_to_le64(mapping);
11194 req.read_addr = cpu_to_le32(reg_off + CHIMP_REG_VIEW_ADDR);
11195 req.read_len32 = cpu_to_le32(num_words);
11196 mutex_lock(&bp->hwrm_cmd_lock);
11197 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
11198 if (rc || resp->error_code) {
11199 rc = -EIO;
11200 goto dbg_rd_reg_exit;
11201 }
11202 for (i = 0; i < num_words; i++)
11203 reg_buf[i] = le32_to_cpu(dbg_reg_buf[i]);
11204
11205 dbg_rd_reg_exit:
11206 mutex_unlock(&bp->hwrm_cmd_lock);
11207 dma_free_coherent(&bp->pdev->dev, num_words * 4, dbg_reg_buf, mapping);
11208 return rc;
11209 }
11210
11211 static int bnxt_dbg_hwrm_ring_info_get(struct bnxt *bp, u8 ring_type,
11212 u32 ring_id, u32 *prod, u32 *cons)
11213 {
11214 struct hwrm_dbg_ring_info_get_output *resp = bp->hwrm_cmd_resp_addr;
11215 struct hwrm_dbg_ring_info_get_input req = {0};
11216 int rc;
11217
11218 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_RING_INFO_GET, -1, -1);
11219 req.ring_type = ring_type;
11220 req.fw_ring_id = cpu_to_le32(ring_id);
11221 mutex_lock(&bp->hwrm_cmd_lock);
11222 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
11223 if (!rc) {
11224 *prod = le32_to_cpu(resp->producer_index);
11225 *cons = le32_to_cpu(resp->consumer_index);
11226 }
11227 mutex_unlock(&bp->hwrm_cmd_lock);
11228 return rc;
11229 }
11230
11231 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
11232 {
11233 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
11234 int i = bnapi->index;
11235
11236 if (!txr)
11237 return;
11238
11239 netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
11240 i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
11241 txr->tx_cons);
11242 }
11243
11244 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
11245 {
11246 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
11247 int i = bnapi->index;
11248
11249 if (!rxr)
11250 return;
11251
11252 netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
11253 i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
11254 rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
11255 rxr->rx_sw_agg_prod);
11256 }
11257
11258 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
11259 {
11260 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
11261 int i = bnapi->index;
11262
11263 netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
11264 i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
11265 }
11266
11267 static void bnxt_dbg_dump_states(struct bnxt *bp)
11268 {
11269 int i;
11270 struct bnxt_napi *bnapi;
11271
11272 for (i = 0; i < bp->cp_nr_rings; i++) {
11273 bnapi = bp->bnapi[i];
11274 if (netif_msg_drv(bp)) {
11275 bnxt_dump_tx_sw_state(bnapi);
11276 bnxt_dump_rx_sw_state(bnapi);
11277 bnxt_dump_cp_sw_state(bnapi);
11278 }
11279 }
11280 }
11281
11282 static int bnxt_hwrm_rx_ring_reset(struct bnxt *bp, int ring_nr)
11283 {
11284 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[ring_nr];
11285 struct hwrm_ring_reset_input req = {0};
11286 struct bnxt_napi *bnapi = rxr->bnapi;
11287 struct bnxt_cp_ring_info *cpr;
11288 u16 cp_ring_id;
11289
11290 cpr = &bnapi->cp_ring;
11291 cp_ring_id = cpr->cp_ring_struct.fw_ring_id;
11292 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_RESET, cp_ring_id, -1);
11293 req.ring_type = RING_RESET_REQ_RING_TYPE_RX_RING_GRP;
11294 req.ring_id = cpu_to_le16(bp->grp_info[bnapi->index].fw_grp_id);
11295 return hwrm_send_message_silent(bp, &req, sizeof(req),
11296 HWRM_CMD_TIMEOUT);
11297 }
11298
11299 static void bnxt_reset_task(struct bnxt *bp, bool silent)
11300 {
11301 if (!silent)
11302 bnxt_dbg_dump_states(bp);
11303 if (netif_running(bp->dev)) {
11304 int rc;
11305
11306 if (silent) {
11307 bnxt_close_nic(bp, false, false);
11308 bnxt_open_nic(bp, false, false);
11309 } else {
11310 bnxt_ulp_stop(bp);
11311 bnxt_close_nic(bp, true, false);
11312 rc = bnxt_open_nic(bp, true, false);
11313 bnxt_ulp_start(bp, rc);
11314 }
11315 }
11316 }
11317
11318 static void bnxt_tx_timeout(struct net_device *dev, unsigned int txqueue)
11319 {
11320 struct bnxt *bp = netdev_priv(dev);
11321
11322 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n");
11323 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
11324 bnxt_queue_sp_work(bp);
11325 }
11326
11327 static void bnxt_fw_health_check(struct bnxt *bp)
11328 {
11329 struct bnxt_fw_health *fw_health = bp->fw_health;
11330 u32 val;
11331
11332 if (!fw_health->enabled || test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
11333 return;
11334
11335 if (fw_health->tmr_counter) {
11336 fw_health->tmr_counter--;
11337 return;
11338 }
11339
11340 val = bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG);
11341 if (val == fw_health->last_fw_heartbeat)
11342 goto fw_reset;
11343
11344 fw_health->last_fw_heartbeat = val;
11345
11346 val = bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG);
11347 if (val != fw_health->last_fw_reset_cnt)
11348 goto fw_reset;
11349
11350 fw_health->tmr_counter = fw_health->tmr_multiplier;
11351 return;
11352
11353 fw_reset:
11354 set_bit(BNXT_FW_EXCEPTION_SP_EVENT, &bp->sp_event);
11355 bnxt_queue_sp_work(bp);
11356 }
11357
11358 static void bnxt_timer(struct timer_list *t)
11359 {
11360 struct bnxt *bp = from_timer(bp, t, timer);
11361 struct net_device *dev = bp->dev;
11362
11363 if (!netif_running(dev) || !test_bit(BNXT_STATE_OPEN, &bp->state))
11364 return;
11365
11366 if (atomic_read(&bp->intr_sem) != 0)
11367 goto bnxt_restart_timer;
11368
11369 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
11370 bnxt_fw_health_check(bp);
11371
11372 if (bp->link_info.link_up && bp->stats_coal_ticks) {
11373 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
11374 bnxt_queue_sp_work(bp);
11375 }
11376
11377 if (bnxt_tc_flower_enabled(bp)) {
11378 set_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event);
11379 bnxt_queue_sp_work(bp);
11380 }
11381
11382 #ifdef CONFIG_RFS_ACCEL
11383 if ((bp->flags & BNXT_FLAG_RFS) && bp->ntp_fltr_count) {
11384 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
11385 bnxt_queue_sp_work(bp);
11386 }
11387 #endif /*CONFIG_RFS_ACCEL*/
11388
11389 if (bp->link_info.phy_retry) {
11390 if (time_after(jiffies, bp->link_info.phy_retry_expires)) {
11391 bp->link_info.phy_retry = false;
11392 netdev_warn(bp->dev, "failed to update phy settings after maximum retries.\n");
11393 } else {
11394 set_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event);
11395 bnxt_queue_sp_work(bp);
11396 }
11397 }
11398
11399 if ((bp->flags & BNXT_FLAG_CHIP_P5) && !bp->chip_rev &&
11400 netif_carrier_ok(dev)) {
11401 set_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event);
11402 bnxt_queue_sp_work(bp);
11403 }
11404 bnxt_restart_timer:
11405 mod_timer(&bp->timer, jiffies + bp->current_interval);
11406 }
11407
11408 static void bnxt_rtnl_lock_sp(struct bnxt *bp)
11409 {
11410 /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK
11411 * set. If the device is being closed, bnxt_close() may be holding
11412 * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we
11413 * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
11414 */
11415 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
11416 rtnl_lock();
11417 }
11418
11419 static void bnxt_rtnl_unlock_sp(struct bnxt *bp)
11420 {
11421 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
11422 rtnl_unlock();
11423 }
11424
11425 /* Only called from bnxt_sp_task() */
11426 static void bnxt_reset(struct bnxt *bp, bool silent)
11427 {
11428 bnxt_rtnl_lock_sp(bp);
11429 if (test_bit(BNXT_STATE_OPEN, &bp->state))
11430 bnxt_reset_task(bp, silent);
11431 bnxt_rtnl_unlock_sp(bp);
11432 }
11433
11434 /* Only called from bnxt_sp_task() */
11435 static void bnxt_rx_ring_reset(struct bnxt *bp)
11436 {
11437 int i;
11438
11439 bnxt_rtnl_lock_sp(bp);
11440 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
11441 bnxt_rtnl_unlock_sp(bp);
11442 return;
11443 }
11444 /* Disable and flush TPA before resetting the RX ring */
11445 if (bp->flags & BNXT_FLAG_TPA)
11446 bnxt_set_tpa(bp, false);
11447 for (i = 0; i < bp->rx_nr_rings; i++) {
11448 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
11449 struct bnxt_cp_ring_info *cpr;
11450 int rc;
11451
11452 if (!rxr->bnapi->in_reset)
11453 continue;
11454
11455 rc = bnxt_hwrm_rx_ring_reset(bp, i);
11456 if (rc) {
11457 if (rc == -EINVAL || rc == -EOPNOTSUPP)
11458 netdev_info_once(bp->dev, "RX ring reset not supported by firmware, falling back to global reset\n");
11459 else
11460 netdev_warn(bp->dev, "RX ring reset failed, rc = %d, falling back to global reset\n",
11461 rc);
11462 bnxt_reset_task(bp, true);
11463 break;
11464 }
11465 bnxt_free_one_rx_ring_skbs(bp, i);
11466 rxr->rx_prod = 0;
11467 rxr->rx_agg_prod = 0;
11468 rxr->rx_sw_agg_prod = 0;
11469 rxr->rx_next_cons = 0;
11470 rxr->bnapi->in_reset = false;
11471 bnxt_alloc_one_rx_ring(bp, i);
11472 cpr = &rxr->bnapi->cp_ring;
11473 cpr->sw_stats.rx.rx_resets++;
11474 if (bp->flags & BNXT_FLAG_AGG_RINGS)
11475 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
11476 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
11477 }
11478 if (bp->flags & BNXT_FLAG_TPA)
11479 bnxt_set_tpa(bp, true);
11480 bnxt_rtnl_unlock_sp(bp);
11481 }
11482
11483 static void bnxt_fw_reset_close(struct bnxt *bp)
11484 {
11485 bnxt_ulp_stop(bp);
11486 /* When firmware is in fatal state, quiesce device and disable
11487 * bus master to prevent any potential bad DMAs before freeing
11488 * kernel memory.
11489 */
11490 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) {
11491 u16 val = 0;
11492
11493 pci_read_config_word(bp->pdev, PCI_SUBSYSTEM_ID, &val);
11494 if (val == 0xffff)
11495 bp->fw_reset_min_dsecs = 0;
11496 bnxt_tx_disable(bp);
11497 bnxt_disable_napi(bp);
11498 bnxt_disable_int_sync(bp);
11499 bnxt_free_irq(bp);
11500 bnxt_clear_int_mode(bp);
11501 pci_disable_device(bp->pdev);
11502 }
11503 __bnxt_close_nic(bp, true, false);
11504 bnxt_vf_reps_free(bp);
11505 bnxt_clear_int_mode(bp);
11506 bnxt_hwrm_func_drv_unrgtr(bp);
11507 if (pci_is_enabled(bp->pdev))
11508 pci_disable_device(bp->pdev);
11509 bnxt_free_ctx_mem(bp);
11510 kfree(bp->ctx);
11511 bp->ctx = NULL;
11512 }
11513
11514 static bool is_bnxt_fw_ok(struct bnxt *bp)
11515 {
11516 struct bnxt_fw_health *fw_health = bp->fw_health;
11517 bool no_heartbeat = false, has_reset = false;
11518 u32 val;
11519
11520 val = bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG);
11521 if (val == fw_health->last_fw_heartbeat)
11522 no_heartbeat = true;
11523
11524 val = bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG);
11525 if (val != fw_health->last_fw_reset_cnt)
11526 has_reset = true;
11527
11528 if (!no_heartbeat && has_reset)
11529 return true;
11530
11531 return false;
11532 }
11533
11534 /* rtnl_lock is acquired before calling this function */
11535 static void bnxt_force_fw_reset(struct bnxt *bp)
11536 {
11537 struct bnxt_fw_health *fw_health = bp->fw_health;
11538 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
11539 u32 wait_dsecs;
11540
11541 if (!test_bit(BNXT_STATE_OPEN, &bp->state) ||
11542 test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
11543 return;
11544
11545 if (ptp) {
11546 spin_lock_bh(&ptp->ptp_lock);
11547 set_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
11548 spin_unlock_bh(&ptp->ptp_lock);
11549 } else {
11550 set_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
11551 }
11552 bnxt_fw_reset_close(bp);
11553 wait_dsecs = fw_health->master_func_wait_dsecs;
11554 if (fw_health->master) {
11555 if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU)
11556 wait_dsecs = 0;
11557 bp->fw_reset_state = BNXT_FW_RESET_STATE_RESET_FW;
11558 } else {
11559 bp->fw_reset_timestamp = jiffies + wait_dsecs * HZ / 10;
11560 wait_dsecs = fw_health->normal_func_wait_dsecs;
11561 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
11562 }
11563
11564 bp->fw_reset_min_dsecs = fw_health->post_reset_wait_dsecs;
11565 bp->fw_reset_max_dsecs = fw_health->post_reset_max_wait_dsecs;
11566 bnxt_queue_fw_reset_work(bp, wait_dsecs * HZ / 10);
11567 }
11568
11569 void bnxt_fw_exception(struct bnxt *bp)
11570 {
11571 netdev_warn(bp->dev, "Detected firmware fatal condition, initiating reset\n");
11572 set_bit(BNXT_STATE_FW_FATAL_COND, &bp->state);
11573 bnxt_rtnl_lock_sp(bp);
11574 bnxt_force_fw_reset(bp);
11575 bnxt_rtnl_unlock_sp(bp);
11576 }
11577
11578 /* Returns the number of registered VFs, or 1 if VF configuration is pending, or
11579 * < 0 on error.
11580 */
11581 static int bnxt_get_registered_vfs(struct bnxt *bp)
11582 {
11583 #ifdef CONFIG_BNXT_SRIOV
11584 int rc;
11585
11586 if (!BNXT_PF(bp))
11587 return 0;
11588
11589 rc = bnxt_hwrm_func_qcfg(bp);
11590 if (rc) {
11591 netdev_err(bp->dev, "func_qcfg cmd failed, rc = %d\n", rc);
11592 return rc;
11593 }
11594 if (bp->pf.registered_vfs)
11595 return bp->pf.registered_vfs;
11596 if (bp->sriov_cfg)
11597 return 1;
11598 #endif
11599 return 0;
11600 }
11601
11602 void bnxt_fw_reset(struct bnxt *bp)
11603 {
11604 bnxt_rtnl_lock_sp(bp);
11605 if (test_bit(BNXT_STATE_OPEN, &bp->state) &&
11606 !test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) {
11607 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
11608 int n = 0, tmo;
11609
11610 if (ptp) {
11611 spin_lock_bh(&ptp->ptp_lock);
11612 set_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
11613 spin_unlock_bh(&ptp->ptp_lock);
11614 } else {
11615 set_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
11616 }
11617 if (bp->pf.active_vfs &&
11618 !test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))
11619 n = bnxt_get_registered_vfs(bp);
11620 if (n < 0) {
11621 netdev_err(bp->dev, "Firmware reset aborted, rc = %d\n",
11622 n);
11623 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
11624 dev_close(bp->dev);
11625 goto fw_reset_exit;
11626 } else if (n > 0) {
11627 u16 vf_tmo_dsecs = n * 10;
11628
11629 if (bp->fw_reset_max_dsecs < vf_tmo_dsecs)
11630 bp->fw_reset_max_dsecs = vf_tmo_dsecs;
11631 bp->fw_reset_state =
11632 BNXT_FW_RESET_STATE_POLL_VF;
11633 bnxt_queue_fw_reset_work(bp, HZ / 10);
11634 goto fw_reset_exit;
11635 }
11636 bnxt_fw_reset_close(bp);
11637 if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) {
11638 bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW_DOWN;
11639 tmo = HZ / 10;
11640 } else {
11641 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
11642 tmo = bp->fw_reset_min_dsecs * HZ / 10;
11643 }
11644 bnxt_queue_fw_reset_work(bp, tmo);
11645 }
11646 fw_reset_exit:
11647 bnxt_rtnl_unlock_sp(bp);
11648 }
11649
11650 static void bnxt_chk_missed_irq(struct bnxt *bp)
11651 {
11652 int i;
11653
11654 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
11655 return;
11656
11657 for (i = 0; i < bp->cp_nr_rings; i++) {
11658 struct bnxt_napi *bnapi = bp->bnapi[i];
11659 struct bnxt_cp_ring_info *cpr;
11660 u32 fw_ring_id;
11661 int j;
11662
11663 if (!bnapi)
11664 continue;
11665
11666 cpr = &bnapi->cp_ring;
11667 for (j = 0; j < 2; j++) {
11668 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
11669 u32 val[2];
11670
11671 if (!cpr2 || cpr2->has_more_work ||
11672 !bnxt_has_work(bp, cpr2))
11673 continue;
11674
11675 if (cpr2->cp_raw_cons != cpr2->last_cp_raw_cons) {
11676 cpr2->last_cp_raw_cons = cpr2->cp_raw_cons;
11677 continue;
11678 }
11679 fw_ring_id = cpr2->cp_ring_struct.fw_ring_id;
11680 bnxt_dbg_hwrm_ring_info_get(bp,
11681 DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL,
11682 fw_ring_id, &val[0], &val[1]);
11683 cpr->sw_stats.cmn.missed_irqs++;
11684 }
11685 }
11686 }
11687
11688 static void bnxt_cfg_ntp_filters(struct bnxt *);
11689
11690 static void bnxt_init_ethtool_link_settings(struct bnxt *bp)
11691 {
11692 struct bnxt_link_info *link_info = &bp->link_info;
11693
11694 if (BNXT_AUTO_MODE(link_info->auto_mode)) {
11695 link_info->autoneg = BNXT_AUTONEG_SPEED;
11696 if (bp->hwrm_spec_code >= 0x10201) {
11697 if (link_info->auto_pause_setting &
11698 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
11699 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
11700 } else {
11701 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
11702 }
11703 link_info->advertising = link_info->auto_link_speeds;
11704 link_info->advertising_pam4 = link_info->auto_pam4_link_speeds;
11705 } else {
11706 link_info->req_link_speed = link_info->force_link_speed;
11707 link_info->req_signal_mode = BNXT_SIG_MODE_NRZ;
11708 if (link_info->force_pam4_link_speed) {
11709 link_info->req_link_speed =
11710 link_info->force_pam4_link_speed;
11711 link_info->req_signal_mode = BNXT_SIG_MODE_PAM4;
11712 }
11713 link_info->req_duplex = link_info->duplex_setting;
11714 }
11715 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
11716 link_info->req_flow_ctrl =
11717 link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
11718 else
11719 link_info->req_flow_ctrl = link_info->force_pause_setting;
11720 }
11721
11722 static void bnxt_fw_echo_reply(struct bnxt *bp)
11723 {
11724 struct bnxt_fw_health *fw_health = bp->fw_health;
11725 struct hwrm_func_echo_response_input req = {0};
11726
11727 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_ECHO_RESPONSE, -1, -1);
11728 req.event_data1 = cpu_to_le32(fw_health->echo_req_data1);
11729 req.event_data2 = cpu_to_le32(fw_health->echo_req_data2);
11730 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
11731 }
11732
11733 static void bnxt_sp_task(struct work_struct *work)
11734 {
11735 struct bnxt *bp = container_of(work, struct bnxt, sp_task);
11736
11737 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
11738 smp_mb__after_atomic();
11739 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
11740 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
11741 return;
11742 }
11743
11744 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
11745 bnxt_cfg_rx_mode(bp);
11746
11747 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
11748 bnxt_cfg_ntp_filters(bp);
11749 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
11750 bnxt_hwrm_exec_fwd_req(bp);
11751 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event)) {
11752 bnxt_hwrm_port_qstats(bp, 0);
11753 bnxt_hwrm_port_qstats_ext(bp, 0);
11754 bnxt_accumulate_all_stats(bp);
11755 }
11756
11757 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
11758 int rc;
11759
11760 mutex_lock(&bp->link_lock);
11761 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT,
11762 &bp->sp_event))
11763 bnxt_hwrm_phy_qcaps(bp);
11764
11765 rc = bnxt_update_link(bp, true);
11766 if (rc)
11767 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
11768 rc);
11769
11770 if (test_and_clear_bit(BNXT_LINK_CFG_CHANGE_SP_EVENT,
11771 &bp->sp_event))
11772 bnxt_init_ethtool_link_settings(bp);
11773 mutex_unlock(&bp->link_lock);
11774 }
11775 if (test_and_clear_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event)) {
11776 int rc;
11777
11778 mutex_lock(&bp->link_lock);
11779 rc = bnxt_update_phy_setting(bp);
11780 mutex_unlock(&bp->link_lock);
11781 if (rc) {
11782 netdev_warn(bp->dev, "update phy settings retry failed\n");
11783 } else {
11784 bp->link_info.phy_retry = false;
11785 netdev_info(bp->dev, "update phy settings retry succeeded\n");
11786 }
11787 }
11788 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) {
11789 mutex_lock(&bp->link_lock);
11790 bnxt_get_port_module_status(bp);
11791 mutex_unlock(&bp->link_lock);
11792 }
11793
11794 if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event))
11795 bnxt_tc_flow_stats_work(bp);
11796
11797 if (test_and_clear_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event))
11798 bnxt_chk_missed_irq(bp);
11799
11800 if (test_and_clear_bit(BNXT_FW_ECHO_REQUEST_SP_EVENT, &bp->sp_event))
11801 bnxt_fw_echo_reply(bp);
11802
11803 /* These functions below will clear BNXT_STATE_IN_SP_TASK. They
11804 * must be the last functions to be called before exiting.
11805 */
11806 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
11807 bnxt_reset(bp, false);
11808
11809 if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
11810 bnxt_reset(bp, true);
11811
11812 if (test_and_clear_bit(BNXT_RST_RING_SP_EVENT, &bp->sp_event))
11813 bnxt_rx_ring_reset(bp);
11814
11815 if (test_and_clear_bit(BNXT_FW_RESET_NOTIFY_SP_EVENT, &bp->sp_event))
11816 bnxt_devlink_health_report(bp, BNXT_FW_RESET_NOTIFY_SP_EVENT);
11817
11818 if (test_and_clear_bit(BNXT_FW_EXCEPTION_SP_EVENT, &bp->sp_event)) {
11819 if (!is_bnxt_fw_ok(bp))
11820 bnxt_devlink_health_report(bp,
11821 BNXT_FW_EXCEPTION_SP_EVENT);
11822 }
11823
11824 smp_mb__before_atomic();
11825 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
11826 }
11827
11828 /* Under rtnl_lock */
11829 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
11830 int tx_xdp)
11831 {
11832 int max_rx, max_tx, tx_sets = 1;
11833 int tx_rings_needed, stats;
11834 int rx_rings = rx;
11835 int cp, vnics, rc;
11836
11837 if (tcs)
11838 tx_sets = tcs;
11839
11840 rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh);
11841 if (rc)
11842 return rc;
11843
11844 if (max_rx < rx)
11845 return -ENOMEM;
11846
11847 tx_rings_needed = tx * tx_sets + tx_xdp;
11848 if (max_tx < tx_rings_needed)
11849 return -ENOMEM;
11850
11851 vnics = 1;
11852 if ((bp->flags & (BNXT_FLAG_RFS | BNXT_FLAG_CHIP_P5)) == BNXT_FLAG_RFS)
11853 vnics += rx_rings;
11854
11855 if (bp->flags & BNXT_FLAG_AGG_RINGS)
11856 rx_rings <<= 1;
11857 cp = sh ? max_t(int, tx_rings_needed, rx) : tx_rings_needed + rx;
11858 stats = cp;
11859 if (BNXT_NEW_RM(bp)) {
11860 cp += bnxt_get_ulp_msix_num(bp);
11861 stats += bnxt_get_ulp_stat_ctxs(bp);
11862 }
11863 return bnxt_hwrm_check_rings(bp, tx_rings_needed, rx_rings, rx, cp,
11864 stats, vnics);
11865 }
11866
11867 static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev)
11868 {
11869 if (bp->bar2) {
11870 pci_iounmap(pdev, bp->bar2);
11871 bp->bar2 = NULL;
11872 }
11873
11874 if (bp->bar1) {
11875 pci_iounmap(pdev, bp->bar1);
11876 bp->bar1 = NULL;
11877 }
11878
11879 if (bp->bar0) {
11880 pci_iounmap(pdev, bp->bar0);
11881 bp->bar0 = NULL;
11882 }
11883 }
11884
11885 static void bnxt_cleanup_pci(struct bnxt *bp)
11886 {
11887 bnxt_unmap_bars(bp, bp->pdev);
11888 pci_release_regions(bp->pdev);
11889 if (pci_is_enabled(bp->pdev))
11890 pci_disable_device(bp->pdev);
11891 }
11892
11893 static void bnxt_init_dflt_coal(struct bnxt *bp)
11894 {
11895 struct bnxt_coal *coal;
11896
11897 /* Tick values in micro seconds.
11898 * 1 coal_buf x bufs_per_record = 1 completion record.
11899 */
11900 coal = &bp->rx_coal;
11901 coal->coal_ticks = 10;
11902 coal->coal_bufs = 30;
11903 coal->coal_ticks_irq = 1;
11904 coal->coal_bufs_irq = 2;
11905 coal->idle_thresh = 50;
11906 coal->bufs_per_record = 2;
11907 coal->budget = 64; /* NAPI budget */
11908
11909 coal = &bp->tx_coal;
11910 coal->coal_ticks = 28;
11911 coal->coal_bufs = 30;
11912 coal->coal_ticks_irq = 2;
11913 coal->coal_bufs_irq = 2;
11914 coal->bufs_per_record = 1;
11915
11916 bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS;
11917 }
11918
11919 static int bnxt_fw_init_one_p1(struct bnxt *bp)
11920 {
11921 int rc;
11922
11923 bp->fw_cap = 0;
11924 rc = bnxt_hwrm_ver_get(bp);
11925 bnxt_try_map_fw_health_reg(bp);
11926 if (rc) {
11927 rc = bnxt_try_recover_fw(bp);
11928 if (rc)
11929 return rc;
11930 rc = bnxt_hwrm_ver_get(bp);
11931 if (rc)
11932 return rc;
11933 }
11934
11935 if (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL) {
11936 rc = bnxt_alloc_kong_hwrm_resources(bp);
11937 if (rc)
11938 bp->fw_cap &= ~BNXT_FW_CAP_KONG_MB_CHNL;
11939 }
11940
11941 if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) ||
11942 bp->hwrm_max_ext_req_len > BNXT_HWRM_MAX_REQ_LEN) {
11943 rc = bnxt_alloc_hwrm_short_cmd_req(bp);
11944 if (rc)
11945 return rc;
11946 }
11947 bnxt_nvm_cfg_ver_get(bp);
11948
11949 rc = bnxt_hwrm_func_reset(bp);
11950 if (rc)
11951 return -ENODEV;
11952
11953 bnxt_hwrm_fw_set_time(bp);
11954 return 0;
11955 }
11956
11957 static int bnxt_fw_init_one_p2(struct bnxt *bp)
11958 {
11959 int rc;
11960
11961 /* Get the MAX capabilities for this function */
11962 rc = bnxt_hwrm_func_qcaps(bp);
11963 if (rc) {
11964 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
11965 rc);
11966 return -ENODEV;
11967 }
11968
11969 rc = bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(bp);
11970 if (rc)
11971 netdev_warn(bp->dev, "hwrm query adv flow mgnt failure rc: %d\n",
11972 rc);
11973
11974 if (bnxt_alloc_fw_health(bp)) {
11975 netdev_warn(bp->dev, "no memory for firmware error recovery\n");
11976 } else {
11977 rc = bnxt_hwrm_error_recovery_qcfg(bp);
11978 if (rc)
11979 netdev_warn(bp->dev, "hwrm query error recovery failure rc: %d\n",
11980 rc);
11981 }
11982
11983 rc = bnxt_hwrm_func_drv_rgtr(bp, NULL, 0, false);
11984 if (rc)
11985 return -ENODEV;
11986
11987 bnxt_hwrm_func_qcfg(bp);
11988 bnxt_hwrm_vnic_qcaps(bp);
11989 bnxt_hwrm_port_led_qcaps(bp);
11990 bnxt_ethtool_init(bp);
11991 bnxt_dcb_init(bp);
11992 return 0;
11993 }
11994
11995 static void bnxt_set_dflt_rss_hash_type(struct bnxt *bp)
11996 {
11997 bp->flags &= ~BNXT_FLAG_UDP_RSS_CAP;
11998 bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 |
11999 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 |
12000 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |
12001 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
12002 if (BNXT_CHIP_P4_PLUS(bp) && bp->hwrm_spec_code >= 0x10501) {
12003 bp->flags |= BNXT_FLAG_UDP_RSS_CAP;
12004 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 |
12005 VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
12006 }
12007 }
12008
12009 static void bnxt_set_dflt_rfs(struct bnxt *bp)
12010 {
12011 struct net_device *dev = bp->dev;
12012
12013 dev->hw_features &= ~NETIF_F_NTUPLE;
12014 dev->features &= ~NETIF_F_NTUPLE;
12015 bp->flags &= ~BNXT_FLAG_RFS;
12016 if (bnxt_rfs_supported(bp)) {
12017 dev->hw_features |= NETIF_F_NTUPLE;
12018 if (bnxt_rfs_capable(bp)) {
12019 bp->flags |= BNXT_FLAG_RFS;
12020 dev->features |= NETIF_F_NTUPLE;
12021 }
12022 }
12023 }
12024
12025 static void bnxt_fw_init_one_p3(struct bnxt *bp)
12026 {
12027 struct pci_dev *pdev = bp->pdev;
12028
12029 bnxt_set_dflt_rss_hash_type(bp);
12030 bnxt_set_dflt_rfs(bp);
12031
12032 bnxt_get_wol_settings(bp);
12033 if (bp->flags & BNXT_FLAG_WOL_CAP)
12034 device_set_wakeup_enable(&pdev->dev, bp->wol);
12035 else
12036 device_set_wakeup_capable(&pdev->dev, false);
12037
12038 bnxt_hwrm_set_cache_line_size(bp, cache_line_size());
12039 bnxt_hwrm_coal_params_qcaps(bp);
12040 }
12041
12042 static int bnxt_probe_phy(struct bnxt *bp, bool fw_dflt);
12043
12044 static int bnxt_fw_init_one(struct bnxt *bp)
12045 {
12046 int rc;
12047
12048 rc = bnxt_fw_init_one_p1(bp);
12049 if (rc) {
12050 netdev_err(bp->dev, "Firmware init phase 1 failed\n");
12051 return rc;
12052 }
12053 rc = bnxt_fw_init_one_p2(bp);
12054 if (rc) {
12055 netdev_err(bp->dev, "Firmware init phase 2 failed\n");
12056 return rc;
12057 }
12058 rc = bnxt_probe_phy(bp, false);
12059 if (rc)
12060 return rc;
12061 rc = bnxt_approve_mac(bp, bp->dev->dev_addr, false);
12062 if (rc)
12063 return rc;
12064
12065 /* In case fw capabilities have changed, destroy the unneeded
12066 * reporters and create newly capable ones.
12067 */
12068 bnxt_dl_fw_reporters_destroy(bp, false);
12069 bnxt_dl_fw_reporters_create(bp);
12070 bnxt_fw_init_one_p3(bp);
12071 return 0;
12072 }
12073
12074 static void bnxt_fw_reset_writel(struct bnxt *bp, int reg_idx)
12075 {
12076 struct bnxt_fw_health *fw_health = bp->fw_health;
12077 u32 reg = fw_health->fw_reset_seq_regs[reg_idx];
12078 u32 val = fw_health->fw_reset_seq_vals[reg_idx];
12079 u32 reg_type, reg_off, delay_msecs;
12080
12081 delay_msecs = fw_health->fw_reset_seq_delay_msec[reg_idx];
12082 reg_type = BNXT_FW_HEALTH_REG_TYPE(reg);
12083 reg_off = BNXT_FW_HEALTH_REG_OFF(reg);
12084 switch (reg_type) {
12085 case BNXT_FW_HEALTH_REG_TYPE_CFG:
12086 pci_write_config_dword(bp->pdev, reg_off, val);
12087 break;
12088 case BNXT_FW_HEALTH_REG_TYPE_GRC:
12089 writel(reg_off & BNXT_GRC_BASE_MASK,
12090 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
12091 reg_off = (reg_off & BNXT_GRC_OFFSET_MASK) + 0x2000;
12092 fallthrough;
12093 case BNXT_FW_HEALTH_REG_TYPE_BAR0:
12094 writel(val, bp->bar0 + reg_off);
12095 break;
12096 case BNXT_FW_HEALTH_REG_TYPE_BAR1:
12097 writel(val, bp->bar1 + reg_off);
12098 break;
12099 }
12100 if (delay_msecs) {
12101 pci_read_config_dword(bp->pdev, 0, &val);
12102 msleep(delay_msecs);
12103 }
12104 }
12105
12106 static void bnxt_reset_all(struct bnxt *bp)
12107 {
12108 struct bnxt_fw_health *fw_health = bp->fw_health;
12109 int i, rc;
12110
12111 if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) {
12112 bnxt_fw_reset_via_optee(bp);
12113 bp->fw_reset_timestamp = jiffies;
12114 return;
12115 }
12116
12117 if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST) {
12118 for (i = 0; i < fw_health->fw_reset_seq_cnt; i++)
12119 bnxt_fw_reset_writel(bp, i);
12120 } else if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) {
12121 struct hwrm_fw_reset_input req = {0};
12122
12123 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_RESET, -1, -1);
12124 req.resp_addr = cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr);
12125 req.embedded_proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP;
12126 req.selfrst_status = FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP;
12127 req.flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL;
12128 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
12129 if (rc != -ENODEV)
12130 netdev_warn(bp->dev, "Unable to reset FW rc=%d\n", rc);
12131 }
12132 bp->fw_reset_timestamp = jiffies;
12133 }
12134
12135 static bool bnxt_fw_reset_timeout(struct bnxt *bp)
12136 {
12137 return time_after(jiffies, bp->fw_reset_timestamp +
12138 (bp->fw_reset_max_dsecs * HZ / 10));
12139 }
12140
12141 static void bnxt_fw_reset_abort(struct bnxt *bp, int rc)
12142 {
12143 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
12144 if (bp->fw_reset_state != BNXT_FW_RESET_STATE_POLL_VF) {
12145 bnxt_ulp_start(bp, rc);
12146 bnxt_dl_health_status_update(bp, false);
12147 }
12148 bp->fw_reset_state = 0;
12149 dev_close(bp->dev);
12150 }
12151
12152 static void bnxt_fw_reset_task(struct work_struct *work)
12153 {
12154 struct bnxt *bp = container_of(work, struct bnxt, fw_reset_task.work);
12155 int rc = 0;
12156
12157 if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) {
12158 netdev_err(bp->dev, "bnxt_fw_reset_task() called when not in fw reset mode!\n");
12159 return;
12160 }
12161
12162 switch (bp->fw_reset_state) {
12163 case BNXT_FW_RESET_STATE_POLL_VF: {
12164 int n = bnxt_get_registered_vfs(bp);
12165 int tmo;
12166
12167 if (n < 0) {
12168 netdev_err(bp->dev, "Firmware reset aborted, subsequent func_qcfg cmd failed, rc = %d, %d msecs since reset timestamp\n",
12169 n, jiffies_to_msecs(jiffies -
12170 bp->fw_reset_timestamp));
12171 goto fw_reset_abort;
12172 } else if (n > 0) {
12173 if (bnxt_fw_reset_timeout(bp)) {
12174 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
12175 bp->fw_reset_state = 0;
12176 netdev_err(bp->dev, "Firmware reset aborted, bnxt_get_registered_vfs() returns %d\n",
12177 n);
12178 return;
12179 }
12180 bnxt_queue_fw_reset_work(bp, HZ / 10);
12181 return;
12182 }
12183 bp->fw_reset_timestamp = jiffies;
12184 rtnl_lock();
12185 if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state)) {
12186 bnxt_fw_reset_abort(bp, rc);
12187 rtnl_unlock();
12188 return;
12189 }
12190 bnxt_fw_reset_close(bp);
12191 if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) {
12192 bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW_DOWN;
12193 tmo = HZ / 10;
12194 } else {
12195 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
12196 tmo = bp->fw_reset_min_dsecs * HZ / 10;
12197 }
12198 rtnl_unlock();
12199 bnxt_queue_fw_reset_work(bp, tmo);
12200 return;
12201 }
12202 case BNXT_FW_RESET_STATE_POLL_FW_DOWN: {
12203 u32 val;
12204
12205 val = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG);
12206 if (!(val & BNXT_FW_STATUS_SHUTDOWN) &&
12207 !bnxt_fw_reset_timeout(bp)) {
12208 bnxt_queue_fw_reset_work(bp, HZ / 5);
12209 return;
12210 }
12211
12212 if (!bp->fw_health->master) {
12213 u32 wait_dsecs = bp->fw_health->normal_func_wait_dsecs;
12214
12215 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
12216 bnxt_queue_fw_reset_work(bp, wait_dsecs * HZ / 10);
12217 return;
12218 }
12219 bp->fw_reset_state = BNXT_FW_RESET_STATE_RESET_FW;
12220 }
12221 fallthrough;
12222 case BNXT_FW_RESET_STATE_RESET_FW:
12223 bnxt_reset_all(bp);
12224 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
12225 bnxt_queue_fw_reset_work(bp, bp->fw_reset_min_dsecs * HZ / 10);
12226 return;
12227 case BNXT_FW_RESET_STATE_ENABLE_DEV:
12228 bnxt_inv_fw_health_reg(bp);
12229 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state) &&
12230 !bp->fw_reset_min_dsecs) {
12231 u16 val;
12232
12233 pci_read_config_word(bp->pdev, PCI_SUBSYSTEM_ID, &val);
12234 if (val == 0xffff) {
12235 if (bnxt_fw_reset_timeout(bp)) {
12236 netdev_err(bp->dev, "Firmware reset aborted, PCI config space invalid\n");
12237 rc = -ETIMEDOUT;
12238 goto fw_reset_abort;
12239 }
12240 bnxt_queue_fw_reset_work(bp, HZ / 1000);
12241 return;
12242 }
12243 }
12244 clear_bit(BNXT_STATE_FW_FATAL_COND, &bp->state);
12245 if (pci_enable_device(bp->pdev)) {
12246 netdev_err(bp->dev, "Cannot re-enable PCI device\n");
12247 rc = -ENODEV;
12248 goto fw_reset_abort;
12249 }
12250 pci_set_master(bp->pdev);
12251 bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW;
12252 fallthrough;
12253 case BNXT_FW_RESET_STATE_POLL_FW:
12254 bp->hwrm_cmd_timeout = SHORT_HWRM_CMD_TIMEOUT;
12255 rc = __bnxt_hwrm_ver_get(bp, true);
12256 if (rc) {
12257 if (bnxt_fw_reset_timeout(bp)) {
12258 netdev_err(bp->dev, "Firmware reset aborted\n");
12259 goto fw_reset_abort_status;
12260 }
12261 bnxt_queue_fw_reset_work(bp, HZ / 5);
12262 return;
12263 }
12264 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
12265 bp->fw_reset_state = BNXT_FW_RESET_STATE_OPENING;
12266 fallthrough;
12267 case BNXT_FW_RESET_STATE_OPENING:
12268 while (!rtnl_trylock()) {
12269 bnxt_queue_fw_reset_work(bp, HZ / 10);
12270 return;
12271 }
12272 rc = bnxt_open(bp->dev);
12273 if (rc) {
12274 netdev_err(bp->dev, "bnxt_open() failed during FW reset\n");
12275 bnxt_fw_reset_abort(bp, rc);
12276 rtnl_unlock();
12277 return;
12278 }
12279
12280 bp->fw_reset_state = 0;
12281 /* Make sure fw_reset_state is 0 before clearing the flag */
12282 smp_mb__before_atomic();
12283 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
12284 bnxt_ulp_start(bp, 0);
12285 bnxt_reenable_sriov(bp);
12286 bnxt_vf_reps_alloc(bp);
12287 bnxt_vf_reps_open(bp);
12288 bnxt_ptp_reapply_pps(bp);
12289 bnxt_dl_health_recovery_done(bp);
12290 bnxt_dl_health_status_update(bp, true);
12291 rtnl_unlock();
12292 break;
12293 }
12294 return;
12295
12296 fw_reset_abort_status:
12297 if (bp->fw_health->status_reliable ||
12298 (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) {
12299 u32 sts = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG);
12300
12301 netdev_err(bp->dev, "fw_health_status 0x%x\n", sts);
12302 }
12303 fw_reset_abort:
12304 rtnl_lock();
12305 bnxt_fw_reset_abort(bp, rc);
12306 rtnl_unlock();
12307 }
12308
12309 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
12310 {
12311 int rc;
12312 struct bnxt *bp = netdev_priv(dev);
12313
12314 SET_NETDEV_DEV(dev, &pdev->dev);
12315
12316 /* enable device (incl. PCI PM wakeup), and bus-mastering */
12317 rc = pci_enable_device(pdev);
12318 if (rc) {
12319 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
12320 goto init_err;
12321 }
12322
12323 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
12324 dev_err(&pdev->dev,
12325 "Cannot find PCI device base address, aborting\n");
12326 rc = -ENODEV;
12327 goto init_err_disable;
12328 }
12329
12330 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
12331 if (rc) {
12332 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
12333 goto init_err_disable;
12334 }
12335
12336 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
12337 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
12338 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
12339 rc = -EIO;
12340 goto init_err_release;
12341 }
12342
12343 pci_set_master(pdev);
12344
12345 bp->dev = dev;
12346 bp->pdev = pdev;
12347
12348 /* Doorbell BAR bp->bar1 is mapped after bnxt_fw_init_one_p2()
12349 * determines the BAR size.
12350 */
12351 bp->bar0 = pci_ioremap_bar(pdev, 0);
12352 if (!bp->bar0) {
12353 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
12354 rc = -ENOMEM;
12355 goto init_err_release;
12356 }
12357
12358 bp->bar2 = pci_ioremap_bar(pdev, 4);
12359 if (!bp->bar2) {
12360 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
12361 rc = -ENOMEM;
12362 goto init_err_release;
12363 }
12364
12365 pci_enable_pcie_error_reporting(pdev);
12366
12367 INIT_WORK(&bp->sp_task, bnxt_sp_task);
12368 INIT_DELAYED_WORK(&bp->fw_reset_task, bnxt_fw_reset_task);
12369
12370 spin_lock_init(&bp->ntp_fltr_lock);
12371 #if BITS_PER_LONG == 32
12372 spin_lock_init(&bp->db_lock);
12373 #endif
12374
12375 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
12376 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
12377
12378 bnxt_init_dflt_coal(bp);
12379
12380 timer_setup(&bp->timer, bnxt_timer, 0);
12381 bp->current_interval = BNXT_TIMER_INTERVAL;
12382
12383 bp->vxlan_fw_dst_port_id = INVALID_HW_RING_ID;
12384 bp->nge_fw_dst_port_id = INVALID_HW_RING_ID;
12385
12386 clear_bit(BNXT_STATE_OPEN, &bp->state);
12387 return 0;
12388
12389 init_err_release:
12390 bnxt_unmap_bars(bp, pdev);
12391 pci_release_regions(pdev);
12392
12393 init_err_disable:
12394 pci_disable_device(pdev);
12395
12396 init_err:
12397 return rc;
12398 }
12399
12400 /* rtnl_lock held */
12401 static int bnxt_change_mac_addr(struct net_device *dev, void *p)
12402 {
12403 struct sockaddr *addr = p;
12404 struct bnxt *bp = netdev_priv(dev);
12405 int rc = 0;
12406
12407 if (!is_valid_ether_addr(addr->sa_data))
12408 return -EADDRNOTAVAIL;
12409
12410 if (ether_addr_equal(addr->sa_data, dev->dev_addr))
12411 return 0;
12412
12413 rc = bnxt_approve_mac(bp, addr->sa_data, true);
12414 if (rc)
12415 return rc;
12416
12417 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
12418 if (netif_running(dev)) {
12419 bnxt_close_nic(bp, false, false);
12420 rc = bnxt_open_nic(bp, false, false);
12421 }
12422
12423 return rc;
12424 }
12425
12426 /* rtnl_lock held */
12427 static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
12428 {
12429 struct bnxt *bp = netdev_priv(dev);
12430
12431 if (netif_running(dev))
12432 bnxt_close_nic(bp, true, false);
12433
12434 dev->mtu = new_mtu;
12435 bnxt_set_ring_params(bp);
12436
12437 if (netif_running(dev))
12438 return bnxt_open_nic(bp, true, false);
12439
12440 return 0;
12441 }
12442
12443 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc)
12444 {
12445 struct bnxt *bp = netdev_priv(dev);
12446 bool sh = false;
12447 int rc;
12448
12449 if (tc > bp->max_tc) {
12450 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n",
12451 tc, bp->max_tc);
12452 return -EINVAL;
12453 }
12454
12455 if (netdev_get_num_tc(dev) == tc)
12456 return 0;
12457
12458 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
12459 sh = true;
12460
12461 rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings,
12462 sh, tc, bp->tx_nr_rings_xdp);
12463 if (rc)
12464 return rc;
12465
12466 /* Needs to close the device and do hw resource re-allocations */
12467 if (netif_running(bp->dev))
12468 bnxt_close_nic(bp, true, false);
12469
12470 if (tc) {
12471 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
12472 netdev_set_num_tc(dev, tc);
12473 } else {
12474 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
12475 netdev_reset_tc(dev);
12476 }
12477 bp->tx_nr_rings += bp->tx_nr_rings_xdp;
12478 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
12479 bp->tx_nr_rings + bp->rx_nr_rings;
12480
12481 if (netif_running(bp->dev))
12482 return bnxt_open_nic(bp, true, false);
12483
12484 return 0;
12485 }
12486
12487 static int bnxt_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
12488 void *cb_priv)
12489 {
12490 struct bnxt *bp = cb_priv;
12491
12492 if (!bnxt_tc_flower_enabled(bp) ||
12493 !tc_cls_can_offload_and_chain0(bp->dev, type_data))
12494 return -EOPNOTSUPP;
12495
12496 switch (type) {
12497 case TC_SETUP_CLSFLOWER:
12498 return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, type_data);
12499 default:
12500 return -EOPNOTSUPP;
12501 }
12502 }
12503
12504 LIST_HEAD(bnxt_block_cb_list);
12505
12506 static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type,
12507 void *type_data)
12508 {
12509 struct bnxt *bp = netdev_priv(dev);
12510
12511 switch (type) {
12512 case TC_SETUP_BLOCK:
12513 return flow_block_cb_setup_simple(type_data,
12514 &bnxt_block_cb_list,
12515 bnxt_setup_tc_block_cb,
12516 bp, bp, true);
12517 case TC_SETUP_QDISC_MQPRIO: {
12518 struct tc_mqprio_qopt *mqprio = type_data;
12519
12520 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
12521
12522 return bnxt_setup_mq_tc(dev, mqprio->num_tc);
12523 }
12524 default:
12525 return -EOPNOTSUPP;
12526 }
12527 }
12528
12529 #ifdef CONFIG_RFS_ACCEL
12530 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
12531 struct bnxt_ntuple_filter *f2)
12532 {
12533 struct flow_keys *keys1 = &f1->fkeys;
12534 struct flow_keys *keys2 = &f2->fkeys;
12535
12536 if (keys1->basic.n_proto != keys2->basic.n_proto ||
12537 keys1->basic.ip_proto != keys2->basic.ip_proto)
12538 return false;
12539
12540 if (keys1->basic.n_proto == htons(ETH_P_IP)) {
12541 if (keys1->addrs.v4addrs.src != keys2->addrs.v4addrs.src ||
12542 keys1->addrs.v4addrs.dst != keys2->addrs.v4addrs.dst)
12543 return false;
12544 } else {
12545 if (memcmp(&keys1->addrs.v6addrs.src, &keys2->addrs.v6addrs.src,
12546 sizeof(keys1->addrs.v6addrs.src)) ||
12547 memcmp(&keys1->addrs.v6addrs.dst, &keys2->addrs.v6addrs.dst,
12548 sizeof(keys1->addrs.v6addrs.dst)))
12549 return false;
12550 }
12551
12552 if (keys1->ports.ports == keys2->ports.ports &&
12553 keys1->control.flags == keys2->control.flags &&
12554 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) &&
12555 ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr))
12556 return true;
12557
12558 return false;
12559 }
12560
12561 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
12562 u16 rxq_index, u32 flow_id)
12563 {
12564 struct bnxt *bp = netdev_priv(dev);
12565 struct bnxt_ntuple_filter *fltr, *new_fltr;
12566 struct flow_keys *fkeys;
12567 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
12568 int rc = 0, idx, bit_id, l2_idx = 0;
12569 struct hlist_head *head;
12570 u32 flags;
12571
12572 if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) {
12573 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
12574 int off = 0, j;
12575
12576 netif_addr_lock_bh(dev);
12577 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) {
12578 if (ether_addr_equal(eth->h_dest,
12579 vnic->uc_list + off)) {
12580 l2_idx = j + 1;
12581 break;
12582 }
12583 }
12584 netif_addr_unlock_bh(dev);
12585 if (!l2_idx)
12586 return -EINVAL;
12587 }
12588 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
12589 if (!new_fltr)
12590 return -ENOMEM;
12591
12592 fkeys = &new_fltr->fkeys;
12593 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
12594 rc = -EPROTONOSUPPORT;
12595 goto err_free;
12596 }
12597
12598 if ((fkeys->basic.n_proto != htons(ETH_P_IP) &&
12599 fkeys->basic.n_proto != htons(ETH_P_IPV6)) ||
12600 ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
12601 (fkeys->basic.ip_proto != IPPROTO_UDP))) {
12602 rc = -EPROTONOSUPPORT;
12603 goto err_free;
12604 }
12605 if (fkeys->basic.n_proto == htons(ETH_P_IPV6) &&
12606 bp->hwrm_spec_code < 0x10601) {
12607 rc = -EPROTONOSUPPORT;
12608 goto err_free;
12609 }
12610 flags = fkeys->control.flags;
12611 if (((flags & FLOW_DIS_ENCAPSULATION) &&
12612 bp->hwrm_spec_code < 0x10601) || (flags & FLOW_DIS_IS_FRAGMENT)) {
12613 rc = -EPROTONOSUPPORT;
12614 goto err_free;
12615 }
12616
12617 memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN);
12618 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
12619
12620 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
12621 head = &bp->ntp_fltr_hash_tbl[idx];
12622 rcu_read_lock();
12623 hlist_for_each_entry_rcu(fltr, head, hash) {
12624 if (bnxt_fltr_match(fltr, new_fltr)) {
12625 rcu_read_unlock();
12626 rc = 0;
12627 goto err_free;
12628 }
12629 }
12630 rcu_read_unlock();
12631
12632 spin_lock_bh(&bp->ntp_fltr_lock);
12633 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
12634 BNXT_NTP_FLTR_MAX_FLTR, 0);
12635 if (bit_id < 0) {
12636 spin_unlock_bh(&bp->ntp_fltr_lock);
12637 rc = -ENOMEM;
12638 goto err_free;
12639 }
12640
12641 new_fltr->sw_id = (u16)bit_id;
12642 new_fltr->flow_id = flow_id;
12643 new_fltr->l2_fltr_idx = l2_idx;
12644 new_fltr->rxq = rxq_index;
12645 hlist_add_head_rcu(&new_fltr->hash, head);
12646 bp->ntp_fltr_count++;
12647 spin_unlock_bh(&bp->ntp_fltr_lock);
12648
12649 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
12650 bnxt_queue_sp_work(bp);
12651
12652 return new_fltr->sw_id;
12653
12654 err_free:
12655 kfree(new_fltr);
12656 return rc;
12657 }
12658
12659 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
12660 {
12661 int i;
12662
12663 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
12664 struct hlist_head *head;
12665 struct hlist_node *tmp;
12666 struct bnxt_ntuple_filter *fltr;
12667 int rc;
12668
12669 head = &bp->ntp_fltr_hash_tbl[i];
12670 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
12671 bool del = false;
12672
12673 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
12674 if (rps_may_expire_flow(bp->dev, fltr->rxq,
12675 fltr->flow_id,
12676 fltr->sw_id)) {
12677 bnxt_hwrm_cfa_ntuple_filter_free(bp,
12678 fltr);
12679 del = true;
12680 }
12681 } else {
12682 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
12683 fltr);
12684 if (rc)
12685 del = true;
12686 else
12687 set_bit(BNXT_FLTR_VALID, &fltr->state);
12688 }
12689
12690 if (del) {
12691 spin_lock_bh(&bp->ntp_fltr_lock);
12692 hlist_del_rcu(&fltr->hash);
12693 bp->ntp_fltr_count--;
12694 spin_unlock_bh(&bp->ntp_fltr_lock);
12695 synchronize_rcu();
12696 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
12697 kfree(fltr);
12698 }
12699 }
12700 }
12701 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
12702 netdev_info(bp->dev, "Receive PF driver unload event!\n");
12703 }
12704
12705 #else
12706
12707 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
12708 {
12709 }
12710
12711 #endif /* CONFIG_RFS_ACCEL */
12712
12713 static int bnxt_udp_tunnel_sync(struct net_device *netdev, unsigned int table)
12714 {
12715 struct bnxt *bp = netdev_priv(netdev);
12716 struct udp_tunnel_info ti;
12717 unsigned int cmd;
12718
12719 udp_tunnel_nic_get_port(netdev, table, 0, &ti);
12720 if (ti.type == UDP_TUNNEL_TYPE_VXLAN) {
12721 bp->vxlan_port = ti.port;
12722 cmd = TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN;
12723 } else {
12724 bp->nge_port = ti.port;
12725 cmd = TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE;
12726 }
12727
12728 if (ti.port)
12729 return bnxt_hwrm_tunnel_dst_port_alloc(bp, ti.port, cmd);
12730
12731 return bnxt_hwrm_tunnel_dst_port_free(bp, cmd);
12732 }
12733
12734 static const struct udp_tunnel_nic_info bnxt_udp_tunnels = {
12735 .sync_table = bnxt_udp_tunnel_sync,
12736 .flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP |
12737 UDP_TUNNEL_NIC_INFO_OPEN_ONLY,
12738 .tables = {
12739 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, },
12740 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_GENEVE, },
12741 },
12742 };
12743
12744 static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
12745 struct net_device *dev, u32 filter_mask,
12746 int nlflags)
12747 {
12748 struct bnxt *bp = netdev_priv(dev);
12749
12750 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0,
12751 nlflags, filter_mask, NULL);
12752 }
12753
12754 static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
12755 u16 flags, struct netlink_ext_ack *extack)
12756 {
12757 struct bnxt *bp = netdev_priv(dev);
12758 struct nlattr *attr, *br_spec;
12759 int rem, rc = 0;
12760
12761 if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp))
12762 return -EOPNOTSUPP;
12763
12764 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
12765 if (!br_spec)
12766 return -EINVAL;
12767
12768 nla_for_each_nested(attr, br_spec, rem) {
12769 u16 mode;
12770
12771 if (nla_type(attr) != IFLA_BRIDGE_MODE)
12772 continue;
12773
12774 if (nla_len(attr) < sizeof(mode))
12775 return -EINVAL;
12776
12777 mode = nla_get_u16(attr);
12778 if (mode == bp->br_mode)
12779 break;
12780
12781 rc = bnxt_hwrm_set_br_mode(bp, mode);
12782 if (!rc)
12783 bp->br_mode = mode;
12784 break;
12785 }
12786 return rc;
12787 }
12788
12789 int bnxt_get_port_parent_id(struct net_device *dev,
12790 struct netdev_phys_item_id *ppid)
12791 {
12792 struct bnxt *bp = netdev_priv(dev);
12793
12794 if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV)
12795 return -EOPNOTSUPP;
12796
12797 /* The PF and it's VF-reps only support the switchdev framework */
12798 if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_DSN_VALID))
12799 return -EOPNOTSUPP;
12800
12801 ppid->id_len = sizeof(bp->dsn);
12802 memcpy(ppid->id, bp->dsn, ppid->id_len);
12803
12804 return 0;
12805 }
12806
12807 static struct devlink_port *bnxt_get_devlink_port(struct net_device *dev)
12808 {
12809 struct bnxt *bp = netdev_priv(dev);
12810
12811 return &bp->dl_port;
12812 }
12813
12814 static const struct net_device_ops bnxt_netdev_ops = {
12815 .ndo_open = bnxt_open,
12816 .ndo_start_xmit = bnxt_start_xmit,
12817 .ndo_stop = bnxt_close,
12818 .ndo_get_stats64 = bnxt_get_stats64,
12819 .ndo_set_rx_mode = bnxt_set_rx_mode,
12820 .ndo_eth_ioctl = bnxt_ioctl,
12821 .ndo_validate_addr = eth_validate_addr,
12822 .ndo_set_mac_address = bnxt_change_mac_addr,
12823 .ndo_change_mtu = bnxt_change_mtu,
12824 .ndo_fix_features = bnxt_fix_features,
12825 .ndo_set_features = bnxt_set_features,
12826 .ndo_features_check = bnxt_features_check,
12827 .ndo_tx_timeout = bnxt_tx_timeout,
12828 #ifdef CONFIG_BNXT_SRIOV
12829 .ndo_get_vf_config = bnxt_get_vf_config,
12830 .ndo_set_vf_mac = bnxt_set_vf_mac,
12831 .ndo_set_vf_vlan = bnxt_set_vf_vlan,
12832 .ndo_set_vf_rate = bnxt_set_vf_bw,
12833 .ndo_set_vf_link_state = bnxt_set_vf_link_state,
12834 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk,
12835 .ndo_set_vf_trust = bnxt_set_vf_trust,
12836 #endif
12837 .ndo_setup_tc = bnxt_setup_tc,
12838 #ifdef CONFIG_RFS_ACCEL
12839 .ndo_rx_flow_steer = bnxt_rx_flow_steer,
12840 #endif
12841 .ndo_bpf = bnxt_xdp,
12842 .ndo_xdp_xmit = bnxt_xdp_xmit,
12843 .ndo_bridge_getlink = bnxt_bridge_getlink,
12844 .ndo_bridge_setlink = bnxt_bridge_setlink,
12845 .ndo_get_devlink_port = bnxt_get_devlink_port,
12846 };
12847
12848 static void bnxt_remove_one(struct pci_dev *pdev)
12849 {
12850 struct net_device *dev = pci_get_drvdata(pdev);
12851 struct bnxt *bp = netdev_priv(dev);
12852
12853 if (BNXT_PF(bp))
12854 bnxt_sriov_disable(bp);
12855
12856 if (BNXT_PF(bp))
12857 devlink_port_type_clear(&bp->dl_port);
12858
12859 bnxt_ptp_clear(bp);
12860 pci_disable_pcie_error_reporting(pdev);
12861 unregister_netdev(dev);
12862 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
12863 /* Flush any pending tasks */
12864 cancel_work_sync(&bp->sp_task);
12865 cancel_delayed_work_sync(&bp->fw_reset_task);
12866 bp->sp_event = 0;
12867
12868 bnxt_dl_fw_reporters_destroy(bp, true);
12869 bnxt_dl_unregister(bp);
12870 bnxt_shutdown_tc(bp);
12871
12872 bnxt_clear_int_mode(bp);
12873 bnxt_hwrm_func_drv_unrgtr(bp);
12874 bnxt_free_hwrm_resources(bp);
12875 bnxt_free_hwrm_short_cmd_req(bp);
12876 bnxt_ethtool_free(bp);
12877 bnxt_dcb_free(bp);
12878 kfree(bp->edev);
12879 bp->edev = NULL;
12880 kfree(bp->ptp_cfg);
12881 bp->ptp_cfg = NULL;
12882 kfree(bp->fw_health);
12883 bp->fw_health = NULL;
12884 bnxt_cleanup_pci(bp);
12885 bnxt_free_ctx_mem(bp);
12886 kfree(bp->ctx);
12887 bp->ctx = NULL;
12888 kfree(bp->rss_indir_tbl);
12889 bp->rss_indir_tbl = NULL;
12890 bnxt_free_port_stats(bp);
12891 free_netdev(dev);
12892 }
12893
12894 static int bnxt_probe_phy(struct bnxt *bp, bool fw_dflt)
12895 {
12896 int rc = 0;
12897 struct bnxt_link_info *link_info = &bp->link_info;
12898
12899 bp->phy_flags = 0;
12900 rc = bnxt_hwrm_phy_qcaps(bp);
12901 if (rc) {
12902 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
12903 rc);
12904 return rc;
12905 }
12906 if (bp->phy_flags & BNXT_PHY_FL_NO_FCS)
12907 bp->dev->priv_flags |= IFF_SUPP_NOFCS;
12908 else
12909 bp->dev->priv_flags &= ~IFF_SUPP_NOFCS;
12910 if (!fw_dflt)
12911 return 0;
12912
12913 rc = bnxt_update_link(bp, false);
12914 if (rc) {
12915 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
12916 rc);
12917 return rc;
12918 }
12919
12920 /* Older firmware does not have supported_auto_speeds, so assume
12921 * that all supported speeds can be autonegotiated.
12922 */
12923 if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
12924 link_info->support_auto_speeds = link_info->support_speeds;
12925
12926 bnxt_init_ethtool_link_settings(bp);
12927 return 0;
12928 }
12929
12930 static int bnxt_get_max_irq(struct pci_dev *pdev)
12931 {
12932 u16 ctrl;
12933
12934 if (!pdev->msix_cap)
12935 return 1;
12936
12937 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
12938 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
12939 }
12940
12941 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
12942 int *max_cp)
12943 {
12944 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
12945 int max_ring_grps = 0, max_irq;
12946
12947 *max_tx = hw_resc->max_tx_rings;
12948 *max_rx = hw_resc->max_rx_rings;
12949 *max_cp = bnxt_get_max_func_cp_rings_for_en(bp);
12950 max_irq = min_t(int, bnxt_get_max_func_irqs(bp) -
12951 bnxt_get_ulp_msix_num(bp),
12952 hw_resc->max_stat_ctxs - bnxt_get_ulp_stat_ctxs(bp));
12953 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
12954 *max_cp = min_t(int, *max_cp, max_irq);
12955 max_ring_grps = hw_resc->max_hw_ring_grps;
12956 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) {
12957 *max_cp -= 1;
12958 *max_rx -= 2;
12959 }
12960 if (bp->flags & BNXT_FLAG_AGG_RINGS)
12961 *max_rx >>= 1;
12962 if (bp->flags & BNXT_FLAG_CHIP_P5) {
12963 bnxt_trim_rings(bp, max_rx, max_tx, *max_cp, false);
12964 /* On P5 chips, max_cp output param should be available NQs */
12965 *max_cp = max_irq;
12966 }
12967 *max_rx = min_t(int, *max_rx, max_ring_grps);
12968 }
12969
12970 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
12971 {
12972 int rx, tx, cp;
12973
12974 _bnxt_get_max_rings(bp, &rx, &tx, &cp);
12975 *max_rx = rx;
12976 *max_tx = tx;
12977 if (!rx || !tx || !cp)
12978 return -ENOMEM;
12979
12980 return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
12981 }
12982
12983 static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx,
12984 bool shared)
12985 {
12986 int rc;
12987
12988 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
12989 if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) {
12990 /* Not enough rings, try disabling agg rings. */
12991 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
12992 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
12993 if (rc) {
12994 /* set BNXT_FLAG_AGG_RINGS back for consistency */
12995 bp->flags |= BNXT_FLAG_AGG_RINGS;
12996 return rc;
12997 }
12998 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
12999 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
13000 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
13001 bnxt_set_ring_params(bp);
13002 }
13003
13004 if (bp->flags & BNXT_FLAG_ROCE_CAP) {
13005 int max_cp, max_stat, max_irq;
13006
13007 /* Reserve minimum resources for RoCE */
13008 max_cp = bnxt_get_max_func_cp_rings(bp);
13009 max_stat = bnxt_get_max_func_stat_ctxs(bp);
13010 max_irq = bnxt_get_max_func_irqs(bp);
13011 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS ||
13012 max_irq <= BNXT_MIN_ROCE_CP_RINGS ||
13013 max_stat <= BNXT_MIN_ROCE_STAT_CTXS)
13014 return 0;
13015
13016 max_cp -= BNXT_MIN_ROCE_CP_RINGS;
13017 max_irq -= BNXT_MIN_ROCE_CP_RINGS;
13018 max_stat -= BNXT_MIN_ROCE_STAT_CTXS;
13019 max_cp = min_t(int, max_cp, max_irq);
13020 max_cp = min_t(int, max_cp, max_stat);
13021 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared);
13022 if (rc)
13023 rc = 0;
13024 }
13025 return rc;
13026 }
13027
13028 /* In initial default shared ring setting, each shared ring must have a
13029 * RX/TX ring pair.
13030 */
13031 static void bnxt_trim_dflt_sh_rings(struct bnxt *bp)
13032 {
13033 bp->cp_nr_rings = min_t(int, bp->tx_nr_rings_per_tc, bp->rx_nr_rings);
13034 bp->rx_nr_rings = bp->cp_nr_rings;
13035 bp->tx_nr_rings_per_tc = bp->cp_nr_rings;
13036 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
13037 }
13038
13039 static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh)
13040 {
13041 int dflt_rings, max_rx_rings, max_tx_rings, rc;
13042
13043 if (!bnxt_can_reserve_rings(bp))
13044 return 0;
13045
13046 if (sh)
13047 bp->flags |= BNXT_FLAG_SHARED_RINGS;
13048 dflt_rings = is_kdump_kernel() ? 1 : netif_get_num_default_rss_queues();
13049 /* Reduce default rings on multi-port cards so that total default
13050 * rings do not exceed CPU count.
13051 */
13052 if (bp->port_count > 1) {
13053 int max_rings =
13054 max_t(int, num_online_cpus() / bp->port_count, 1);
13055
13056 dflt_rings = min_t(int, dflt_rings, max_rings);
13057 }
13058 rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh);
13059 if (rc)
13060 return rc;
13061 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
13062 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
13063 if (sh)
13064 bnxt_trim_dflt_sh_rings(bp);
13065 else
13066 bp->cp_nr_rings = bp->tx_nr_rings_per_tc + bp->rx_nr_rings;
13067 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
13068
13069 rc = __bnxt_reserve_rings(bp);
13070 if (rc)
13071 netdev_warn(bp->dev, "Unable to reserve tx rings\n");
13072 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
13073 if (sh)
13074 bnxt_trim_dflt_sh_rings(bp);
13075
13076 /* Rings may have been trimmed, re-reserve the trimmed rings. */
13077 if (bnxt_need_reserve_rings(bp)) {
13078 rc = __bnxt_reserve_rings(bp);
13079 if (rc)
13080 netdev_warn(bp->dev, "2nd rings reservation failed.\n");
13081 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
13082 }
13083 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
13084 bp->rx_nr_rings++;
13085 bp->cp_nr_rings++;
13086 }
13087 if (rc) {
13088 bp->tx_nr_rings = 0;
13089 bp->rx_nr_rings = 0;
13090 }
13091 return rc;
13092 }
13093
13094 static int bnxt_init_dflt_ring_mode(struct bnxt *bp)
13095 {
13096 int rc;
13097
13098 if (bp->tx_nr_rings)
13099 return 0;
13100
13101 bnxt_ulp_irq_stop(bp);
13102 bnxt_clear_int_mode(bp);
13103 rc = bnxt_set_dflt_rings(bp, true);
13104 if (rc) {
13105 netdev_err(bp->dev, "Not enough rings available.\n");
13106 goto init_dflt_ring_err;
13107 }
13108 rc = bnxt_init_int_mode(bp);
13109 if (rc)
13110 goto init_dflt_ring_err;
13111
13112 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
13113 if (bnxt_rfs_supported(bp) && bnxt_rfs_capable(bp)) {
13114 bp->flags |= BNXT_FLAG_RFS;
13115 bp->dev->features |= NETIF_F_NTUPLE;
13116 }
13117 init_dflt_ring_err:
13118 bnxt_ulp_irq_restart(bp, rc);
13119 return rc;
13120 }
13121
13122 int bnxt_restore_pf_fw_resources(struct bnxt *bp)
13123 {
13124 int rc;
13125
13126 ASSERT_RTNL();
13127 bnxt_hwrm_func_qcaps(bp);
13128
13129 if (netif_running(bp->dev))
13130 __bnxt_close_nic(bp, true, false);
13131
13132 bnxt_ulp_irq_stop(bp);
13133 bnxt_clear_int_mode(bp);
13134 rc = bnxt_init_int_mode(bp);
13135 bnxt_ulp_irq_restart(bp, rc);
13136
13137 if (netif_running(bp->dev)) {
13138 if (rc)
13139 dev_close(bp->dev);
13140 else
13141 rc = bnxt_open_nic(bp, true, false);
13142 }
13143
13144 return rc;
13145 }
13146
13147 static int bnxt_init_mac_addr(struct bnxt *bp)
13148 {
13149 int rc = 0;
13150
13151 if (BNXT_PF(bp)) {
13152 memcpy(bp->dev->dev_addr, bp->pf.mac_addr, ETH_ALEN);
13153 } else {
13154 #ifdef CONFIG_BNXT_SRIOV
13155 struct bnxt_vf_info *vf = &bp->vf;
13156 bool strict_approval = true;
13157
13158 if (is_valid_ether_addr(vf->mac_addr)) {
13159 /* overwrite netdev dev_addr with admin VF MAC */
13160 memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
13161 /* Older PF driver or firmware may not approve this
13162 * correctly.
13163 */
13164 strict_approval = false;
13165 } else {
13166 eth_hw_addr_random(bp->dev);
13167 }
13168 rc = bnxt_approve_mac(bp, bp->dev->dev_addr, strict_approval);
13169 #endif
13170 }
13171 return rc;
13172 }
13173
13174 #define BNXT_VPD_LEN 512
13175 static void bnxt_vpd_read_info(struct bnxt *bp)
13176 {
13177 struct pci_dev *pdev = bp->pdev;
13178 int i, len, pos, ro_size, size;
13179 ssize_t vpd_size;
13180 u8 *vpd_data;
13181
13182 vpd_data = kmalloc(BNXT_VPD_LEN, GFP_KERNEL);
13183 if (!vpd_data)
13184 return;
13185
13186 vpd_size = pci_read_vpd(pdev, 0, BNXT_VPD_LEN, vpd_data);
13187 if (vpd_size <= 0) {
13188 netdev_err(bp->dev, "Unable to read VPD\n");
13189 goto exit;
13190 }
13191
13192 i = pci_vpd_find_tag(vpd_data, vpd_size, PCI_VPD_LRDT_RO_DATA);
13193 if (i < 0) {
13194 netdev_err(bp->dev, "VPD READ-Only not found\n");
13195 goto exit;
13196 }
13197
13198 ro_size = pci_vpd_lrdt_size(&vpd_data[i]);
13199 i += PCI_VPD_LRDT_TAG_SIZE;
13200 if (i + ro_size > vpd_size)
13201 goto exit;
13202
13203 pos = pci_vpd_find_info_keyword(vpd_data, i, ro_size,
13204 PCI_VPD_RO_KEYWORD_PARTNO);
13205 if (pos < 0)
13206 goto read_sn;
13207
13208 len = pci_vpd_info_field_size(&vpd_data[pos]);
13209 pos += PCI_VPD_INFO_FLD_HDR_SIZE;
13210 if (len + pos > vpd_size)
13211 goto read_sn;
13212
13213 size = min(len, BNXT_VPD_FLD_LEN - 1);
13214 memcpy(bp->board_partno, &vpd_data[pos], size);
13215
13216 read_sn:
13217 pos = pci_vpd_find_info_keyword(vpd_data, i, ro_size,
13218 PCI_VPD_RO_KEYWORD_SERIALNO);
13219 if (pos < 0)
13220 goto exit;
13221
13222 len = pci_vpd_info_field_size(&vpd_data[pos]);
13223 pos += PCI_VPD_INFO_FLD_HDR_SIZE;
13224 if (len + pos > vpd_size)
13225 goto exit;
13226
13227 size = min(len, BNXT_VPD_FLD_LEN - 1);
13228 memcpy(bp->board_serialno, &vpd_data[pos], size);
13229 exit:
13230 kfree(vpd_data);
13231 }
13232
13233 static int bnxt_pcie_dsn_get(struct bnxt *bp, u8 dsn[])
13234 {
13235 struct pci_dev *pdev = bp->pdev;
13236 u64 qword;
13237
13238 qword = pci_get_dsn(pdev);
13239 if (!qword) {
13240 netdev_info(bp->dev, "Unable to read adapter's DSN\n");
13241 return -EOPNOTSUPP;
13242 }
13243
13244 put_unaligned_le64(qword, dsn);
13245
13246 bp->flags |= BNXT_FLAG_DSN_VALID;
13247 return 0;
13248 }
13249
13250 static int bnxt_map_db_bar(struct bnxt *bp)
13251 {
13252 if (!bp->db_size)
13253 return -ENODEV;
13254 bp->bar1 = pci_iomap(bp->pdev, 2, bp->db_size);
13255 if (!bp->bar1)
13256 return -ENOMEM;
13257 return 0;
13258 }
13259
13260 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
13261 {
13262 struct net_device *dev;
13263 struct bnxt *bp;
13264 int rc, max_irqs;
13265
13266 if (pci_is_bridge(pdev))
13267 return -ENODEV;
13268
13269 /* Clear any pending DMA transactions from crash kernel
13270 * while loading driver in capture kernel.
13271 */
13272 if (is_kdump_kernel()) {
13273 pci_clear_master(pdev);
13274 pcie_flr(pdev);
13275 }
13276
13277 max_irqs = bnxt_get_max_irq(pdev);
13278 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
13279 if (!dev)
13280 return -ENOMEM;
13281
13282 bp = netdev_priv(dev);
13283 bp->msg_enable = BNXT_DEF_MSG_ENABLE;
13284 bnxt_set_max_func_irqs(bp, max_irqs);
13285
13286 if (bnxt_vf_pciid(ent->driver_data))
13287 bp->flags |= BNXT_FLAG_VF;
13288
13289 if (pdev->msix_cap)
13290 bp->flags |= BNXT_FLAG_MSIX_CAP;
13291
13292 rc = bnxt_init_board(pdev, dev);
13293 if (rc < 0)
13294 goto init_err_free;
13295
13296 dev->netdev_ops = &bnxt_netdev_ops;
13297 dev->watchdog_timeo = BNXT_TX_TIMEOUT;
13298 dev->ethtool_ops = &bnxt_ethtool_ops;
13299 pci_set_drvdata(pdev, dev);
13300
13301 rc = bnxt_alloc_hwrm_resources(bp);
13302 if (rc)
13303 goto init_err_pci_clean;
13304
13305 mutex_init(&bp->hwrm_cmd_lock);
13306 mutex_init(&bp->link_lock);
13307
13308 rc = bnxt_fw_init_one_p1(bp);
13309 if (rc)
13310 goto init_err_pci_clean;
13311
13312 if (BNXT_PF(bp))
13313 bnxt_vpd_read_info(bp);
13314
13315 if (BNXT_CHIP_P5(bp)) {
13316 bp->flags |= BNXT_FLAG_CHIP_P5;
13317 if (BNXT_CHIP_SR2(bp))
13318 bp->flags |= BNXT_FLAG_CHIP_SR2;
13319 }
13320
13321 rc = bnxt_alloc_rss_indir_tbl(bp);
13322 if (rc)
13323 goto init_err_pci_clean;
13324
13325 rc = bnxt_fw_init_one_p2(bp);
13326 if (rc)
13327 goto init_err_pci_clean;
13328
13329 rc = bnxt_map_db_bar(bp);
13330 if (rc) {
13331 dev_err(&pdev->dev, "Cannot map doorbell BAR rc = %d, aborting\n",
13332 rc);
13333 goto init_err_pci_clean;
13334 }
13335
13336 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
13337 NETIF_F_TSO | NETIF_F_TSO6 |
13338 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
13339 NETIF_F_GSO_IPXIP4 |
13340 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
13341 NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
13342 NETIF_F_RXCSUM | NETIF_F_GRO;
13343
13344 if (BNXT_SUPPORTS_TPA(bp))
13345 dev->hw_features |= NETIF_F_LRO;
13346
13347 dev->hw_enc_features =
13348 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
13349 NETIF_F_TSO | NETIF_F_TSO6 |
13350 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
13351 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
13352 NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;
13353 dev->udp_tunnel_nic_info = &bnxt_udp_tunnels;
13354
13355 dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
13356 NETIF_F_GSO_GRE_CSUM;
13357 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
13358 if (bp->fw_cap & BNXT_FW_CAP_VLAN_RX_STRIP)
13359 dev->hw_features |= BNXT_HW_FEATURE_VLAN_ALL_RX;
13360 if (bp->fw_cap & BNXT_FW_CAP_VLAN_TX_INSERT)
13361 dev->hw_features |= BNXT_HW_FEATURE_VLAN_ALL_TX;
13362 if (BNXT_SUPPORTS_TPA(bp))
13363 dev->hw_features |= NETIF_F_GRO_HW;
13364 dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
13365 if (dev->features & NETIF_F_GRO_HW)
13366 dev->features &= ~NETIF_F_LRO;
13367 dev->priv_flags |= IFF_UNICAST_FLT;
13368
13369 #ifdef CONFIG_BNXT_SRIOV
13370 init_waitqueue_head(&bp->sriov_cfg_wait);
13371 mutex_init(&bp->sriov_lock);
13372 #endif
13373 if (BNXT_SUPPORTS_TPA(bp)) {
13374 bp->gro_func = bnxt_gro_func_5730x;
13375 if (BNXT_CHIP_P4(bp))
13376 bp->gro_func = bnxt_gro_func_5731x;
13377 else if (BNXT_CHIP_P5(bp))
13378 bp->gro_func = bnxt_gro_func_5750x;
13379 }
13380 if (!BNXT_CHIP_P4_PLUS(bp))
13381 bp->flags |= BNXT_FLAG_DOUBLE_DB;
13382
13383 rc = bnxt_init_mac_addr(bp);
13384 if (rc) {
13385 dev_err(&pdev->dev, "Unable to initialize mac address.\n");
13386 rc = -EADDRNOTAVAIL;
13387 goto init_err_pci_clean;
13388 }
13389
13390 if (BNXT_PF(bp)) {
13391 /* Read the adapter's DSN to use as the eswitch switch_id */
13392 rc = bnxt_pcie_dsn_get(bp, bp->dsn);
13393 }
13394
13395 /* MTU range: 60 - FW defined max */
13396 dev->min_mtu = ETH_ZLEN;
13397 dev->max_mtu = bp->max_mtu;
13398
13399 rc = bnxt_probe_phy(bp, true);
13400 if (rc)
13401 goto init_err_pci_clean;
13402
13403 bnxt_set_rx_skb_mode(bp, false);
13404 bnxt_set_tpa_flags(bp);
13405 bnxt_set_ring_params(bp);
13406 rc = bnxt_set_dflt_rings(bp, true);
13407 if (rc) {
13408 netdev_err(bp->dev, "Not enough rings available.\n");
13409 rc = -ENOMEM;
13410 goto init_err_pci_clean;
13411 }
13412
13413 bnxt_fw_init_one_p3(bp);
13414
13415 if (dev->hw_features & BNXT_HW_FEATURE_VLAN_ALL_RX)
13416 bp->flags |= BNXT_FLAG_STRIP_VLAN;
13417
13418 rc = bnxt_init_int_mode(bp);
13419 if (rc)
13420 goto init_err_pci_clean;
13421
13422 /* No TC has been set yet and rings may have been trimmed due to
13423 * limited MSIX, so we re-initialize the TX rings per TC.
13424 */
13425 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
13426
13427 if (BNXT_PF(bp)) {
13428 if (!bnxt_pf_wq) {
13429 bnxt_pf_wq =
13430 create_singlethread_workqueue("bnxt_pf_wq");
13431 if (!bnxt_pf_wq) {
13432 dev_err(&pdev->dev, "Unable to create workqueue.\n");
13433 rc = -ENOMEM;
13434 goto init_err_pci_clean;
13435 }
13436 }
13437 rc = bnxt_init_tc(bp);
13438 if (rc)
13439 netdev_err(dev, "Failed to initialize TC flower offload, err = %d.\n",
13440 rc);
13441 }
13442
13443 bnxt_inv_fw_health_reg(bp);
13444 bnxt_dl_register(bp);
13445
13446 rc = register_netdev(dev);
13447 if (rc)
13448 goto init_err_cleanup;
13449
13450 if (BNXT_PF(bp))
13451 devlink_port_type_eth_set(&bp->dl_port, bp->dev);
13452 bnxt_dl_fw_reporters_create(bp);
13453
13454 netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
13455 board_info[ent->driver_data].name,
13456 (long)pci_resource_start(pdev, 0), dev->dev_addr);
13457 pcie_print_link_status(pdev);
13458
13459 pci_save_state(pdev);
13460 return 0;
13461
13462 init_err_cleanup:
13463 bnxt_dl_unregister(bp);
13464 bnxt_shutdown_tc(bp);
13465 bnxt_clear_int_mode(bp);
13466
13467 init_err_pci_clean:
13468 bnxt_hwrm_func_drv_unrgtr(bp);
13469 bnxt_free_hwrm_short_cmd_req(bp);
13470 bnxt_free_hwrm_resources(bp);
13471 bnxt_ethtool_free(bp);
13472 bnxt_ptp_clear(bp);
13473 kfree(bp->ptp_cfg);
13474 bp->ptp_cfg = NULL;
13475 kfree(bp->fw_health);
13476 bp->fw_health = NULL;
13477 bnxt_cleanup_pci(bp);
13478 bnxt_free_ctx_mem(bp);
13479 kfree(bp->ctx);
13480 bp->ctx = NULL;
13481 kfree(bp->rss_indir_tbl);
13482 bp->rss_indir_tbl = NULL;
13483
13484 init_err_free:
13485 free_netdev(dev);
13486 return rc;
13487 }
13488
13489 static void bnxt_shutdown(struct pci_dev *pdev)
13490 {
13491 struct net_device *dev = pci_get_drvdata(pdev);
13492 struct bnxt *bp;
13493
13494 if (!dev)
13495 return;
13496
13497 rtnl_lock();
13498 bp = netdev_priv(dev);
13499 if (!bp)
13500 goto shutdown_exit;
13501
13502 if (netif_running(dev))
13503 dev_close(dev);
13504
13505 bnxt_ulp_shutdown(bp);
13506 bnxt_clear_int_mode(bp);
13507 pci_disable_device(pdev);
13508
13509 if (system_state == SYSTEM_POWER_OFF) {
13510 pci_wake_from_d3(pdev, bp->wol);
13511 pci_set_power_state(pdev, PCI_D3hot);
13512 }
13513
13514 shutdown_exit:
13515 rtnl_unlock();
13516 }
13517
13518 #ifdef CONFIG_PM_SLEEP
13519 static int bnxt_suspend(struct device *device)
13520 {
13521 struct net_device *dev = dev_get_drvdata(device);
13522 struct bnxt *bp = netdev_priv(dev);
13523 int rc = 0;
13524
13525 rtnl_lock();
13526 bnxt_ulp_stop(bp);
13527 if (netif_running(dev)) {
13528 netif_device_detach(dev);
13529 rc = bnxt_close(dev);
13530 }
13531 bnxt_hwrm_func_drv_unrgtr(bp);
13532 pci_disable_device(bp->pdev);
13533 bnxt_free_ctx_mem(bp);
13534 kfree(bp->ctx);
13535 bp->ctx = NULL;
13536 rtnl_unlock();
13537 return rc;
13538 }
13539
13540 static int bnxt_resume(struct device *device)
13541 {
13542 struct net_device *dev = dev_get_drvdata(device);
13543 struct bnxt *bp = netdev_priv(dev);
13544 int rc = 0;
13545
13546 rtnl_lock();
13547 rc = pci_enable_device(bp->pdev);
13548 if (rc) {
13549 netdev_err(dev, "Cannot re-enable PCI device during resume, err = %d\n",
13550 rc);
13551 goto resume_exit;
13552 }
13553 pci_set_master(bp->pdev);
13554 if (bnxt_hwrm_ver_get(bp)) {
13555 rc = -ENODEV;
13556 goto resume_exit;
13557 }
13558 rc = bnxt_hwrm_func_reset(bp);
13559 if (rc) {
13560 rc = -EBUSY;
13561 goto resume_exit;
13562 }
13563
13564 rc = bnxt_hwrm_func_qcaps(bp);
13565 if (rc)
13566 goto resume_exit;
13567
13568 if (bnxt_hwrm_func_drv_rgtr(bp, NULL, 0, false)) {
13569 rc = -ENODEV;
13570 goto resume_exit;
13571 }
13572
13573 bnxt_get_wol_settings(bp);
13574 if (netif_running(dev)) {
13575 rc = bnxt_open(dev);
13576 if (!rc)
13577 netif_device_attach(dev);
13578 }
13579
13580 resume_exit:
13581 bnxt_ulp_start(bp, rc);
13582 if (!rc)
13583 bnxt_reenable_sriov(bp);
13584 rtnl_unlock();
13585 return rc;
13586 }
13587
13588 static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume);
13589 #define BNXT_PM_OPS (&bnxt_pm_ops)
13590
13591 #else
13592
13593 #define BNXT_PM_OPS NULL
13594
13595 #endif /* CONFIG_PM_SLEEP */
13596
13597 /**
13598 * bnxt_io_error_detected - called when PCI error is detected
13599 * @pdev: Pointer to PCI device
13600 * @state: The current pci connection state
13601 *
13602 * This function is called after a PCI bus error affecting
13603 * this device has been detected.
13604 */
13605 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
13606 pci_channel_state_t state)
13607 {
13608 struct net_device *netdev = pci_get_drvdata(pdev);
13609 struct bnxt *bp = netdev_priv(netdev);
13610
13611 netdev_info(netdev, "PCI I/O error detected\n");
13612
13613 rtnl_lock();
13614 netif_device_detach(netdev);
13615
13616 bnxt_ulp_stop(bp);
13617
13618 if (state == pci_channel_io_perm_failure) {
13619 rtnl_unlock();
13620 return PCI_ERS_RESULT_DISCONNECT;
13621 }
13622
13623 if (state == pci_channel_io_frozen)
13624 set_bit(BNXT_STATE_PCI_CHANNEL_IO_FROZEN, &bp->state);
13625
13626 if (netif_running(netdev))
13627 bnxt_close(netdev);
13628
13629 if (pci_is_enabled(pdev))
13630 pci_disable_device(pdev);
13631 bnxt_free_ctx_mem(bp);
13632 kfree(bp->ctx);
13633 bp->ctx = NULL;
13634 rtnl_unlock();
13635
13636 /* Request a slot slot reset. */
13637 return PCI_ERS_RESULT_NEED_RESET;
13638 }
13639
13640 /**
13641 * bnxt_io_slot_reset - called after the pci bus has been reset.
13642 * @pdev: Pointer to PCI device
13643 *
13644 * Restart the card from scratch, as if from a cold-boot.
13645 * At this point, the card has exprienced a hard reset,
13646 * followed by fixups by BIOS, and has its config space
13647 * set up identically to what it was at cold boot.
13648 */
13649 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
13650 {
13651 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
13652 struct net_device *netdev = pci_get_drvdata(pdev);
13653 struct bnxt *bp = netdev_priv(netdev);
13654 int err = 0, off;
13655
13656 netdev_info(bp->dev, "PCI Slot Reset\n");
13657
13658 rtnl_lock();
13659
13660 if (pci_enable_device(pdev)) {
13661 dev_err(&pdev->dev,
13662 "Cannot re-enable PCI device after reset.\n");
13663 } else {
13664 pci_set_master(pdev);
13665 /* Upon fatal error, our device internal logic that latches to
13666 * BAR value is getting reset and will restore only upon
13667 * rewritting the BARs.
13668 *
13669 * As pci_restore_state() does not re-write the BARs if the
13670 * value is same as saved value earlier, driver needs to
13671 * write the BARs to 0 to force restore, in case of fatal error.
13672 */
13673 if (test_and_clear_bit(BNXT_STATE_PCI_CHANNEL_IO_FROZEN,
13674 &bp->state)) {
13675 for (off = PCI_BASE_ADDRESS_0;
13676 off <= PCI_BASE_ADDRESS_5; off += 4)
13677 pci_write_config_dword(bp->pdev, off, 0);
13678 }
13679 pci_restore_state(pdev);
13680 pci_save_state(pdev);
13681
13682 err = bnxt_hwrm_func_reset(bp);
13683 if (!err)
13684 result = PCI_ERS_RESULT_RECOVERED;
13685 }
13686
13687 rtnl_unlock();
13688
13689 return result;
13690 }
13691
13692 /**
13693 * bnxt_io_resume - called when traffic can start flowing again.
13694 * @pdev: Pointer to PCI device
13695 *
13696 * This callback is called when the error recovery driver tells
13697 * us that its OK to resume normal operation.
13698 */
13699 static void bnxt_io_resume(struct pci_dev *pdev)
13700 {
13701 struct net_device *netdev = pci_get_drvdata(pdev);
13702 struct bnxt *bp = netdev_priv(netdev);
13703 int err;
13704
13705 netdev_info(bp->dev, "PCI Slot Resume\n");
13706 rtnl_lock();
13707
13708 err = bnxt_hwrm_func_qcaps(bp);
13709 if (!err && netif_running(netdev))
13710 err = bnxt_open(netdev);
13711
13712 bnxt_ulp_start(bp, err);
13713 if (!err) {
13714 bnxt_reenable_sriov(bp);
13715 netif_device_attach(netdev);
13716 }
13717
13718 rtnl_unlock();
13719 }
13720
13721 static const struct pci_error_handlers bnxt_err_handler = {
13722 .error_detected = bnxt_io_error_detected,
13723 .slot_reset = bnxt_io_slot_reset,
13724 .resume = bnxt_io_resume
13725 };
13726
13727 static struct pci_driver bnxt_pci_driver = {
13728 .name = DRV_MODULE_NAME,
13729 .id_table = bnxt_pci_tbl,
13730 .probe = bnxt_init_one,
13731 .remove = bnxt_remove_one,
13732 .shutdown = bnxt_shutdown,
13733 .driver.pm = BNXT_PM_OPS,
13734 .err_handler = &bnxt_err_handler,
13735 #if defined(CONFIG_BNXT_SRIOV)
13736 .sriov_configure = bnxt_sriov_configure,
13737 #endif
13738 };
13739
13740 static int __init bnxt_init(void)
13741 {
13742 bnxt_debug_init();
13743 return pci_register_driver(&bnxt_pci_driver);
13744 }
13745
13746 static void __exit bnxt_exit(void)
13747 {
13748 pci_unregister_driver(&bnxt_pci_driver);
13749 if (bnxt_pf_wq)
13750 destroy_workqueue(bnxt_pf_wq);
13751 bnxt_debug_exit();
13752 }
13753
13754 module_init(bnxt_init);
13755 module_exit(bnxt_exit);
Ubuntu Jammy Linux kernel mirror