1 /* Broadcom NetXtreme-C/E network driver.
3 * Copyright (c) 2014-2015 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
10 #include <linux/module.h>
12 #include <linux/stringify.h>
13 #include <linux/kernel.h>
14 #include <linux/timer.h>
15 #include <linux/errno.h>
16 #include <linux/ioport.h>
17 #include <linux/slab.h>
18 #include <linux/vmalloc.h>
19 #include <linux/interrupt.h>
20 #include <linux/pci.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23 #include <linux/skbuff.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/bitops.h>
27 #include <linux/irq.h>
28 #include <linux/delay.h>
29 #include <asm/byteorder.h>
31 #include <linux/time.h>
32 #include <linux/mii.h>
34 #include <linux/if_vlan.h>
38 #include <net/checksum.h>
39 #include <net/ip6_checksum.h>
40 #if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE)
41 #include <net/vxlan.h>
43 #ifdef CONFIG_NET_RX_BUSY_POLL
44 #include <net/busy_poll.h>
46 #include <linux/workqueue.h>
47 #include <linux/prefetch.h>
48 #include <linux/cache.h>
49 #include <linux/log2.h>
50 #include <linux/aer.h>
51 #include <linux/bitmap.h>
52 #include <linux/cpu_rmap.h>
56 #include "bnxt_sriov.h"
57 #include "bnxt_ethtool.h"
59 #define BNXT_TX_TIMEOUT (5 * HZ)
61 static const char version
[] =
62 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME
" v" DRV_MODULE_VERSION
"\n";
64 MODULE_LICENSE("GPL");
65 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
66 MODULE_VERSION(DRV_MODULE_VERSION
);
68 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
69 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
70 #define BNXT_RX_COPY_THRESH 256
72 #define BNXT_TX_PUSH_THRESH 164
85 /* indexed by enum above */
89 { "Broadcom BCM57301 NetXtreme-C Single-port 10Gb Ethernet" },
90 { "Broadcom BCM57302 NetXtreme-C Dual-port 10Gb/25Gb Ethernet" },
91 { "Broadcom BCM57304 NetXtreme-C Dual-port 10Gb/25Gb/40Gb/50Gb Ethernet" },
92 { "Broadcom BCM57402 NetXtreme-E Dual-port 10Gb Ethernet" },
93 { "Broadcom BCM57404 NetXtreme-E Dual-port 10Gb/25Gb Ethernet" },
94 { "Broadcom BCM57406 NetXtreme-E Dual-port 10GBase-T Ethernet" },
95 { "Broadcom BCM57304 NetXtreme-C Ethernet Virtual Function" },
96 { "Broadcom BCM57404 NetXtreme-E Ethernet Virtual Function" },
99 static const struct pci_device_id bnxt_pci_tbl
[] = {
100 { PCI_VDEVICE(BROADCOM
, 0x16c8), .driver_data
= BCM57301
},
101 { PCI_VDEVICE(BROADCOM
, 0x16c9), .driver_data
= BCM57302
},
102 { PCI_VDEVICE(BROADCOM
, 0x16ca), .driver_data
= BCM57304
},
103 { PCI_VDEVICE(BROADCOM
, 0x16d0), .driver_data
= BCM57402
},
104 { PCI_VDEVICE(BROADCOM
, 0x16d1), .driver_data
= BCM57404
},
105 { PCI_VDEVICE(BROADCOM
, 0x16d2), .driver_data
= BCM57406
},
106 #ifdef CONFIG_BNXT_SRIOV
107 { PCI_VDEVICE(BROADCOM
, 0x16cb), .driver_data
= BCM57304_VF
},
108 { PCI_VDEVICE(BROADCOM
, 0x16d3), .driver_data
= BCM57404_VF
},
113 MODULE_DEVICE_TABLE(pci
, bnxt_pci_tbl
);
115 static const u16 bnxt_vf_req_snif
[] = {
118 HWRM_CFA_L2_FILTER_ALLOC
,
121 static bool bnxt_vf_pciid(enum board_idx idx
)
123 return (idx
== BCM57304_VF
|| idx
== BCM57404_VF
);
126 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
127 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
128 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
130 #define BNXT_CP_DB_REARM(db, raw_cons) \
131 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
133 #define BNXT_CP_DB(db, raw_cons) \
134 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
136 #define BNXT_CP_DB_IRQ_DIS(db) \
137 writel(DB_CP_IRQ_DIS_FLAGS, db)
139 static inline u32
bnxt_tx_avail(struct bnxt
*bp
, struct bnxt_tx_ring_info
*txr
)
141 /* Tell compiler to fetch tx indices from memory. */
144 return bp
->tx_ring_size
-
145 ((txr
->tx_prod
- txr
->tx_cons
) & bp
->tx_ring_mask
);
148 static const u16 bnxt_lhint_arr
[] = {
149 TX_BD_FLAGS_LHINT_512_AND_SMALLER
,
150 TX_BD_FLAGS_LHINT_512_TO_1023
,
151 TX_BD_FLAGS_LHINT_1024_TO_2047
,
152 TX_BD_FLAGS_LHINT_1024_TO_2047
,
153 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
154 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
155 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
156 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
157 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
158 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
159 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
160 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
161 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
162 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
163 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
164 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
165 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
166 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
167 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
170 static netdev_tx_t
bnxt_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
172 struct bnxt
*bp
= netdev_priv(dev
);
174 struct tx_bd_ext
*txbd1
;
175 struct netdev_queue
*txq
;
178 unsigned int length
, pad
= 0;
179 u32 len
, free_size
, vlan_tag_flags
, cfa_action
, flags
;
181 struct pci_dev
*pdev
= bp
->pdev
;
182 struct bnxt_tx_ring_info
*txr
;
183 struct bnxt_sw_tx_bd
*tx_buf
;
185 i
= skb_get_queue_mapping(skb
);
186 if (unlikely(i
>= bp
->tx_nr_rings
)) {
187 dev_kfree_skb_any(skb
);
191 txr
= &bp
->tx_ring
[i
];
192 txq
= netdev_get_tx_queue(dev
, i
);
195 free_size
= bnxt_tx_avail(bp
, txr
);
196 if (unlikely(free_size
< skb_shinfo(skb
)->nr_frags
+ 2)) {
197 netif_tx_stop_queue(txq
);
198 return NETDEV_TX_BUSY
;
202 len
= skb_headlen(skb
);
203 last_frag
= skb_shinfo(skb
)->nr_frags
;
205 txbd
= &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
207 txbd
->tx_bd_opaque
= prod
;
209 tx_buf
= &txr
->tx_buf_ring
[prod
];
211 tx_buf
->nr_frags
= last_frag
;
215 if (skb_vlan_tag_present(skb
)) {
216 vlan_tag_flags
= TX_BD_CFA_META_KEY_VLAN
|
217 skb_vlan_tag_get(skb
);
218 /* Currently supports 8021Q, 8021AD vlan offloads
219 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
221 if (skb
->vlan_proto
== htons(ETH_P_8021Q
))
222 vlan_tag_flags
|= 1 << TX_BD_CFA_META_TPID_SHIFT
;
225 if (free_size
== bp
->tx_ring_size
&& length
<= bp
->tx_push_thresh
) {
226 struct tx_push_buffer
*tx_push_buf
= txr
->tx_push
;
227 struct tx_push_bd
*tx_push
= &tx_push_buf
->push_bd
;
228 struct tx_bd_ext
*tx_push1
= &tx_push
->txbd2
;
229 void *pdata
= tx_push_buf
->data
;
233 /* Set COAL_NOW to be ready quickly for the next push */
234 tx_push
->tx_bd_len_flags_type
=
235 cpu_to_le32((length
<< TX_BD_LEN_SHIFT
) |
236 TX_BD_TYPE_LONG_TX_BD
|
237 TX_BD_FLAGS_LHINT_512_AND_SMALLER
|
238 TX_BD_FLAGS_COAL_NOW
|
239 TX_BD_FLAGS_PACKET_END
|
240 (2 << TX_BD_FLAGS_BD_CNT_SHIFT
));
242 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
243 tx_push1
->tx_bd_hsize_lflags
=
244 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM
);
246 tx_push1
->tx_bd_hsize_lflags
= 0;
248 tx_push1
->tx_bd_cfa_meta
= cpu_to_le32(vlan_tag_flags
);
249 tx_push1
->tx_bd_cfa_action
= cpu_to_le32(cfa_action
);
251 end
= pdata
+ length
;
252 end
= PTR_ALIGN(end
, 8) - 1;
255 skb_copy_from_linear_data(skb
, pdata
, len
);
257 for (j
= 0; j
< last_frag
; j
++) {
258 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[j
];
261 fptr
= skb_frag_address_safe(frag
);
265 memcpy(pdata
, fptr
, skb_frag_size(frag
));
266 pdata
+= skb_frag_size(frag
);
269 txbd
->tx_bd_len_flags_type
= tx_push
->tx_bd_len_flags_type
;
270 txbd
->tx_bd_haddr
= txr
->data_mapping
;
271 prod
= NEXT_TX(prod
);
272 txbd
= &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
273 memcpy(txbd
, tx_push1
, sizeof(*txbd
));
274 prod
= NEXT_TX(prod
);
276 cpu_to_le32(DB_KEY_TX_PUSH
| DB_LONG_TX_PUSH
| prod
);
279 netdev_tx_sent_queue(txq
, skb
->len
);
281 push_len
= (length
+ sizeof(*tx_push
) + 7) / 8;
283 __iowrite64_copy(txr
->tx_doorbell
, tx_push_buf
, 16);
284 __iowrite64_copy(txr
->tx_doorbell
+ 4, tx_push_buf
+ 1,
287 __iowrite64_copy(txr
->tx_doorbell
, tx_push_buf
,
296 if (length
< BNXT_MIN_PKT_SIZE
) {
297 pad
= BNXT_MIN_PKT_SIZE
- length
;
298 if (skb_pad(skb
, pad
)) {
299 /* SKB already freed. */
303 length
= BNXT_MIN_PKT_SIZE
;
306 mapping
= dma_map_single(&pdev
->dev
, skb
->data
, len
, DMA_TO_DEVICE
);
308 if (unlikely(dma_mapping_error(&pdev
->dev
, mapping
))) {
309 dev_kfree_skb_any(skb
);
314 dma_unmap_addr_set(tx_buf
, mapping
, mapping
);
315 flags
= (len
<< TX_BD_LEN_SHIFT
) | TX_BD_TYPE_LONG_TX_BD
|
316 ((last_frag
+ 2) << TX_BD_FLAGS_BD_CNT_SHIFT
);
318 txbd
->tx_bd_haddr
= cpu_to_le64(mapping
);
320 prod
= NEXT_TX(prod
);
321 txbd1
= (struct tx_bd_ext
*)
322 &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
324 txbd1
->tx_bd_hsize_lflags
= 0;
325 if (skb_is_gso(skb
)) {
328 if (skb
->encapsulation
)
329 hdr_len
= skb_inner_network_offset(skb
) +
330 skb_inner_network_header_len(skb
) +
331 inner_tcp_hdrlen(skb
);
333 hdr_len
= skb_transport_offset(skb
) +
336 txbd1
->tx_bd_hsize_lflags
= cpu_to_le32(TX_BD_FLAGS_LSO
|
338 (hdr_len
<< (TX_BD_HSIZE_SHIFT
- 1)));
339 length
= skb_shinfo(skb
)->gso_size
;
340 txbd1
->tx_bd_mss
= cpu_to_le32(length
);
342 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
343 txbd1
->tx_bd_hsize_lflags
=
344 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM
);
345 txbd1
->tx_bd_mss
= 0;
349 flags
|= bnxt_lhint_arr
[length
];
350 txbd
->tx_bd_len_flags_type
= cpu_to_le32(flags
);
352 txbd1
->tx_bd_cfa_meta
= cpu_to_le32(vlan_tag_flags
);
353 txbd1
->tx_bd_cfa_action
= cpu_to_le32(cfa_action
);
354 for (i
= 0; i
< last_frag
; i
++) {
355 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
357 prod
= NEXT_TX(prod
);
358 txbd
= &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
360 len
= skb_frag_size(frag
);
361 mapping
= skb_frag_dma_map(&pdev
->dev
, frag
, 0, len
,
364 if (unlikely(dma_mapping_error(&pdev
->dev
, mapping
)))
367 tx_buf
= &txr
->tx_buf_ring
[prod
];
368 dma_unmap_addr_set(tx_buf
, mapping
, mapping
);
370 txbd
->tx_bd_haddr
= cpu_to_le64(mapping
);
372 flags
= len
<< TX_BD_LEN_SHIFT
;
373 txbd
->tx_bd_len_flags_type
= cpu_to_le32(flags
);
377 txbd
->tx_bd_len_flags_type
=
378 cpu_to_le32(((len
+ pad
) << TX_BD_LEN_SHIFT
) | flags
|
379 TX_BD_FLAGS_PACKET_END
);
381 netdev_tx_sent_queue(txq
, skb
->len
);
383 /* Sync BD data before updating doorbell */
386 prod
= NEXT_TX(prod
);
389 writel(DB_KEY_TX
| prod
, txr
->tx_doorbell
);
390 writel(DB_KEY_TX
| prod
, txr
->tx_doorbell
);
396 if (unlikely(bnxt_tx_avail(bp
, txr
) <= MAX_SKB_FRAGS
+ 1)) {
397 netif_tx_stop_queue(txq
);
399 /* netif_tx_stop_queue() must be done before checking
400 * tx index in bnxt_tx_avail() below, because in
401 * bnxt_tx_int(), we update tx index before checking for
402 * netif_tx_queue_stopped().
405 if (bnxt_tx_avail(bp
, txr
) > bp
->tx_wake_thresh
)
406 netif_tx_wake_queue(txq
);
413 /* start back at beginning and unmap skb */
415 tx_buf
= &txr
->tx_buf_ring
[prod
];
417 dma_unmap_single(&pdev
->dev
, dma_unmap_addr(tx_buf
, mapping
),
418 skb_headlen(skb
), PCI_DMA_TODEVICE
);
419 prod
= NEXT_TX(prod
);
421 /* unmap remaining mapped pages */
422 for (i
= 0; i
< last_frag
; i
++) {
423 prod
= NEXT_TX(prod
);
424 tx_buf
= &txr
->tx_buf_ring
[prod
];
425 dma_unmap_page(&pdev
->dev
, dma_unmap_addr(tx_buf
, mapping
),
426 skb_frag_size(&skb_shinfo(skb
)->frags
[i
]),
430 dev_kfree_skb_any(skb
);
434 static void bnxt_tx_int(struct bnxt
*bp
, struct bnxt_napi
*bnapi
, int nr_pkts
)
436 struct bnxt_tx_ring_info
*txr
= bnapi
->tx_ring
;
437 int index
= txr
- &bp
->tx_ring
[0];
438 struct netdev_queue
*txq
= netdev_get_tx_queue(bp
->dev
, index
);
439 u16 cons
= txr
->tx_cons
;
440 struct pci_dev
*pdev
= bp
->pdev
;
442 unsigned int tx_bytes
= 0;
444 for (i
= 0; i
< nr_pkts
; i
++) {
445 struct bnxt_sw_tx_bd
*tx_buf
;
449 tx_buf
= &txr
->tx_buf_ring
[cons
];
450 cons
= NEXT_TX(cons
);
454 if (tx_buf
->is_push
) {
459 dma_unmap_single(&pdev
->dev
, dma_unmap_addr(tx_buf
, mapping
),
460 skb_headlen(skb
), PCI_DMA_TODEVICE
);
461 last
= tx_buf
->nr_frags
;
463 for (j
= 0; j
< last
; j
++) {
464 cons
= NEXT_TX(cons
);
465 tx_buf
= &txr
->tx_buf_ring
[cons
];
468 dma_unmap_addr(tx_buf
, mapping
),
469 skb_frag_size(&skb_shinfo(skb
)->frags
[j
]),
474 cons
= NEXT_TX(cons
);
476 tx_bytes
+= skb
->len
;
477 dev_kfree_skb_any(skb
);
480 netdev_tx_completed_queue(txq
, nr_pkts
, tx_bytes
);
483 /* Need to make the tx_cons update visible to bnxt_start_xmit()
484 * before checking for netif_tx_queue_stopped(). Without the
485 * memory barrier, there is a small possibility that bnxt_start_xmit()
486 * will miss it and cause the queue to be stopped forever.
490 if (unlikely(netif_tx_queue_stopped(txq
)) &&
491 (bnxt_tx_avail(bp
, txr
) > bp
->tx_wake_thresh
)) {
492 __netif_tx_lock(txq
, smp_processor_id());
493 if (netif_tx_queue_stopped(txq
) &&
494 bnxt_tx_avail(bp
, txr
) > bp
->tx_wake_thresh
&&
495 txr
->dev_state
!= BNXT_DEV_STATE_CLOSING
)
496 netif_tx_wake_queue(txq
);
497 __netif_tx_unlock(txq
);
501 static inline u8
*__bnxt_alloc_rx_data(struct bnxt
*bp
, dma_addr_t
*mapping
,
505 struct pci_dev
*pdev
= bp
->pdev
;
507 data
= kmalloc(bp
->rx_buf_size
, gfp
);
511 *mapping
= dma_map_single(&pdev
->dev
, data
+ BNXT_RX_DMA_OFFSET
,
512 bp
->rx_buf_use_size
, PCI_DMA_FROMDEVICE
);
514 if (dma_mapping_error(&pdev
->dev
, *mapping
)) {
521 static inline int bnxt_alloc_rx_data(struct bnxt
*bp
,
522 struct bnxt_rx_ring_info
*rxr
,
525 struct rx_bd
*rxbd
= &rxr
->rx_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
526 struct bnxt_sw_rx_bd
*rx_buf
= &rxr
->rx_buf_ring
[prod
];
530 data
= __bnxt_alloc_rx_data(bp
, &mapping
, gfp
);
535 dma_unmap_addr_set(rx_buf
, mapping
, mapping
);
537 rxbd
->rx_bd_haddr
= cpu_to_le64(mapping
);
542 static void bnxt_reuse_rx_data(struct bnxt_rx_ring_info
*rxr
, u16 cons
,
545 u16 prod
= rxr
->rx_prod
;
546 struct bnxt_sw_rx_bd
*cons_rx_buf
, *prod_rx_buf
;
547 struct rx_bd
*cons_bd
, *prod_bd
;
549 prod_rx_buf
= &rxr
->rx_buf_ring
[prod
];
550 cons_rx_buf
= &rxr
->rx_buf_ring
[cons
];
552 prod_rx_buf
->data
= data
;
554 dma_unmap_addr_set(prod_rx_buf
, mapping
,
555 dma_unmap_addr(cons_rx_buf
, mapping
));
557 prod_bd
= &rxr
->rx_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
558 cons_bd
= &rxr
->rx_desc_ring
[RX_RING(cons
)][RX_IDX(cons
)];
560 prod_bd
->rx_bd_haddr
= cons_bd
->rx_bd_haddr
;
563 static inline u16
bnxt_find_next_agg_idx(struct bnxt_rx_ring_info
*rxr
, u16 idx
)
565 u16 next
, max
= rxr
->rx_agg_bmap_size
;
567 next
= find_next_zero_bit(rxr
->rx_agg_bmap
, max
, idx
);
569 next
= find_first_zero_bit(rxr
->rx_agg_bmap
, max
);
573 static inline int bnxt_alloc_rx_page(struct bnxt
*bp
,
574 struct bnxt_rx_ring_info
*rxr
,
578 &rxr
->rx_agg_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
579 struct bnxt_sw_rx_agg_bd
*rx_agg_buf
;
580 struct pci_dev
*pdev
= bp
->pdev
;
583 u16 sw_prod
= rxr
->rx_sw_agg_prod
;
584 unsigned int offset
= 0;
586 if (PAGE_SIZE
> BNXT_RX_PAGE_SIZE
) {
589 page
= alloc_page(gfp
);
593 rxr
->rx_page_offset
= 0;
595 offset
= rxr
->rx_page_offset
;
596 rxr
->rx_page_offset
+= BNXT_RX_PAGE_SIZE
;
597 if (rxr
->rx_page_offset
== PAGE_SIZE
)
602 page
= alloc_page(gfp
);
607 mapping
= dma_map_page(&pdev
->dev
, page
, offset
, BNXT_RX_PAGE_SIZE
,
609 if (dma_mapping_error(&pdev
->dev
, mapping
)) {
614 if (unlikely(test_bit(sw_prod
, rxr
->rx_agg_bmap
)))
615 sw_prod
= bnxt_find_next_agg_idx(rxr
, sw_prod
);
617 __set_bit(sw_prod
, rxr
->rx_agg_bmap
);
618 rx_agg_buf
= &rxr
->rx_agg_ring
[sw_prod
];
619 rxr
->rx_sw_agg_prod
= NEXT_RX_AGG(sw_prod
);
621 rx_agg_buf
->page
= page
;
622 rx_agg_buf
->offset
= offset
;
623 rx_agg_buf
->mapping
= mapping
;
624 rxbd
->rx_bd_haddr
= cpu_to_le64(mapping
);
625 rxbd
->rx_bd_opaque
= sw_prod
;
629 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi
*bnapi
, u16 cp_cons
,
632 struct bnxt
*bp
= bnapi
->bp
;
633 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
634 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
635 u16 prod
= rxr
->rx_agg_prod
;
636 u16 sw_prod
= rxr
->rx_sw_agg_prod
;
639 for (i
= 0; i
< agg_bufs
; i
++) {
641 struct rx_agg_cmp
*agg
;
642 struct bnxt_sw_rx_agg_bd
*cons_rx_buf
, *prod_rx_buf
;
643 struct rx_bd
*prod_bd
;
646 agg
= (struct rx_agg_cmp
*)
647 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
648 cons
= agg
->rx_agg_cmp_opaque
;
649 __clear_bit(cons
, rxr
->rx_agg_bmap
);
651 if (unlikely(test_bit(sw_prod
, rxr
->rx_agg_bmap
)))
652 sw_prod
= bnxt_find_next_agg_idx(rxr
, sw_prod
);
654 __set_bit(sw_prod
, rxr
->rx_agg_bmap
);
655 prod_rx_buf
= &rxr
->rx_agg_ring
[sw_prod
];
656 cons_rx_buf
= &rxr
->rx_agg_ring
[cons
];
658 /* It is possible for sw_prod to be equal to cons, so
659 * set cons_rx_buf->page to NULL first.
661 page
= cons_rx_buf
->page
;
662 cons_rx_buf
->page
= NULL
;
663 prod_rx_buf
->page
= page
;
664 prod_rx_buf
->offset
= cons_rx_buf
->offset
;
666 prod_rx_buf
->mapping
= cons_rx_buf
->mapping
;
668 prod_bd
= &rxr
->rx_agg_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
670 prod_bd
->rx_bd_haddr
= cpu_to_le64(cons_rx_buf
->mapping
);
671 prod_bd
->rx_bd_opaque
= sw_prod
;
673 prod
= NEXT_RX_AGG(prod
);
674 sw_prod
= NEXT_RX_AGG(sw_prod
);
675 cp_cons
= NEXT_CMP(cp_cons
);
677 rxr
->rx_agg_prod
= prod
;
678 rxr
->rx_sw_agg_prod
= sw_prod
;
681 static struct sk_buff
*bnxt_rx_skb(struct bnxt
*bp
,
682 struct bnxt_rx_ring_info
*rxr
, u16 cons
,
683 u16 prod
, u8
*data
, dma_addr_t dma_addr
,
689 err
= bnxt_alloc_rx_data(bp
, rxr
, prod
, GFP_ATOMIC
);
691 bnxt_reuse_rx_data(rxr
, cons
, data
);
695 skb
= build_skb(data
, 0);
696 dma_unmap_single(&bp
->pdev
->dev
, dma_addr
, bp
->rx_buf_use_size
,
703 skb_reserve(skb
, BNXT_RX_OFFSET
);
708 static struct sk_buff
*bnxt_rx_pages(struct bnxt
*bp
, struct bnxt_napi
*bnapi
,
709 struct sk_buff
*skb
, u16 cp_cons
,
712 struct pci_dev
*pdev
= bp
->pdev
;
713 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
714 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
715 u16 prod
= rxr
->rx_agg_prod
;
718 for (i
= 0; i
< agg_bufs
; i
++) {
720 struct rx_agg_cmp
*agg
;
721 struct bnxt_sw_rx_agg_bd
*cons_rx_buf
;
725 agg
= (struct rx_agg_cmp
*)
726 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
727 cons
= agg
->rx_agg_cmp_opaque
;
728 frag_len
= (le32_to_cpu(agg
->rx_agg_cmp_len_flags_type
) &
729 RX_AGG_CMP_LEN
) >> RX_AGG_CMP_LEN_SHIFT
;
731 cons_rx_buf
= &rxr
->rx_agg_ring
[cons
];
732 skb_fill_page_desc(skb
, i
, cons_rx_buf
->page
,
733 cons_rx_buf
->offset
, frag_len
);
734 __clear_bit(cons
, rxr
->rx_agg_bmap
);
736 /* It is possible for bnxt_alloc_rx_page() to allocate
737 * a sw_prod index that equals the cons index, so we
738 * need to clear the cons entry now.
740 mapping
= dma_unmap_addr(cons_rx_buf
, mapping
);
741 page
= cons_rx_buf
->page
;
742 cons_rx_buf
->page
= NULL
;
744 if (bnxt_alloc_rx_page(bp
, rxr
, prod
, GFP_ATOMIC
) != 0) {
745 struct skb_shared_info
*shinfo
;
746 unsigned int nr_frags
;
748 shinfo
= skb_shinfo(skb
);
749 nr_frags
= --shinfo
->nr_frags
;
750 __skb_frag_set_page(&shinfo
->frags
[nr_frags
], NULL
);
754 cons_rx_buf
->page
= page
;
756 /* Update prod since possibly some pages have been
759 rxr
->rx_agg_prod
= prod
;
760 bnxt_reuse_rx_agg_bufs(bnapi
, cp_cons
, agg_bufs
- i
);
764 dma_unmap_page(&pdev
->dev
, mapping
, BNXT_RX_PAGE_SIZE
,
767 skb
->data_len
+= frag_len
;
768 skb
->len
+= frag_len
;
769 skb
->truesize
+= PAGE_SIZE
;
771 prod
= NEXT_RX_AGG(prod
);
772 cp_cons
= NEXT_CMP(cp_cons
);
774 rxr
->rx_agg_prod
= prod
;
778 static int bnxt_agg_bufs_valid(struct bnxt
*bp
, struct bnxt_cp_ring_info
*cpr
,
779 u8 agg_bufs
, u32
*raw_cons
)
782 struct rx_agg_cmp
*agg
;
784 *raw_cons
= ADV_RAW_CMP(*raw_cons
, agg_bufs
);
785 last
= RING_CMP(*raw_cons
);
786 agg
= (struct rx_agg_cmp
*)
787 &cpr
->cp_desc_ring
[CP_RING(last
)][CP_IDX(last
)];
788 return RX_AGG_CMP_VALID(agg
, *raw_cons
);
791 static inline struct sk_buff
*bnxt_copy_skb(struct bnxt_napi
*bnapi
, u8
*data
,
795 struct bnxt
*bp
= bnapi
->bp
;
796 struct pci_dev
*pdev
= bp
->pdev
;
799 skb
= napi_alloc_skb(&bnapi
->napi
, len
);
803 dma_sync_single_for_cpu(&pdev
->dev
, mapping
,
804 bp
->rx_copy_thresh
, PCI_DMA_FROMDEVICE
);
806 memcpy(skb
->data
- BNXT_RX_OFFSET
, data
, len
+ BNXT_RX_OFFSET
);
808 dma_sync_single_for_device(&pdev
->dev
, mapping
,
816 static void bnxt_tpa_start(struct bnxt
*bp
, struct bnxt_rx_ring_info
*rxr
,
817 struct rx_tpa_start_cmp
*tpa_start
,
818 struct rx_tpa_start_cmp_ext
*tpa_start1
)
820 u8 agg_id
= TPA_START_AGG_ID(tpa_start
);
822 struct bnxt_tpa_info
*tpa_info
;
823 struct bnxt_sw_rx_bd
*cons_rx_buf
, *prod_rx_buf
;
824 struct rx_bd
*prod_bd
;
827 cons
= tpa_start
->rx_tpa_start_cmp_opaque
;
829 cons_rx_buf
= &rxr
->rx_buf_ring
[cons
];
830 prod_rx_buf
= &rxr
->rx_buf_ring
[prod
];
831 tpa_info
= &rxr
->rx_tpa
[agg_id
];
833 prod_rx_buf
->data
= tpa_info
->data
;
835 mapping
= tpa_info
->mapping
;
836 dma_unmap_addr_set(prod_rx_buf
, mapping
, mapping
);
838 prod_bd
= &rxr
->rx_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
840 prod_bd
->rx_bd_haddr
= cpu_to_le64(mapping
);
842 tpa_info
->data
= cons_rx_buf
->data
;
843 cons_rx_buf
->data
= NULL
;
844 tpa_info
->mapping
= dma_unmap_addr(cons_rx_buf
, mapping
);
847 le32_to_cpu(tpa_start
->rx_tpa_start_cmp_len_flags_type
) >>
848 RX_TPA_START_CMP_LEN_SHIFT
;
849 if (likely(TPA_START_HASH_VALID(tpa_start
))) {
850 u32 hash_type
= TPA_START_HASH_TYPE(tpa_start
);
852 tpa_info
->hash_type
= PKT_HASH_TYPE_L4
;
853 tpa_info
->gso_type
= SKB_GSO_TCPV4
;
854 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
856 tpa_info
->gso_type
= SKB_GSO_TCPV6
;
858 le32_to_cpu(tpa_start
->rx_tpa_start_cmp_rss_hash
);
860 tpa_info
->hash_type
= PKT_HASH_TYPE_NONE
;
861 tpa_info
->gso_type
= 0;
862 if (netif_msg_rx_err(bp
))
863 netdev_warn(bp
->dev
, "TPA packet without valid hash\n");
865 tpa_info
->flags2
= le32_to_cpu(tpa_start1
->rx_tpa_start_cmp_flags2
);
866 tpa_info
->metadata
= le32_to_cpu(tpa_start1
->rx_tpa_start_cmp_metadata
);
868 rxr
->rx_prod
= NEXT_RX(prod
);
869 cons
= NEXT_RX(cons
);
870 cons_rx_buf
= &rxr
->rx_buf_ring
[cons
];
872 bnxt_reuse_rx_data(rxr
, cons
, cons_rx_buf
->data
);
873 rxr
->rx_prod
= NEXT_RX(rxr
->rx_prod
);
874 cons_rx_buf
->data
= NULL
;
877 static void bnxt_abort_tpa(struct bnxt
*bp
, struct bnxt_napi
*bnapi
,
878 u16 cp_cons
, u32 agg_bufs
)
881 bnxt_reuse_rx_agg_bufs(bnapi
, cp_cons
, agg_bufs
);
884 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
885 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
887 static inline struct sk_buff
*bnxt_gro_skb(struct bnxt_tpa_info
*tpa_info
,
888 struct rx_tpa_end_cmp
*tpa_end
,
889 struct rx_tpa_end_cmp_ext
*tpa_end1
,
894 int payload_off
, tcp_opt_len
= 0;
898 segs
= TPA_END_TPA_SEGS(tpa_end
);
902 NAPI_GRO_CB(skb
)->count
= segs
;
903 skb_shinfo(skb
)->gso_size
=
904 le32_to_cpu(tpa_end1
->rx_tpa_end_cmp_seg_len
);
905 skb_shinfo(skb
)->gso_type
= tpa_info
->gso_type
;
906 payload_off
= (le32_to_cpu(tpa_end
->rx_tpa_end_cmp_misc_v1
) &
907 RX_TPA_END_CMP_PAYLOAD_OFFSET
) >>
908 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT
;
909 if (TPA_END_GRO_TS(tpa_end
))
912 if (tpa_info
->gso_type
== SKB_GSO_TCPV4
) {
915 nw_off
= payload_off
- BNXT_IPV4_HDR_SIZE
- tcp_opt_len
-
917 skb_set_network_header(skb
, nw_off
);
919 skb_set_transport_header(skb
, nw_off
+ sizeof(struct iphdr
));
920 len
= skb
->len
- skb_transport_offset(skb
);
922 th
->check
= ~tcp_v4_check(len
, iph
->saddr
, iph
->daddr
, 0);
923 } else if (tpa_info
->gso_type
== SKB_GSO_TCPV6
) {
926 nw_off
= payload_off
- BNXT_IPV6_HDR_SIZE
- tcp_opt_len
-
928 skb_set_network_header(skb
, nw_off
);
930 skb_set_transport_header(skb
, nw_off
+ sizeof(struct ipv6hdr
));
931 len
= skb
->len
- skb_transport_offset(skb
);
933 th
->check
= ~tcp_v6_check(len
, &iph
->saddr
, &iph
->daddr
, 0);
935 dev_kfree_skb_any(skb
);
938 tcp_gro_complete(skb
);
940 if (nw_off
) { /* tunnel */
941 struct udphdr
*uh
= NULL
;
943 if (skb
->protocol
== htons(ETH_P_IP
)) {
944 struct iphdr
*iph
= (struct iphdr
*)skb
->data
;
946 if (iph
->protocol
== IPPROTO_UDP
)
947 uh
= (struct udphdr
*)(iph
+ 1);
949 struct ipv6hdr
*iph
= (struct ipv6hdr
*)skb
->data
;
951 if (iph
->nexthdr
== IPPROTO_UDP
)
952 uh
= (struct udphdr
*)(iph
+ 1);
956 skb_shinfo(skb
)->gso_type
|=
957 SKB_GSO_UDP_TUNNEL_CSUM
;
959 skb_shinfo(skb
)->gso_type
|= SKB_GSO_UDP_TUNNEL
;
966 static inline struct sk_buff
*bnxt_tpa_end(struct bnxt
*bp
,
967 struct bnxt_napi
*bnapi
,
969 struct rx_tpa_end_cmp
*tpa_end
,
970 struct rx_tpa_end_cmp_ext
*tpa_end1
,
973 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
974 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
975 u8 agg_id
= TPA_END_AGG_ID(tpa_end
);
977 u16 cp_cons
= RING_CMP(*raw_cons
);
979 struct bnxt_tpa_info
*tpa_info
;
983 tpa_info
= &rxr
->rx_tpa
[agg_id
];
984 data
= tpa_info
->data
;
987 mapping
= tpa_info
->mapping
;
989 agg_bufs
= (le32_to_cpu(tpa_end
->rx_tpa_end_cmp_misc_v1
) &
990 RX_TPA_END_CMP_AGG_BUFS
) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT
;
993 if (!bnxt_agg_bufs_valid(bp
, cpr
, agg_bufs
, raw_cons
))
994 return ERR_PTR(-EBUSY
);
997 cp_cons
= NEXT_CMP(cp_cons
);
1000 if (unlikely(agg_bufs
> MAX_SKB_FRAGS
)) {
1001 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
1002 netdev_warn(bp
->dev
, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1003 agg_bufs
, (int)MAX_SKB_FRAGS
);
1007 if (len
<= bp
->rx_copy_thresh
) {
1008 skb
= bnxt_copy_skb(bnapi
, data
, len
, mapping
);
1010 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
1015 dma_addr_t new_mapping
;
1017 new_data
= __bnxt_alloc_rx_data(bp
, &new_mapping
, GFP_ATOMIC
);
1019 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
1023 tpa_info
->data
= new_data
;
1024 tpa_info
->mapping
= new_mapping
;
1026 skb
= build_skb(data
, 0);
1027 dma_unmap_single(&bp
->pdev
->dev
, mapping
, bp
->rx_buf_use_size
,
1028 PCI_DMA_FROMDEVICE
);
1032 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
1035 skb_reserve(skb
, BNXT_RX_OFFSET
);
1040 skb
= bnxt_rx_pages(bp
, bnapi
, skb
, cp_cons
, agg_bufs
);
1042 /* Page reuse already handled by bnxt_rx_pages(). */
1046 skb
->protocol
= eth_type_trans(skb
, bp
->dev
);
1048 if (tpa_info
->hash_type
!= PKT_HASH_TYPE_NONE
)
1049 skb_set_hash(skb
, tpa_info
->rss_hash
, tpa_info
->hash_type
);
1051 if (tpa_info
->flags2
& RX_CMP_FLAGS2_META_FORMAT_VLAN
) {
1052 netdev_features_t features
= skb
->dev
->features
;
1053 u16 vlan_proto
= tpa_info
->metadata
>>
1054 RX_CMP_FLAGS2_METADATA_TPID_SFT
;
1056 if (((features
& NETIF_F_HW_VLAN_CTAG_RX
) &&
1057 vlan_proto
== ETH_P_8021Q
) ||
1058 ((features
& NETIF_F_HW_VLAN_STAG_RX
) &&
1059 vlan_proto
== ETH_P_8021AD
)) {
1060 __vlan_hwaccel_put_tag(skb
, htons(vlan_proto
),
1061 tpa_info
->metadata
&
1062 RX_CMP_FLAGS2_METADATA_VID_MASK
);
1066 skb_checksum_none_assert(skb
);
1067 if (likely(tpa_info
->flags2
& RX_TPA_START_CMP_FLAGS2_L4_CS_CALC
)) {
1068 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1070 (tpa_info
->flags2
& RX_CMP_FLAGS2_T_L4_CS_CALC
) >> 3;
1073 if (TPA_END_GRO(tpa_end
))
1074 skb
= bnxt_gro_skb(tpa_info
, tpa_end
, tpa_end1
, skb
);
1079 /* returns the following:
1080 * 1 - 1 packet successfully received
1081 * 0 - successful TPA_START, packet not completed yet
1082 * -EBUSY - completion ring does not have all the agg buffers yet
1083 * -ENOMEM - packet aborted due to out of memory
1084 * -EIO - packet aborted due to hw error indicated in BD
1086 static int bnxt_rx_pkt(struct bnxt
*bp
, struct bnxt_napi
*bnapi
, u32
*raw_cons
,
1089 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1090 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
1091 struct net_device
*dev
= bp
->dev
;
1092 struct rx_cmp
*rxcmp
;
1093 struct rx_cmp_ext
*rxcmp1
;
1094 u32 tmp_raw_cons
= *raw_cons
;
1095 u16 cons
, prod
, cp_cons
= RING_CMP(tmp_raw_cons
);
1096 struct bnxt_sw_rx_bd
*rx_buf
;
1098 u8
*data
, agg_bufs
, cmp_type
;
1099 dma_addr_t dma_addr
;
1100 struct sk_buff
*skb
;
1103 rxcmp
= (struct rx_cmp
*)
1104 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
1106 tmp_raw_cons
= NEXT_RAW_CMP(tmp_raw_cons
);
1107 cp_cons
= RING_CMP(tmp_raw_cons
);
1108 rxcmp1
= (struct rx_cmp_ext
*)
1109 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
1111 if (!RX_CMP_VALID(rxcmp1
, tmp_raw_cons
))
1114 cmp_type
= RX_CMP_TYPE(rxcmp
);
1116 prod
= rxr
->rx_prod
;
1118 if (cmp_type
== CMP_TYPE_RX_L2_TPA_START_CMP
) {
1119 bnxt_tpa_start(bp
, rxr
, (struct rx_tpa_start_cmp
*)rxcmp
,
1120 (struct rx_tpa_start_cmp_ext
*)rxcmp1
);
1122 goto next_rx_no_prod
;
1124 } else if (cmp_type
== CMP_TYPE_RX_L2_TPA_END_CMP
) {
1125 skb
= bnxt_tpa_end(bp
, bnapi
, &tmp_raw_cons
,
1126 (struct rx_tpa_end_cmp
*)rxcmp
,
1127 (struct rx_tpa_end_cmp_ext
*)rxcmp1
,
1130 if (unlikely(IS_ERR(skb
)))
1135 skb_record_rx_queue(skb
, bnapi
->index
);
1136 skb_mark_napi_id(skb
, &bnapi
->napi
);
1137 if (bnxt_busy_polling(bnapi
))
1138 netif_receive_skb(skb
);
1140 napi_gro_receive(&bnapi
->napi
, skb
);
1143 goto next_rx_no_prod
;
1146 cons
= rxcmp
->rx_cmp_opaque
;
1147 rx_buf
= &rxr
->rx_buf_ring
[cons
];
1148 data
= rx_buf
->data
;
1151 agg_bufs
= (le32_to_cpu(rxcmp
->rx_cmp_misc_v1
) & RX_CMP_AGG_BUFS
) >>
1152 RX_CMP_AGG_BUFS_SHIFT
;
1155 if (!bnxt_agg_bufs_valid(bp
, cpr
, agg_bufs
, &tmp_raw_cons
))
1158 cp_cons
= NEXT_CMP(cp_cons
);
1162 rx_buf
->data
= NULL
;
1163 if (rxcmp1
->rx_cmp_cfa_code_errors_v2
& RX_CMP_L2_ERRORS
) {
1164 bnxt_reuse_rx_data(rxr
, cons
, data
);
1166 bnxt_reuse_rx_agg_bufs(bnapi
, cp_cons
, agg_bufs
);
1172 len
= le32_to_cpu(rxcmp
->rx_cmp_len_flags_type
) >> RX_CMP_LEN_SHIFT
;
1173 dma_addr
= dma_unmap_addr(rx_buf
, mapping
);
1175 if (len
<= bp
->rx_copy_thresh
) {
1176 skb
= bnxt_copy_skb(bnapi
, data
, len
, dma_addr
);
1177 bnxt_reuse_rx_data(rxr
, cons
, data
);
1183 skb
= bnxt_rx_skb(bp
, rxr
, cons
, prod
, data
, dma_addr
, len
);
1191 skb
= bnxt_rx_pages(bp
, bnapi
, skb
, cp_cons
, agg_bufs
);
1198 if (RX_CMP_HASH_VALID(rxcmp
)) {
1199 u32 hash_type
= RX_CMP_HASH_TYPE(rxcmp
);
1200 enum pkt_hash_types type
= PKT_HASH_TYPE_L4
;
1202 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1203 if (hash_type
!= 1 && hash_type
!= 3)
1204 type
= PKT_HASH_TYPE_L3
;
1205 skb_set_hash(skb
, le32_to_cpu(rxcmp
->rx_cmp_rss_hash
), type
);
1208 skb
->protocol
= eth_type_trans(skb
, dev
);
1210 if (rxcmp1
->rx_cmp_flags2
&
1211 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN
)) {
1212 netdev_features_t features
= skb
->dev
->features
;
1213 u32 meta_data
= le32_to_cpu(rxcmp1
->rx_cmp_meta_data
);
1214 u16 vlan_proto
= meta_data
>> RX_CMP_FLAGS2_METADATA_TPID_SFT
;
1216 if (((features
& NETIF_F_HW_VLAN_CTAG_RX
) &&
1217 vlan_proto
== ETH_P_8021Q
) ||
1218 ((features
& NETIF_F_HW_VLAN_STAG_RX
) &&
1219 vlan_proto
== ETH_P_8021AD
))
1220 __vlan_hwaccel_put_tag(skb
, htons(vlan_proto
),
1222 RX_CMP_FLAGS2_METADATA_VID_MASK
);
1225 skb_checksum_none_assert(skb
);
1226 if (RX_CMP_L4_CS_OK(rxcmp1
)) {
1227 if (dev
->features
& NETIF_F_RXCSUM
) {
1228 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1229 skb
->csum_level
= RX_CMP_ENCAP(rxcmp1
);
1232 if (rxcmp1
->rx_cmp_cfa_code_errors_v2
& RX_CMP_L4_CS_ERR_BITS
) {
1233 if (dev
->features
& NETIF_F_RXCSUM
)
1234 cpr
->rx_l4_csum_errors
++;
1238 skb_record_rx_queue(skb
, bnapi
->index
);
1239 skb_mark_napi_id(skb
, &bnapi
->napi
);
1240 if (bnxt_busy_polling(bnapi
))
1241 netif_receive_skb(skb
);
1243 napi_gro_receive(&bnapi
->napi
, skb
);
1247 rxr
->rx_prod
= NEXT_RX(prod
);
1250 *raw_cons
= tmp_raw_cons
;
1255 static int bnxt_async_event_process(struct bnxt
*bp
,
1256 struct hwrm_async_event_cmpl
*cmpl
)
1258 u16 event_id
= le16_to_cpu(cmpl
->event_id
);
1260 /* TODO CHIMP_FW: Define event id's for link change, error etc */
1262 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE
:
1263 set_bit(BNXT_LINK_CHNG_SP_EVENT
, &bp
->sp_event
);
1265 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD
:
1266 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT
, &bp
->sp_event
);
1269 netdev_err(bp
->dev
, "unhandled ASYNC event (id 0x%x)\n",
1271 goto async_event_process_exit
;
1273 schedule_work(&bp
->sp_task
);
1274 async_event_process_exit
:
1278 static int bnxt_hwrm_handler(struct bnxt
*bp
, struct tx_cmp
*txcmp
)
1280 u16 cmpl_type
= TX_CMP_TYPE(txcmp
), vf_id
, seq_id
;
1281 struct hwrm_cmpl
*h_cmpl
= (struct hwrm_cmpl
*)txcmp
;
1282 struct hwrm_fwd_req_cmpl
*fwd_req_cmpl
=
1283 (struct hwrm_fwd_req_cmpl
*)txcmp
;
1285 switch (cmpl_type
) {
1286 case CMPL_BASE_TYPE_HWRM_DONE
:
1287 seq_id
= le16_to_cpu(h_cmpl
->sequence_id
);
1288 if (seq_id
== bp
->hwrm_intr_seq_id
)
1289 bp
->hwrm_intr_seq_id
= HWRM_SEQ_ID_INVALID
;
1291 netdev_err(bp
->dev
, "Invalid hwrm seq id %d\n", seq_id
);
1294 case CMPL_BASE_TYPE_HWRM_FWD_REQ
:
1295 vf_id
= le16_to_cpu(fwd_req_cmpl
->source_id
);
1297 if ((vf_id
< bp
->pf
.first_vf_id
) ||
1298 (vf_id
>= bp
->pf
.first_vf_id
+ bp
->pf
.active_vfs
)) {
1299 netdev_err(bp
->dev
, "Msg contains invalid VF id %x\n",
1304 set_bit(vf_id
- bp
->pf
.first_vf_id
, bp
->pf
.vf_event_bmap
);
1305 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT
, &bp
->sp_event
);
1306 schedule_work(&bp
->sp_task
);
1309 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT
:
1310 bnxt_async_event_process(bp
,
1311 (struct hwrm_async_event_cmpl
*)txcmp
);
1320 static irqreturn_t
bnxt_msix(int irq
, void *dev_instance
)
1322 struct bnxt_napi
*bnapi
= dev_instance
;
1323 struct bnxt
*bp
= bnapi
->bp
;
1324 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1325 u32 cons
= RING_CMP(cpr
->cp_raw_cons
);
1327 prefetch(&cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)]);
1328 napi_schedule(&bnapi
->napi
);
1332 static inline int bnxt_has_work(struct bnxt
*bp
, struct bnxt_cp_ring_info
*cpr
)
1334 u32 raw_cons
= cpr
->cp_raw_cons
;
1335 u16 cons
= RING_CMP(raw_cons
);
1336 struct tx_cmp
*txcmp
;
1338 txcmp
= &cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)];
1340 return TX_CMP_VALID(txcmp
, raw_cons
);
1343 static irqreturn_t
bnxt_inta(int irq
, void *dev_instance
)
1345 struct bnxt_napi
*bnapi
= dev_instance
;
1346 struct bnxt
*bp
= bnapi
->bp
;
1347 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1348 u32 cons
= RING_CMP(cpr
->cp_raw_cons
);
1351 prefetch(&cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)]);
1353 if (!bnxt_has_work(bp
, cpr
)) {
1354 int_status
= readl(bp
->bar0
+ BNXT_CAG_REG_LEGACY_INT_STATUS
);
1355 /* return if erroneous interrupt */
1356 if (!(int_status
& (0x10000 << cpr
->cp_ring_struct
.fw_ring_id
)))
1360 /* disable ring IRQ */
1361 BNXT_CP_DB_IRQ_DIS(cpr
->cp_doorbell
);
1363 /* Return here if interrupt is shared and is disabled. */
1364 if (unlikely(atomic_read(&bp
->intr_sem
) != 0))
1367 napi_schedule(&bnapi
->napi
);
1371 static int bnxt_poll_work(struct bnxt
*bp
, struct bnxt_napi
*bnapi
, int budget
)
1373 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1374 u32 raw_cons
= cpr
->cp_raw_cons
;
1378 bool rx_event
= false;
1379 bool agg_event
= false;
1380 struct tx_cmp
*txcmp
;
1385 cons
= RING_CMP(raw_cons
);
1386 txcmp
= &cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)];
1388 if (!TX_CMP_VALID(txcmp
, raw_cons
))
1391 if (TX_CMP_TYPE(txcmp
) == CMP_TYPE_TX_L2_CMP
) {
1393 /* return full budget so NAPI will complete. */
1394 if (unlikely(tx_pkts
> bp
->tx_wake_thresh
))
1396 } else if ((TX_CMP_TYPE(txcmp
) & 0x30) == 0x10) {
1397 rc
= bnxt_rx_pkt(bp
, bnapi
, &raw_cons
, &agg_event
);
1398 if (likely(rc
>= 0))
1400 else if (rc
== -EBUSY
) /* partial completion */
1403 } else if (unlikely((TX_CMP_TYPE(txcmp
) ==
1404 CMPL_BASE_TYPE_HWRM_DONE
) ||
1405 (TX_CMP_TYPE(txcmp
) ==
1406 CMPL_BASE_TYPE_HWRM_FWD_REQ
) ||
1407 (TX_CMP_TYPE(txcmp
) ==
1408 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT
))) {
1409 bnxt_hwrm_handler(bp
, txcmp
);
1411 raw_cons
= NEXT_RAW_CMP(raw_cons
);
1413 if (rx_pkts
== budget
)
1417 cpr
->cp_raw_cons
= raw_cons
;
1418 /* ACK completion ring before freeing tx ring and producing new
1419 * buffers in rx/agg rings to prevent overflowing the completion
1422 BNXT_CP_DB(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
1425 bnxt_tx_int(bp
, bnapi
, tx_pkts
);
1428 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
1430 writel(DB_KEY_RX
| rxr
->rx_prod
, rxr
->rx_doorbell
);
1431 writel(DB_KEY_RX
| rxr
->rx_prod
, rxr
->rx_doorbell
);
1433 writel(DB_KEY_RX
| rxr
->rx_agg_prod
,
1434 rxr
->rx_agg_doorbell
);
1435 writel(DB_KEY_RX
| rxr
->rx_agg_prod
,
1436 rxr
->rx_agg_doorbell
);
1442 static int bnxt_poll(struct napi_struct
*napi
, int budget
)
1444 struct bnxt_napi
*bnapi
= container_of(napi
, struct bnxt_napi
, napi
);
1445 struct bnxt
*bp
= bnapi
->bp
;
1446 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1449 if (!bnxt_lock_napi(bnapi
))
1453 work_done
+= bnxt_poll_work(bp
, bnapi
, budget
- work_done
);
1455 if (work_done
>= budget
)
1458 if (!bnxt_has_work(bp
, cpr
)) {
1459 napi_complete(napi
);
1460 BNXT_CP_DB_REARM(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
1465 bnxt_unlock_napi(bnapi
);
1469 #ifdef CONFIG_NET_RX_BUSY_POLL
1470 static int bnxt_busy_poll(struct napi_struct
*napi
)
1472 struct bnxt_napi
*bnapi
= container_of(napi
, struct bnxt_napi
, napi
);
1473 struct bnxt
*bp
= bnapi
->bp
;
1474 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1475 int rx_work
, budget
= 4;
1477 if (atomic_read(&bp
->intr_sem
) != 0)
1478 return LL_FLUSH_FAILED
;
1480 if (!bnxt_lock_poll(bnapi
))
1481 return LL_FLUSH_BUSY
;
1483 rx_work
= bnxt_poll_work(bp
, bnapi
, budget
);
1485 BNXT_CP_DB_REARM(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
1487 bnxt_unlock_poll(bnapi
);
1492 static void bnxt_free_tx_skbs(struct bnxt
*bp
)
1495 struct pci_dev
*pdev
= bp
->pdev
;
1500 max_idx
= bp
->tx_nr_pages
* TX_DESC_CNT
;
1501 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
1502 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
1505 for (j
= 0; j
< max_idx
;) {
1506 struct bnxt_sw_tx_bd
*tx_buf
= &txr
->tx_buf_ring
[j
];
1507 struct sk_buff
*skb
= tx_buf
->skb
;
1517 if (tx_buf
->is_push
) {
1523 dma_unmap_single(&pdev
->dev
,
1524 dma_unmap_addr(tx_buf
, mapping
),
1528 last
= tx_buf
->nr_frags
;
1530 for (k
= 0; k
< last
; k
++, j
++) {
1531 int ring_idx
= j
& bp
->tx_ring_mask
;
1532 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[k
];
1534 tx_buf
= &txr
->tx_buf_ring
[ring_idx
];
1537 dma_unmap_addr(tx_buf
, mapping
),
1538 skb_frag_size(frag
), PCI_DMA_TODEVICE
);
1542 netdev_tx_reset_queue(netdev_get_tx_queue(bp
->dev
, i
));
1546 static void bnxt_free_rx_skbs(struct bnxt
*bp
)
1548 int i
, max_idx
, max_agg_idx
;
1549 struct pci_dev
*pdev
= bp
->pdev
;
1554 max_idx
= bp
->rx_nr_pages
* RX_DESC_CNT
;
1555 max_agg_idx
= bp
->rx_agg_nr_pages
* RX_DESC_CNT
;
1556 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
1557 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
1561 for (j
= 0; j
< MAX_TPA
; j
++) {
1562 struct bnxt_tpa_info
*tpa_info
=
1564 u8
*data
= tpa_info
->data
;
1571 dma_unmap_addr(tpa_info
, mapping
),
1572 bp
->rx_buf_use_size
,
1573 PCI_DMA_FROMDEVICE
);
1575 tpa_info
->data
= NULL
;
1581 for (j
= 0; j
< max_idx
; j
++) {
1582 struct bnxt_sw_rx_bd
*rx_buf
= &rxr
->rx_buf_ring
[j
];
1583 u8
*data
= rx_buf
->data
;
1588 dma_unmap_single(&pdev
->dev
,
1589 dma_unmap_addr(rx_buf
, mapping
),
1590 bp
->rx_buf_use_size
,
1591 PCI_DMA_FROMDEVICE
);
1593 rx_buf
->data
= NULL
;
1598 for (j
= 0; j
< max_agg_idx
; j
++) {
1599 struct bnxt_sw_rx_agg_bd
*rx_agg_buf
=
1600 &rxr
->rx_agg_ring
[j
];
1601 struct page
*page
= rx_agg_buf
->page
;
1606 dma_unmap_page(&pdev
->dev
,
1607 dma_unmap_addr(rx_agg_buf
, mapping
),
1608 BNXT_RX_PAGE_SIZE
, PCI_DMA_FROMDEVICE
);
1610 rx_agg_buf
->page
= NULL
;
1611 __clear_bit(j
, rxr
->rx_agg_bmap
);
1616 __free_page(rxr
->rx_page
);
1617 rxr
->rx_page
= NULL
;
1622 static void bnxt_free_skbs(struct bnxt
*bp
)
1624 bnxt_free_tx_skbs(bp
);
1625 bnxt_free_rx_skbs(bp
);
1628 static void bnxt_free_ring(struct bnxt
*bp
, struct bnxt_ring_struct
*ring
)
1630 struct pci_dev
*pdev
= bp
->pdev
;
1633 for (i
= 0; i
< ring
->nr_pages
; i
++) {
1634 if (!ring
->pg_arr
[i
])
1637 dma_free_coherent(&pdev
->dev
, ring
->page_size
,
1638 ring
->pg_arr
[i
], ring
->dma_arr
[i
]);
1640 ring
->pg_arr
[i
] = NULL
;
1643 dma_free_coherent(&pdev
->dev
, ring
->nr_pages
* 8,
1644 ring
->pg_tbl
, ring
->pg_tbl_map
);
1645 ring
->pg_tbl
= NULL
;
1647 if (ring
->vmem_size
&& *ring
->vmem
) {
1653 static int bnxt_alloc_ring(struct bnxt
*bp
, struct bnxt_ring_struct
*ring
)
1656 struct pci_dev
*pdev
= bp
->pdev
;
1658 if (ring
->nr_pages
> 1) {
1659 ring
->pg_tbl
= dma_alloc_coherent(&pdev
->dev
,
1667 for (i
= 0; i
< ring
->nr_pages
; i
++) {
1668 ring
->pg_arr
[i
] = dma_alloc_coherent(&pdev
->dev
,
1672 if (!ring
->pg_arr
[i
])
1675 if (ring
->nr_pages
> 1)
1676 ring
->pg_tbl
[i
] = cpu_to_le64(ring
->dma_arr
[i
]);
1679 if (ring
->vmem_size
) {
1680 *ring
->vmem
= vzalloc(ring
->vmem_size
);
1687 static void bnxt_free_rx_rings(struct bnxt
*bp
)
1694 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
1695 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
1696 struct bnxt_ring_struct
*ring
;
1701 kfree(rxr
->rx_agg_bmap
);
1702 rxr
->rx_agg_bmap
= NULL
;
1704 ring
= &rxr
->rx_ring_struct
;
1705 bnxt_free_ring(bp
, ring
);
1707 ring
= &rxr
->rx_agg_ring_struct
;
1708 bnxt_free_ring(bp
, ring
);
1712 static int bnxt_alloc_rx_rings(struct bnxt
*bp
)
1714 int i
, rc
, agg_rings
= 0, tpa_rings
= 0;
1719 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
)
1722 if (bp
->flags
& BNXT_FLAG_TPA
)
1725 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
1726 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
1727 struct bnxt_ring_struct
*ring
;
1729 ring
= &rxr
->rx_ring_struct
;
1731 rc
= bnxt_alloc_ring(bp
, ring
);
1738 ring
= &rxr
->rx_agg_ring_struct
;
1739 rc
= bnxt_alloc_ring(bp
, ring
);
1743 rxr
->rx_agg_bmap_size
= bp
->rx_agg_ring_mask
+ 1;
1744 mem_size
= rxr
->rx_agg_bmap_size
/ 8;
1745 rxr
->rx_agg_bmap
= kzalloc(mem_size
, GFP_KERNEL
);
1746 if (!rxr
->rx_agg_bmap
)
1750 rxr
->rx_tpa
= kcalloc(MAX_TPA
,
1751 sizeof(struct bnxt_tpa_info
),
1761 static void bnxt_free_tx_rings(struct bnxt
*bp
)
1764 struct pci_dev
*pdev
= bp
->pdev
;
1769 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
1770 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
1771 struct bnxt_ring_struct
*ring
;
1774 dma_free_coherent(&pdev
->dev
, bp
->tx_push_size
,
1775 txr
->tx_push
, txr
->tx_push_mapping
);
1776 txr
->tx_push
= NULL
;
1779 ring
= &txr
->tx_ring_struct
;
1781 bnxt_free_ring(bp
, ring
);
1785 static int bnxt_alloc_tx_rings(struct bnxt
*bp
)
1788 struct pci_dev
*pdev
= bp
->pdev
;
1790 bp
->tx_push_size
= 0;
1791 if (bp
->tx_push_thresh
) {
1794 push_size
= L1_CACHE_ALIGN(sizeof(struct tx_push_bd
) +
1795 bp
->tx_push_thresh
);
1797 if (push_size
> 256) {
1799 bp
->tx_push_thresh
= 0;
1802 bp
->tx_push_size
= push_size
;
1805 for (i
= 0, j
= 0; i
< bp
->tx_nr_rings
; i
++) {
1806 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
1807 struct bnxt_ring_struct
*ring
;
1809 ring
= &txr
->tx_ring_struct
;
1811 rc
= bnxt_alloc_ring(bp
, ring
);
1815 if (bp
->tx_push_size
) {
1818 /* One pre-allocated DMA buffer to backup
1821 txr
->tx_push
= dma_alloc_coherent(&pdev
->dev
,
1823 &txr
->tx_push_mapping
,
1829 mapping
= txr
->tx_push_mapping
+
1830 sizeof(struct tx_push_bd
);
1831 txr
->data_mapping
= cpu_to_le64(mapping
);
1833 memset(txr
->tx_push
, 0, sizeof(struct tx_push_bd
));
1835 ring
->queue_id
= bp
->q_info
[j
].queue_id
;
1836 if (i
% bp
->tx_nr_rings_per_tc
== (bp
->tx_nr_rings_per_tc
- 1))
1842 static void bnxt_free_cp_rings(struct bnxt
*bp
)
1849 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
1850 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
1851 struct bnxt_cp_ring_info
*cpr
;
1852 struct bnxt_ring_struct
*ring
;
1857 cpr
= &bnapi
->cp_ring
;
1858 ring
= &cpr
->cp_ring_struct
;
1860 bnxt_free_ring(bp
, ring
);
1864 static int bnxt_alloc_cp_rings(struct bnxt
*bp
)
1868 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
1869 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
1870 struct bnxt_cp_ring_info
*cpr
;
1871 struct bnxt_ring_struct
*ring
;
1876 cpr
= &bnapi
->cp_ring
;
1877 ring
= &cpr
->cp_ring_struct
;
1879 rc
= bnxt_alloc_ring(bp
, ring
);
1886 static void bnxt_init_ring_struct(struct bnxt
*bp
)
1890 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
1891 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
1892 struct bnxt_cp_ring_info
*cpr
;
1893 struct bnxt_rx_ring_info
*rxr
;
1894 struct bnxt_tx_ring_info
*txr
;
1895 struct bnxt_ring_struct
*ring
;
1900 cpr
= &bnapi
->cp_ring
;
1901 ring
= &cpr
->cp_ring_struct
;
1902 ring
->nr_pages
= bp
->cp_nr_pages
;
1903 ring
->page_size
= HW_CMPD_RING_SIZE
;
1904 ring
->pg_arr
= (void **)cpr
->cp_desc_ring
;
1905 ring
->dma_arr
= cpr
->cp_desc_mapping
;
1906 ring
->vmem_size
= 0;
1908 rxr
= bnapi
->rx_ring
;
1912 ring
= &rxr
->rx_ring_struct
;
1913 ring
->nr_pages
= bp
->rx_nr_pages
;
1914 ring
->page_size
= HW_RXBD_RING_SIZE
;
1915 ring
->pg_arr
= (void **)rxr
->rx_desc_ring
;
1916 ring
->dma_arr
= rxr
->rx_desc_mapping
;
1917 ring
->vmem_size
= SW_RXBD_RING_SIZE
* bp
->rx_nr_pages
;
1918 ring
->vmem
= (void **)&rxr
->rx_buf_ring
;
1920 ring
= &rxr
->rx_agg_ring_struct
;
1921 ring
->nr_pages
= bp
->rx_agg_nr_pages
;
1922 ring
->page_size
= HW_RXBD_RING_SIZE
;
1923 ring
->pg_arr
= (void **)rxr
->rx_agg_desc_ring
;
1924 ring
->dma_arr
= rxr
->rx_agg_desc_mapping
;
1925 ring
->vmem_size
= SW_RXBD_AGG_RING_SIZE
* bp
->rx_agg_nr_pages
;
1926 ring
->vmem
= (void **)&rxr
->rx_agg_ring
;
1929 txr
= bnapi
->tx_ring
;
1933 ring
= &txr
->tx_ring_struct
;
1934 ring
->nr_pages
= bp
->tx_nr_pages
;
1935 ring
->page_size
= HW_RXBD_RING_SIZE
;
1936 ring
->pg_arr
= (void **)txr
->tx_desc_ring
;
1937 ring
->dma_arr
= txr
->tx_desc_mapping
;
1938 ring
->vmem_size
= SW_TXBD_RING_SIZE
* bp
->tx_nr_pages
;
1939 ring
->vmem
= (void **)&txr
->tx_buf_ring
;
1943 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct
*ring
, u32 type
)
1947 struct rx_bd
**rx_buf_ring
;
1949 rx_buf_ring
= (struct rx_bd
**)ring
->pg_arr
;
1950 for (i
= 0, prod
= 0; i
< ring
->nr_pages
; i
++) {
1954 rxbd
= rx_buf_ring
[i
];
1958 for (j
= 0; j
< RX_DESC_CNT
; j
++, rxbd
++, prod
++) {
1959 rxbd
->rx_bd_len_flags_type
= cpu_to_le32(type
);
1960 rxbd
->rx_bd_opaque
= prod
;
1965 static int bnxt_init_one_rx_ring(struct bnxt
*bp
, int ring_nr
)
1967 struct net_device
*dev
= bp
->dev
;
1968 struct bnxt_rx_ring_info
*rxr
;
1969 struct bnxt_ring_struct
*ring
;
1973 type
= (bp
->rx_buf_use_size
<< RX_BD_LEN_SHIFT
) |
1974 RX_BD_TYPE_RX_PACKET_BD
| RX_BD_FLAGS_EOP
;
1976 if (NET_IP_ALIGN
== 2)
1977 type
|= RX_BD_FLAGS_SOP
;
1979 rxr
= &bp
->rx_ring
[ring_nr
];
1980 ring
= &rxr
->rx_ring_struct
;
1981 bnxt_init_rxbd_pages(ring
, type
);
1983 prod
= rxr
->rx_prod
;
1984 for (i
= 0; i
< bp
->rx_ring_size
; i
++) {
1985 if (bnxt_alloc_rx_data(bp
, rxr
, prod
, GFP_KERNEL
) != 0) {
1986 netdev_warn(dev
, "init'ed rx ring %d with %d/%d skbs only\n",
1987 ring_nr
, i
, bp
->rx_ring_size
);
1990 prod
= NEXT_RX(prod
);
1992 rxr
->rx_prod
= prod
;
1993 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
1995 ring
= &rxr
->rx_agg_ring_struct
;
1996 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
1998 if (!(bp
->flags
& BNXT_FLAG_AGG_RINGS
))
2001 type
= ((u32
)BNXT_RX_PAGE_SIZE
<< RX_BD_LEN_SHIFT
) |
2002 RX_BD_TYPE_RX_AGG_BD
| RX_BD_FLAGS_SOP
;
2004 bnxt_init_rxbd_pages(ring
, type
);
2006 prod
= rxr
->rx_agg_prod
;
2007 for (i
= 0; i
< bp
->rx_agg_ring_size
; i
++) {
2008 if (bnxt_alloc_rx_page(bp
, rxr
, prod
, GFP_KERNEL
) != 0) {
2009 netdev_warn(dev
, "init'ed rx ring %d with %d/%d pages only\n",
2010 ring_nr
, i
, bp
->rx_ring_size
);
2013 prod
= NEXT_RX_AGG(prod
);
2015 rxr
->rx_agg_prod
= prod
;
2017 if (bp
->flags
& BNXT_FLAG_TPA
) {
2022 for (i
= 0; i
< MAX_TPA
; i
++) {
2023 data
= __bnxt_alloc_rx_data(bp
, &mapping
,
2028 rxr
->rx_tpa
[i
].data
= data
;
2029 rxr
->rx_tpa
[i
].mapping
= mapping
;
2032 netdev_err(bp
->dev
, "No resource allocated for LRO/GRO\n");
2040 static int bnxt_init_rx_rings(struct bnxt
*bp
)
2044 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
2045 rc
= bnxt_init_one_rx_ring(bp
, i
);
2053 static int bnxt_init_tx_rings(struct bnxt
*bp
)
2057 bp
->tx_wake_thresh
= max_t(int, bp
->tx_ring_size
/ 2,
2060 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
2061 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
2062 struct bnxt_ring_struct
*ring
= &txr
->tx_ring_struct
;
2064 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
2070 static void bnxt_free_ring_grps(struct bnxt
*bp
)
2072 kfree(bp
->grp_info
);
2073 bp
->grp_info
= NULL
;
2076 static int bnxt_init_ring_grps(struct bnxt
*bp
, bool irq_re_init
)
2081 bp
->grp_info
= kcalloc(bp
->cp_nr_rings
,
2082 sizeof(struct bnxt_ring_grp_info
),
2087 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2089 bp
->grp_info
[i
].fw_stats_ctx
= INVALID_HW_RING_ID
;
2090 bp
->grp_info
[i
].fw_grp_id
= INVALID_HW_RING_ID
;
2091 bp
->grp_info
[i
].rx_fw_ring_id
= INVALID_HW_RING_ID
;
2092 bp
->grp_info
[i
].agg_fw_ring_id
= INVALID_HW_RING_ID
;
2093 bp
->grp_info
[i
].cp_fw_ring_id
= INVALID_HW_RING_ID
;
2098 static void bnxt_free_vnics(struct bnxt
*bp
)
2100 kfree(bp
->vnic_info
);
2101 bp
->vnic_info
= NULL
;
2105 static int bnxt_alloc_vnics(struct bnxt
*bp
)
2109 #ifdef CONFIG_RFS_ACCEL
2110 if (bp
->flags
& BNXT_FLAG_RFS
)
2111 num_vnics
+= bp
->rx_nr_rings
;
2114 bp
->vnic_info
= kcalloc(num_vnics
, sizeof(struct bnxt_vnic_info
),
2119 bp
->nr_vnics
= num_vnics
;
2123 static void bnxt_init_vnics(struct bnxt
*bp
)
2127 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
2128 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[i
];
2130 vnic
->fw_vnic_id
= INVALID_HW_RING_ID
;
2131 vnic
->fw_rss_cos_lb_ctx
= INVALID_HW_RING_ID
;
2132 vnic
->fw_l2_ctx_id
= INVALID_HW_RING_ID
;
2134 if (bp
->vnic_info
[i
].rss_hash_key
) {
2136 prandom_bytes(vnic
->rss_hash_key
,
2139 memcpy(vnic
->rss_hash_key
,
2140 bp
->vnic_info
[0].rss_hash_key
,
2146 static int bnxt_calc_nr_ring_pages(u32 ring_size
, int desc_per_pg
)
2150 pages
= ring_size
/ desc_per_pg
;
2157 while (pages
& (pages
- 1))
2163 static void bnxt_set_tpa_flags(struct bnxt
*bp
)
2165 bp
->flags
&= ~BNXT_FLAG_TPA
;
2166 if (bp
->dev
->features
& NETIF_F_LRO
)
2167 bp
->flags
|= BNXT_FLAG_LRO
;
2168 if ((bp
->dev
->features
& NETIF_F_GRO
) && (bp
->pdev
->revision
> 0))
2169 bp
->flags
|= BNXT_FLAG_GRO
;
2172 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2175 void bnxt_set_ring_params(struct bnxt
*bp
)
2177 u32 ring_size
, rx_size
, rx_space
;
2178 u32 agg_factor
= 0, agg_ring_size
= 0;
2180 /* 8 for CRC and VLAN */
2181 rx_size
= SKB_DATA_ALIGN(bp
->dev
->mtu
+ ETH_HLEN
+ NET_IP_ALIGN
+ 8);
2183 rx_space
= rx_size
+ NET_SKB_PAD
+
2184 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
2186 bp
->rx_copy_thresh
= BNXT_RX_COPY_THRESH
;
2187 ring_size
= bp
->rx_ring_size
;
2188 bp
->rx_agg_ring_size
= 0;
2189 bp
->rx_agg_nr_pages
= 0;
2191 if (bp
->flags
& BNXT_FLAG_TPA
)
2192 agg_factor
= min_t(u32
, 4, 65536 / BNXT_RX_PAGE_SIZE
);
2194 bp
->flags
&= ~BNXT_FLAG_JUMBO
;
2195 if (rx_space
> PAGE_SIZE
) {
2198 bp
->flags
|= BNXT_FLAG_JUMBO
;
2199 jumbo_factor
= PAGE_ALIGN(bp
->dev
->mtu
- 40) >> PAGE_SHIFT
;
2200 if (jumbo_factor
> agg_factor
)
2201 agg_factor
= jumbo_factor
;
2203 agg_ring_size
= ring_size
* agg_factor
;
2205 if (agg_ring_size
) {
2206 bp
->rx_agg_nr_pages
= bnxt_calc_nr_ring_pages(agg_ring_size
,
2208 if (bp
->rx_agg_nr_pages
> MAX_RX_AGG_PAGES
) {
2209 u32 tmp
= agg_ring_size
;
2211 bp
->rx_agg_nr_pages
= MAX_RX_AGG_PAGES
;
2212 agg_ring_size
= MAX_RX_AGG_PAGES
* RX_DESC_CNT
- 1;
2213 netdev_warn(bp
->dev
, "rx agg ring size %d reduced to %d.\n",
2214 tmp
, agg_ring_size
);
2216 bp
->rx_agg_ring_size
= agg_ring_size
;
2217 bp
->rx_agg_ring_mask
= (bp
->rx_agg_nr_pages
* RX_DESC_CNT
) - 1;
2218 rx_size
= SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH
+ NET_IP_ALIGN
);
2219 rx_space
= rx_size
+ NET_SKB_PAD
+
2220 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
2223 bp
->rx_buf_use_size
= rx_size
;
2224 bp
->rx_buf_size
= rx_space
;
2226 bp
->rx_nr_pages
= bnxt_calc_nr_ring_pages(ring_size
, RX_DESC_CNT
);
2227 bp
->rx_ring_mask
= (bp
->rx_nr_pages
* RX_DESC_CNT
) - 1;
2229 ring_size
= bp
->tx_ring_size
;
2230 bp
->tx_nr_pages
= bnxt_calc_nr_ring_pages(ring_size
, TX_DESC_CNT
);
2231 bp
->tx_ring_mask
= (bp
->tx_nr_pages
* TX_DESC_CNT
) - 1;
2233 ring_size
= bp
->rx_ring_size
* (2 + agg_factor
) + bp
->tx_ring_size
;
2234 bp
->cp_ring_size
= ring_size
;
2236 bp
->cp_nr_pages
= bnxt_calc_nr_ring_pages(ring_size
, CP_DESC_CNT
);
2237 if (bp
->cp_nr_pages
> MAX_CP_PAGES
) {
2238 bp
->cp_nr_pages
= MAX_CP_PAGES
;
2239 bp
->cp_ring_size
= MAX_CP_PAGES
* CP_DESC_CNT
- 1;
2240 netdev_warn(bp
->dev
, "completion ring size %d reduced to %d.\n",
2241 ring_size
, bp
->cp_ring_size
);
2243 bp
->cp_bit
= bp
->cp_nr_pages
* CP_DESC_CNT
;
2244 bp
->cp_ring_mask
= bp
->cp_bit
- 1;
2247 static void bnxt_free_vnic_attributes(struct bnxt
*bp
)
2250 struct bnxt_vnic_info
*vnic
;
2251 struct pci_dev
*pdev
= bp
->pdev
;
2256 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
2257 vnic
= &bp
->vnic_info
[i
];
2259 kfree(vnic
->fw_grp_ids
);
2260 vnic
->fw_grp_ids
= NULL
;
2262 kfree(vnic
->uc_list
);
2263 vnic
->uc_list
= NULL
;
2265 if (vnic
->mc_list
) {
2266 dma_free_coherent(&pdev
->dev
, vnic
->mc_list_size
,
2267 vnic
->mc_list
, vnic
->mc_list_mapping
);
2268 vnic
->mc_list
= NULL
;
2271 if (vnic
->rss_table
) {
2272 dma_free_coherent(&pdev
->dev
, PAGE_SIZE
,
2274 vnic
->rss_table_dma_addr
);
2275 vnic
->rss_table
= NULL
;
2278 vnic
->rss_hash_key
= NULL
;
2283 static int bnxt_alloc_vnic_attributes(struct bnxt
*bp
)
2285 int i
, rc
= 0, size
;
2286 struct bnxt_vnic_info
*vnic
;
2287 struct pci_dev
*pdev
= bp
->pdev
;
2290 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
2291 vnic
= &bp
->vnic_info
[i
];
2293 if (vnic
->flags
& BNXT_VNIC_UCAST_FLAG
) {
2294 int mem_size
= (BNXT_MAX_UC_ADDRS
- 1) * ETH_ALEN
;
2297 vnic
->uc_list
= kmalloc(mem_size
, GFP_KERNEL
);
2298 if (!vnic
->uc_list
) {
2305 if (vnic
->flags
& BNXT_VNIC_MCAST_FLAG
) {
2306 vnic
->mc_list_size
= BNXT_MAX_MC_ADDRS
* ETH_ALEN
;
2308 dma_alloc_coherent(&pdev
->dev
,
2310 &vnic
->mc_list_mapping
,
2312 if (!vnic
->mc_list
) {
2318 if (vnic
->flags
& BNXT_VNIC_RSS_FLAG
)
2319 max_rings
= bp
->rx_nr_rings
;
2323 vnic
->fw_grp_ids
= kcalloc(max_rings
, sizeof(u16
), GFP_KERNEL
);
2324 if (!vnic
->fw_grp_ids
) {
2329 /* Allocate rss table and hash key */
2330 vnic
->rss_table
= dma_alloc_coherent(&pdev
->dev
, PAGE_SIZE
,
2331 &vnic
->rss_table_dma_addr
,
2333 if (!vnic
->rss_table
) {
2338 size
= L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE
* sizeof(u16
));
2340 vnic
->rss_hash_key
= ((void *)vnic
->rss_table
) + size
;
2341 vnic
->rss_hash_key_dma_addr
= vnic
->rss_table_dma_addr
+ size
;
2349 static void bnxt_free_hwrm_resources(struct bnxt
*bp
)
2351 struct pci_dev
*pdev
= bp
->pdev
;
2353 dma_free_coherent(&pdev
->dev
, PAGE_SIZE
, bp
->hwrm_cmd_resp_addr
,
2354 bp
->hwrm_cmd_resp_dma_addr
);
2356 bp
->hwrm_cmd_resp_addr
= NULL
;
2357 if (bp
->hwrm_dbg_resp_addr
) {
2358 dma_free_coherent(&pdev
->dev
, HWRM_DBG_REG_BUF_SIZE
,
2359 bp
->hwrm_dbg_resp_addr
,
2360 bp
->hwrm_dbg_resp_dma_addr
);
2362 bp
->hwrm_dbg_resp_addr
= NULL
;
2366 static int bnxt_alloc_hwrm_resources(struct bnxt
*bp
)
2368 struct pci_dev
*pdev
= bp
->pdev
;
2370 bp
->hwrm_cmd_resp_addr
= dma_alloc_coherent(&pdev
->dev
, PAGE_SIZE
,
2371 &bp
->hwrm_cmd_resp_dma_addr
,
2373 if (!bp
->hwrm_cmd_resp_addr
)
2375 bp
->hwrm_dbg_resp_addr
= dma_alloc_coherent(&pdev
->dev
,
2376 HWRM_DBG_REG_BUF_SIZE
,
2377 &bp
->hwrm_dbg_resp_dma_addr
,
2379 if (!bp
->hwrm_dbg_resp_addr
)
2380 netdev_warn(bp
->dev
, "fail to alloc debug register dma mem\n");
2385 static void bnxt_free_stats(struct bnxt
*bp
)
2388 struct pci_dev
*pdev
= bp
->pdev
;
2390 if (bp
->hw_rx_port_stats
) {
2391 dma_free_coherent(&pdev
->dev
, bp
->hw_port_stats_size
,
2392 bp
->hw_rx_port_stats
,
2393 bp
->hw_rx_port_stats_map
);
2394 bp
->hw_rx_port_stats
= NULL
;
2395 bp
->flags
&= ~BNXT_FLAG_PORT_STATS
;
2401 size
= sizeof(struct ctx_hw_stats
);
2403 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2404 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2405 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
2407 if (cpr
->hw_stats
) {
2408 dma_free_coherent(&pdev
->dev
, size
, cpr
->hw_stats
,
2410 cpr
->hw_stats
= NULL
;
2415 static int bnxt_alloc_stats(struct bnxt
*bp
)
2418 struct pci_dev
*pdev
= bp
->pdev
;
2420 size
= sizeof(struct ctx_hw_stats
);
2422 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2423 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2424 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
2426 cpr
->hw_stats
= dma_alloc_coherent(&pdev
->dev
, size
,
2432 cpr
->hw_stats_ctx_id
= INVALID_STATS_CTX_ID
;
2436 bp
->hw_port_stats_size
= sizeof(struct rx_port_stats
) +
2437 sizeof(struct tx_port_stats
) + 1024;
2439 bp
->hw_rx_port_stats
=
2440 dma_alloc_coherent(&pdev
->dev
, bp
->hw_port_stats_size
,
2441 &bp
->hw_rx_port_stats_map
,
2443 if (!bp
->hw_rx_port_stats
)
2446 bp
->hw_tx_port_stats
= (void *)(bp
->hw_rx_port_stats
+ 1) +
2448 bp
->hw_tx_port_stats_map
= bp
->hw_rx_port_stats_map
+
2449 sizeof(struct rx_port_stats
) + 512;
2450 bp
->flags
|= BNXT_FLAG_PORT_STATS
;
2455 static void bnxt_clear_ring_indices(struct bnxt
*bp
)
2462 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2463 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2464 struct bnxt_cp_ring_info
*cpr
;
2465 struct bnxt_rx_ring_info
*rxr
;
2466 struct bnxt_tx_ring_info
*txr
;
2471 cpr
= &bnapi
->cp_ring
;
2472 cpr
->cp_raw_cons
= 0;
2474 txr
= bnapi
->tx_ring
;
2480 rxr
= bnapi
->rx_ring
;
2483 rxr
->rx_agg_prod
= 0;
2484 rxr
->rx_sw_agg_prod
= 0;
2489 static void bnxt_free_ntp_fltrs(struct bnxt
*bp
, bool irq_reinit
)
2491 #ifdef CONFIG_RFS_ACCEL
2494 /* Under rtnl_lock and all our NAPIs have been disabled. It's
2495 * safe to delete the hash table.
2497 for (i
= 0; i
< BNXT_NTP_FLTR_HASH_SIZE
; i
++) {
2498 struct hlist_head
*head
;
2499 struct hlist_node
*tmp
;
2500 struct bnxt_ntuple_filter
*fltr
;
2502 head
= &bp
->ntp_fltr_hash_tbl
[i
];
2503 hlist_for_each_entry_safe(fltr
, tmp
, head
, hash
) {
2504 hlist_del(&fltr
->hash
);
2509 kfree(bp
->ntp_fltr_bmap
);
2510 bp
->ntp_fltr_bmap
= NULL
;
2512 bp
->ntp_fltr_count
= 0;
2516 static int bnxt_alloc_ntp_fltrs(struct bnxt
*bp
)
2518 #ifdef CONFIG_RFS_ACCEL
2521 if (!(bp
->flags
& BNXT_FLAG_RFS
))
2524 for (i
= 0; i
< BNXT_NTP_FLTR_HASH_SIZE
; i
++)
2525 INIT_HLIST_HEAD(&bp
->ntp_fltr_hash_tbl
[i
]);
2527 bp
->ntp_fltr_count
= 0;
2528 bp
->ntp_fltr_bmap
= kzalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR
),
2531 if (!bp
->ntp_fltr_bmap
)
2540 static void bnxt_free_mem(struct bnxt
*bp
, bool irq_re_init
)
2542 bnxt_free_vnic_attributes(bp
);
2543 bnxt_free_tx_rings(bp
);
2544 bnxt_free_rx_rings(bp
);
2545 bnxt_free_cp_rings(bp
);
2546 bnxt_free_ntp_fltrs(bp
, irq_re_init
);
2548 bnxt_free_stats(bp
);
2549 bnxt_free_ring_grps(bp
);
2550 bnxt_free_vnics(bp
);
2558 bnxt_clear_ring_indices(bp
);
2562 static int bnxt_alloc_mem(struct bnxt
*bp
, bool irq_re_init
)
2564 int i
, j
, rc
, size
, arr_size
;
2568 /* Allocate bnapi mem pointer array and mem block for
2571 arr_size
= L1_CACHE_ALIGN(sizeof(struct bnxt_napi
*) *
2573 size
= L1_CACHE_ALIGN(sizeof(struct bnxt_napi
));
2574 bnapi
= kzalloc(arr_size
+ size
* bp
->cp_nr_rings
, GFP_KERNEL
);
2580 for (i
= 0; i
< bp
->cp_nr_rings
; i
++, bnapi
+= size
) {
2581 bp
->bnapi
[i
] = bnapi
;
2582 bp
->bnapi
[i
]->index
= i
;
2583 bp
->bnapi
[i
]->bp
= bp
;
2586 bp
->rx_ring
= kcalloc(bp
->rx_nr_rings
,
2587 sizeof(struct bnxt_rx_ring_info
),
2592 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
2593 bp
->rx_ring
[i
].bnapi
= bp
->bnapi
[i
];
2594 bp
->bnapi
[i
]->rx_ring
= &bp
->rx_ring
[i
];
2597 bp
->tx_ring
= kcalloc(bp
->tx_nr_rings
,
2598 sizeof(struct bnxt_tx_ring_info
),
2603 if (bp
->flags
& BNXT_FLAG_SHARED_RINGS
)
2606 j
= bp
->rx_nr_rings
;
2608 for (i
= 0; i
< bp
->tx_nr_rings
; i
++, j
++) {
2609 bp
->tx_ring
[i
].bnapi
= bp
->bnapi
[j
];
2610 bp
->bnapi
[j
]->tx_ring
= &bp
->tx_ring
[i
];
2613 rc
= bnxt_alloc_stats(bp
);
2617 rc
= bnxt_alloc_ntp_fltrs(bp
);
2621 rc
= bnxt_alloc_vnics(bp
);
2626 bnxt_init_ring_struct(bp
);
2628 rc
= bnxt_alloc_rx_rings(bp
);
2632 rc
= bnxt_alloc_tx_rings(bp
);
2636 rc
= bnxt_alloc_cp_rings(bp
);
2640 bp
->vnic_info
[0].flags
|= BNXT_VNIC_RSS_FLAG
| BNXT_VNIC_MCAST_FLAG
|
2641 BNXT_VNIC_UCAST_FLAG
;
2642 rc
= bnxt_alloc_vnic_attributes(bp
);
2648 bnxt_free_mem(bp
, true);
2652 void bnxt_hwrm_cmd_hdr_init(struct bnxt
*bp
, void *request
, u16 req_type
,
2653 u16 cmpl_ring
, u16 target_id
)
2655 struct input
*req
= request
;
2657 req
->req_type
= cpu_to_le16(req_type
);
2658 req
->cmpl_ring
= cpu_to_le16(cmpl_ring
);
2659 req
->target_id
= cpu_to_le16(target_id
);
2660 req
->resp_addr
= cpu_to_le64(bp
->hwrm_cmd_resp_dma_addr
);
2663 static int bnxt_hwrm_do_send_msg(struct bnxt
*bp
, void *msg
, u32 msg_len
,
2664 int timeout
, bool silent
)
2666 int i
, intr_process
, rc
;
2667 struct input
*req
= msg
;
2669 __le32
*resp_len
, *valid
;
2670 u16 cp_ring_id
, len
= 0;
2671 struct hwrm_err_output
*resp
= bp
->hwrm_cmd_resp_addr
;
2673 req
->seq_id
= cpu_to_le16(bp
->hwrm_cmd_seq
++);
2674 memset(resp
, 0, PAGE_SIZE
);
2675 cp_ring_id
= le16_to_cpu(req
->cmpl_ring
);
2676 intr_process
= (cp_ring_id
== INVALID_HW_RING_ID
) ? 0 : 1;
2678 /* Write request msg to hwrm channel */
2679 __iowrite32_copy(bp
->bar0
, data
, msg_len
/ 4);
2681 for (i
= msg_len
; i
< BNXT_HWRM_MAX_REQ_LEN
; i
+= 4)
2682 writel(0, bp
->bar0
+ i
);
2684 /* currently supports only one outstanding message */
2686 bp
->hwrm_intr_seq_id
= le16_to_cpu(req
->seq_id
);
2688 /* Ring channel doorbell */
2689 writel(1, bp
->bar0
+ 0x100);
2692 timeout
= DFLT_HWRM_CMD_TIMEOUT
;
2696 /* Wait until hwrm response cmpl interrupt is processed */
2697 while (bp
->hwrm_intr_seq_id
!= HWRM_SEQ_ID_INVALID
&&
2699 usleep_range(600, 800);
2702 if (bp
->hwrm_intr_seq_id
!= HWRM_SEQ_ID_INVALID
) {
2703 netdev_err(bp
->dev
, "Resp cmpl intr err msg: 0x%x\n",
2704 le16_to_cpu(req
->req_type
));
2708 /* Check if response len is updated */
2709 resp_len
= bp
->hwrm_cmd_resp_addr
+ HWRM_RESP_LEN_OFFSET
;
2710 for (i
= 0; i
< timeout
; i
++) {
2711 len
= (le32_to_cpu(*resp_len
) & HWRM_RESP_LEN_MASK
) >>
2715 usleep_range(600, 800);
2719 netdev_err(bp
->dev
, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
2720 timeout
, le16_to_cpu(req
->req_type
),
2721 le16_to_cpu(req
->seq_id
), *resp_len
);
2725 /* Last word of resp contains valid bit */
2726 valid
= bp
->hwrm_cmd_resp_addr
+ len
- 4;
2727 for (i
= 0; i
< timeout
; i
++) {
2728 if (le32_to_cpu(*valid
) & HWRM_RESP_VALID_MASK
)
2730 usleep_range(600, 800);
2734 netdev_err(bp
->dev
, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
2735 timeout
, le16_to_cpu(req
->req_type
),
2736 le16_to_cpu(req
->seq_id
), len
, *valid
);
2741 rc
= le16_to_cpu(resp
->error_code
);
2743 netdev_err(bp
->dev
, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
2744 le16_to_cpu(resp
->req_type
),
2745 le16_to_cpu(resp
->seq_id
), rc
);
2749 int _hwrm_send_message(struct bnxt
*bp
, void *msg
, u32 msg_len
, int timeout
)
2751 return bnxt_hwrm_do_send_msg(bp
, msg
, msg_len
, timeout
, false);
2754 int hwrm_send_message(struct bnxt
*bp
, void *msg
, u32 msg_len
, int timeout
)
2758 mutex_lock(&bp
->hwrm_cmd_lock
);
2759 rc
= _hwrm_send_message(bp
, msg
, msg_len
, timeout
);
2760 mutex_unlock(&bp
->hwrm_cmd_lock
);
2764 int hwrm_send_message_silent(struct bnxt
*bp
, void *msg
, u32 msg_len
,
2769 mutex_lock(&bp
->hwrm_cmd_lock
);
2770 rc
= bnxt_hwrm_do_send_msg(bp
, msg
, msg_len
, timeout
, true);
2771 mutex_unlock(&bp
->hwrm_cmd_lock
);
2775 static int bnxt_hwrm_func_drv_rgtr(struct bnxt
*bp
)
2777 struct hwrm_func_drv_rgtr_input req
= {0};
2780 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_DRV_RGTR
, -1, -1);
2783 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE
|
2784 FUNC_DRV_RGTR_REQ_ENABLES_VER
|
2785 FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD
);
2787 /* TODO: current async event fwd bits are not defined and the firmware
2788 * only checks if it is non-zero to enable async event forwarding
2790 req
.async_event_fwd
[0] |= cpu_to_le32(1);
2791 req
.os_type
= cpu_to_le16(1);
2792 req
.ver_maj
= DRV_VER_MAJ
;
2793 req
.ver_min
= DRV_VER_MIN
;
2794 req
.ver_upd
= DRV_VER_UPD
;
2797 DECLARE_BITMAP(vf_req_snif_bmap
, 256);
2798 u32
*data
= (u32
*)vf_req_snif_bmap
;
2800 memset(vf_req_snif_bmap
, 0, sizeof(vf_req_snif_bmap
));
2801 for (i
= 0; i
< ARRAY_SIZE(bnxt_vf_req_snif
); i
++)
2802 __set_bit(bnxt_vf_req_snif
[i
], vf_req_snif_bmap
);
2804 for (i
= 0; i
< 8; i
++)
2805 req
.vf_req_fwd
[i
] = cpu_to_le32(data
[i
]);
2808 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD
);
2811 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2814 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt
*bp
)
2816 struct hwrm_func_drv_unrgtr_input req
= {0};
2818 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_DRV_UNRGTR
, -1, -1);
2819 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2822 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt
*bp
, u8 tunnel_type
)
2825 struct hwrm_tunnel_dst_port_free_input req
= {0};
2827 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_TUNNEL_DST_PORT_FREE
, -1, -1);
2828 req
.tunnel_type
= tunnel_type
;
2830 switch (tunnel_type
) {
2831 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
:
2832 req
.tunnel_dst_port_id
= bp
->vxlan_fw_dst_port_id
;
2834 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
:
2835 req
.tunnel_dst_port_id
= bp
->nge_fw_dst_port_id
;
2841 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2843 netdev_err(bp
->dev
, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
2848 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt
*bp
, __be16 port
,
2852 struct hwrm_tunnel_dst_port_alloc_input req
= {0};
2853 struct hwrm_tunnel_dst_port_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
2855 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_TUNNEL_DST_PORT_ALLOC
, -1, -1);
2857 req
.tunnel_type
= tunnel_type
;
2858 req
.tunnel_dst_port_val
= port
;
2860 mutex_lock(&bp
->hwrm_cmd_lock
);
2861 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2863 netdev_err(bp
->dev
, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
2868 if (tunnel_type
& TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN
)
2869 bp
->vxlan_fw_dst_port_id
= resp
->tunnel_dst_port_id
;
2871 else if (tunnel_type
& TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE
)
2872 bp
->nge_fw_dst_port_id
= resp
->tunnel_dst_port_id
;
2874 mutex_unlock(&bp
->hwrm_cmd_lock
);
2878 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt
*bp
, u16 vnic_id
)
2880 struct hwrm_cfa_l2_set_rx_mask_input req
= {0};
2881 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
2883 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_L2_SET_RX_MASK
, -1, -1);
2884 req
.vnic_id
= cpu_to_le32(vnic
->fw_vnic_id
);
2886 req
.num_mc_entries
= cpu_to_le32(vnic
->mc_list_count
);
2887 req
.mc_tbl_addr
= cpu_to_le64(vnic
->mc_list_mapping
);
2888 req
.mask
= cpu_to_le32(vnic
->rx_mask
);
2889 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2892 #ifdef CONFIG_RFS_ACCEL
2893 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt
*bp
,
2894 struct bnxt_ntuple_filter
*fltr
)
2896 struct hwrm_cfa_ntuple_filter_free_input req
= {0};
2898 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_NTUPLE_FILTER_FREE
, -1, -1);
2899 req
.ntuple_filter_id
= fltr
->filter_id
;
2900 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2903 #define BNXT_NTP_FLTR_FLAGS \
2904 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
2905 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
2906 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
2907 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
2908 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
2909 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
2910 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
2911 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
2912 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
2913 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
2914 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
2915 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
2916 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
2917 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
2919 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt
*bp
,
2920 struct bnxt_ntuple_filter
*fltr
)
2923 struct hwrm_cfa_ntuple_filter_alloc_input req
= {0};
2924 struct hwrm_cfa_ntuple_filter_alloc_output
*resp
=
2925 bp
->hwrm_cmd_resp_addr
;
2926 struct flow_keys
*keys
= &fltr
->fkeys
;
2927 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[fltr
->rxq
+ 1];
2929 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_NTUPLE_FILTER_ALLOC
, -1, -1);
2930 req
.l2_filter_id
= bp
->vnic_info
[0].fw_l2_filter_id
[0];
2932 req
.enables
= cpu_to_le32(BNXT_NTP_FLTR_FLAGS
);
2934 req
.ethertype
= htons(ETH_P_IP
);
2935 memcpy(req
.src_macaddr
, fltr
->src_mac_addr
, ETH_ALEN
);
2936 req
.ip_addr_type
= CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4
;
2937 req
.ip_protocol
= keys
->basic
.ip_proto
;
2939 req
.src_ipaddr
[0] = keys
->addrs
.v4addrs
.src
;
2940 req
.src_ipaddr_mask
[0] = cpu_to_be32(0xffffffff);
2941 req
.dst_ipaddr
[0] = keys
->addrs
.v4addrs
.dst
;
2942 req
.dst_ipaddr_mask
[0] = cpu_to_be32(0xffffffff);
2944 req
.src_port
= keys
->ports
.src
;
2945 req
.src_port_mask
= cpu_to_be16(0xffff);
2946 req
.dst_port
= keys
->ports
.dst
;
2947 req
.dst_port_mask
= cpu_to_be16(0xffff);
2949 req
.dst_id
= cpu_to_le16(vnic
->fw_vnic_id
);
2950 mutex_lock(&bp
->hwrm_cmd_lock
);
2951 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2953 fltr
->filter_id
= resp
->ntuple_filter_id
;
2954 mutex_unlock(&bp
->hwrm_cmd_lock
);
2959 static int bnxt_hwrm_set_vnic_filter(struct bnxt
*bp
, u16 vnic_id
, u16 idx
,
2963 struct hwrm_cfa_l2_filter_alloc_input req
= {0};
2964 struct hwrm_cfa_l2_filter_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
2966 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_L2_FILTER_ALLOC
, -1, -1);
2967 req
.flags
= cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX
|
2968 CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST
);
2969 req
.dst_id
= cpu_to_le16(bp
->vnic_info
[vnic_id
].fw_vnic_id
);
2971 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR
|
2972 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID
|
2973 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK
);
2974 memcpy(req
.l2_addr
, mac_addr
, ETH_ALEN
);
2975 req
.l2_addr_mask
[0] = 0xff;
2976 req
.l2_addr_mask
[1] = 0xff;
2977 req
.l2_addr_mask
[2] = 0xff;
2978 req
.l2_addr_mask
[3] = 0xff;
2979 req
.l2_addr_mask
[4] = 0xff;
2980 req
.l2_addr_mask
[5] = 0xff;
2982 mutex_lock(&bp
->hwrm_cmd_lock
);
2983 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2985 bp
->vnic_info
[vnic_id
].fw_l2_filter_id
[idx
] =
2987 mutex_unlock(&bp
->hwrm_cmd_lock
);
2991 static int bnxt_hwrm_clear_vnic_filter(struct bnxt
*bp
)
2993 u16 i
, j
, num_of_vnics
= 1; /* only vnic 0 supported */
2996 /* Any associated ntuple filters will also be cleared by firmware. */
2997 mutex_lock(&bp
->hwrm_cmd_lock
);
2998 for (i
= 0; i
< num_of_vnics
; i
++) {
2999 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[i
];
3001 for (j
= 0; j
< vnic
->uc_filter_count
; j
++) {
3002 struct hwrm_cfa_l2_filter_free_input req
= {0};
3004 bnxt_hwrm_cmd_hdr_init(bp
, &req
,
3005 HWRM_CFA_L2_FILTER_FREE
, -1, -1);
3007 req
.l2_filter_id
= vnic
->fw_l2_filter_id
[j
];
3009 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3012 vnic
->uc_filter_count
= 0;
3014 mutex_unlock(&bp
->hwrm_cmd_lock
);
3019 static int bnxt_hwrm_vnic_set_tpa(struct bnxt
*bp
, u16 vnic_id
, u32 tpa_flags
)
3021 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
3022 struct hwrm_vnic_tpa_cfg_input req
= {0};
3024 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_TPA_CFG
, -1, -1);
3027 u16 mss
= bp
->dev
->mtu
- 40;
3028 u32 nsegs
, n
, segs
= 0, flags
;
3030 flags
= VNIC_TPA_CFG_REQ_FLAGS_TPA
|
3031 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA
|
3032 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE
|
3033 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN
|
3034 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ
;
3035 if (tpa_flags
& BNXT_FLAG_GRO
)
3036 flags
|= VNIC_TPA_CFG_REQ_FLAGS_GRO
;
3038 req
.flags
= cpu_to_le32(flags
);
3041 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS
|
3042 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS
|
3043 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN
);
3045 /* Number of segs are log2 units, and first packet is not
3046 * included as part of this units.
3048 if (mss
<= BNXT_RX_PAGE_SIZE
) {
3049 n
= BNXT_RX_PAGE_SIZE
/ mss
;
3050 nsegs
= (MAX_SKB_FRAGS
- 1) * n
;
3052 n
= mss
/ BNXT_RX_PAGE_SIZE
;
3053 if (mss
& (BNXT_RX_PAGE_SIZE
- 1))
3055 nsegs
= (MAX_SKB_FRAGS
- n
) / n
;
3058 segs
= ilog2(nsegs
);
3059 req
.max_agg_segs
= cpu_to_le16(segs
);
3060 req
.max_aggs
= cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX
);
3062 req
.min_agg_len
= cpu_to_le32(512);
3064 req
.vnic_id
= cpu_to_le16(vnic
->fw_vnic_id
);
3066 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3069 static int bnxt_hwrm_vnic_set_rss(struct bnxt
*bp
, u16 vnic_id
, bool set_rss
)
3071 u32 i
, j
, max_rings
;
3072 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
3073 struct hwrm_vnic_rss_cfg_input req
= {0};
3075 if (vnic
->fw_rss_cos_lb_ctx
== INVALID_HW_RING_ID
)
3078 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_RSS_CFG
, -1, -1);
3080 vnic
->hash_type
= BNXT_RSS_HASH_TYPE_FLAG_IPV4
|
3081 BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV4
|
3082 BNXT_RSS_HASH_TYPE_FLAG_IPV6
|
3083 BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV6
;
3085 req
.hash_type
= cpu_to_le32(vnic
->hash_type
);
3087 if (vnic
->flags
& BNXT_VNIC_RSS_FLAG
)
3088 max_rings
= bp
->rx_nr_rings
;
3092 /* Fill the RSS indirection table with ring group ids */
3093 for (i
= 0, j
= 0; i
< HW_HASH_INDEX_SIZE
; i
++, j
++) {
3096 vnic
->rss_table
[i
] = cpu_to_le16(vnic
->fw_grp_ids
[j
]);
3099 req
.ring_grp_tbl_addr
= cpu_to_le64(vnic
->rss_table_dma_addr
);
3100 req
.hash_key_tbl_addr
=
3101 cpu_to_le64(vnic
->rss_hash_key_dma_addr
);
3103 req
.rss_ctx_idx
= cpu_to_le16(vnic
->fw_rss_cos_lb_ctx
);
3104 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3107 static int bnxt_hwrm_vnic_set_hds(struct bnxt
*bp
, u16 vnic_id
)
3109 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
3110 struct hwrm_vnic_plcmodes_cfg_input req
= {0};
3112 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_PLCMODES_CFG
, -1, -1);
3113 req
.flags
= cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT
|
3114 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4
|
3115 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6
);
3117 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID
|
3118 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID
);
3119 /* thresholds not implemented in firmware yet */
3120 req
.jumbo_thresh
= cpu_to_le16(bp
->rx_copy_thresh
);
3121 req
.hds_threshold
= cpu_to_le16(bp
->rx_copy_thresh
);
3122 req
.vnic_id
= cpu_to_le32(vnic
->fw_vnic_id
);
3123 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3126 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt
*bp
, u16 vnic_id
)
3128 struct hwrm_vnic_rss_cos_lb_ctx_free_input req
= {0};
3130 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_RSS_COS_LB_CTX_FREE
, -1, -1);
3131 req
.rss_cos_lb_ctx_id
=
3132 cpu_to_le16(bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
);
3134 hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3135 bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
= INVALID_HW_RING_ID
;
3138 static void bnxt_hwrm_vnic_ctx_free(struct bnxt
*bp
)
3142 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
3143 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[i
];
3145 if (vnic
->fw_rss_cos_lb_ctx
!= INVALID_HW_RING_ID
)
3146 bnxt_hwrm_vnic_ctx_free_one(bp
, i
);
3148 bp
->rsscos_nr_ctxs
= 0;
3151 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt
*bp
, u16 vnic_id
)
3154 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req
= {0};
3155 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output
*resp
=
3156 bp
->hwrm_cmd_resp_addr
;
3158 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC
, -1,
3161 mutex_lock(&bp
->hwrm_cmd_lock
);
3162 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3164 bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
=
3165 le16_to_cpu(resp
->rss_cos_lb_ctx_id
);
3166 mutex_unlock(&bp
->hwrm_cmd_lock
);
3171 static int bnxt_hwrm_vnic_cfg(struct bnxt
*bp
, u16 vnic_id
)
3173 unsigned int ring
= 0, grp_idx
;
3174 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
3175 struct hwrm_vnic_cfg_input req
= {0};
3177 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_CFG
, -1, -1);
3178 /* Only RSS support for now TBD: COS & LB */
3179 req
.enables
= cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP
|
3180 VNIC_CFG_REQ_ENABLES_RSS_RULE
);
3181 req
.rss_rule
= cpu_to_le16(vnic
->fw_rss_cos_lb_ctx
);
3182 req
.cos_rule
= cpu_to_le16(0xffff);
3183 if (vnic
->flags
& BNXT_VNIC_RSS_FLAG
)
3185 else if (vnic
->flags
& BNXT_VNIC_RFS_FLAG
)
3188 grp_idx
= bp
->rx_ring
[ring
].bnapi
->index
;
3189 req
.vnic_id
= cpu_to_le16(vnic
->fw_vnic_id
);
3190 req
.dflt_ring_grp
= cpu_to_le16(bp
->grp_info
[grp_idx
].fw_grp_id
);
3192 req
.lb_rule
= cpu_to_le16(0xffff);
3193 req
.mru
= cpu_to_le16(bp
->dev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+
3196 if (bp
->flags
& BNXT_FLAG_STRIP_VLAN
)
3197 req
.flags
|= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE
);
3199 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3202 static int bnxt_hwrm_vnic_free_one(struct bnxt
*bp
, u16 vnic_id
)
3206 if (bp
->vnic_info
[vnic_id
].fw_vnic_id
!= INVALID_HW_RING_ID
) {
3207 struct hwrm_vnic_free_input req
= {0};
3209 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_FREE
, -1, -1);
3211 cpu_to_le32(bp
->vnic_info
[vnic_id
].fw_vnic_id
);
3213 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3216 bp
->vnic_info
[vnic_id
].fw_vnic_id
= INVALID_HW_RING_ID
;
3221 static void bnxt_hwrm_vnic_free(struct bnxt
*bp
)
3225 for (i
= 0; i
< bp
->nr_vnics
; i
++)
3226 bnxt_hwrm_vnic_free_one(bp
, i
);
3229 static int bnxt_hwrm_vnic_alloc(struct bnxt
*bp
, u16 vnic_id
,
3230 unsigned int start_rx_ring_idx
,
3231 unsigned int nr_rings
)
3234 unsigned int i
, j
, grp_idx
, end_idx
= start_rx_ring_idx
+ nr_rings
;
3235 struct hwrm_vnic_alloc_input req
= {0};
3236 struct hwrm_vnic_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3238 /* map ring groups to this vnic */
3239 for (i
= start_rx_ring_idx
, j
= 0; i
< end_idx
; i
++, j
++) {
3240 grp_idx
= bp
->rx_ring
[i
].bnapi
->index
;
3241 if (bp
->grp_info
[grp_idx
].fw_grp_id
== INVALID_HW_RING_ID
) {
3242 netdev_err(bp
->dev
, "Not enough ring groups avail:%x req:%x\n",
3246 bp
->vnic_info
[vnic_id
].fw_grp_ids
[j
] =
3247 bp
->grp_info
[grp_idx
].fw_grp_id
;
3250 bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
= INVALID_HW_RING_ID
;
3252 req
.flags
= cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT
);
3254 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_ALLOC
, -1, -1);
3256 mutex_lock(&bp
->hwrm_cmd_lock
);
3257 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3259 bp
->vnic_info
[vnic_id
].fw_vnic_id
= le32_to_cpu(resp
->vnic_id
);
3260 mutex_unlock(&bp
->hwrm_cmd_lock
);
3264 static int bnxt_hwrm_ring_grp_alloc(struct bnxt
*bp
)
3269 mutex_lock(&bp
->hwrm_cmd_lock
);
3270 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3271 struct hwrm_ring_grp_alloc_input req
= {0};
3272 struct hwrm_ring_grp_alloc_output
*resp
=
3273 bp
->hwrm_cmd_resp_addr
;
3274 unsigned int grp_idx
= bp
->rx_ring
[i
].bnapi
->index
;
3276 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_GRP_ALLOC
, -1, -1);
3278 req
.cr
= cpu_to_le16(bp
->grp_info
[grp_idx
].cp_fw_ring_id
);
3279 req
.rr
= cpu_to_le16(bp
->grp_info
[grp_idx
].rx_fw_ring_id
);
3280 req
.ar
= cpu_to_le16(bp
->grp_info
[grp_idx
].agg_fw_ring_id
);
3281 req
.sc
= cpu_to_le16(bp
->grp_info
[grp_idx
].fw_stats_ctx
);
3283 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3288 bp
->grp_info
[grp_idx
].fw_grp_id
=
3289 le32_to_cpu(resp
->ring_group_id
);
3291 mutex_unlock(&bp
->hwrm_cmd_lock
);
3295 static int bnxt_hwrm_ring_grp_free(struct bnxt
*bp
)
3299 struct hwrm_ring_grp_free_input req
= {0};
3304 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_GRP_FREE
, -1, -1);
3306 mutex_lock(&bp
->hwrm_cmd_lock
);
3307 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3308 if (bp
->grp_info
[i
].fw_grp_id
== INVALID_HW_RING_ID
)
3311 cpu_to_le32(bp
->grp_info
[i
].fw_grp_id
);
3313 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3317 bp
->grp_info
[i
].fw_grp_id
= INVALID_HW_RING_ID
;
3319 mutex_unlock(&bp
->hwrm_cmd_lock
);
3323 static int hwrm_ring_alloc_send_msg(struct bnxt
*bp
,
3324 struct bnxt_ring_struct
*ring
,
3325 u32 ring_type
, u32 map_index
,
3328 int rc
= 0, err
= 0;
3329 struct hwrm_ring_alloc_input req
= {0};
3330 struct hwrm_ring_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3333 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_ALLOC
, -1, -1);
3336 if (ring
->nr_pages
> 1) {
3337 req
.page_tbl_addr
= cpu_to_le64(ring
->pg_tbl_map
);
3338 /* Page size is in log2 units */
3339 req
.page_size
= BNXT_PAGE_SHIFT
;
3340 req
.page_tbl_depth
= 1;
3342 req
.page_tbl_addr
= cpu_to_le64(ring
->dma_arr
[0]);
3345 /* Association of ring index with doorbell index and MSIX number */
3346 req
.logical_id
= cpu_to_le16(map_index
);
3348 switch (ring_type
) {
3349 case HWRM_RING_ALLOC_TX
:
3350 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_TX
;
3351 /* Association of transmit ring with completion ring */
3353 cpu_to_le16(bp
->grp_info
[map_index
].cp_fw_ring_id
);
3354 req
.length
= cpu_to_le32(bp
->tx_ring_mask
+ 1);
3355 req
.stat_ctx_id
= cpu_to_le32(stats_ctx_id
);
3356 req
.queue_id
= cpu_to_le16(ring
->queue_id
);
3358 case HWRM_RING_ALLOC_RX
:
3359 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_RX
;
3360 req
.length
= cpu_to_le32(bp
->rx_ring_mask
+ 1);
3362 case HWRM_RING_ALLOC_AGG
:
3363 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_RX
;
3364 req
.length
= cpu_to_le32(bp
->rx_agg_ring_mask
+ 1);
3366 case HWRM_RING_ALLOC_CMPL
:
3367 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_CMPL
;
3368 req
.length
= cpu_to_le32(bp
->cp_ring_mask
+ 1);
3369 if (bp
->flags
& BNXT_FLAG_USING_MSIX
)
3370 req
.int_mode
= RING_ALLOC_REQ_INT_MODE_MSIX
;
3373 netdev_err(bp
->dev
, "hwrm alloc invalid ring type %d\n",
3378 mutex_lock(&bp
->hwrm_cmd_lock
);
3379 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3380 err
= le16_to_cpu(resp
->error_code
);
3381 ring_id
= le16_to_cpu(resp
->ring_id
);
3382 mutex_unlock(&bp
->hwrm_cmd_lock
);
3385 switch (ring_type
) {
3386 case RING_FREE_REQ_RING_TYPE_CMPL
:
3387 netdev_err(bp
->dev
, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
3391 case RING_FREE_REQ_RING_TYPE_RX
:
3392 netdev_err(bp
->dev
, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
3396 case RING_FREE_REQ_RING_TYPE_TX
:
3397 netdev_err(bp
->dev
, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
3402 netdev_err(bp
->dev
, "Invalid ring\n");
3406 ring
->fw_ring_id
= ring_id
;
3410 static int bnxt_hwrm_ring_alloc(struct bnxt
*bp
)
3414 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3415 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3416 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3417 struct bnxt_ring_struct
*ring
= &cpr
->cp_ring_struct
;
3419 cpr
->cp_doorbell
= bp
->bar1
+ i
* 0x80;
3420 rc
= hwrm_ring_alloc_send_msg(bp
, ring
, HWRM_RING_ALLOC_CMPL
, i
,
3421 INVALID_STATS_CTX_ID
);
3424 BNXT_CP_DB(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
3425 bp
->grp_info
[i
].cp_fw_ring_id
= ring
->fw_ring_id
;
3428 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
3429 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
3430 struct bnxt_ring_struct
*ring
= &txr
->tx_ring_struct
;
3431 u32 map_idx
= txr
->bnapi
->index
;
3432 u16 fw_stats_ctx
= bp
->grp_info
[map_idx
].fw_stats_ctx
;
3434 rc
= hwrm_ring_alloc_send_msg(bp
, ring
, HWRM_RING_ALLOC_TX
,
3435 map_idx
, fw_stats_ctx
);
3438 txr
->tx_doorbell
= bp
->bar1
+ map_idx
* 0x80;
3441 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3442 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
3443 struct bnxt_ring_struct
*ring
= &rxr
->rx_ring_struct
;
3444 u32 map_idx
= rxr
->bnapi
->index
;
3446 rc
= hwrm_ring_alloc_send_msg(bp
, ring
, HWRM_RING_ALLOC_RX
,
3447 map_idx
, INVALID_STATS_CTX_ID
);
3450 rxr
->rx_doorbell
= bp
->bar1
+ map_idx
* 0x80;
3451 writel(DB_KEY_RX
| rxr
->rx_prod
, rxr
->rx_doorbell
);
3452 bp
->grp_info
[map_idx
].rx_fw_ring_id
= ring
->fw_ring_id
;
3455 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
) {
3456 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3457 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
3458 struct bnxt_ring_struct
*ring
=
3459 &rxr
->rx_agg_ring_struct
;
3460 u32 grp_idx
= rxr
->bnapi
->index
;
3461 u32 map_idx
= grp_idx
+ bp
->rx_nr_rings
;
3463 rc
= hwrm_ring_alloc_send_msg(bp
, ring
,
3464 HWRM_RING_ALLOC_AGG
,
3466 INVALID_STATS_CTX_ID
);
3470 rxr
->rx_agg_doorbell
= bp
->bar1
+ map_idx
* 0x80;
3471 writel(DB_KEY_RX
| rxr
->rx_agg_prod
,
3472 rxr
->rx_agg_doorbell
);
3473 bp
->grp_info
[grp_idx
].agg_fw_ring_id
= ring
->fw_ring_id
;
3480 static int hwrm_ring_free_send_msg(struct bnxt
*bp
,
3481 struct bnxt_ring_struct
*ring
,
3482 u32 ring_type
, int cmpl_ring_id
)
3485 struct hwrm_ring_free_input req
= {0};
3486 struct hwrm_ring_free_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3489 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_FREE
, cmpl_ring_id
, -1);
3490 req
.ring_type
= ring_type
;
3491 req
.ring_id
= cpu_to_le16(ring
->fw_ring_id
);
3493 mutex_lock(&bp
->hwrm_cmd_lock
);
3494 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3495 error_code
= le16_to_cpu(resp
->error_code
);
3496 mutex_unlock(&bp
->hwrm_cmd_lock
);
3498 if (rc
|| error_code
) {
3499 switch (ring_type
) {
3500 case RING_FREE_REQ_RING_TYPE_CMPL
:
3501 netdev_err(bp
->dev
, "hwrm_ring_free cp failed. rc:%d\n",
3504 case RING_FREE_REQ_RING_TYPE_RX
:
3505 netdev_err(bp
->dev
, "hwrm_ring_free rx failed. rc:%d\n",
3508 case RING_FREE_REQ_RING_TYPE_TX
:
3509 netdev_err(bp
->dev
, "hwrm_ring_free tx failed. rc:%d\n",
3513 netdev_err(bp
->dev
, "Invalid ring\n");
3520 static void bnxt_hwrm_ring_free(struct bnxt
*bp
, bool close_path
)
3527 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
3528 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
3529 struct bnxt_ring_struct
*ring
= &txr
->tx_ring_struct
;
3530 u32 grp_idx
= txr
->bnapi
->index
;
3531 u32 cmpl_ring_id
= bp
->grp_info
[grp_idx
].cp_fw_ring_id
;
3533 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
3534 hwrm_ring_free_send_msg(bp
, ring
,
3535 RING_FREE_REQ_RING_TYPE_TX
,
3536 close_path
? cmpl_ring_id
:
3537 INVALID_HW_RING_ID
);
3538 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
3542 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3543 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
3544 struct bnxt_ring_struct
*ring
= &rxr
->rx_ring_struct
;
3545 u32 grp_idx
= rxr
->bnapi
->index
;
3546 u32 cmpl_ring_id
= bp
->grp_info
[grp_idx
].cp_fw_ring_id
;
3548 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
3549 hwrm_ring_free_send_msg(bp
, ring
,
3550 RING_FREE_REQ_RING_TYPE_RX
,
3551 close_path
? cmpl_ring_id
:
3552 INVALID_HW_RING_ID
);
3553 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
3554 bp
->grp_info
[grp_idx
].rx_fw_ring_id
=
3559 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3560 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
3561 struct bnxt_ring_struct
*ring
= &rxr
->rx_agg_ring_struct
;
3562 u32 grp_idx
= rxr
->bnapi
->index
;
3563 u32 cmpl_ring_id
= bp
->grp_info
[grp_idx
].cp_fw_ring_id
;
3565 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
3566 hwrm_ring_free_send_msg(bp
, ring
,
3567 RING_FREE_REQ_RING_TYPE_RX
,
3568 close_path
? cmpl_ring_id
:
3569 INVALID_HW_RING_ID
);
3570 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
3571 bp
->grp_info
[grp_idx
].agg_fw_ring_id
=
3576 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3577 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3578 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3579 struct bnxt_ring_struct
*ring
= &cpr
->cp_ring_struct
;
3581 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
3582 hwrm_ring_free_send_msg(bp
, ring
,
3583 RING_FREE_REQ_RING_TYPE_CMPL
,
3584 INVALID_HW_RING_ID
);
3585 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
3586 bp
->grp_info
[i
].cp_fw_ring_id
= INVALID_HW_RING_ID
;
3591 static void bnxt_hwrm_set_coal_params(struct bnxt
*bp
, u32 max_bufs
,
3592 u32 buf_tmrs
, u16 flags
,
3593 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input
*req
)
3595 req
->flags
= cpu_to_le16(flags
);
3596 req
->num_cmpl_dma_aggr
= cpu_to_le16((u16
)max_bufs
);
3597 req
->num_cmpl_dma_aggr_during_int
= cpu_to_le16(max_bufs
>> 16);
3598 req
->cmpl_aggr_dma_tmr
= cpu_to_le16((u16
)buf_tmrs
);
3599 req
->cmpl_aggr_dma_tmr_during_int
= cpu_to_le16(buf_tmrs
>> 16);
3600 /* Minimum time between 2 interrupts set to buf_tmr x 2 */
3601 req
->int_lat_tmr_min
= cpu_to_le16((u16
)buf_tmrs
* 2);
3602 req
->int_lat_tmr_max
= cpu_to_le16((u16
)buf_tmrs
* 4);
3603 req
->num_cmpl_aggr_int
= cpu_to_le16((u16
)max_bufs
* 4);
3606 int bnxt_hwrm_set_coal(struct bnxt
*bp
)
3609 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx
= {0},
3611 u16 max_buf
, max_buf_irq
;
3612 u16 buf_tmr
, buf_tmr_irq
;
3615 bnxt_hwrm_cmd_hdr_init(bp
, &req_rx
,
3616 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS
, -1, -1);
3617 bnxt_hwrm_cmd_hdr_init(bp
, &req_tx
,
3618 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS
, -1, -1);
3620 /* Each rx completion (2 records) should be DMAed immediately.
3621 * DMA 1/4 of the completion buffers at a time.
3623 max_buf
= min_t(u16
, bp
->rx_coal_bufs
/ 4, 2);
3624 /* max_buf must not be zero */
3625 max_buf
= clamp_t(u16
, max_buf
, 1, 63);
3626 max_buf_irq
= clamp_t(u16
, bp
->rx_coal_bufs_irq
, 1, 63);
3627 buf_tmr
= BNXT_USEC_TO_COAL_TIMER(bp
->rx_coal_ticks
);
3628 /* buf timer set to 1/4 of interrupt timer */
3629 buf_tmr
= max_t(u16
, buf_tmr
/ 4, 1);
3630 buf_tmr_irq
= BNXT_USEC_TO_COAL_TIMER(bp
->rx_coal_ticks_irq
);
3631 buf_tmr_irq
= max_t(u16
, buf_tmr_irq
, 1);
3633 flags
= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET
;
3635 /* RING_IDLE generates more IRQs for lower latency. Enable it only
3636 * if coal_ticks is less than 25 us.
3638 if (bp
->rx_coal_ticks
< 25)
3639 flags
|= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE
;
3641 bnxt_hwrm_set_coal_params(bp
, max_buf_irq
<< 16 | max_buf
,
3642 buf_tmr_irq
<< 16 | buf_tmr
, flags
, &req_rx
);
3644 /* max_buf must not be zero */
3645 max_buf
= clamp_t(u16
, bp
->tx_coal_bufs
, 1, 63);
3646 max_buf_irq
= clamp_t(u16
, bp
->tx_coal_bufs_irq
, 1, 63);
3647 buf_tmr
= BNXT_USEC_TO_COAL_TIMER(bp
->tx_coal_ticks
);
3648 /* buf timer set to 1/4 of interrupt timer */
3649 buf_tmr
= max_t(u16
, buf_tmr
/ 4, 1);
3650 buf_tmr_irq
= BNXT_USEC_TO_COAL_TIMER(bp
->tx_coal_ticks_irq
);
3651 buf_tmr_irq
= max_t(u16
, buf_tmr_irq
, 1);
3653 flags
= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET
;
3654 bnxt_hwrm_set_coal_params(bp
, max_buf_irq
<< 16 | max_buf
,
3655 buf_tmr_irq
<< 16 | buf_tmr
, flags
, &req_tx
);
3657 mutex_lock(&bp
->hwrm_cmd_lock
);
3658 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3659 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3662 if (!bnapi
->rx_ring
)
3664 req
->ring_id
= cpu_to_le16(bp
->grp_info
[i
].cp_fw_ring_id
);
3666 rc
= _hwrm_send_message(bp
, req
, sizeof(*req
),
3671 mutex_unlock(&bp
->hwrm_cmd_lock
);
3675 static int bnxt_hwrm_stat_ctx_free(struct bnxt
*bp
)
3678 struct hwrm_stat_ctx_free_input req
= {0};
3683 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_STAT_CTX_FREE
, -1, -1);
3685 mutex_lock(&bp
->hwrm_cmd_lock
);
3686 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3687 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3688 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3690 if (cpr
->hw_stats_ctx_id
!= INVALID_STATS_CTX_ID
) {
3691 req
.stat_ctx_id
= cpu_to_le32(cpr
->hw_stats_ctx_id
);
3693 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3698 cpr
->hw_stats_ctx_id
= INVALID_STATS_CTX_ID
;
3701 mutex_unlock(&bp
->hwrm_cmd_lock
);
3705 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt
*bp
)
3708 struct hwrm_stat_ctx_alloc_input req
= {0};
3709 struct hwrm_stat_ctx_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3711 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_STAT_CTX_ALLOC
, -1, -1);
3713 req
.update_period_ms
= cpu_to_le32(1000);
3715 mutex_lock(&bp
->hwrm_cmd_lock
);
3716 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3717 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3718 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3720 req
.stats_dma_addr
= cpu_to_le64(cpr
->hw_stats_map
);
3722 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3727 cpr
->hw_stats_ctx_id
= le32_to_cpu(resp
->stat_ctx_id
);
3729 bp
->grp_info
[i
].fw_stats_ctx
= cpr
->hw_stats_ctx_id
;
3731 mutex_unlock(&bp
->hwrm_cmd_lock
);
3735 int bnxt_hwrm_func_qcaps(struct bnxt
*bp
)
3738 struct hwrm_func_qcaps_input req
= {0};
3739 struct hwrm_func_qcaps_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3741 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_QCAPS
, -1, -1);
3742 req
.fid
= cpu_to_le16(0xffff);
3744 mutex_lock(&bp
->hwrm_cmd_lock
);
3745 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3747 goto hwrm_func_qcaps_exit
;
3750 struct bnxt_pf_info
*pf
= &bp
->pf
;
3752 pf
->fw_fid
= le16_to_cpu(resp
->fid
);
3753 pf
->port_id
= le16_to_cpu(resp
->port_id
);
3754 memcpy(pf
->mac_addr
, resp
->perm_mac_address
, ETH_ALEN
);
3755 memcpy(bp
->dev
->dev_addr
, pf
->mac_addr
, ETH_ALEN
);
3756 pf
->max_rsscos_ctxs
= le16_to_cpu(resp
->max_rsscos_ctx
);
3757 pf
->max_cp_rings
= le16_to_cpu(resp
->max_cmpl_rings
);
3758 pf
->max_tx_rings
= le16_to_cpu(resp
->max_tx_rings
);
3759 pf
->max_rx_rings
= le16_to_cpu(resp
->max_rx_rings
);
3760 pf
->max_hw_ring_grps
= le32_to_cpu(resp
->max_hw_ring_grps
);
3761 if (!pf
->max_hw_ring_grps
)
3762 pf
->max_hw_ring_grps
= pf
->max_tx_rings
;
3763 pf
->max_l2_ctxs
= le16_to_cpu(resp
->max_l2_ctxs
);
3764 pf
->max_vnics
= le16_to_cpu(resp
->max_vnics
);
3765 pf
->max_stat_ctxs
= le16_to_cpu(resp
->max_stat_ctx
);
3766 pf
->first_vf_id
= le16_to_cpu(resp
->first_vf_id
);
3767 pf
->max_vfs
= le16_to_cpu(resp
->max_vfs
);
3768 pf
->max_encap_records
= le32_to_cpu(resp
->max_encap_records
);
3769 pf
->max_decap_records
= le32_to_cpu(resp
->max_decap_records
);
3770 pf
->max_tx_em_flows
= le32_to_cpu(resp
->max_tx_em_flows
);
3771 pf
->max_tx_wm_flows
= le32_to_cpu(resp
->max_tx_wm_flows
);
3772 pf
->max_rx_em_flows
= le32_to_cpu(resp
->max_rx_em_flows
);
3773 pf
->max_rx_wm_flows
= le32_to_cpu(resp
->max_rx_wm_flows
);
3775 #ifdef CONFIG_BNXT_SRIOV
3776 struct bnxt_vf_info
*vf
= &bp
->vf
;
3778 vf
->fw_fid
= le16_to_cpu(resp
->fid
);
3779 memcpy(vf
->mac_addr
, resp
->perm_mac_address
, ETH_ALEN
);
3780 if (is_valid_ether_addr(vf
->mac_addr
))
3781 /* overwrite netdev dev_adr with admin VF MAC */
3782 memcpy(bp
->dev
->dev_addr
, vf
->mac_addr
, ETH_ALEN
);
3784 random_ether_addr(bp
->dev
->dev_addr
);
3786 vf
->max_rsscos_ctxs
= le16_to_cpu(resp
->max_rsscos_ctx
);
3787 vf
->max_cp_rings
= le16_to_cpu(resp
->max_cmpl_rings
);
3788 vf
->max_tx_rings
= le16_to_cpu(resp
->max_tx_rings
);
3789 vf
->max_rx_rings
= le16_to_cpu(resp
->max_rx_rings
);
3790 vf
->max_hw_ring_grps
= le32_to_cpu(resp
->max_hw_ring_grps
);
3791 if (!vf
->max_hw_ring_grps
)
3792 vf
->max_hw_ring_grps
= vf
->max_tx_rings
;
3793 vf
->max_l2_ctxs
= le16_to_cpu(resp
->max_l2_ctxs
);
3794 vf
->max_vnics
= le16_to_cpu(resp
->max_vnics
);
3795 vf
->max_stat_ctxs
= le16_to_cpu(resp
->max_stat_ctx
);
3799 bp
->tx_push_thresh
= 0;
3801 cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED
))
3802 bp
->tx_push_thresh
= BNXT_TX_PUSH_THRESH
;
3804 hwrm_func_qcaps_exit
:
3805 mutex_unlock(&bp
->hwrm_cmd_lock
);
3809 static int bnxt_hwrm_func_reset(struct bnxt
*bp
)
3811 struct hwrm_func_reset_input req
= {0};
3813 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_RESET
, -1, -1);
3816 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_RESET_TIMEOUT
);
3819 static int bnxt_hwrm_queue_qportcfg(struct bnxt
*bp
)
3822 struct hwrm_queue_qportcfg_input req
= {0};
3823 struct hwrm_queue_qportcfg_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3826 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_QUEUE_QPORTCFG
, -1, -1);
3828 mutex_lock(&bp
->hwrm_cmd_lock
);
3829 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3833 if (!resp
->max_configurable_queues
) {
3837 bp
->max_tc
= resp
->max_configurable_queues
;
3838 if (bp
->max_tc
> BNXT_MAX_QUEUE
)
3839 bp
->max_tc
= BNXT_MAX_QUEUE
;
3841 qptr
= &resp
->queue_id0
;
3842 for (i
= 0; i
< bp
->max_tc
; i
++) {
3843 bp
->q_info
[i
].queue_id
= *qptr
++;
3844 bp
->q_info
[i
].queue_profile
= *qptr
++;
3848 mutex_unlock(&bp
->hwrm_cmd_lock
);
3852 static int bnxt_hwrm_ver_get(struct bnxt
*bp
)
3855 struct hwrm_ver_get_input req
= {0};
3856 struct hwrm_ver_get_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3858 bp
->hwrm_max_req_len
= HWRM_MAX_REQ_LEN
;
3859 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VER_GET
, -1, -1);
3860 req
.hwrm_intf_maj
= HWRM_VERSION_MAJOR
;
3861 req
.hwrm_intf_min
= HWRM_VERSION_MINOR
;
3862 req
.hwrm_intf_upd
= HWRM_VERSION_UPDATE
;
3863 mutex_lock(&bp
->hwrm_cmd_lock
);
3864 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3866 goto hwrm_ver_get_exit
;
3868 memcpy(&bp
->ver_resp
, resp
, sizeof(struct hwrm_ver_get_output
));
3870 if (resp
->hwrm_intf_maj
< 1) {
3871 netdev_warn(bp
->dev
, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
3872 resp
->hwrm_intf_maj
, resp
->hwrm_intf_min
,
3873 resp
->hwrm_intf_upd
);
3874 netdev_warn(bp
->dev
, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
3876 snprintf(bp
->fw_ver_str
, BC_HWRM_STR_LEN
, "%d.%d.%d/%d.%d.%d",
3877 resp
->hwrm_fw_maj
, resp
->hwrm_fw_min
, resp
->hwrm_fw_bld
,
3878 resp
->hwrm_intf_maj
, resp
->hwrm_intf_min
, resp
->hwrm_intf_upd
);
3880 bp
->hwrm_cmd_timeout
= le16_to_cpu(resp
->def_req_timeout
);
3881 if (!bp
->hwrm_cmd_timeout
)
3882 bp
->hwrm_cmd_timeout
= DFLT_HWRM_CMD_TIMEOUT
;
3884 if (resp
->hwrm_intf_maj
>= 1)
3885 bp
->hwrm_max_req_len
= le16_to_cpu(resp
->max_req_win_len
);
3888 mutex_unlock(&bp
->hwrm_cmd_lock
);
3892 static int bnxt_hwrm_port_qstats(struct bnxt
*bp
)
3895 struct bnxt_pf_info
*pf
= &bp
->pf
;
3896 struct hwrm_port_qstats_input req
= {0};
3898 if (!(bp
->flags
& BNXT_FLAG_PORT_STATS
))
3901 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_QSTATS
, -1, -1);
3902 req
.port_id
= cpu_to_le16(pf
->port_id
);
3903 req
.tx_stat_host_addr
= cpu_to_le64(bp
->hw_tx_port_stats_map
);
3904 req
.rx_stat_host_addr
= cpu_to_le64(bp
->hw_rx_port_stats_map
);
3905 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3909 static void bnxt_hwrm_free_tunnel_ports(struct bnxt
*bp
)
3911 if (bp
->vxlan_port_cnt
) {
3912 bnxt_hwrm_tunnel_dst_port_free(
3913 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
);
3915 bp
->vxlan_port_cnt
= 0;
3916 if (bp
->nge_port_cnt
) {
3917 bnxt_hwrm_tunnel_dst_port_free(
3918 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
);
3920 bp
->nge_port_cnt
= 0;
3923 static int bnxt_set_tpa(struct bnxt
*bp
, bool set_tpa
)
3929 tpa_flags
= bp
->flags
& BNXT_FLAG_TPA
;
3930 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
3931 rc
= bnxt_hwrm_vnic_set_tpa(bp
, i
, tpa_flags
);
3933 netdev_err(bp
->dev
, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
3941 static void bnxt_hwrm_clear_vnic_rss(struct bnxt
*bp
)
3945 for (i
= 0; i
< bp
->nr_vnics
; i
++)
3946 bnxt_hwrm_vnic_set_rss(bp
, i
, false);
3949 static void bnxt_hwrm_resource_free(struct bnxt
*bp
, bool close_path
,
3952 if (bp
->vnic_info
) {
3953 bnxt_hwrm_clear_vnic_filter(bp
);
3954 /* clear all RSS setting before free vnic ctx */
3955 bnxt_hwrm_clear_vnic_rss(bp
);
3956 bnxt_hwrm_vnic_ctx_free(bp
);
3957 /* before free the vnic, undo the vnic tpa settings */
3958 if (bp
->flags
& BNXT_FLAG_TPA
)
3959 bnxt_set_tpa(bp
, false);
3960 bnxt_hwrm_vnic_free(bp
);
3962 bnxt_hwrm_ring_free(bp
, close_path
);
3963 bnxt_hwrm_ring_grp_free(bp
);
3965 bnxt_hwrm_stat_ctx_free(bp
);
3966 bnxt_hwrm_free_tunnel_ports(bp
);
3970 static int bnxt_setup_vnic(struct bnxt
*bp
, u16 vnic_id
)
3974 /* allocate context for vnic */
3975 rc
= bnxt_hwrm_vnic_ctx_alloc(bp
, vnic_id
);
3977 netdev_err(bp
->dev
, "hwrm vnic %d alloc failure rc: %x\n",
3979 goto vnic_setup_err
;
3981 bp
->rsscos_nr_ctxs
++;
3983 /* configure default vnic, ring grp */
3984 rc
= bnxt_hwrm_vnic_cfg(bp
, vnic_id
);
3986 netdev_err(bp
->dev
, "hwrm vnic %d cfg failure rc: %x\n",
3988 goto vnic_setup_err
;
3991 /* Enable RSS hashing on vnic */
3992 rc
= bnxt_hwrm_vnic_set_rss(bp
, vnic_id
, true);
3994 netdev_err(bp
->dev
, "hwrm vnic %d set rss failure rc: %x\n",
3996 goto vnic_setup_err
;
3999 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
) {
4000 rc
= bnxt_hwrm_vnic_set_hds(bp
, vnic_id
);
4002 netdev_err(bp
->dev
, "hwrm vnic %d set hds failure rc: %x\n",
4011 static int bnxt_alloc_rfs_vnics(struct bnxt
*bp
)
4013 #ifdef CONFIG_RFS_ACCEL
4016 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
4017 u16 vnic_id
= i
+ 1;
4020 if (vnic_id
>= bp
->nr_vnics
)
4023 bp
->vnic_info
[vnic_id
].flags
|= BNXT_VNIC_RFS_FLAG
;
4024 rc
= bnxt_hwrm_vnic_alloc(bp
, vnic_id
, ring_id
, 1);
4026 netdev_err(bp
->dev
, "hwrm vnic %d alloc failure rc: %x\n",
4030 rc
= bnxt_setup_vnic(bp
, vnic_id
);
4040 static int bnxt_cfg_rx_mode(struct bnxt
*);
4042 static int bnxt_init_chip(struct bnxt
*bp
, bool irq_re_init
)
4047 rc
= bnxt_hwrm_stat_ctx_alloc(bp
);
4049 netdev_err(bp
->dev
, "hwrm stat ctx alloc failure rc: %x\n",
4055 rc
= bnxt_hwrm_ring_alloc(bp
);
4057 netdev_err(bp
->dev
, "hwrm ring alloc failure rc: %x\n", rc
);
4061 rc
= bnxt_hwrm_ring_grp_alloc(bp
);
4063 netdev_err(bp
->dev
, "hwrm_ring_grp alloc failure: %x\n", rc
);
4067 /* default vnic 0 */
4068 rc
= bnxt_hwrm_vnic_alloc(bp
, 0, 0, bp
->rx_nr_rings
);
4070 netdev_err(bp
->dev
, "hwrm vnic alloc failure rc: %x\n", rc
);
4074 rc
= bnxt_setup_vnic(bp
, 0);
4078 if (bp
->flags
& BNXT_FLAG_RFS
) {
4079 rc
= bnxt_alloc_rfs_vnics(bp
);
4084 if (bp
->flags
& BNXT_FLAG_TPA
) {
4085 rc
= bnxt_set_tpa(bp
, true);
4091 bnxt_update_vf_mac(bp
);
4093 /* Filter for default vnic 0 */
4094 rc
= bnxt_hwrm_set_vnic_filter(bp
, 0, 0, bp
->dev
->dev_addr
);
4096 netdev_err(bp
->dev
, "HWRM vnic filter failure rc: %x\n", rc
);
4099 bp
->vnic_info
[0].uc_filter_count
= 1;
4101 bp
->vnic_info
[0].rx_mask
= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST
;
4103 if ((bp
->dev
->flags
& IFF_PROMISC
) && BNXT_PF(bp
))
4104 bp
->vnic_info
[0].rx_mask
|=
4105 CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
;
4107 rc
= bnxt_cfg_rx_mode(bp
);
4111 rc
= bnxt_hwrm_set_coal(bp
);
4113 netdev_warn(bp
->dev
, "HWRM set coalescing failure rc: %x\n",
4119 bnxt_hwrm_resource_free(bp
, 0, true);
4124 static int bnxt_shutdown_nic(struct bnxt
*bp
, bool irq_re_init
)
4126 bnxt_hwrm_resource_free(bp
, 1, irq_re_init
);
4130 static int bnxt_init_nic(struct bnxt
*bp
, bool irq_re_init
)
4132 bnxt_init_rx_rings(bp
);
4133 bnxt_init_tx_rings(bp
);
4134 bnxt_init_ring_grps(bp
, irq_re_init
);
4135 bnxt_init_vnics(bp
);
4137 return bnxt_init_chip(bp
, irq_re_init
);
4140 static void bnxt_disable_int(struct bnxt
*bp
)
4147 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4148 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4149 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
4151 BNXT_CP_DB(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
4155 static void bnxt_enable_int(struct bnxt
*bp
)
4159 atomic_set(&bp
->intr_sem
, 0);
4160 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4161 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4162 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
4164 BNXT_CP_DB_REARM(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
4168 static int bnxt_set_real_num_queues(struct bnxt
*bp
)
4171 struct net_device
*dev
= bp
->dev
;
4173 rc
= netif_set_real_num_tx_queues(dev
, bp
->tx_nr_rings
);
4177 rc
= netif_set_real_num_rx_queues(dev
, bp
->rx_nr_rings
);
4181 #ifdef CONFIG_RFS_ACCEL
4182 if (bp
->flags
& BNXT_FLAG_RFS
)
4183 dev
->rx_cpu_rmap
= alloc_irq_cpu_rmap(bp
->rx_nr_rings
);
4189 static int bnxt_trim_rings(struct bnxt
*bp
, int *rx
, int *tx
, int max
,
4192 int _rx
= *rx
, _tx
= *tx
;
4195 *rx
= min_t(int, _rx
, max
);
4196 *tx
= min_t(int, _tx
, max
);
4201 while (_rx
+ _tx
> max
) {
4202 if (_rx
> _tx
&& _rx
> 1)
4213 static int bnxt_setup_msix(struct bnxt
*bp
)
4215 struct msix_entry
*msix_ent
;
4216 struct net_device
*dev
= bp
->dev
;
4217 int i
, total_vecs
, rc
= 0, min
= 1;
4218 const int len
= sizeof(bp
->irq_tbl
[0].name
);
4220 bp
->flags
&= ~BNXT_FLAG_USING_MSIX
;
4221 total_vecs
= bp
->cp_nr_rings
;
4223 msix_ent
= kcalloc(total_vecs
, sizeof(struct msix_entry
), GFP_KERNEL
);
4227 for (i
= 0; i
< total_vecs
; i
++) {
4228 msix_ent
[i
].entry
= i
;
4229 msix_ent
[i
].vector
= 0;
4232 if (!(bp
->flags
& BNXT_FLAG_SHARED_RINGS
))
4235 total_vecs
= pci_enable_msix_range(bp
->pdev
, msix_ent
, min
, total_vecs
);
4236 if (total_vecs
< 0) {
4238 goto msix_setup_exit
;
4241 bp
->irq_tbl
= kcalloc(total_vecs
, sizeof(struct bnxt_irq
), GFP_KERNEL
);
4245 /* Trim rings based upon num of vectors allocated */
4246 rc
= bnxt_trim_rings(bp
, &bp
->rx_nr_rings
, &bp
->tx_nr_rings
,
4247 total_vecs
, min
== 1);
4249 goto msix_setup_exit
;
4251 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
;
4252 tcs
= netdev_get_num_tc(dev
);
4254 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
/ tcs
;
4255 if (bp
->tx_nr_rings_per_tc
== 0) {
4256 netdev_reset_tc(dev
);
4257 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
;
4261 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
* tcs
;
4262 for (i
= 0; i
< tcs
; i
++) {
4263 count
= bp
->tx_nr_rings_per_tc
;
4265 netdev_set_tc_queue(dev
, i
, count
, off
);
4269 bp
->cp_nr_rings
= total_vecs
;
4271 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4274 bp
->irq_tbl
[i
].vector
= msix_ent
[i
].vector
;
4275 if (bp
->flags
& BNXT_FLAG_SHARED_RINGS
)
4277 else if (i
< bp
->rx_nr_rings
)
4282 snprintf(bp
->irq_tbl
[i
].name
, len
,
4283 "%s-%s-%d", dev
->name
, attr
, i
);
4284 bp
->irq_tbl
[i
].handler
= bnxt_msix
;
4286 rc
= bnxt_set_real_num_queues(bp
);
4288 goto msix_setup_exit
;
4291 goto msix_setup_exit
;
4293 bp
->flags
|= BNXT_FLAG_USING_MSIX
;
4298 netdev_err(bp
->dev
, "bnxt_setup_msix err: %x\n", rc
);
4299 pci_disable_msix(bp
->pdev
);
4304 static int bnxt_setup_inta(struct bnxt
*bp
)
4307 const int len
= sizeof(bp
->irq_tbl
[0].name
);
4309 if (netdev_get_num_tc(bp
->dev
))
4310 netdev_reset_tc(bp
->dev
);
4312 bp
->irq_tbl
= kcalloc(1, sizeof(struct bnxt_irq
), GFP_KERNEL
);
4317 bp
->rx_nr_rings
= 1;
4318 bp
->tx_nr_rings
= 1;
4319 bp
->cp_nr_rings
= 1;
4320 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
;
4321 bp
->flags
|= BNXT_FLAG_SHARED_RINGS
;
4322 bp
->irq_tbl
[0].vector
= bp
->pdev
->irq
;
4323 snprintf(bp
->irq_tbl
[0].name
, len
,
4324 "%s-%s-%d", bp
->dev
->name
, "TxRx", 0);
4325 bp
->irq_tbl
[0].handler
= bnxt_inta
;
4326 rc
= bnxt_set_real_num_queues(bp
);
4330 static int bnxt_setup_int_mode(struct bnxt
*bp
)
4334 if (bp
->flags
& BNXT_FLAG_MSIX_CAP
)
4335 rc
= bnxt_setup_msix(bp
);
4337 if (!(bp
->flags
& BNXT_FLAG_USING_MSIX
) && BNXT_PF(bp
)) {
4338 /* fallback to INTA */
4339 rc
= bnxt_setup_inta(bp
);
4344 static void bnxt_free_irq(struct bnxt
*bp
)
4346 struct bnxt_irq
*irq
;
4349 #ifdef CONFIG_RFS_ACCEL
4350 free_irq_cpu_rmap(bp
->dev
->rx_cpu_rmap
);
4351 bp
->dev
->rx_cpu_rmap
= NULL
;
4356 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4357 irq
= &bp
->irq_tbl
[i
];
4359 free_irq(irq
->vector
, bp
->bnapi
[i
]);
4362 if (bp
->flags
& BNXT_FLAG_USING_MSIX
)
4363 pci_disable_msix(bp
->pdev
);
4368 static int bnxt_request_irq(struct bnxt
*bp
)
4371 unsigned long flags
= 0;
4372 #ifdef CONFIG_RFS_ACCEL
4373 struct cpu_rmap
*rmap
= bp
->dev
->rx_cpu_rmap
;
4376 if (!(bp
->flags
& BNXT_FLAG_USING_MSIX
))
4377 flags
= IRQF_SHARED
;
4379 for (i
= 0, j
= 0; i
< bp
->cp_nr_rings
; i
++) {
4380 struct bnxt_irq
*irq
= &bp
->irq_tbl
[i
];
4381 #ifdef CONFIG_RFS_ACCEL
4382 if (rmap
&& bp
->bnapi
[i
]->rx_ring
) {
4383 rc
= irq_cpu_rmap_add(rmap
, irq
->vector
);
4385 netdev_warn(bp
->dev
, "failed adding irq rmap for ring %d\n",
4390 rc
= request_irq(irq
->vector
, irq
->handler
, flags
, irq
->name
,
4400 static void bnxt_del_napi(struct bnxt
*bp
)
4407 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4408 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4410 napi_hash_del(&bnapi
->napi
);
4411 netif_napi_del(&bnapi
->napi
);
4415 static void bnxt_init_napi(struct bnxt
*bp
)
4418 struct bnxt_napi
*bnapi
;
4420 if (bp
->flags
& BNXT_FLAG_USING_MSIX
) {
4421 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4422 bnapi
= bp
->bnapi
[i
];
4423 netif_napi_add(bp
->dev
, &bnapi
->napi
,
4427 bnapi
= bp
->bnapi
[0];
4428 netif_napi_add(bp
->dev
, &bnapi
->napi
, bnxt_poll
, 64);
4432 static void bnxt_disable_napi(struct bnxt
*bp
)
4439 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4440 napi_disable(&bp
->bnapi
[i
]->napi
);
4441 bnxt_disable_poll(bp
->bnapi
[i
]);
4445 static void bnxt_enable_napi(struct bnxt
*bp
)
4449 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4450 bnxt_enable_poll(bp
->bnapi
[i
]);
4451 napi_enable(&bp
->bnapi
[i
]->napi
);
4455 static void bnxt_tx_disable(struct bnxt
*bp
)
4458 struct bnxt_tx_ring_info
*txr
;
4459 struct netdev_queue
*txq
;
4462 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
4463 txr
= &bp
->tx_ring
[i
];
4464 txq
= netdev_get_tx_queue(bp
->dev
, i
);
4465 __netif_tx_lock(txq
, smp_processor_id());
4466 txr
->dev_state
= BNXT_DEV_STATE_CLOSING
;
4467 __netif_tx_unlock(txq
);
4470 /* Stop all TX queues */
4471 netif_tx_disable(bp
->dev
);
4472 netif_carrier_off(bp
->dev
);
4475 static void bnxt_tx_enable(struct bnxt
*bp
)
4478 struct bnxt_tx_ring_info
*txr
;
4479 struct netdev_queue
*txq
;
4481 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
4482 txr
= &bp
->tx_ring
[i
];
4483 txq
= netdev_get_tx_queue(bp
->dev
, i
);
4486 netif_tx_wake_all_queues(bp
->dev
);
4487 if (bp
->link_info
.link_up
)
4488 netif_carrier_on(bp
->dev
);
4491 static void bnxt_report_link(struct bnxt
*bp
)
4493 if (bp
->link_info
.link_up
) {
4495 const char *flow_ctrl
;
4498 netif_carrier_on(bp
->dev
);
4499 if (bp
->link_info
.duplex
== BNXT_LINK_DUPLEX_FULL
)
4503 if (bp
->link_info
.pause
== BNXT_LINK_PAUSE_BOTH
)
4504 flow_ctrl
= "ON - receive & transmit";
4505 else if (bp
->link_info
.pause
== BNXT_LINK_PAUSE_TX
)
4506 flow_ctrl
= "ON - transmit";
4507 else if (bp
->link_info
.pause
== BNXT_LINK_PAUSE_RX
)
4508 flow_ctrl
= "ON - receive";
4511 speed
= bnxt_fw_to_ethtool_speed(bp
->link_info
.link_speed
);
4512 netdev_info(bp
->dev
, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
4513 speed
, duplex
, flow_ctrl
);
4515 netif_carrier_off(bp
->dev
);
4516 netdev_err(bp
->dev
, "NIC Link is Down\n");
4520 static int bnxt_update_link(struct bnxt
*bp
, bool chng_link_state
)
4523 struct bnxt_link_info
*link_info
= &bp
->link_info
;
4524 struct hwrm_port_phy_qcfg_input req
= {0};
4525 struct hwrm_port_phy_qcfg_output
*resp
= bp
->hwrm_cmd_resp_addr
;
4526 u8 link_up
= link_info
->link_up
;
4528 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_QCFG
, -1, -1);
4530 mutex_lock(&bp
->hwrm_cmd_lock
);
4531 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4533 mutex_unlock(&bp
->hwrm_cmd_lock
);
4537 memcpy(&link_info
->phy_qcfg_resp
, resp
, sizeof(*resp
));
4538 link_info
->phy_link_status
= resp
->link
;
4539 link_info
->duplex
= resp
->duplex
;
4540 link_info
->pause
= resp
->pause
;
4541 link_info
->auto_mode
= resp
->auto_mode
;
4542 link_info
->auto_pause_setting
= resp
->auto_pause
;
4543 link_info
->lp_pause
= resp
->link_partner_adv_pause
;
4544 link_info
->force_pause_setting
= resp
->force_pause
;
4545 link_info
->duplex_setting
= resp
->duplex
;
4546 if (link_info
->phy_link_status
== BNXT_LINK_LINK
)
4547 link_info
->link_speed
= le16_to_cpu(resp
->link_speed
);
4549 link_info
->link_speed
= 0;
4550 link_info
->force_link_speed
= le16_to_cpu(resp
->force_link_speed
);
4551 link_info
->auto_link_speed
= le16_to_cpu(resp
->auto_link_speed
);
4552 link_info
->support_speeds
= le16_to_cpu(resp
->support_speeds
);
4553 link_info
->auto_link_speeds
= le16_to_cpu(resp
->auto_link_speed_mask
);
4554 link_info
->lp_auto_link_speeds
=
4555 le16_to_cpu(resp
->link_partner_adv_speeds
);
4556 link_info
->preemphasis
= le32_to_cpu(resp
->preemphasis
);
4557 link_info
->phy_ver
[0] = resp
->phy_maj
;
4558 link_info
->phy_ver
[1] = resp
->phy_min
;
4559 link_info
->phy_ver
[2] = resp
->phy_bld
;
4560 link_info
->media_type
= resp
->media_type
;
4561 link_info
->transceiver
= resp
->transceiver_type
;
4562 link_info
->phy_addr
= resp
->phy_addr
;
4564 /* TODO: need to add more logic to report VF link */
4565 if (chng_link_state
) {
4566 if (link_info
->phy_link_status
== BNXT_LINK_LINK
)
4567 link_info
->link_up
= 1;
4569 link_info
->link_up
= 0;
4570 if (link_up
!= link_info
->link_up
)
4571 bnxt_report_link(bp
);
4573 /* alwasy link down if not require to update link state */
4574 link_info
->link_up
= 0;
4576 mutex_unlock(&bp
->hwrm_cmd_lock
);
4581 bnxt_hwrm_set_pause_common(struct bnxt
*bp
, struct hwrm_port_phy_cfg_input
*req
)
4583 if (bp
->link_info
.autoneg
& BNXT_AUTONEG_FLOW_CTRL
) {
4584 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_RX
)
4585 req
->auto_pause
|= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX
;
4586 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_TX
)
4587 req
->auto_pause
|= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX
;
4589 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE
);
4591 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_RX
)
4592 req
->force_pause
|= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX
;
4593 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_TX
)
4594 req
->force_pause
|= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX
;
4596 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE
);
4600 static void bnxt_hwrm_set_link_common(struct bnxt
*bp
,
4601 struct hwrm_port_phy_cfg_input
*req
)
4603 u8 autoneg
= bp
->link_info
.autoneg
;
4604 u16 fw_link_speed
= bp
->link_info
.req_link_speed
;
4605 u32 advertising
= bp
->link_info
.advertising
;
4607 if (autoneg
& BNXT_AUTONEG_SPEED
) {
4609 PORT_PHY_CFG_REQ_AUTO_MODE_MASK
;
4611 req
->enables
|= cpu_to_le32(
4612 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK
);
4613 req
->auto_link_speed_mask
= cpu_to_le16(advertising
);
4615 req
->enables
|= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE
);
4617 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG
);
4619 req
->force_link_speed
= cpu_to_le16(fw_link_speed
);
4620 req
->flags
|= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE
);
4623 /* currently don't support half duplex */
4624 req
->auto_duplex
= PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL
;
4625 req
->enables
|= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX
);
4626 /* tell chimp that the setting takes effect immediately */
4627 req
->flags
|= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY
);
4630 int bnxt_hwrm_set_pause(struct bnxt
*bp
)
4632 struct hwrm_port_phy_cfg_input req
= {0};
4635 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_CFG
, -1, -1);
4636 bnxt_hwrm_set_pause_common(bp
, &req
);
4638 if ((bp
->link_info
.autoneg
& BNXT_AUTONEG_FLOW_CTRL
) ||
4639 bp
->link_info
.force_link_chng
)
4640 bnxt_hwrm_set_link_common(bp
, &req
);
4642 mutex_lock(&bp
->hwrm_cmd_lock
);
4643 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4644 if (!rc
&& !(bp
->link_info
.autoneg
& BNXT_AUTONEG_FLOW_CTRL
)) {
4645 /* since changing of pause setting doesn't trigger any link
4646 * change event, the driver needs to update the current pause
4647 * result upon successfully return of the phy_cfg command
4649 bp
->link_info
.pause
=
4650 bp
->link_info
.force_pause_setting
= bp
->link_info
.req_flow_ctrl
;
4651 bp
->link_info
.auto_pause_setting
= 0;
4652 if (!bp
->link_info
.force_link_chng
)
4653 bnxt_report_link(bp
);
4655 bp
->link_info
.force_link_chng
= false;
4656 mutex_unlock(&bp
->hwrm_cmd_lock
);
4660 int bnxt_hwrm_set_link_setting(struct bnxt
*bp
, bool set_pause
)
4662 struct hwrm_port_phy_cfg_input req
= {0};
4664 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_CFG
, -1, -1);
4666 bnxt_hwrm_set_pause_common(bp
, &req
);
4668 bnxt_hwrm_set_link_common(bp
, &req
);
4669 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4672 static int bnxt_update_phy_setting(struct bnxt
*bp
)
4675 bool update_link
= false;
4676 bool update_pause
= false;
4677 struct bnxt_link_info
*link_info
= &bp
->link_info
;
4679 rc
= bnxt_update_link(bp
, true);
4681 netdev_err(bp
->dev
, "failed to update link (rc: %x)\n",
4685 if ((link_info
->autoneg
& BNXT_AUTONEG_FLOW_CTRL
) &&
4686 link_info
->auto_pause_setting
!= link_info
->req_flow_ctrl
)
4687 update_pause
= true;
4688 if (!(link_info
->autoneg
& BNXT_AUTONEG_FLOW_CTRL
) &&
4689 link_info
->force_pause_setting
!= link_info
->req_flow_ctrl
)
4690 update_pause
= true;
4691 if (!(link_info
->autoneg
& BNXT_AUTONEG_SPEED
)) {
4692 if (BNXT_AUTO_MODE(link_info
->auto_mode
))
4694 if (link_info
->req_link_speed
!= link_info
->force_link_speed
)
4696 if (link_info
->req_duplex
!= link_info
->duplex_setting
)
4699 if (link_info
->auto_mode
== BNXT_LINK_AUTO_NONE
)
4701 if (link_info
->advertising
!= link_info
->auto_link_speeds
)
4706 rc
= bnxt_hwrm_set_link_setting(bp
, update_pause
);
4707 else if (update_pause
)
4708 rc
= bnxt_hwrm_set_pause(bp
);
4710 netdev_err(bp
->dev
, "failed to update phy setting (rc: %x)\n",
4718 /* Common routine to pre-map certain register block to different GRC window.
4719 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
4720 * in PF and 3 windows in VF that can be customized to map in different
4723 static void bnxt_preset_reg_win(struct bnxt
*bp
)
4726 /* CAG registers map to GRC window #4 */
4727 writel(BNXT_CAG_REG_BASE
,
4728 bp
->bar0
+ BNXT_GRCPF_REG_WINDOW_BASE_OUT
+ 12);
4732 static int __bnxt_open_nic(struct bnxt
*bp
, bool irq_re_init
, bool link_re_init
)
4736 bnxt_preset_reg_win(bp
);
4737 netif_carrier_off(bp
->dev
);
4739 rc
= bnxt_setup_int_mode(bp
);
4741 netdev_err(bp
->dev
, "bnxt_setup_int_mode err: %x\n",
4746 if ((bp
->flags
& BNXT_FLAG_RFS
) &&
4747 !(bp
->flags
& BNXT_FLAG_USING_MSIX
)) {
4748 /* disable RFS if falling back to INTA */
4749 bp
->dev
->hw_features
&= ~NETIF_F_NTUPLE
;
4750 bp
->flags
&= ~BNXT_FLAG_RFS
;
4753 rc
= bnxt_alloc_mem(bp
, irq_re_init
);
4755 netdev_err(bp
->dev
, "bnxt_alloc_mem err: %x\n", rc
);
4756 goto open_err_free_mem
;
4761 rc
= bnxt_request_irq(bp
);
4763 netdev_err(bp
->dev
, "bnxt_request_irq err: %x\n", rc
);
4768 bnxt_enable_napi(bp
);
4770 rc
= bnxt_init_nic(bp
, irq_re_init
);
4772 netdev_err(bp
->dev
, "bnxt_init_nic err: %x\n", rc
);
4777 rc
= bnxt_update_phy_setting(bp
);
4779 netdev_warn(bp
->dev
, "failed to update phy settings\n");
4783 #if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE)
4784 vxlan_get_rx_port(bp
->dev
);
4786 if (!bnxt_hwrm_tunnel_dst_port_alloc(
4788 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
))
4789 bp
->nge_port_cnt
= 1;
4792 set_bit(BNXT_STATE_OPEN
, &bp
->state
);
4793 bnxt_enable_int(bp
);
4794 /* Enable TX queues */
4796 mod_timer(&bp
->timer
, jiffies
+ bp
->current_interval
);
4797 bnxt_update_link(bp
, true);
4802 bnxt_disable_napi(bp
);
4808 bnxt_free_mem(bp
, true);
4812 /* rtnl_lock held */
4813 int bnxt_open_nic(struct bnxt
*bp
, bool irq_re_init
, bool link_re_init
)
4817 rc
= __bnxt_open_nic(bp
, irq_re_init
, link_re_init
);
4819 netdev_err(bp
->dev
, "nic open fail (rc: %x)\n", rc
);
4825 static int bnxt_open(struct net_device
*dev
)
4827 struct bnxt
*bp
= netdev_priv(dev
);
4830 rc
= bnxt_hwrm_func_reset(bp
);
4832 netdev_err(bp
->dev
, "hwrm chip reset failure rc: %x\n",
4837 return __bnxt_open_nic(bp
, true, true);
4840 static void bnxt_disable_int_sync(struct bnxt
*bp
)
4844 atomic_inc(&bp
->intr_sem
);
4845 if (!netif_running(bp
->dev
))
4848 bnxt_disable_int(bp
);
4849 for (i
= 0; i
< bp
->cp_nr_rings
; i
++)
4850 synchronize_irq(bp
->irq_tbl
[i
].vector
);
4853 int bnxt_close_nic(struct bnxt
*bp
, bool irq_re_init
, bool link_re_init
)
4857 #ifdef CONFIG_BNXT_SRIOV
4858 if (bp
->sriov_cfg
) {
4859 rc
= wait_event_interruptible_timeout(bp
->sriov_cfg_wait
,
4861 BNXT_SRIOV_CFG_WAIT_TMO
);
4863 netdev_warn(bp
->dev
, "timeout waiting for SRIOV config operation to complete!\n");
4866 /* Change device state to avoid TX queue wake up's */
4867 bnxt_tx_disable(bp
);
4869 clear_bit(BNXT_STATE_OPEN
, &bp
->state
);
4870 smp_mb__after_atomic();
4871 while (test_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
))
4874 /* Flush rings before disabling interrupts */
4875 bnxt_shutdown_nic(bp
, irq_re_init
);
4877 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
4879 bnxt_disable_napi(bp
);
4880 bnxt_disable_int_sync(bp
);
4881 del_timer_sync(&bp
->timer
);
4888 bnxt_free_mem(bp
, irq_re_init
);
4892 static int bnxt_close(struct net_device
*dev
)
4894 struct bnxt
*bp
= netdev_priv(dev
);
4896 bnxt_close_nic(bp
, true, true);
4900 /* rtnl_lock held */
4901 static int bnxt_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
4907 if (!netif_running(dev
))
4914 if (!netif_running(dev
))
4926 static struct rtnl_link_stats64
*
4927 bnxt_get_stats64(struct net_device
*dev
, struct rtnl_link_stats64
*stats
)
4930 struct bnxt
*bp
= netdev_priv(dev
);
4932 memset(stats
, 0, sizeof(struct rtnl_link_stats64
));
4937 /* TODO check if we need to synchronize with bnxt_close path */
4938 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4939 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4940 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
4941 struct ctx_hw_stats
*hw_stats
= cpr
->hw_stats
;
4943 stats
->rx_packets
+= le64_to_cpu(hw_stats
->rx_ucast_pkts
);
4944 stats
->rx_packets
+= le64_to_cpu(hw_stats
->rx_mcast_pkts
);
4945 stats
->rx_packets
+= le64_to_cpu(hw_stats
->rx_bcast_pkts
);
4947 stats
->tx_packets
+= le64_to_cpu(hw_stats
->tx_ucast_pkts
);
4948 stats
->tx_packets
+= le64_to_cpu(hw_stats
->tx_mcast_pkts
);
4949 stats
->tx_packets
+= le64_to_cpu(hw_stats
->tx_bcast_pkts
);
4951 stats
->rx_bytes
+= le64_to_cpu(hw_stats
->rx_ucast_bytes
);
4952 stats
->rx_bytes
+= le64_to_cpu(hw_stats
->rx_mcast_bytes
);
4953 stats
->rx_bytes
+= le64_to_cpu(hw_stats
->rx_bcast_bytes
);
4955 stats
->tx_bytes
+= le64_to_cpu(hw_stats
->tx_ucast_bytes
);
4956 stats
->tx_bytes
+= le64_to_cpu(hw_stats
->tx_mcast_bytes
);
4957 stats
->tx_bytes
+= le64_to_cpu(hw_stats
->tx_bcast_bytes
);
4959 stats
->rx_missed_errors
+=
4960 le64_to_cpu(hw_stats
->rx_discard_pkts
);
4962 stats
->multicast
+= le64_to_cpu(hw_stats
->rx_mcast_pkts
);
4964 stats
->tx_dropped
+= le64_to_cpu(hw_stats
->tx_drop_pkts
);
4967 if (bp
->flags
& BNXT_FLAG_PORT_STATS
) {
4968 struct rx_port_stats
*rx
= bp
->hw_rx_port_stats
;
4969 struct tx_port_stats
*tx
= bp
->hw_tx_port_stats
;
4971 stats
->rx_crc_errors
= le64_to_cpu(rx
->rx_fcs_err_frames
);
4972 stats
->rx_frame_errors
= le64_to_cpu(rx
->rx_align_err_frames
);
4973 stats
->rx_length_errors
= le64_to_cpu(rx
->rx_undrsz_frames
) +
4974 le64_to_cpu(rx
->rx_ovrsz_frames
) +
4975 le64_to_cpu(rx
->rx_runt_frames
);
4976 stats
->rx_errors
= le64_to_cpu(rx
->rx_false_carrier_frames
) +
4977 le64_to_cpu(rx
->rx_jbr_frames
);
4978 stats
->collisions
= le64_to_cpu(tx
->tx_total_collisions
);
4979 stats
->tx_fifo_errors
= le64_to_cpu(tx
->tx_fifo_underruns
);
4980 stats
->tx_errors
= le64_to_cpu(tx
->tx_err
);
4986 static bool bnxt_mc_list_updated(struct bnxt
*bp
, u32
*rx_mask
)
4988 struct net_device
*dev
= bp
->dev
;
4989 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
4990 struct netdev_hw_addr
*ha
;
4993 bool update
= false;
4996 netdev_for_each_mc_addr(ha
, dev
) {
4997 if (mc_count
>= BNXT_MAX_MC_ADDRS
) {
4998 *rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
;
4999 vnic
->mc_list_count
= 0;
5003 if (!ether_addr_equal(haddr
, vnic
->mc_list
+ off
)) {
5004 memcpy(vnic
->mc_list
+ off
, haddr
, ETH_ALEN
);
5011 *rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST
;
5013 if (mc_count
!= vnic
->mc_list_count
) {
5014 vnic
->mc_list_count
= mc_count
;
5020 static bool bnxt_uc_list_updated(struct bnxt
*bp
)
5022 struct net_device
*dev
= bp
->dev
;
5023 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
5024 struct netdev_hw_addr
*ha
;
5027 if (netdev_uc_count(dev
) != (vnic
->uc_filter_count
- 1))
5030 netdev_for_each_uc_addr(ha
, dev
) {
5031 if (!ether_addr_equal(ha
->addr
, vnic
->uc_list
+ off
))
5039 static void bnxt_set_rx_mode(struct net_device
*dev
)
5041 struct bnxt
*bp
= netdev_priv(dev
);
5042 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
5043 u32 mask
= vnic
->rx_mask
;
5044 bool mc_update
= false;
5047 if (!netif_running(dev
))
5050 mask
&= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
|
5051 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST
|
5052 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
);
5054 /* Only allow PF to be in promiscuous mode */
5055 if ((dev
->flags
& IFF_PROMISC
) && BNXT_PF(bp
))
5056 mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
;
5058 uc_update
= bnxt_uc_list_updated(bp
);
5060 if (dev
->flags
& IFF_ALLMULTI
) {
5061 mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
;
5062 vnic
->mc_list_count
= 0;
5064 mc_update
= bnxt_mc_list_updated(bp
, &mask
);
5067 if (mask
!= vnic
->rx_mask
|| uc_update
|| mc_update
) {
5068 vnic
->rx_mask
= mask
;
5070 set_bit(BNXT_RX_MASK_SP_EVENT
, &bp
->sp_event
);
5071 schedule_work(&bp
->sp_task
);
5075 static int bnxt_cfg_rx_mode(struct bnxt
*bp
)
5077 struct net_device
*dev
= bp
->dev
;
5078 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
5079 struct netdev_hw_addr
*ha
;
5083 netif_addr_lock_bh(dev
);
5084 uc_update
= bnxt_uc_list_updated(bp
);
5085 netif_addr_unlock_bh(dev
);
5090 mutex_lock(&bp
->hwrm_cmd_lock
);
5091 for (i
= 1; i
< vnic
->uc_filter_count
; i
++) {
5092 struct hwrm_cfa_l2_filter_free_input req
= {0};
5094 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_L2_FILTER_FREE
, -1,
5097 req
.l2_filter_id
= vnic
->fw_l2_filter_id
[i
];
5099 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
5102 mutex_unlock(&bp
->hwrm_cmd_lock
);
5104 vnic
->uc_filter_count
= 1;
5106 netif_addr_lock_bh(dev
);
5107 if (netdev_uc_count(dev
) > (BNXT_MAX_UC_ADDRS
- 1)) {
5108 vnic
->rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
;
5110 netdev_for_each_uc_addr(ha
, dev
) {
5111 memcpy(vnic
->uc_list
+ off
, ha
->addr
, ETH_ALEN
);
5113 vnic
->uc_filter_count
++;
5116 netif_addr_unlock_bh(dev
);
5118 for (i
= 1, off
= 0; i
< vnic
->uc_filter_count
; i
++, off
+= ETH_ALEN
) {
5119 rc
= bnxt_hwrm_set_vnic_filter(bp
, 0, i
, vnic
->uc_list
+ off
);
5121 netdev_err(bp
->dev
, "HWRM vnic filter failure rc: %x\n",
5123 vnic
->uc_filter_count
= i
;
5129 rc
= bnxt_hwrm_cfa_l2_set_rx_mask(bp
, 0);
5131 netdev_err(bp
->dev
, "HWRM cfa l2 rx mask failure rc: %x\n",
5137 static bool bnxt_rfs_capable(struct bnxt
*bp
)
5139 #ifdef CONFIG_RFS_ACCEL
5140 struct bnxt_pf_info
*pf
= &bp
->pf
;
5143 if (BNXT_VF(bp
) || !(bp
->flags
& BNXT_FLAG_MSIX_CAP
))
5146 vnics
= 1 + bp
->rx_nr_rings
;
5147 if (vnics
> pf
->max_rsscos_ctxs
|| vnics
> pf
->max_vnics
)
5156 static netdev_features_t
bnxt_fix_features(struct net_device
*dev
,
5157 netdev_features_t features
)
5159 struct bnxt
*bp
= netdev_priv(dev
);
5161 if (!bnxt_rfs_capable(bp
))
5162 features
&= ~NETIF_F_NTUPLE
;
5166 static int bnxt_set_features(struct net_device
*dev
, netdev_features_t features
)
5168 struct bnxt
*bp
= netdev_priv(dev
);
5169 u32 flags
= bp
->flags
;
5172 bool re_init
= false;
5173 bool update_tpa
= false;
5175 flags
&= ~BNXT_FLAG_ALL_CONFIG_FEATS
;
5176 if ((features
& NETIF_F_GRO
) && (bp
->pdev
->revision
> 0))
5177 flags
|= BNXT_FLAG_GRO
;
5178 if (features
& NETIF_F_LRO
)
5179 flags
|= BNXT_FLAG_LRO
;
5181 if (features
& NETIF_F_HW_VLAN_CTAG_RX
)
5182 flags
|= BNXT_FLAG_STRIP_VLAN
;
5184 if (features
& NETIF_F_NTUPLE
)
5185 flags
|= BNXT_FLAG_RFS
;
5187 changes
= flags
^ bp
->flags
;
5188 if (changes
& BNXT_FLAG_TPA
) {
5190 if ((bp
->flags
& BNXT_FLAG_TPA
) == 0 ||
5191 (flags
& BNXT_FLAG_TPA
) == 0)
5195 if (changes
& ~BNXT_FLAG_TPA
)
5198 if (flags
!= bp
->flags
) {
5199 u32 old_flags
= bp
->flags
;
5203 if (!test_bit(BNXT_STATE_OPEN
, &bp
->state
)) {
5205 bnxt_set_ring_params(bp
);
5210 bnxt_close_nic(bp
, false, false);
5212 bnxt_set_ring_params(bp
);
5214 return bnxt_open_nic(bp
, false, false);
5217 rc
= bnxt_set_tpa(bp
,
5218 (flags
& BNXT_FLAG_TPA
) ?
5221 bp
->flags
= old_flags
;
5227 static void bnxt_dump_tx_sw_state(struct bnxt_napi
*bnapi
)
5229 struct bnxt_tx_ring_info
*txr
= bnapi
->tx_ring
;
5230 int i
= bnapi
->index
;
5235 netdev_info(bnapi
->bp
->dev
, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
5236 i
, txr
->tx_ring_struct
.fw_ring_id
, txr
->tx_prod
,
5240 static void bnxt_dump_rx_sw_state(struct bnxt_napi
*bnapi
)
5242 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
5243 int i
= bnapi
->index
;
5248 netdev_info(bnapi
->bp
->dev
, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
5249 i
, rxr
->rx_ring_struct
.fw_ring_id
, rxr
->rx_prod
,
5250 rxr
->rx_agg_ring_struct
.fw_ring_id
, rxr
->rx_agg_prod
,
5251 rxr
->rx_sw_agg_prod
);
5254 static void bnxt_dump_cp_sw_state(struct bnxt_napi
*bnapi
)
5256 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
5257 int i
= bnapi
->index
;
5259 netdev_info(bnapi
->bp
->dev
, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
5260 i
, cpr
->cp_ring_struct
.fw_ring_id
, cpr
->cp_raw_cons
);
5263 static void bnxt_dbg_dump_states(struct bnxt
*bp
)
5266 struct bnxt_napi
*bnapi
;
5268 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
5269 bnapi
= bp
->bnapi
[i
];
5270 if (netif_msg_drv(bp
)) {
5271 bnxt_dump_tx_sw_state(bnapi
);
5272 bnxt_dump_rx_sw_state(bnapi
);
5273 bnxt_dump_cp_sw_state(bnapi
);
5278 static void bnxt_reset_task(struct bnxt
*bp
)
5280 bnxt_dbg_dump_states(bp
);
5281 if (netif_running(bp
->dev
)) {
5282 bnxt_close_nic(bp
, false, false);
5283 bnxt_open_nic(bp
, false, false);
5287 static void bnxt_tx_timeout(struct net_device
*dev
)
5289 struct bnxt
*bp
= netdev_priv(dev
);
5291 netdev_err(bp
->dev
, "TX timeout detected, starting reset task!\n");
5292 set_bit(BNXT_RESET_TASK_SP_EVENT
, &bp
->sp_event
);
5293 schedule_work(&bp
->sp_task
);
5296 #ifdef CONFIG_NET_POLL_CONTROLLER
5297 static void bnxt_poll_controller(struct net_device
*dev
)
5299 struct bnxt
*bp
= netdev_priv(dev
);
5302 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
5303 struct bnxt_irq
*irq
= &bp
->irq_tbl
[i
];
5305 disable_irq(irq
->vector
);
5306 irq
->handler(irq
->vector
, bp
->bnapi
[i
]);
5307 enable_irq(irq
->vector
);
5312 static void bnxt_timer(unsigned long data
)
5314 struct bnxt
*bp
= (struct bnxt
*)data
;
5315 struct net_device
*dev
= bp
->dev
;
5317 if (!netif_running(dev
))
5320 if (atomic_read(&bp
->intr_sem
) != 0)
5321 goto bnxt_restart_timer
;
5323 if (bp
->link_info
.link_up
&& (bp
->flags
& BNXT_FLAG_PORT_STATS
)) {
5324 set_bit(BNXT_PERIODIC_STATS_SP_EVENT
, &bp
->sp_event
);
5325 schedule_work(&bp
->sp_task
);
5328 mod_timer(&bp
->timer
, jiffies
+ bp
->current_interval
);
5331 static void bnxt_cfg_ntp_filters(struct bnxt
*);
5333 static void bnxt_sp_task(struct work_struct
*work
)
5335 struct bnxt
*bp
= container_of(work
, struct bnxt
, sp_task
);
5338 set_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
5339 smp_mb__after_atomic();
5340 if (!test_bit(BNXT_STATE_OPEN
, &bp
->state
)) {
5341 clear_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
5345 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT
, &bp
->sp_event
))
5346 bnxt_cfg_rx_mode(bp
);
5348 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT
, &bp
->sp_event
))
5349 bnxt_cfg_ntp_filters(bp
);
5350 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT
, &bp
->sp_event
)) {
5351 rc
= bnxt_update_link(bp
, true);
5353 netdev_err(bp
->dev
, "SP task can't update link (rc: %x)\n",
5356 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT
, &bp
->sp_event
))
5357 bnxt_hwrm_exec_fwd_req(bp
);
5358 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT
, &bp
->sp_event
)) {
5359 bnxt_hwrm_tunnel_dst_port_alloc(
5361 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
);
5363 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT
, &bp
->sp_event
)) {
5364 bnxt_hwrm_tunnel_dst_port_free(
5365 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
);
5367 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT
, &bp
->sp_event
)) {
5368 /* bnxt_reset_task() calls bnxt_close_nic() which waits
5369 * for BNXT_STATE_IN_SP_TASK to clear.
5371 clear_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
5373 bnxt_reset_task(bp
);
5374 set_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
5378 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT
, &bp
->sp_event
))
5379 bnxt_hwrm_port_qstats(bp
);
5381 smp_mb__before_atomic();
5382 clear_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
5385 static int bnxt_init_board(struct pci_dev
*pdev
, struct net_device
*dev
)
5388 struct bnxt
*bp
= netdev_priv(dev
);
5390 SET_NETDEV_DEV(dev
, &pdev
->dev
);
5392 /* enable device (incl. PCI PM wakeup), and bus-mastering */
5393 rc
= pci_enable_device(pdev
);
5395 dev_err(&pdev
->dev
, "Cannot enable PCI device, aborting\n");
5399 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
5401 "Cannot find PCI device base address, aborting\n");
5403 goto init_err_disable
;
5406 rc
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
5408 dev_err(&pdev
->dev
, "Cannot obtain PCI resources, aborting\n");
5409 goto init_err_disable
;
5412 if (dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(64)) != 0 &&
5413 dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(32)) != 0) {
5414 dev_err(&pdev
->dev
, "System does not support DMA, aborting\n");
5415 goto init_err_disable
;
5418 pci_set_master(pdev
);
5423 bp
->bar0
= pci_ioremap_bar(pdev
, 0);
5425 dev_err(&pdev
->dev
, "Cannot map device registers, aborting\n");
5427 goto init_err_release
;
5430 bp
->bar1
= pci_ioremap_bar(pdev
, 2);
5432 dev_err(&pdev
->dev
, "Cannot map doorbell registers, aborting\n");
5434 goto init_err_release
;
5437 bp
->bar2
= pci_ioremap_bar(pdev
, 4);
5439 dev_err(&pdev
->dev
, "Cannot map bar4 registers, aborting\n");
5441 goto init_err_release
;
5444 pci_enable_pcie_error_reporting(pdev
);
5446 INIT_WORK(&bp
->sp_task
, bnxt_sp_task
);
5448 spin_lock_init(&bp
->ntp_fltr_lock
);
5450 bp
->rx_ring_size
= BNXT_DEFAULT_RX_RING_SIZE
;
5451 bp
->tx_ring_size
= BNXT_DEFAULT_TX_RING_SIZE
;
5453 /* tick values in micro seconds */
5454 bp
->rx_coal_ticks
= 12;
5455 bp
->rx_coal_bufs
= 30;
5456 bp
->rx_coal_ticks_irq
= 1;
5457 bp
->rx_coal_bufs_irq
= 2;
5459 bp
->tx_coal_ticks
= 25;
5460 bp
->tx_coal_bufs
= 30;
5461 bp
->tx_coal_ticks_irq
= 2;
5462 bp
->tx_coal_bufs_irq
= 2;
5464 init_timer(&bp
->timer
);
5465 bp
->timer
.data
= (unsigned long)bp
;
5466 bp
->timer
.function
= bnxt_timer
;
5467 bp
->current_interval
= BNXT_TIMER_INTERVAL
;
5469 clear_bit(BNXT_STATE_OPEN
, &bp
->state
);
5475 pci_iounmap(pdev
, bp
->bar2
);
5480 pci_iounmap(pdev
, bp
->bar1
);
5485 pci_iounmap(pdev
, bp
->bar0
);
5489 pci_release_regions(pdev
);
5492 pci_disable_device(pdev
);
5498 /* rtnl_lock held */
5499 static int bnxt_change_mac_addr(struct net_device
*dev
, void *p
)
5501 struct sockaddr
*addr
= p
;
5502 struct bnxt
*bp
= netdev_priv(dev
);
5505 if (!is_valid_ether_addr(addr
->sa_data
))
5506 return -EADDRNOTAVAIL
;
5508 #ifdef CONFIG_BNXT_SRIOV
5509 if (BNXT_VF(bp
) && is_valid_ether_addr(bp
->vf
.mac_addr
))
5510 return -EADDRNOTAVAIL
;
5513 if (ether_addr_equal(addr
->sa_data
, dev
->dev_addr
))
5516 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
5517 if (netif_running(dev
)) {
5518 bnxt_close_nic(bp
, false, false);
5519 rc
= bnxt_open_nic(bp
, false, false);
5525 /* rtnl_lock held */
5526 static int bnxt_change_mtu(struct net_device
*dev
, int new_mtu
)
5528 struct bnxt
*bp
= netdev_priv(dev
);
5530 if (new_mtu
< 60 || new_mtu
> 9000)
5533 if (netif_running(dev
))
5534 bnxt_close_nic(bp
, false, false);
5537 bnxt_set_ring_params(bp
);
5539 if (netif_running(dev
))
5540 return bnxt_open_nic(bp
, false, false);
5545 static int bnxt_setup_tc(struct net_device
*dev
, u32 handle
, __be16 proto
,
5546 struct tc_to_netdev
*ntc
)
5548 struct bnxt
*bp
= netdev_priv(dev
);
5551 if (ntc
->type
!= TC_SETUP_MQPRIO
)
5556 if (tc
> bp
->max_tc
) {
5557 netdev_err(dev
, "too many traffic classes requested: %d Max supported is %d\n",
5562 if (netdev_get_num_tc(dev
) == tc
)
5566 int max_rx_rings
, max_tx_rings
, rc
;
5569 if (bp
->flags
& BNXT_FLAG_SHARED_RINGS
)
5572 rc
= bnxt_get_max_rings(bp
, &max_rx_rings
, &max_tx_rings
, sh
);
5573 if (rc
|| bp
->tx_nr_rings_per_tc
* tc
> max_tx_rings
)
5577 /* Needs to close the device and do hw resource re-allocations */
5578 if (netif_running(bp
->dev
))
5579 bnxt_close_nic(bp
, true, false);
5582 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
* tc
;
5583 netdev_set_num_tc(dev
, tc
);
5585 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
;
5586 netdev_reset_tc(dev
);
5588 bp
->cp_nr_rings
= max_t(int, bp
->tx_nr_rings
, bp
->rx_nr_rings
);
5589 bp
->num_stat_ctxs
= bp
->cp_nr_rings
;
5591 if (netif_running(bp
->dev
))
5592 return bnxt_open_nic(bp
, true, false);
5597 #ifdef CONFIG_RFS_ACCEL
5598 static bool bnxt_fltr_match(struct bnxt_ntuple_filter
*f1
,
5599 struct bnxt_ntuple_filter
*f2
)
5601 struct flow_keys
*keys1
= &f1
->fkeys
;
5602 struct flow_keys
*keys2
= &f2
->fkeys
;
5604 if (keys1
->addrs
.v4addrs
.src
== keys2
->addrs
.v4addrs
.src
&&
5605 keys1
->addrs
.v4addrs
.dst
== keys2
->addrs
.v4addrs
.dst
&&
5606 keys1
->ports
.ports
== keys2
->ports
.ports
&&
5607 keys1
->basic
.ip_proto
== keys2
->basic
.ip_proto
&&
5608 keys1
->basic
.n_proto
== keys2
->basic
.n_proto
&&
5609 ether_addr_equal(f1
->src_mac_addr
, f2
->src_mac_addr
))
5615 static int bnxt_rx_flow_steer(struct net_device
*dev
, const struct sk_buff
*skb
,
5616 u16 rxq_index
, u32 flow_id
)
5618 struct bnxt
*bp
= netdev_priv(dev
);
5619 struct bnxt_ntuple_filter
*fltr
, *new_fltr
;
5620 struct flow_keys
*fkeys
;
5621 struct ethhdr
*eth
= (struct ethhdr
*)skb_mac_header(skb
);
5622 int rc
= 0, idx
, bit_id
;
5623 struct hlist_head
*head
;
5625 if (skb
->encapsulation
)
5626 return -EPROTONOSUPPORT
;
5628 new_fltr
= kzalloc(sizeof(*new_fltr
), GFP_ATOMIC
);
5632 fkeys
= &new_fltr
->fkeys
;
5633 if (!skb_flow_dissect_flow_keys(skb
, fkeys
, 0)) {
5634 rc
= -EPROTONOSUPPORT
;
5638 if ((fkeys
->basic
.n_proto
!= htons(ETH_P_IP
)) ||
5639 ((fkeys
->basic
.ip_proto
!= IPPROTO_TCP
) &&
5640 (fkeys
->basic
.ip_proto
!= IPPROTO_UDP
))) {
5641 rc
= -EPROTONOSUPPORT
;
5645 memcpy(new_fltr
->src_mac_addr
, eth
->h_source
, ETH_ALEN
);
5647 idx
= skb_get_hash_raw(skb
) & BNXT_NTP_FLTR_HASH_MASK
;
5648 head
= &bp
->ntp_fltr_hash_tbl
[idx
];
5650 hlist_for_each_entry_rcu(fltr
, head
, hash
) {
5651 if (bnxt_fltr_match(fltr
, new_fltr
)) {
5659 spin_lock_bh(&bp
->ntp_fltr_lock
);
5660 bit_id
= bitmap_find_free_region(bp
->ntp_fltr_bmap
,
5661 BNXT_NTP_FLTR_MAX_FLTR
, 0);
5663 spin_unlock_bh(&bp
->ntp_fltr_lock
);
5668 new_fltr
->sw_id
= (u16
)bit_id
;
5669 new_fltr
->flow_id
= flow_id
;
5670 new_fltr
->rxq
= rxq_index
;
5671 hlist_add_head_rcu(&new_fltr
->hash
, head
);
5672 bp
->ntp_fltr_count
++;
5673 spin_unlock_bh(&bp
->ntp_fltr_lock
);
5675 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT
, &bp
->sp_event
);
5676 schedule_work(&bp
->sp_task
);
5678 return new_fltr
->sw_id
;
5685 static void bnxt_cfg_ntp_filters(struct bnxt
*bp
)
5689 for (i
= 0; i
< BNXT_NTP_FLTR_HASH_SIZE
; i
++) {
5690 struct hlist_head
*head
;
5691 struct hlist_node
*tmp
;
5692 struct bnxt_ntuple_filter
*fltr
;
5695 head
= &bp
->ntp_fltr_hash_tbl
[i
];
5696 hlist_for_each_entry_safe(fltr
, tmp
, head
, hash
) {
5699 if (test_bit(BNXT_FLTR_VALID
, &fltr
->state
)) {
5700 if (rps_may_expire_flow(bp
->dev
, fltr
->rxq
,
5703 bnxt_hwrm_cfa_ntuple_filter_free(bp
,
5708 rc
= bnxt_hwrm_cfa_ntuple_filter_alloc(bp
,
5713 set_bit(BNXT_FLTR_VALID
, &fltr
->state
);
5717 spin_lock_bh(&bp
->ntp_fltr_lock
);
5718 hlist_del_rcu(&fltr
->hash
);
5719 bp
->ntp_fltr_count
--;
5720 spin_unlock_bh(&bp
->ntp_fltr_lock
);
5722 clear_bit(fltr
->sw_id
, bp
->ntp_fltr_bmap
);
5727 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT
, &bp
->sp_event
))
5728 netdev_info(bp
->dev
, "Receive PF driver unload event!");
5733 static void bnxt_cfg_ntp_filters(struct bnxt
*bp
)
5737 #endif /* CONFIG_RFS_ACCEL */
5739 static void bnxt_add_vxlan_port(struct net_device
*dev
, sa_family_t sa_family
,
5742 struct bnxt
*bp
= netdev_priv(dev
);
5744 if (!netif_running(dev
))
5747 if (sa_family
!= AF_INET6
&& sa_family
!= AF_INET
)
5750 if (bp
->vxlan_port_cnt
&& bp
->vxlan_port
!= port
)
5753 bp
->vxlan_port_cnt
++;
5754 if (bp
->vxlan_port_cnt
== 1) {
5755 bp
->vxlan_port
= port
;
5756 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT
, &bp
->sp_event
);
5757 schedule_work(&bp
->sp_task
);
5761 static void bnxt_del_vxlan_port(struct net_device
*dev
, sa_family_t sa_family
,
5764 struct bnxt
*bp
= netdev_priv(dev
);
5766 if (!netif_running(dev
))
5769 if (sa_family
!= AF_INET6
&& sa_family
!= AF_INET
)
5772 if (bp
->vxlan_port_cnt
&& bp
->vxlan_port
== port
) {
5773 bp
->vxlan_port_cnt
--;
5775 if (bp
->vxlan_port_cnt
== 0) {
5776 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT
, &bp
->sp_event
);
5777 schedule_work(&bp
->sp_task
);
5782 static const struct net_device_ops bnxt_netdev_ops
= {
5783 .ndo_open
= bnxt_open
,
5784 .ndo_start_xmit
= bnxt_start_xmit
,
5785 .ndo_stop
= bnxt_close
,
5786 .ndo_get_stats64
= bnxt_get_stats64
,
5787 .ndo_set_rx_mode
= bnxt_set_rx_mode
,
5788 .ndo_do_ioctl
= bnxt_ioctl
,
5789 .ndo_validate_addr
= eth_validate_addr
,
5790 .ndo_set_mac_address
= bnxt_change_mac_addr
,
5791 .ndo_change_mtu
= bnxt_change_mtu
,
5792 .ndo_fix_features
= bnxt_fix_features
,
5793 .ndo_set_features
= bnxt_set_features
,
5794 .ndo_tx_timeout
= bnxt_tx_timeout
,
5795 #ifdef CONFIG_BNXT_SRIOV
5796 .ndo_get_vf_config
= bnxt_get_vf_config
,
5797 .ndo_set_vf_mac
= bnxt_set_vf_mac
,
5798 .ndo_set_vf_vlan
= bnxt_set_vf_vlan
,
5799 .ndo_set_vf_rate
= bnxt_set_vf_bw
,
5800 .ndo_set_vf_link_state
= bnxt_set_vf_link_state
,
5801 .ndo_set_vf_spoofchk
= bnxt_set_vf_spoofchk
,
5803 #ifdef CONFIG_NET_POLL_CONTROLLER
5804 .ndo_poll_controller
= bnxt_poll_controller
,
5806 .ndo_setup_tc
= bnxt_setup_tc
,
5807 #ifdef CONFIG_RFS_ACCEL
5808 .ndo_rx_flow_steer
= bnxt_rx_flow_steer
,
5810 .ndo_add_vxlan_port
= bnxt_add_vxlan_port
,
5811 .ndo_del_vxlan_port
= bnxt_del_vxlan_port
,
5812 #ifdef CONFIG_NET_RX_BUSY_POLL
5813 .ndo_busy_poll
= bnxt_busy_poll
,
5817 static void bnxt_remove_one(struct pci_dev
*pdev
)
5819 struct net_device
*dev
= pci_get_drvdata(pdev
);
5820 struct bnxt
*bp
= netdev_priv(dev
);
5823 bnxt_sriov_disable(bp
);
5825 pci_disable_pcie_error_reporting(pdev
);
5826 unregister_netdev(dev
);
5827 cancel_work_sync(&bp
->sp_task
);
5830 bnxt_hwrm_func_drv_unrgtr(bp
);
5831 bnxt_free_hwrm_resources(bp
);
5832 pci_iounmap(pdev
, bp
->bar2
);
5833 pci_iounmap(pdev
, bp
->bar1
);
5834 pci_iounmap(pdev
, bp
->bar0
);
5837 pci_release_regions(pdev
);
5838 pci_disable_device(pdev
);
5841 static int bnxt_probe_phy(struct bnxt
*bp
)
5844 struct bnxt_link_info
*link_info
= &bp
->link_info
;
5846 rc
= bnxt_update_link(bp
, false);
5848 netdev_err(bp
->dev
, "Probe phy can't update link (rc: %x)\n",
5853 /*initialize the ethool setting copy with NVM settings */
5854 if (BNXT_AUTO_MODE(link_info
->auto_mode
)) {
5855 link_info
->autoneg
= BNXT_AUTONEG_SPEED
|
5856 BNXT_AUTONEG_FLOW_CTRL
;
5857 link_info
->advertising
= link_info
->auto_link_speeds
;
5858 link_info
->req_flow_ctrl
= link_info
->auto_pause_setting
;
5860 link_info
->req_link_speed
= link_info
->force_link_speed
;
5861 link_info
->req_duplex
= link_info
->duplex_setting
;
5862 link_info
->req_flow_ctrl
= link_info
->force_pause_setting
;
5867 static int bnxt_get_max_irq(struct pci_dev
*pdev
)
5871 if (!pdev
->msix_cap
)
5874 pci_read_config_word(pdev
, pdev
->msix_cap
+ PCI_MSIX_FLAGS
, &ctrl
);
5875 return (ctrl
& PCI_MSIX_FLAGS_QSIZE
) + 1;
5878 static void _bnxt_get_max_rings(struct bnxt
*bp
, int *max_rx
, int *max_tx
,
5881 int max_ring_grps
= 0;
5883 #ifdef CONFIG_BNXT_SRIOV
5885 *max_tx
= bp
->vf
.max_tx_rings
;
5886 *max_rx
= bp
->vf
.max_rx_rings
;
5887 *max_cp
= min_t(int, bp
->vf
.max_irqs
, bp
->vf
.max_cp_rings
);
5888 *max_cp
= min_t(int, *max_cp
, bp
->vf
.max_stat_ctxs
);
5889 max_ring_grps
= bp
->vf
.max_hw_ring_grps
;
5893 *max_tx
= bp
->pf
.max_tx_rings
;
5894 *max_rx
= bp
->pf
.max_rx_rings
;
5895 *max_cp
= min_t(int, bp
->pf
.max_irqs
, bp
->pf
.max_cp_rings
);
5896 *max_cp
= min_t(int, *max_cp
, bp
->pf
.max_stat_ctxs
);
5897 max_ring_grps
= bp
->pf
.max_hw_ring_grps
;
5900 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
)
5902 *max_rx
= min_t(int, *max_rx
, max_ring_grps
);
5905 int bnxt_get_max_rings(struct bnxt
*bp
, int *max_rx
, int *max_tx
, bool shared
)
5909 _bnxt_get_max_rings(bp
, &rx
, &tx
, &cp
);
5910 if (!rx
|| !tx
|| !cp
)
5915 return bnxt_trim_rings(bp
, max_rx
, max_tx
, cp
, shared
);
5918 static int bnxt_set_dflt_rings(struct bnxt
*bp
)
5920 int dflt_rings
, max_rx_rings
, max_tx_rings
, rc
;
5924 bp
->flags
|= BNXT_FLAG_SHARED_RINGS
;
5925 dflt_rings
= netif_get_num_default_rss_queues();
5926 rc
= bnxt_get_max_rings(bp
, &max_rx_rings
, &max_tx_rings
, sh
);
5929 bp
->rx_nr_rings
= min_t(int, dflt_rings
, max_rx_rings
);
5930 bp
->tx_nr_rings_per_tc
= min_t(int, dflt_rings
, max_tx_rings
);
5931 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
;
5932 bp
->cp_nr_rings
= sh
? max_t(int, bp
->tx_nr_rings
, bp
->rx_nr_rings
) :
5933 bp
->tx_nr_rings
+ bp
->rx_nr_rings
;
5934 bp
->num_stat_ctxs
= bp
->cp_nr_rings
;
5938 static int bnxt_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
5940 static int version_printed
;
5941 struct net_device
*dev
;
5945 if (version_printed
++ == 0)
5946 pr_info("%s", version
);
5948 max_irqs
= bnxt_get_max_irq(pdev
);
5949 dev
= alloc_etherdev_mq(sizeof(*bp
), max_irqs
);
5953 bp
= netdev_priv(dev
);
5955 if (bnxt_vf_pciid(ent
->driver_data
))
5956 bp
->flags
|= BNXT_FLAG_VF
;
5959 bp
->flags
|= BNXT_FLAG_MSIX_CAP
;
5961 rc
= bnxt_init_board(pdev
, dev
);
5965 dev
->netdev_ops
= &bnxt_netdev_ops
;
5966 dev
->watchdog_timeo
= BNXT_TX_TIMEOUT
;
5967 dev
->ethtool_ops
= &bnxt_ethtool_ops
;
5969 pci_set_drvdata(pdev
, dev
);
5971 dev
->hw_features
= NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
| NETIF_F_SG
|
5972 NETIF_F_TSO
| NETIF_F_TSO6
|
5973 NETIF_F_GSO_UDP_TUNNEL
| NETIF_F_GSO_GRE
|
5974 NETIF_F_GSO_IPIP
| NETIF_F_GSO_SIT
|
5976 NETIF_F_RXCSUM
| NETIF_F_LRO
| NETIF_F_GRO
;
5978 dev
->hw_enc_features
=
5979 NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
| NETIF_F_SG
|
5980 NETIF_F_TSO
| NETIF_F_TSO6
|
5981 NETIF_F_GSO_UDP_TUNNEL
| NETIF_F_GSO_GRE
|
5982 NETIF_F_GSO_IPIP
| NETIF_F_GSO_SIT
;
5983 dev
->vlan_features
= dev
->hw_features
| NETIF_F_HIGHDMA
;
5984 dev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_RX
| NETIF_F_HW_VLAN_CTAG_TX
|
5985 NETIF_F_HW_VLAN_STAG_RX
| NETIF_F_HW_VLAN_STAG_TX
;
5986 dev
->features
|= dev
->hw_features
| NETIF_F_HIGHDMA
;
5987 dev
->priv_flags
|= IFF_UNICAST_FLT
;
5989 #ifdef CONFIG_BNXT_SRIOV
5990 init_waitqueue_head(&bp
->sriov_cfg_wait
);
5992 rc
= bnxt_alloc_hwrm_resources(bp
);
5996 mutex_init(&bp
->hwrm_cmd_lock
);
5997 bnxt_hwrm_ver_get(bp
);
5999 rc
= bnxt_hwrm_func_drv_rgtr(bp
);
6003 /* Get the MAX capabilities for this function */
6004 rc
= bnxt_hwrm_func_qcaps(bp
);
6006 netdev_err(bp
->dev
, "hwrm query capability failure rc: %x\n",
6012 rc
= bnxt_hwrm_queue_qportcfg(bp
);
6014 netdev_err(bp
->dev
, "hwrm query qportcfg failure rc: %x\n",
6020 bnxt_set_tpa_flags(bp
);
6021 bnxt_set_ring_params(bp
);
6023 bp
->pf
.max_irqs
= max_irqs
;
6024 #if defined(CONFIG_BNXT_SRIOV)
6026 bp
->vf
.max_irqs
= max_irqs
;
6028 bnxt_set_dflt_rings(bp
);
6031 dev
->hw_features
|= NETIF_F_NTUPLE
;
6032 if (bnxt_rfs_capable(bp
)) {
6033 bp
->flags
|= BNXT_FLAG_RFS
;
6034 dev
->features
|= NETIF_F_NTUPLE
;
6038 if (dev
->hw_features
& NETIF_F_HW_VLAN_CTAG_RX
)
6039 bp
->flags
|= BNXT_FLAG_STRIP_VLAN
;
6041 rc
= bnxt_probe_phy(bp
);
6045 rc
= register_netdev(dev
);
6049 netdev_info(dev
, "%s found at mem %lx, node addr %pM\n",
6050 board_info
[ent
->driver_data
].name
,
6051 (long)pci_resource_start(pdev
, 0), dev
->dev_addr
);
6056 pci_iounmap(pdev
, bp
->bar0
);
6057 pci_release_regions(pdev
);
6058 pci_disable_device(pdev
);
6066 * bnxt_io_error_detected - called when PCI error is detected
6067 * @pdev: Pointer to PCI device
6068 * @state: The current pci connection state
6070 * This function is called after a PCI bus error affecting
6071 * this device has been detected.
6073 static pci_ers_result_t
bnxt_io_error_detected(struct pci_dev
*pdev
,
6074 pci_channel_state_t state
)
6076 struct net_device
*netdev
= pci_get_drvdata(pdev
);
6078 netdev_info(netdev
, "PCI I/O error detected\n");
6081 netif_device_detach(netdev
);
6083 if (state
== pci_channel_io_perm_failure
) {
6085 return PCI_ERS_RESULT_DISCONNECT
;
6088 if (netif_running(netdev
))
6091 pci_disable_device(pdev
);
6094 /* Request a slot slot reset. */
6095 return PCI_ERS_RESULT_NEED_RESET
;
6099 * bnxt_io_slot_reset - called after the pci bus has been reset.
6100 * @pdev: Pointer to PCI device
6102 * Restart the card from scratch, as if from a cold-boot.
6103 * At this point, the card has exprienced a hard reset,
6104 * followed by fixups by BIOS, and has its config space
6105 * set up identically to what it was at cold boot.
6107 static pci_ers_result_t
bnxt_io_slot_reset(struct pci_dev
*pdev
)
6109 struct net_device
*netdev
= pci_get_drvdata(pdev
);
6110 struct bnxt
*bp
= netdev_priv(netdev
);
6112 pci_ers_result_t result
= PCI_ERS_RESULT_DISCONNECT
;
6114 netdev_info(bp
->dev
, "PCI Slot Reset\n");
6118 if (pci_enable_device(pdev
)) {
6120 "Cannot re-enable PCI device after reset.\n");
6122 pci_set_master(pdev
);
6124 if (netif_running(netdev
))
6125 err
= bnxt_open(netdev
);
6128 result
= PCI_ERS_RESULT_RECOVERED
;
6131 if (result
!= PCI_ERS_RESULT_RECOVERED
&& netif_running(netdev
))
6136 err
= pci_cleanup_aer_uncorrect_error_status(pdev
);
6139 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
6140 err
); /* non-fatal, continue */
6143 return PCI_ERS_RESULT_RECOVERED
;
6147 * bnxt_io_resume - called when traffic can start flowing again.
6148 * @pdev: Pointer to PCI device
6150 * This callback is called when the error recovery driver tells
6151 * us that its OK to resume normal operation.
6153 static void bnxt_io_resume(struct pci_dev
*pdev
)
6155 struct net_device
*netdev
= pci_get_drvdata(pdev
);
6159 netif_device_attach(netdev
);
6164 static const struct pci_error_handlers bnxt_err_handler
= {
6165 .error_detected
= bnxt_io_error_detected
,
6166 .slot_reset
= bnxt_io_slot_reset
,
6167 .resume
= bnxt_io_resume
6170 static struct pci_driver bnxt_pci_driver
= {
6171 .name
= DRV_MODULE_NAME
,
6172 .id_table
= bnxt_pci_tbl
,
6173 .probe
= bnxt_init_one
,
6174 .remove
= bnxt_remove_one
,
6175 .err_handler
= &bnxt_err_handler
,
6176 #if defined(CONFIG_BNXT_SRIOV)
6177 .sriov_configure
= bnxt_sriov_configure
,
6181 module_pci_driver(bnxt_pci_driver
);