1 /* Broadcom NetXtreme-C/E network driver.
3 * Copyright (c) 2014-2016 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
10 #include <linux/module.h>
12 #include <linux/stringify.h>
13 #include <linux/kernel.h>
14 #include <linux/timer.h>
15 #include <linux/errno.h>
16 #include <linux/ioport.h>
17 #include <linux/slab.h>
18 #include <linux/vmalloc.h>
19 #include <linux/interrupt.h>
20 #include <linux/pci.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23 #include <linux/skbuff.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/bitops.h>
27 #include <linux/irq.h>
28 #include <linux/delay.h>
29 #include <asm/byteorder.h>
31 #include <linux/time.h>
32 #include <linux/mii.h>
34 #include <linux/if_vlan.h>
38 #include <net/checksum.h>
39 #include <net/ip6_checksum.h>
40 #if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE)
41 #include <net/vxlan.h>
43 #ifdef CONFIG_NET_RX_BUSY_POLL
44 #include <net/busy_poll.h>
46 #include <linux/workqueue.h>
47 #include <linux/prefetch.h>
48 #include <linux/cache.h>
49 #include <linux/log2.h>
50 #include <linux/aer.h>
51 #include <linux/bitmap.h>
52 #include <linux/cpu_rmap.h>
56 #include "bnxt_sriov.h"
57 #include "bnxt_ethtool.h"
59 #define BNXT_TX_TIMEOUT (5 * HZ)
61 static const char version
[] =
62 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME
" v" DRV_MODULE_VERSION
"\n";
64 MODULE_LICENSE("GPL");
65 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
66 MODULE_VERSION(DRV_MODULE_VERSION
);
68 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
69 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
70 #define BNXT_RX_COPY_THRESH 256
72 #define BNXT_TX_PUSH_THRESH 164
86 /* indexed by enum above */
90 { "Broadcom BCM57301 NetXtreme-C Single-port 10Gb Ethernet" },
91 { "Broadcom BCM57302 NetXtreme-C Dual-port 10Gb/25Gb Ethernet" },
92 { "Broadcom BCM57304 NetXtreme-C Dual-port 10Gb/25Gb/40Gb/50Gb Ethernet" },
93 { "Broadcom BCM57402 NetXtreme-E Dual-port 10Gb Ethernet" },
94 { "Broadcom BCM57404 NetXtreme-E Dual-port 10Gb/25Gb Ethernet" },
95 { "Broadcom BCM57406 NetXtreme-E Dual-port 10GBase-T Ethernet" },
96 { "Broadcom BCM57314 NetXtreme-C Dual-port 10Gb/25Gb/40Gb/50Gb Ethernet" },
97 { "Broadcom BCM57304 NetXtreme-C Ethernet Virtual Function" },
98 { "Broadcom BCM57404 NetXtreme-E Ethernet Virtual Function" },
101 static const struct pci_device_id bnxt_pci_tbl
[] = {
102 { PCI_VDEVICE(BROADCOM
, 0x16c8), .driver_data
= BCM57301
},
103 { PCI_VDEVICE(BROADCOM
, 0x16c9), .driver_data
= BCM57302
},
104 { PCI_VDEVICE(BROADCOM
, 0x16ca), .driver_data
= BCM57304
},
105 { PCI_VDEVICE(BROADCOM
, 0x16d0), .driver_data
= BCM57402
},
106 { PCI_VDEVICE(BROADCOM
, 0x16d1), .driver_data
= BCM57404
},
107 { PCI_VDEVICE(BROADCOM
, 0x16d2), .driver_data
= BCM57406
},
108 { PCI_VDEVICE(BROADCOM
, 0x16df), .driver_data
= BCM57314
},
109 #ifdef CONFIG_BNXT_SRIOV
110 { PCI_VDEVICE(BROADCOM
, 0x16cb), .driver_data
= BCM57304_VF
},
111 { PCI_VDEVICE(BROADCOM
, 0x16d3), .driver_data
= BCM57404_VF
},
116 MODULE_DEVICE_TABLE(pci
, bnxt_pci_tbl
);
118 static const u16 bnxt_vf_req_snif
[] = {
121 HWRM_CFA_L2_FILTER_ALLOC
,
124 static const u16 bnxt_async_events_arr
[] = {
125 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE
,
126 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD
,
127 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED
,
128 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE
,
131 static bool bnxt_vf_pciid(enum board_idx idx
)
133 return (idx
== BCM57304_VF
|| idx
== BCM57404_VF
);
136 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
137 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
138 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
140 #define BNXT_CP_DB_REARM(db, raw_cons) \
141 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
143 #define BNXT_CP_DB(db, raw_cons) \
144 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
146 #define BNXT_CP_DB_IRQ_DIS(db) \
147 writel(DB_CP_IRQ_DIS_FLAGS, db)
149 static inline u32
bnxt_tx_avail(struct bnxt
*bp
, struct bnxt_tx_ring_info
*txr
)
151 /* Tell compiler to fetch tx indices from memory. */
154 return bp
->tx_ring_size
-
155 ((txr
->tx_prod
- txr
->tx_cons
) & bp
->tx_ring_mask
);
158 static const u16 bnxt_lhint_arr
[] = {
159 TX_BD_FLAGS_LHINT_512_AND_SMALLER
,
160 TX_BD_FLAGS_LHINT_512_TO_1023
,
161 TX_BD_FLAGS_LHINT_1024_TO_2047
,
162 TX_BD_FLAGS_LHINT_1024_TO_2047
,
163 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
164 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
165 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
166 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
167 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
168 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
169 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
170 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
171 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
172 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
173 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
174 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
175 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
176 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
177 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
180 static netdev_tx_t
bnxt_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
182 struct bnxt
*bp
= netdev_priv(dev
);
184 struct tx_bd_ext
*txbd1
;
185 struct netdev_queue
*txq
;
188 unsigned int length
, pad
= 0;
189 u32 len
, free_size
, vlan_tag_flags
, cfa_action
, flags
;
191 struct pci_dev
*pdev
= bp
->pdev
;
192 struct bnxt_tx_ring_info
*txr
;
193 struct bnxt_sw_tx_bd
*tx_buf
;
195 i
= skb_get_queue_mapping(skb
);
196 if (unlikely(i
>= bp
->tx_nr_rings
)) {
197 dev_kfree_skb_any(skb
);
201 txr
= &bp
->tx_ring
[i
];
202 txq
= netdev_get_tx_queue(dev
, i
);
205 free_size
= bnxt_tx_avail(bp
, txr
);
206 if (unlikely(free_size
< skb_shinfo(skb
)->nr_frags
+ 2)) {
207 netif_tx_stop_queue(txq
);
208 return NETDEV_TX_BUSY
;
212 len
= skb_headlen(skb
);
213 last_frag
= skb_shinfo(skb
)->nr_frags
;
215 txbd
= &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
217 txbd
->tx_bd_opaque
= prod
;
219 tx_buf
= &txr
->tx_buf_ring
[prod
];
221 tx_buf
->nr_frags
= last_frag
;
225 if (skb_vlan_tag_present(skb
)) {
226 vlan_tag_flags
= TX_BD_CFA_META_KEY_VLAN
|
227 skb_vlan_tag_get(skb
);
228 /* Currently supports 8021Q, 8021AD vlan offloads
229 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
231 if (skb
->vlan_proto
== htons(ETH_P_8021Q
))
232 vlan_tag_flags
|= 1 << TX_BD_CFA_META_TPID_SHIFT
;
235 if (free_size
== bp
->tx_ring_size
&& length
<= bp
->tx_push_thresh
) {
236 struct tx_push_buffer
*tx_push_buf
= txr
->tx_push
;
237 struct tx_push_bd
*tx_push
= &tx_push_buf
->push_bd
;
238 struct tx_bd_ext
*tx_push1
= &tx_push
->txbd2
;
239 void *pdata
= tx_push_buf
->data
;
243 /* Set COAL_NOW to be ready quickly for the next push */
244 tx_push
->tx_bd_len_flags_type
=
245 cpu_to_le32((length
<< TX_BD_LEN_SHIFT
) |
246 TX_BD_TYPE_LONG_TX_BD
|
247 TX_BD_FLAGS_LHINT_512_AND_SMALLER
|
248 TX_BD_FLAGS_COAL_NOW
|
249 TX_BD_FLAGS_PACKET_END
|
250 (2 << TX_BD_FLAGS_BD_CNT_SHIFT
));
252 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
253 tx_push1
->tx_bd_hsize_lflags
=
254 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM
);
256 tx_push1
->tx_bd_hsize_lflags
= 0;
258 tx_push1
->tx_bd_cfa_meta
= cpu_to_le32(vlan_tag_flags
);
259 tx_push1
->tx_bd_cfa_action
= cpu_to_le32(cfa_action
);
261 end
= pdata
+ length
;
262 end
= PTR_ALIGN(end
, 8) - 1;
265 skb_copy_from_linear_data(skb
, pdata
, len
);
267 for (j
= 0; j
< last_frag
; j
++) {
268 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[j
];
271 fptr
= skb_frag_address_safe(frag
);
275 memcpy(pdata
, fptr
, skb_frag_size(frag
));
276 pdata
+= skb_frag_size(frag
);
279 txbd
->tx_bd_len_flags_type
= tx_push
->tx_bd_len_flags_type
;
280 txbd
->tx_bd_haddr
= txr
->data_mapping
;
281 prod
= NEXT_TX(prod
);
282 txbd
= &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
283 memcpy(txbd
, tx_push1
, sizeof(*txbd
));
284 prod
= NEXT_TX(prod
);
286 cpu_to_le32(DB_KEY_TX_PUSH
| DB_LONG_TX_PUSH
| prod
);
290 netdev_tx_sent_queue(txq
, skb
->len
);
291 wmb(); /* Sync is_push and byte queue before pushing data */
293 push_len
= (length
+ sizeof(*tx_push
) + 7) / 8;
295 __iowrite64_copy(txr
->tx_doorbell
, tx_push_buf
, 16);
296 __iowrite64_copy(txr
->tx_doorbell
+ 4, tx_push_buf
+ 1,
299 __iowrite64_copy(txr
->tx_doorbell
, tx_push_buf
,
307 if (length
< BNXT_MIN_PKT_SIZE
) {
308 pad
= BNXT_MIN_PKT_SIZE
- length
;
309 if (skb_pad(skb
, pad
)) {
310 /* SKB already freed. */
314 length
= BNXT_MIN_PKT_SIZE
;
317 mapping
= dma_map_single(&pdev
->dev
, skb
->data
, len
, DMA_TO_DEVICE
);
319 if (unlikely(dma_mapping_error(&pdev
->dev
, mapping
))) {
320 dev_kfree_skb_any(skb
);
325 dma_unmap_addr_set(tx_buf
, mapping
, mapping
);
326 flags
= (len
<< TX_BD_LEN_SHIFT
) | TX_BD_TYPE_LONG_TX_BD
|
327 ((last_frag
+ 2) << TX_BD_FLAGS_BD_CNT_SHIFT
);
329 txbd
->tx_bd_haddr
= cpu_to_le64(mapping
);
331 prod
= NEXT_TX(prod
);
332 txbd1
= (struct tx_bd_ext
*)
333 &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
335 txbd1
->tx_bd_hsize_lflags
= 0;
336 if (skb_is_gso(skb
)) {
339 if (skb
->encapsulation
)
340 hdr_len
= skb_inner_network_offset(skb
) +
341 skb_inner_network_header_len(skb
) +
342 inner_tcp_hdrlen(skb
);
344 hdr_len
= skb_transport_offset(skb
) +
347 txbd1
->tx_bd_hsize_lflags
= cpu_to_le32(TX_BD_FLAGS_LSO
|
349 (hdr_len
<< (TX_BD_HSIZE_SHIFT
- 1)));
350 length
= skb_shinfo(skb
)->gso_size
;
351 txbd1
->tx_bd_mss
= cpu_to_le32(length
);
353 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
354 txbd1
->tx_bd_hsize_lflags
=
355 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM
);
356 txbd1
->tx_bd_mss
= 0;
360 flags
|= bnxt_lhint_arr
[length
];
361 txbd
->tx_bd_len_flags_type
= cpu_to_le32(flags
);
363 txbd1
->tx_bd_cfa_meta
= cpu_to_le32(vlan_tag_flags
);
364 txbd1
->tx_bd_cfa_action
= cpu_to_le32(cfa_action
);
365 for (i
= 0; i
< last_frag
; i
++) {
366 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
368 prod
= NEXT_TX(prod
);
369 txbd
= &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
371 len
= skb_frag_size(frag
);
372 mapping
= skb_frag_dma_map(&pdev
->dev
, frag
, 0, len
,
375 if (unlikely(dma_mapping_error(&pdev
->dev
, mapping
)))
378 tx_buf
= &txr
->tx_buf_ring
[prod
];
379 dma_unmap_addr_set(tx_buf
, mapping
, mapping
);
381 txbd
->tx_bd_haddr
= cpu_to_le64(mapping
);
383 flags
= len
<< TX_BD_LEN_SHIFT
;
384 txbd
->tx_bd_len_flags_type
= cpu_to_le32(flags
);
388 txbd
->tx_bd_len_flags_type
=
389 cpu_to_le32(((len
+ pad
) << TX_BD_LEN_SHIFT
) | flags
|
390 TX_BD_FLAGS_PACKET_END
);
392 netdev_tx_sent_queue(txq
, skb
->len
);
394 /* Sync BD data before updating doorbell */
397 prod
= NEXT_TX(prod
);
400 writel(DB_KEY_TX
| prod
, txr
->tx_doorbell
);
401 writel(DB_KEY_TX
| prod
, txr
->tx_doorbell
);
407 if (unlikely(bnxt_tx_avail(bp
, txr
) <= MAX_SKB_FRAGS
+ 1)) {
408 netif_tx_stop_queue(txq
);
410 /* netif_tx_stop_queue() must be done before checking
411 * tx index in bnxt_tx_avail() below, because in
412 * bnxt_tx_int(), we update tx index before checking for
413 * netif_tx_queue_stopped().
416 if (bnxt_tx_avail(bp
, txr
) > bp
->tx_wake_thresh
)
417 netif_tx_wake_queue(txq
);
424 /* start back at beginning and unmap skb */
426 tx_buf
= &txr
->tx_buf_ring
[prod
];
428 dma_unmap_single(&pdev
->dev
, dma_unmap_addr(tx_buf
, mapping
),
429 skb_headlen(skb
), PCI_DMA_TODEVICE
);
430 prod
= NEXT_TX(prod
);
432 /* unmap remaining mapped pages */
433 for (i
= 0; i
< last_frag
; i
++) {
434 prod
= NEXT_TX(prod
);
435 tx_buf
= &txr
->tx_buf_ring
[prod
];
436 dma_unmap_page(&pdev
->dev
, dma_unmap_addr(tx_buf
, mapping
),
437 skb_frag_size(&skb_shinfo(skb
)->frags
[i
]),
441 dev_kfree_skb_any(skb
);
445 static void bnxt_tx_int(struct bnxt
*bp
, struct bnxt_napi
*bnapi
, int nr_pkts
)
447 struct bnxt_tx_ring_info
*txr
= bnapi
->tx_ring
;
448 int index
= txr
- &bp
->tx_ring
[0];
449 struct netdev_queue
*txq
= netdev_get_tx_queue(bp
->dev
, index
);
450 u16 cons
= txr
->tx_cons
;
451 struct pci_dev
*pdev
= bp
->pdev
;
453 unsigned int tx_bytes
= 0;
455 for (i
= 0; i
< nr_pkts
; i
++) {
456 struct bnxt_sw_tx_bd
*tx_buf
;
460 tx_buf
= &txr
->tx_buf_ring
[cons
];
461 cons
= NEXT_TX(cons
);
465 if (tx_buf
->is_push
) {
470 dma_unmap_single(&pdev
->dev
, dma_unmap_addr(tx_buf
, mapping
),
471 skb_headlen(skb
), PCI_DMA_TODEVICE
);
472 last
= tx_buf
->nr_frags
;
474 for (j
= 0; j
< last
; j
++) {
475 cons
= NEXT_TX(cons
);
476 tx_buf
= &txr
->tx_buf_ring
[cons
];
479 dma_unmap_addr(tx_buf
, mapping
),
480 skb_frag_size(&skb_shinfo(skb
)->frags
[j
]),
485 cons
= NEXT_TX(cons
);
487 tx_bytes
+= skb
->len
;
488 dev_kfree_skb_any(skb
);
491 netdev_tx_completed_queue(txq
, nr_pkts
, tx_bytes
);
494 /* Need to make the tx_cons update visible to bnxt_start_xmit()
495 * before checking for netif_tx_queue_stopped(). Without the
496 * memory barrier, there is a small possibility that bnxt_start_xmit()
497 * will miss it and cause the queue to be stopped forever.
501 if (unlikely(netif_tx_queue_stopped(txq
)) &&
502 (bnxt_tx_avail(bp
, txr
) > bp
->tx_wake_thresh
)) {
503 __netif_tx_lock(txq
, smp_processor_id());
504 if (netif_tx_queue_stopped(txq
) &&
505 bnxt_tx_avail(bp
, txr
) > bp
->tx_wake_thresh
&&
506 txr
->dev_state
!= BNXT_DEV_STATE_CLOSING
)
507 netif_tx_wake_queue(txq
);
508 __netif_tx_unlock(txq
);
512 static inline u8
*__bnxt_alloc_rx_data(struct bnxt
*bp
, dma_addr_t
*mapping
,
516 struct pci_dev
*pdev
= bp
->pdev
;
518 data
= kmalloc(bp
->rx_buf_size
, gfp
);
522 *mapping
= dma_map_single(&pdev
->dev
, data
+ BNXT_RX_DMA_OFFSET
,
523 bp
->rx_buf_use_size
, PCI_DMA_FROMDEVICE
);
525 if (dma_mapping_error(&pdev
->dev
, *mapping
)) {
532 static inline int bnxt_alloc_rx_data(struct bnxt
*bp
,
533 struct bnxt_rx_ring_info
*rxr
,
536 struct rx_bd
*rxbd
= &rxr
->rx_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
537 struct bnxt_sw_rx_bd
*rx_buf
= &rxr
->rx_buf_ring
[prod
];
541 data
= __bnxt_alloc_rx_data(bp
, &mapping
, gfp
);
546 dma_unmap_addr_set(rx_buf
, mapping
, mapping
);
548 rxbd
->rx_bd_haddr
= cpu_to_le64(mapping
);
553 static void bnxt_reuse_rx_data(struct bnxt_rx_ring_info
*rxr
, u16 cons
,
556 u16 prod
= rxr
->rx_prod
;
557 struct bnxt_sw_rx_bd
*cons_rx_buf
, *prod_rx_buf
;
558 struct rx_bd
*cons_bd
, *prod_bd
;
560 prod_rx_buf
= &rxr
->rx_buf_ring
[prod
];
561 cons_rx_buf
= &rxr
->rx_buf_ring
[cons
];
563 prod_rx_buf
->data
= data
;
565 dma_unmap_addr_set(prod_rx_buf
, mapping
,
566 dma_unmap_addr(cons_rx_buf
, mapping
));
568 prod_bd
= &rxr
->rx_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
569 cons_bd
= &rxr
->rx_desc_ring
[RX_RING(cons
)][RX_IDX(cons
)];
571 prod_bd
->rx_bd_haddr
= cons_bd
->rx_bd_haddr
;
574 static inline u16
bnxt_find_next_agg_idx(struct bnxt_rx_ring_info
*rxr
, u16 idx
)
576 u16 next
, max
= rxr
->rx_agg_bmap_size
;
578 next
= find_next_zero_bit(rxr
->rx_agg_bmap
, max
, idx
);
580 next
= find_first_zero_bit(rxr
->rx_agg_bmap
, max
);
584 static inline int bnxt_alloc_rx_page(struct bnxt
*bp
,
585 struct bnxt_rx_ring_info
*rxr
,
589 &rxr
->rx_agg_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
590 struct bnxt_sw_rx_agg_bd
*rx_agg_buf
;
591 struct pci_dev
*pdev
= bp
->pdev
;
594 u16 sw_prod
= rxr
->rx_sw_agg_prod
;
595 unsigned int offset
= 0;
597 if (PAGE_SIZE
> BNXT_RX_PAGE_SIZE
) {
600 page
= alloc_page(gfp
);
604 rxr
->rx_page_offset
= 0;
606 offset
= rxr
->rx_page_offset
;
607 rxr
->rx_page_offset
+= BNXT_RX_PAGE_SIZE
;
608 if (rxr
->rx_page_offset
== PAGE_SIZE
)
613 page
= alloc_page(gfp
);
618 mapping
= dma_map_page(&pdev
->dev
, page
, offset
, BNXT_RX_PAGE_SIZE
,
620 if (dma_mapping_error(&pdev
->dev
, mapping
)) {
625 if (unlikely(test_bit(sw_prod
, rxr
->rx_agg_bmap
)))
626 sw_prod
= bnxt_find_next_agg_idx(rxr
, sw_prod
);
628 __set_bit(sw_prod
, rxr
->rx_agg_bmap
);
629 rx_agg_buf
= &rxr
->rx_agg_ring
[sw_prod
];
630 rxr
->rx_sw_agg_prod
= NEXT_RX_AGG(sw_prod
);
632 rx_agg_buf
->page
= page
;
633 rx_agg_buf
->offset
= offset
;
634 rx_agg_buf
->mapping
= mapping
;
635 rxbd
->rx_bd_haddr
= cpu_to_le64(mapping
);
636 rxbd
->rx_bd_opaque
= sw_prod
;
640 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi
*bnapi
, u16 cp_cons
,
643 struct bnxt
*bp
= bnapi
->bp
;
644 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
645 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
646 u16 prod
= rxr
->rx_agg_prod
;
647 u16 sw_prod
= rxr
->rx_sw_agg_prod
;
650 for (i
= 0; i
< agg_bufs
; i
++) {
652 struct rx_agg_cmp
*agg
;
653 struct bnxt_sw_rx_agg_bd
*cons_rx_buf
, *prod_rx_buf
;
654 struct rx_bd
*prod_bd
;
657 agg
= (struct rx_agg_cmp
*)
658 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
659 cons
= agg
->rx_agg_cmp_opaque
;
660 __clear_bit(cons
, rxr
->rx_agg_bmap
);
662 if (unlikely(test_bit(sw_prod
, rxr
->rx_agg_bmap
)))
663 sw_prod
= bnxt_find_next_agg_idx(rxr
, sw_prod
);
665 __set_bit(sw_prod
, rxr
->rx_agg_bmap
);
666 prod_rx_buf
= &rxr
->rx_agg_ring
[sw_prod
];
667 cons_rx_buf
= &rxr
->rx_agg_ring
[cons
];
669 /* It is possible for sw_prod to be equal to cons, so
670 * set cons_rx_buf->page to NULL first.
672 page
= cons_rx_buf
->page
;
673 cons_rx_buf
->page
= NULL
;
674 prod_rx_buf
->page
= page
;
675 prod_rx_buf
->offset
= cons_rx_buf
->offset
;
677 prod_rx_buf
->mapping
= cons_rx_buf
->mapping
;
679 prod_bd
= &rxr
->rx_agg_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
681 prod_bd
->rx_bd_haddr
= cpu_to_le64(cons_rx_buf
->mapping
);
682 prod_bd
->rx_bd_opaque
= sw_prod
;
684 prod
= NEXT_RX_AGG(prod
);
685 sw_prod
= NEXT_RX_AGG(sw_prod
);
686 cp_cons
= NEXT_CMP(cp_cons
);
688 rxr
->rx_agg_prod
= prod
;
689 rxr
->rx_sw_agg_prod
= sw_prod
;
692 static struct sk_buff
*bnxt_rx_skb(struct bnxt
*bp
,
693 struct bnxt_rx_ring_info
*rxr
, u16 cons
,
694 u16 prod
, u8
*data
, dma_addr_t dma_addr
,
700 err
= bnxt_alloc_rx_data(bp
, rxr
, prod
, GFP_ATOMIC
);
702 bnxt_reuse_rx_data(rxr
, cons
, data
);
706 skb
= build_skb(data
, 0);
707 dma_unmap_single(&bp
->pdev
->dev
, dma_addr
, bp
->rx_buf_use_size
,
714 skb_reserve(skb
, BNXT_RX_OFFSET
);
719 static struct sk_buff
*bnxt_rx_pages(struct bnxt
*bp
, struct bnxt_napi
*bnapi
,
720 struct sk_buff
*skb
, u16 cp_cons
,
723 struct pci_dev
*pdev
= bp
->pdev
;
724 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
725 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
726 u16 prod
= rxr
->rx_agg_prod
;
729 for (i
= 0; i
< agg_bufs
; i
++) {
731 struct rx_agg_cmp
*agg
;
732 struct bnxt_sw_rx_agg_bd
*cons_rx_buf
;
736 agg
= (struct rx_agg_cmp
*)
737 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
738 cons
= agg
->rx_agg_cmp_opaque
;
739 frag_len
= (le32_to_cpu(agg
->rx_agg_cmp_len_flags_type
) &
740 RX_AGG_CMP_LEN
) >> RX_AGG_CMP_LEN_SHIFT
;
742 cons_rx_buf
= &rxr
->rx_agg_ring
[cons
];
743 skb_fill_page_desc(skb
, i
, cons_rx_buf
->page
,
744 cons_rx_buf
->offset
, frag_len
);
745 __clear_bit(cons
, rxr
->rx_agg_bmap
);
747 /* It is possible for bnxt_alloc_rx_page() to allocate
748 * a sw_prod index that equals the cons index, so we
749 * need to clear the cons entry now.
751 mapping
= dma_unmap_addr(cons_rx_buf
, mapping
);
752 page
= cons_rx_buf
->page
;
753 cons_rx_buf
->page
= NULL
;
755 if (bnxt_alloc_rx_page(bp
, rxr
, prod
, GFP_ATOMIC
) != 0) {
756 struct skb_shared_info
*shinfo
;
757 unsigned int nr_frags
;
759 shinfo
= skb_shinfo(skb
);
760 nr_frags
= --shinfo
->nr_frags
;
761 __skb_frag_set_page(&shinfo
->frags
[nr_frags
], NULL
);
765 cons_rx_buf
->page
= page
;
767 /* Update prod since possibly some pages have been
770 rxr
->rx_agg_prod
= prod
;
771 bnxt_reuse_rx_agg_bufs(bnapi
, cp_cons
, agg_bufs
- i
);
775 dma_unmap_page(&pdev
->dev
, mapping
, BNXT_RX_PAGE_SIZE
,
778 skb
->data_len
+= frag_len
;
779 skb
->len
+= frag_len
;
780 skb
->truesize
+= PAGE_SIZE
;
782 prod
= NEXT_RX_AGG(prod
);
783 cp_cons
= NEXT_CMP(cp_cons
);
785 rxr
->rx_agg_prod
= prod
;
789 static int bnxt_agg_bufs_valid(struct bnxt
*bp
, struct bnxt_cp_ring_info
*cpr
,
790 u8 agg_bufs
, u32
*raw_cons
)
793 struct rx_agg_cmp
*agg
;
795 *raw_cons
= ADV_RAW_CMP(*raw_cons
, agg_bufs
);
796 last
= RING_CMP(*raw_cons
);
797 agg
= (struct rx_agg_cmp
*)
798 &cpr
->cp_desc_ring
[CP_RING(last
)][CP_IDX(last
)];
799 return RX_AGG_CMP_VALID(agg
, *raw_cons
);
802 static inline struct sk_buff
*bnxt_copy_skb(struct bnxt_napi
*bnapi
, u8
*data
,
806 struct bnxt
*bp
= bnapi
->bp
;
807 struct pci_dev
*pdev
= bp
->pdev
;
810 skb
= napi_alloc_skb(&bnapi
->napi
, len
);
814 dma_sync_single_for_cpu(&pdev
->dev
, mapping
,
815 bp
->rx_copy_thresh
, PCI_DMA_FROMDEVICE
);
817 memcpy(skb
->data
- BNXT_RX_OFFSET
, data
, len
+ BNXT_RX_OFFSET
);
819 dma_sync_single_for_device(&pdev
->dev
, mapping
,
827 static int bnxt_discard_rx(struct bnxt
*bp
, struct bnxt_napi
*bnapi
,
828 u32
*raw_cons
, void *cmp
)
830 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
831 struct rx_cmp
*rxcmp
= cmp
;
832 u32 tmp_raw_cons
= *raw_cons
;
833 u8 cmp_type
, agg_bufs
= 0;
835 cmp_type
= RX_CMP_TYPE(rxcmp
);
837 if (cmp_type
== CMP_TYPE_RX_L2_CMP
) {
838 agg_bufs
= (le32_to_cpu(rxcmp
->rx_cmp_misc_v1
) &
840 RX_CMP_AGG_BUFS_SHIFT
;
841 } else if (cmp_type
== CMP_TYPE_RX_L2_TPA_END_CMP
) {
842 struct rx_tpa_end_cmp
*tpa_end
= cmp
;
844 agg_bufs
= (le32_to_cpu(tpa_end
->rx_tpa_end_cmp_misc_v1
) &
845 RX_TPA_END_CMP_AGG_BUFS
) >>
846 RX_TPA_END_CMP_AGG_BUFS_SHIFT
;
850 if (!bnxt_agg_bufs_valid(bp
, cpr
, agg_bufs
, &tmp_raw_cons
))
853 *raw_cons
= tmp_raw_cons
;
857 static void bnxt_sched_reset(struct bnxt
*bp
, struct bnxt_rx_ring_info
*rxr
)
859 if (!rxr
->bnapi
->in_reset
) {
860 rxr
->bnapi
->in_reset
= true;
861 set_bit(BNXT_RESET_TASK_SP_EVENT
, &bp
->sp_event
);
862 schedule_work(&bp
->sp_task
);
864 rxr
->rx_next_cons
= 0xffff;
867 static void bnxt_tpa_start(struct bnxt
*bp
, struct bnxt_rx_ring_info
*rxr
,
868 struct rx_tpa_start_cmp
*tpa_start
,
869 struct rx_tpa_start_cmp_ext
*tpa_start1
)
871 u8 agg_id
= TPA_START_AGG_ID(tpa_start
);
873 struct bnxt_tpa_info
*tpa_info
;
874 struct bnxt_sw_rx_bd
*cons_rx_buf
, *prod_rx_buf
;
875 struct rx_bd
*prod_bd
;
878 cons
= tpa_start
->rx_tpa_start_cmp_opaque
;
880 cons_rx_buf
= &rxr
->rx_buf_ring
[cons
];
881 prod_rx_buf
= &rxr
->rx_buf_ring
[prod
];
882 tpa_info
= &rxr
->rx_tpa
[agg_id
];
884 if (unlikely(cons
!= rxr
->rx_next_cons
)) {
885 bnxt_sched_reset(bp
, rxr
);
889 prod_rx_buf
->data
= tpa_info
->data
;
891 mapping
= tpa_info
->mapping
;
892 dma_unmap_addr_set(prod_rx_buf
, mapping
, mapping
);
894 prod_bd
= &rxr
->rx_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
896 prod_bd
->rx_bd_haddr
= cpu_to_le64(mapping
);
898 tpa_info
->data
= cons_rx_buf
->data
;
899 cons_rx_buf
->data
= NULL
;
900 tpa_info
->mapping
= dma_unmap_addr(cons_rx_buf
, mapping
);
903 le32_to_cpu(tpa_start
->rx_tpa_start_cmp_len_flags_type
) >>
904 RX_TPA_START_CMP_LEN_SHIFT
;
905 if (likely(TPA_START_HASH_VALID(tpa_start
))) {
906 u32 hash_type
= TPA_START_HASH_TYPE(tpa_start
);
908 tpa_info
->hash_type
= PKT_HASH_TYPE_L4
;
909 tpa_info
->gso_type
= SKB_GSO_TCPV4
;
910 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
912 tpa_info
->gso_type
= SKB_GSO_TCPV6
;
914 le32_to_cpu(tpa_start
->rx_tpa_start_cmp_rss_hash
);
916 tpa_info
->hash_type
= PKT_HASH_TYPE_NONE
;
917 tpa_info
->gso_type
= 0;
918 if (netif_msg_rx_err(bp
))
919 netdev_warn(bp
->dev
, "TPA packet without valid hash\n");
921 tpa_info
->flags2
= le32_to_cpu(tpa_start1
->rx_tpa_start_cmp_flags2
);
922 tpa_info
->metadata
= le32_to_cpu(tpa_start1
->rx_tpa_start_cmp_metadata
);
924 rxr
->rx_prod
= NEXT_RX(prod
);
925 cons
= NEXT_RX(cons
);
926 rxr
->rx_next_cons
= NEXT_RX(cons
);
927 cons_rx_buf
= &rxr
->rx_buf_ring
[cons
];
929 bnxt_reuse_rx_data(rxr
, cons
, cons_rx_buf
->data
);
930 rxr
->rx_prod
= NEXT_RX(rxr
->rx_prod
);
931 cons_rx_buf
->data
= NULL
;
934 static void bnxt_abort_tpa(struct bnxt
*bp
, struct bnxt_napi
*bnapi
,
935 u16 cp_cons
, u32 agg_bufs
)
938 bnxt_reuse_rx_agg_bufs(bnapi
, cp_cons
, agg_bufs
);
941 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
942 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
944 static inline struct sk_buff
*bnxt_gro_skb(struct bnxt_tpa_info
*tpa_info
,
945 struct rx_tpa_end_cmp
*tpa_end
,
946 struct rx_tpa_end_cmp_ext
*tpa_end1
,
951 int payload_off
, tcp_opt_len
= 0;
955 segs
= TPA_END_TPA_SEGS(tpa_end
);
959 NAPI_GRO_CB(skb
)->count
= segs
;
960 skb_shinfo(skb
)->gso_size
=
961 le32_to_cpu(tpa_end1
->rx_tpa_end_cmp_seg_len
);
962 skb_shinfo(skb
)->gso_type
= tpa_info
->gso_type
;
963 payload_off
= (le32_to_cpu(tpa_end
->rx_tpa_end_cmp_misc_v1
) &
964 RX_TPA_END_CMP_PAYLOAD_OFFSET
) >>
965 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT
;
966 if (TPA_END_GRO_TS(tpa_end
))
969 if (tpa_info
->gso_type
== SKB_GSO_TCPV4
) {
972 nw_off
= payload_off
- BNXT_IPV4_HDR_SIZE
- tcp_opt_len
-
974 skb_set_network_header(skb
, nw_off
);
976 skb_set_transport_header(skb
, nw_off
+ sizeof(struct iphdr
));
977 len
= skb
->len
- skb_transport_offset(skb
);
979 th
->check
= ~tcp_v4_check(len
, iph
->saddr
, iph
->daddr
, 0);
980 } else if (tpa_info
->gso_type
== SKB_GSO_TCPV6
) {
983 nw_off
= payload_off
- BNXT_IPV6_HDR_SIZE
- tcp_opt_len
-
985 skb_set_network_header(skb
, nw_off
);
987 skb_set_transport_header(skb
, nw_off
+ sizeof(struct ipv6hdr
));
988 len
= skb
->len
- skb_transport_offset(skb
);
990 th
->check
= ~tcp_v6_check(len
, &iph
->saddr
, &iph
->daddr
, 0);
992 dev_kfree_skb_any(skb
);
995 tcp_gro_complete(skb
);
997 if (nw_off
) { /* tunnel */
998 struct udphdr
*uh
= NULL
;
1000 if (skb
->protocol
== htons(ETH_P_IP
)) {
1001 struct iphdr
*iph
= (struct iphdr
*)skb
->data
;
1003 if (iph
->protocol
== IPPROTO_UDP
)
1004 uh
= (struct udphdr
*)(iph
+ 1);
1006 struct ipv6hdr
*iph
= (struct ipv6hdr
*)skb
->data
;
1008 if (iph
->nexthdr
== IPPROTO_UDP
)
1009 uh
= (struct udphdr
*)(iph
+ 1);
1013 skb_shinfo(skb
)->gso_type
|=
1014 SKB_GSO_UDP_TUNNEL_CSUM
;
1016 skb_shinfo(skb
)->gso_type
|= SKB_GSO_UDP_TUNNEL
;
1023 static inline struct sk_buff
*bnxt_tpa_end(struct bnxt
*bp
,
1024 struct bnxt_napi
*bnapi
,
1026 struct rx_tpa_end_cmp
*tpa_end
,
1027 struct rx_tpa_end_cmp_ext
*tpa_end1
,
1030 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1031 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
1032 u8 agg_id
= TPA_END_AGG_ID(tpa_end
);
1034 u16 cp_cons
= RING_CMP(*raw_cons
);
1036 struct bnxt_tpa_info
*tpa_info
;
1038 struct sk_buff
*skb
;
1040 if (unlikely(bnapi
->in_reset
)) {
1041 int rc
= bnxt_discard_rx(bp
, bnapi
, raw_cons
, tpa_end
);
1044 return ERR_PTR(-EBUSY
);
1048 tpa_info
= &rxr
->rx_tpa
[agg_id
];
1049 data
= tpa_info
->data
;
1051 len
= tpa_info
->len
;
1052 mapping
= tpa_info
->mapping
;
1054 agg_bufs
= (le32_to_cpu(tpa_end
->rx_tpa_end_cmp_misc_v1
) &
1055 RX_TPA_END_CMP_AGG_BUFS
) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT
;
1058 if (!bnxt_agg_bufs_valid(bp
, cpr
, agg_bufs
, raw_cons
))
1059 return ERR_PTR(-EBUSY
);
1062 cp_cons
= NEXT_CMP(cp_cons
);
1065 if (unlikely(agg_bufs
> MAX_SKB_FRAGS
)) {
1066 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
1067 netdev_warn(bp
->dev
, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1068 agg_bufs
, (int)MAX_SKB_FRAGS
);
1072 if (len
<= bp
->rx_copy_thresh
) {
1073 skb
= bnxt_copy_skb(bnapi
, data
, len
, mapping
);
1075 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
1080 dma_addr_t new_mapping
;
1082 new_data
= __bnxt_alloc_rx_data(bp
, &new_mapping
, GFP_ATOMIC
);
1084 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
1088 tpa_info
->data
= new_data
;
1089 tpa_info
->mapping
= new_mapping
;
1091 skb
= build_skb(data
, 0);
1092 dma_unmap_single(&bp
->pdev
->dev
, mapping
, bp
->rx_buf_use_size
,
1093 PCI_DMA_FROMDEVICE
);
1097 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
1100 skb_reserve(skb
, BNXT_RX_OFFSET
);
1105 skb
= bnxt_rx_pages(bp
, bnapi
, skb
, cp_cons
, agg_bufs
);
1107 /* Page reuse already handled by bnxt_rx_pages(). */
1111 skb
->protocol
= eth_type_trans(skb
, bp
->dev
);
1113 if (tpa_info
->hash_type
!= PKT_HASH_TYPE_NONE
)
1114 skb_set_hash(skb
, tpa_info
->rss_hash
, tpa_info
->hash_type
);
1116 if ((tpa_info
->flags2
& RX_CMP_FLAGS2_META_FORMAT_VLAN
) &&
1117 (skb
->dev
->features
& NETIF_F_HW_VLAN_CTAG_RX
)) {
1118 u16 vlan_proto
= tpa_info
->metadata
>>
1119 RX_CMP_FLAGS2_METADATA_TPID_SFT
;
1120 u16 vtag
= tpa_info
->metadata
& RX_CMP_FLAGS2_METADATA_VID_MASK
;
1122 __vlan_hwaccel_put_tag(skb
, htons(vlan_proto
), vtag
);
1125 skb_checksum_none_assert(skb
);
1126 if (likely(tpa_info
->flags2
& RX_TPA_START_CMP_FLAGS2_L4_CS_CALC
)) {
1127 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1129 (tpa_info
->flags2
& RX_CMP_FLAGS2_T_L4_CS_CALC
) >> 3;
1132 if (TPA_END_GRO(tpa_end
))
1133 skb
= bnxt_gro_skb(tpa_info
, tpa_end
, tpa_end1
, skb
);
1138 /* returns the following:
1139 * 1 - 1 packet successfully received
1140 * 0 - successful TPA_START, packet not completed yet
1141 * -EBUSY - completion ring does not have all the agg buffers yet
1142 * -ENOMEM - packet aborted due to out of memory
1143 * -EIO - packet aborted due to hw error indicated in BD
1145 static int bnxt_rx_pkt(struct bnxt
*bp
, struct bnxt_napi
*bnapi
, u32
*raw_cons
,
1148 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1149 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
1150 struct net_device
*dev
= bp
->dev
;
1151 struct rx_cmp
*rxcmp
;
1152 struct rx_cmp_ext
*rxcmp1
;
1153 u32 tmp_raw_cons
= *raw_cons
;
1154 u16 cons
, prod
, cp_cons
= RING_CMP(tmp_raw_cons
);
1155 struct bnxt_sw_rx_bd
*rx_buf
;
1157 u8
*data
, agg_bufs
, cmp_type
;
1158 dma_addr_t dma_addr
;
1159 struct sk_buff
*skb
;
1162 rxcmp
= (struct rx_cmp
*)
1163 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
1165 tmp_raw_cons
= NEXT_RAW_CMP(tmp_raw_cons
);
1166 cp_cons
= RING_CMP(tmp_raw_cons
);
1167 rxcmp1
= (struct rx_cmp_ext
*)
1168 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
1170 if (!RX_CMP_VALID(rxcmp1
, tmp_raw_cons
))
1173 cmp_type
= RX_CMP_TYPE(rxcmp
);
1175 prod
= rxr
->rx_prod
;
1177 if (cmp_type
== CMP_TYPE_RX_L2_TPA_START_CMP
) {
1178 bnxt_tpa_start(bp
, rxr
, (struct rx_tpa_start_cmp
*)rxcmp
,
1179 (struct rx_tpa_start_cmp_ext
*)rxcmp1
);
1181 goto next_rx_no_prod
;
1183 } else if (cmp_type
== CMP_TYPE_RX_L2_TPA_END_CMP
) {
1184 skb
= bnxt_tpa_end(bp
, bnapi
, &tmp_raw_cons
,
1185 (struct rx_tpa_end_cmp
*)rxcmp
,
1186 (struct rx_tpa_end_cmp_ext
*)rxcmp1
,
1189 if (unlikely(IS_ERR(skb
)))
1194 skb_record_rx_queue(skb
, bnapi
->index
);
1195 skb_mark_napi_id(skb
, &bnapi
->napi
);
1196 if (bnxt_busy_polling(bnapi
))
1197 netif_receive_skb(skb
);
1199 napi_gro_receive(&bnapi
->napi
, skb
);
1202 goto next_rx_no_prod
;
1205 cons
= rxcmp
->rx_cmp_opaque
;
1206 rx_buf
= &rxr
->rx_buf_ring
[cons
];
1207 data
= rx_buf
->data
;
1208 if (unlikely(cons
!= rxr
->rx_next_cons
)) {
1209 int rc1
= bnxt_discard_rx(bp
, bnapi
, raw_cons
, rxcmp
);
1211 bnxt_sched_reset(bp
, rxr
);
1216 agg_bufs
= (le32_to_cpu(rxcmp
->rx_cmp_misc_v1
) & RX_CMP_AGG_BUFS
) >>
1217 RX_CMP_AGG_BUFS_SHIFT
;
1220 if (!bnxt_agg_bufs_valid(bp
, cpr
, agg_bufs
, &tmp_raw_cons
))
1223 cp_cons
= NEXT_CMP(cp_cons
);
1227 rx_buf
->data
= NULL
;
1228 if (rxcmp1
->rx_cmp_cfa_code_errors_v2
& RX_CMP_L2_ERRORS
) {
1229 bnxt_reuse_rx_data(rxr
, cons
, data
);
1231 bnxt_reuse_rx_agg_bufs(bnapi
, cp_cons
, agg_bufs
);
1237 len
= le32_to_cpu(rxcmp
->rx_cmp_len_flags_type
) >> RX_CMP_LEN_SHIFT
;
1238 dma_addr
= dma_unmap_addr(rx_buf
, mapping
);
1240 if (len
<= bp
->rx_copy_thresh
) {
1241 skb
= bnxt_copy_skb(bnapi
, data
, len
, dma_addr
);
1242 bnxt_reuse_rx_data(rxr
, cons
, data
);
1248 skb
= bnxt_rx_skb(bp
, rxr
, cons
, prod
, data
, dma_addr
, len
);
1256 skb
= bnxt_rx_pages(bp
, bnapi
, skb
, cp_cons
, agg_bufs
);
1263 if (RX_CMP_HASH_VALID(rxcmp
)) {
1264 u32 hash_type
= RX_CMP_HASH_TYPE(rxcmp
);
1265 enum pkt_hash_types type
= PKT_HASH_TYPE_L4
;
1267 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1268 if (hash_type
!= 1 && hash_type
!= 3)
1269 type
= PKT_HASH_TYPE_L3
;
1270 skb_set_hash(skb
, le32_to_cpu(rxcmp
->rx_cmp_rss_hash
), type
);
1273 skb
->protocol
= eth_type_trans(skb
, dev
);
1275 if ((rxcmp1
->rx_cmp_flags2
&
1276 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN
)) &&
1277 (skb
->dev
->features
& NETIF_F_HW_VLAN_CTAG_RX
)) {
1278 u32 meta_data
= le32_to_cpu(rxcmp1
->rx_cmp_meta_data
);
1279 u16 vtag
= meta_data
& RX_CMP_FLAGS2_METADATA_VID_MASK
;
1280 u16 vlan_proto
= meta_data
>> RX_CMP_FLAGS2_METADATA_TPID_SFT
;
1282 __vlan_hwaccel_put_tag(skb
, htons(vlan_proto
), vtag
);
1285 skb_checksum_none_assert(skb
);
1286 if (RX_CMP_L4_CS_OK(rxcmp1
)) {
1287 if (dev
->features
& NETIF_F_RXCSUM
) {
1288 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1289 skb
->csum_level
= RX_CMP_ENCAP(rxcmp1
);
1292 if (rxcmp1
->rx_cmp_cfa_code_errors_v2
& RX_CMP_L4_CS_ERR_BITS
) {
1293 if (dev
->features
& NETIF_F_RXCSUM
)
1294 cpr
->rx_l4_csum_errors
++;
1298 skb_record_rx_queue(skb
, bnapi
->index
);
1299 skb_mark_napi_id(skb
, &bnapi
->napi
);
1300 if (bnxt_busy_polling(bnapi
))
1301 netif_receive_skb(skb
);
1303 napi_gro_receive(&bnapi
->napi
, skb
);
1307 rxr
->rx_prod
= NEXT_RX(prod
);
1308 rxr
->rx_next_cons
= NEXT_RX(cons
);
1311 *raw_cons
= tmp_raw_cons
;
1316 #define BNXT_GET_EVENT_PORT(data) \
1318 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
1320 static int bnxt_async_event_process(struct bnxt
*bp
,
1321 struct hwrm_async_event_cmpl
*cmpl
)
1323 u16 event_id
= le16_to_cpu(cmpl
->event_id
);
1325 /* TODO CHIMP_FW: Define event id's for link change, error etc */
1327 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE
: {
1328 u32 data1
= le32_to_cpu(cmpl
->event_data1
);
1329 struct bnxt_link_info
*link_info
= &bp
->link_info
;
1332 goto async_event_process_exit
;
1333 if (data1
& 0x20000) {
1334 u16 fw_speed
= link_info
->force_link_speed
;
1335 u32 speed
= bnxt_fw_to_ethtool_speed(fw_speed
);
1337 netdev_warn(bp
->dev
, "Link speed %d no longer supported\n",
1342 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE
:
1343 set_bit(BNXT_LINK_CHNG_SP_EVENT
, &bp
->sp_event
);
1345 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD
:
1346 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT
, &bp
->sp_event
);
1348 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED
: {
1349 u32 data1
= le32_to_cpu(cmpl
->event_data1
);
1350 u16 port_id
= BNXT_GET_EVENT_PORT(data1
);
1355 if (bp
->pf
.port_id
!= port_id
)
1358 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT
, &bp
->sp_event
);
1362 netdev_err(bp
->dev
, "unhandled ASYNC event (id 0x%x)\n",
1364 goto async_event_process_exit
;
1366 schedule_work(&bp
->sp_task
);
1367 async_event_process_exit
:
1371 static int bnxt_hwrm_handler(struct bnxt
*bp
, struct tx_cmp
*txcmp
)
1373 u16 cmpl_type
= TX_CMP_TYPE(txcmp
), vf_id
, seq_id
;
1374 struct hwrm_cmpl
*h_cmpl
= (struct hwrm_cmpl
*)txcmp
;
1375 struct hwrm_fwd_req_cmpl
*fwd_req_cmpl
=
1376 (struct hwrm_fwd_req_cmpl
*)txcmp
;
1378 switch (cmpl_type
) {
1379 case CMPL_BASE_TYPE_HWRM_DONE
:
1380 seq_id
= le16_to_cpu(h_cmpl
->sequence_id
);
1381 if (seq_id
== bp
->hwrm_intr_seq_id
)
1382 bp
->hwrm_intr_seq_id
= HWRM_SEQ_ID_INVALID
;
1384 netdev_err(bp
->dev
, "Invalid hwrm seq id %d\n", seq_id
);
1387 case CMPL_BASE_TYPE_HWRM_FWD_REQ
:
1388 vf_id
= le16_to_cpu(fwd_req_cmpl
->source_id
);
1390 if ((vf_id
< bp
->pf
.first_vf_id
) ||
1391 (vf_id
>= bp
->pf
.first_vf_id
+ bp
->pf
.active_vfs
)) {
1392 netdev_err(bp
->dev
, "Msg contains invalid VF id %x\n",
1397 set_bit(vf_id
- bp
->pf
.first_vf_id
, bp
->pf
.vf_event_bmap
);
1398 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT
, &bp
->sp_event
);
1399 schedule_work(&bp
->sp_task
);
1402 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT
:
1403 bnxt_async_event_process(bp
,
1404 (struct hwrm_async_event_cmpl
*)txcmp
);
1413 static irqreturn_t
bnxt_msix(int irq
, void *dev_instance
)
1415 struct bnxt_napi
*bnapi
= dev_instance
;
1416 struct bnxt
*bp
= bnapi
->bp
;
1417 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1418 u32 cons
= RING_CMP(cpr
->cp_raw_cons
);
1420 prefetch(&cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)]);
1421 napi_schedule(&bnapi
->napi
);
1425 static inline int bnxt_has_work(struct bnxt
*bp
, struct bnxt_cp_ring_info
*cpr
)
1427 u32 raw_cons
= cpr
->cp_raw_cons
;
1428 u16 cons
= RING_CMP(raw_cons
);
1429 struct tx_cmp
*txcmp
;
1431 txcmp
= &cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)];
1433 return TX_CMP_VALID(txcmp
, raw_cons
);
1436 static irqreturn_t
bnxt_inta(int irq
, void *dev_instance
)
1438 struct bnxt_napi
*bnapi
= dev_instance
;
1439 struct bnxt
*bp
= bnapi
->bp
;
1440 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1441 u32 cons
= RING_CMP(cpr
->cp_raw_cons
);
1444 prefetch(&cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)]);
1446 if (!bnxt_has_work(bp
, cpr
)) {
1447 int_status
= readl(bp
->bar0
+ BNXT_CAG_REG_LEGACY_INT_STATUS
);
1448 /* return if erroneous interrupt */
1449 if (!(int_status
& (0x10000 << cpr
->cp_ring_struct
.fw_ring_id
)))
1453 /* disable ring IRQ */
1454 BNXT_CP_DB_IRQ_DIS(cpr
->cp_doorbell
);
1456 /* Return here if interrupt is shared and is disabled. */
1457 if (unlikely(atomic_read(&bp
->intr_sem
) != 0))
1460 napi_schedule(&bnapi
->napi
);
1464 static int bnxt_poll_work(struct bnxt
*bp
, struct bnxt_napi
*bnapi
, int budget
)
1466 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1467 u32 raw_cons
= cpr
->cp_raw_cons
;
1471 bool rx_event
= false;
1472 bool agg_event
= false;
1473 struct tx_cmp
*txcmp
;
1478 cons
= RING_CMP(raw_cons
);
1479 txcmp
= &cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)];
1481 if (!TX_CMP_VALID(txcmp
, raw_cons
))
1484 /* The valid test of the entry must be done first before
1485 * reading any further.
1488 if (TX_CMP_TYPE(txcmp
) == CMP_TYPE_TX_L2_CMP
) {
1490 /* return full budget so NAPI will complete. */
1491 if (unlikely(tx_pkts
> bp
->tx_wake_thresh
))
1493 } else if ((TX_CMP_TYPE(txcmp
) & 0x30) == 0x10) {
1494 rc
= bnxt_rx_pkt(bp
, bnapi
, &raw_cons
, &agg_event
);
1495 if (likely(rc
>= 0))
1497 else if (rc
== -EBUSY
) /* partial completion */
1500 } else if (unlikely((TX_CMP_TYPE(txcmp
) ==
1501 CMPL_BASE_TYPE_HWRM_DONE
) ||
1502 (TX_CMP_TYPE(txcmp
) ==
1503 CMPL_BASE_TYPE_HWRM_FWD_REQ
) ||
1504 (TX_CMP_TYPE(txcmp
) ==
1505 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT
))) {
1506 bnxt_hwrm_handler(bp
, txcmp
);
1508 raw_cons
= NEXT_RAW_CMP(raw_cons
);
1510 if (rx_pkts
== budget
)
1514 cpr
->cp_raw_cons
= raw_cons
;
1515 /* ACK completion ring before freeing tx ring and producing new
1516 * buffers in rx/agg rings to prevent overflowing the completion
1519 BNXT_CP_DB(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
1522 bnxt_tx_int(bp
, bnapi
, tx_pkts
);
1525 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
1527 writel(DB_KEY_RX
| rxr
->rx_prod
, rxr
->rx_doorbell
);
1528 writel(DB_KEY_RX
| rxr
->rx_prod
, rxr
->rx_doorbell
);
1530 writel(DB_KEY_RX
| rxr
->rx_agg_prod
,
1531 rxr
->rx_agg_doorbell
);
1532 writel(DB_KEY_RX
| rxr
->rx_agg_prod
,
1533 rxr
->rx_agg_doorbell
);
1539 static int bnxt_poll(struct napi_struct
*napi
, int budget
)
1541 struct bnxt_napi
*bnapi
= container_of(napi
, struct bnxt_napi
, napi
);
1542 struct bnxt
*bp
= bnapi
->bp
;
1543 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1546 if (!bnxt_lock_napi(bnapi
))
1550 work_done
+= bnxt_poll_work(bp
, bnapi
, budget
- work_done
);
1552 if (work_done
>= budget
)
1555 if (!bnxt_has_work(bp
, cpr
)) {
1556 napi_complete(napi
);
1557 BNXT_CP_DB_REARM(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
1562 bnxt_unlock_napi(bnapi
);
1566 #ifdef CONFIG_NET_RX_BUSY_POLL
1567 static int bnxt_busy_poll(struct napi_struct
*napi
)
1569 struct bnxt_napi
*bnapi
= container_of(napi
, struct bnxt_napi
, napi
);
1570 struct bnxt
*bp
= bnapi
->bp
;
1571 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1572 int rx_work
, budget
= 4;
1574 if (atomic_read(&bp
->intr_sem
) != 0)
1575 return LL_FLUSH_FAILED
;
1577 if (!bnxt_lock_poll(bnapi
))
1578 return LL_FLUSH_BUSY
;
1580 rx_work
= bnxt_poll_work(bp
, bnapi
, budget
);
1582 BNXT_CP_DB_REARM(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
1584 bnxt_unlock_poll(bnapi
);
1589 static void bnxt_free_tx_skbs(struct bnxt
*bp
)
1592 struct pci_dev
*pdev
= bp
->pdev
;
1597 max_idx
= bp
->tx_nr_pages
* TX_DESC_CNT
;
1598 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
1599 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
1602 for (j
= 0; j
< max_idx
;) {
1603 struct bnxt_sw_tx_bd
*tx_buf
= &txr
->tx_buf_ring
[j
];
1604 struct sk_buff
*skb
= tx_buf
->skb
;
1614 if (tx_buf
->is_push
) {
1620 dma_unmap_single(&pdev
->dev
,
1621 dma_unmap_addr(tx_buf
, mapping
),
1625 last
= tx_buf
->nr_frags
;
1627 for (k
= 0; k
< last
; k
++, j
++) {
1628 int ring_idx
= j
& bp
->tx_ring_mask
;
1629 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[k
];
1631 tx_buf
= &txr
->tx_buf_ring
[ring_idx
];
1634 dma_unmap_addr(tx_buf
, mapping
),
1635 skb_frag_size(frag
), PCI_DMA_TODEVICE
);
1639 netdev_tx_reset_queue(netdev_get_tx_queue(bp
->dev
, i
));
1643 static void bnxt_free_rx_skbs(struct bnxt
*bp
)
1645 int i
, max_idx
, max_agg_idx
;
1646 struct pci_dev
*pdev
= bp
->pdev
;
1651 max_idx
= bp
->rx_nr_pages
* RX_DESC_CNT
;
1652 max_agg_idx
= bp
->rx_agg_nr_pages
* RX_DESC_CNT
;
1653 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
1654 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
1658 for (j
= 0; j
< MAX_TPA
; j
++) {
1659 struct bnxt_tpa_info
*tpa_info
=
1661 u8
*data
= tpa_info
->data
;
1668 dma_unmap_addr(tpa_info
, mapping
),
1669 bp
->rx_buf_use_size
,
1670 PCI_DMA_FROMDEVICE
);
1672 tpa_info
->data
= NULL
;
1678 for (j
= 0; j
< max_idx
; j
++) {
1679 struct bnxt_sw_rx_bd
*rx_buf
= &rxr
->rx_buf_ring
[j
];
1680 u8
*data
= rx_buf
->data
;
1685 dma_unmap_single(&pdev
->dev
,
1686 dma_unmap_addr(rx_buf
, mapping
),
1687 bp
->rx_buf_use_size
,
1688 PCI_DMA_FROMDEVICE
);
1690 rx_buf
->data
= NULL
;
1695 for (j
= 0; j
< max_agg_idx
; j
++) {
1696 struct bnxt_sw_rx_agg_bd
*rx_agg_buf
=
1697 &rxr
->rx_agg_ring
[j
];
1698 struct page
*page
= rx_agg_buf
->page
;
1703 dma_unmap_page(&pdev
->dev
,
1704 dma_unmap_addr(rx_agg_buf
, mapping
),
1705 BNXT_RX_PAGE_SIZE
, PCI_DMA_FROMDEVICE
);
1707 rx_agg_buf
->page
= NULL
;
1708 __clear_bit(j
, rxr
->rx_agg_bmap
);
1713 __free_page(rxr
->rx_page
);
1714 rxr
->rx_page
= NULL
;
1719 static void bnxt_free_skbs(struct bnxt
*bp
)
1721 bnxt_free_tx_skbs(bp
);
1722 bnxt_free_rx_skbs(bp
);
1725 static void bnxt_free_ring(struct bnxt
*bp
, struct bnxt_ring_struct
*ring
)
1727 struct pci_dev
*pdev
= bp
->pdev
;
1730 for (i
= 0; i
< ring
->nr_pages
; i
++) {
1731 if (!ring
->pg_arr
[i
])
1734 dma_free_coherent(&pdev
->dev
, ring
->page_size
,
1735 ring
->pg_arr
[i
], ring
->dma_arr
[i
]);
1737 ring
->pg_arr
[i
] = NULL
;
1740 dma_free_coherent(&pdev
->dev
, ring
->nr_pages
* 8,
1741 ring
->pg_tbl
, ring
->pg_tbl_map
);
1742 ring
->pg_tbl
= NULL
;
1744 if (ring
->vmem_size
&& *ring
->vmem
) {
1750 static int bnxt_alloc_ring(struct bnxt
*bp
, struct bnxt_ring_struct
*ring
)
1753 struct pci_dev
*pdev
= bp
->pdev
;
1755 if (ring
->nr_pages
> 1) {
1756 ring
->pg_tbl
= dma_alloc_coherent(&pdev
->dev
,
1764 for (i
= 0; i
< ring
->nr_pages
; i
++) {
1765 ring
->pg_arr
[i
] = dma_alloc_coherent(&pdev
->dev
,
1769 if (!ring
->pg_arr
[i
])
1772 if (ring
->nr_pages
> 1)
1773 ring
->pg_tbl
[i
] = cpu_to_le64(ring
->dma_arr
[i
]);
1776 if (ring
->vmem_size
) {
1777 *ring
->vmem
= vzalloc(ring
->vmem_size
);
1784 static void bnxt_free_rx_rings(struct bnxt
*bp
)
1791 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
1792 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
1793 struct bnxt_ring_struct
*ring
;
1798 kfree(rxr
->rx_agg_bmap
);
1799 rxr
->rx_agg_bmap
= NULL
;
1801 ring
= &rxr
->rx_ring_struct
;
1802 bnxt_free_ring(bp
, ring
);
1804 ring
= &rxr
->rx_agg_ring_struct
;
1805 bnxt_free_ring(bp
, ring
);
1809 static int bnxt_alloc_rx_rings(struct bnxt
*bp
)
1811 int i
, rc
, agg_rings
= 0, tpa_rings
= 0;
1816 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
)
1819 if (bp
->flags
& BNXT_FLAG_TPA
)
1822 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
1823 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
1824 struct bnxt_ring_struct
*ring
;
1826 ring
= &rxr
->rx_ring_struct
;
1828 rc
= bnxt_alloc_ring(bp
, ring
);
1835 ring
= &rxr
->rx_agg_ring_struct
;
1836 rc
= bnxt_alloc_ring(bp
, ring
);
1840 rxr
->rx_agg_bmap_size
= bp
->rx_agg_ring_mask
+ 1;
1841 mem_size
= rxr
->rx_agg_bmap_size
/ 8;
1842 rxr
->rx_agg_bmap
= kzalloc(mem_size
, GFP_KERNEL
);
1843 if (!rxr
->rx_agg_bmap
)
1847 rxr
->rx_tpa
= kcalloc(MAX_TPA
,
1848 sizeof(struct bnxt_tpa_info
),
1858 static void bnxt_free_tx_rings(struct bnxt
*bp
)
1861 struct pci_dev
*pdev
= bp
->pdev
;
1866 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
1867 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
1868 struct bnxt_ring_struct
*ring
;
1871 dma_free_coherent(&pdev
->dev
, bp
->tx_push_size
,
1872 txr
->tx_push
, txr
->tx_push_mapping
);
1873 txr
->tx_push
= NULL
;
1876 ring
= &txr
->tx_ring_struct
;
1878 bnxt_free_ring(bp
, ring
);
1882 static int bnxt_alloc_tx_rings(struct bnxt
*bp
)
1885 struct pci_dev
*pdev
= bp
->pdev
;
1887 bp
->tx_push_size
= 0;
1888 if (bp
->tx_push_thresh
) {
1891 push_size
= L1_CACHE_ALIGN(sizeof(struct tx_push_bd
) +
1892 bp
->tx_push_thresh
);
1894 if (push_size
> 256) {
1896 bp
->tx_push_thresh
= 0;
1899 bp
->tx_push_size
= push_size
;
1902 for (i
= 0, j
= 0; i
< bp
->tx_nr_rings
; i
++) {
1903 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
1904 struct bnxt_ring_struct
*ring
;
1906 ring
= &txr
->tx_ring_struct
;
1908 rc
= bnxt_alloc_ring(bp
, ring
);
1912 if (bp
->tx_push_size
) {
1915 /* One pre-allocated DMA buffer to backup
1918 txr
->tx_push
= dma_alloc_coherent(&pdev
->dev
,
1920 &txr
->tx_push_mapping
,
1926 mapping
= txr
->tx_push_mapping
+
1927 sizeof(struct tx_push_bd
);
1928 txr
->data_mapping
= cpu_to_le64(mapping
);
1930 memset(txr
->tx_push
, 0, sizeof(struct tx_push_bd
));
1932 ring
->queue_id
= bp
->q_info
[j
].queue_id
;
1933 if (i
% bp
->tx_nr_rings_per_tc
== (bp
->tx_nr_rings_per_tc
- 1))
1939 static void bnxt_free_cp_rings(struct bnxt
*bp
)
1946 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
1947 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
1948 struct bnxt_cp_ring_info
*cpr
;
1949 struct bnxt_ring_struct
*ring
;
1954 cpr
= &bnapi
->cp_ring
;
1955 ring
= &cpr
->cp_ring_struct
;
1957 bnxt_free_ring(bp
, ring
);
1961 static int bnxt_alloc_cp_rings(struct bnxt
*bp
)
1965 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
1966 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
1967 struct bnxt_cp_ring_info
*cpr
;
1968 struct bnxt_ring_struct
*ring
;
1973 cpr
= &bnapi
->cp_ring
;
1974 ring
= &cpr
->cp_ring_struct
;
1976 rc
= bnxt_alloc_ring(bp
, ring
);
1983 static void bnxt_init_ring_struct(struct bnxt
*bp
)
1987 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
1988 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
1989 struct bnxt_cp_ring_info
*cpr
;
1990 struct bnxt_rx_ring_info
*rxr
;
1991 struct bnxt_tx_ring_info
*txr
;
1992 struct bnxt_ring_struct
*ring
;
1997 cpr
= &bnapi
->cp_ring
;
1998 ring
= &cpr
->cp_ring_struct
;
1999 ring
->nr_pages
= bp
->cp_nr_pages
;
2000 ring
->page_size
= HW_CMPD_RING_SIZE
;
2001 ring
->pg_arr
= (void **)cpr
->cp_desc_ring
;
2002 ring
->dma_arr
= cpr
->cp_desc_mapping
;
2003 ring
->vmem_size
= 0;
2005 rxr
= bnapi
->rx_ring
;
2009 ring
= &rxr
->rx_ring_struct
;
2010 ring
->nr_pages
= bp
->rx_nr_pages
;
2011 ring
->page_size
= HW_RXBD_RING_SIZE
;
2012 ring
->pg_arr
= (void **)rxr
->rx_desc_ring
;
2013 ring
->dma_arr
= rxr
->rx_desc_mapping
;
2014 ring
->vmem_size
= SW_RXBD_RING_SIZE
* bp
->rx_nr_pages
;
2015 ring
->vmem
= (void **)&rxr
->rx_buf_ring
;
2017 ring
= &rxr
->rx_agg_ring_struct
;
2018 ring
->nr_pages
= bp
->rx_agg_nr_pages
;
2019 ring
->page_size
= HW_RXBD_RING_SIZE
;
2020 ring
->pg_arr
= (void **)rxr
->rx_agg_desc_ring
;
2021 ring
->dma_arr
= rxr
->rx_agg_desc_mapping
;
2022 ring
->vmem_size
= SW_RXBD_AGG_RING_SIZE
* bp
->rx_agg_nr_pages
;
2023 ring
->vmem
= (void **)&rxr
->rx_agg_ring
;
2026 txr
= bnapi
->tx_ring
;
2030 ring
= &txr
->tx_ring_struct
;
2031 ring
->nr_pages
= bp
->tx_nr_pages
;
2032 ring
->page_size
= HW_RXBD_RING_SIZE
;
2033 ring
->pg_arr
= (void **)txr
->tx_desc_ring
;
2034 ring
->dma_arr
= txr
->tx_desc_mapping
;
2035 ring
->vmem_size
= SW_TXBD_RING_SIZE
* bp
->tx_nr_pages
;
2036 ring
->vmem
= (void **)&txr
->tx_buf_ring
;
2040 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct
*ring
, u32 type
)
2044 struct rx_bd
**rx_buf_ring
;
2046 rx_buf_ring
= (struct rx_bd
**)ring
->pg_arr
;
2047 for (i
= 0, prod
= 0; i
< ring
->nr_pages
; i
++) {
2051 rxbd
= rx_buf_ring
[i
];
2055 for (j
= 0; j
< RX_DESC_CNT
; j
++, rxbd
++, prod
++) {
2056 rxbd
->rx_bd_len_flags_type
= cpu_to_le32(type
);
2057 rxbd
->rx_bd_opaque
= prod
;
2062 static int bnxt_init_one_rx_ring(struct bnxt
*bp
, int ring_nr
)
2064 struct net_device
*dev
= bp
->dev
;
2065 struct bnxt_rx_ring_info
*rxr
;
2066 struct bnxt_ring_struct
*ring
;
2070 type
= (bp
->rx_buf_use_size
<< RX_BD_LEN_SHIFT
) |
2071 RX_BD_TYPE_RX_PACKET_BD
| RX_BD_FLAGS_EOP
;
2073 if (NET_IP_ALIGN
== 2)
2074 type
|= RX_BD_FLAGS_SOP
;
2076 rxr
= &bp
->rx_ring
[ring_nr
];
2077 ring
= &rxr
->rx_ring_struct
;
2078 bnxt_init_rxbd_pages(ring
, type
);
2080 prod
= rxr
->rx_prod
;
2081 for (i
= 0; i
< bp
->rx_ring_size
; i
++) {
2082 if (bnxt_alloc_rx_data(bp
, rxr
, prod
, GFP_KERNEL
) != 0) {
2083 netdev_warn(dev
, "init'ed rx ring %d with %d/%d skbs only\n",
2084 ring_nr
, i
, bp
->rx_ring_size
);
2087 prod
= NEXT_RX(prod
);
2089 rxr
->rx_prod
= prod
;
2090 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
2092 ring
= &rxr
->rx_agg_ring_struct
;
2093 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
2095 if (!(bp
->flags
& BNXT_FLAG_AGG_RINGS
))
2098 type
= ((u32
)BNXT_RX_PAGE_SIZE
<< RX_BD_LEN_SHIFT
) |
2099 RX_BD_TYPE_RX_AGG_BD
| RX_BD_FLAGS_SOP
;
2101 bnxt_init_rxbd_pages(ring
, type
);
2103 prod
= rxr
->rx_agg_prod
;
2104 for (i
= 0; i
< bp
->rx_agg_ring_size
; i
++) {
2105 if (bnxt_alloc_rx_page(bp
, rxr
, prod
, GFP_KERNEL
) != 0) {
2106 netdev_warn(dev
, "init'ed rx ring %d with %d/%d pages only\n",
2107 ring_nr
, i
, bp
->rx_ring_size
);
2110 prod
= NEXT_RX_AGG(prod
);
2112 rxr
->rx_agg_prod
= prod
;
2114 if (bp
->flags
& BNXT_FLAG_TPA
) {
2119 for (i
= 0; i
< MAX_TPA
; i
++) {
2120 data
= __bnxt_alloc_rx_data(bp
, &mapping
,
2125 rxr
->rx_tpa
[i
].data
= data
;
2126 rxr
->rx_tpa
[i
].mapping
= mapping
;
2129 netdev_err(bp
->dev
, "No resource allocated for LRO/GRO\n");
2137 static int bnxt_init_rx_rings(struct bnxt
*bp
)
2141 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
2142 rc
= bnxt_init_one_rx_ring(bp
, i
);
2150 static int bnxt_init_tx_rings(struct bnxt
*bp
)
2154 bp
->tx_wake_thresh
= max_t(int, bp
->tx_ring_size
/ 2,
2157 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
2158 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
2159 struct bnxt_ring_struct
*ring
= &txr
->tx_ring_struct
;
2161 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
2167 static void bnxt_free_ring_grps(struct bnxt
*bp
)
2169 kfree(bp
->grp_info
);
2170 bp
->grp_info
= NULL
;
2173 static int bnxt_init_ring_grps(struct bnxt
*bp
, bool irq_re_init
)
2178 bp
->grp_info
= kcalloc(bp
->cp_nr_rings
,
2179 sizeof(struct bnxt_ring_grp_info
),
2184 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2186 bp
->grp_info
[i
].fw_stats_ctx
= INVALID_HW_RING_ID
;
2187 bp
->grp_info
[i
].fw_grp_id
= INVALID_HW_RING_ID
;
2188 bp
->grp_info
[i
].rx_fw_ring_id
= INVALID_HW_RING_ID
;
2189 bp
->grp_info
[i
].agg_fw_ring_id
= INVALID_HW_RING_ID
;
2190 bp
->grp_info
[i
].cp_fw_ring_id
= INVALID_HW_RING_ID
;
2195 static void bnxt_free_vnics(struct bnxt
*bp
)
2197 kfree(bp
->vnic_info
);
2198 bp
->vnic_info
= NULL
;
2202 static int bnxt_alloc_vnics(struct bnxt
*bp
)
2206 #ifdef CONFIG_RFS_ACCEL
2207 if (bp
->flags
& BNXT_FLAG_RFS
)
2208 num_vnics
+= bp
->rx_nr_rings
;
2211 bp
->vnic_info
= kcalloc(num_vnics
, sizeof(struct bnxt_vnic_info
),
2216 bp
->nr_vnics
= num_vnics
;
2220 static void bnxt_init_vnics(struct bnxt
*bp
)
2224 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
2225 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[i
];
2227 vnic
->fw_vnic_id
= INVALID_HW_RING_ID
;
2228 vnic
->fw_rss_cos_lb_ctx
= INVALID_HW_RING_ID
;
2229 vnic
->fw_l2_ctx_id
= INVALID_HW_RING_ID
;
2231 if (bp
->vnic_info
[i
].rss_hash_key
) {
2233 prandom_bytes(vnic
->rss_hash_key
,
2236 memcpy(vnic
->rss_hash_key
,
2237 bp
->vnic_info
[0].rss_hash_key
,
2243 static int bnxt_calc_nr_ring_pages(u32 ring_size
, int desc_per_pg
)
2247 pages
= ring_size
/ desc_per_pg
;
2254 while (pages
& (pages
- 1))
2260 static void bnxt_set_tpa_flags(struct bnxt
*bp
)
2262 bp
->flags
&= ~BNXT_FLAG_TPA
;
2263 if (bp
->dev
->features
& NETIF_F_LRO
)
2264 bp
->flags
|= BNXT_FLAG_LRO
;
2265 if ((bp
->dev
->features
& NETIF_F_GRO
) && (bp
->pdev
->revision
> 0))
2266 bp
->flags
|= BNXT_FLAG_GRO
;
2269 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2272 void bnxt_set_ring_params(struct bnxt
*bp
)
2274 u32 ring_size
, rx_size
, rx_space
;
2275 u32 agg_factor
= 0, agg_ring_size
= 0;
2277 /* 8 for CRC and VLAN */
2278 rx_size
= SKB_DATA_ALIGN(bp
->dev
->mtu
+ ETH_HLEN
+ NET_IP_ALIGN
+ 8);
2280 rx_space
= rx_size
+ NET_SKB_PAD
+
2281 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
2283 bp
->rx_copy_thresh
= BNXT_RX_COPY_THRESH
;
2284 ring_size
= bp
->rx_ring_size
;
2285 bp
->rx_agg_ring_size
= 0;
2286 bp
->rx_agg_nr_pages
= 0;
2288 if (bp
->flags
& BNXT_FLAG_TPA
)
2289 agg_factor
= min_t(u32
, 4, 65536 / BNXT_RX_PAGE_SIZE
);
2291 bp
->flags
&= ~BNXT_FLAG_JUMBO
;
2292 if (rx_space
> PAGE_SIZE
) {
2295 bp
->flags
|= BNXT_FLAG_JUMBO
;
2296 jumbo_factor
= PAGE_ALIGN(bp
->dev
->mtu
- 40) >> PAGE_SHIFT
;
2297 if (jumbo_factor
> agg_factor
)
2298 agg_factor
= jumbo_factor
;
2300 agg_ring_size
= ring_size
* agg_factor
;
2302 if (agg_ring_size
) {
2303 bp
->rx_agg_nr_pages
= bnxt_calc_nr_ring_pages(agg_ring_size
,
2305 if (bp
->rx_agg_nr_pages
> MAX_RX_AGG_PAGES
) {
2306 u32 tmp
= agg_ring_size
;
2308 bp
->rx_agg_nr_pages
= MAX_RX_AGG_PAGES
;
2309 agg_ring_size
= MAX_RX_AGG_PAGES
* RX_DESC_CNT
- 1;
2310 netdev_warn(bp
->dev
, "rx agg ring size %d reduced to %d.\n",
2311 tmp
, agg_ring_size
);
2313 bp
->rx_agg_ring_size
= agg_ring_size
;
2314 bp
->rx_agg_ring_mask
= (bp
->rx_agg_nr_pages
* RX_DESC_CNT
) - 1;
2315 rx_size
= SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH
+ NET_IP_ALIGN
);
2316 rx_space
= rx_size
+ NET_SKB_PAD
+
2317 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
2320 bp
->rx_buf_use_size
= rx_size
;
2321 bp
->rx_buf_size
= rx_space
;
2323 bp
->rx_nr_pages
= bnxt_calc_nr_ring_pages(ring_size
, RX_DESC_CNT
);
2324 bp
->rx_ring_mask
= (bp
->rx_nr_pages
* RX_DESC_CNT
) - 1;
2326 ring_size
= bp
->tx_ring_size
;
2327 bp
->tx_nr_pages
= bnxt_calc_nr_ring_pages(ring_size
, TX_DESC_CNT
);
2328 bp
->tx_ring_mask
= (bp
->tx_nr_pages
* TX_DESC_CNT
) - 1;
2330 ring_size
= bp
->rx_ring_size
* (2 + agg_factor
) + bp
->tx_ring_size
;
2331 bp
->cp_ring_size
= ring_size
;
2333 bp
->cp_nr_pages
= bnxt_calc_nr_ring_pages(ring_size
, CP_DESC_CNT
);
2334 if (bp
->cp_nr_pages
> MAX_CP_PAGES
) {
2335 bp
->cp_nr_pages
= MAX_CP_PAGES
;
2336 bp
->cp_ring_size
= MAX_CP_PAGES
* CP_DESC_CNT
- 1;
2337 netdev_warn(bp
->dev
, "completion ring size %d reduced to %d.\n",
2338 ring_size
, bp
->cp_ring_size
);
2340 bp
->cp_bit
= bp
->cp_nr_pages
* CP_DESC_CNT
;
2341 bp
->cp_ring_mask
= bp
->cp_bit
- 1;
2344 static void bnxt_free_vnic_attributes(struct bnxt
*bp
)
2347 struct bnxt_vnic_info
*vnic
;
2348 struct pci_dev
*pdev
= bp
->pdev
;
2353 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
2354 vnic
= &bp
->vnic_info
[i
];
2356 kfree(vnic
->fw_grp_ids
);
2357 vnic
->fw_grp_ids
= NULL
;
2359 kfree(vnic
->uc_list
);
2360 vnic
->uc_list
= NULL
;
2362 if (vnic
->mc_list
) {
2363 dma_free_coherent(&pdev
->dev
, vnic
->mc_list_size
,
2364 vnic
->mc_list
, vnic
->mc_list_mapping
);
2365 vnic
->mc_list
= NULL
;
2368 if (vnic
->rss_table
) {
2369 dma_free_coherent(&pdev
->dev
, PAGE_SIZE
,
2371 vnic
->rss_table_dma_addr
);
2372 vnic
->rss_table
= NULL
;
2375 vnic
->rss_hash_key
= NULL
;
2380 static int bnxt_alloc_vnic_attributes(struct bnxt
*bp
)
2382 int i
, rc
= 0, size
;
2383 struct bnxt_vnic_info
*vnic
;
2384 struct pci_dev
*pdev
= bp
->pdev
;
2387 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
2388 vnic
= &bp
->vnic_info
[i
];
2390 if (vnic
->flags
& BNXT_VNIC_UCAST_FLAG
) {
2391 int mem_size
= (BNXT_MAX_UC_ADDRS
- 1) * ETH_ALEN
;
2394 vnic
->uc_list
= kmalloc(mem_size
, GFP_KERNEL
);
2395 if (!vnic
->uc_list
) {
2402 if (vnic
->flags
& BNXT_VNIC_MCAST_FLAG
) {
2403 vnic
->mc_list_size
= BNXT_MAX_MC_ADDRS
* ETH_ALEN
;
2405 dma_alloc_coherent(&pdev
->dev
,
2407 &vnic
->mc_list_mapping
,
2409 if (!vnic
->mc_list
) {
2415 if (vnic
->flags
& BNXT_VNIC_RSS_FLAG
)
2416 max_rings
= bp
->rx_nr_rings
;
2420 vnic
->fw_grp_ids
= kcalloc(max_rings
, sizeof(u16
), GFP_KERNEL
);
2421 if (!vnic
->fw_grp_ids
) {
2426 /* Allocate rss table and hash key */
2427 vnic
->rss_table
= dma_alloc_coherent(&pdev
->dev
, PAGE_SIZE
,
2428 &vnic
->rss_table_dma_addr
,
2430 if (!vnic
->rss_table
) {
2435 size
= L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE
* sizeof(u16
));
2437 vnic
->rss_hash_key
= ((void *)vnic
->rss_table
) + size
;
2438 vnic
->rss_hash_key_dma_addr
= vnic
->rss_table_dma_addr
+ size
;
2446 static void bnxt_free_hwrm_resources(struct bnxt
*bp
)
2448 struct pci_dev
*pdev
= bp
->pdev
;
2450 dma_free_coherent(&pdev
->dev
, PAGE_SIZE
, bp
->hwrm_cmd_resp_addr
,
2451 bp
->hwrm_cmd_resp_dma_addr
);
2453 bp
->hwrm_cmd_resp_addr
= NULL
;
2454 if (bp
->hwrm_dbg_resp_addr
) {
2455 dma_free_coherent(&pdev
->dev
, HWRM_DBG_REG_BUF_SIZE
,
2456 bp
->hwrm_dbg_resp_addr
,
2457 bp
->hwrm_dbg_resp_dma_addr
);
2459 bp
->hwrm_dbg_resp_addr
= NULL
;
2463 static int bnxt_alloc_hwrm_resources(struct bnxt
*bp
)
2465 struct pci_dev
*pdev
= bp
->pdev
;
2467 bp
->hwrm_cmd_resp_addr
= dma_alloc_coherent(&pdev
->dev
, PAGE_SIZE
,
2468 &bp
->hwrm_cmd_resp_dma_addr
,
2470 if (!bp
->hwrm_cmd_resp_addr
)
2472 bp
->hwrm_dbg_resp_addr
= dma_alloc_coherent(&pdev
->dev
,
2473 HWRM_DBG_REG_BUF_SIZE
,
2474 &bp
->hwrm_dbg_resp_dma_addr
,
2476 if (!bp
->hwrm_dbg_resp_addr
)
2477 netdev_warn(bp
->dev
, "fail to alloc debug register dma mem\n");
2482 static void bnxt_free_stats(struct bnxt
*bp
)
2485 struct pci_dev
*pdev
= bp
->pdev
;
2487 if (bp
->hw_rx_port_stats
) {
2488 dma_free_coherent(&pdev
->dev
, bp
->hw_port_stats_size
,
2489 bp
->hw_rx_port_stats
,
2490 bp
->hw_rx_port_stats_map
);
2491 bp
->hw_rx_port_stats
= NULL
;
2492 bp
->flags
&= ~BNXT_FLAG_PORT_STATS
;
2498 size
= sizeof(struct ctx_hw_stats
);
2500 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2501 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2502 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
2504 if (cpr
->hw_stats
) {
2505 dma_free_coherent(&pdev
->dev
, size
, cpr
->hw_stats
,
2507 cpr
->hw_stats
= NULL
;
2512 static int bnxt_alloc_stats(struct bnxt
*bp
)
2515 struct pci_dev
*pdev
= bp
->pdev
;
2517 size
= sizeof(struct ctx_hw_stats
);
2519 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2520 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2521 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
2523 cpr
->hw_stats
= dma_alloc_coherent(&pdev
->dev
, size
,
2529 cpr
->hw_stats_ctx_id
= INVALID_STATS_CTX_ID
;
2533 bp
->hw_port_stats_size
= sizeof(struct rx_port_stats
) +
2534 sizeof(struct tx_port_stats
) + 1024;
2536 bp
->hw_rx_port_stats
=
2537 dma_alloc_coherent(&pdev
->dev
, bp
->hw_port_stats_size
,
2538 &bp
->hw_rx_port_stats_map
,
2540 if (!bp
->hw_rx_port_stats
)
2543 bp
->hw_tx_port_stats
= (void *)(bp
->hw_rx_port_stats
+ 1) +
2545 bp
->hw_tx_port_stats_map
= bp
->hw_rx_port_stats_map
+
2546 sizeof(struct rx_port_stats
) + 512;
2547 bp
->flags
|= BNXT_FLAG_PORT_STATS
;
2552 static void bnxt_clear_ring_indices(struct bnxt
*bp
)
2559 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2560 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2561 struct bnxt_cp_ring_info
*cpr
;
2562 struct bnxt_rx_ring_info
*rxr
;
2563 struct bnxt_tx_ring_info
*txr
;
2568 cpr
= &bnapi
->cp_ring
;
2569 cpr
->cp_raw_cons
= 0;
2571 txr
= bnapi
->tx_ring
;
2577 rxr
= bnapi
->rx_ring
;
2580 rxr
->rx_agg_prod
= 0;
2581 rxr
->rx_sw_agg_prod
= 0;
2582 rxr
->rx_next_cons
= 0;
2587 static void bnxt_free_ntp_fltrs(struct bnxt
*bp
, bool irq_reinit
)
2589 #ifdef CONFIG_RFS_ACCEL
2592 /* Under rtnl_lock and all our NAPIs have been disabled. It's
2593 * safe to delete the hash table.
2595 for (i
= 0; i
< BNXT_NTP_FLTR_HASH_SIZE
; i
++) {
2596 struct hlist_head
*head
;
2597 struct hlist_node
*tmp
;
2598 struct bnxt_ntuple_filter
*fltr
;
2600 head
= &bp
->ntp_fltr_hash_tbl
[i
];
2601 hlist_for_each_entry_safe(fltr
, tmp
, head
, hash
) {
2602 hlist_del(&fltr
->hash
);
2607 kfree(bp
->ntp_fltr_bmap
);
2608 bp
->ntp_fltr_bmap
= NULL
;
2610 bp
->ntp_fltr_count
= 0;
2614 static int bnxt_alloc_ntp_fltrs(struct bnxt
*bp
)
2616 #ifdef CONFIG_RFS_ACCEL
2619 if (!(bp
->flags
& BNXT_FLAG_RFS
))
2622 for (i
= 0; i
< BNXT_NTP_FLTR_HASH_SIZE
; i
++)
2623 INIT_HLIST_HEAD(&bp
->ntp_fltr_hash_tbl
[i
]);
2625 bp
->ntp_fltr_count
= 0;
2626 bp
->ntp_fltr_bmap
= kzalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR
),
2629 if (!bp
->ntp_fltr_bmap
)
2638 static void bnxt_free_mem(struct bnxt
*bp
, bool irq_re_init
)
2640 bnxt_free_vnic_attributes(bp
);
2641 bnxt_free_tx_rings(bp
);
2642 bnxt_free_rx_rings(bp
);
2643 bnxt_free_cp_rings(bp
);
2644 bnxt_free_ntp_fltrs(bp
, irq_re_init
);
2646 bnxt_free_stats(bp
);
2647 bnxt_free_ring_grps(bp
);
2648 bnxt_free_vnics(bp
);
2656 bnxt_clear_ring_indices(bp
);
2660 static int bnxt_alloc_mem(struct bnxt
*bp
, bool irq_re_init
)
2662 int i
, j
, rc
, size
, arr_size
;
2666 /* Allocate bnapi mem pointer array and mem block for
2669 arr_size
= L1_CACHE_ALIGN(sizeof(struct bnxt_napi
*) *
2671 size
= L1_CACHE_ALIGN(sizeof(struct bnxt_napi
));
2672 bnapi
= kzalloc(arr_size
+ size
* bp
->cp_nr_rings
, GFP_KERNEL
);
2678 for (i
= 0; i
< bp
->cp_nr_rings
; i
++, bnapi
+= size
) {
2679 bp
->bnapi
[i
] = bnapi
;
2680 bp
->bnapi
[i
]->index
= i
;
2681 bp
->bnapi
[i
]->bp
= bp
;
2684 bp
->rx_ring
= kcalloc(bp
->rx_nr_rings
,
2685 sizeof(struct bnxt_rx_ring_info
),
2690 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
2691 bp
->rx_ring
[i
].bnapi
= bp
->bnapi
[i
];
2692 bp
->bnapi
[i
]->rx_ring
= &bp
->rx_ring
[i
];
2695 bp
->tx_ring
= kcalloc(bp
->tx_nr_rings
,
2696 sizeof(struct bnxt_tx_ring_info
),
2701 if (bp
->flags
& BNXT_FLAG_SHARED_RINGS
)
2704 j
= bp
->rx_nr_rings
;
2706 for (i
= 0; i
< bp
->tx_nr_rings
; i
++, j
++) {
2707 bp
->tx_ring
[i
].bnapi
= bp
->bnapi
[j
];
2708 bp
->bnapi
[j
]->tx_ring
= &bp
->tx_ring
[i
];
2711 rc
= bnxt_alloc_stats(bp
);
2715 rc
= bnxt_alloc_ntp_fltrs(bp
);
2719 rc
= bnxt_alloc_vnics(bp
);
2724 bnxt_init_ring_struct(bp
);
2726 rc
= bnxt_alloc_rx_rings(bp
);
2730 rc
= bnxt_alloc_tx_rings(bp
);
2734 rc
= bnxt_alloc_cp_rings(bp
);
2738 bp
->vnic_info
[0].flags
|= BNXT_VNIC_RSS_FLAG
| BNXT_VNIC_MCAST_FLAG
|
2739 BNXT_VNIC_UCAST_FLAG
;
2740 rc
= bnxt_alloc_vnic_attributes(bp
);
2746 bnxt_free_mem(bp
, true);
2750 void bnxt_hwrm_cmd_hdr_init(struct bnxt
*bp
, void *request
, u16 req_type
,
2751 u16 cmpl_ring
, u16 target_id
)
2753 struct input
*req
= request
;
2755 req
->req_type
= cpu_to_le16(req_type
);
2756 req
->cmpl_ring
= cpu_to_le16(cmpl_ring
);
2757 req
->target_id
= cpu_to_le16(target_id
);
2758 req
->resp_addr
= cpu_to_le64(bp
->hwrm_cmd_resp_dma_addr
);
2761 static int bnxt_hwrm_do_send_msg(struct bnxt
*bp
, void *msg
, u32 msg_len
,
2762 int timeout
, bool silent
)
2764 int i
, intr_process
, rc
, tmo_count
;
2765 struct input
*req
= msg
;
2767 __le32
*resp_len
, *valid
;
2768 u16 cp_ring_id
, len
= 0;
2769 struct hwrm_err_output
*resp
= bp
->hwrm_cmd_resp_addr
;
2771 req
->seq_id
= cpu_to_le16(bp
->hwrm_cmd_seq
++);
2772 memset(resp
, 0, PAGE_SIZE
);
2773 cp_ring_id
= le16_to_cpu(req
->cmpl_ring
);
2774 intr_process
= (cp_ring_id
== INVALID_HW_RING_ID
) ? 0 : 1;
2776 /* Write request msg to hwrm channel */
2777 __iowrite32_copy(bp
->bar0
, data
, msg_len
/ 4);
2779 for (i
= msg_len
; i
< BNXT_HWRM_MAX_REQ_LEN
; i
+= 4)
2780 writel(0, bp
->bar0
+ i
);
2782 /* currently supports only one outstanding message */
2784 bp
->hwrm_intr_seq_id
= le16_to_cpu(req
->seq_id
);
2786 /* Ring channel doorbell */
2787 writel(1, bp
->bar0
+ 0x100);
2790 timeout
= DFLT_HWRM_CMD_TIMEOUT
;
2793 tmo_count
= timeout
* 40;
2795 /* Wait until hwrm response cmpl interrupt is processed */
2796 while (bp
->hwrm_intr_seq_id
!= HWRM_SEQ_ID_INVALID
&&
2798 usleep_range(25, 40);
2801 if (bp
->hwrm_intr_seq_id
!= HWRM_SEQ_ID_INVALID
) {
2802 netdev_err(bp
->dev
, "Resp cmpl intr err msg: 0x%x\n",
2803 le16_to_cpu(req
->req_type
));
2807 /* Check if response len is updated */
2808 resp_len
= bp
->hwrm_cmd_resp_addr
+ HWRM_RESP_LEN_OFFSET
;
2809 for (i
= 0; i
< tmo_count
; i
++) {
2810 len
= (le32_to_cpu(*resp_len
) & HWRM_RESP_LEN_MASK
) >>
2814 usleep_range(25, 40);
2817 if (i
>= tmo_count
) {
2818 netdev_err(bp
->dev
, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
2819 timeout
, le16_to_cpu(req
->req_type
),
2820 le16_to_cpu(req
->seq_id
), len
);
2824 /* Last word of resp contains valid bit */
2825 valid
= bp
->hwrm_cmd_resp_addr
+ len
- 4;
2826 for (i
= 0; i
< 5; i
++) {
2827 if (le32_to_cpu(*valid
) & HWRM_RESP_VALID_MASK
)
2833 netdev_err(bp
->dev
, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
2834 timeout
, le16_to_cpu(req
->req_type
),
2835 le16_to_cpu(req
->seq_id
), len
, *valid
);
2840 rc
= le16_to_cpu(resp
->error_code
);
2842 netdev_err(bp
->dev
, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
2843 le16_to_cpu(resp
->req_type
),
2844 le16_to_cpu(resp
->seq_id
), rc
);
2848 int _hwrm_send_message(struct bnxt
*bp
, void *msg
, u32 msg_len
, int timeout
)
2850 return bnxt_hwrm_do_send_msg(bp
, msg
, msg_len
, timeout
, false);
2853 int hwrm_send_message(struct bnxt
*bp
, void *msg
, u32 msg_len
, int timeout
)
2857 mutex_lock(&bp
->hwrm_cmd_lock
);
2858 rc
= _hwrm_send_message(bp
, msg
, msg_len
, timeout
);
2859 mutex_unlock(&bp
->hwrm_cmd_lock
);
2863 int hwrm_send_message_silent(struct bnxt
*bp
, void *msg
, u32 msg_len
,
2868 mutex_lock(&bp
->hwrm_cmd_lock
);
2869 rc
= bnxt_hwrm_do_send_msg(bp
, msg
, msg_len
, timeout
, true);
2870 mutex_unlock(&bp
->hwrm_cmd_lock
);
2874 static int bnxt_hwrm_func_drv_rgtr(struct bnxt
*bp
)
2876 struct hwrm_func_drv_rgtr_input req
= {0};
2878 DECLARE_BITMAP(async_events_bmap
, 256);
2879 u32
*events
= (u32
*)async_events_bmap
;
2881 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_DRV_RGTR
, -1, -1);
2884 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE
|
2885 FUNC_DRV_RGTR_REQ_ENABLES_VER
|
2886 FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD
);
2888 memset(async_events_bmap
, 0, sizeof(async_events_bmap
));
2889 for (i
= 0; i
< ARRAY_SIZE(bnxt_async_events_arr
); i
++)
2890 __set_bit(bnxt_async_events_arr
[i
], async_events_bmap
);
2892 for (i
= 0; i
< 8; i
++)
2893 req
.async_event_fwd
[i
] |= cpu_to_le32(events
[i
]);
2895 req
.os_type
= cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX
);
2896 req
.ver_maj
= DRV_VER_MAJ
;
2897 req
.ver_min
= DRV_VER_MIN
;
2898 req
.ver_upd
= DRV_VER_UPD
;
2901 DECLARE_BITMAP(vf_req_snif_bmap
, 256);
2902 u32
*data
= (u32
*)vf_req_snif_bmap
;
2904 memset(vf_req_snif_bmap
, 0, sizeof(vf_req_snif_bmap
));
2905 for (i
= 0; i
< ARRAY_SIZE(bnxt_vf_req_snif
); i
++)
2906 __set_bit(bnxt_vf_req_snif
[i
], vf_req_snif_bmap
);
2908 for (i
= 0; i
< 8; i
++)
2909 req
.vf_req_fwd
[i
] = cpu_to_le32(data
[i
]);
2912 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD
);
2915 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2918 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt
*bp
)
2920 struct hwrm_func_drv_unrgtr_input req
= {0};
2922 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_DRV_UNRGTR
, -1, -1);
2923 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2926 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt
*bp
, u8 tunnel_type
)
2929 struct hwrm_tunnel_dst_port_free_input req
= {0};
2931 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_TUNNEL_DST_PORT_FREE
, -1, -1);
2932 req
.tunnel_type
= tunnel_type
;
2934 switch (tunnel_type
) {
2935 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
:
2936 req
.tunnel_dst_port_id
= bp
->vxlan_fw_dst_port_id
;
2938 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
:
2939 req
.tunnel_dst_port_id
= bp
->nge_fw_dst_port_id
;
2945 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2947 netdev_err(bp
->dev
, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
2952 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt
*bp
, __be16 port
,
2956 struct hwrm_tunnel_dst_port_alloc_input req
= {0};
2957 struct hwrm_tunnel_dst_port_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
2959 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_TUNNEL_DST_PORT_ALLOC
, -1, -1);
2961 req
.tunnel_type
= tunnel_type
;
2962 req
.tunnel_dst_port_val
= port
;
2964 mutex_lock(&bp
->hwrm_cmd_lock
);
2965 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2967 netdev_err(bp
->dev
, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
2972 if (tunnel_type
& TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN
)
2973 bp
->vxlan_fw_dst_port_id
= resp
->tunnel_dst_port_id
;
2975 else if (tunnel_type
& TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE
)
2976 bp
->nge_fw_dst_port_id
= resp
->tunnel_dst_port_id
;
2978 mutex_unlock(&bp
->hwrm_cmd_lock
);
2982 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt
*bp
, u16 vnic_id
)
2984 struct hwrm_cfa_l2_set_rx_mask_input req
= {0};
2985 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
2987 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_L2_SET_RX_MASK
, -1, -1);
2988 req
.vnic_id
= cpu_to_le32(vnic
->fw_vnic_id
);
2990 req
.num_mc_entries
= cpu_to_le32(vnic
->mc_list_count
);
2991 req
.mc_tbl_addr
= cpu_to_le64(vnic
->mc_list_mapping
);
2992 req
.mask
= cpu_to_le32(vnic
->rx_mask
);
2993 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2996 #ifdef CONFIG_RFS_ACCEL
2997 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt
*bp
,
2998 struct bnxt_ntuple_filter
*fltr
)
3000 struct hwrm_cfa_ntuple_filter_free_input req
= {0};
3002 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_NTUPLE_FILTER_FREE
, -1, -1);
3003 req
.ntuple_filter_id
= fltr
->filter_id
;
3004 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3007 #define BNXT_NTP_FLTR_FLAGS \
3008 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
3009 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
3010 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
3011 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
3012 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
3013 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
3014 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
3015 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
3016 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
3017 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
3018 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
3019 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
3020 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
3021 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
3023 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt
*bp
,
3024 struct bnxt_ntuple_filter
*fltr
)
3027 struct hwrm_cfa_ntuple_filter_alloc_input req
= {0};
3028 struct hwrm_cfa_ntuple_filter_alloc_output
*resp
=
3029 bp
->hwrm_cmd_resp_addr
;
3030 struct flow_keys
*keys
= &fltr
->fkeys
;
3031 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[fltr
->rxq
+ 1];
3033 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_NTUPLE_FILTER_ALLOC
, -1, -1);
3034 req
.l2_filter_id
= bp
->vnic_info
[0].fw_l2_filter_id
[0];
3036 req
.enables
= cpu_to_le32(BNXT_NTP_FLTR_FLAGS
);
3038 req
.ethertype
= htons(ETH_P_IP
);
3039 memcpy(req
.src_macaddr
, fltr
->src_mac_addr
, ETH_ALEN
);
3040 req
.ip_addr_type
= CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4
;
3041 req
.ip_protocol
= keys
->basic
.ip_proto
;
3043 req
.src_ipaddr
[0] = keys
->addrs
.v4addrs
.src
;
3044 req
.src_ipaddr_mask
[0] = cpu_to_be32(0xffffffff);
3045 req
.dst_ipaddr
[0] = keys
->addrs
.v4addrs
.dst
;
3046 req
.dst_ipaddr_mask
[0] = cpu_to_be32(0xffffffff);
3048 req
.src_port
= keys
->ports
.src
;
3049 req
.src_port_mask
= cpu_to_be16(0xffff);
3050 req
.dst_port
= keys
->ports
.dst
;
3051 req
.dst_port_mask
= cpu_to_be16(0xffff);
3053 req
.dst_id
= cpu_to_le16(vnic
->fw_vnic_id
);
3054 mutex_lock(&bp
->hwrm_cmd_lock
);
3055 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3057 fltr
->filter_id
= resp
->ntuple_filter_id
;
3058 mutex_unlock(&bp
->hwrm_cmd_lock
);
3063 static int bnxt_hwrm_set_vnic_filter(struct bnxt
*bp
, u16 vnic_id
, u16 idx
,
3067 struct hwrm_cfa_l2_filter_alloc_input req
= {0};
3068 struct hwrm_cfa_l2_filter_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3070 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_L2_FILTER_ALLOC
, -1, -1);
3071 req
.flags
= cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX
|
3072 CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST
);
3073 req
.dst_id
= cpu_to_le16(bp
->vnic_info
[vnic_id
].fw_vnic_id
);
3075 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR
|
3076 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID
|
3077 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK
);
3078 memcpy(req
.l2_addr
, mac_addr
, ETH_ALEN
);
3079 req
.l2_addr_mask
[0] = 0xff;
3080 req
.l2_addr_mask
[1] = 0xff;
3081 req
.l2_addr_mask
[2] = 0xff;
3082 req
.l2_addr_mask
[3] = 0xff;
3083 req
.l2_addr_mask
[4] = 0xff;
3084 req
.l2_addr_mask
[5] = 0xff;
3086 mutex_lock(&bp
->hwrm_cmd_lock
);
3087 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3089 bp
->vnic_info
[vnic_id
].fw_l2_filter_id
[idx
] =
3091 mutex_unlock(&bp
->hwrm_cmd_lock
);
3095 static int bnxt_hwrm_clear_vnic_filter(struct bnxt
*bp
)
3097 u16 i
, j
, num_of_vnics
= 1; /* only vnic 0 supported */
3100 /* Any associated ntuple filters will also be cleared by firmware. */
3101 mutex_lock(&bp
->hwrm_cmd_lock
);
3102 for (i
= 0; i
< num_of_vnics
; i
++) {
3103 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[i
];
3105 for (j
= 0; j
< vnic
->uc_filter_count
; j
++) {
3106 struct hwrm_cfa_l2_filter_free_input req
= {0};
3108 bnxt_hwrm_cmd_hdr_init(bp
, &req
,
3109 HWRM_CFA_L2_FILTER_FREE
, -1, -1);
3111 req
.l2_filter_id
= vnic
->fw_l2_filter_id
[j
];
3113 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3116 vnic
->uc_filter_count
= 0;
3118 mutex_unlock(&bp
->hwrm_cmd_lock
);
3123 static int bnxt_hwrm_vnic_set_tpa(struct bnxt
*bp
, u16 vnic_id
, u32 tpa_flags
)
3125 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
3126 struct hwrm_vnic_tpa_cfg_input req
= {0};
3128 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_TPA_CFG
, -1, -1);
3131 u16 mss
= bp
->dev
->mtu
- 40;
3132 u32 nsegs
, n
, segs
= 0, flags
;
3134 flags
= VNIC_TPA_CFG_REQ_FLAGS_TPA
|
3135 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA
|
3136 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE
|
3137 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN
|
3138 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ
;
3139 if (tpa_flags
& BNXT_FLAG_GRO
)
3140 flags
|= VNIC_TPA_CFG_REQ_FLAGS_GRO
;
3142 req
.flags
= cpu_to_le32(flags
);
3145 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS
|
3146 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS
|
3147 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN
);
3149 /* Number of segs are log2 units, and first packet is not
3150 * included as part of this units.
3152 if (mss
<= BNXT_RX_PAGE_SIZE
) {
3153 n
= BNXT_RX_PAGE_SIZE
/ mss
;
3154 nsegs
= (MAX_SKB_FRAGS
- 1) * n
;
3156 n
= mss
/ BNXT_RX_PAGE_SIZE
;
3157 if (mss
& (BNXT_RX_PAGE_SIZE
- 1))
3159 nsegs
= (MAX_SKB_FRAGS
- n
) / n
;
3162 segs
= ilog2(nsegs
);
3163 req
.max_agg_segs
= cpu_to_le16(segs
);
3164 req
.max_aggs
= cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX
);
3166 req
.min_agg_len
= cpu_to_le32(512);
3168 req
.vnic_id
= cpu_to_le16(vnic
->fw_vnic_id
);
3170 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3173 static int bnxt_hwrm_vnic_set_rss(struct bnxt
*bp
, u16 vnic_id
, bool set_rss
)
3175 u32 i
, j
, max_rings
;
3176 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
3177 struct hwrm_vnic_rss_cfg_input req
= {0};
3179 if (vnic
->fw_rss_cos_lb_ctx
== INVALID_HW_RING_ID
)
3182 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_RSS_CFG
, -1, -1);
3184 vnic
->hash_type
= BNXT_RSS_HASH_TYPE_FLAG_IPV4
|
3185 BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV4
|
3186 BNXT_RSS_HASH_TYPE_FLAG_IPV6
|
3187 BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV6
;
3189 req
.hash_type
= cpu_to_le32(vnic
->hash_type
);
3191 if (vnic
->flags
& BNXT_VNIC_RSS_FLAG
)
3192 max_rings
= bp
->rx_nr_rings
;
3196 /* Fill the RSS indirection table with ring group ids */
3197 for (i
= 0, j
= 0; i
< HW_HASH_INDEX_SIZE
; i
++, j
++) {
3200 vnic
->rss_table
[i
] = cpu_to_le16(vnic
->fw_grp_ids
[j
]);
3203 req
.ring_grp_tbl_addr
= cpu_to_le64(vnic
->rss_table_dma_addr
);
3204 req
.hash_key_tbl_addr
=
3205 cpu_to_le64(vnic
->rss_hash_key_dma_addr
);
3207 req
.rss_ctx_idx
= cpu_to_le16(vnic
->fw_rss_cos_lb_ctx
);
3208 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3211 static int bnxt_hwrm_vnic_set_hds(struct bnxt
*bp
, u16 vnic_id
)
3213 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
3214 struct hwrm_vnic_plcmodes_cfg_input req
= {0};
3216 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_PLCMODES_CFG
, -1, -1);
3217 req
.flags
= cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT
|
3218 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4
|
3219 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6
);
3221 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID
|
3222 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID
);
3223 /* thresholds not implemented in firmware yet */
3224 req
.jumbo_thresh
= cpu_to_le16(bp
->rx_copy_thresh
);
3225 req
.hds_threshold
= cpu_to_le16(bp
->rx_copy_thresh
);
3226 req
.vnic_id
= cpu_to_le32(vnic
->fw_vnic_id
);
3227 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3230 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt
*bp
, u16 vnic_id
)
3232 struct hwrm_vnic_rss_cos_lb_ctx_free_input req
= {0};
3234 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_RSS_COS_LB_CTX_FREE
, -1, -1);
3235 req
.rss_cos_lb_ctx_id
=
3236 cpu_to_le16(bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
);
3238 hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3239 bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
= INVALID_HW_RING_ID
;
3242 static void bnxt_hwrm_vnic_ctx_free(struct bnxt
*bp
)
3246 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
3247 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[i
];
3249 if (vnic
->fw_rss_cos_lb_ctx
!= INVALID_HW_RING_ID
)
3250 bnxt_hwrm_vnic_ctx_free_one(bp
, i
);
3252 bp
->rsscos_nr_ctxs
= 0;
3255 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt
*bp
, u16 vnic_id
)
3258 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req
= {0};
3259 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output
*resp
=
3260 bp
->hwrm_cmd_resp_addr
;
3262 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC
, -1,
3265 mutex_lock(&bp
->hwrm_cmd_lock
);
3266 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3268 bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
=
3269 le16_to_cpu(resp
->rss_cos_lb_ctx_id
);
3270 mutex_unlock(&bp
->hwrm_cmd_lock
);
3275 static int bnxt_hwrm_vnic_cfg(struct bnxt
*bp
, u16 vnic_id
)
3277 unsigned int ring
= 0, grp_idx
;
3278 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
3279 struct hwrm_vnic_cfg_input req
= {0};
3281 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_CFG
, -1, -1);
3282 /* Only RSS support for now TBD: COS & LB */
3283 req
.enables
= cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP
|
3284 VNIC_CFG_REQ_ENABLES_RSS_RULE
);
3285 req
.rss_rule
= cpu_to_le16(vnic
->fw_rss_cos_lb_ctx
);
3286 req
.cos_rule
= cpu_to_le16(0xffff);
3287 if (vnic
->flags
& BNXT_VNIC_RSS_FLAG
)
3289 else if (vnic
->flags
& BNXT_VNIC_RFS_FLAG
)
3292 grp_idx
= bp
->rx_ring
[ring
].bnapi
->index
;
3293 req
.vnic_id
= cpu_to_le16(vnic
->fw_vnic_id
);
3294 req
.dflt_ring_grp
= cpu_to_le16(bp
->grp_info
[grp_idx
].fw_grp_id
);
3296 req
.lb_rule
= cpu_to_le16(0xffff);
3297 req
.mru
= cpu_to_le16(bp
->dev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+
3300 if (bp
->flags
& BNXT_FLAG_STRIP_VLAN
)
3301 req
.flags
|= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE
);
3303 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3306 static int bnxt_hwrm_vnic_free_one(struct bnxt
*bp
, u16 vnic_id
)
3310 if (bp
->vnic_info
[vnic_id
].fw_vnic_id
!= INVALID_HW_RING_ID
) {
3311 struct hwrm_vnic_free_input req
= {0};
3313 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_FREE
, -1, -1);
3315 cpu_to_le32(bp
->vnic_info
[vnic_id
].fw_vnic_id
);
3317 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3320 bp
->vnic_info
[vnic_id
].fw_vnic_id
= INVALID_HW_RING_ID
;
3325 static void bnxt_hwrm_vnic_free(struct bnxt
*bp
)
3329 for (i
= 0; i
< bp
->nr_vnics
; i
++)
3330 bnxt_hwrm_vnic_free_one(bp
, i
);
3333 static int bnxt_hwrm_vnic_alloc(struct bnxt
*bp
, u16 vnic_id
,
3334 unsigned int start_rx_ring_idx
,
3335 unsigned int nr_rings
)
3338 unsigned int i
, j
, grp_idx
, end_idx
= start_rx_ring_idx
+ nr_rings
;
3339 struct hwrm_vnic_alloc_input req
= {0};
3340 struct hwrm_vnic_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3342 /* map ring groups to this vnic */
3343 for (i
= start_rx_ring_idx
, j
= 0; i
< end_idx
; i
++, j
++) {
3344 grp_idx
= bp
->rx_ring
[i
].bnapi
->index
;
3345 if (bp
->grp_info
[grp_idx
].fw_grp_id
== INVALID_HW_RING_ID
) {
3346 netdev_err(bp
->dev
, "Not enough ring groups avail:%x req:%x\n",
3350 bp
->vnic_info
[vnic_id
].fw_grp_ids
[j
] =
3351 bp
->grp_info
[grp_idx
].fw_grp_id
;
3354 bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
= INVALID_HW_RING_ID
;
3356 req
.flags
= cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT
);
3358 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_ALLOC
, -1, -1);
3360 mutex_lock(&bp
->hwrm_cmd_lock
);
3361 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3363 bp
->vnic_info
[vnic_id
].fw_vnic_id
= le32_to_cpu(resp
->vnic_id
);
3364 mutex_unlock(&bp
->hwrm_cmd_lock
);
3368 static int bnxt_hwrm_ring_grp_alloc(struct bnxt
*bp
)
3373 mutex_lock(&bp
->hwrm_cmd_lock
);
3374 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3375 struct hwrm_ring_grp_alloc_input req
= {0};
3376 struct hwrm_ring_grp_alloc_output
*resp
=
3377 bp
->hwrm_cmd_resp_addr
;
3378 unsigned int grp_idx
= bp
->rx_ring
[i
].bnapi
->index
;
3380 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_GRP_ALLOC
, -1, -1);
3382 req
.cr
= cpu_to_le16(bp
->grp_info
[grp_idx
].cp_fw_ring_id
);
3383 req
.rr
= cpu_to_le16(bp
->grp_info
[grp_idx
].rx_fw_ring_id
);
3384 req
.ar
= cpu_to_le16(bp
->grp_info
[grp_idx
].agg_fw_ring_id
);
3385 req
.sc
= cpu_to_le16(bp
->grp_info
[grp_idx
].fw_stats_ctx
);
3387 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3392 bp
->grp_info
[grp_idx
].fw_grp_id
=
3393 le32_to_cpu(resp
->ring_group_id
);
3395 mutex_unlock(&bp
->hwrm_cmd_lock
);
3399 static int bnxt_hwrm_ring_grp_free(struct bnxt
*bp
)
3403 struct hwrm_ring_grp_free_input req
= {0};
3408 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_GRP_FREE
, -1, -1);
3410 mutex_lock(&bp
->hwrm_cmd_lock
);
3411 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3412 if (bp
->grp_info
[i
].fw_grp_id
== INVALID_HW_RING_ID
)
3415 cpu_to_le32(bp
->grp_info
[i
].fw_grp_id
);
3417 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3421 bp
->grp_info
[i
].fw_grp_id
= INVALID_HW_RING_ID
;
3423 mutex_unlock(&bp
->hwrm_cmd_lock
);
3427 static int hwrm_ring_alloc_send_msg(struct bnxt
*bp
,
3428 struct bnxt_ring_struct
*ring
,
3429 u32 ring_type
, u32 map_index
,
3432 int rc
= 0, err
= 0;
3433 struct hwrm_ring_alloc_input req
= {0};
3434 struct hwrm_ring_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3437 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_ALLOC
, -1, -1);
3440 if (ring
->nr_pages
> 1) {
3441 req
.page_tbl_addr
= cpu_to_le64(ring
->pg_tbl_map
);
3442 /* Page size is in log2 units */
3443 req
.page_size
= BNXT_PAGE_SHIFT
;
3444 req
.page_tbl_depth
= 1;
3446 req
.page_tbl_addr
= cpu_to_le64(ring
->dma_arr
[0]);
3449 /* Association of ring index with doorbell index and MSIX number */
3450 req
.logical_id
= cpu_to_le16(map_index
);
3452 switch (ring_type
) {
3453 case HWRM_RING_ALLOC_TX
:
3454 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_TX
;
3455 /* Association of transmit ring with completion ring */
3457 cpu_to_le16(bp
->grp_info
[map_index
].cp_fw_ring_id
);
3458 req
.length
= cpu_to_le32(bp
->tx_ring_mask
+ 1);
3459 req
.stat_ctx_id
= cpu_to_le32(stats_ctx_id
);
3460 req
.queue_id
= cpu_to_le16(ring
->queue_id
);
3462 case HWRM_RING_ALLOC_RX
:
3463 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_RX
;
3464 req
.length
= cpu_to_le32(bp
->rx_ring_mask
+ 1);
3466 case HWRM_RING_ALLOC_AGG
:
3467 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_RX
;
3468 req
.length
= cpu_to_le32(bp
->rx_agg_ring_mask
+ 1);
3470 case HWRM_RING_ALLOC_CMPL
:
3471 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_CMPL
;
3472 req
.length
= cpu_to_le32(bp
->cp_ring_mask
+ 1);
3473 if (bp
->flags
& BNXT_FLAG_USING_MSIX
)
3474 req
.int_mode
= RING_ALLOC_REQ_INT_MODE_MSIX
;
3477 netdev_err(bp
->dev
, "hwrm alloc invalid ring type %d\n",
3482 mutex_lock(&bp
->hwrm_cmd_lock
);
3483 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3484 err
= le16_to_cpu(resp
->error_code
);
3485 ring_id
= le16_to_cpu(resp
->ring_id
);
3486 mutex_unlock(&bp
->hwrm_cmd_lock
);
3489 switch (ring_type
) {
3490 case RING_FREE_REQ_RING_TYPE_CMPL
:
3491 netdev_err(bp
->dev
, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
3495 case RING_FREE_REQ_RING_TYPE_RX
:
3496 netdev_err(bp
->dev
, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
3500 case RING_FREE_REQ_RING_TYPE_TX
:
3501 netdev_err(bp
->dev
, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
3506 netdev_err(bp
->dev
, "Invalid ring\n");
3510 ring
->fw_ring_id
= ring_id
;
3514 static int bnxt_hwrm_ring_alloc(struct bnxt
*bp
)
3518 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3519 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3520 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3521 struct bnxt_ring_struct
*ring
= &cpr
->cp_ring_struct
;
3523 cpr
->cp_doorbell
= bp
->bar1
+ i
* 0x80;
3524 rc
= hwrm_ring_alloc_send_msg(bp
, ring
, HWRM_RING_ALLOC_CMPL
, i
,
3525 INVALID_STATS_CTX_ID
);
3528 BNXT_CP_DB(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
3529 bp
->grp_info
[i
].cp_fw_ring_id
= ring
->fw_ring_id
;
3532 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
3533 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
3534 struct bnxt_ring_struct
*ring
= &txr
->tx_ring_struct
;
3535 u32 map_idx
= txr
->bnapi
->index
;
3536 u16 fw_stats_ctx
= bp
->grp_info
[map_idx
].fw_stats_ctx
;
3538 rc
= hwrm_ring_alloc_send_msg(bp
, ring
, HWRM_RING_ALLOC_TX
,
3539 map_idx
, fw_stats_ctx
);
3542 txr
->tx_doorbell
= bp
->bar1
+ map_idx
* 0x80;
3545 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3546 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
3547 struct bnxt_ring_struct
*ring
= &rxr
->rx_ring_struct
;
3548 u32 map_idx
= rxr
->bnapi
->index
;
3550 rc
= hwrm_ring_alloc_send_msg(bp
, ring
, HWRM_RING_ALLOC_RX
,
3551 map_idx
, INVALID_STATS_CTX_ID
);
3554 rxr
->rx_doorbell
= bp
->bar1
+ map_idx
* 0x80;
3555 writel(DB_KEY_RX
| rxr
->rx_prod
, rxr
->rx_doorbell
);
3556 bp
->grp_info
[map_idx
].rx_fw_ring_id
= ring
->fw_ring_id
;
3559 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
) {
3560 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3561 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
3562 struct bnxt_ring_struct
*ring
=
3563 &rxr
->rx_agg_ring_struct
;
3564 u32 grp_idx
= rxr
->bnapi
->index
;
3565 u32 map_idx
= grp_idx
+ bp
->rx_nr_rings
;
3567 rc
= hwrm_ring_alloc_send_msg(bp
, ring
,
3568 HWRM_RING_ALLOC_AGG
,
3570 INVALID_STATS_CTX_ID
);
3574 rxr
->rx_agg_doorbell
= bp
->bar1
+ map_idx
* 0x80;
3575 writel(DB_KEY_RX
| rxr
->rx_agg_prod
,
3576 rxr
->rx_agg_doorbell
);
3577 bp
->grp_info
[grp_idx
].agg_fw_ring_id
= ring
->fw_ring_id
;
3584 static int hwrm_ring_free_send_msg(struct bnxt
*bp
,
3585 struct bnxt_ring_struct
*ring
,
3586 u32 ring_type
, int cmpl_ring_id
)
3589 struct hwrm_ring_free_input req
= {0};
3590 struct hwrm_ring_free_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3593 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_FREE
, cmpl_ring_id
, -1);
3594 req
.ring_type
= ring_type
;
3595 req
.ring_id
= cpu_to_le16(ring
->fw_ring_id
);
3597 mutex_lock(&bp
->hwrm_cmd_lock
);
3598 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3599 error_code
= le16_to_cpu(resp
->error_code
);
3600 mutex_unlock(&bp
->hwrm_cmd_lock
);
3602 if (rc
|| error_code
) {
3603 switch (ring_type
) {
3604 case RING_FREE_REQ_RING_TYPE_CMPL
:
3605 netdev_err(bp
->dev
, "hwrm_ring_free cp failed. rc:%d\n",
3608 case RING_FREE_REQ_RING_TYPE_RX
:
3609 netdev_err(bp
->dev
, "hwrm_ring_free rx failed. rc:%d\n",
3612 case RING_FREE_REQ_RING_TYPE_TX
:
3613 netdev_err(bp
->dev
, "hwrm_ring_free tx failed. rc:%d\n",
3617 netdev_err(bp
->dev
, "Invalid ring\n");
3624 static void bnxt_hwrm_ring_free(struct bnxt
*bp
, bool close_path
)
3631 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
3632 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
3633 struct bnxt_ring_struct
*ring
= &txr
->tx_ring_struct
;
3634 u32 grp_idx
= txr
->bnapi
->index
;
3635 u32 cmpl_ring_id
= bp
->grp_info
[grp_idx
].cp_fw_ring_id
;
3637 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
3638 hwrm_ring_free_send_msg(bp
, ring
,
3639 RING_FREE_REQ_RING_TYPE_TX
,
3640 close_path
? cmpl_ring_id
:
3641 INVALID_HW_RING_ID
);
3642 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
3646 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3647 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
3648 struct bnxt_ring_struct
*ring
= &rxr
->rx_ring_struct
;
3649 u32 grp_idx
= rxr
->bnapi
->index
;
3650 u32 cmpl_ring_id
= bp
->grp_info
[grp_idx
].cp_fw_ring_id
;
3652 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
3653 hwrm_ring_free_send_msg(bp
, ring
,
3654 RING_FREE_REQ_RING_TYPE_RX
,
3655 close_path
? cmpl_ring_id
:
3656 INVALID_HW_RING_ID
);
3657 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
3658 bp
->grp_info
[grp_idx
].rx_fw_ring_id
=
3663 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3664 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
3665 struct bnxt_ring_struct
*ring
= &rxr
->rx_agg_ring_struct
;
3666 u32 grp_idx
= rxr
->bnapi
->index
;
3667 u32 cmpl_ring_id
= bp
->grp_info
[grp_idx
].cp_fw_ring_id
;
3669 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
3670 hwrm_ring_free_send_msg(bp
, ring
,
3671 RING_FREE_REQ_RING_TYPE_RX
,
3672 close_path
? cmpl_ring_id
:
3673 INVALID_HW_RING_ID
);
3674 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
3675 bp
->grp_info
[grp_idx
].agg_fw_ring_id
=
3680 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3681 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3682 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3683 struct bnxt_ring_struct
*ring
= &cpr
->cp_ring_struct
;
3685 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
3686 hwrm_ring_free_send_msg(bp
, ring
,
3687 RING_FREE_REQ_RING_TYPE_CMPL
,
3688 INVALID_HW_RING_ID
);
3689 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
3690 bp
->grp_info
[i
].cp_fw_ring_id
= INVALID_HW_RING_ID
;
3695 static void bnxt_hwrm_set_coal_params(struct bnxt
*bp
, u32 max_bufs
,
3696 u32 buf_tmrs
, u16 flags
,
3697 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input
*req
)
3699 req
->flags
= cpu_to_le16(flags
);
3700 req
->num_cmpl_dma_aggr
= cpu_to_le16((u16
)max_bufs
);
3701 req
->num_cmpl_dma_aggr_during_int
= cpu_to_le16(max_bufs
>> 16);
3702 req
->cmpl_aggr_dma_tmr
= cpu_to_le16((u16
)buf_tmrs
);
3703 req
->cmpl_aggr_dma_tmr_during_int
= cpu_to_le16(buf_tmrs
>> 16);
3704 /* Minimum time between 2 interrupts set to buf_tmr x 2 */
3705 req
->int_lat_tmr_min
= cpu_to_le16((u16
)buf_tmrs
* 2);
3706 req
->int_lat_tmr_max
= cpu_to_le16((u16
)buf_tmrs
* 4);
3707 req
->num_cmpl_aggr_int
= cpu_to_le16((u16
)max_bufs
* 4);
3710 int bnxt_hwrm_set_coal(struct bnxt
*bp
)
3713 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx
= {0},
3715 u16 max_buf
, max_buf_irq
;
3716 u16 buf_tmr
, buf_tmr_irq
;
3719 bnxt_hwrm_cmd_hdr_init(bp
, &req_rx
,
3720 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS
, -1, -1);
3721 bnxt_hwrm_cmd_hdr_init(bp
, &req_tx
,
3722 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS
, -1, -1);
3724 /* Each rx completion (2 records) should be DMAed immediately.
3725 * DMA 1/4 of the completion buffers at a time.
3727 max_buf
= min_t(u16
, bp
->rx_coal_bufs
/ 4, 2);
3728 /* max_buf must not be zero */
3729 max_buf
= clamp_t(u16
, max_buf
, 1, 63);
3730 max_buf_irq
= clamp_t(u16
, bp
->rx_coal_bufs_irq
, 1, 63);
3731 buf_tmr
= BNXT_USEC_TO_COAL_TIMER(bp
->rx_coal_ticks
);
3732 /* buf timer set to 1/4 of interrupt timer */
3733 buf_tmr
= max_t(u16
, buf_tmr
/ 4, 1);
3734 buf_tmr_irq
= BNXT_USEC_TO_COAL_TIMER(bp
->rx_coal_ticks_irq
);
3735 buf_tmr_irq
= max_t(u16
, buf_tmr_irq
, 1);
3737 flags
= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET
;
3739 /* RING_IDLE generates more IRQs for lower latency. Enable it only
3740 * if coal_ticks is less than 25 us.
3742 if (bp
->rx_coal_ticks
< 25)
3743 flags
|= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE
;
3745 bnxt_hwrm_set_coal_params(bp
, max_buf_irq
<< 16 | max_buf
,
3746 buf_tmr_irq
<< 16 | buf_tmr
, flags
, &req_rx
);
3748 /* max_buf must not be zero */
3749 max_buf
= clamp_t(u16
, bp
->tx_coal_bufs
, 1, 63);
3750 max_buf_irq
= clamp_t(u16
, bp
->tx_coal_bufs_irq
, 1, 63);
3751 buf_tmr
= BNXT_USEC_TO_COAL_TIMER(bp
->tx_coal_ticks
);
3752 /* buf timer set to 1/4 of interrupt timer */
3753 buf_tmr
= max_t(u16
, buf_tmr
/ 4, 1);
3754 buf_tmr_irq
= BNXT_USEC_TO_COAL_TIMER(bp
->tx_coal_ticks_irq
);
3755 buf_tmr_irq
= max_t(u16
, buf_tmr_irq
, 1);
3757 flags
= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET
;
3758 bnxt_hwrm_set_coal_params(bp
, max_buf_irq
<< 16 | max_buf
,
3759 buf_tmr_irq
<< 16 | buf_tmr
, flags
, &req_tx
);
3761 mutex_lock(&bp
->hwrm_cmd_lock
);
3762 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3763 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3766 if (!bnapi
->rx_ring
)
3768 req
->ring_id
= cpu_to_le16(bp
->grp_info
[i
].cp_fw_ring_id
);
3770 rc
= _hwrm_send_message(bp
, req
, sizeof(*req
),
3775 mutex_unlock(&bp
->hwrm_cmd_lock
);
3779 static int bnxt_hwrm_stat_ctx_free(struct bnxt
*bp
)
3782 struct hwrm_stat_ctx_free_input req
= {0};
3787 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_STAT_CTX_FREE
, -1, -1);
3789 mutex_lock(&bp
->hwrm_cmd_lock
);
3790 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3791 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3792 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3794 if (cpr
->hw_stats_ctx_id
!= INVALID_STATS_CTX_ID
) {
3795 req
.stat_ctx_id
= cpu_to_le32(cpr
->hw_stats_ctx_id
);
3797 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3802 cpr
->hw_stats_ctx_id
= INVALID_STATS_CTX_ID
;
3805 mutex_unlock(&bp
->hwrm_cmd_lock
);
3809 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt
*bp
)
3812 struct hwrm_stat_ctx_alloc_input req
= {0};
3813 struct hwrm_stat_ctx_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3815 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_STAT_CTX_ALLOC
, -1, -1);
3817 req
.update_period_ms
= cpu_to_le32(1000);
3819 mutex_lock(&bp
->hwrm_cmd_lock
);
3820 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3821 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3822 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3824 req
.stats_dma_addr
= cpu_to_le64(cpr
->hw_stats_map
);
3826 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3831 cpr
->hw_stats_ctx_id
= le32_to_cpu(resp
->stat_ctx_id
);
3833 bp
->grp_info
[i
].fw_stats_ctx
= cpr
->hw_stats_ctx_id
;
3835 mutex_unlock(&bp
->hwrm_cmd_lock
);
3839 int bnxt_hwrm_func_qcaps(struct bnxt
*bp
)
3842 struct hwrm_func_qcaps_input req
= {0};
3843 struct hwrm_func_qcaps_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3845 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_QCAPS
, -1, -1);
3846 req
.fid
= cpu_to_le16(0xffff);
3848 mutex_lock(&bp
->hwrm_cmd_lock
);
3849 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3851 goto hwrm_func_qcaps_exit
;
3854 struct bnxt_pf_info
*pf
= &bp
->pf
;
3856 pf
->fw_fid
= le16_to_cpu(resp
->fid
);
3857 pf
->port_id
= le16_to_cpu(resp
->port_id
);
3858 memcpy(pf
->mac_addr
, resp
->mac_address
, ETH_ALEN
);
3859 memcpy(bp
->dev
->dev_addr
, pf
->mac_addr
, ETH_ALEN
);
3860 pf
->max_rsscos_ctxs
= le16_to_cpu(resp
->max_rsscos_ctx
);
3861 pf
->max_cp_rings
= le16_to_cpu(resp
->max_cmpl_rings
);
3862 pf
->max_tx_rings
= le16_to_cpu(resp
->max_tx_rings
);
3863 pf
->max_rx_rings
= le16_to_cpu(resp
->max_rx_rings
);
3864 pf
->max_hw_ring_grps
= le32_to_cpu(resp
->max_hw_ring_grps
);
3865 if (!pf
->max_hw_ring_grps
)
3866 pf
->max_hw_ring_grps
= pf
->max_tx_rings
;
3867 pf
->max_l2_ctxs
= le16_to_cpu(resp
->max_l2_ctxs
);
3868 pf
->max_vnics
= le16_to_cpu(resp
->max_vnics
);
3869 pf
->max_stat_ctxs
= le16_to_cpu(resp
->max_stat_ctx
);
3870 pf
->first_vf_id
= le16_to_cpu(resp
->first_vf_id
);
3871 pf
->max_vfs
= le16_to_cpu(resp
->max_vfs
);
3872 pf
->max_encap_records
= le32_to_cpu(resp
->max_encap_records
);
3873 pf
->max_decap_records
= le32_to_cpu(resp
->max_decap_records
);
3874 pf
->max_tx_em_flows
= le32_to_cpu(resp
->max_tx_em_flows
);
3875 pf
->max_tx_wm_flows
= le32_to_cpu(resp
->max_tx_wm_flows
);
3876 pf
->max_rx_em_flows
= le32_to_cpu(resp
->max_rx_em_flows
);
3877 pf
->max_rx_wm_flows
= le32_to_cpu(resp
->max_rx_wm_flows
);
3879 #ifdef CONFIG_BNXT_SRIOV
3880 struct bnxt_vf_info
*vf
= &bp
->vf
;
3882 vf
->fw_fid
= le16_to_cpu(resp
->fid
);
3883 memcpy(vf
->mac_addr
, resp
->mac_address
, ETH_ALEN
);
3884 if (is_valid_ether_addr(vf
->mac_addr
))
3885 /* overwrite netdev dev_adr with admin VF MAC */
3886 memcpy(bp
->dev
->dev_addr
, vf
->mac_addr
, ETH_ALEN
);
3888 random_ether_addr(bp
->dev
->dev_addr
);
3890 vf
->max_rsscos_ctxs
= le16_to_cpu(resp
->max_rsscos_ctx
);
3891 vf
->max_cp_rings
= le16_to_cpu(resp
->max_cmpl_rings
);
3892 vf
->max_tx_rings
= le16_to_cpu(resp
->max_tx_rings
);
3893 vf
->max_rx_rings
= le16_to_cpu(resp
->max_rx_rings
);
3894 vf
->max_hw_ring_grps
= le32_to_cpu(resp
->max_hw_ring_grps
);
3895 if (!vf
->max_hw_ring_grps
)
3896 vf
->max_hw_ring_grps
= vf
->max_tx_rings
;
3897 vf
->max_l2_ctxs
= le16_to_cpu(resp
->max_l2_ctxs
);
3898 vf
->max_vnics
= le16_to_cpu(resp
->max_vnics
);
3899 vf
->max_stat_ctxs
= le16_to_cpu(resp
->max_stat_ctx
);
3903 bp
->tx_push_thresh
= 0;
3905 cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED
))
3906 bp
->tx_push_thresh
= BNXT_TX_PUSH_THRESH
;
3908 hwrm_func_qcaps_exit
:
3909 mutex_unlock(&bp
->hwrm_cmd_lock
);
3913 static int bnxt_hwrm_func_reset(struct bnxt
*bp
)
3915 struct hwrm_func_reset_input req
= {0};
3917 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_RESET
, -1, -1);
3920 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_RESET_TIMEOUT
);
3923 static int bnxt_hwrm_queue_qportcfg(struct bnxt
*bp
)
3926 struct hwrm_queue_qportcfg_input req
= {0};
3927 struct hwrm_queue_qportcfg_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3930 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_QUEUE_QPORTCFG
, -1, -1);
3932 mutex_lock(&bp
->hwrm_cmd_lock
);
3933 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3937 if (!resp
->max_configurable_queues
) {
3941 bp
->max_tc
= resp
->max_configurable_queues
;
3942 if (bp
->max_tc
> BNXT_MAX_QUEUE
)
3943 bp
->max_tc
= BNXT_MAX_QUEUE
;
3945 qptr
= &resp
->queue_id0
;
3946 for (i
= 0; i
< bp
->max_tc
; i
++) {
3947 bp
->q_info
[i
].queue_id
= *qptr
++;
3948 bp
->q_info
[i
].queue_profile
= *qptr
++;
3952 mutex_unlock(&bp
->hwrm_cmd_lock
);
3956 static int bnxt_hwrm_ver_get(struct bnxt
*bp
)
3959 struct hwrm_ver_get_input req
= {0};
3960 struct hwrm_ver_get_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3962 bp
->hwrm_max_req_len
= HWRM_MAX_REQ_LEN
;
3963 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VER_GET
, -1, -1);
3964 req
.hwrm_intf_maj
= HWRM_VERSION_MAJOR
;
3965 req
.hwrm_intf_min
= HWRM_VERSION_MINOR
;
3966 req
.hwrm_intf_upd
= HWRM_VERSION_UPDATE
;
3967 mutex_lock(&bp
->hwrm_cmd_lock
);
3968 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3970 goto hwrm_ver_get_exit
;
3972 memcpy(&bp
->ver_resp
, resp
, sizeof(struct hwrm_ver_get_output
));
3974 bp
->hwrm_spec_code
= resp
->hwrm_intf_maj
<< 16 |
3975 resp
->hwrm_intf_min
<< 8 | resp
->hwrm_intf_upd
;
3976 if (resp
->hwrm_intf_maj
< 1) {
3977 netdev_warn(bp
->dev
, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
3978 resp
->hwrm_intf_maj
, resp
->hwrm_intf_min
,
3979 resp
->hwrm_intf_upd
);
3980 netdev_warn(bp
->dev
, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
3982 snprintf(bp
->fw_ver_str
, BC_HWRM_STR_LEN
, "%d.%d.%d/%d.%d.%d",
3983 resp
->hwrm_fw_maj
, resp
->hwrm_fw_min
, resp
->hwrm_fw_bld
,
3984 resp
->hwrm_intf_maj
, resp
->hwrm_intf_min
, resp
->hwrm_intf_upd
);
3986 bp
->hwrm_cmd_timeout
= le16_to_cpu(resp
->def_req_timeout
);
3987 if (!bp
->hwrm_cmd_timeout
)
3988 bp
->hwrm_cmd_timeout
= DFLT_HWRM_CMD_TIMEOUT
;
3990 if (resp
->hwrm_intf_maj
>= 1)
3991 bp
->hwrm_max_req_len
= le16_to_cpu(resp
->max_req_win_len
);
3994 mutex_unlock(&bp
->hwrm_cmd_lock
);
3998 static int bnxt_hwrm_port_qstats(struct bnxt
*bp
)
4001 struct bnxt_pf_info
*pf
= &bp
->pf
;
4002 struct hwrm_port_qstats_input req
= {0};
4004 if (!(bp
->flags
& BNXT_FLAG_PORT_STATS
))
4007 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_QSTATS
, -1, -1);
4008 req
.port_id
= cpu_to_le16(pf
->port_id
);
4009 req
.tx_stat_host_addr
= cpu_to_le64(bp
->hw_tx_port_stats_map
);
4010 req
.rx_stat_host_addr
= cpu_to_le64(bp
->hw_rx_port_stats_map
);
4011 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4015 static void bnxt_hwrm_free_tunnel_ports(struct bnxt
*bp
)
4017 if (bp
->vxlan_port_cnt
) {
4018 bnxt_hwrm_tunnel_dst_port_free(
4019 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
);
4021 bp
->vxlan_port_cnt
= 0;
4022 if (bp
->nge_port_cnt
) {
4023 bnxt_hwrm_tunnel_dst_port_free(
4024 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
);
4026 bp
->nge_port_cnt
= 0;
4029 static int bnxt_set_tpa(struct bnxt
*bp
, bool set_tpa
)
4035 tpa_flags
= bp
->flags
& BNXT_FLAG_TPA
;
4036 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
4037 rc
= bnxt_hwrm_vnic_set_tpa(bp
, i
, tpa_flags
);
4039 netdev_err(bp
->dev
, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
4047 static void bnxt_hwrm_clear_vnic_rss(struct bnxt
*bp
)
4051 for (i
= 0; i
< bp
->nr_vnics
; i
++)
4052 bnxt_hwrm_vnic_set_rss(bp
, i
, false);
4055 static void bnxt_hwrm_resource_free(struct bnxt
*bp
, bool close_path
,
4058 if (bp
->vnic_info
) {
4059 bnxt_hwrm_clear_vnic_filter(bp
);
4060 /* clear all RSS setting before free vnic ctx */
4061 bnxt_hwrm_clear_vnic_rss(bp
);
4062 bnxt_hwrm_vnic_ctx_free(bp
);
4063 /* before free the vnic, undo the vnic tpa settings */
4064 if (bp
->flags
& BNXT_FLAG_TPA
)
4065 bnxt_set_tpa(bp
, false);
4066 bnxt_hwrm_vnic_free(bp
);
4068 bnxt_hwrm_ring_free(bp
, close_path
);
4069 bnxt_hwrm_ring_grp_free(bp
);
4071 bnxt_hwrm_stat_ctx_free(bp
);
4072 bnxt_hwrm_free_tunnel_ports(bp
);
4076 static int bnxt_setup_vnic(struct bnxt
*bp
, u16 vnic_id
)
4080 /* allocate context for vnic */
4081 rc
= bnxt_hwrm_vnic_ctx_alloc(bp
, vnic_id
);
4083 netdev_err(bp
->dev
, "hwrm vnic %d alloc failure rc: %x\n",
4085 goto vnic_setup_err
;
4087 bp
->rsscos_nr_ctxs
++;
4089 /* configure default vnic, ring grp */
4090 rc
= bnxt_hwrm_vnic_cfg(bp
, vnic_id
);
4092 netdev_err(bp
->dev
, "hwrm vnic %d cfg failure rc: %x\n",
4094 goto vnic_setup_err
;
4097 /* Enable RSS hashing on vnic */
4098 rc
= bnxt_hwrm_vnic_set_rss(bp
, vnic_id
, true);
4100 netdev_err(bp
->dev
, "hwrm vnic %d set rss failure rc: %x\n",
4102 goto vnic_setup_err
;
4105 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
) {
4106 rc
= bnxt_hwrm_vnic_set_hds(bp
, vnic_id
);
4108 netdev_err(bp
->dev
, "hwrm vnic %d set hds failure rc: %x\n",
4117 static int bnxt_alloc_rfs_vnics(struct bnxt
*bp
)
4119 #ifdef CONFIG_RFS_ACCEL
4122 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
4123 u16 vnic_id
= i
+ 1;
4126 if (vnic_id
>= bp
->nr_vnics
)
4129 bp
->vnic_info
[vnic_id
].flags
|= BNXT_VNIC_RFS_FLAG
;
4130 rc
= bnxt_hwrm_vnic_alloc(bp
, vnic_id
, ring_id
, 1);
4132 netdev_err(bp
->dev
, "hwrm vnic %d alloc failure rc: %x\n",
4136 rc
= bnxt_setup_vnic(bp
, vnic_id
);
4146 static int bnxt_cfg_rx_mode(struct bnxt
*);
4147 static bool bnxt_mc_list_updated(struct bnxt
*, u32
*);
4149 static int bnxt_init_chip(struct bnxt
*bp
, bool irq_re_init
)
4151 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
4155 rc
= bnxt_hwrm_stat_ctx_alloc(bp
);
4157 netdev_err(bp
->dev
, "hwrm stat ctx alloc failure rc: %x\n",
4163 rc
= bnxt_hwrm_ring_alloc(bp
);
4165 netdev_err(bp
->dev
, "hwrm ring alloc failure rc: %x\n", rc
);
4169 rc
= bnxt_hwrm_ring_grp_alloc(bp
);
4171 netdev_err(bp
->dev
, "hwrm_ring_grp alloc failure: %x\n", rc
);
4175 /* default vnic 0 */
4176 rc
= bnxt_hwrm_vnic_alloc(bp
, 0, 0, bp
->rx_nr_rings
);
4178 netdev_err(bp
->dev
, "hwrm vnic alloc failure rc: %x\n", rc
);
4182 rc
= bnxt_setup_vnic(bp
, 0);
4186 if (bp
->flags
& BNXT_FLAG_RFS
) {
4187 rc
= bnxt_alloc_rfs_vnics(bp
);
4192 if (bp
->flags
& BNXT_FLAG_TPA
) {
4193 rc
= bnxt_set_tpa(bp
, true);
4199 bnxt_update_vf_mac(bp
);
4201 /* Filter for default vnic 0 */
4202 rc
= bnxt_hwrm_set_vnic_filter(bp
, 0, 0, bp
->dev
->dev_addr
);
4204 netdev_err(bp
->dev
, "HWRM vnic filter failure rc: %x\n", rc
);
4207 vnic
->uc_filter_count
= 1;
4209 vnic
->rx_mask
= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST
;
4211 if ((bp
->dev
->flags
& IFF_PROMISC
) && BNXT_PF(bp
))
4212 vnic
->rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
;
4214 if (bp
->dev
->flags
& IFF_ALLMULTI
) {
4215 vnic
->rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
;
4216 vnic
->mc_list_count
= 0;
4220 bnxt_mc_list_updated(bp
, &mask
);
4221 vnic
->rx_mask
|= mask
;
4224 rc
= bnxt_cfg_rx_mode(bp
);
4228 rc
= bnxt_hwrm_set_coal(bp
);
4230 netdev_warn(bp
->dev
, "HWRM set coalescing failure rc: %x\n",
4236 bnxt_hwrm_resource_free(bp
, 0, true);
4241 static int bnxt_shutdown_nic(struct bnxt
*bp
, bool irq_re_init
)
4243 bnxt_hwrm_resource_free(bp
, 1, irq_re_init
);
4247 static int bnxt_init_nic(struct bnxt
*bp
, bool irq_re_init
)
4249 bnxt_init_rx_rings(bp
);
4250 bnxt_init_tx_rings(bp
);
4251 bnxt_init_ring_grps(bp
, irq_re_init
);
4252 bnxt_init_vnics(bp
);
4254 return bnxt_init_chip(bp
, irq_re_init
);
4257 static void bnxt_disable_int(struct bnxt
*bp
)
4264 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4265 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4266 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
4268 BNXT_CP_DB(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
4272 static void bnxt_enable_int(struct bnxt
*bp
)
4276 atomic_set(&bp
->intr_sem
, 0);
4277 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4278 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4279 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
4281 BNXT_CP_DB_REARM(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
4285 static int bnxt_set_real_num_queues(struct bnxt
*bp
)
4288 struct net_device
*dev
= bp
->dev
;
4290 rc
= netif_set_real_num_tx_queues(dev
, bp
->tx_nr_rings
);
4294 rc
= netif_set_real_num_rx_queues(dev
, bp
->rx_nr_rings
);
4298 #ifdef CONFIG_RFS_ACCEL
4299 if (bp
->flags
& BNXT_FLAG_RFS
)
4300 dev
->rx_cpu_rmap
= alloc_irq_cpu_rmap(bp
->rx_nr_rings
);
4306 static int bnxt_trim_rings(struct bnxt
*bp
, int *rx
, int *tx
, int max
,
4309 int _rx
= *rx
, _tx
= *tx
;
4312 *rx
= min_t(int, _rx
, max
);
4313 *tx
= min_t(int, _tx
, max
);
4318 while (_rx
+ _tx
> max
) {
4319 if (_rx
> _tx
&& _rx
> 1)
4330 static int bnxt_setup_msix(struct bnxt
*bp
)
4332 struct msix_entry
*msix_ent
;
4333 struct net_device
*dev
= bp
->dev
;
4334 int i
, total_vecs
, rc
= 0, min
= 1;
4335 const int len
= sizeof(bp
->irq_tbl
[0].name
);
4337 bp
->flags
&= ~BNXT_FLAG_USING_MSIX
;
4338 total_vecs
= bp
->cp_nr_rings
;
4340 msix_ent
= kcalloc(total_vecs
, sizeof(struct msix_entry
), GFP_KERNEL
);
4344 for (i
= 0; i
< total_vecs
; i
++) {
4345 msix_ent
[i
].entry
= i
;
4346 msix_ent
[i
].vector
= 0;
4349 if (!(bp
->flags
& BNXT_FLAG_SHARED_RINGS
))
4352 total_vecs
= pci_enable_msix_range(bp
->pdev
, msix_ent
, min
, total_vecs
);
4353 if (total_vecs
< 0) {
4355 goto msix_setup_exit
;
4358 bp
->irq_tbl
= kcalloc(total_vecs
, sizeof(struct bnxt_irq
), GFP_KERNEL
);
4362 /* Trim rings based upon num of vectors allocated */
4363 rc
= bnxt_trim_rings(bp
, &bp
->rx_nr_rings
, &bp
->tx_nr_rings
,
4364 total_vecs
, min
== 1);
4366 goto msix_setup_exit
;
4368 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
;
4369 tcs
= netdev_get_num_tc(dev
);
4371 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
/ tcs
;
4372 if (bp
->tx_nr_rings_per_tc
== 0) {
4373 netdev_reset_tc(dev
);
4374 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
;
4378 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
* tcs
;
4379 for (i
= 0; i
< tcs
; i
++) {
4380 count
= bp
->tx_nr_rings_per_tc
;
4382 netdev_set_tc_queue(dev
, i
, count
, off
);
4386 bp
->cp_nr_rings
= total_vecs
;
4388 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4391 bp
->irq_tbl
[i
].vector
= msix_ent
[i
].vector
;
4392 if (bp
->flags
& BNXT_FLAG_SHARED_RINGS
)
4394 else if (i
< bp
->rx_nr_rings
)
4399 snprintf(bp
->irq_tbl
[i
].name
, len
,
4400 "%s-%s-%d", dev
->name
, attr
, i
);
4401 bp
->irq_tbl
[i
].handler
= bnxt_msix
;
4403 rc
= bnxt_set_real_num_queues(bp
);
4405 goto msix_setup_exit
;
4408 goto msix_setup_exit
;
4410 bp
->flags
|= BNXT_FLAG_USING_MSIX
;
4415 netdev_err(bp
->dev
, "bnxt_setup_msix err: %x\n", rc
);
4416 pci_disable_msix(bp
->pdev
);
4421 static int bnxt_setup_inta(struct bnxt
*bp
)
4424 const int len
= sizeof(bp
->irq_tbl
[0].name
);
4426 if (netdev_get_num_tc(bp
->dev
))
4427 netdev_reset_tc(bp
->dev
);
4429 bp
->irq_tbl
= kcalloc(1, sizeof(struct bnxt_irq
), GFP_KERNEL
);
4434 bp
->rx_nr_rings
= 1;
4435 bp
->tx_nr_rings
= 1;
4436 bp
->cp_nr_rings
= 1;
4437 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
;
4438 bp
->flags
|= BNXT_FLAG_SHARED_RINGS
;
4439 bp
->irq_tbl
[0].vector
= bp
->pdev
->irq
;
4440 snprintf(bp
->irq_tbl
[0].name
, len
,
4441 "%s-%s-%d", bp
->dev
->name
, "TxRx", 0);
4442 bp
->irq_tbl
[0].handler
= bnxt_inta
;
4443 rc
= bnxt_set_real_num_queues(bp
);
4447 static int bnxt_setup_int_mode(struct bnxt
*bp
)
4451 if (bp
->flags
& BNXT_FLAG_MSIX_CAP
)
4452 rc
= bnxt_setup_msix(bp
);
4454 if (!(bp
->flags
& BNXT_FLAG_USING_MSIX
) && BNXT_PF(bp
)) {
4455 /* fallback to INTA */
4456 rc
= bnxt_setup_inta(bp
);
4461 static void bnxt_free_irq(struct bnxt
*bp
)
4463 struct bnxt_irq
*irq
;
4466 #ifdef CONFIG_RFS_ACCEL
4467 free_irq_cpu_rmap(bp
->dev
->rx_cpu_rmap
);
4468 bp
->dev
->rx_cpu_rmap
= NULL
;
4473 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4474 irq
= &bp
->irq_tbl
[i
];
4476 free_irq(irq
->vector
, bp
->bnapi
[i
]);
4479 if (bp
->flags
& BNXT_FLAG_USING_MSIX
)
4480 pci_disable_msix(bp
->pdev
);
4485 static int bnxt_request_irq(struct bnxt
*bp
)
4488 unsigned long flags
= 0;
4489 #ifdef CONFIG_RFS_ACCEL
4490 struct cpu_rmap
*rmap
= bp
->dev
->rx_cpu_rmap
;
4493 if (!(bp
->flags
& BNXT_FLAG_USING_MSIX
))
4494 flags
= IRQF_SHARED
;
4496 for (i
= 0, j
= 0; i
< bp
->cp_nr_rings
; i
++) {
4497 struct bnxt_irq
*irq
= &bp
->irq_tbl
[i
];
4498 #ifdef CONFIG_RFS_ACCEL
4499 if (rmap
&& bp
->bnapi
[i
]->rx_ring
) {
4500 rc
= irq_cpu_rmap_add(rmap
, irq
->vector
);
4502 netdev_warn(bp
->dev
, "failed adding irq rmap for ring %d\n",
4507 rc
= request_irq(irq
->vector
, irq
->handler
, flags
, irq
->name
,
4517 static void bnxt_del_napi(struct bnxt
*bp
)
4524 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4525 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4527 napi_hash_del(&bnapi
->napi
);
4528 netif_napi_del(&bnapi
->napi
);
4532 static void bnxt_init_napi(struct bnxt
*bp
)
4535 struct bnxt_napi
*bnapi
;
4537 if (bp
->flags
& BNXT_FLAG_USING_MSIX
) {
4538 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4539 bnapi
= bp
->bnapi
[i
];
4540 netif_napi_add(bp
->dev
, &bnapi
->napi
,
4544 bnapi
= bp
->bnapi
[0];
4545 netif_napi_add(bp
->dev
, &bnapi
->napi
, bnxt_poll
, 64);
4549 static void bnxt_disable_napi(struct bnxt
*bp
)
4556 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4557 napi_disable(&bp
->bnapi
[i
]->napi
);
4558 bnxt_disable_poll(bp
->bnapi
[i
]);
4562 static void bnxt_enable_napi(struct bnxt
*bp
)
4566 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4567 bp
->bnapi
[i
]->in_reset
= false;
4568 bnxt_enable_poll(bp
->bnapi
[i
]);
4569 napi_enable(&bp
->bnapi
[i
]->napi
);
4573 static void bnxt_tx_disable(struct bnxt
*bp
)
4576 struct bnxt_tx_ring_info
*txr
;
4577 struct netdev_queue
*txq
;
4580 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
4581 txr
= &bp
->tx_ring
[i
];
4582 txq
= netdev_get_tx_queue(bp
->dev
, i
);
4583 __netif_tx_lock(txq
, smp_processor_id());
4584 txr
->dev_state
= BNXT_DEV_STATE_CLOSING
;
4585 __netif_tx_unlock(txq
);
4588 /* Stop all TX queues */
4589 netif_tx_disable(bp
->dev
);
4590 netif_carrier_off(bp
->dev
);
4593 static void bnxt_tx_enable(struct bnxt
*bp
)
4596 struct bnxt_tx_ring_info
*txr
;
4597 struct netdev_queue
*txq
;
4599 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
4600 txr
= &bp
->tx_ring
[i
];
4601 txq
= netdev_get_tx_queue(bp
->dev
, i
);
4604 netif_tx_wake_all_queues(bp
->dev
);
4605 if (bp
->link_info
.link_up
)
4606 netif_carrier_on(bp
->dev
);
4609 static void bnxt_report_link(struct bnxt
*bp
)
4611 if (bp
->link_info
.link_up
) {
4613 const char *flow_ctrl
;
4616 netif_carrier_on(bp
->dev
);
4617 if (bp
->link_info
.duplex
== BNXT_LINK_DUPLEX_FULL
)
4621 if (bp
->link_info
.pause
== BNXT_LINK_PAUSE_BOTH
)
4622 flow_ctrl
= "ON - receive & transmit";
4623 else if (bp
->link_info
.pause
== BNXT_LINK_PAUSE_TX
)
4624 flow_ctrl
= "ON - transmit";
4625 else if (bp
->link_info
.pause
== BNXT_LINK_PAUSE_RX
)
4626 flow_ctrl
= "ON - receive";
4629 speed
= bnxt_fw_to_ethtool_speed(bp
->link_info
.link_speed
);
4630 netdev_info(bp
->dev
, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
4631 speed
, duplex
, flow_ctrl
);
4632 if (bp
->flags
& BNXT_FLAG_EEE_CAP
)
4633 netdev_info(bp
->dev
, "EEE is %s\n",
4634 bp
->eee
.eee_active
? "active" :
4637 netif_carrier_off(bp
->dev
);
4638 netdev_err(bp
->dev
, "NIC Link is Down\n");
4642 static int bnxt_hwrm_phy_qcaps(struct bnxt
*bp
)
4645 struct hwrm_port_phy_qcaps_input req
= {0};
4646 struct hwrm_port_phy_qcaps_output
*resp
= bp
->hwrm_cmd_resp_addr
;
4648 if (bp
->hwrm_spec_code
< 0x10201)
4651 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_QCAPS
, -1, -1);
4653 mutex_lock(&bp
->hwrm_cmd_lock
);
4654 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4656 goto hwrm_phy_qcaps_exit
;
4658 if (resp
->eee_supported
& PORT_PHY_QCAPS_RESP_EEE_SUPPORTED
) {
4659 struct ethtool_eee
*eee
= &bp
->eee
;
4660 u16 fw_speeds
= le16_to_cpu(resp
->supported_speeds_eee_mode
);
4662 bp
->flags
|= BNXT_FLAG_EEE_CAP
;
4663 eee
->supported
= _bnxt_fw_to_ethtool_adv_spds(fw_speeds
, 0);
4664 bp
->lpi_tmr_lo
= le32_to_cpu(resp
->tx_lpi_timer_low
) &
4665 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK
;
4666 bp
->lpi_tmr_hi
= le32_to_cpu(resp
->valid_tx_lpi_timer_high
) &
4667 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK
;
4670 hwrm_phy_qcaps_exit
:
4671 mutex_unlock(&bp
->hwrm_cmd_lock
);
4675 static int bnxt_update_link(struct bnxt
*bp
, bool chng_link_state
)
4678 struct bnxt_link_info
*link_info
= &bp
->link_info
;
4679 struct hwrm_port_phy_qcfg_input req
= {0};
4680 struct hwrm_port_phy_qcfg_output
*resp
= bp
->hwrm_cmd_resp_addr
;
4681 u8 link_up
= link_info
->link_up
;
4683 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_QCFG
, -1, -1);
4685 mutex_lock(&bp
->hwrm_cmd_lock
);
4686 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4688 mutex_unlock(&bp
->hwrm_cmd_lock
);
4692 memcpy(&link_info
->phy_qcfg_resp
, resp
, sizeof(*resp
));
4693 link_info
->phy_link_status
= resp
->link
;
4694 link_info
->duplex
= resp
->duplex
;
4695 link_info
->pause
= resp
->pause
;
4696 link_info
->auto_mode
= resp
->auto_mode
;
4697 link_info
->auto_pause_setting
= resp
->auto_pause
;
4698 link_info
->lp_pause
= resp
->link_partner_adv_pause
;
4699 link_info
->force_pause_setting
= resp
->force_pause
;
4700 link_info
->duplex_setting
= resp
->duplex
;
4701 if (link_info
->phy_link_status
== BNXT_LINK_LINK
)
4702 link_info
->link_speed
= le16_to_cpu(resp
->link_speed
);
4704 link_info
->link_speed
= 0;
4705 link_info
->force_link_speed
= le16_to_cpu(resp
->force_link_speed
);
4706 link_info
->support_speeds
= le16_to_cpu(resp
->support_speeds
);
4707 link_info
->auto_link_speeds
= le16_to_cpu(resp
->auto_link_speed_mask
);
4708 link_info
->lp_auto_link_speeds
=
4709 le16_to_cpu(resp
->link_partner_adv_speeds
);
4710 link_info
->preemphasis
= le32_to_cpu(resp
->preemphasis
);
4711 link_info
->phy_ver
[0] = resp
->phy_maj
;
4712 link_info
->phy_ver
[1] = resp
->phy_min
;
4713 link_info
->phy_ver
[2] = resp
->phy_bld
;
4714 link_info
->media_type
= resp
->media_type
;
4715 link_info
->phy_type
= resp
->phy_type
;
4716 link_info
->transceiver
= resp
->xcvr_pkg_type
;
4717 link_info
->phy_addr
= resp
->eee_config_phy_addr
&
4718 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK
;
4719 link_info
->module_status
= resp
->module_status
;
4721 if (bp
->flags
& BNXT_FLAG_EEE_CAP
) {
4722 struct ethtool_eee
*eee
= &bp
->eee
;
4725 eee
->eee_active
= 0;
4726 if (resp
->eee_config_phy_addr
&
4727 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE
) {
4728 eee
->eee_active
= 1;
4729 fw_speeds
= le16_to_cpu(
4730 resp
->link_partner_adv_eee_link_speed_mask
);
4731 eee
->lp_advertised
=
4732 _bnxt_fw_to_ethtool_adv_spds(fw_speeds
, 0);
4735 /* Pull initial EEE config */
4736 if (!chng_link_state
) {
4737 if (resp
->eee_config_phy_addr
&
4738 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED
)
4739 eee
->eee_enabled
= 1;
4741 fw_speeds
= le16_to_cpu(resp
->adv_eee_link_speed_mask
);
4743 _bnxt_fw_to_ethtool_adv_spds(fw_speeds
, 0);
4745 if (resp
->eee_config_phy_addr
&
4746 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI
) {
4749 eee
->tx_lpi_enabled
= 1;
4750 tmr
= resp
->xcvr_identifier_type_tx_lpi_timer
;
4751 eee
->tx_lpi_timer
= le32_to_cpu(tmr
) &
4752 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK
;
4756 /* TODO: need to add more logic to report VF link */
4757 if (chng_link_state
) {
4758 if (link_info
->phy_link_status
== BNXT_LINK_LINK
)
4759 link_info
->link_up
= 1;
4761 link_info
->link_up
= 0;
4762 if (link_up
!= link_info
->link_up
)
4763 bnxt_report_link(bp
);
4765 /* alwasy link down if not require to update link state */
4766 link_info
->link_up
= 0;
4768 mutex_unlock(&bp
->hwrm_cmd_lock
);
4772 static void bnxt_get_port_module_status(struct bnxt
*bp
)
4774 struct bnxt_link_info
*link_info
= &bp
->link_info
;
4775 struct hwrm_port_phy_qcfg_output
*resp
= &link_info
->phy_qcfg_resp
;
4778 if (bnxt_update_link(bp
, true))
4781 module_status
= link_info
->module_status
;
4782 switch (module_status
) {
4783 case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX
:
4784 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN
:
4785 case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG
:
4786 netdev_warn(bp
->dev
, "Unqualified SFP+ module detected on port %d\n",
4788 if (bp
->hwrm_spec_code
>= 0x10201) {
4789 netdev_warn(bp
->dev
, "Module part number %s\n",
4790 resp
->phy_vendor_partnumber
);
4792 if (module_status
== PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX
)
4793 netdev_warn(bp
->dev
, "TX is disabled\n");
4794 if (module_status
== PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN
)
4795 netdev_warn(bp
->dev
, "SFP+ module is shutdown\n");
4800 bnxt_hwrm_set_pause_common(struct bnxt
*bp
, struct hwrm_port_phy_cfg_input
*req
)
4802 if (bp
->link_info
.autoneg
& BNXT_AUTONEG_FLOW_CTRL
) {
4803 if (bp
->hwrm_spec_code
>= 0x10201)
4805 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE
;
4806 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_RX
)
4807 req
->auto_pause
|= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX
;
4808 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_TX
)
4809 req
->auto_pause
|= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX
;
4811 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE
);
4813 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_RX
)
4814 req
->force_pause
|= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX
;
4815 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_TX
)
4816 req
->force_pause
|= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX
;
4818 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE
);
4819 if (bp
->hwrm_spec_code
>= 0x10201) {
4820 req
->auto_pause
= req
->force_pause
;
4821 req
->enables
|= cpu_to_le32(
4822 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE
);
4827 static void bnxt_hwrm_set_link_common(struct bnxt
*bp
,
4828 struct hwrm_port_phy_cfg_input
*req
)
4830 u8 autoneg
= bp
->link_info
.autoneg
;
4831 u16 fw_link_speed
= bp
->link_info
.req_link_speed
;
4832 u32 advertising
= bp
->link_info
.advertising
;
4834 if (autoneg
& BNXT_AUTONEG_SPEED
) {
4836 PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK
;
4838 req
->enables
|= cpu_to_le32(
4839 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK
);
4840 req
->auto_link_speed_mask
= cpu_to_le16(advertising
);
4842 req
->enables
|= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE
);
4844 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG
);
4846 req
->force_link_speed
= cpu_to_le16(fw_link_speed
);
4847 req
->flags
|= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE
);
4850 /* tell chimp that the setting takes effect immediately */
4851 req
->flags
|= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY
);
4854 int bnxt_hwrm_set_pause(struct bnxt
*bp
)
4856 struct hwrm_port_phy_cfg_input req
= {0};
4859 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_CFG
, -1, -1);
4860 bnxt_hwrm_set_pause_common(bp
, &req
);
4862 if ((bp
->link_info
.autoneg
& BNXT_AUTONEG_FLOW_CTRL
) ||
4863 bp
->link_info
.force_link_chng
)
4864 bnxt_hwrm_set_link_common(bp
, &req
);
4866 mutex_lock(&bp
->hwrm_cmd_lock
);
4867 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4868 if (!rc
&& !(bp
->link_info
.autoneg
& BNXT_AUTONEG_FLOW_CTRL
)) {
4869 /* since changing of pause setting doesn't trigger any link
4870 * change event, the driver needs to update the current pause
4871 * result upon successfully return of the phy_cfg command
4873 bp
->link_info
.pause
=
4874 bp
->link_info
.force_pause_setting
= bp
->link_info
.req_flow_ctrl
;
4875 bp
->link_info
.auto_pause_setting
= 0;
4876 if (!bp
->link_info
.force_link_chng
)
4877 bnxt_report_link(bp
);
4879 bp
->link_info
.force_link_chng
= false;
4880 mutex_unlock(&bp
->hwrm_cmd_lock
);
4884 static void bnxt_hwrm_set_eee(struct bnxt
*bp
,
4885 struct hwrm_port_phy_cfg_input
*req
)
4887 struct ethtool_eee
*eee
= &bp
->eee
;
4889 if (eee
->eee_enabled
) {
4891 u32 flags
= PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE
;
4893 if (eee
->tx_lpi_enabled
)
4894 flags
|= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE
;
4896 flags
|= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE
;
4898 req
->flags
|= cpu_to_le32(flags
);
4899 eee_speeds
= bnxt_get_fw_auto_link_speeds(eee
->advertised
);
4900 req
->eee_link_speed_mask
= cpu_to_le16(eee_speeds
);
4901 req
->tx_lpi_timer
= cpu_to_le32(eee
->tx_lpi_timer
);
4903 req
->flags
|= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE
);
4907 int bnxt_hwrm_set_link_setting(struct bnxt
*bp
, bool set_pause
, bool set_eee
)
4909 struct hwrm_port_phy_cfg_input req
= {0};
4911 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_CFG
, -1, -1);
4913 bnxt_hwrm_set_pause_common(bp
, &req
);
4915 bnxt_hwrm_set_link_common(bp
, &req
);
4918 bnxt_hwrm_set_eee(bp
, &req
);
4919 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4922 static int bnxt_hwrm_shutdown_link(struct bnxt
*bp
)
4924 struct hwrm_port_phy_cfg_input req
= {0};
4929 if (pci_num_vf(bp
->pdev
))
4932 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_CFG
, -1, -1);
4933 req
.flags
= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DOWN
);
4934 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4937 static bool bnxt_eee_config_ok(struct bnxt
*bp
)
4939 struct ethtool_eee
*eee
= &bp
->eee
;
4940 struct bnxt_link_info
*link_info
= &bp
->link_info
;
4942 if (!(bp
->flags
& BNXT_FLAG_EEE_CAP
))
4945 if (eee
->eee_enabled
) {
4947 _bnxt_fw_to_ethtool_adv_spds(link_info
->advertising
, 0);
4949 if (!(link_info
->autoneg
& BNXT_AUTONEG_SPEED
)) {
4950 eee
->eee_enabled
= 0;
4953 if (eee
->advertised
& ~advertising
) {
4954 eee
->advertised
= advertising
& eee
->supported
;
4961 static int bnxt_update_phy_setting(struct bnxt
*bp
)
4964 bool update_link
= false;
4965 bool update_pause
= false;
4966 bool update_eee
= false;
4967 struct bnxt_link_info
*link_info
= &bp
->link_info
;
4969 rc
= bnxt_update_link(bp
, true);
4971 netdev_err(bp
->dev
, "failed to update link (rc: %x)\n",
4975 if ((link_info
->autoneg
& BNXT_AUTONEG_FLOW_CTRL
) &&
4976 (link_info
->auto_pause_setting
& BNXT_LINK_PAUSE_BOTH
) !=
4977 link_info
->req_flow_ctrl
)
4978 update_pause
= true;
4979 if (!(link_info
->autoneg
& BNXT_AUTONEG_FLOW_CTRL
) &&
4980 link_info
->force_pause_setting
!= link_info
->req_flow_ctrl
)
4981 update_pause
= true;
4982 if (!(link_info
->autoneg
& BNXT_AUTONEG_SPEED
)) {
4983 if (BNXT_AUTO_MODE(link_info
->auto_mode
))
4985 if (link_info
->req_link_speed
!= link_info
->force_link_speed
)
4987 if (link_info
->req_duplex
!= link_info
->duplex_setting
)
4990 if (link_info
->auto_mode
== BNXT_LINK_AUTO_NONE
)
4992 if (link_info
->advertising
!= link_info
->auto_link_speeds
)
4996 if (!bnxt_eee_config_ok(bp
))
5000 rc
= bnxt_hwrm_set_link_setting(bp
, update_pause
, update_eee
);
5001 else if (update_pause
)
5002 rc
= bnxt_hwrm_set_pause(bp
);
5004 netdev_err(bp
->dev
, "failed to update phy setting (rc: %x)\n",
5012 /* Common routine to pre-map certain register block to different GRC window.
5013 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
5014 * in PF and 3 windows in VF that can be customized to map in different
5017 static void bnxt_preset_reg_win(struct bnxt
*bp
)
5020 /* CAG registers map to GRC window #4 */
5021 writel(BNXT_CAG_REG_BASE
,
5022 bp
->bar0
+ BNXT_GRCPF_REG_WINDOW_BASE_OUT
+ 12);
5026 static int __bnxt_open_nic(struct bnxt
*bp
, bool irq_re_init
, bool link_re_init
)
5030 bnxt_preset_reg_win(bp
);
5031 netif_carrier_off(bp
->dev
);
5033 rc
= bnxt_setup_int_mode(bp
);
5035 netdev_err(bp
->dev
, "bnxt_setup_int_mode err: %x\n",
5040 if ((bp
->flags
& BNXT_FLAG_RFS
) &&
5041 !(bp
->flags
& BNXT_FLAG_USING_MSIX
)) {
5042 /* disable RFS if falling back to INTA */
5043 bp
->dev
->hw_features
&= ~NETIF_F_NTUPLE
;
5044 bp
->flags
&= ~BNXT_FLAG_RFS
;
5047 rc
= bnxt_alloc_mem(bp
, irq_re_init
);
5049 netdev_err(bp
->dev
, "bnxt_alloc_mem err: %x\n", rc
);
5050 goto open_err_free_mem
;
5055 rc
= bnxt_request_irq(bp
);
5057 netdev_err(bp
->dev
, "bnxt_request_irq err: %x\n", rc
);
5062 bnxt_enable_napi(bp
);
5064 rc
= bnxt_init_nic(bp
, irq_re_init
);
5066 netdev_err(bp
->dev
, "bnxt_init_nic err: %x\n", rc
);
5071 rc
= bnxt_update_phy_setting(bp
);
5073 netdev_warn(bp
->dev
, "failed to update phy settings\n");
5077 #if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE)
5078 vxlan_get_rx_port(bp
->dev
);
5080 if (!bnxt_hwrm_tunnel_dst_port_alloc(
5082 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
))
5083 bp
->nge_port_cnt
= 1;
5086 set_bit(BNXT_STATE_OPEN
, &bp
->state
);
5087 bnxt_enable_int(bp
);
5088 /* Enable TX queues */
5090 mod_timer(&bp
->timer
, jiffies
+ bp
->current_interval
);
5091 /* Poll link status and check for SFP+ module status */
5092 bnxt_get_port_module_status(bp
);
5097 bnxt_disable_napi(bp
);
5103 bnxt_free_mem(bp
, true);
5107 /* rtnl_lock held */
5108 int bnxt_open_nic(struct bnxt
*bp
, bool irq_re_init
, bool link_re_init
)
5112 rc
= __bnxt_open_nic(bp
, irq_re_init
, link_re_init
);
5114 netdev_err(bp
->dev
, "nic open fail (rc: %x)\n", rc
);
5120 static int bnxt_open(struct net_device
*dev
)
5122 struct bnxt
*bp
= netdev_priv(dev
);
5125 rc
= bnxt_hwrm_func_reset(bp
);
5127 netdev_err(bp
->dev
, "hwrm chip reset failure rc: %x\n",
5132 return __bnxt_open_nic(bp
, true, true);
5135 static void bnxt_disable_int_sync(struct bnxt
*bp
)
5139 atomic_inc(&bp
->intr_sem
);
5140 if (!netif_running(bp
->dev
))
5143 bnxt_disable_int(bp
);
5144 for (i
= 0; i
< bp
->cp_nr_rings
; i
++)
5145 synchronize_irq(bp
->irq_tbl
[i
].vector
);
5148 int bnxt_close_nic(struct bnxt
*bp
, bool irq_re_init
, bool link_re_init
)
5152 #ifdef CONFIG_BNXT_SRIOV
5153 if (bp
->sriov_cfg
) {
5154 rc
= wait_event_interruptible_timeout(bp
->sriov_cfg_wait
,
5156 BNXT_SRIOV_CFG_WAIT_TMO
);
5158 netdev_warn(bp
->dev
, "timeout waiting for SRIOV config operation to complete!\n");
5161 /* Change device state to avoid TX queue wake up's */
5162 bnxt_tx_disable(bp
);
5164 clear_bit(BNXT_STATE_OPEN
, &bp
->state
);
5165 smp_mb__after_atomic();
5166 while (test_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
))
5169 /* Flush rings before disabling interrupts */
5170 bnxt_shutdown_nic(bp
, irq_re_init
);
5172 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
5174 bnxt_disable_napi(bp
);
5175 bnxt_disable_int_sync(bp
);
5176 del_timer_sync(&bp
->timer
);
5183 bnxt_free_mem(bp
, irq_re_init
);
5187 static int bnxt_close(struct net_device
*dev
)
5189 struct bnxt
*bp
= netdev_priv(dev
);
5191 bnxt_close_nic(bp
, true, true);
5192 bnxt_hwrm_shutdown_link(bp
);
5196 /* rtnl_lock held */
5197 static int bnxt_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
5203 if (!netif_running(dev
))
5210 if (!netif_running(dev
))
5222 static struct rtnl_link_stats64
*
5223 bnxt_get_stats64(struct net_device
*dev
, struct rtnl_link_stats64
*stats
)
5226 struct bnxt
*bp
= netdev_priv(dev
);
5228 memset(stats
, 0, sizeof(struct rtnl_link_stats64
));
5233 /* TODO check if we need to synchronize with bnxt_close path */
5234 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
5235 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
5236 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
5237 struct ctx_hw_stats
*hw_stats
= cpr
->hw_stats
;
5239 stats
->rx_packets
+= le64_to_cpu(hw_stats
->rx_ucast_pkts
);
5240 stats
->rx_packets
+= le64_to_cpu(hw_stats
->rx_mcast_pkts
);
5241 stats
->rx_packets
+= le64_to_cpu(hw_stats
->rx_bcast_pkts
);
5243 stats
->tx_packets
+= le64_to_cpu(hw_stats
->tx_ucast_pkts
);
5244 stats
->tx_packets
+= le64_to_cpu(hw_stats
->tx_mcast_pkts
);
5245 stats
->tx_packets
+= le64_to_cpu(hw_stats
->tx_bcast_pkts
);
5247 stats
->rx_bytes
+= le64_to_cpu(hw_stats
->rx_ucast_bytes
);
5248 stats
->rx_bytes
+= le64_to_cpu(hw_stats
->rx_mcast_bytes
);
5249 stats
->rx_bytes
+= le64_to_cpu(hw_stats
->rx_bcast_bytes
);
5251 stats
->tx_bytes
+= le64_to_cpu(hw_stats
->tx_ucast_bytes
);
5252 stats
->tx_bytes
+= le64_to_cpu(hw_stats
->tx_mcast_bytes
);
5253 stats
->tx_bytes
+= le64_to_cpu(hw_stats
->tx_bcast_bytes
);
5255 stats
->rx_missed_errors
+=
5256 le64_to_cpu(hw_stats
->rx_discard_pkts
);
5258 stats
->multicast
+= le64_to_cpu(hw_stats
->rx_mcast_pkts
);
5260 stats
->tx_dropped
+= le64_to_cpu(hw_stats
->tx_drop_pkts
);
5263 if (bp
->flags
& BNXT_FLAG_PORT_STATS
) {
5264 struct rx_port_stats
*rx
= bp
->hw_rx_port_stats
;
5265 struct tx_port_stats
*tx
= bp
->hw_tx_port_stats
;
5267 stats
->rx_crc_errors
= le64_to_cpu(rx
->rx_fcs_err_frames
);
5268 stats
->rx_frame_errors
= le64_to_cpu(rx
->rx_align_err_frames
);
5269 stats
->rx_length_errors
= le64_to_cpu(rx
->rx_undrsz_frames
) +
5270 le64_to_cpu(rx
->rx_ovrsz_frames
) +
5271 le64_to_cpu(rx
->rx_runt_frames
);
5272 stats
->rx_errors
= le64_to_cpu(rx
->rx_false_carrier_frames
) +
5273 le64_to_cpu(rx
->rx_jbr_frames
);
5274 stats
->collisions
= le64_to_cpu(tx
->tx_total_collisions
);
5275 stats
->tx_fifo_errors
= le64_to_cpu(tx
->tx_fifo_underruns
);
5276 stats
->tx_errors
= le64_to_cpu(tx
->tx_err
);
5282 static bool bnxt_mc_list_updated(struct bnxt
*bp
, u32
*rx_mask
)
5284 struct net_device
*dev
= bp
->dev
;
5285 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
5286 struct netdev_hw_addr
*ha
;
5289 bool update
= false;
5292 netdev_for_each_mc_addr(ha
, dev
) {
5293 if (mc_count
>= BNXT_MAX_MC_ADDRS
) {
5294 *rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
;
5295 vnic
->mc_list_count
= 0;
5299 if (!ether_addr_equal(haddr
, vnic
->mc_list
+ off
)) {
5300 memcpy(vnic
->mc_list
+ off
, haddr
, ETH_ALEN
);
5307 *rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST
;
5309 if (mc_count
!= vnic
->mc_list_count
) {
5310 vnic
->mc_list_count
= mc_count
;
5316 static bool bnxt_uc_list_updated(struct bnxt
*bp
)
5318 struct net_device
*dev
= bp
->dev
;
5319 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
5320 struct netdev_hw_addr
*ha
;
5323 if (netdev_uc_count(dev
) != (vnic
->uc_filter_count
- 1))
5326 netdev_for_each_uc_addr(ha
, dev
) {
5327 if (!ether_addr_equal(ha
->addr
, vnic
->uc_list
+ off
))
5335 static void bnxt_set_rx_mode(struct net_device
*dev
)
5337 struct bnxt
*bp
= netdev_priv(dev
);
5338 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
5339 u32 mask
= vnic
->rx_mask
;
5340 bool mc_update
= false;
5343 if (!netif_running(dev
))
5346 mask
&= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
|
5347 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST
|
5348 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
);
5350 /* Only allow PF to be in promiscuous mode */
5351 if ((dev
->flags
& IFF_PROMISC
) && BNXT_PF(bp
))
5352 mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
;
5354 uc_update
= bnxt_uc_list_updated(bp
);
5356 if (dev
->flags
& IFF_ALLMULTI
) {
5357 mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
;
5358 vnic
->mc_list_count
= 0;
5360 mc_update
= bnxt_mc_list_updated(bp
, &mask
);
5363 if (mask
!= vnic
->rx_mask
|| uc_update
|| mc_update
) {
5364 vnic
->rx_mask
= mask
;
5366 set_bit(BNXT_RX_MASK_SP_EVENT
, &bp
->sp_event
);
5367 schedule_work(&bp
->sp_task
);
5371 static int bnxt_cfg_rx_mode(struct bnxt
*bp
)
5373 struct net_device
*dev
= bp
->dev
;
5374 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
5375 struct netdev_hw_addr
*ha
;
5379 netif_addr_lock_bh(dev
);
5380 uc_update
= bnxt_uc_list_updated(bp
);
5381 netif_addr_unlock_bh(dev
);
5386 mutex_lock(&bp
->hwrm_cmd_lock
);
5387 for (i
= 1; i
< vnic
->uc_filter_count
; i
++) {
5388 struct hwrm_cfa_l2_filter_free_input req
= {0};
5390 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_L2_FILTER_FREE
, -1,
5393 req
.l2_filter_id
= vnic
->fw_l2_filter_id
[i
];
5395 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
5398 mutex_unlock(&bp
->hwrm_cmd_lock
);
5400 vnic
->uc_filter_count
= 1;
5402 netif_addr_lock_bh(dev
);
5403 if (netdev_uc_count(dev
) > (BNXT_MAX_UC_ADDRS
- 1)) {
5404 vnic
->rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
;
5406 netdev_for_each_uc_addr(ha
, dev
) {
5407 memcpy(vnic
->uc_list
+ off
, ha
->addr
, ETH_ALEN
);
5409 vnic
->uc_filter_count
++;
5412 netif_addr_unlock_bh(dev
);
5414 for (i
= 1, off
= 0; i
< vnic
->uc_filter_count
; i
++, off
+= ETH_ALEN
) {
5415 rc
= bnxt_hwrm_set_vnic_filter(bp
, 0, i
, vnic
->uc_list
+ off
);
5417 netdev_err(bp
->dev
, "HWRM vnic filter failure rc: %x\n",
5419 vnic
->uc_filter_count
= i
;
5425 rc
= bnxt_hwrm_cfa_l2_set_rx_mask(bp
, 0);
5427 netdev_err(bp
->dev
, "HWRM cfa l2 rx mask failure rc: %x\n",
5433 static bool bnxt_rfs_capable(struct bnxt
*bp
)
5435 #ifdef CONFIG_RFS_ACCEL
5436 struct bnxt_pf_info
*pf
= &bp
->pf
;
5439 if (BNXT_VF(bp
) || !(bp
->flags
& BNXT_FLAG_MSIX_CAP
))
5442 vnics
= 1 + bp
->rx_nr_rings
;
5443 if (vnics
> pf
->max_rsscos_ctxs
|| vnics
> pf
->max_vnics
)
5452 static netdev_features_t
bnxt_fix_features(struct net_device
*dev
,
5453 netdev_features_t features
)
5455 struct bnxt
*bp
= netdev_priv(dev
);
5457 if (!bnxt_rfs_capable(bp
))
5458 features
&= ~NETIF_F_NTUPLE
;
5460 /* Both CTAG and STAG VLAN accelaration on the RX side have to be
5461 * turned on or off together.
5463 if ((features
& (NETIF_F_HW_VLAN_CTAG_RX
| NETIF_F_HW_VLAN_STAG_RX
)) !=
5464 (NETIF_F_HW_VLAN_CTAG_RX
| NETIF_F_HW_VLAN_STAG_RX
)) {
5465 if (dev
->features
& NETIF_F_HW_VLAN_CTAG_RX
)
5466 features
&= ~(NETIF_F_HW_VLAN_CTAG_RX
|
5467 NETIF_F_HW_VLAN_STAG_RX
);
5469 features
|= NETIF_F_HW_VLAN_CTAG_RX
|
5470 NETIF_F_HW_VLAN_STAG_RX
;
5476 static int bnxt_set_features(struct net_device
*dev
, netdev_features_t features
)
5478 struct bnxt
*bp
= netdev_priv(dev
);
5479 u32 flags
= bp
->flags
;
5482 bool re_init
= false;
5483 bool update_tpa
= false;
5485 flags
&= ~BNXT_FLAG_ALL_CONFIG_FEATS
;
5486 if ((features
& NETIF_F_GRO
) && (bp
->pdev
->revision
> 0))
5487 flags
|= BNXT_FLAG_GRO
;
5488 if (features
& NETIF_F_LRO
)
5489 flags
|= BNXT_FLAG_LRO
;
5491 if (features
& NETIF_F_HW_VLAN_CTAG_RX
)
5492 flags
|= BNXT_FLAG_STRIP_VLAN
;
5494 if (features
& NETIF_F_NTUPLE
)
5495 flags
|= BNXT_FLAG_RFS
;
5497 changes
= flags
^ bp
->flags
;
5498 if (changes
& BNXT_FLAG_TPA
) {
5500 if ((bp
->flags
& BNXT_FLAG_TPA
) == 0 ||
5501 (flags
& BNXT_FLAG_TPA
) == 0)
5505 if (changes
& ~BNXT_FLAG_TPA
)
5508 if (flags
!= bp
->flags
) {
5509 u32 old_flags
= bp
->flags
;
5513 if (!test_bit(BNXT_STATE_OPEN
, &bp
->state
)) {
5515 bnxt_set_ring_params(bp
);
5520 bnxt_close_nic(bp
, false, false);
5522 bnxt_set_ring_params(bp
);
5524 return bnxt_open_nic(bp
, false, false);
5527 rc
= bnxt_set_tpa(bp
,
5528 (flags
& BNXT_FLAG_TPA
) ?
5531 bp
->flags
= old_flags
;
5537 static void bnxt_dump_tx_sw_state(struct bnxt_napi
*bnapi
)
5539 struct bnxt_tx_ring_info
*txr
= bnapi
->tx_ring
;
5540 int i
= bnapi
->index
;
5545 netdev_info(bnapi
->bp
->dev
, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
5546 i
, txr
->tx_ring_struct
.fw_ring_id
, txr
->tx_prod
,
5550 static void bnxt_dump_rx_sw_state(struct bnxt_napi
*bnapi
)
5552 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
5553 int i
= bnapi
->index
;
5558 netdev_info(bnapi
->bp
->dev
, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
5559 i
, rxr
->rx_ring_struct
.fw_ring_id
, rxr
->rx_prod
,
5560 rxr
->rx_agg_ring_struct
.fw_ring_id
, rxr
->rx_agg_prod
,
5561 rxr
->rx_sw_agg_prod
);
5564 static void bnxt_dump_cp_sw_state(struct bnxt_napi
*bnapi
)
5566 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
5567 int i
= bnapi
->index
;
5569 netdev_info(bnapi
->bp
->dev
, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
5570 i
, cpr
->cp_ring_struct
.fw_ring_id
, cpr
->cp_raw_cons
);
5573 static void bnxt_dbg_dump_states(struct bnxt
*bp
)
5576 struct bnxt_napi
*bnapi
;
5578 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
5579 bnapi
= bp
->bnapi
[i
];
5580 if (netif_msg_drv(bp
)) {
5581 bnxt_dump_tx_sw_state(bnapi
);
5582 bnxt_dump_rx_sw_state(bnapi
);
5583 bnxt_dump_cp_sw_state(bnapi
);
5588 static void bnxt_reset_task(struct bnxt
*bp
)
5590 bnxt_dbg_dump_states(bp
);
5591 if (netif_running(bp
->dev
)) {
5592 bnxt_close_nic(bp
, false, false);
5593 bnxt_open_nic(bp
, false, false);
5597 static void bnxt_tx_timeout(struct net_device
*dev
)
5599 struct bnxt
*bp
= netdev_priv(dev
);
5601 netdev_err(bp
->dev
, "TX timeout detected, starting reset task!\n");
5602 set_bit(BNXT_RESET_TASK_SP_EVENT
, &bp
->sp_event
);
5603 schedule_work(&bp
->sp_task
);
5606 #ifdef CONFIG_NET_POLL_CONTROLLER
5607 static void bnxt_poll_controller(struct net_device
*dev
)
5609 struct bnxt
*bp
= netdev_priv(dev
);
5612 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
5613 struct bnxt_irq
*irq
= &bp
->irq_tbl
[i
];
5615 disable_irq(irq
->vector
);
5616 irq
->handler(irq
->vector
, bp
->bnapi
[i
]);
5617 enable_irq(irq
->vector
);
5622 static void bnxt_timer(unsigned long data
)
5624 struct bnxt
*bp
= (struct bnxt
*)data
;
5625 struct net_device
*dev
= bp
->dev
;
5627 if (!netif_running(dev
))
5630 if (atomic_read(&bp
->intr_sem
) != 0)
5631 goto bnxt_restart_timer
;
5633 if (bp
->link_info
.link_up
&& (bp
->flags
& BNXT_FLAG_PORT_STATS
)) {
5634 set_bit(BNXT_PERIODIC_STATS_SP_EVENT
, &bp
->sp_event
);
5635 schedule_work(&bp
->sp_task
);
5638 mod_timer(&bp
->timer
, jiffies
+ bp
->current_interval
);
5641 static void bnxt_cfg_ntp_filters(struct bnxt
*);
5643 static void bnxt_sp_task(struct work_struct
*work
)
5645 struct bnxt
*bp
= container_of(work
, struct bnxt
, sp_task
);
5648 set_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
5649 smp_mb__after_atomic();
5650 if (!test_bit(BNXT_STATE_OPEN
, &bp
->state
)) {
5651 clear_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
5655 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT
, &bp
->sp_event
))
5656 bnxt_cfg_rx_mode(bp
);
5658 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT
, &bp
->sp_event
))
5659 bnxt_cfg_ntp_filters(bp
);
5660 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT
, &bp
->sp_event
)) {
5661 rc
= bnxt_update_link(bp
, true);
5663 netdev_err(bp
->dev
, "SP task can't update link (rc: %x)\n",
5666 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT
, &bp
->sp_event
))
5667 bnxt_hwrm_exec_fwd_req(bp
);
5668 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT
, &bp
->sp_event
)) {
5669 bnxt_hwrm_tunnel_dst_port_alloc(
5671 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
);
5673 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT
, &bp
->sp_event
)) {
5674 bnxt_hwrm_tunnel_dst_port_free(
5675 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
);
5677 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT
, &bp
->sp_event
)) {
5678 /* bnxt_reset_task() calls bnxt_close_nic() which waits
5679 * for BNXT_STATE_IN_SP_TASK to clear.
5681 clear_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
5683 bnxt_reset_task(bp
);
5684 set_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
5688 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT
, &bp
->sp_event
))
5689 bnxt_get_port_module_status(bp
);
5691 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT
, &bp
->sp_event
))
5692 bnxt_hwrm_port_qstats(bp
);
5694 smp_mb__before_atomic();
5695 clear_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
5698 static int bnxt_init_board(struct pci_dev
*pdev
, struct net_device
*dev
)
5701 struct bnxt
*bp
= netdev_priv(dev
);
5703 SET_NETDEV_DEV(dev
, &pdev
->dev
);
5705 /* enable device (incl. PCI PM wakeup), and bus-mastering */
5706 rc
= pci_enable_device(pdev
);
5708 dev_err(&pdev
->dev
, "Cannot enable PCI device, aborting\n");
5712 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
5714 "Cannot find PCI device base address, aborting\n");
5716 goto init_err_disable
;
5719 rc
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
5721 dev_err(&pdev
->dev
, "Cannot obtain PCI resources, aborting\n");
5722 goto init_err_disable
;
5725 if (dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(64)) != 0 &&
5726 dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(32)) != 0) {
5727 dev_err(&pdev
->dev
, "System does not support DMA, aborting\n");
5728 goto init_err_disable
;
5731 pci_set_master(pdev
);
5736 bp
->bar0
= pci_ioremap_bar(pdev
, 0);
5738 dev_err(&pdev
->dev
, "Cannot map device registers, aborting\n");
5740 goto init_err_release
;
5743 bp
->bar1
= pci_ioremap_bar(pdev
, 2);
5745 dev_err(&pdev
->dev
, "Cannot map doorbell registers, aborting\n");
5747 goto init_err_release
;
5750 bp
->bar2
= pci_ioremap_bar(pdev
, 4);
5752 dev_err(&pdev
->dev
, "Cannot map bar4 registers, aborting\n");
5754 goto init_err_release
;
5757 pci_enable_pcie_error_reporting(pdev
);
5759 INIT_WORK(&bp
->sp_task
, bnxt_sp_task
);
5761 spin_lock_init(&bp
->ntp_fltr_lock
);
5763 bp
->rx_ring_size
= BNXT_DEFAULT_RX_RING_SIZE
;
5764 bp
->tx_ring_size
= BNXT_DEFAULT_TX_RING_SIZE
;
5766 /* tick values in micro seconds */
5767 bp
->rx_coal_ticks
= 12;
5768 bp
->rx_coal_bufs
= 30;
5769 bp
->rx_coal_ticks_irq
= 1;
5770 bp
->rx_coal_bufs_irq
= 2;
5772 bp
->tx_coal_ticks
= 25;
5773 bp
->tx_coal_bufs
= 30;
5774 bp
->tx_coal_ticks_irq
= 2;
5775 bp
->tx_coal_bufs_irq
= 2;
5777 init_timer(&bp
->timer
);
5778 bp
->timer
.data
= (unsigned long)bp
;
5779 bp
->timer
.function
= bnxt_timer
;
5780 bp
->current_interval
= BNXT_TIMER_INTERVAL
;
5782 clear_bit(BNXT_STATE_OPEN
, &bp
->state
);
5788 pci_iounmap(pdev
, bp
->bar2
);
5793 pci_iounmap(pdev
, bp
->bar1
);
5798 pci_iounmap(pdev
, bp
->bar0
);
5802 pci_release_regions(pdev
);
5805 pci_disable_device(pdev
);
5811 /* rtnl_lock held */
5812 static int bnxt_change_mac_addr(struct net_device
*dev
, void *p
)
5814 struct sockaddr
*addr
= p
;
5815 struct bnxt
*bp
= netdev_priv(dev
);
5818 if (!is_valid_ether_addr(addr
->sa_data
))
5819 return -EADDRNOTAVAIL
;
5821 rc
= bnxt_approve_mac(bp
, addr
->sa_data
);
5825 if (ether_addr_equal(addr
->sa_data
, dev
->dev_addr
))
5828 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
5829 if (netif_running(dev
)) {
5830 bnxt_close_nic(bp
, false, false);
5831 rc
= bnxt_open_nic(bp
, false, false);
5837 /* rtnl_lock held */
5838 static int bnxt_change_mtu(struct net_device
*dev
, int new_mtu
)
5840 struct bnxt
*bp
= netdev_priv(dev
);
5842 if (new_mtu
< 60 || new_mtu
> 9000)
5845 if (netif_running(dev
))
5846 bnxt_close_nic(bp
, false, false);
5849 bnxt_set_ring_params(bp
);
5851 if (netif_running(dev
))
5852 return bnxt_open_nic(bp
, false, false);
5857 static int bnxt_setup_tc(struct net_device
*dev
, u32 handle
, __be16 proto
,
5858 struct tc_to_netdev
*ntc
)
5860 struct bnxt
*bp
= netdev_priv(dev
);
5863 if (ntc
->type
!= TC_SETUP_MQPRIO
)
5868 if (tc
> bp
->max_tc
) {
5869 netdev_err(dev
, "too many traffic classes requested: %d Max supported is %d\n",
5874 if (netdev_get_num_tc(dev
) == tc
)
5878 int max_rx_rings
, max_tx_rings
, rc
;
5881 if (bp
->flags
& BNXT_FLAG_SHARED_RINGS
)
5884 rc
= bnxt_get_max_rings(bp
, &max_rx_rings
, &max_tx_rings
, sh
);
5885 if (rc
|| bp
->tx_nr_rings_per_tc
* tc
> max_tx_rings
)
5889 /* Needs to close the device and do hw resource re-allocations */
5890 if (netif_running(bp
->dev
))
5891 bnxt_close_nic(bp
, true, false);
5894 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
* tc
;
5895 netdev_set_num_tc(dev
, tc
);
5897 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
;
5898 netdev_reset_tc(dev
);
5900 bp
->cp_nr_rings
= max_t(int, bp
->tx_nr_rings
, bp
->rx_nr_rings
);
5901 bp
->num_stat_ctxs
= bp
->cp_nr_rings
;
5903 if (netif_running(bp
->dev
))
5904 return bnxt_open_nic(bp
, true, false);
5909 #ifdef CONFIG_RFS_ACCEL
5910 static bool bnxt_fltr_match(struct bnxt_ntuple_filter
*f1
,
5911 struct bnxt_ntuple_filter
*f2
)
5913 struct flow_keys
*keys1
= &f1
->fkeys
;
5914 struct flow_keys
*keys2
= &f2
->fkeys
;
5916 if (keys1
->addrs
.v4addrs
.src
== keys2
->addrs
.v4addrs
.src
&&
5917 keys1
->addrs
.v4addrs
.dst
== keys2
->addrs
.v4addrs
.dst
&&
5918 keys1
->ports
.ports
== keys2
->ports
.ports
&&
5919 keys1
->basic
.ip_proto
== keys2
->basic
.ip_proto
&&
5920 keys1
->basic
.n_proto
== keys2
->basic
.n_proto
&&
5921 ether_addr_equal(f1
->src_mac_addr
, f2
->src_mac_addr
))
5927 static int bnxt_rx_flow_steer(struct net_device
*dev
, const struct sk_buff
*skb
,
5928 u16 rxq_index
, u32 flow_id
)
5930 struct bnxt
*bp
= netdev_priv(dev
);
5931 struct bnxt_ntuple_filter
*fltr
, *new_fltr
;
5932 struct flow_keys
*fkeys
;
5933 struct ethhdr
*eth
= (struct ethhdr
*)skb_mac_header(skb
);
5934 int rc
= 0, idx
, bit_id
;
5935 struct hlist_head
*head
;
5937 if (skb
->encapsulation
)
5938 return -EPROTONOSUPPORT
;
5940 new_fltr
= kzalloc(sizeof(*new_fltr
), GFP_ATOMIC
);
5944 fkeys
= &new_fltr
->fkeys
;
5945 if (!skb_flow_dissect_flow_keys(skb
, fkeys
, 0)) {
5946 rc
= -EPROTONOSUPPORT
;
5950 if ((fkeys
->basic
.n_proto
!= htons(ETH_P_IP
)) ||
5951 ((fkeys
->basic
.ip_proto
!= IPPROTO_TCP
) &&
5952 (fkeys
->basic
.ip_proto
!= IPPROTO_UDP
))) {
5953 rc
= -EPROTONOSUPPORT
;
5957 memcpy(new_fltr
->src_mac_addr
, eth
->h_source
, ETH_ALEN
);
5959 idx
= skb_get_hash_raw(skb
) & BNXT_NTP_FLTR_HASH_MASK
;
5960 head
= &bp
->ntp_fltr_hash_tbl
[idx
];
5962 hlist_for_each_entry_rcu(fltr
, head
, hash
) {
5963 if (bnxt_fltr_match(fltr
, new_fltr
)) {
5971 spin_lock_bh(&bp
->ntp_fltr_lock
);
5972 bit_id
= bitmap_find_free_region(bp
->ntp_fltr_bmap
,
5973 BNXT_NTP_FLTR_MAX_FLTR
, 0);
5975 spin_unlock_bh(&bp
->ntp_fltr_lock
);
5980 new_fltr
->sw_id
= (u16
)bit_id
;
5981 new_fltr
->flow_id
= flow_id
;
5982 new_fltr
->rxq
= rxq_index
;
5983 hlist_add_head_rcu(&new_fltr
->hash
, head
);
5984 bp
->ntp_fltr_count
++;
5985 spin_unlock_bh(&bp
->ntp_fltr_lock
);
5987 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT
, &bp
->sp_event
);
5988 schedule_work(&bp
->sp_task
);
5990 return new_fltr
->sw_id
;
5997 static void bnxt_cfg_ntp_filters(struct bnxt
*bp
)
6001 for (i
= 0; i
< BNXT_NTP_FLTR_HASH_SIZE
; i
++) {
6002 struct hlist_head
*head
;
6003 struct hlist_node
*tmp
;
6004 struct bnxt_ntuple_filter
*fltr
;
6007 head
= &bp
->ntp_fltr_hash_tbl
[i
];
6008 hlist_for_each_entry_safe(fltr
, tmp
, head
, hash
) {
6011 if (test_bit(BNXT_FLTR_VALID
, &fltr
->state
)) {
6012 if (rps_may_expire_flow(bp
->dev
, fltr
->rxq
,
6015 bnxt_hwrm_cfa_ntuple_filter_free(bp
,
6020 rc
= bnxt_hwrm_cfa_ntuple_filter_alloc(bp
,
6025 set_bit(BNXT_FLTR_VALID
, &fltr
->state
);
6029 spin_lock_bh(&bp
->ntp_fltr_lock
);
6030 hlist_del_rcu(&fltr
->hash
);
6031 bp
->ntp_fltr_count
--;
6032 spin_unlock_bh(&bp
->ntp_fltr_lock
);
6034 clear_bit(fltr
->sw_id
, bp
->ntp_fltr_bmap
);
6039 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT
, &bp
->sp_event
))
6040 netdev_info(bp
->dev
, "Receive PF driver unload event!");
6045 static void bnxt_cfg_ntp_filters(struct bnxt
*bp
)
6049 #endif /* CONFIG_RFS_ACCEL */
6051 static void bnxt_add_vxlan_port(struct net_device
*dev
, sa_family_t sa_family
,
6054 struct bnxt
*bp
= netdev_priv(dev
);
6056 if (!netif_running(dev
))
6059 if (sa_family
!= AF_INET6
&& sa_family
!= AF_INET
)
6062 if (bp
->vxlan_port_cnt
&& bp
->vxlan_port
!= port
)
6065 bp
->vxlan_port_cnt
++;
6066 if (bp
->vxlan_port_cnt
== 1) {
6067 bp
->vxlan_port
= port
;
6068 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT
, &bp
->sp_event
);
6069 schedule_work(&bp
->sp_task
);
6073 static void bnxt_del_vxlan_port(struct net_device
*dev
, sa_family_t sa_family
,
6076 struct bnxt
*bp
= netdev_priv(dev
);
6078 if (!netif_running(dev
))
6081 if (sa_family
!= AF_INET6
&& sa_family
!= AF_INET
)
6084 if (bp
->vxlan_port_cnt
&& bp
->vxlan_port
== port
) {
6085 bp
->vxlan_port_cnt
--;
6087 if (bp
->vxlan_port_cnt
== 0) {
6088 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT
, &bp
->sp_event
);
6089 schedule_work(&bp
->sp_task
);
6094 static const struct net_device_ops bnxt_netdev_ops
= {
6095 .ndo_open
= bnxt_open
,
6096 .ndo_start_xmit
= bnxt_start_xmit
,
6097 .ndo_stop
= bnxt_close
,
6098 .ndo_get_stats64
= bnxt_get_stats64
,
6099 .ndo_set_rx_mode
= bnxt_set_rx_mode
,
6100 .ndo_do_ioctl
= bnxt_ioctl
,
6101 .ndo_validate_addr
= eth_validate_addr
,
6102 .ndo_set_mac_address
= bnxt_change_mac_addr
,
6103 .ndo_change_mtu
= bnxt_change_mtu
,
6104 .ndo_fix_features
= bnxt_fix_features
,
6105 .ndo_set_features
= bnxt_set_features
,
6106 .ndo_tx_timeout
= bnxt_tx_timeout
,
6107 #ifdef CONFIG_BNXT_SRIOV
6108 .ndo_get_vf_config
= bnxt_get_vf_config
,
6109 .ndo_set_vf_mac
= bnxt_set_vf_mac
,
6110 .ndo_set_vf_vlan
= bnxt_set_vf_vlan
,
6111 .ndo_set_vf_rate
= bnxt_set_vf_bw
,
6112 .ndo_set_vf_link_state
= bnxt_set_vf_link_state
,
6113 .ndo_set_vf_spoofchk
= bnxt_set_vf_spoofchk
,
6115 #ifdef CONFIG_NET_POLL_CONTROLLER
6116 .ndo_poll_controller
= bnxt_poll_controller
,
6118 .ndo_setup_tc
= bnxt_setup_tc
,
6119 #ifdef CONFIG_RFS_ACCEL
6120 .ndo_rx_flow_steer
= bnxt_rx_flow_steer
,
6122 .ndo_add_vxlan_port
= bnxt_add_vxlan_port
,
6123 .ndo_del_vxlan_port
= bnxt_del_vxlan_port
,
6124 #ifdef CONFIG_NET_RX_BUSY_POLL
6125 .ndo_busy_poll
= bnxt_busy_poll
,
6129 static void bnxt_remove_one(struct pci_dev
*pdev
)
6131 struct net_device
*dev
= pci_get_drvdata(pdev
);
6132 struct bnxt
*bp
= netdev_priv(dev
);
6135 bnxt_sriov_disable(bp
);
6137 pci_disable_pcie_error_reporting(pdev
);
6138 unregister_netdev(dev
);
6139 cancel_work_sync(&bp
->sp_task
);
6142 bnxt_hwrm_func_drv_unrgtr(bp
);
6143 bnxt_free_hwrm_resources(bp
);
6144 pci_iounmap(pdev
, bp
->bar2
);
6145 pci_iounmap(pdev
, bp
->bar1
);
6146 pci_iounmap(pdev
, bp
->bar0
);
6149 pci_release_regions(pdev
);
6150 pci_disable_device(pdev
);
6153 static int bnxt_probe_phy(struct bnxt
*bp
)
6156 struct bnxt_link_info
*link_info
= &bp
->link_info
;
6158 rc
= bnxt_hwrm_phy_qcaps(bp
);
6160 netdev_err(bp
->dev
, "Probe phy can't get phy capabilities (rc: %x)\n",
6165 rc
= bnxt_update_link(bp
, false);
6167 netdev_err(bp
->dev
, "Probe phy can't update link (rc: %x)\n",
6172 /*initialize the ethool setting copy with NVM settings */
6173 if (BNXT_AUTO_MODE(link_info
->auto_mode
)) {
6174 link_info
->autoneg
= BNXT_AUTONEG_SPEED
;
6175 if (bp
->hwrm_spec_code
>= 0x10201) {
6176 if (link_info
->auto_pause_setting
&
6177 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE
)
6178 link_info
->autoneg
|= BNXT_AUTONEG_FLOW_CTRL
;
6180 link_info
->autoneg
|= BNXT_AUTONEG_FLOW_CTRL
;
6182 link_info
->advertising
= link_info
->auto_link_speeds
;
6184 link_info
->req_link_speed
= link_info
->force_link_speed
;
6185 link_info
->req_duplex
= link_info
->duplex_setting
;
6187 if (link_info
->autoneg
& BNXT_AUTONEG_FLOW_CTRL
)
6188 link_info
->req_flow_ctrl
=
6189 link_info
->auto_pause_setting
& BNXT_LINK_PAUSE_BOTH
;
6191 link_info
->req_flow_ctrl
= link_info
->force_pause_setting
;
6195 static int bnxt_get_max_irq(struct pci_dev
*pdev
)
6199 if (!pdev
->msix_cap
)
6202 pci_read_config_word(pdev
, pdev
->msix_cap
+ PCI_MSIX_FLAGS
, &ctrl
);
6203 return (ctrl
& PCI_MSIX_FLAGS_QSIZE
) + 1;
6206 static void _bnxt_get_max_rings(struct bnxt
*bp
, int *max_rx
, int *max_tx
,
6209 int max_ring_grps
= 0;
6211 #ifdef CONFIG_BNXT_SRIOV
6213 *max_tx
= bp
->vf
.max_tx_rings
;
6214 *max_rx
= bp
->vf
.max_rx_rings
;
6215 *max_cp
= min_t(int, bp
->vf
.max_irqs
, bp
->vf
.max_cp_rings
);
6216 *max_cp
= min_t(int, *max_cp
, bp
->vf
.max_stat_ctxs
);
6217 max_ring_grps
= bp
->vf
.max_hw_ring_grps
;
6221 *max_tx
= bp
->pf
.max_tx_rings
;
6222 *max_rx
= bp
->pf
.max_rx_rings
;
6223 *max_cp
= min_t(int, bp
->pf
.max_irqs
, bp
->pf
.max_cp_rings
);
6224 *max_cp
= min_t(int, *max_cp
, bp
->pf
.max_stat_ctxs
);
6225 max_ring_grps
= bp
->pf
.max_hw_ring_grps
;
6228 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
)
6230 *max_rx
= min_t(int, *max_rx
, max_ring_grps
);
6233 int bnxt_get_max_rings(struct bnxt
*bp
, int *max_rx
, int *max_tx
, bool shared
)
6237 _bnxt_get_max_rings(bp
, &rx
, &tx
, &cp
);
6238 if (!rx
|| !tx
|| !cp
)
6243 return bnxt_trim_rings(bp
, max_rx
, max_tx
, cp
, shared
);
6246 static int bnxt_set_dflt_rings(struct bnxt
*bp
)
6248 int dflt_rings
, max_rx_rings
, max_tx_rings
, rc
;
6252 bp
->flags
|= BNXT_FLAG_SHARED_RINGS
;
6253 dflt_rings
= netif_get_num_default_rss_queues();
6254 rc
= bnxt_get_max_rings(bp
, &max_rx_rings
, &max_tx_rings
, sh
);
6257 bp
->rx_nr_rings
= min_t(int, dflt_rings
, max_rx_rings
);
6258 bp
->tx_nr_rings_per_tc
= min_t(int, dflt_rings
, max_tx_rings
);
6259 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
;
6260 bp
->cp_nr_rings
= sh
? max_t(int, bp
->tx_nr_rings
, bp
->rx_nr_rings
) :
6261 bp
->tx_nr_rings
+ bp
->rx_nr_rings
;
6262 bp
->num_stat_ctxs
= bp
->cp_nr_rings
;
6266 static void bnxt_parse_log_pcie_link(struct bnxt
*bp
)
6268 enum pcie_link_width width
= PCIE_LNK_WIDTH_UNKNOWN
;
6269 enum pci_bus_speed speed
= PCI_SPEED_UNKNOWN
;
6271 if (pcie_get_minimum_link(bp
->pdev
, &speed
, &width
) ||
6272 speed
== PCI_SPEED_UNKNOWN
|| width
== PCIE_LNK_WIDTH_UNKNOWN
)
6273 netdev_info(bp
->dev
, "Failed to determine PCIe Link Info\n");
6275 netdev_info(bp
->dev
, "PCIe: Speed %s Width x%d\n",
6276 speed
== PCIE_SPEED_2_5GT
? "2.5GT/s" :
6277 speed
== PCIE_SPEED_5_0GT
? "5.0GT/s" :
6278 speed
== PCIE_SPEED_8_0GT
? "8.0GT/s" :
6282 static int bnxt_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
6284 static int version_printed
;
6285 struct net_device
*dev
;
6289 if (version_printed
++ == 0)
6290 pr_info("%s", version
);
6292 max_irqs
= bnxt_get_max_irq(pdev
);
6293 dev
= alloc_etherdev_mq(sizeof(*bp
), max_irqs
);
6297 bp
= netdev_priv(dev
);
6299 if (bnxt_vf_pciid(ent
->driver_data
))
6300 bp
->flags
|= BNXT_FLAG_VF
;
6303 bp
->flags
|= BNXT_FLAG_MSIX_CAP
;
6305 rc
= bnxt_init_board(pdev
, dev
);
6309 dev
->netdev_ops
= &bnxt_netdev_ops
;
6310 dev
->watchdog_timeo
= BNXT_TX_TIMEOUT
;
6311 dev
->ethtool_ops
= &bnxt_ethtool_ops
;
6313 pci_set_drvdata(pdev
, dev
);
6315 dev
->hw_features
= NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
| NETIF_F_SG
|
6316 NETIF_F_TSO
| NETIF_F_TSO6
|
6317 NETIF_F_GSO_UDP_TUNNEL
| NETIF_F_GSO_GRE
|
6318 NETIF_F_GSO_IPXIP4
|
6319 NETIF_F_GSO_UDP_TUNNEL_CSUM
| NETIF_F_GSO_GRE_CSUM
|
6320 NETIF_F_GSO_PARTIAL
| NETIF_F_RXHASH
|
6321 NETIF_F_RXCSUM
| NETIF_F_LRO
| NETIF_F_GRO
;
6323 dev
->hw_enc_features
=
6324 NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
| NETIF_F_SG
|
6325 NETIF_F_TSO
| NETIF_F_TSO6
|
6326 NETIF_F_GSO_UDP_TUNNEL
| NETIF_F_GSO_GRE
|
6327 NETIF_F_GSO_UDP_TUNNEL_CSUM
| NETIF_F_GSO_GRE_CSUM
|
6328 NETIF_F_GSO_IPXIP4
| NETIF_F_GSO_PARTIAL
;
6329 dev
->gso_partial_features
= NETIF_F_GSO_UDP_TUNNEL_CSUM
|
6330 NETIF_F_GSO_GRE_CSUM
;
6331 dev
->vlan_features
= dev
->hw_features
| NETIF_F_HIGHDMA
;
6332 dev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_RX
| NETIF_F_HW_VLAN_CTAG_TX
|
6333 NETIF_F_HW_VLAN_STAG_RX
| NETIF_F_HW_VLAN_STAG_TX
;
6334 dev
->features
|= dev
->hw_features
| NETIF_F_HIGHDMA
;
6335 dev
->priv_flags
|= IFF_UNICAST_FLT
;
6337 #ifdef CONFIG_BNXT_SRIOV
6338 init_waitqueue_head(&bp
->sriov_cfg_wait
);
6340 rc
= bnxt_alloc_hwrm_resources(bp
);
6344 mutex_init(&bp
->hwrm_cmd_lock
);
6345 bnxt_hwrm_ver_get(bp
);
6347 rc
= bnxt_hwrm_func_drv_rgtr(bp
);
6351 /* Get the MAX capabilities for this function */
6352 rc
= bnxt_hwrm_func_qcaps(bp
);
6354 netdev_err(bp
->dev
, "hwrm query capability failure rc: %x\n",
6360 rc
= bnxt_hwrm_queue_qportcfg(bp
);
6362 netdev_err(bp
->dev
, "hwrm query qportcfg failure rc: %x\n",
6368 bnxt_set_tpa_flags(bp
);
6369 bnxt_set_ring_params(bp
);
6371 bp
->pf
.max_irqs
= max_irqs
;
6372 #if defined(CONFIG_BNXT_SRIOV)
6374 bp
->vf
.max_irqs
= max_irqs
;
6376 bnxt_set_dflt_rings(bp
);
6379 dev
->hw_features
|= NETIF_F_NTUPLE
;
6380 if (bnxt_rfs_capable(bp
)) {
6381 bp
->flags
|= BNXT_FLAG_RFS
;
6382 dev
->features
|= NETIF_F_NTUPLE
;
6386 if (dev
->hw_features
& NETIF_F_HW_VLAN_CTAG_RX
)
6387 bp
->flags
|= BNXT_FLAG_STRIP_VLAN
;
6389 rc
= bnxt_probe_phy(bp
);
6393 rc
= register_netdev(dev
);
6397 netdev_info(dev
, "%s found at mem %lx, node addr %pM\n",
6398 board_info
[ent
->driver_data
].name
,
6399 (long)pci_resource_start(pdev
, 0), dev
->dev_addr
);
6401 bnxt_parse_log_pcie_link(bp
);
6406 pci_iounmap(pdev
, bp
->bar0
);
6407 pci_release_regions(pdev
);
6408 pci_disable_device(pdev
);
6416 * bnxt_io_error_detected - called when PCI error is detected
6417 * @pdev: Pointer to PCI device
6418 * @state: The current pci connection state
6420 * This function is called after a PCI bus error affecting
6421 * this device has been detected.
6423 static pci_ers_result_t
bnxt_io_error_detected(struct pci_dev
*pdev
,
6424 pci_channel_state_t state
)
6426 struct net_device
*netdev
= pci_get_drvdata(pdev
);
6428 netdev_info(netdev
, "PCI I/O error detected\n");
6431 netif_device_detach(netdev
);
6433 if (state
== pci_channel_io_perm_failure
) {
6435 return PCI_ERS_RESULT_DISCONNECT
;
6438 if (netif_running(netdev
))
6441 pci_disable_device(pdev
);
6444 /* Request a slot slot reset. */
6445 return PCI_ERS_RESULT_NEED_RESET
;
6449 * bnxt_io_slot_reset - called after the pci bus has been reset.
6450 * @pdev: Pointer to PCI device
6452 * Restart the card from scratch, as if from a cold-boot.
6453 * At this point, the card has exprienced a hard reset,
6454 * followed by fixups by BIOS, and has its config space
6455 * set up identically to what it was at cold boot.
6457 static pci_ers_result_t
bnxt_io_slot_reset(struct pci_dev
*pdev
)
6459 struct net_device
*netdev
= pci_get_drvdata(pdev
);
6460 struct bnxt
*bp
= netdev_priv(netdev
);
6462 pci_ers_result_t result
= PCI_ERS_RESULT_DISCONNECT
;
6464 netdev_info(bp
->dev
, "PCI Slot Reset\n");
6468 if (pci_enable_device(pdev
)) {
6470 "Cannot re-enable PCI device after reset.\n");
6472 pci_set_master(pdev
);
6474 if (netif_running(netdev
))
6475 err
= bnxt_open(netdev
);
6478 result
= PCI_ERS_RESULT_RECOVERED
;
6481 if (result
!= PCI_ERS_RESULT_RECOVERED
&& netif_running(netdev
))
6486 err
= pci_cleanup_aer_uncorrect_error_status(pdev
);
6489 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
6490 err
); /* non-fatal, continue */
6493 return PCI_ERS_RESULT_RECOVERED
;
6497 * bnxt_io_resume - called when traffic can start flowing again.
6498 * @pdev: Pointer to PCI device
6500 * This callback is called when the error recovery driver tells
6501 * us that its OK to resume normal operation.
6503 static void bnxt_io_resume(struct pci_dev
*pdev
)
6505 struct net_device
*netdev
= pci_get_drvdata(pdev
);
6509 netif_device_attach(netdev
);
6514 static const struct pci_error_handlers bnxt_err_handler
= {
6515 .error_detected
= bnxt_io_error_detected
,
6516 .slot_reset
= bnxt_io_slot_reset
,
6517 .resume
= bnxt_io_resume
6520 static struct pci_driver bnxt_pci_driver
= {
6521 .name
= DRV_MODULE_NAME
,
6522 .id_table
= bnxt_pci_tbl
,
6523 .probe
= bnxt_init_one
,
6524 .remove
= bnxt_remove_one
,
6525 .err_handler
= &bnxt_err_handler
,
6526 #if defined(CONFIG_BNXT_SRIOV)
6527 .sriov_configure
= bnxt_sriov_configure
,
6531 module_pci_driver(bnxt_pci_driver
);