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Merge tag 'riscv-for-linus-5.14-rc6' of git://git.kernel.org/pub/scm/linux/kernel...
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / broadcom / bnxt / bnxt.c
1 /* Broadcom NetXtreme-C/E network driver.
2 *
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2019 Broadcom Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
9 */
10
11 #include <linux/module.h>
12
13 #include <linux/stringify.h>
14 #include <linux/kernel.h>
15 #include <linux/timer.h>
16 #include <linux/errno.h>
17 #include <linux/ioport.h>
18 #include <linux/slab.h>
19 #include <linux/vmalloc.h>
20 #include <linux/interrupt.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
23 #include <linux/etherdevice.h>
24 #include <linux/skbuff.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/bitops.h>
27 #include <linux/io.h>
28 #include <linux/irq.h>
29 #include <linux/delay.h>
30 #include <asm/byteorder.h>
31 #include <asm/page.h>
32 #include <linux/time.h>
33 #include <linux/mii.h>
34 #include <linux/mdio.h>
35 #include <linux/if.h>
36 #include <linux/if_vlan.h>
37 #include <linux/if_bridge.h>
38 #include <linux/rtc.h>
39 #include <linux/bpf.h>
40 #include <net/ip.h>
41 #include <net/tcp.h>
42 #include <net/udp.h>
43 #include <net/checksum.h>
44 #include <net/ip6_checksum.h>
45 #include <net/udp_tunnel.h>
46 #include <linux/workqueue.h>
47 #include <linux/prefetch.h>
48 #include <linux/cache.h>
49 #include <linux/log2.h>
50 #include <linux/aer.h>
51 #include <linux/bitmap.h>
52 #include <linux/ptp_clock_kernel.h>
53 #include <linux/timecounter.h>
54 #include <linux/cpu_rmap.h>
55 #include <linux/cpumask.h>
56 #include <net/pkt_cls.h>
57 #include <linux/hwmon.h>
58 #include <linux/hwmon-sysfs.h>
59 #include <net/page_pool.h>
60
61 #include "bnxt_hsi.h"
62 #include "bnxt.h"
63 #include "bnxt_ulp.h"
64 #include "bnxt_sriov.h"
65 #include "bnxt_ethtool.h"
66 #include "bnxt_dcb.h"
67 #include "bnxt_xdp.h"
68 #include "bnxt_ptp.h"
69 #include "bnxt_vfr.h"
70 #include "bnxt_tc.h"
71 #include "bnxt_devlink.h"
72 #include "bnxt_debugfs.h"
73
74 #define BNXT_TX_TIMEOUT (5 * HZ)
75 #define BNXT_DEF_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_HW)
76
77 MODULE_LICENSE("GPL");
78 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
79
80 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
81 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
82 #define BNXT_RX_COPY_THRESH 256
83
84 #define BNXT_TX_PUSH_THRESH 164
85
86 enum board_idx {
87 BCM57301,
88 BCM57302,
89 BCM57304,
90 BCM57417_NPAR,
91 BCM58700,
92 BCM57311,
93 BCM57312,
94 BCM57402,
95 BCM57404,
96 BCM57406,
97 BCM57402_NPAR,
98 BCM57407,
99 BCM57412,
100 BCM57414,
101 BCM57416,
102 BCM57417,
103 BCM57412_NPAR,
104 BCM57314,
105 BCM57417_SFP,
106 BCM57416_SFP,
107 BCM57404_NPAR,
108 BCM57406_NPAR,
109 BCM57407_SFP,
110 BCM57407_NPAR,
111 BCM57414_NPAR,
112 BCM57416_NPAR,
113 BCM57452,
114 BCM57454,
115 BCM5745x_NPAR,
116 BCM57508,
117 BCM57504,
118 BCM57502,
119 BCM57508_NPAR,
120 BCM57504_NPAR,
121 BCM57502_NPAR,
122 BCM58802,
123 BCM58804,
124 BCM58808,
125 NETXTREME_E_VF,
126 NETXTREME_C_VF,
127 NETXTREME_S_VF,
128 NETXTREME_C_VF_HV,
129 NETXTREME_E_VF_HV,
130 NETXTREME_E_P5_VF,
131 NETXTREME_E_P5_VF_HV,
132 };
133
134 /* indexed by enum above */
135 static const struct {
136 char *name;
137 } board_info[] = {
138 [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
139 [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
140 [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
141 [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
142 [BCM58700] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
143 [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
144 [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
145 [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
146 [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
147 [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
148 [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
149 [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
150 [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
151 [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
152 [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
153 [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
154 [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
155 [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
156 [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
157 [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
158 [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
159 [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
160 [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
161 [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
162 [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
163 [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
164 [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" },
165 [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
166 [BCM5745x_NPAR] = { "Broadcom BCM5745x NetXtreme-E Ethernet Partition" },
167 [BCM57508] = { "Broadcom BCM57508 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" },
168 [BCM57504] = { "Broadcom BCM57504 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" },
169 [BCM57502] = { "Broadcom BCM57502 NetXtreme-E 10Gb/25Gb/50Gb Ethernet" },
170 [BCM57508_NPAR] = { "Broadcom BCM57508 NetXtreme-E Ethernet Partition" },
171 [BCM57504_NPAR] = { "Broadcom BCM57504 NetXtreme-E Ethernet Partition" },
172 [BCM57502_NPAR] = { "Broadcom BCM57502 NetXtreme-E Ethernet Partition" },
173 [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" },
174 [BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
175 [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
176 [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" },
177 [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" },
178 [NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" },
179 [NETXTREME_C_VF_HV] = { "Broadcom NetXtreme-C Virtual Function for Hyper-V" },
180 [NETXTREME_E_VF_HV] = { "Broadcom NetXtreme-E Virtual Function for Hyper-V" },
181 [NETXTREME_E_P5_VF] = { "Broadcom BCM5750X NetXtreme-E Ethernet Virtual Function" },
182 [NETXTREME_E_P5_VF_HV] = { "Broadcom BCM5750X NetXtreme-E Virtual Function for Hyper-V" },
183 };
184
185 static const struct pci_device_id bnxt_pci_tbl[] = {
186 { PCI_VDEVICE(BROADCOM, 0x1604), .driver_data = BCM5745x_NPAR },
187 { PCI_VDEVICE(BROADCOM, 0x1605), .driver_data = BCM5745x_NPAR },
188 { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 },
189 { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR },
190 { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
191 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
192 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
193 { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR },
194 { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 },
195 { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 },
196 { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 },
197 { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
198 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
199 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
200 { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR },
201 { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 },
202 { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 },
203 { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 },
204 { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 },
205 { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 },
206 { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR },
207 { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
208 { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP },
209 { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP },
210 { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR },
211 { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR },
212 { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP },
213 { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR },
214 { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR },
215 { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR },
216 { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR },
217 { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR },
218 { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR },
219 { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 },
220 { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 },
221 { PCI_VDEVICE(BROADCOM, 0x1750), .driver_data = BCM57508 },
222 { PCI_VDEVICE(BROADCOM, 0x1751), .driver_data = BCM57504 },
223 { PCI_VDEVICE(BROADCOM, 0x1752), .driver_data = BCM57502 },
224 { PCI_VDEVICE(BROADCOM, 0x1800), .driver_data = BCM57508_NPAR },
225 { PCI_VDEVICE(BROADCOM, 0x1801), .driver_data = BCM57504_NPAR },
226 { PCI_VDEVICE(BROADCOM, 0x1802), .driver_data = BCM57502_NPAR },
227 { PCI_VDEVICE(BROADCOM, 0x1803), .driver_data = BCM57508_NPAR },
228 { PCI_VDEVICE(BROADCOM, 0x1804), .driver_data = BCM57504_NPAR },
229 { PCI_VDEVICE(BROADCOM, 0x1805), .driver_data = BCM57502_NPAR },
230 { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 },
231 { PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 },
232 #ifdef CONFIG_BNXT_SRIOV
233 { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF },
234 { PCI_VDEVICE(BROADCOM, 0x1607), .driver_data = NETXTREME_E_VF_HV },
235 { PCI_VDEVICE(BROADCOM, 0x1608), .driver_data = NETXTREME_E_VF_HV },
236 { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF },
237 { PCI_VDEVICE(BROADCOM, 0x16bd), .driver_data = NETXTREME_E_VF_HV },
238 { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF },
239 { PCI_VDEVICE(BROADCOM, 0x16c2), .driver_data = NETXTREME_C_VF_HV },
240 { PCI_VDEVICE(BROADCOM, 0x16c3), .driver_data = NETXTREME_C_VF_HV },
241 { PCI_VDEVICE(BROADCOM, 0x16c4), .driver_data = NETXTREME_E_VF_HV },
242 { PCI_VDEVICE(BROADCOM, 0x16c5), .driver_data = NETXTREME_E_VF_HV },
243 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF },
244 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF },
245 { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF },
246 { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF },
247 { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF },
248 { PCI_VDEVICE(BROADCOM, 0x16e6), .driver_data = NETXTREME_C_VF_HV },
249 { PCI_VDEVICE(BROADCOM, 0x1806), .driver_data = NETXTREME_E_P5_VF },
250 { PCI_VDEVICE(BROADCOM, 0x1807), .driver_data = NETXTREME_E_P5_VF },
251 { PCI_VDEVICE(BROADCOM, 0x1808), .driver_data = NETXTREME_E_P5_VF_HV },
252 { PCI_VDEVICE(BROADCOM, 0x1809), .driver_data = NETXTREME_E_P5_VF_HV },
253 { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF },
254 #endif
255 { 0 }
256 };
257
258 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
259
260 static const u16 bnxt_vf_req_snif[] = {
261 HWRM_FUNC_CFG,
262 HWRM_FUNC_VF_CFG,
263 HWRM_PORT_PHY_QCFG,
264 HWRM_CFA_L2_FILTER_ALLOC,
265 };
266
267 static const u16 bnxt_async_events_arr[] = {
268 ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
269 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE,
270 ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
271 ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
272 ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
273 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
274 ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE,
275 ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY,
276 ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY,
277 ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION,
278 ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG,
279 ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST,
280 };
281
282 static struct workqueue_struct *bnxt_pf_wq;
283
284 static bool bnxt_vf_pciid(enum board_idx idx)
285 {
286 return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF ||
287 idx == NETXTREME_S_VF || idx == NETXTREME_C_VF_HV ||
288 idx == NETXTREME_E_VF_HV || idx == NETXTREME_E_P5_VF ||
289 idx == NETXTREME_E_P5_VF_HV);
290 }
291
292 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
293 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
294 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
295
296 #define BNXT_CP_DB_IRQ_DIS(db) \
297 writel(DB_CP_IRQ_DIS_FLAGS, db)
298
299 #define BNXT_DB_CQ(db, idx) \
300 writel(DB_CP_FLAGS | RING_CMP(idx), (db)->doorbell)
301
302 #define BNXT_DB_NQ_P5(db, idx) \
303 writeq((db)->db_key64 | DBR_TYPE_NQ | RING_CMP(idx), (db)->doorbell)
304
305 #define BNXT_DB_CQ_ARM(db, idx) \
306 writel(DB_CP_REARM_FLAGS | RING_CMP(idx), (db)->doorbell)
307
308 #define BNXT_DB_NQ_ARM_P5(db, idx) \
309 writeq((db)->db_key64 | DBR_TYPE_NQ_ARM | RING_CMP(idx), (db)->doorbell)
310
311 static void bnxt_db_nq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
312 {
313 if (bp->flags & BNXT_FLAG_CHIP_P5)
314 BNXT_DB_NQ_P5(db, idx);
315 else
316 BNXT_DB_CQ(db, idx);
317 }
318
319 static void bnxt_db_nq_arm(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
320 {
321 if (bp->flags & BNXT_FLAG_CHIP_P5)
322 BNXT_DB_NQ_ARM_P5(db, idx);
323 else
324 BNXT_DB_CQ_ARM(db, idx);
325 }
326
327 static void bnxt_db_cq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
328 {
329 if (bp->flags & BNXT_FLAG_CHIP_P5)
330 writeq(db->db_key64 | DBR_TYPE_CQ_ARMALL | RING_CMP(idx),
331 db->doorbell);
332 else
333 BNXT_DB_CQ(db, idx);
334 }
335
336 const u16 bnxt_lhint_arr[] = {
337 TX_BD_FLAGS_LHINT_512_AND_SMALLER,
338 TX_BD_FLAGS_LHINT_512_TO_1023,
339 TX_BD_FLAGS_LHINT_1024_TO_2047,
340 TX_BD_FLAGS_LHINT_1024_TO_2047,
341 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
342 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
343 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
344 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
345 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
346 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
347 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
348 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
349 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
350 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
351 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
352 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
353 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
354 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
355 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
356 };
357
358 static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb)
359 {
360 struct metadata_dst *md_dst = skb_metadata_dst(skb);
361
362 if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX)
363 return 0;
364
365 return md_dst->u.port_info.port_id;
366 }
367
368 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
369 {
370 struct bnxt *bp = netdev_priv(dev);
371 struct tx_bd *txbd;
372 struct tx_bd_ext *txbd1;
373 struct netdev_queue *txq;
374 int i;
375 dma_addr_t mapping;
376 unsigned int length, pad = 0;
377 u32 len, free_size, vlan_tag_flags, cfa_action, flags;
378 u16 prod, last_frag;
379 struct pci_dev *pdev = bp->pdev;
380 struct bnxt_tx_ring_info *txr;
381 struct bnxt_sw_tx_bd *tx_buf;
382 __le32 lflags = 0;
383
384 i = skb_get_queue_mapping(skb);
385 if (unlikely(i >= bp->tx_nr_rings)) {
386 dev_kfree_skb_any(skb);
387 return NETDEV_TX_OK;
388 }
389
390 txq = netdev_get_tx_queue(dev, i);
391 txr = &bp->tx_ring[bp->tx_ring_map[i]];
392 prod = txr->tx_prod;
393
394 free_size = bnxt_tx_avail(bp, txr);
395 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
396 netif_tx_stop_queue(txq);
397 return NETDEV_TX_BUSY;
398 }
399
400 length = skb->len;
401 len = skb_headlen(skb);
402 last_frag = skb_shinfo(skb)->nr_frags;
403
404 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
405
406 txbd->tx_bd_opaque = prod;
407
408 tx_buf = &txr->tx_buf_ring[prod];
409 tx_buf->skb = skb;
410 tx_buf->nr_frags = last_frag;
411
412 vlan_tag_flags = 0;
413 cfa_action = bnxt_xmit_get_cfa_action(skb);
414 if (skb_vlan_tag_present(skb)) {
415 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
416 skb_vlan_tag_get(skb);
417 /* Currently supports 8021Q, 8021AD vlan offloads
418 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
419 */
420 if (skb->vlan_proto == htons(ETH_P_8021Q))
421 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
422 }
423
424 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
425 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
426
427 if (ptp && ptp->tx_tstamp_en && !skb_is_gso(skb) &&
428 atomic_dec_if_positive(&ptp->tx_avail) >= 0) {
429 if (!bnxt_ptp_parse(skb, &ptp->tx_seqid,
430 &ptp->tx_hdr_off)) {
431 if (vlan_tag_flags)
432 ptp->tx_hdr_off += VLAN_HLEN;
433 lflags |= cpu_to_le32(TX_BD_FLAGS_STAMP);
434 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
435 } else {
436 atomic_inc(&bp->ptp_cfg->tx_avail);
437 }
438 }
439 }
440
441 if (unlikely(skb->no_fcs))
442 lflags |= cpu_to_le32(TX_BD_FLAGS_NO_CRC);
443
444 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh &&
445 !lflags) {
446 struct tx_push_buffer *tx_push_buf = txr->tx_push;
447 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
448 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
449 void __iomem *db = txr->tx_db.doorbell;
450 void *pdata = tx_push_buf->data;
451 u64 *end;
452 int j, push_len;
453
454 /* Set COAL_NOW to be ready quickly for the next push */
455 tx_push->tx_bd_len_flags_type =
456 cpu_to_le32((length << TX_BD_LEN_SHIFT) |
457 TX_BD_TYPE_LONG_TX_BD |
458 TX_BD_FLAGS_LHINT_512_AND_SMALLER |
459 TX_BD_FLAGS_COAL_NOW |
460 TX_BD_FLAGS_PACKET_END |
461 (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
462
463 if (skb->ip_summed == CHECKSUM_PARTIAL)
464 tx_push1->tx_bd_hsize_lflags =
465 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
466 else
467 tx_push1->tx_bd_hsize_lflags = 0;
468
469 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
470 tx_push1->tx_bd_cfa_action =
471 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
472
473 end = pdata + length;
474 end = PTR_ALIGN(end, 8) - 1;
475 *end = 0;
476
477 skb_copy_from_linear_data(skb, pdata, len);
478 pdata += len;
479 for (j = 0; j < last_frag; j++) {
480 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
481 void *fptr;
482
483 fptr = skb_frag_address_safe(frag);
484 if (!fptr)
485 goto normal_tx;
486
487 memcpy(pdata, fptr, skb_frag_size(frag));
488 pdata += skb_frag_size(frag);
489 }
490
491 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
492 txbd->tx_bd_haddr = txr->data_mapping;
493 prod = NEXT_TX(prod);
494 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
495 memcpy(txbd, tx_push1, sizeof(*txbd));
496 prod = NEXT_TX(prod);
497 tx_push->doorbell =
498 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
499 txr->tx_prod = prod;
500
501 tx_buf->is_push = 1;
502 netdev_tx_sent_queue(txq, skb->len);
503 wmb(); /* Sync is_push and byte queue before pushing data */
504
505 push_len = (length + sizeof(*tx_push) + 7) / 8;
506 if (push_len > 16) {
507 __iowrite64_copy(db, tx_push_buf, 16);
508 __iowrite32_copy(db + 4, tx_push_buf + 1,
509 (push_len - 16) << 1);
510 } else {
511 __iowrite64_copy(db, tx_push_buf, push_len);
512 }
513
514 goto tx_done;
515 }
516
517 normal_tx:
518 if (length < BNXT_MIN_PKT_SIZE) {
519 pad = BNXT_MIN_PKT_SIZE - length;
520 if (skb_pad(skb, pad)) {
521 /* SKB already freed. */
522 tx_buf->skb = NULL;
523 return NETDEV_TX_OK;
524 }
525 length = BNXT_MIN_PKT_SIZE;
526 }
527
528 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
529
530 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
531 dev_kfree_skb_any(skb);
532 tx_buf->skb = NULL;
533 return NETDEV_TX_OK;
534 }
535
536 dma_unmap_addr_set(tx_buf, mapping, mapping);
537 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
538 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
539
540 txbd->tx_bd_haddr = cpu_to_le64(mapping);
541
542 prod = NEXT_TX(prod);
543 txbd1 = (struct tx_bd_ext *)
544 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
545
546 txbd1->tx_bd_hsize_lflags = lflags;
547 if (skb_is_gso(skb)) {
548 u32 hdr_len;
549
550 if (skb->encapsulation)
551 hdr_len = skb_inner_network_offset(skb) +
552 skb_inner_network_header_len(skb) +
553 inner_tcp_hdrlen(skb);
554 else
555 hdr_len = skb_transport_offset(skb) +
556 tcp_hdrlen(skb);
557
558 txbd1->tx_bd_hsize_lflags |= cpu_to_le32(TX_BD_FLAGS_LSO |
559 TX_BD_FLAGS_T_IPID |
560 (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
561 length = skb_shinfo(skb)->gso_size;
562 txbd1->tx_bd_mss = cpu_to_le32(length);
563 length += hdr_len;
564 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
565 txbd1->tx_bd_hsize_lflags |=
566 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
567 txbd1->tx_bd_mss = 0;
568 }
569
570 length >>= 9;
571 if (unlikely(length >= ARRAY_SIZE(bnxt_lhint_arr))) {
572 dev_warn_ratelimited(&pdev->dev, "Dropped oversize %d bytes TX packet.\n",
573 skb->len);
574 i = 0;
575 goto tx_dma_error;
576 }
577 flags |= bnxt_lhint_arr[length];
578 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
579
580 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
581 txbd1->tx_bd_cfa_action =
582 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
583 for (i = 0; i < last_frag; i++) {
584 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
585
586 prod = NEXT_TX(prod);
587 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
588
589 len = skb_frag_size(frag);
590 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
591 DMA_TO_DEVICE);
592
593 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
594 goto tx_dma_error;
595
596 tx_buf = &txr->tx_buf_ring[prod];
597 dma_unmap_addr_set(tx_buf, mapping, mapping);
598
599 txbd->tx_bd_haddr = cpu_to_le64(mapping);
600
601 flags = len << TX_BD_LEN_SHIFT;
602 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
603 }
604
605 flags &= ~TX_BD_LEN;
606 txbd->tx_bd_len_flags_type =
607 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
608 TX_BD_FLAGS_PACKET_END);
609
610 netdev_tx_sent_queue(txq, skb->len);
611
612 skb_tx_timestamp(skb);
613
614 /* Sync BD data before updating doorbell */
615 wmb();
616
617 prod = NEXT_TX(prod);
618 txr->tx_prod = prod;
619
620 if (!netdev_xmit_more() || netif_xmit_stopped(txq))
621 bnxt_db_write(bp, &txr->tx_db, prod);
622
623 tx_done:
624
625 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
626 if (netdev_xmit_more() && !tx_buf->is_push)
627 bnxt_db_write(bp, &txr->tx_db, prod);
628
629 netif_tx_stop_queue(txq);
630
631 /* netif_tx_stop_queue() must be done before checking
632 * tx index in bnxt_tx_avail() below, because in
633 * bnxt_tx_int(), we update tx index before checking for
634 * netif_tx_queue_stopped().
635 */
636 smp_mb();
637 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
638 netif_tx_wake_queue(txq);
639 }
640 return NETDEV_TX_OK;
641
642 tx_dma_error:
643 if (BNXT_TX_PTP_IS_SET(lflags))
644 atomic_inc(&bp->ptp_cfg->tx_avail);
645
646 last_frag = i;
647
648 /* start back at beginning and unmap skb */
649 prod = txr->tx_prod;
650 tx_buf = &txr->tx_buf_ring[prod];
651 tx_buf->skb = NULL;
652 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
653 skb_headlen(skb), PCI_DMA_TODEVICE);
654 prod = NEXT_TX(prod);
655
656 /* unmap remaining mapped pages */
657 for (i = 0; i < last_frag; i++) {
658 prod = NEXT_TX(prod);
659 tx_buf = &txr->tx_buf_ring[prod];
660 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
661 skb_frag_size(&skb_shinfo(skb)->frags[i]),
662 PCI_DMA_TODEVICE);
663 }
664
665 dev_kfree_skb_any(skb);
666 return NETDEV_TX_OK;
667 }
668
669 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
670 {
671 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
672 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index);
673 u16 cons = txr->tx_cons;
674 struct pci_dev *pdev = bp->pdev;
675 int i;
676 unsigned int tx_bytes = 0;
677
678 for (i = 0; i < nr_pkts; i++) {
679 struct bnxt_sw_tx_bd *tx_buf;
680 bool compl_deferred = false;
681 struct sk_buff *skb;
682 int j, last;
683
684 tx_buf = &txr->tx_buf_ring[cons];
685 cons = NEXT_TX(cons);
686 skb = tx_buf->skb;
687 tx_buf->skb = NULL;
688
689 if (tx_buf->is_push) {
690 tx_buf->is_push = 0;
691 goto next_tx_int;
692 }
693
694 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
695 skb_headlen(skb), PCI_DMA_TODEVICE);
696 last = tx_buf->nr_frags;
697
698 for (j = 0; j < last; j++) {
699 cons = NEXT_TX(cons);
700 tx_buf = &txr->tx_buf_ring[cons];
701 dma_unmap_page(
702 &pdev->dev,
703 dma_unmap_addr(tx_buf, mapping),
704 skb_frag_size(&skb_shinfo(skb)->frags[j]),
705 PCI_DMA_TODEVICE);
706 }
707 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
708 if (bp->flags & BNXT_FLAG_CHIP_P5) {
709 if (!bnxt_get_tx_ts_p5(bp, skb))
710 compl_deferred = true;
711 else
712 atomic_inc(&bp->ptp_cfg->tx_avail);
713 }
714 }
715
716 next_tx_int:
717 cons = NEXT_TX(cons);
718
719 tx_bytes += skb->len;
720 if (!compl_deferred)
721 dev_kfree_skb_any(skb);
722 }
723
724 netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
725 txr->tx_cons = cons;
726
727 /* Need to make the tx_cons update visible to bnxt_start_xmit()
728 * before checking for netif_tx_queue_stopped(). Without the
729 * memory barrier, there is a small possibility that bnxt_start_xmit()
730 * will miss it and cause the queue to be stopped forever.
731 */
732 smp_mb();
733
734 if (unlikely(netif_tx_queue_stopped(txq)) &&
735 (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
736 __netif_tx_lock(txq, smp_processor_id());
737 if (netif_tx_queue_stopped(txq) &&
738 bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
739 txr->dev_state != BNXT_DEV_STATE_CLOSING)
740 netif_tx_wake_queue(txq);
741 __netif_tx_unlock(txq);
742 }
743 }
744
745 static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping,
746 struct bnxt_rx_ring_info *rxr,
747 gfp_t gfp)
748 {
749 struct device *dev = &bp->pdev->dev;
750 struct page *page;
751
752 page = page_pool_dev_alloc_pages(rxr->page_pool);
753 if (!page)
754 return NULL;
755
756 *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir,
757 DMA_ATTR_WEAK_ORDERING);
758 if (dma_mapping_error(dev, *mapping)) {
759 page_pool_recycle_direct(rxr->page_pool, page);
760 return NULL;
761 }
762 *mapping += bp->rx_dma_offset;
763 return page;
764 }
765
766 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
767 gfp_t gfp)
768 {
769 u8 *data;
770 struct pci_dev *pdev = bp->pdev;
771
772 data = kmalloc(bp->rx_buf_size, gfp);
773 if (!data)
774 return NULL;
775
776 *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset,
777 bp->rx_buf_use_size, bp->rx_dir,
778 DMA_ATTR_WEAK_ORDERING);
779
780 if (dma_mapping_error(&pdev->dev, *mapping)) {
781 kfree(data);
782 data = NULL;
783 }
784 return data;
785 }
786
787 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
788 u16 prod, gfp_t gfp)
789 {
790 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
791 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
792 dma_addr_t mapping;
793
794 if (BNXT_RX_PAGE_MODE(bp)) {
795 struct page *page =
796 __bnxt_alloc_rx_page(bp, &mapping, rxr, gfp);
797
798 if (!page)
799 return -ENOMEM;
800
801 rx_buf->data = page;
802 rx_buf->data_ptr = page_address(page) + bp->rx_offset;
803 } else {
804 u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
805
806 if (!data)
807 return -ENOMEM;
808
809 rx_buf->data = data;
810 rx_buf->data_ptr = data + bp->rx_offset;
811 }
812 rx_buf->mapping = mapping;
813
814 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
815 return 0;
816 }
817
818 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data)
819 {
820 u16 prod = rxr->rx_prod;
821 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
822 struct rx_bd *cons_bd, *prod_bd;
823
824 prod_rx_buf = &rxr->rx_buf_ring[prod];
825 cons_rx_buf = &rxr->rx_buf_ring[cons];
826
827 prod_rx_buf->data = data;
828 prod_rx_buf->data_ptr = cons_rx_buf->data_ptr;
829
830 prod_rx_buf->mapping = cons_rx_buf->mapping;
831
832 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
833 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
834
835 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
836 }
837
838 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
839 {
840 u16 next, max = rxr->rx_agg_bmap_size;
841
842 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
843 if (next >= max)
844 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
845 return next;
846 }
847
848 static inline int bnxt_alloc_rx_page(struct bnxt *bp,
849 struct bnxt_rx_ring_info *rxr,
850 u16 prod, gfp_t gfp)
851 {
852 struct rx_bd *rxbd =
853 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
854 struct bnxt_sw_rx_agg_bd *rx_agg_buf;
855 struct pci_dev *pdev = bp->pdev;
856 struct page *page;
857 dma_addr_t mapping;
858 u16 sw_prod = rxr->rx_sw_agg_prod;
859 unsigned int offset = 0;
860
861 if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
862 page = rxr->rx_page;
863 if (!page) {
864 page = alloc_page(gfp);
865 if (!page)
866 return -ENOMEM;
867 rxr->rx_page = page;
868 rxr->rx_page_offset = 0;
869 }
870 offset = rxr->rx_page_offset;
871 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
872 if (rxr->rx_page_offset == PAGE_SIZE)
873 rxr->rx_page = NULL;
874 else
875 get_page(page);
876 } else {
877 page = alloc_page(gfp);
878 if (!page)
879 return -ENOMEM;
880 }
881
882 mapping = dma_map_page_attrs(&pdev->dev, page, offset,
883 BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE,
884 DMA_ATTR_WEAK_ORDERING);
885 if (dma_mapping_error(&pdev->dev, mapping)) {
886 __free_page(page);
887 return -EIO;
888 }
889
890 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
891 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
892
893 __set_bit(sw_prod, rxr->rx_agg_bmap);
894 rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
895 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
896
897 rx_agg_buf->page = page;
898 rx_agg_buf->offset = offset;
899 rx_agg_buf->mapping = mapping;
900 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
901 rxbd->rx_bd_opaque = sw_prod;
902 return 0;
903 }
904
905 static struct rx_agg_cmp *bnxt_get_agg(struct bnxt *bp,
906 struct bnxt_cp_ring_info *cpr,
907 u16 cp_cons, u16 curr)
908 {
909 struct rx_agg_cmp *agg;
910
911 cp_cons = RING_CMP(ADV_RAW_CMP(cp_cons, curr));
912 agg = (struct rx_agg_cmp *)
913 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
914 return agg;
915 }
916
917 static struct rx_agg_cmp *bnxt_get_tpa_agg_p5(struct bnxt *bp,
918 struct bnxt_rx_ring_info *rxr,
919 u16 agg_id, u16 curr)
920 {
921 struct bnxt_tpa_info *tpa_info = &rxr->rx_tpa[agg_id];
922
923 return &tpa_info->agg_arr[curr];
924 }
925
926 static void bnxt_reuse_rx_agg_bufs(struct bnxt_cp_ring_info *cpr, u16 idx,
927 u16 start, u32 agg_bufs, bool tpa)
928 {
929 struct bnxt_napi *bnapi = cpr->bnapi;
930 struct bnxt *bp = bnapi->bp;
931 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
932 u16 prod = rxr->rx_agg_prod;
933 u16 sw_prod = rxr->rx_sw_agg_prod;
934 bool p5_tpa = false;
935 u32 i;
936
937 if ((bp->flags & BNXT_FLAG_CHIP_P5) && tpa)
938 p5_tpa = true;
939
940 for (i = 0; i < agg_bufs; i++) {
941 u16 cons;
942 struct rx_agg_cmp *agg;
943 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
944 struct rx_bd *prod_bd;
945 struct page *page;
946
947 if (p5_tpa)
948 agg = bnxt_get_tpa_agg_p5(bp, rxr, idx, start + i);
949 else
950 agg = bnxt_get_agg(bp, cpr, idx, start + i);
951 cons = agg->rx_agg_cmp_opaque;
952 __clear_bit(cons, rxr->rx_agg_bmap);
953
954 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
955 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
956
957 __set_bit(sw_prod, rxr->rx_agg_bmap);
958 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
959 cons_rx_buf = &rxr->rx_agg_ring[cons];
960
961 /* It is possible for sw_prod to be equal to cons, so
962 * set cons_rx_buf->page to NULL first.
963 */
964 page = cons_rx_buf->page;
965 cons_rx_buf->page = NULL;
966 prod_rx_buf->page = page;
967 prod_rx_buf->offset = cons_rx_buf->offset;
968
969 prod_rx_buf->mapping = cons_rx_buf->mapping;
970
971 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
972
973 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
974 prod_bd->rx_bd_opaque = sw_prod;
975
976 prod = NEXT_RX_AGG(prod);
977 sw_prod = NEXT_RX_AGG(sw_prod);
978 }
979 rxr->rx_agg_prod = prod;
980 rxr->rx_sw_agg_prod = sw_prod;
981 }
982
983 static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp,
984 struct bnxt_rx_ring_info *rxr,
985 u16 cons, void *data, u8 *data_ptr,
986 dma_addr_t dma_addr,
987 unsigned int offset_and_len)
988 {
989 unsigned int payload = offset_and_len >> 16;
990 unsigned int len = offset_and_len & 0xffff;
991 skb_frag_t *frag;
992 struct page *page = data;
993 u16 prod = rxr->rx_prod;
994 struct sk_buff *skb;
995 int off, err;
996
997 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
998 if (unlikely(err)) {
999 bnxt_reuse_rx_data(rxr, cons, data);
1000 return NULL;
1001 }
1002 dma_addr -= bp->rx_dma_offset;
1003 dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir,
1004 DMA_ATTR_WEAK_ORDERING);
1005 page_pool_release_page(rxr->page_pool, page);
1006
1007 if (unlikely(!payload))
1008 payload = eth_get_headlen(bp->dev, data_ptr, len);
1009
1010 skb = napi_alloc_skb(&rxr->bnapi->napi, payload);
1011 if (!skb) {
1012 __free_page(page);
1013 return NULL;
1014 }
1015
1016 off = (void *)data_ptr - page_address(page);
1017 skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE);
1018 memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN,
1019 payload + NET_IP_ALIGN);
1020
1021 frag = &skb_shinfo(skb)->frags[0];
1022 skb_frag_size_sub(frag, payload);
1023 skb_frag_off_add(frag, payload);
1024 skb->data_len -= payload;
1025 skb->tail += payload;
1026
1027 return skb;
1028 }
1029
1030 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
1031 struct bnxt_rx_ring_info *rxr, u16 cons,
1032 void *data, u8 *data_ptr,
1033 dma_addr_t dma_addr,
1034 unsigned int offset_and_len)
1035 {
1036 u16 prod = rxr->rx_prod;
1037 struct sk_buff *skb;
1038 int err;
1039
1040 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
1041 if (unlikely(err)) {
1042 bnxt_reuse_rx_data(rxr, cons, data);
1043 return NULL;
1044 }
1045
1046 skb = build_skb(data, 0);
1047 dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
1048 bp->rx_dir, DMA_ATTR_WEAK_ORDERING);
1049 if (!skb) {
1050 kfree(data);
1051 return NULL;
1052 }
1053
1054 skb_reserve(skb, bp->rx_offset);
1055 skb_put(skb, offset_and_len & 0xffff);
1056 return skb;
1057 }
1058
1059 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp,
1060 struct bnxt_cp_ring_info *cpr,
1061 struct sk_buff *skb, u16 idx,
1062 u32 agg_bufs, bool tpa)
1063 {
1064 struct bnxt_napi *bnapi = cpr->bnapi;
1065 struct pci_dev *pdev = bp->pdev;
1066 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1067 u16 prod = rxr->rx_agg_prod;
1068 bool p5_tpa = false;
1069 u32 i;
1070
1071 if ((bp->flags & BNXT_FLAG_CHIP_P5) && tpa)
1072 p5_tpa = true;
1073
1074 for (i = 0; i < agg_bufs; i++) {
1075 u16 cons, frag_len;
1076 struct rx_agg_cmp *agg;
1077 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
1078 struct page *page;
1079 dma_addr_t mapping;
1080
1081 if (p5_tpa)
1082 agg = bnxt_get_tpa_agg_p5(bp, rxr, idx, i);
1083 else
1084 agg = bnxt_get_agg(bp, cpr, idx, i);
1085 cons = agg->rx_agg_cmp_opaque;
1086 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
1087 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
1088
1089 cons_rx_buf = &rxr->rx_agg_ring[cons];
1090 skb_fill_page_desc(skb, i, cons_rx_buf->page,
1091 cons_rx_buf->offset, frag_len);
1092 __clear_bit(cons, rxr->rx_agg_bmap);
1093
1094 /* It is possible for bnxt_alloc_rx_page() to allocate
1095 * a sw_prod index that equals the cons index, so we
1096 * need to clear the cons entry now.
1097 */
1098 mapping = cons_rx_buf->mapping;
1099 page = cons_rx_buf->page;
1100 cons_rx_buf->page = NULL;
1101
1102 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
1103 struct skb_shared_info *shinfo;
1104 unsigned int nr_frags;
1105
1106 shinfo = skb_shinfo(skb);
1107 nr_frags = --shinfo->nr_frags;
1108 __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
1109
1110 dev_kfree_skb(skb);
1111
1112 cons_rx_buf->page = page;
1113
1114 /* Update prod since possibly some pages have been
1115 * allocated already.
1116 */
1117 rxr->rx_agg_prod = prod;
1118 bnxt_reuse_rx_agg_bufs(cpr, idx, i, agg_bufs - i, tpa);
1119 return NULL;
1120 }
1121
1122 dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
1123 PCI_DMA_FROMDEVICE,
1124 DMA_ATTR_WEAK_ORDERING);
1125
1126 skb->data_len += frag_len;
1127 skb->len += frag_len;
1128 skb->truesize += PAGE_SIZE;
1129
1130 prod = NEXT_RX_AGG(prod);
1131 }
1132 rxr->rx_agg_prod = prod;
1133 return skb;
1134 }
1135
1136 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1137 u8 agg_bufs, u32 *raw_cons)
1138 {
1139 u16 last;
1140 struct rx_agg_cmp *agg;
1141
1142 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
1143 last = RING_CMP(*raw_cons);
1144 agg = (struct rx_agg_cmp *)
1145 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
1146 return RX_AGG_CMP_VALID(agg, *raw_cons);
1147 }
1148
1149 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
1150 unsigned int len,
1151 dma_addr_t mapping)
1152 {
1153 struct bnxt *bp = bnapi->bp;
1154 struct pci_dev *pdev = bp->pdev;
1155 struct sk_buff *skb;
1156
1157 skb = napi_alloc_skb(&bnapi->napi, len);
1158 if (!skb)
1159 return NULL;
1160
1161 dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh,
1162 bp->rx_dir);
1163
1164 memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN,
1165 len + NET_IP_ALIGN);
1166
1167 dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh,
1168 bp->rx_dir);
1169
1170 skb_put(skb, len);
1171 return skb;
1172 }
1173
1174 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1175 u32 *raw_cons, void *cmp)
1176 {
1177 struct rx_cmp *rxcmp = cmp;
1178 u32 tmp_raw_cons = *raw_cons;
1179 u8 cmp_type, agg_bufs = 0;
1180
1181 cmp_type = RX_CMP_TYPE(rxcmp);
1182
1183 if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1184 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
1185 RX_CMP_AGG_BUFS) >>
1186 RX_CMP_AGG_BUFS_SHIFT;
1187 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1188 struct rx_tpa_end_cmp *tpa_end = cmp;
1189
1190 if (bp->flags & BNXT_FLAG_CHIP_P5)
1191 return 0;
1192
1193 agg_bufs = TPA_END_AGG_BUFS(tpa_end);
1194 }
1195
1196 if (agg_bufs) {
1197 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1198 return -EBUSY;
1199 }
1200 *raw_cons = tmp_raw_cons;
1201 return 0;
1202 }
1203
1204 static void bnxt_queue_fw_reset_work(struct bnxt *bp, unsigned long delay)
1205 {
1206 if (!(test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)))
1207 return;
1208
1209 if (BNXT_PF(bp))
1210 queue_delayed_work(bnxt_pf_wq, &bp->fw_reset_task, delay);
1211 else
1212 schedule_delayed_work(&bp->fw_reset_task, delay);
1213 }
1214
1215 static void bnxt_queue_sp_work(struct bnxt *bp)
1216 {
1217 if (BNXT_PF(bp))
1218 queue_work(bnxt_pf_wq, &bp->sp_task);
1219 else
1220 schedule_work(&bp->sp_task);
1221 }
1222
1223 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
1224 {
1225 if (!rxr->bnapi->in_reset) {
1226 rxr->bnapi->in_reset = true;
1227 if (bp->flags & BNXT_FLAG_CHIP_P5)
1228 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
1229 else
1230 set_bit(BNXT_RST_RING_SP_EVENT, &bp->sp_event);
1231 bnxt_queue_sp_work(bp);
1232 }
1233 rxr->rx_next_cons = 0xffff;
1234 }
1235
1236 static u16 bnxt_alloc_agg_idx(struct bnxt_rx_ring_info *rxr, u16 agg_id)
1237 {
1238 struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map;
1239 u16 idx = agg_id & MAX_TPA_P5_MASK;
1240
1241 if (test_bit(idx, map->agg_idx_bmap))
1242 idx = find_first_zero_bit(map->agg_idx_bmap,
1243 BNXT_AGG_IDX_BMAP_SIZE);
1244 __set_bit(idx, map->agg_idx_bmap);
1245 map->agg_id_tbl[agg_id] = idx;
1246 return idx;
1247 }
1248
1249 static void bnxt_free_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
1250 {
1251 struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map;
1252
1253 __clear_bit(idx, map->agg_idx_bmap);
1254 }
1255
1256 static u16 bnxt_lookup_agg_idx(struct bnxt_rx_ring_info *rxr, u16 agg_id)
1257 {
1258 struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map;
1259
1260 return map->agg_id_tbl[agg_id];
1261 }
1262
1263 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1264 struct rx_tpa_start_cmp *tpa_start,
1265 struct rx_tpa_start_cmp_ext *tpa_start1)
1266 {
1267 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
1268 struct bnxt_tpa_info *tpa_info;
1269 u16 cons, prod, agg_id;
1270 struct rx_bd *prod_bd;
1271 dma_addr_t mapping;
1272
1273 if (bp->flags & BNXT_FLAG_CHIP_P5) {
1274 agg_id = TPA_START_AGG_ID_P5(tpa_start);
1275 agg_id = bnxt_alloc_agg_idx(rxr, agg_id);
1276 } else {
1277 agg_id = TPA_START_AGG_ID(tpa_start);
1278 }
1279 cons = tpa_start->rx_tpa_start_cmp_opaque;
1280 prod = rxr->rx_prod;
1281 cons_rx_buf = &rxr->rx_buf_ring[cons];
1282 prod_rx_buf = &rxr->rx_buf_ring[prod];
1283 tpa_info = &rxr->rx_tpa[agg_id];
1284
1285 if (unlikely(cons != rxr->rx_next_cons ||
1286 TPA_START_ERROR(tpa_start))) {
1287 netdev_warn(bp->dev, "TPA cons %x, expected cons %x, error code %x\n",
1288 cons, rxr->rx_next_cons,
1289 TPA_START_ERROR_CODE(tpa_start1));
1290 bnxt_sched_reset(bp, rxr);
1291 return;
1292 }
1293 /* Store cfa_code in tpa_info to use in tpa_end
1294 * completion processing.
1295 */
1296 tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1);
1297 prod_rx_buf->data = tpa_info->data;
1298 prod_rx_buf->data_ptr = tpa_info->data_ptr;
1299
1300 mapping = tpa_info->mapping;
1301 prod_rx_buf->mapping = mapping;
1302
1303 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1304
1305 prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
1306
1307 tpa_info->data = cons_rx_buf->data;
1308 tpa_info->data_ptr = cons_rx_buf->data_ptr;
1309 cons_rx_buf->data = NULL;
1310 tpa_info->mapping = cons_rx_buf->mapping;
1311
1312 tpa_info->len =
1313 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
1314 RX_TPA_START_CMP_LEN_SHIFT;
1315 if (likely(TPA_START_HASH_VALID(tpa_start))) {
1316 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
1317
1318 tpa_info->hash_type = PKT_HASH_TYPE_L4;
1319 tpa_info->gso_type = SKB_GSO_TCPV4;
1320 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1321 if (hash_type == 3 || TPA_START_IS_IPV6(tpa_start1))
1322 tpa_info->gso_type = SKB_GSO_TCPV6;
1323 tpa_info->rss_hash =
1324 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
1325 } else {
1326 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
1327 tpa_info->gso_type = 0;
1328 netif_warn(bp, rx_err, bp->dev, "TPA packet without valid hash\n");
1329 }
1330 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
1331 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
1332 tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
1333 tpa_info->agg_count = 0;
1334
1335 rxr->rx_prod = NEXT_RX(prod);
1336 cons = NEXT_RX(cons);
1337 rxr->rx_next_cons = NEXT_RX(cons);
1338 cons_rx_buf = &rxr->rx_buf_ring[cons];
1339
1340 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
1341 rxr->rx_prod = NEXT_RX(rxr->rx_prod);
1342 cons_rx_buf->data = NULL;
1343 }
1344
1345 static void bnxt_abort_tpa(struct bnxt_cp_ring_info *cpr, u16 idx, u32 agg_bufs)
1346 {
1347 if (agg_bufs)
1348 bnxt_reuse_rx_agg_bufs(cpr, idx, 0, agg_bufs, true);
1349 }
1350
1351 #ifdef CONFIG_INET
1352 static void bnxt_gro_tunnel(struct sk_buff *skb, __be16 ip_proto)
1353 {
1354 struct udphdr *uh = NULL;
1355
1356 if (ip_proto == htons(ETH_P_IP)) {
1357 struct iphdr *iph = (struct iphdr *)skb->data;
1358
1359 if (iph->protocol == IPPROTO_UDP)
1360 uh = (struct udphdr *)(iph + 1);
1361 } else {
1362 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1363
1364 if (iph->nexthdr == IPPROTO_UDP)
1365 uh = (struct udphdr *)(iph + 1);
1366 }
1367 if (uh) {
1368 if (uh->check)
1369 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL_CSUM;
1370 else
1371 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1372 }
1373 }
1374 #endif
1375
1376 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info,
1377 int payload_off, int tcp_ts,
1378 struct sk_buff *skb)
1379 {
1380 #ifdef CONFIG_INET
1381 struct tcphdr *th;
1382 int len, nw_off;
1383 u16 outer_ip_off, inner_ip_off, inner_mac_off;
1384 u32 hdr_info = tpa_info->hdr_info;
1385 bool loopback = false;
1386
1387 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1388 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1389 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1390
1391 /* If the packet is an internal loopback packet, the offsets will
1392 * have an extra 4 bytes.
1393 */
1394 if (inner_mac_off == 4) {
1395 loopback = true;
1396 } else if (inner_mac_off > 4) {
1397 __be16 proto = *((__be16 *)(skb->data + inner_ip_off -
1398 ETH_HLEN - 2));
1399
1400 /* We only support inner iPv4/ipv6. If we don't see the
1401 * correct protocol ID, it must be a loopback packet where
1402 * the offsets are off by 4.
1403 */
1404 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6))
1405 loopback = true;
1406 }
1407 if (loopback) {
1408 /* internal loopback packet, subtract all offsets by 4 */
1409 inner_ip_off -= 4;
1410 inner_mac_off -= 4;
1411 outer_ip_off -= 4;
1412 }
1413
1414 nw_off = inner_ip_off - ETH_HLEN;
1415 skb_set_network_header(skb, nw_off);
1416 if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) {
1417 struct ipv6hdr *iph = ipv6_hdr(skb);
1418
1419 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1420 len = skb->len - skb_transport_offset(skb);
1421 th = tcp_hdr(skb);
1422 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1423 } else {
1424 struct iphdr *iph = ip_hdr(skb);
1425
1426 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1427 len = skb->len - skb_transport_offset(skb);
1428 th = tcp_hdr(skb);
1429 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1430 }
1431
1432 if (inner_mac_off) { /* tunnel */
1433 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1434 ETH_HLEN - 2));
1435
1436 bnxt_gro_tunnel(skb, proto);
1437 }
1438 #endif
1439 return skb;
1440 }
1441
1442 static struct sk_buff *bnxt_gro_func_5750x(struct bnxt_tpa_info *tpa_info,
1443 int payload_off, int tcp_ts,
1444 struct sk_buff *skb)
1445 {
1446 #ifdef CONFIG_INET
1447 u16 outer_ip_off, inner_ip_off, inner_mac_off;
1448 u32 hdr_info = tpa_info->hdr_info;
1449 int iphdr_len, nw_off;
1450
1451 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1452 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1453 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1454
1455 nw_off = inner_ip_off - ETH_HLEN;
1456 skb_set_network_header(skb, nw_off);
1457 iphdr_len = (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) ?
1458 sizeof(struct ipv6hdr) : sizeof(struct iphdr);
1459 skb_set_transport_header(skb, nw_off + iphdr_len);
1460
1461 if (inner_mac_off) { /* tunnel */
1462 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1463 ETH_HLEN - 2));
1464
1465 bnxt_gro_tunnel(skb, proto);
1466 }
1467 #endif
1468 return skb;
1469 }
1470
1471 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
1472 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1473
1474 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info,
1475 int payload_off, int tcp_ts,
1476 struct sk_buff *skb)
1477 {
1478 #ifdef CONFIG_INET
1479 struct tcphdr *th;
1480 int len, nw_off, tcp_opt_len = 0;
1481
1482 if (tcp_ts)
1483 tcp_opt_len = 12;
1484
1485 if (tpa_info->gso_type == SKB_GSO_TCPV4) {
1486 struct iphdr *iph;
1487
1488 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
1489 ETH_HLEN;
1490 skb_set_network_header(skb, nw_off);
1491 iph = ip_hdr(skb);
1492 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1493 len = skb->len - skb_transport_offset(skb);
1494 th = tcp_hdr(skb);
1495 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1496 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
1497 struct ipv6hdr *iph;
1498
1499 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
1500 ETH_HLEN;
1501 skb_set_network_header(skb, nw_off);
1502 iph = ipv6_hdr(skb);
1503 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1504 len = skb->len - skb_transport_offset(skb);
1505 th = tcp_hdr(skb);
1506 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1507 } else {
1508 dev_kfree_skb_any(skb);
1509 return NULL;
1510 }
1511
1512 if (nw_off) /* tunnel */
1513 bnxt_gro_tunnel(skb, skb->protocol);
1514 #endif
1515 return skb;
1516 }
1517
1518 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp,
1519 struct bnxt_tpa_info *tpa_info,
1520 struct rx_tpa_end_cmp *tpa_end,
1521 struct rx_tpa_end_cmp_ext *tpa_end1,
1522 struct sk_buff *skb)
1523 {
1524 #ifdef CONFIG_INET
1525 int payload_off;
1526 u16 segs;
1527
1528 segs = TPA_END_TPA_SEGS(tpa_end);
1529 if (segs == 1)
1530 return skb;
1531
1532 NAPI_GRO_CB(skb)->count = segs;
1533 skb_shinfo(skb)->gso_size =
1534 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1535 skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1536 if (bp->flags & BNXT_FLAG_CHIP_P5)
1537 payload_off = TPA_END_PAYLOAD_OFF_P5(tpa_end1);
1538 else
1539 payload_off = TPA_END_PAYLOAD_OFF(tpa_end);
1540 skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
1541 if (likely(skb))
1542 tcp_gro_complete(skb);
1543 #endif
1544 return skb;
1545 }
1546
1547 /* Given the cfa_code of a received packet determine which
1548 * netdev (vf-rep or PF) the packet is destined to.
1549 */
1550 static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code)
1551 {
1552 struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code);
1553
1554 /* if vf-rep dev is NULL, the must belongs to the PF */
1555 return dev ? dev : bp->dev;
1556 }
1557
1558 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
1559 struct bnxt_cp_ring_info *cpr,
1560 u32 *raw_cons,
1561 struct rx_tpa_end_cmp *tpa_end,
1562 struct rx_tpa_end_cmp_ext *tpa_end1,
1563 u8 *event)
1564 {
1565 struct bnxt_napi *bnapi = cpr->bnapi;
1566 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1567 u8 *data_ptr, agg_bufs;
1568 unsigned int len;
1569 struct bnxt_tpa_info *tpa_info;
1570 dma_addr_t mapping;
1571 struct sk_buff *skb;
1572 u16 idx = 0, agg_id;
1573 void *data;
1574 bool gro;
1575
1576 if (unlikely(bnapi->in_reset)) {
1577 int rc = bnxt_discard_rx(bp, cpr, raw_cons, tpa_end);
1578
1579 if (rc < 0)
1580 return ERR_PTR(-EBUSY);
1581 return NULL;
1582 }
1583
1584 if (bp->flags & BNXT_FLAG_CHIP_P5) {
1585 agg_id = TPA_END_AGG_ID_P5(tpa_end);
1586 agg_id = bnxt_lookup_agg_idx(rxr, agg_id);
1587 agg_bufs = TPA_END_AGG_BUFS_P5(tpa_end1);
1588 tpa_info = &rxr->rx_tpa[agg_id];
1589 if (unlikely(agg_bufs != tpa_info->agg_count)) {
1590 netdev_warn(bp->dev, "TPA end agg_buf %d != expected agg_bufs %d\n",
1591 agg_bufs, tpa_info->agg_count);
1592 agg_bufs = tpa_info->agg_count;
1593 }
1594 tpa_info->agg_count = 0;
1595 *event |= BNXT_AGG_EVENT;
1596 bnxt_free_agg_idx(rxr, agg_id);
1597 idx = agg_id;
1598 gro = !!(bp->flags & BNXT_FLAG_GRO);
1599 } else {
1600 agg_id = TPA_END_AGG_ID(tpa_end);
1601 agg_bufs = TPA_END_AGG_BUFS(tpa_end);
1602 tpa_info = &rxr->rx_tpa[agg_id];
1603 idx = RING_CMP(*raw_cons);
1604 if (agg_bufs) {
1605 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1606 return ERR_PTR(-EBUSY);
1607
1608 *event |= BNXT_AGG_EVENT;
1609 idx = NEXT_CMP(idx);
1610 }
1611 gro = !!TPA_END_GRO(tpa_end);
1612 }
1613 data = tpa_info->data;
1614 data_ptr = tpa_info->data_ptr;
1615 prefetch(data_ptr);
1616 len = tpa_info->len;
1617 mapping = tpa_info->mapping;
1618
1619 if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) {
1620 bnxt_abort_tpa(cpr, idx, agg_bufs);
1621 if (agg_bufs > MAX_SKB_FRAGS)
1622 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1623 agg_bufs, (int)MAX_SKB_FRAGS);
1624 return NULL;
1625 }
1626
1627 if (len <= bp->rx_copy_thresh) {
1628 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping);
1629 if (!skb) {
1630 bnxt_abort_tpa(cpr, idx, agg_bufs);
1631 return NULL;
1632 }
1633 } else {
1634 u8 *new_data;
1635 dma_addr_t new_mapping;
1636
1637 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1638 if (!new_data) {
1639 bnxt_abort_tpa(cpr, idx, agg_bufs);
1640 return NULL;
1641 }
1642
1643 tpa_info->data = new_data;
1644 tpa_info->data_ptr = new_data + bp->rx_offset;
1645 tpa_info->mapping = new_mapping;
1646
1647 skb = build_skb(data, 0);
1648 dma_unmap_single_attrs(&bp->pdev->dev, mapping,
1649 bp->rx_buf_use_size, bp->rx_dir,
1650 DMA_ATTR_WEAK_ORDERING);
1651
1652 if (!skb) {
1653 kfree(data);
1654 bnxt_abort_tpa(cpr, idx, agg_bufs);
1655 return NULL;
1656 }
1657 skb_reserve(skb, bp->rx_offset);
1658 skb_put(skb, len);
1659 }
1660
1661 if (agg_bufs) {
1662 skb = bnxt_rx_pages(bp, cpr, skb, idx, agg_bufs, true);
1663 if (!skb) {
1664 /* Page reuse already handled by bnxt_rx_pages(). */
1665 return NULL;
1666 }
1667 }
1668
1669 skb->protocol =
1670 eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code));
1671
1672 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1673 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1674
1675 if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1676 (skb->dev->features & BNXT_HW_FEATURE_VLAN_ALL_RX)) {
1677 __be16 vlan_proto = htons(tpa_info->metadata >>
1678 RX_CMP_FLAGS2_METADATA_TPID_SFT);
1679 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1680
1681 if (eth_type_vlan(vlan_proto)) {
1682 __vlan_hwaccel_put_tag(skb, vlan_proto, vtag);
1683 } else {
1684 dev_kfree_skb(skb);
1685 return NULL;
1686 }
1687 }
1688
1689 skb_checksum_none_assert(skb);
1690 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1691 skb->ip_summed = CHECKSUM_UNNECESSARY;
1692 skb->csum_level =
1693 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1694 }
1695
1696 if (gro)
1697 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb);
1698
1699 return skb;
1700 }
1701
1702 static void bnxt_tpa_agg(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1703 struct rx_agg_cmp *rx_agg)
1704 {
1705 u16 agg_id = TPA_AGG_AGG_ID(rx_agg);
1706 struct bnxt_tpa_info *tpa_info;
1707
1708 agg_id = bnxt_lookup_agg_idx(rxr, agg_id);
1709 tpa_info = &rxr->rx_tpa[agg_id];
1710 BUG_ON(tpa_info->agg_count >= MAX_SKB_FRAGS);
1711 tpa_info->agg_arr[tpa_info->agg_count++] = *rx_agg;
1712 }
1713
1714 static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi,
1715 struct sk_buff *skb)
1716 {
1717 if (skb->dev != bp->dev) {
1718 /* this packet belongs to a vf-rep */
1719 bnxt_vf_rep_rx(bp, skb);
1720 return;
1721 }
1722 skb_record_rx_queue(skb, bnapi->index);
1723 napi_gro_receive(&bnapi->napi, skb);
1724 }
1725
1726 /* returns the following:
1727 * 1 - 1 packet successfully received
1728 * 0 - successful TPA_START, packet not completed yet
1729 * -EBUSY - completion ring does not have all the agg buffers yet
1730 * -ENOMEM - packet aborted due to out of memory
1731 * -EIO - packet aborted due to hw error indicated in BD
1732 */
1733 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1734 u32 *raw_cons, u8 *event)
1735 {
1736 struct bnxt_napi *bnapi = cpr->bnapi;
1737 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1738 struct net_device *dev = bp->dev;
1739 struct rx_cmp *rxcmp;
1740 struct rx_cmp_ext *rxcmp1;
1741 u32 tmp_raw_cons = *raw_cons;
1742 u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1743 struct bnxt_sw_rx_bd *rx_buf;
1744 unsigned int len;
1745 u8 *data_ptr, agg_bufs, cmp_type;
1746 dma_addr_t dma_addr;
1747 struct sk_buff *skb;
1748 u32 flags, misc;
1749 void *data;
1750 int rc = 0;
1751
1752 rxcmp = (struct rx_cmp *)
1753 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1754
1755 cmp_type = RX_CMP_TYPE(rxcmp);
1756
1757 if (cmp_type == CMP_TYPE_RX_TPA_AGG_CMP) {
1758 bnxt_tpa_agg(bp, rxr, (struct rx_agg_cmp *)rxcmp);
1759 goto next_rx_no_prod_no_len;
1760 }
1761
1762 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1763 cp_cons = RING_CMP(tmp_raw_cons);
1764 rxcmp1 = (struct rx_cmp_ext *)
1765 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1766
1767 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1768 return -EBUSY;
1769
1770 prod = rxr->rx_prod;
1771
1772 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1773 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1774 (struct rx_tpa_start_cmp_ext *)rxcmp1);
1775
1776 *event |= BNXT_RX_EVENT;
1777 goto next_rx_no_prod_no_len;
1778
1779 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1780 skb = bnxt_tpa_end(bp, cpr, &tmp_raw_cons,
1781 (struct rx_tpa_end_cmp *)rxcmp,
1782 (struct rx_tpa_end_cmp_ext *)rxcmp1, event);
1783
1784 if (IS_ERR(skb))
1785 return -EBUSY;
1786
1787 rc = -ENOMEM;
1788 if (likely(skb)) {
1789 bnxt_deliver_skb(bp, bnapi, skb);
1790 rc = 1;
1791 }
1792 *event |= BNXT_RX_EVENT;
1793 goto next_rx_no_prod_no_len;
1794 }
1795
1796 cons = rxcmp->rx_cmp_opaque;
1797 if (unlikely(cons != rxr->rx_next_cons)) {
1798 int rc1 = bnxt_discard_rx(bp, cpr, &tmp_raw_cons, rxcmp);
1799
1800 /* 0xffff is forced error, don't print it */
1801 if (rxr->rx_next_cons != 0xffff)
1802 netdev_warn(bp->dev, "RX cons %x != expected cons %x\n",
1803 cons, rxr->rx_next_cons);
1804 bnxt_sched_reset(bp, rxr);
1805 if (rc1)
1806 return rc1;
1807 goto next_rx_no_prod_no_len;
1808 }
1809 rx_buf = &rxr->rx_buf_ring[cons];
1810 data = rx_buf->data;
1811 data_ptr = rx_buf->data_ptr;
1812 prefetch(data_ptr);
1813
1814 misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1);
1815 agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT;
1816
1817 if (agg_bufs) {
1818 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1819 return -EBUSY;
1820
1821 cp_cons = NEXT_CMP(cp_cons);
1822 *event |= BNXT_AGG_EVENT;
1823 }
1824 *event |= BNXT_RX_EVENT;
1825
1826 rx_buf->data = NULL;
1827 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1828 u32 rx_err = le32_to_cpu(rxcmp1->rx_cmp_cfa_code_errors_v2);
1829
1830 bnxt_reuse_rx_data(rxr, cons, data);
1831 if (agg_bufs)
1832 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, 0, agg_bufs,
1833 false);
1834
1835 rc = -EIO;
1836 if (rx_err & RX_CMPL_ERRORS_BUFFER_ERROR_MASK) {
1837 bnapi->cp_ring.sw_stats.rx.rx_buf_errors++;
1838 if (!(bp->flags & BNXT_FLAG_CHIP_P5) &&
1839 !(bp->fw_cap & BNXT_FW_CAP_RING_MONITOR)) {
1840 netdev_warn_once(bp->dev, "RX buffer error %x\n",
1841 rx_err);
1842 bnxt_sched_reset(bp, rxr);
1843 }
1844 }
1845 goto next_rx_no_len;
1846 }
1847
1848 flags = le32_to_cpu(rxcmp->rx_cmp_len_flags_type);
1849 len = flags >> RX_CMP_LEN_SHIFT;
1850 dma_addr = rx_buf->mapping;
1851
1852 if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) {
1853 rc = 1;
1854 goto next_rx;
1855 }
1856
1857 if (len <= bp->rx_copy_thresh) {
1858 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr);
1859 bnxt_reuse_rx_data(rxr, cons, data);
1860 if (!skb) {
1861 if (agg_bufs)
1862 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, 0,
1863 agg_bufs, false);
1864 rc = -ENOMEM;
1865 goto next_rx;
1866 }
1867 } else {
1868 u32 payload;
1869
1870 if (rx_buf->data_ptr == data_ptr)
1871 payload = misc & RX_CMP_PAYLOAD_OFFSET;
1872 else
1873 payload = 0;
1874 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr,
1875 payload | len);
1876 if (!skb) {
1877 rc = -ENOMEM;
1878 goto next_rx;
1879 }
1880 }
1881
1882 if (agg_bufs) {
1883 skb = bnxt_rx_pages(bp, cpr, skb, cp_cons, agg_bufs, false);
1884 if (!skb) {
1885 rc = -ENOMEM;
1886 goto next_rx;
1887 }
1888 }
1889
1890 if (RX_CMP_HASH_VALID(rxcmp)) {
1891 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1892 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1893
1894 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1895 if (hash_type != 1 && hash_type != 3)
1896 type = PKT_HASH_TYPE_L3;
1897 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1898 }
1899
1900 cfa_code = RX_CMP_CFA_CODE(rxcmp1);
1901 skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code));
1902
1903 if ((rxcmp1->rx_cmp_flags2 &
1904 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
1905 (skb->dev->features & BNXT_HW_FEATURE_VLAN_ALL_RX)) {
1906 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1907 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1908 __be16 vlan_proto = htons(meta_data >>
1909 RX_CMP_FLAGS2_METADATA_TPID_SFT);
1910
1911 if (eth_type_vlan(vlan_proto)) {
1912 __vlan_hwaccel_put_tag(skb, vlan_proto, vtag);
1913 } else {
1914 dev_kfree_skb(skb);
1915 goto next_rx;
1916 }
1917 }
1918
1919 skb_checksum_none_assert(skb);
1920 if (RX_CMP_L4_CS_OK(rxcmp1)) {
1921 if (dev->features & NETIF_F_RXCSUM) {
1922 skb->ip_summed = CHECKSUM_UNNECESSARY;
1923 skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1924 }
1925 } else {
1926 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1927 if (dev->features & NETIF_F_RXCSUM)
1928 bnapi->cp_ring.sw_stats.rx.rx_l4_csum_errors++;
1929 }
1930 }
1931
1932 if (unlikely((flags & RX_CMP_FLAGS_ITYPES_MASK) ==
1933 RX_CMP_FLAGS_ITYPE_PTP_W_TS)) {
1934 if (bp->flags & BNXT_FLAG_CHIP_P5) {
1935 u32 cmpl_ts = le32_to_cpu(rxcmp1->rx_cmp_timestamp);
1936 u64 ns, ts;
1937
1938 if (!bnxt_get_rx_ts_p5(bp, &ts, cmpl_ts)) {
1939 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1940
1941 spin_lock_bh(&ptp->ptp_lock);
1942 ns = timecounter_cyc2time(&ptp->tc, ts);
1943 spin_unlock_bh(&ptp->ptp_lock);
1944 memset(skb_hwtstamps(skb), 0,
1945 sizeof(*skb_hwtstamps(skb)));
1946 skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns);
1947 }
1948 }
1949 }
1950 bnxt_deliver_skb(bp, bnapi, skb);
1951 rc = 1;
1952
1953 next_rx:
1954 cpr->rx_packets += 1;
1955 cpr->rx_bytes += len;
1956
1957 next_rx_no_len:
1958 rxr->rx_prod = NEXT_RX(prod);
1959 rxr->rx_next_cons = NEXT_RX(cons);
1960
1961 next_rx_no_prod_no_len:
1962 *raw_cons = tmp_raw_cons;
1963
1964 return rc;
1965 }
1966
1967 /* In netpoll mode, if we are using a combined completion ring, we need to
1968 * discard the rx packets and recycle the buffers.
1969 */
1970 static int bnxt_force_rx_discard(struct bnxt *bp,
1971 struct bnxt_cp_ring_info *cpr,
1972 u32 *raw_cons, u8 *event)
1973 {
1974 u32 tmp_raw_cons = *raw_cons;
1975 struct rx_cmp_ext *rxcmp1;
1976 struct rx_cmp *rxcmp;
1977 u16 cp_cons;
1978 u8 cmp_type;
1979
1980 cp_cons = RING_CMP(tmp_raw_cons);
1981 rxcmp = (struct rx_cmp *)
1982 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1983
1984 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1985 cp_cons = RING_CMP(tmp_raw_cons);
1986 rxcmp1 = (struct rx_cmp_ext *)
1987 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1988
1989 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1990 return -EBUSY;
1991
1992 cmp_type = RX_CMP_TYPE(rxcmp);
1993 if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1994 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1995 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1996 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1997 struct rx_tpa_end_cmp_ext *tpa_end1;
1998
1999 tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1;
2000 tpa_end1->rx_tpa_end_cmp_errors_v2 |=
2001 cpu_to_le32(RX_TPA_END_CMP_ERRORS);
2002 }
2003 return bnxt_rx_pkt(bp, cpr, raw_cons, event);
2004 }
2005
2006 u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx)
2007 {
2008 struct bnxt_fw_health *fw_health = bp->fw_health;
2009 u32 reg = fw_health->regs[reg_idx];
2010 u32 reg_type, reg_off, val = 0;
2011
2012 reg_type = BNXT_FW_HEALTH_REG_TYPE(reg);
2013 reg_off = BNXT_FW_HEALTH_REG_OFF(reg);
2014 switch (reg_type) {
2015 case BNXT_FW_HEALTH_REG_TYPE_CFG:
2016 pci_read_config_dword(bp->pdev, reg_off, &val);
2017 break;
2018 case BNXT_FW_HEALTH_REG_TYPE_GRC:
2019 reg_off = fw_health->mapped_regs[reg_idx];
2020 fallthrough;
2021 case BNXT_FW_HEALTH_REG_TYPE_BAR0:
2022 val = readl(bp->bar0 + reg_off);
2023 break;
2024 case BNXT_FW_HEALTH_REG_TYPE_BAR1:
2025 val = readl(bp->bar1 + reg_off);
2026 break;
2027 }
2028 if (reg_idx == BNXT_FW_RESET_INPROG_REG)
2029 val &= fw_health->fw_reset_inprog_reg_mask;
2030 return val;
2031 }
2032
2033 static u16 bnxt_agg_ring_id_to_grp_idx(struct bnxt *bp, u16 ring_id)
2034 {
2035 int i;
2036
2037 for (i = 0; i < bp->rx_nr_rings; i++) {
2038 u16 grp_idx = bp->rx_ring[i].bnapi->index;
2039 struct bnxt_ring_grp_info *grp_info;
2040
2041 grp_info = &bp->grp_info[grp_idx];
2042 if (grp_info->agg_fw_ring_id == ring_id)
2043 return grp_idx;
2044 }
2045 return INVALID_HW_RING_ID;
2046 }
2047
2048 #define BNXT_GET_EVENT_PORT(data) \
2049 ((data) & \
2050 ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
2051
2052 #define BNXT_EVENT_RING_TYPE(data2) \
2053 ((data2) & \
2054 ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK)
2055
2056 #define BNXT_EVENT_RING_TYPE_RX(data2) \
2057 (BNXT_EVENT_RING_TYPE(data2) == \
2058 ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX)
2059
2060 static int bnxt_async_event_process(struct bnxt *bp,
2061 struct hwrm_async_event_cmpl *cmpl)
2062 {
2063 u16 event_id = le16_to_cpu(cmpl->event_id);
2064 u32 data1 = le32_to_cpu(cmpl->event_data1);
2065 u32 data2 = le32_to_cpu(cmpl->event_data2);
2066
2067 /* TODO CHIMP_FW: Define event id's for link change, error etc */
2068 switch (event_id) {
2069 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
2070 struct bnxt_link_info *link_info = &bp->link_info;
2071
2072 if (BNXT_VF(bp))
2073 goto async_event_process_exit;
2074
2075 /* print unsupported speed warning in forced speed mode only */
2076 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED) &&
2077 (data1 & 0x20000)) {
2078 u16 fw_speed = link_info->force_link_speed;
2079 u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
2080
2081 if (speed != SPEED_UNKNOWN)
2082 netdev_warn(bp->dev, "Link speed %d no longer supported\n",
2083 speed);
2084 }
2085 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event);
2086 }
2087 fallthrough;
2088 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE:
2089 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE:
2090 set_bit(BNXT_LINK_CFG_CHANGE_SP_EVENT, &bp->sp_event);
2091 fallthrough;
2092 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
2093 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
2094 break;
2095 case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
2096 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
2097 break;
2098 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
2099 u16 port_id = BNXT_GET_EVENT_PORT(data1);
2100
2101 if (BNXT_VF(bp))
2102 break;
2103
2104 if (bp->pf.port_id != port_id)
2105 break;
2106
2107 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
2108 break;
2109 }
2110 case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE:
2111 if (BNXT_PF(bp))
2112 goto async_event_process_exit;
2113 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
2114 break;
2115 case ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY: {
2116 char *fatal_str = "non-fatal";
2117
2118 if (!bp->fw_health)
2119 goto async_event_process_exit;
2120
2121 bp->fw_reset_timestamp = jiffies;
2122 bp->fw_reset_min_dsecs = cmpl->timestamp_lo;
2123 if (!bp->fw_reset_min_dsecs)
2124 bp->fw_reset_min_dsecs = BNXT_DFLT_FW_RST_MIN_DSECS;
2125 bp->fw_reset_max_dsecs = le16_to_cpu(cmpl->timestamp_hi);
2126 if (!bp->fw_reset_max_dsecs)
2127 bp->fw_reset_max_dsecs = BNXT_DFLT_FW_RST_MAX_DSECS;
2128 if (EVENT_DATA1_RESET_NOTIFY_FATAL(data1)) {
2129 fatal_str = "fatal";
2130 set_bit(BNXT_STATE_FW_FATAL_COND, &bp->state);
2131 }
2132 netif_warn(bp, hw, bp->dev,
2133 "Firmware %s reset event, data1: 0x%x, data2: 0x%x, min wait %u ms, max wait %u ms\n",
2134 fatal_str, data1, data2,
2135 bp->fw_reset_min_dsecs * 100,
2136 bp->fw_reset_max_dsecs * 100);
2137 set_bit(BNXT_FW_RESET_NOTIFY_SP_EVENT, &bp->sp_event);
2138 break;
2139 }
2140 case ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY: {
2141 struct bnxt_fw_health *fw_health = bp->fw_health;
2142
2143 if (!fw_health)
2144 goto async_event_process_exit;
2145
2146 fw_health->enabled = EVENT_DATA1_RECOVERY_ENABLED(data1);
2147 fw_health->master = EVENT_DATA1_RECOVERY_MASTER_FUNC(data1);
2148 if (!fw_health->enabled) {
2149 netif_info(bp, drv, bp->dev,
2150 "Error recovery info: error recovery[0]\n");
2151 break;
2152 }
2153 fw_health->tmr_multiplier =
2154 DIV_ROUND_UP(fw_health->polling_dsecs * HZ,
2155 bp->current_interval * 10);
2156 fw_health->tmr_counter = fw_health->tmr_multiplier;
2157 fw_health->last_fw_heartbeat =
2158 bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG);
2159 fw_health->last_fw_reset_cnt =
2160 bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG);
2161 netif_info(bp, drv, bp->dev,
2162 "Error recovery info: error recovery[1], master[%d], reset count[%u], health status: 0x%x\n",
2163 fw_health->master, fw_health->last_fw_reset_cnt,
2164 bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG));
2165 goto async_event_process_exit;
2166 }
2167 case ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION:
2168 netif_notice(bp, hw, bp->dev,
2169 "Received firmware debug notification, data1: 0x%x, data2: 0x%x\n",
2170 data1, data2);
2171 goto async_event_process_exit;
2172 case ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG: {
2173 struct bnxt_rx_ring_info *rxr;
2174 u16 grp_idx;
2175
2176 if (bp->flags & BNXT_FLAG_CHIP_P5)
2177 goto async_event_process_exit;
2178
2179 netdev_warn(bp->dev, "Ring monitor event, ring type %lu id 0x%x\n",
2180 BNXT_EVENT_RING_TYPE(data2), data1);
2181 if (!BNXT_EVENT_RING_TYPE_RX(data2))
2182 goto async_event_process_exit;
2183
2184 grp_idx = bnxt_agg_ring_id_to_grp_idx(bp, data1);
2185 if (grp_idx == INVALID_HW_RING_ID) {
2186 netdev_warn(bp->dev, "Unknown RX agg ring id 0x%x\n",
2187 data1);
2188 goto async_event_process_exit;
2189 }
2190 rxr = bp->bnapi[grp_idx]->rx_ring;
2191 bnxt_sched_reset(bp, rxr);
2192 goto async_event_process_exit;
2193 }
2194 case ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST: {
2195 struct bnxt_fw_health *fw_health = bp->fw_health;
2196
2197 netif_notice(bp, hw, bp->dev,
2198 "Received firmware echo request, data1: 0x%x, data2: 0x%x\n",
2199 data1, data2);
2200 if (fw_health) {
2201 fw_health->echo_req_data1 = data1;
2202 fw_health->echo_req_data2 = data2;
2203 set_bit(BNXT_FW_ECHO_REQUEST_SP_EVENT, &bp->sp_event);
2204 break;
2205 }
2206 goto async_event_process_exit;
2207 }
2208 default:
2209 goto async_event_process_exit;
2210 }
2211 bnxt_queue_sp_work(bp);
2212 async_event_process_exit:
2213 bnxt_ulp_async_events(bp, cmpl);
2214 return 0;
2215 }
2216
2217 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
2218 {
2219 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
2220 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
2221 struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
2222 (struct hwrm_fwd_req_cmpl *)txcmp;
2223
2224 switch (cmpl_type) {
2225 case CMPL_BASE_TYPE_HWRM_DONE:
2226 seq_id = le16_to_cpu(h_cmpl->sequence_id);
2227 if (seq_id == bp->hwrm_intr_seq_id)
2228 bp->hwrm_intr_seq_id = (u16)~bp->hwrm_intr_seq_id;
2229 else
2230 netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
2231 break;
2232
2233 case CMPL_BASE_TYPE_HWRM_FWD_REQ:
2234 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
2235
2236 if ((vf_id < bp->pf.first_vf_id) ||
2237 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
2238 netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
2239 vf_id);
2240 return -EINVAL;
2241 }
2242
2243 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
2244 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
2245 bnxt_queue_sp_work(bp);
2246 break;
2247
2248 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
2249 bnxt_async_event_process(bp,
2250 (struct hwrm_async_event_cmpl *)txcmp);
2251 break;
2252
2253 default:
2254 break;
2255 }
2256
2257 return 0;
2258 }
2259
2260 static irqreturn_t bnxt_msix(int irq, void *dev_instance)
2261 {
2262 struct bnxt_napi *bnapi = dev_instance;
2263 struct bnxt *bp = bnapi->bp;
2264 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2265 u32 cons = RING_CMP(cpr->cp_raw_cons);
2266
2267 cpr->event_ctr++;
2268 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
2269 napi_schedule(&bnapi->napi);
2270 return IRQ_HANDLED;
2271 }
2272
2273 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2274 {
2275 u32 raw_cons = cpr->cp_raw_cons;
2276 u16 cons = RING_CMP(raw_cons);
2277 struct tx_cmp *txcmp;
2278
2279 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
2280
2281 return TX_CMP_VALID(txcmp, raw_cons);
2282 }
2283
2284 static irqreturn_t bnxt_inta(int irq, void *dev_instance)
2285 {
2286 struct bnxt_napi *bnapi = dev_instance;
2287 struct bnxt *bp = bnapi->bp;
2288 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2289 u32 cons = RING_CMP(cpr->cp_raw_cons);
2290 u32 int_status;
2291
2292 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
2293
2294 if (!bnxt_has_work(bp, cpr)) {
2295 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
2296 /* return if erroneous interrupt */
2297 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
2298 return IRQ_NONE;
2299 }
2300
2301 /* disable ring IRQ */
2302 BNXT_CP_DB_IRQ_DIS(cpr->cp_db.doorbell);
2303
2304 /* Return here if interrupt is shared and is disabled. */
2305 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2306 return IRQ_HANDLED;
2307
2308 napi_schedule(&bnapi->napi);
2309 return IRQ_HANDLED;
2310 }
2311
2312 static int __bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
2313 int budget)
2314 {
2315 struct bnxt_napi *bnapi = cpr->bnapi;
2316 u32 raw_cons = cpr->cp_raw_cons;
2317 u32 cons;
2318 int tx_pkts = 0;
2319 int rx_pkts = 0;
2320 u8 event = 0;
2321 struct tx_cmp *txcmp;
2322
2323 cpr->has_more_work = 0;
2324 cpr->had_work_done = 1;
2325 while (1) {
2326 int rc;
2327
2328 cons = RING_CMP(raw_cons);
2329 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
2330
2331 if (!TX_CMP_VALID(txcmp, raw_cons))
2332 break;
2333
2334 /* The valid test of the entry must be done first before
2335 * reading any further.
2336 */
2337 dma_rmb();
2338 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
2339 tx_pkts++;
2340 /* return full budget so NAPI will complete. */
2341 if (unlikely(tx_pkts > bp->tx_wake_thresh)) {
2342 rx_pkts = budget;
2343 raw_cons = NEXT_RAW_CMP(raw_cons);
2344 if (budget)
2345 cpr->has_more_work = 1;
2346 break;
2347 }
2348 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
2349 if (likely(budget))
2350 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event);
2351 else
2352 rc = bnxt_force_rx_discard(bp, cpr, &raw_cons,
2353 &event);
2354 if (likely(rc >= 0))
2355 rx_pkts += rc;
2356 /* Increment rx_pkts when rc is -ENOMEM to count towards
2357 * the NAPI budget. Otherwise, we may potentially loop
2358 * here forever if we consistently cannot allocate
2359 * buffers.
2360 */
2361 else if (rc == -ENOMEM && budget)
2362 rx_pkts++;
2363 else if (rc == -EBUSY) /* partial completion */
2364 break;
2365 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
2366 CMPL_BASE_TYPE_HWRM_DONE) ||
2367 (TX_CMP_TYPE(txcmp) ==
2368 CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
2369 (TX_CMP_TYPE(txcmp) ==
2370 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
2371 bnxt_hwrm_handler(bp, txcmp);
2372 }
2373 raw_cons = NEXT_RAW_CMP(raw_cons);
2374
2375 if (rx_pkts && rx_pkts == budget) {
2376 cpr->has_more_work = 1;
2377 break;
2378 }
2379 }
2380
2381 if (event & BNXT_REDIRECT_EVENT)
2382 xdp_do_flush_map();
2383
2384 if (event & BNXT_TX_EVENT) {
2385 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
2386 u16 prod = txr->tx_prod;
2387
2388 /* Sync BD data before updating doorbell */
2389 wmb();
2390
2391 bnxt_db_write_relaxed(bp, &txr->tx_db, prod);
2392 }
2393
2394 cpr->cp_raw_cons = raw_cons;
2395 bnapi->tx_pkts += tx_pkts;
2396 bnapi->events |= event;
2397 return rx_pkts;
2398 }
2399
2400 static void __bnxt_poll_work_done(struct bnxt *bp, struct bnxt_napi *bnapi)
2401 {
2402 if (bnapi->tx_pkts) {
2403 bnapi->tx_int(bp, bnapi, bnapi->tx_pkts);
2404 bnapi->tx_pkts = 0;
2405 }
2406
2407 if ((bnapi->events & BNXT_RX_EVENT) && !(bnapi->in_reset)) {
2408 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
2409
2410 if (bnapi->events & BNXT_AGG_EVENT)
2411 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
2412 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
2413 }
2414 bnapi->events = 0;
2415 }
2416
2417 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
2418 int budget)
2419 {
2420 struct bnxt_napi *bnapi = cpr->bnapi;
2421 int rx_pkts;
2422
2423 rx_pkts = __bnxt_poll_work(bp, cpr, budget);
2424
2425 /* ACK completion ring before freeing tx ring and producing new
2426 * buffers in rx/agg rings to prevent overflowing the completion
2427 * ring.
2428 */
2429 bnxt_db_cq(bp, &cpr->cp_db, cpr->cp_raw_cons);
2430
2431 __bnxt_poll_work_done(bp, bnapi);
2432 return rx_pkts;
2433 }
2434
2435 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget)
2436 {
2437 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2438 struct bnxt *bp = bnapi->bp;
2439 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2440 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
2441 struct tx_cmp *txcmp;
2442 struct rx_cmp_ext *rxcmp1;
2443 u32 cp_cons, tmp_raw_cons;
2444 u32 raw_cons = cpr->cp_raw_cons;
2445 u32 rx_pkts = 0;
2446 u8 event = 0;
2447
2448 while (1) {
2449 int rc;
2450
2451 cp_cons = RING_CMP(raw_cons);
2452 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2453
2454 if (!TX_CMP_VALID(txcmp, raw_cons))
2455 break;
2456
2457 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
2458 tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
2459 cp_cons = RING_CMP(tmp_raw_cons);
2460 rxcmp1 = (struct rx_cmp_ext *)
2461 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2462
2463 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
2464 break;
2465
2466 /* force an error to recycle the buffer */
2467 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
2468 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
2469
2470 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event);
2471 if (likely(rc == -EIO) && budget)
2472 rx_pkts++;
2473 else if (rc == -EBUSY) /* partial completion */
2474 break;
2475 } else if (unlikely(TX_CMP_TYPE(txcmp) ==
2476 CMPL_BASE_TYPE_HWRM_DONE)) {
2477 bnxt_hwrm_handler(bp, txcmp);
2478 } else {
2479 netdev_err(bp->dev,
2480 "Invalid completion received on special ring\n");
2481 }
2482 raw_cons = NEXT_RAW_CMP(raw_cons);
2483
2484 if (rx_pkts == budget)
2485 break;
2486 }
2487
2488 cpr->cp_raw_cons = raw_cons;
2489 BNXT_DB_CQ(&cpr->cp_db, cpr->cp_raw_cons);
2490 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
2491
2492 if (event & BNXT_AGG_EVENT)
2493 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
2494
2495 if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) {
2496 napi_complete_done(napi, rx_pkts);
2497 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2498 }
2499 return rx_pkts;
2500 }
2501
2502 static int bnxt_poll(struct napi_struct *napi, int budget)
2503 {
2504 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2505 struct bnxt *bp = bnapi->bp;
2506 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2507 int work_done = 0;
2508
2509 if (unlikely(test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))) {
2510 napi_complete(napi);
2511 return 0;
2512 }
2513 while (1) {
2514 work_done += bnxt_poll_work(bp, cpr, budget - work_done);
2515
2516 if (work_done >= budget) {
2517 if (!budget)
2518 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2519 break;
2520 }
2521
2522 if (!bnxt_has_work(bp, cpr)) {
2523 if (napi_complete_done(napi, work_done))
2524 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2525 break;
2526 }
2527 }
2528 if (bp->flags & BNXT_FLAG_DIM) {
2529 struct dim_sample dim_sample = {};
2530
2531 dim_update_sample(cpr->event_ctr,
2532 cpr->rx_packets,
2533 cpr->rx_bytes,
2534 &dim_sample);
2535 net_dim(&cpr->dim, dim_sample);
2536 }
2537 return work_done;
2538 }
2539
2540 static int __bnxt_poll_cqs(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
2541 {
2542 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2543 int i, work_done = 0;
2544
2545 for (i = 0; i < 2; i++) {
2546 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i];
2547
2548 if (cpr2) {
2549 work_done += __bnxt_poll_work(bp, cpr2,
2550 budget - work_done);
2551 cpr->has_more_work |= cpr2->has_more_work;
2552 }
2553 }
2554 return work_done;
2555 }
2556
2557 static void __bnxt_poll_cqs_done(struct bnxt *bp, struct bnxt_napi *bnapi,
2558 u64 dbr_type)
2559 {
2560 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2561 int i;
2562
2563 for (i = 0; i < 2; i++) {
2564 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i];
2565 struct bnxt_db_info *db;
2566
2567 if (cpr2 && cpr2->had_work_done) {
2568 db = &cpr2->cp_db;
2569 writeq(db->db_key64 | dbr_type |
2570 RING_CMP(cpr2->cp_raw_cons), db->doorbell);
2571 cpr2->had_work_done = 0;
2572 }
2573 }
2574 __bnxt_poll_work_done(bp, bnapi);
2575 }
2576
2577 static int bnxt_poll_p5(struct napi_struct *napi, int budget)
2578 {
2579 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2580 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2581 u32 raw_cons = cpr->cp_raw_cons;
2582 struct bnxt *bp = bnapi->bp;
2583 struct nqe_cn *nqcmp;
2584 int work_done = 0;
2585 u32 cons;
2586
2587 if (unlikely(test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))) {
2588 napi_complete(napi);
2589 return 0;
2590 }
2591 if (cpr->has_more_work) {
2592 cpr->has_more_work = 0;
2593 work_done = __bnxt_poll_cqs(bp, bnapi, budget);
2594 }
2595 while (1) {
2596 cons = RING_CMP(raw_cons);
2597 nqcmp = &cpr->nq_desc_ring[CP_RING(cons)][CP_IDX(cons)];
2598
2599 if (!NQ_CMP_VALID(nqcmp, raw_cons)) {
2600 if (cpr->has_more_work)
2601 break;
2602
2603 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL);
2604 cpr->cp_raw_cons = raw_cons;
2605 if (napi_complete_done(napi, work_done))
2606 BNXT_DB_NQ_ARM_P5(&cpr->cp_db,
2607 cpr->cp_raw_cons);
2608 return work_done;
2609 }
2610
2611 /* The valid test of the entry must be done first before
2612 * reading any further.
2613 */
2614 dma_rmb();
2615
2616 if (nqcmp->type == cpu_to_le16(NQ_CN_TYPE_CQ_NOTIFICATION)) {
2617 u32 idx = le32_to_cpu(nqcmp->cq_handle_low);
2618 struct bnxt_cp_ring_info *cpr2;
2619
2620 cpr2 = cpr->cp_ring_arr[idx];
2621 work_done += __bnxt_poll_work(bp, cpr2,
2622 budget - work_done);
2623 cpr->has_more_work |= cpr2->has_more_work;
2624 } else {
2625 bnxt_hwrm_handler(bp, (struct tx_cmp *)nqcmp);
2626 }
2627 raw_cons = NEXT_RAW_CMP(raw_cons);
2628 }
2629 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ);
2630 if (raw_cons != cpr->cp_raw_cons) {
2631 cpr->cp_raw_cons = raw_cons;
2632 BNXT_DB_NQ_P5(&cpr->cp_db, raw_cons);
2633 }
2634 return work_done;
2635 }
2636
2637 static void bnxt_free_tx_skbs(struct bnxt *bp)
2638 {
2639 int i, max_idx;
2640 struct pci_dev *pdev = bp->pdev;
2641
2642 if (!bp->tx_ring)
2643 return;
2644
2645 max_idx = bp->tx_nr_pages * TX_DESC_CNT;
2646 for (i = 0; i < bp->tx_nr_rings; i++) {
2647 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2648 int j;
2649
2650 for (j = 0; j < max_idx;) {
2651 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
2652 struct sk_buff *skb;
2653 int k, last;
2654
2655 if (i < bp->tx_nr_rings_xdp &&
2656 tx_buf->action == XDP_REDIRECT) {
2657 dma_unmap_single(&pdev->dev,
2658 dma_unmap_addr(tx_buf, mapping),
2659 dma_unmap_len(tx_buf, len),
2660 PCI_DMA_TODEVICE);
2661 xdp_return_frame(tx_buf->xdpf);
2662 tx_buf->action = 0;
2663 tx_buf->xdpf = NULL;
2664 j++;
2665 continue;
2666 }
2667
2668 skb = tx_buf->skb;
2669 if (!skb) {
2670 j++;
2671 continue;
2672 }
2673
2674 tx_buf->skb = NULL;
2675
2676 if (tx_buf->is_push) {
2677 dev_kfree_skb(skb);
2678 j += 2;
2679 continue;
2680 }
2681
2682 dma_unmap_single(&pdev->dev,
2683 dma_unmap_addr(tx_buf, mapping),
2684 skb_headlen(skb),
2685 PCI_DMA_TODEVICE);
2686
2687 last = tx_buf->nr_frags;
2688 j += 2;
2689 for (k = 0; k < last; k++, j++) {
2690 int ring_idx = j & bp->tx_ring_mask;
2691 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
2692
2693 tx_buf = &txr->tx_buf_ring[ring_idx];
2694 dma_unmap_page(
2695 &pdev->dev,
2696 dma_unmap_addr(tx_buf, mapping),
2697 skb_frag_size(frag), PCI_DMA_TODEVICE);
2698 }
2699 dev_kfree_skb(skb);
2700 }
2701 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
2702 }
2703 }
2704
2705 static void bnxt_free_one_rx_ring_skbs(struct bnxt *bp, int ring_nr)
2706 {
2707 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[ring_nr];
2708 struct pci_dev *pdev = bp->pdev;
2709 struct bnxt_tpa_idx_map *map;
2710 int i, max_idx, max_agg_idx;
2711
2712 max_idx = bp->rx_nr_pages * RX_DESC_CNT;
2713 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
2714 if (!rxr->rx_tpa)
2715 goto skip_rx_tpa_free;
2716
2717 for (i = 0; i < bp->max_tpa; i++) {
2718 struct bnxt_tpa_info *tpa_info = &rxr->rx_tpa[i];
2719 u8 *data = tpa_info->data;
2720
2721 if (!data)
2722 continue;
2723
2724 dma_unmap_single_attrs(&pdev->dev, tpa_info->mapping,
2725 bp->rx_buf_use_size, bp->rx_dir,
2726 DMA_ATTR_WEAK_ORDERING);
2727
2728 tpa_info->data = NULL;
2729
2730 kfree(data);
2731 }
2732
2733 skip_rx_tpa_free:
2734 for (i = 0; i < max_idx; i++) {
2735 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[i];
2736 dma_addr_t mapping = rx_buf->mapping;
2737 void *data = rx_buf->data;
2738
2739 if (!data)
2740 continue;
2741
2742 rx_buf->data = NULL;
2743 if (BNXT_RX_PAGE_MODE(bp)) {
2744 mapping -= bp->rx_dma_offset;
2745 dma_unmap_page_attrs(&pdev->dev, mapping, PAGE_SIZE,
2746 bp->rx_dir,
2747 DMA_ATTR_WEAK_ORDERING);
2748 page_pool_recycle_direct(rxr->page_pool, data);
2749 } else {
2750 dma_unmap_single_attrs(&pdev->dev, mapping,
2751 bp->rx_buf_use_size, bp->rx_dir,
2752 DMA_ATTR_WEAK_ORDERING);
2753 kfree(data);
2754 }
2755 }
2756 for (i = 0; i < max_agg_idx; i++) {
2757 struct bnxt_sw_rx_agg_bd *rx_agg_buf = &rxr->rx_agg_ring[i];
2758 struct page *page = rx_agg_buf->page;
2759
2760 if (!page)
2761 continue;
2762
2763 dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping,
2764 BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE,
2765 DMA_ATTR_WEAK_ORDERING);
2766
2767 rx_agg_buf->page = NULL;
2768 __clear_bit(i, rxr->rx_agg_bmap);
2769
2770 __free_page(page);
2771 }
2772 if (rxr->rx_page) {
2773 __free_page(rxr->rx_page);
2774 rxr->rx_page = NULL;
2775 }
2776 map = rxr->rx_tpa_idx_map;
2777 if (map)
2778 memset(map->agg_idx_bmap, 0, sizeof(map->agg_idx_bmap));
2779 }
2780
2781 static void bnxt_free_rx_skbs(struct bnxt *bp)
2782 {
2783 int i;
2784
2785 if (!bp->rx_ring)
2786 return;
2787
2788 for (i = 0; i < bp->rx_nr_rings; i++)
2789 bnxt_free_one_rx_ring_skbs(bp, i);
2790 }
2791
2792 static void bnxt_free_skbs(struct bnxt *bp)
2793 {
2794 bnxt_free_tx_skbs(bp);
2795 bnxt_free_rx_skbs(bp);
2796 }
2797
2798 static void bnxt_init_ctx_mem(struct bnxt_mem_init *mem_init, void *p, int len)
2799 {
2800 u8 init_val = mem_init->init_val;
2801 u16 offset = mem_init->offset;
2802 u8 *p2 = p;
2803 int i;
2804
2805 if (!init_val)
2806 return;
2807 if (offset == BNXT_MEM_INVALID_OFFSET) {
2808 memset(p, init_val, len);
2809 return;
2810 }
2811 for (i = 0; i < len; i += mem_init->size)
2812 *(p2 + i + offset) = init_val;
2813 }
2814
2815 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem)
2816 {
2817 struct pci_dev *pdev = bp->pdev;
2818 int i;
2819
2820 for (i = 0; i < rmem->nr_pages; i++) {
2821 if (!rmem->pg_arr[i])
2822 continue;
2823
2824 dma_free_coherent(&pdev->dev, rmem->page_size,
2825 rmem->pg_arr[i], rmem->dma_arr[i]);
2826
2827 rmem->pg_arr[i] = NULL;
2828 }
2829 if (rmem->pg_tbl) {
2830 size_t pg_tbl_size = rmem->nr_pages * 8;
2831
2832 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG)
2833 pg_tbl_size = rmem->page_size;
2834 dma_free_coherent(&pdev->dev, pg_tbl_size,
2835 rmem->pg_tbl, rmem->pg_tbl_map);
2836 rmem->pg_tbl = NULL;
2837 }
2838 if (rmem->vmem_size && *rmem->vmem) {
2839 vfree(*rmem->vmem);
2840 *rmem->vmem = NULL;
2841 }
2842 }
2843
2844 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem)
2845 {
2846 struct pci_dev *pdev = bp->pdev;
2847 u64 valid_bit = 0;
2848 int i;
2849
2850 if (rmem->flags & (BNXT_RMEM_VALID_PTE_FLAG | BNXT_RMEM_RING_PTE_FLAG))
2851 valid_bit = PTU_PTE_VALID;
2852 if ((rmem->nr_pages > 1 || rmem->depth > 0) && !rmem->pg_tbl) {
2853 size_t pg_tbl_size = rmem->nr_pages * 8;
2854
2855 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG)
2856 pg_tbl_size = rmem->page_size;
2857 rmem->pg_tbl = dma_alloc_coherent(&pdev->dev, pg_tbl_size,
2858 &rmem->pg_tbl_map,
2859 GFP_KERNEL);
2860 if (!rmem->pg_tbl)
2861 return -ENOMEM;
2862 }
2863
2864 for (i = 0; i < rmem->nr_pages; i++) {
2865 u64 extra_bits = valid_bit;
2866
2867 rmem->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
2868 rmem->page_size,
2869 &rmem->dma_arr[i],
2870 GFP_KERNEL);
2871 if (!rmem->pg_arr[i])
2872 return -ENOMEM;
2873
2874 if (rmem->mem_init)
2875 bnxt_init_ctx_mem(rmem->mem_init, rmem->pg_arr[i],
2876 rmem->page_size);
2877 if (rmem->nr_pages > 1 || rmem->depth > 0) {
2878 if (i == rmem->nr_pages - 2 &&
2879 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
2880 extra_bits |= PTU_PTE_NEXT_TO_LAST;
2881 else if (i == rmem->nr_pages - 1 &&
2882 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
2883 extra_bits |= PTU_PTE_LAST;
2884 rmem->pg_tbl[i] =
2885 cpu_to_le64(rmem->dma_arr[i] | extra_bits);
2886 }
2887 }
2888
2889 if (rmem->vmem_size) {
2890 *rmem->vmem = vzalloc(rmem->vmem_size);
2891 if (!(*rmem->vmem))
2892 return -ENOMEM;
2893 }
2894 return 0;
2895 }
2896
2897 static void bnxt_free_tpa_info(struct bnxt *bp)
2898 {
2899 int i;
2900
2901 for (i = 0; i < bp->rx_nr_rings; i++) {
2902 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2903
2904 kfree(rxr->rx_tpa_idx_map);
2905 rxr->rx_tpa_idx_map = NULL;
2906 if (rxr->rx_tpa) {
2907 kfree(rxr->rx_tpa[0].agg_arr);
2908 rxr->rx_tpa[0].agg_arr = NULL;
2909 }
2910 kfree(rxr->rx_tpa);
2911 rxr->rx_tpa = NULL;
2912 }
2913 }
2914
2915 static int bnxt_alloc_tpa_info(struct bnxt *bp)
2916 {
2917 int i, j, total_aggs = 0;
2918
2919 bp->max_tpa = MAX_TPA;
2920 if (bp->flags & BNXT_FLAG_CHIP_P5) {
2921 if (!bp->max_tpa_v2)
2922 return 0;
2923 bp->max_tpa = max_t(u16, bp->max_tpa_v2, MAX_TPA_P5);
2924 total_aggs = bp->max_tpa * MAX_SKB_FRAGS;
2925 }
2926
2927 for (i = 0; i < bp->rx_nr_rings; i++) {
2928 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2929 struct rx_agg_cmp *agg;
2930
2931 rxr->rx_tpa = kcalloc(bp->max_tpa, sizeof(struct bnxt_tpa_info),
2932 GFP_KERNEL);
2933 if (!rxr->rx_tpa)
2934 return -ENOMEM;
2935
2936 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
2937 continue;
2938 agg = kcalloc(total_aggs, sizeof(*agg), GFP_KERNEL);
2939 rxr->rx_tpa[0].agg_arr = agg;
2940 if (!agg)
2941 return -ENOMEM;
2942 for (j = 1; j < bp->max_tpa; j++)
2943 rxr->rx_tpa[j].agg_arr = agg + j * MAX_SKB_FRAGS;
2944 rxr->rx_tpa_idx_map = kzalloc(sizeof(*rxr->rx_tpa_idx_map),
2945 GFP_KERNEL);
2946 if (!rxr->rx_tpa_idx_map)
2947 return -ENOMEM;
2948 }
2949 return 0;
2950 }
2951
2952 static void bnxt_free_rx_rings(struct bnxt *bp)
2953 {
2954 int i;
2955
2956 if (!bp->rx_ring)
2957 return;
2958
2959 bnxt_free_tpa_info(bp);
2960 for (i = 0; i < bp->rx_nr_rings; i++) {
2961 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2962 struct bnxt_ring_struct *ring;
2963
2964 if (rxr->xdp_prog)
2965 bpf_prog_put(rxr->xdp_prog);
2966
2967 if (xdp_rxq_info_is_reg(&rxr->xdp_rxq))
2968 xdp_rxq_info_unreg(&rxr->xdp_rxq);
2969
2970 page_pool_destroy(rxr->page_pool);
2971 rxr->page_pool = NULL;
2972
2973 kfree(rxr->rx_agg_bmap);
2974 rxr->rx_agg_bmap = NULL;
2975
2976 ring = &rxr->rx_ring_struct;
2977 bnxt_free_ring(bp, &ring->ring_mem);
2978
2979 ring = &rxr->rx_agg_ring_struct;
2980 bnxt_free_ring(bp, &ring->ring_mem);
2981 }
2982 }
2983
2984 static int bnxt_alloc_rx_page_pool(struct bnxt *bp,
2985 struct bnxt_rx_ring_info *rxr)
2986 {
2987 struct page_pool_params pp = { 0 };
2988
2989 pp.pool_size = bp->rx_ring_size;
2990 pp.nid = dev_to_node(&bp->pdev->dev);
2991 pp.dev = &bp->pdev->dev;
2992 pp.dma_dir = DMA_BIDIRECTIONAL;
2993
2994 rxr->page_pool = page_pool_create(&pp);
2995 if (IS_ERR(rxr->page_pool)) {
2996 int err = PTR_ERR(rxr->page_pool);
2997
2998 rxr->page_pool = NULL;
2999 return err;
3000 }
3001 return 0;
3002 }
3003
3004 static int bnxt_alloc_rx_rings(struct bnxt *bp)
3005 {
3006 int i, rc = 0, agg_rings = 0;
3007
3008 if (!bp->rx_ring)
3009 return -ENOMEM;
3010
3011 if (bp->flags & BNXT_FLAG_AGG_RINGS)
3012 agg_rings = 1;
3013
3014 for (i = 0; i < bp->rx_nr_rings; i++) {
3015 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3016 struct bnxt_ring_struct *ring;
3017
3018 ring = &rxr->rx_ring_struct;
3019
3020 rc = bnxt_alloc_rx_page_pool(bp, rxr);
3021 if (rc)
3022 return rc;
3023
3024 rc = xdp_rxq_info_reg(&rxr->xdp_rxq, bp->dev, i, 0);
3025 if (rc < 0)
3026 return rc;
3027
3028 rc = xdp_rxq_info_reg_mem_model(&rxr->xdp_rxq,
3029 MEM_TYPE_PAGE_POOL,
3030 rxr->page_pool);
3031 if (rc) {
3032 xdp_rxq_info_unreg(&rxr->xdp_rxq);
3033 return rc;
3034 }
3035
3036 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
3037 if (rc)
3038 return rc;
3039
3040 ring->grp_idx = i;
3041 if (agg_rings) {
3042 u16 mem_size;
3043
3044 ring = &rxr->rx_agg_ring_struct;
3045 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
3046 if (rc)
3047 return rc;
3048
3049 ring->grp_idx = i;
3050 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
3051 mem_size = rxr->rx_agg_bmap_size / 8;
3052 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
3053 if (!rxr->rx_agg_bmap)
3054 return -ENOMEM;
3055 }
3056 }
3057 if (bp->flags & BNXT_FLAG_TPA)
3058 rc = bnxt_alloc_tpa_info(bp);
3059 return rc;
3060 }
3061
3062 static void bnxt_free_tx_rings(struct bnxt *bp)
3063 {
3064 int i;
3065 struct pci_dev *pdev = bp->pdev;
3066
3067 if (!bp->tx_ring)
3068 return;
3069
3070 for (i = 0; i < bp->tx_nr_rings; i++) {
3071 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3072 struct bnxt_ring_struct *ring;
3073
3074 if (txr->tx_push) {
3075 dma_free_coherent(&pdev->dev, bp->tx_push_size,
3076 txr->tx_push, txr->tx_push_mapping);
3077 txr->tx_push = NULL;
3078 }
3079
3080 ring = &txr->tx_ring_struct;
3081
3082 bnxt_free_ring(bp, &ring->ring_mem);
3083 }
3084 }
3085
3086 static int bnxt_alloc_tx_rings(struct bnxt *bp)
3087 {
3088 int i, j, rc;
3089 struct pci_dev *pdev = bp->pdev;
3090
3091 bp->tx_push_size = 0;
3092 if (bp->tx_push_thresh) {
3093 int push_size;
3094
3095 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
3096 bp->tx_push_thresh);
3097
3098 if (push_size > 256) {
3099 push_size = 0;
3100 bp->tx_push_thresh = 0;
3101 }
3102
3103 bp->tx_push_size = push_size;
3104 }
3105
3106 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
3107 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3108 struct bnxt_ring_struct *ring;
3109 u8 qidx;
3110
3111 ring = &txr->tx_ring_struct;
3112
3113 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
3114 if (rc)
3115 return rc;
3116
3117 ring->grp_idx = txr->bnapi->index;
3118 if (bp->tx_push_size) {
3119 dma_addr_t mapping;
3120
3121 /* One pre-allocated DMA buffer to backup
3122 * TX push operation
3123 */
3124 txr->tx_push = dma_alloc_coherent(&pdev->dev,
3125 bp->tx_push_size,
3126 &txr->tx_push_mapping,
3127 GFP_KERNEL);
3128
3129 if (!txr->tx_push)
3130 return -ENOMEM;
3131
3132 mapping = txr->tx_push_mapping +
3133 sizeof(struct tx_push_bd);
3134 txr->data_mapping = cpu_to_le64(mapping);
3135 }
3136 qidx = bp->tc_to_qidx[j];
3137 ring->queue_id = bp->q_info[qidx].queue_id;
3138 if (i < bp->tx_nr_rings_xdp)
3139 continue;
3140 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
3141 j++;
3142 }
3143 return 0;
3144 }
3145
3146 static void bnxt_free_cp_rings(struct bnxt *bp)
3147 {
3148 int i;
3149
3150 if (!bp->bnapi)
3151 return;
3152
3153 for (i = 0; i < bp->cp_nr_rings; i++) {
3154 struct bnxt_napi *bnapi = bp->bnapi[i];
3155 struct bnxt_cp_ring_info *cpr;
3156 struct bnxt_ring_struct *ring;
3157 int j;
3158
3159 if (!bnapi)
3160 continue;
3161
3162 cpr = &bnapi->cp_ring;
3163 ring = &cpr->cp_ring_struct;
3164
3165 bnxt_free_ring(bp, &ring->ring_mem);
3166
3167 for (j = 0; j < 2; j++) {
3168 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
3169
3170 if (cpr2) {
3171 ring = &cpr2->cp_ring_struct;
3172 bnxt_free_ring(bp, &ring->ring_mem);
3173 kfree(cpr2);
3174 cpr->cp_ring_arr[j] = NULL;
3175 }
3176 }
3177 }
3178 }
3179
3180 static struct bnxt_cp_ring_info *bnxt_alloc_cp_sub_ring(struct bnxt *bp)
3181 {
3182 struct bnxt_ring_mem_info *rmem;
3183 struct bnxt_ring_struct *ring;
3184 struct bnxt_cp_ring_info *cpr;
3185 int rc;
3186
3187 cpr = kzalloc(sizeof(*cpr), GFP_KERNEL);
3188 if (!cpr)
3189 return NULL;
3190
3191 ring = &cpr->cp_ring_struct;
3192 rmem = &ring->ring_mem;
3193 rmem->nr_pages = bp->cp_nr_pages;
3194 rmem->page_size = HW_CMPD_RING_SIZE;
3195 rmem->pg_arr = (void **)cpr->cp_desc_ring;
3196 rmem->dma_arr = cpr->cp_desc_mapping;
3197 rmem->flags = BNXT_RMEM_RING_PTE_FLAG;
3198 rc = bnxt_alloc_ring(bp, rmem);
3199 if (rc) {
3200 bnxt_free_ring(bp, rmem);
3201 kfree(cpr);
3202 cpr = NULL;
3203 }
3204 return cpr;
3205 }
3206
3207 static int bnxt_alloc_cp_rings(struct bnxt *bp)
3208 {
3209 bool sh = !!(bp->flags & BNXT_FLAG_SHARED_RINGS);
3210 int i, rc, ulp_base_vec, ulp_msix;
3211
3212 ulp_msix = bnxt_get_ulp_msix_num(bp);
3213 ulp_base_vec = bnxt_get_ulp_msix_base(bp);
3214 for (i = 0; i < bp->cp_nr_rings; i++) {
3215 struct bnxt_napi *bnapi = bp->bnapi[i];
3216 struct bnxt_cp_ring_info *cpr;
3217 struct bnxt_ring_struct *ring;
3218
3219 if (!bnapi)
3220 continue;
3221
3222 cpr = &bnapi->cp_ring;
3223 cpr->bnapi = bnapi;
3224 ring = &cpr->cp_ring_struct;
3225
3226 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
3227 if (rc)
3228 return rc;
3229
3230 if (ulp_msix && i >= ulp_base_vec)
3231 ring->map_idx = i + ulp_msix;
3232 else
3233 ring->map_idx = i;
3234
3235 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
3236 continue;
3237
3238 if (i < bp->rx_nr_rings) {
3239 struct bnxt_cp_ring_info *cpr2 =
3240 bnxt_alloc_cp_sub_ring(bp);
3241
3242 cpr->cp_ring_arr[BNXT_RX_HDL] = cpr2;
3243 if (!cpr2)
3244 return -ENOMEM;
3245 cpr2->bnapi = bnapi;
3246 }
3247 if ((sh && i < bp->tx_nr_rings) ||
3248 (!sh && i >= bp->rx_nr_rings)) {
3249 struct bnxt_cp_ring_info *cpr2 =
3250 bnxt_alloc_cp_sub_ring(bp);
3251
3252 cpr->cp_ring_arr[BNXT_TX_HDL] = cpr2;
3253 if (!cpr2)
3254 return -ENOMEM;
3255 cpr2->bnapi = bnapi;
3256 }
3257 }
3258 return 0;
3259 }
3260
3261 static void bnxt_init_ring_struct(struct bnxt *bp)
3262 {
3263 int i;
3264
3265 for (i = 0; i < bp->cp_nr_rings; i++) {
3266 struct bnxt_napi *bnapi = bp->bnapi[i];
3267 struct bnxt_ring_mem_info *rmem;
3268 struct bnxt_cp_ring_info *cpr;
3269 struct bnxt_rx_ring_info *rxr;
3270 struct bnxt_tx_ring_info *txr;
3271 struct bnxt_ring_struct *ring;
3272
3273 if (!bnapi)
3274 continue;
3275
3276 cpr = &bnapi->cp_ring;
3277 ring = &cpr->cp_ring_struct;
3278 rmem = &ring->ring_mem;
3279 rmem->nr_pages = bp->cp_nr_pages;
3280 rmem->page_size = HW_CMPD_RING_SIZE;
3281 rmem->pg_arr = (void **)cpr->cp_desc_ring;
3282 rmem->dma_arr = cpr->cp_desc_mapping;
3283 rmem->vmem_size = 0;
3284
3285 rxr = bnapi->rx_ring;
3286 if (!rxr)
3287 goto skip_rx;
3288
3289 ring = &rxr->rx_ring_struct;
3290 rmem = &ring->ring_mem;
3291 rmem->nr_pages = bp->rx_nr_pages;
3292 rmem->page_size = HW_RXBD_RING_SIZE;
3293 rmem->pg_arr = (void **)rxr->rx_desc_ring;
3294 rmem->dma_arr = rxr->rx_desc_mapping;
3295 rmem->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
3296 rmem->vmem = (void **)&rxr->rx_buf_ring;
3297
3298 ring = &rxr->rx_agg_ring_struct;
3299 rmem = &ring->ring_mem;
3300 rmem->nr_pages = bp->rx_agg_nr_pages;
3301 rmem->page_size = HW_RXBD_RING_SIZE;
3302 rmem->pg_arr = (void **)rxr->rx_agg_desc_ring;
3303 rmem->dma_arr = rxr->rx_agg_desc_mapping;
3304 rmem->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
3305 rmem->vmem = (void **)&rxr->rx_agg_ring;
3306
3307 skip_rx:
3308 txr = bnapi->tx_ring;
3309 if (!txr)
3310 continue;
3311
3312 ring = &txr->tx_ring_struct;
3313 rmem = &ring->ring_mem;
3314 rmem->nr_pages = bp->tx_nr_pages;
3315 rmem->page_size = HW_RXBD_RING_SIZE;
3316 rmem->pg_arr = (void **)txr->tx_desc_ring;
3317 rmem->dma_arr = txr->tx_desc_mapping;
3318 rmem->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
3319 rmem->vmem = (void **)&txr->tx_buf_ring;
3320 }
3321 }
3322
3323 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
3324 {
3325 int i;
3326 u32 prod;
3327 struct rx_bd **rx_buf_ring;
3328
3329 rx_buf_ring = (struct rx_bd **)ring->ring_mem.pg_arr;
3330 for (i = 0, prod = 0; i < ring->ring_mem.nr_pages; i++) {
3331 int j;
3332 struct rx_bd *rxbd;
3333
3334 rxbd = rx_buf_ring[i];
3335 if (!rxbd)
3336 continue;
3337
3338 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
3339 rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
3340 rxbd->rx_bd_opaque = prod;
3341 }
3342 }
3343 }
3344
3345 static int bnxt_alloc_one_rx_ring(struct bnxt *bp, int ring_nr)
3346 {
3347 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[ring_nr];
3348 struct net_device *dev = bp->dev;
3349 u32 prod;
3350 int i;
3351
3352 prod = rxr->rx_prod;
3353 for (i = 0; i < bp->rx_ring_size; i++) {
3354 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL)) {
3355 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
3356 ring_nr, i, bp->rx_ring_size);
3357 break;
3358 }
3359 prod = NEXT_RX(prod);
3360 }
3361 rxr->rx_prod = prod;
3362
3363 if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
3364 return 0;
3365
3366 prod = rxr->rx_agg_prod;
3367 for (i = 0; i < bp->rx_agg_ring_size; i++) {
3368 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL)) {
3369 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
3370 ring_nr, i, bp->rx_ring_size);
3371 break;
3372 }
3373 prod = NEXT_RX_AGG(prod);
3374 }
3375 rxr->rx_agg_prod = prod;
3376
3377 if (rxr->rx_tpa) {
3378 dma_addr_t mapping;
3379 u8 *data;
3380
3381 for (i = 0; i < bp->max_tpa; i++) {
3382 data = __bnxt_alloc_rx_data(bp, &mapping, GFP_KERNEL);
3383 if (!data)
3384 return -ENOMEM;
3385
3386 rxr->rx_tpa[i].data = data;
3387 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset;
3388 rxr->rx_tpa[i].mapping = mapping;
3389 }
3390 }
3391 return 0;
3392 }
3393
3394 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
3395 {
3396 struct bnxt_rx_ring_info *rxr;
3397 struct bnxt_ring_struct *ring;
3398 u32 type;
3399
3400 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
3401 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
3402
3403 if (NET_IP_ALIGN == 2)
3404 type |= RX_BD_FLAGS_SOP;
3405
3406 rxr = &bp->rx_ring[ring_nr];
3407 ring = &rxr->rx_ring_struct;
3408 bnxt_init_rxbd_pages(ring, type);
3409
3410 if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) {
3411 bpf_prog_add(bp->xdp_prog, 1);
3412 rxr->xdp_prog = bp->xdp_prog;
3413 }
3414 ring->fw_ring_id = INVALID_HW_RING_ID;
3415
3416 ring = &rxr->rx_agg_ring_struct;
3417 ring->fw_ring_id = INVALID_HW_RING_ID;
3418
3419 if ((bp->flags & BNXT_FLAG_AGG_RINGS)) {
3420 type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
3421 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
3422
3423 bnxt_init_rxbd_pages(ring, type);
3424 }
3425
3426 return bnxt_alloc_one_rx_ring(bp, ring_nr);
3427 }
3428
3429 static void bnxt_init_cp_rings(struct bnxt *bp)
3430 {
3431 int i, j;
3432
3433 for (i = 0; i < bp->cp_nr_rings; i++) {
3434 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
3435 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3436
3437 ring->fw_ring_id = INVALID_HW_RING_ID;
3438 cpr->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
3439 cpr->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
3440 for (j = 0; j < 2; j++) {
3441 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
3442
3443 if (!cpr2)
3444 continue;
3445
3446 ring = &cpr2->cp_ring_struct;
3447 ring->fw_ring_id = INVALID_HW_RING_ID;
3448 cpr2->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
3449 cpr2->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
3450 }
3451 }
3452 }
3453
3454 static int bnxt_init_rx_rings(struct bnxt *bp)
3455 {
3456 int i, rc = 0;
3457
3458 if (BNXT_RX_PAGE_MODE(bp)) {
3459 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM;
3460 bp->rx_dma_offset = XDP_PACKET_HEADROOM;
3461 } else {
3462 bp->rx_offset = BNXT_RX_OFFSET;
3463 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET;
3464 }
3465
3466 for (i = 0; i < bp->rx_nr_rings; i++) {
3467 rc = bnxt_init_one_rx_ring(bp, i);
3468 if (rc)
3469 break;
3470 }
3471
3472 return rc;
3473 }
3474
3475 static int bnxt_init_tx_rings(struct bnxt *bp)
3476 {
3477 u16 i;
3478
3479 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
3480 MAX_SKB_FRAGS + 1);
3481
3482 for (i = 0; i < bp->tx_nr_rings; i++) {
3483 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3484 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
3485
3486 ring->fw_ring_id = INVALID_HW_RING_ID;
3487 }
3488
3489 return 0;
3490 }
3491
3492 static void bnxt_free_ring_grps(struct bnxt *bp)
3493 {
3494 kfree(bp->grp_info);
3495 bp->grp_info = NULL;
3496 }
3497
3498 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
3499 {
3500 int i;
3501
3502 if (irq_re_init) {
3503 bp->grp_info = kcalloc(bp->cp_nr_rings,
3504 sizeof(struct bnxt_ring_grp_info),
3505 GFP_KERNEL);
3506 if (!bp->grp_info)
3507 return -ENOMEM;
3508 }
3509 for (i = 0; i < bp->cp_nr_rings; i++) {
3510 if (irq_re_init)
3511 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
3512 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
3513 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
3514 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
3515 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
3516 }
3517 return 0;
3518 }
3519
3520 static void bnxt_free_vnics(struct bnxt *bp)
3521 {
3522 kfree(bp->vnic_info);
3523 bp->vnic_info = NULL;
3524 bp->nr_vnics = 0;
3525 }
3526
3527 static int bnxt_alloc_vnics(struct bnxt *bp)
3528 {
3529 int num_vnics = 1;
3530
3531 #ifdef CONFIG_RFS_ACCEL
3532 if ((bp->flags & (BNXT_FLAG_RFS | BNXT_FLAG_CHIP_P5)) == BNXT_FLAG_RFS)
3533 num_vnics += bp->rx_nr_rings;
3534 #endif
3535
3536 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
3537 num_vnics++;
3538
3539 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
3540 GFP_KERNEL);
3541 if (!bp->vnic_info)
3542 return -ENOMEM;
3543
3544 bp->nr_vnics = num_vnics;
3545 return 0;
3546 }
3547
3548 static void bnxt_init_vnics(struct bnxt *bp)
3549 {
3550 int i;
3551
3552 for (i = 0; i < bp->nr_vnics; i++) {
3553 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3554 int j;
3555
3556 vnic->fw_vnic_id = INVALID_HW_RING_ID;
3557 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++)
3558 vnic->fw_rss_cos_lb_ctx[j] = INVALID_HW_RING_ID;
3559
3560 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
3561
3562 if (bp->vnic_info[i].rss_hash_key) {
3563 if (i == 0)
3564 prandom_bytes(vnic->rss_hash_key,
3565 HW_HASH_KEY_SIZE);
3566 else
3567 memcpy(vnic->rss_hash_key,
3568 bp->vnic_info[0].rss_hash_key,
3569 HW_HASH_KEY_SIZE);
3570 }
3571 }
3572 }
3573
3574 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
3575 {
3576 int pages;
3577
3578 pages = ring_size / desc_per_pg;
3579
3580 if (!pages)
3581 return 1;
3582
3583 pages++;
3584
3585 while (pages & (pages - 1))
3586 pages++;
3587
3588 return pages;
3589 }
3590
3591 void bnxt_set_tpa_flags(struct bnxt *bp)
3592 {
3593 bp->flags &= ~BNXT_FLAG_TPA;
3594 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
3595 return;
3596 if (bp->dev->features & NETIF_F_LRO)
3597 bp->flags |= BNXT_FLAG_LRO;
3598 else if (bp->dev->features & NETIF_F_GRO_HW)
3599 bp->flags |= BNXT_FLAG_GRO;
3600 }
3601
3602 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
3603 * be set on entry.
3604 */
3605 void bnxt_set_ring_params(struct bnxt *bp)
3606 {
3607 u32 ring_size, rx_size, rx_space, max_rx_cmpl;
3608 u32 agg_factor = 0, agg_ring_size = 0;
3609
3610 /* 8 for CRC and VLAN */
3611 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
3612
3613 rx_space = rx_size + NET_SKB_PAD +
3614 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3615
3616 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
3617 ring_size = bp->rx_ring_size;
3618 bp->rx_agg_ring_size = 0;
3619 bp->rx_agg_nr_pages = 0;
3620
3621 if (bp->flags & BNXT_FLAG_TPA)
3622 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
3623
3624 bp->flags &= ~BNXT_FLAG_JUMBO;
3625 if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) {
3626 u32 jumbo_factor;
3627
3628 bp->flags |= BNXT_FLAG_JUMBO;
3629 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
3630 if (jumbo_factor > agg_factor)
3631 agg_factor = jumbo_factor;
3632 }
3633 agg_ring_size = ring_size * agg_factor;
3634
3635 if (agg_ring_size) {
3636 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
3637 RX_DESC_CNT);
3638 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
3639 u32 tmp = agg_ring_size;
3640
3641 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
3642 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
3643 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
3644 tmp, agg_ring_size);
3645 }
3646 bp->rx_agg_ring_size = agg_ring_size;
3647 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
3648 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
3649 rx_space = rx_size + NET_SKB_PAD +
3650 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3651 }
3652
3653 bp->rx_buf_use_size = rx_size;
3654 bp->rx_buf_size = rx_space;
3655
3656 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
3657 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
3658
3659 ring_size = bp->tx_ring_size;
3660 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
3661 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
3662
3663 max_rx_cmpl = bp->rx_ring_size;
3664 /* MAX TPA needs to be added because TPA_START completions are
3665 * immediately recycled, so the TPA completions are not bound by
3666 * the RX ring size.
3667 */
3668 if (bp->flags & BNXT_FLAG_TPA)
3669 max_rx_cmpl += bp->max_tpa;
3670 /* RX and TPA completions are 32-byte, all others are 16-byte */
3671 ring_size = max_rx_cmpl * 2 + agg_ring_size + bp->tx_ring_size;
3672 bp->cp_ring_size = ring_size;
3673
3674 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
3675 if (bp->cp_nr_pages > MAX_CP_PAGES) {
3676 bp->cp_nr_pages = MAX_CP_PAGES;
3677 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
3678 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
3679 ring_size, bp->cp_ring_size);
3680 }
3681 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
3682 bp->cp_ring_mask = bp->cp_bit - 1;
3683 }
3684
3685 /* Changing allocation mode of RX rings.
3686 * TODO: Update when extending xdp_rxq_info to support allocation modes.
3687 */
3688 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode)
3689 {
3690 if (page_mode) {
3691 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU)
3692 return -EOPNOTSUPP;
3693 bp->dev->max_mtu =
3694 min_t(u16, bp->max_mtu, BNXT_MAX_PAGE_MODE_MTU);
3695 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
3696 bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE;
3697 bp->rx_dir = DMA_BIDIRECTIONAL;
3698 bp->rx_skb_func = bnxt_rx_page_skb;
3699 /* Disable LRO or GRO_HW */
3700 netdev_update_features(bp->dev);
3701 } else {
3702 bp->dev->max_mtu = bp->max_mtu;
3703 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE;
3704 bp->rx_dir = DMA_FROM_DEVICE;
3705 bp->rx_skb_func = bnxt_rx_skb;
3706 }
3707 return 0;
3708 }
3709
3710 static void bnxt_free_vnic_attributes(struct bnxt *bp)
3711 {
3712 int i;
3713 struct bnxt_vnic_info *vnic;
3714 struct pci_dev *pdev = bp->pdev;
3715
3716 if (!bp->vnic_info)
3717 return;
3718
3719 for (i = 0; i < bp->nr_vnics; i++) {
3720 vnic = &bp->vnic_info[i];
3721
3722 kfree(vnic->fw_grp_ids);
3723 vnic->fw_grp_ids = NULL;
3724
3725 kfree(vnic->uc_list);
3726 vnic->uc_list = NULL;
3727
3728 if (vnic->mc_list) {
3729 dma_free_coherent(&pdev->dev, vnic->mc_list_size,
3730 vnic->mc_list, vnic->mc_list_mapping);
3731 vnic->mc_list = NULL;
3732 }
3733
3734 if (vnic->rss_table) {
3735 dma_free_coherent(&pdev->dev, vnic->rss_table_size,
3736 vnic->rss_table,
3737 vnic->rss_table_dma_addr);
3738 vnic->rss_table = NULL;
3739 }
3740
3741 vnic->rss_hash_key = NULL;
3742 vnic->flags = 0;
3743 }
3744 }
3745
3746 static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
3747 {
3748 int i, rc = 0, size;
3749 struct bnxt_vnic_info *vnic;
3750 struct pci_dev *pdev = bp->pdev;
3751 int max_rings;
3752
3753 for (i = 0; i < bp->nr_vnics; i++) {
3754 vnic = &bp->vnic_info[i];
3755
3756 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
3757 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
3758
3759 if (mem_size > 0) {
3760 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
3761 if (!vnic->uc_list) {
3762 rc = -ENOMEM;
3763 goto out;
3764 }
3765 }
3766 }
3767
3768 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
3769 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
3770 vnic->mc_list =
3771 dma_alloc_coherent(&pdev->dev,
3772 vnic->mc_list_size,
3773 &vnic->mc_list_mapping,
3774 GFP_KERNEL);
3775 if (!vnic->mc_list) {
3776 rc = -ENOMEM;
3777 goto out;
3778 }
3779 }
3780
3781 if (bp->flags & BNXT_FLAG_CHIP_P5)
3782 goto vnic_skip_grps;
3783
3784 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3785 max_rings = bp->rx_nr_rings;
3786 else
3787 max_rings = 1;
3788
3789 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
3790 if (!vnic->fw_grp_ids) {
3791 rc = -ENOMEM;
3792 goto out;
3793 }
3794 vnic_skip_grps:
3795 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
3796 !(vnic->flags & BNXT_VNIC_RSS_FLAG))
3797 continue;
3798
3799 /* Allocate rss table and hash key */
3800 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
3801 if (bp->flags & BNXT_FLAG_CHIP_P5)
3802 size = L1_CACHE_ALIGN(BNXT_MAX_RSS_TABLE_SIZE_P5);
3803
3804 vnic->rss_table_size = size + HW_HASH_KEY_SIZE;
3805 vnic->rss_table = dma_alloc_coherent(&pdev->dev,
3806 vnic->rss_table_size,
3807 &vnic->rss_table_dma_addr,
3808 GFP_KERNEL);
3809 if (!vnic->rss_table) {
3810 rc = -ENOMEM;
3811 goto out;
3812 }
3813
3814 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
3815 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
3816 }
3817 return 0;
3818
3819 out:
3820 return rc;
3821 }
3822
3823 static void bnxt_free_hwrm_resources(struct bnxt *bp)
3824 {
3825 struct pci_dev *pdev = bp->pdev;
3826
3827 if (bp->hwrm_cmd_resp_addr) {
3828 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
3829 bp->hwrm_cmd_resp_dma_addr);
3830 bp->hwrm_cmd_resp_addr = NULL;
3831 }
3832
3833 if (bp->hwrm_cmd_kong_resp_addr) {
3834 dma_free_coherent(&pdev->dev, PAGE_SIZE,
3835 bp->hwrm_cmd_kong_resp_addr,
3836 bp->hwrm_cmd_kong_resp_dma_addr);
3837 bp->hwrm_cmd_kong_resp_addr = NULL;
3838 }
3839 }
3840
3841 static int bnxt_alloc_kong_hwrm_resources(struct bnxt *bp)
3842 {
3843 struct pci_dev *pdev = bp->pdev;
3844
3845 if (bp->hwrm_cmd_kong_resp_addr)
3846 return 0;
3847
3848 bp->hwrm_cmd_kong_resp_addr =
3849 dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3850 &bp->hwrm_cmd_kong_resp_dma_addr,
3851 GFP_KERNEL);
3852 if (!bp->hwrm_cmd_kong_resp_addr)
3853 return -ENOMEM;
3854
3855 return 0;
3856 }
3857
3858 static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
3859 {
3860 struct pci_dev *pdev = bp->pdev;
3861
3862 bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3863 &bp->hwrm_cmd_resp_dma_addr,
3864 GFP_KERNEL);
3865 if (!bp->hwrm_cmd_resp_addr)
3866 return -ENOMEM;
3867
3868 return 0;
3869 }
3870
3871 static void bnxt_free_hwrm_short_cmd_req(struct bnxt *bp)
3872 {
3873 if (bp->hwrm_short_cmd_req_addr) {
3874 struct pci_dev *pdev = bp->pdev;
3875
3876 dma_free_coherent(&pdev->dev, bp->hwrm_max_ext_req_len,
3877 bp->hwrm_short_cmd_req_addr,
3878 bp->hwrm_short_cmd_req_dma_addr);
3879 bp->hwrm_short_cmd_req_addr = NULL;
3880 }
3881 }
3882
3883 static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt *bp)
3884 {
3885 struct pci_dev *pdev = bp->pdev;
3886
3887 if (bp->hwrm_short_cmd_req_addr)
3888 return 0;
3889
3890 bp->hwrm_short_cmd_req_addr =
3891 dma_alloc_coherent(&pdev->dev, bp->hwrm_max_ext_req_len,
3892 &bp->hwrm_short_cmd_req_dma_addr,
3893 GFP_KERNEL);
3894 if (!bp->hwrm_short_cmd_req_addr)
3895 return -ENOMEM;
3896
3897 return 0;
3898 }
3899
3900 static void bnxt_free_stats_mem(struct bnxt *bp, struct bnxt_stats_mem *stats)
3901 {
3902 kfree(stats->hw_masks);
3903 stats->hw_masks = NULL;
3904 kfree(stats->sw_stats);
3905 stats->sw_stats = NULL;
3906 if (stats->hw_stats) {
3907 dma_free_coherent(&bp->pdev->dev, stats->len, stats->hw_stats,
3908 stats->hw_stats_map);
3909 stats->hw_stats = NULL;
3910 }
3911 }
3912
3913 static int bnxt_alloc_stats_mem(struct bnxt *bp, struct bnxt_stats_mem *stats,
3914 bool alloc_masks)
3915 {
3916 stats->hw_stats = dma_alloc_coherent(&bp->pdev->dev, stats->len,
3917 &stats->hw_stats_map, GFP_KERNEL);
3918 if (!stats->hw_stats)
3919 return -ENOMEM;
3920
3921 stats->sw_stats = kzalloc(stats->len, GFP_KERNEL);
3922 if (!stats->sw_stats)
3923 goto stats_mem_err;
3924
3925 if (alloc_masks) {
3926 stats->hw_masks = kzalloc(stats->len, GFP_KERNEL);
3927 if (!stats->hw_masks)
3928 goto stats_mem_err;
3929 }
3930 return 0;
3931
3932 stats_mem_err:
3933 bnxt_free_stats_mem(bp, stats);
3934 return -ENOMEM;
3935 }
3936
3937 static void bnxt_fill_masks(u64 *mask_arr, u64 mask, int count)
3938 {
3939 int i;
3940
3941 for (i = 0; i < count; i++)
3942 mask_arr[i] = mask;
3943 }
3944
3945 static void bnxt_copy_hw_masks(u64 *mask_arr, __le64 *hw_mask_arr, int count)
3946 {
3947 int i;
3948
3949 for (i = 0; i < count; i++)
3950 mask_arr[i] = le64_to_cpu(hw_mask_arr[i]);
3951 }
3952
3953 static int bnxt_hwrm_func_qstat_ext(struct bnxt *bp,
3954 struct bnxt_stats_mem *stats)
3955 {
3956 struct hwrm_func_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
3957 struct hwrm_func_qstats_ext_input req = {0};
3958 __le64 *hw_masks;
3959 int rc;
3960
3961 if (!(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED) ||
3962 !(bp->flags & BNXT_FLAG_CHIP_P5))
3963 return -EOPNOTSUPP;
3964
3965 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QSTATS_EXT, -1, -1);
3966 req.fid = cpu_to_le16(0xffff);
3967 req.flags = FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK;
3968 mutex_lock(&bp->hwrm_cmd_lock);
3969 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3970 if (rc)
3971 goto qstat_exit;
3972
3973 hw_masks = &resp->rx_ucast_pkts;
3974 bnxt_copy_hw_masks(stats->hw_masks, hw_masks, stats->len / 8);
3975
3976 qstat_exit:
3977 mutex_unlock(&bp->hwrm_cmd_lock);
3978 return rc;
3979 }
3980
3981 static int bnxt_hwrm_port_qstats(struct bnxt *bp, u8 flags);
3982 static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp, u8 flags);
3983
3984 static void bnxt_init_stats(struct bnxt *bp)
3985 {
3986 struct bnxt_napi *bnapi = bp->bnapi[0];
3987 struct bnxt_cp_ring_info *cpr;
3988 struct bnxt_stats_mem *stats;
3989 __le64 *rx_stats, *tx_stats;
3990 int rc, rx_count, tx_count;
3991 u64 *rx_masks, *tx_masks;
3992 u64 mask;
3993 u8 flags;
3994
3995 cpr = &bnapi->cp_ring;
3996 stats = &cpr->stats;
3997 rc = bnxt_hwrm_func_qstat_ext(bp, stats);
3998 if (rc) {
3999 if (bp->flags & BNXT_FLAG_CHIP_P5)
4000 mask = (1ULL << 48) - 1;
4001 else
4002 mask = -1ULL;
4003 bnxt_fill_masks(stats->hw_masks, mask, stats->len / 8);
4004 }
4005 if (bp->flags & BNXT_FLAG_PORT_STATS) {
4006 stats = &bp->port_stats;
4007 rx_stats = stats->hw_stats;
4008 rx_masks = stats->hw_masks;
4009 rx_count = sizeof(struct rx_port_stats) / 8;
4010 tx_stats = rx_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
4011 tx_masks = rx_masks + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
4012 tx_count = sizeof(struct tx_port_stats) / 8;
4013
4014 flags = PORT_QSTATS_REQ_FLAGS_COUNTER_MASK;
4015 rc = bnxt_hwrm_port_qstats(bp, flags);
4016 if (rc) {
4017 mask = (1ULL << 40) - 1;
4018
4019 bnxt_fill_masks(rx_masks, mask, rx_count);
4020 bnxt_fill_masks(tx_masks, mask, tx_count);
4021 } else {
4022 bnxt_copy_hw_masks(rx_masks, rx_stats, rx_count);
4023 bnxt_copy_hw_masks(tx_masks, tx_stats, tx_count);
4024 bnxt_hwrm_port_qstats(bp, 0);
4025 }
4026 }
4027 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
4028 stats = &bp->rx_port_stats_ext;
4029 rx_stats = stats->hw_stats;
4030 rx_masks = stats->hw_masks;
4031 rx_count = sizeof(struct rx_port_stats_ext) / 8;
4032 stats = &bp->tx_port_stats_ext;
4033 tx_stats = stats->hw_stats;
4034 tx_masks = stats->hw_masks;
4035 tx_count = sizeof(struct tx_port_stats_ext) / 8;
4036
4037 flags = PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK;
4038 rc = bnxt_hwrm_port_qstats_ext(bp, flags);
4039 if (rc) {
4040 mask = (1ULL << 40) - 1;
4041
4042 bnxt_fill_masks(rx_masks, mask, rx_count);
4043 if (tx_stats)
4044 bnxt_fill_masks(tx_masks, mask, tx_count);
4045 } else {
4046 bnxt_copy_hw_masks(rx_masks, rx_stats, rx_count);
4047 if (tx_stats)
4048 bnxt_copy_hw_masks(tx_masks, tx_stats,
4049 tx_count);
4050 bnxt_hwrm_port_qstats_ext(bp, 0);
4051 }
4052 }
4053 }
4054
4055 static void bnxt_free_port_stats(struct bnxt *bp)
4056 {
4057 bp->flags &= ~BNXT_FLAG_PORT_STATS;
4058 bp->flags &= ~BNXT_FLAG_PORT_STATS_EXT;
4059
4060 bnxt_free_stats_mem(bp, &bp->port_stats);
4061 bnxt_free_stats_mem(bp, &bp->rx_port_stats_ext);
4062 bnxt_free_stats_mem(bp, &bp->tx_port_stats_ext);
4063 }
4064
4065 static void bnxt_free_ring_stats(struct bnxt *bp)
4066 {
4067 int i;
4068
4069 if (!bp->bnapi)
4070 return;
4071
4072 for (i = 0; i < bp->cp_nr_rings; i++) {
4073 struct bnxt_napi *bnapi = bp->bnapi[i];
4074 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4075
4076 bnxt_free_stats_mem(bp, &cpr->stats);
4077 }
4078 }
4079
4080 static int bnxt_alloc_stats(struct bnxt *bp)
4081 {
4082 u32 size, i;
4083 int rc;
4084
4085 size = bp->hw_ring_stats_size;
4086
4087 for (i = 0; i < bp->cp_nr_rings; i++) {
4088 struct bnxt_napi *bnapi = bp->bnapi[i];
4089 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4090
4091 cpr->stats.len = size;
4092 rc = bnxt_alloc_stats_mem(bp, &cpr->stats, !i);
4093 if (rc)
4094 return rc;
4095
4096 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
4097 }
4098
4099 if (BNXT_VF(bp) || bp->chip_num == CHIP_NUM_58700)
4100 return 0;
4101
4102 if (bp->port_stats.hw_stats)
4103 goto alloc_ext_stats;
4104
4105 bp->port_stats.len = BNXT_PORT_STATS_SIZE;
4106 rc = bnxt_alloc_stats_mem(bp, &bp->port_stats, true);
4107 if (rc)
4108 return rc;
4109
4110 bp->flags |= BNXT_FLAG_PORT_STATS;
4111
4112 alloc_ext_stats:
4113 /* Display extended statistics only if FW supports it */
4114 if (bp->hwrm_spec_code < 0x10804 || bp->hwrm_spec_code == 0x10900)
4115 if (!(bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED))
4116 return 0;
4117
4118 if (bp->rx_port_stats_ext.hw_stats)
4119 goto alloc_tx_ext_stats;
4120
4121 bp->rx_port_stats_ext.len = sizeof(struct rx_port_stats_ext);
4122 rc = bnxt_alloc_stats_mem(bp, &bp->rx_port_stats_ext, true);
4123 /* Extended stats are optional */
4124 if (rc)
4125 return 0;
4126
4127 alloc_tx_ext_stats:
4128 if (bp->tx_port_stats_ext.hw_stats)
4129 return 0;
4130
4131 if (bp->hwrm_spec_code >= 0x10902 ||
4132 (bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED)) {
4133 bp->tx_port_stats_ext.len = sizeof(struct tx_port_stats_ext);
4134 rc = bnxt_alloc_stats_mem(bp, &bp->tx_port_stats_ext, true);
4135 /* Extended stats are optional */
4136 if (rc)
4137 return 0;
4138 }
4139 bp->flags |= BNXT_FLAG_PORT_STATS_EXT;
4140 return 0;
4141 }
4142
4143 static void bnxt_clear_ring_indices(struct bnxt *bp)
4144 {
4145 int i;
4146
4147 if (!bp->bnapi)
4148 return;
4149
4150 for (i = 0; i < bp->cp_nr_rings; i++) {
4151 struct bnxt_napi *bnapi = bp->bnapi[i];
4152 struct bnxt_cp_ring_info *cpr;
4153 struct bnxt_rx_ring_info *rxr;
4154 struct bnxt_tx_ring_info *txr;
4155
4156 if (!bnapi)
4157 continue;
4158
4159 cpr = &bnapi->cp_ring;
4160 cpr->cp_raw_cons = 0;
4161
4162 txr = bnapi->tx_ring;
4163 if (txr) {
4164 txr->tx_prod = 0;
4165 txr->tx_cons = 0;
4166 }
4167
4168 rxr = bnapi->rx_ring;
4169 if (rxr) {
4170 rxr->rx_prod = 0;
4171 rxr->rx_agg_prod = 0;
4172 rxr->rx_sw_agg_prod = 0;
4173 rxr->rx_next_cons = 0;
4174 }
4175 }
4176 }
4177
4178 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
4179 {
4180 #ifdef CONFIG_RFS_ACCEL
4181 int i;
4182
4183 /* Under rtnl_lock and all our NAPIs have been disabled. It's
4184 * safe to delete the hash table.
4185 */
4186 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
4187 struct hlist_head *head;
4188 struct hlist_node *tmp;
4189 struct bnxt_ntuple_filter *fltr;
4190
4191 head = &bp->ntp_fltr_hash_tbl[i];
4192 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
4193 hlist_del(&fltr->hash);
4194 kfree(fltr);
4195 }
4196 }
4197 if (irq_reinit) {
4198 kfree(bp->ntp_fltr_bmap);
4199 bp->ntp_fltr_bmap = NULL;
4200 }
4201 bp->ntp_fltr_count = 0;
4202 #endif
4203 }
4204
4205 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
4206 {
4207 #ifdef CONFIG_RFS_ACCEL
4208 int i, rc = 0;
4209
4210 if (!(bp->flags & BNXT_FLAG_RFS))
4211 return 0;
4212
4213 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
4214 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
4215
4216 bp->ntp_fltr_count = 0;
4217 bp->ntp_fltr_bmap = kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
4218 sizeof(long),
4219 GFP_KERNEL);
4220
4221 if (!bp->ntp_fltr_bmap)
4222 rc = -ENOMEM;
4223
4224 return rc;
4225 #else
4226 return 0;
4227 #endif
4228 }
4229
4230 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
4231 {
4232 bnxt_free_vnic_attributes(bp);
4233 bnxt_free_tx_rings(bp);
4234 bnxt_free_rx_rings(bp);
4235 bnxt_free_cp_rings(bp);
4236 bnxt_free_ntp_fltrs(bp, irq_re_init);
4237 if (irq_re_init) {
4238 bnxt_free_ring_stats(bp);
4239 if (!(bp->phy_flags & BNXT_PHY_FL_PORT_STATS_NO_RESET) ||
4240 test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
4241 bnxt_free_port_stats(bp);
4242 bnxt_free_ring_grps(bp);
4243 bnxt_free_vnics(bp);
4244 kfree(bp->tx_ring_map);
4245 bp->tx_ring_map = NULL;
4246 kfree(bp->tx_ring);
4247 bp->tx_ring = NULL;
4248 kfree(bp->rx_ring);
4249 bp->rx_ring = NULL;
4250 kfree(bp->bnapi);
4251 bp->bnapi = NULL;
4252 } else {
4253 bnxt_clear_ring_indices(bp);
4254 }
4255 }
4256
4257 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
4258 {
4259 int i, j, rc, size, arr_size;
4260 void *bnapi;
4261
4262 if (irq_re_init) {
4263 /* Allocate bnapi mem pointer array and mem block for
4264 * all queues
4265 */
4266 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
4267 bp->cp_nr_rings);
4268 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
4269 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
4270 if (!bnapi)
4271 return -ENOMEM;
4272
4273 bp->bnapi = bnapi;
4274 bnapi += arr_size;
4275 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
4276 bp->bnapi[i] = bnapi;
4277 bp->bnapi[i]->index = i;
4278 bp->bnapi[i]->bp = bp;
4279 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4280 struct bnxt_cp_ring_info *cpr =
4281 &bp->bnapi[i]->cp_ring;
4282
4283 cpr->cp_ring_struct.ring_mem.flags =
4284 BNXT_RMEM_RING_PTE_FLAG;
4285 }
4286 }
4287
4288 bp->rx_ring = kcalloc(bp->rx_nr_rings,
4289 sizeof(struct bnxt_rx_ring_info),
4290 GFP_KERNEL);
4291 if (!bp->rx_ring)
4292 return -ENOMEM;
4293
4294 for (i = 0; i < bp->rx_nr_rings; i++) {
4295 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4296
4297 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4298 rxr->rx_ring_struct.ring_mem.flags =
4299 BNXT_RMEM_RING_PTE_FLAG;
4300 rxr->rx_agg_ring_struct.ring_mem.flags =
4301 BNXT_RMEM_RING_PTE_FLAG;
4302 }
4303 rxr->bnapi = bp->bnapi[i];
4304 bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
4305 }
4306
4307 bp->tx_ring = kcalloc(bp->tx_nr_rings,
4308 sizeof(struct bnxt_tx_ring_info),
4309 GFP_KERNEL);
4310 if (!bp->tx_ring)
4311 return -ENOMEM;
4312
4313 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16),
4314 GFP_KERNEL);
4315
4316 if (!bp->tx_ring_map)
4317 return -ENOMEM;
4318
4319 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
4320 j = 0;
4321 else
4322 j = bp->rx_nr_rings;
4323
4324 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
4325 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
4326
4327 if (bp->flags & BNXT_FLAG_CHIP_P5)
4328 txr->tx_ring_struct.ring_mem.flags =
4329 BNXT_RMEM_RING_PTE_FLAG;
4330 txr->bnapi = bp->bnapi[j];
4331 bp->bnapi[j]->tx_ring = txr;
4332 bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i;
4333 if (i >= bp->tx_nr_rings_xdp) {
4334 txr->txq_index = i - bp->tx_nr_rings_xdp;
4335 bp->bnapi[j]->tx_int = bnxt_tx_int;
4336 } else {
4337 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP;
4338 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp;
4339 }
4340 }
4341
4342 rc = bnxt_alloc_stats(bp);
4343 if (rc)
4344 goto alloc_mem_err;
4345 bnxt_init_stats(bp);
4346
4347 rc = bnxt_alloc_ntp_fltrs(bp);
4348 if (rc)
4349 goto alloc_mem_err;
4350
4351 rc = bnxt_alloc_vnics(bp);
4352 if (rc)
4353 goto alloc_mem_err;
4354 }
4355
4356 bnxt_init_ring_struct(bp);
4357
4358 rc = bnxt_alloc_rx_rings(bp);
4359 if (rc)
4360 goto alloc_mem_err;
4361
4362 rc = bnxt_alloc_tx_rings(bp);
4363 if (rc)
4364 goto alloc_mem_err;
4365
4366 rc = bnxt_alloc_cp_rings(bp);
4367 if (rc)
4368 goto alloc_mem_err;
4369
4370 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
4371 BNXT_VNIC_UCAST_FLAG;
4372 rc = bnxt_alloc_vnic_attributes(bp);
4373 if (rc)
4374 goto alloc_mem_err;
4375 return 0;
4376
4377 alloc_mem_err:
4378 bnxt_free_mem(bp, true);
4379 return rc;
4380 }
4381
4382 static void bnxt_disable_int(struct bnxt *bp)
4383 {
4384 int i;
4385
4386 if (!bp->bnapi)
4387 return;
4388
4389 for (i = 0; i < bp->cp_nr_rings; i++) {
4390 struct bnxt_napi *bnapi = bp->bnapi[i];
4391 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4392 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4393
4394 if (ring->fw_ring_id != INVALID_HW_RING_ID)
4395 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons);
4396 }
4397 }
4398
4399 static int bnxt_cp_num_to_irq_num(struct bnxt *bp, int n)
4400 {
4401 struct bnxt_napi *bnapi = bp->bnapi[n];
4402 struct bnxt_cp_ring_info *cpr;
4403
4404 cpr = &bnapi->cp_ring;
4405 return cpr->cp_ring_struct.map_idx;
4406 }
4407
4408 static void bnxt_disable_int_sync(struct bnxt *bp)
4409 {
4410 int i;
4411
4412 if (!bp->irq_tbl)
4413 return;
4414
4415 atomic_inc(&bp->intr_sem);
4416
4417 bnxt_disable_int(bp);
4418 for (i = 0; i < bp->cp_nr_rings; i++) {
4419 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
4420
4421 synchronize_irq(bp->irq_tbl[map_idx].vector);
4422 }
4423 }
4424
4425 static void bnxt_enable_int(struct bnxt *bp)
4426 {
4427 int i;
4428
4429 atomic_set(&bp->intr_sem, 0);
4430 for (i = 0; i < bp->cp_nr_rings; i++) {
4431 struct bnxt_napi *bnapi = bp->bnapi[i];
4432 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4433
4434 bnxt_db_nq_arm(bp, &cpr->cp_db, cpr->cp_raw_cons);
4435 }
4436 }
4437
4438 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
4439 u16 cmpl_ring, u16 target_id)
4440 {
4441 struct input *req = request;
4442
4443 req->req_type = cpu_to_le16(req_type);
4444 req->cmpl_ring = cpu_to_le16(cmpl_ring);
4445 req->target_id = cpu_to_le16(target_id);
4446 if (bnxt_kong_hwrm_message(bp, req))
4447 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr);
4448 else
4449 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
4450 }
4451
4452 static int bnxt_hwrm_to_stderr(u32 hwrm_err)
4453 {
4454 switch (hwrm_err) {
4455 case HWRM_ERR_CODE_SUCCESS:
4456 return 0;
4457 case HWRM_ERR_CODE_RESOURCE_LOCKED:
4458 return -EROFS;
4459 case HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED:
4460 return -EACCES;
4461 case HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR:
4462 return -ENOSPC;
4463 case HWRM_ERR_CODE_INVALID_PARAMS:
4464 case HWRM_ERR_CODE_INVALID_FLAGS:
4465 case HWRM_ERR_CODE_INVALID_ENABLES:
4466 case HWRM_ERR_CODE_UNSUPPORTED_TLV:
4467 case HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR:
4468 return -EINVAL;
4469 case HWRM_ERR_CODE_NO_BUFFER:
4470 return -ENOMEM;
4471 case HWRM_ERR_CODE_HOT_RESET_PROGRESS:
4472 case HWRM_ERR_CODE_BUSY:
4473 return -EAGAIN;
4474 case HWRM_ERR_CODE_CMD_NOT_SUPPORTED:
4475 return -EOPNOTSUPP;
4476 default:
4477 return -EIO;
4478 }
4479 }
4480
4481 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
4482 int timeout, bool silent)
4483 {
4484 int i, intr_process, rc, tmo_count;
4485 struct input *req = msg;
4486 u32 *data = msg;
4487 u8 *valid;
4488 u16 cp_ring_id, len = 0;
4489 struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
4490 u16 max_req_len = BNXT_HWRM_MAX_REQ_LEN;
4491 struct hwrm_short_input short_input = {0};
4492 u32 doorbell_offset = BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER;
4493 u32 bar_offset = BNXT_GRCPF_REG_CHIMP_COMM;
4494 u16 dst = BNXT_HWRM_CHNL_CHIMP;
4495
4496 if (BNXT_NO_FW_ACCESS(bp) &&
4497 le16_to_cpu(req->req_type) != HWRM_FUNC_RESET)
4498 return -EBUSY;
4499
4500 if (msg_len > BNXT_HWRM_MAX_REQ_LEN) {
4501 if (msg_len > bp->hwrm_max_ext_req_len ||
4502 !bp->hwrm_short_cmd_req_addr)
4503 return -EINVAL;
4504 }
4505
4506 if (bnxt_hwrm_kong_chnl(bp, req)) {
4507 dst = BNXT_HWRM_CHNL_KONG;
4508 bar_offset = BNXT_GRCPF_REG_KONG_COMM;
4509 doorbell_offset = BNXT_GRCPF_REG_KONG_COMM_TRIGGER;
4510 resp = bp->hwrm_cmd_kong_resp_addr;
4511 }
4512
4513 memset(resp, 0, PAGE_SIZE);
4514 cp_ring_id = le16_to_cpu(req->cmpl_ring);
4515 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
4516
4517 req->seq_id = cpu_to_le16(bnxt_get_hwrm_seq_id(bp, dst));
4518 /* currently supports only one outstanding message */
4519 if (intr_process)
4520 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
4521
4522 if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) ||
4523 msg_len > BNXT_HWRM_MAX_REQ_LEN) {
4524 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
4525 u16 max_msg_len;
4526
4527 /* Set boundary for maximum extended request length for short
4528 * cmd format. If passed up from device use the max supported
4529 * internal req length.
4530 */
4531 max_msg_len = bp->hwrm_max_ext_req_len;
4532
4533 memcpy(short_cmd_req, req, msg_len);
4534 if (msg_len < max_msg_len)
4535 memset(short_cmd_req + msg_len, 0,
4536 max_msg_len - msg_len);
4537
4538 short_input.req_type = req->req_type;
4539 short_input.signature =
4540 cpu_to_le16(SHORT_REQ_SIGNATURE_SHORT_CMD);
4541 short_input.size = cpu_to_le16(msg_len);
4542 short_input.req_addr =
4543 cpu_to_le64(bp->hwrm_short_cmd_req_dma_addr);
4544
4545 data = (u32 *)&short_input;
4546 msg_len = sizeof(short_input);
4547
4548 /* Sync memory write before updating doorbell */
4549 wmb();
4550
4551 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
4552 }
4553
4554 /* Write request msg to hwrm channel */
4555 __iowrite32_copy(bp->bar0 + bar_offset, data, msg_len / 4);
4556
4557 for (i = msg_len; i < max_req_len; i += 4)
4558 writel(0, bp->bar0 + bar_offset + i);
4559
4560 /* Ring channel doorbell */
4561 writel(1, bp->bar0 + doorbell_offset);
4562
4563 if (!pci_is_enabled(bp->pdev))
4564 return -ENODEV;
4565
4566 if (!timeout)
4567 timeout = DFLT_HWRM_CMD_TIMEOUT;
4568 /* Limit timeout to an upper limit */
4569 timeout = min(timeout, HWRM_CMD_MAX_TIMEOUT);
4570 /* convert timeout to usec */
4571 timeout *= 1000;
4572
4573 i = 0;
4574 /* Short timeout for the first few iterations:
4575 * number of loops = number of loops for short timeout +
4576 * number of loops for standard timeout.
4577 */
4578 tmo_count = HWRM_SHORT_TIMEOUT_COUNTER;
4579 timeout = timeout - HWRM_SHORT_MIN_TIMEOUT * HWRM_SHORT_TIMEOUT_COUNTER;
4580 tmo_count += DIV_ROUND_UP(timeout, HWRM_MIN_TIMEOUT);
4581
4582 if (intr_process) {
4583 u16 seq_id = bp->hwrm_intr_seq_id;
4584
4585 /* Wait until hwrm response cmpl interrupt is processed */
4586 while (bp->hwrm_intr_seq_id != (u16)~seq_id &&
4587 i++ < tmo_count) {
4588 /* Abort the wait for completion if the FW health
4589 * check has failed.
4590 */
4591 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))
4592 return -EBUSY;
4593 /* on first few passes, just barely sleep */
4594 if (i < HWRM_SHORT_TIMEOUT_COUNTER) {
4595 usleep_range(HWRM_SHORT_MIN_TIMEOUT,
4596 HWRM_SHORT_MAX_TIMEOUT);
4597 } else {
4598 if (HWRM_WAIT_MUST_ABORT(bp, req))
4599 break;
4600 usleep_range(HWRM_MIN_TIMEOUT,
4601 HWRM_MAX_TIMEOUT);
4602 }
4603 }
4604
4605 if (bp->hwrm_intr_seq_id != (u16)~seq_id) {
4606 if (!silent)
4607 netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
4608 le16_to_cpu(req->req_type));
4609 return -EBUSY;
4610 }
4611 len = le16_to_cpu(resp->resp_len);
4612 valid = ((u8 *)resp) + len - 1;
4613 } else {
4614 int j;
4615
4616 /* Check if response len is updated */
4617 for (i = 0; i < tmo_count; i++) {
4618 /* Abort the wait for completion if the FW health
4619 * check has failed.
4620 */
4621 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))
4622 return -EBUSY;
4623 len = le16_to_cpu(resp->resp_len);
4624 if (len)
4625 break;
4626 /* on first few passes, just barely sleep */
4627 if (i < HWRM_SHORT_TIMEOUT_COUNTER) {
4628 usleep_range(HWRM_SHORT_MIN_TIMEOUT,
4629 HWRM_SHORT_MAX_TIMEOUT);
4630 } else {
4631 if (HWRM_WAIT_MUST_ABORT(bp, req))
4632 goto timeout_abort;
4633 usleep_range(HWRM_MIN_TIMEOUT,
4634 HWRM_MAX_TIMEOUT);
4635 }
4636 }
4637
4638 if (i >= tmo_count) {
4639 timeout_abort:
4640 if (!silent)
4641 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
4642 HWRM_TOTAL_TIMEOUT(i),
4643 le16_to_cpu(req->req_type),
4644 le16_to_cpu(req->seq_id), len);
4645 return -EBUSY;
4646 }
4647
4648 /* Last byte of resp contains valid bit */
4649 valid = ((u8 *)resp) + len - 1;
4650 for (j = 0; j < HWRM_VALID_BIT_DELAY_USEC; j++) {
4651 /* make sure we read from updated DMA memory */
4652 dma_rmb();
4653 if (*valid)
4654 break;
4655 usleep_range(1, 5);
4656 }
4657
4658 if (j >= HWRM_VALID_BIT_DELAY_USEC) {
4659 if (!silent)
4660 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
4661 HWRM_TOTAL_TIMEOUT(i),
4662 le16_to_cpu(req->req_type),
4663 le16_to_cpu(req->seq_id), len,
4664 *valid);
4665 return -EBUSY;
4666 }
4667 }
4668
4669 /* Zero valid bit for compatibility. Valid bit in an older spec
4670 * may become a new field in a newer spec. We must make sure that
4671 * a new field not implemented by old spec will read zero.
4672 */
4673 *valid = 0;
4674 rc = le16_to_cpu(resp->error_code);
4675 if (rc && !silent)
4676 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
4677 le16_to_cpu(resp->req_type),
4678 le16_to_cpu(resp->seq_id), rc);
4679 return bnxt_hwrm_to_stderr(rc);
4680 }
4681
4682 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
4683 {
4684 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
4685 }
4686
4687 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
4688 int timeout)
4689 {
4690 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
4691 }
4692
4693 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
4694 {
4695 int rc;
4696
4697 mutex_lock(&bp->hwrm_cmd_lock);
4698 rc = _hwrm_send_message(bp, msg, msg_len, timeout);
4699 mutex_unlock(&bp->hwrm_cmd_lock);
4700 return rc;
4701 }
4702
4703 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
4704 int timeout)
4705 {
4706 int rc;
4707
4708 mutex_lock(&bp->hwrm_cmd_lock);
4709 rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
4710 mutex_unlock(&bp->hwrm_cmd_lock);
4711 return rc;
4712 }
4713
4714 int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp, unsigned long *bmap, int bmap_size,
4715 bool async_only)
4716 {
4717 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
4718 struct hwrm_func_drv_rgtr_input req = {0};
4719 DECLARE_BITMAP(async_events_bmap, 256);
4720 u32 *events = (u32 *)async_events_bmap;
4721 u32 flags;
4722 int rc, i;
4723
4724 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
4725
4726 req.enables =
4727 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
4728 FUNC_DRV_RGTR_REQ_ENABLES_VER |
4729 FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
4730
4731 req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
4732 flags = FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE;
4733 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
4734 flags |= FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT;
4735 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
4736 flags |= FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT |
4737 FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT;
4738 req.flags = cpu_to_le32(flags);
4739 req.ver_maj_8b = DRV_VER_MAJ;
4740 req.ver_min_8b = DRV_VER_MIN;
4741 req.ver_upd_8b = DRV_VER_UPD;
4742 req.ver_maj = cpu_to_le16(DRV_VER_MAJ);
4743 req.ver_min = cpu_to_le16(DRV_VER_MIN);
4744 req.ver_upd = cpu_to_le16(DRV_VER_UPD);
4745
4746 if (BNXT_PF(bp)) {
4747 u32 data[8];
4748 int i;
4749
4750 memset(data, 0, sizeof(data));
4751 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) {
4752 u16 cmd = bnxt_vf_req_snif[i];
4753 unsigned int bit, idx;
4754
4755 idx = cmd / 32;
4756 bit = cmd % 32;
4757 data[idx] |= 1 << bit;
4758 }
4759
4760 for (i = 0; i < 8; i++)
4761 req.vf_req_fwd[i] = cpu_to_le32(data[i]);
4762
4763 req.enables |=
4764 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
4765 }
4766
4767 if (bp->fw_cap & BNXT_FW_CAP_OVS_64BIT_HANDLE)
4768 req.flags |= cpu_to_le32(
4769 FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE);
4770
4771 memset(async_events_bmap, 0, sizeof(async_events_bmap));
4772 for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++) {
4773 u16 event_id = bnxt_async_events_arr[i];
4774
4775 if (event_id == ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY &&
4776 !(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4777 continue;
4778 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
4779 }
4780 if (bmap && bmap_size) {
4781 for (i = 0; i < bmap_size; i++) {
4782 if (test_bit(i, bmap))
4783 __set_bit(i, async_events_bmap);
4784 }
4785 }
4786 for (i = 0; i < 8; i++)
4787 req.async_event_fwd[i] |= cpu_to_le32(events[i]);
4788
4789 if (async_only)
4790 req.enables =
4791 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
4792
4793 mutex_lock(&bp->hwrm_cmd_lock);
4794 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4795 if (!rc) {
4796 set_bit(BNXT_STATE_DRV_REGISTERED, &bp->state);
4797 if (resp->flags &
4798 cpu_to_le32(FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED))
4799 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
4800 }
4801 mutex_unlock(&bp->hwrm_cmd_lock);
4802 return rc;
4803 }
4804
4805 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
4806 {
4807 struct hwrm_func_drv_unrgtr_input req = {0};
4808
4809 if (!test_and_clear_bit(BNXT_STATE_DRV_REGISTERED, &bp->state))
4810 return 0;
4811
4812 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
4813 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4814 }
4815
4816 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
4817 {
4818 u32 rc = 0;
4819 struct hwrm_tunnel_dst_port_free_input req = {0};
4820
4821 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
4822 req.tunnel_type = tunnel_type;
4823
4824 switch (tunnel_type) {
4825 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
4826 req.tunnel_dst_port_id = cpu_to_le16(bp->vxlan_fw_dst_port_id);
4827 bp->vxlan_fw_dst_port_id = INVALID_HW_RING_ID;
4828 break;
4829 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
4830 req.tunnel_dst_port_id = cpu_to_le16(bp->nge_fw_dst_port_id);
4831 bp->nge_fw_dst_port_id = INVALID_HW_RING_ID;
4832 break;
4833 default:
4834 break;
4835 }
4836
4837 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4838 if (rc)
4839 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
4840 rc);
4841 return rc;
4842 }
4843
4844 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
4845 u8 tunnel_type)
4846 {
4847 u32 rc = 0;
4848 struct hwrm_tunnel_dst_port_alloc_input req = {0};
4849 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4850
4851 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
4852
4853 req.tunnel_type = tunnel_type;
4854 req.tunnel_dst_port_val = port;
4855
4856 mutex_lock(&bp->hwrm_cmd_lock);
4857 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4858 if (rc) {
4859 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
4860 rc);
4861 goto err_out;
4862 }
4863
4864 switch (tunnel_type) {
4865 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN:
4866 bp->vxlan_fw_dst_port_id =
4867 le16_to_cpu(resp->tunnel_dst_port_id);
4868 break;
4869 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE:
4870 bp->nge_fw_dst_port_id = le16_to_cpu(resp->tunnel_dst_port_id);
4871 break;
4872 default:
4873 break;
4874 }
4875
4876 err_out:
4877 mutex_unlock(&bp->hwrm_cmd_lock);
4878 return rc;
4879 }
4880
4881 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
4882 {
4883 struct hwrm_cfa_l2_set_rx_mask_input req = {0};
4884 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4885
4886 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
4887 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
4888
4889 req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
4890 req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
4891 req.mask = cpu_to_le32(vnic->rx_mask);
4892 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4893 }
4894
4895 #ifdef CONFIG_RFS_ACCEL
4896 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
4897 struct bnxt_ntuple_filter *fltr)
4898 {
4899 struct hwrm_cfa_ntuple_filter_free_input req = {0};
4900
4901 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
4902 req.ntuple_filter_id = fltr->filter_id;
4903 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4904 }
4905
4906 #define BNXT_NTP_FLTR_FLAGS \
4907 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
4908 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
4909 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
4910 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
4911 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
4912 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
4913 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
4914 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
4915 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
4916 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
4917 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
4918 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
4919 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
4920 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
4921
4922 #define BNXT_NTP_TUNNEL_FLTR_FLAG \
4923 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE
4924
4925 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
4926 struct bnxt_ntuple_filter *fltr)
4927 {
4928 struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
4929 struct hwrm_cfa_ntuple_filter_alloc_output *resp;
4930 struct flow_keys *keys = &fltr->fkeys;
4931 struct bnxt_vnic_info *vnic;
4932 u32 flags = 0;
4933 int rc = 0;
4934
4935 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
4936 req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx];
4937
4938 if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2) {
4939 flags = CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_RFS_RING_IDX;
4940 req.dst_id = cpu_to_le16(fltr->rxq);
4941 } else {
4942 vnic = &bp->vnic_info[fltr->rxq + 1];
4943 req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
4944 }
4945 req.flags = cpu_to_le32(flags);
4946 req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
4947
4948 req.ethertype = htons(ETH_P_IP);
4949 memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
4950 req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
4951 req.ip_protocol = keys->basic.ip_proto;
4952
4953 if (keys->basic.n_proto == htons(ETH_P_IPV6)) {
4954 int i;
4955
4956 req.ethertype = htons(ETH_P_IPV6);
4957 req.ip_addr_type =
4958 CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6;
4959 *(struct in6_addr *)&req.src_ipaddr[0] =
4960 keys->addrs.v6addrs.src;
4961 *(struct in6_addr *)&req.dst_ipaddr[0] =
4962 keys->addrs.v6addrs.dst;
4963 for (i = 0; i < 4; i++) {
4964 req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
4965 req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
4966 }
4967 } else {
4968 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
4969 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
4970 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
4971 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
4972 }
4973 if (keys->control.flags & FLOW_DIS_ENCAPSULATION) {
4974 req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG);
4975 req.tunnel_type =
4976 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL;
4977 }
4978
4979 req.src_port = keys->ports.src;
4980 req.src_port_mask = cpu_to_be16(0xffff);
4981 req.dst_port = keys->ports.dst;
4982 req.dst_port_mask = cpu_to_be16(0xffff);
4983
4984 mutex_lock(&bp->hwrm_cmd_lock);
4985 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4986 if (!rc) {
4987 resp = bnxt_get_hwrm_resp_addr(bp, &req);
4988 fltr->filter_id = resp->ntuple_filter_id;
4989 }
4990 mutex_unlock(&bp->hwrm_cmd_lock);
4991 return rc;
4992 }
4993 #endif
4994
4995 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
4996 u8 *mac_addr)
4997 {
4998 u32 rc = 0;
4999 struct hwrm_cfa_l2_filter_alloc_input req = {0};
5000 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5001
5002 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
5003 req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX);
5004 if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
5005 req.flags |=
5006 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
5007 req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
5008 req.enables =
5009 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
5010 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
5011 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
5012 memcpy(req.l2_addr, mac_addr, ETH_ALEN);
5013 req.l2_addr_mask[0] = 0xff;
5014 req.l2_addr_mask[1] = 0xff;
5015 req.l2_addr_mask[2] = 0xff;
5016 req.l2_addr_mask[3] = 0xff;
5017 req.l2_addr_mask[4] = 0xff;
5018 req.l2_addr_mask[5] = 0xff;
5019
5020 mutex_lock(&bp->hwrm_cmd_lock);
5021 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5022 if (!rc)
5023 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
5024 resp->l2_filter_id;
5025 mutex_unlock(&bp->hwrm_cmd_lock);
5026 return rc;
5027 }
5028
5029 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
5030 {
5031 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
5032 int rc = 0;
5033
5034 /* Any associated ntuple filters will also be cleared by firmware. */
5035 mutex_lock(&bp->hwrm_cmd_lock);
5036 for (i = 0; i < num_of_vnics; i++) {
5037 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
5038
5039 for (j = 0; j < vnic->uc_filter_count; j++) {
5040 struct hwrm_cfa_l2_filter_free_input req = {0};
5041
5042 bnxt_hwrm_cmd_hdr_init(bp, &req,
5043 HWRM_CFA_L2_FILTER_FREE, -1, -1);
5044
5045 req.l2_filter_id = vnic->fw_l2_filter_id[j];
5046
5047 rc = _hwrm_send_message(bp, &req, sizeof(req),
5048 HWRM_CMD_TIMEOUT);
5049 }
5050 vnic->uc_filter_count = 0;
5051 }
5052 mutex_unlock(&bp->hwrm_cmd_lock);
5053
5054 return rc;
5055 }
5056
5057 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
5058 {
5059 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5060 u16 max_aggs = VNIC_TPA_CFG_REQ_MAX_AGGS_MAX;
5061 struct hwrm_vnic_tpa_cfg_input req = {0};
5062
5063 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
5064 return 0;
5065
5066 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
5067
5068 if (tpa_flags) {
5069 u16 mss = bp->dev->mtu - 40;
5070 u32 nsegs, n, segs = 0, flags;
5071
5072 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
5073 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
5074 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
5075 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
5076 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
5077 if (tpa_flags & BNXT_FLAG_GRO)
5078 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
5079
5080 req.flags = cpu_to_le32(flags);
5081
5082 req.enables =
5083 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
5084 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
5085 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
5086
5087 /* Number of segs are log2 units, and first packet is not
5088 * included as part of this units.
5089 */
5090 if (mss <= BNXT_RX_PAGE_SIZE) {
5091 n = BNXT_RX_PAGE_SIZE / mss;
5092 nsegs = (MAX_SKB_FRAGS - 1) * n;
5093 } else {
5094 n = mss / BNXT_RX_PAGE_SIZE;
5095 if (mss & (BNXT_RX_PAGE_SIZE - 1))
5096 n++;
5097 nsegs = (MAX_SKB_FRAGS - n) / n;
5098 }
5099
5100 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5101 segs = MAX_TPA_SEGS_P5;
5102 max_aggs = bp->max_tpa;
5103 } else {
5104 segs = ilog2(nsegs);
5105 }
5106 req.max_agg_segs = cpu_to_le16(segs);
5107 req.max_aggs = cpu_to_le16(max_aggs);
5108
5109 req.min_agg_len = cpu_to_le32(512);
5110 }
5111 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
5112
5113 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5114 }
5115
5116 static u16 bnxt_cp_ring_from_grp(struct bnxt *bp, struct bnxt_ring_struct *ring)
5117 {
5118 struct bnxt_ring_grp_info *grp_info;
5119
5120 grp_info = &bp->grp_info[ring->grp_idx];
5121 return grp_info->cp_fw_ring_id;
5122 }
5123
5124 static u16 bnxt_cp_ring_for_rx(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
5125 {
5126 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5127 struct bnxt_napi *bnapi = rxr->bnapi;
5128 struct bnxt_cp_ring_info *cpr;
5129
5130 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_RX_HDL];
5131 return cpr->cp_ring_struct.fw_ring_id;
5132 } else {
5133 return bnxt_cp_ring_from_grp(bp, &rxr->rx_ring_struct);
5134 }
5135 }
5136
5137 static u16 bnxt_cp_ring_for_tx(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
5138 {
5139 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5140 struct bnxt_napi *bnapi = txr->bnapi;
5141 struct bnxt_cp_ring_info *cpr;
5142
5143 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_TX_HDL];
5144 return cpr->cp_ring_struct.fw_ring_id;
5145 } else {
5146 return bnxt_cp_ring_from_grp(bp, &txr->tx_ring_struct);
5147 }
5148 }
5149
5150 static int bnxt_alloc_rss_indir_tbl(struct bnxt *bp)
5151 {
5152 int entries;
5153
5154 if (bp->flags & BNXT_FLAG_CHIP_P5)
5155 entries = BNXT_MAX_RSS_TABLE_ENTRIES_P5;
5156 else
5157 entries = HW_HASH_INDEX_SIZE;
5158
5159 bp->rss_indir_tbl_entries = entries;
5160 bp->rss_indir_tbl = kmalloc_array(entries, sizeof(*bp->rss_indir_tbl),
5161 GFP_KERNEL);
5162 if (!bp->rss_indir_tbl)
5163 return -ENOMEM;
5164 return 0;
5165 }
5166
5167 static void bnxt_set_dflt_rss_indir_tbl(struct bnxt *bp)
5168 {
5169 u16 max_rings, max_entries, pad, i;
5170
5171 if (!bp->rx_nr_rings)
5172 return;
5173
5174 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5175 max_rings = bp->rx_nr_rings - 1;
5176 else
5177 max_rings = bp->rx_nr_rings;
5178
5179 max_entries = bnxt_get_rxfh_indir_size(bp->dev);
5180
5181 for (i = 0; i < max_entries; i++)
5182 bp->rss_indir_tbl[i] = ethtool_rxfh_indir_default(i, max_rings);
5183
5184 pad = bp->rss_indir_tbl_entries - max_entries;
5185 if (pad)
5186 memset(&bp->rss_indir_tbl[i], 0, pad * sizeof(u16));
5187 }
5188
5189 static u16 bnxt_get_max_rss_ring(struct bnxt *bp)
5190 {
5191 u16 i, tbl_size, max_ring = 0;
5192
5193 if (!bp->rss_indir_tbl)
5194 return 0;
5195
5196 tbl_size = bnxt_get_rxfh_indir_size(bp->dev);
5197 for (i = 0; i < tbl_size; i++)
5198 max_ring = max(max_ring, bp->rss_indir_tbl[i]);
5199 return max_ring;
5200 }
5201
5202 int bnxt_get_nr_rss_ctxs(struct bnxt *bp, int rx_rings)
5203 {
5204 if (bp->flags & BNXT_FLAG_CHIP_P5)
5205 return DIV_ROUND_UP(rx_rings, BNXT_RSS_TABLE_ENTRIES_P5);
5206 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5207 return 2;
5208 return 1;
5209 }
5210
5211 static void __bnxt_fill_hw_rss_tbl(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5212 {
5213 bool no_rss = !(vnic->flags & BNXT_VNIC_RSS_FLAG);
5214 u16 i, j;
5215
5216 /* Fill the RSS indirection table with ring group ids */
5217 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++) {
5218 if (!no_rss)
5219 j = bp->rss_indir_tbl[i];
5220 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
5221 }
5222 }
5223
5224 static void __bnxt_fill_hw_rss_tbl_p5(struct bnxt *bp,
5225 struct bnxt_vnic_info *vnic)
5226 {
5227 __le16 *ring_tbl = vnic->rss_table;
5228 struct bnxt_rx_ring_info *rxr;
5229 u16 tbl_size, i;
5230
5231 tbl_size = bnxt_get_rxfh_indir_size(bp->dev);
5232
5233 for (i = 0; i < tbl_size; i++) {
5234 u16 ring_id, j;
5235
5236 j = bp->rss_indir_tbl[i];
5237 rxr = &bp->rx_ring[j];
5238
5239 ring_id = rxr->rx_ring_struct.fw_ring_id;
5240 *ring_tbl++ = cpu_to_le16(ring_id);
5241 ring_id = bnxt_cp_ring_for_rx(bp, rxr);
5242 *ring_tbl++ = cpu_to_le16(ring_id);
5243 }
5244 }
5245
5246 static void bnxt_fill_hw_rss_tbl(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5247 {
5248 if (bp->flags & BNXT_FLAG_CHIP_P5)
5249 __bnxt_fill_hw_rss_tbl_p5(bp, vnic);
5250 else
5251 __bnxt_fill_hw_rss_tbl(bp, vnic);
5252 }
5253
5254 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
5255 {
5256 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5257 struct hwrm_vnic_rss_cfg_input req = {0};
5258
5259 if ((bp->flags & BNXT_FLAG_CHIP_P5) ||
5260 vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)
5261 return 0;
5262
5263 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
5264 if (set_rss) {
5265 bnxt_fill_hw_rss_tbl(bp, vnic);
5266 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
5267 req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT;
5268 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
5269 req.hash_key_tbl_addr =
5270 cpu_to_le64(vnic->rss_hash_key_dma_addr);
5271 }
5272 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
5273 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5274 }
5275
5276 static int bnxt_hwrm_vnic_set_rss_p5(struct bnxt *bp, u16 vnic_id, bool set_rss)
5277 {
5278 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5279 struct hwrm_vnic_rss_cfg_input req = {0};
5280 dma_addr_t ring_tbl_map;
5281 u32 i, nr_ctxs;
5282
5283 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
5284 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
5285 if (!set_rss) {
5286 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5287 return 0;
5288 }
5289 bnxt_fill_hw_rss_tbl(bp, vnic);
5290 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
5291 req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT;
5292 req.hash_key_tbl_addr = cpu_to_le64(vnic->rss_hash_key_dma_addr);
5293 ring_tbl_map = vnic->rss_table_dma_addr;
5294 nr_ctxs = bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings);
5295 for (i = 0; i < nr_ctxs; ring_tbl_map += BNXT_RSS_TABLE_SIZE_P5, i++) {
5296 int rc;
5297
5298 req.ring_grp_tbl_addr = cpu_to_le64(ring_tbl_map);
5299 req.ring_table_pair_index = i;
5300 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[i]);
5301 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5302 if (rc)
5303 return rc;
5304 }
5305 return 0;
5306 }
5307
5308 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
5309 {
5310 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5311 struct hwrm_vnic_plcmodes_cfg_input req = {0};
5312
5313 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
5314 req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
5315 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
5316 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
5317 req.enables =
5318 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
5319 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
5320 /* thresholds not implemented in firmware yet */
5321 req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
5322 req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
5323 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
5324 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5325 }
5326
5327 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id,
5328 u16 ctx_idx)
5329 {
5330 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
5331
5332 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
5333 req.rss_cos_lb_ctx_id =
5334 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]);
5335
5336 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5337 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID;
5338 }
5339
5340 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
5341 {
5342 int i, j;
5343
5344 for (i = 0; i < bp->nr_vnics; i++) {
5345 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
5346
5347 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) {
5348 if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID)
5349 bnxt_hwrm_vnic_ctx_free_one(bp, i, j);
5350 }
5351 }
5352 bp->rsscos_nr_ctxs = 0;
5353 }
5354
5355 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx)
5356 {
5357 int rc;
5358 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
5359 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
5360 bp->hwrm_cmd_resp_addr;
5361
5362 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
5363 -1);
5364
5365 mutex_lock(&bp->hwrm_cmd_lock);
5366 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5367 if (!rc)
5368 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] =
5369 le16_to_cpu(resp->rss_cos_lb_ctx_id);
5370 mutex_unlock(&bp->hwrm_cmd_lock);
5371
5372 return rc;
5373 }
5374
5375 static u32 bnxt_get_roce_vnic_mode(struct bnxt *bp)
5376 {
5377 if (bp->flags & BNXT_FLAG_ROCE_MIRROR_CAP)
5378 return VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE;
5379 return VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE;
5380 }
5381
5382 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
5383 {
5384 unsigned int ring = 0, grp_idx;
5385 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5386 struct hwrm_vnic_cfg_input req = {0};
5387 u16 def_vlan = 0;
5388
5389 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
5390
5391 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5392 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0];
5393
5394 req.default_rx_ring_id =
5395 cpu_to_le16(rxr->rx_ring_struct.fw_ring_id);
5396 req.default_cmpl_ring_id =
5397 cpu_to_le16(bnxt_cp_ring_for_rx(bp, rxr));
5398 req.enables =
5399 cpu_to_le32(VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID |
5400 VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID);
5401 goto vnic_mru;
5402 }
5403 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP);
5404 /* Only RSS support for now TBD: COS & LB */
5405 if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) {
5406 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
5407 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
5408 VNIC_CFG_REQ_ENABLES_MRU);
5409 } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) {
5410 req.rss_rule =
5411 cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]);
5412 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
5413 VNIC_CFG_REQ_ENABLES_MRU);
5414 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE);
5415 } else {
5416 req.rss_rule = cpu_to_le16(0xffff);
5417 }
5418
5419 if (BNXT_CHIP_TYPE_NITRO_A0(bp) &&
5420 (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) {
5421 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]);
5422 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE);
5423 } else {
5424 req.cos_rule = cpu_to_le16(0xffff);
5425 }
5426
5427 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
5428 ring = 0;
5429 else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
5430 ring = vnic_id - 1;
5431 else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp))
5432 ring = bp->rx_nr_rings - 1;
5433
5434 grp_idx = bp->rx_ring[ring].bnapi->index;
5435 req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
5436 req.lb_rule = cpu_to_le16(0xffff);
5437 vnic_mru:
5438 req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + VLAN_HLEN);
5439
5440 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
5441 #ifdef CONFIG_BNXT_SRIOV
5442 if (BNXT_VF(bp))
5443 def_vlan = bp->vf.vlan;
5444 #endif
5445 if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
5446 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
5447 if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP))
5448 req.flags |= cpu_to_le32(bnxt_get_roce_vnic_mode(bp));
5449
5450 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5451 }
5452
5453 static void bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
5454 {
5455 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
5456 struct hwrm_vnic_free_input req = {0};
5457
5458 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
5459 req.vnic_id =
5460 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
5461
5462 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5463 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
5464 }
5465 }
5466
5467 static void bnxt_hwrm_vnic_free(struct bnxt *bp)
5468 {
5469 u16 i;
5470
5471 for (i = 0; i < bp->nr_vnics; i++)
5472 bnxt_hwrm_vnic_free_one(bp, i);
5473 }
5474
5475 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
5476 unsigned int start_rx_ring_idx,
5477 unsigned int nr_rings)
5478 {
5479 int rc = 0;
5480 unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
5481 struct hwrm_vnic_alloc_input req = {0};
5482 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5483 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5484
5485 if (bp->flags & BNXT_FLAG_CHIP_P5)
5486 goto vnic_no_ring_grps;
5487
5488 /* map ring groups to this vnic */
5489 for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
5490 grp_idx = bp->rx_ring[i].bnapi->index;
5491 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
5492 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
5493 j, nr_rings);
5494 break;
5495 }
5496 vnic->fw_grp_ids[j] = bp->grp_info[grp_idx].fw_grp_id;
5497 }
5498
5499 vnic_no_ring_grps:
5500 for (i = 0; i < BNXT_MAX_CTX_PER_VNIC; i++)
5501 vnic->fw_rss_cos_lb_ctx[i] = INVALID_HW_RING_ID;
5502 if (vnic_id == 0)
5503 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
5504
5505 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
5506
5507 mutex_lock(&bp->hwrm_cmd_lock);
5508 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5509 if (!rc)
5510 vnic->fw_vnic_id = le32_to_cpu(resp->vnic_id);
5511 mutex_unlock(&bp->hwrm_cmd_lock);
5512 return rc;
5513 }
5514
5515 static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
5516 {
5517 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5518 struct hwrm_vnic_qcaps_input req = {0};
5519 int rc;
5520
5521 bp->hw_ring_stats_size = sizeof(struct ctx_hw_stats);
5522 bp->flags &= ~(BNXT_FLAG_NEW_RSS_CAP | BNXT_FLAG_ROCE_MIRROR_CAP);
5523 if (bp->hwrm_spec_code < 0x10600)
5524 return 0;
5525
5526 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1);
5527 mutex_lock(&bp->hwrm_cmd_lock);
5528 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5529 if (!rc) {
5530 u32 flags = le32_to_cpu(resp->flags);
5531
5532 if (!(bp->flags & BNXT_FLAG_CHIP_P5) &&
5533 (flags & VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP))
5534 bp->flags |= BNXT_FLAG_NEW_RSS_CAP;
5535 if (flags &
5536 VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP)
5537 bp->flags |= BNXT_FLAG_ROCE_MIRROR_CAP;
5538
5539 /* Older P5 fw before EXT_HW_STATS support did not set
5540 * VLAN_STRIP_CAP properly.
5541 */
5542 if ((flags & VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP) ||
5543 (BNXT_CHIP_P5_THOR(bp) &&
5544 !(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED)))
5545 bp->fw_cap |= BNXT_FW_CAP_VLAN_RX_STRIP;
5546 bp->max_tpa_v2 = le16_to_cpu(resp->max_aggs_supported);
5547 if (bp->max_tpa_v2) {
5548 if (BNXT_CHIP_P5_THOR(bp))
5549 bp->hw_ring_stats_size = BNXT_RING_STATS_SIZE_P5;
5550 else
5551 bp->hw_ring_stats_size = BNXT_RING_STATS_SIZE_P5_SR2;
5552 }
5553 }
5554 mutex_unlock(&bp->hwrm_cmd_lock);
5555 return rc;
5556 }
5557
5558 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
5559 {
5560 u16 i;
5561 u32 rc = 0;
5562
5563 if (bp->flags & BNXT_FLAG_CHIP_P5)
5564 return 0;
5565
5566 mutex_lock(&bp->hwrm_cmd_lock);
5567 for (i = 0; i < bp->rx_nr_rings; i++) {
5568 struct hwrm_ring_grp_alloc_input req = {0};
5569 struct hwrm_ring_grp_alloc_output *resp =
5570 bp->hwrm_cmd_resp_addr;
5571 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
5572
5573 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
5574
5575 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
5576 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
5577 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
5578 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
5579
5580 rc = _hwrm_send_message(bp, &req, sizeof(req),
5581 HWRM_CMD_TIMEOUT);
5582 if (rc)
5583 break;
5584
5585 bp->grp_info[grp_idx].fw_grp_id =
5586 le32_to_cpu(resp->ring_group_id);
5587 }
5588 mutex_unlock(&bp->hwrm_cmd_lock);
5589 return rc;
5590 }
5591
5592 static void bnxt_hwrm_ring_grp_free(struct bnxt *bp)
5593 {
5594 u16 i;
5595 struct hwrm_ring_grp_free_input req = {0};
5596
5597 if (!bp->grp_info || (bp->flags & BNXT_FLAG_CHIP_P5))
5598 return;
5599
5600 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
5601
5602 mutex_lock(&bp->hwrm_cmd_lock);
5603 for (i = 0; i < bp->cp_nr_rings; i++) {
5604 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
5605 continue;
5606 req.ring_group_id =
5607 cpu_to_le32(bp->grp_info[i].fw_grp_id);
5608
5609 _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5610 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
5611 }
5612 mutex_unlock(&bp->hwrm_cmd_lock);
5613 }
5614
5615 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
5616 struct bnxt_ring_struct *ring,
5617 u32 ring_type, u32 map_index)
5618 {
5619 int rc = 0, err = 0;
5620 struct hwrm_ring_alloc_input req = {0};
5621 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5622 struct bnxt_ring_mem_info *rmem = &ring->ring_mem;
5623 struct bnxt_ring_grp_info *grp_info;
5624 u16 ring_id;
5625
5626 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
5627
5628 req.enables = 0;
5629 if (rmem->nr_pages > 1) {
5630 req.page_tbl_addr = cpu_to_le64(rmem->pg_tbl_map);
5631 /* Page size is in log2 units */
5632 req.page_size = BNXT_PAGE_SHIFT;
5633 req.page_tbl_depth = 1;
5634 } else {
5635 req.page_tbl_addr = cpu_to_le64(rmem->dma_arr[0]);
5636 }
5637 req.fbo = 0;
5638 /* Association of ring index with doorbell index and MSIX number */
5639 req.logical_id = cpu_to_le16(map_index);
5640
5641 switch (ring_type) {
5642 case HWRM_RING_ALLOC_TX: {
5643 struct bnxt_tx_ring_info *txr;
5644
5645 txr = container_of(ring, struct bnxt_tx_ring_info,
5646 tx_ring_struct);
5647 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
5648 /* Association of transmit ring with completion ring */
5649 grp_info = &bp->grp_info[ring->grp_idx];
5650 req.cmpl_ring_id = cpu_to_le16(bnxt_cp_ring_for_tx(bp, txr));
5651 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
5652 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
5653 req.queue_id = cpu_to_le16(ring->queue_id);
5654 break;
5655 }
5656 case HWRM_RING_ALLOC_RX:
5657 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
5658 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
5659 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5660 u16 flags = 0;
5661
5662 /* Association of rx ring with stats context */
5663 grp_info = &bp->grp_info[ring->grp_idx];
5664 req.rx_buf_size = cpu_to_le16(bp->rx_buf_use_size);
5665 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
5666 req.enables |= cpu_to_le32(
5667 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID);
5668 if (NET_IP_ALIGN == 2)
5669 flags = RING_ALLOC_REQ_FLAGS_RX_SOP_PAD;
5670 req.flags = cpu_to_le16(flags);
5671 }
5672 break;
5673 case HWRM_RING_ALLOC_AGG:
5674 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5675 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX_AGG;
5676 /* Association of agg ring with rx ring */
5677 grp_info = &bp->grp_info[ring->grp_idx];
5678 req.rx_ring_id = cpu_to_le16(grp_info->rx_fw_ring_id);
5679 req.rx_buf_size = cpu_to_le16(BNXT_RX_PAGE_SIZE);
5680 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
5681 req.enables |= cpu_to_le32(
5682 RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID |
5683 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID);
5684 } else {
5685 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
5686 }
5687 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
5688 break;
5689 case HWRM_RING_ALLOC_CMPL:
5690 req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL;
5691 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
5692 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5693 /* Association of cp ring with nq */
5694 grp_info = &bp->grp_info[map_index];
5695 req.nq_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id);
5696 req.cq_handle = cpu_to_le64(ring->handle);
5697 req.enables |= cpu_to_le32(
5698 RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID);
5699 } else if (bp->flags & BNXT_FLAG_USING_MSIX) {
5700 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
5701 }
5702 break;
5703 case HWRM_RING_ALLOC_NQ:
5704 req.ring_type = RING_ALLOC_REQ_RING_TYPE_NQ;
5705 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
5706 if (bp->flags & BNXT_FLAG_USING_MSIX)
5707 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
5708 break;
5709 default:
5710 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
5711 ring_type);
5712 return -1;
5713 }
5714
5715 mutex_lock(&bp->hwrm_cmd_lock);
5716 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5717 err = le16_to_cpu(resp->error_code);
5718 ring_id = le16_to_cpu(resp->ring_id);
5719 mutex_unlock(&bp->hwrm_cmd_lock);
5720
5721 if (rc || err) {
5722 netdev_err(bp->dev, "hwrm_ring_alloc type %d failed. rc:%x err:%x\n",
5723 ring_type, rc, err);
5724 return -EIO;
5725 }
5726 ring->fw_ring_id = ring_id;
5727 return rc;
5728 }
5729
5730 static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx)
5731 {
5732 int rc;
5733
5734 if (BNXT_PF(bp)) {
5735 struct hwrm_func_cfg_input req = {0};
5736
5737 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
5738 req.fid = cpu_to_le16(0xffff);
5739 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
5740 req.async_event_cr = cpu_to_le16(idx);
5741 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5742 } else {
5743 struct hwrm_func_vf_cfg_input req = {0};
5744
5745 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1);
5746 req.enables =
5747 cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
5748 req.async_event_cr = cpu_to_le16(idx);
5749 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5750 }
5751 return rc;
5752 }
5753
5754 static void bnxt_set_db(struct bnxt *bp, struct bnxt_db_info *db, u32 ring_type,
5755 u32 map_idx, u32 xid)
5756 {
5757 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5758 if (BNXT_PF(bp))
5759 db->doorbell = bp->bar1 + DB_PF_OFFSET_P5;
5760 else
5761 db->doorbell = bp->bar1 + DB_VF_OFFSET_P5;
5762 switch (ring_type) {
5763 case HWRM_RING_ALLOC_TX:
5764 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SQ;
5765 break;
5766 case HWRM_RING_ALLOC_RX:
5767 case HWRM_RING_ALLOC_AGG:
5768 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SRQ;
5769 break;
5770 case HWRM_RING_ALLOC_CMPL:
5771 db->db_key64 = DBR_PATH_L2;
5772 break;
5773 case HWRM_RING_ALLOC_NQ:
5774 db->db_key64 = DBR_PATH_L2;
5775 break;
5776 }
5777 db->db_key64 |= (u64)xid << DBR_XID_SFT;
5778 } else {
5779 db->doorbell = bp->bar1 + map_idx * 0x80;
5780 switch (ring_type) {
5781 case HWRM_RING_ALLOC_TX:
5782 db->db_key32 = DB_KEY_TX;
5783 break;
5784 case HWRM_RING_ALLOC_RX:
5785 case HWRM_RING_ALLOC_AGG:
5786 db->db_key32 = DB_KEY_RX;
5787 break;
5788 case HWRM_RING_ALLOC_CMPL:
5789 db->db_key32 = DB_KEY_CP;
5790 break;
5791 }
5792 }
5793 }
5794
5795 static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
5796 {
5797 bool agg_rings = !!(bp->flags & BNXT_FLAG_AGG_RINGS);
5798 int i, rc = 0;
5799 u32 type;
5800
5801 if (bp->flags & BNXT_FLAG_CHIP_P5)
5802 type = HWRM_RING_ALLOC_NQ;
5803 else
5804 type = HWRM_RING_ALLOC_CMPL;
5805 for (i = 0; i < bp->cp_nr_rings; i++) {
5806 struct bnxt_napi *bnapi = bp->bnapi[i];
5807 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5808 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
5809 u32 map_idx = ring->map_idx;
5810 unsigned int vector;
5811
5812 vector = bp->irq_tbl[map_idx].vector;
5813 disable_irq_nosync(vector);
5814 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5815 if (rc) {
5816 enable_irq(vector);
5817 goto err_out;
5818 }
5819 bnxt_set_db(bp, &cpr->cp_db, type, map_idx, ring->fw_ring_id);
5820 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons);
5821 enable_irq(vector);
5822 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
5823
5824 if (!i) {
5825 rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id);
5826 if (rc)
5827 netdev_warn(bp->dev, "Failed to set async event completion ring.\n");
5828 }
5829 }
5830
5831 type = HWRM_RING_ALLOC_TX;
5832 for (i = 0; i < bp->tx_nr_rings; i++) {
5833 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
5834 struct bnxt_ring_struct *ring;
5835 u32 map_idx;
5836
5837 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5838 struct bnxt_napi *bnapi = txr->bnapi;
5839 struct bnxt_cp_ring_info *cpr, *cpr2;
5840 u32 type2 = HWRM_RING_ALLOC_CMPL;
5841
5842 cpr = &bnapi->cp_ring;
5843 cpr2 = cpr->cp_ring_arr[BNXT_TX_HDL];
5844 ring = &cpr2->cp_ring_struct;
5845 ring->handle = BNXT_TX_HDL;
5846 map_idx = bnapi->index;
5847 rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx);
5848 if (rc)
5849 goto err_out;
5850 bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx,
5851 ring->fw_ring_id);
5852 bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons);
5853 }
5854 ring = &txr->tx_ring_struct;
5855 map_idx = i;
5856 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5857 if (rc)
5858 goto err_out;
5859 bnxt_set_db(bp, &txr->tx_db, type, map_idx, ring->fw_ring_id);
5860 }
5861
5862 type = HWRM_RING_ALLOC_RX;
5863 for (i = 0; i < bp->rx_nr_rings; i++) {
5864 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5865 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
5866 struct bnxt_napi *bnapi = rxr->bnapi;
5867 u32 map_idx = bnapi->index;
5868
5869 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5870 if (rc)
5871 goto err_out;
5872 bnxt_set_db(bp, &rxr->rx_db, type, map_idx, ring->fw_ring_id);
5873 /* If we have agg rings, post agg buffers first. */
5874 if (!agg_rings)
5875 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
5876 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
5877 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5878 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5879 u32 type2 = HWRM_RING_ALLOC_CMPL;
5880 struct bnxt_cp_ring_info *cpr2;
5881
5882 cpr2 = cpr->cp_ring_arr[BNXT_RX_HDL];
5883 ring = &cpr2->cp_ring_struct;
5884 ring->handle = BNXT_RX_HDL;
5885 rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx);
5886 if (rc)
5887 goto err_out;
5888 bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx,
5889 ring->fw_ring_id);
5890 bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons);
5891 }
5892 }
5893
5894 if (agg_rings) {
5895 type = HWRM_RING_ALLOC_AGG;
5896 for (i = 0; i < bp->rx_nr_rings; i++) {
5897 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5898 struct bnxt_ring_struct *ring =
5899 &rxr->rx_agg_ring_struct;
5900 u32 grp_idx = ring->grp_idx;
5901 u32 map_idx = grp_idx + bp->rx_nr_rings;
5902
5903 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5904 if (rc)
5905 goto err_out;
5906
5907 bnxt_set_db(bp, &rxr->rx_agg_db, type, map_idx,
5908 ring->fw_ring_id);
5909 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
5910 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
5911 bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
5912 }
5913 }
5914 err_out:
5915 return rc;
5916 }
5917
5918 static int hwrm_ring_free_send_msg(struct bnxt *bp,
5919 struct bnxt_ring_struct *ring,
5920 u32 ring_type, int cmpl_ring_id)
5921 {
5922 int rc;
5923 struct hwrm_ring_free_input req = {0};
5924 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
5925 u16 error_code;
5926
5927 if (BNXT_NO_FW_ACCESS(bp))
5928 return 0;
5929
5930 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
5931 req.ring_type = ring_type;
5932 req.ring_id = cpu_to_le16(ring->fw_ring_id);
5933
5934 mutex_lock(&bp->hwrm_cmd_lock);
5935 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5936 error_code = le16_to_cpu(resp->error_code);
5937 mutex_unlock(&bp->hwrm_cmd_lock);
5938
5939 if (rc || error_code) {
5940 netdev_err(bp->dev, "hwrm_ring_free type %d failed. rc:%x err:%x\n",
5941 ring_type, rc, error_code);
5942 return -EIO;
5943 }
5944 return 0;
5945 }
5946
5947 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
5948 {
5949 u32 type;
5950 int i;
5951
5952 if (!bp->bnapi)
5953 return;
5954
5955 for (i = 0; i < bp->tx_nr_rings; i++) {
5956 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
5957 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
5958
5959 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5960 u32 cmpl_ring_id = bnxt_cp_ring_for_tx(bp, txr);
5961
5962 hwrm_ring_free_send_msg(bp, ring,
5963 RING_FREE_REQ_RING_TYPE_TX,
5964 close_path ? cmpl_ring_id :
5965 INVALID_HW_RING_ID);
5966 ring->fw_ring_id = INVALID_HW_RING_ID;
5967 }
5968 }
5969
5970 for (i = 0; i < bp->rx_nr_rings; i++) {
5971 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5972 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
5973 u32 grp_idx = rxr->bnapi->index;
5974
5975 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5976 u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr);
5977
5978 hwrm_ring_free_send_msg(bp, ring,
5979 RING_FREE_REQ_RING_TYPE_RX,
5980 close_path ? cmpl_ring_id :
5981 INVALID_HW_RING_ID);
5982 ring->fw_ring_id = INVALID_HW_RING_ID;
5983 bp->grp_info[grp_idx].rx_fw_ring_id =
5984 INVALID_HW_RING_ID;
5985 }
5986 }
5987
5988 if (bp->flags & BNXT_FLAG_CHIP_P5)
5989 type = RING_FREE_REQ_RING_TYPE_RX_AGG;
5990 else
5991 type = RING_FREE_REQ_RING_TYPE_RX;
5992 for (i = 0; i < bp->rx_nr_rings; i++) {
5993 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5994 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
5995 u32 grp_idx = rxr->bnapi->index;
5996
5997 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5998 u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr);
5999
6000 hwrm_ring_free_send_msg(bp, ring, type,
6001 close_path ? cmpl_ring_id :
6002 INVALID_HW_RING_ID);
6003 ring->fw_ring_id = INVALID_HW_RING_ID;
6004 bp->grp_info[grp_idx].agg_fw_ring_id =
6005 INVALID_HW_RING_ID;
6006 }
6007 }
6008
6009 /* The completion rings are about to be freed. After that the
6010 * IRQ doorbell will not work anymore. So we need to disable
6011 * IRQ here.
6012 */
6013 bnxt_disable_int_sync(bp);
6014
6015 if (bp->flags & BNXT_FLAG_CHIP_P5)
6016 type = RING_FREE_REQ_RING_TYPE_NQ;
6017 else
6018 type = RING_FREE_REQ_RING_TYPE_L2_CMPL;
6019 for (i = 0; i < bp->cp_nr_rings; i++) {
6020 struct bnxt_napi *bnapi = bp->bnapi[i];
6021 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6022 struct bnxt_ring_struct *ring;
6023 int j;
6024
6025 for (j = 0; j < 2; j++) {
6026 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
6027
6028 if (cpr2) {
6029 ring = &cpr2->cp_ring_struct;
6030 if (ring->fw_ring_id == INVALID_HW_RING_ID)
6031 continue;
6032 hwrm_ring_free_send_msg(bp, ring,
6033 RING_FREE_REQ_RING_TYPE_L2_CMPL,
6034 INVALID_HW_RING_ID);
6035 ring->fw_ring_id = INVALID_HW_RING_ID;
6036 }
6037 }
6038 ring = &cpr->cp_ring_struct;
6039 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
6040 hwrm_ring_free_send_msg(bp, ring, type,
6041 INVALID_HW_RING_ID);
6042 ring->fw_ring_id = INVALID_HW_RING_ID;
6043 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
6044 }
6045 }
6046 }
6047
6048 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
6049 bool shared);
6050
6051 static int bnxt_hwrm_get_rings(struct bnxt *bp)
6052 {
6053 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
6054 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6055 struct hwrm_func_qcfg_input req = {0};
6056 int rc;
6057
6058 if (bp->hwrm_spec_code < 0x10601)
6059 return 0;
6060
6061 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
6062 req.fid = cpu_to_le16(0xffff);
6063 mutex_lock(&bp->hwrm_cmd_lock);
6064 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6065 if (rc) {
6066 mutex_unlock(&bp->hwrm_cmd_lock);
6067 return rc;
6068 }
6069
6070 hw_resc->resv_tx_rings = le16_to_cpu(resp->alloc_tx_rings);
6071 if (BNXT_NEW_RM(bp)) {
6072 u16 cp, stats;
6073
6074 hw_resc->resv_rx_rings = le16_to_cpu(resp->alloc_rx_rings);
6075 hw_resc->resv_hw_ring_grps =
6076 le32_to_cpu(resp->alloc_hw_ring_grps);
6077 hw_resc->resv_vnics = le16_to_cpu(resp->alloc_vnics);
6078 cp = le16_to_cpu(resp->alloc_cmpl_rings);
6079 stats = le16_to_cpu(resp->alloc_stat_ctx);
6080 hw_resc->resv_irqs = cp;
6081 if (bp->flags & BNXT_FLAG_CHIP_P5) {
6082 int rx = hw_resc->resv_rx_rings;
6083 int tx = hw_resc->resv_tx_rings;
6084
6085 if (bp->flags & BNXT_FLAG_AGG_RINGS)
6086 rx >>= 1;
6087 if (cp < (rx + tx)) {
6088 bnxt_trim_rings(bp, &rx, &tx, cp, false);
6089 if (bp->flags & BNXT_FLAG_AGG_RINGS)
6090 rx <<= 1;
6091 hw_resc->resv_rx_rings = rx;
6092 hw_resc->resv_tx_rings = tx;
6093 }
6094 hw_resc->resv_irqs = le16_to_cpu(resp->alloc_msix);
6095 hw_resc->resv_hw_ring_grps = rx;
6096 }
6097 hw_resc->resv_cp_rings = cp;
6098 hw_resc->resv_stat_ctxs = stats;
6099 }
6100 mutex_unlock(&bp->hwrm_cmd_lock);
6101 return 0;
6102 }
6103
6104 /* Caller must hold bp->hwrm_cmd_lock */
6105 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings)
6106 {
6107 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
6108 struct hwrm_func_qcfg_input req = {0};
6109 int rc;
6110
6111 if (bp->hwrm_spec_code < 0x10601)
6112 return 0;
6113
6114 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
6115 req.fid = cpu_to_le16(fid);
6116 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6117 if (!rc)
6118 *tx_rings = le16_to_cpu(resp->alloc_tx_rings);
6119
6120 return rc;
6121 }
6122
6123 static bool bnxt_rfs_supported(struct bnxt *bp);
6124
6125 static void
6126 __bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, struct hwrm_func_cfg_input *req,
6127 int tx_rings, int rx_rings, int ring_grps,
6128 int cp_rings, int stats, int vnics)
6129 {
6130 u32 enables = 0;
6131
6132 bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_CFG, -1, -1);
6133 req->fid = cpu_to_le16(0xffff);
6134 enables |= tx_rings ? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
6135 req->num_tx_rings = cpu_to_le16(tx_rings);
6136 if (BNXT_NEW_RM(bp)) {
6137 enables |= rx_rings ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0;
6138 enables |= stats ? FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
6139 if (bp->flags & BNXT_FLAG_CHIP_P5) {
6140 enables |= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_MSIX : 0;
6141 enables |= tx_rings + ring_grps ?
6142 FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
6143 enables |= rx_rings ?
6144 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
6145 } else {
6146 enables |= cp_rings ?
6147 FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
6148 enables |= ring_grps ?
6149 FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS |
6150 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
6151 }
6152 enables |= vnics ? FUNC_CFG_REQ_ENABLES_NUM_VNICS : 0;
6153
6154 req->num_rx_rings = cpu_to_le16(rx_rings);
6155 if (bp->flags & BNXT_FLAG_CHIP_P5) {
6156 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps);
6157 req->num_msix = cpu_to_le16(cp_rings);
6158 req->num_rsscos_ctxs =
6159 cpu_to_le16(DIV_ROUND_UP(ring_grps, 64));
6160 } else {
6161 req->num_cmpl_rings = cpu_to_le16(cp_rings);
6162 req->num_hw_ring_grps = cpu_to_le16(ring_grps);
6163 req->num_rsscos_ctxs = cpu_to_le16(1);
6164 if (!(bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
6165 bnxt_rfs_supported(bp))
6166 req->num_rsscos_ctxs =
6167 cpu_to_le16(ring_grps + 1);
6168 }
6169 req->num_stat_ctxs = cpu_to_le16(stats);
6170 req->num_vnics = cpu_to_le16(vnics);
6171 }
6172 req->enables = cpu_to_le32(enables);
6173 }
6174
6175 static void
6176 __bnxt_hwrm_reserve_vf_rings(struct bnxt *bp,
6177 struct hwrm_func_vf_cfg_input *req, int tx_rings,
6178 int rx_rings, int ring_grps, int cp_rings,
6179 int stats, int vnics)
6180 {
6181 u32 enables = 0;
6182
6183 bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_VF_CFG, -1, -1);
6184 enables |= tx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
6185 enables |= rx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS |
6186 FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
6187 enables |= stats ? FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
6188 if (bp->flags & BNXT_FLAG_CHIP_P5) {
6189 enables |= tx_rings + ring_grps ?
6190 FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
6191 } else {
6192 enables |= cp_rings ?
6193 FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
6194 enables |= ring_grps ?
6195 FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0;
6196 }
6197 enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0;
6198 enables |= FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS;
6199
6200 req->num_l2_ctxs = cpu_to_le16(BNXT_VF_MAX_L2_CTX);
6201 req->num_tx_rings = cpu_to_le16(tx_rings);
6202 req->num_rx_rings = cpu_to_le16(rx_rings);
6203 if (bp->flags & BNXT_FLAG_CHIP_P5) {
6204 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps);
6205 req->num_rsscos_ctxs = cpu_to_le16(DIV_ROUND_UP(ring_grps, 64));
6206 } else {
6207 req->num_cmpl_rings = cpu_to_le16(cp_rings);
6208 req->num_hw_ring_grps = cpu_to_le16(ring_grps);
6209 req->num_rsscos_ctxs = cpu_to_le16(BNXT_VF_MAX_RSS_CTX);
6210 }
6211 req->num_stat_ctxs = cpu_to_le16(stats);
6212 req->num_vnics = cpu_to_le16(vnics);
6213
6214 req->enables = cpu_to_le32(enables);
6215 }
6216
6217 static int
6218 bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
6219 int ring_grps, int cp_rings, int stats, int vnics)
6220 {
6221 struct hwrm_func_cfg_input req = {0};
6222 int rc;
6223
6224 __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
6225 cp_rings, stats, vnics);
6226 if (!req.enables)
6227 return 0;
6228
6229 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6230 if (rc)
6231 return rc;
6232
6233 if (bp->hwrm_spec_code < 0x10601)
6234 bp->hw_resc.resv_tx_rings = tx_rings;
6235
6236 return bnxt_hwrm_get_rings(bp);
6237 }
6238
6239 static int
6240 bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
6241 int ring_grps, int cp_rings, int stats, int vnics)
6242 {
6243 struct hwrm_func_vf_cfg_input req = {0};
6244 int rc;
6245
6246 if (!BNXT_NEW_RM(bp)) {
6247 bp->hw_resc.resv_tx_rings = tx_rings;
6248 return 0;
6249 }
6250
6251 __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
6252 cp_rings, stats, vnics);
6253 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6254 if (rc)
6255 return rc;
6256
6257 return bnxt_hwrm_get_rings(bp);
6258 }
6259
6260 static int bnxt_hwrm_reserve_rings(struct bnxt *bp, int tx, int rx, int grp,
6261 int cp, int stat, int vnic)
6262 {
6263 if (BNXT_PF(bp))
6264 return bnxt_hwrm_reserve_pf_rings(bp, tx, rx, grp, cp, stat,
6265 vnic);
6266 else
6267 return bnxt_hwrm_reserve_vf_rings(bp, tx, rx, grp, cp, stat,
6268 vnic);
6269 }
6270
6271 int bnxt_nq_rings_in_use(struct bnxt *bp)
6272 {
6273 int cp = bp->cp_nr_rings;
6274 int ulp_msix, ulp_base;
6275
6276 ulp_msix = bnxt_get_ulp_msix_num(bp);
6277 if (ulp_msix) {
6278 ulp_base = bnxt_get_ulp_msix_base(bp);
6279 cp += ulp_msix;
6280 if ((ulp_base + ulp_msix) > cp)
6281 cp = ulp_base + ulp_msix;
6282 }
6283 return cp;
6284 }
6285
6286 static int bnxt_cp_rings_in_use(struct bnxt *bp)
6287 {
6288 int cp;
6289
6290 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
6291 return bnxt_nq_rings_in_use(bp);
6292
6293 cp = bp->tx_nr_rings + bp->rx_nr_rings;
6294 return cp;
6295 }
6296
6297 static int bnxt_get_func_stat_ctxs(struct bnxt *bp)
6298 {
6299 int ulp_stat = bnxt_get_ulp_stat_ctxs(bp);
6300 int cp = bp->cp_nr_rings;
6301
6302 if (!ulp_stat)
6303 return cp;
6304
6305 if (bnxt_nq_rings_in_use(bp) > cp + bnxt_get_ulp_msix_num(bp))
6306 return bnxt_get_ulp_msix_base(bp) + ulp_stat;
6307
6308 return cp + ulp_stat;
6309 }
6310
6311 /* Check if a default RSS map needs to be setup. This function is only
6312 * used on older firmware that does not require reserving RX rings.
6313 */
6314 static void bnxt_check_rss_tbl_no_rmgr(struct bnxt *bp)
6315 {
6316 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6317
6318 /* The RSS map is valid for RX rings set to resv_rx_rings */
6319 if (hw_resc->resv_rx_rings != bp->rx_nr_rings) {
6320 hw_resc->resv_rx_rings = bp->rx_nr_rings;
6321 if (!netif_is_rxfh_configured(bp->dev))
6322 bnxt_set_dflt_rss_indir_tbl(bp);
6323 }
6324 }
6325
6326 static bool bnxt_need_reserve_rings(struct bnxt *bp)
6327 {
6328 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6329 int cp = bnxt_cp_rings_in_use(bp);
6330 int nq = bnxt_nq_rings_in_use(bp);
6331 int rx = bp->rx_nr_rings, stat;
6332 int vnic = 1, grp = rx;
6333
6334 if (hw_resc->resv_tx_rings != bp->tx_nr_rings &&
6335 bp->hwrm_spec_code >= 0x10601)
6336 return true;
6337
6338 /* Old firmware does not need RX ring reservations but we still
6339 * need to setup a default RSS map when needed. With new firmware
6340 * we go through RX ring reservations first and then set up the
6341 * RSS map for the successfully reserved RX rings when needed.
6342 */
6343 if (!BNXT_NEW_RM(bp)) {
6344 bnxt_check_rss_tbl_no_rmgr(bp);
6345 return false;
6346 }
6347 if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5))
6348 vnic = rx + 1;
6349 if (bp->flags & BNXT_FLAG_AGG_RINGS)
6350 rx <<= 1;
6351 stat = bnxt_get_func_stat_ctxs(bp);
6352 if (hw_resc->resv_rx_rings != rx || hw_resc->resv_cp_rings != cp ||
6353 hw_resc->resv_vnics != vnic || hw_resc->resv_stat_ctxs != stat ||
6354 (hw_resc->resv_hw_ring_grps != grp &&
6355 !(bp->flags & BNXT_FLAG_CHIP_P5)))
6356 return true;
6357 if ((bp->flags & BNXT_FLAG_CHIP_P5) && BNXT_PF(bp) &&
6358 hw_resc->resv_irqs != nq)
6359 return true;
6360 return false;
6361 }
6362
6363 static int __bnxt_reserve_rings(struct bnxt *bp)
6364 {
6365 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6366 int cp = bnxt_nq_rings_in_use(bp);
6367 int tx = bp->tx_nr_rings;
6368 int rx = bp->rx_nr_rings;
6369 int grp, rx_rings, rc;
6370 int vnic = 1, stat;
6371 bool sh = false;
6372
6373 if (!bnxt_need_reserve_rings(bp))
6374 return 0;
6375
6376 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
6377 sh = true;
6378 if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5))
6379 vnic = rx + 1;
6380 if (bp->flags & BNXT_FLAG_AGG_RINGS)
6381 rx <<= 1;
6382 grp = bp->rx_nr_rings;
6383 stat = bnxt_get_func_stat_ctxs(bp);
6384
6385 rc = bnxt_hwrm_reserve_rings(bp, tx, rx, grp, cp, stat, vnic);
6386 if (rc)
6387 return rc;
6388
6389 tx = hw_resc->resv_tx_rings;
6390 if (BNXT_NEW_RM(bp)) {
6391 rx = hw_resc->resv_rx_rings;
6392 cp = hw_resc->resv_irqs;
6393 grp = hw_resc->resv_hw_ring_grps;
6394 vnic = hw_resc->resv_vnics;
6395 stat = hw_resc->resv_stat_ctxs;
6396 }
6397
6398 rx_rings = rx;
6399 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
6400 if (rx >= 2) {
6401 rx_rings = rx >> 1;
6402 } else {
6403 if (netif_running(bp->dev))
6404 return -ENOMEM;
6405
6406 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
6407 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
6408 bp->dev->hw_features &= ~NETIF_F_LRO;
6409 bp->dev->features &= ~NETIF_F_LRO;
6410 bnxt_set_ring_params(bp);
6411 }
6412 }
6413 rx_rings = min_t(int, rx_rings, grp);
6414 cp = min_t(int, cp, bp->cp_nr_rings);
6415 if (stat > bnxt_get_ulp_stat_ctxs(bp))
6416 stat -= bnxt_get_ulp_stat_ctxs(bp);
6417 cp = min_t(int, cp, stat);
6418 rc = bnxt_trim_rings(bp, &rx_rings, &tx, cp, sh);
6419 if (bp->flags & BNXT_FLAG_AGG_RINGS)
6420 rx = rx_rings << 1;
6421 cp = sh ? max_t(int, tx, rx_rings) : tx + rx_rings;
6422 bp->tx_nr_rings = tx;
6423
6424 /* If we cannot reserve all the RX rings, reset the RSS map only
6425 * if absolutely necessary
6426 */
6427 if (rx_rings != bp->rx_nr_rings) {
6428 netdev_warn(bp->dev, "Able to reserve only %d out of %d requested RX rings\n",
6429 rx_rings, bp->rx_nr_rings);
6430 if ((bp->dev->priv_flags & IFF_RXFH_CONFIGURED) &&
6431 (bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) !=
6432 bnxt_get_nr_rss_ctxs(bp, rx_rings) ||
6433 bnxt_get_max_rss_ring(bp) >= rx_rings)) {
6434 netdev_warn(bp->dev, "RSS table entries reverting to default\n");
6435 bp->dev->priv_flags &= ~IFF_RXFH_CONFIGURED;
6436 }
6437 }
6438 bp->rx_nr_rings = rx_rings;
6439 bp->cp_nr_rings = cp;
6440
6441 if (!tx || !rx || !cp || !grp || !vnic || !stat)
6442 return -ENOMEM;
6443
6444 if (!netif_is_rxfh_configured(bp->dev))
6445 bnxt_set_dflt_rss_indir_tbl(bp);
6446
6447 return rc;
6448 }
6449
6450 static int bnxt_hwrm_check_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
6451 int ring_grps, int cp_rings, int stats,
6452 int vnics)
6453 {
6454 struct hwrm_func_vf_cfg_input req = {0};
6455 u32 flags;
6456
6457 if (!BNXT_NEW_RM(bp))
6458 return 0;
6459
6460 __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
6461 cp_rings, stats, vnics);
6462 flags = FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST |
6463 FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST |
6464 FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
6465 FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
6466 FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST |
6467 FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST;
6468 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
6469 flags |= FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST;
6470
6471 req.flags = cpu_to_le32(flags);
6472 return hwrm_send_message_silent(bp, &req, sizeof(req),
6473 HWRM_CMD_TIMEOUT);
6474 }
6475
6476 static int bnxt_hwrm_check_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
6477 int ring_grps, int cp_rings, int stats,
6478 int vnics)
6479 {
6480 struct hwrm_func_cfg_input req = {0};
6481 u32 flags;
6482
6483 __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
6484 cp_rings, stats, vnics);
6485 flags = FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST;
6486 if (BNXT_NEW_RM(bp)) {
6487 flags |= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST |
6488 FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
6489 FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
6490 FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST;
6491 if (bp->flags & BNXT_FLAG_CHIP_P5)
6492 flags |= FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST |
6493 FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST;
6494 else
6495 flags |= FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST;
6496 }
6497
6498 req.flags = cpu_to_le32(flags);
6499 return hwrm_send_message_silent(bp, &req, sizeof(req),
6500 HWRM_CMD_TIMEOUT);
6501 }
6502
6503 static int bnxt_hwrm_check_rings(struct bnxt *bp, int tx_rings, int rx_rings,
6504 int ring_grps, int cp_rings, int stats,
6505 int vnics)
6506 {
6507 if (bp->hwrm_spec_code < 0x10801)
6508 return 0;
6509
6510 if (BNXT_PF(bp))
6511 return bnxt_hwrm_check_pf_rings(bp, tx_rings, rx_rings,
6512 ring_grps, cp_rings, stats,
6513 vnics);
6514
6515 return bnxt_hwrm_check_vf_rings(bp, tx_rings, rx_rings, ring_grps,
6516 cp_rings, stats, vnics);
6517 }
6518
6519 static void bnxt_hwrm_coal_params_qcaps(struct bnxt *bp)
6520 {
6521 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6522 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
6523 struct hwrm_ring_aggint_qcaps_input req = {0};
6524 int rc;
6525
6526 coal_cap->cmpl_params = BNXT_LEGACY_COAL_CMPL_PARAMS;
6527 coal_cap->num_cmpl_dma_aggr_max = 63;
6528 coal_cap->num_cmpl_dma_aggr_during_int_max = 63;
6529 coal_cap->cmpl_aggr_dma_tmr_max = 65535;
6530 coal_cap->cmpl_aggr_dma_tmr_during_int_max = 65535;
6531 coal_cap->int_lat_tmr_min_max = 65535;
6532 coal_cap->int_lat_tmr_max_max = 65535;
6533 coal_cap->num_cmpl_aggr_int_max = 65535;
6534 coal_cap->timer_units = 80;
6535
6536 if (bp->hwrm_spec_code < 0x10902)
6537 return;
6538
6539 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_AGGINT_QCAPS, -1, -1);
6540 mutex_lock(&bp->hwrm_cmd_lock);
6541 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6542 if (!rc) {
6543 coal_cap->cmpl_params = le32_to_cpu(resp->cmpl_params);
6544 coal_cap->nq_params = le32_to_cpu(resp->nq_params);
6545 coal_cap->num_cmpl_dma_aggr_max =
6546 le16_to_cpu(resp->num_cmpl_dma_aggr_max);
6547 coal_cap->num_cmpl_dma_aggr_during_int_max =
6548 le16_to_cpu(resp->num_cmpl_dma_aggr_during_int_max);
6549 coal_cap->cmpl_aggr_dma_tmr_max =
6550 le16_to_cpu(resp->cmpl_aggr_dma_tmr_max);
6551 coal_cap->cmpl_aggr_dma_tmr_during_int_max =
6552 le16_to_cpu(resp->cmpl_aggr_dma_tmr_during_int_max);
6553 coal_cap->int_lat_tmr_min_max =
6554 le16_to_cpu(resp->int_lat_tmr_min_max);
6555 coal_cap->int_lat_tmr_max_max =
6556 le16_to_cpu(resp->int_lat_tmr_max_max);
6557 coal_cap->num_cmpl_aggr_int_max =
6558 le16_to_cpu(resp->num_cmpl_aggr_int_max);
6559 coal_cap->timer_units = le16_to_cpu(resp->timer_units);
6560 }
6561 mutex_unlock(&bp->hwrm_cmd_lock);
6562 }
6563
6564 static u16 bnxt_usec_to_coal_tmr(struct bnxt *bp, u16 usec)
6565 {
6566 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
6567
6568 return usec * 1000 / coal_cap->timer_units;
6569 }
6570
6571 static void bnxt_hwrm_set_coal_params(struct bnxt *bp,
6572 struct bnxt_coal *hw_coal,
6573 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
6574 {
6575 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
6576 u32 cmpl_params = coal_cap->cmpl_params;
6577 u16 val, tmr, max, flags = 0;
6578
6579 max = hw_coal->bufs_per_record * 128;
6580 if (hw_coal->budget)
6581 max = hw_coal->bufs_per_record * hw_coal->budget;
6582 max = min_t(u16, max, coal_cap->num_cmpl_aggr_int_max);
6583
6584 val = clamp_t(u16, hw_coal->coal_bufs, 1, max);
6585 req->num_cmpl_aggr_int = cpu_to_le16(val);
6586
6587 val = min_t(u16, val, coal_cap->num_cmpl_dma_aggr_max);
6588 req->num_cmpl_dma_aggr = cpu_to_le16(val);
6589
6590 val = clamp_t(u16, hw_coal->coal_bufs_irq, 1,
6591 coal_cap->num_cmpl_dma_aggr_during_int_max);
6592 req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val);
6593
6594 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks);
6595 tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_max_max);
6596 req->int_lat_tmr_max = cpu_to_le16(tmr);
6597
6598 /* min timer set to 1/2 of interrupt timer */
6599 if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN) {
6600 val = tmr / 2;
6601 val = clamp_t(u16, val, 1, coal_cap->int_lat_tmr_min_max);
6602 req->int_lat_tmr_min = cpu_to_le16(val);
6603 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE);
6604 }
6605
6606 /* buf timer set to 1/4 of interrupt timer */
6607 val = clamp_t(u16, tmr / 4, 1, coal_cap->cmpl_aggr_dma_tmr_max);
6608 req->cmpl_aggr_dma_tmr = cpu_to_le16(val);
6609
6610 if (cmpl_params &
6611 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT) {
6612 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks_irq);
6613 val = clamp_t(u16, tmr, 1,
6614 coal_cap->cmpl_aggr_dma_tmr_during_int_max);
6615 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(val);
6616 req->enables |=
6617 cpu_to_le16(BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE);
6618 }
6619
6620 if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET)
6621 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
6622 if ((cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE) &&
6623 hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh)
6624 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
6625 req->flags = cpu_to_le16(flags);
6626 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_ENABLES);
6627 }
6628
6629 /* Caller holds bp->hwrm_cmd_lock */
6630 static int __bnxt_hwrm_set_coal_nq(struct bnxt *bp, struct bnxt_napi *bnapi,
6631 struct bnxt_coal *hw_coal)
6632 {
6633 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
6634 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6635 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
6636 u32 nq_params = coal_cap->nq_params;
6637 u16 tmr;
6638
6639 if (!(nq_params & RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN))
6640 return 0;
6641
6642 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
6643 -1, -1);
6644 req.ring_id = cpu_to_le16(cpr->cp_ring_struct.fw_ring_id);
6645 req.flags =
6646 cpu_to_le16(RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ);
6647
6648 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks) / 2;
6649 tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_min_max);
6650 req.int_lat_tmr_min = cpu_to_le16(tmr);
6651 req.enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE);
6652 return _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6653 }
6654
6655 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi)
6656 {
6657 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0};
6658 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6659 struct bnxt_coal coal;
6660
6661 /* Tick values in micro seconds.
6662 * 1 coal_buf x bufs_per_record = 1 completion record.
6663 */
6664 memcpy(&coal, &bp->rx_coal, sizeof(struct bnxt_coal));
6665
6666 coal.coal_ticks = cpr->rx_ring_coal.coal_ticks;
6667 coal.coal_bufs = cpr->rx_ring_coal.coal_bufs;
6668
6669 if (!bnapi->rx_ring)
6670 return -ENODEV;
6671
6672 bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
6673 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
6674
6675 bnxt_hwrm_set_coal_params(bp, &coal, &req_rx);
6676
6677 req_rx.ring_id = cpu_to_le16(bnxt_cp_ring_for_rx(bp, bnapi->rx_ring));
6678
6679 return hwrm_send_message(bp, &req_rx, sizeof(req_rx),
6680 HWRM_CMD_TIMEOUT);
6681 }
6682
6683 int bnxt_hwrm_set_coal(struct bnxt *bp)
6684 {
6685 int i, rc = 0;
6686 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
6687 req_tx = {0}, *req;
6688
6689 bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
6690 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
6691 bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
6692 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
6693
6694 bnxt_hwrm_set_coal_params(bp, &bp->rx_coal, &req_rx);
6695 bnxt_hwrm_set_coal_params(bp, &bp->tx_coal, &req_tx);
6696
6697 mutex_lock(&bp->hwrm_cmd_lock);
6698 for (i = 0; i < bp->cp_nr_rings; i++) {
6699 struct bnxt_napi *bnapi = bp->bnapi[i];
6700 struct bnxt_coal *hw_coal;
6701 u16 ring_id;
6702
6703 req = &req_rx;
6704 if (!bnapi->rx_ring) {
6705 ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring);
6706 req = &req_tx;
6707 } else {
6708 ring_id = bnxt_cp_ring_for_rx(bp, bnapi->rx_ring);
6709 }
6710 req->ring_id = cpu_to_le16(ring_id);
6711
6712 rc = _hwrm_send_message(bp, req, sizeof(*req),
6713 HWRM_CMD_TIMEOUT);
6714 if (rc)
6715 break;
6716
6717 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
6718 continue;
6719
6720 if (bnapi->rx_ring && bnapi->tx_ring) {
6721 req = &req_tx;
6722 ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring);
6723 req->ring_id = cpu_to_le16(ring_id);
6724 rc = _hwrm_send_message(bp, req, sizeof(*req),
6725 HWRM_CMD_TIMEOUT);
6726 if (rc)
6727 break;
6728 }
6729 if (bnapi->rx_ring)
6730 hw_coal = &bp->rx_coal;
6731 else
6732 hw_coal = &bp->tx_coal;
6733 __bnxt_hwrm_set_coal_nq(bp, bnapi, hw_coal);
6734 }
6735 mutex_unlock(&bp->hwrm_cmd_lock);
6736 return rc;
6737 }
6738
6739 static void bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
6740 {
6741 struct hwrm_stat_ctx_clr_stats_input req0 = {0};
6742 struct hwrm_stat_ctx_free_input req = {0};
6743 int i;
6744
6745 if (!bp->bnapi)
6746 return;
6747
6748 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
6749 return;
6750
6751 bnxt_hwrm_cmd_hdr_init(bp, &req0, HWRM_STAT_CTX_CLR_STATS, -1, -1);
6752 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
6753
6754 mutex_lock(&bp->hwrm_cmd_lock);
6755 for (i = 0; i < bp->cp_nr_rings; i++) {
6756 struct bnxt_napi *bnapi = bp->bnapi[i];
6757 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6758
6759 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
6760 req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
6761 if (BNXT_FW_MAJ(bp) <= 20) {
6762 req0.stat_ctx_id = req.stat_ctx_id;
6763 _hwrm_send_message(bp, &req0, sizeof(req0),
6764 HWRM_CMD_TIMEOUT);
6765 }
6766 _hwrm_send_message(bp, &req, sizeof(req),
6767 HWRM_CMD_TIMEOUT);
6768
6769 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
6770 }
6771 }
6772 mutex_unlock(&bp->hwrm_cmd_lock);
6773 }
6774
6775 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
6776 {
6777 int rc = 0, i;
6778 struct hwrm_stat_ctx_alloc_input req = {0};
6779 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
6780
6781 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
6782 return 0;
6783
6784 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
6785
6786 req.stats_dma_length = cpu_to_le16(bp->hw_ring_stats_size);
6787 req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000);
6788
6789 mutex_lock(&bp->hwrm_cmd_lock);
6790 for (i = 0; i < bp->cp_nr_rings; i++) {
6791 struct bnxt_napi *bnapi = bp->bnapi[i];
6792 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6793
6794 req.stats_dma_addr = cpu_to_le64(cpr->stats.hw_stats_map);
6795
6796 rc = _hwrm_send_message(bp, &req, sizeof(req),
6797 HWRM_CMD_TIMEOUT);
6798 if (rc)
6799 break;
6800
6801 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
6802
6803 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
6804 }
6805 mutex_unlock(&bp->hwrm_cmd_lock);
6806 return rc;
6807 }
6808
6809 static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
6810 {
6811 struct hwrm_func_qcfg_input req = {0};
6812 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
6813 u32 min_db_offset = 0;
6814 u16 flags;
6815 int rc;
6816
6817 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
6818 req.fid = cpu_to_le16(0xffff);
6819 mutex_lock(&bp->hwrm_cmd_lock);
6820 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6821 if (rc)
6822 goto func_qcfg_exit;
6823
6824 #ifdef CONFIG_BNXT_SRIOV
6825 if (BNXT_VF(bp)) {
6826 struct bnxt_vf_info *vf = &bp->vf;
6827
6828 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
6829 } else {
6830 bp->pf.registered_vfs = le16_to_cpu(resp->registered_vfs);
6831 }
6832 #endif
6833 flags = le16_to_cpu(resp->flags);
6834 if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED |
6835 FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) {
6836 bp->fw_cap |= BNXT_FW_CAP_LLDP_AGENT;
6837 if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED)
6838 bp->fw_cap |= BNXT_FW_CAP_DCBX_AGENT;
6839 }
6840 if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST))
6841 bp->flags |= BNXT_FLAG_MULTI_HOST;
6842 if (flags & FUNC_QCFG_RESP_FLAGS_RING_MONITOR_ENABLED)
6843 bp->fw_cap |= BNXT_FW_CAP_RING_MONITOR;
6844
6845 switch (resp->port_partition_type) {
6846 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
6847 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
6848 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0:
6849 bp->port_partition_type = resp->port_partition_type;
6850 break;
6851 }
6852 if (bp->hwrm_spec_code < 0x10707 ||
6853 resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB)
6854 bp->br_mode = BRIDGE_MODE_VEB;
6855 else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA)
6856 bp->br_mode = BRIDGE_MODE_VEPA;
6857 else
6858 bp->br_mode = BRIDGE_MODE_UNDEF;
6859
6860 bp->max_mtu = le16_to_cpu(resp->max_mtu_configured);
6861 if (!bp->max_mtu)
6862 bp->max_mtu = BNXT_MAX_MTU;
6863
6864 if (bp->db_size)
6865 goto func_qcfg_exit;
6866
6867 if (bp->flags & BNXT_FLAG_CHIP_P5) {
6868 if (BNXT_PF(bp))
6869 min_db_offset = DB_PF_OFFSET_P5;
6870 else
6871 min_db_offset = DB_VF_OFFSET_P5;
6872 }
6873 bp->db_size = PAGE_ALIGN(le16_to_cpu(resp->l2_doorbell_bar_size_kb) *
6874 1024);
6875 if (!bp->db_size || bp->db_size > pci_resource_len(bp->pdev, 2) ||
6876 bp->db_size <= min_db_offset)
6877 bp->db_size = pci_resource_len(bp->pdev, 2);
6878
6879 func_qcfg_exit:
6880 mutex_unlock(&bp->hwrm_cmd_lock);
6881 return rc;
6882 }
6883
6884 static void bnxt_init_ctx_initializer(struct bnxt_ctx_mem_info *ctx,
6885 struct hwrm_func_backing_store_qcaps_output *resp)
6886 {
6887 struct bnxt_mem_init *mem_init;
6888 u16 init_mask;
6889 u8 init_val;
6890 u8 *offset;
6891 int i;
6892
6893 init_val = resp->ctx_kind_initializer;
6894 init_mask = le16_to_cpu(resp->ctx_init_mask);
6895 offset = &resp->qp_init_offset;
6896 mem_init = &ctx->mem_init[BNXT_CTX_MEM_INIT_QP];
6897 for (i = 0; i < BNXT_CTX_MEM_INIT_MAX; i++, mem_init++, offset++) {
6898 mem_init->init_val = init_val;
6899 mem_init->offset = BNXT_MEM_INVALID_OFFSET;
6900 if (!init_mask)
6901 continue;
6902 if (i == BNXT_CTX_MEM_INIT_STAT)
6903 offset = &resp->stat_init_offset;
6904 if (init_mask & (1 << i))
6905 mem_init->offset = *offset * 4;
6906 else
6907 mem_init->init_val = 0;
6908 }
6909 ctx->mem_init[BNXT_CTX_MEM_INIT_QP].size = ctx->qp_entry_size;
6910 ctx->mem_init[BNXT_CTX_MEM_INIT_SRQ].size = ctx->srq_entry_size;
6911 ctx->mem_init[BNXT_CTX_MEM_INIT_CQ].size = ctx->cq_entry_size;
6912 ctx->mem_init[BNXT_CTX_MEM_INIT_VNIC].size = ctx->vnic_entry_size;
6913 ctx->mem_init[BNXT_CTX_MEM_INIT_STAT].size = ctx->stat_entry_size;
6914 ctx->mem_init[BNXT_CTX_MEM_INIT_MRAV].size = ctx->mrav_entry_size;
6915 }
6916
6917 static int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
6918 {
6919 struct hwrm_func_backing_store_qcaps_input req = {0};
6920 struct hwrm_func_backing_store_qcaps_output *resp =
6921 bp->hwrm_cmd_resp_addr;
6922 int rc;
6923
6924 if (bp->hwrm_spec_code < 0x10902 || BNXT_VF(bp) || bp->ctx)
6925 return 0;
6926
6927 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_QCAPS, -1, -1);
6928 mutex_lock(&bp->hwrm_cmd_lock);
6929 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6930 if (!rc) {
6931 struct bnxt_ctx_pg_info *ctx_pg;
6932 struct bnxt_ctx_mem_info *ctx;
6933 int i, tqm_rings;
6934
6935 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
6936 if (!ctx) {
6937 rc = -ENOMEM;
6938 goto ctx_err;
6939 }
6940 ctx->qp_max_entries = le32_to_cpu(resp->qp_max_entries);
6941 ctx->qp_min_qp1_entries = le16_to_cpu(resp->qp_min_qp1_entries);
6942 ctx->qp_max_l2_entries = le16_to_cpu(resp->qp_max_l2_entries);
6943 ctx->qp_entry_size = le16_to_cpu(resp->qp_entry_size);
6944 ctx->srq_max_l2_entries = le16_to_cpu(resp->srq_max_l2_entries);
6945 ctx->srq_max_entries = le32_to_cpu(resp->srq_max_entries);
6946 ctx->srq_entry_size = le16_to_cpu(resp->srq_entry_size);
6947 ctx->cq_max_l2_entries = le16_to_cpu(resp->cq_max_l2_entries);
6948 ctx->cq_max_entries = le32_to_cpu(resp->cq_max_entries);
6949 ctx->cq_entry_size = le16_to_cpu(resp->cq_entry_size);
6950 ctx->vnic_max_vnic_entries =
6951 le16_to_cpu(resp->vnic_max_vnic_entries);
6952 ctx->vnic_max_ring_table_entries =
6953 le16_to_cpu(resp->vnic_max_ring_table_entries);
6954 ctx->vnic_entry_size = le16_to_cpu(resp->vnic_entry_size);
6955 ctx->stat_max_entries = le32_to_cpu(resp->stat_max_entries);
6956 ctx->stat_entry_size = le16_to_cpu(resp->stat_entry_size);
6957 ctx->tqm_entry_size = le16_to_cpu(resp->tqm_entry_size);
6958 ctx->tqm_min_entries_per_ring =
6959 le32_to_cpu(resp->tqm_min_entries_per_ring);
6960 ctx->tqm_max_entries_per_ring =
6961 le32_to_cpu(resp->tqm_max_entries_per_ring);
6962 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
6963 if (!ctx->tqm_entries_multiple)
6964 ctx->tqm_entries_multiple = 1;
6965 ctx->mrav_max_entries = le32_to_cpu(resp->mrav_max_entries);
6966 ctx->mrav_entry_size = le16_to_cpu(resp->mrav_entry_size);
6967 ctx->mrav_num_entries_units =
6968 le16_to_cpu(resp->mrav_num_entries_units);
6969 ctx->tim_entry_size = le16_to_cpu(resp->tim_entry_size);
6970 ctx->tim_max_entries = le32_to_cpu(resp->tim_max_entries);
6971
6972 bnxt_init_ctx_initializer(ctx, resp);
6973
6974 ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
6975 if (!ctx->tqm_fp_rings_count)
6976 ctx->tqm_fp_rings_count = bp->max_q;
6977 else if (ctx->tqm_fp_rings_count > BNXT_MAX_TQM_FP_RINGS)
6978 ctx->tqm_fp_rings_count = BNXT_MAX_TQM_FP_RINGS;
6979
6980 tqm_rings = ctx->tqm_fp_rings_count + BNXT_MAX_TQM_SP_RINGS;
6981 ctx_pg = kcalloc(tqm_rings, sizeof(*ctx_pg), GFP_KERNEL);
6982 if (!ctx_pg) {
6983 kfree(ctx);
6984 rc = -ENOMEM;
6985 goto ctx_err;
6986 }
6987 for (i = 0; i < tqm_rings; i++, ctx_pg++)
6988 ctx->tqm_mem[i] = ctx_pg;
6989 bp->ctx = ctx;
6990 } else {
6991 rc = 0;
6992 }
6993 ctx_err:
6994 mutex_unlock(&bp->hwrm_cmd_lock);
6995 return rc;
6996 }
6997
6998 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem, u8 *pg_attr,
6999 __le64 *pg_dir)
7000 {
7001 if (!rmem->nr_pages)
7002 return;
7003
7004 BNXT_SET_CTX_PAGE_ATTR(*pg_attr);
7005 if (rmem->depth >= 1) {
7006 if (rmem->depth == 2)
7007 *pg_attr |= 2;
7008 else
7009 *pg_attr |= 1;
7010 *pg_dir = cpu_to_le64(rmem->pg_tbl_map);
7011 } else {
7012 *pg_dir = cpu_to_le64(rmem->dma_arr[0]);
7013 }
7014 }
7015
7016 #define FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES \
7017 (FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP | \
7018 FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ | \
7019 FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ | \
7020 FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC | \
7021 FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT)
7022
7023 static int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, u32 enables)
7024 {
7025 struct hwrm_func_backing_store_cfg_input req = {0};
7026 struct bnxt_ctx_mem_info *ctx = bp->ctx;
7027 struct bnxt_ctx_pg_info *ctx_pg;
7028 u32 req_len = sizeof(req);
7029 __le32 *num_entries;
7030 __le64 *pg_dir;
7031 u32 flags = 0;
7032 u8 *pg_attr;
7033 u32 ena;
7034 int i;
7035
7036 if (!ctx)
7037 return 0;
7038
7039 if (req_len > bp->hwrm_max_ext_req_len)
7040 req_len = BNXT_BACKING_STORE_CFG_LEGACY_LEN;
7041 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_CFG, -1, -1);
7042 req.enables = cpu_to_le32(enables);
7043
7044 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP) {
7045 ctx_pg = &ctx->qp_mem;
7046 req.qp_num_entries = cpu_to_le32(ctx_pg->entries);
7047 req.qp_num_qp1_entries = cpu_to_le16(ctx->qp_min_qp1_entries);
7048 req.qp_num_l2_entries = cpu_to_le16(ctx->qp_max_l2_entries);
7049 req.qp_entry_size = cpu_to_le16(ctx->qp_entry_size);
7050 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
7051 &req.qpc_pg_size_qpc_lvl,
7052 &req.qpc_page_dir);
7053 }
7054 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ) {
7055 ctx_pg = &ctx->srq_mem;
7056 req.srq_num_entries = cpu_to_le32(ctx_pg->entries);
7057 req.srq_num_l2_entries = cpu_to_le16(ctx->srq_max_l2_entries);
7058 req.srq_entry_size = cpu_to_le16(ctx->srq_entry_size);
7059 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
7060 &req.srq_pg_size_srq_lvl,
7061 &req.srq_page_dir);
7062 }
7063 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ) {
7064 ctx_pg = &ctx->cq_mem;
7065 req.cq_num_entries = cpu_to_le32(ctx_pg->entries);
7066 req.cq_num_l2_entries = cpu_to_le16(ctx->cq_max_l2_entries);
7067 req.cq_entry_size = cpu_to_le16(ctx->cq_entry_size);
7068 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, &req.cq_pg_size_cq_lvl,
7069 &req.cq_page_dir);
7070 }
7071 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC) {
7072 ctx_pg = &ctx->vnic_mem;
7073 req.vnic_num_vnic_entries =
7074 cpu_to_le16(ctx->vnic_max_vnic_entries);
7075 req.vnic_num_ring_table_entries =
7076 cpu_to_le16(ctx->vnic_max_ring_table_entries);
7077 req.vnic_entry_size = cpu_to_le16(ctx->vnic_entry_size);
7078 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
7079 &req.vnic_pg_size_vnic_lvl,
7080 &req.vnic_page_dir);
7081 }
7082 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) {
7083 ctx_pg = &ctx->stat_mem;
7084 req.stat_num_entries = cpu_to_le32(ctx->stat_max_entries);
7085 req.stat_entry_size = cpu_to_le16(ctx->stat_entry_size);
7086 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
7087 &req.stat_pg_size_stat_lvl,
7088 &req.stat_page_dir);
7089 }
7090 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV) {
7091 ctx_pg = &ctx->mrav_mem;
7092 req.mrav_num_entries = cpu_to_le32(ctx_pg->entries);
7093 if (ctx->mrav_num_entries_units)
7094 flags |=
7095 FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT;
7096 req.mrav_entry_size = cpu_to_le16(ctx->mrav_entry_size);
7097 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
7098 &req.mrav_pg_size_mrav_lvl,
7099 &req.mrav_page_dir);
7100 }
7101 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM) {
7102 ctx_pg = &ctx->tim_mem;
7103 req.tim_num_entries = cpu_to_le32(ctx_pg->entries);
7104 req.tim_entry_size = cpu_to_le16(ctx->tim_entry_size);
7105 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
7106 &req.tim_pg_size_tim_lvl,
7107 &req.tim_page_dir);
7108 }
7109 for (i = 0, num_entries = &req.tqm_sp_num_entries,
7110 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl,
7111 pg_dir = &req.tqm_sp_page_dir,
7112 ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP;
7113 i < BNXT_MAX_TQM_RINGS;
7114 i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
7115 if (!(enables & ena))
7116 continue;
7117
7118 req.tqm_entry_size = cpu_to_le16(ctx->tqm_entry_size);
7119 ctx_pg = ctx->tqm_mem[i];
7120 *num_entries = cpu_to_le32(ctx_pg->entries);
7121 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
7122 }
7123 req.flags = cpu_to_le32(flags);
7124 return hwrm_send_message(bp, &req, req_len, HWRM_CMD_TIMEOUT);
7125 }
7126
7127 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
7128 struct bnxt_ctx_pg_info *ctx_pg)
7129 {
7130 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
7131
7132 rmem->page_size = BNXT_PAGE_SIZE;
7133 rmem->pg_arr = ctx_pg->ctx_pg_arr;
7134 rmem->dma_arr = ctx_pg->ctx_dma_arr;
7135 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
7136 if (rmem->depth >= 1)
7137 rmem->flags |= BNXT_RMEM_USE_FULL_PAGE_FLAG;
7138 return bnxt_alloc_ring(bp, rmem);
7139 }
7140
7141 static int bnxt_alloc_ctx_pg_tbls(struct bnxt *bp,
7142 struct bnxt_ctx_pg_info *ctx_pg, u32 mem_size,
7143 u8 depth, struct bnxt_mem_init *mem_init)
7144 {
7145 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
7146 int rc;
7147
7148 if (!mem_size)
7149 return -EINVAL;
7150
7151 ctx_pg->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE);
7152 if (ctx_pg->nr_pages > MAX_CTX_TOTAL_PAGES) {
7153 ctx_pg->nr_pages = 0;
7154 return -EINVAL;
7155 }
7156 if (ctx_pg->nr_pages > MAX_CTX_PAGES || depth > 1) {
7157 int nr_tbls, i;
7158
7159 rmem->depth = 2;
7160 ctx_pg->ctx_pg_tbl = kcalloc(MAX_CTX_PAGES, sizeof(ctx_pg),
7161 GFP_KERNEL);
7162 if (!ctx_pg->ctx_pg_tbl)
7163 return -ENOMEM;
7164 nr_tbls = DIV_ROUND_UP(ctx_pg->nr_pages, MAX_CTX_PAGES);
7165 rmem->nr_pages = nr_tbls;
7166 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg);
7167 if (rc)
7168 return rc;
7169 for (i = 0; i < nr_tbls; i++) {
7170 struct bnxt_ctx_pg_info *pg_tbl;
7171
7172 pg_tbl = kzalloc(sizeof(*pg_tbl), GFP_KERNEL);
7173 if (!pg_tbl)
7174 return -ENOMEM;
7175 ctx_pg->ctx_pg_tbl[i] = pg_tbl;
7176 rmem = &pg_tbl->ring_mem;
7177 rmem->pg_tbl = ctx_pg->ctx_pg_arr[i];
7178 rmem->pg_tbl_map = ctx_pg->ctx_dma_arr[i];
7179 rmem->depth = 1;
7180 rmem->nr_pages = MAX_CTX_PAGES;
7181 rmem->mem_init = mem_init;
7182 if (i == (nr_tbls - 1)) {
7183 int rem = ctx_pg->nr_pages % MAX_CTX_PAGES;
7184
7185 if (rem)
7186 rmem->nr_pages = rem;
7187 }
7188 rc = bnxt_alloc_ctx_mem_blk(bp, pg_tbl);
7189 if (rc)
7190 break;
7191 }
7192 } else {
7193 rmem->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE);
7194 if (rmem->nr_pages > 1 || depth)
7195 rmem->depth = 1;
7196 rmem->mem_init = mem_init;
7197 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg);
7198 }
7199 return rc;
7200 }
7201
7202 static void bnxt_free_ctx_pg_tbls(struct bnxt *bp,
7203 struct bnxt_ctx_pg_info *ctx_pg)
7204 {
7205 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
7206
7207 if (rmem->depth > 1 || ctx_pg->nr_pages > MAX_CTX_PAGES ||
7208 ctx_pg->ctx_pg_tbl) {
7209 int i, nr_tbls = rmem->nr_pages;
7210
7211 for (i = 0; i < nr_tbls; i++) {
7212 struct bnxt_ctx_pg_info *pg_tbl;
7213 struct bnxt_ring_mem_info *rmem2;
7214
7215 pg_tbl = ctx_pg->ctx_pg_tbl[i];
7216 if (!pg_tbl)
7217 continue;
7218 rmem2 = &pg_tbl->ring_mem;
7219 bnxt_free_ring(bp, rmem2);
7220 ctx_pg->ctx_pg_arr[i] = NULL;
7221 kfree(pg_tbl);
7222 ctx_pg->ctx_pg_tbl[i] = NULL;
7223 }
7224 kfree(ctx_pg->ctx_pg_tbl);
7225 ctx_pg->ctx_pg_tbl = NULL;
7226 }
7227 bnxt_free_ring(bp, rmem);
7228 ctx_pg->nr_pages = 0;
7229 }
7230
7231 static void bnxt_free_ctx_mem(struct bnxt *bp)
7232 {
7233 struct bnxt_ctx_mem_info *ctx = bp->ctx;
7234 int i;
7235
7236 if (!ctx)
7237 return;
7238
7239 if (ctx->tqm_mem[0]) {
7240 for (i = 0; i < ctx->tqm_fp_rings_count + 1; i++)
7241 bnxt_free_ctx_pg_tbls(bp, ctx->tqm_mem[i]);
7242 kfree(ctx->tqm_mem[0]);
7243 ctx->tqm_mem[0] = NULL;
7244 }
7245
7246 bnxt_free_ctx_pg_tbls(bp, &ctx->tim_mem);
7247 bnxt_free_ctx_pg_tbls(bp, &ctx->mrav_mem);
7248 bnxt_free_ctx_pg_tbls(bp, &ctx->stat_mem);
7249 bnxt_free_ctx_pg_tbls(bp, &ctx->vnic_mem);
7250 bnxt_free_ctx_pg_tbls(bp, &ctx->cq_mem);
7251 bnxt_free_ctx_pg_tbls(bp, &ctx->srq_mem);
7252 bnxt_free_ctx_pg_tbls(bp, &ctx->qp_mem);
7253 ctx->flags &= ~BNXT_CTX_FLAG_INITED;
7254 }
7255
7256 static int bnxt_alloc_ctx_mem(struct bnxt *bp)
7257 {
7258 struct bnxt_ctx_pg_info *ctx_pg;
7259 struct bnxt_ctx_mem_info *ctx;
7260 struct bnxt_mem_init *init;
7261 u32 mem_size, ena, entries;
7262 u32 entries_sp, min;
7263 u32 num_mr, num_ah;
7264 u32 extra_srqs = 0;
7265 u32 extra_qps = 0;
7266 u8 pg_lvl = 1;
7267 int i, rc;
7268
7269 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
7270 if (rc) {
7271 netdev_err(bp->dev, "Failed querying context mem capability, rc = %d.\n",
7272 rc);
7273 return rc;
7274 }
7275 ctx = bp->ctx;
7276 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
7277 return 0;
7278
7279 if ((bp->flags & BNXT_FLAG_ROCE_CAP) && !is_kdump_kernel()) {
7280 pg_lvl = 2;
7281 extra_qps = 65536;
7282 extra_srqs = 8192;
7283 }
7284
7285 ctx_pg = &ctx->qp_mem;
7286 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries +
7287 extra_qps;
7288 if (ctx->qp_entry_size) {
7289 mem_size = ctx->qp_entry_size * ctx_pg->entries;
7290 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_QP];
7291 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, init);
7292 if (rc)
7293 return rc;
7294 }
7295
7296 ctx_pg = &ctx->srq_mem;
7297 ctx_pg->entries = ctx->srq_max_l2_entries + extra_srqs;
7298 if (ctx->srq_entry_size) {
7299 mem_size = ctx->srq_entry_size * ctx_pg->entries;
7300 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_SRQ];
7301 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, init);
7302 if (rc)
7303 return rc;
7304 }
7305
7306 ctx_pg = &ctx->cq_mem;
7307 ctx_pg->entries = ctx->cq_max_l2_entries + extra_qps * 2;
7308 if (ctx->cq_entry_size) {
7309 mem_size = ctx->cq_entry_size * ctx_pg->entries;
7310 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_CQ];
7311 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, init);
7312 if (rc)
7313 return rc;
7314 }
7315
7316 ctx_pg = &ctx->vnic_mem;
7317 ctx_pg->entries = ctx->vnic_max_vnic_entries +
7318 ctx->vnic_max_ring_table_entries;
7319 if (ctx->vnic_entry_size) {
7320 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
7321 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_VNIC];
7322 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, init);
7323 if (rc)
7324 return rc;
7325 }
7326
7327 ctx_pg = &ctx->stat_mem;
7328 ctx_pg->entries = ctx->stat_max_entries;
7329 if (ctx->stat_entry_size) {
7330 mem_size = ctx->stat_entry_size * ctx_pg->entries;
7331 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_STAT];
7332 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, init);
7333 if (rc)
7334 return rc;
7335 }
7336
7337 ena = 0;
7338 if (!(bp->flags & BNXT_FLAG_ROCE_CAP))
7339 goto skip_rdma;
7340
7341 ctx_pg = &ctx->mrav_mem;
7342 /* 128K extra is needed to accommodate static AH context
7343 * allocation by f/w.
7344 */
7345 num_mr = 1024 * 256;
7346 num_ah = 1024 * 128;
7347 ctx_pg->entries = num_mr + num_ah;
7348 if (ctx->mrav_entry_size) {
7349 mem_size = ctx->mrav_entry_size * ctx_pg->entries;
7350 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_MRAV];
7351 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 2, init);
7352 if (rc)
7353 return rc;
7354 }
7355 ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV;
7356 if (ctx->mrav_num_entries_units)
7357 ctx_pg->entries =
7358 ((num_mr / ctx->mrav_num_entries_units) << 16) |
7359 (num_ah / ctx->mrav_num_entries_units);
7360
7361 ctx_pg = &ctx->tim_mem;
7362 ctx_pg->entries = ctx->qp_mem.entries;
7363 if (ctx->tim_entry_size) {
7364 mem_size = ctx->tim_entry_size * ctx_pg->entries;
7365 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, NULL);
7366 if (rc)
7367 return rc;
7368 }
7369 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM;
7370
7371 skip_rdma:
7372 min = ctx->tqm_min_entries_per_ring;
7373 entries_sp = ctx->vnic_max_vnic_entries + ctx->qp_max_l2_entries +
7374 2 * (extra_qps + ctx->qp_min_qp1_entries) + min;
7375 entries_sp = roundup(entries_sp, ctx->tqm_entries_multiple);
7376 entries = ctx->qp_max_l2_entries + 2 * (extra_qps + ctx->qp_min_qp1_entries);
7377 entries = roundup(entries, ctx->tqm_entries_multiple);
7378 entries = clamp_t(u32, entries, min, ctx->tqm_max_entries_per_ring);
7379 for (i = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
7380 ctx_pg = ctx->tqm_mem[i];
7381 ctx_pg->entries = i ? entries : entries_sp;
7382 if (ctx->tqm_entry_size) {
7383 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
7384 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1,
7385 NULL);
7386 if (rc)
7387 return rc;
7388 }
7389 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP << i;
7390 }
7391 ena |= FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES;
7392 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
7393 if (rc) {
7394 netdev_err(bp->dev, "Failed configuring context mem, rc = %d.\n",
7395 rc);
7396 return rc;
7397 }
7398 ctx->flags |= BNXT_CTX_FLAG_INITED;
7399 return 0;
7400 }
7401
7402 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all)
7403 {
7404 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
7405 struct hwrm_func_resource_qcaps_input req = {0};
7406 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
7407 int rc;
7408
7409 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESOURCE_QCAPS, -1, -1);
7410 req.fid = cpu_to_le16(0xffff);
7411
7412 mutex_lock(&bp->hwrm_cmd_lock);
7413 rc = _hwrm_send_message_silent(bp, &req, sizeof(req),
7414 HWRM_CMD_TIMEOUT);
7415 if (rc)
7416 goto hwrm_func_resc_qcaps_exit;
7417
7418 hw_resc->max_tx_sch_inputs = le16_to_cpu(resp->max_tx_scheduler_inputs);
7419 if (!all)
7420 goto hwrm_func_resc_qcaps_exit;
7421
7422 hw_resc->min_rsscos_ctxs = le16_to_cpu(resp->min_rsscos_ctx);
7423 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
7424 hw_resc->min_cp_rings = le16_to_cpu(resp->min_cmpl_rings);
7425 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
7426 hw_resc->min_tx_rings = le16_to_cpu(resp->min_tx_rings);
7427 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
7428 hw_resc->min_rx_rings = le16_to_cpu(resp->min_rx_rings);
7429 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
7430 hw_resc->min_hw_ring_grps = le16_to_cpu(resp->min_hw_ring_grps);
7431 hw_resc->max_hw_ring_grps = le16_to_cpu(resp->max_hw_ring_grps);
7432 hw_resc->min_l2_ctxs = le16_to_cpu(resp->min_l2_ctxs);
7433 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
7434 hw_resc->min_vnics = le16_to_cpu(resp->min_vnics);
7435 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
7436 hw_resc->min_stat_ctxs = le16_to_cpu(resp->min_stat_ctx);
7437 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
7438
7439 if (bp->flags & BNXT_FLAG_CHIP_P5) {
7440 u16 max_msix = le16_to_cpu(resp->max_msix);
7441
7442 hw_resc->max_nqs = max_msix;
7443 hw_resc->max_hw_ring_grps = hw_resc->max_rx_rings;
7444 }
7445
7446 if (BNXT_PF(bp)) {
7447 struct bnxt_pf_info *pf = &bp->pf;
7448
7449 pf->vf_resv_strategy =
7450 le16_to_cpu(resp->vf_reservation_strategy);
7451 if (pf->vf_resv_strategy > BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC)
7452 pf->vf_resv_strategy = BNXT_VF_RESV_STRATEGY_MAXIMAL;
7453 }
7454 hwrm_func_resc_qcaps_exit:
7455 mutex_unlock(&bp->hwrm_cmd_lock);
7456 return rc;
7457 }
7458
7459 /* bp->hwrm_cmd_lock already held. */
7460 static int __bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
7461 {
7462 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
7463 struct hwrm_port_mac_ptp_qcfg_input req = {0};
7464 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
7465 u8 flags;
7466 int rc;
7467
7468 if (bp->hwrm_spec_code < 0x10801) {
7469 rc = -ENODEV;
7470 goto no_ptp;
7471 }
7472
7473 req.port_id = cpu_to_le16(bp->pf.port_id);
7474 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_MAC_PTP_QCFG, -1, -1);
7475 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7476 if (rc)
7477 goto no_ptp;
7478
7479 flags = resp->flags;
7480 if (!(flags & PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS)) {
7481 rc = -ENODEV;
7482 goto no_ptp;
7483 }
7484 if (!ptp) {
7485 ptp = kzalloc(sizeof(*ptp), GFP_KERNEL);
7486 if (!ptp)
7487 return -ENOMEM;
7488 ptp->bp = bp;
7489 bp->ptp_cfg = ptp;
7490 }
7491 if (flags & PORT_MAC_PTP_QCFG_RESP_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK) {
7492 ptp->refclk_regs[0] = le32_to_cpu(resp->ts_ref_clock_reg_lower);
7493 ptp->refclk_regs[1] = le32_to_cpu(resp->ts_ref_clock_reg_upper);
7494 } else if (bp->flags & BNXT_FLAG_CHIP_P5) {
7495 ptp->refclk_regs[0] = BNXT_TS_REG_TIMESYNC_TS0_LOWER;
7496 ptp->refclk_regs[1] = BNXT_TS_REG_TIMESYNC_TS0_UPPER;
7497 } else {
7498 rc = -ENODEV;
7499 goto no_ptp;
7500 }
7501 return 0;
7502
7503 no_ptp:
7504 kfree(ptp);
7505 bp->ptp_cfg = NULL;
7506 return rc;
7507 }
7508
7509 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
7510 {
7511 int rc = 0;
7512 struct hwrm_func_qcaps_input req = {0};
7513 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
7514 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
7515 u32 flags, flags_ext;
7516
7517 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
7518 req.fid = cpu_to_le16(0xffff);
7519
7520 mutex_lock(&bp->hwrm_cmd_lock);
7521 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7522 if (rc)
7523 goto hwrm_func_qcaps_exit;
7524
7525 flags = le32_to_cpu(resp->flags);
7526 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED)
7527 bp->flags |= BNXT_FLAG_ROCEV1_CAP;
7528 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED)
7529 bp->flags |= BNXT_FLAG_ROCEV2_CAP;
7530 if (flags & FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED)
7531 bp->fw_cap |= BNXT_FW_CAP_PCIE_STATS_SUPPORTED;
7532 if (flags & FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE)
7533 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
7534 if (flags & FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED)
7535 bp->fw_cap |= BNXT_FW_CAP_EXT_STATS_SUPPORTED;
7536 if (flags & FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE)
7537 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
7538 if (flags & FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD)
7539 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
7540 if (!(flags & FUNC_QCAPS_RESP_FLAGS_VLAN_ACCELERATION_TX_DISABLED))
7541 bp->fw_cap |= BNXT_FW_CAP_VLAN_TX_INSERT;
7542
7543 flags_ext = le32_to_cpu(resp->flags_ext);
7544 if (flags_ext & FUNC_QCAPS_RESP_FLAGS_EXT_EXT_HW_STATS_SUPPORTED)
7545 bp->fw_cap |= BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED;
7546
7547 bp->tx_push_thresh = 0;
7548 if ((flags & FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED) &&
7549 BNXT_FW_MAJ(bp) > 217)
7550 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
7551
7552 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
7553 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
7554 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
7555 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
7556 hw_resc->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
7557 if (!hw_resc->max_hw_ring_grps)
7558 hw_resc->max_hw_ring_grps = hw_resc->max_tx_rings;
7559 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
7560 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
7561 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
7562
7563 if (BNXT_PF(bp)) {
7564 struct bnxt_pf_info *pf = &bp->pf;
7565
7566 pf->fw_fid = le16_to_cpu(resp->fid);
7567 pf->port_id = le16_to_cpu(resp->port_id);
7568 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
7569 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
7570 pf->max_vfs = le16_to_cpu(resp->max_vfs);
7571 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
7572 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
7573 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
7574 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
7575 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
7576 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
7577 bp->flags &= ~BNXT_FLAG_WOL_CAP;
7578 if (flags & FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED)
7579 bp->flags |= BNXT_FLAG_WOL_CAP;
7580 if (flags & FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED) {
7581 __bnxt_hwrm_ptp_qcfg(bp);
7582 } else {
7583 kfree(bp->ptp_cfg);
7584 bp->ptp_cfg = NULL;
7585 }
7586 } else {
7587 #ifdef CONFIG_BNXT_SRIOV
7588 struct bnxt_vf_info *vf = &bp->vf;
7589
7590 vf->fw_fid = le16_to_cpu(resp->fid);
7591 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
7592 #endif
7593 }
7594
7595 hwrm_func_qcaps_exit:
7596 mutex_unlock(&bp->hwrm_cmd_lock);
7597 return rc;
7598 }
7599
7600 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp);
7601
7602 static int bnxt_hwrm_func_qcaps(struct bnxt *bp)
7603 {
7604 int rc;
7605
7606 rc = __bnxt_hwrm_func_qcaps(bp);
7607 if (rc)
7608 return rc;
7609 rc = bnxt_hwrm_queue_qportcfg(bp);
7610 if (rc) {
7611 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %d\n", rc);
7612 return rc;
7613 }
7614 if (bp->hwrm_spec_code >= 0x10803) {
7615 rc = bnxt_alloc_ctx_mem(bp);
7616 if (rc)
7617 return rc;
7618 rc = bnxt_hwrm_func_resc_qcaps(bp, true);
7619 if (!rc)
7620 bp->fw_cap |= BNXT_FW_CAP_NEW_RM;
7621 }
7622 return 0;
7623 }
7624
7625 static int bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(struct bnxt *bp)
7626 {
7627 struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
7628 struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp;
7629 int rc = 0;
7630 u32 flags;
7631
7632 if (!(bp->fw_cap & BNXT_FW_CAP_CFA_ADV_FLOW))
7633 return 0;
7634
7635 resp = bp->hwrm_cmd_resp_addr;
7636 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, -1, -1);
7637
7638 mutex_lock(&bp->hwrm_cmd_lock);
7639 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7640 if (rc)
7641 goto hwrm_cfa_adv_qcaps_exit;
7642
7643 flags = le32_to_cpu(resp->flags);
7644 if (flags &
7645 CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED)
7646 bp->fw_cap |= BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2;
7647
7648 hwrm_cfa_adv_qcaps_exit:
7649 mutex_unlock(&bp->hwrm_cmd_lock);
7650 return rc;
7651 }
7652
7653 static int __bnxt_alloc_fw_health(struct bnxt *bp)
7654 {
7655 if (bp->fw_health)
7656 return 0;
7657
7658 bp->fw_health = kzalloc(sizeof(*bp->fw_health), GFP_KERNEL);
7659 if (!bp->fw_health)
7660 return -ENOMEM;
7661
7662 return 0;
7663 }
7664
7665 static int bnxt_alloc_fw_health(struct bnxt *bp)
7666 {
7667 int rc;
7668
7669 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET) &&
7670 !(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
7671 return 0;
7672
7673 rc = __bnxt_alloc_fw_health(bp);
7674 if (rc) {
7675 bp->fw_cap &= ~BNXT_FW_CAP_HOT_RESET;
7676 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
7677 return rc;
7678 }
7679
7680 return 0;
7681 }
7682
7683 static void __bnxt_map_fw_health_reg(struct bnxt *bp, u32 reg)
7684 {
7685 writel(reg & BNXT_GRC_BASE_MASK, bp->bar0 +
7686 BNXT_GRCPF_REG_WINDOW_BASE_OUT +
7687 BNXT_FW_HEALTH_WIN_MAP_OFF);
7688 }
7689
7690 bool bnxt_is_fw_healthy(struct bnxt *bp)
7691 {
7692 if (bp->fw_health && bp->fw_health->status_reliable) {
7693 u32 fw_status;
7694
7695 fw_status = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG);
7696 if (fw_status && !BNXT_FW_IS_HEALTHY(fw_status))
7697 return false;
7698 }
7699
7700 return true;
7701 }
7702
7703 static void bnxt_inv_fw_health_reg(struct bnxt *bp)
7704 {
7705 struct bnxt_fw_health *fw_health = bp->fw_health;
7706 u32 reg_type;
7707
7708 if (!fw_health || !fw_health->status_reliable)
7709 return;
7710
7711 reg_type = BNXT_FW_HEALTH_REG_TYPE(fw_health->regs[BNXT_FW_HEALTH_REG]);
7712 if (reg_type == BNXT_FW_HEALTH_REG_TYPE_GRC)
7713 fw_health->status_reliable = false;
7714 }
7715
7716 static void bnxt_try_map_fw_health_reg(struct bnxt *bp)
7717 {
7718 void __iomem *hs;
7719 u32 status_loc;
7720 u32 reg_type;
7721 u32 sig;
7722
7723 if (bp->fw_health)
7724 bp->fw_health->status_reliable = false;
7725
7726 __bnxt_map_fw_health_reg(bp, HCOMM_STATUS_STRUCT_LOC);
7727 hs = bp->bar0 + BNXT_FW_HEALTH_WIN_OFF(HCOMM_STATUS_STRUCT_LOC);
7728
7729 sig = readl(hs + offsetof(struct hcomm_status, sig_ver));
7730 if ((sig & HCOMM_STATUS_SIGNATURE_MASK) != HCOMM_STATUS_SIGNATURE_VAL) {
7731 if (!bp->chip_num) {
7732 __bnxt_map_fw_health_reg(bp, BNXT_GRC_REG_BASE);
7733 bp->chip_num = readl(bp->bar0 +
7734 BNXT_FW_HEALTH_WIN_BASE +
7735 BNXT_GRC_REG_CHIP_NUM);
7736 }
7737 if (!BNXT_CHIP_P5(bp))
7738 return;
7739
7740 status_loc = BNXT_GRC_REG_STATUS_P5 |
7741 BNXT_FW_HEALTH_REG_TYPE_BAR0;
7742 } else {
7743 status_loc = readl(hs + offsetof(struct hcomm_status,
7744 fw_status_loc));
7745 }
7746
7747 if (__bnxt_alloc_fw_health(bp)) {
7748 netdev_warn(bp->dev, "no memory for firmware status checks\n");
7749 return;
7750 }
7751
7752 bp->fw_health->regs[BNXT_FW_HEALTH_REG] = status_loc;
7753 reg_type = BNXT_FW_HEALTH_REG_TYPE(status_loc);
7754 if (reg_type == BNXT_FW_HEALTH_REG_TYPE_GRC) {
7755 __bnxt_map_fw_health_reg(bp, status_loc);
7756 bp->fw_health->mapped_regs[BNXT_FW_HEALTH_REG] =
7757 BNXT_FW_HEALTH_WIN_OFF(status_loc);
7758 }
7759
7760 bp->fw_health->status_reliable = true;
7761 }
7762
7763 static int bnxt_map_fw_health_regs(struct bnxt *bp)
7764 {
7765 struct bnxt_fw_health *fw_health = bp->fw_health;
7766 u32 reg_base = 0xffffffff;
7767 int i;
7768
7769 bp->fw_health->status_reliable = false;
7770 /* Only pre-map the monitoring GRC registers using window 3 */
7771 for (i = 0; i < 4; i++) {
7772 u32 reg = fw_health->regs[i];
7773
7774 if (BNXT_FW_HEALTH_REG_TYPE(reg) != BNXT_FW_HEALTH_REG_TYPE_GRC)
7775 continue;
7776 if (reg_base == 0xffffffff)
7777 reg_base = reg & BNXT_GRC_BASE_MASK;
7778 if ((reg & BNXT_GRC_BASE_MASK) != reg_base)
7779 return -ERANGE;
7780 fw_health->mapped_regs[i] = BNXT_FW_HEALTH_WIN_OFF(reg);
7781 }
7782 bp->fw_health->status_reliable = true;
7783 if (reg_base == 0xffffffff)
7784 return 0;
7785
7786 __bnxt_map_fw_health_reg(bp, reg_base);
7787 return 0;
7788 }
7789
7790 static int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
7791 {
7792 struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
7793 struct bnxt_fw_health *fw_health = bp->fw_health;
7794 struct hwrm_error_recovery_qcfg_input req = {0};
7795 int rc, i;
7796
7797 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
7798 return 0;
7799
7800 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_ERROR_RECOVERY_QCFG, -1, -1);
7801 mutex_lock(&bp->hwrm_cmd_lock);
7802 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7803 if (rc)
7804 goto err_recovery_out;
7805 fw_health->flags = le32_to_cpu(resp->flags);
7806 if ((fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) &&
7807 !(bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL)) {
7808 rc = -EINVAL;
7809 goto err_recovery_out;
7810 }
7811 fw_health->polling_dsecs = le32_to_cpu(resp->driver_polling_freq);
7812 fw_health->master_func_wait_dsecs =
7813 le32_to_cpu(resp->master_func_wait_period);
7814 fw_health->normal_func_wait_dsecs =
7815 le32_to_cpu(resp->normal_func_wait_period);
7816 fw_health->post_reset_wait_dsecs =
7817 le32_to_cpu(resp->master_func_wait_period_after_reset);
7818 fw_health->post_reset_max_wait_dsecs =
7819 le32_to_cpu(resp->max_bailout_time_after_reset);
7820 fw_health->regs[BNXT_FW_HEALTH_REG] =
7821 le32_to_cpu(resp->fw_health_status_reg);
7822 fw_health->regs[BNXT_FW_HEARTBEAT_REG] =
7823 le32_to_cpu(resp->fw_heartbeat_reg);
7824 fw_health->regs[BNXT_FW_RESET_CNT_REG] =
7825 le32_to_cpu(resp->fw_reset_cnt_reg);
7826 fw_health->regs[BNXT_FW_RESET_INPROG_REG] =
7827 le32_to_cpu(resp->reset_inprogress_reg);
7828 fw_health->fw_reset_inprog_reg_mask =
7829 le32_to_cpu(resp->reset_inprogress_reg_mask);
7830 fw_health->fw_reset_seq_cnt = resp->reg_array_cnt;
7831 if (fw_health->fw_reset_seq_cnt >= 16) {
7832 rc = -EINVAL;
7833 goto err_recovery_out;
7834 }
7835 for (i = 0; i < fw_health->fw_reset_seq_cnt; i++) {
7836 fw_health->fw_reset_seq_regs[i] =
7837 le32_to_cpu(resp->reset_reg[i]);
7838 fw_health->fw_reset_seq_vals[i] =
7839 le32_to_cpu(resp->reset_reg_val[i]);
7840 fw_health->fw_reset_seq_delay_msec[i] =
7841 resp->delay_after_reset[i];
7842 }
7843 err_recovery_out:
7844 mutex_unlock(&bp->hwrm_cmd_lock);
7845 if (!rc)
7846 rc = bnxt_map_fw_health_regs(bp);
7847 if (rc)
7848 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
7849 return rc;
7850 }
7851
7852 static int bnxt_hwrm_func_reset(struct bnxt *bp)
7853 {
7854 struct hwrm_func_reset_input req = {0};
7855
7856 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
7857 req.enables = 0;
7858
7859 return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
7860 }
7861
7862 static void bnxt_nvm_cfg_ver_get(struct bnxt *bp)
7863 {
7864 struct hwrm_nvm_get_dev_info_output nvm_info;
7865
7866 if (!bnxt_hwrm_nvm_get_dev_info(bp, &nvm_info))
7867 snprintf(bp->nvm_cfg_ver, FW_VER_STR_LEN, "%d.%d.%d",
7868 nvm_info.nvm_cfg_ver_maj, nvm_info.nvm_cfg_ver_min,
7869 nvm_info.nvm_cfg_ver_upd);
7870 }
7871
7872 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
7873 {
7874 int rc = 0;
7875 struct hwrm_queue_qportcfg_input req = {0};
7876 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
7877 u8 i, j, *qptr;
7878 bool no_rdma;
7879
7880 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
7881
7882 mutex_lock(&bp->hwrm_cmd_lock);
7883 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7884 if (rc)
7885 goto qportcfg_exit;
7886
7887 if (!resp->max_configurable_queues) {
7888 rc = -EINVAL;
7889 goto qportcfg_exit;
7890 }
7891 bp->max_tc = resp->max_configurable_queues;
7892 bp->max_lltc = resp->max_configurable_lossless_queues;
7893 if (bp->max_tc > BNXT_MAX_QUEUE)
7894 bp->max_tc = BNXT_MAX_QUEUE;
7895
7896 no_rdma = !(bp->flags & BNXT_FLAG_ROCE_CAP);
7897 qptr = &resp->queue_id0;
7898 for (i = 0, j = 0; i < bp->max_tc; i++) {
7899 bp->q_info[j].queue_id = *qptr;
7900 bp->q_ids[i] = *qptr++;
7901 bp->q_info[j].queue_profile = *qptr++;
7902 bp->tc_to_qidx[j] = j;
7903 if (!BNXT_CNPQ(bp->q_info[j].queue_profile) ||
7904 (no_rdma && BNXT_PF(bp)))
7905 j++;
7906 }
7907 bp->max_q = bp->max_tc;
7908 bp->max_tc = max_t(u8, j, 1);
7909
7910 if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG)
7911 bp->max_tc = 1;
7912
7913 if (bp->max_lltc > bp->max_tc)
7914 bp->max_lltc = bp->max_tc;
7915
7916 qportcfg_exit:
7917 mutex_unlock(&bp->hwrm_cmd_lock);
7918 return rc;
7919 }
7920
7921 static int __bnxt_hwrm_ver_get(struct bnxt *bp, bool silent)
7922 {
7923 struct hwrm_ver_get_input req = {0};
7924 int rc;
7925
7926 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
7927 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
7928 req.hwrm_intf_min = HWRM_VERSION_MINOR;
7929 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
7930
7931 rc = bnxt_hwrm_do_send_msg(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT,
7932 silent);
7933 return rc;
7934 }
7935
7936 static int bnxt_hwrm_ver_get(struct bnxt *bp)
7937 {
7938 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
7939 u16 fw_maj, fw_min, fw_bld, fw_rsv;
7940 u32 dev_caps_cfg, hwrm_ver;
7941 int rc, len;
7942
7943 bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
7944 mutex_lock(&bp->hwrm_cmd_lock);
7945 rc = __bnxt_hwrm_ver_get(bp, false);
7946 if (rc)
7947 goto hwrm_ver_get_exit;
7948
7949 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
7950
7951 bp->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 |
7952 resp->hwrm_intf_min_8b << 8 |
7953 resp->hwrm_intf_upd_8b;
7954 if (resp->hwrm_intf_maj_8b < 1) {
7955 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
7956 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
7957 resp->hwrm_intf_upd_8b);
7958 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
7959 }
7960
7961 hwrm_ver = HWRM_VERSION_MAJOR << 16 | HWRM_VERSION_MINOR << 8 |
7962 HWRM_VERSION_UPDATE;
7963
7964 if (bp->hwrm_spec_code > hwrm_ver)
7965 snprintf(bp->hwrm_ver_supp, FW_VER_STR_LEN, "%d.%d.%d",
7966 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR,
7967 HWRM_VERSION_UPDATE);
7968 else
7969 snprintf(bp->hwrm_ver_supp, FW_VER_STR_LEN, "%d.%d.%d",
7970 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
7971 resp->hwrm_intf_upd_8b);
7972
7973 fw_maj = le16_to_cpu(resp->hwrm_fw_major);
7974 if (bp->hwrm_spec_code > 0x10803 && fw_maj) {
7975 fw_min = le16_to_cpu(resp->hwrm_fw_minor);
7976 fw_bld = le16_to_cpu(resp->hwrm_fw_build);
7977 fw_rsv = le16_to_cpu(resp->hwrm_fw_patch);
7978 len = FW_VER_STR_LEN;
7979 } else {
7980 fw_maj = resp->hwrm_fw_maj_8b;
7981 fw_min = resp->hwrm_fw_min_8b;
7982 fw_bld = resp->hwrm_fw_bld_8b;
7983 fw_rsv = resp->hwrm_fw_rsvd_8b;
7984 len = BC_HWRM_STR_LEN;
7985 }
7986 bp->fw_ver_code = BNXT_FW_VER_CODE(fw_maj, fw_min, fw_bld, fw_rsv);
7987 snprintf(bp->fw_ver_str, len, "%d.%d.%d.%d", fw_maj, fw_min, fw_bld,
7988 fw_rsv);
7989
7990 if (strlen(resp->active_pkg_name)) {
7991 int fw_ver_len = strlen(bp->fw_ver_str);
7992
7993 snprintf(bp->fw_ver_str + fw_ver_len,
7994 FW_VER_STR_LEN - fw_ver_len - 1, "/pkg %s",
7995 resp->active_pkg_name);
7996 bp->fw_cap |= BNXT_FW_CAP_PKG_VER;
7997 }
7998
7999 bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
8000 if (!bp->hwrm_cmd_timeout)
8001 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
8002
8003 if (resp->hwrm_intf_maj_8b >= 1) {
8004 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
8005 bp->hwrm_max_ext_req_len = le16_to_cpu(resp->max_ext_req_len);
8006 }
8007 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
8008 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
8009
8010 bp->chip_num = le16_to_cpu(resp->chip_num);
8011 bp->chip_rev = resp->chip_rev;
8012 if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev &&
8013 !resp->chip_metal)
8014 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0;
8015
8016 dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg);
8017 if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
8018 (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED))
8019 bp->fw_cap |= BNXT_FW_CAP_SHORT_CMD;
8020
8021 if (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED)
8022 bp->fw_cap |= BNXT_FW_CAP_KONG_MB_CHNL;
8023
8024 if (dev_caps_cfg &
8025 VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED)
8026 bp->fw_cap |= BNXT_FW_CAP_OVS_64BIT_HANDLE;
8027
8028 if (dev_caps_cfg &
8029 VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
8030 bp->fw_cap |= BNXT_FW_CAP_TRUSTED_VF;
8031
8032 if (dev_caps_cfg &
8033 VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED)
8034 bp->fw_cap |= BNXT_FW_CAP_CFA_ADV_FLOW;
8035
8036 hwrm_ver_get_exit:
8037 mutex_unlock(&bp->hwrm_cmd_lock);
8038 return rc;
8039 }
8040
8041 int bnxt_hwrm_fw_set_time(struct bnxt *bp)
8042 {
8043 struct hwrm_fw_set_time_input req = {0};
8044 struct tm tm;
8045 time64_t now = ktime_get_real_seconds();
8046
8047 if ((BNXT_VF(bp) && bp->hwrm_spec_code < 0x10901) ||
8048 bp->hwrm_spec_code < 0x10400)
8049 return -EOPNOTSUPP;
8050
8051 time64_to_tm(now, 0, &tm);
8052 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1);
8053 req.year = cpu_to_le16(1900 + tm.tm_year);
8054 req.month = 1 + tm.tm_mon;
8055 req.day = tm.tm_mday;
8056 req.hour = tm.tm_hour;
8057 req.minute = tm.tm_min;
8058 req.second = tm.tm_sec;
8059 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8060 }
8061
8062 static void bnxt_add_one_ctr(u64 hw, u64 *sw, u64 mask)
8063 {
8064 u64 sw_tmp;
8065
8066 hw &= mask;
8067 sw_tmp = (*sw & ~mask) | hw;
8068 if (hw < (*sw & mask))
8069 sw_tmp += mask + 1;
8070 WRITE_ONCE(*sw, sw_tmp);
8071 }
8072
8073 static void __bnxt_accumulate_stats(__le64 *hw_stats, u64 *sw_stats, u64 *masks,
8074 int count, bool ignore_zero)
8075 {
8076 int i;
8077
8078 for (i = 0; i < count; i++) {
8079 u64 hw = le64_to_cpu(READ_ONCE(hw_stats[i]));
8080
8081 if (ignore_zero && !hw)
8082 continue;
8083
8084 if (masks[i] == -1ULL)
8085 sw_stats[i] = hw;
8086 else
8087 bnxt_add_one_ctr(hw, &sw_stats[i], masks[i]);
8088 }
8089 }
8090
8091 static void bnxt_accumulate_stats(struct bnxt_stats_mem *stats)
8092 {
8093 if (!stats->hw_stats)
8094 return;
8095
8096 __bnxt_accumulate_stats(stats->hw_stats, stats->sw_stats,
8097 stats->hw_masks, stats->len / 8, false);
8098 }
8099
8100 static void bnxt_accumulate_all_stats(struct bnxt *bp)
8101 {
8102 struct bnxt_stats_mem *ring0_stats;
8103 bool ignore_zero = false;
8104 int i;
8105
8106 /* Chip bug. Counter intermittently becomes 0. */
8107 if (bp->flags & BNXT_FLAG_CHIP_P5)
8108 ignore_zero = true;
8109
8110 for (i = 0; i < bp->cp_nr_rings; i++) {
8111 struct bnxt_napi *bnapi = bp->bnapi[i];
8112 struct bnxt_cp_ring_info *cpr;
8113 struct bnxt_stats_mem *stats;
8114
8115 cpr = &bnapi->cp_ring;
8116 stats = &cpr->stats;
8117 if (!i)
8118 ring0_stats = stats;
8119 __bnxt_accumulate_stats(stats->hw_stats, stats->sw_stats,
8120 ring0_stats->hw_masks,
8121 ring0_stats->len / 8, ignore_zero);
8122 }
8123 if (bp->flags & BNXT_FLAG_PORT_STATS) {
8124 struct bnxt_stats_mem *stats = &bp->port_stats;
8125 __le64 *hw_stats = stats->hw_stats;
8126 u64 *sw_stats = stats->sw_stats;
8127 u64 *masks = stats->hw_masks;
8128 int cnt;
8129
8130 cnt = sizeof(struct rx_port_stats) / 8;
8131 __bnxt_accumulate_stats(hw_stats, sw_stats, masks, cnt, false);
8132
8133 hw_stats += BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
8134 sw_stats += BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
8135 masks += BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
8136 cnt = sizeof(struct tx_port_stats) / 8;
8137 __bnxt_accumulate_stats(hw_stats, sw_stats, masks, cnt, false);
8138 }
8139 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
8140 bnxt_accumulate_stats(&bp->rx_port_stats_ext);
8141 bnxt_accumulate_stats(&bp->tx_port_stats_ext);
8142 }
8143 }
8144
8145 static int bnxt_hwrm_port_qstats(struct bnxt *bp, u8 flags)
8146 {
8147 struct bnxt_pf_info *pf = &bp->pf;
8148 struct hwrm_port_qstats_input req = {0};
8149
8150 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
8151 return 0;
8152
8153 if (flags && !(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED))
8154 return -EOPNOTSUPP;
8155
8156 req.flags = flags;
8157 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
8158 req.port_id = cpu_to_le16(pf->port_id);
8159 req.tx_stat_host_addr = cpu_to_le64(bp->port_stats.hw_stats_map +
8160 BNXT_TX_PORT_STATS_BYTE_OFFSET);
8161 req.rx_stat_host_addr = cpu_to_le64(bp->port_stats.hw_stats_map);
8162 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8163 }
8164
8165 static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp, u8 flags)
8166 {
8167 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
8168 struct hwrm_queue_pri2cos_qcfg_input req2 = {0};
8169 struct hwrm_port_qstats_ext_input req = {0};
8170 struct bnxt_pf_info *pf = &bp->pf;
8171 u32 tx_stat_size;
8172 int rc;
8173
8174 if (!(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
8175 return 0;
8176
8177 if (flags && !(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED))
8178 return -EOPNOTSUPP;
8179
8180 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS_EXT, -1, -1);
8181 req.flags = flags;
8182 req.port_id = cpu_to_le16(pf->port_id);
8183 req.rx_stat_size = cpu_to_le16(sizeof(struct rx_port_stats_ext));
8184 req.rx_stat_host_addr = cpu_to_le64(bp->rx_port_stats_ext.hw_stats_map);
8185 tx_stat_size = bp->tx_port_stats_ext.hw_stats ?
8186 sizeof(struct tx_port_stats_ext) : 0;
8187 req.tx_stat_size = cpu_to_le16(tx_stat_size);
8188 req.tx_stat_host_addr = cpu_to_le64(bp->tx_port_stats_ext.hw_stats_map);
8189 mutex_lock(&bp->hwrm_cmd_lock);
8190 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8191 if (!rc) {
8192 bp->fw_rx_stats_ext_size = le16_to_cpu(resp->rx_stat_size) / 8;
8193 bp->fw_tx_stats_ext_size = tx_stat_size ?
8194 le16_to_cpu(resp->tx_stat_size) / 8 : 0;
8195 } else {
8196 bp->fw_rx_stats_ext_size = 0;
8197 bp->fw_tx_stats_ext_size = 0;
8198 }
8199 if (flags)
8200 goto qstats_done;
8201
8202 if (bp->fw_tx_stats_ext_size <=
8203 offsetof(struct tx_port_stats_ext, pfc_pri0_tx_duration_us) / 8) {
8204 mutex_unlock(&bp->hwrm_cmd_lock);
8205 bp->pri2cos_valid = 0;
8206 return rc;
8207 }
8208
8209 bnxt_hwrm_cmd_hdr_init(bp, &req2, HWRM_QUEUE_PRI2COS_QCFG, -1, -1);
8210 req2.flags = cpu_to_le32(QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN);
8211
8212 rc = _hwrm_send_message(bp, &req2, sizeof(req2), HWRM_CMD_TIMEOUT);
8213 if (!rc) {
8214 struct hwrm_queue_pri2cos_qcfg_output *resp2;
8215 u8 *pri2cos;
8216 int i, j;
8217
8218 resp2 = bp->hwrm_cmd_resp_addr;
8219 pri2cos = &resp2->pri0_cos_queue_id;
8220 for (i = 0; i < 8; i++) {
8221 u8 queue_id = pri2cos[i];
8222 u8 queue_idx;
8223
8224 /* Per port queue IDs start from 0, 10, 20, etc */
8225 queue_idx = queue_id % 10;
8226 if (queue_idx > BNXT_MAX_QUEUE) {
8227 bp->pri2cos_valid = false;
8228 goto qstats_done;
8229 }
8230 for (j = 0; j < bp->max_q; j++) {
8231 if (bp->q_ids[j] == queue_id)
8232 bp->pri2cos_idx[i] = queue_idx;
8233 }
8234 }
8235 bp->pri2cos_valid = 1;
8236 }
8237 qstats_done:
8238 mutex_unlock(&bp->hwrm_cmd_lock);
8239 return rc;
8240 }
8241
8242 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
8243 {
8244 if (bp->vxlan_fw_dst_port_id != INVALID_HW_RING_ID)
8245 bnxt_hwrm_tunnel_dst_port_free(
8246 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
8247 if (bp->nge_fw_dst_port_id != INVALID_HW_RING_ID)
8248 bnxt_hwrm_tunnel_dst_port_free(
8249 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
8250 }
8251
8252 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
8253 {
8254 int rc, i;
8255 u32 tpa_flags = 0;
8256
8257 if (set_tpa)
8258 tpa_flags = bp->flags & BNXT_FLAG_TPA;
8259 else if (BNXT_NO_FW_ACCESS(bp))
8260 return 0;
8261 for (i = 0; i < bp->nr_vnics; i++) {
8262 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
8263 if (rc) {
8264 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
8265 i, rc);
8266 return rc;
8267 }
8268 }
8269 return 0;
8270 }
8271
8272 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
8273 {
8274 int i;
8275
8276 for (i = 0; i < bp->nr_vnics; i++)
8277 bnxt_hwrm_vnic_set_rss(bp, i, false);
8278 }
8279
8280 static void bnxt_clear_vnic(struct bnxt *bp)
8281 {
8282 if (!bp->vnic_info)
8283 return;
8284
8285 bnxt_hwrm_clear_vnic_filter(bp);
8286 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) {
8287 /* clear all RSS setting before free vnic ctx */
8288 bnxt_hwrm_clear_vnic_rss(bp);
8289 bnxt_hwrm_vnic_ctx_free(bp);
8290 }
8291 /* before free the vnic, undo the vnic tpa settings */
8292 if (bp->flags & BNXT_FLAG_TPA)
8293 bnxt_set_tpa(bp, false);
8294 bnxt_hwrm_vnic_free(bp);
8295 if (bp->flags & BNXT_FLAG_CHIP_P5)
8296 bnxt_hwrm_vnic_ctx_free(bp);
8297 }
8298
8299 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
8300 bool irq_re_init)
8301 {
8302 bnxt_clear_vnic(bp);
8303 bnxt_hwrm_ring_free(bp, close_path);
8304 bnxt_hwrm_ring_grp_free(bp);
8305 if (irq_re_init) {
8306 bnxt_hwrm_stat_ctx_free(bp);
8307 bnxt_hwrm_free_tunnel_ports(bp);
8308 }
8309 }
8310
8311 static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode)
8312 {
8313 struct hwrm_func_cfg_input req = {0};
8314
8315 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
8316 req.fid = cpu_to_le16(0xffff);
8317 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE);
8318 if (br_mode == BRIDGE_MODE_VEB)
8319 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB;
8320 else if (br_mode == BRIDGE_MODE_VEPA)
8321 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA;
8322 else
8323 return -EINVAL;
8324 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8325 }
8326
8327 static int bnxt_hwrm_set_cache_line_size(struct bnxt *bp, int size)
8328 {
8329 struct hwrm_func_cfg_input req = {0};
8330
8331 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10803)
8332 return 0;
8333
8334 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
8335 req.fid = cpu_to_le16(0xffff);
8336 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE);
8337 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64;
8338 if (size == 128)
8339 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128;
8340
8341 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8342 }
8343
8344 static int __bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
8345 {
8346 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
8347 int rc;
8348
8349 if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG)
8350 goto skip_rss_ctx;
8351
8352 /* allocate context for vnic */
8353 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0);
8354 if (rc) {
8355 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
8356 vnic_id, rc);
8357 goto vnic_setup_err;
8358 }
8359 bp->rsscos_nr_ctxs++;
8360
8361 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
8362 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1);
8363 if (rc) {
8364 netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
8365 vnic_id, rc);
8366 goto vnic_setup_err;
8367 }
8368 bp->rsscos_nr_ctxs++;
8369 }
8370
8371 skip_rss_ctx:
8372 /* configure default vnic, ring grp */
8373 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
8374 if (rc) {
8375 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
8376 vnic_id, rc);
8377 goto vnic_setup_err;
8378 }
8379
8380 /* Enable RSS hashing on vnic */
8381 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
8382 if (rc) {
8383 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
8384 vnic_id, rc);
8385 goto vnic_setup_err;
8386 }
8387
8388 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
8389 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
8390 if (rc) {
8391 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
8392 vnic_id, rc);
8393 }
8394 }
8395
8396 vnic_setup_err:
8397 return rc;
8398 }
8399
8400 static int __bnxt_setup_vnic_p5(struct bnxt *bp, u16 vnic_id)
8401 {
8402 int rc, i, nr_ctxs;
8403
8404 nr_ctxs = bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings);
8405 for (i = 0; i < nr_ctxs; i++) {
8406 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, i);
8407 if (rc) {
8408 netdev_err(bp->dev, "hwrm vnic %d ctx %d alloc failure rc: %x\n",
8409 vnic_id, i, rc);
8410 break;
8411 }
8412 bp->rsscos_nr_ctxs++;
8413 }
8414 if (i < nr_ctxs)
8415 return -ENOMEM;
8416
8417 rc = bnxt_hwrm_vnic_set_rss_p5(bp, vnic_id, true);
8418 if (rc) {
8419 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %d\n",
8420 vnic_id, rc);
8421 return rc;
8422 }
8423 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
8424 if (rc) {
8425 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
8426 vnic_id, rc);
8427 return rc;
8428 }
8429 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
8430 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
8431 if (rc) {
8432 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
8433 vnic_id, rc);
8434 }
8435 }
8436 return rc;
8437 }
8438
8439 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
8440 {
8441 if (bp->flags & BNXT_FLAG_CHIP_P5)
8442 return __bnxt_setup_vnic_p5(bp, vnic_id);
8443 else
8444 return __bnxt_setup_vnic(bp, vnic_id);
8445 }
8446
8447 static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
8448 {
8449 #ifdef CONFIG_RFS_ACCEL
8450 int i, rc = 0;
8451
8452 if (bp->flags & BNXT_FLAG_CHIP_P5)
8453 return 0;
8454
8455 for (i = 0; i < bp->rx_nr_rings; i++) {
8456 struct bnxt_vnic_info *vnic;
8457 u16 vnic_id = i + 1;
8458 u16 ring_id = i;
8459
8460 if (vnic_id >= bp->nr_vnics)
8461 break;
8462
8463 vnic = &bp->vnic_info[vnic_id];
8464 vnic->flags |= BNXT_VNIC_RFS_FLAG;
8465 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
8466 vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG;
8467 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
8468 if (rc) {
8469 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
8470 vnic_id, rc);
8471 break;
8472 }
8473 rc = bnxt_setup_vnic(bp, vnic_id);
8474 if (rc)
8475 break;
8476 }
8477 return rc;
8478 #else
8479 return 0;
8480 #endif
8481 }
8482
8483 /* Allow PF, trusted VFs and VFs with default VLAN to be in promiscuous mode */
8484 static bool bnxt_promisc_ok(struct bnxt *bp)
8485 {
8486 #ifdef CONFIG_BNXT_SRIOV
8487 if (BNXT_VF(bp) && !bp->vf.vlan && !bnxt_is_trusted_vf(bp, &bp->vf))
8488 return false;
8489 #endif
8490 return true;
8491 }
8492
8493 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp)
8494 {
8495 unsigned int rc = 0;
8496
8497 rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1);
8498 if (rc) {
8499 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
8500 rc);
8501 return rc;
8502 }
8503
8504 rc = bnxt_hwrm_vnic_cfg(bp, 1);
8505 if (rc) {
8506 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
8507 rc);
8508 return rc;
8509 }
8510 return rc;
8511 }
8512
8513 static int bnxt_cfg_rx_mode(struct bnxt *);
8514 static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
8515
8516 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
8517 {
8518 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
8519 int rc = 0;
8520 unsigned int rx_nr_rings = bp->rx_nr_rings;
8521
8522 if (irq_re_init) {
8523 rc = bnxt_hwrm_stat_ctx_alloc(bp);
8524 if (rc) {
8525 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
8526 rc);
8527 goto err_out;
8528 }
8529 }
8530
8531 rc = bnxt_hwrm_ring_alloc(bp);
8532 if (rc) {
8533 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
8534 goto err_out;
8535 }
8536
8537 rc = bnxt_hwrm_ring_grp_alloc(bp);
8538 if (rc) {
8539 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
8540 goto err_out;
8541 }
8542
8543 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
8544 rx_nr_rings--;
8545
8546 /* default vnic 0 */
8547 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings);
8548 if (rc) {
8549 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
8550 goto err_out;
8551 }
8552
8553 rc = bnxt_setup_vnic(bp, 0);
8554 if (rc)
8555 goto err_out;
8556
8557 if (bp->flags & BNXT_FLAG_RFS) {
8558 rc = bnxt_alloc_rfs_vnics(bp);
8559 if (rc)
8560 goto err_out;
8561 }
8562
8563 if (bp->flags & BNXT_FLAG_TPA) {
8564 rc = bnxt_set_tpa(bp, true);
8565 if (rc)
8566 goto err_out;
8567 }
8568
8569 if (BNXT_VF(bp))
8570 bnxt_update_vf_mac(bp);
8571
8572 /* Filter for default vnic 0 */
8573 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
8574 if (rc) {
8575 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
8576 goto err_out;
8577 }
8578 vnic->uc_filter_count = 1;
8579
8580 vnic->rx_mask = 0;
8581 if (bp->dev->flags & IFF_BROADCAST)
8582 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
8583
8584 if (bp->dev->flags & IFF_PROMISC)
8585 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
8586
8587 if (bp->dev->flags & IFF_ALLMULTI) {
8588 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
8589 vnic->mc_list_count = 0;
8590 } else {
8591 u32 mask = 0;
8592
8593 bnxt_mc_list_updated(bp, &mask);
8594 vnic->rx_mask |= mask;
8595 }
8596
8597 rc = bnxt_cfg_rx_mode(bp);
8598 if (rc)
8599 goto err_out;
8600
8601 rc = bnxt_hwrm_set_coal(bp);
8602 if (rc)
8603 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
8604 rc);
8605
8606 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
8607 rc = bnxt_setup_nitroa0_vnic(bp);
8608 if (rc)
8609 netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n",
8610 rc);
8611 }
8612
8613 if (BNXT_VF(bp)) {
8614 bnxt_hwrm_func_qcfg(bp);
8615 netdev_update_features(bp->dev);
8616 }
8617
8618 return 0;
8619
8620 err_out:
8621 bnxt_hwrm_resource_free(bp, 0, true);
8622
8623 return rc;
8624 }
8625
8626 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
8627 {
8628 bnxt_hwrm_resource_free(bp, 1, irq_re_init);
8629 return 0;
8630 }
8631
8632 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
8633 {
8634 bnxt_init_cp_rings(bp);
8635 bnxt_init_rx_rings(bp);
8636 bnxt_init_tx_rings(bp);
8637 bnxt_init_ring_grps(bp, irq_re_init);
8638 bnxt_init_vnics(bp);
8639
8640 return bnxt_init_chip(bp, irq_re_init);
8641 }
8642
8643 static int bnxt_set_real_num_queues(struct bnxt *bp)
8644 {
8645 int rc;
8646 struct net_device *dev = bp->dev;
8647
8648 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings -
8649 bp->tx_nr_rings_xdp);
8650 if (rc)
8651 return rc;
8652
8653 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
8654 if (rc)
8655 return rc;
8656
8657 #ifdef CONFIG_RFS_ACCEL
8658 if (bp->flags & BNXT_FLAG_RFS)
8659 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
8660 #endif
8661
8662 return rc;
8663 }
8664
8665 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
8666 bool shared)
8667 {
8668 int _rx = *rx, _tx = *tx;
8669
8670 if (shared) {
8671 *rx = min_t(int, _rx, max);
8672 *tx = min_t(int, _tx, max);
8673 } else {
8674 if (max < 2)
8675 return -ENOMEM;
8676
8677 while (_rx + _tx > max) {
8678 if (_rx > _tx && _rx > 1)
8679 _rx--;
8680 else if (_tx > 1)
8681 _tx--;
8682 }
8683 *rx = _rx;
8684 *tx = _tx;
8685 }
8686 return 0;
8687 }
8688
8689 static void bnxt_setup_msix(struct bnxt *bp)
8690 {
8691 const int len = sizeof(bp->irq_tbl[0].name);
8692 struct net_device *dev = bp->dev;
8693 int tcs, i;
8694
8695 tcs = netdev_get_num_tc(dev);
8696 if (tcs) {
8697 int i, off, count;
8698
8699 for (i = 0; i < tcs; i++) {
8700 count = bp->tx_nr_rings_per_tc;
8701 off = i * count;
8702 netdev_set_tc_queue(dev, i, count, off);
8703 }
8704 }
8705
8706 for (i = 0; i < bp->cp_nr_rings; i++) {
8707 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
8708 char *attr;
8709
8710 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
8711 attr = "TxRx";
8712 else if (i < bp->rx_nr_rings)
8713 attr = "rx";
8714 else
8715 attr = "tx";
8716
8717 snprintf(bp->irq_tbl[map_idx].name, len, "%s-%s-%d", dev->name,
8718 attr, i);
8719 bp->irq_tbl[map_idx].handler = bnxt_msix;
8720 }
8721 }
8722
8723 static void bnxt_setup_inta(struct bnxt *bp)
8724 {
8725 const int len = sizeof(bp->irq_tbl[0].name);
8726
8727 if (netdev_get_num_tc(bp->dev))
8728 netdev_reset_tc(bp->dev);
8729
8730 snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx",
8731 0);
8732 bp->irq_tbl[0].handler = bnxt_inta;
8733 }
8734
8735 static int bnxt_init_int_mode(struct bnxt *bp);
8736
8737 static int bnxt_setup_int_mode(struct bnxt *bp)
8738 {
8739 int rc;
8740
8741 if (!bp->irq_tbl) {
8742 rc = bnxt_init_int_mode(bp);
8743 if (rc || !bp->irq_tbl)
8744 return rc ?: -ENODEV;
8745 }
8746
8747 if (bp->flags & BNXT_FLAG_USING_MSIX)
8748 bnxt_setup_msix(bp);
8749 else
8750 bnxt_setup_inta(bp);
8751
8752 rc = bnxt_set_real_num_queues(bp);
8753 return rc;
8754 }
8755
8756 #ifdef CONFIG_RFS_ACCEL
8757 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp)
8758 {
8759 return bp->hw_resc.max_rsscos_ctxs;
8760 }
8761
8762 static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp)
8763 {
8764 return bp->hw_resc.max_vnics;
8765 }
8766 #endif
8767
8768 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp)
8769 {
8770 return bp->hw_resc.max_stat_ctxs;
8771 }
8772
8773 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp)
8774 {
8775 return bp->hw_resc.max_cp_rings;
8776 }
8777
8778 static unsigned int bnxt_get_max_func_cp_rings_for_en(struct bnxt *bp)
8779 {
8780 unsigned int cp = bp->hw_resc.max_cp_rings;
8781
8782 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
8783 cp -= bnxt_get_ulp_msix_num(bp);
8784
8785 return cp;
8786 }
8787
8788 static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp)
8789 {
8790 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
8791
8792 if (bp->flags & BNXT_FLAG_CHIP_P5)
8793 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_nqs);
8794
8795 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_cp_rings);
8796 }
8797
8798 static void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs)
8799 {
8800 bp->hw_resc.max_irqs = max_irqs;
8801 }
8802
8803 unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp)
8804 {
8805 unsigned int cp;
8806
8807 cp = bnxt_get_max_func_cp_rings_for_en(bp);
8808 if (bp->flags & BNXT_FLAG_CHIP_P5)
8809 return cp - bp->rx_nr_rings - bp->tx_nr_rings;
8810 else
8811 return cp - bp->cp_nr_rings;
8812 }
8813
8814 unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp)
8815 {
8816 return bnxt_get_max_func_stat_ctxs(bp) - bnxt_get_func_stat_ctxs(bp);
8817 }
8818
8819 int bnxt_get_avail_msix(struct bnxt *bp, int num)
8820 {
8821 int max_cp = bnxt_get_max_func_cp_rings(bp);
8822 int max_irq = bnxt_get_max_func_irqs(bp);
8823 int total_req = bp->cp_nr_rings + num;
8824 int max_idx, avail_msix;
8825
8826 max_idx = bp->total_irqs;
8827 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
8828 max_idx = min_t(int, bp->total_irqs, max_cp);
8829 avail_msix = max_idx - bp->cp_nr_rings;
8830 if (!BNXT_NEW_RM(bp) || avail_msix >= num)
8831 return avail_msix;
8832
8833 if (max_irq < total_req) {
8834 num = max_irq - bp->cp_nr_rings;
8835 if (num <= 0)
8836 return 0;
8837 }
8838 return num;
8839 }
8840
8841 static int bnxt_get_num_msix(struct bnxt *bp)
8842 {
8843 if (!BNXT_NEW_RM(bp))
8844 return bnxt_get_max_func_irqs(bp);
8845
8846 return bnxt_nq_rings_in_use(bp);
8847 }
8848
8849 static int bnxt_init_msix(struct bnxt *bp)
8850 {
8851 int i, total_vecs, max, rc = 0, min = 1, ulp_msix;
8852 struct msix_entry *msix_ent;
8853
8854 total_vecs = bnxt_get_num_msix(bp);
8855 max = bnxt_get_max_func_irqs(bp);
8856 if (total_vecs > max)
8857 total_vecs = max;
8858
8859 if (!total_vecs)
8860 return 0;
8861
8862 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
8863 if (!msix_ent)
8864 return -ENOMEM;
8865
8866 for (i = 0; i < total_vecs; i++) {
8867 msix_ent[i].entry = i;
8868 msix_ent[i].vector = 0;
8869 }
8870
8871 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
8872 min = 2;
8873
8874 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
8875 ulp_msix = bnxt_get_ulp_msix_num(bp);
8876 if (total_vecs < 0 || total_vecs < ulp_msix) {
8877 rc = -ENODEV;
8878 goto msix_setup_exit;
8879 }
8880
8881 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
8882 if (bp->irq_tbl) {
8883 for (i = 0; i < total_vecs; i++)
8884 bp->irq_tbl[i].vector = msix_ent[i].vector;
8885
8886 bp->total_irqs = total_vecs;
8887 /* Trim rings based upon num of vectors allocated */
8888 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
8889 total_vecs - ulp_msix, min == 1);
8890 if (rc)
8891 goto msix_setup_exit;
8892
8893 bp->cp_nr_rings = (min == 1) ?
8894 max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
8895 bp->tx_nr_rings + bp->rx_nr_rings;
8896
8897 } else {
8898 rc = -ENOMEM;
8899 goto msix_setup_exit;
8900 }
8901 bp->flags |= BNXT_FLAG_USING_MSIX;
8902 kfree(msix_ent);
8903 return 0;
8904
8905 msix_setup_exit:
8906 netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc);
8907 kfree(bp->irq_tbl);
8908 bp->irq_tbl = NULL;
8909 pci_disable_msix(bp->pdev);
8910 kfree(msix_ent);
8911 return rc;
8912 }
8913
8914 static int bnxt_init_inta(struct bnxt *bp)
8915 {
8916 bp->irq_tbl = kzalloc(sizeof(struct bnxt_irq), GFP_KERNEL);
8917 if (!bp->irq_tbl)
8918 return -ENOMEM;
8919
8920 bp->total_irqs = 1;
8921 bp->rx_nr_rings = 1;
8922 bp->tx_nr_rings = 1;
8923 bp->cp_nr_rings = 1;
8924 bp->flags |= BNXT_FLAG_SHARED_RINGS;
8925 bp->irq_tbl[0].vector = bp->pdev->irq;
8926 return 0;
8927 }
8928
8929 static int bnxt_init_int_mode(struct bnxt *bp)
8930 {
8931 int rc = -ENODEV;
8932
8933 if (bp->flags & BNXT_FLAG_MSIX_CAP)
8934 rc = bnxt_init_msix(bp);
8935
8936 if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
8937 /* fallback to INTA */
8938 rc = bnxt_init_inta(bp);
8939 }
8940 return rc;
8941 }
8942
8943 static void bnxt_clear_int_mode(struct bnxt *bp)
8944 {
8945 if (bp->flags & BNXT_FLAG_USING_MSIX)
8946 pci_disable_msix(bp->pdev);
8947
8948 kfree(bp->irq_tbl);
8949 bp->irq_tbl = NULL;
8950 bp->flags &= ~BNXT_FLAG_USING_MSIX;
8951 }
8952
8953 int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init)
8954 {
8955 int tcs = netdev_get_num_tc(bp->dev);
8956 bool irq_cleared = false;
8957 int rc;
8958
8959 if (!bnxt_need_reserve_rings(bp))
8960 return 0;
8961
8962 if (irq_re_init && BNXT_NEW_RM(bp) &&
8963 bnxt_get_num_msix(bp) != bp->total_irqs) {
8964 bnxt_ulp_irq_stop(bp);
8965 bnxt_clear_int_mode(bp);
8966 irq_cleared = true;
8967 }
8968 rc = __bnxt_reserve_rings(bp);
8969 if (irq_cleared) {
8970 if (!rc)
8971 rc = bnxt_init_int_mode(bp);
8972 bnxt_ulp_irq_restart(bp, rc);
8973 }
8974 if (rc) {
8975 netdev_err(bp->dev, "ring reservation/IRQ init failure rc: %d\n", rc);
8976 return rc;
8977 }
8978 if (tcs && (bp->tx_nr_rings_per_tc * tcs != bp->tx_nr_rings)) {
8979 netdev_err(bp->dev, "tx ring reservation failure\n");
8980 netdev_reset_tc(bp->dev);
8981 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
8982 return -ENOMEM;
8983 }
8984 return 0;
8985 }
8986
8987 static void bnxt_free_irq(struct bnxt *bp)
8988 {
8989 struct bnxt_irq *irq;
8990 int i;
8991
8992 #ifdef CONFIG_RFS_ACCEL
8993 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
8994 bp->dev->rx_cpu_rmap = NULL;
8995 #endif
8996 if (!bp->irq_tbl || !bp->bnapi)
8997 return;
8998
8999 for (i = 0; i < bp->cp_nr_rings; i++) {
9000 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
9001
9002 irq = &bp->irq_tbl[map_idx];
9003 if (irq->requested) {
9004 if (irq->have_cpumask) {
9005 irq_set_affinity_hint(irq->vector, NULL);
9006 free_cpumask_var(irq->cpu_mask);
9007 irq->have_cpumask = 0;
9008 }
9009 free_irq(irq->vector, bp->bnapi[i]);
9010 }
9011
9012 irq->requested = 0;
9013 }
9014 }
9015
9016 static int bnxt_request_irq(struct bnxt *bp)
9017 {
9018 int i, j, rc = 0;
9019 unsigned long flags = 0;
9020 #ifdef CONFIG_RFS_ACCEL
9021 struct cpu_rmap *rmap;
9022 #endif
9023
9024 rc = bnxt_setup_int_mode(bp);
9025 if (rc) {
9026 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
9027 rc);
9028 return rc;
9029 }
9030 #ifdef CONFIG_RFS_ACCEL
9031 rmap = bp->dev->rx_cpu_rmap;
9032 #endif
9033 if (!(bp->flags & BNXT_FLAG_USING_MSIX))
9034 flags = IRQF_SHARED;
9035
9036 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
9037 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
9038 struct bnxt_irq *irq = &bp->irq_tbl[map_idx];
9039
9040 #ifdef CONFIG_RFS_ACCEL
9041 if (rmap && bp->bnapi[i]->rx_ring) {
9042 rc = irq_cpu_rmap_add(rmap, irq->vector);
9043 if (rc)
9044 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
9045 j);
9046 j++;
9047 }
9048 #endif
9049 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
9050 bp->bnapi[i]);
9051 if (rc)
9052 break;
9053
9054 irq->requested = 1;
9055
9056 if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) {
9057 int numa_node = dev_to_node(&bp->pdev->dev);
9058
9059 irq->have_cpumask = 1;
9060 cpumask_set_cpu(cpumask_local_spread(i, numa_node),
9061 irq->cpu_mask);
9062 rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask);
9063 if (rc) {
9064 netdev_warn(bp->dev,
9065 "Set affinity failed, IRQ = %d\n",
9066 irq->vector);
9067 break;
9068 }
9069 }
9070 }
9071 return rc;
9072 }
9073
9074 static void bnxt_del_napi(struct bnxt *bp)
9075 {
9076 int i;
9077
9078 if (!bp->bnapi)
9079 return;
9080
9081 for (i = 0; i < bp->cp_nr_rings; i++) {
9082 struct bnxt_napi *bnapi = bp->bnapi[i];
9083
9084 __netif_napi_del(&bnapi->napi);
9085 }
9086 /* We called __netif_napi_del(), we need
9087 * to respect an RCU grace period before freeing napi structures.
9088 */
9089 synchronize_net();
9090 }
9091
9092 static void bnxt_init_napi(struct bnxt *bp)
9093 {
9094 int i;
9095 unsigned int cp_nr_rings = bp->cp_nr_rings;
9096 struct bnxt_napi *bnapi;
9097
9098 if (bp->flags & BNXT_FLAG_USING_MSIX) {
9099 int (*poll_fn)(struct napi_struct *, int) = bnxt_poll;
9100
9101 if (bp->flags & BNXT_FLAG_CHIP_P5)
9102 poll_fn = bnxt_poll_p5;
9103 else if (BNXT_CHIP_TYPE_NITRO_A0(bp))
9104 cp_nr_rings--;
9105 for (i = 0; i < cp_nr_rings; i++) {
9106 bnapi = bp->bnapi[i];
9107 netif_napi_add(bp->dev, &bnapi->napi, poll_fn, 64);
9108 }
9109 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
9110 bnapi = bp->bnapi[cp_nr_rings];
9111 netif_napi_add(bp->dev, &bnapi->napi,
9112 bnxt_poll_nitroa0, 64);
9113 }
9114 } else {
9115 bnapi = bp->bnapi[0];
9116 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
9117 }
9118 }
9119
9120 static void bnxt_disable_napi(struct bnxt *bp)
9121 {
9122 int i;
9123
9124 if (!bp->bnapi ||
9125 test_and_set_bit(BNXT_STATE_NAPI_DISABLED, &bp->state))
9126 return;
9127
9128 for (i = 0; i < bp->cp_nr_rings; i++) {
9129 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
9130
9131 if (bp->bnapi[i]->rx_ring)
9132 cancel_work_sync(&cpr->dim.work);
9133
9134 napi_disable(&bp->bnapi[i]->napi);
9135 }
9136 }
9137
9138 static void bnxt_enable_napi(struct bnxt *bp)
9139 {
9140 int i;
9141
9142 clear_bit(BNXT_STATE_NAPI_DISABLED, &bp->state);
9143 for (i = 0; i < bp->cp_nr_rings; i++) {
9144 struct bnxt_napi *bnapi = bp->bnapi[i];
9145 struct bnxt_cp_ring_info *cpr;
9146
9147 cpr = &bnapi->cp_ring;
9148 if (bnapi->in_reset)
9149 cpr->sw_stats.rx.rx_resets++;
9150 bnapi->in_reset = false;
9151
9152 if (bnapi->rx_ring) {
9153 INIT_WORK(&cpr->dim.work, bnxt_dim_work);
9154 cpr->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
9155 }
9156 napi_enable(&bnapi->napi);
9157 }
9158 }
9159
9160 void bnxt_tx_disable(struct bnxt *bp)
9161 {
9162 int i;
9163 struct bnxt_tx_ring_info *txr;
9164
9165 if (bp->tx_ring) {
9166 for (i = 0; i < bp->tx_nr_rings; i++) {
9167 txr = &bp->tx_ring[i];
9168 txr->dev_state = BNXT_DEV_STATE_CLOSING;
9169 }
9170 }
9171 /* Drop carrier first to prevent TX timeout */
9172 netif_carrier_off(bp->dev);
9173 /* Stop all TX queues */
9174 netif_tx_disable(bp->dev);
9175 }
9176
9177 void bnxt_tx_enable(struct bnxt *bp)
9178 {
9179 int i;
9180 struct bnxt_tx_ring_info *txr;
9181
9182 for (i = 0; i < bp->tx_nr_rings; i++) {
9183 txr = &bp->tx_ring[i];
9184 txr->dev_state = 0;
9185 }
9186 netif_tx_wake_all_queues(bp->dev);
9187 if (bp->link_info.link_up)
9188 netif_carrier_on(bp->dev);
9189 }
9190
9191 static char *bnxt_report_fec(struct bnxt_link_info *link_info)
9192 {
9193 u8 active_fec = link_info->active_fec_sig_mode &
9194 PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK;
9195
9196 switch (active_fec) {
9197 default:
9198 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE:
9199 return "None";
9200 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE:
9201 return "Clause 74 BaseR";
9202 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE:
9203 return "Clause 91 RS(528,514)";
9204 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE:
9205 return "Clause 91 RS544_1XN";
9206 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE:
9207 return "Clause 91 RS(544,514)";
9208 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE:
9209 return "Clause 91 RS272_1XN";
9210 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE:
9211 return "Clause 91 RS(272,257)";
9212 }
9213 }
9214
9215 static void bnxt_report_link(struct bnxt *bp)
9216 {
9217 if (bp->link_info.link_up) {
9218 const char *signal = "";
9219 const char *flow_ctrl;
9220 const char *duplex;
9221 u32 speed;
9222 u16 fec;
9223
9224 netif_carrier_on(bp->dev);
9225 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
9226 if (speed == SPEED_UNKNOWN) {
9227 netdev_info(bp->dev, "NIC Link is Up, speed unknown\n");
9228 return;
9229 }
9230 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
9231 duplex = "full";
9232 else
9233 duplex = "half";
9234 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
9235 flow_ctrl = "ON - receive & transmit";
9236 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
9237 flow_ctrl = "ON - transmit";
9238 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
9239 flow_ctrl = "ON - receive";
9240 else
9241 flow_ctrl = "none";
9242 if (bp->link_info.phy_qcfg_resp.option_flags &
9243 PORT_PHY_QCFG_RESP_OPTION_FLAGS_SIGNAL_MODE_KNOWN) {
9244 u8 sig_mode = bp->link_info.active_fec_sig_mode &
9245 PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK;
9246 switch (sig_mode) {
9247 case PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ:
9248 signal = "(NRZ) ";
9249 break;
9250 case PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4:
9251 signal = "(PAM4) ";
9252 break;
9253 default:
9254 break;
9255 }
9256 }
9257 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s%s duplex, Flow control: %s\n",
9258 speed, signal, duplex, flow_ctrl);
9259 if (bp->phy_flags & BNXT_PHY_FL_EEE_CAP)
9260 netdev_info(bp->dev, "EEE is %s\n",
9261 bp->eee.eee_active ? "active" :
9262 "not active");
9263 fec = bp->link_info.fec_cfg;
9264 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED))
9265 netdev_info(bp->dev, "FEC autoneg %s encoding: %s\n",
9266 (fec & BNXT_FEC_AUTONEG) ? "on" : "off",
9267 bnxt_report_fec(&bp->link_info));
9268 } else {
9269 netif_carrier_off(bp->dev);
9270 netdev_err(bp->dev, "NIC Link is Down\n");
9271 }
9272 }
9273
9274 static bool bnxt_phy_qcaps_no_speed(struct hwrm_port_phy_qcaps_output *resp)
9275 {
9276 if (!resp->supported_speeds_auto_mode &&
9277 !resp->supported_speeds_force_mode &&
9278 !resp->supported_pam4_speeds_auto_mode &&
9279 !resp->supported_pam4_speeds_force_mode)
9280 return true;
9281 return false;
9282 }
9283
9284 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
9285 {
9286 int rc = 0;
9287 struct hwrm_port_phy_qcaps_input req = {0};
9288 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
9289 struct bnxt_link_info *link_info = &bp->link_info;
9290
9291 if (bp->hwrm_spec_code < 0x10201)
9292 return 0;
9293
9294 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
9295
9296 mutex_lock(&bp->hwrm_cmd_lock);
9297 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9298 if (rc)
9299 goto hwrm_phy_qcaps_exit;
9300
9301 bp->phy_flags = resp->flags;
9302 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) {
9303 struct ethtool_eee *eee = &bp->eee;
9304 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
9305
9306 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
9307 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
9308 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
9309 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
9310 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
9311 }
9312
9313 if (bp->hwrm_spec_code >= 0x10a01) {
9314 if (bnxt_phy_qcaps_no_speed(resp)) {
9315 link_info->phy_state = BNXT_PHY_STATE_DISABLED;
9316 netdev_warn(bp->dev, "Ethernet link disabled\n");
9317 } else if (link_info->phy_state == BNXT_PHY_STATE_DISABLED) {
9318 link_info->phy_state = BNXT_PHY_STATE_ENABLED;
9319 netdev_info(bp->dev, "Ethernet link enabled\n");
9320 /* Phy re-enabled, reprobe the speeds */
9321 link_info->support_auto_speeds = 0;
9322 link_info->support_pam4_auto_speeds = 0;
9323 }
9324 }
9325 if (resp->supported_speeds_auto_mode)
9326 link_info->support_auto_speeds =
9327 le16_to_cpu(resp->supported_speeds_auto_mode);
9328 if (resp->supported_pam4_speeds_auto_mode)
9329 link_info->support_pam4_auto_speeds =
9330 le16_to_cpu(resp->supported_pam4_speeds_auto_mode);
9331
9332 bp->port_count = resp->port_cnt;
9333
9334 hwrm_phy_qcaps_exit:
9335 mutex_unlock(&bp->hwrm_cmd_lock);
9336 return rc;
9337 }
9338
9339 static bool bnxt_support_dropped(u16 advertising, u16 supported)
9340 {
9341 u16 diff = advertising ^ supported;
9342
9343 return ((supported | diff) != supported);
9344 }
9345
9346 int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
9347 {
9348 int rc = 0;
9349 struct bnxt_link_info *link_info = &bp->link_info;
9350 struct hwrm_port_phy_qcfg_input req = {0};
9351 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
9352 u8 link_up = link_info->link_up;
9353 bool support_changed = false;
9354
9355 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
9356
9357 mutex_lock(&bp->hwrm_cmd_lock);
9358 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9359 if (rc) {
9360 mutex_unlock(&bp->hwrm_cmd_lock);
9361 return rc;
9362 }
9363
9364 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
9365 link_info->phy_link_status = resp->link;
9366 link_info->duplex = resp->duplex_cfg;
9367 if (bp->hwrm_spec_code >= 0x10800)
9368 link_info->duplex = resp->duplex_state;
9369 link_info->pause = resp->pause;
9370 link_info->auto_mode = resp->auto_mode;
9371 link_info->auto_pause_setting = resp->auto_pause;
9372 link_info->lp_pause = resp->link_partner_adv_pause;
9373 link_info->force_pause_setting = resp->force_pause;
9374 link_info->duplex_setting = resp->duplex_cfg;
9375 if (link_info->phy_link_status == BNXT_LINK_LINK)
9376 link_info->link_speed = le16_to_cpu(resp->link_speed);
9377 else
9378 link_info->link_speed = 0;
9379 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
9380 link_info->force_pam4_link_speed =
9381 le16_to_cpu(resp->force_pam4_link_speed);
9382 link_info->support_speeds = le16_to_cpu(resp->support_speeds);
9383 link_info->support_pam4_speeds = le16_to_cpu(resp->support_pam4_speeds);
9384 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
9385 link_info->auto_pam4_link_speeds =
9386 le16_to_cpu(resp->auto_pam4_link_speed_mask);
9387 link_info->lp_auto_link_speeds =
9388 le16_to_cpu(resp->link_partner_adv_speeds);
9389 link_info->lp_auto_pam4_link_speeds =
9390 resp->link_partner_pam4_adv_speeds;
9391 link_info->preemphasis = le32_to_cpu(resp->preemphasis);
9392 link_info->phy_ver[0] = resp->phy_maj;
9393 link_info->phy_ver[1] = resp->phy_min;
9394 link_info->phy_ver[2] = resp->phy_bld;
9395 link_info->media_type = resp->media_type;
9396 link_info->phy_type = resp->phy_type;
9397 link_info->transceiver = resp->xcvr_pkg_type;
9398 link_info->phy_addr = resp->eee_config_phy_addr &
9399 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
9400 link_info->module_status = resp->module_status;
9401
9402 if (bp->phy_flags & BNXT_PHY_FL_EEE_CAP) {
9403 struct ethtool_eee *eee = &bp->eee;
9404 u16 fw_speeds;
9405
9406 eee->eee_active = 0;
9407 if (resp->eee_config_phy_addr &
9408 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
9409 eee->eee_active = 1;
9410 fw_speeds = le16_to_cpu(
9411 resp->link_partner_adv_eee_link_speed_mask);
9412 eee->lp_advertised =
9413 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
9414 }
9415
9416 /* Pull initial EEE config */
9417 if (!chng_link_state) {
9418 if (resp->eee_config_phy_addr &
9419 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
9420 eee->eee_enabled = 1;
9421
9422 fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
9423 eee->advertised =
9424 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
9425
9426 if (resp->eee_config_phy_addr &
9427 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
9428 __le32 tmr;
9429
9430 eee->tx_lpi_enabled = 1;
9431 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
9432 eee->tx_lpi_timer = le32_to_cpu(tmr) &
9433 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
9434 }
9435 }
9436 }
9437
9438 link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED;
9439 if (bp->hwrm_spec_code >= 0x10504) {
9440 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg);
9441 link_info->active_fec_sig_mode = resp->active_fec_signal_mode;
9442 }
9443 /* TODO: need to add more logic to report VF link */
9444 if (chng_link_state) {
9445 if (link_info->phy_link_status == BNXT_LINK_LINK)
9446 link_info->link_up = 1;
9447 else
9448 link_info->link_up = 0;
9449 if (link_up != link_info->link_up)
9450 bnxt_report_link(bp);
9451 } else {
9452 /* alwasy link down if not require to update link state */
9453 link_info->link_up = 0;
9454 }
9455 mutex_unlock(&bp->hwrm_cmd_lock);
9456
9457 if (!BNXT_PHY_CFG_ABLE(bp))
9458 return 0;
9459
9460 /* Check if any advertised speeds are no longer supported. The caller
9461 * holds the link_lock mutex, so we can modify link_info settings.
9462 */
9463 if (bnxt_support_dropped(link_info->advertising,
9464 link_info->support_auto_speeds)) {
9465 link_info->advertising = link_info->support_auto_speeds;
9466 support_changed = true;
9467 }
9468 if (bnxt_support_dropped(link_info->advertising_pam4,
9469 link_info->support_pam4_auto_speeds)) {
9470 link_info->advertising_pam4 = link_info->support_pam4_auto_speeds;
9471 support_changed = true;
9472 }
9473 if (support_changed && (link_info->autoneg & BNXT_AUTONEG_SPEED))
9474 bnxt_hwrm_set_link_setting(bp, true, false);
9475 return 0;
9476 }
9477
9478 static void bnxt_get_port_module_status(struct bnxt *bp)
9479 {
9480 struct bnxt_link_info *link_info = &bp->link_info;
9481 struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
9482 u8 module_status;
9483
9484 if (bnxt_update_link(bp, true))
9485 return;
9486
9487 module_status = link_info->module_status;
9488 switch (module_status) {
9489 case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX:
9490 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
9491 case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG:
9492 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
9493 bp->pf.port_id);
9494 if (bp->hwrm_spec_code >= 0x10201) {
9495 netdev_warn(bp->dev, "Module part number %s\n",
9496 resp->phy_vendor_partnumber);
9497 }
9498 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX)
9499 netdev_warn(bp->dev, "TX is disabled\n");
9500 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN)
9501 netdev_warn(bp->dev, "SFP+ module is shutdown\n");
9502 }
9503 }
9504
9505 static void
9506 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
9507 {
9508 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
9509 if (bp->hwrm_spec_code >= 0x10201)
9510 req->auto_pause =
9511 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
9512 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
9513 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
9514 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
9515 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
9516 req->enables |=
9517 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
9518 } else {
9519 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
9520 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
9521 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
9522 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
9523 req->enables |=
9524 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
9525 if (bp->hwrm_spec_code >= 0x10201) {
9526 req->auto_pause = req->force_pause;
9527 req->enables |= cpu_to_le32(
9528 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
9529 }
9530 }
9531 }
9532
9533 static void bnxt_hwrm_set_link_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
9534 {
9535 if (bp->link_info.autoneg & BNXT_AUTONEG_SPEED) {
9536 req->auto_mode |= PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
9537 if (bp->link_info.advertising) {
9538 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
9539 req->auto_link_speed_mask = cpu_to_le16(bp->link_info.advertising);
9540 }
9541 if (bp->link_info.advertising_pam4) {
9542 req->enables |=
9543 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAM4_LINK_SPEED_MASK);
9544 req->auto_link_pam4_speed_mask =
9545 cpu_to_le16(bp->link_info.advertising_pam4);
9546 }
9547 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
9548 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
9549 } else {
9550 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
9551 if (bp->link_info.req_signal_mode == BNXT_SIG_MODE_PAM4) {
9552 req->force_pam4_link_speed = cpu_to_le16(bp->link_info.req_link_speed);
9553 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED);
9554 } else {
9555 req->force_link_speed = cpu_to_le16(bp->link_info.req_link_speed);
9556 }
9557 }
9558
9559 /* tell chimp that the setting takes effect immediately */
9560 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
9561 }
9562
9563 int bnxt_hwrm_set_pause(struct bnxt *bp)
9564 {
9565 struct hwrm_port_phy_cfg_input req = {0};
9566 int rc;
9567
9568 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
9569 bnxt_hwrm_set_pause_common(bp, &req);
9570
9571 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
9572 bp->link_info.force_link_chng)
9573 bnxt_hwrm_set_link_common(bp, &req);
9574
9575 mutex_lock(&bp->hwrm_cmd_lock);
9576 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9577 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
9578 /* since changing of pause setting doesn't trigger any link
9579 * change event, the driver needs to update the current pause
9580 * result upon successfully return of the phy_cfg command
9581 */
9582 bp->link_info.pause =
9583 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
9584 bp->link_info.auto_pause_setting = 0;
9585 if (!bp->link_info.force_link_chng)
9586 bnxt_report_link(bp);
9587 }
9588 bp->link_info.force_link_chng = false;
9589 mutex_unlock(&bp->hwrm_cmd_lock);
9590 return rc;
9591 }
9592
9593 static void bnxt_hwrm_set_eee(struct bnxt *bp,
9594 struct hwrm_port_phy_cfg_input *req)
9595 {
9596 struct ethtool_eee *eee = &bp->eee;
9597
9598 if (eee->eee_enabled) {
9599 u16 eee_speeds;
9600 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
9601
9602 if (eee->tx_lpi_enabled)
9603 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
9604 else
9605 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
9606
9607 req->flags |= cpu_to_le32(flags);
9608 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
9609 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
9610 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
9611 } else {
9612 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
9613 }
9614 }
9615
9616 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
9617 {
9618 struct hwrm_port_phy_cfg_input req = {0};
9619
9620 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
9621 if (set_pause)
9622 bnxt_hwrm_set_pause_common(bp, &req);
9623
9624 bnxt_hwrm_set_link_common(bp, &req);
9625
9626 if (set_eee)
9627 bnxt_hwrm_set_eee(bp, &req);
9628 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9629 }
9630
9631 static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
9632 {
9633 struct hwrm_port_phy_cfg_input req = {0};
9634
9635 if (!BNXT_SINGLE_PF(bp))
9636 return 0;
9637
9638 if (pci_num_vf(bp->pdev) &&
9639 !(bp->phy_flags & BNXT_PHY_FL_FW_MANAGED_LKDN))
9640 return 0;
9641
9642 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
9643 req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN);
9644 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9645 }
9646
9647 static int bnxt_fw_init_one(struct bnxt *bp);
9648
9649 static int bnxt_fw_reset_via_optee(struct bnxt *bp)
9650 {
9651 #ifdef CONFIG_TEE_BNXT_FW
9652 int rc = tee_bnxt_fw_load();
9653
9654 if (rc)
9655 netdev_err(bp->dev, "Failed FW reset via OP-TEE, rc=%d\n", rc);
9656
9657 return rc;
9658 #else
9659 netdev_err(bp->dev, "OP-TEE not supported\n");
9660 return -ENODEV;
9661 #endif
9662 }
9663
9664 static int bnxt_try_recover_fw(struct bnxt *bp)
9665 {
9666 if (bp->fw_health && bp->fw_health->status_reliable) {
9667 int retry = 0, rc;
9668 u32 sts;
9669
9670 mutex_lock(&bp->hwrm_cmd_lock);
9671 do {
9672 sts = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG);
9673 rc = __bnxt_hwrm_ver_get(bp, true);
9674 if (!BNXT_FW_IS_BOOTING(sts) &&
9675 !BNXT_FW_IS_RECOVERING(sts))
9676 break;
9677 retry++;
9678 } while (rc == -EBUSY && retry < BNXT_FW_RETRY);
9679 mutex_unlock(&bp->hwrm_cmd_lock);
9680
9681 if (!BNXT_FW_IS_HEALTHY(sts)) {
9682 netdev_err(bp->dev,
9683 "Firmware not responding, status: 0x%x\n",
9684 sts);
9685 rc = -ENODEV;
9686 }
9687 if (sts & FW_STATUS_REG_CRASHED_NO_MASTER) {
9688 netdev_warn(bp->dev, "Firmware recover via OP-TEE requested\n");
9689 return bnxt_fw_reset_via_optee(bp);
9690 }
9691 return rc;
9692 }
9693
9694 return -ENODEV;
9695 }
9696
9697 static int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
9698 {
9699 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
9700 struct hwrm_func_drv_if_change_input req = {0};
9701 bool fw_reset = !bp->irq_tbl;
9702 bool resc_reinit = false;
9703 int rc, retry = 0;
9704 u32 flags = 0;
9705
9706 if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
9707 return 0;
9708
9709 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_IF_CHANGE, -1, -1);
9710 if (up)
9711 req.flags = cpu_to_le32(FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP);
9712 mutex_lock(&bp->hwrm_cmd_lock);
9713 while (retry < BNXT_FW_IF_RETRY) {
9714 rc = _hwrm_send_message(bp, &req, sizeof(req),
9715 HWRM_CMD_TIMEOUT);
9716 if (rc != -EAGAIN)
9717 break;
9718
9719 msleep(50);
9720 retry++;
9721 }
9722 if (!rc)
9723 flags = le32_to_cpu(resp->flags);
9724 mutex_unlock(&bp->hwrm_cmd_lock);
9725
9726 if (rc == -EAGAIN)
9727 return rc;
9728 if (rc && up) {
9729 rc = bnxt_try_recover_fw(bp);
9730 fw_reset = true;
9731 }
9732 if (rc)
9733 return rc;
9734
9735 if (!up) {
9736 bnxt_inv_fw_health_reg(bp);
9737 return 0;
9738 }
9739
9740 if (flags & FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE)
9741 resc_reinit = true;
9742 if (flags & FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE)
9743 fw_reset = true;
9744 else if (bp->fw_health && !bp->fw_health->status_reliable)
9745 bnxt_try_map_fw_health_reg(bp);
9746
9747 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state) && !fw_reset) {
9748 netdev_err(bp->dev, "RESET_DONE not set during FW reset.\n");
9749 set_bit(BNXT_STATE_ABORT_ERR, &bp->state);
9750 return -ENODEV;
9751 }
9752 if (resc_reinit || fw_reset) {
9753 if (fw_reset) {
9754 set_bit(BNXT_STATE_FW_RESET_DET, &bp->state);
9755 if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
9756 bnxt_ulp_stop(bp);
9757 bnxt_free_ctx_mem(bp);
9758 kfree(bp->ctx);
9759 bp->ctx = NULL;
9760 bnxt_dcb_free(bp);
9761 rc = bnxt_fw_init_one(bp);
9762 if (rc) {
9763 clear_bit(BNXT_STATE_FW_RESET_DET, &bp->state);
9764 set_bit(BNXT_STATE_ABORT_ERR, &bp->state);
9765 return rc;
9766 }
9767 bnxt_clear_int_mode(bp);
9768 rc = bnxt_init_int_mode(bp);
9769 if (rc) {
9770 clear_bit(BNXT_STATE_FW_RESET_DET, &bp->state);
9771 netdev_err(bp->dev, "init int mode failed\n");
9772 return rc;
9773 }
9774 }
9775 if (BNXT_NEW_RM(bp)) {
9776 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
9777
9778 rc = bnxt_hwrm_func_resc_qcaps(bp, true);
9779 if (rc)
9780 netdev_err(bp->dev, "resc_qcaps failed\n");
9781
9782 hw_resc->resv_cp_rings = 0;
9783 hw_resc->resv_stat_ctxs = 0;
9784 hw_resc->resv_irqs = 0;
9785 hw_resc->resv_tx_rings = 0;
9786 hw_resc->resv_rx_rings = 0;
9787 hw_resc->resv_hw_ring_grps = 0;
9788 hw_resc->resv_vnics = 0;
9789 if (!fw_reset) {
9790 bp->tx_nr_rings = 0;
9791 bp->rx_nr_rings = 0;
9792 }
9793 }
9794 }
9795 return rc;
9796 }
9797
9798 static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
9799 {
9800 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
9801 struct hwrm_port_led_qcaps_input req = {0};
9802 struct bnxt_pf_info *pf = &bp->pf;
9803 int rc;
9804
9805 bp->num_leds = 0;
9806 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601)
9807 return 0;
9808
9809 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1);
9810 req.port_id = cpu_to_le16(pf->port_id);
9811 mutex_lock(&bp->hwrm_cmd_lock);
9812 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9813 if (rc) {
9814 mutex_unlock(&bp->hwrm_cmd_lock);
9815 return rc;
9816 }
9817 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
9818 int i;
9819
9820 bp->num_leds = resp->num_leds;
9821 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) *
9822 bp->num_leds);
9823 for (i = 0; i < bp->num_leds; i++) {
9824 struct bnxt_led_info *led = &bp->leds[i];
9825 __le16 caps = led->led_state_caps;
9826
9827 if (!led->led_group_id ||
9828 !BNXT_LED_ALT_BLINK_CAP(caps)) {
9829 bp->num_leds = 0;
9830 break;
9831 }
9832 }
9833 }
9834 mutex_unlock(&bp->hwrm_cmd_lock);
9835 return 0;
9836 }
9837
9838 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp)
9839 {
9840 struct hwrm_wol_filter_alloc_input req = {0};
9841 struct hwrm_wol_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
9842 int rc;
9843
9844 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_ALLOC, -1, -1);
9845 req.port_id = cpu_to_le16(bp->pf.port_id);
9846 req.wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT;
9847 req.enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS);
9848 memcpy(req.mac_address, bp->dev->dev_addr, ETH_ALEN);
9849 mutex_lock(&bp->hwrm_cmd_lock);
9850 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9851 if (!rc)
9852 bp->wol_filter_id = resp->wol_filter_id;
9853 mutex_unlock(&bp->hwrm_cmd_lock);
9854 return rc;
9855 }
9856
9857 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp)
9858 {
9859 struct hwrm_wol_filter_free_input req = {0};
9860
9861 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1);
9862 req.port_id = cpu_to_le16(bp->pf.port_id);
9863 req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID);
9864 req.wol_filter_id = bp->wol_filter_id;
9865 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9866 }
9867
9868 static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle)
9869 {
9870 struct hwrm_wol_filter_qcfg_input req = {0};
9871 struct hwrm_wol_filter_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
9872 u16 next_handle = 0;
9873 int rc;
9874
9875 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_QCFG, -1, -1);
9876 req.port_id = cpu_to_le16(bp->pf.port_id);
9877 req.handle = cpu_to_le16(handle);
9878 mutex_lock(&bp->hwrm_cmd_lock);
9879 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9880 if (!rc) {
9881 next_handle = le16_to_cpu(resp->next_handle);
9882 if (next_handle != 0) {
9883 if (resp->wol_type ==
9884 WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) {
9885 bp->wol = 1;
9886 bp->wol_filter_id = resp->wol_filter_id;
9887 }
9888 }
9889 }
9890 mutex_unlock(&bp->hwrm_cmd_lock);
9891 return next_handle;
9892 }
9893
9894 static void bnxt_get_wol_settings(struct bnxt *bp)
9895 {
9896 u16 handle = 0;
9897
9898 bp->wol = 0;
9899 if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP))
9900 return;
9901
9902 do {
9903 handle = bnxt_hwrm_get_wol_fltrs(bp, handle);
9904 } while (handle && handle != 0xffff);
9905 }
9906
9907 #ifdef CONFIG_BNXT_HWMON
9908 static ssize_t bnxt_show_temp(struct device *dev,
9909 struct device_attribute *devattr, char *buf)
9910 {
9911 struct hwrm_temp_monitor_query_input req = {0};
9912 struct hwrm_temp_monitor_query_output *resp;
9913 struct bnxt *bp = dev_get_drvdata(dev);
9914 u32 len = 0;
9915 int rc;
9916
9917 resp = bp->hwrm_cmd_resp_addr;
9918 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TEMP_MONITOR_QUERY, -1, -1);
9919 mutex_lock(&bp->hwrm_cmd_lock);
9920 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9921 if (!rc)
9922 len = sprintf(buf, "%u\n", resp->temp * 1000); /* display millidegree */
9923 mutex_unlock(&bp->hwrm_cmd_lock);
9924 if (rc)
9925 return rc;
9926 return len;
9927 }
9928 static SENSOR_DEVICE_ATTR(temp1_input, 0444, bnxt_show_temp, NULL, 0);
9929
9930 static struct attribute *bnxt_attrs[] = {
9931 &sensor_dev_attr_temp1_input.dev_attr.attr,
9932 NULL
9933 };
9934 ATTRIBUTE_GROUPS(bnxt);
9935
9936 static void bnxt_hwmon_close(struct bnxt *bp)
9937 {
9938 if (bp->hwmon_dev) {
9939 hwmon_device_unregister(bp->hwmon_dev);
9940 bp->hwmon_dev = NULL;
9941 }
9942 }
9943
9944 static void bnxt_hwmon_open(struct bnxt *bp)
9945 {
9946 struct hwrm_temp_monitor_query_input req = {0};
9947 struct pci_dev *pdev = bp->pdev;
9948 int rc;
9949
9950 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TEMP_MONITOR_QUERY, -1, -1);
9951 rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9952 if (rc == -EACCES || rc == -EOPNOTSUPP) {
9953 bnxt_hwmon_close(bp);
9954 return;
9955 }
9956
9957 if (bp->hwmon_dev)
9958 return;
9959
9960 bp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev,
9961 DRV_MODULE_NAME, bp,
9962 bnxt_groups);
9963 if (IS_ERR(bp->hwmon_dev)) {
9964 bp->hwmon_dev = NULL;
9965 dev_warn(&pdev->dev, "Cannot register hwmon device\n");
9966 }
9967 }
9968 #else
9969 static void bnxt_hwmon_close(struct bnxt *bp)
9970 {
9971 }
9972
9973 static void bnxt_hwmon_open(struct bnxt *bp)
9974 {
9975 }
9976 #endif
9977
9978 static bool bnxt_eee_config_ok(struct bnxt *bp)
9979 {
9980 struct ethtool_eee *eee = &bp->eee;
9981 struct bnxt_link_info *link_info = &bp->link_info;
9982
9983 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP))
9984 return true;
9985
9986 if (eee->eee_enabled) {
9987 u32 advertising =
9988 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
9989
9990 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
9991 eee->eee_enabled = 0;
9992 return false;
9993 }
9994 if (eee->advertised & ~advertising) {
9995 eee->advertised = advertising & eee->supported;
9996 return false;
9997 }
9998 }
9999 return true;
10000 }
10001
10002 static int bnxt_update_phy_setting(struct bnxt *bp)
10003 {
10004 int rc;
10005 bool update_link = false;
10006 bool update_pause = false;
10007 bool update_eee = false;
10008 struct bnxt_link_info *link_info = &bp->link_info;
10009
10010 rc = bnxt_update_link(bp, true);
10011 if (rc) {
10012 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
10013 rc);
10014 return rc;
10015 }
10016 if (!BNXT_SINGLE_PF(bp))
10017 return 0;
10018
10019 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
10020 (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
10021 link_info->req_flow_ctrl)
10022 update_pause = true;
10023 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
10024 link_info->force_pause_setting != link_info->req_flow_ctrl)
10025 update_pause = true;
10026 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
10027 if (BNXT_AUTO_MODE(link_info->auto_mode))
10028 update_link = true;
10029 if (link_info->req_signal_mode == BNXT_SIG_MODE_NRZ &&
10030 link_info->req_link_speed != link_info->force_link_speed)
10031 update_link = true;
10032 else if (link_info->req_signal_mode == BNXT_SIG_MODE_PAM4 &&
10033 link_info->req_link_speed != link_info->force_pam4_link_speed)
10034 update_link = true;
10035 if (link_info->req_duplex != link_info->duplex_setting)
10036 update_link = true;
10037 } else {
10038 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
10039 update_link = true;
10040 if (link_info->advertising != link_info->auto_link_speeds ||
10041 link_info->advertising_pam4 != link_info->auto_pam4_link_speeds)
10042 update_link = true;
10043 }
10044
10045 /* The last close may have shutdown the link, so need to call
10046 * PHY_CFG to bring it back up.
10047 */
10048 if (!bp->link_info.link_up)
10049 update_link = true;
10050
10051 if (!bnxt_eee_config_ok(bp))
10052 update_eee = true;
10053
10054 if (update_link)
10055 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
10056 else if (update_pause)
10057 rc = bnxt_hwrm_set_pause(bp);
10058 if (rc) {
10059 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
10060 rc);
10061 return rc;
10062 }
10063
10064 return rc;
10065 }
10066
10067 /* Common routine to pre-map certain register block to different GRC window.
10068 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
10069 * in PF and 3 windows in VF that can be customized to map in different
10070 * register blocks.
10071 */
10072 static void bnxt_preset_reg_win(struct bnxt *bp)
10073 {
10074 if (BNXT_PF(bp)) {
10075 /* CAG registers map to GRC window #4 */
10076 writel(BNXT_CAG_REG_BASE,
10077 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
10078 }
10079 }
10080
10081 static int bnxt_init_dflt_ring_mode(struct bnxt *bp);
10082
10083 static int bnxt_reinit_after_abort(struct bnxt *bp)
10084 {
10085 int rc;
10086
10087 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
10088 return -EBUSY;
10089
10090 if (bp->dev->reg_state == NETREG_UNREGISTERED)
10091 return -ENODEV;
10092
10093 rc = bnxt_fw_init_one(bp);
10094 if (!rc) {
10095 bnxt_clear_int_mode(bp);
10096 rc = bnxt_init_int_mode(bp);
10097 if (!rc) {
10098 clear_bit(BNXT_STATE_ABORT_ERR, &bp->state);
10099 set_bit(BNXT_STATE_FW_RESET_DET, &bp->state);
10100 }
10101 }
10102 return rc;
10103 }
10104
10105 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
10106 {
10107 int rc = 0;
10108
10109 bnxt_preset_reg_win(bp);
10110 netif_carrier_off(bp->dev);
10111 if (irq_re_init) {
10112 /* Reserve rings now if none were reserved at driver probe. */
10113 rc = bnxt_init_dflt_ring_mode(bp);
10114 if (rc) {
10115 netdev_err(bp->dev, "Failed to reserve default rings at open\n");
10116 return rc;
10117 }
10118 }
10119 rc = bnxt_reserve_rings(bp, irq_re_init);
10120 if (rc)
10121 return rc;
10122 if ((bp->flags & BNXT_FLAG_RFS) &&
10123 !(bp->flags & BNXT_FLAG_USING_MSIX)) {
10124 /* disable RFS if falling back to INTA */
10125 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
10126 bp->flags &= ~BNXT_FLAG_RFS;
10127 }
10128
10129 rc = bnxt_alloc_mem(bp, irq_re_init);
10130 if (rc) {
10131 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
10132 goto open_err_free_mem;
10133 }
10134
10135 if (irq_re_init) {
10136 bnxt_init_napi(bp);
10137 rc = bnxt_request_irq(bp);
10138 if (rc) {
10139 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
10140 goto open_err_irq;
10141 }
10142 }
10143
10144 rc = bnxt_init_nic(bp, irq_re_init);
10145 if (rc) {
10146 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
10147 goto open_err_irq;
10148 }
10149
10150 bnxt_enable_napi(bp);
10151 bnxt_debug_dev_init(bp);
10152
10153 if (link_re_init) {
10154 mutex_lock(&bp->link_lock);
10155 rc = bnxt_update_phy_setting(bp);
10156 mutex_unlock(&bp->link_lock);
10157 if (rc) {
10158 netdev_warn(bp->dev, "failed to update phy settings\n");
10159 if (BNXT_SINGLE_PF(bp)) {
10160 bp->link_info.phy_retry = true;
10161 bp->link_info.phy_retry_expires =
10162 jiffies + 5 * HZ;
10163 }
10164 }
10165 }
10166
10167 if (irq_re_init)
10168 udp_tunnel_nic_reset_ntf(bp->dev);
10169
10170 set_bit(BNXT_STATE_OPEN, &bp->state);
10171 bnxt_enable_int(bp);
10172 /* Enable TX queues */
10173 bnxt_tx_enable(bp);
10174 mod_timer(&bp->timer, jiffies + bp->current_interval);
10175 /* Poll link status and check for SFP+ module status */
10176 bnxt_get_port_module_status(bp);
10177
10178 /* VF-reps may need to be re-opened after the PF is re-opened */
10179 if (BNXT_PF(bp))
10180 bnxt_vf_reps_open(bp);
10181 return 0;
10182
10183 open_err_irq:
10184 bnxt_del_napi(bp);
10185
10186 open_err_free_mem:
10187 bnxt_free_skbs(bp);
10188 bnxt_free_irq(bp);
10189 bnxt_free_mem(bp, true);
10190 return rc;
10191 }
10192
10193 /* rtnl_lock held */
10194 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
10195 {
10196 int rc = 0;
10197
10198 if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state))
10199 rc = -EIO;
10200 if (!rc)
10201 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
10202 if (rc) {
10203 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
10204 dev_close(bp->dev);
10205 }
10206 return rc;
10207 }
10208
10209 /* rtnl_lock held, open the NIC half way by allocating all resources, but
10210 * NAPI, IRQ, and TX are not enabled. This is mainly used for offline
10211 * self tests.
10212 */
10213 int bnxt_half_open_nic(struct bnxt *bp)
10214 {
10215 int rc = 0;
10216
10217 if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state)) {
10218 netdev_err(bp->dev, "A previous firmware reset has not completed, aborting half open\n");
10219 rc = -ENODEV;
10220 goto half_open_err;
10221 }
10222
10223 rc = bnxt_alloc_mem(bp, false);
10224 if (rc) {
10225 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
10226 goto half_open_err;
10227 }
10228 rc = bnxt_init_nic(bp, false);
10229 if (rc) {
10230 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
10231 goto half_open_err;
10232 }
10233 return 0;
10234
10235 half_open_err:
10236 bnxt_free_skbs(bp);
10237 bnxt_free_mem(bp, false);
10238 dev_close(bp->dev);
10239 return rc;
10240 }
10241
10242 /* rtnl_lock held, this call can only be made after a previous successful
10243 * call to bnxt_half_open_nic().
10244 */
10245 void bnxt_half_close_nic(struct bnxt *bp)
10246 {
10247 bnxt_hwrm_resource_free(bp, false, false);
10248 bnxt_free_skbs(bp);
10249 bnxt_free_mem(bp, false);
10250 }
10251
10252 static void bnxt_reenable_sriov(struct bnxt *bp)
10253 {
10254 if (BNXT_PF(bp)) {
10255 struct bnxt_pf_info *pf = &bp->pf;
10256 int n = pf->active_vfs;
10257
10258 if (n)
10259 bnxt_cfg_hw_sriov(bp, &n, true);
10260 }
10261 }
10262
10263 static int bnxt_open(struct net_device *dev)
10264 {
10265 struct bnxt *bp = netdev_priv(dev);
10266 int rc;
10267
10268 if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state)) {
10269 rc = bnxt_reinit_after_abort(bp);
10270 if (rc) {
10271 if (rc == -EBUSY)
10272 netdev_err(bp->dev, "A previous firmware reset has not completed, aborting\n");
10273 else
10274 netdev_err(bp->dev, "Failed to reinitialize after aborted firmware reset\n");
10275 return -ENODEV;
10276 }
10277 }
10278
10279 rc = bnxt_hwrm_if_change(bp, true);
10280 if (rc)
10281 return rc;
10282
10283 if (bnxt_ptp_init(bp)) {
10284 netdev_warn(dev, "PTP initialization failed.\n");
10285 kfree(bp->ptp_cfg);
10286 bp->ptp_cfg = NULL;
10287 }
10288 rc = __bnxt_open_nic(bp, true, true);
10289 if (rc) {
10290 bnxt_hwrm_if_change(bp, false);
10291 bnxt_ptp_clear(bp);
10292 } else {
10293 if (test_and_clear_bit(BNXT_STATE_FW_RESET_DET, &bp->state)) {
10294 if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) {
10295 bnxt_ulp_start(bp, 0);
10296 bnxt_reenable_sriov(bp);
10297 }
10298 }
10299 bnxt_hwmon_open(bp);
10300 }
10301
10302 return rc;
10303 }
10304
10305 static bool bnxt_drv_busy(struct bnxt *bp)
10306 {
10307 return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) ||
10308 test_bit(BNXT_STATE_READ_STATS, &bp->state));
10309 }
10310
10311 static void bnxt_get_ring_stats(struct bnxt *bp,
10312 struct rtnl_link_stats64 *stats);
10313
10314 static void __bnxt_close_nic(struct bnxt *bp, bool irq_re_init,
10315 bool link_re_init)
10316 {
10317 /* Close the VF-reps before closing PF */
10318 if (BNXT_PF(bp))
10319 bnxt_vf_reps_close(bp);
10320
10321 /* Change device state to avoid TX queue wake up's */
10322 bnxt_tx_disable(bp);
10323
10324 clear_bit(BNXT_STATE_OPEN, &bp->state);
10325 smp_mb__after_atomic();
10326 while (bnxt_drv_busy(bp))
10327 msleep(20);
10328
10329 /* Flush rings and and disable interrupts */
10330 bnxt_shutdown_nic(bp, irq_re_init);
10331
10332 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
10333
10334 bnxt_debug_dev_exit(bp);
10335 bnxt_disable_napi(bp);
10336 del_timer_sync(&bp->timer);
10337 bnxt_free_skbs(bp);
10338
10339 /* Save ring stats before shutdown */
10340 if (bp->bnapi && irq_re_init)
10341 bnxt_get_ring_stats(bp, &bp->net_stats_prev);
10342 if (irq_re_init) {
10343 bnxt_free_irq(bp);
10344 bnxt_del_napi(bp);
10345 }
10346 bnxt_free_mem(bp, irq_re_init);
10347 }
10348
10349 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
10350 {
10351 int rc = 0;
10352
10353 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) {
10354 /* If we get here, it means firmware reset is in progress
10355 * while we are trying to close. We can safely proceed with
10356 * the close because we are holding rtnl_lock(). Some firmware
10357 * messages may fail as we proceed to close. We set the
10358 * ABORT_ERR flag here so that the FW reset thread will later
10359 * abort when it gets the rtnl_lock() and sees the flag.
10360 */
10361 netdev_warn(bp->dev, "FW reset in progress during close, FW reset will be aborted\n");
10362 set_bit(BNXT_STATE_ABORT_ERR, &bp->state);
10363 }
10364
10365 #ifdef CONFIG_BNXT_SRIOV
10366 if (bp->sriov_cfg) {
10367 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
10368 !bp->sriov_cfg,
10369 BNXT_SRIOV_CFG_WAIT_TMO);
10370 if (rc)
10371 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
10372 }
10373 #endif
10374 __bnxt_close_nic(bp, irq_re_init, link_re_init);
10375 return rc;
10376 }
10377
10378 static int bnxt_close(struct net_device *dev)
10379 {
10380 struct bnxt *bp = netdev_priv(dev);
10381
10382 bnxt_ptp_clear(bp);
10383 bnxt_hwmon_close(bp);
10384 bnxt_close_nic(bp, true, true);
10385 bnxt_hwrm_shutdown_link(bp);
10386 bnxt_hwrm_if_change(bp, false);
10387 return 0;
10388 }
10389
10390 static int bnxt_hwrm_port_phy_read(struct bnxt *bp, u16 phy_addr, u16 reg,
10391 u16 *val)
10392 {
10393 struct hwrm_port_phy_mdio_read_output *resp = bp->hwrm_cmd_resp_addr;
10394 struct hwrm_port_phy_mdio_read_input req = {0};
10395 int rc;
10396
10397 if (bp->hwrm_spec_code < 0x10a00)
10398 return -EOPNOTSUPP;
10399
10400 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_READ, -1, -1);
10401 req.port_id = cpu_to_le16(bp->pf.port_id);
10402 req.phy_addr = phy_addr;
10403 req.reg_addr = cpu_to_le16(reg & 0x1f);
10404 if (mdio_phy_id_is_c45(phy_addr)) {
10405 req.cl45_mdio = 1;
10406 req.phy_addr = mdio_phy_id_prtad(phy_addr);
10407 req.dev_addr = mdio_phy_id_devad(phy_addr);
10408 req.reg_addr = cpu_to_le16(reg);
10409 }
10410
10411 mutex_lock(&bp->hwrm_cmd_lock);
10412 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
10413 if (!rc)
10414 *val = le16_to_cpu(resp->reg_data);
10415 mutex_unlock(&bp->hwrm_cmd_lock);
10416 return rc;
10417 }
10418
10419 static int bnxt_hwrm_port_phy_write(struct bnxt *bp, u16 phy_addr, u16 reg,
10420 u16 val)
10421 {
10422 struct hwrm_port_phy_mdio_write_input req = {0};
10423
10424 if (bp->hwrm_spec_code < 0x10a00)
10425 return -EOPNOTSUPP;
10426
10427 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_WRITE, -1, -1);
10428 req.port_id = cpu_to_le16(bp->pf.port_id);
10429 req.phy_addr = phy_addr;
10430 req.reg_addr = cpu_to_le16(reg & 0x1f);
10431 if (mdio_phy_id_is_c45(phy_addr)) {
10432 req.cl45_mdio = 1;
10433 req.phy_addr = mdio_phy_id_prtad(phy_addr);
10434 req.dev_addr = mdio_phy_id_devad(phy_addr);
10435 req.reg_addr = cpu_to_le16(reg);
10436 }
10437 req.reg_data = cpu_to_le16(val);
10438
10439 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
10440 }
10441
10442 /* rtnl_lock held */
10443 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10444 {
10445 struct mii_ioctl_data *mdio = if_mii(ifr);
10446 struct bnxt *bp = netdev_priv(dev);
10447 int rc;
10448
10449 switch (cmd) {
10450 case SIOCGMIIPHY:
10451 mdio->phy_id = bp->link_info.phy_addr;
10452
10453 fallthrough;
10454 case SIOCGMIIREG: {
10455 u16 mii_regval = 0;
10456
10457 if (!netif_running(dev))
10458 return -EAGAIN;
10459
10460 rc = bnxt_hwrm_port_phy_read(bp, mdio->phy_id, mdio->reg_num,
10461 &mii_regval);
10462 mdio->val_out = mii_regval;
10463 return rc;
10464 }
10465
10466 case SIOCSMIIREG:
10467 if (!netif_running(dev))
10468 return -EAGAIN;
10469
10470 return bnxt_hwrm_port_phy_write(bp, mdio->phy_id, mdio->reg_num,
10471 mdio->val_in);
10472
10473 case SIOCSHWTSTAMP:
10474 return bnxt_hwtstamp_set(dev, ifr);
10475
10476 case SIOCGHWTSTAMP:
10477 return bnxt_hwtstamp_get(dev, ifr);
10478
10479 default:
10480 /* do nothing */
10481 break;
10482 }
10483 return -EOPNOTSUPP;
10484 }
10485
10486 static void bnxt_get_ring_stats(struct bnxt *bp,
10487 struct rtnl_link_stats64 *stats)
10488 {
10489 int i;
10490
10491 for (i = 0; i < bp->cp_nr_rings; i++) {
10492 struct bnxt_napi *bnapi = bp->bnapi[i];
10493 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
10494 u64 *sw = cpr->stats.sw_stats;
10495
10496 stats->rx_packets += BNXT_GET_RING_STATS64(sw, rx_ucast_pkts);
10497 stats->rx_packets += BNXT_GET_RING_STATS64(sw, rx_mcast_pkts);
10498 stats->rx_packets += BNXT_GET_RING_STATS64(sw, rx_bcast_pkts);
10499
10500 stats->tx_packets += BNXT_GET_RING_STATS64(sw, tx_ucast_pkts);
10501 stats->tx_packets += BNXT_GET_RING_STATS64(sw, tx_mcast_pkts);
10502 stats->tx_packets += BNXT_GET_RING_STATS64(sw, tx_bcast_pkts);
10503
10504 stats->rx_bytes += BNXT_GET_RING_STATS64(sw, rx_ucast_bytes);
10505 stats->rx_bytes += BNXT_GET_RING_STATS64(sw, rx_mcast_bytes);
10506 stats->rx_bytes += BNXT_GET_RING_STATS64(sw, rx_bcast_bytes);
10507
10508 stats->tx_bytes += BNXT_GET_RING_STATS64(sw, tx_ucast_bytes);
10509 stats->tx_bytes += BNXT_GET_RING_STATS64(sw, tx_mcast_bytes);
10510 stats->tx_bytes += BNXT_GET_RING_STATS64(sw, tx_bcast_bytes);
10511
10512 stats->rx_missed_errors +=
10513 BNXT_GET_RING_STATS64(sw, rx_discard_pkts);
10514
10515 stats->multicast += BNXT_GET_RING_STATS64(sw, rx_mcast_pkts);
10516
10517 stats->tx_dropped += BNXT_GET_RING_STATS64(sw, tx_error_pkts);
10518 }
10519 }
10520
10521 static void bnxt_add_prev_stats(struct bnxt *bp,
10522 struct rtnl_link_stats64 *stats)
10523 {
10524 struct rtnl_link_stats64 *prev_stats = &bp->net_stats_prev;
10525
10526 stats->rx_packets += prev_stats->rx_packets;
10527 stats->tx_packets += prev_stats->tx_packets;
10528 stats->rx_bytes += prev_stats->rx_bytes;
10529 stats->tx_bytes += prev_stats->tx_bytes;
10530 stats->rx_missed_errors += prev_stats->rx_missed_errors;
10531 stats->multicast += prev_stats->multicast;
10532 stats->tx_dropped += prev_stats->tx_dropped;
10533 }
10534
10535 static void
10536 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
10537 {
10538 struct bnxt *bp = netdev_priv(dev);
10539
10540 set_bit(BNXT_STATE_READ_STATS, &bp->state);
10541 /* Make sure bnxt_close_nic() sees that we are reading stats before
10542 * we check the BNXT_STATE_OPEN flag.
10543 */
10544 smp_mb__after_atomic();
10545 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
10546 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
10547 *stats = bp->net_stats_prev;
10548 return;
10549 }
10550
10551 bnxt_get_ring_stats(bp, stats);
10552 bnxt_add_prev_stats(bp, stats);
10553
10554 if (bp->flags & BNXT_FLAG_PORT_STATS) {
10555 u64 *rx = bp->port_stats.sw_stats;
10556 u64 *tx = bp->port_stats.sw_stats +
10557 BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
10558
10559 stats->rx_crc_errors =
10560 BNXT_GET_RX_PORT_STATS64(rx, rx_fcs_err_frames);
10561 stats->rx_frame_errors =
10562 BNXT_GET_RX_PORT_STATS64(rx, rx_align_err_frames);
10563 stats->rx_length_errors =
10564 BNXT_GET_RX_PORT_STATS64(rx, rx_undrsz_frames) +
10565 BNXT_GET_RX_PORT_STATS64(rx, rx_ovrsz_frames) +
10566 BNXT_GET_RX_PORT_STATS64(rx, rx_runt_frames);
10567 stats->rx_errors =
10568 BNXT_GET_RX_PORT_STATS64(rx, rx_false_carrier_frames) +
10569 BNXT_GET_RX_PORT_STATS64(rx, rx_jbr_frames);
10570 stats->collisions =
10571 BNXT_GET_TX_PORT_STATS64(tx, tx_total_collisions);
10572 stats->tx_fifo_errors =
10573 BNXT_GET_TX_PORT_STATS64(tx, tx_fifo_underruns);
10574 stats->tx_errors = BNXT_GET_TX_PORT_STATS64(tx, tx_err);
10575 }
10576 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
10577 }
10578
10579 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
10580 {
10581 struct net_device *dev = bp->dev;
10582 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
10583 struct netdev_hw_addr *ha;
10584 u8 *haddr;
10585 int mc_count = 0;
10586 bool update = false;
10587 int off = 0;
10588
10589 netdev_for_each_mc_addr(ha, dev) {
10590 if (mc_count >= BNXT_MAX_MC_ADDRS) {
10591 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
10592 vnic->mc_list_count = 0;
10593 return false;
10594 }
10595 haddr = ha->addr;
10596 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
10597 memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
10598 update = true;
10599 }
10600 off += ETH_ALEN;
10601 mc_count++;
10602 }
10603 if (mc_count)
10604 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
10605
10606 if (mc_count != vnic->mc_list_count) {
10607 vnic->mc_list_count = mc_count;
10608 update = true;
10609 }
10610 return update;
10611 }
10612
10613 static bool bnxt_uc_list_updated(struct bnxt *bp)
10614 {
10615 struct net_device *dev = bp->dev;
10616 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
10617 struct netdev_hw_addr *ha;
10618 int off = 0;
10619
10620 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
10621 return true;
10622
10623 netdev_for_each_uc_addr(ha, dev) {
10624 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
10625 return true;
10626
10627 off += ETH_ALEN;
10628 }
10629 return false;
10630 }
10631
10632 static void bnxt_set_rx_mode(struct net_device *dev)
10633 {
10634 struct bnxt *bp = netdev_priv(dev);
10635 struct bnxt_vnic_info *vnic;
10636 bool mc_update = false;
10637 bool uc_update;
10638 u32 mask;
10639
10640 if (!test_bit(BNXT_STATE_OPEN, &bp->state))
10641 return;
10642
10643 vnic = &bp->vnic_info[0];
10644 mask = vnic->rx_mask;
10645 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
10646 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
10647 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST |
10648 CFA_L2_SET_RX_MASK_REQ_MASK_BCAST);
10649
10650 if (dev->flags & IFF_PROMISC)
10651 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
10652
10653 uc_update = bnxt_uc_list_updated(bp);
10654
10655 if (dev->flags & IFF_BROADCAST)
10656 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
10657 if (dev->flags & IFF_ALLMULTI) {
10658 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
10659 vnic->mc_list_count = 0;
10660 } else {
10661 mc_update = bnxt_mc_list_updated(bp, &mask);
10662 }
10663
10664 if (mask != vnic->rx_mask || uc_update || mc_update) {
10665 vnic->rx_mask = mask;
10666
10667 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
10668 bnxt_queue_sp_work(bp);
10669 }
10670 }
10671
10672 static int bnxt_cfg_rx_mode(struct bnxt *bp)
10673 {
10674 struct net_device *dev = bp->dev;
10675 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
10676 struct netdev_hw_addr *ha;
10677 int i, off = 0, rc;
10678 bool uc_update;
10679
10680 netif_addr_lock_bh(dev);
10681 uc_update = bnxt_uc_list_updated(bp);
10682 netif_addr_unlock_bh(dev);
10683
10684 if (!uc_update)
10685 goto skip_uc;
10686
10687 mutex_lock(&bp->hwrm_cmd_lock);
10688 for (i = 1; i < vnic->uc_filter_count; i++) {
10689 struct hwrm_cfa_l2_filter_free_input req = {0};
10690
10691 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
10692 -1);
10693
10694 req.l2_filter_id = vnic->fw_l2_filter_id[i];
10695
10696 rc = _hwrm_send_message(bp, &req, sizeof(req),
10697 HWRM_CMD_TIMEOUT);
10698 }
10699 mutex_unlock(&bp->hwrm_cmd_lock);
10700
10701 vnic->uc_filter_count = 1;
10702
10703 netif_addr_lock_bh(dev);
10704 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
10705 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
10706 } else {
10707 netdev_for_each_uc_addr(ha, dev) {
10708 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
10709 off += ETH_ALEN;
10710 vnic->uc_filter_count++;
10711 }
10712 }
10713 netif_addr_unlock_bh(dev);
10714
10715 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
10716 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
10717 if (rc) {
10718 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
10719 rc);
10720 vnic->uc_filter_count = i;
10721 return rc;
10722 }
10723 }
10724
10725 skip_uc:
10726 if ((vnic->rx_mask & CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS) &&
10727 !bnxt_promisc_ok(bp))
10728 vnic->rx_mask &= ~CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
10729 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
10730 if (rc && vnic->mc_list_count) {
10731 netdev_info(bp->dev, "Failed setting MC filters rc: %d, turning on ALL_MCAST mode\n",
10732 rc);
10733 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
10734 vnic->mc_list_count = 0;
10735 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
10736 }
10737 if (rc)
10738 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %d\n",
10739 rc);
10740
10741 return rc;
10742 }
10743
10744 static bool bnxt_can_reserve_rings(struct bnxt *bp)
10745 {
10746 #ifdef CONFIG_BNXT_SRIOV
10747 if (BNXT_NEW_RM(bp) && BNXT_VF(bp)) {
10748 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
10749
10750 /* No minimum rings were provisioned by the PF. Don't
10751 * reserve rings by default when device is down.
10752 */
10753 if (hw_resc->min_tx_rings || hw_resc->resv_tx_rings)
10754 return true;
10755
10756 if (!netif_running(bp->dev))
10757 return false;
10758 }
10759 #endif
10760 return true;
10761 }
10762
10763 /* If the chip and firmware supports RFS */
10764 static bool bnxt_rfs_supported(struct bnxt *bp)
10765 {
10766 if (bp->flags & BNXT_FLAG_CHIP_P5) {
10767 if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2)
10768 return true;
10769 return false;
10770 }
10771 if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
10772 return true;
10773 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
10774 return true;
10775 return false;
10776 }
10777
10778 /* If runtime conditions support RFS */
10779 static bool bnxt_rfs_capable(struct bnxt *bp)
10780 {
10781 #ifdef CONFIG_RFS_ACCEL
10782 int vnics, max_vnics, max_rss_ctxs;
10783
10784 if (bp->flags & BNXT_FLAG_CHIP_P5)
10785 return bnxt_rfs_supported(bp);
10786 if (!(bp->flags & BNXT_FLAG_MSIX_CAP) || !bnxt_can_reserve_rings(bp))
10787 return false;
10788
10789 vnics = 1 + bp->rx_nr_rings;
10790 max_vnics = bnxt_get_max_func_vnics(bp);
10791 max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp);
10792
10793 /* RSS contexts not a limiting factor */
10794 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
10795 max_rss_ctxs = max_vnics;
10796 if (vnics > max_vnics || vnics > max_rss_ctxs) {
10797 if (bp->rx_nr_rings > 1)
10798 netdev_warn(bp->dev,
10799 "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
10800 min(max_rss_ctxs - 1, max_vnics - 1));
10801 return false;
10802 }
10803
10804 if (!BNXT_NEW_RM(bp))
10805 return true;
10806
10807 if (vnics == bp->hw_resc.resv_vnics)
10808 return true;
10809
10810 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, vnics);
10811 if (vnics <= bp->hw_resc.resv_vnics)
10812 return true;
10813
10814 netdev_warn(bp->dev, "Unable to reserve resources to support NTUPLE filters.\n");
10815 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, 1);
10816 return false;
10817 #else
10818 return false;
10819 #endif
10820 }
10821
10822 static netdev_features_t bnxt_fix_features(struct net_device *dev,
10823 netdev_features_t features)
10824 {
10825 struct bnxt *bp = netdev_priv(dev);
10826 netdev_features_t vlan_features;
10827
10828 if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp))
10829 features &= ~NETIF_F_NTUPLE;
10830
10831 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
10832 features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
10833
10834 if (!(features & NETIF_F_GRO))
10835 features &= ~NETIF_F_GRO_HW;
10836
10837 if (features & NETIF_F_GRO_HW)
10838 features &= ~NETIF_F_LRO;
10839
10840 /* Both CTAG and STAG VLAN accelaration on the RX side have to be
10841 * turned on or off together.
10842 */
10843 vlan_features = features & BNXT_HW_FEATURE_VLAN_ALL_RX;
10844 if (vlan_features != BNXT_HW_FEATURE_VLAN_ALL_RX) {
10845 if (dev->features & BNXT_HW_FEATURE_VLAN_ALL_RX)
10846 features &= ~BNXT_HW_FEATURE_VLAN_ALL_RX;
10847 else if (vlan_features)
10848 features |= BNXT_HW_FEATURE_VLAN_ALL_RX;
10849 }
10850 #ifdef CONFIG_BNXT_SRIOV
10851 if (BNXT_VF(bp) && bp->vf.vlan)
10852 features &= ~BNXT_HW_FEATURE_VLAN_ALL_RX;
10853 #endif
10854 return features;
10855 }
10856
10857 static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
10858 {
10859 struct bnxt *bp = netdev_priv(dev);
10860 u32 flags = bp->flags;
10861 u32 changes;
10862 int rc = 0;
10863 bool re_init = false;
10864 bool update_tpa = false;
10865
10866 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
10867 if (features & NETIF_F_GRO_HW)
10868 flags |= BNXT_FLAG_GRO;
10869 else if (features & NETIF_F_LRO)
10870 flags |= BNXT_FLAG_LRO;
10871
10872 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
10873 flags &= ~BNXT_FLAG_TPA;
10874
10875 if (features & BNXT_HW_FEATURE_VLAN_ALL_RX)
10876 flags |= BNXT_FLAG_STRIP_VLAN;
10877
10878 if (features & NETIF_F_NTUPLE)
10879 flags |= BNXT_FLAG_RFS;
10880
10881 changes = flags ^ bp->flags;
10882 if (changes & BNXT_FLAG_TPA) {
10883 update_tpa = true;
10884 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
10885 (flags & BNXT_FLAG_TPA) == 0 ||
10886 (bp->flags & BNXT_FLAG_CHIP_P5))
10887 re_init = true;
10888 }
10889
10890 if (changes & ~BNXT_FLAG_TPA)
10891 re_init = true;
10892
10893 if (flags != bp->flags) {
10894 u32 old_flags = bp->flags;
10895
10896 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
10897 bp->flags = flags;
10898 if (update_tpa)
10899 bnxt_set_ring_params(bp);
10900 return rc;
10901 }
10902
10903 if (re_init) {
10904 bnxt_close_nic(bp, false, false);
10905 bp->flags = flags;
10906 if (update_tpa)
10907 bnxt_set_ring_params(bp);
10908
10909 return bnxt_open_nic(bp, false, false);
10910 }
10911 if (update_tpa) {
10912 bp->flags = flags;
10913 rc = bnxt_set_tpa(bp,
10914 (flags & BNXT_FLAG_TPA) ?
10915 true : false);
10916 if (rc)
10917 bp->flags = old_flags;
10918 }
10919 }
10920 return rc;
10921 }
10922
10923 static bool bnxt_exthdr_check(struct bnxt *bp, struct sk_buff *skb, int nw_off,
10924 u8 **nextp)
10925 {
10926 struct ipv6hdr *ip6h = (struct ipv6hdr *)(skb->data + nw_off);
10927 int hdr_count = 0;
10928 u8 *nexthdr;
10929 int start;
10930
10931 /* Check that there are at most 2 IPv6 extension headers, no
10932 * fragment header, and each is <= 64 bytes.
10933 */
10934 start = nw_off + sizeof(*ip6h);
10935 nexthdr = &ip6h->nexthdr;
10936 while (ipv6_ext_hdr(*nexthdr)) {
10937 struct ipv6_opt_hdr *hp;
10938 int hdrlen;
10939
10940 if (hdr_count >= 3 || *nexthdr == NEXTHDR_NONE ||
10941 *nexthdr == NEXTHDR_FRAGMENT)
10942 return false;
10943 hp = __skb_header_pointer(NULL, start, sizeof(*hp), skb->data,
10944 skb_headlen(skb), NULL);
10945 if (!hp)
10946 return false;
10947 if (*nexthdr == NEXTHDR_AUTH)
10948 hdrlen = ipv6_authlen(hp);
10949 else
10950 hdrlen = ipv6_optlen(hp);
10951
10952 if (hdrlen > 64)
10953 return false;
10954 nexthdr = &hp->nexthdr;
10955 start += hdrlen;
10956 hdr_count++;
10957 }
10958 if (nextp) {
10959 /* Caller will check inner protocol */
10960 if (skb->encapsulation) {
10961 *nextp = nexthdr;
10962 return true;
10963 }
10964 *nextp = NULL;
10965 }
10966 /* Only support TCP/UDP for non-tunneled ipv6 and inner ipv6 */
10967 return *nexthdr == IPPROTO_TCP || *nexthdr == IPPROTO_UDP;
10968 }
10969
10970 /* For UDP, we can only handle 1 Vxlan port and 1 Geneve port. */
10971 static bool bnxt_udp_tunl_check(struct bnxt *bp, struct sk_buff *skb)
10972 {
10973 struct udphdr *uh = udp_hdr(skb);
10974 __be16 udp_port = uh->dest;
10975
10976 if (udp_port != bp->vxlan_port && udp_port != bp->nge_port)
10977 return false;
10978 if (skb->inner_protocol_type == ENCAP_TYPE_ETHER) {
10979 struct ethhdr *eh = inner_eth_hdr(skb);
10980
10981 switch (eh->h_proto) {
10982 case htons(ETH_P_IP):
10983 return true;
10984 case htons(ETH_P_IPV6):
10985 return bnxt_exthdr_check(bp, skb,
10986 skb_inner_network_offset(skb),
10987 NULL);
10988 }
10989 }
10990 return false;
10991 }
10992
10993 static bool bnxt_tunl_check(struct bnxt *bp, struct sk_buff *skb, u8 l4_proto)
10994 {
10995 switch (l4_proto) {
10996 case IPPROTO_UDP:
10997 return bnxt_udp_tunl_check(bp, skb);
10998 case IPPROTO_IPIP:
10999 return true;
11000 case IPPROTO_GRE: {
11001 switch (skb->inner_protocol) {
11002 default:
11003 return false;
11004 case htons(ETH_P_IP):
11005 return true;
11006 case htons(ETH_P_IPV6):
11007 fallthrough;
11008 }
11009 }
11010 case IPPROTO_IPV6:
11011 /* Check ext headers of inner ipv6 */
11012 return bnxt_exthdr_check(bp, skb, skb_inner_network_offset(skb),
11013 NULL);
11014 }
11015 return false;
11016 }
11017
11018 static netdev_features_t bnxt_features_check(struct sk_buff *skb,
11019 struct net_device *dev,
11020 netdev_features_t features)
11021 {
11022 struct bnxt *bp = netdev_priv(dev);
11023 u8 *l4_proto;
11024
11025 features = vlan_features_check(skb, features);
11026 switch (vlan_get_protocol(skb)) {
11027 case htons(ETH_P_IP):
11028 if (!skb->encapsulation)
11029 return features;
11030 l4_proto = &ip_hdr(skb)->protocol;
11031 if (bnxt_tunl_check(bp, skb, *l4_proto))
11032 return features;
11033 break;
11034 case htons(ETH_P_IPV6):
11035 if (!bnxt_exthdr_check(bp, skb, skb_network_offset(skb),
11036 &l4_proto))
11037 break;
11038 if (!l4_proto || bnxt_tunl_check(bp, skb, *l4_proto))
11039 return features;
11040 break;
11041 }
11042 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
11043 }
11044
11045 int bnxt_dbg_hwrm_rd_reg(struct bnxt *bp, u32 reg_off, u16 num_words,
11046 u32 *reg_buf)
11047 {
11048 struct hwrm_dbg_read_direct_output *resp = bp->hwrm_cmd_resp_addr;
11049 struct hwrm_dbg_read_direct_input req = {0};
11050 __le32 *dbg_reg_buf;
11051 dma_addr_t mapping;
11052 int rc, i;
11053
11054 dbg_reg_buf = dma_alloc_coherent(&bp->pdev->dev, num_words * 4,
11055 &mapping, GFP_KERNEL);
11056 if (!dbg_reg_buf)
11057 return -ENOMEM;
11058 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_READ_DIRECT, -1, -1);
11059 req.host_dest_addr = cpu_to_le64(mapping);
11060 req.read_addr = cpu_to_le32(reg_off + CHIMP_REG_VIEW_ADDR);
11061 req.read_len32 = cpu_to_le32(num_words);
11062 mutex_lock(&bp->hwrm_cmd_lock);
11063 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
11064 if (rc || resp->error_code) {
11065 rc = -EIO;
11066 goto dbg_rd_reg_exit;
11067 }
11068 for (i = 0; i < num_words; i++)
11069 reg_buf[i] = le32_to_cpu(dbg_reg_buf[i]);
11070
11071 dbg_rd_reg_exit:
11072 mutex_unlock(&bp->hwrm_cmd_lock);
11073 dma_free_coherent(&bp->pdev->dev, num_words * 4, dbg_reg_buf, mapping);
11074 return rc;
11075 }
11076
11077 static int bnxt_dbg_hwrm_ring_info_get(struct bnxt *bp, u8 ring_type,
11078 u32 ring_id, u32 *prod, u32 *cons)
11079 {
11080 struct hwrm_dbg_ring_info_get_output *resp = bp->hwrm_cmd_resp_addr;
11081 struct hwrm_dbg_ring_info_get_input req = {0};
11082 int rc;
11083
11084 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_RING_INFO_GET, -1, -1);
11085 req.ring_type = ring_type;
11086 req.fw_ring_id = cpu_to_le32(ring_id);
11087 mutex_lock(&bp->hwrm_cmd_lock);
11088 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
11089 if (!rc) {
11090 *prod = le32_to_cpu(resp->producer_index);
11091 *cons = le32_to_cpu(resp->consumer_index);
11092 }
11093 mutex_unlock(&bp->hwrm_cmd_lock);
11094 return rc;
11095 }
11096
11097 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
11098 {
11099 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
11100 int i = bnapi->index;
11101
11102 if (!txr)
11103 return;
11104
11105 netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
11106 i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
11107 txr->tx_cons);
11108 }
11109
11110 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
11111 {
11112 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
11113 int i = bnapi->index;
11114
11115 if (!rxr)
11116 return;
11117
11118 netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
11119 i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
11120 rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
11121 rxr->rx_sw_agg_prod);
11122 }
11123
11124 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
11125 {
11126 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
11127 int i = bnapi->index;
11128
11129 netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
11130 i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
11131 }
11132
11133 static void bnxt_dbg_dump_states(struct bnxt *bp)
11134 {
11135 int i;
11136 struct bnxt_napi *bnapi;
11137
11138 for (i = 0; i < bp->cp_nr_rings; i++) {
11139 bnapi = bp->bnapi[i];
11140 if (netif_msg_drv(bp)) {
11141 bnxt_dump_tx_sw_state(bnapi);
11142 bnxt_dump_rx_sw_state(bnapi);
11143 bnxt_dump_cp_sw_state(bnapi);
11144 }
11145 }
11146 }
11147
11148 static int bnxt_hwrm_rx_ring_reset(struct bnxt *bp, int ring_nr)
11149 {
11150 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[ring_nr];
11151 struct hwrm_ring_reset_input req = {0};
11152 struct bnxt_napi *bnapi = rxr->bnapi;
11153 struct bnxt_cp_ring_info *cpr;
11154 u16 cp_ring_id;
11155
11156 cpr = &bnapi->cp_ring;
11157 cp_ring_id = cpr->cp_ring_struct.fw_ring_id;
11158 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_RESET, cp_ring_id, -1);
11159 req.ring_type = RING_RESET_REQ_RING_TYPE_RX_RING_GRP;
11160 req.ring_id = cpu_to_le16(bp->grp_info[bnapi->index].fw_grp_id);
11161 return hwrm_send_message_silent(bp, &req, sizeof(req),
11162 HWRM_CMD_TIMEOUT);
11163 }
11164
11165 static void bnxt_reset_task(struct bnxt *bp, bool silent)
11166 {
11167 if (!silent)
11168 bnxt_dbg_dump_states(bp);
11169 if (netif_running(bp->dev)) {
11170 int rc;
11171
11172 if (silent) {
11173 bnxt_close_nic(bp, false, false);
11174 bnxt_open_nic(bp, false, false);
11175 } else {
11176 bnxt_ulp_stop(bp);
11177 bnxt_close_nic(bp, true, false);
11178 rc = bnxt_open_nic(bp, true, false);
11179 bnxt_ulp_start(bp, rc);
11180 }
11181 }
11182 }
11183
11184 static void bnxt_tx_timeout(struct net_device *dev, unsigned int txqueue)
11185 {
11186 struct bnxt *bp = netdev_priv(dev);
11187
11188 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n");
11189 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
11190 bnxt_queue_sp_work(bp);
11191 }
11192
11193 static void bnxt_fw_health_check(struct bnxt *bp)
11194 {
11195 struct bnxt_fw_health *fw_health = bp->fw_health;
11196 u32 val;
11197
11198 if (!fw_health->enabled || test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
11199 return;
11200
11201 if (fw_health->tmr_counter) {
11202 fw_health->tmr_counter--;
11203 return;
11204 }
11205
11206 val = bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG);
11207 if (val == fw_health->last_fw_heartbeat)
11208 goto fw_reset;
11209
11210 fw_health->last_fw_heartbeat = val;
11211
11212 val = bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG);
11213 if (val != fw_health->last_fw_reset_cnt)
11214 goto fw_reset;
11215
11216 fw_health->tmr_counter = fw_health->tmr_multiplier;
11217 return;
11218
11219 fw_reset:
11220 set_bit(BNXT_FW_EXCEPTION_SP_EVENT, &bp->sp_event);
11221 bnxt_queue_sp_work(bp);
11222 }
11223
11224 static void bnxt_timer(struct timer_list *t)
11225 {
11226 struct bnxt *bp = from_timer(bp, t, timer);
11227 struct net_device *dev = bp->dev;
11228
11229 if (!netif_running(dev) || !test_bit(BNXT_STATE_OPEN, &bp->state))
11230 return;
11231
11232 if (atomic_read(&bp->intr_sem) != 0)
11233 goto bnxt_restart_timer;
11234
11235 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
11236 bnxt_fw_health_check(bp);
11237
11238 if (bp->link_info.link_up && bp->stats_coal_ticks) {
11239 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
11240 bnxt_queue_sp_work(bp);
11241 }
11242
11243 if (bnxt_tc_flower_enabled(bp)) {
11244 set_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event);
11245 bnxt_queue_sp_work(bp);
11246 }
11247
11248 #ifdef CONFIG_RFS_ACCEL
11249 if ((bp->flags & BNXT_FLAG_RFS) && bp->ntp_fltr_count) {
11250 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
11251 bnxt_queue_sp_work(bp);
11252 }
11253 #endif /*CONFIG_RFS_ACCEL*/
11254
11255 if (bp->link_info.phy_retry) {
11256 if (time_after(jiffies, bp->link_info.phy_retry_expires)) {
11257 bp->link_info.phy_retry = false;
11258 netdev_warn(bp->dev, "failed to update phy settings after maximum retries.\n");
11259 } else {
11260 set_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event);
11261 bnxt_queue_sp_work(bp);
11262 }
11263 }
11264
11265 if ((bp->flags & BNXT_FLAG_CHIP_P5) && !bp->chip_rev &&
11266 netif_carrier_ok(dev)) {
11267 set_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event);
11268 bnxt_queue_sp_work(bp);
11269 }
11270 bnxt_restart_timer:
11271 mod_timer(&bp->timer, jiffies + bp->current_interval);
11272 }
11273
11274 static void bnxt_rtnl_lock_sp(struct bnxt *bp)
11275 {
11276 /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK
11277 * set. If the device is being closed, bnxt_close() may be holding
11278 * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we
11279 * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
11280 */
11281 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
11282 rtnl_lock();
11283 }
11284
11285 static void bnxt_rtnl_unlock_sp(struct bnxt *bp)
11286 {
11287 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
11288 rtnl_unlock();
11289 }
11290
11291 /* Only called from bnxt_sp_task() */
11292 static void bnxt_reset(struct bnxt *bp, bool silent)
11293 {
11294 bnxt_rtnl_lock_sp(bp);
11295 if (test_bit(BNXT_STATE_OPEN, &bp->state))
11296 bnxt_reset_task(bp, silent);
11297 bnxt_rtnl_unlock_sp(bp);
11298 }
11299
11300 /* Only called from bnxt_sp_task() */
11301 static void bnxt_rx_ring_reset(struct bnxt *bp)
11302 {
11303 int i;
11304
11305 bnxt_rtnl_lock_sp(bp);
11306 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
11307 bnxt_rtnl_unlock_sp(bp);
11308 return;
11309 }
11310 /* Disable and flush TPA before resetting the RX ring */
11311 if (bp->flags & BNXT_FLAG_TPA)
11312 bnxt_set_tpa(bp, false);
11313 for (i = 0; i < bp->rx_nr_rings; i++) {
11314 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
11315 struct bnxt_cp_ring_info *cpr;
11316 int rc;
11317
11318 if (!rxr->bnapi->in_reset)
11319 continue;
11320
11321 rc = bnxt_hwrm_rx_ring_reset(bp, i);
11322 if (rc) {
11323 if (rc == -EINVAL || rc == -EOPNOTSUPP)
11324 netdev_info_once(bp->dev, "RX ring reset not supported by firmware, falling back to global reset\n");
11325 else
11326 netdev_warn(bp->dev, "RX ring reset failed, rc = %d, falling back to global reset\n",
11327 rc);
11328 bnxt_reset_task(bp, true);
11329 break;
11330 }
11331 bnxt_free_one_rx_ring_skbs(bp, i);
11332 rxr->rx_prod = 0;
11333 rxr->rx_agg_prod = 0;
11334 rxr->rx_sw_agg_prod = 0;
11335 rxr->rx_next_cons = 0;
11336 rxr->bnapi->in_reset = false;
11337 bnxt_alloc_one_rx_ring(bp, i);
11338 cpr = &rxr->bnapi->cp_ring;
11339 cpr->sw_stats.rx.rx_resets++;
11340 if (bp->flags & BNXT_FLAG_AGG_RINGS)
11341 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
11342 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
11343 }
11344 if (bp->flags & BNXT_FLAG_TPA)
11345 bnxt_set_tpa(bp, true);
11346 bnxt_rtnl_unlock_sp(bp);
11347 }
11348
11349 static void bnxt_fw_reset_close(struct bnxt *bp)
11350 {
11351 bnxt_ulp_stop(bp);
11352 /* When firmware is in fatal state, quiesce device and disable
11353 * bus master to prevent any potential bad DMAs before freeing
11354 * kernel memory.
11355 */
11356 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) {
11357 u16 val = 0;
11358
11359 pci_read_config_word(bp->pdev, PCI_SUBSYSTEM_ID, &val);
11360 if (val == 0xffff)
11361 bp->fw_reset_min_dsecs = 0;
11362 bnxt_tx_disable(bp);
11363 bnxt_disable_napi(bp);
11364 bnxt_disable_int_sync(bp);
11365 bnxt_free_irq(bp);
11366 bnxt_clear_int_mode(bp);
11367 pci_disable_device(bp->pdev);
11368 }
11369 bnxt_ptp_clear(bp);
11370 __bnxt_close_nic(bp, true, false);
11371 bnxt_vf_reps_free(bp);
11372 bnxt_clear_int_mode(bp);
11373 bnxt_hwrm_func_drv_unrgtr(bp);
11374 if (pci_is_enabled(bp->pdev))
11375 pci_disable_device(bp->pdev);
11376 bnxt_free_ctx_mem(bp);
11377 kfree(bp->ctx);
11378 bp->ctx = NULL;
11379 }
11380
11381 static bool is_bnxt_fw_ok(struct bnxt *bp)
11382 {
11383 struct bnxt_fw_health *fw_health = bp->fw_health;
11384 bool no_heartbeat = false, has_reset = false;
11385 u32 val;
11386
11387 val = bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG);
11388 if (val == fw_health->last_fw_heartbeat)
11389 no_heartbeat = true;
11390
11391 val = bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG);
11392 if (val != fw_health->last_fw_reset_cnt)
11393 has_reset = true;
11394
11395 if (!no_heartbeat && has_reset)
11396 return true;
11397
11398 return false;
11399 }
11400
11401 /* rtnl_lock is acquired before calling this function */
11402 static void bnxt_force_fw_reset(struct bnxt *bp)
11403 {
11404 struct bnxt_fw_health *fw_health = bp->fw_health;
11405 u32 wait_dsecs;
11406
11407 if (!test_bit(BNXT_STATE_OPEN, &bp->state) ||
11408 test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
11409 return;
11410
11411 set_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
11412 bnxt_fw_reset_close(bp);
11413 wait_dsecs = fw_health->master_func_wait_dsecs;
11414 if (fw_health->master) {
11415 if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU)
11416 wait_dsecs = 0;
11417 bp->fw_reset_state = BNXT_FW_RESET_STATE_RESET_FW;
11418 } else {
11419 bp->fw_reset_timestamp = jiffies + wait_dsecs * HZ / 10;
11420 wait_dsecs = fw_health->normal_func_wait_dsecs;
11421 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
11422 }
11423
11424 bp->fw_reset_min_dsecs = fw_health->post_reset_wait_dsecs;
11425 bp->fw_reset_max_dsecs = fw_health->post_reset_max_wait_dsecs;
11426 bnxt_queue_fw_reset_work(bp, wait_dsecs * HZ / 10);
11427 }
11428
11429 void bnxt_fw_exception(struct bnxt *bp)
11430 {
11431 netdev_warn(bp->dev, "Detected firmware fatal condition, initiating reset\n");
11432 set_bit(BNXT_STATE_FW_FATAL_COND, &bp->state);
11433 bnxt_rtnl_lock_sp(bp);
11434 bnxt_force_fw_reset(bp);
11435 bnxt_rtnl_unlock_sp(bp);
11436 }
11437
11438 /* Returns the number of registered VFs, or 1 if VF configuration is pending, or
11439 * < 0 on error.
11440 */
11441 static int bnxt_get_registered_vfs(struct bnxt *bp)
11442 {
11443 #ifdef CONFIG_BNXT_SRIOV
11444 int rc;
11445
11446 if (!BNXT_PF(bp))
11447 return 0;
11448
11449 rc = bnxt_hwrm_func_qcfg(bp);
11450 if (rc) {
11451 netdev_err(bp->dev, "func_qcfg cmd failed, rc = %d\n", rc);
11452 return rc;
11453 }
11454 if (bp->pf.registered_vfs)
11455 return bp->pf.registered_vfs;
11456 if (bp->sriov_cfg)
11457 return 1;
11458 #endif
11459 return 0;
11460 }
11461
11462 void bnxt_fw_reset(struct bnxt *bp)
11463 {
11464 bnxt_rtnl_lock_sp(bp);
11465 if (test_bit(BNXT_STATE_OPEN, &bp->state) &&
11466 !test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) {
11467 int n = 0, tmo;
11468
11469 set_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
11470 if (bp->pf.active_vfs &&
11471 !test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))
11472 n = bnxt_get_registered_vfs(bp);
11473 if (n < 0) {
11474 netdev_err(bp->dev, "Firmware reset aborted, rc = %d\n",
11475 n);
11476 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
11477 dev_close(bp->dev);
11478 goto fw_reset_exit;
11479 } else if (n > 0) {
11480 u16 vf_tmo_dsecs = n * 10;
11481
11482 if (bp->fw_reset_max_dsecs < vf_tmo_dsecs)
11483 bp->fw_reset_max_dsecs = vf_tmo_dsecs;
11484 bp->fw_reset_state =
11485 BNXT_FW_RESET_STATE_POLL_VF;
11486 bnxt_queue_fw_reset_work(bp, HZ / 10);
11487 goto fw_reset_exit;
11488 }
11489 bnxt_fw_reset_close(bp);
11490 if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) {
11491 bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW_DOWN;
11492 tmo = HZ / 10;
11493 } else {
11494 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
11495 tmo = bp->fw_reset_min_dsecs * HZ / 10;
11496 }
11497 bnxt_queue_fw_reset_work(bp, tmo);
11498 }
11499 fw_reset_exit:
11500 bnxt_rtnl_unlock_sp(bp);
11501 }
11502
11503 static void bnxt_chk_missed_irq(struct bnxt *bp)
11504 {
11505 int i;
11506
11507 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
11508 return;
11509
11510 for (i = 0; i < bp->cp_nr_rings; i++) {
11511 struct bnxt_napi *bnapi = bp->bnapi[i];
11512 struct bnxt_cp_ring_info *cpr;
11513 u32 fw_ring_id;
11514 int j;
11515
11516 if (!bnapi)
11517 continue;
11518
11519 cpr = &bnapi->cp_ring;
11520 for (j = 0; j < 2; j++) {
11521 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
11522 u32 val[2];
11523
11524 if (!cpr2 || cpr2->has_more_work ||
11525 !bnxt_has_work(bp, cpr2))
11526 continue;
11527
11528 if (cpr2->cp_raw_cons != cpr2->last_cp_raw_cons) {
11529 cpr2->last_cp_raw_cons = cpr2->cp_raw_cons;
11530 continue;
11531 }
11532 fw_ring_id = cpr2->cp_ring_struct.fw_ring_id;
11533 bnxt_dbg_hwrm_ring_info_get(bp,
11534 DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL,
11535 fw_ring_id, &val[0], &val[1]);
11536 cpr->sw_stats.cmn.missed_irqs++;
11537 }
11538 }
11539 }
11540
11541 static void bnxt_cfg_ntp_filters(struct bnxt *);
11542
11543 static void bnxt_init_ethtool_link_settings(struct bnxt *bp)
11544 {
11545 struct bnxt_link_info *link_info = &bp->link_info;
11546
11547 if (BNXT_AUTO_MODE(link_info->auto_mode)) {
11548 link_info->autoneg = BNXT_AUTONEG_SPEED;
11549 if (bp->hwrm_spec_code >= 0x10201) {
11550 if (link_info->auto_pause_setting &
11551 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
11552 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
11553 } else {
11554 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
11555 }
11556 link_info->advertising = link_info->auto_link_speeds;
11557 link_info->advertising_pam4 = link_info->auto_pam4_link_speeds;
11558 } else {
11559 link_info->req_link_speed = link_info->force_link_speed;
11560 link_info->req_signal_mode = BNXT_SIG_MODE_NRZ;
11561 if (link_info->force_pam4_link_speed) {
11562 link_info->req_link_speed =
11563 link_info->force_pam4_link_speed;
11564 link_info->req_signal_mode = BNXT_SIG_MODE_PAM4;
11565 }
11566 link_info->req_duplex = link_info->duplex_setting;
11567 }
11568 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
11569 link_info->req_flow_ctrl =
11570 link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
11571 else
11572 link_info->req_flow_ctrl = link_info->force_pause_setting;
11573 }
11574
11575 static void bnxt_fw_echo_reply(struct bnxt *bp)
11576 {
11577 struct bnxt_fw_health *fw_health = bp->fw_health;
11578 struct hwrm_func_echo_response_input req = {0};
11579
11580 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_ECHO_RESPONSE, -1, -1);
11581 req.event_data1 = cpu_to_le32(fw_health->echo_req_data1);
11582 req.event_data2 = cpu_to_le32(fw_health->echo_req_data2);
11583 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
11584 }
11585
11586 static void bnxt_sp_task(struct work_struct *work)
11587 {
11588 struct bnxt *bp = container_of(work, struct bnxt, sp_task);
11589
11590 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
11591 smp_mb__after_atomic();
11592 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
11593 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
11594 return;
11595 }
11596
11597 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
11598 bnxt_cfg_rx_mode(bp);
11599
11600 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
11601 bnxt_cfg_ntp_filters(bp);
11602 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
11603 bnxt_hwrm_exec_fwd_req(bp);
11604 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event)) {
11605 bnxt_hwrm_port_qstats(bp, 0);
11606 bnxt_hwrm_port_qstats_ext(bp, 0);
11607 bnxt_accumulate_all_stats(bp);
11608 }
11609
11610 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
11611 int rc;
11612
11613 mutex_lock(&bp->link_lock);
11614 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT,
11615 &bp->sp_event))
11616 bnxt_hwrm_phy_qcaps(bp);
11617
11618 rc = bnxt_update_link(bp, true);
11619 if (rc)
11620 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
11621 rc);
11622
11623 if (test_and_clear_bit(BNXT_LINK_CFG_CHANGE_SP_EVENT,
11624 &bp->sp_event))
11625 bnxt_init_ethtool_link_settings(bp);
11626 mutex_unlock(&bp->link_lock);
11627 }
11628 if (test_and_clear_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event)) {
11629 int rc;
11630
11631 mutex_lock(&bp->link_lock);
11632 rc = bnxt_update_phy_setting(bp);
11633 mutex_unlock(&bp->link_lock);
11634 if (rc) {
11635 netdev_warn(bp->dev, "update phy settings retry failed\n");
11636 } else {
11637 bp->link_info.phy_retry = false;
11638 netdev_info(bp->dev, "update phy settings retry succeeded\n");
11639 }
11640 }
11641 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) {
11642 mutex_lock(&bp->link_lock);
11643 bnxt_get_port_module_status(bp);
11644 mutex_unlock(&bp->link_lock);
11645 }
11646
11647 if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event))
11648 bnxt_tc_flow_stats_work(bp);
11649
11650 if (test_and_clear_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event))
11651 bnxt_chk_missed_irq(bp);
11652
11653 if (test_and_clear_bit(BNXT_FW_ECHO_REQUEST_SP_EVENT, &bp->sp_event))
11654 bnxt_fw_echo_reply(bp);
11655
11656 /* These functions below will clear BNXT_STATE_IN_SP_TASK. They
11657 * must be the last functions to be called before exiting.
11658 */
11659 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
11660 bnxt_reset(bp, false);
11661
11662 if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
11663 bnxt_reset(bp, true);
11664
11665 if (test_and_clear_bit(BNXT_RST_RING_SP_EVENT, &bp->sp_event))
11666 bnxt_rx_ring_reset(bp);
11667
11668 if (test_and_clear_bit(BNXT_FW_RESET_NOTIFY_SP_EVENT, &bp->sp_event))
11669 bnxt_devlink_health_report(bp, BNXT_FW_RESET_NOTIFY_SP_EVENT);
11670
11671 if (test_and_clear_bit(BNXT_FW_EXCEPTION_SP_EVENT, &bp->sp_event)) {
11672 if (!is_bnxt_fw_ok(bp))
11673 bnxt_devlink_health_report(bp,
11674 BNXT_FW_EXCEPTION_SP_EVENT);
11675 }
11676
11677 smp_mb__before_atomic();
11678 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
11679 }
11680
11681 /* Under rtnl_lock */
11682 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
11683 int tx_xdp)
11684 {
11685 int max_rx, max_tx, tx_sets = 1;
11686 int tx_rings_needed, stats;
11687 int rx_rings = rx;
11688 int cp, vnics, rc;
11689
11690 if (tcs)
11691 tx_sets = tcs;
11692
11693 rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh);
11694 if (rc)
11695 return rc;
11696
11697 if (max_rx < rx)
11698 return -ENOMEM;
11699
11700 tx_rings_needed = tx * tx_sets + tx_xdp;
11701 if (max_tx < tx_rings_needed)
11702 return -ENOMEM;
11703
11704 vnics = 1;
11705 if ((bp->flags & (BNXT_FLAG_RFS | BNXT_FLAG_CHIP_P5)) == BNXT_FLAG_RFS)
11706 vnics += rx_rings;
11707
11708 if (bp->flags & BNXT_FLAG_AGG_RINGS)
11709 rx_rings <<= 1;
11710 cp = sh ? max_t(int, tx_rings_needed, rx) : tx_rings_needed + rx;
11711 stats = cp;
11712 if (BNXT_NEW_RM(bp)) {
11713 cp += bnxt_get_ulp_msix_num(bp);
11714 stats += bnxt_get_ulp_stat_ctxs(bp);
11715 }
11716 return bnxt_hwrm_check_rings(bp, tx_rings_needed, rx_rings, rx, cp,
11717 stats, vnics);
11718 }
11719
11720 static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev)
11721 {
11722 if (bp->bar2) {
11723 pci_iounmap(pdev, bp->bar2);
11724 bp->bar2 = NULL;
11725 }
11726
11727 if (bp->bar1) {
11728 pci_iounmap(pdev, bp->bar1);
11729 bp->bar1 = NULL;
11730 }
11731
11732 if (bp->bar0) {
11733 pci_iounmap(pdev, bp->bar0);
11734 bp->bar0 = NULL;
11735 }
11736 }
11737
11738 static void bnxt_cleanup_pci(struct bnxt *bp)
11739 {
11740 bnxt_unmap_bars(bp, bp->pdev);
11741 pci_release_regions(bp->pdev);
11742 if (pci_is_enabled(bp->pdev))
11743 pci_disable_device(bp->pdev);
11744 }
11745
11746 static void bnxt_init_dflt_coal(struct bnxt *bp)
11747 {
11748 struct bnxt_coal *coal;
11749
11750 /* Tick values in micro seconds.
11751 * 1 coal_buf x bufs_per_record = 1 completion record.
11752 */
11753 coal = &bp->rx_coal;
11754 coal->coal_ticks = 10;
11755 coal->coal_bufs = 30;
11756 coal->coal_ticks_irq = 1;
11757 coal->coal_bufs_irq = 2;
11758 coal->idle_thresh = 50;
11759 coal->bufs_per_record = 2;
11760 coal->budget = 64; /* NAPI budget */
11761
11762 coal = &bp->tx_coal;
11763 coal->coal_ticks = 28;
11764 coal->coal_bufs = 30;
11765 coal->coal_ticks_irq = 2;
11766 coal->coal_bufs_irq = 2;
11767 coal->bufs_per_record = 1;
11768
11769 bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS;
11770 }
11771
11772 static int bnxt_fw_init_one_p1(struct bnxt *bp)
11773 {
11774 int rc;
11775
11776 bp->fw_cap = 0;
11777 rc = bnxt_hwrm_ver_get(bp);
11778 bnxt_try_map_fw_health_reg(bp);
11779 if (rc) {
11780 rc = bnxt_try_recover_fw(bp);
11781 if (rc)
11782 return rc;
11783 rc = bnxt_hwrm_ver_get(bp);
11784 if (rc)
11785 return rc;
11786 }
11787
11788 if (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL) {
11789 rc = bnxt_alloc_kong_hwrm_resources(bp);
11790 if (rc)
11791 bp->fw_cap &= ~BNXT_FW_CAP_KONG_MB_CHNL;
11792 }
11793
11794 if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) ||
11795 bp->hwrm_max_ext_req_len > BNXT_HWRM_MAX_REQ_LEN) {
11796 rc = bnxt_alloc_hwrm_short_cmd_req(bp);
11797 if (rc)
11798 return rc;
11799 }
11800 bnxt_nvm_cfg_ver_get(bp);
11801
11802 rc = bnxt_hwrm_func_reset(bp);
11803 if (rc)
11804 return -ENODEV;
11805
11806 bnxt_hwrm_fw_set_time(bp);
11807 return 0;
11808 }
11809
11810 static int bnxt_fw_init_one_p2(struct bnxt *bp)
11811 {
11812 int rc;
11813
11814 /* Get the MAX capabilities for this function */
11815 rc = bnxt_hwrm_func_qcaps(bp);
11816 if (rc) {
11817 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
11818 rc);
11819 return -ENODEV;
11820 }
11821
11822 rc = bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(bp);
11823 if (rc)
11824 netdev_warn(bp->dev, "hwrm query adv flow mgnt failure rc: %d\n",
11825 rc);
11826
11827 if (bnxt_alloc_fw_health(bp)) {
11828 netdev_warn(bp->dev, "no memory for firmware error recovery\n");
11829 } else {
11830 rc = bnxt_hwrm_error_recovery_qcfg(bp);
11831 if (rc)
11832 netdev_warn(bp->dev, "hwrm query error recovery failure rc: %d\n",
11833 rc);
11834 }
11835
11836 rc = bnxt_hwrm_func_drv_rgtr(bp, NULL, 0, false);
11837 if (rc)
11838 return -ENODEV;
11839
11840 bnxt_hwrm_func_qcfg(bp);
11841 bnxt_hwrm_vnic_qcaps(bp);
11842 bnxt_hwrm_port_led_qcaps(bp);
11843 bnxt_ethtool_init(bp);
11844 bnxt_dcb_init(bp);
11845 return 0;
11846 }
11847
11848 static void bnxt_set_dflt_rss_hash_type(struct bnxt *bp)
11849 {
11850 bp->flags &= ~BNXT_FLAG_UDP_RSS_CAP;
11851 bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 |
11852 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 |
11853 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |
11854 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
11855 if (BNXT_CHIP_P4_PLUS(bp) && bp->hwrm_spec_code >= 0x10501) {
11856 bp->flags |= BNXT_FLAG_UDP_RSS_CAP;
11857 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 |
11858 VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
11859 }
11860 }
11861
11862 static void bnxt_set_dflt_rfs(struct bnxt *bp)
11863 {
11864 struct net_device *dev = bp->dev;
11865
11866 dev->hw_features &= ~NETIF_F_NTUPLE;
11867 dev->features &= ~NETIF_F_NTUPLE;
11868 bp->flags &= ~BNXT_FLAG_RFS;
11869 if (bnxt_rfs_supported(bp)) {
11870 dev->hw_features |= NETIF_F_NTUPLE;
11871 if (bnxt_rfs_capable(bp)) {
11872 bp->flags |= BNXT_FLAG_RFS;
11873 dev->features |= NETIF_F_NTUPLE;
11874 }
11875 }
11876 }
11877
11878 static void bnxt_fw_init_one_p3(struct bnxt *bp)
11879 {
11880 struct pci_dev *pdev = bp->pdev;
11881
11882 bnxt_set_dflt_rss_hash_type(bp);
11883 bnxt_set_dflt_rfs(bp);
11884
11885 bnxt_get_wol_settings(bp);
11886 if (bp->flags & BNXT_FLAG_WOL_CAP)
11887 device_set_wakeup_enable(&pdev->dev, bp->wol);
11888 else
11889 device_set_wakeup_capable(&pdev->dev, false);
11890
11891 bnxt_hwrm_set_cache_line_size(bp, cache_line_size());
11892 bnxt_hwrm_coal_params_qcaps(bp);
11893 }
11894
11895 static int bnxt_probe_phy(struct bnxt *bp, bool fw_dflt);
11896
11897 static int bnxt_fw_init_one(struct bnxt *bp)
11898 {
11899 int rc;
11900
11901 rc = bnxt_fw_init_one_p1(bp);
11902 if (rc) {
11903 netdev_err(bp->dev, "Firmware init phase 1 failed\n");
11904 return rc;
11905 }
11906 rc = bnxt_fw_init_one_p2(bp);
11907 if (rc) {
11908 netdev_err(bp->dev, "Firmware init phase 2 failed\n");
11909 return rc;
11910 }
11911 rc = bnxt_probe_phy(bp, false);
11912 if (rc)
11913 return rc;
11914 rc = bnxt_approve_mac(bp, bp->dev->dev_addr, false);
11915 if (rc)
11916 return rc;
11917
11918 /* In case fw capabilities have changed, destroy the unneeded
11919 * reporters and create newly capable ones.
11920 */
11921 bnxt_dl_fw_reporters_destroy(bp, false);
11922 bnxt_dl_fw_reporters_create(bp);
11923 bnxt_fw_init_one_p3(bp);
11924 return 0;
11925 }
11926
11927 static void bnxt_fw_reset_writel(struct bnxt *bp, int reg_idx)
11928 {
11929 struct bnxt_fw_health *fw_health = bp->fw_health;
11930 u32 reg = fw_health->fw_reset_seq_regs[reg_idx];
11931 u32 val = fw_health->fw_reset_seq_vals[reg_idx];
11932 u32 reg_type, reg_off, delay_msecs;
11933
11934 delay_msecs = fw_health->fw_reset_seq_delay_msec[reg_idx];
11935 reg_type = BNXT_FW_HEALTH_REG_TYPE(reg);
11936 reg_off = BNXT_FW_HEALTH_REG_OFF(reg);
11937 switch (reg_type) {
11938 case BNXT_FW_HEALTH_REG_TYPE_CFG:
11939 pci_write_config_dword(bp->pdev, reg_off, val);
11940 break;
11941 case BNXT_FW_HEALTH_REG_TYPE_GRC:
11942 writel(reg_off & BNXT_GRC_BASE_MASK,
11943 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
11944 reg_off = (reg_off & BNXT_GRC_OFFSET_MASK) + 0x2000;
11945 fallthrough;
11946 case BNXT_FW_HEALTH_REG_TYPE_BAR0:
11947 writel(val, bp->bar0 + reg_off);
11948 break;
11949 case BNXT_FW_HEALTH_REG_TYPE_BAR1:
11950 writel(val, bp->bar1 + reg_off);
11951 break;
11952 }
11953 if (delay_msecs) {
11954 pci_read_config_dword(bp->pdev, 0, &val);
11955 msleep(delay_msecs);
11956 }
11957 }
11958
11959 static void bnxt_reset_all(struct bnxt *bp)
11960 {
11961 struct bnxt_fw_health *fw_health = bp->fw_health;
11962 int i, rc;
11963
11964 if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) {
11965 bnxt_fw_reset_via_optee(bp);
11966 bp->fw_reset_timestamp = jiffies;
11967 return;
11968 }
11969
11970 if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST) {
11971 for (i = 0; i < fw_health->fw_reset_seq_cnt; i++)
11972 bnxt_fw_reset_writel(bp, i);
11973 } else if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) {
11974 struct hwrm_fw_reset_input req = {0};
11975
11976 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_RESET, -1, -1);
11977 req.resp_addr = cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr);
11978 req.embedded_proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP;
11979 req.selfrst_status = FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP;
11980 req.flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL;
11981 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
11982 if (rc != -ENODEV)
11983 netdev_warn(bp->dev, "Unable to reset FW rc=%d\n", rc);
11984 }
11985 bp->fw_reset_timestamp = jiffies;
11986 }
11987
11988 static bool bnxt_fw_reset_timeout(struct bnxt *bp)
11989 {
11990 return time_after(jiffies, bp->fw_reset_timestamp +
11991 (bp->fw_reset_max_dsecs * HZ / 10));
11992 }
11993
11994 static void bnxt_fw_reset_abort(struct bnxt *bp, int rc)
11995 {
11996 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
11997 if (bp->fw_reset_state != BNXT_FW_RESET_STATE_POLL_VF) {
11998 bnxt_ulp_start(bp, rc);
11999 bnxt_dl_health_status_update(bp, false);
12000 }
12001 bp->fw_reset_state = 0;
12002 dev_close(bp->dev);
12003 }
12004
12005 static void bnxt_fw_reset_task(struct work_struct *work)
12006 {
12007 struct bnxt *bp = container_of(work, struct bnxt, fw_reset_task.work);
12008 int rc = 0;
12009
12010 if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) {
12011 netdev_err(bp->dev, "bnxt_fw_reset_task() called when not in fw reset mode!\n");
12012 return;
12013 }
12014
12015 switch (bp->fw_reset_state) {
12016 case BNXT_FW_RESET_STATE_POLL_VF: {
12017 int n = bnxt_get_registered_vfs(bp);
12018 int tmo;
12019
12020 if (n < 0) {
12021 netdev_err(bp->dev, "Firmware reset aborted, subsequent func_qcfg cmd failed, rc = %d, %d msecs since reset timestamp\n",
12022 n, jiffies_to_msecs(jiffies -
12023 bp->fw_reset_timestamp));
12024 goto fw_reset_abort;
12025 } else if (n > 0) {
12026 if (bnxt_fw_reset_timeout(bp)) {
12027 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
12028 bp->fw_reset_state = 0;
12029 netdev_err(bp->dev, "Firmware reset aborted, bnxt_get_registered_vfs() returns %d\n",
12030 n);
12031 return;
12032 }
12033 bnxt_queue_fw_reset_work(bp, HZ / 10);
12034 return;
12035 }
12036 bp->fw_reset_timestamp = jiffies;
12037 rtnl_lock();
12038 if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state)) {
12039 bnxt_fw_reset_abort(bp, rc);
12040 rtnl_unlock();
12041 return;
12042 }
12043 bnxt_fw_reset_close(bp);
12044 if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) {
12045 bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW_DOWN;
12046 tmo = HZ / 10;
12047 } else {
12048 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
12049 tmo = bp->fw_reset_min_dsecs * HZ / 10;
12050 }
12051 rtnl_unlock();
12052 bnxt_queue_fw_reset_work(bp, tmo);
12053 return;
12054 }
12055 case BNXT_FW_RESET_STATE_POLL_FW_DOWN: {
12056 u32 val;
12057
12058 val = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG);
12059 if (!(val & BNXT_FW_STATUS_SHUTDOWN) &&
12060 !bnxt_fw_reset_timeout(bp)) {
12061 bnxt_queue_fw_reset_work(bp, HZ / 5);
12062 return;
12063 }
12064
12065 if (!bp->fw_health->master) {
12066 u32 wait_dsecs = bp->fw_health->normal_func_wait_dsecs;
12067
12068 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
12069 bnxt_queue_fw_reset_work(bp, wait_dsecs * HZ / 10);
12070 return;
12071 }
12072 bp->fw_reset_state = BNXT_FW_RESET_STATE_RESET_FW;
12073 }
12074 fallthrough;
12075 case BNXT_FW_RESET_STATE_RESET_FW:
12076 bnxt_reset_all(bp);
12077 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
12078 bnxt_queue_fw_reset_work(bp, bp->fw_reset_min_dsecs * HZ / 10);
12079 return;
12080 case BNXT_FW_RESET_STATE_ENABLE_DEV:
12081 bnxt_inv_fw_health_reg(bp);
12082 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state) &&
12083 !bp->fw_reset_min_dsecs) {
12084 u16 val;
12085
12086 pci_read_config_word(bp->pdev, PCI_SUBSYSTEM_ID, &val);
12087 if (val == 0xffff) {
12088 if (bnxt_fw_reset_timeout(bp)) {
12089 netdev_err(bp->dev, "Firmware reset aborted, PCI config space invalid\n");
12090 rc = -ETIMEDOUT;
12091 goto fw_reset_abort;
12092 }
12093 bnxt_queue_fw_reset_work(bp, HZ / 1000);
12094 return;
12095 }
12096 }
12097 clear_bit(BNXT_STATE_FW_FATAL_COND, &bp->state);
12098 if (pci_enable_device(bp->pdev)) {
12099 netdev_err(bp->dev, "Cannot re-enable PCI device\n");
12100 rc = -ENODEV;
12101 goto fw_reset_abort;
12102 }
12103 pci_set_master(bp->pdev);
12104 bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW;
12105 fallthrough;
12106 case BNXT_FW_RESET_STATE_POLL_FW:
12107 bp->hwrm_cmd_timeout = SHORT_HWRM_CMD_TIMEOUT;
12108 rc = __bnxt_hwrm_ver_get(bp, true);
12109 if (rc) {
12110 if (bnxt_fw_reset_timeout(bp)) {
12111 netdev_err(bp->dev, "Firmware reset aborted\n");
12112 goto fw_reset_abort_status;
12113 }
12114 bnxt_queue_fw_reset_work(bp, HZ / 5);
12115 return;
12116 }
12117 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
12118 bp->fw_reset_state = BNXT_FW_RESET_STATE_OPENING;
12119 fallthrough;
12120 case BNXT_FW_RESET_STATE_OPENING:
12121 while (!rtnl_trylock()) {
12122 bnxt_queue_fw_reset_work(bp, HZ / 10);
12123 return;
12124 }
12125 rc = bnxt_open(bp->dev);
12126 if (rc) {
12127 netdev_err(bp->dev, "bnxt_open() failed during FW reset\n");
12128 bnxt_fw_reset_abort(bp, rc);
12129 rtnl_unlock();
12130 return;
12131 }
12132
12133 bp->fw_reset_state = 0;
12134 /* Make sure fw_reset_state is 0 before clearing the flag */
12135 smp_mb__before_atomic();
12136 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
12137 bnxt_ulp_start(bp, 0);
12138 bnxt_reenable_sriov(bp);
12139 bnxt_vf_reps_alloc(bp);
12140 bnxt_vf_reps_open(bp);
12141 bnxt_dl_health_recovery_done(bp);
12142 bnxt_dl_health_status_update(bp, true);
12143 rtnl_unlock();
12144 break;
12145 }
12146 return;
12147
12148 fw_reset_abort_status:
12149 if (bp->fw_health->status_reliable ||
12150 (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) {
12151 u32 sts = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG);
12152
12153 netdev_err(bp->dev, "fw_health_status 0x%x\n", sts);
12154 }
12155 fw_reset_abort:
12156 rtnl_lock();
12157 bnxt_fw_reset_abort(bp, rc);
12158 rtnl_unlock();
12159 }
12160
12161 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
12162 {
12163 int rc;
12164 struct bnxt *bp = netdev_priv(dev);
12165
12166 SET_NETDEV_DEV(dev, &pdev->dev);
12167
12168 /* enable device (incl. PCI PM wakeup), and bus-mastering */
12169 rc = pci_enable_device(pdev);
12170 if (rc) {
12171 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
12172 goto init_err;
12173 }
12174
12175 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
12176 dev_err(&pdev->dev,
12177 "Cannot find PCI device base address, aborting\n");
12178 rc = -ENODEV;
12179 goto init_err_disable;
12180 }
12181
12182 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
12183 if (rc) {
12184 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
12185 goto init_err_disable;
12186 }
12187
12188 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
12189 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
12190 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
12191 rc = -EIO;
12192 goto init_err_release;
12193 }
12194
12195 pci_set_master(pdev);
12196
12197 bp->dev = dev;
12198 bp->pdev = pdev;
12199
12200 /* Doorbell BAR bp->bar1 is mapped after bnxt_fw_init_one_p2()
12201 * determines the BAR size.
12202 */
12203 bp->bar0 = pci_ioremap_bar(pdev, 0);
12204 if (!bp->bar0) {
12205 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
12206 rc = -ENOMEM;
12207 goto init_err_release;
12208 }
12209
12210 bp->bar2 = pci_ioremap_bar(pdev, 4);
12211 if (!bp->bar2) {
12212 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
12213 rc = -ENOMEM;
12214 goto init_err_release;
12215 }
12216
12217 pci_enable_pcie_error_reporting(pdev);
12218
12219 INIT_WORK(&bp->sp_task, bnxt_sp_task);
12220 INIT_DELAYED_WORK(&bp->fw_reset_task, bnxt_fw_reset_task);
12221
12222 spin_lock_init(&bp->ntp_fltr_lock);
12223 #if BITS_PER_LONG == 32
12224 spin_lock_init(&bp->db_lock);
12225 #endif
12226
12227 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
12228 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
12229
12230 bnxt_init_dflt_coal(bp);
12231
12232 timer_setup(&bp->timer, bnxt_timer, 0);
12233 bp->current_interval = BNXT_TIMER_INTERVAL;
12234
12235 bp->vxlan_fw_dst_port_id = INVALID_HW_RING_ID;
12236 bp->nge_fw_dst_port_id = INVALID_HW_RING_ID;
12237
12238 clear_bit(BNXT_STATE_OPEN, &bp->state);
12239 return 0;
12240
12241 init_err_release:
12242 bnxt_unmap_bars(bp, pdev);
12243 pci_release_regions(pdev);
12244
12245 init_err_disable:
12246 pci_disable_device(pdev);
12247
12248 init_err:
12249 return rc;
12250 }
12251
12252 /* rtnl_lock held */
12253 static int bnxt_change_mac_addr(struct net_device *dev, void *p)
12254 {
12255 struct sockaddr *addr = p;
12256 struct bnxt *bp = netdev_priv(dev);
12257 int rc = 0;
12258
12259 if (!is_valid_ether_addr(addr->sa_data))
12260 return -EADDRNOTAVAIL;
12261
12262 if (ether_addr_equal(addr->sa_data, dev->dev_addr))
12263 return 0;
12264
12265 rc = bnxt_approve_mac(bp, addr->sa_data, true);
12266 if (rc)
12267 return rc;
12268
12269 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
12270 if (netif_running(dev)) {
12271 bnxt_close_nic(bp, false, false);
12272 rc = bnxt_open_nic(bp, false, false);
12273 }
12274
12275 return rc;
12276 }
12277
12278 /* rtnl_lock held */
12279 static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
12280 {
12281 struct bnxt *bp = netdev_priv(dev);
12282
12283 if (netif_running(dev))
12284 bnxt_close_nic(bp, true, false);
12285
12286 dev->mtu = new_mtu;
12287 bnxt_set_ring_params(bp);
12288
12289 if (netif_running(dev))
12290 return bnxt_open_nic(bp, true, false);
12291
12292 return 0;
12293 }
12294
12295 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc)
12296 {
12297 struct bnxt *bp = netdev_priv(dev);
12298 bool sh = false;
12299 int rc;
12300
12301 if (tc > bp->max_tc) {
12302 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n",
12303 tc, bp->max_tc);
12304 return -EINVAL;
12305 }
12306
12307 if (netdev_get_num_tc(dev) == tc)
12308 return 0;
12309
12310 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
12311 sh = true;
12312
12313 rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings,
12314 sh, tc, bp->tx_nr_rings_xdp);
12315 if (rc)
12316 return rc;
12317
12318 /* Needs to close the device and do hw resource re-allocations */
12319 if (netif_running(bp->dev))
12320 bnxt_close_nic(bp, true, false);
12321
12322 if (tc) {
12323 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
12324 netdev_set_num_tc(dev, tc);
12325 } else {
12326 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
12327 netdev_reset_tc(dev);
12328 }
12329 bp->tx_nr_rings += bp->tx_nr_rings_xdp;
12330 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
12331 bp->tx_nr_rings + bp->rx_nr_rings;
12332
12333 if (netif_running(bp->dev))
12334 return bnxt_open_nic(bp, true, false);
12335
12336 return 0;
12337 }
12338
12339 static int bnxt_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
12340 void *cb_priv)
12341 {
12342 struct bnxt *bp = cb_priv;
12343
12344 if (!bnxt_tc_flower_enabled(bp) ||
12345 !tc_cls_can_offload_and_chain0(bp->dev, type_data))
12346 return -EOPNOTSUPP;
12347
12348 switch (type) {
12349 case TC_SETUP_CLSFLOWER:
12350 return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, type_data);
12351 default:
12352 return -EOPNOTSUPP;
12353 }
12354 }
12355
12356 LIST_HEAD(bnxt_block_cb_list);
12357
12358 static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type,
12359 void *type_data)
12360 {
12361 struct bnxt *bp = netdev_priv(dev);
12362
12363 switch (type) {
12364 case TC_SETUP_BLOCK:
12365 return flow_block_cb_setup_simple(type_data,
12366 &bnxt_block_cb_list,
12367 bnxt_setup_tc_block_cb,
12368 bp, bp, true);
12369 case TC_SETUP_QDISC_MQPRIO: {
12370 struct tc_mqprio_qopt *mqprio = type_data;
12371
12372 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
12373
12374 return bnxt_setup_mq_tc(dev, mqprio->num_tc);
12375 }
12376 default:
12377 return -EOPNOTSUPP;
12378 }
12379 }
12380
12381 #ifdef CONFIG_RFS_ACCEL
12382 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
12383 struct bnxt_ntuple_filter *f2)
12384 {
12385 struct flow_keys *keys1 = &f1->fkeys;
12386 struct flow_keys *keys2 = &f2->fkeys;
12387
12388 if (keys1->basic.n_proto != keys2->basic.n_proto ||
12389 keys1->basic.ip_proto != keys2->basic.ip_proto)
12390 return false;
12391
12392 if (keys1->basic.n_proto == htons(ETH_P_IP)) {
12393 if (keys1->addrs.v4addrs.src != keys2->addrs.v4addrs.src ||
12394 keys1->addrs.v4addrs.dst != keys2->addrs.v4addrs.dst)
12395 return false;
12396 } else {
12397 if (memcmp(&keys1->addrs.v6addrs.src, &keys2->addrs.v6addrs.src,
12398 sizeof(keys1->addrs.v6addrs.src)) ||
12399 memcmp(&keys1->addrs.v6addrs.dst, &keys2->addrs.v6addrs.dst,
12400 sizeof(keys1->addrs.v6addrs.dst)))
12401 return false;
12402 }
12403
12404 if (keys1->ports.ports == keys2->ports.ports &&
12405 keys1->control.flags == keys2->control.flags &&
12406 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) &&
12407 ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr))
12408 return true;
12409
12410 return false;
12411 }
12412
12413 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
12414 u16 rxq_index, u32 flow_id)
12415 {
12416 struct bnxt *bp = netdev_priv(dev);
12417 struct bnxt_ntuple_filter *fltr, *new_fltr;
12418 struct flow_keys *fkeys;
12419 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
12420 int rc = 0, idx, bit_id, l2_idx = 0;
12421 struct hlist_head *head;
12422 u32 flags;
12423
12424 if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) {
12425 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
12426 int off = 0, j;
12427
12428 netif_addr_lock_bh(dev);
12429 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) {
12430 if (ether_addr_equal(eth->h_dest,
12431 vnic->uc_list + off)) {
12432 l2_idx = j + 1;
12433 break;
12434 }
12435 }
12436 netif_addr_unlock_bh(dev);
12437 if (!l2_idx)
12438 return -EINVAL;
12439 }
12440 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
12441 if (!new_fltr)
12442 return -ENOMEM;
12443
12444 fkeys = &new_fltr->fkeys;
12445 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
12446 rc = -EPROTONOSUPPORT;
12447 goto err_free;
12448 }
12449
12450 if ((fkeys->basic.n_proto != htons(ETH_P_IP) &&
12451 fkeys->basic.n_proto != htons(ETH_P_IPV6)) ||
12452 ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
12453 (fkeys->basic.ip_proto != IPPROTO_UDP))) {
12454 rc = -EPROTONOSUPPORT;
12455 goto err_free;
12456 }
12457 if (fkeys->basic.n_proto == htons(ETH_P_IPV6) &&
12458 bp->hwrm_spec_code < 0x10601) {
12459 rc = -EPROTONOSUPPORT;
12460 goto err_free;
12461 }
12462 flags = fkeys->control.flags;
12463 if (((flags & FLOW_DIS_ENCAPSULATION) &&
12464 bp->hwrm_spec_code < 0x10601) || (flags & FLOW_DIS_IS_FRAGMENT)) {
12465 rc = -EPROTONOSUPPORT;
12466 goto err_free;
12467 }
12468
12469 memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN);
12470 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
12471
12472 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
12473 head = &bp->ntp_fltr_hash_tbl[idx];
12474 rcu_read_lock();
12475 hlist_for_each_entry_rcu(fltr, head, hash) {
12476 if (bnxt_fltr_match(fltr, new_fltr)) {
12477 rcu_read_unlock();
12478 rc = 0;
12479 goto err_free;
12480 }
12481 }
12482 rcu_read_unlock();
12483
12484 spin_lock_bh(&bp->ntp_fltr_lock);
12485 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
12486 BNXT_NTP_FLTR_MAX_FLTR, 0);
12487 if (bit_id < 0) {
12488 spin_unlock_bh(&bp->ntp_fltr_lock);
12489 rc = -ENOMEM;
12490 goto err_free;
12491 }
12492
12493 new_fltr->sw_id = (u16)bit_id;
12494 new_fltr->flow_id = flow_id;
12495 new_fltr->l2_fltr_idx = l2_idx;
12496 new_fltr->rxq = rxq_index;
12497 hlist_add_head_rcu(&new_fltr->hash, head);
12498 bp->ntp_fltr_count++;
12499 spin_unlock_bh(&bp->ntp_fltr_lock);
12500
12501 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
12502 bnxt_queue_sp_work(bp);
12503
12504 return new_fltr->sw_id;
12505
12506 err_free:
12507 kfree(new_fltr);
12508 return rc;
12509 }
12510
12511 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
12512 {
12513 int i;
12514
12515 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
12516 struct hlist_head *head;
12517 struct hlist_node *tmp;
12518 struct bnxt_ntuple_filter *fltr;
12519 int rc;
12520
12521 head = &bp->ntp_fltr_hash_tbl[i];
12522 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
12523 bool del = false;
12524
12525 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
12526 if (rps_may_expire_flow(bp->dev, fltr->rxq,
12527 fltr->flow_id,
12528 fltr->sw_id)) {
12529 bnxt_hwrm_cfa_ntuple_filter_free(bp,
12530 fltr);
12531 del = true;
12532 }
12533 } else {
12534 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
12535 fltr);
12536 if (rc)
12537 del = true;
12538 else
12539 set_bit(BNXT_FLTR_VALID, &fltr->state);
12540 }
12541
12542 if (del) {
12543 spin_lock_bh(&bp->ntp_fltr_lock);
12544 hlist_del_rcu(&fltr->hash);
12545 bp->ntp_fltr_count--;
12546 spin_unlock_bh(&bp->ntp_fltr_lock);
12547 synchronize_rcu();
12548 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
12549 kfree(fltr);
12550 }
12551 }
12552 }
12553 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
12554 netdev_info(bp->dev, "Receive PF driver unload event!\n");
12555 }
12556
12557 #else
12558
12559 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
12560 {
12561 }
12562
12563 #endif /* CONFIG_RFS_ACCEL */
12564
12565 static int bnxt_udp_tunnel_sync(struct net_device *netdev, unsigned int table)
12566 {
12567 struct bnxt *bp = netdev_priv(netdev);
12568 struct udp_tunnel_info ti;
12569 unsigned int cmd;
12570
12571 udp_tunnel_nic_get_port(netdev, table, 0, &ti);
12572 if (ti.type == UDP_TUNNEL_TYPE_VXLAN) {
12573 bp->vxlan_port = ti.port;
12574 cmd = TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN;
12575 } else {
12576 bp->nge_port = ti.port;
12577 cmd = TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE;
12578 }
12579
12580 if (ti.port)
12581 return bnxt_hwrm_tunnel_dst_port_alloc(bp, ti.port, cmd);
12582
12583 return bnxt_hwrm_tunnel_dst_port_free(bp, cmd);
12584 }
12585
12586 static const struct udp_tunnel_nic_info bnxt_udp_tunnels = {
12587 .sync_table = bnxt_udp_tunnel_sync,
12588 .flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP |
12589 UDP_TUNNEL_NIC_INFO_OPEN_ONLY,
12590 .tables = {
12591 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, },
12592 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_GENEVE, },
12593 },
12594 };
12595
12596 static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
12597 struct net_device *dev, u32 filter_mask,
12598 int nlflags)
12599 {
12600 struct bnxt *bp = netdev_priv(dev);
12601
12602 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0,
12603 nlflags, filter_mask, NULL);
12604 }
12605
12606 static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
12607 u16 flags, struct netlink_ext_ack *extack)
12608 {
12609 struct bnxt *bp = netdev_priv(dev);
12610 struct nlattr *attr, *br_spec;
12611 int rem, rc = 0;
12612
12613 if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp))
12614 return -EOPNOTSUPP;
12615
12616 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
12617 if (!br_spec)
12618 return -EINVAL;
12619
12620 nla_for_each_nested(attr, br_spec, rem) {
12621 u16 mode;
12622
12623 if (nla_type(attr) != IFLA_BRIDGE_MODE)
12624 continue;
12625
12626 if (nla_len(attr) < sizeof(mode))
12627 return -EINVAL;
12628
12629 mode = nla_get_u16(attr);
12630 if (mode == bp->br_mode)
12631 break;
12632
12633 rc = bnxt_hwrm_set_br_mode(bp, mode);
12634 if (!rc)
12635 bp->br_mode = mode;
12636 break;
12637 }
12638 return rc;
12639 }
12640
12641 int bnxt_get_port_parent_id(struct net_device *dev,
12642 struct netdev_phys_item_id *ppid)
12643 {
12644 struct bnxt *bp = netdev_priv(dev);
12645
12646 if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV)
12647 return -EOPNOTSUPP;
12648
12649 /* The PF and it's VF-reps only support the switchdev framework */
12650 if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_DSN_VALID))
12651 return -EOPNOTSUPP;
12652
12653 ppid->id_len = sizeof(bp->dsn);
12654 memcpy(ppid->id, bp->dsn, ppid->id_len);
12655
12656 return 0;
12657 }
12658
12659 static struct devlink_port *bnxt_get_devlink_port(struct net_device *dev)
12660 {
12661 struct bnxt *bp = netdev_priv(dev);
12662
12663 return &bp->dl_port;
12664 }
12665
12666 static const struct net_device_ops bnxt_netdev_ops = {
12667 .ndo_open = bnxt_open,
12668 .ndo_start_xmit = bnxt_start_xmit,
12669 .ndo_stop = bnxt_close,
12670 .ndo_get_stats64 = bnxt_get_stats64,
12671 .ndo_set_rx_mode = bnxt_set_rx_mode,
12672 .ndo_do_ioctl = bnxt_ioctl,
12673 .ndo_validate_addr = eth_validate_addr,
12674 .ndo_set_mac_address = bnxt_change_mac_addr,
12675 .ndo_change_mtu = bnxt_change_mtu,
12676 .ndo_fix_features = bnxt_fix_features,
12677 .ndo_set_features = bnxt_set_features,
12678 .ndo_features_check = bnxt_features_check,
12679 .ndo_tx_timeout = bnxt_tx_timeout,
12680 #ifdef CONFIG_BNXT_SRIOV
12681 .ndo_get_vf_config = bnxt_get_vf_config,
12682 .ndo_set_vf_mac = bnxt_set_vf_mac,
12683 .ndo_set_vf_vlan = bnxt_set_vf_vlan,
12684 .ndo_set_vf_rate = bnxt_set_vf_bw,
12685 .ndo_set_vf_link_state = bnxt_set_vf_link_state,
12686 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk,
12687 .ndo_set_vf_trust = bnxt_set_vf_trust,
12688 #endif
12689 .ndo_setup_tc = bnxt_setup_tc,
12690 #ifdef CONFIG_RFS_ACCEL
12691 .ndo_rx_flow_steer = bnxt_rx_flow_steer,
12692 #endif
12693 .ndo_bpf = bnxt_xdp,
12694 .ndo_xdp_xmit = bnxt_xdp_xmit,
12695 .ndo_bridge_getlink = bnxt_bridge_getlink,
12696 .ndo_bridge_setlink = bnxt_bridge_setlink,
12697 .ndo_get_devlink_port = bnxt_get_devlink_port,
12698 };
12699
12700 static void bnxt_remove_one(struct pci_dev *pdev)
12701 {
12702 struct net_device *dev = pci_get_drvdata(pdev);
12703 struct bnxt *bp = netdev_priv(dev);
12704
12705 if (BNXT_PF(bp))
12706 bnxt_sriov_disable(bp);
12707
12708 if (BNXT_PF(bp))
12709 devlink_port_type_clear(&bp->dl_port);
12710
12711 pci_disable_pcie_error_reporting(pdev);
12712 unregister_netdev(dev);
12713 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
12714 /* Flush any pending tasks */
12715 cancel_work_sync(&bp->sp_task);
12716 cancel_delayed_work_sync(&bp->fw_reset_task);
12717 bp->sp_event = 0;
12718
12719 bnxt_dl_fw_reporters_destroy(bp, true);
12720 bnxt_dl_unregister(bp);
12721 bnxt_shutdown_tc(bp);
12722
12723 bnxt_clear_int_mode(bp);
12724 bnxt_hwrm_func_drv_unrgtr(bp);
12725 bnxt_free_hwrm_resources(bp);
12726 bnxt_free_hwrm_short_cmd_req(bp);
12727 bnxt_ethtool_free(bp);
12728 bnxt_dcb_free(bp);
12729 kfree(bp->edev);
12730 bp->edev = NULL;
12731 kfree(bp->ptp_cfg);
12732 bp->ptp_cfg = NULL;
12733 kfree(bp->fw_health);
12734 bp->fw_health = NULL;
12735 bnxt_cleanup_pci(bp);
12736 bnxt_free_ctx_mem(bp);
12737 kfree(bp->ctx);
12738 bp->ctx = NULL;
12739 kfree(bp->rss_indir_tbl);
12740 bp->rss_indir_tbl = NULL;
12741 bnxt_free_port_stats(bp);
12742 free_netdev(dev);
12743 }
12744
12745 static int bnxt_probe_phy(struct bnxt *bp, bool fw_dflt)
12746 {
12747 int rc = 0;
12748 struct bnxt_link_info *link_info = &bp->link_info;
12749
12750 bp->phy_flags = 0;
12751 rc = bnxt_hwrm_phy_qcaps(bp);
12752 if (rc) {
12753 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
12754 rc);
12755 return rc;
12756 }
12757 if (bp->phy_flags & BNXT_PHY_FL_NO_FCS)
12758 bp->dev->priv_flags |= IFF_SUPP_NOFCS;
12759 else
12760 bp->dev->priv_flags &= ~IFF_SUPP_NOFCS;
12761 if (!fw_dflt)
12762 return 0;
12763
12764 rc = bnxt_update_link(bp, false);
12765 if (rc) {
12766 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
12767 rc);
12768 return rc;
12769 }
12770
12771 /* Older firmware does not have supported_auto_speeds, so assume
12772 * that all supported speeds can be autonegotiated.
12773 */
12774 if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
12775 link_info->support_auto_speeds = link_info->support_speeds;
12776
12777 bnxt_init_ethtool_link_settings(bp);
12778 return 0;
12779 }
12780
12781 static int bnxt_get_max_irq(struct pci_dev *pdev)
12782 {
12783 u16 ctrl;
12784
12785 if (!pdev->msix_cap)
12786 return 1;
12787
12788 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
12789 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
12790 }
12791
12792 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
12793 int *max_cp)
12794 {
12795 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
12796 int max_ring_grps = 0, max_irq;
12797
12798 *max_tx = hw_resc->max_tx_rings;
12799 *max_rx = hw_resc->max_rx_rings;
12800 *max_cp = bnxt_get_max_func_cp_rings_for_en(bp);
12801 max_irq = min_t(int, bnxt_get_max_func_irqs(bp) -
12802 bnxt_get_ulp_msix_num(bp),
12803 hw_resc->max_stat_ctxs - bnxt_get_ulp_stat_ctxs(bp));
12804 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
12805 *max_cp = min_t(int, *max_cp, max_irq);
12806 max_ring_grps = hw_resc->max_hw_ring_grps;
12807 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) {
12808 *max_cp -= 1;
12809 *max_rx -= 2;
12810 }
12811 if (bp->flags & BNXT_FLAG_AGG_RINGS)
12812 *max_rx >>= 1;
12813 if (bp->flags & BNXT_FLAG_CHIP_P5) {
12814 bnxt_trim_rings(bp, max_rx, max_tx, *max_cp, false);
12815 /* On P5 chips, max_cp output param should be available NQs */
12816 *max_cp = max_irq;
12817 }
12818 *max_rx = min_t(int, *max_rx, max_ring_grps);
12819 }
12820
12821 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
12822 {
12823 int rx, tx, cp;
12824
12825 _bnxt_get_max_rings(bp, &rx, &tx, &cp);
12826 *max_rx = rx;
12827 *max_tx = tx;
12828 if (!rx || !tx || !cp)
12829 return -ENOMEM;
12830
12831 return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
12832 }
12833
12834 static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx,
12835 bool shared)
12836 {
12837 int rc;
12838
12839 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
12840 if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) {
12841 /* Not enough rings, try disabling agg rings. */
12842 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
12843 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
12844 if (rc) {
12845 /* set BNXT_FLAG_AGG_RINGS back for consistency */
12846 bp->flags |= BNXT_FLAG_AGG_RINGS;
12847 return rc;
12848 }
12849 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
12850 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
12851 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
12852 bnxt_set_ring_params(bp);
12853 }
12854
12855 if (bp->flags & BNXT_FLAG_ROCE_CAP) {
12856 int max_cp, max_stat, max_irq;
12857
12858 /* Reserve minimum resources for RoCE */
12859 max_cp = bnxt_get_max_func_cp_rings(bp);
12860 max_stat = bnxt_get_max_func_stat_ctxs(bp);
12861 max_irq = bnxt_get_max_func_irqs(bp);
12862 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS ||
12863 max_irq <= BNXT_MIN_ROCE_CP_RINGS ||
12864 max_stat <= BNXT_MIN_ROCE_STAT_CTXS)
12865 return 0;
12866
12867 max_cp -= BNXT_MIN_ROCE_CP_RINGS;
12868 max_irq -= BNXT_MIN_ROCE_CP_RINGS;
12869 max_stat -= BNXT_MIN_ROCE_STAT_CTXS;
12870 max_cp = min_t(int, max_cp, max_irq);
12871 max_cp = min_t(int, max_cp, max_stat);
12872 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared);
12873 if (rc)
12874 rc = 0;
12875 }
12876 return rc;
12877 }
12878
12879 /* In initial default shared ring setting, each shared ring must have a
12880 * RX/TX ring pair.
12881 */
12882 static void bnxt_trim_dflt_sh_rings(struct bnxt *bp)
12883 {
12884 bp->cp_nr_rings = min_t(int, bp->tx_nr_rings_per_tc, bp->rx_nr_rings);
12885 bp->rx_nr_rings = bp->cp_nr_rings;
12886 bp->tx_nr_rings_per_tc = bp->cp_nr_rings;
12887 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
12888 }
12889
12890 static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh)
12891 {
12892 int dflt_rings, max_rx_rings, max_tx_rings, rc;
12893
12894 if (!bnxt_can_reserve_rings(bp))
12895 return 0;
12896
12897 if (sh)
12898 bp->flags |= BNXT_FLAG_SHARED_RINGS;
12899 dflt_rings = is_kdump_kernel() ? 1 : netif_get_num_default_rss_queues();
12900 /* Reduce default rings on multi-port cards so that total default
12901 * rings do not exceed CPU count.
12902 */
12903 if (bp->port_count > 1) {
12904 int max_rings =
12905 max_t(int, num_online_cpus() / bp->port_count, 1);
12906
12907 dflt_rings = min_t(int, dflt_rings, max_rings);
12908 }
12909 rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh);
12910 if (rc)
12911 return rc;
12912 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
12913 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
12914 if (sh)
12915 bnxt_trim_dflt_sh_rings(bp);
12916 else
12917 bp->cp_nr_rings = bp->tx_nr_rings_per_tc + bp->rx_nr_rings;
12918 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
12919
12920 rc = __bnxt_reserve_rings(bp);
12921 if (rc)
12922 netdev_warn(bp->dev, "Unable to reserve tx rings\n");
12923 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
12924 if (sh)
12925 bnxt_trim_dflt_sh_rings(bp);
12926
12927 /* Rings may have been trimmed, re-reserve the trimmed rings. */
12928 if (bnxt_need_reserve_rings(bp)) {
12929 rc = __bnxt_reserve_rings(bp);
12930 if (rc)
12931 netdev_warn(bp->dev, "2nd rings reservation failed.\n");
12932 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
12933 }
12934 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
12935 bp->rx_nr_rings++;
12936 bp->cp_nr_rings++;
12937 }
12938 if (rc) {
12939 bp->tx_nr_rings = 0;
12940 bp->rx_nr_rings = 0;
12941 }
12942 return rc;
12943 }
12944
12945 static int bnxt_init_dflt_ring_mode(struct bnxt *bp)
12946 {
12947 int rc;
12948
12949 if (bp->tx_nr_rings)
12950 return 0;
12951
12952 bnxt_ulp_irq_stop(bp);
12953 bnxt_clear_int_mode(bp);
12954 rc = bnxt_set_dflt_rings(bp, true);
12955 if (rc) {
12956 netdev_err(bp->dev, "Not enough rings available.\n");
12957 goto init_dflt_ring_err;
12958 }
12959 rc = bnxt_init_int_mode(bp);
12960 if (rc)
12961 goto init_dflt_ring_err;
12962
12963 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
12964 if (bnxt_rfs_supported(bp) && bnxt_rfs_capable(bp)) {
12965 bp->flags |= BNXT_FLAG_RFS;
12966 bp->dev->features |= NETIF_F_NTUPLE;
12967 }
12968 init_dflt_ring_err:
12969 bnxt_ulp_irq_restart(bp, rc);
12970 return rc;
12971 }
12972
12973 int bnxt_restore_pf_fw_resources(struct bnxt *bp)
12974 {
12975 int rc;
12976
12977 ASSERT_RTNL();
12978 bnxt_hwrm_func_qcaps(bp);
12979
12980 if (netif_running(bp->dev))
12981 __bnxt_close_nic(bp, true, false);
12982
12983 bnxt_ulp_irq_stop(bp);
12984 bnxt_clear_int_mode(bp);
12985 rc = bnxt_init_int_mode(bp);
12986 bnxt_ulp_irq_restart(bp, rc);
12987
12988 if (netif_running(bp->dev)) {
12989 if (rc)
12990 dev_close(bp->dev);
12991 else
12992 rc = bnxt_open_nic(bp, true, false);
12993 }
12994
12995 return rc;
12996 }
12997
12998 static int bnxt_init_mac_addr(struct bnxt *bp)
12999 {
13000 int rc = 0;
13001
13002 if (BNXT_PF(bp)) {
13003 memcpy(bp->dev->dev_addr, bp->pf.mac_addr, ETH_ALEN);
13004 } else {
13005 #ifdef CONFIG_BNXT_SRIOV
13006 struct bnxt_vf_info *vf = &bp->vf;
13007 bool strict_approval = true;
13008
13009 if (is_valid_ether_addr(vf->mac_addr)) {
13010 /* overwrite netdev dev_addr with admin VF MAC */
13011 memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
13012 /* Older PF driver or firmware may not approve this
13013 * correctly.
13014 */
13015 strict_approval = false;
13016 } else {
13017 eth_hw_addr_random(bp->dev);
13018 }
13019 rc = bnxt_approve_mac(bp, bp->dev->dev_addr, strict_approval);
13020 #endif
13021 }
13022 return rc;
13023 }
13024
13025 #define BNXT_VPD_LEN 512
13026 static void bnxt_vpd_read_info(struct bnxt *bp)
13027 {
13028 struct pci_dev *pdev = bp->pdev;
13029 int i, len, pos, ro_size, size;
13030 ssize_t vpd_size;
13031 u8 *vpd_data;
13032
13033 vpd_data = kmalloc(BNXT_VPD_LEN, GFP_KERNEL);
13034 if (!vpd_data)
13035 return;
13036
13037 vpd_size = pci_read_vpd(pdev, 0, BNXT_VPD_LEN, vpd_data);
13038 if (vpd_size <= 0) {
13039 netdev_err(bp->dev, "Unable to read VPD\n");
13040 goto exit;
13041 }
13042
13043 i = pci_vpd_find_tag(vpd_data, vpd_size, PCI_VPD_LRDT_RO_DATA);
13044 if (i < 0) {
13045 netdev_err(bp->dev, "VPD READ-Only not found\n");
13046 goto exit;
13047 }
13048
13049 ro_size = pci_vpd_lrdt_size(&vpd_data[i]);
13050 i += PCI_VPD_LRDT_TAG_SIZE;
13051 if (i + ro_size > vpd_size)
13052 goto exit;
13053
13054 pos = pci_vpd_find_info_keyword(vpd_data, i, ro_size,
13055 PCI_VPD_RO_KEYWORD_PARTNO);
13056 if (pos < 0)
13057 goto read_sn;
13058
13059 len = pci_vpd_info_field_size(&vpd_data[pos]);
13060 pos += PCI_VPD_INFO_FLD_HDR_SIZE;
13061 if (len + pos > vpd_size)
13062 goto read_sn;
13063
13064 size = min(len, BNXT_VPD_FLD_LEN - 1);
13065 memcpy(bp->board_partno, &vpd_data[pos], size);
13066
13067 read_sn:
13068 pos = pci_vpd_find_info_keyword(vpd_data, i, ro_size,
13069 PCI_VPD_RO_KEYWORD_SERIALNO);
13070 if (pos < 0)
13071 goto exit;
13072
13073 len = pci_vpd_info_field_size(&vpd_data[pos]);
13074 pos += PCI_VPD_INFO_FLD_HDR_SIZE;
13075 if (len + pos > vpd_size)
13076 goto exit;
13077
13078 size = min(len, BNXT_VPD_FLD_LEN - 1);
13079 memcpy(bp->board_serialno, &vpd_data[pos], size);
13080 exit:
13081 kfree(vpd_data);
13082 }
13083
13084 static int bnxt_pcie_dsn_get(struct bnxt *bp, u8 dsn[])
13085 {
13086 struct pci_dev *pdev = bp->pdev;
13087 u64 qword;
13088
13089 qword = pci_get_dsn(pdev);
13090 if (!qword) {
13091 netdev_info(bp->dev, "Unable to read adapter's DSN\n");
13092 return -EOPNOTSUPP;
13093 }
13094
13095 put_unaligned_le64(qword, dsn);
13096
13097 bp->flags |= BNXT_FLAG_DSN_VALID;
13098 return 0;
13099 }
13100
13101 static int bnxt_map_db_bar(struct bnxt *bp)
13102 {
13103 if (!bp->db_size)
13104 return -ENODEV;
13105 bp->bar1 = pci_iomap(bp->pdev, 2, bp->db_size);
13106 if (!bp->bar1)
13107 return -ENOMEM;
13108 return 0;
13109 }
13110
13111 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
13112 {
13113 struct net_device *dev;
13114 struct bnxt *bp;
13115 int rc, max_irqs;
13116
13117 if (pci_is_bridge(pdev))
13118 return -ENODEV;
13119
13120 /* Clear any pending DMA transactions from crash kernel
13121 * while loading driver in capture kernel.
13122 */
13123 if (is_kdump_kernel()) {
13124 pci_clear_master(pdev);
13125 pcie_flr(pdev);
13126 }
13127
13128 max_irqs = bnxt_get_max_irq(pdev);
13129 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
13130 if (!dev)
13131 return -ENOMEM;
13132
13133 bp = netdev_priv(dev);
13134 bp->msg_enable = BNXT_DEF_MSG_ENABLE;
13135 bnxt_set_max_func_irqs(bp, max_irqs);
13136
13137 if (bnxt_vf_pciid(ent->driver_data))
13138 bp->flags |= BNXT_FLAG_VF;
13139
13140 if (pdev->msix_cap)
13141 bp->flags |= BNXT_FLAG_MSIX_CAP;
13142
13143 rc = bnxt_init_board(pdev, dev);
13144 if (rc < 0)
13145 goto init_err_free;
13146
13147 dev->netdev_ops = &bnxt_netdev_ops;
13148 dev->watchdog_timeo = BNXT_TX_TIMEOUT;
13149 dev->ethtool_ops = &bnxt_ethtool_ops;
13150 pci_set_drvdata(pdev, dev);
13151
13152 rc = bnxt_alloc_hwrm_resources(bp);
13153 if (rc)
13154 goto init_err_pci_clean;
13155
13156 mutex_init(&bp->hwrm_cmd_lock);
13157 mutex_init(&bp->link_lock);
13158
13159 rc = bnxt_fw_init_one_p1(bp);
13160 if (rc)
13161 goto init_err_pci_clean;
13162
13163 if (BNXT_PF(bp))
13164 bnxt_vpd_read_info(bp);
13165
13166 if (BNXT_CHIP_P5(bp)) {
13167 bp->flags |= BNXT_FLAG_CHIP_P5;
13168 if (BNXT_CHIP_SR2(bp))
13169 bp->flags |= BNXT_FLAG_CHIP_SR2;
13170 }
13171
13172 rc = bnxt_alloc_rss_indir_tbl(bp);
13173 if (rc)
13174 goto init_err_pci_clean;
13175
13176 rc = bnxt_fw_init_one_p2(bp);
13177 if (rc)
13178 goto init_err_pci_clean;
13179
13180 rc = bnxt_map_db_bar(bp);
13181 if (rc) {
13182 dev_err(&pdev->dev, "Cannot map doorbell BAR rc = %d, aborting\n",
13183 rc);
13184 goto init_err_pci_clean;
13185 }
13186
13187 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
13188 NETIF_F_TSO | NETIF_F_TSO6 |
13189 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
13190 NETIF_F_GSO_IPXIP4 |
13191 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
13192 NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
13193 NETIF_F_RXCSUM | NETIF_F_GRO;
13194
13195 if (BNXT_SUPPORTS_TPA(bp))
13196 dev->hw_features |= NETIF_F_LRO;
13197
13198 dev->hw_enc_features =
13199 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
13200 NETIF_F_TSO | NETIF_F_TSO6 |
13201 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
13202 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
13203 NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;
13204 dev->udp_tunnel_nic_info = &bnxt_udp_tunnels;
13205
13206 dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
13207 NETIF_F_GSO_GRE_CSUM;
13208 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
13209 if (bp->fw_cap & BNXT_FW_CAP_VLAN_RX_STRIP)
13210 dev->hw_features |= BNXT_HW_FEATURE_VLAN_ALL_RX;
13211 if (bp->fw_cap & BNXT_FW_CAP_VLAN_TX_INSERT)
13212 dev->hw_features |= BNXT_HW_FEATURE_VLAN_ALL_TX;
13213 if (BNXT_SUPPORTS_TPA(bp))
13214 dev->hw_features |= NETIF_F_GRO_HW;
13215 dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
13216 if (dev->features & NETIF_F_GRO_HW)
13217 dev->features &= ~NETIF_F_LRO;
13218 dev->priv_flags |= IFF_UNICAST_FLT;
13219
13220 #ifdef CONFIG_BNXT_SRIOV
13221 init_waitqueue_head(&bp->sriov_cfg_wait);
13222 mutex_init(&bp->sriov_lock);
13223 #endif
13224 if (BNXT_SUPPORTS_TPA(bp)) {
13225 bp->gro_func = bnxt_gro_func_5730x;
13226 if (BNXT_CHIP_P4(bp))
13227 bp->gro_func = bnxt_gro_func_5731x;
13228 else if (BNXT_CHIP_P5(bp))
13229 bp->gro_func = bnxt_gro_func_5750x;
13230 }
13231 if (!BNXT_CHIP_P4_PLUS(bp))
13232 bp->flags |= BNXT_FLAG_DOUBLE_DB;
13233
13234 rc = bnxt_init_mac_addr(bp);
13235 if (rc) {
13236 dev_err(&pdev->dev, "Unable to initialize mac address.\n");
13237 rc = -EADDRNOTAVAIL;
13238 goto init_err_pci_clean;
13239 }
13240
13241 if (BNXT_PF(bp)) {
13242 /* Read the adapter's DSN to use as the eswitch switch_id */
13243 rc = bnxt_pcie_dsn_get(bp, bp->dsn);
13244 }
13245
13246 /* MTU range: 60 - FW defined max */
13247 dev->min_mtu = ETH_ZLEN;
13248 dev->max_mtu = bp->max_mtu;
13249
13250 rc = bnxt_probe_phy(bp, true);
13251 if (rc)
13252 goto init_err_pci_clean;
13253
13254 bnxt_set_rx_skb_mode(bp, false);
13255 bnxt_set_tpa_flags(bp);
13256 bnxt_set_ring_params(bp);
13257 rc = bnxt_set_dflt_rings(bp, true);
13258 if (rc) {
13259 netdev_err(bp->dev, "Not enough rings available.\n");
13260 rc = -ENOMEM;
13261 goto init_err_pci_clean;
13262 }
13263
13264 bnxt_fw_init_one_p3(bp);
13265
13266 if (dev->hw_features & BNXT_HW_FEATURE_VLAN_ALL_RX)
13267 bp->flags |= BNXT_FLAG_STRIP_VLAN;
13268
13269 rc = bnxt_init_int_mode(bp);
13270 if (rc)
13271 goto init_err_pci_clean;
13272
13273 /* No TC has been set yet and rings may have been trimmed due to
13274 * limited MSIX, so we re-initialize the TX rings per TC.
13275 */
13276 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
13277
13278 if (BNXT_PF(bp)) {
13279 if (!bnxt_pf_wq) {
13280 bnxt_pf_wq =
13281 create_singlethread_workqueue("bnxt_pf_wq");
13282 if (!bnxt_pf_wq) {
13283 dev_err(&pdev->dev, "Unable to create workqueue.\n");
13284 rc = -ENOMEM;
13285 goto init_err_pci_clean;
13286 }
13287 }
13288 rc = bnxt_init_tc(bp);
13289 if (rc)
13290 netdev_err(dev, "Failed to initialize TC flower offload, err = %d.\n",
13291 rc);
13292 }
13293
13294 bnxt_inv_fw_health_reg(bp);
13295 bnxt_dl_register(bp);
13296
13297 rc = register_netdev(dev);
13298 if (rc)
13299 goto init_err_cleanup;
13300
13301 if (BNXT_PF(bp))
13302 devlink_port_type_eth_set(&bp->dl_port, bp->dev);
13303 bnxt_dl_fw_reporters_create(bp);
13304
13305 netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
13306 board_info[ent->driver_data].name,
13307 (long)pci_resource_start(pdev, 0), dev->dev_addr);
13308 pcie_print_link_status(pdev);
13309
13310 pci_save_state(pdev);
13311 return 0;
13312
13313 init_err_cleanup:
13314 bnxt_dl_unregister(bp);
13315 bnxt_shutdown_tc(bp);
13316 bnxt_clear_int_mode(bp);
13317
13318 init_err_pci_clean:
13319 bnxt_hwrm_func_drv_unrgtr(bp);
13320 bnxt_free_hwrm_short_cmd_req(bp);
13321 bnxt_free_hwrm_resources(bp);
13322 bnxt_ethtool_free(bp);
13323 kfree(bp->ptp_cfg);
13324 bp->ptp_cfg = NULL;
13325 kfree(bp->fw_health);
13326 bp->fw_health = NULL;
13327 bnxt_cleanup_pci(bp);
13328 bnxt_free_ctx_mem(bp);
13329 kfree(bp->ctx);
13330 bp->ctx = NULL;
13331 kfree(bp->rss_indir_tbl);
13332 bp->rss_indir_tbl = NULL;
13333
13334 init_err_free:
13335 free_netdev(dev);
13336 return rc;
13337 }
13338
13339 static void bnxt_shutdown(struct pci_dev *pdev)
13340 {
13341 struct net_device *dev = pci_get_drvdata(pdev);
13342 struct bnxt *bp;
13343
13344 if (!dev)
13345 return;
13346
13347 rtnl_lock();
13348 bp = netdev_priv(dev);
13349 if (!bp)
13350 goto shutdown_exit;
13351
13352 if (netif_running(dev))
13353 dev_close(dev);
13354
13355 bnxt_ulp_shutdown(bp);
13356 bnxt_clear_int_mode(bp);
13357 pci_disable_device(pdev);
13358
13359 if (system_state == SYSTEM_POWER_OFF) {
13360 pci_wake_from_d3(pdev, bp->wol);
13361 pci_set_power_state(pdev, PCI_D3hot);
13362 }
13363
13364 shutdown_exit:
13365 rtnl_unlock();
13366 }
13367
13368 #ifdef CONFIG_PM_SLEEP
13369 static int bnxt_suspend(struct device *device)
13370 {
13371 struct net_device *dev = dev_get_drvdata(device);
13372 struct bnxt *bp = netdev_priv(dev);
13373 int rc = 0;
13374
13375 rtnl_lock();
13376 bnxt_ulp_stop(bp);
13377 if (netif_running(dev)) {
13378 netif_device_detach(dev);
13379 rc = bnxt_close(dev);
13380 }
13381 bnxt_hwrm_func_drv_unrgtr(bp);
13382 pci_disable_device(bp->pdev);
13383 bnxt_free_ctx_mem(bp);
13384 kfree(bp->ctx);
13385 bp->ctx = NULL;
13386 rtnl_unlock();
13387 return rc;
13388 }
13389
13390 static int bnxt_resume(struct device *device)
13391 {
13392 struct net_device *dev = dev_get_drvdata(device);
13393 struct bnxt *bp = netdev_priv(dev);
13394 int rc = 0;
13395
13396 rtnl_lock();
13397 rc = pci_enable_device(bp->pdev);
13398 if (rc) {
13399 netdev_err(dev, "Cannot re-enable PCI device during resume, err = %d\n",
13400 rc);
13401 goto resume_exit;
13402 }
13403 pci_set_master(bp->pdev);
13404 if (bnxt_hwrm_ver_get(bp)) {
13405 rc = -ENODEV;
13406 goto resume_exit;
13407 }
13408 rc = bnxt_hwrm_func_reset(bp);
13409 if (rc) {
13410 rc = -EBUSY;
13411 goto resume_exit;
13412 }
13413
13414 rc = bnxt_hwrm_func_qcaps(bp);
13415 if (rc)
13416 goto resume_exit;
13417
13418 if (bnxt_hwrm_func_drv_rgtr(bp, NULL, 0, false)) {
13419 rc = -ENODEV;
13420 goto resume_exit;
13421 }
13422
13423 bnxt_get_wol_settings(bp);
13424 if (netif_running(dev)) {
13425 rc = bnxt_open(dev);
13426 if (!rc)
13427 netif_device_attach(dev);
13428 }
13429
13430 resume_exit:
13431 bnxt_ulp_start(bp, rc);
13432 if (!rc)
13433 bnxt_reenable_sriov(bp);
13434 rtnl_unlock();
13435 return rc;
13436 }
13437
13438 static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume);
13439 #define BNXT_PM_OPS (&bnxt_pm_ops)
13440
13441 #else
13442
13443 #define BNXT_PM_OPS NULL
13444
13445 #endif /* CONFIG_PM_SLEEP */
13446
13447 /**
13448 * bnxt_io_error_detected - called when PCI error is detected
13449 * @pdev: Pointer to PCI device
13450 * @state: The current pci connection state
13451 *
13452 * This function is called after a PCI bus error affecting
13453 * this device has been detected.
13454 */
13455 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
13456 pci_channel_state_t state)
13457 {
13458 struct net_device *netdev = pci_get_drvdata(pdev);
13459 struct bnxt *bp = netdev_priv(netdev);
13460
13461 netdev_info(netdev, "PCI I/O error detected\n");
13462
13463 rtnl_lock();
13464 netif_device_detach(netdev);
13465
13466 bnxt_ulp_stop(bp);
13467
13468 if (state == pci_channel_io_perm_failure) {
13469 rtnl_unlock();
13470 return PCI_ERS_RESULT_DISCONNECT;
13471 }
13472
13473 if (state == pci_channel_io_frozen)
13474 set_bit(BNXT_STATE_PCI_CHANNEL_IO_FROZEN, &bp->state);
13475
13476 if (netif_running(netdev))
13477 bnxt_close(netdev);
13478
13479 if (pci_is_enabled(pdev))
13480 pci_disable_device(pdev);
13481 bnxt_free_ctx_mem(bp);
13482 kfree(bp->ctx);
13483 bp->ctx = NULL;
13484 rtnl_unlock();
13485
13486 /* Request a slot slot reset. */
13487 return PCI_ERS_RESULT_NEED_RESET;
13488 }
13489
13490 /**
13491 * bnxt_io_slot_reset - called after the pci bus has been reset.
13492 * @pdev: Pointer to PCI device
13493 *
13494 * Restart the card from scratch, as if from a cold-boot.
13495 * At this point, the card has exprienced a hard reset,
13496 * followed by fixups by BIOS, and has its config space
13497 * set up identically to what it was at cold boot.
13498 */
13499 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
13500 {
13501 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
13502 struct net_device *netdev = pci_get_drvdata(pdev);
13503 struct bnxt *bp = netdev_priv(netdev);
13504 int err = 0, off;
13505
13506 netdev_info(bp->dev, "PCI Slot Reset\n");
13507
13508 rtnl_lock();
13509
13510 if (pci_enable_device(pdev)) {
13511 dev_err(&pdev->dev,
13512 "Cannot re-enable PCI device after reset.\n");
13513 } else {
13514 pci_set_master(pdev);
13515 /* Upon fatal error, our device internal logic that latches to
13516 * BAR value is getting reset and will restore only upon
13517 * rewritting the BARs.
13518 *
13519 * As pci_restore_state() does not re-write the BARs if the
13520 * value is same as saved value earlier, driver needs to
13521 * write the BARs to 0 to force restore, in case of fatal error.
13522 */
13523 if (test_and_clear_bit(BNXT_STATE_PCI_CHANNEL_IO_FROZEN,
13524 &bp->state)) {
13525 for (off = PCI_BASE_ADDRESS_0;
13526 off <= PCI_BASE_ADDRESS_5; off += 4)
13527 pci_write_config_dword(bp->pdev, off, 0);
13528 }
13529 pci_restore_state(pdev);
13530 pci_save_state(pdev);
13531
13532 err = bnxt_hwrm_func_reset(bp);
13533 if (!err)
13534 result = PCI_ERS_RESULT_RECOVERED;
13535 }
13536
13537 rtnl_unlock();
13538
13539 return result;
13540 }
13541
13542 /**
13543 * bnxt_io_resume - called when traffic can start flowing again.
13544 * @pdev: Pointer to PCI device
13545 *
13546 * This callback is called when the error recovery driver tells
13547 * us that its OK to resume normal operation.
13548 */
13549 static void bnxt_io_resume(struct pci_dev *pdev)
13550 {
13551 struct net_device *netdev = pci_get_drvdata(pdev);
13552 struct bnxt *bp = netdev_priv(netdev);
13553 int err;
13554
13555 netdev_info(bp->dev, "PCI Slot Resume\n");
13556 rtnl_lock();
13557
13558 err = bnxt_hwrm_func_qcaps(bp);
13559 if (!err && netif_running(netdev))
13560 err = bnxt_open(netdev);
13561
13562 bnxt_ulp_start(bp, err);
13563 if (!err) {
13564 bnxt_reenable_sriov(bp);
13565 netif_device_attach(netdev);
13566 }
13567
13568 rtnl_unlock();
13569 }
13570
13571 static const struct pci_error_handlers bnxt_err_handler = {
13572 .error_detected = bnxt_io_error_detected,
13573 .slot_reset = bnxt_io_slot_reset,
13574 .resume = bnxt_io_resume
13575 };
13576
13577 static struct pci_driver bnxt_pci_driver = {
13578 .name = DRV_MODULE_NAME,
13579 .id_table = bnxt_pci_tbl,
13580 .probe = bnxt_init_one,
13581 .remove = bnxt_remove_one,
13582 .shutdown = bnxt_shutdown,
13583 .driver.pm = BNXT_PM_OPS,
13584 .err_handler = &bnxt_err_handler,
13585 #if defined(CONFIG_BNXT_SRIOV)
13586 .sriov_configure = bnxt_sriov_configure,
13587 #endif
13588 };
13589
13590 static int __init bnxt_init(void)
13591 {
13592 bnxt_debug_init();
13593 return pci_register_driver(&bnxt_pci_driver);
13594 }
13595
13596 static void __exit bnxt_exit(void)
13597 {
13598 pci_unregister_driver(&bnxt_pci_driver);
13599 if (bnxt_pf_wq)
13600 destroy_workqueue(bnxt_pf_wq);
13601 bnxt_debug_exit();
13602 }
13603
13604 module_init(bnxt_init);
13605 module_exit(bnxt_exit);
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