1 /* Broadcom NetXtreme-C/E network driver.
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2018 Broadcom Limited
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
11 #include <linux/module.h>
13 #include <linux/stringify.h>
14 #include <linux/kernel.h>
15 #include <linux/timer.h>
16 #include <linux/errno.h>
17 #include <linux/ioport.h>
18 #include <linux/slab.h>
19 #include <linux/vmalloc.h>
20 #include <linux/interrupt.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
23 #include <linux/etherdevice.h>
24 #include <linux/skbuff.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/bitops.h>
28 #include <linux/irq.h>
29 #include <linux/delay.h>
30 #include <asm/byteorder.h>
32 #include <linux/time.h>
33 #include <linux/mii.h>
35 #include <linux/if_vlan.h>
36 #include <linux/if_bridge.h>
37 #include <linux/rtc.h>
38 #include <linux/bpf.h>
42 #include <net/checksum.h>
43 #include <net/ip6_checksum.h>
44 #include <net/udp_tunnel.h>
45 #include <linux/workqueue.h>
46 #include <linux/prefetch.h>
47 #include <linux/cache.h>
48 #include <linux/log2.h>
49 #include <linux/aer.h>
50 #include <linux/bitmap.h>
51 #include <linux/cpu_rmap.h>
52 #include <linux/cpumask.h>
53 #include <net/pkt_cls.h>
58 #include "bnxt_sriov.h"
59 #include "bnxt_ethtool.h"
64 #include "bnxt_devlink.h"
66 #define BNXT_TX_TIMEOUT (5 * HZ)
68 static const char version
[] =
69 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME
" v" DRV_MODULE_VERSION
"\n";
71 MODULE_LICENSE("GPL");
72 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
73 MODULE_VERSION(DRV_MODULE_VERSION
);
75 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
76 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
77 #define BNXT_RX_COPY_THRESH 256
79 #define BNXT_TX_PUSH_THRESH 164
119 /* indexed by enum above */
120 static const struct {
123 [BCM57301
] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
124 [BCM57302
] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
125 [BCM57304
] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
126 [BCM57417_NPAR
] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
127 [BCM58700
] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
128 [BCM57311
] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
129 [BCM57312
] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
130 [BCM57402
] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
131 [BCM57404
] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
132 [BCM57406
] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
133 [BCM57402_NPAR
] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
134 [BCM57407
] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
135 [BCM57412
] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
136 [BCM57414
] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
137 [BCM57416
] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
138 [BCM57417
] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
139 [BCM57412_NPAR
] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
140 [BCM57314
] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
141 [BCM57417_SFP
] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
142 [BCM57416_SFP
] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
143 [BCM57404_NPAR
] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
144 [BCM57406_NPAR
] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
145 [BCM57407_SFP
] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
146 [BCM57407_NPAR
] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
147 [BCM57414_NPAR
] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
148 [BCM57416_NPAR
] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
149 [BCM57452
] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" },
150 [BCM57454
] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
151 [BCM5745x_NPAR
] = { "Broadcom BCM5745x NetXtreme-E Ethernet Partition" },
152 [BCM58802
] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" },
153 [BCM58804
] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
154 [BCM58808
] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
155 [NETXTREME_E_VF
] = { "Broadcom NetXtreme-E Ethernet Virtual Function" },
156 [NETXTREME_C_VF
] = { "Broadcom NetXtreme-C Ethernet Virtual Function" },
157 [NETXTREME_S_VF
] = { "Broadcom NetXtreme-S Ethernet Virtual Function" },
160 static const struct pci_device_id bnxt_pci_tbl
[] = {
161 { PCI_VDEVICE(BROADCOM
, 0x1604), .driver_data
= BCM5745x_NPAR
},
162 { PCI_VDEVICE(BROADCOM
, 0x1605), .driver_data
= BCM5745x_NPAR
},
163 { PCI_VDEVICE(BROADCOM
, 0x1614), .driver_data
= BCM57454
},
164 { PCI_VDEVICE(BROADCOM
, 0x16c0), .driver_data
= BCM57417_NPAR
},
165 { PCI_VDEVICE(BROADCOM
, 0x16c8), .driver_data
= BCM57301
},
166 { PCI_VDEVICE(BROADCOM
, 0x16c9), .driver_data
= BCM57302
},
167 { PCI_VDEVICE(BROADCOM
, 0x16ca), .driver_data
= BCM57304
},
168 { PCI_VDEVICE(BROADCOM
, 0x16cc), .driver_data
= BCM57417_NPAR
},
169 { PCI_VDEVICE(BROADCOM
, 0x16cd), .driver_data
= BCM58700
},
170 { PCI_VDEVICE(BROADCOM
, 0x16ce), .driver_data
= BCM57311
},
171 { PCI_VDEVICE(BROADCOM
, 0x16cf), .driver_data
= BCM57312
},
172 { PCI_VDEVICE(BROADCOM
, 0x16d0), .driver_data
= BCM57402
},
173 { PCI_VDEVICE(BROADCOM
, 0x16d1), .driver_data
= BCM57404
},
174 { PCI_VDEVICE(BROADCOM
, 0x16d2), .driver_data
= BCM57406
},
175 { PCI_VDEVICE(BROADCOM
, 0x16d4), .driver_data
= BCM57402_NPAR
},
176 { PCI_VDEVICE(BROADCOM
, 0x16d5), .driver_data
= BCM57407
},
177 { PCI_VDEVICE(BROADCOM
, 0x16d6), .driver_data
= BCM57412
},
178 { PCI_VDEVICE(BROADCOM
, 0x16d7), .driver_data
= BCM57414
},
179 { PCI_VDEVICE(BROADCOM
, 0x16d8), .driver_data
= BCM57416
},
180 { PCI_VDEVICE(BROADCOM
, 0x16d9), .driver_data
= BCM57417
},
181 { PCI_VDEVICE(BROADCOM
, 0x16de), .driver_data
= BCM57412_NPAR
},
182 { PCI_VDEVICE(BROADCOM
, 0x16df), .driver_data
= BCM57314
},
183 { PCI_VDEVICE(BROADCOM
, 0x16e2), .driver_data
= BCM57417_SFP
},
184 { PCI_VDEVICE(BROADCOM
, 0x16e3), .driver_data
= BCM57416_SFP
},
185 { PCI_VDEVICE(BROADCOM
, 0x16e7), .driver_data
= BCM57404_NPAR
},
186 { PCI_VDEVICE(BROADCOM
, 0x16e8), .driver_data
= BCM57406_NPAR
},
187 { PCI_VDEVICE(BROADCOM
, 0x16e9), .driver_data
= BCM57407_SFP
},
188 { PCI_VDEVICE(BROADCOM
, 0x16ea), .driver_data
= BCM57407_NPAR
},
189 { PCI_VDEVICE(BROADCOM
, 0x16eb), .driver_data
= BCM57412_NPAR
},
190 { PCI_VDEVICE(BROADCOM
, 0x16ec), .driver_data
= BCM57414_NPAR
},
191 { PCI_VDEVICE(BROADCOM
, 0x16ed), .driver_data
= BCM57414_NPAR
},
192 { PCI_VDEVICE(BROADCOM
, 0x16ee), .driver_data
= BCM57416_NPAR
},
193 { PCI_VDEVICE(BROADCOM
, 0x16ef), .driver_data
= BCM57416_NPAR
},
194 { PCI_VDEVICE(BROADCOM
, 0x16f0), .driver_data
= BCM58808
},
195 { PCI_VDEVICE(BROADCOM
, 0x16f1), .driver_data
= BCM57452
},
196 { PCI_VDEVICE(BROADCOM
, 0xd802), .driver_data
= BCM58802
},
197 { PCI_VDEVICE(BROADCOM
, 0xd804), .driver_data
= BCM58804
},
198 #ifdef CONFIG_BNXT_SRIOV
199 { PCI_VDEVICE(BROADCOM
, 0x1606), .driver_data
= NETXTREME_E_VF
},
200 { PCI_VDEVICE(BROADCOM
, 0x1609), .driver_data
= NETXTREME_E_VF
},
201 { PCI_VDEVICE(BROADCOM
, 0x16c1), .driver_data
= NETXTREME_E_VF
},
202 { PCI_VDEVICE(BROADCOM
, 0x16cb), .driver_data
= NETXTREME_C_VF
},
203 { PCI_VDEVICE(BROADCOM
, 0x16d3), .driver_data
= NETXTREME_E_VF
},
204 { PCI_VDEVICE(BROADCOM
, 0x16dc), .driver_data
= NETXTREME_E_VF
},
205 { PCI_VDEVICE(BROADCOM
, 0x16e1), .driver_data
= NETXTREME_C_VF
},
206 { PCI_VDEVICE(BROADCOM
, 0x16e5), .driver_data
= NETXTREME_C_VF
},
207 { PCI_VDEVICE(BROADCOM
, 0xd800), .driver_data
= NETXTREME_S_VF
},
212 MODULE_DEVICE_TABLE(pci
, bnxt_pci_tbl
);
214 static const u16 bnxt_vf_req_snif
[] = {
218 HWRM_CFA_L2_FILTER_ALLOC
,
221 static const u16 bnxt_async_events_arr
[] = {
222 ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE
,
223 ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD
,
224 ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED
,
225 ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE
,
226 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE
,
229 static struct workqueue_struct
*bnxt_pf_wq
;
231 static bool bnxt_vf_pciid(enum board_idx idx
)
233 return (idx
== NETXTREME_C_VF
|| idx
== NETXTREME_E_VF
||
234 idx
== NETXTREME_S_VF
);
237 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
238 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
239 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
241 #define BNXT_CP_DB_REARM(db, raw_cons) \
242 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
244 #define BNXT_CP_DB(db, raw_cons) \
245 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
247 #define BNXT_CP_DB_IRQ_DIS(db) \
248 writel(DB_CP_IRQ_DIS_FLAGS, db)
250 const u16 bnxt_lhint_arr
[] = {
251 TX_BD_FLAGS_LHINT_512_AND_SMALLER
,
252 TX_BD_FLAGS_LHINT_512_TO_1023
,
253 TX_BD_FLAGS_LHINT_1024_TO_2047
,
254 TX_BD_FLAGS_LHINT_1024_TO_2047
,
255 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
256 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
257 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
258 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
259 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
260 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
261 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
262 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
263 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
264 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
265 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
266 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
267 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
268 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
269 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
272 static u16
bnxt_xmit_get_cfa_action(struct sk_buff
*skb
)
274 struct metadata_dst
*md_dst
= skb_metadata_dst(skb
);
276 if (!md_dst
|| md_dst
->type
!= METADATA_HW_PORT_MUX
)
279 return md_dst
->u
.port_info
.port_id
;
282 static netdev_tx_t
bnxt_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
284 struct bnxt
*bp
= netdev_priv(dev
);
286 struct tx_bd_ext
*txbd1
;
287 struct netdev_queue
*txq
;
290 unsigned int length
, pad
= 0;
291 u32 len
, free_size
, vlan_tag_flags
, cfa_action
, flags
;
293 struct pci_dev
*pdev
= bp
->pdev
;
294 struct bnxt_tx_ring_info
*txr
;
295 struct bnxt_sw_tx_bd
*tx_buf
;
297 i
= skb_get_queue_mapping(skb
);
298 if (unlikely(i
>= bp
->tx_nr_rings
)) {
299 dev_kfree_skb_any(skb
);
303 txq
= netdev_get_tx_queue(dev
, i
);
304 txr
= &bp
->tx_ring
[bp
->tx_ring_map
[i
]];
307 free_size
= bnxt_tx_avail(bp
, txr
);
308 if (unlikely(free_size
< skb_shinfo(skb
)->nr_frags
+ 2)) {
309 netif_tx_stop_queue(txq
);
310 return NETDEV_TX_BUSY
;
314 len
= skb_headlen(skb
);
315 last_frag
= skb_shinfo(skb
)->nr_frags
;
317 txbd
= &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
319 txbd
->tx_bd_opaque
= prod
;
321 tx_buf
= &txr
->tx_buf_ring
[prod
];
323 tx_buf
->nr_frags
= last_frag
;
326 cfa_action
= bnxt_xmit_get_cfa_action(skb
);
327 if (skb_vlan_tag_present(skb
)) {
328 vlan_tag_flags
= TX_BD_CFA_META_KEY_VLAN
|
329 skb_vlan_tag_get(skb
);
330 /* Currently supports 8021Q, 8021AD vlan offloads
331 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
333 if (skb
->vlan_proto
== htons(ETH_P_8021Q
))
334 vlan_tag_flags
|= 1 << TX_BD_CFA_META_TPID_SHIFT
;
337 if (free_size
== bp
->tx_ring_size
&& length
<= bp
->tx_push_thresh
) {
338 struct tx_push_buffer
*tx_push_buf
= txr
->tx_push
;
339 struct tx_push_bd
*tx_push
= &tx_push_buf
->push_bd
;
340 struct tx_bd_ext
*tx_push1
= &tx_push
->txbd2
;
341 void *pdata
= tx_push_buf
->data
;
345 /* Set COAL_NOW to be ready quickly for the next push */
346 tx_push
->tx_bd_len_flags_type
=
347 cpu_to_le32((length
<< TX_BD_LEN_SHIFT
) |
348 TX_BD_TYPE_LONG_TX_BD
|
349 TX_BD_FLAGS_LHINT_512_AND_SMALLER
|
350 TX_BD_FLAGS_COAL_NOW
|
351 TX_BD_FLAGS_PACKET_END
|
352 (2 << TX_BD_FLAGS_BD_CNT_SHIFT
));
354 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
355 tx_push1
->tx_bd_hsize_lflags
=
356 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM
);
358 tx_push1
->tx_bd_hsize_lflags
= 0;
360 tx_push1
->tx_bd_cfa_meta
= cpu_to_le32(vlan_tag_flags
);
361 tx_push1
->tx_bd_cfa_action
=
362 cpu_to_le32(cfa_action
<< TX_BD_CFA_ACTION_SHIFT
);
364 end
= pdata
+ length
;
365 end
= PTR_ALIGN(end
, 8) - 1;
368 skb_copy_from_linear_data(skb
, pdata
, len
);
370 for (j
= 0; j
< last_frag
; j
++) {
371 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[j
];
374 fptr
= skb_frag_address_safe(frag
);
378 memcpy(pdata
, fptr
, skb_frag_size(frag
));
379 pdata
+= skb_frag_size(frag
);
382 txbd
->tx_bd_len_flags_type
= tx_push
->tx_bd_len_flags_type
;
383 txbd
->tx_bd_haddr
= txr
->data_mapping
;
384 prod
= NEXT_TX(prod
);
385 txbd
= &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
386 memcpy(txbd
, tx_push1
, sizeof(*txbd
));
387 prod
= NEXT_TX(prod
);
389 cpu_to_le32(DB_KEY_TX_PUSH
| DB_LONG_TX_PUSH
| prod
);
393 netdev_tx_sent_queue(txq
, skb
->len
);
394 wmb(); /* Sync is_push and byte queue before pushing data */
396 push_len
= (length
+ sizeof(*tx_push
) + 7) / 8;
398 __iowrite64_copy(txr
->tx_doorbell
, tx_push_buf
, 16);
399 __iowrite32_copy(txr
->tx_doorbell
+ 4, tx_push_buf
+ 1,
400 (push_len
- 16) << 1);
402 __iowrite64_copy(txr
->tx_doorbell
, tx_push_buf
,
410 if (length
< BNXT_MIN_PKT_SIZE
) {
411 pad
= BNXT_MIN_PKT_SIZE
- length
;
412 if (skb_pad(skb
, pad
)) {
413 /* SKB already freed. */
417 length
= BNXT_MIN_PKT_SIZE
;
420 mapping
= dma_map_single(&pdev
->dev
, skb
->data
, len
, DMA_TO_DEVICE
);
422 if (unlikely(dma_mapping_error(&pdev
->dev
, mapping
))) {
423 dev_kfree_skb_any(skb
);
428 dma_unmap_addr_set(tx_buf
, mapping
, mapping
);
429 flags
= (len
<< TX_BD_LEN_SHIFT
) | TX_BD_TYPE_LONG_TX_BD
|
430 ((last_frag
+ 2) << TX_BD_FLAGS_BD_CNT_SHIFT
);
432 txbd
->tx_bd_haddr
= cpu_to_le64(mapping
);
434 prod
= NEXT_TX(prod
);
435 txbd1
= (struct tx_bd_ext
*)
436 &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
438 txbd1
->tx_bd_hsize_lflags
= 0;
439 if (skb_is_gso(skb
)) {
442 if (skb
->encapsulation
)
443 hdr_len
= skb_inner_network_offset(skb
) +
444 skb_inner_network_header_len(skb
) +
445 inner_tcp_hdrlen(skb
);
447 hdr_len
= skb_transport_offset(skb
) +
450 txbd1
->tx_bd_hsize_lflags
= cpu_to_le32(TX_BD_FLAGS_LSO
|
452 (hdr_len
<< (TX_BD_HSIZE_SHIFT
- 1)));
453 length
= skb_shinfo(skb
)->gso_size
;
454 txbd1
->tx_bd_mss
= cpu_to_le32(length
);
456 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
457 txbd1
->tx_bd_hsize_lflags
=
458 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM
);
459 txbd1
->tx_bd_mss
= 0;
463 flags
|= bnxt_lhint_arr
[length
];
464 txbd
->tx_bd_len_flags_type
= cpu_to_le32(flags
);
466 txbd1
->tx_bd_cfa_meta
= cpu_to_le32(vlan_tag_flags
);
467 txbd1
->tx_bd_cfa_action
=
468 cpu_to_le32(cfa_action
<< TX_BD_CFA_ACTION_SHIFT
);
469 for (i
= 0; i
< last_frag
; i
++) {
470 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
472 prod
= NEXT_TX(prod
);
473 txbd
= &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
475 len
= skb_frag_size(frag
);
476 mapping
= skb_frag_dma_map(&pdev
->dev
, frag
, 0, len
,
479 if (unlikely(dma_mapping_error(&pdev
->dev
, mapping
)))
482 tx_buf
= &txr
->tx_buf_ring
[prod
];
483 dma_unmap_addr_set(tx_buf
, mapping
, mapping
);
485 txbd
->tx_bd_haddr
= cpu_to_le64(mapping
);
487 flags
= len
<< TX_BD_LEN_SHIFT
;
488 txbd
->tx_bd_len_flags_type
= cpu_to_le32(flags
);
492 txbd
->tx_bd_len_flags_type
=
493 cpu_to_le32(((len
+ pad
) << TX_BD_LEN_SHIFT
) | flags
|
494 TX_BD_FLAGS_PACKET_END
);
496 netdev_tx_sent_queue(txq
, skb
->len
);
498 /* Sync BD data before updating doorbell */
501 prod
= NEXT_TX(prod
);
504 if (!skb
->xmit_more
|| netif_xmit_stopped(txq
))
505 bnxt_db_write(bp
, txr
->tx_doorbell
, DB_KEY_TX
| prod
);
511 if (unlikely(bnxt_tx_avail(bp
, txr
) <= MAX_SKB_FRAGS
+ 1)) {
512 if (skb
->xmit_more
&& !tx_buf
->is_push
)
513 bnxt_db_write(bp
, txr
->tx_doorbell
, DB_KEY_TX
| prod
);
515 netif_tx_stop_queue(txq
);
517 /* netif_tx_stop_queue() must be done before checking
518 * tx index in bnxt_tx_avail() below, because in
519 * bnxt_tx_int(), we update tx index before checking for
520 * netif_tx_queue_stopped().
523 if (bnxt_tx_avail(bp
, txr
) > bp
->tx_wake_thresh
)
524 netif_tx_wake_queue(txq
);
531 /* start back at beginning and unmap skb */
533 tx_buf
= &txr
->tx_buf_ring
[prod
];
535 dma_unmap_single(&pdev
->dev
, dma_unmap_addr(tx_buf
, mapping
),
536 skb_headlen(skb
), PCI_DMA_TODEVICE
);
537 prod
= NEXT_TX(prod
);
539 /* unmap remaining mapped pages */
540 for (i
= 0; i
< last_frag
; i
++) {
541 prod
= NEXT_TX(prod
);
542 tx_buf
= &txr
->tx_buf_ring
[prod
];
543 dma_unmap_page(&pdev
->dev
, dma_unmap_addr(tx_buf
, mapping
),
544 skb_frag_size(&skb_shinfo(skb
)->frags
[i
]),
548 dev_kfree_skb_any(skb
);
552 static void bnxt_tx_int(struct bnxt
*bp
, struct bnxt_napi
*bnapi
, int nr_pkts
)
554 struct bnxt_tx_ring_info
*txr
= bnapi
->tx_ring
;
555 struct netdev_queue
*txq
= netdev_get_tx_queue(bp
->dev
, txr
->txq_index
);
556 u16 cons
= txr
->tx_cons
;
557 struct pci_dev
*pdev
= bp
->pdev
;
559 unsigned int tx_bytes
= 0;
561 for (i
= 0; i
< nr_pkts
; i
++) {
562 struct bnxt_sw_tx_bd
*tx_buf
;
566 tx_buf
= &txr
->tx_buf_ring
[cons
];
567 cons
= NEXT_TX(cons
);
571 if (tx_buf
->is_push
) {
576 dma_unmap_single(&pdev
->dev
, dma_unmap_addr(tx_buf
, mapping
),
577 skb_headlen(skb
), PCI_DMA_TODEVICE
);
578 last
= tx_buf
->nr_frags
;
580 for (j
= 0; j
< last
; j
++) {
581 cons
= NEXT_TX(cons
);
582 tx_buf
= &txr
->tx_buf_ring
[cons
];
585 dma_unmap_addr(tx_buf
, mapping
),
586 skb_frag_size(&skb_shinfo(skb
)->frags
[j
]),
591 cons
= NEXT_TX(cons
);
593 tx_bytes
+= skb
->len
;
594 dev_kfree_skb_any(skb
);
597 netdev_tx_completed_queue(txq
, nr_pkts
, tx_bytes
);
600 /* Need to make the tx_cons update visible to bnxt_start_xmit()
601 * before checking for netif_tx_queue_stopped(). Without the
602 * memory barrier, there is a small possibility that bnxt_start_xmit()
603 * will miss it and cause the queue to be stopped forever.
607 if (unlikely(netif_tx_queue_stopped(txq
)) &&
608 (bnxt_tx_avail(bp
, txr
) > bp
->tx_wake_thresh
)) {
609 __netif_tx_lock(txq
, smp_processor_id());
610 if (netif_tx_queue_stopped(txq
) &&
611 bnxt_tx_avail(bp
, txr
) > bp
->tx_wake_thresh
&&
612 txr
->dev_state
!= BNXT_DEV_STATE_CLOSING
)
613 netif_tx_wake_queue(txq
);
614 __netif_tx_unlock(txq
);
618 static struct page
*__bnxt_alloc_rx_page(struct bnxt
*bp
, dma_addr_t
*mapping
,
621 struct device
*dev
= &bp
->pdev
->dev
;
624 page
= alloc_page(gfp
);
628 *mapping
= dma_map_page_attrs(dev
, page
, 0, PAGE_SIZE
, bp
->rx_dir
,
629 DMA_ATTR_WEAK_ORDERING
);
630 if (dma_mapping_error(dev
, *mapping
)) {
634 *mapping
+= bp
->rx_dma_offset
;
638 static inline u8
*__bnxt_alloc_rx_data(struct bnxt
*bp
, dma_addr_t
*mapping
,
642 struct pci_dev
*pdev
= bp
->pdev
;
644 data
= kmalloc(bp
->rx_buf_size
, gfp
);
648 *mapping
= dma_map_single_attrs(&pdev
->dev
, data
+ bp
->rx_dma_offset
,
649 bp
->rx_buf_use_size
, bp
->rx_dir
,
650 DMA_ATTR_WEAK_ORDERING
);
652 if (dma_mapping_error(&pdev
->dev
, *mapping
)) {
659 int bnxt_alloc_rx_data(struct bnxt
*bp
, struct bnxt_rx_ring_info
*rxr
,
662 struct rx_bd
*rxbd
= &rxr
->rx_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
663 struct bnxt_sw_rx_bd
*rx_buf
= &rxr
->rx_buf_ring
[prod
];
666 if (BNXT_RX_PAGE_MODE(bp
)) {
667 struct page
*page
= __bnxt_alloc_rx_page(bp
, &mapping
, gfp
);
673 rx_buf
->data_ptr
= page_address(page
) + bp
->rx_offset
;
675 u8
*data
= __bnxt_alloc_rx_data(bp
, &mapping
, gfp
);
681 rx_buf
->data_ptr
= data
+ bp
->rx_offset
;
683 rx_buf
->mapping
= mapping
;
685 rxbd
->rx_bd_haddr
= cpu_to_le64(mapping
);
689 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info
*rxr
, u16 cons
, void *data
)
691 u16 prod
= rxr
->rx_prod
;
692 struct bnxt_sw_rx_bd
*cons_rx_buf
, *prod_rx_buf
;
693 struct rx_bd
*cons_bd
, *prod_bd
;
695 prod_rx_buf
= &rxr
->rx_buf_ring
[prod
];
696 cons_rx_buf
= &rxr
->rx_buf_ring
[cons
];
698 prod_rx_buf
->data
= data
;
699 prod_rx_buf
->data_ptr
= cons_rx_buf
->data_ptr
;
701 prod_rx_buf
->mapping
= cons_rx_buf
->mapping
;
703 prod_bd
= &rxr
->rx_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
704 cons_bd
= &rxr
->rx_desc_ring
[RX_RING(cons
)][RX_IDX(cons
)];
706 prod_bd
->rx_bd_haddr
= cons_bd
->rx_bd_haddr
;
709 static inline u16
bnxt_find_next_agg_idx(struct bnxt_rx_ring_info
*rxr
, u16 idx
)
711 u16 next
, max
= rxr
->rx_agg_bmap_size
;
713 next
= find_next_zero_bit(rxr
->rx_agg_bmap
, max
, idx
);
715 next
= find_first_zero_bit(rxr
->rx_agg_bmap
, max
);
719 static inline int bnxt_alloc_rx_page(struct bnxt
*bp
,
720 struct bnxt_rx_ring_info
*rxr
,
724 &rxr
->rx_agg_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
725 struct bnxt_sw_rx_agg_bd
*rx_agg_buf
;
726 struct pci_dev
*pdev
= bp
->pdev
;
729 u16 sw_prod
= rxr
->rx_sw_agg_prod
;
730 unsigned int offset
= 0;
732 if (PAGE_SIZE
> BNXT_RX_PAGE_SIZE
) {
735 page
= alloc_page(gfp
);
739 rxr
->rx_page_offset
= 0;
741 offset
= rxr
->rx_page_offset
;
742 rxr
->rx_page_offset
+= BNXT_RX_PAGE_SIZE
;
743 if (rxr
->rx_page_offset
== PAGE_SIZE
)
748 page
= alloc_page(gfp
);
753 mapping
= dma_map_page_attrs(&pdev
->dev
, page
, offset
,
754 BNXT_RX_PAGE_SIZE
, PCI_DMA_FROMDEVICE
,
755 DMA_ATTR_WEAK_ORDERING
);
756 if (dma_mapping_error(&pdev
->dev
, mapping
)) {
761 if (unlikely(test_bit(sw_prod
, rxr
->rx_agg_bmap
)))
762 sw_prod
= bnxt_find_next_agg_idx(rxr
, sw_prod
);
764 __set_bit(sw_prod
, rxr
->rx_agg_bmap
);
765 rx_agg_buf
= &rxr
->rx_agg_ring
[sw_prod
];
766 rxr
->rx_sw_agg_prod
= NEXT_RX_AGG(sw_prod
);
768 rx_agg_buf
->page
= page
;
769 rx_agg_buf
->offset
= offset
;
770 rx_agg_buf
->mapping
= mapping
;
771 rxbd
->rx_bd_haddr
= cpu_to_le64(mapping
);
772 rxbd
->rx_bd_opaque
= sw_prod
;
776 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi
*bnapi
, u16 cp_cons
,
779 struct bnxt
*bp
= bnapi
->bp
;
780 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
781 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
782 u16 prod
= rxr
->rx_agg_prod
;
783 u16 sw_prod
= rxr
->rx_sw_agg_prod
;
786 for (i
= 0; i
< agg_bufs
; i
++) {
788 struct rx_agg_cmp
*agg
;
789 struct bnxt_sw_rx_agg_bd
*cons_rx_buf
, *prod_rx_buf
;
790 struct rx_bd
*prod_bd
;
793 agg
= (struct rx_agg_cmp
*)
794 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
795 cons
= agg
->rx_agg_cmp_opaque
;
796 __clear_bit(cons
, rxr
->rx_agg_bmap
);
798 if (unlikely(test_bit(sw_prod
, rxr
->rx_agg_bmap
)))
799 sw_prod
= bnxt_find_next_agg_idx(rxr
, sw_prod
);
801 __set_bit(sw_prod
, rxr
->rx_agg_bmap
);
802 prod_rx_buf
= &rxr
->rx_agg_ring
[sw_prod
];
803 cons_rx_buf
= &rxr
->rx_agg_ring
[cons
];
805 /* It is possible for sw_prod to be equal to cons, so
806 * set cons_rx_buf->page to NULL first.
808 page
= cons_rx_buf
->page
;
809 cons_rx_buf
->page
= NULL
;
810 prod_rx_buf
->page
= page
;
811 prod_rx_buf
->offset
= cons_rx_buf
->offset
;
813 prod_rx_buf
->mapping
= cons_rx_buf
->mapping
;
815 prod_bd
= &rxr
->rx_agg_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
817 prod_bd
->rx_bd_haddr
= cpu_to_le64(cons_rx_buf
->mapping
);
818 prod_bd
->rx_bd_opaque
= sw_prod
;
820 prod
= NEXT_RX_AGG(prod
);
821 sw_prod
= NEXT_RX_AGG(sw_prod
);
822 cp_cons
= NEXT_CMP(cp_cons
);
824 rxr
->rx_agg_prod
= prod
;
825 rxr
->rx_sw_agg_prod
= sw_prod
;
828 static struct sk_buff
*bnxt_rx_page_skb(struct bnxt
*bp
,
829 struct bnxt_rx_ring_info
*rxr
,
830 u16 cons
, void *data
, u8
*data_ptr
,
832 unsigned int offset_and_len
)
834 unsigned int payload
= offset_and_len
>> 16;
835 unsigned int len
= offset_and_len
& 0xffff;
836 struct skb_frag_struct
*frag
;
837 struct page
*page
= data
;
838 u16 prod
= rxr
->rx_prod
;
842 err
= bnxt_alloc_rx_data(bp
, rxr
, prod
, GFP_ATOMIC
);
844 bnxt_reuse_rx_data(rxr
, cons
, data
);
847 dma_addr
-= bp
->rx_dma_offset
;
848 dma_unmap_page_attrs(&bp
->pdev
->dev
, dma_addr
, PAGE_SIZE
, bp
->rx_dir
,
849 DMA_ATTR_WEAK_ORDERING
);
851 if (unlikely(!payload
))
852 payload
= eth_get_headlen(data_ptr
, len
);
854 skb
= napi_alloc_skb(&rxr
->bnapi
->napi
, payload
);
860 off
= (void *)data_ptr
- page_address(page
);
861 skb_add_rx_frag(skb
, 0, page
, off
, len
, PAGE_SIZE
);
862 memcpy(skb
->data
- NET_IP_ALIGN
, data_ptr
- NET_IP_ALIGN
,
863 payload
+ NET_IP_ALIGN
);
865 frag
= &skb_shinfo(skb
)->frags
[0];
866 skb_frag_size_sub(frag
, payload
);
867 frag
->page_offset
+= payload
;
868 skb
->data_len
-= payload
;
869 skb
->tail
+= payload
;
874 static struct sk_buff
*bnxt_rx_skb(struct bnxt
*bp
,
875 struct bnxt_rx_ring_info
*rxr
, u16 cons
,
876 void *data
, u8
*data_ptr
,
878 unsigned int offset_and_len
)
880 u16 prod
= rxr
->rx_prod
;
884 err
= bnxt_alloc_rx_data(bp
, rxr
, prod
, GFP_ATOMIC
);
886 bnxt_reuse_rx_data(rxr
, cons
, data
);
890 skb
= build_skb(data
, 0);
891 dma_unmap_single_attrs(&bp
->pdev
->dev
, dma_addr
, bp
->rx_buf_use_size
,
892 bp
->rx_dir
, DMA_ATTR_WEAK_ORDERING
);
898 skb_reserve(skb
, bp
->rx_offset
);
899 skb_put(skb
, offset_and_len
& 0xffff);
903 static struct sk_buff
*bnxt_rx_pages(struct bnxt
*bp
, struct bnxt_napi
*bnapi
,
904 struct sk_buff
*skb
, u16 cp_cons
,
907 struct pci_dev
*pdev
= bp
->pdev
;
908 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
909 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
910 u16 prod
= rxr
->rx_agg_prod
;
913 for (i
= 0; i
< agg_bufs
; i
++) {
915 struct rx_agg_cmp
*agg
;
916 struct bnxt_sw_rx_agg_bd
*cons_rx_buf
;
920 agg
= (struct rx_agg_cmp
*)
921 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
922 cons
= agg
->rx_agg_cmp_opaque
;
923 frag_len
= (le32_to_cpu(agg
->rx_agg_cmp_len_flags_type
) &
924 RX_AGG_CMP_LEN
) >> RX_AGG_CMP_LEN_SHIFT
;
926 cons_rx_buf
= &rxr
->rx_agg_ring
[cons
];
927 skb_fill_page_desc(skb
, i
, cons_rx_buf
->page
,
928 cons_rx_buf
->offset
, frag_len
);
929 __clear_bit(cons
, rxr
->rx_agg_bmap
);
931 /* It is possible for bnxt_alloc_rx_page() to allocate
932 * a sw_prod index that equals the cons index, so we
933 * need to clear the cons entry now.
935 mapping
= cons_rx_buf
->mapping
;
936 page
= cons_rx_buf
->page
;
937 cons_rx_buf
->page
= NULL
;
939 if (bnxt_alloc_rx_page(bp
, rxr
, prod
, GFP_ATOMIC
) != 0) {
940 struct skb_shared_info
*shinfo
;
941 unsigned int nr_frags
;
943 shinfo
= skb_shinfo(skb
);
944 nr_frags
= --shinfo
->nr_frags
;
945 __skb_frag_set_page(&shinfo
->frags
[nr_frags
], NULL
);
949 cons_rx_buf
->page
= page
;
951 /* Update prod since possibly some pages have been
954 rxr
->rx_agg_prod
= prod
;
955 bnxt_reuse_rx_agg_bufs(bnapi
, cp_cons
, agg_bufs
- i
);
959 dma_unmap_page_attrs(&pdev
->dev
, mapping
, BNXT_RX_PAGE_SIZE
,
961 DMA_ATTR_WEAK_ORDERING
);
963 skb
->data_len
+= frag_len
;
964 skb
->len
+= frag_len
;
965 skb
->truesize
+= PAGE_SIZE
;
967 prod
= NEXT_RX_AGG(prod
);
968 cp_cons
= NEXT_CMP(cp_cons
);
970 rxr
->rx_agg_prod
= prod
;
974 static int bnxt_agg_bufs_valid(struct bnxt
*bp
, struct bnxt_cp_ring_info
*cpr
,
975 u8 agg_bufs
, u32
*raw_cons
)
978 struct rx_agg_cmp
*agg
;
980 *raw_cons
= ADV_RAW_CMP(*raw_cons
, agg_bufs
);
981 last
= RING_CMP(*raw_cons
);
982 agg
= (struct rx_agg_cmp
*)
983 &cpr
->cp_desc_ring
[CP_RING(last
)][CP_IDX(last
)];
984 return RX_AGG_CMP_VALID(agg
, *raw_cons
);
987 static inline struct sk_buff
*bnxt_copy_skb(struct bnxt_napi
*bnapi
, u8
*data
,
991 struct bnxt
*bp
= bnapi
->bp
;
992 struct pci_dev
*pdev
= bp
->pdev
;
995 skb
= napi_alloc_skb(&bnapi
->napi
, len
);
999 dma_sync_single_for_cpu(&pdev
->dev
, mapping
, bp
->rx_copy_thresh
,
1002 memcpy(skb
->data
- NET_IP_ALIGN
, data
- NET_IP_ALIGN
,
1003 len
+ NET_IP_ALIGN
);
1005 dma_sync_single_for_device(&pdev
->dev
, mapping
, bp
->rx_copy_thresh
,
1012 static int bnxt_discard_rx(struct bnxt
*bp
, struct bnxt_napi
*bnapi
,
1013 u32
*raw_cons
, void *cmp
)
1015 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1016 struct rx_cmp
*rxcmp
= cmp
;
1017 u32 tmp_raw_cons
= *raw_cons
;
1018 u8 cmp_type
, agg_bufs
= 0;
1020 cmp_type
= RX_CMP_TYPE(rxcmp
);
1022 if (cmp_type
== CMP_TYPE_RX_L2_CMP
) {
1023 agg_bufs
= (le32_to_cpu(rxcmp
->rx_cmp_misc_v1
) &
1025 RX_CMP_AGG_BUFS_SHIFT
;
1026 } else if (cmp_type
== CMP_TYPE_RX_L2_TPA_END_CMP
) {
1027 struct rx_tpa_end_cmp
*tpa_end
= cmp
;
1029 agg_bufs
= (le32_to_cpu(tpa_end
->rx_tpa_end_cmp_misc_v1
) &
1030 RX_TPA_END_CMP_AGG_BUFS
) >>
1031 RX_TPA_END_CMP_AGG_BUFS_SHIFT
;
1035 if (!bnxt_agg_bufs_valid(bp
, cpr
, agg_bufs
, &tmp_raw_cons
))
1038 *raw_cons
= tmp_raw_cons
;
1042 static void bnxt_queue_sp_work(struct bnxt
*bp
)
1045 queue_work(bnxt_pf_wq
, &bp
->sp_task
);
1047 schedule_work(&bp
->sp_task
);
1050 static void bnxt_cancel_sp_work(struct bnxt
*bp
)
1053 flush_workqueue(bnxt_pf_wq
);
1055 cancel_work_sync(&bp
->sp_task
);
1058 static void bnxt_sched_reset(struct bnxt
*bp
, struct bnxt_rx_ring_info
*rxr
)
1060 if (!rxr
->bnapi
->in_reset
) {
1061 rxr
->bnapi
->in_reset
= true;
1062 set_bit(BNXT_RESET_TASK_SP_EVENT
, &bp
->sp_event
);
1063 bnxt_queue_sp_work(bp
);
1065 rxr
->rx_next_cons
= 0xffff;
1068 static void bnxt_tpa_start(struct bnxt
*bp
, struct bnxt_rx_ring_info
*rxr
,
1069 struct rx_tpa_start_cmp
*tpa_start
,
1070 struct rx_tpa_start_cmp_ext
*tpa_start1
)
1072 u8 agg_id
= TPA_START_AGG_ID(tpa_start
);
1074 struct bnxt_tpa_info
*tpa_info
;
1075 struct bnxt_sw_rx_bd
*cons_rx_buf
, *prod_rx_buf
;
1076 struct rx_bd
*prod_bd
;
1079 cons
= tpa_start
->rx_tpa_start_cmp_opaque
;
1080 prod
= rxr
->rx_prod
;
1081 cons_rx_buf
= &rxr
->rx_buf_ring
[cons
];
1082 prod_rx_buf
= &rxr
->rx_buf_ring
[prod
];
1083 tpa_info
= &rxr
->rx_tpa
[agg_id
];
1085 if (unlikely(cons
!= rxr
->rx_next_cons
)) {
1086 bnxt_sched_reset(bp
, rxr
);
1089 /* Store cfa_code in tpa_info to use in tpa_end
1090 * completion processing.
1092 tpa_info
->cfa_code
= TPA_START_CFA_CODE(tpa_start1
);
1093 prod_rx_buf
->data
= tpa_info
->data
;
1094 prod_rx_buf
->data_ptr
= tpa_info
->data_ptr
;
1096 mapping
= tpa_info
->mapping
;
1097 prod_rx_buf
->mapping
= mapping
;
1099 prod_bd
= &rxr
->rx_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
1101 prod_bd
->rx_bd_haddr
= cpu_to_le64(mapping
);
1103 tpa_info
->data
= cons_rx_buf
->data
;
1104 tpa_info
->data_ptr
= cons_rx_buf
->data_ptr
;
1105 cons_rx_buf
->data
= NULL
;
1106 tpa_info
->mapping
= cons_rx_buf
->mapping
;
1109 le32_to_cpu(tpa_start
->rx_tpa_start_cmp_len_flags_type
) >>
1110 RX_TPA_START_CMP_LEN_SHIFT
;
1111 if (likely(TPA_START_HASH_VALID(tpa_start
))) {
1112 u32 hash_type
= TPA_START_HASH_TYPE(tpa_start
);
1114 tpa_info
->hash_type
= PKT_HASH_TYPE_L4
;
1115 tpa_info
->gso_type
= SKB_GSO_TCPV4
;
1116 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1118 tpa_info
->gso_type
= SKB_GSO_TCPV6
;
1119 tpa_info
->rss_hash
=
1120 le32_to_cpu(tpa_start
->rx_tpa_start_cmp_rss_hash
);
1122 tpa_info
->hash_type
= PKT_HASH_TYPE_NONE
;
1123 tpa_info
->gso_type
= 0;
1124 if (netif_msg_rx_err(bp
))
1125 netdev_warn(bp
->dev
, "TPA packet without valid hash\n");
1127 tpa_info
->flags2
= le32_to_cpu(tpa_start1
->rx_tpa_start_cmp_flags2
);
1128 tpa_info
->metadata
= le32_to_cpu(tpa_start1
->rx_tpa_start_cmp_metadata
);
1129 tpa_info
->hdr_info
= le32_to_cpu(tpa_start1
->rx_tpa_start_cmp_hdr_info
);
1131 rxr
->rx_prod
= NEXT_RX(prod
);
1132 cons
= NEXT_RX(cons
);
1133 rxr
->rx_next_cons
= NEXT_RX(cons
);
1134 cons_rx_buf
= &rxr
->rx_buf_ring
[cons
];
1136 bnxt_reuse_rx_data(rxr
, cons
, cons_rx_buf
->data
);
1137 rxr
->rx_prod
= NEXT_RX(rxr
->rx_prod
);
1138 cons_rx_buf
->data
= NULL
;
1141 static void bnxt_abort_tpa(struct bnxt
*bp
, struct bnxt_napi
*bnapi
,
1142 u16 cp_cons
, u32 agg_bufs
)
1145 bnxt_reuse_rx_agg_bufs(bnapi
, cp_cons
, agg_bufs
);
1148 static struct sk_buff
*bnxt_gro_func_5731x(struct bnxt_tpa_info
*tpa_info
,
1149 int payload_off
, int tcp_ts
,
1150 struct sk_buff
*skb
)
1155 u16 outer_ip_off
, inner_ip_off
, inner_mac_off
;
1156 u32 hdr_info
= tpa_info
->hdr_info
;
1157 bool loopback
= false;
1159 inner_ip_off
= BNXT_TPA_INNER_L3_OFF(hdr_info
);
1160 inner_mac_off
= BNXT_TPA_INNER_L2_OFF(hdr_info
);
1161 outer_ip_off
= BNXT_TPA_OUTER_L3_OFF(hdr_info
);
1163 /* If the packet is an internal loopback packet, the offsets will
1164 * have an extra 4 bytes.
1166 if (inner_mac_off
== 4) {
1168 } else if (inner_mac_off
> 4) {
1169 __be16 proto
= *((__be16
*)(skb
->data
+ inner_ip_off
-
1172 /* We only support inner iPv4/ipv6. If we don't see the
1173 * correct protocol ID, it must be a loopback packet where
1174 * the offsets are off by 4.
1176 if (proto
!= htons(ETH_P_IP
) && proto
!= htons(ETH_P_IPV6
))
1180 /* internal loopback packet, subtract all offsets by 4 */
1186 nw_off
= inner_ip_off
- ETH_HLEN
;
1187 skb_set_network_header(skb
, nw_off
);
1188 if (tpa_info
->flags2
& RX_TPA_START_CMP_FLAGS2_IP_TYPE
) {
1189 struct ipv6hdr
*iph
= ipv6_hdr(skb
);
1191 skb_set_transport_header(skb
, nw_off
+ sizeof(struct ipv6hdr
));
1192 len
= skb
->len
- skb_transport_offset(skb
);
1194 th
->check
= ~tcp_v6_check(len
, &iph
->saddr
, &iph
->daddr
, 0);
1196 struct iphdr
*iph
= ip_hdr(skb
);
1198 skb_set_transport_header(skb
, nw_off
+ sizeof(struct iphdr
));
1199 len
= skb
->len
- skb_transport_offset(skb
);
1201 th
->check
= ~tcp_v4_check(len
, iph
->saddr
, iph
->daddr
, 0);
1204 if (inner_mac_off
) { /* tunnel */
1205 struct udphdr
*uh
= NULL
;
1206 __be16 proto
= *((__be16
*)(skb
->data
+ outer_ip_off
-
1209 if (proto
== htons(ETH_P_IP
)) {
1210 struct iphdr
*iph
= (struct iphdr
*)skb
->data
;
1212 if (iph
->protocol
== IPPROTO_UDP
)
1213 uh
= (struct udphdr
*)(iph
+ 1);
1215 struct ipv6hdr
*iph
= (struct ipv6hdr
*)skb
->data
;
1217 if (iph
->nexthdr
== IPPROTO_UDP
)
1218 uh
= (struct udphdr
*)(iph
+ 1);
1222 skb_shinfo(skb
)->gso_type
|=
1223 SKB_GSO_UDP_TUNNEL_CSUM
;
1225 skb_shinfo(skb
)->gso_type
|= SKB_GSO_UDP_TUNNEL
;
1232 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
1233 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1235 static struct sk_buff
*bnxt_gro_func_5730x(struct bnxt_tpa_info
*tpa_info
,
1236 int payload_off
, int tcp_ts
,
1237 struct sk_buff
*skb
)
1241 int len
, nw_off
, tcp_opt_len
= 0;
1246 if (tpa_info
->gso_type
== SKB_GSO_TCPV4
) {
1249 nw_off
= payload_off
- BNXT_IPV4_HDR_SIZE
- tcp_opt_len
-
1251 skb_set_network_header(skb
, nw_off
);
1253 skb_set_transport_header(skb
, nw_off
+ sizeof(struct iphdr
));
1254 len
= skb
->len
- skb_transport_offset(skb
);
1256 th
->check
= ~tcp_v4_check(len
, iph
->saddr
, iph
->daddr
, 0);
1257 } else if (tpa_info
->gso_type
== SKB_GSO_TCPV6
) {
1258 struct ipv6hdr
*iph
;
1260 nw_off
= payload_off
- BNXT_IPV6_HDR_SIZE
- tcp_opt_len
-
1262 skb_set_network_header(skb
, nw_off
);
1263 iph
= ipv6_hdr(skb
);
1264 skb_set_transport_header(skb
, nw_off
+ sizeof(struct ipv6hdr
));
1265 len
= skb
->len
- skb_transport_offset(skb
);
1267 th
->check
= ~tcp_v6_check(len
, &iph
->saddr
, &iph
->daddr
, 0);
1269 dev_kfree_skb_any(skb
);
1273 if (nw_off
) { /* tunnel */
1274 struct udphdr
*uh
= NULL
;
1276 if (skb
->protocol
== htons(ETH_P_IP
)) {
1277 struct iphdr
*iph
= (struct iphdr
*)skb
->data
;
1279 if (iph
->protocol
== IPPROTO_UDP
)
1280 uh
= (struct udphdr
*)(iph
+ 1);
1282 struct ipv6hdr
*iph
= (struct ipv6hdr
*)skb
->data
;
1284 if (iph
->nexthdr
== IPPROTO_UDP
)
1285 uh
= (struct udphdr
*)(iph
+ 1);
1289 skb_shinfo(skb
)->gso_type
|=
1290 SKB_GSO_UDP_TUNNEL_CSUM
;
1292 skb_shinfo(skb
)->gso_type
|= SKB_GSO_UDP_TUNNEL
;
1299 static inline struct sk_buff
*bnxt_gro_skb(struct bnxt
*bp
,
1300 struct bnxt_tpa_info
*tpa_info
,
1301 struct rx_tpa_end_cmp
*tpa_end
,
1302 struct rx_tpa_end_cmp_ext
*tpa_end1
,
1303 struct sk_buff
*skb
)
1309 segs
= TPA_END_TPA_SEGS(tpa_end
);
1313 NAPI_GRO_CB(skb
)->count
= segs
;
1314 skb_shinfo(skb
)->gso_size
=
1315 le32_to_cpu(tpa_end1
->rx_tpa_end_cmp_seg_len
);
1316 skb_shinfo(skb
)->gso_type
= tpa_info
->gso_type
;
1317 payload_off
= (le32_to_cpu(tpa_end
->rx_tpa_end_cmp_misc_v1
) &
1318 RX_TPA_END_CMP_PAYLOAD_OFFSET
) >>
1319 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT
;
1320 skb
= bp
->gro_func(tpa_info
, payload_off
, TPA_END_GRO_TS(tpa_end
), skb
);
1322 tcp_gro_complete(skb
);
1327 /* Given the cfa_code of a received packet determine which
1328 * netdev (vf-rep or PF) the packet is destined to.
1330 static struct net_device
*bnxt_get_pkt_dev(struct bnxt
*bp
, u16 cfa_code
)
1332 struct net_device
*dev
= bnxt_get_vf_rep(bp
, cfa_code
);
1334 /* if vf-rep dev is NULL, the must belongs to the PF */
1335 return dev
? dev
: bp
->dev
;
1338 static inline struct sk_buff
*bnxt_tpa_end(struct bnxt
*bp
,
1339 struct bnxt_napi
*bnapi
,
1341 struct rx_tpa_end_cmp
*tpa_end
,
1342 struct rx_tpa_end_cmp_ext
*tpa_end1
,
1345 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1346 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
1347 u8 agg_id
= TPA_END_AGG_ID(tpa_end
);
1348 u8
*data_ptr
, agg_bufs
;
1349 u16 cp_cons
= RING_CMP(*raw_cons
);
1351 struct bnxt_tpa_info
*tpa_info
;
1353 struct sk_buff
*skb
;
1356 if (unlikely(bnapi
->in_reset
)) {
1357 int rc
= bnxt_discard_rx(bp
, bnapi
, raw_cons
, tpa_end
);
1360 return ERR_PTR(-EBUSY
);
1364 tpa_info
= &rxr
->rx_tpa
[agg_id
];
1365 data
= tpa_info
->data
;
1366 data_ptr
= tpa_info
->data_ptr
;
1368 len
= tpa_info
->len
;
1369 mapping
= tpa_info
->mapping
;
1371 agg_bufs
= (le32_to_cpu(tpa_end
->rx_tpa_end_cmp_misc_v1
) &
1372 RX_TPA_END_CMP_AGG_BUFS
) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT
;
1375 if (!bnxt_agg_bufs_valid(bp
, cpr
, agg_bufs
, raw_cons
))
1376 return ERR_PTR(-EBUSY
);
1378 *event
|= BNXT_AGG_EVENT
;
1379 cp_cons
= NEXT_CMP(cp_cons
);
1382 if (unlikely(agg_bufs
> MAX_SKB_FRAGS
|| TPA_END_ERRORS(tpa_end1
))) {
1383 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
1384 if (agg_bufs
> MAX_SKB_FRAGS
)
1385 netdev_warn(bp
->dev
, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1386 agg_bufs
, (int)MAX_SKB_FRAGS
);
1390 if (len
<= bp
->rx_copy_thresh
) {
1391 skb
= bnxt_copy_skb(bnapi
, data_ptr
, len
, mapping
);
1393 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
1398 dma_addr_t new_mapping
;
1400 new_data
= __bnxt_alloc_rx_data(bp
, &new_mapping
, GFP_ATOMIC
);
1402 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
1406 tpa_info
->data
= new_data
;
1407 tpa_info
->data_ptr
= new_data
+ bp
->rx_offset
;
1408 tpa_info
->mapping
= new_mapping
;
1410 skb
= build_skb(data
, 0);
1411 dma_unmap_single_attrs(&bp
->pdev
->dev
, mapping
,
1412 bp
->rx_buf_use_size
, bp
->rx_dir
,
1413 DMA_ATTR_WEAK_ORDERING
);
1417 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
1420 skb_reserve(skb
, bp
->rx_offset
);
1425 skb
= bnxt_rx_pages(bp
, bnapi
, skb
, cp_cons
, agg_bufs
);
1427 /* Page reuse already handled by bnxt_rx_pages(). */
1433 eth_type_trans(skb
, bnxt_get_pkt_dev(bp
, tpa_info
->cfa_code
));
1435 if (tpa_info
->hash_type
!= PKT_HASH_TYPE_NONE
)
1436 skb_set_hash(skb
, tpa_info
->rss_hash
, tpa_info
->hash_type
);
1438 if ((tpa_info
->flags2
& RX_CMP_FLAGS2_META_FORMAT_VLAN
) &&
1439 (skb
->dev
->features
& NETIF_F_HW_VLAN_CTAG_RX
)) {
1440 u16 vlan_proto
= tpa_info
->metadata
>>
1441 RX_CMP_FLAGS2_METADATA_TPID_SFT
;
1442 u16 vtag
= tpa_info
->metadata
& RX_CMP_FLAGS2_METADATA_TCI_MASK
;
1444 __vlan_hwaccel_put_tag(skb
, htons(vlan_proto
), vtag
);
1447 skb_checksum_none_assert(skb
);
1448 if (likely(tpa_info
->flags2
& RX_TPA_START_CMP_FLAGS2_L4_CS_CALC
)) {
1449 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1451 (tpa_info
->flags2
& RX_CMP_FLAGS2_T_L4_CS_CALC
) >> 3;
1454 if (TPA_END_GRO(tpa_end
))
1455 skb
= bnxt_gro_skb(bp
, tpa_info
, tpa_end
, tpa_end1
, skb
);
1460 static void bnxt_deliver_skb(struct bnxt
*bp
, struct bnxt_napi
*bnapi
,
1461 struct sk_buff
*skb
)
1463 if (skb
->dev
!= bp
->dev
) {
1464 /* this packet belongs to a vf-rep */
1465 bnxt_vf_rep_rx(bp
, skb
);
1468 skb_record_rx_queue(skb
, bnapi
->index
);
1469 napi_gro_receive(&bnapi
->napi
, skb
);
1472 /* returns the following:
1473 * 1 - 1 packet successfully received
1474 * 0 - successful TPA_START, packet not completed yet
1475 * -EBUSY - completion ring does not have all the agg buffers yet
1476 * -ENOMEM - packet aborted due to out of memory
1477 * -EIO - packet aborted due to hw error indicated in BD
1479 static int bnxt_rx_pkt(struct bnxt
*bp
, struct bnxt_napi
*bnapi
, u32
*raw_cons
,
1482 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1483 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
1484 struct net_device
*dev
= bp
->dev
;
1485 struct rx_cmp
*rxcmp
;
1486 struct rx_cmp_ext
*rxcmp1
;
1487 u32 tmp_raw_cons
= *raw_cons
;
1488 u16 cfa_code
, cons
, prod
, cp_cons
= RING_CMP(tmp_raw_cons
);
1489 struct bnxt_sw_rx_bd
*rx_buf
;
1491 u8
*data_ptr
, agg_bufs
, cmp_type
;
1492 dma_addr_t dma_addr
;
1493 struct sk_buff
*skb
;
1498 rxcmp
= (struct rx_cmp
*)
1499 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
1501 tmp_raw_cons
= NEXT_RAW_CMP(tmp_raw_cons
);
1502 cp_cons
= RING_CMP(tmp_raw_cons
);
1503 rxcmp1
= (struct rx_cmp_ext
*)
1504 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
1506 if (!RX_CMP_VALID(rxcmp1
, tmp_raw_cons
))
1509 cmp_type
= RX_CMP_TYPE(rxcmp
);
1511 prod
= rxr
->rx_prod
;
1513 if (cmp_type
== CMP_TYPE_RX_L2_TPA_START_CMP
) {
1514 bnxt_tpa_start(bp
, rxr
, (struct rx_tpa_start_cmp
*)rxcmp
,
1515 (struct rx_tpa_start_cmp_ext
*)rxcmp1
);
1517 *event
|= BNXT_RX_EVENT
;
1518 goto next_rx_no_prod_no_len
;
1520 } else if (cmp_type
== CMP_TYPE_RX_L2_TPA_END_CMP
) {
1521 skb
= bnxt_tpa_end(bp
, bnapi
, &tmp_raw_cons
,
1522 (struct rx_tpa_end_cmp
*)rxcmp
,
1523 (struct rx_tpa_end_cmp_ext
*)rxcmp1
, event
);
1530 bnxt_deliver_skb(bp
, bnapi
, skb
);
1533 *event
|= BNXT_RX_EVENT
;
1534 goto next_rx_no_prod_no_len
;
1537 cons
= rxcmp
->rx_cmp_opaque
;
1538 rx_buf
= &rxr
->rx_buf_ring
[cons
];
1539 data
= rx_buf
->data
;
1540 data_ptr
= rx_buf
->data_ptr
;
1541 if (unlikely(cons
!= rxr
->rx_next_cons
)) {
1542 int rc1
= bnxt_discard_rx(bp
, bnapi
, raw_cons
, rxcmp
);
1544 bnxt_sched_reset(bp
, rxr
);
1549 misc
= le32_to_cpu(rxcmp
->rx_cmp_misc_v1
);
1550 agg_bufs
= (misc
& RX_CMP_AGG_BUFS
) >> RX_CMP_AGG_BUFS_SHIFT
;
1553 if (!bnxt_agg_bufs_valid(bp
, cpr
, agg_bufs
, &tmp_raw_cons
))
1556 cp_cons
= NEXT_CMP(cp_cons
);
1557 *event
|= BNXT_AGG_EVENT
;
1559 *event
|= BNXT_RX_EVENT
;
1561 rx_buf
->data
= NULL
;
1562 if (rxcmp1
->rx_cmp_cfa_code_errors_v2
& RX_CMP_L2_ERRORS
) {
1563 bnxt_reuse_rx_data(rxr
, cons
, data
);
1565 bnxt_reuse_rx_agg_bufs(bnapi
, cp_cons
, agg_bufs
);
1571 len
= le32_to_cpu(rxcmp
->rx_cmp_len_flags_type
) >> RX_CMP_LEN_SHIFT
;
1572 dma_addr
= rx_buf
->mapping
;
1574 if (bnxt_rx_xdp(bp
, rxr
, cons
, data
, &data_ptr
, &len
, event
)) {
1579 if (len
<= bp
->rx_copy_thresh
) {
1580 skb
= bnxt_copy_skb(bnapi
, data_ptr
, len
, dma_addr
);
1581 bnxt_reuse_rx_data(rxr
, cons
, data
);
1589 if (rx_buf
->data_ptr
== data_ptr
)
1590 payload
= misc
& RX_CMP_PAYLOAD_OFFSET
;
1593 skb
= bp
->rx_skb_func(bp
, rxr
, cons
, data
, data_ptr
, dma_addr
,
1602 skb
= bnxt_rx_pages(bp
, bnapi
, skb
, cp_cons
, agg_bufs
);
1609 if (RX_CMP_HASH_VALID(rxcmp
)) {
1610 u32 hash_type
= RX_CMP_HASH_TYPE(rxcmp
);
1611 enum pkt_hash_types type
= PKT_HASH_TYPE_L4
;
1613 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1614 if (hash_type
!= 1 && hash_type
!= 3)
1615 type
= PKT_HASH_TYPE_L3
;
1616 skb_set_hash(skb
, le32_to_cpu(rxcmp
->rx_cmp_rss_hash
), type
);
1619 cfa_code
= RX_CMP_CFA_CODE(rxcmp1
);
1620 skb
->protocol
= eth_type_trans(skb
, bnxt_get_pkt_dev(bp
, cfa_code
));
1622 if ((rxcmp1
->rx_cmp_flags2
&
1623 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN
)) &&
1624 (skb
->dev
->features
& NETIF_F_HW_VLAN_CTAG_RX
)) {
1625 u32 meta_data
= le32_to_cpu(rxcmp1
->rx_cmp_meta_data
);
1626 u16 vtag
= meta_data
& RX_CMP_FLAGS2_METADATA_TCI_MASK
;
1627 u16 vlan_proto
= meta_data
>> RX_CMP_FLAGS2_METADATA_TPID_SFT
;
1629 __vlan_hwaccel_put_tag(skb
, htons(vlan_proto
), vtag
);
1632 skb_checksum_none_assert(skb
);
1633 if (RX_CMP_L4_CS_OK(rxcmp1
)) {
1634 if (dev
->features
& NETIF_F_RXCSUM
) {
1635 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1636 skb
->csum_level
= RX_CMP_ENCAP(rxcmp1
);
1639 if (rxcmp1
->rx_cmp_cfa_code_errors_v2
& RX_CMP_L4_CS_ERR_BITS
) {
1640 if (dev
->features
& NETIF_F_RXCSUM
)
1641 cpr
->rx_l4_csum_errors
++;
1645 bnxt_deliver_skb(bp
, bnapi
, skb
);
1649 rxr
->rx_prod
= NEXT_RX(prod
);
1650 rxr
->rx_next_cons
= NEXT_RX(cons
);
1652 cpr
->rx_packets
+= 1;
1653 cpr
->rx_bytes
+= len
;
1655 next_rx_no_prod_no_len
:
1656 *raw_cons
= tmp_raw_cons
;
1661 /* In netpoll mode, if we are using a combined completion ring, we need to
1662 * discard the rx packets and recycle the buffers.
1664 static int bnxt_force_rx_discard(struct bnxt
*bp
, struct bnxt_napi
*bnapi
,
1665 u32
*raw_cons
, u8
*event
)
1667 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1668 u32 tmp_raw_cons
= *raw_cons
;
1669 struct rx_cmp_ext
*rxcmp1
;
1670 struct rx_cmp
*rxcmp
;
1674 cp_cons
= RING_CMP(tmp_raw_cons
);
1675 rxcmp
= (struct rx_cmp
*)
1676 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
1678 tmp_raw_cons
= NEXT_RAW_CMP(tmp_raw_cons
);
1679 cp_cons
= RING_CMP(tmp_raw_cons
);
1680 rxcmp1
= (struct rx_cmp_ext
*)
1681 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
1683 if (!RX_CMP_VALID(rxcmp1
, tmp_raw_cons
))
1686 cmp_type
= RX_CMP_TYPE(rxcmp
);
1687 if (cmp_type
== CMP_TYPE_RX_L2_CMP
) {
1688 rxcmp1
->rx_cmp_cfa_code_errors_v2
|=
1689 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR
);
1690 } else if (cmp_type
== CMP_TYPE_RX_L2_TPA_END_CMP
) {
1691 struct rx_tpa_end_cmp_ext
*tpa_end1
;
1693 tpa_end1
= (struct rx_tpa_end_cmp_ext
*)rxcmp1
;
1694 tpa_end1
->rx_tpa_end_cmp_errors_v2
|=
1695 cpu_to_le32(RX_TPA_END_CMP_ERRORS
);
1697 return bnxt_rx_pkt(bp
, bnapi
, raw_cons
, event
);
1700 #define BNXT_GET_EVENT_PORT(data) \
1702 ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
1704 static int bnxt_async_event_process(struct bnxt
*bp
,
1705 struct hwrm_async_event_cmpl
*cmpl
)
1707 u16 event_id
= le16_to_cpu(cmpl
->event_id
);
1709 /* TODO CHIMP_FW: Define event id's for link change, error etc */
1711 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE
: {
1712 u32 data1
= le32_to_cpu(cmpl
->event_data1
);
1713 struct bnxt_link_info
*link_info
= &bp
->link_info
;
1716 goto async_event_process_exit
;
1718 /* print unsupported speed warning in forced speed mode only */
1719 if (!(link_info
->autoneg
& BNXT_AUTONEG_SPEED
) &&
1720 (data1
& 0x20000)) {
1721 u16 fw_speed
= link_info
->force_link_speed
;
1722 u32 speed
= bnxt_fw_to_ethtool_speed(fw_speed
);
1724 if (speed
!= SPEED_UNKNOWN
)
1725 netdev_warn(bp
->dev
, "Link speed %d no longer supported\n",
1728 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT
, &bp
->sp_event
);
1731 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE
:
1732 set_bit(BNXT_LINK_CHNG_SP_EVENT
, &bp
->sp_event
);
1734 case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD
:
1735 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT
, &bp
->sp_event
);
1737 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED
: {
1738 u32 data1
= le32_to_cpu(cmpl
->event_data1
);
1739 u16 port_id
= BNXT_GET_EVENT_PORT(data1
);
1744 if (bp
->pf
.port_id
!= port_id
)
1747 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT
, &bp
->sp_event
);
1750 case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE
:
1752 goto async_event_process_exit
;
1753 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT
, &bp
->sp_event
);
1756 goto async_event_process_exit
;
1758 bnxt_queue_sp_work(bp
);
1759 async_event_process_exit
:
1760 bnxt_ulp_async_events(bp
, cmpl
);
1764 static int bnxt_hwrm_handler(struct bnxt
*bp
, struct tx_cmp
*txcmp
)
1766 u16 cmpl_type
= TX_CMP_TYPE(txcmp
), vf_id
, seq_id
;
1767 struct hwrm_cmpl
*h_cmpl
= (struct hwrm_cmpl
*)txcmp
;
1768 struct hwrm_fwd_req_cmpl
*fwd_req_cmpl
=
1769 (struct hwrm_fwd_req_cmpl
*)txcmp
;
1771 switch (cmpl_type
) {
1772 case CMPL_BASE_TYPE_HWRM_DONE
:
1773 seq_id
= le16_to_cpu(h_cmpl
->sequence_id
);
1774 if (seq_id
== bp
->hwrm_intr_seq_id
)
1775 bp
->hwrm_intr_seq_id
= HWRM_SEQ_ID_INVALID
;
1777 netdev_err(bp
->dev
, "Invalid hwrm seq id %d\n", seq_id
);
1780 case CMPL_BASE_TYPE_HWRM_FWD_REQ
:
1781 vf_id
= le16_to_cpu(fwd_req_cmpl
->source_id
);
1783 if ((vf_id
< bp
->pf
.first_vf_id
) ||
1784 (vf_id
>= bp
->pf
.first_vf_id
+ bp
->pf
.active_vfs
)) {
1785 netdev_err(bp
->dev
, "Msg contains invalid VF id %x\n",
1790 set_bit(vf_id
- bp
->pf
.first_vf_id
, bp
->pf
.vf_event_bmap
);
1791 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT
, &bp
->sp_event
);
1792 bnxt_queue_sp_work(bp
);
1795 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT
:
1796 bnxt_async_event_process(bp
,
1797 (struct hwrm_async_event_cmpl
*)txcmp
);
1806 static irqreturn_t
bnxt_msix(int irq
, void *dev_instance
)
1808 struct bnxt_napi
*bnapi
= dev_instance
;
1809 struct bnxt
*bp
= bnapi
->bp
;
1810 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1811 u32 cons
= RING_CMP(cpr
->cp_raw_cons
);
1814 prefetch(&cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)]);
1815 napi_schedule(&bnapi
->napi
);
1819 static inline int bnxt_has_work(struct bnxt
*bp
, struct bnxt_cp_ring_info
*cpr
)
1821 u32 raw_cons
= cpr
->cp_raw_cons
;
1822 u16 cons
= RING_CMP(raw_cons
);
1823 struct tx_cmp
*txcmp
;
1825 txcmp
= &cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)];
1827 return TX_CMP_VALID(txcmp
, raw_cons
);
1830 static irqreturn_t
bnxt_inta(int irq
, void *dev_instance
)
1832 struct bnxt_napi
*bnapi
= dev_instance
;
1833 struct bnxt
*bp
= bnapi
->bp
;
1834 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1835 u32 cons
= RING_CMP(cpr
->cp_raw_cons
);
1838 prefetch(&cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)]);
1840 if (!bnxt_has_work(bp
, cpr
)) {
1841 int_status
= readl(bp
->bar0
+ BNXT_CAG_REG_LEGACY_INT_STATUS
);
1842 /* return if erroneous interrupt */
1843 if (!(int_status
& (0x10000 << cpr
->cp_ring_struct
.fw_ring_id
)))
1847 /* disable ring IRQ */
1848 BNXT_CP_DB_IRQ_DIS(cpr
->cp_doorbell
);
1850 /* Return here if interrupt is shared and is disabled. */
1851 if (unlikely(atomic_read(&bp
->intr_sem
) != 0))
1854 napi_schedule(&bnapi
->napi
);
1858 static int bnxt_poll_work(struct bnxt
*bp
, struct bnxt_napi
*bnapi
, int budget
)
1860 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1861 u32 raw_cons
= cpr
->cp_raw_cons
;
1866 struct tx_cmp
*txcmp
;
1871 cons
= RING_CMP(raw_cons
);
1872 txcmp
= &cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)];
1874 if (!TX_CMP_VALID(txcmp
, raw_cons
))
1877 /* The valid test of the entry must be done first before
1878 * reading any further.
1881 if (TX_CMP_TYPE(txcmp
) == CMP_TYPE_TX_L2_CMP
) {
1883 /* return full budget so NAPI will complete. */
1884 if (unlikely(tx_pkts
> bp
->tx_wake_thresh
))
1886 } else if ((TX_CMP_TYPE(txcmp
) & 0x30) == 0x10) {
1888 rc
= bnxt_rx_pkt(bp
, bnapi
, &raw_cons
, &event
);
1890 rc
= bnxt_force_rx_discard(bp
, bnapi
, &raw_cons
,
1892 if (likely(rc
>= 0))
1894 /* Increment rx_pkts when rc is -ENOMEM to count towards
1895 * the NAPI budget. Otherwise, we may potentially loop
1896 * here forever if we consistently cannot allocate
1899 else if (rc
== -ENOMEM
&& budget
)
1901 else if (rc
== -EBUSY
) /* partial completion */
1903 } else if (unlikely((TX_CMP_TYPE(txcmp
) ==
1904 CMPL_BASE_TYPE_HWRM_DONE
) ||
1905 (TX_CMP_TYPE(txcmp
) ==
1906 CMPL_BASE_TYPE_HWRM_FWD_REQ
) ||
1907 (TX_CMP_TYPE(txcmp
) ==
1908 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT
))) {
1909 bnxt_hwrm_handler(bp
, txcmp
);
1911 raw_cons
= NEXT_RAW_CMP(raw_cons
);
1913 if (rx_pkts
== budget
)
1917 if (event
& BNXT_TX_EVENT
) {
1918 struct bnxt_tx_ring_info
*txr
= bnapi
->tx_ring
;
1919 void __iomem
*db
= txr
->tx_doorbell
;
1920 u16 prod
= txr
->tx_prod
;
1922 /* Sync BD data before updating doorbell */
1925 bnxt_db_write(bp
, db
, DB_KEY_TX
| prod
);
1928 cpr
->cp_raw_cons
= raw_cons
;
1929 /* ACK completion ring before freeing tx ring and producing new
1930 * buffers in rx/agg rings to prevent overflowing the completion
1933 BNXT_CP_DB(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
1936 bnapi
->tx_int(bp
, bnapi
, tx_pkts
);
1938 if (event
& BNXT_RX_EVENT
) {
1939 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
1941 bnxt_db_write(bp
, rxr
->rx_doorbell
, DB_KEY_RX
| rxr
->rx_prod
);
1942 if (event
& BNXT_AGG_EVENT
)
1943 bnxt_db_write(bp
, rxr
->rx_agg_doorbell
,
1944 DB_KEY_RX
| rxr
->rx_agg_prod
);
1949 static int bnxt_poll_nitroa0(struct napi_struct
*napi
, int budget
)
1951 struct bnxt_napi
*bnapi
= container_of(napi
, struct bnxt_napi
, napi
);
1952 struct bnxt
*bp
= bnapi
->bp
;
1953 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1954 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
1955 struct tx_cmp
*txcmp
;
1956 struct rx_cmp_ext
*rxcmp1
;
1957 u32 cp_cons
, tmp_raw_cons
;
1958 u32 raw_cons
= cpr
->cp_raw_cons
;
1965 cp_cons
= RING_CMP(raw_cons
);
1966 txcmp
= &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
1968 if (!TX_CMP_VALID(txcmp
, raw_cons
))
1971 if ((TX_CMP_TYPE(txcmp
) & 0x30) == 0x10) {
1972 tmp_raw_cons
= NEXT_RAW_CMP(raw_cons
);
1973 cp_cons
= RING_CMP(tmp_raw_cons
);
1974 rxcmp1
= (struct rx_cmp_ext
*)
1975 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
1977 if (!RX_CMP_VALID(rxcmp1
, tmp_raw_cons
))
1980 /* force an error to recycle the buffer */
1981 rxcmp1
->rx_cmp_cfa_code_errors_v2
|=
1982 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR
);
1984 rc
= bnxt_rx_pkt(bp
, bnapi
, &raw_cons
, &event
);
1985 if (likely(rc
== -EIO
) && budget
)
1987 else if (rc
== -EBUSY
) /* partial completion */
1989 } else if (unlikely(TX_CMP_TYPE(txcmp
) ==
1990 CMPL_BASE_TYPE_HWRM_DONE
)) {
1991 bnxt_hwrm_handler(bp
, txcmp
);
1994 "Invalid completion received on special ring\n");
1996 raw_cons
= NEXT_RAW_CMP(raw_cons
);
1998 if (rx_pkts
== budget
)
2002 cpr
->cp_raw_cons
= raw_cons
;
2003 BNXT_CP_DB(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
2004 bnxt_db_write(bp
, rxr
->rx_doorbell
, DB_KEY_RX
| rxr
->rx_prod
);
2006 if (event
& BNXT_AGG_EVENT
)
2007 bnxt_db_write(bp
, rxr
->rx_agg_doorbell
,
2008 DB_KEY_RX
| rxr
->rx_agg_prod
);
2010 if (!bnxt_has_work(bp
, cpr
) && rx_pkts
< budget
) {
2011 napi_complete_done(napi
, rx_pkts
);
2012 BNXT_CP_DB_REARM(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
2017 static int bnxt_poll(struct napi_struct
*napi
, int budget
)
2019 struct bnxt_napi
*bnapi
= container_of(napi
, struct bnxt_napi
, napi
);
2020 struct bnxt
*bp
= bnapi
->bp
;
2021 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
2025 work_done
+= bnxt_poll_work(bp
, bnapi
, budget
- work_done
);
2027 if (work_done
>= budget
)
2030 if (!bnxt_has_work(bp
, cpr
)) {
2031 if (napi_complete_done(napi
, work_done
))
2032 BNXT_CP_DB_REARM(cpr
->cp_doorbell
,
2037 if (bp
->flags
& BNXT_FLAG_DIM
) {
2038 struct net_dim_sample dim_sample
;
2040 net_dim_sample(cpr
->event_ctr
,
2044 net_dim(&cpr
->dim
, dim_sample
);
2050 static void bnxt_free_tx_skbs(struct bnxt
*bp
)
2053 struct pci_dev
*pdev
= bp
->pdev
;
2058 max_idx
= bp
->tx_nr_pages
* TX_DESC_CNT
;
2059 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
2060 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
2063 for (j
= 0; j
< max_idx
;) {
2064 struct bnxt_sw_tx_bd
*tx_buf
= &txr
->tx_buf_ring
[j
];
2065 struct sk_buff
*skb
= tx_buf
->skb
;
2075 if (tx_buf
->is_push
) {
2081 dma_unmap_single(&pdev
->dev
,
2082 dma_unmap_addr(tx_buf
, mapping
),
2086 last
= tx_buf
->nr_frags
;
2088 for (k
= 0; k
< last
; k
++, j
++) {
2089 int ring_idx
= j
& bp
->tx_ring_mask
;
2090 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[k
];
2092 tx_buf
= &txr
->tx_buf_ring
[ring_idx
];
2095 dma_unmap_addr(tx_buf
, mapping
),
2096 skb_frag_size(frag
), PCI_DMA_TODEVICE
);
2100 netdev_tx_reset_queue(netdev_get_tx_queue(bp
->dev
, i
));
2104 static void bnxt_free_rx_skbs(struct bnxt
*bp
)
2106 int i
, max_idx
, max_agg_idx
;
2107 struct pci_dev
*pdev
= bp
->pdev
;
2112 max_idx
= bp
->rx_nr_pages
* RX_DESC_CNT
;
2113 max_agg_idx
= bp
->rx_agg_nr_pages
* RX_DESC_CNT
;
2114 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
2115 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
2119 for (j
= 0; j
< MAX_TPA
; j
++) {
2120 struct bnxt_tpa_info
*tpa_info
=
2122 u8
*data
= tpa_info
->data
;
2127 dma_unmap_single_attrs(&pdev
->dev
,
2129 bp
->rx_buf_use_size
,
2131 DMA_ATTR_WEAK_ORDERING
);
2133 tpa_info
->data
= NULL
;
2139 for (j
= 0; j
< max_idx
; j
++) {
2140 struct bnxt_sw_rx_bd
*rx_buf
= &rxr
->rx_buf_ring
[j
];
2141 dma_addr_t mapping
= rx_buf
->mapping
;
2142 void *data
= rx_buf
->data
;
2147 rx_buf
->data
= NULL
;
2149 if (BNXT_RX_PAGE_MODE(bp
)) {
2150 mapping
-= bp
->rx_dma_offset
;
2151 dma_unmap_page_attrs(&pdev
->dev
, mapping
,
2152 PAGE_SIZE
, bp
->rx_dir
,
2153 DMA_ATTR_WEAK_ORDERING
);
2156 dma_unmap_single_attrs(&pdev
->dev
, mapping
,
2157 bp
->rx_buf_use_size
,
2159 DMA_ATTR_WEAK_ORDERING
);
2164 for (j
= 0; j
< max_agg_idx
; j
++) {
2165 struct bnxt_sw_rx_agg_bd
*rx_agg_buf
=
2166 &rxr
->rx_agg_ring
[j
];
2167 struct page
*page
= rx_agg_buf
->page
;
2172 dma_unmap_page_attrs(&pdev
->dev
, rx_agg_buf
->mapping
,
2175 DMA_ATTR_WEAK_ORDERING
);
2177 rx_agg_buf
->page
= NULL
;
2178 __clear_bit(j
, rxr
->rx_agg_bmap
);
2183 __free_page(rxr
->rx_page
);
2184 rxr
->rx_page
= NULL
;
2189 static void bnxt_free_skbs(struct bnxt
*bp
)
2191 bnxt_free_tx_skbs(bp
);
2192 bnxt_free_rx_skbs(bp
);
2195 static void bnxt_free_ring(struct bnxt
*bp
, struct bnxt_ring_struct
*ring
)
2197 struct pci_dev
*pdev
= bp
->pdev
;
2200 for (i
= 0; i
< ring
->nr_pages
; i
++) {
2201 if (!ring
->pg_arr
[i
])
2204 dma_free_coherent(&pdev
->dev
, ring
->page_size
,
2205 ring
->pg_arr
[i
], ring
->dma_arr
[i
]);
2207 ring
->pg_arr
[i
] = NULL
;
2210 dma_free_coherent(&pdev
->dev
, ring
->nr_pages
* 8,
2211 ring
->pg_tbl
, ring
->pg_tbl_map
);
2212 ring
->pg_tbl
= NULL
;
2214 if (ring
->vmem_size
&& *ring
->vmem
) {
2220 static int bnxt_alloc_ring(struct bnxt
*bp
, struct bnxt_ring_struct
*ring
)
2223 struct pci_dev
*pdev
= bp
->pdev
;
2225 if (ring
->nr_pages
> 1) {
2226 ring
->pg_tbl
= dma_alloc_coherent(&pdev
->dev
,
2234 for (i
= 0; i
< ring
->nr_pages
; i
++) {
2235 ring
->pg_arr
[i
] = dma_alloc_coherent(&pdev
->dev
,
2239 if (!ring
->pg_arr
[i
])
2242 if (ring
->nr_pages
> 1)
2243 ring
->pg_tbl
[i
] = cpu_to_le64(ring
->dma_arr
[i
]);
2246 if (ring
->vmem_size
) {
2247 *ring
->vmem
= vzalloc(ring
->vmem_size
);
2254 static void bnxt_free_rx_rings(struct bnxt
*bp
)
2261 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
2262 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
2263 struct bnxt_ring_struct
*ring
;
2266 bpf_prog_put(rxr
->xdp_prog
);
2268 if (xdp_rxq_info_is_reg(&rxr
->xdp_rxq
))
2269 xdp_rxq_info_unreg(&rxr
->xdp_rxq
);
2274 kfree(rxr
->rx_agg_bmap
);
2275 rxr
->rx_agg_bmap
= NULL
;
2277 ring
= &rxr
->rx_ring_struct
;
2278 bnxt_free_ring(bp
, ring
);
2280 ring
= &rxr
->rx_agg_ring_struct
;
2281 bnxt_free_ring(bp
, ring
);
2285 static int bnxt_alloc_rx_rings(struct bnxt
*bp
)
2287 int i
, rc
, agg_rings
= 0, tpa_rings
= 0;
2292 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
)
2295 if (bp
->flags
& BNXT_FLAG_TPA
)
2298 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
2299 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
2300 struct bnxt_ring_struct
*ring
;
2302 ring
= &rxr
->rx_ring_struct
;
2304 rc
= xdp_rxq_info_reg(&rxr
->xdp_rxq
, bp
->dev
, i
);
2308 rc
= bnxt_alloc_ring(bp
, ring
);
2315 ring
= &rxr
->rx_agg_ring_struct
;
2316 rc
= bnxt_alloc_ring(bp
, ring
);
2320 rxr
->rx_agg_bmap_size
= bp
->rx_agg_ring_mask
+ 1;
2321 mem_size
= rxr
->rx_agg_bmap_size
/ 8;
2322 rxr
->rx_agg_bmap
= kzalloc(mem_size
, GFP_KERNEL
);
2323 if (!rxr
->rx_agg_bmap
)
2327 rxr
->rx_tpa
= kcalloc(MAX_TPA
,
2328 sizeof(struct bnxt_tpa_info
),
2338 static void bnxt_free_tx_rings(struct bnxt
*bp
)
2341 struct pci_dev
*pdev
= bp
->pdev
;
2346 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
2347 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
2348 struct bnxt_ring_struct
*ring
;
2351 dma_free_coherent(&pdev
->dev
, bp
->tx_push_size
,
2352 txr
->tx_push
, txr
->tx_push_mapping
);
2353 txr
->tx_push
= NULL
;
2356 ring
= &txr
->tx_ring_struct
;
2358 bnxt_free_ring(bp
, ring
);
2362 static int bnxt_alloc_tx_rings(struct bnxt
*bp
)
2365 struct pci_dev
*pdev
= bp
->pdev
;
2367 bp
->tx_push_size
= 0;
2368 if (bp
->tx_push_thresh
) {
2371 push_size
= L1_CACHE_ALIGN(sizeof(struct tx_push_bd
) +
2372 bp
->tx_push_thresh
);
2374 if (push_size
> 256) {
2376 bp
->tx_push_thresh
= 0;
2379 bp
->tx_push_size
= push_size
;
2382 for (i
= 0, j
= 0; i
< bp
->tx_nr_rings
; i
++) {
2383 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
2384 struct bnxt_ring_struct
*ring
;
2386 ring
= &txr
->tx_ring_struct
;
2388 rc
= bnxt_alloc_ring(bp
, ring
);
2392 if (bp
->tx_push_size
) {
2395 /* One pre-allocated DMA buffer to backup
2398 txr
->tx_push
= dma_alloc_coherent(&pdev
->dev
,
2400 &txr
->tx_push_mapping
,
2406 mapping
= txr
->tx_push_mapping
+
2407 sizeof(struct tx_push_bd
);
2408 txr
->data_mapping
= cpu_to_le64(mapping
);
2410 memset(txr
->tx_push
, 0, sizeof(struct tx_push_bd
));
2412 ring
->queue_id
= bp
->q_info
[j
].queue_id
;
2413 if (i
< bp
->tx_nr_rings_xdp
)
2415 if (i
% bp
->tx_nr_rings_per_tc
== (bp
->tx_nr_rings_per_tc
- 1))
2421 static void bnxt_free_cp_rings(struct bnxt
*bp
)
2428 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2429 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2430 struct bnxt_cp_ring_info
*cpr
;
2431 struct bnxt_ring_struct
*ring
;
2436 cpr
= &bnapi
->cp_ring
;
2437 ring
= &cpr
->cp_ring_struct
;
2439 bnxt_free_ring(bp
, ring
);
2443 static int bnxt_alloc_cp_rings(struct bnxt
*bp
)
2447 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2448 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2449 struct bnxt_cp_ring_info
*cpr
;
2450 struct bnxt_ring_struct
*ring
;
2455 cpr
= &bnapi
->cp_ring
;
2456 ring
= &cpr
->cp_ring_struct
;
2458 rc
= bnxt_alloc_ring(bp
, ring
);
2465 static void bnxt_init_ring_struct(struct bnxt
*bp
)
2469 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2470 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2471 struct bnxt_cp_ring_info
*cpr
;
2472 struct bnxt_rx_ring_info
*rxr
;
2473 struct bnxt_tx_ring_info
*txr
;
2474 struct bnxt_ring_struct
*ring
;
2479 cpr
= &bnapi
->cp_ring
;
2480 ring
= &cpr
->cp_ring_struct
;
2481 ring
->nr_pages
= bp
->cp_nr_pages
;
2482 ring
->page_size
= HW_CMPD_RING_SIZE
;
2483 ring
->pg_arr
= (void **)cpr
->cp_desc_ring
;
2484 ring
->dma_arr
= cpr
->cp_desc_mapping
;
2485 ring
->vmem_size
= 0;
2487 rxr
= bnapi
->rx_ring
;
2491 ring
= &rxr
->rx_ring_struct
;
2492 ring
->nr_pages
= bp
->rx_nr_pages
;
2493 ring
->page_size
= HW_RXBD_RING_SIZE
;
2494 ring
->pg_arr
= (void **)rxr
->rx_desc_ring
;
2495 ring
->dma_arr
= rxr
->rx_desc_mapping
;
2496 ring
->vmem_size
= SW_RXBD_RING_SIZE
* bp
->rx_nr_pages
;
2497 ring
->vmem
= (void **)&rxr
->rx_buf_ring
;
2499 ring
= &rxr
->rx_agg_ring_struct
;
2500 ring
->nr_pages
= bp
->rx_agg_nr_pages
;
2501 ring
->page_size
= HW_RXBD_RING_SIZE
;
2502 ring
->pg_arr
= (void **)rxr
->rx_agg_desc_ring
;
2503 ring
->dma_arr
= rxr
->rx_agg_desc_mapping
;
2504 ring
->vmem_size
= SW_RXBD_AGG_RING_SIZE
* bp
->rx_agg_nr_pages
;
2505 ring
->vmem
= (void **)&rxr
->rx_agg_ring
;
2508 txr
= bnapi
->tx_ring
;
2512 ring
= &txr
->tx_ring_struct
;
2513 ring
->nr_pages
= bp
->tx_nr_pages
;
2514 ring
->page_size
= HW_RXBD_RING_SIZE
;
2515 ring
->pg_arr
= (void **)txr
->tx_desc_ring
;
2516 ring
->dma_arr
= txr
->tx_desc_mapping
;
2517 ring
->vmem_size
= SW_TXBD_RING_SIZE
* bp
->tx_nr_pages
;
2518 ring
->vmem
= (void **)&txr
->tx_buf_ring
;
2522 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct
*ring
, u32 type
)
2526 struct rx_bd
**rx_buf_ring
;
2528 rx_buf_ring
= (struct rx_bd
**)ring
->pg_arr
;
2529 for (i
= 0, prod
= 0; i
< ring
->nr_pages
; i
++) {
2533 rxbd
= rx_buf_ring
[i
];
2537 for (j
= 0; j
< RX_DESC_CNT
; j
++, rxbd
++, prod
++) {
2538 rxbd
->rx_bd_len_flags_type
= cpu_to_le32(type
);
2539 rxbd
->rx_bd_opaque
= prod
;
2544 static int bnxt_init_one_rx_ring(struct bnxt
*bp
, int ring_nr
)
2546 struct net_device
*dev
= bp
->dev
;
2547 struct bnxt_rx_ring_info
*rxr
;
2548 struct bnxt_ring_struct
*ring
;
2552 type
= (bp
->rx_buf_use_size
<< RX_BD_LEN_SHIFT
) |
2553 RX_BD_TYPE_RX_PACKET_BD
| RX_BD_FLAGS_EOP
;
2555 if (NET_IP_ALIGN
== 2)
2556 type
|= RX_BD_FLAGS_SOP
;
2558 rxr
= &bp
->rx_ring
[ring_nr
];
2559 ring
= &rxr
->rx_ring_struct
;
2560 bnxt_init_rxbd_pages(ring
, type
);
2562 if (BNXT_RX_PAGE_MODE(bp
) && bp
->xdp_prog
) {
2563 rxr
->xdp_prog
= bpf_prog_add(bp
->xdp_prog
, 1);
2564 if (IS_ERR(rxr
->xdp_prog
)) {
2565 int rc
= PTR_ERR(rxr
->xdp_prog
);
2567 rxr
->xdp_prog
= NULL
;
2571 prod
= rxr
->rx_prod
;
2572 for (i
= 0; i
< bp
->rx_ring_size
; i
++) {
2573 if (bnxt_alloc_rx_data(bp
, rxr
, prod
, GFP_KERNEL
) != 0) {
2574 netdev_warn(dev
, "init'ed rx ring %d with %d/%d skbs only\n",
2575 ring_nr
, i
, bp
->rx_ring_size
);
2578 prod
= NEXT_RX(prod
);
2580 rxr
->rx_prod
= prod
;
2581 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
2583 ring
= &rxr
->rx_agg_ring_struct
;
2584 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
2586 if (!(bp
->flags
& BNXT_FLAG_AGG_RINGS
))
2589 type
= ((u32
)BNXT_RX_PAGE_SIZE
<< RX_BD_LEN_SHIFT
) |
2590 RX_BD_TYPE_RX_AGG_BD
| RX_BD_FLAGS_SOP
;
2592 bnxt_init_rxbd_pages(ring
, type
);
2594 prod
= rxr
->rx_agg_prod
;
2595 for (i
= 0; i
< bp
->rx_agg_ring_size
; i
++) {
2596 if (bnxt_alloc_rx_page(bp
, rxr
, prod
, GFP_KERNEL
) != 0) {
2597 netdev_warn(dev
, "init'ed rx ring %d with %d/%d pages only\n",
2598 ring_nr
, i
, bp
->rx_ring_size
);
2601 prod
= NEXT_RX_AGG(prod
);
2603 rxr
->rx_agg_prod
= prod
;
2605 if (bp
->flags
& BNXT_FLAG_TPA
) {
2610 for (i
= 0; i
< MAX_TPA
; i
++) {
2611 data
= __bnxt_alloc_rx_data(bp
, &mapping
,
2616 rxr
->rx_tpa
[i
].data
= data
;
2617 rxr
->rx_tpa
[i
].data_ptr
= data
+ bp
->rx_offset
;
2618 rxr
->rx_tpa
[i
].mapping
= mapping
;
2621 netdev_err(bp
->dev
, "No resource allocated for LRO/GRO\n");
2629 static void bnxt_init_cp_rings(struct bnxt
*bp
)
2633 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2634 struct bnxt_cp_ring_info
*cpr
= &bp
->bnapi
[i
]->cp_ring
;
2635 struct bnxt_ring_struct
*ring
= &cpr
->cp_ring_struct
;
2637 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
2638 cpr
->rx_ring_coal
.coal_ticks
= bp
->rx_coal
.coal_ticks
;
2639 cpr
->rx_ring_coal
.coal_bufs
= bp
->rx_coal
.coal_bufs
;
2643 static int bnxt_init_rx_rings(struct bnxt
*bp
)
2647 if (BNXT_RX_PAGE_MODE(bp
)) {
2648 bp
->rx_offset
= NET_IP_ALIGN
+ XDP_PACKET_HEADROOM
;
2649 bp
->rx_dma_offset
= XDP_PACKET_HEADROOM
;
2651 bp
->rx_offset
= BNXT_RX_OFFSET
;
2652 bp
->rx_dma_offset
= BNXT_RX_DMA_OFFSET
;
2655 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
2656 rc
= bnxt_init_one_rx_ring(bp
, i
);
2664 static int bnxt_init_tx_rings(struct bnxt
*bp
)
2668 bp
->tx_wake_thresh
= max_t(int, bp
->tx_ring_size
/ 2,
2671 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
2672 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
2673 struct bnxt_ring_struct
*ring
= &txr
->tx_ring_struct
;
2675 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
2681 static void bnxt_free_ring_grps(struct bnxt
*bp
)
2683 kfree(bp
->grp_info
);
2684 bp
->grp_info
= NULL
;
2687 static int bnxt_init_ring_grps(struct bnxt
*bp
, bool irq_re_init
)
2692 bp
->grp_info
= kcalloc(bp
->cp_nr_rings
,
2693 sizeof(struct bnxt_ring_grp_info
),
2698 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2700 bp
->grp_info
[i
].fw_stats_ctx
= INVALID_HW_RING_ID
;
2701 bp
->grp_info
[i
].fw_grp_id
= INVALID_HW_RING_ID
;
2702 bp
->grp_info
[i
].rx_fw_ring_id
= INVALID_HW_RING_ID
;
2703 bp
->grp_info
[i
].agg_fw_ring_id
= INVALID_HW_RING_ID
;
2704 bp
->grp_info
[i
].cp_fw_ring_id
= INVALID_HW_RING_ID
;
2709 static void bnxt_free_vnics(struct bnxt
*bp
)
2711 kfree(bp
->vnic_info
);
2712 bp
->vnic_info
= NULL
;
2716 static int bnxt_alloc_vnics(struct bnxt
*bp
)
2720 #ifdef CONFIG_RFS_ACCEL
2721 if (bp
->flags
& BNXT_FLAG_RFS
)
2722 num_vnics
+= bp
->rx_nr_rings
;
2725 if (BNXT_CHIP_TYPE_NITRO_A0(bp
))
2728 bp
->vnic_info
= kcalloc(num_vnics
, sizeof(struct bnxt_vnic_info
),
2733 bp
->nr_vnics
= num_vnics
;
2737 static void bnxt_init_vnics(struct bnxt
*bp
)
2741 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
2742 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[i
];
2744 vnic
->fw_vnic_id
= INVALID_HW_RING_ID
;
2745 vnic
->fw_rss_cos_lb_ctx
[0] = INVALID_HW_RING_ID
;
2746 vnic
->fw_rss_cos_lb_ctx
[1] = INVALID_HW_RING_ID
;
2747 vnic
->fw_l2_ctx_id
= INVALID_HW_RING_ID
;
2749 if (bp
->vnic_info
[i
].rss_hash_key
) {
2751 prandom_bytes(vnic
->rss_hash_key
,
2754 memcpy(vnic
->rss_hash_key
,
2755 bp
->vnic_info
[0].rss_hash_key
,
2761 static int bnxt_calc_nr_ring_pages(u32 ring_size
, int desc_per_pg
)
2765 pages
= ring_size
/ desc_per_pg
;
2772 while (pages
& (pages
- 1))
2778 void bnxt_set_tpa_flags(struct bnxt
*bp
)
2780 bp
->flags
&= ~BNXT_FLAG_TPA
;
2781 if (bp
->flags
& BNXT_FLAG_NO_AGG_RINGS
)
2783 if (bp
->dev
->features
& NETIF_F_LRO
)
2784 bp
->flags
|= BNXT_FLAG_LRO
;
2785 else if (bp
->dev
->features
& NETIF_F_GRO_HW
)
2786 bp
->flags
|= BNXT_FLAG_GRO
;
2789 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2792 void bnxt_set_ring_params(struct bnxt
*bp
)
2794 u32 ring_size
, rx_size
, rx_space
;
2795 u32 agg_factor
= 0, agg_ring_size
= 0;
2797 /* 8 for CRC and VLAN */
2798 rx_size
= SKB_DATA_ALIGN(bp
->dev
->mtu
+ ETH_HLEN
+ NET_IP_ALIGN
+ 8);
2800 rx_space
= rx_size
+ NET_SKB_PAD
+
2801 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
2803 bp
->rx_copy_thresh
= BNXT_RX_COPY_THRESH
;
2804 ring_size
= bp
->rx_ring_size
;
2805 bp
->rx_agg_ring_size
= 0;
2806 bp
->rx_agg_nr_pages
= 0;
2808 if (bp
->flags
& BNXT_FLAG_TPA
)
2809 agg_factor
= min_t(u32
, 4, 65536 / BNXT_RX_PAGE_SIZE
);
2811 bp
->flags
&= ~BNXT_FLAG_JUMBO
;
2812 if (rx_space
> PAGE_SIZE
&& !(bp
->flags
& BNXT_FLAG_NO_AGG_RINGS
)) {
2815 bp
->flags
|= BNXT_FLAG_JUMBO
;
2816 jumbo_factor
= PAGE_ALIGN(bp
->dev
->mtu
- 40) >> PAGE_SHIFT
;
2817 if (jumbo_factor
> agg_factor
)
2818 agg_factor
= jumbo_factor
;
2820 agg_ring_size
= ring_size
* agg_factor
;
2822 if (agg_ring_size
) {
2823 bp
->rx_agg_nr_pages
= bnxt_calc_nr_ring_pages(agg_ring_size
,
2825 if (bp
->rx_agg_nr_pages
> MAX_RX_AGG_PAGES
) {
2826 u32 tmp
= agg_ring_size
;
2828 bp
->rx_agg_nr_pages
= MAX_RX_AGG_PAGES
;
2829 agg_ring_size
= MAX_RX_AGG_PAGES
* RX_DESC_CNT
- 1;
2830 netdev_warn(bp
->dev
, "rx agg ring size %d reduced to %d.\n",
2831 tmp
, agg_ring_size
);
2833 bp
->rx_agg_ring_size
= agg_ring_size
;
2834 bp
->rx_agg_ring_mask
= (bp
->rx_agg_nr_pages
* RX_DESC_CNT
) - 1;
2835 rx_size
= SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH
+ NET_IP_ALIGN
);
2836 rx_space
= rx_size
+ NET_SKB_PAD
+
2837 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
2840 bp
->rx_buf_use_size
= rx_size
;
2841 bp
->rx_buf_size
= rx_space
;
2843 bp
->rx_nr_pages
= bnxt_calc_nr_ring_pages(ring_size
, RX_DESC_CNT
);
2844 bp
->rx_ring_mask
= (bp
->rx_nr_pages
* RX_DESC_CNT
) - 1;
2846 ring_size
= bp
->tx_ring_size
;
2847 bp
->tx_nr_pages
= bnxt_calc_nr_ring_pages(ring_size
, TX_DESC_CNT
);
2848 bp
->tx_ring_mask
= (bp
->tx_nr_pages
* TX_DESC_CNT
) - 1;
2850 ring_size
= bp
->rx_ring_size
* (2 + agg_factor
) + bp
->tx_ring_size
;
2851 bp
->cp_ring_size
= ring_size
;
2853 bp
->cp_nr_pages
= bnxt_calc_nr_ring_pages(ring_size
, CP_DESC_CNT
);
2854 if (bp
->cp_nr_pages
> MAX_CP_PAGES
) {
2855 bp
->cp_nr_pages
= MAX_CP_PAGES
;
2856 bp
->cp_ring_size
= MAX_CP_PAGES
* CP_DESC_CNT
- 1;
2857 netdev_warn(bp
->dev
, "completion ring size %d reduced to %d.\n",
2858 ring_size
, bp
->cp_ring_size
);
2860 bp
->cp_bit
= bp
->cp_nr_pages
* CP_DESC_CNT
;
2861 bp
->cp_ring_mask
= bp
->cp_bit
- 1;
2864 /* Changing allocation mode of RX rings.
2865 * TODO: Update when extending xdp_rxq_info to support allocation modes.
2867 int bnxt_set_rx_skb_mode(struct bnxt
*bp
, bool page_mode
)
2870 if (bp
->dev
->mtu
> BNXT_MAX_PAGE_MODE_MTU
)
2873 min_t(u16
, bp
->max_mtu
, BNXT_MAX_PAGE_MODE_MTU
);
2874 bp
->flags
&= ~BNXT_FLAG_AGG_RINGS
;
2875 bp
->flags
|= BNXT_FLAG_NO_AGG_RINGS
| BNXT_FLAG_RX_PAGE_MODE
;
2876 bp
->rx_dir
= DMA_BIDIRECTIONAL
;
2877 bp
->rx_skb_func
= bnxt_rx_page_skb
;
2878 /* Disable LRO or GRO_HW */
2879 netdev_update_features(bp
->dev
);
2881 bp
->dev
->max_mtu
= bp
->max_mtu
;
2882 bp
->flags
&= ~BNXT_FLAG_RX_PAGE_MODE
;
2883 bp
->rx_dir
= DMA_FROM_DEVICE
;
2884 bp
->rx_skb_func
= bnxt_rx_skb
;
2889 static void bnxt_free_vnic_attributes(struct bnxt
*bp
)
2892 struct bnxt_vnic_info
*vnic
;
2893 struct pci_dev
*pdev
= bp
->pdev
;
2898 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
2899 vnic
= &bp
->vnic_info
[i
];
2901 kfree(vnic
->fw_grp_ids
);
2902 vnic
->fw_grp_ids
= NULL
;
2904 kfree(vnic
->uc_list
);
2905 vnic
->uc_list
= NULL
;
2907 if (vnic
->mc_list
) {
2908 dma_free_coherent(&pdev
->dev
, vnic
->mc_list_size
,
2909 vnic
->mc_list
, vnic
->mc_list_mapping
);
2910 vnic
->mc_list
= NULL
;
2913 if (vnic
->rss_table
) {
2914 dma_free_coherent(&pdev
->dev
, PAGE_SIZE
,
2916 vnic
->rss_table_dma_addr
);
2917 vnic
->rss_table
= NULL
;
2920 vnic
->rss_hash_key
= NULL
;
2925 static int bnxt_alloc_vnic_attributes(struct bnxt
*bp
)
2927 int i
, rc
= 0, size
;
2928 struct bnxt_vnic_info
*vnic
;
2929 struct pci_dev
*pdev
= bp
->pdev
;
2932 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
2933 vnic
= &bp
->vnic_info
[i
];
2935 if (vnic
->flags
& BNXT_VNIC_UCAST_FLAG
) {
2936 int mem_size
= (BNXT_MAX_UC_ADDRS
- 1) * ETH_ALEN
;
2939 vnic
->uc_list
= kmalloc(mem_size
, GFP_KERNEL
);
2940 if (!vnic
->uc_list
) {
2947 if (vnic
->flags
& BNXT_VNIC_MCAST_FLAG
) {
2948 vnic
->mc_list_size
= BNXT_MAX_MC_ADDRS
* ETH_ALEN
;
2950 dma_alloc_coherent(&pdev
->dev
,
2952 &vnic
->mc_list_mapping
,
2954 if (!vnic
->mc_list
) {
2960 if (vnic
->flags
& BNXT_VNIC_RSS_FLAG
)
2961 max_rings
= bp
->rx_nr_rings
;
2965 vnic
->fw_grp_ids
= kcalloc(max_rings
, sizeof(u16
), GFP_KERNEL
);
2966 if (!vnic
->fw_grp_ids
) {
2971 if ((bp
->flags
& BNXT_FLAG_NEW_RSS_CAP
) &&
2972 !(vnic
->flags
& BNXT_VNIC_RSS_FLAG
))
2975 /* Allocate rss table and hash key */
2976 vnic
->rss_table
= dma_alloc_coherent(&pdev
->dev
, PAGE_SIZE
,
2977 &vnic
->rss_table_dma_addr
,
2979 if (!vnic
->rss_table
) {
2984 size
= L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE
* sizeof(u16
));
2986 vnic
->rss_hash_key
= ((void *)vnic
->rss_table
) + size
;
2987 vnic
->rss_hash_key_dma_addr
= vnic
->rss_table_dma_addr
+ size
;
2995 static void bnxt_free_hwrm_resources(struct bnxt
*bp
)
2997 struct pci_dev
*pdev
= bp
->pdev
;
2999 dma_free_coherent(&pdev
->dev
, PAGE_SIZE
, bp
->hwrm_cmd_resp_addr
,
3000 bp
->hwrm_cmd_resp_dma_addr
);
3002 bp
->hwrm_cmd_resp_addr
= NULL
;
3003 if (bp
->hwrm_dbg_resp_addr
) {
3004 dma_free_coherent(&pdev
->dev
, HWRM_DBG_REG_BUF_SIZE
,
3005 bp
->hwrm_dbg_resp_addr
,
3006 bp
->hwrm_dbg_resp_dma_addr
);
3008 bp
->hwrm_dbg_resp_addr
= NULL
;
3012 static int bnxt_alloc_hwrm_resources(struct bnxt
*bp
)
3014 struct pci_dev
*pdev
= bp
->pdev
;
3016 bp
->hwrm_cmd_resp_addr
= dma_alloc_coherent(&pdev
->dev
, PAGE_SIZE
,
3017 &bp
->hwrm_cmd_resp_dma_addr
,
3019 if (!bp
->hwrm_cmd_resp_addr
)
3021 bp
->hwrm_dbg_resp_addr
= dma_alloc_coherent(&pdev
->dev
,
3022 HWRM_DBG_REG_BUF_SIZE
,
3023 &bp
->hwrm_dbg_resp_dma_addr
,
3025 if (!bp
->hwrm_dbg_resp_addr
)
3026 netdev_warn(bp
->dev
, "fail to alloc debug register dma mem\n");
3031 static void bnxt_free_hwrm_short_cmd_req(struct bnxt
*bp
)
3033 if (bp
->hwrm_short_cmd_req_addr
) {
3034 struct pci_dev
*pdev
= bp
->pdev
;
3036 dma_free_coherent(&pdev
->dev
, BNXT_HWRM_MAX_REQ_LEN
,
3037 bp
->hwrm_short_cmd_req_addr
,
3038 bp
->hwrm_short_cmd_req_dma_addr
);
3039 bp
->hwrm_short_cmd_req_addr
= NULL
;
3043 static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt
*bp
)
3045 struct pci_dev
*pdev
= bp
->pdev
;
3047 bp
->hwrm_short_cmd_req_addr
=
3048 dma_alloc_coherent(&pdev
->dev
, BNXT_HWRM_MAX_REQ_LEN
,
3049 &bp
->hwrm_short_cmd_req_dma_addr
,
3051 if (!bp
->hwrm_short_cmd_req_addr
)
3057 static void bnxt_free_stats(struct bnxt
*bp
)
3060 struct pci_dev
*pdev
= bp
->pdev
;
3062 if (bp
->hw_rx_port_stats
) {
3063 dma_free_coherent(&pdev
->dev
, bp
->hw_port_stats_size
,
3064 bp
->hw_rx_port_stats
,
3065 bp
->hw_rx_port_stats_map
);
3066 bp
->hw_rx_port_stats
= NULL
;
3067 bp
->flags
&= ~BNXT_FLAG_PORT_STATS
;
3073 size
= sizeof(struct ctx_hw_stats
);
3075 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3076 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3077 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3079 if (cpr
->hw_stats
) {
3080 dma_free_coherent(&pdev
->dev
, size
, cpr
->hw_stats
,
3082 cpr
->hw_stats
= NULL
;
3087 static int bnxt_alloc_stats(struct bnxt
*bp
)
3090 struct pci_dev
*pdev
= bp
->pdev
;
3092 size
= sizeof(struct ctx_hw_stats
);
3094 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3095 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3096 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3098 cpr
->hw_stats
= dma_alloc_coherent(&pdev
->dev
, size
,
3104 cpr
->hw_stats_ctx_id
= INVALID_STATS_CTX_ID
;
3107 if (BNXT_PF(bp
) && bp
->chip_num
!= CHIP_NUM_58700
) {
3108 bp
->hw_port_stats_size
= sizeof(struct rx_port_stats
) +
3109 sizeof(struct tx_port_stats
) + 1024;
3111 bp
->hw_rx_port_stats
=
3112 dma_alloc_coherent(&pdev
->dev
, bp
->hw_port_stats_size
,
3113 &bp
->hw_rx_port_stats_map
,
3115 if (!bp
->hw_rx_port_stats
)
3118 bp
->hw_tx_port_stats
= (void *)(bp
->hw_rx_port_stats
+ 1) +
3120 bp
->hw_tx_port_stats_map
= bp
->hw_rx_port_stats_map
+
3121 sizeof(struct rx_port_stats
) + 512;
3122 bp
->flags
|= BNXT_FLAG_PORT_STATS
;
3127 static void bnxt_clear_ring_indices(struct bnxt
*bp
)
3134 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3135 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3136 struct bnxt_cp_ring_info
*cpr
;
3137 struct bnxt_rx_ring_info
*rxr
;
3138 struct bnxt_tx_ring_info
*txr
;
3143 cpr
= &bnapi
->cp_ring
;
3144 cpr
->cp_raw_cons
= 0;
3146 txr
= bnapi
->tx_ring
;
3152 rxr
= bnapi
->rx_ring
;
3155 rxr
->rx_agg_prod
= 0;
3156 rxr
->rx_sw_agg_prod
= 0;
3157 rxr
->rx_next_cons
= 0;
3162 static void bnxt_free_ntp_fltrs(struct bnxt
*bp
, bool irq_reinit
)
3164 #ifdef CONFIG_RFS_ACCEL
3167 /* Under rtnl_lock and all our NAPIs have been disabled. It's
3168 * safe to delete the hash table.
3170 for (i
= 0; i
< BNXT_NTP_FLTR_HASH_SIZE
; i
++) {
3171 struct hlist_head
*head
;
3172 struct hlist_node
*tmp
;
3173 struct bnxt_ntuple_filter
*fltr
;
3175 head
= &bp
->ntp_fltr_hash_tbl
[i
];
3176 hlist_for_each_entry_safe(fltr
, tmp
, head
, hash
) {
3177 hlist_del(&fltr
->hash
);
3182 kfree(bp
->ntp_fltr_bmap
);
3183 bp
->ntp_fltr_bmap
= NULL
;
3185 bp
->ntp_fltr_count
= 0;
3189 static int bnxt_alloc_ntp_fltrs(struct bnxt
*bp
)
3191 #ifdef CONFIG_RFS_ACCEL
3194 if (!(bp
->flags
& BNXT_FLAG_RFS
))
3197 for (i
= 0; i
< BNXT_NTP_FLTR_HASH_SIZE
; i
++)
3198 INIT_HLIST_HEAD(&bp
->ntp_fltr_hash_tbl
[i
]);
3200 bp
->ntp_fltr_count
= 0;
3201 bp
->ntp_fltr_bmap
= kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR
),
3205 if (!bp
->ntp_fltr_bmap
)
3214 static void bnxt_free_mem(struct bnxt
*bp
, bool irq_re_init
)
3216 bnxt_free_vnic_attributes(bp
);
3217 bnxt_free_tx_rings(bp
);
3218 bnxt_free_rx_rings(bp
);
3219 bnxt_free_cp_rings(bp
);
3220 bnxt_free_ntp_fltrs(bp
, irq_re_init
);
3222 bnxt_free_stats(bp
);
3223 bnxt_free_ring_grps(bp
);
3224 bnxt_free_vnics(bp
);
3225 kfree(bp
->tx_ring_map
);
3226 bp
->tx_ring_map
= NULL
;
3234 bnxt_clear_ring_indices(bp
);
3238 static int bnxt_alloc_mem(struct bnxt
*bp
, bool irq_re_init
)
3240 int i
, j
, rc
, size
, arr_size
;
3244 /* Allocate bnapi mem pointer array and mem block for
3247 arr_size
= L1_CACHE_ALIGN(sizeof(struct bnxt_napi
*) *
3249 size
= L1_CACHE_ALIGN(sizeof(struct bnxt_napi
));
3250 bnapi
= kzalloc(arr_size
+ size
* bp
->cp_nr_rings
, GFP_KERNEL
);
3256 for (i
= 0; i
< bp
->cp_nr_rings
; i
++, bnapi
+= size
) {
3257 bp
->bnapi
[i
] = bnapi
;
3258 bp
->bnapi
[i
]->index
= i
;
3259 bp
->bnapi
[i
]->bp
= bp
;
3262 bp
->rx_ring
= kcalloc(bp
->rx_nr_rings
,
3263 sizeof(struct bnxt_rx_ring_info
),
3268 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3269 bp
->rx_ring
[i
].bnapi
= bp
->bnapi
[i
];
3270 bp
->bnapi
[i
]->rx_ring
= &bp
->rx_ring
[i
];
3273 bp
->tx_ring
= kcalloc(bp
->tx_nr_rings
,
3274 sizeof(struct bnxt_tx_ring_info
),
3279 bp
->tx_ring_map
= kcalloc(bp
->tx_nr_rings
, sizeof(u16
),
3282 if (!bp
->tx_ring_map
)
3285 if (bp
->flags
& BNXT_FLAG_SHARED_RINGS
)
3288 j
= bp
->rx_nr_rings
;
3290 for (i
= 0; i
< bp
->tx_nr_rings
; i
++, j
++) {
3291 bp
->tx_ring
[i
].bnapi
= bp
->bnapi
[j
];
3292 bp
->bnapi
[j
]->tx_ring
= &bp
->tx_ring
[i
];
3293 bp
->tx_ring_map
[i
] = bp
->tx_nr_rings_xdp
+ i
;
3294 if (i
>= bp
->tx_nr_rings_xdp
) {
3295 bp
->tx_ring
[i
].txq_index
= i
-
3296 bp
->tx_nr_rings_xdp
;
3297 bp
->bnapi
[j
]->tx_int
= bnxt_tx_int
;
3299 bp
->bnapi
[j
]->flags
|= BNXT_NAPI_FLAG_XDP
;
3300 bp
->bnapi
[j
]->tx_int
= bnxt_tx_int_xdp
;
3304 rc
= bnxt_alloc_stats(bp
);
3308 rc
= bnxt_alloc_ntp_fltrs(bp
);
3312 rc
= bnxt_alloc_vnics(bp
);
3317 bnxt_init_ring_struct(bp
);
3319 rc
= bnxt_alloc_rx_rings(bp
);
3323 rc
= bnxt_alloc_tx_rings(bp
);
3327 rc
= bnxt_alloc_cp_rings(bp
);
3331 bp
->vnic_info
[0].flags
|= BNXT_VNIC_RSS_FLAG
| BNXT_VNIC_MCAST_FLAG
|
3332 BNXT_VNIC_UCAST_FLAG
;
3333 rc
= bnxt_alloc_vnic_attributes(bp
);
3339 bnxt_free_mem(bp
, true);
3343 static void bnxt_disable_int(struct bnxt
*bp
)
3350 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3351 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3352 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3353 struct bnxt_ring_struct
*ring
= &cpr
->cp_ring_struct
;
3355 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
)
3356 BNXT_CP_DB(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
3360 static void bnxt_disable_int_sync(struct bnxt
*bp
)
3364 atomic_inc(&bp
->intr_sem
);
3366 bnxt_disable_int(bp
);
3367 for (i
= 0; i
< bp
->cp_nr_rings
; i
++)
3368 synchronize_irq(bp
->irq_tbl
[i
].vector
);
3371 static void bnxt_enable_int(struct bnxt
*bp
)
3375 atomic_set(&bp
->intr_sem
, 0);
3376 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3377 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3378 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3380 BNXT_CP_DB_REARM(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
3384 void bnxt_hwrm_cmd_hdr_init(struct bnxt
*bp
, void *request
, u16 req_type
,
3385 u16 cmpl_ring
, u16 target_id
)
3387 struct input
*req
= request
;
3389 req
->req_type
= cpu_to_le16(req_type
);
3390 req
->cmpl_ring
= cpu_to_le16(cmpl_ring
);
3391 req
->target_id
= cpu_to_le16(target_id
);
3392 req
->resp_addr
= cpu_to_le64(bp
->hwrm_cmd_resp_dma_addr
);
3395 static int bnxt_hwrm_do_send_msg(struct bnxt
*bp
, void *msg
, u32 msg_len
,
3396 int timeout
, bool silent
)
3398 int i
, intr_process
, rc
, tmo_count
;
3399 struct input
*req
= msg
;
3401 __le32
*resp_len
, *valid
;
3402 u16 cp_ring_id
, len
= 0;
3403 struct hwrm_err_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3404 u16 max_req_len
= BNXT_HWRM_MAX_REQ_LEN
;
3405 struct hwrm_short_input short_input
= {0};
3407 req
->seq_id
= cpu_to_le16(bp
->hwrm_cmd_seq
++);
3408 memset(resp
, 0, PAGE_SIZE
);
3409 cp_ring_id
= le16_to_cpu(req
->cmpl_ring
);
3410 intr_process
= (cp_ring_id
== INVALID_HW_RING_ID
) ? 0 : 1;
3412 if (bp
->flags
& BNXT_FLAG_SHORT_CMD
) {
3413 void *short_cmd_req
= bp
->hwrm_short_cmd_req_addr
;
3415 memcpy(short_cmd_req
, req
, msg_len
);
3416 memset(short_cmd_req
+ msg_len
, 0, BNXT_HWRM_MAX_REQ_LEN
-
3419 short_input
.req_type
= req
->req_type
;
3420 short_input
.signature
=
3421 cpu_to_le16(SHORT_REQ_SIGNATURE_SHORT_CMD
);
3422 short_input
.size
= cpu_to_le16(msg_len
);
3423 short_input
.req_addr
=
3424 cpu_to_le64(bp
->hwrm_short_cmd_req_dma_addr
);
3426 data
= (u32
*)&short_input
;
3427 msg_len
= sizeof(short_input
);
3429 /* Sync memory write before updating doorbell */
3432 max_req_len
= BNXT_HWRM_SHORT_REQ_LEN
;
3435 /* Write request msg to hwrm channel */
3436 __iowrite32_copy(bp
->bar0
, data
, msg_len
/ 4);
3438 for (i
= msg_len
; i
< max_req_len
; i
+= 4)
3439 writel(0, bp
->bar0
+ i
);
3441 /* currently supports only one outstanding message */
3443 bp
->hwrm_intr_seq_id
= le16_to_cpu(req
->seq_id
);
3445 /* Ring channel doorbell */
3446 writel(1, bp
->bar0
+ 0x100);
3449 timeout
= DFLT_HWRM_CMD_TIMEOUT
;
3452 tmo_count
= timeout
* 40;
3454 /* Wait until hwrm response cmpl interrupt is processed */
3455 while (bp
->hwrm_intr_seq_id
!= HWRM_SEQ_ID_INVALID
&&
3457 usleep_range(25, 40);
3460 if (bp
->hwrm_intr_seq_id
!= HWRM_SEQ_ID_INVALID
) {
3461 netdev_err(bp
->dev
, "Resp cmpl intr err msg: 0x%x\n",
3462 le16_to_cpu(req
->req_type
));
3466 /* Check if response len is updated */
3467 resp_len
= bp
->hwrm_cmd_resp_addr
+ HWRM_RESP_LEN_OFFSET
;
3468 for (i
= 0; i
< tmo_count
; i
++) {
3469 len
= (le32_to_cpu(*resp_len
) & HWRM_RESP_LEN_MASK
) >>
3473 usleep_range(25, 40);
3476 if (i
>= tmo_count
) {
3477 netdev_err(bp
->dev
, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
3478 timeout
, le16_to_cpu(req
->req_type
),
3479 le16_to_cpu(req
->seq_id
), len
);
3483 /* Last word of resp contains valid bit */
3484 valid
= bp
->hwrm_cmd_resp_addr
+ len
- 4;
3485 for (i
= 0; i
< 5; i
++) {
3486 if (le32_to_cpu(*valid
) & HWRM_RESP_VALID_MASK
)
3492 netdev_err(bp
->dev
, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
3493 timeout
, le16_to_cpu(req
->req_type
),
3494 le16_to_cpu(req
->seq_id
), len
, *valid
);
3499 rc
= le16_to_cpu(resp
->error_code
);
3501 netdev_err(bp
->dev
, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
3502 le16_to_cpu(resp
->req_type
),
3503 le16_to_cpu(resp
->seq_id
), rc
);
3507 int _hwrm_send_message(struct bnxt
*bp
, void *msg
, u32 msg_len
, int timeout
)
3509 return bnxt_hwrm_do_send_msg(bp
, msg
, msg_len
, timeout
, false);
3512 int _hwrm_send_message_silent(struct bnxt
*bp
, void *msg
, u32 msg_len
,
3515 return bnxt_hwrm_do_send_msg(bp
, msg
, msg_len
, timeout
, true);
3518 int hwrm_send_message(struct bnxt
*bp
, void *msg
, u32 msg_len
, int timeout
)
3522 mutex_lock(&bp
->hwrm_cmd_lock
);
3523 rc
= _hwrm_send_message(bp
, msg
, msg_len
, timeout
);
3524 mutex_unlock(&bp
->hwrm_cmd_lock
);
3528 int hwrm_send_message_silent(struct bnxt
*bp
, void *msg
, u32 msg_len
,
3533 mutex_lock(&bp
->hwrm_cmd_lock
);
3534 rc
= bnxt_hwrm_do_send_msg(bp
, msg
, msg_len
, timeout
, true);
3535 mutex_unlock(&bp
->hwrm_cmd_lock
);
3539 int bnxt_hwrm_func_rgtr_async_events(struct bnxt
*bp
, unsigned long *bmap
,
3542 struct hwrm_func_drv_rgtr_input req
= {0};
3543 DECLARE_BITMAP(async_events_bmap
, 256);
3544 u32
*events
= (u32
*)async_events_bmap
;
3547 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_DRV_RGTR
, -1, -1);
3550 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD
);
3552 memset(async_events_bmap
, 0, sizeof(async_events_bmap
));
3553 for (i
= 0; i
< ARRAY_SIZE(bnxt_async_events_arr
); i
++)
3554 __set_bit(bnxt_async_events_arr
[i
], async_events_bmap
);
3556 if (bmap
&& bmap_size
) {
3557 for (i
= 0; i
< bmap_size
; i
++) {
3558 if (test_bit(i
, bmap
))
3559 __set_bit(i
, async_events_bmap
);
3563 for (i
= 0; i
< 8; i
++)
3564 req
.async_event_fwd
[i
] |= cpu_to_le32(events
[i
]);
3566 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3569 static int bnxt_hwrm_func_drv_rgtr(struct bnxt
*bp
)
3571 struct hwrm_func_drv_rgtr_input req
= {0};
3573 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_DRV_RGTR
, -1, -1);
3576 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE
|
3577 FUNC_DRV_RGTR_REQ_ENABLES_VER
);
3579 req
.os_type
= cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX
);
3580 req
.ver_maj
= DRV_VER_MAJ
;
3581 req
.ver_min
= DRV_VER_MIN
;
3582 req
.ver_upd
= DRV_VER_UPD
;
3588 memset(data
, 0, sizeof(data
));
3589 for (i
= 0; i
< ARRAY_SIZE(bnxt_vf_req_snif
); i
++) {
3590 u16 cmd
= bnxt_vf_req_snif
[i
];
3591 unsigned int bit
, idx
;
3595 data
[idx
] |= 1 << bit
;
3598 for (i
= 0; i
< 8; i
++)
3599 req
.vf_req_fwd
[i
] = cpu_to_le32(data
[i
]);
3602 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD
);
3605 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3608 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt
*bp
)
3610 struct hwrm_func_drv_unrgtr_input req
= {0};
3612 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_DRV_UNRGTR
, -1, -1);
3613 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3616 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt
*bp
, u8 tunnel_type
)
3619 struct hwrm_tunnel_dst_port_free_input req
= {0};
3621 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_TUNNEL_DST_PORT_FREE
, -1, -1);
3622 req
.tunnel_type
= tunnel_type
;
3624 switch (tunnel_type
) {
3625 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
:
3626 req
.tunnel_dst_port_id
= bp
->vxlan_fw_dst_port_id
;
3628 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
:
3629 req
.tunnel_dst_port_id
= bp
->nge_fw_dst_port_id
;
3635 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3637 netdev_err(bp
->dev
, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
3642 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt
*bp
, __be16 port
,
3646 struct hwrm_tunnel_dst_port_alloc_input req
= {0};
3647 struct hwrm_tunnel_dst_port_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3649 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_TUNNEL_DST_PORT_ALLOC
, -1, -1);
3651 req
.tunnel_type
= tunnel_type
;
3652 req
.tunnel_dst_port_val
= port
;
3654 mutex_lock(&bp
->hwrm_cmd_lock
);
3655 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3657 netdev_err(bp
->dev
, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
3662 switch (tunnel_type
) {
3663 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN
:
3664 bp
->vxlan_fw_dst_port_id
= resp
->tunnel_dst_port_id
;
3666 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE
:
3667 bp
->nge_fw_dst_port_id
= resp
->tunnel_dst_port_id
;
3674 mutex_unlock(&bp
->hwrm_cmd_lock
);
3678 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt
*bp
, u16 vnic_id
)
3680 struct hwrm_cfa_l2_set_rx_mask_input req
= {0};
3681 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
3683 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_L2_SET_RX_MASK
, -1, -1);
3684 req
.vnic_id
= cpu_to_le32(vnic
->fw_vnic_id
);
3686 req
.num_mc_entries
= cpu_to_le32(vnic
->mc_list_count
);
3687 req
.mc_tbl_addr
= cpu_to_le64(vnic
->mc_list_mapping
);
3688 req
.mask
= cpu_to_le32(vnic
->rx_mask
);
3689 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3692 #ifdef CONFIG_RFS_ACCEL
3693 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt
*bp
,
3694 struct bnxt_ntuple_filter
*fltr
)
3696 struct hwrm_cfa_ntuple_filter_free_input req
= {0};
3698 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_NTUPLE_FILTER_FREE
, -1, -1);
3699 req
.ntuple_filter_id
= fltr
->filter_id
;
3700 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3703 #define BNXT_NTP_FLTR_FLAGS \
3704 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
3705 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
3706 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
3707 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
3708 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
3709 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
3710 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
3711 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
3712 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
3713 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
3714 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
3715 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
3716 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
3717 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
3719 #define BNXT_NTP_TUNNEL_FLTR_FLAG \
3720 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE
3722 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt
*bp
,
3723 struct bnxt_ntuple_filter
*fltr
)
3726 struct hwrm_cfa_ntuple_filter_alloc_input req
= {0};
3727 struct hwrm_cfa_ntuple_filter_alloc_output
*resp
=
3728 bp
->hwrm_cmd_resp_addr
;
3729 struct flow_keys
*keys
= &fltr
->fkeys
;
3730 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[fltr
->rxq
+ 1];
3732 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_NTUPLE_FILTER_ALLOC
, -1, -1);
3733 req
.l2_filter_id
= bp
->vnic_info
[0].fw_l2_filter_id
[fltr
->l2_fltr_idx
];
3735 req
.enables
= cpu_to_le32(BNXT_NTP_FLTR_FLAGS
);
3737 req
.ethertype
= htons(ETH_P_IP
);
3738 memcpy(req
.src_macaddr
, fltr
->src_mac_addr
, ETH_ALEN
);
3739 req
.ip_addr_type
= CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4
;
3740 req
.ip_protocol
= keys
->basic
.ip_proto
;
3742 if (keys
->basic
.n_proto
== htons(ETH_P_IPV6
)) {
3745 req
.ethertype
= htons(ETH_P_IPV6
);
3747 CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6
;
3748 *(struct in6_addr
*)&req
.src_ipaddr
[0] =
3749 keys
->addrs
.v6addrs
.src
;
3750 *(struct in6_addr
*)&req
.dst_ipaddr
[0] =
3751 keys
->addrs
.v6addrs
.dst
;
3752 for (i
= 0; i
< 4; i
++) {
3753 req
.src_ipaddr_mask
[i
] = cpu_to_be32(0xffffffff);
3754 req
.dst_ipaddr_mask
[i
] = cpu_to_be32(0xffffffff);
3757 req
.src_ipaddr
[0] = keys
->addrs
.v4addrs
.src
;
3758 req
.src_ipaddr_mask
[0] = cpu_to_be32(0xffffffff);
3759 req
.dst_ipaddr
[0] = keys
->addrs
.v4addrs
.dst
;
3760 req
.dst_ipaddr_mask
[0] = cpu_to_be32(0xffffffff);
3762 if (keys
->control
.flags
& FLOW_DIS_ENCAPSULATION
) {
3763 req
.enables
|= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG
);
3765 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
;
3768 req
.src_port
= keys
->ports
.src
;
3769 req
.src_port_mask
= cpu_to_be16(0xffff);
3770 req
.dst_port
= keys
->ports
.dst
;
3771 req
.dst_port_mask
= cpu_to_be16(0xffff);
3773 req
.dst_id
= cpu_to_le16(vnic
->fw_vnic_id
);
3774 mutex_lock(&bp
->hwrm_cmd_lock
);
3775 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3777 fltr
->filter_id
= resp
->ntuple_filter_id
;
3778 mutex_unlock(&bp
->hwrm_cmd_lock
);
3783 static int bnxt_hwrm_set_vnic_filter(struct bnxt
*bp
, u16 vnic_id
, u16 idx
,
3787 struct hwrm_cfa_l2_filter_alloc_input req
= {0};
3788 struct hwrm_cfa_l2_filter_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3790 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_L2_FILTER_ALLOC
, -1, -1);
3791 req
.flags
= cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX
);
3792 if (!BNXT_CHIP_TYPE_NITRO_A0(bp
))
3794 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST
);
3795 req
.dst_id
= cpu_to_le16(bp
->vnic_info
[vnic_id
].fw_vnic_id
);
3797 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR
|
3798 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID
|
3799 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK
);
3800 memcpy(req
.l2_addr
, mac_addr
, ETH_ALEN
);
3801 req
.l2_addr_mask
[0] = 0xff;
3802 req
.l2_addr_mask
[1] = 0xff;
3803 req
.l2_addr_mask
[2] = 0xff;
3804 req
.l2_addr_mask
[3] = 0xff;
3805 req
.l2_addr_mask
[4] = 0xff;
3806 req
.l2_addr_mask
[5] = 0xff;
3808 mutex_lock(&bp
->hwrm_cmd_lock
);
3809 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3811 bp
->vnic_info
[vnic_id
].fw_l2_filter_id
[idx
] =
3813 mutex_unlock(&bp
->hwrm_cmd_lock
);
3817 static int bnxt_hwrm_clear_vnic_filter(struct bnxt
*bp
)
3819 u16 i
, j
, num_of_vnics
= 1; /* only vnic 0 supported */
3822 /* Any associated ntuple filters will also be cleared by firmware. */
3823 mutex_lock(&bp
->hwrm_cmd_lock
);
3824 for (i
= 0; i
< num_of_vnics
; i
++) {
3825 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[i
];
3827 for (j
= 0; j
< vnic
->uc_filter_count
; j
++) {
3828 struct hwrm_cfa_l2_filter_free_input req
= {0};
3830 bnxt_hwrm_cmd_hdr_init(bp
, &req
,
3831 HWRM_CFA_L2_FILTER_FREE
, -1, -1);
3833 req
.l2_filter_id
= vnic
->fw_l2_filter_id
[j
];
3835 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3838 vnic
->uc_filter_count
= 0;
3840 mutex_unlock(&bp
->hwrm_cmd_lock
);
3845 static int bnxt_hwrm_vnic_set_tpa(struct bnxt
*bp
, u16 vnic_id
, u32 tpa_flags
)
3847 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
3848 struct hwrm_vnic_tpa_cfg_input req
= {0};
3850 if (vnic
->fw_vnic_id
== INVALID_HW_RING_ID
)
3853 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_TPA_CFG
, -1, -1);
3856 u16 mss
= bp
->dev
->mtu
- 40;
3857 u32 nsegs
, n
, segs
= 0, flags
;
3859 flags
= VNIC_TPA_CFG_REQ_FLAGS_TPA
|
3860 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA
|
3861 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE
|
3862 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN
|
3863 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ
;
3864 if (tpa_flags
& BNXT_FLAG_GRO
)
3865 flags
|= VNIC_TPA_CFG_REQ_FLAGS_GRO
;
3867 req
.flags
= cpu_to_le32(flags
);
3870 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS
|
3871 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS
|
3872 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN
);
3874 /* Number of segs are log2 units, and first packet is not
3875 * included as part of this units.
3877 if (mss
<= BNXT_RX_PAGE_SIZE
) {
3878 n
= BNXT_RX_PAGE_SIZE
/ mss
;
3879 nsegs
= (MAX_SKB_FRAGS
- 1) * n
;
3881 n
= mss
/ BNXT_RX_PAGE_SIZE
;
3882 if (mss
& (BNXT_RX_PAGE_SIZE
- 1))
3884 nsegs
= (MAX_SKB_FRAGS
- n
) / n
;
3887 segs
= ilog2(nsegs
);
3888 req
.max_agg_segs
= cpu_to_le16(segs
);
3889 req
.max_aggs
= cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX
);
3891 req
.min_agg_len
= cpu_to_le32(512);
3893 req
.vnic_id
= cpu_to_le16(vnic
->fw_vnic_id
);
3895 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3898 static int bnxt_hwrm_vnic_set_rss(struct bnxt
*bp
, u16 vnic_id
, bool set_rss
)
3900 u32 i
, j
, max_rings
;
3901 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
3902 struct hwrm_vnic_rss_cfg_input req
= {0};
3904 if (vnic
->fw_rss_cos_lb_ctx
[0] == INVALID_HW_RING_ID
)
3907 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_RSS_CFG
, -1, -1);
3909 req
.hash_type
= cpu_to_le32(bp
->rss_hash_cfg
);
3910 if (vnic
->flags
& BNXT_VNIC_RSS_FLAG
) {
3911 if (BNXT_CHIP_TYPE_NITRO_A0(bp
))
3912 max_rings
= bp
->rx_nr_rings
- 1;
3914 max_rings
= bp
->rx_nr_rings
;
3919 /* Fill the RSS indirection table with ring group ids */
3920 for (i
= 0, j
= 0; i
< HW_HASH_INDEX_SIZE
; i
++, j
++) {
3923 vnic
->rss_table
[i
] = cpu_to_le16(vnic
->fw_grp_ids
[j
]);
3926 req
.ring_grp_tbl_addr
= cpu_to_le64(vnic
->rss_table_dma_addr
);
3927 req
.hash_key_tbl_addr
=
3928 cpu_to_le64(vnic
->rss_hash_key_dma_addr
);
3930 req
.rss_ctx_idx
= cpu_to_le16(vnic
->fw_rss_cos_lb_ctx
[0]);
3931 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3934 static int bnxt_hwrm_vnic_set_hds(struct bnxt
*bp
, u16 vnic_id
)
3936 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
3937 struct hwrm_vnic_plcmodes_cfg_input req
= {0};
3939 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_PLCMODES_CFG
, -1, -1);
3940 req
.flags
= cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT
|
3941 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4
|
3942 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6
);
3944 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID
|
3945 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID
);
3946 /* thresholds not implemented in firmware yet */
3947 req
.jumbo_thresh
= cpu_to_le16(bp
->rx_copy_thresh
);
3948 req
.hds_threshold
= cpu_to_le16(bp
->rx_copy_thresh
);
3949 req
.vnic_id
= cpu_to_le32(vnic
->fw_vnic_id
);
3950 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3953 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt
*bp
, u16 vnic_id
,
3956 struct hwrm_vnic_rss_cos_lb_ctx_free_input req
= {0};
3958 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_RSS_COS_LB_CTX_FREE
, -1, -1);
3959 req
.rss_cos_lb_ctx_id
=
3960 cpu_to_le16(bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
[ctx_idx
]);
3962 hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3963 bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
[ctx_idx
] = INVALID_HW_RING_ID
;
3966 static void bnxt_hwrm_vnic_ctx_free(struct bnxt
*bp
)
3970 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
3971 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[i
];
3973 for (j
= 0; j
< BNXT_MAX_CTX_PER_VNIC
; j
++) {
3974 if (vnic
->fw_rss_cos_lb_ctx
[j
] != INVALID_HW_RING_ID
)
3975 bnxt_hwrm_vnic_ctx_free_one(bp
, i
, j
);
3978 bp
->rsscos_nr_ctxs
= 0;
3981 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt
*bp
, u16 vnic_id
, u16 ctx_idx
)
3984 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req
= {0};
3985 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output
*resp
=
3986 bp
->hwrm_cmd_resp_addr
;
3988 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC
, -1,
3991 mutex_lock(&bp
->hwrm_cmd_lock
);
3992 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3994 bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
[ctx_idx
] =
3995 le16_to_cpu(resp
->rss_cos_lb_ctx_id
);
3996 mutex_unlock(&bp
->hwrm_cmd_lock
);
4001 int bnxt_hwrm_vnic_cfg(struct bnxt
*bp
, u16 vnic_id
)
4003 unsigned int ring
= 0, grp_idx
;
4004 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
4005 struct hwrm_vnic_cfg_input req
= {0};
4008 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_CFG
, -1, -1);
4010 req
.enables
= cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP
);
4011 /* Only RSS support for now TBD: COS & LB */
4012 if (vnic
->fw_rss_cos_lb_ctx
[0] != INVALID_HW_RING_ID
) {
4013 req
.rss_rule
= cpu_to_le16(vnic
->fw_rss_cos_lb_ctx
[0]);
4014 req
.enables
|= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE
|
4015 VNIC_CFG_REQ_ENABLES_MRU
);
4016 } else if (vnic
->flags
& BNXT_VNIC_RFS_NEW_RSS_FLAG
) {
4018 cpu_to_le16(bp
->vnic_info
[0].fw_rss_cos_lb_ctx
[0]);
4019 req
.enables
|= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE
|
4020 VNIC_CFG_REQ_ENABLES_MRU
);
4021 req
.flags
|= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE
);
4023 req
.rss_rule
= cpu_to_le16(0xffff);
4026 if (BNXT_CHIP_TYPE_NITRO_A0(bp
) &&
4027 (vnic
->fw_rss_cos_lb_ctx
[0] != INVALID_HW_RING_ID
)) {
4028 req
.cos_rule
= cpu_to_le16(vnic
->fw_rss_cos_lb_ctx
[1]);
4029 req
.enables
|= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE
);
4031 req
.cos_rule
= cpu_to_le16(0xffff);
4034 if (vnic
->flags
& BNXT_VNIC_RSS_FLAG
)
4036 else if (vnic
->flags
& BNXT_VNIC_RFS_FLAG
)
4038 else if ((vnic_id
== 1) && BNXT_CHIP_TYPE_NITRO_A0(bp
))
4039 ring
= bp
->rx_nr_rings
- 1;
4041 grp_idx
= bp
->rx_ring
[ring
].bnapi
->index
;
4042 req
.vnic_id
= cpu_to_le16(vnic
->fw_vnic_id
);
4043 req
.dflt_ring_grp
= cpu_to_le16(bp
->grp_info
[grp_idx
].fw_grp_id
);
4045 req
.lb_rule
= cpu_to_le16(0xffff);
4046 req
.mru
= cpu_to_le16(bp
->dev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+
4049 #ifdef CONFIG_BNXT_SRIOV
4051 def_vlan
= bp
->vf
.vlan
;
4053 if ((bp
->flags
& BNXT_FLAG_STRIP_VLAN
) || def_vlan
)
4054 req
.flags
|= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE
);
4055 if (!vnic_id
&& bnxt_ulp_registered(bp
->edev
, BNXT_ROCE_ULP
))
4057 cpu_to_le32(VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE
);
4059 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4062 static int bnxt_hwrm_vnic_free_one(struct bnxt
*bp
, u16 vnic_id
)
4066 if (bp
->vnic_info
[vnic_id
].fw_vnic_id
!= INVALID_HW_RING_ID
) {
4067 struct hwrm_vnic_free_input req
= {0};
4069 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_FREE
, -1, -1);
4071 cpu_to_le32(bp
->vnic_info
[vnic_id
].fw_vnic_id
);
4073 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4076 bp
->vnic_info
[vnic_id
].fw_vnic_id
= INVALID_HW_RING_ID
;
4081 static void bnxt_hwrm_vnic_free(struct bnxt
*bp
)
4085 for (i
= 0; i
< bp
->nr_vnics
; i
++)
4086 bnxt_hwrm_vnic_free_one(bp
, i
);
4089 static int bnxt_hwrm_vnic_alloc(struct bnxt
*bp
, u16 vnic_id
,
4090 unsigned int start_rx_ring_idx
,
4091 unsigned int nr_rings
)
4094 unsigned int i
, j
, grp_idx
, end_idx
= start_rx_ring_idx
+ nr_rings
;
4095 struct hwrm_vnic_alloc_input req
= {0};
4096 struct hwrm_vnic_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
4098 /* map ring groups to this vnic */
4099 for (i
= start_rx_ring_idx
, j
= 0; i
< end_idx
; i
++, j
++) {
4100 grp_idx
= bp
->rx_ring
[i
].bnapi
->index
;
4101 if (bp
->grp_info
[grp_idx
].fw_grp_id
== INVALID_HW_RING_ID
) {
4102 netdev_err(bp
->dev
, "Not enough ring groups avail:%x req:%x\n",
4106 bp
->vnic_info
[vnic_id
].fw_grp_ids
[j
] =
4107 bp
->grp_info
[grp_idx
].fw_grp_id
;
4110 bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
[0] = INVALID_HW_RING_ID
;
4111 bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
[1] = INVALID_HW_RING_ID
;
4113 req
.flags
= cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT
);
4115 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_ALLOC
, -1, -1);
4117 mutex_lock(&bp
->hwrm_cmd_lock
);
4118 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4120 bp
->vnic_info
[vnic_id
].fw_vnic_id
= le32_to_cpu(resp
->vnic_id
);
4121 mutex_unlock(&bp
->hwrm_cmd_lock
);
4125 static int bnxt_hwrm_vnic_qcaps(struct bnxt
*bp
)
4127 struct hwrm_vnic_qcaps_output
*resp
= bp
->hwrm_cmd_resp_addr
;
4128 struct hwrm_vnic_qcaps_input req
= {0};
4131 if (bp
->hwrm_spec_code
< 0x10600)
4134 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_QCAPS
, -1, -1);
4135 mutex_lock(&bp
->hwrm_cmd_lock
);
4136 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4139 cpu_to_le32(VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP
))
4140 bp
->flags
|= BNXT_FLAG_NEW_RSS_CAP
;
4142 mutex_unlock(&bp
->hwrm_cmd_lock
);
4146 static int bnxt_hwrm_ring_grp_alloc(struct bnxt
*bp
)
4151 mutex_lock(&bp
->hwrm_cmd_lock
);
4152 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
4153 struct hwrm_ring_grp_alloc_input req
= {0};
4154 struct hwrm_ring_grp_alloc_output
*resp
=
4155 bp
->hwrm_cmd_resp_addr
;
4156 unsigned int grp_idx
= bp
->rx_ring
[i
].bnapi
->index
;
4158 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_GRP_ALLOC
, -1, -1);
4160 req
.cr
= cpu_to_le16(bp
->grp_info
[grp_idx
].cp_fw_ring_id
);
4161 req
.rr
= cpu_to_le16(bp
->grp_info
[grp_idx
].rx_fw_ring_id
);
4162 req
.ar
= cpu_to_le16(bp
->grp_info
[grp_idx
].agg_fw_ring_id
);
4163 req
.sc
= cpu_to_le16(bp
->grp_info
[grp_idx
].fw_stats_ctx
);
4165 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
4170 bp
->grp_info
[grp_idx
].fw_grp_id
=
4171 le32_to_cpu(resp
->ring_group_id
);
4173 mutex_unlock(&bp
->hwrm_cmd_lock
);
4177 static int bnxt_hwrm_ring_grp_free(struct bnxt
*bp
)
4181 struct hwrm_ring_grp_free_input req
= {0};
4186 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_GRP_FREE
, -1, -1);
4188 mutex_lock(&bp
->hwrm_cmd_lock
);
4189 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4190 if (bp
->grp_info
[i
].fw_grp_id
== INVALID_HW_RING_ID
)
4193 cpu_to_le32(bp
->grp_info
[i
].fw_grp_id
);
4195 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
4199 bp
->grp_info
[i
].fw_grp_id
= INVALID_HW_RING_ID
;
4201 mutex_unlock(&bp
->hwrm_cmd_lock
);
4205 static int hwrm_ring_alloc_send_msg(struct bnxt
*bp
,
4206 struct bnxt_ring_struct
*ring
,
4207 u32 ring_type
, u32 map_index
,
4210 int rc
= 0, err
= 0;
4211 struct hwrm_ring_alloc_input req
= {0};
4212 struct hwrm_ring_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
4215 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_ALLOC
, -1, -1);
4218 if (ring
->nr_pages
> 1) {
4219 req
.page_tbl_addr
= cpu_to_le64(ring
->pg_tbl_map
);
4220 /* Page size is in log2 units */
4221 req
.page_size
= BNXT_PAGE_SHIFT
;
4222 req
.page_tbl_depth
= 1;
4224 req
.page_tbl_addr
= cpu_to_le64(ring
->dma_arr
[0]);
4227 /* Association of ring index with doorbell index and MSIX number */
4228 req
.logical_id
= cpu_to_le16(map_index
);
4230 switch (ring_type
) {
4231 case HWRM_RING_ALLOC_TX
:
4232 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_TX
;
4233 /* Association of transmit ring with completion ring */
4235 cpu_to_le16(bp
->grp_info
[map_index
].cp_fw_ring_id
);
4236 req
.length
= cpu_to_le32(bp
->tx_ring_mask
+ 1);
4237 req
.stat_ctx_id
= cpu_to_le32(stats_ctx_id
);
4238 req
.queue_id
= cpu_to_le16(ring
->queue_id
);
4240 case HWRM_RING_ALLOC_RX
:
4241 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_RX
;
4242 req
.length
= cpu_to_le32(bp
->rx_ring_mask
+ 1);
4244 case HWRM_RING_ALLOC_AGG
:
4245 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_RX
;
4246 req
.length
= cpu_to_le32(bp
->rx_agg_ring_mask
+ 1);
4248 case HWRM_RING_ALLOC_CMPL
:
4249 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_L2_CMPL
;
4250 req
.length
= cpu_to_le32(bp
->cp_ring_mask
+ 1);
4251 if (bp
->flags
& BNXT_FLAG_USING_MSIX
)
4252 req
.int_mode
= RING_ALLOC_REQ_INT_MODE_MSIX
;
4255 netdev_err(bp
->dev
, "hwrm alloc invalid ring type %d\n",
4260 mutex_lock(&bp
->hwrm_cmd_lock
);
4261 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4262 err
= le16_to_cpu(resp
->error_code
);
4263 ring_id
= le16_to_cpu(resp
->ring_id
);
4264 mutex_unlock(&bp
->hwrm_cmd_lock
);
4267 switch (ring_type
) {
4268 case RING_FREE_REQ_RING_TYPE_L2_CMPL
:
4269 netdev_err(bp
->dev
, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
4273 case RING_FREE_REQ_RING_TYPE_RX
:
4274 netdev_err(bp
->dev
, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
4278 case RING_FREE_REQ_RING_TYPE_TX
:
4279 netdev_err(bp
->dev
, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
4284 netdev_err(bp
->dev
, "Invalid ring\n");
4288 ring
->fw_ring_id
= ring_id
;
4292 static int bnxt_hwrm_set_async_event_cr(struct bnxt
*bp
, int idx
)
4297 struct hwrm_func_cfg_input req
= {0};
4299 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_CFG
, -1, -1);
4300 req
.fid
= cpu_to_le16(0xffff);
4301 req
.enables
= cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR
);
4302 req
.async_event_cr
= cpu_to_le16(idx
);
4303 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4305 struct hwrm_func_vf_cfg_input req
= {0};
4307 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_VF_CFG
, -1, -1);
4309 cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR
);
4310 req
.async_event_cr
= cpu_to_le16(idx
);
4311 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4316 static int bnxt_hwrm_ring_alloc(struct bnxt
*bp
)
4320 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4321 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4322 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
4323 struct bnxt_ring_struct
*ring
= &cpr
->cp_ring_struct
;
4325 cpr
->cp_doorbell
= bp
->bar1
+ i
* 0x80;
4326 rc
= hwrm_ring_alloc_send_msg(bp
, ring
, HWRM_RING_ALLOC_CMPL
, i
,
4327 INVALID_STATS_CTX_ID
);
4330 BNXT_CP_DB(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
4331 bp
->grp_info
[i
].cp_fw_ring_id
= ring
->fw_ring_id
;
4334 rc
= bnxt_hwrm_set_async_event_cr(bp
, ring
->fw_ring_id
);
4336 netdev_warn(bp
->dev
, "Failed to set async event completion ring.\n");
4340 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
4341 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
4342 struct bnxt_ring_struct
*ring
= &txr
->tx_ring_struct
;
4343 u32 map_idx
= txr
->bnapi
->index
;
4344 u16 fw_stats_ctx
= bp
->grp_info
[map_idx
].fw_stats_ctx
;
4346 rc
= hwrm_ring_alloc_send_msg(bp
, ring
, HWRM_RING_ALLOC_TX
,
4347 map_idx
, fw_stats_ctx
);
4350 txr
->tx_doorbell
= bp
->bar1
+ map_idx
* 0x80;
4353 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
4354 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
4355 struct bnxt_ring_struct
*ring
= &rxr
->rx_ring_struct
;
4356 u32 map_idx
= rxr
->bnapi
->index
;
4358 rc
= hwrm_ring_alloc_send_msg(bp
, ring
, HWRM_RING_ALLOC_RX
,
4359 map_idx
, INVALID_STATS_CTX_ID
);
4362 rxr
->rx_doorbell
= bp
->bar1
+ map_idx
* 0x80;
4363 writel(DB_KEY_RX
| rxr
->rx_prod
, rxr
->rx_doorbell
);
4364 bp
->grp_info
[map_idx
].rx_fw_ring_id
= ring
->fw_ring_id
;
4367 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
) {
4368 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
4369 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
4370 struct bnxt_ring_struct
*ring
=
4371 &rxr
->rx_agg_ring_struct
;
4372 u32 grp_idx
= rxr
->bnapi
->index
;
4373 u32 map_idx
= grp_idx
+ bp
->rx_nr_rings
;
4375 rc
= hwrm_ring_alloc_send_msg(bp
, ring
,
4376 HWRM_RING_ALLOC_AGG
,
4378 INVALID_STATS_CTX_ID
);
4382 rxr
->rx_agg_doorbell
= bp
->bar1
+ map_idx
* 0x80;
4383 writel(DB_KEY_RX
| rxr
->rx_agg_prod
,
4384 rxr
->rx_agg_doorbell
);
4385 bp
->grp_info
[grp_idx
].agg_fw_ring_id
= ring
->fw_ring_id
;
4392 static int hwrm_ring_free_send_msg(struct bnxt
*bp
,
4393 struct bnxt_ring_struct
*ring
,
4394 u32 ring_type
, int cmpl_ring_id
)
4397 struct hwrm_ring_free_input req
= {0};
4398 struct hwrm_ring_free_output
*resp
= bp
->hwrm_cmd_resp_addr
;
4401 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_FREE
, cmpl_ring_id
, -1);
4402 req
.ring_type
= ring_type
;
4403 req
.ring_id
= cpu_to_le16(ring
->fw_ring_id
);
4405 mutex_lock(&bp
->hwrm_cmd_lock
);
4406 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4407 error_code
= le16_to_cpu(resp
->error_code
);
4408 mutex_unlock(&bp
->hwrm_cmd_lock
);
4410 if (rc
|| error_code
) {
4411 switch (ring_type
) {
4412 case RING_FREE_REQ_RING_TYPE_L2_CMPL
:
4413 netdev_err(bp
->dev
, "hwrm_ring_free cp failed. rc:%d\n",
4416 case RING_FREE_REQ_RING_TYPE_RX
:
4417 netdev_err(bp
->dev
, "hwrm_ring_free rx failed. rc:%d\n",
4420 case RING_FREE_REQ_RING_TYPE_TX
:
4421 netdev_err(bp
->dev
, "hwrm_ring_free tx failed. rc:%d\n",
4425 netdev_err(bp
->dev
, "Invalid ring\n");
4432 static void bnxt_hwrm_ring_free(struct bnxt
*bp
, bool close_path
)
4439 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
4440 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
4441 struct bnxt_ring_struct
*ring
= &txr
->tx_ring_struct
;
4442 u32 grp_idx
= txr
->bnapi
->index
;
4443 u32 cmpl_ring_id
= bp
->grp_info
[grp_idx
].cp_fw_ring_id
;
4445 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
4446 hwrm_ring_free_send_msg(bp
, ring
,
4447 RING_FREE_REQ_RING_TYPE_TX
,
4448 close_path
? cmpl_ring_id
:
4449 INVALID_HW_RING_ID
);
4450 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
4454 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
4455 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
4456 struct bnxt_ring_struct
*ring
= &rxr
->rx_ring_struct
;
4457 u32 grp_idx
= rxr
->bnapi
->index
;
4458 u32 cmpl_ring_id
= bp
->grp_info
[grp_idx
].cp_fw_ring_id
;
4460 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
4461 hwrm_ring_free_send_msg(bp
, ring
,
4462 RING_FREE_REQ_RING_TYPE_RX
,
4463 close_path
? cmpl_ring_id
:
4464 INVALID_HW_RING_ID
);
4465 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
4466 bp
->grp_info
[grp_idx
].rx_fw_ring_id
=
4471 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
4472 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
4473 struct bnxt_ring_struct
*ring
= &rxr
->rx_agg_ring_struct
;
4474 u32 grp_idx
= rxr
->bnapi
->index
;
4475 u32 cmpl_ring_id
= bp
->grp_info
[grp_idx
].cp_fw_ring_id
;
4477 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
4478 hwrm_ring_free_send_msg(bp
, ring
,
4479 RING_FREE_REQ_RING_TYPE_RX
,
4480 close_path
? cmpl_ring_id
:
4481 INVALID_HW_RING_ID
);
4482 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
4483 bp
->grp_info
[grp_idx
].agg_fw_ring_id
=
4488 /* The completion rings are about to be freed. After that the
4489 * IRQ doorbell will not work anymore. So we need to disable
4492 bnxt_disable_int_sync(bp
);
4494 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4495 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4496 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
4497 struct bnxt_ring_struct
*ring
= &cpr
->cp_ring_struct
;
4499 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
4500 hwrm_ring_free_send_msg(bp
, ring
,
4501 RING_FREE_REQ_RING_TYPE_L2_CMPL
,
4502 INVALID_HW_RING_ID
);
4503 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
4504 bp
->grp_info
[i
].cp_fw_ring_id
= INVALID_HW_RING_ID
;
4509 static int bnxt_hwrm_get_rings(struct bnxt
*bp
)
4511 struct hwrm_func_qcfg_output
*resp
= bp
->hwrm_cmd_resp_addr
;
4512 struct bnxt_hw_resc
*hw_resc
= &bp
->hw_resc
;
4513 struct hwrm_func_qcfg_input req
= {0};
4516 if (bp
->hwrm_spec_code
< 0x10601)
4519 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_QCFG
, -1, -1);
4520 req
.fid
= cpu_to_le16(0xffff);
4521 mutex_lock(&bp
->hwrm_cmd_lock
);
4522 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4524 mutex_unlock(&bp
->hwrm_cmd_lock
);
4528 hw_resc
->resv_tx_rings
= le16_to_cpu(resp
->alloc_tx_rings
);
4529 if (bp
->flags
& BNXT_FLAG_NEW_RM
) {
4532 hw_resc
->resv_rx_rings
= le16_to_cpu(resp
->alloc_rx_rings
);
4533 hw_resc
->resv_hw_ring_grps
=
4534 le32_to_cpu(resp
->alloc_hw_ring_grps
);
4535 hw_resc
->resv_vnics
= le16_to_cpu(resp
->alloc_vnics
);
4536 cp
= le16_to_cpu(resp
->alloc_cmpl_rings
);
4537 stats
= le16_to_cpu(resp
->alloc_stat_ctx
);
4538 cp
= min_t(u16
, cp
, stats
);
4539 hw_resc
->resv_cp_rings
= cp
;
4541 mutex_unlock(&bp
->hwrm_cmd_lock
);
4545 /* Caller must hold bp->hwrm_cmd_lock */
4546 int __bnxt_hwrm_get_tx_rings(struct bnxt
*bp
, u16 fid
, int *tx_rings
)
4548 struct hwrm_func_qcfg_output
*resp
= bp
->hwrm_cmd_resp_addr
;
4549 struct hwrm_func_qcfg_input req
= {0};
4552 if (bp
->hwrm_spec_code
< 0x10601)
4555 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_QCFG
, -1, -1);
4556 req
.fid
= cpu_to_le16(fid
);
4557 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4559 *tx_rings
= le16_to_cpu(resp
->alloc_tx_rings
);
4565 __bnxt_hwrm_reserve_pf_rings(struct bnxt
*bp
, struct hwrm_func_cfg_input
*req
,
4566 int tx_rings
, int rx_rings
, int ring_grps
,
4567 int cp_rings
, int vnics
)
4571 bnxt_hwrm_cmd_hdr_init(bp
, req
, HWRM_FUNC_CFG
, -1, -1);
4572 req
->fid
= cpu_to_le16(0xffff);
4573 enables
|= tx_rings
? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS
: 0;
4574 req
->num_tx_rings
= cpu_to_le16(tx_rings
);
4575 if (bp
->flags
& BNXT_FLAG_NEW_RM
) {
4576 enables
|= rx_rings
? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS
: 0;
4577 enables
|= cp_rings
? FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS
|
4578 FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS
: 0;
4579 enables
|= ring_grps
?
4580 FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS
: 0;
4581 enables
|= vnics
? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS
: 0;
4583 req
->num_rx_rings
= cpu_to_le16(rx_rings
);
4584 req
->num_hw_ring_grps
= cpu_to_le16(ring_grps
);
4585 req
->num_cmpl_rings
= cpu_to_le16(cp_rings
);
4586 req
->num_stat_ctxs
= req
->num_cmpl_rings
;
4587 req
->num_vnics
= cpu_to_le16(vnics
);
4589 req
->enables
= cpu_to_le32(enables
);
4593 __bnxt_hwrm_reserve_vf_rings(struct bnxt
*bp
,
4594 struct hwrm_func_vf_cfg_input
*req
, int tx_rings
,
4595 int rx_rings
, int ring_grps
, int cp_rings
,
4600 bnxt_hwrm_cmd_hdr_init(bp
, req
, HWRM_FUNC_VF_CFG
, -1, -1);
4601 enables
|= tx_rings
? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS
: 0;
4602 enables
|= rx_rings
? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS
: 0;
4603 enables
|= cp_rings
? FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS
|
4604 FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS
: 0;
4605 enables
|= ring_grps
? FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS
: 0;
4606 enables
|= vnics
? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS
: 0;
4608 req
->num_tx_rings
= cpu_to_le16(tx_rings
);
4609 req
->num_rx_rings
= cpu_to_le16(rx_rings
);
4610 req
->num_hw_ring_grps
= cpu_to_le16(ring_grps
);
4611 req
->num_cmpl_rings
= cpu_to_le16(cp_rings
);
4612 req
->num_stat_ctxs
= req
->num_cmpl_rings
;
4613 req
->num_vnics
= cpu_to_le16(vnics
);
4615 req
->enables
= cpu_to_le32(enables
);
4619 bnxt_hwrm_reserve_pf_rings(struct bnxt
*bp
, int tx_rings
, int rx_rings
,
4620 int ring_grps
, int cp_rings
, int vnics
)
4622 struct hwrm_func_cfg_input req
= {0};
4625 __bnxt_hwrm_reserve_pf_rings(bp
, &req
, tx_rings
, rx_rings
, ring_grps
,
4630 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4634 if (bp
->hwrm_spec_code
< 0x10601)
4635 bp
->hw_resc
.resv_tx_rings
= tx_rings
;
4637 rc
= bnxt_hwrm_get_rings(bp
);
4642 bnxt_hwrm_reserve_vf_rings(struct bnxt
*bp
, int tx_rings
, int rx_rings
,
4643 int ring_grps
, int cp_rings
, int vnics
)
4645 struct hwrm_func_vf_cfg_input req
= {0};
4648 if (!(bp
->flags
& BNXT_FLAG_NEW_RM
)) {
4649 bp
->hw_resc
.resv_tx_rings
= tx_rings
;
4653 __bnxt_hwrm_reserve_vf_rings(bp
, &req
, tx_rings
, rx_rings
, ring_grps
,
4655 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4659 rc
= bnxt_hwrm_get_rings(bp
);
4663 static int bnxt_hwrm_reserve_rings(struct bnxt
*bp
, int tx
, int rx
, int grp
,
4667 return bnxt_hwrm_reserve_pf_rings(bp
, tx
, rx
, grp
, cp
, vnic
);
4669 return bnxt_hwrm_reserve_vf_rings(bp
, tx
, rx
, grp
, cp
, vnic
);
4672 static int bnxt_trim_rings(struct bnxt
*bp
, int *rx
, int *tx
, int max
,
4675 static int __bnxt_reserve_rings(struct bnxt
*bp
)
4677 struct bnxt_hw_resc
*hw_resc
= &bp
->hw_resc
;
4678 int tx
= bp
->tx_nr_rings
;
4679 int rx
= bp
->rx_nr_rings
;
4680 int cp
= bp
->cp_nr_rings
;
4681 int grp
, rx_rings
, rc
;
4685 if (bp
->hwrm_spec_code
< 0x10601)
4688 if (bp
->flags
& BNXT_FLAG_SHARED_RINGS
)
4690 if (bp
->flags
& BNXT_FLAG_RFS
)
4692 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
)
4695 grp
= bp
->rx_nr_rings
;
4696 if (tx
== hw_resc
->resv_tx_rings
&&
4697 (!(bp
->flags
& BNXT_FLAG_NEW_RM
) ||
4698 (rx
== hw_resc
->resv_rx_rings
&&
4699 grp
== hw_resc
->resv_hw_ring_grps
&&
4700 cp
== hw_resc
->resv_cp_rings
&& vnic
== hw_resc
->resv_vnics
)))
4703 rc
= bnxt_hwrm_reserve_rings(bp
, tx
, rx
, grp
, cp
, vnic
);
4707 tx
= hw_resc
->resv_tx_rings
;
4708 if (bp
->flags
& BNXT_FLAG_NEW_RM
) {
4709 rx
= hw_resc
->resv_rx_rings
;
4710 cp
= hw_resc
->resv_cp_rings
;
4711 grp
= hw_resc
->resv_hw_ring_grps
;
4712 vnic
= hw_resc
->resv_vnics
;
4716 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
) {
4720 if (netif_running(bp
->dev
))
4723 bp
->flags
&= ~BNXT_FLAG_AGG_RINGS
;
4724 bp
->flags
|= BNXT_FLAG_NO_AGG_RINGS
;
4725 bp
->dev
->hw_features
&= ~NETIF_F_LRO
;
4726 bp
->dev
->features
&= ~NETIF_F_LRO
;
4727 bnxt_set_ring_params(bp
);
4730 rx_rings
= min_t(int, rx_rings
, grp
);
4731 rc
= bnxt_trim_rings(bp
, &rx_rings
, &tx
, cp
, sh
);
4732 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
)
4734 cp
= sh
? max_t(int, tx
, rx_rings
) : tx
+ rx_rings
;
4735 bp
->tx_nr_rings
= tx
;
4736 bp
->rx_nr_rings
= rx_rings
;
4737 bp
->cp_nr_rings
= cp
;
4739 if (!tx
|| !rx
|| !cp
|| !grp
|| !vnic
)
4745 static bool bnxt_need_reserve_rings(struct bnxt
*bp
)
4747 struct bnxt_hw_resc
*hw_resc
= &bp
->hw_resc
;
4748 int rx
= bp
->rx_nr_rings
;
4751 if (bp
->hwrm_spec_code
< 0x10601)
4754 if (hw_resc
->resv_tx_rings
!= bp
->tx_nr_rings
)
4757 if (bp
->flags
& BNXT_FLAG_RFS
)
4759 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
)
4761 if ((bp
->flags
& BNXT_FLAG_NEW_RM
) &&
4762 (hw_resc
->resv_rx_rings
!= rx
||
4763 hw_resc
->resv_cp_rings
!= bp
->cp_nr_rings
||
4764 hw_resc
->resv_vnics
!= vnic
))
4769 static int bnxt_hwrm_check_vf_rings(struct bnxt
*bp
, int tx_rings
, int rx_rings
,
4770 int ring_grps
, int cp_rings
, int vnics
)
4772 struct hwrm_func_vf_cfg_input req
= {0};
4776 if (!(bp
->flags
& BNXT_FLAG_NEW_RM
))
4779 __bnxt_hwrm_reserve_vf_rings(bp
, &req
, tx_rings
, rx_rings
, ring_grps
,
4781 flags
= FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST
|
4782 FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST
|
4783 FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST
|
4784 FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST
|
4785 FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST
|
4786 FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST
;
4788 req
.flags
= cpu_to_le32(flags
);
4789 rc
= hwrm_send_message_silent(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4795 static int bnxt_hwrm_check_pf_rings(struct bnxt
*bp
, int tx_rings
, int rx_rings
,
4796 int ring_grps
, int cp_rings
, int vnics
)
4798 struct hwrm_func_cfg_input req
= {0};
4802 __bnxt_hwrm_reserve_pf_rings(bp
, &req
, tx_rings
, rx_rings
, ring_grps
,
4804 flags
= FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST
;
4805 if (bp
->flags
& BNXT_FLAG_NEW_RM
)
4806 flags
|= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST
|
4807 FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST
|
4808 FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST
|
4809 FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST
|
4810 FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST
;
4812 req
.flags
= cpu_to_le32(flags
);
4813 rc
= hwrm_send_message_silent(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4819 static int bnxt_hwrm_check_rings(struct bnxt
*bp
, int tx_rings
, int rx_rings
,
4820 int ring_grps
, int cp_rings
, int vnics
)
4822 if (bp
->hwrm_spec_code
< 0x10801)
4826 return bnxt_hwrm_check_pf_rings(bp
, tx_rings
, rx_rings
,
4827 ring_grps
, cp_rings
, vnics
);
4829 return bnxt_hwrm_check_vf_rings(bp
, tx_rings
, rx_rings
, ring_grps
,
4833 static void bnxt_hwrm_set_coal_params(struct bnxt_coal
*hw_coal
,
4834 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input
*req
)
4836 u16 val
, tmr
, max
, flags
;
4838 max
= hw_coal
->bufs_per_record
* 128;
4839 if (hw_coal
->budget
)
4840 max
= hw_coal
->bufs_per_record
* hw_coal
->budget
;
4842 val
= clamp_t(u16
, hw_coal
->coal_bufs
, 1, max
);
4843 req
->num_cmpl_aggr_int
= cpu_to_le16(val
);
4845 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4846 val
= min_t(u16
, val
, 63);
4847 req
->num_cmpl_dma_aggr
= cpu_to_le16(val
);
4849 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4850 val
= clamp_t(u16
, hw_coal
->coal_bufs_irq
, 1, 63);
4851 req
->num_cmpl_dma_aggr_during_int
= cpu_to_le16(val
);
4853 tmr
= BNXT_USEC_TO_COAL_TIMER(hw_coal
->coal_ticks
);
4854 tmr
= max_t(u16
, tmr
, 1);
4855 req
->int_lat_tmr_max
= cpu_to_le16(tmr
);
4857 /* min timer set to 1/2 of interrupt timer */
4859 req
->int_lat_tmr_min
= cpu_to_le16(val
);
4861 /* buf timer set to 1/4 of interrupt timer */
4862 val
= max_t(u16
, tmr
/ 4, 1);
4863 req
->cmpl_aggr_dma_tmr
= cpu_to_le16(val
);
4865 tmr
= BNXT_USEC_TO_COAL_TIMER(hw_coal
->coal_ticks_irq
);
4866 tmr
= max_t(u16
, tmr
, 1);
4867 req
->cmpl_aggr_dma_tmr_during_int
= cpu_to_le16(tmr
);
4869 flags
= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET
;
4870 if (hw_coal
->idle_thresh
&& hw_coal
->coal_ticks
< hw_coal
->idle_thresh
)
4871 flags
|= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE
;
4872 req
->flags
= cpu_to_le16(flags
);
4875 int bnxt_hwrm_set_ring_coal(struct bnxt
*bp
, struct bnxt_napi
*bnapi
)
4877 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx
= {0};
4878 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
4879 struct bnxt_coal coal
;
4880 unsigned int grp_idx
;
4882 /* Tick values in micro seconds.
4883 * 1 coal_buf x bufs_per_record = 1 completion record.
4885 memcpy(&coal
, &bp
->rx_coal
, sizeof(struct bnxt_coal
));
4887 coal
.coal_ticks
= cpr
->rx_ring_coal
.coal_ticks
;
4888 coal
.coal_bufs
= cpr
->rx_ring_coal
.coal_bufs
;
4890 if (!bnapi
->rx_ring
)
4893 bnxt_hwrm_cmd_hdr_init(bp
, &req_rx
,
4894 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS
, -1, -1);
4896 bnxt_hwrm_set_coal_params(&coal
, &req_rx
);
4898 grp_idx
= bnapi
->index
;
4899 req_rx
.ring_id
= cpu_to_le16(bp
->grp_info
[grp_idx
].cp_fw_ring_id
);
4901 return hwrm_send_message(bp
, &req_rx
, sizeof(req_rx
),
4905 int bnxt_hwrm_set_coal(struct bnxt
*bp
)
4908 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx
= {0},
4911 bnxt_hwrm_cmd_hdr_init(bp
, &req_rx
,
4912 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS
, -1, -1);
4913 bnxt_hwrm_cmd_hdr_init(bp
, &req_tx
,
4914 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS
, -1, -1);
4916 bnxt_hwrm_set_coal_params(&bp
->rx_coal
, &req_rx
);
4917 bnxt_hwrm_set_coal_params(&bp
->tx_coal
, &req_tx
);
4919 mutex_lock(&bp
->hwrm_cmd_lock
);
4920 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4921 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4924 if (!bnapi
->rx_ring
)
4926 req
->ring_id
= cpu_to_le16(bp
->grp_info
[i
].cp_fw_ring_id
);
4928 rc
= _hwrm_send_message(bp
, req
, sizeof(*req
),
4933 mutex_unlock(&bp
->hwrm_cmd_lock
);
4937 static int bnxt_hwrm_stat_ctx_free(struct bnxt
*bp
)
4940 struct hwrm_stat_ctx_free_input req
= {0};
4945 if (BNXT_CHIP_TYPE_NITRO_A0(bp
))
4948 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_STAT_CTX_FREE
, -1, -1);
4950 mutex_lock(&bp
->hwrm_cmd_lock
);
4951 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4952 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4953 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
4955 if (cpr
->hw_stats_ctx_id
!= INVALID_STATS_CTX_ID
) {
4956 req
.stat_ctx_id
= cpu_to_le32(cpr
->hw_stats_ctx_id
);
4958 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
4963 cpr
->hw_stats_ctx_id
= INVALID_STATS_CTX_ID
;
4966 mutex_unlock(&bp
->hwrm_cmd_lock
);
4970 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt
*bp
)
4973 struct hwrm_stat_ctx_alloc_input req
= {0};
4974 struct hwrm_stat_ctx_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
4976 if (BNXT_CHIP_TYPE_NITRO_A0(bp
))
4979 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_STAT_CTX_ALLOC
, -1, -1);
4981 req
.update_period_ms
= cpu_to_le32(bp
->stats_coal_ticks
/ 1000);
4983 mutex_lock(&bp
->hwrm_cmd_lock
);
4984 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4985 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4986 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
4988 req
.stats_dma_addr
= cpu_to_le64(cpr
->hw_stats_map
);
4990 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
4995 cpr
->hw_stats_ctx_id
= le32_to_cpu(resp
->stat_ctx_id
);
4997 bp
->grp_info
[i
].fw_stats_ctx
= cpr
->hw_stats_ctx_id
;
4999 mutex_unlock(&bp
->hwrm_cmd_lock
);
5003 static int bnxt_hwrm_func_qcfg(struct bnxt
*bp
)
5005 struct hwrm_func_qcfg_input req
= {0};
5006 struct hwrm_func_qcfg_output
*resp
= bp
->hwrm_cmd_resp_addr
;
5010 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_QCFG
, -1, -1);
5011 req
.fid
= cpu_to_le16(0xffff);
5012 mutex_lock(&bp
->hwrm_cmd_lock
);
5013 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
5015 goto func_qcfg_exit
;
5017 #ifdef CONFIG_BNXT_SRIOV
5019 struct bnxt_vf_info
*vf
= &bp
->vf
;
5021 vf
->vlan
= le16_to_cpu(resp
->vlan
) & VLAN_VID_MASK
;
5024 flags
= le16_to_cpu(resp
->flags
);
5025 if (flags
& (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED
|
5026 FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED
)) {
5027 bp
->flags
|= BNXT_FLAG_FW_LLDP_AGENT
;
5028 if (flags
& FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED
)
5029 bp
->flags
|= BNXT_FLAG_FW_DCBX_AGENT
;
5031 if (BNXT_PF(bp
) && (flags
& FUNC_QCFG_RESP_FLAGS_MULTI_HOST
))
5032 bp
->flags
|= BNXT_FLAG_MULTI_HOST
;
5034 switch (resp
->port_partition_type
) {
5035 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0
:
5036 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5
:
5037 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0
:
5038 bp
->port_partition_type
= resp
->port_partition_type
;
5041 if (bp
->hwrm_spec_code
< 0x10707 ||
5042 resp
->evb_mode
== FUNC_QCFG_RESP_EVB_MODE_VEB
)
5043 bp
->br_mode
= BRIDGE_MODE_VEB
;
5044 else if (resp
->evb_mode
== FUNC_QCFG_RESP_EVB_MODE_VEPA
)
5045 bp
->br_mode
= BRIDGE_MODE_VEPA
;
5047 bp
->br_mode
= BRIDGE_MODE_UNDEF
;
5049 bp
->max_mtu
= le16_to_cpu(resp
->max_mtu_configured
);
5051 bp
->max_mtu
= BNXT_MAX_MTU
;
5054 mutex_unlock(&bp
->hwrm_cmd_lock
);
5058 static int bnxt_hwrm_func_resc_qcaps(struct bnxt
*bp
)
5060 struct hwrm_func_resource_qcaps_output
*resp
= bp
->hwrm_cmd_resp_addr
;
5061 struct hwrm_func_resource_qcaps_input req
= {0};
5062 struct bnxt_hw_resc
*hw_resc
= &bp
->hw_resc
;
5065 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_RESOURCE_QCAPS
, -1, -1);
5066 req
.fid
= cpu_to_le16(0xffff);
5068 mutex_lock(&bp
->hwrm_cmd_lock
);
5069 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
5072 goto hwrm_func_resc_qcaps_exit
;
5075 hw_resc
->min_rsscos_ctxs
= le16_to_cpu(resp
->min_rsscos_ctx
);
5076 hw_resc
->max_rsscos_ctxs
= le16_to_cpu(resp
->max_rsscos_ctx
);
5077 hw_resc
->min_cp_rings
= le16_to_cpu(resp
->min_cmpl_rings
);
5078 hw_resc
->max_cp_rings
= le16_to_cpu(resp
->max_cmpl_rings
);
5079 hw_resc
->min_tx_rings
= le16_to_cpu(resp
->min_tx_rings
);
5080 hw_resc
->max_tx_rings
= le16_to_cpu(resp
->max_tx_rings
);
5081 hw_resc
->min_rx_rings
= le16_to_cpu(resp
->min_rx_rings
);
5082 hw_resc
->max_rx_rings
= le16_to_cpu(resp
->max_rx_rings
);
5083 hw_resc
->min_hw_ring_grps
= le16_to_cpu(resp
->min_hw_ring_grps
);
5084 hw_resc
->max_hw_ring_grps
= le16_to_cpu(resp
->max_hw_ring_grps
);
5085 hw_resc
->min_l2_ctxs
= le16_to_cpu(resp
->min_l2_ctxs
);
5086 hw_resc
->max_l2_ctxs
= le16_to_cpu(resp
->max_l2_ctxs
);
5087 hw_resc
->min_vnics
= le16_to_cpu(resp
->min_vnics
);
5088 hw_resc
->max_vnics
= le16_to_cpu(resp
->max_vnics
);
5089 hw_resc
->min_stat_ctxs
= le16_to_cpu(resp
->min_stat_ctx
);
5090 hw_resc
->max_stat_ctxs
= le16_to_cpu(resp
->max_stat_ctx
);
5093 struct bnxt_pf_info
*pf
= &bp
->pf
;
5095 pf
->vf_resv_strategy
=
5096 le16_to_cpu(resp
->vf_reservation_strategy
);
5097 if (pf
->vf_resv_strategy
> BNXT_VF_RESV_STRATEGY_MINIMAL
)
5098 pf
->vf_resv_strategy
= BNXT_VF_RESV_STRATEGY_MAXIMAL
;
5100 hwrm_func_resc_qcaps_exit
:
5101 mutex_unlock(&bp
->hwrm_cmd_lock
);
5105 static int __bnxt_hwrm_func_qcaps(struct bnxt
*bp
)
5108 struct hwrm_func_qcaps_input req
= {0};
5109 struct hwrm_func_qcaps_output
*resp
= bp
->hwrm_cmd_resp_addr
;
5110 struct bnxt_hw_resc
*hw_resc
= &bp
->hw_resc
;
5113 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_QCAPS
, -1, -1);
5114 req
.fid
= cpu_to_le16(0xffff);
5116 mutex_lock(&bp
->hwrm_cmd_lock
);
5117 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
5119 goto hwrm_func_qcaps_exit
;
5121 flags
= le32_to_cpu(resp
->flags
);
5122 if (flags
& FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED
)
5123 bp
->flags
|= BNXT_FLAG_ROCEV1_CAP
;
5124 if (flags
& FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED
)
5125 bp
->flags
|= BNXT_FLAG_ROCEV2_CAP
;
5127 bp
->tx_push_thresh
= 0;
5128 if (flags
& FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED
)
5129 bp
->tx_push_thresh
= BNXT_TX_PUSH_THRESH
;
5131 hw_resc
->max_rsscos_ctxs
= le16_to_cpu(resp
->max_rsscos_ctx
);
5132 hw_resc
->max_cp_rings
= le16_to_cpu(resp
->max_cmpl_rings
);
5133 hw_resc
->max_tx_rings
= le16_to_cpu(resp
->max_tx_rings
);
5134 hw_resc
->max_rx_rings
= le16_to_cpu(resp
->max_rx_rings
);
5135 hw_resc
->max_hw_ring_grps
= le32_to_cpu(resp
->max_hw_ring_grps
);
5136 if (!hw_resc
->max_hw_ring_grps
)
5137 hw_resc
->max_hw_ring_grps
= hw_resc
->max_tx_rings
;
5138 hw_resc
->max_l2_ctxs
= le16_to_cpu(resp
->max_l2_ctxs
);
5139 hw_resc
->max_vnics
= le16_to_cpu(resp
->max_vnics
);
5140 hw_resc
->max_stat_ctxs
= le16_to_cpu(resp
->max_stat_ctx
);
5143 struct bnxt_pf_info
*pf
= &bp
->pf
;
5145 pf
->fw_fid
= le16_to_cpu(resp
->fid
);
5146 pf
->port_id
= le16_to_cpu(resp
->port_id
);
5147 bp
->dev
->dev_port
= pf
->port_id
;
5148 memcpy(pf
->mac_addr
, resp
->mac_address
, ETH_ALEN
);
5149 pf
->first_vf_id
= le16_to_cpu(resp
->first_vf_id
);
5150 pf
->max_vfs
= le16_to_cpu(resp
->max_vfs
);
5151 pf
->max_encap_records
= le32_to_cpu(resp
->max_encap_records
);
5152 pf
->max_decap_records
= le32_to_cpu(resp
->max_decap_records
);
5153 pf
->max_tx_em_flows
= le32_to_cpu(resp
->max_tx_em_flows
);
5154 pf
->max_tx_wm_flows
= le32_to_cpu(resp
->max_tx_wm_flows
);
5155 pf
->max_rx_em_flows
= le32_to_cpu(resp
->max_rx_em_flows
);
5156 pf
->max_rx_wm_flows
= le32_to_cpu(resp
->max_rx_wm_flows
);
5157 if (flags
& FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED
)
5158 bp
->flags
|= BNXT_FLAG_WOL_CAP
;
5160 #ifdef CONFIG_BNXT_SRIOV
5161 struct bnxt_vf_info
*vf
= &bp
->vf
;
5163 vf
->fw_fid
= le16_to_cpu(resp
->fid
);
5164 memcpy(vf
->mac_addr
, resp
->mac_address
, ETH_ALEN
);
5168 hwrm_func_qcaps_exit
:
5169 mutex_unlock(&bp
->hwrm_cmd_lock
);
5173 static int bnxt_hwrm_func_qcaps(struct bnxt
*bp
)
5177 rc
= __bnxt_hwrm_func_qcaps(bp
);
5180 if (bp
->hwrm_spec_code
>= 0x10803) {
5181 rc
= bnxt_hwrm_func_resc_qcaps(bp
);
5183 bp
->flags
|= BNXT_FLAG_NEW_RM
;
5188 static int bnxt_hwrm_func_reset(struct bnxt
*bp
)
5190 struct hwrm_func_reset_input req
= {0};
5192 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_RESET
, -1, -1);
5195 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_RESET_TIMEOUT
);
5198 static int bnxt_hwrm_queue_qportcfg(struct bnxt
*bp
)
5201 struct hwrm_queue_qportcfg_input req
= {0};
5202 struct hwrm_queue_qportcfg_output
*resp
= bp
->hwrm_cmd_resp_addr
;
5205 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_QUEUE_QPORTCFG
, -1, -1);
5207 mutex_lock(&bp
->hwrm_cmd_lock
);
5208 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
5212 if (!resp
->max_configurable_queues
) {
5216 bp
->max_tc
= resp
->max_configurable_queues
;
5217 bp
->max_lltc
= resp
->max_configurable_lossless_queues
;
5218 if (bp
->max_tc
> BNXT_MAX_QUEUE
)
5219 bp
->max_tc
= BNXT_MAX_QUEUE
;
5221 if (resp
->queue_cfg_info
& QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG
)
5224 if (bp
->max_lltc
> bp
->max_tc
)
5225 bp
->max_lltc
= bp
->max_tc
;
5227 qptr
= &resp
->queue_id0
;
5228 for (i
= 0; i
< bp
->max_tc
; i
++) {
5229 bp
->q_info
[i
].queue_id
= *qptr
++;
5230 bp
->q_info
[i
].queue_profile
= *qptr
++;
5234 mutex_unlock(&bp
->hwrm_cmd_lock
);
5238 static int bnxt_hwrm_ver_get(struct bnxt
*bp
)
5241 struct hwrm_ver_get_input req
= {0};
5242 struct hwrm_ver_get_output
*resp
= bp
->hwrm_cmd_resp_addr
;
5245 bp
->hwrm_max_req_len
= HWRM_MAX_REQ_LEN
;
5246 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VER_GET
, -1, -1);
5247 req
.hwrm_intf_maj
= HWRM_VERSION_MAJOR
;
5248 req
.hwrm_intf_min
= HWRM_VERSION_MINOR
;
5249 req
.hwrm_intf_upd
= HWRM_VERSION_UPDATE
;
5250 mutex_lock(&bp
->hwrm_cmd_lock
);
5251 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
5253 goto hwrm_ver_get_exit
;
5255 memcpy(&bp
->ver_resp
, resp
, sizeof(struct hwrm_ver_get_output
));
5257 bp
->hwrm_spec_code
= resp
->hwrm_intf_maj_8b
<< 16 |
5258 resp
->hwrm_intf_min_8b
<< 8 |
5259 resp
->hwrm_intf_upd_8b
;
5260 if (resp
->hwrm_intf_maj_8b
< 1) {
5261 netdev_warn(bp
->dev
, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
5262 resp
->hwrm_intf_maj_8b
, resp
->hwrm_intf_min_8b
,
5263 resp
->hwrm_intf_upd_8b
);
5264 netdev_warn(bp
->dev
, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
5266 snprintf(bp
->fw_ver_str
, BC_HWRM_STR_LEN
, "%d.%d.%d.%d",
5267 resp
->hwrm_fw_maj_8b
, resp
->hwrm_fw_min_8b
,
5268 resp
->hwrm_fw_bld_8b
, resp
->hwrm_fw_rsvd_8b
);
5270 bp
->hwrm_cmd_timeout
= le16_to_cpu(resp
->def_req_timeout
);
5271 if (!bp
->hwrm_cmd_timeout
)
5272 bp
->hwrm_cmd_timeout
= DFLT_HWRM_CMD_TIMEOUT
;
5274 if (resp
->hwrm_intf_maj_8b
>= 1)
5275 bp
->hwrm_max_req_len
= le16_to_cpu(resp
->max_req_win_len
);
5277 bp
->chip_num
= le16_to_cpu(resp
->chip_num
);
5278 if (bp
->chip_num
== CHIP_NUM_58700
&& !resp
->chip_rev
&&
5280 bp
->flags
|= BNXT_FLAG_CHIP_NITRO_A0
;
5282 dev_caps_cfg
= le32_to_cpu(resp
->dev_caps_cfg
);
5283 if ((dev_caps_cfg
& VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED
) &&
5284 (dev_caps_cfg
& VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED
))
5285 bp
->flags
|= BNXT_FLAG_SHORT_CMD
;
5288 mutex_unlock(&bp
->hwrm_cmd_lock
);
5292 int bnxt_hwrm_fw_set_time(struct bnxt
*bp
)
5294 struct hwrm_fw_set_time_input req
= {0};
5296 time64_t now
= ktime_get_real_seconds();
5298 if (bp
->hwrm_spec_code
< 0x10400)
5301 time64_to_tm(now
, 0, &tm
);
5302 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FW_SET_TIME
, -1, -1);
5303 req
.year
= cpu_to_le16(1900 + tm
.tm_year
);
5304 req
.month
= 1 + tm
.tm_mon
;
5305 req
.day
= tm
.tm_mday
;
5306 req
.hour
= tm
.tm_hour
;
5307 req
.minute
= tm
.tm_min
;
5308 req
.second
= tm
.tm_sec
;
5309 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
5312 static int bnxt_hwrm_port_qstats(struct bnxt
*bp
)
5315 struct bnxt_pf_info
*pf
= &bp
->pf
;
5316 struct hwrm_port_qstats_input req
= {0};
5318 if (!(bp
->flags
& BNXT_FLAG_PORT_STATS
))
5321 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_QSTATS
, -1, -1);
5322 req
.port_id
= cpu_to_le16(pf
->port_id
);
5323 req
.tx_stat_host_addr
= cpu_to_le64(bp
->hw_tx_port_stats_map
);
5324 req
.rx_stat_host_addr
= cpu_to_le64(bp
->hw_rx_port_stats_map
);
5325 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
5329 static void bnxt_hwrm_free_tunnel_ports(struct bnxt
*bp
)
5331 if (bp
->vxlan_port_cnt
) {
5332 bnxt_hwrm_tunnel_dst_port_free(
5333 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
);
5335 bp
->vxlan_port_cnt
= 0;
5336 if (bp
->nge_port_cnt
) {
5337 bnxt_hwrm_tunnel_dst_port_free(
5338 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
);
5340 bp
->nge_port_cnt
= 0;
5343 static int bnxt_set_tpa(struct bnxt
*bp
, bool set_tpa
)
5349 tpa_flags
= bp
->flags
& BNXT_FLAG_TPA
;
5350 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
5351 rc
= bnxt_hwrm_vnic_set_tpa(bp
, i
, tpa_flags
);
5353 netdev_err(bp
->dev
, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
5361 static void bnxt_hwrm_clear_vnic_rss(struct bnxt
*bp
)
5365 for (i
= 0; i
< bp
->nr_vnics
; i
++)
5366 bnxt_hwrm_vnic_set_rss(bp
, i
, false);
5369 static void bnxt_hwrm_resource_free(struct bnxt
*bp
, bool close_path
,
5372 if (bp
->vnic_info
) {
5373 bnxt_hwrm_clear_vnic_filter(bp
);
5374 /* clear all RSS setting before free vnic ctx */
5375 bnxt_hwrm_clear_vnic_rss(bp
);
5376 bnxt_hwrm_vnic_ctx_free(bp
);
5377 /* before free the vnic, undo the vnic tpa settings */
5378 if (bp
->flags
& BNXT_FLAG_TPA
)
5379 bnxt_set_tpa(bp
, false);
5380 bnxt_hwrm_vnic_free(bp
);
5382 bnxt_hwrm_ring_free(bp
, close_path
);
5383 bnxt_hwrm_ring_grp_free(bp
);
5385 bnxt_hwrm_stat_ctx_free(bp
);
5386 bnxt_hwrm_free_tunnel_ports(bp
);
5390 static int bnxt_hwrm_set_br_mode(struct bnxt
*bp
, u16 br_mode
)
5392 struct hwrm_func_cfg_input req
= {0};
5395 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_CFG
, -1, -1);
5396 req
.fid
= cpu_to_le16(0xffff);
5397 req
.enables
= cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE
);
5398 if (br_mode
== BRIDGE_MODE_VEB
)
5399 req
.evb_mode
= FUNC_CFG_REQ_EVB_MODE_VEB
;
5400 else if (br_mode
== BRIDGE_MODE_VEPA
)
5401 req
.evb_mode
= FUNC_CFG_REQ_EVB_MODE_VEPA
;
5404 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
5410 static int bnxt_hwrm_set_cache_line_size(struct bnxt
*bp
, int size
)
5412 struct hwrm_func_cfg_input req
= {0};
5415 if (BNXT_VF(bp
) || bp
->hwrm_spec_code
< 0x10803)
5418 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_CFG
, -1, -1);
5419 req
.fid
= cpu_to_le16(0xffff);
5420 req
.enables
= cpu_to_le32(FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE
);
5421 req
.cache_linesize
= FUNC_QCFG_RESP_CACHE_LINESIZE_CACHE_LINESIZE_64
;
5423 req
.cache_linesize
=
5424 FUNC_QCFG_RESP_CACHE_LINESIZE_CACHE_LINESIZE_128
;
5426 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
5432 static int bnxt_setup_vnic(struct bnxt
*bp
, u16 vnic_id
)
5434 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
5437 if (vnic
->flags
& BNXT_VNIC_RFS_NEW_RSS_FLAG
)
5440 /* allocate context for vnic */
5441 rc
= bnxt_hwrm_vnic_ctx_alloc(bp
, vnic_id
, 0);
5443 netdev_err(bp
->dev
, "hwrm vnic %d alloc failure rc: %x\n",
5445 goto vnic_setup_err
;
5447 bp
->rsscos_nr_ctxs
++;
5449 if (BNXT_CHIP_TYPE_NITRO_A0(bp
)) {
5450 rc
= bnxt_hwrm_vnic_ctx_alloc(bp
, vnic_id
, 1);
5452 netdev_err(bp
->dev
, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
5454 goto vnic_setup_err
;
5456 bp
->rsscos_nr_ctxs
++;
5460 /* configure default vnic, ring grp */
5461 rc
= bnxt_hwrm_vnic_cfg(bp
, vnic_id
);
5463 netdev_err(bp
->dev
, "hwrm vnic %d cfg failure rc: %x\n",
5465 goto vnic_setup_err
;
5468 /* Enable RSS hashing on vnic */
5469 rc
= bnxt_hwrm_vnic_set_rss(bp
, vnic_id
, true);
5471 netdev_err(bp
->dev
, "hwrm vnic %d set rss failure rc: %x\n",
5473 goto vnic_setup_err
;
5476 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
) {
5477 rc
= bnxt_hwrm_vnic_set_hds(bp
, vnic_id
);
5479 netdev_err(bp
->dev
, "hwrm vnic %d set hds failure rc: %x\n",
5488 static int bnxt_alloc_rfs_vnics(struct bnxt
*bp
)
5490 #ifdef CONFIG_RFS_ACCEL
5493 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
5494 struct bnxt_vnic_info
*vnic
;
5495 u16 vnic_id
= i
+ 1;
5498 if (vnic_id
>= bp
->nr_vnics
)
5501 vnic
= &bp
->vnic_info
[vnic_id
];
5502 vnic
->flags
|= BNXT_VNIC_RFS_FLAG
;
5503 if (bp
->flags
& BNXT_FLAG_NEW_RSS_CAP
)
5504 vnic
->flags
|= BNXT_VNIC_RFS_NEW_RSS_FLAG
;
5505 rc
= bnxt_hwrm_vnic_alloc(bp
, vnic_id
, ring_id
, 1);
5507 netdev_err(bp
->dev
, "hwrm vnic %d alloc failure rc: %x\n",
5511 rc
= bnxt_setup_vnic(bp
, vnic_id
);
5521 /* Allow PF and VF with default VLAN to be in promiscuous mode */
5522 static bool bnxt_promisc_ok(struct bnxt
*bp
)
5524 #ifdef CONFIG_BNXT_SRIOV
5525 if (BNXT_VF(bp
) && !bp
->vf
.vlan
)
5531 static int bnxt_setup_nitroa0_vnic(struct bnxt
*bp
)
5533 unsigned int rc
= 0;
5535 rc
= bnxt_hwrm_vnic_alloc(bp
, 1, bp
->rx_nr_rings
- 1, 1);
5537 netdev_err(bp
->dev
, "Cannot allocate special vnic for NS2 A0: %x\n",
5542 rc
= bnxt_hwrm_vnic_cfg(bp
, 1);
5544 netdev_err(bp
->dev
, "Cannot allocate special vnic for NS2 A0: %x\n",
5551 static int bnxt_cfg_rx_mode(struct bnxt
*);
5552 static bool bnxt_mc_list_updated(struct bnxt
*, u32
*);
5554 static int bnxt_init_chip(struct bnxt
*bp
, bool irq_re_init
)
5556 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
5558 unsigned int rx_nr_rings
= bp
->rx_nr_rings
;
5561 rc
= bnxt_hwrm_stat_ctx_alloc(bp
);
5563 netdev_err(bp
->dev
, "hwrm stat ctx alloc failure rc: %x\n",
5569 rc
= bnxt_hwrm_ring_alloc(bp
);
5571 netdev_err(bp
->dev
, "hwrm ring alloc failure rc: %x\n", rc
);
5575 rc
= bnxt_hwrm_ring_grp_alloc(bp
);
5577 netdev_err(bp
->dev
, "hwrm_ring_grp alloc failure: %x\n", rc
);
5581 if (BNXT_CHIP_TYPE_NITRO_A0(bp
))
5584 /* default vnic 0 */
5585 rc
= bnxt_hwrm_vnic_alloc(bp
, 0, 0, rx_nr_rings
);
5587 netdev_err(bp
->dev
, "hwrm vnic alloc failure rc: %x\n", rc
);
5591 rc
= bnxt_setup_vnic(bp
, 0);
5595 if (bp
->flags
& BNXT_FLAG_RFS
) {
5596 rc
= bnxt_alloc_rfs_vnics(bp
);
5601 if (bp
->flags
& BNXT_FLAG_TPA
) {
5602 rc
= bnxt_set_tpa(bp
, true);
5608 bnxt_update_vf_mac(bp
);
5610 /* Filter for default vnic 0 */
5611 rc
= bnxt_hwrm_set_vnic_filter(bp
, 0, 0, bp
->dev
->dev_addr
);
5613 netdev_err(bp
->dev
, "HWRM vnic filter failure rc: %x\n", rc
);
5616 vnic
->uc_filter_count
= 1;
5618 vnic
->rx_mask
= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST
;
5620 if ((bp
->dev
->flags
& IFF_PROMISC
) && bnxt_promisc_ok(bp
))
5621 vnic
->rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
;
5623 if (bp
->dev
->flags
& IFF_ALLMULTI
) {
5624 vnic
->rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
;
5625 vnic
->mc_list_count
= 0;
5629 bnxt_mc_list_updated(bp
, &mask
);
5630 vnic
->rx_mask
|= mask
;
5633 rc
= bnxt_cfg_rx_mode(bp
);
5637 rc
= bnxt_hwrm_set_coal(bp
);
5639 netdev_warn(bp
->dev
, "HWRM set coalescing failure rc: %x\n",
5642 if (BNXT_CHIP_TYPE_NITRO_A0(bp
)) {
5643 rc
= bnxt_setup_nitroa0_vnic(bp
);
5645 netdev_err(bp
->dev
, "Special vnic setup failure for NS2 A0 rc: %x\n",
5650 bnxt_hwrm_func_qcfg(bp
);
5651 netdev_update_features(bp
->dev
);
5657 bnxt_hwrm_resource_free(bp
, 0, true);
5662 static int bnxt_shutdown_nic(struct bnxt
*bp
, bool irq_re_init
)
5664 bnxt_hwrm_resource_free(bp
, 1, irq_re_init
);
5668 static int bnxt_init_nic(struct bnxt
*bp
, bool irq_re_init
)
5670 bnxt_init_cp_rings(bp
);
5671 bnxt_init_rx_rings(bp
);
5672 bnxt_init_tx_rings(bp
);
5673 bnxt_init_ring_grps(bp
, irq_re_init
);
5674 bnxt_init_vnics(bp
);
5676 return bnxt_init_chip(bp
, irq_re_init
);
5679 static int bnxt_set_real_num_queues(struct bnxt
*bp
)
5682 struct net_device
*dev
= bp
->dev
;
5684 rc
= netif_set_real_num_tx_queues(dev
, bp
->tx_nr_rings
-
5685 bp
->tx_nr_rings_xdp
);
5689 rc
= netif_set_real_num_rx_queues(dev
, bp
->rx_nr_rings
);
5693 #ifdef CONFIG_RFS_ACCEL
5694 if (bp
->flags
& BNXT_FLAG_RFS
)
5695 dev
->rx_cpu_rmap
= alloc_irq_cpu_rmap(bp
->rx_nr_rings
);
5701 static int bnxt_trim_rings(struct bnxt
*bp
, int *rx
, int *tx
, int max
,
5704 int _rx
= *rx
, _tx
= *tx
;
5707 *rx
= min_t(int, _rx
, max
);
5708 *tx
= min_t(int, _tx
, max
);
5713 while (_rx
+ _tx
> max
) {
5714 if (_rx
> _tx
&& _rx
> 1)
5725 static void bnxt_setup_msix(struct bnxt
*bp
)
5727 const int len
= sizeof(bp
->irq_tbl
[0].name
);
5728 struct net_device
*dev
= bp
->dev
;
5731 tcs
= netdev_get_num_tc(dev
);
5735 for (i
= 0; i
< tcs
; i
++) {
5736 count
= bp
->tx_nr_rings_per_tc
;
5738 netdev_set_tc_queue(dev
, i
, count
, off
);
5742 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
5745 if (bp
->flags
& BNXT_FLAG_SHARED_RINGS
)
5747 else if (i
< bp
->rx_nr_rings
)
5752 snprintf(bp
->irq_tbl
[i
].name
, len
, "%s-%s-%d", dev
->name
, attr
,
5754 bp
->irq_tbl
[i
].handler
= bnxt_msix
;
5758 static void bnxt_setup_inta(struct bnxt
*bp
)
5760 const int len
= sizeof(bp
->irq_tbl
[0].name
);
5762 if (netdev_get_num_tc(bp
->dev
))
5763 netdev_reset_tc(bp
->dev
);
5765 snprintf(bp
->irq_tbl
[0].name
, len
, "%s-%s-%d", bp
->dev
->name
, "TxRx",
5767 bp
->irq_tbl
[0].handler
= bnxt_inta
;
5770 static int bnxt_setup_int_mode(struct bnxt
*bp
)
5774 if (bp
->flags
& BNXT_FLAG_USING_MSIX
)
5775 bnxt_setup_msix(bp
);
5777 bnxt_setup_inta(bp
);
5779 rc
= bnxt_set_real_num_queues(bp
);
5783 #ifdef CONFIG_RFS_ACCEL
5784 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt
*bp
)
5786 return bp
->hw_resc
.max_rsscos_ctxs
;
5789 static unsigned int bnxt_get_max_func_vnics(struct bnxt
*bp
)
5791 return bp
->hw_resc
.max_vnics
;
5795 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt
*bp
)
5797 return bp
->hw_resc
.max_stat_ctxs
;
5800 void bnxt_set_max_func_stat_ctxs(struct bnxt
*bp
, unsigned int max
)
5802 bp
->hw_resc
.max_stat_ctxs
= max
;
5805 unsigned int bnxt_get_max_func_cp_rings(struct bnxt
*bp
)
5807 return bp
->hw_resc
.max_cp_rings
;
5810 void bnxt_set_max_func_cp_rings(struct bnxt
*bp
, unsigned int max
)
5812 bp
->hw_resc
.max_cp_rings
= max
;
5815 static unsigned int bnxt_get_max_func_irqs(struct bnxt
*bp
)
5817 struct bnxt_hw_resc
*hw_resc
= &bp
->hw_resc
;
5819 return min_t(unsigned int, hw_resc
->max_irqs
, hw_resc
->max_cp_rings
);
5822 void bnxt_set_max_func_irqs(struct bnxt
*bp
, unsigned int max_irqs
)
5824 bp
->hw_resc
.max_irqs
= max_irqs
;
5827 static int bnxt_init_msix(struct bnxt
*bp
)
5829 int i
, total_vecs
, rc
= 0, min
= 1;
5830 struct msix_entry
*msix_ent
;
5832 total_vecs
= bnxt_get_max_func_irqs(bp
);
5833 msix_ent
= kcalloc(total_vecs
, sizeof(struct msix_entry
), GFP_KERNEL
);
5837 for (i
= 0; i
< total_vecs
; i
++) {
5838 msix_ent
[i
].entry
= i
;
5839 msix_ent
[i
].vector
= 0;
5842 if (!(bp
->flags
& BNXT_FLAG_SHARED_RINGS
))
5845 total_vecs
= pci_enable_msix_range(bp
->pdev
, msix_ent
, min
, total_vecs
);
5846 if (total_vecs
< 0) {
5848 goto msix_setup_exit
;
5851 bp
->irq_tbl
= kcalloc(total_vecs
, sizeof(struct bnxt_irq
), GFP_KERNEL
);
5853 for (i
= 0; i
< total_vecs
; i
++)
5854 bp
->irq_tbl
[i
].vector
= msix_ent
[i
].vector
;
5856 bp
->total_irqs
= total_vecs
;
5857 /* Trim rings based upon num of vectors allocated */
5858 rc
= bnxt_trim_rings(bp
, &bp
->rx_nr_rings
, &bp
->tx_nr_rings
,
5859 total_vecs
, min
== 1);
5861 goto msix_setup_exit
;
5863 bp
->cp_nr_rings
= (min
== 1) ?
5864 max_t(int, bp
->tx_nr_rings
, bp
->rx_nr_rings
) :
5865 bp
->tx_nr_rings
+ bp
->rx_nr_rings
;
5869 goto msix_setup_exit
;
5871 bp
->flags
|= BNXT_FLAG_USING_MSIX
;
5876 netdev_err(bp
->dev
, "bnxt_init_msix err: %x\n", rc
);
5879 pci_disable_msix(bp
->pdev
);
5884 static int bnxt_init_inta(struct bnxt
*bp
)
5886 bp
->irq_tbl
= kcalloc(1, sizeof(struct bnxt_irq
), GFP_KERNEL
);
5891 bp
->rx_nr_rings
= 1;
5892 bp
->tx_nr_rings
= 1;
5893 bp
->cp_nr_rings
= 1;
5894 bp
->flags
|= BNXT_FLAG_SHARED_RINGS
;
5895 bp
->irq_tbl
[0].vector
= bp
->pdev
->irq
;
5899 static int bnxt_init_int_mode(struct bnxt
*bp
)
5903 if (bp
->flags
& BNXT_FLAG_MSIX_CAP
)
5904 rc
= bnxt_init_msix(bp
);
5906 if (!(bp
->flags
& BNXT_FLAG_USING_MSIX
) && BNXT_PF(bp
)) {
5907 /* fallback to INTA */
5908 rc
= bnxt_init_inta(bp
);
5913 static void bnxt_clear_int_mode(struct bnxt
*bp
)
5915 if (bp
->flags
& BNXT_FLAG_USING_MSIX
)
5916 pci_disable_msix(bp
->pdev
);
5920 bp
->flags
&= ~BNXT_FLAG_USING_MSIX
;
5923 static int bnxt_reserve_rings(struct bnxt
*bp
)
5925 int orig_cp
= bp
->hw_resc
.resv_cp_rings
;
5926 int tcs
= netdev_get_num_tc(bp
->dev
);
5929 if (!bnxt_need_reserve_rings(bp
))
5932 rc
= __bnxt_reserve_rings(bp
);
5934 netdev_err(bp
->dev
, "ring reservation failure rc: %d\n", rc
);
5937 if ((bp
->flags
& BNXT_FLAG_NEW_RM
) && bp
->cp_nr_rings
> orig_cp
) {
5938 bnxt_clear_int_mode(bp
);
5939 rc
= bnxt_init_int_mode(bp
);
5943 if (tcs
&& (bp
->tx_nr_rings_per_tc
* tcs
!= bp
->tx_nr_rings
)) {
5944 netdev_err(bp
->dev
, "tx ring reservation failure\n");
5945 netdev_reset_tc(bp
->dev
);
5946 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
;
5949 bp
->num_stat_ctxs
= bp
->cp_nr_rings
;
5953 static void bnxt_free_irq(struct bnxt
*bp
)
5955 struct bnxt_irq
*irq
;
5958 #ifdef CONFIG_RFS_ACCEL
5959 free_irq_cpu_rmap(bp
->dev
->rx_cpu_rmap
);
5960 bp
->dev
->rx_cpu_rmap
= NULL
;
5965 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
5966 irq
= &bp
->irq_tbl
[i
];
5967 if (irq
->requested
) {
5968 if (irq
->have_cpumask
) {
5969 irq_set_affinity_hint(irq
->vector
, NULL
);
5970 free_cpumask_var(irq
->cpu_mask
);
5971 irq
->have_cpumask
= 0;
5973 free_irq(irq
->vector
, bp
->bnapi
[i
]);
5980 static int bnxt_request_irq(struct bnxt
*bp
)
5983 unsigned long flags
= 0;
5984 #ifdef CONFIG_RFS_ACCEL
5985 struct cpu_rmap
*rmap
= bp
->dev
->rx_cpu_rmap
;
5988 if (!(bp
->flags
& BNXT_FLAG_USING_MSIX
))
5989 flags
= IRQF_SHARED
;
5991 for (i
= 0, j
= 0; i
< bp
->cp_nr_rings
; i
++) {
5992 struct bnxt_irq
*irq
= &bp
->irq_tbl
[i
];
5993 #ifdef CONFIG_RFS_ACCEL
5994 if (rmap
&& bp
->bnapi
[i
]->rx_ring
) {
5995 rc
= irq_cpu_rmap_add(rmap
, irq
->vector
);
5997 netdev_warn(bp
->dev
, "failed adding irq rmap for ring %d\n",
6002 rc
= request_irq(irq
->vector
, irq
->handler
, flags
, irq
->name
,
6009 if (zalloc_cpumask_var(&irq
->cpu_mask
, GFP_KERNEL
)) {
6010 int numa_node
= dev_to_node(&bp
->pdev
->dev
);
6012 irq
->have_cpumask
= 1;
6013 cpumask_set_cpu(cpumask_local_spread(i
, numa_node
),
6015 rc
= irq_set_affinity_hint(irq
->vector
, irq
->cpu_mask
);
6017 netdev_warn(bp
->dev
,
6018 "Set affinity failed, IRQ = %d\n",
6027 static void bnxt_del_napi(struct bnxt
*bp
)
6034 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
6035 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
6037 napi_hash_del(&bnapi
->napi
);
6038 netif_napi_del(&bnapi
->napi
);
6040 /* We called napi_hash_del() before netif_napi_del(), we need
6041 * to respect an RCU grace period before freeing napi structures.
6046 static void bnxt_init_napi(struct bnxt
*bp
)
6049 unsigned int cp_nr_rings
= bp
->cp_nr_rings
;
6050 struct bnxt_napi
*bnapi
;
6052 if (bp
->flags
& BNXT_FLAG_USING_MSIX
) {
6053 if (BNXT_CHIP_TYPE_NITRO_A0(bp
))
6055 for (i
= 0; i
< cp_nr_rings
; i
++) {
6056 bnapi
= bp
->bnapi
[i
];
6057 netif_napi_add(bp
->dev
, &bnapi
->napi
,
6060 if (BNXT_CHIP_TYPE_NITRO_A0(bp
)) {
6061 bnapi
= bp
->bnapi
[cp_nr_rings
];
6062 netif_napi_add(bp
->dev
, &bnapi
->napi
,
6063 bnxt_poll_nitroa0
, 64);
6066 bnapi
= bp
->bnapi
[0];
6067 netif_napi_add(bp
->dev
, &bnapi
->napi
, bnxt_poll
, 64);
6071 static void bnxt_disable_napi(struct bnxt
*bp
)
6078 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
6079 struct bnxt_cp_ring_info
*cpr
= &bp
->bnapi
[i
]->cp_ring
;
6081 if (bp
->bnapi
[i
]->rx_ring
)
6082 cancel_work_sync(&cpr
->dim
.work
);
6084 napi_disable(&bp
->bnapi
[i
]->napi
);
6088 static void bnxt_enable_napi(struct bnxt
*bp
)
6092 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
6093 struct bnxt_cp_ring_info
*cpr
= &bp
->bnapi
[i
]->cp_ring
;
6094 bp
->bnapi
[i
]->in_reset
= false;
6096 if (bp
->bnapi
[i
]->rx_ring
) {
6097 INIT_WORK(&cpr
->dim
.work
, bnxt_dim_work
);
6098 cpr
->dim
.mode
= NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE
;
6100 napi_enable(&bp
->bnapi
[i
]->napi
);
6104 void bnxt_tx_disable(struct bnxt
*bp
)
6107 struct bnxt_tx_ring_info
*txr
;
6110 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
6111 txr
= &bp
->tx_ring
[i
];
6112 txr
->dev_state
= BNXT_DEV_STATE_CLOSING
;
6115 /* Stop all TX queues */
6116 netif_tx_disable(bp
->dev
);
6117 netif_carrier_off(bp
->dev
);
6120 void bnxt_tx_enable(struct bnxt
*bp
)
6123 struct bnxt_tx_ring_info
*txr
;
6125 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
6126 txr
= &bp
->tx_ring
[i
];
6129 netif_tx_wake_all_queues(bp
->dev
);
6130 if (bp
->link_info
.link_up
)
6131 netif_carrier_on(bp
->dev
);
6134 static void bnxt_report_link(struct bnxt
*bp
)
6136 if (bp
->link_info
.link_up
) {
6138 const char *flow_ctrl
;
6142 netif_carrier_on(bp
->dev
);
6143 if (bp
->link_info
.duplex
== BNXT_LINK_DUPLEX_FULL
)
6147 if (bp
->link_info
.pause
== BNXT_LINK_PAUSE_BOTH
)
6148 flow_ctrl
= "ON - receive & transmit";
6149 else if (bp
->link_info
.pause
== BNXT_LINK_PAUSE_TX
)
6150 flow_ctrl
= "ON - transmit";
6151 else if (bp
->link_info
.pause
== BNXT_LINK_PAUSE_RX
)
6152 flow_ctrl
= "ON - receive";
6155 speed
= bnxt_fw_to_ethtool_speed(bp
->link_info
.link_speed
);
6156 netdev_info(bp
->dev
, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n",
6157 speed
, duplex
, flow_ctrl
);
6158 if (bp
->flags
& BNXT_FLAG_EEE_CAP
)
6159 netdev_info(bp
->dev
, "EEE is %s\n",
6160 bp
->eee
.eee_active
? "active" :
6162 fec
= bp
->link_info
.fec_cfg
;
6163 if (!(fec
& PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED
))
6164 netdev_info(bp
->dev
, "FEC autoneg %s encodings: %s\n",
6165 (fec
& BNXT_FEC_AUTONEG
) ? "on" : "off",
6166 (fec
& BNXT_FEC_ENC_BASE_R
) ? "BaseR" :
6167 (fec
& BNXT_FEC_ENC_RS
) ? "RS" : "None");
6169 netif_carrier_off(bp
->dev
);
6170 netdev_err(bp
->dev
, "NIC Link is Down\n");
6174 static int bnxt_hwrm_phy_qcaps(struct bnxt
*bp
)
6177 struct hwrm_port_phy_qcaps_input req
= {0};
6178 struct hwrm_port_phy_qcaps_output
*resp
= bp
->hwrm_cmd_resp_addr
;
6179 struct bnxt_link_info
*link_info
= &bp
->link_info
;
6181 if (bp
->hwrm_spec_code
< 0x10201)
6184 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_QCAPS
, -1, -1);
6186 mutex_lock(&bp
->hwrm_cmd_lock
);
6187 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
6189 goto hwrm_phy_qcaps_exit
;
6191 if (resp
->flags
& PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED
) {
6192 struct ethtool_eee
*eee
= &bp
->eee
;
6193 u16 fw_speeds
= le16_to_cpu(resp
->supported_speeds_eee_mode
);
6195 bp
->flags
|= BNXT_FLAG_EEE_CAP
;
6196 eee
->supported
= _bnxt_fw_to_ethtool_adv_spds(fw_speeds
, 0);
6197 bp
->lpi_tmr_lo
= le32_to_cpu(resp
->tx_lpi_timer_low
) &
6198 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK
;
6199 bp
->lpi_tmr_hi
= le32_to_cpu(resp
->valid_tx_lpi_timer_high
) &
6200 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK
;
6202 if (resp
->supported_speeds_auto_mode
)
6203 link_info
->support_auto_speeds
=
6204 le16_to_cpu(resp
->supported_speeds_auto_mode
);
6206 bp
->port_count
= resp
->port_cnt
;
6208 hwrm_phy_qcaps_exit
:
6209 mutex_unlock(&bp
->hwrm_cmd_lock
);
6213 static int bnxt_update_link(struct bnxt
*bp
, bool chng_link_state
)
6216 struct bnxt_link_info
*link_info
= &bp
->link_info
;
6217 struct hwrm_port_phy_qcfg_input req
= {0};
6218 struct hwrm_port_phy_qcfg_output
*resp
= bp
->hwrm_cmd_resp_addr
;
6219 u8 link_up
= link_info
->link_up
;
6222 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_QCFG
, -1, -1);
6224 mutex_lock(&bp
->hwrm_cmd_lock
);
6225 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
6227 mutex_unlock(&bp
->hwrm_cmd_lock
);
6231 memcpy(&link_info
->phy_qcfg_resp
, resp
, sizeof(*resp
));
6232 link_info
->phy_link_status
= resp
->link
;
6233 link_info
->duplex
= resp
->duplex_cfg
;
6234 if (bp
->hwrm_spec_code
>= 0x10800)
6235 link_info
->duplex
= resp
->duplex_state
;
6236 link_info
->pause
= resp
->pause
;
6237 link_info
->auto_mode
= resp
->auto_mode
;
6238 link_info
->auto_pause_setting
= resp
->auto_pause
;
6239 link_info
->lp_pause
= resp
->link_partner_adv_pause
;
6240 link_info
->force_pause_setting
= resp
->force_pause
;
6241 link_info
->duplex_setting
= resp
->duplex_cfg
;
6242 if (link_info
->phy_link_status
== BNXT_LINK_LINK
)
6243 link_info
->link_speed
= le16_to_cpu(resp
->link_speed
);
6245 link_info
->link_speed
= 0;
6246 link_info
->force_link_speed
= le16_to_cpu(resp
->force_link_speed
);
6247 link_info
->support_speeds
= le16_to_cpu(resp
->support_speeds
);
6248 link_info
->auto_link_speeds
= le16_to_cpu(resp
->auto_link_speed_mask
);
6249 link_info
->lp_auto_link_speeds
=
6250 le16_to_cpu(resp
->link_partner_adv_speeds
);
6251 link_info
->preemphasis
= le32_to_cpu(resp
->preemphasis
);
6252 link_info
->phy_ver
[0] = resp
->phy_maj
;
6253 link_info
->phy_ver
[1] = resp
->phy_min
;
6254 link_info
->phy_ver
[2] = resp
->phy_bld
;
6255 link_info
->media_type
= resp
->media_type
;
6256 link_info
->phy_type
= resp
->phy_type
;
6257 link_info
->transceiver
= resp
->xcvr_pkg_type
;
6258 link_info
->phy_addr
= resp
->eee_config_phy_addr
&
6259 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK
;
6260 link_info
->module_status
= resp
->module_status
;
6262 if (bp
->flags
& BNXT_FLAG_EEE_CAP
) {
6263 struct ethtool_eee
*eee
= &bp
->eee
;
6266 eee
->eee_active
= 0;
6267 if (resp
->eee_config_phy_addr
&
6268 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE
) {
6269 eee
->eee_active
= 1;
6270 fw_speeds
= le16_to_cpu(
6271 resp
->link_partner_adv_eee_link_speed_mask
);
6272 eee
->lp_advertised
=
6273 _bnxt_fw_to_ethtool_adv_spds(fw_speeds
, 0);
6276 /* Pull initial EEE config */
6277 if (!chng_link_state
) {
6278 if (resp
->eee_config_phy_addr
&
6279 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED
)
6280 eee
->eee_enabled
= 1;
6282 fw_speeds
= le16_to_cpu(resp
->adv_eee_link_speed_mask
);
6284 _bnxt_fw_to_ethtool_adv_spds(fw_speeds
, 0);
6286 if (resp
->eee_config_phy_addr
&
6287 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI
) {
6290 eee
->tx_lpi_enabled
= 1;
6291 tmr
= resp
->xcvr_identifier_type_tx_lpi_timer
;
6292 eee
->tx_lpi_timer
= le32_to_cpu(tmr
) &
6293 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK
;
6298 link_info
->fec_cfg
= PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED
;
6299 if (bp
->hwrm_spec_code
>= 0x10504)
6300 link_info
->fec_cfg
= le16_to_cpu(resp
->fec_cfg
);
6302 /* TODO: need to add more logic to report VF link */
6303 if (chng_link_state
) {
6304 if (link_info
->phy_link_status
== BNXT_LINK_LINK
)
6305 link_info
->link_up
= 1;
6307 link_info
->link_up
= 0;
6308 if (link_up
!= link_info
->link_up
)
6309 bnxt_report_link(bp
);
6311 /* alwasy link down if not require to update link state */
6312 link_info
->link_up
= 0;
6314 mutex_unlock(&bp
->hwrm_cmd_lock
);
6316 diff
= link_info
->support_auto_speeds
^ link_info
->advertising
;
6317 if ((link_info
->support_auto_speeds
| diff
) !=
6318 link_info
->support_auto_speeds
) {
6319 /* An advertised speed is no longer supported, so we need to
6320 * update the advertisement settings. Caller holds RTNL
6321 * so we can modify link settings.
6323 link_info
->advertising
= link_info
->support_auto_speeds
;
6324 if (link_info
->autoneg
& BNXT_AUTONEG_SPEED
)
6325 bnxt_hwrm_set_link_setting(bp
, true, false);
6330 static void bnxt_get_port_module_status(struct bnxt
*bp
)
6332 struct bnxt_link_info
*link_info
= &bp
->link_info
;
6333 struct hwrm_port_phy_qcfg_output
*resp
= &link_info
->phy_qcfg_resp
;
6336 if (bnxt_update_link(bp
, true))
6339 module_status
= link_info
->module_status
;
6340 switch (module_status
) {
6341 case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX
:
6342 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN
:
6343 case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG
:
6344 netdev_warn(bp
->dev
, "Unqualified SFP+ module detected on port %d\n",
6346 if (bp
->hwrm_spec_code
>= 0x10201) {
6347 netdev_warn(bp
->dev
, "Module part number %s\n",
6348 resp
->phy_vendor_partnumber
);
6350 if (module_status
== PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX
)
6351 netdev_warn(bp
->dev
, "TX is disabled\n");
6352 if (module_status
== PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN
)
6353 netdev_warn(bp
->dev
, "SFP+ module is shutdown\n");
6358 bnxt_hwrm_set_pause_common(struct bnxt
*bp
, struct hwrm_port_phy_cfg_input
*req
)
6360 if (bp
->link_info
.autoneg
& BNXT_AUTONEG_FLOW_CTRL
) {
6361 if (bp
->hwrm_spec_code
>= 0x10201)
6363 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE
;
6364 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_RX
)
6365 req
->auto_pause
|= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX
;
6366 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_TX
)
6367 req
->auto_pause
|= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX
;
6369 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE
);
6371 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_RX
)
6372 req
->force_pause
|= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX
;
6373 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_TX
)
6374 req
->force_pause
|= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX
;
6376 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE
);
6377 if (bp
->hwrm_spec_code
>= 0x10201) {
6378 req
->auto_pause
= req
->force_pause
;
6379 req
->enables
|= cpu_to_le32(
6380 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE
);
6385 static void bnxt_hwrm_set_link_common(struct bnxt
*bp
,
6386 struct hwrm_port_phy_cfg_input
*req
)
6388 u8 autoneg
= bp
->link_info
.autoneg
;
6389 u16 fw_link_speed
= bp
->link_info
.req_link_speed
;
6390 u16 advertising
= bp
->link_info
.advertising
;
6392 if (autoneg
& BNXT_AUTONEG_SPEED
) {
6394 PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK
;
6396 req
->enables
|= cpu_to_le32(
6397 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK
);
6398 req
->auto_link_speed_mask
= cpu_to_le16(advertising
);
6400 req
->enables
|= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE
);
6402 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG
);
6404 req
->force_link_speed
= cpu_to_le16(fw_link_speed
);
6405 req
->flags
|= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE
);
6408 /* tell chimp that the setting takes effect immediately */
6409 req
->flags
|= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY
);
6412 int bnxt_hwrm_set_pause(struct bnxt
*bp
)
6414 struct hwrm_port_phy_cfg_input req
= {0};
6417 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_CFG
, -1, -1);
6418 bnxt_hwrm_set_pause_common(bp
, &req
);
6420 if ((bp
->link_info
.autoneg
& BNXT_AUTONEG_FLOW_CTRL
) ||
6421 bp
->link_info
.force_link_chng
)
6422 bnxt_hwrm_set_link_common(bp
, &req
);
6424 mutex_lock(&bp
->hwrm_cmd_lock
);
6425 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
6426 if (!rc
&& !(bp
->link_info
.autoneg
& BNXT_AUTONEG_FLOW_CTRL
)) {
6427 /* since changing of pause setting doesn't trigger any link
6428 * change event, the driver needs to update the current pause
6429 * result upon successfully return of the phy_cfg command
6431 bp
->link_info
.pause
=
6432 bp
->link_info
.force_pause_setting
= bp
->link_info
.req_flow_ctrl
;
6433 bp
->link_info
.auto_pause_setting
= 0;
6434 if (!bp
->link_info
.force_link_chng
)
6435 bnxt_report_link(bp
);
6437 bp
->link_info
.force_link_chng
= false;
6438 mutex_unlock(&bp
->hwrm_cmd_lock
);
6442 static void bnxt_hwrm_set_eee(struct bnxt
*bp
,
6443 struct hwrm_port_phy_cfg_input
*req
)
6445 struct ethtool_eee
*eee
= &bp
->eee
;
6447 if (eee
->eee_enabled
) {
6449 u32 flags
= PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE
;
6451 if (eee
->tx_lpi_enabled
)
6452 flags
|= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE
;
6454 flags
|= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE
;
6456 req
->flags
|= cpu_to_le32(flags
);
6457 eee_speeds
= bnxt_get_fw_auto_link_speeds(eee
->advertised
);
6458 req
->eee_link_speed_mask
= cpu_to_le16(eee_speeds
);
6459 req
->tx_lpi_timer
= cpu_to_le32(eee
->tx_lpi_timer
);
6461 req
->flags
|= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE
);
6465 int bnxt_hwrm_set_link_setting(struct bnxt
*bp
, bool set_pause
, bool set_eee
)
6467 struct hwrm_port_phy_cfg_input req
= {0};
6469 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_CFG
, -1, -1);
6471 bnxt_hwrm_set_pause_common(bp
, &req
);
6473 bnxt_hwrm_set_link_common(bp
, &req
);
6476 bnxt_hwrm_set_eee(bp
, &req
);
6477 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
6480 static int bnxt_hwrm_shutdown_link(struct bnxt
*bp
)
6482 struct hwrm_port_phy_cfg_input req
= {0};
6484 if (!BNXT_SINGLE_PF(bp
))
6487 if (pci_num_vf(bp
->pdev
))
6490 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_CFG
, -1, -1);
6491 req
.flags
= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN
);
6492 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
6495 static int bnxt_hwrm_port_led_qcaps(struct bnxt
*bp
)
6497 struct hwrm_port_led_qcaps_output
*resp
= bp
->hwrm_cmd_resp_addr
;
6498 struct hwrm_port_led_qcaps_input req
= {0};
6499 struct bnxt_pf_info
*pf
= &bp
->pf
;
6502 if (BNXT_VF(bp
) || bp
->hwrm_spec_code
< 0x10601)
6505 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_LED_QCAPS
, -1, -1);
6506 req
.port_id
= cpu_to_le16(pf
->port_id
);
6507 mutex_lock(&bp
->hwrm_cmd_lock
);
6508 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
6510 mutex_unlock(&bp
->hwrm_cmd_lock
);
6513 if (resp
->num_leds
> 0 && resp
->num_leds
< BNXT_MAX_LED
) {
6516 bp
->num_leds
= resp
->num_leds
;
6517 memcpy(bp
->leds
, &resp
->led0_id
, sizeof(bp
->leds
[0]) *
6519 for (i
= 0; i
< bp
->num_leds
; i
++) {
6520 struct bnxt_led_info
*led
= &bp
->leds
[i
];
6521 __le16 caps
= led
->led_state_caps
;
6523 if (!led
->led_group_id
||
6524 !BNXT_LED_ALT_BLINK_CAP(caps
)) {
6530 mutex_unlock(&bp
->hwrm_cmd_lock
);
6534 int bnxt_hwrm_alloc_wol_fltr(struct bnxt
*bp
)
6536 struct hwrm_wol_filter_alloc_input req
= {0};
6537 struct hwrm_wol_filter_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
6540 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_WOL_FILTER_ALLOC
, -1, -1);
6541 req
.port_id
= cpu_to_le16(bp
->pf
.port_id
);
6542 req
.wol_type
= WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT
;
6543 req
.enables
= cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS
);
6544 memcpy(req
.mac_address
, bp
->dev
->dev_addr
, ETH_ALEN
);
6545 mutex_lock(&bp
->hwrm_cmd_lock
);
6546 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
6548 bp
->wol_filter_id
= resp
->wol_filter_id
;
6549 mutex_unlock(&bp
->hwrm_cmd_lock
);
6553 int bnxt_hwrm_free_wol_fltr(struct bnxt
*bp
)
6555 struct hwrm_wol_filter_free_input req
= {0};
6558 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_WOL_FILTER_FREE
, -1, -1);
6559 req
.port_id
= cpu_to_le16(bp
->pf
.port_id
);
6560 req
.enables
= cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID
);
6561 req
.wol_filter_id
= bp
->wol_filter_id
;
6562 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
6566 static u16
bnxt_hwrm_get_wol_fltrs(struct bnxt
*bp
, u16 handle
)
6568 struct hwrm_wol_filter_qcfg_input req
= {0};
6569 struct hwrm_wol_filter_qcfg_output
*resp
= bp
->hwrm_cmd_resp_addr
;
6570 u16 next_handle
= 0;
6573 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_WOL_FILTER_QCFG
, -1, -1);
6574 req
.port_id
= cpu_to_le16(bp
->pf
.port_id
);
6575 req
.handle
= cpu_to_le16(handle
);
6576 mutex_lock(&bp
->hwrm_cmd_lock
);
6577 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
6579 next_handle
= le16_to_cpu(resp
->next_handle
);
6580 if (next_handle
!= 0) {
6581 if (resp
->wol_type
==
6582 WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT
) {
6584 bp
->wol_filter_id
= resp
->wol_filter_id
;
6588 mutex_unlock(&bp
->hwrm_cmd_lock
);
6592 static void bnxt_get_wol_settings(struct bnxt
*bp
)
6596 if (!BNXT_PF(bp
) || !(bp
->flags
& BNXT_FLAG_WOL_CAP
))
6600 handle
= bnxt_hwrm_get_wol_fltrs(bp
, handle
);
6601 } while (handle
&& handle
!= 0xffff);
6604 static bool bnxt_eee_config_ok(struct bnxt
*bp
)
6606 struct ethtool_eee
*eee
= &bp
->eee
;
6607 struct bnxt_link_info
*link_info
= &bp
->link_info
;
6609 if (!(bp
->flags
& BNXT_FLAG_EEE_CAP
))
6612 if (eee
->eee_enabled
) {
6614 _bnxt_fw_to_ethtool_adv_spds(link_info
->advertising
, 0);
6616 if (!(link_info
->autoneg
& BNXT_AUTONEG_SPEED
)) {
6617 eee
->eee_enabled
= 0;
6620 if (eee
->advertised
& ~advertising
) {
6621 eee
->advertised
= advertising
& eee
->supported
;
6628 static int bnxt_update_phy_setting(struct bnxt
*bp
)
6631 bool update_link
= false;
6632 bool update_pause
= false;
6633 bool update_eee
= false;
6634 struct bnxt_link_info
*link_info
= &bp
->link_info
;
6636 rc
= bnxt_update_link(bp
, true);
6638 netdev_err(bp
->dev
, "failed to update link (rc: %x)\n",
6642 if (!BNXT_SINGLE_PF(bp
))
6645 if ((link_info
->autoneg
& BNXT_AUTONEG_FLOW_CTRL
) &&
6646 (link_info
->auto_pause_setting
& BNXT_LINK_PAUSE_BOTH
) !=
6647 link_info
->req_flow_ctrl
)
6648 update_pause
= true;
6649 if (!(link_info
->autoneg
& BNXT_AUTONEG_FLOW_CTRL
) &&
6650 link_info
->force_pause_setting
!= link_info
->req_flow_ctrl
)
6651 update_pause
= true;
6652 if (!(link_info
->autoneg
& BNXT_AUTONEG_SPEED
)) {
6653 if (BNXT_AUTO_MODE(link_info
->auto_mode
))
6655 if (link_info
->req_link_speed
!= link_info
->force_link_speed
)
6657 if (link_info
->req_duplex
!= link_info
->duplex_setting
)
6660 if (link_info
->auto_mode
== BNXT_LINK_AUTO_NONE
)
6662 if (link_info
->advertising
!= link_info
->auto_link_speeds
)
6666 /* The last close may have shutdown the link, so need to call
6667 * PHY_CFG to bring it back up.
6669 if (!netif_carrier_ok(bp
->dev
))
6672 if (!bnxt_eee_config_ok(bp
))
6676 rc
= bnxt_hwrm_set_link_setting(bp
, update_pause
, update_eee
);
6677 else if (update_pause
)
6678 rc
= bnxt_hwrm_set_pause(bp
);
6680 netdev_err(bp
->dev
, "failed to update phy setting (rc: %x)\n",
6688 /* Common routine to pre-map certain register block to different GRC window.
6689 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
6690 * in PF and 3 windows in VF that can be customized to map in different
6693 static void bnxt_preset_reg_win(struct bnxt
*bp
)
6696 /* CAG registers map to GRC window #4 */
6697 writel(BNXT_CAG_REG_BASE
,
6698 bp
->bar0
+ BNXT_GRCPF_REG_WINDOW_BASE_OUT
+ 12);
6702 static int __bnxt_open_nic(struct bnxt
*bp
, bool irq_re_init
, bool link_re_init
)
6706 bnxt_preset_reg_win(bp
);
6707 netif_carrier_off(bp
->dev
);
6709 rc
= bnxt_reserve_rings(bp
);
6713 rc
= bnxt_setup_int_mode(bp
);
6715 netdev_err(bp
->dev
, "bnxt_setup_int_mode err: %x\n",
6720 if ((bp
->flags
& BNXT_FLAG_RFS
) &&
6721 !(bp
->flags
& BNXT_FLAG_USING_MSIX
)) {
6722 /* disable RFS if falling back to INTA */
6723 bp
->dev
->hw_features
&= ~NETIF_F_NTUPLE
;
6724 bp
->flags
&= ~BNXT_FLAG_RFS
;
6727 rc
= bnxt_alloc_mem(bp
, irq_re_init
);
6729 netdev_err(bp
->dev
, "bnxt_alloc_mem err: %x\n", rc
);
6730 goto open_err_free_mem
;
6735 rc
= bnxt_request_irq(bp
);
6737 netdev_err(bp
->dev
, "bnxt_request_irq err: %x\n", rc
);
6742 bnxt_enable_napi(bp
);
6744 rc
= bnxt_init_nic(bp
, irq_re_init
);
6746 netdev_err(bp
->dev
, "bnxt_init_nic err: %x\n", rc
);
6751 mutex_lock(&bp
->link_lock
);
6752 rc
= bnxt_update_phy_setting(bp
);
6753 mutex_unlock(&bp
->link_lock
);
6755 netdev_warn(bp
->dev
, "failed to update phy settings\n");
6759 udp_tunnel_get_rx_info(bp
->dev
);
6761 set_bit(BNXT_STATE_OPEN
, &bp
->state
);
6762 bnxt_enable_int(bp
);
6763 /* Enable TX queues */
6765 mod_timer(&bp
->timer
, jiffies
+ bp
->current_interval
);
6766 /* Poll link status and check for SFP+ module status */
6767 bnxt_get_port_module_status(bp
);
6769 /* VF-reps may need to be re-opened after the PF is re-opened */
6771 bnxt_vf_reps_open(bp
);
6775 bnxt_disable_napi(bp
);
6781 bnxt_free_mem(bp
, true);
6785 /* rtnl_lock held */
6786 int bnxt_open_nic(struct bnxt
*bp
, bool irq_re_init
, bool link_re_init
)
6790 rc
= __bnxt_open_nic(bp
, irq_re_init
, link_re_init
);
6792 netdev_err(bp
->dev
, "nic open fail (rc: %x)\n", rc
);
6798 /* rtnl_lock held, open the NIC half way by allocating all resources, but
6799 * NAPI, IRQ, and TX are not enabled. This is mainly used for offline
6802 int bnxt_half_open_nic(struct bnxt
*bp
)
6806 rc
= bnxt_alloc_mem(bp
, false);
6808 netdev_err(bp
->dev
, "bnxt_alloc_mem err: %x\n", rc
);
6811 rc
= bnxt_init_nic(bp
, false);
6813 netdev_err(bp
->dev
, "bnxt_init_nic err: %x\n", rc
);
6820 bnxt_free_mem(bp
, false);
6825 /* rtnl_lock held, this call can only be made after a previous successful
6826 * call to bnxt_half_open_nic().
6828 void bnxt_half_close_nic(struct bnxt
*bp
)
6830 bnxt_hwrm_resource_free(bp
, false, false);
6832 bnxt_free_mem(bp
, false);
6835 static int bnxt_open(struct net_device
*dev
)
6837 struct bnxt
*bp
= netdev_priv(dev
);
6839 return __bnxt_open_nic(bp
, true, true);
6842 static bool bnxt_drv_busy(struct bnxt
*bp
)
6844 return (test_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
) ||
6845 test_bit(BNXT_STATE_READ_STATS
, &bp
->state
));
6848 static void __bnxt_close_nic(struct bnxt
*bp
, bool irq_re_init
,
6851 /* Close the VF-reps before closing PF */
6853 bnxt_vf_reps_close(bp
);
6855 /* Change device state to avoid TX queue wake up's */
6856 bnxt_tx_disable(bp
);
6858 clear_bit(BNXT_STATE_OPEN
, &bp
->state
);
6859 smp_mb__after_atomic();
6860 while (bnxt_drv_busy(bp
))
6863 /* Flush rings and and disable interrupts */
6864 bnxt_shutdown_nic(bp
, irq_re_init
);
6866 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
6868 bnxt_disable_napi(bp
);
6869 del_timer_sync(&bp
->timer
);
6876 bnxt_free_mem(bp
, irq_re_init
);
6879 int bnxt_close_nic(struct bnxt
*bp
, bool irq_re_init
, bool link_re_init
)
6883 #ifdef CONFIG_BNXT_SRIOV
6884 if (bp
->sriov_cfg
) {
6885 rc
= wait_event_interruptible_timeout(bp
->sriov_cfg_wait
,
6887 BNXT_SRIOV_CFG_WAIT_TMO
);
6889 netdev_warn(bp
->dev
, "timeout waiting for SRIOV config operation to complete!\n");
6892 __bnxt_close_nic(bp
, irq_re_init
, link_re_init
);
6896 static int bnxt_close(struct net_device
*dev
)
6898 struct bnxt
*bp
= netdev_priv(dev
);
6900 bnxt_close_nic(bp
, true, true);
6901 bnxt_hwrm_shutdown_link(bp
);
6905 /* rtnl_lock held */
6906 static int bnxt_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
6912 if (!netif_running(dev
))
6919 if (!netif_running(dev
))
6932 bnxt_get_stats64(struct net_device
*dev
, struct rtnl_link_stats64
*stats
)
6935 struct bnxt
*bp
= netdev_priv(dev
);
6937 set_bit(BNXT_STATE_READ_STATS
, &bp
->state
);
6938 /* Make sure bnxt_close_nic() sees that we are reading stats before
6939 * we check the BNXT_STATE_OPEN flag.
6941 smp_mb__after_atomic();
6942 if (!test_bit(BNXT_STATE_OPEN
, &bp
->state
)) {
6943 clear_bit(BNXT_STATE_READ_STATS
, &bp
->state
);
6947 /* TODO check if we need to synchronize with bnxt_close path */
6948 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
6949 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
6950 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
6951 struct ctx_hw_stats
*hw_stats
= cpr
->hw_stats
;
6953 stats
->rx_packets
+= le64_to_cpu(hw_stats
->rx_ucast_pkts
);
6954 stats
->rx_packets
+= le64_to_cpu(hw_stats
->rx_mcast_pkts
);
6955 stats
->rx_packets
+= le64_to_cpu(hw_stats
->rx_bcast_pkts
);
6957 stats
->tx_packets
+= le64_to_cpu(hw_stats
->tx_ucast_pkts
);
6958 stats
->tx_packets
+= le64_to_cpu(hw_stats
->tx_mcast_pkts
);
6959 stats
->tx_packets
+= le64_to_cpu(hw_stats
->tx_bcast_pkts
);
6961 stats
->rx_bytes
+= le64_to_cpu(hw_stats
->rx_ucast_bytes
);
6962 stats
->rx_bytes
+= le64_to_cpu(hw_stats
->rx_mcast_bytes
);
6963 stats
->rx_bytes
+= le64_to_cpu(hw_stats
->rx_bcast_bytes
);
6965 stats
->tx_bytes
+= le64_to_cpu(hw_stats
->tx_ucast_bytes
);
6966 stats
->tx_bytes
+= le64_to_cpu(hw_stats
->tx_mcast_bytes
);
6967 stats
->tx_bytes
+= le64_to_cpu(hw_stats
->tx_bcast_bytes
);
6969 stats
->rx_missed_errors
+=
6970 le64_to_cpu(hw_stats
->rx_discard_pkts
);
6972 stats
->multicast
+= le64_to_cpu(hw_stats
->rx_mcast_pkts
);
6974 stats
->tx_dropped
+= le64_to_cpu(hw_stats
->tx_drop_pkts
);
6977 if (bp
->flags
& BNXT_FLAG_PORT_STATS
) {
6978 struct rx_port_stats
*rx
= bp
->hw_rx_port_stats
;
6979 struct tx_port_stats
*tx
= bp
->hw_tx_port_stats
;
6981 stats
->rx_crc_errors
= le64_to_cpu(rx
->rx_fcs_err_frames
);
6982 stats
->rx_frame_errors
= le64_to_cpu(rx
->rx_align_err_frames
);
6983 stats
->rx_length_errors
= le64_to_cpu(rx
->rx_undrsz_frames
) +
6984 le64_to_cpu(rx
->rx_ovrsz_frames
) +
6985 le64_to_cpu(rx
->rx_runt_frames
);
6986 stats
->rx_errors
= le64_to_cpu(rx
->rx_false_carrier_frames
) +
6987 le64_to_cpu(rx
->rx_jbr_frames
);
6988 stats
->collisions
= le64_to_cpu(tx
->tx_total_collisions
);
6989 stats
->tx_fifo_errors
= le64_to_cpu(tx
->tx_fifo_underruns
);
6990 stats
->tx_errors
= le64_to_cpu(tx
->tx_err
);
6992 clear_bit(BNXT_STATE_READ_STATS
, &bp
->state
);
6995 static bool bnxt_mc_list_updated(struct bnxt
*bp
, u32
*rx_mask
)
6997 struct net_device
*dev
= bp
->dev
;
6998 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
6999 struct netdev_hw_addr
*ha
;
7002 bool update
= false;
7005 netdev_for_each_mc_addr(ha
, dev
) {
7006 if (mc_count
>= BNXT_MAX_MC_ADDRS
) {
7007 *rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
;
7008 vnic
->mc_list_count
= 0;
7012 if (!ether_addr_equal(haddr
, vnic
->mc_list
+ off
)) {
7013 memcpy(vnic
->mc_list
+ off
, haddr
, ETH_ALEN
);
7020 *rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST
;
7022 if (mc_count
!= vnic
->mc_list_count
) {
7023 vnic
->mc_list_count
= mc_count
;
7029 static bool bnxt_uc_list_updated(struct bnxt
*bp
)
7031 struct net_device
*dev
= bp
->dev
;
7032 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
7033 struct netdev_hw_addr
*ha
;
7036 if (netdev_uc_count(dev
) != (vnic
->uc_filter_count
- 1))
7039 netdev_for_each_uc_addr(ha
, dev
) {
7040 if (!ether_addr_equal(ha
->addr
, vnic
->uc_list
+ off
))
7048 static void bnxt_set_rx_mode(struct net_device
*dev
)
7050 struct bnxt
*bp
= netdev_priv(dev
);
7051 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
7052 u32 mask
= vnic
->rx_mask
;
7053 bool mc_update
= false;
7056 if (!netif_running(dev
))
7059 mask
&= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
|
7060 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST
|
7061 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
);
7063 if ((dev
->flags
& IFF_PROMISC
) && bnxt_promisc_ok(bp
))
7064 mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
;
7066 uc_update
= bnxt_uc_list_updated(bp
);
7068 if (dev
->flags
& IFF_ALLMULTI
) {
7069 mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
;
7070 vnic
->mc_list_count
= 0;
7072 mc_update
= bnxt_mc_list_updated(bp
, &mask
);
7075 if (mask
!= vnic
->rx_mask
|| uc_update
|| mc_update
) {
7076 vnic
->rx_mask
= mask
;
7078 set_bit(BNXT_RX_MASK_SP_EVENT
, &bp
->sp_event
);
7079 bnxt_queue_sp_work(bp
);
7083 static int bnxt_cfg_rx_mode(struct bnxt
*bp
)
7085 struct net_device
*dev
= bp
->dev
;
7086 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
7087 struct netdev_hw_addr
*ha
;
7091 netif_addr_lock_bh(dev
);
7092 uc_update
= bnxt_uc_list_updated(bp
);
7093 netif_addr_unlock_bh(dev
);
7098 mutex_lock(&bp
->hwrm_cmd_lock
);
7099 for (i
= 1; i
< vnic
->uc_filter_count
; i
++) {
7100 struct hwrm_cfa_l2_filter_free_input req
= {0};
7102 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_L2_FILTER_FREE
, -1,
7105 req
.l2_filter_id
= vnic
->fw_l2_filter_id
[i
];
7107 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
7110 mutex_unlock(&bp
->hwrm_cmd_lock
);
7112 vnic
->uc_filter_count
= 1;
7114 netif_addr_lock_bh(dev
);
7115 if (netdev_uc_count(dev
) > (BNXT_MAX_UC_ADDRS
- 1)) {
7116 vnic
->rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
;
7118 netdev_for_each_uc_addr(ha
, dev
) {
7119 memcpy(vnic
->uc_list
+ off
, ha
->addr
, ETH_ALEN
);
7121 vnic
->uc_filter_count
++;
7124 netif_addr_unlock_bh(dev
);
7126 for (i
= 1, off
= 0; i
< vnic
->uc_filter_count
; i
++, off
+= ETH_ALEN
) {
7127 rc
= bnxt_hwrm_set_vnic_filter(bp
, 0, i
, vnic
->uc_list
+ off
);
7129 netdev_err(bp
->dev
, "HWRM vnic filter failure rc: %x\n",
7131 vnic
->uc_filter_count
= i
;
7137 rc
= bnxt_hwrm_cfa_l2_set_rx_mask(bp
, 0);
7139 netdev_err(bp
->dev
, "HWRM cfa l2 rx mask failure rc: %x\n",
7145 /* If the chip and firmware supports RFS */
7146 static bool bnxt_rfs_supported(struct bnxt
*bp
)
7148 if (BNXT_PF(bp
) && !BNXT_CHIP_TYPE_NITRO_A0(bp
))
7150 if (bp
->flags
& BNXT_FLAG_NEW_RSS_CAP
)
7155 /* If runtime conditions support RFS */
7156 static bool bnxt_rfs_capable(struct bnxt
*bp
)
7158 #ifdef CONFIG_RFS_ACCEL
7159 int vnics
, max_vnics
, max_rss_ctxs
;
7161 if (!(bp
->flags
& BNXT_FLAG_MSIX_CAP
))
7164 vnics
= 1 + bp
->rx_nr_rings
;
7165 max_vnics
= bnxt_get_max_func_vnics(bp
);
7166 max_rss_ctxs
= bnxt_get_max_func_rss_ctxs(bp
);
7168 /* RSS contexts not a limiting factor */
7169 if (bp
->flags
& BNXT_FLAG_NEW_RSS_CAP
)
7170 max_rss_ctxs
= max_vnics
;
7171 if (vnics
> max_vnics
|| vnics
> max_rss_ctxs
) {
7172 if (bp
->rx_nr_rings
> 1)
7173 netdev_warn(bp
->dev
,
7174 "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
7175 min(max_rss_ctxs
- 1, max_vnics
- 1));
7179 if (!(bp
->flags
& BNXT_FLAG_NEW_RM
))
7182 if (vnics
== bp
->hw_resc
.resv_vnics
)
7185 bnxt_hwrm_reserve_rings(bp
, 0, 0, 0, 0, vnics
);
7186 if (vnics
<= bp
->hw_resc
.resv_vnics
)
7189 netdev_warn(bp
->dev
, "Unable to reserve resources to support NTUPLE filters.\n");
7190 bnxt_hwrm_reserve_rings(bp
, 0, 0, 0, 0, 1);
7197 static netdev_features_t
bnxt_fix_features(struct net_device
*dev
,
7198 netdev_features_t features
)
7200 struct bnxt
*bp
= netdev_priv(dev
);
7202 if ((features
& NETIF_F_NTUPLE
) && !bnxt_rfs_capable(bp
))
7203 features
&= ~NETIF_F_NTUPLE
;
7205 if (bp
->flags
& BNXT_FLAG_NO_AGG_RINGS
)
7206 features
&= ~(NETIF_F_LRO
| NETIF_F_GRO_HW
);
7208 if (!(features
& NETIF_F_GRO
))
7209 features
&= ~NETIF_F_GRO_HW
;
7211 if (features
& NETIF_F_GRO_HW
)
7212 features
&= ~NETIF_F_LRO
;
7214 /* Both CTAG and STAG VLAN accelaration on the RX side have to be
7215 * turned on or off together.
7217 if ((features
& (NETIF_F_HW_VLAN_CTAG_RX
| NETIF_F_HW_VLAN_STAG_RX
)) !=
7218 (NETIF_F_HW_VLAN_CTAG_RX
| NETIF_F_HW_VLAN_STAG_RX
)) {
7219 if (dev
->features
& NETIF_F_HW_VLAN_CTAG_RX
)
7220 features
&= ~(NETIF_F_HW_VLAN_CTAG_RX
|
7221 NETIF_F_HW_VLAN_STAG_RX
);
7223 features
|= NETIF_F_HW_VLAN_CTAG_RX
|
7224 NETIF_F_HW_VLAN_STAG_RX
;
7226 #ifdef CONFIG_BNXT_SRIOV
7229 features
&= ~(NETIF_F_HW_VLAN_CTAG_RX
|
7230 NETIF_F_HW_VLAN_STAG_RX
);
7237 static int bnxt_set_features(struct net_device
*dev
, netdev_features_t features
)
7239 struct bnxt
*bp
= netdev_priv(dev
);
7240 u32 flags
= bp
->flags
;
7243 bool re_init
= false;
7244 bool update_tpa
= false;
7246 flags
&= ~BNXT_FLAG_ALL_CONFIG_FEATS
;
7247 if (features
& NETIF_F_GRO_HW
)
7248 flags
|= BNXT_FLAG_GRO
;
7249 else if (features
& NETIF_F_LRO
)
7250 flags
|= BNXT_FLAG_LRO
;
7252 if (bp
->flags
& BNXT_FLAG_NO_AGG_RINGS
)
7253 flags
&= ~BNXT_FLAG_TPA
;
7255 if (features
& NETIF_F_HW_VLAN_CTAG_RX
)
7256 flags
|= BNXT_FLAG_STRIP_VLAN
;
7258 if (features
& NETIF_F_NTUPLE
)
7259 flags
|= BNXT_FLAG_RFS
;
7261 changes
= flags
^ bp
->flags
;
7262 if (changes
& BNXT_FLAG_TPA
) {
7264 if ((bp
->flags
& BNXT_FLAG_TPA
) == 0 ||
7265 (flags
& BNXT_FLAG_TPA
) == 0)
7269 if (changes
& ~BNXT_FLAG_TPA
)
7272 if (flags
!= bp
->flags
) {
7273 u32 old_flags
= bp
->flags
;
7277 if (!test_bit(BNXT_STATE_OPEN
, &bp
->state
)) {
7279 bnxt_set_ring_params(bp
);
7284 bnxt_close_nic(bp
, false, false);
7286 bnxt_set_ring_params(bp
);
7288 return bnxt_open_nic(bp
, false, false);
7291 rc
= bnxt_set_tpa(bp
,
7292 (flags
& BNXT_FLAG_TPA
) ?
7295 bp
->flags
= old_flags
;
7301 static void bnxt_dump_tx_sw_state(struct bnxt_napi
*bnapi
)
7303 struct bnxt_tx_ring_info
*txr
= bnapi
->tx_ring
;
7304 int i
= bnapi
->index
;
7309 netdev_info(bnapi
->bp
->dev
, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
7310 i
, txr
->tx_ring_struct
.fw_ring_id
, txr
->tx_prod
,
7314 static void bnxt_dump_rx_sw_state(struct bnxt_napi
*bnapi
)
7316 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
7317 int i
= bnapi
->index
;
7322 netdev_info(bnapi
->bp
->dev
, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
7323 i
, rxr
->rx_ring_struct
.fw_ring_id
, rxr
->rx_prod
,
7324 rxr
->rx_agg_ring_struct
.fw_ring_id
, rxr
->rx_agg_prod
,
7325 rxr
->rx_sw_agg_prod
);
7328 static void bnxt_dump_cp_sw_state(struct bnxt_napi
*bnapi
)
7330 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
7331 int i
= bnapi
->index
;
7333 netdev_info(bnapi
->bp
->dev
, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
7334 i
, cpr
->cp_ring_struct
.fw_ring_id
, cpr
->cp_raw_cons
);
7337 static void bnxt_dbg_dump_states(struct bnxt
*bp
)
7340 struct bnxt_napi
*bnapi
;
7342 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
7343 bnapi
= bp
->bnapi
[i
];
7344 if (netif_msg_drv(bp
)) {
7345 bnxt_dump_tx_sw_state(bnapi
);
7346 bnxt_dump_rx_sw_state(bnapi
);
7347 bnxt_dump_cp_sw_state(bnapi
);
7352 static void bnxt_reset_task(struct bnxt
*bp
, bool silent
)
7355 bnxt_dbg_dump_states(bp
);
7356 if (netif_running(bp
->dev
)) {
7361 bnxt_close_nic(bp
, false, false);
7362 rc
= bnxt_open_nic(bp
, false, false);
7368 static void bnxt_tx_timeout(struct net_device
*dev
)
7370 struct bnxt
*bp
= netdev_priv(dev
);
7372 netdev_err(bp
->dev
, "TX timeout detected, starting reset task!\n");
7373 set_bit(BNXT_RESET_TASK_SP_EVENT
, &bp
->sp_event
);
7374 bnxt_queue_sp_work(bp
);
7377 #ifdef CONFIG_NET_POLL_CONTROLLER
7378 static void bnxt_poll_controller(struct net_device
*dev
)
7380 struct bnxt
*bp
= netdev_priv(dev
);
7383 /* Only process tx rings/combined rings in netpoll mode. */
7384 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
7385 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
7387 napi_schedule(&txr
->bnapi
->napi
);
7392 static void bnxt_timer(struct timer_list
*t
)
7394 struct bnxt
*bp
= from_timer(bp
, t
, timer
);
7395 struct net_device
*dev
= bp
->dev
;
7397 if (!netif_running(dev
))
7400 if (atomic_read(&bp
->intr_sem
) != 0)
7401 goto bnxt_restart_timer
;
7403 if (bp
->link_info
.link_up
&& (bp
->flags
& BNXT_FLAG_PORT_STATS
) &&
7404 bp
->stats_coal_ticks
) {
7405 set_bit(BNXT_PERIODIC_STATS_SP_EVENT
, &bp
->sp_event
);
7406 bnxt_queue_sp_work(bp
);
7409 if (bnxt_tc_flower_enabled(bp
)) {
7410 set_bit(BNXT_FLOW_STATS_SP_EVENT
, &bp
->sp_event
);
7411 bnxt_queue_sp_work(bp
);
7414 mod_timer(&bp
->timer
, jiffies
+ bp
->current_interval
);
7417 static void bnxt_rtnl_lock_sp(struct bnxt
*bp
)
7419 /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK
7420 * set. If the device is being closed, bnxt_close() may be holding
7421 * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we
7422 * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
7424 clear_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
7428 static void bnxt_rtnl_unlock_sp(struct bnxt
*bp
)
7430 set_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
7434 /* Only called from bnxt_sp_task() */
7435 static void bnxt_reset(struct bnxt
*bp
, bool silent
)
7437 bnxt_rtnl_lock_sp(bp
);
7438 if (test_bit(BNXT_STATE_OPEN
, &bp
->state
))
7439 bnxt_reset_task(bp
, silent
);
7440 bnxt_rtnl_unlock_sp(bp
);
7443 static void bnxt_cfg_ntp_filters(struct bnxt
*);
7445 static void bnxt_sp_task(struct work_struct
*work
)
7447 struct bnxt
*bp
= container_of(work
, struct bnxt
, sp_task
);
7449 set_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
7450 smp_mb__after_atomic();
7451 if (!test_bit(BNXT_STATE_OPEN
, &bp
->state
)) {
7452 clear_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
7456 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT
, &bp
->sp_event
))
7457 bnxt_cfg_rx_mode(bp
);
7459 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT
, &bp
->sp_event
))
7460 bnxt_cfg_ntp_filters(bp
);
7461 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT
, &bp
->sp_event
))
7462 bnxt_hwrm_exec_fwd_req(bp
);
7463 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT
, &bp
->sp_event
)) {
7464 bnxt_hwrm_tunnel_dst_port_alloc(
7466 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
);
7468 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT
, &bp
->sp_event
)) {
7469 bnxt_hwrm_tunnel_dst_port_free(
7470 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
);
7472 if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT
, &bp
->sp_event
)) {
7473 bnxt_hwrm_tunnel_dst_port_alloc(
7475 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
);
7477 if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT
, &bp
->sp_event
)) {
7478 bnxt_hwrm_tunnel_dst_port_free(
7479 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
);
7481 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT
, &bp
->sp_event
))
7482 bnxt_hwrm_port_qstats(bp
);
7484 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT
, &bp
->sp_event
)) {
7487 mutex_lock(&bp
->link_lock
);
7488 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT
,
7490 bnxt_hwrm_phy_qcaps(bp
);
7492 rc
= bnxt_update_link(bp
, true);
7493 mutex_unlock(&bp
->link_lock
);
7495 netdev_err(bp
->dev
, "SP task can't update link (rc: %x)\n",
7498 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT
, &bp
->sp_event
)) {
7499 mutex_lock(&bp
->link_lock
);
7500 bnxt_get_port_module_status(bp
);
7501 mutex_unlock(&bp
->link_lock
);
7504 if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT
, &bp
->sp_event
))
7505 bnxt_tc_flow_stats_work(bp
);
7507 /* These functions below will clear BNXT_STATE_IN_SP_TASK. They
7508 * must be the last functions to be called before exiting.
7510 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT
, &bp
->sp_event
))
7511 bnxt_reset(bp
, false);
7513 if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT
, &bp
->sp_event
))
7514 bnxt_reset(bp
, true);
7516 smp_mb__before_atomic();
7517 clear_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
7520 /* Under rtnl_lock */
7521 int bnxt_check_rings(struct bnxt
*bp
, int tx
, int rx
, bool sh
, int tcs
,
7524 int max_rx
, max_tx
, tx_sets
= 1;
7525 int tx_rings_needed
;
7532 rc
= bnxt_get_max_rings(bp
, &max_rx
, &max_tx
, sh
);
7539 tx_rings_needed
= tx
* tx_sets
+ tx_xdp
;
7540 if (max_tx
< tx_rings_needed
)
7544 if (bp
->flags
& BNXT_FLAG_RFS
)
7547 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
)
7549 cp
= sh
? max_t(int, tx_rings_needed
, rx
) : tx_rings_needed
+ rx
;
7550 return bnxt_hwrm_check_rings(bp
, tx_rings_needed
, rx_rings
, rx
, cp
,
7554 static void bnxt_unmap_bars(struct bnxt
*bp
, struct pci_dev
*pdev
)
7557 pci_iounmap(pdev
, bp
->bar2
);
7562 pci_iounmap(pdev
, bp
->bar1
);
7567 pci_iounmap(pdev
, bp
->bar0
);
7572 static void bnxt_cleanup_pci(struct bnxt
*bp
)
7574 bnxt_unmap_bars(bp
, bp
->pdev
);
7575 pci_release_regions(bp
->pdev
);
7576 pci_disable_device(bp
->pdev
);
7579 static void bnxt_init_dflt_coal(struct bnxt
*bp
)
7581 struct bnxt_coal
*coal
;
7583 /* Tick values in micro seconds.
7584 * 1 coal_buf x bufs_per_record = 1 completion record.
7586 coal
= &bp
->rx_coal
;
7587 coal
->coal_ticks
= 14;
7588 coal
->coal_bufs
= 30;
7589 coal
->coal_ticks_irq
= 1;
7590 coal
->coal_bufs_irq
= 2;
7591 coal
->idle_thresh
= 25;
7592 coal
->bufs_per_record
= 2;
7593 coal
->budget
= 64; /* NAPI budget */
7595 coal
= &bp
->tx_coal
;
7596 coal
->coal_ticks
= 28;
7597 coal
->coal_bufs
= 30;
7598 coal
->coal_ticks_irq
= 2;
7599 coal
->coal_bufs_irq
= 2;
7600 coal
->bufs_per_record
= 1;
7602 bp
->stats_coal_ticks
= BNXT_DEF_STATS_COAL_TICKS
;
7605 static int bnxt_init_board(struct pci_dev
*pdev
, struct net_device
*dev
)
7608 struct bnxt
*bp
= netdev_priv(dev
);
7610 SET_NETDEV_DEV(dev
, &pdev
->dev
);
7612 /* enable device (incl. PCI PM wakeup), and bus-mastering */
7613 rc
= pci_enable_device(pdev
);
7615 dev_err(&pdev
->dev
, "Cannot enable PCI device, aborting\n");
7619 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
7621 "Cannot find PCI device base address, aborting\n");
7623 goto init_err_disable
;
7626 rc
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
7628 dev_err(&pdev
->dev
, "Cannot obtain PCI resources, aborting\n");
7629 goto init_err_disable
;
7632 if (dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(64)) != 0 &&
7633 dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(32)) != 0) {
7634 dev_err(&pdev
->dev
, "System does not support DMA, aborting\n");
7635 goto init_err_disable
;
7638 pci_set_master(pdev
);
7643 bp
->bar0
= pci_ioremap_bar(pdev
, 0);
7645 dev_err(&pdev
->dev
, "Cannot map device registers, aborting\n");
7647 goto init_err_release
;
7650 bp
->bar1
= pci_ioremap_bar(pdev
, 2);
7652 dev_err(&pdev
->dev
, "Cannot map doorbell registers, aborting\n");
7654 goto init_err_release
;
7657 bp
->bar2
= pci_ioremap_bar(pdev
, 4);
7659 dev_err(&pdev
->dev
, "Cannot map bar4 registers, aborting\n");
7661 goto init_err_release
;
7664 pci_enable_pcie_error_reporting(pdev
);
7666 INIT_WORK(&bp
->sp_task
, bnxt_sp_task
);
7668 spin_lock_init(&bp
->ntp_fltr_lock
);
7670 bp
->rx_ring_size
= BNXT_DEFAULT_RX_RING_SIZE
;
7671 bp
->tx_ring_size
= BNXT_DEFAULT_TX_RING_SIZE
;
7673 bnxt_init_dflt_coal(bp
);
7675 timer_setup(&bp
->timer
, bnxt_timer
, 0);
7676 bp
->current_interval
= BNXT_TIMER_INTERVAL
;
7678 clear_bit(BNXT_STATE_OPEN
, &bp
->state
);
7682 bnxt_unmap_bars(bp
, pdev
);
7683 pci_release_regions(pdev
);
7686 pci_disable_device(pdev
);
7692 /* rtnl_lock held */
7693 static int bnxt_change_mac_addr(struct net_device
*dev
, void *p
)
7695 struct sockaddr
*addr
= p
;
7696 struct bnxt
*bp
= netdev_priv(dev
);
7699 if (!is_valid_ether_addr(addr
->sa_data
))
7700 return -EADDRNOTAVAIL
;
7702 if (ether_addr_equal(addr
->sa_data
, dev
->dev_addr
))
7705 rc
= bnxt_approve_mac(bp
, addr
->sa_data
);
7709 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
7710 if (netif_running(dev
)) {
7711 bnxt_close_nic(bp
, false, false);
7712 rc
= bnxt_open_nic(bp
, false, false);
7718 /* rtnl_lock held */
7719 static int bnxt_change_mtu(struct net_device
*dev
, int new_mtu
)
7721 struct bnxt
*bp
= netdev_priv(dev
);
7723 if (netif_running(dev
))
7724 bnxt_close_nic(bp
, false, false);
7727 bnxt_set_ring_params(bp
);
7729 if (netif_running(dev
))
7730 return bnxt_open_nic(bp
, false, false);
7735 int bnxt_setup_mq_tc(struct net_device
*dev
, u8 tc
)
7737 struct bnxt
*bp
= netdev_priv(dev
);
7741 if (tc
> bp
->max_tc
) {
7742 netdev_err(dev
, "Too many traffic classes requested: %d. Max supported is %d.\n",
7747 if (netdev_get_num_tc(dev
) == tc
)
7750 if (bp
->flags
& BNXT_FLAG_SHARED_RINGS
)
7753 rc
= bnxt_check_rings(bp
, bp
->tx_nr_rings_per_tc
, bp
->rx_nr_rings
,
7754 sh
, tc
, bp
->tx_nr_rings_xdp
);
7758 /* Needs to close the device and do hw resource re-allocations */
7759 if (netif_running(bp
->dev
))
7760 bnxt_close_nic(bp
, true, false);
7763 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
* tc
;
7764 netdev_set_num_tc(dev
, tc
);
7766 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
;
7767 netdev_reset_tc(dev
);
7769 bp
->tx_nr_rings
+= bp
->tx_nr_rings_xdp
;
7770 bp
->cp_nr_rings
= sh
? max_t(int, bp
->tx_nr_rings
, bp
->rx_nr_rings
) :
7771 bp
->tx_nr_rings
+ bp
->rx_nr_rings
;
7772 bp
->num_stat_ctxs
= bp
->cp_nr_rings
;
7774 if (netif_running(bp
->dev
))
7775 return bnxt_open_nic(bp
, true, false);
7780 static int bnxt_setup_tc_block_cb(enum tc_setup_type type
, void *type_data
,
7783 struct bnxt
*bp
= cb_priv
;
7785 if (!bnxt_tc_flower_enabled(bp
) ||
7786 !tc_cls_can_offload_and_chain0(bp
->dev
, type_data
))
7790 case TC_SETUP_CLSFLOWER
:
7791 return bnxt_tc_setup_flower(bp
, bp
->pf
.fw_fid
, type_data
);
7797 static int bnxt_setup_tc_block(struct net_device
*dev
,
7798 struct tc_block_offload
*f
)
7800 struct bnxt
*bp
= netdev_priv(dev
);
7802 if (f
->binder_type
!= TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS
)
7805 switch (f
->command
) {
7807 return tcf_block_cb_register(f
->block
, bnxt_setup_tc_block_cb
,
7809 case TC_BLOCK_UNBIND
:
7810 tcf_block_cb_unregister(f
->block
, bnxt_setup_tc_block_cb
, bp
);
7817 static int bnxt_setup_tc(struct net_device
*dev
, enum tc_setup_type type
,
7821 case TC_SETUP_BLOCK
:
7822 return bnxt_setup_tc_block(dev
, type_data
);
7823 case TC_SETUP_QDISC_MQPRIO
: {
7824 struct tc_mqprio_qopt
*mqprio
= type_data
;
7826 mqprio
->hw
= TC_MQPRIO_HW_OFFLOAD_TCS
;
7828 return bnxt_setup_mq_tc(dev
, mqprio
->num_tc
);
7835 #ifdef CONFIG_RFS_ACCEL
7836 static bool bnxt_fltr_match(struct bnxt_ntuple_filter
*f1
,
7837 struct bnxt_ntuple_filter
*f2
)
7839 struct flow_keys
*keys1
= &f1
->fkeys
;
7840 struct flow_keys
*keys2
= &f2
->fkeys
;
7842 if (keys1
->addrs
.v4addrs
.src
== keys2
->addrs
.v4addrs
.src
&&
7843 keys1
->addrs
.v4addrs
.dst
== keys2
->addrs
.v4addrs
.dst
&&
7844 keys1
->ports
.ports
== keys2
->ports
.ports
&&
7845 keys1
->basic
.ip_proto
== keys2
->basic
.ip_proto
&&
7846 keys1
->basic
.n_proto
== keys2
->basic
.n_proto
&&
7847 keys1
->control
.flags
== keys2
->control
.flags
&&
7848 ether_addr_equal(f1
->src_mac_addr
, f2
->src_mac_addr
) &&
7849 ether_addr_equal(f1
->dst_mac_addr
, f2
->dst_mac_addr
))
7855 static int bnxt_rx_flow_steer(struct net_device
*dev
, const struct sk_buff
*skb
,
7856 u16 rxq_index
, u32 flow_id
)
7858 struct bnxt
*bp
= netdev_priv(dev
);
7859 struct bnxt_ntuple_filter
*fltr
, *new_fltr
;
7860 struct flow_keys
*fkeys
;
7861 struct ethhdr
*eth
= (struct ethhdr
*)skb_mac_header(skb
);
7862 int rc
= 0, idx
, bit_id
, l2_idx
= 0;
7863 struct hlist_head
*head
;
7865 if (!ether_addr_equal(dev
->dev_addr
, eth
->h_dest
)) {
7866 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
7869 netif_addr_lock_bh(dev
);
7870 for (j
= 0; j
< vnic
->uc_filter_count
; j
++, off
+= ETH_ALEN
) {
7871 if (ether_addr_equal(eth
->h_dest
,
7872 vnic
->uc_list
+ off
)) {
7877 netif_addr_unlock_bh(dev
);
7881 new_fltr
= kzalloc(sizeof(*new_fltr
), GFP_ATOMIC
);
7885 fkeys
= &new_fltr
->fkeys
;
7886 if (!skb_flow_dissect_flow_keys(skb
, fkeys
, 0)) {
7887 rc
= -EPROTONOSUPPORT
;
7891 if ((fkeys
->basic
.n_proto
!= htons(ETH_P_IP
) &&
7892 fkeys
->basic
.n_proto
!= htons(ETH_P_IPV6
)) ||
7893 ((fkeys
->basic
.ip_proto
!= IPPROTO_TCP
) &&
7894 (fkeys
->basic
.ip_proto
!= IPPROTO_UDP
))) {
7895 rc
= -EPROTONOSUPPORT
;
7898 if (fkeys
->basic
.n_proto
== htons(ETH_P_IPV6
) &&
7899 bp
->hwrm_spec_code
< 0x10601) {
7900 rc
= -EPROTONOSUPPORT
;
7903 if ((fkeys
->control
.flags
& FLOW_DIS_ENCAPSULATION
) &&
7904 bp
->hwrm_spec_code
< 0x10601) {
7905 rc
= -EPROTONOSUPPORT
;
7909 memcpy(new_fltr
->dst_mac_addr
, eth
->h_dest
, ETH_ALEN
);
7910 memcpy(new_fltr
->src_mac_addr
, eth
->h_source
, ETH_ALEN
);
7912 idx
= skb_get_hash_raw(skb
) & BNXT_NTP_FLTR_HASH_MASK
;
7913 head
= &bp
->ntp_fltr_hash_tbl
[idx
];
7915 hlist_for_each_entry_rcu(fltr
, head
, hash
) {
7916 if (bnxt_fltr_match(fltr
, new_fltr
)) {
7924 spin_lock_bh(&bp
->ntp_fltr_lock
);
7925 bit_id
= bitmap_find_free_region(bp
->ntp_fltr_bmap
,
7926 BNXT_NTP_FLTR_MAX_FLTR
, 0);
7928 spin_unlock_bh(&bp
->ntp_fltr_lock
);
7933 new_fltr
->sw_id
= (u16
)bit_id
;
7934 new_fltr
->flow_id
= flow_id
;
7935 new_fltr
->l2_fltr_idx
= l2_idx
;
7936 new_fltr
->rxq
= rxq_index
;
7937 hlist_add_head_rcu(&new_fltr
->hash
, head
);
7938 bp
->ntp_fltr_count
++;
7939 spin_unlock_bh(&bp
->ntp_fltr_lock
);
7941 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT
, &bp
->sp_event
);
7942 bnxt_queue_sp_work(bp
);
7944 return new_fltr
->sw_id
;
7951 static void bnxt_cfg_ntp_filters(struct bnxt
*bp
)
7955 for (i
= 0; i
< BNXT_NTP_FLTR_HASH_SIZE
; i
++) {
7956 struct hlist_head
*head
;
7957 struct hlist_node
*tmp
;
7958 struct bnxt_ntuple_filter
*fltr
;
7961 head
= &bp
->ntp_fltr_hash_tbl
[i
];
7962 hlist_for_each_entry_safe(fltr
, tmp
, head
, hash
) {
7965 if (test_bit(BNXT_FLTR_VALID
, &fltr
->state
)) {
7966 if (rps_may_expire_flow(bp
->dev
, fltr
->rxq
,
7969 bnxt_hwrm_cfa_ntuple_filter_free(bp
,
7974 rc
= bnxt_hwrm_cfa_ntuple_filter_alloc(bp
,
7979 set_bit(BNXT_FLTR_VALID
, &fltr
->state
);
7983 spin_lock_bh(&bp
->ntp_fltr_lock
);
7984 hlist_del_rcu(&fltr
->hash
);
7985 bp
->ntp_fltr_count
--;
7986 spin_unlock_bh(&bp
->ntp_fltr_lock
);
7988 clear_bit(fltr
->sw_id
, bp
->ntp_fltr_bmap
);
7993 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT
, &bp
->sp_event
))
7994 netdev_info(bp
->dev
, "Receive PF driver unload event!");
7999 static void bnxt_cfg_ntp_filters(struct bnxt
*bp
)
8003 #endif /* CONFIG_RFS_ACCEL */
8005 static void bnxt_udp_tunnel_add(struct net_device
*dev
,
8006 struct udp_tunnel_info
*ti
)
8008 struct bnxt
*bp
= netdev_priv(dev
);
8010 if (ti
->sa_family
!= AF_INET6
&& ti
->sa_family
!= AF_INET
)
8013 if (!netif_running(dev
))
8017 case UDP_TUNNEL_TYPE_VXLAN
:
8018 if (bp
->vxlan_port_cnt
&& bp
->vxlan_port
!= ti
->port
)
8021 bp
->vxlan_port_cnt
++;
8022 if (bp
->vxlan_port_cnt
== 1) {
8023 bp
->vxlan_port
= ti
->port
;
8024 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT
, &bp
->sp_event
);
8025 bnxt_queue_sp_work(bp
);
8028 case UDP_TUNNEL_TYPE_GENEVE
:
8029 if (bp
->nge_port_cnt
&& bp
->nge_port
!= ti
->port
)
8033 if (bp
->nge_port_cnt
== 1) {
8034 bp
->nge_port
= ti
->port
;
8035 set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT
, &bp
->sp_event
);
8042 bnxt_queue_sp_work(bp
);
8045 static void bnxt_udp_tunnel_del(struct net_device
*dev
,
8046 struct udp_tunnel_info
*ti
)
8048 struct bnxt
*bp
= netdev_priv(dev
);
8050 if (ti
->sa_family
!= AF_INET6
&& ti
->sa_family
!= AF_INET
)
8053 if (!netif_running(dev
))
8057 case UDP_TUNNEL_TYPE_VXLAN
:
8058 if (!bp
->vxlan_port_cnt
|| bp
->vxlan_port
!= ti
->port
)
8060 bp
->vxlan_port_cnt
--;
8062 if (bp
->vxlan_port_cnt
!= 0)
8065 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT
, &bp
->sp_event
);
8067 case UDP_TUNNEL_TYPE_GENEVE
:
8068 if (!bp
->nge_port_cnt
|| bp
->nge_port
!= ti
->port
)
8072 if (bp
->nge_port_cnt
!= 0)
8075 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT
, &bp
->sp_event
);
8081 bnxt_queue_sp_work(bp
);
8084 static int bnxt_bridge_getlink(struct sk_buff
*skb
, u32 pid
, u32 seq
,
8085 struct net_device
*dev
, u32 filter_mask
,
8088 struct bnxt
*bp
= netdev_priv(dev
);
8090 return ndo_dflt_bridge_getlink(skb
, pid
, seq
, dev
, bp
->br_mode
, 0, 0,
8091 nlflags
, filter_mask
, NULL
);
8094 static int bnxt_bridge_setlink(struct net_device
*dev
, struct nlmsghdr
*nlh
,
8097 struct bnxt
*bp
= netdev_priv(dev
);
8098 struct nlattr
*attr
, *br_spec
;
8101 if (bp
->hwrm_spec_code
< 0x10708 || !BNXT_SINGLE_PF(bp
))
8104 br_spec
= nlmsg_find_attr(nlh
, sizeof(struct ifinfomsg
), IFLA_AF_SPEC
);
8108 nla_for_each_nested(attr
, br_spec
, rem
) {
8111 if (nla_type(attr
) != IFLA_BRIDGE_MODE
)
8114 if (nla_len(attr
) < sizeof(mode
))
8117 mode
= nla_get_u16(attr
);
8118 if (mode
== bp
->br_mode
)
8121 rc
= bnxt_hwrm_set_br_mode(bp
, mode
);
8129 static int bnxt_get_phys_port_name(struct net_device
*dev
, char *buf
,
8132 struct bnxt
*bp
= netdev_priv(dev
);
8135 /* The PF and it's VF-reps only support the switchdev framework */
8139 rc
= snprintf(buf
, len
, "p%d", bp
->pf
.port_id
);
8146 int bnxt_port_attr_get(struct bnxt
*bp
, struct switchdev_attr
*attr
)
8148 if (bp
->eswitch_mode
!= DEVLINK_ESWITCH_MODE_SWITCHDEV
)
8151 /* The PF and it's VF-reps only support the switchdev framework */
8156 case SWITCHDEV_ATTR_ID_PORT_PARENT_ID
:
8157 attr
->u
.ppid
.id_len
= sizeof(bp
->switch_id
);
8158 memcpy(attr
->u
.ppid
.id
, bp
->switch_id
, attr
->u
.ppid
.id_len
);
8166 static int bnxt_swdev_port_attr_get(struct net_device
*dev
,
8167 struct switchdev_attr
*attr
)
8169 return bnxt_port_attr_get(netdev_priv(dev
), attr
);
8172 static const struct switchdev_ops bnxt_switchdev_ops
= {
8173 .switchdev_port_attr_get
= bnxt_swdev_port_attr_get
8176 static const struct net_device_ops bnxt_netdev_ops
= {
8177 .ndo_open
= bnxt_open
,
8178 .ndo_start_xmit
= bnxt_start_xmit
,
8179 .ndo_stop
= bnxt_close
,
8180 .ndo_get_stats64
= bnxt_get_stats64
,
8181 .ndo_set_rx_mode
= bnxt_set_rx_mode
,
8182 .ndo_do_ioctl
= bnxt_ioctl
,
8183 .ndo_validate_addr
= eth_validate_addr
,
8184 .ndo_set_mac_address
= bnxt_change_mac_addr
,
8185 .ndo_change_mtu
= bnxt_change_mtu
,
8186 .ndo_fix_features
= bnxt_fix_features
,
8187 .ndo_set_features
= bnxt_set_features
,
8188 .ndo_tx_timeout
= bnxt_tx_timeout
,
8189 #ifdef CONFIG_BNXT_SRIOV
8190 .ndo_get_vf_config
= bnxt_get_vf_config
,
8191 .ndo_set_vf_mac
= bnxt_set_vf_mac
,
8192 .ndo_set_vf_vlan
= bnxt_set_vf_vlan
,
8193 .ndo_set_vf_rate
= bnxt_set_vf_bw
,
8194 .ndo_set_vf_link_state
= bnxt_set_vf_link_state
,
8195 .ndo_set_vf_spoofchk
= bnxt_set_vf_spoofchk
,
8197 #ifdef CONFIG_NET_POLL_CONTROLLER
8198 .ndo_poll_controller
= bnxt_poll_controller
,
8200 .ndo_setup_tc
= bnxt_setup_tc
,
8201 #ifdef CONFIG_RFS_ACCEL
8202 .ndo_rx_flow_steer
= bnxt_rx_flow_steer
,
8204 .ndo_udp_tunnel_add
= bnxt_udp_tunnel_add
,
8205 .ndo_udp_tunnel_del
= bnxt_udp_tunnel_del
,
8206 .ndo_bpf
= bnxt_xdp
,
8207 .ndo_bridge_getlink
= bnxt_bridge_getlink
,
8208 .ndo_bridge_setlink
= bnxt_bridge_setlink
,
8209 .ndo_get_phys_port_name
= bnxt_get_phys_port_name
8212 static void bnxt_remove_one(struct pci_dev
*pdev
)
8214 struct net_device
*dev
= pci_get_drvdata(pdev
);
8215 struct bnxt
*bp
= netdev_priv(dev
);
8218 bnxt_sriov_disable(bp
);
8219 bnxt_dl_unregister(bp
);
8222 pci_disable_pcie_error_reporting(pdev
);
8223 unregister_netdev(dev
);
8224 bnxt_shutdown_tc(bp
);
8225 bnxt_cancel_sp_work(bp
);
8228 bnxt_clear_int_mode(bp
);
8229 bnxt_hwrm_func_drv_unrgtr(bp
);
8230 bnxt_free_hwrm_resources(bp
);
8231 bnxt_free_hwrm_short_cmd_req(bp
);
8232 bnxt_ethtool_free(bp
);
8236 bnxt_cleanup_pci(bp
);
8240 static int bnxt_probe_phy(struct bnxt
*bp
)
8243 struct bnxt_link_info
*link_info
= &bp
->link_info
;
8245 rc
= bnxt_hwrm_phy_qcaps(bp
);
8247 netdev_err(bp
->dev
, "Probe phy can't get phy capabilities (rc: %x)\n",
8251 mutex_init(&bp
->link_lock
);
8253 rc
= bnxt_update_link(bp
, false);
8255 netdev_err(bp
->dev
, "Probe phy can't update link (rc: %x)\n",
8260 /* Older firmware does not have supported_auto_speeds, so assume
8261 * that all supported speeds can be autonegotiated.
8263 if (link_info
->auto_link_speeds
&& !link_info
->support_auto_speeds
)
8264 link_info
->support_auto_speeds
= link_info
->support_speeds
;
8266 /*initialize the ethool setting copy with NVM settings */
8267 if (BNXT_AUTO_MODE(link_info
->auto_mode
)) {
8268 link_info
->autoneg
= BNXT_AUTONEG_SPEED
;
8269 if (bp
->hwrm_spec_code
>= 0x10201) {
8270 if (link_info
->auto_pause_setting
&
8271 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE
)
8272 link_info
->autoneg
|= BNXT_AUTONEG_FLOW_CTRL
;
8274 link_info
->autoneg
|= BNXT_AUTONEG_FLOW_CTRL
;
8276 link_info
->advertising
= link_info
->auto_link_speeds
;
8278 link_info
->req_link_speed
= link_info
->force_link_speed
;
8279 link_info
->req_duplex
= link_info
->duplex_setting
;
8281 if (link_info
->autoneg
& BNXT_AUTONEG_FLOW_CTRL
)
8282 link_info
->req_flow_ctrl
=
8283 link_info
->auto_pause_setting
& BNXT_LINK_PAUSE_BOTH
;
8285 link_info
->req_flow_ctrl
= link_info
->force_pause_setting
;
8289 static int bnxt_get_max_irq(struct pci_dev
*pdev
)
8293 if (!pdev
->msix_cap
)
8296 pci_read_config_word(pdev
, pdev
->msix_cap
+ PCI_MSIX_FLAGS
, &ctrl
);
8297 return (ctrl
& PCI_MSIX_FLAGS_QSIZE
) + 1;
8300 static void _bnxt_get_max_rings(struct bnxt
*bp
, int *max_rx
, int *max_tx
,
8303 struct bnxt_hw_resc
*hw_resc
= &bp
->hw_resc
;
8304 int max_ring_grps
= 0;
8306 *max_tx
= hw_resc
->max_tx_rings
;
8307 *max_rx
= hw_resc
->max_rx_rings
;
8308 *max_cp
= min_t(int, hw_resc
->max_irqs
, hw_resc
->max_cp_rings
);
8309 *max_cp
= min_t(int, *max_cp
, hw_resc
->max_stat_ctxs
);
8310 max_ring_grps
= hw_resc
->max_hw_ring_grps
;
8311 if (BNXT_CHIP_TYPE_NITRO_A0(bp
) && BNXT_PF(bp
)) {
8315 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
)
8317 *max_rx
= min_t(int, *max_rx
, max_ring_grps
);
8320 int bnxt_get_max_rings(struct bnxt
*bp
, int *max_rx
, int *max_tx
, bool shared
)
8324 _bnxt_get_max_rings(bp
, &rx
, &tx
, &cp
);
8325 if (!rx
|| !tx
|| !cp
)
8330 return bnxt_trim_rings(bp
, max_rx
, max_tx
, cp
, shared
);
8333 static int bnxt_get_dflt_rings(struct bnxt
*bp
, int *max_rx
, int *max_tx
,
8338 rc
= bnxt_get_max_rings(bp
, max_rx
, max_tx
, shared
);
8339 if (rc
&& (bp
->flags
& BNXT_FLAG_AGG_RINGS
)) {
8340 /* Not enough rings, try disabling agg rings. */
8341 bp
->flags
&= ~BNXT_FLAG_AGG_RINGS
;
8342 rc
= bnxt_get_max_rings(bp
, max_rx
, max_tx
, shared
);
8345 bp
->flags
|= BNXT_FLAG_NO_AGG_RINGS
;
8346 bp
->dev
->hw_features
&= ~(NETIF_F_LRO
| NETIF_F_GRO_HW
);
8347 bp
->dev
->features
&= ~(NETIF_F_LRO
| NETIF_F_GRO_HW
);
8348 bnxt_set_ring_params(bp
);
8351 if (bp
->flags
& BNXT_FLAG_ROCE_CAP
) {
8352 int max_cp
, max_stat
, max_irq
;
8354 /* Reserve minimum resources for RoCE */
8355 max_cp
= bnxt_get_max_func_cp_rings(bp
);
8356 max_stat
= bnxt_get_max_func_stat_ctxs(bp
);
8357 max_irq
= bnxt_get_max_func_irqs(bp
);
8358 if (max_cp
<= BNXT_MIN_ROCE_CP_RINGS
||
8359 max_irq
<= BNXT_MIN_ROCE_CP_RINGS
||
8360 max_stat
<= BNXT_MIN_ROCE_STAT_CTXS
)
8363 max_cp
-= BNXT_MIN_ROCE_CP_RINGS
;
8364 max_irq
-= BNXT_MIN_ROCE_CP_RINGS
;
8365 max_stat
-= BNXT_MIN_ROCE_STAT_CTXS
;
8366 max_cp
= min_t(int, max_cp
, max_irq
);
8367 max_cp
= min_t(int, max_cp
, max_stat
);
8368 rc
= bnxt_trim_rings(bp
, max_rx
, max_tx
, max_cp
, shared
);
8375 /* In initial default shared ring setting, each shared ring must have a
8378 static void bnxt_trim_dflt_sh_rings(struct bnxt
*bp
)
8380 bp
->cp_nr_rings
= min_t(int, bp
->tx_nr_rings_per_tc
, bp
->rx_nr_rings
);
8381 bp
->rx_nr_rings
= bp
->cp_nr_rings
;
8382 bp
->tx_nr_rings_per_tc
= bp
->cp_nr_rings
;
8383 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
;
8386 static int bnxt_set_dflt_rings(struct bnxt
*bp
, bool sh
)
8388 int dflt_rings
, max_rx_rings
, max_tx_rings
, rc
;
8391 bp
->flags
|= BNXT_FLAG_SHARED_RINGS
;
8392 dflt_rings
= netif_get_num_default_rss_queues();
8393 /* Reduce default rings to reduce memory usage on multi-port cards */
8394 if (bp
->port_count
> 1)
8395 dflt_rings
= min_t(int, dflt_rings
, 4);
8396 rc
= bnxt_get_dflt_rings(bp
, &max_rx_rings
, &max_tx_rings
, sh
);
8399 bp
->rx_nr_rings
= min_t(int, dflt_rings
, max_rx_rings
);
8400 bp
->tx_nr_rings_per_tc
= min_t(int, dflt_rings
, max_tx_rings
);
8402 bnxt_trim_dflt_sh_rings(bp
);
8404 bp
->cp_nr_rings
= bp
->tx_nr_rings_per_tc
+ bp
->rx_nr_rings
;
8405 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
;
8407 rc
= __bnxt_reserve_rings(bp
);
8409 netdev_warn(bp
->dev
, "Unable to reserve tx rings\n");
8410 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
;
8412 bnxt_trim_dflt_sh_rings(bp
);
8414 /* Rings may have been trimmed, re-reserve the trimmed rings. */
8415 if (bnxt_need_reserve_rings(bp
)) {
8416 rc
= __bnxt_reserve_rings(bp
);
8418 netdev_warn(bp
->dev
, "2nd rings reservation failed.\n");
8419 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
;
8421 bp
->num_stat_ctxs
= bp
->cp_nr_rings
;
8422 if (BNXT_CHIP_TYPE_NITRO_A0(bp
)) {
8429 int bnxt_restore_pf_fw_resources(struct bnxt
*bp
)
8434 if (bnxt_ulp_registered(bp
->edev
, BNXT_ROCE_ULP
))
8437 bnxt_hwrm_func_qcaps(bp
);
8439 if (netif_running(bp
->dev
))
8440 __bnxt_close_nic(bp
, true, false);
8442 bnxt_clear_int_mode(bp
);
8443 rc
= bnxt_init_int_mode(bp
);
8445 if (netif_running(bp
->dev
)) {
8449 rc
= bnxt_open_nic(bp
, true, false);
8455 static int bnxt_init_mac_addr(struct bnxt
*bp
)
8460 memcpy(bp
->dev
->dev_addr
, bp
->pf
.mac_addr
, ETH_ALEN
);
8462 #ifdef CONFIG_BNXT_SRIOV
8463 struct bnxt_vf_info
*vf
= &bp
->vf
;
8465 if (is_valid_ether_addr(vf
->mac_addr
)) {
8466 /* overwrite netdev dev_addr with admin VF MAC */
8467 memcpy(bp
->dev
->dev_addr
, vf
->mac_addr
, ETH_ALEN
);
8469 eth_hw_addr_random(bp
->dev
);
8470 rc
= bnxt_approve_mac(bp
, bp
->dev
->dev_addr
);
8477 static void bnxt_parse_log_pcie_link(struct bnxt
*bp
)
8479 enum pcie_link_width width
= PCIE_LNK_WIDTH_UNKNOWN
;
8480 enum pci_bus_speed speed
= PCI_SPEED_UNKNOWN
;
8482 if (pcie_get_minimum_link(pci_physfn(bp
->pdev
), &speed
, &width
) ||
8483 speed
== PCI_SPEED_UNKNOWN
|| width
== PCIE_LNK_WIDTH_UNKNOWN
)
8484 netdev_info(bp
->dev
, "Failed to determine PCIe Link Info\n");
8486 netdev_info(bp
->dev
, "PCIe: Speed %s Width x%d\n",
8487 speed
== PCIE_SPEED_2_5GT
? "2.5GT/s" :
8488 speed
== PCIE_SPEED_5_0GT
? "5.0GT/s" :
8489 speed
== PCIE_SPEED_8_0GT
? "8.0GT/s" :
8493 static int bnxt_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
8495 static int version_printed
;
8496 struct net_device
*dev
;
8500 if (pci_is_bridge(pdev
))
8503 if (version_printed
++ == 0)
8504 pr_info("%s", version
);
8506 max_irqs
= bnxt_get_max_irq(pdev
);
8507 dev
= alloc_etherdev_mq(sizeof(*bp
), max_irqs
);
8511 bp
= netdev_priv(dev
);
8513 if (bnxt_vf_pciid(ent
->driver_data
))
8514 bp
->flags
|= BNXT_FLAG_VF
;
8517 bp
->flags
|= BNXT_FLAG_MSIX_CAP
;
8519 rc
= bnxt_init_board(pdev
, dev
);
8523 dev
->netdev_ops
= &bnxt_netdev_ops
;
8524 dev
->watchdog_timeo
= BNXT_TX_TIMEOUT
;
8525 dev
->ethtool_ops
= &bnxt_ethtool_ops
;
8526 SWITCHDEV_SET_OPS(dev
, &bnxt_switchdev_ops
);
8527 pci_set_drvdata(pdev
, dev
);
8529 rc
= bnxt_alloc_hwrm_resources(bp
);
8531 goto init_err_pci_clean
;
8533 mutex_init(&bp
->hwrm_cmd_lock
);
8534 rc
= bnxt_hwrm_ver_get(bp
);
8536 goto init_err_pci_clean
;
8538 if (bp
->flags
& BNXT_FLAG_SHORT_CMD
) {
8539 rc
= bnxt_alloc_hwrm_short_cmd_req(bp
);
8541 goto init_err_pci_clean
;
8544 rc
= bnxt_hwrm_func_reset(bp
);
8546 goto init_err_pci_clean
;
8548 bnxt_hwrm_fw_set_time(bp
);
8550 dev
->hw_features
= NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
| NETIF_F_SG
|
8551 NETIF_F_TSO
| NETIF_F_TSO6
|
8552 NETIF_F_GSO_UDP_TUNNEL
| NETIF_F_GSO_GRE
|
8553 NETIF_F_GSO_IPXIP4
|
8554 NETIF_F_GSO_UDP_TUNNEL_CSUM
| NETIF_F_GSO_GRE_CSUM
|
8555 NETIF_F_GSO_PARTIAL
| NETIF_F_RXHASH
|
8556 NETIF_F_RXCSUM
| NETIF_F_GRO
;
8558 if (!BNXT_CHIP_TYPE_NITRO_A0(bp
))
8559 dev
->hw_features
|= NETIF_F_LRO
;
8561 dev
->hw_enc_features
=
8562 NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
| NETIF_F_SG
|
8563 NETIF_F_TSO
| NETIF_F_TSO6
|
8564 NETIF_F_GSO_UDP_TUNNEL
| NETIF_F_GSO_GRE
|
8565 NETIF_F_GSO_UDP_TUNNEL_CSUM
| NETIF_F_GSO_GRE_CSUM
|
8566 NETIF_F_GSO_IPXIP4
| NETIF_F_GSO_PARTIAL
;
8567 dev
->gso_partial_features
= NETIF_F_GSO_UDP_TUNNEL_CSUM
|
8568 NETIF_F_GSO_GRE_CSUM
;
8569 dev
->vlan_features
= dev
->hw_features
| NETIF_F_HIGHDMA
;
8570 dev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_RX
| NETIF_F_HW_VLAN_CTAG_TX
|
8571 NETIF_F_HW_VLAN_STAG_RX
| NETIF_F_HW_VLAN_STAG_TX
;
8572 if (!BNXT_CHIP_TYPE_NITRO_A0(bp
))
8573 dev
->hw_features
|= NETIF_F_GRO_HW
;
8574 dev
->features
|= dev
->hw_features
| NETIF_F_HIGHDMA
;
8575 if (dev
->features
& NETIF_F_GRO_HW
)
8576 dev
->features
&= ~NETIF_F_LRO
;
8577 dev
->priv_flags
|= IFF_UNICAST_FLT
;
8579 #ifdef CONFIG_BNXT_SRIOV
8580 init_waitqueue_head(&bp
->sriov_cfg_wait
);
8581 mutex_init(&bp
->sriov_lock
);
8583 bp
->gro_func
= bnxt_gro_func_5730x
;
8584 if (BNXT_CHIP_P4_PLUS(bp
))
8585 bp
->gro_func
= bnxt_gro_func_5731x
;
8587 bp
->flags
|= BNXT_FLAG_DOUBLE_DB
;
8589 rc
= bnxt_hwrm_func_drv_rgtr(bp
);
8591 goto init_err_pci_clean
;
8593 rc
= bnxt_hwrm_func_rgtr_async_events(bp
, NULL
, 0);
8595 goto init_err_pci_clean
;
8597 bp
->ulp_probe
= bnxt_ulp_probe
;
8599 /* Get the MAX capabilities for this function */
8600 rc
= bnxt_hwrm_func_qcaps(bp
);
8602 netdev_err(bp
->dev
, "hwrm query capability failure rc: %x\n",
8605 goto init_err_pci_clean
;
8607 rc
= bnxt_init_mac_addr(bp
);
8609 dev_err(&pdev
->dev
, "Unable to initialize mac address.\n");
8610 rc
= -EADDRNOTAVAIL
;
8611 goto init_err_pci_clean
;
8613 rc
= bnxt_hwrm_queue_qportcfg(bp
);
8615 netdev_err(bp
->dev
, "hwrm query qportcfg failure rc: %x\n",
8618 goto init_err_pci_clean
;
8621 bnxt_hwrm_func_qcfg(bp
);
8622 bnxt_hwrm_port_led_qcaps(bp
);
8623 bnxt_ethtool_init(bp
);
8626 /* MTU range: 60 - FW defined max */
8627 dev
->min_mtu
= ETH_ZLEN
;
8628 dev
->max_mtu
= bp
->max_mtu
;
8630 rc
= bnxt_probe_phy(bp
);
8632 goto init_err_pci_clean
;
8634 bnxt_set_rx_skb_mode(bp
, false);
8635 bnxt_set_tpa_flags(bp
);
8636 bnxt_set_ring_params(bp
);
8637 bnxt_set_max_func_irqs(bp
, max_irqs
);
8638 rc
= bnxt_set_dflt_rings(bp
, true);
8640 netdev_err(bp
->dev
, "Not enough rings available.\n");
8642 goto init_err_pci_clean
;
8645 /* Default RSS hash cfg. */
8646 bp
->rss_hash_cfg
= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4
|
8647 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4
|
8648 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6
|
8649 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6
;
8650 if (BNXT_CHIP_P4_PLUS(bp
) && bp
->hwrm_spec_code
>= 0x10501) {
8651 bp
->flags
|= BNXT_FLAG_UDP_RSS_CAP
;
8652 bp
->rss_hash_cfg
|= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4
|
8653 VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6
;
8656 bnxt_hwrm_vnic_qcaps(bp
);
8657 if (bnxt_rfs_supported(bp
)) {
8658 dev
->hw_features
|= NETIF_F_NTUPLE
;
8659 if (bnxt_rfs_capable(bp
)) {
8660 bp
->flags
|= BNXT_FLAG_RFS
;
8661 dev
->features
|= NETIF_F_NTUPLE
;
8665 if (dev
->hw_features
& NETIF_F_HW_VLAN_CTAG_RX
)
8666 bp
->flags
|= BNXT_FLAG_STRIP_VLAN
;
8668 rc
= bnxt_init_int_mode(bp
);
8670 goto init_err_pci_clean
;
8672 /* No TC has been set yet and rings may have been trimmed due to
8673 * limited MSIX, so we re-initialize the TX rings per TC.
8675 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
;
8677 bnxt_get_wol_settings(bp
);
8678 if (bp
->flags
& BNXT_FLAG_WOL_CAP
)
8679 device_set_wakeup_enable(&pdev
->dev
, bp
->wol
);
8681 device_set_wakeup_capable(&pdev
->dev
, false);
8683 bnxt_hwrm_set_cache_line_size(bp
, cache_line_size());
8688 create_singlethread_workqueue("bnxt_pf_wq");
8690 dev_err(&pdev
->dev
, "Unable to create workqueue.\n");
8691 goto init_err_pci_clean
;
8697 rc
= register_netdev(dev
);
8699 goto init_err_cleanup_tc
;
8702 bnxt_dl_register(bp
);
8704 netdev_info(dev
, "%s found at mem %lx, node addr %pM\n",
8705 board_info
[ent
->driver_data
].name
,
8706 (long)pci_resource_start(pdev
, 0), dev
->dev_addr
);
8708 bnxt_parse_log_pcie_link(bp
);
8712 init_err_cleanup_tc
:
8713 bnxt_shutdown_tc(bp
);
8714 bnxt_clear_int_mode(bp
);
8717 bnxt_cleanup_pci(bp
);
8724 static void bnxt_shutdown(struct pci_dev
*pdev
)
8726 struct net_device
*dev
= pci_get_drvdata(pdev
);
8733 bp
= netdev_priv(dev
);
8737 if (netif_running(dev
))
8740 bnxt_ulp_shutdown(bp
);
8742 if (system_state
== SYSTEM_POWER_OFF
) {
8743 bnxt_clear_int_mode(bp
);
8744 pci_wake_from_d3(pdev
, bp
->wol
);
8745 pci_set_power_state(pdev
, PCI_D3hot
);
8752 #ifdef CONFIG_PM_SLEEP
8753 static int bnxt_suspend(struct device
*device
)
8755 struct pci_dev
*pdev
= to_pci_dev(device
);
8756 struct net_device
*dev
= pci_get_drvdata(pdev
);
8757 struct bnxt
*bp
= netdev_priv(dev
);
8761 if (netif_running(dev
)) {
8762 netif_device_detach(dev
);
8763 rc
= bnxt_close(dev
);
8765 bnxt_hwrm_func_drv_unrgtr(bp
);
8770 static int bnxt_resume(struct device
*device
)
8772 struct pci_dev
*pdev
= to_pci_dev(device
);
8773 struct net_device
*dev
= pci_get_drvdata(pdev
);
8774 struct bnxt
*bp
= netdev_priv(dev
);
8778 if (bnxt_hwrm_ver_get(bp
) || bnxt_hwrm_func_drv_rgtr(bp
)) {
8782 rc
= bnxt_hwrm_func_reset(bp
);
8787 bnxt_get_wol_settings(bp
);
8788 if (netif_running(dev
)) {
8789 rc
= bnxt_open(dev
);
8791 netif_device_attach(dev
);
8799 static SIMPLE_DEV_PM_OPS(bnxt_pm_ops
, bnxt_suspend
, bnxt_resume
);
8800 #define BNXT_PM_OPS (&bnxt_pm_ops)
8804 #define BNXT_PM_OPS NULL
8806 #endif /* CONFIG_PM_SLEEP */
8809 * bnxt_io_error_detected - called when PCI error is detected
8810 * @pdev: Pointer to PCI device
8811 * @state: The current pci connection state
8813 * This function is called after a PCI bus error affecting
8814 * this device has been detected.
8816 static pci_ers_result_t
bnxt_io_error_detected(struct pci_dev
*pdev
,
8817 pci_channel_state_t state
)
8819 struct net_device
*netdev
= pci_get_drvdata(pdev
);
8820 struct bnxt
*bp
= netdev_priv(netdev
);
8822 netdev_info(netdev
, "PCI I/O error detected\n");
8825 netif_device_detach(netdev
);
8829 if (state
== pci_channel_io_perm_failure
) {
8831 return PCI_ERS_RESULT_DISCONNECT
;
8834 if (netif_running(netdev
))
8837 pci_disable_device(pdev
);
8840 /* Request a slot slot reset. */
8841 return PCI_ERS_RESULT_NEED_RESET
;
8845 * bnxt_io_slot_reset - called after the pci bus has been reset.
8846 * @pdev: Pointer to PCI device
8848 * Restart the card from scratch, as if from a cold-boot.
8849 * At this point, the card has exprienced a hard reset,
8850 * followed by fixups by BIOS, and has its config space
8851 * set up identically to what it was at cold boot.
8853 static pci_ers_result_t
bnxt_io_slot_reset(struct pci_dev
*pdev
)
8855 struct net_device
*netdev
= pci_get_drvdata(pdev
);
8856 struct bnxt
*bp
= netdev_priv(netdev
);
8858 pci_ers_result_t result
= PCI_ERS_RESULT_DISCONNECT
;
8860 netdev_info(bp
->dev
, "PCI Slot Reset\n");
8864 if (pci_enable_device(pdev
)) {
8866 "Cannot re-enable PCI device after reset.\n");
8868 pci_set_master(pdev
);
8870 err
= bnxt_hwrm_func_reset(bp
);
8871 if (!err
&& netif_running(netdev
))
8872 err
= bnxt_open(netdev
);
8875 result
= PCI_ERS_RESULT_RECOVERED
;
8880 if (result
!= PCI_ERS_RESULT_RECOVERED
&& netif_running(netdev
))
8885 err
= pci_cleanup_aer_uncorrect_error_status(pdev
);
8888 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
8889 err
); /* non-fatal, continue */
8892 return PCI_ERS_RESULT_RECOVERED
;
8896 * bnxt_io_resume - called when traffic can start flowing again.
8897 * @pdev: Pointer to PCI device
8899 * This callback is called when the error recovery driver tells
8900 * us that its OK to resume normal operation.
8902 static void bnxt_io_resume(struct pci_dev
*pdev
)
8904 struct net_device
*netdev
= pci_get_drvdata(pdev
);
8908 netif_device_attach(netdev
);
8913 static const struct pci_error_handlers bnxt_err_handler
= {
8914 .error_detected
= bnxt_io_error_detected
,
8915 .slot_reset
= bnxt_io_slot_reset
,
8916 .resume
= bnxt_io_resume
8919 static struct pci_driver bnxt_pci_driver
= {
8920 .name
= DRV_MODULE_NAME
,
8921 .id_table
= bnxt_pci_tbl
,
8922 .probe
= bnxt_init_one
,
8923 .remove
= bnxt_remove_one
,
8924 .shutdown
= bnxt_shutdown
,
8925 .driver
.pm
= BNXT_PM_OPS
,
8926 .err_handler
= &bnxt_err_handler
,
8927 #if defined(CONFIG_BNXT_SRIOV)
8928 .sriov_configure
= bnxt_sriov_configure
,
8932 static int __init
bnxt_init(void)
8934 return pci_register_driver(&bnxt_pci_driver
);
8937 static void __exit
bnxt_exit(void)
8939 pci_unregister_driver(&bnxt_pci_driver
);
8941 destroy_workqueue(bnxt_pf_wq
);
8944 module_init(bnxt_init
);
8945 module_exit(bnxt_exit
);