1 /* Broadcom NetXtreme-C/E network driver.
3 * Copyright (c) 2014-2016 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
10 #include <linux/module.h>
12 #include <linux/stringify.h>
13 #include <linux/kernel.h>
14 #include <linux/timer.h>
15 #include <linux/errno.h>
16 #include <linux/ioport.h>
17 #include <linux/slab.h>
18 #include <linux/vmalloc.h>
19 #include <linux/interrupt.h>
20 #include <linux/pci.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23 #include <linux/skbuff.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/bitops.h>
27 #include <linux/irq.h>
28 #include <linux/delay.h>
29 #include <asm/byteorder.h>
31 #include <linux/time.h>
32 #include <linux/mii.h>
34 #include <linux/if_vlan.h>
38 #include <net/checksum.h>
39 #include <net/ip6_checksum.h>
40 #if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE)
41 #include <net/vxlan.h>
43 #ifdef CONFIG_NET_RX_BUSY_POLL
44 #include <net/busy_poll.h>
46 #include <linux/workqueue.h>
47 #include <linux/prefetch.h>
48 #include <linux/cache.h>
49 #include <linux/log2.h>
50 #include <linux/aer.h>
51 #include <linux/bitmap.h>
52 #include <linux/cpu_rmap.h>
56 #include "bnxt_sriov.h"
57 #include "bnxt_ethtool.h"
59 #define BNXT_TX_TIMEOUT (5 * HZ)
61 static const char version
[] =
62 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME
" v" DRV_MODULE_VERSION
"\n";
64 MODULE_LICENSE("GPL");
65 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
66 MODULE_VERSION(DRV_MODULE_VERSION
);
68 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
69 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
70 #define BNXT_RX_COPY_THRESH 256
72 #define BNXT_TX_PUSH_THRESH 164
85 /* indexed by enum above */
89 { "Broadcom BCM57301 NetXtreme-C Single-port 10Gb Ethernet" },
90 { "Broadcom BCM57302 NetXtreme-C Dual-port 10Gb/25Gb Ethernet" },
91 { "Broadcom BCM57304 NetXtreme-C Dual-port 10Gb/25Gb/40Gb/50Gb Ethernet" },
92 { "Broadcom BCM57402 NetXtreme-E Dual-port 10Gb Ethernet" },
93 { "Broadcom BCM57404 NetXtreme-E Dual-port 10Gb/25Gb Ethernet" },
94 { "Broadcom BCM57406 NetXtreme-E Dual-port 10GBase-T Ethernet" },
95 { "Broadcom BCM57304 NetXtreme-C Ethernet Virtual Function" },
96 { "Broadcom BCM57404 NetXtreme-E Ethernet Virtual Function" },
99 static const struct pci_device_id bnxt_pci_tbl
[] = {
100 { PCI_VDEVICE(BROADCOM
, 0x16c8), .driver_data
= BCM57301
},
101 { PCI_VDEVICE(BROADCOM
, 0x16c9), .driver_data
= BCM57302
},
102 { PCI_VDEVICE(BROADCOM
, 0x16ca), .driver_data
= BCM57304
},
103 { PCI_VDEVICE(BROADCOM
, 0x16d0), .driver_data
= BCM57402
},
104 { PCI_VDEVICE(BROADCOM
, 0x16d1), .driver_data
= BCM57404
},
105 { PCI_VDEVICE(BROADCOM
, 0x16d2), .driver_data
= BCM57406
},
106 #ifdef CONFIG_BNXT_SRIOV
107 { PCI_VDEVICE(BROADCOM
, 0x16cb), .driver_data
= BCM57304_VF
},
108 { PCI_VDEVICE(BROADCOM
, 0x16d3), .driver_data
= BCM57404_VF
},
113 MODULE_DEVICE_TABLE(pci
, bnxt_pci_tbl
);
115 static const u16 bnxt_vf_req_snif
[] = {
118 HWRM_CFA_L2_FILTER_ALLOC
,
121 static const u16 bnxt_async_events_arr
[] = {
122 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE
,
123 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD
,
124 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED
,
125 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE
,
128 static bool bnxt_vf_pciid(enum board_idx idx
)
130 return (idx
== BCM57304_VF
|| idx
== BCM57404_VF
);
133 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
134 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
135 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
137 #define BNXT_CP_DB_REARM(db, raw_cons) \
138 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
140 #define BNXT_CP_DB(db, raw_cons) \
141 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
143 #define BNXT_CP_DB_IRQ_DIS(db) \
144 writel(DB_CP_IRQ_DIS_FLAGS, db)
146 static inline u32
bnxt_tx_avail(struct bnxt
*bp
, struct bnxt_tx_ring_info
*txr
)
148 /* Tell compiler to fetch tx indices from memory. */
151 return bp
->tx_ring_size
-
152 ((txr
->tx_prod
- txr
->tx_cons
) & bp
->tx_ring_mask
);
155 static const u16 bnxt_lhint_arr
[] = {
156 TX_BD_FLAGS_LHINT_512_AND_SMALLER
,
157 TX_BD_FLAGS_LHINT_512_TO_1023
,
158 TX_BD_FLAGS_LHINT_1024_TO_2047
,
159 TX_BD_FLAGS_LHINT_1024_TO_2047
,
160 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
161 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
162 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
163 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
164 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
165 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
166 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
167 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
168 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
169 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
170 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
171 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
172 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
173 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
174 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
177 static netdev_tx_t
bnxt_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
179 struct bnxt
*bp
= netdev_priv(dev
);
181 struct tx_bd_ext
*txbd1
;
182 struct netdev_queue
*txq
;
185 unsigned int length
, pad
= 0;
186 u32 len
, free_size
, vlan_tag_flags
, cfa_action
, flags
;
188 struct pci_dev
*pdev
= bp
->pdev
;
189 struct bnxt_tx_ring_info
*txr
;
190 struct bnxt_sw_tx_bd
*tx_buf
;
192 i
= skb_get_queue_mapping(skb
);
193 if (unlikely(i
>= bp
->tx_nr_rings
)) {
194 dev_kfree_skb_any(skb
);
198 txr
= &bp
->tx_ring
[i
];
199 txq
= netdev_get_tx_queue(dev
, i
);
202 free_size
= bnxt_tx_avail(bp
, txr
);
203 if (unlikely(free_size
< skb_shinfo(skb
)->nr_frags
+ 2)) {
204 netif_tx_stop_queue(txq
);
205 return NETDEV_TX_BUSY
;
209 len
= skb_headlen(skb
);
210 last_frag
= skb_shinfo(skb
)->nr_frags
;
212 txbd
= &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
214 txbd
->tx_bd_opaque
= prod
;
216 tx_buf
= &txr
->tx_buf_ring
[prod
];
218 tx_buf
->nr_frags
= last_frag
;
222 if (skb_vlan_tag_present(skb
)) {
223 vlan_tag_flags
= TX_BD_CFA_META_KEY_VLAN
|
224 skb_vlan_tag_get(skb
);
225 /* Currently supports 8021Q, 8021AD vlan offloads
226 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
228 if (skb
->vlan_proto
== htons(ETH_P_8021Q
))
229 vlan_tag_flags
|= 1 << TX_BD_CFA_META_TPID_SHIFT
;
232 if (free_size
== bp
->tx_ring_size
&& length
<= bp
->tx_push_thresh
) {
233 struct tx_push_buffer
*tx_push_buf
= txr
->tx_push
;
234 struct tx_push_bd
*tx_push
= &tx_push_buf
->push_bd
;
235 struct tx_bd_ext
*tx_push1
= &tx_push
->txbd2
;
236 void *pdata
= tx_push_buf
->data
;
240 /* Set COAL_NOW to be ready quickly for the next push */
241 tx_push
->tx_bd_len_flags_type
=
242 cpu_to_le32((length
<< TX_BD_LEN_SHIFT
) |
243 TX_BD_TYPE_LONG_TX_BD
|
244 TX_BD_FLAGS_LHINT_512_AND_SMALLER
|
245 TX_BD_FLAGS_COAL_NOW
|
246 TX_BD_FLAGS_PACKET_END
|
247 (2 << TX_BD_FLAGS_BD_CNT_SHIFT
));
249 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
250 tx_push1
->tx_bd_hsize_lflags
=
251 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM
);
253 tx_push1
->tx_bd_hsize_lflags
= 0;
255 tx_push1
->tx_bd_cfa_meta
= cpu_to_le32(vlan_tag_flags
);
256 tx_push1
->tx_bd_cfa_action
= cpu_to_le32(cfa_action
);
258 end
= pdata
+ length
;
259 end
= PTR_ALIGN(end
, 8) - 1;
262 skb_copy_from_linear_data(skb
, pdata
, len
);
264 for (j
= 0; j
< last_frag
; j
++) {
265 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[j
];
268 fptr
= skb_frag_address_safe(frag
);
272 memcpy(pdata
, fptr
, skb_frag_size(frag
));
273 pdata
+= skb_frag_size(frag
);
276 txbd
->tx_bd_len_flags_type
= tx_push
->tx_bd_len_flags_type
;
277 txbd
->tx_bd_haddr
= txr
->data_mapping
;
278 prod
= NEXT_TX(prod
);
279 txbd
= &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
280 memcpy(txbd
, tx_push1
, sizeof(*txbd
));
281 prod
= NEXT_TX(prod
);
283 cpu_to_le32(DB_KEY_TX_PUSH
| DB_LONG_TX_PUSH
| prod
);
286 netdev_tx_sent_queue(txq
, skb
->len
);
288 push_len
= (length
+ sizeof(*tx_push
) + 7) / 8;
290 __iowrite64_copy(txr
->tx_doorbell
, tx_push_buf
, 16);
291 __iowrite64_copy(txr
->tx_doorbell
+ 4, tx_push_buf
+ 1,
294 __iowrite64_copy(txr
->tx_doorbell
, tx_push_buf
,
303 if (length
< BNXT_MIN_PKT_SIZE
) {
304 pad
= BNXT_MIN_PKT_SIZE
- length
;
305 if (skb_pad(skb
, pad
)) {
306 /* SKB already freed. */
310 length
= BNXT_MIN_PKT_SIZE
;
313 mapping
= dma_map_single(&pdev
->dev
, skb
->data
, len
, DMA_TO_DEVICE
);
315 if (unlikely(dma_mapping_error(&pdev
->dev
, mapping
))) {
316 dev_kfree_skb_any(skb
);
321 dma_unmap_addr_set(tx_buf
, mapping
, mapping
);
322 flags
= (len
<< TX_BD_LEN_SHIFT
) | TX_BD_TYPE_LONG_TX_BD
|
323 ((last_frag
+ 2) << TX_BD_FLAGS_BD_CNT_SHIFT
);
325 txbd
->tx_bd_haddr
= cpu_to_le64(mapping
);
327 prod
= NEXT_TX(prod
);
328 txbd1
= (struct tx_bd_ext
*)
329 &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
331 txbd1
->tx_bd_hsize_lflags
= 0;
332 if (skb_is_gso(skb
)) {
335 if (skb
->encapsulation
)
336 hdr_len
= skb_inner_network_offset(skb
) +
337 skb_inner_network_header_len(skb
) +
338 inner_tcp_hdrlen(skb
);
340 hdr_len
= skb_transport_offset(skb
) +
343 txbd1
->tx_bd_hsize_lflags
= cpu_to_le32(TX_BD_FLAGS_LSO
|
345 (hdr_len
<< (TX_BD_HSIZE_SHIFT
- 1)));
346 length
= skb_shinfo(skb
)->gso_size
;
347 txbd1
->tx_bd_mss
= cpu_to_le32(length
);
349 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
350 txbd1
->tx_bd_hsize_lflags
=
351 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM
);
352 txbd1
->tx_bd_mss
= 0;
356 flags
|= bnxt_lhint_arr
[length
];
357 txbd
->tx_bd_len_flags_type
= cpu_to_le32(flags
);
359 txbd1
->tx_bd_cfa_meta
= cpu_to_le32(vlan_tag_flags
);
360 txbd1
->tx_bd_cfa_action
= cpu_to_le32(cfa_action
);
361 for (i
= 0; i
< last_frag
; i
++) {
362 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
364 prod
= NEXT_TX(prod
);
365 txbd
= &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
367 len
= skb_frag_size(frag
);
368 mapping
= skb_frag_dma_map(&pdev
->dev
, frag
, 0, len
,
371 if (unlikely(dma_mapping_error(&pdev
->dev
, mapping
)))
374 tx_buf
= &txr
->tx_buf_ring
[prod
];
375 dma_unmap_addr_set(tx_buf
, mapping
, mapping
);
377 txbd
->tx_bd_haddr
= cpu_to_le64(mapping
);
379 flags
= len
<< TX_BD_LEN_SHIFT
;
380 txbd
->tx_bd_len_flags_type
= cpu_to_le32(flags
);
384 txbd
->tx_bd_len_flags_type
=
385 cpu_to_le32(((len
+ pad
) << TX_BD_LEN_SHIFT
) | flags
|
386 TX_BD_FLAGS_PACKET_END
);
388 netdev_tx_sent_queue(txq
, skb
->len
);
390 /* Sync BD data before updating doorbell */
393 prod
= NEXT_TX(prod
);
396 writel(DB_KEY_TX
| prod
, txr
->tx_doorbell
);
397 writel(DB_KEY_TX
| prod
, txr
->tx_doorbell
);
403 if (unlikely(bnxt_tx_avail(bp
, txr
) <= MAX_SKB_FRAGS
+ 1)) {
404 netif_tx_stop_queue(txq
);
406 /* netif_tx_stop_queue() must be done before checking
407 * tx index in bnxt_tx_avail() below, because in
408 * bnxt_tx_int(), we update tx index before checking for
409 * netif_tx_queue_stopped().
412 if (bnxt_tx_avail(bp
, txr
) > bp
->tx_wake_thresh
)
413 netif_tx_wake_queue(txq
);
420 /* start back at beginning and unmap skb */
422 tx_buf
= &txr
->tx_buf_ring
[prod
];
424 dma_unmap_single(&pdev
->dev
, dma_unmap_addr(tx_buf
, mapping
),
425 skb_headlen(skb
), PCI_DMA_TODEVICE
);
426 prod
= NEXT_TX(prod
);
428 /* unmap remaining mapped pages */
429 for (i
= 0; i
< last_frag
; i
++) {
430 prod
= NEXT_TX(prod
);
431 tx_buf
= &txr
->tx_buf_ring
[prod
];
432 dma_unmap_page(&pdev
->dev
, dma_unmap_addr(tx_buf
, mapping
),
433 skb_frag_size(&skb_shinfo(skb
)->frags
[i
]),
437 dev_kfree_skb_any(skb
);
441 static void bnxt_tx_int(struct bnxt
*bp
, struct bnxt_napi
*bnapi
, int nr_pkts
)
443 struct bnxt_tx_ring_info
*txr
= bnapi
->tx_ring
;
444 int index
= txr
- &bp
->tx_ring
[0];
445 struct netdev_queue
*txq
= netdev_get_tx_queue(bp
->dev
, index
);
446 u16 cons
= txr
->tx_cons
;
447 struct pci_dev
*pdev
= bp
->pdev
;
449 unsigned int tx_bytes
= 0;
451 for (i
= 0; i
< nr_pkts
; i
++) {
452 struct bnxt_sw_tx_bd
*tx_buf
;
456 tx_buf
= &txr
->tx_buf_ring
[cons
];
457 cons
= NEXT_TX(cons
);
461 if (tx_buf
->is_push
) {
466 dma_unmap_single(&pdev
->dev
, dma_unmap_addr(tx_buf
, mapping
),
467 skb_headlen(skb
), PCI_DMA_TODEVICE
);
468 last
= tx_buf
->nr_frags
;
470 for (j
= 0; j
< last
; j
++) {
471 cons
= NEXT_TX(cons
);
472 tx_buf
= &txr
->tx_buf_ring
[cons
];
475 dma_unmap_addr(tx_buf
, mapping
),
476 skb_frag_size(&skb_shinfo(skb
)->frags
[j
]),
481 cons
= NEXT_TX(cons
);
483 tx_bytes
+= skb
->len
;
484 dev_kfree_skb_any(skb
);
487 netdev_tx_completed_queue(txq
, nr_pkts
, tx_bytes
);
490 /* Need to make the tx_cons update visible to bnxt_start_xmit()
491 * before checking for netif_tx_queue_stopped(). Without the
492 * memory barrier, there is a small possibility that bnxt_start_xmit()
493 * will miss it and cause the queue to be stopped forever.
497 if (unlikely(netif_tx_queue_stopped(txq
)) &&
498 (bnxt_tx_avail(bp
, txr
) > bp
->tx_wake_thresh
)) {
499 __netif_tx_lock(txq
, smp_processor_id());
500 if (netif_tx_queue_stopped(txq
) &&
501 bnxt_tx_avail(bp
, txr
) > bp
->tx_wake_thresh
&&
502 txr
->dev_state
!= BNXT_DEV_STATE_CLOSING
)
503 netif_tx_wake_queue(txq
);
504 __netif_tx_unlock(txq
);
508 static inline u8
*__bnxt_alloc_rx_data(struct bnxt
*bp
, dma_addr_t
*mapping
,
512 struct pci_dev
*pdev
= bp
->pdev
;
514 data
= kmalloc(bp
->rx_buf_size
, gfp
);
518 *mapping
= dma_map_single(&pdev
->dev
, data
+ BNXT_RX_DMA_OFFSET
,
519 bp
->rx_buf_use_size
, PCI_DMA_FROMDEVICE
);
521 if (dma_mapping_error(&pdev
->dev
, *mapping
)) {
528 static inline int bnxt_alloc_rx_data(struct bnxt
*bp
,
529 struct bnxt_rx_ring_info
*rxr
,
532 struct rx_bd
*rxbd
= &rxr
->rx_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
533 struct bnxt_sw_rx_bd
*rx_buf
= &rxr
->rx_buf_ring
[prod
];
537 data
= __bnxt_alloc_rx_data(bp
, &mapping
, gfp
);
542 dma_unmap_addr_set(rx_buf
, mapping
, mapping
);
544 rxbd
->rx_bd_haddr
= cpu_to_le64(mapping
);
549 static void bnxt_reuse_rx_data(struct bnxt_rx_ring_info
*rxr
, u16 cons
,
552 u16 prod
= rxr
->rx_prod
;
553 struct bnxt_sw_rx_bd
*cons_rx_buf
, *prod_rx_buf
;
554 struct rx_bd
*cons_bd
, *prod_bd
;
556 prod_rx_buf
= &rxr
->rx_buf_ring
[prod
];
557 cons_rx_buf
= &rxr
->rx_buf_ring
[cons
];
559 prod_rx_buf
->data
= data
;
561 dma_unmap_addr_set(prod_rx_buf
, mapping
,
562 dma_unmap_addr(cons_rx_buf
, mapping
));
564 prod_bd
= &rxr
->rx_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
565 cons_bd
= &rxr
->rx_desc_ring
[RX_RING(cons
)][RX_IDX(cons
)];
567 prod_bd
->rx_bd_haddr
= cons_bd
->rx_bd_haddr
;
570 static inline u16
bnxt_find_next_agg_idx(struct bnxt_rx_ring_info
*rxr
, u16 idx
)
572 u16 next
, max
= rxr
->rx_agg_bmap_size
;
574 next
= find_next_zero_bit(rxr
->rx_agg_bmap
, max
, idx
);
576 next
= find_first_zero_bit(rxr
->rx_agg_bmap
, max
);
580 static inline int bnxt_alloc_rx_page(struct bnxt
*bp
,
581 struct bnxt_rx_ring_info
*rxr
,
585 &rxr
->rx_agg_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
586 struct bnxt_sw_rx_agg_bd
*rx_agg_buf
;
587 struct pci_dev
*pdev
= bp
->pdev
;
590 u16 sw_prod
= rxr
->rx_sw_agg_prod
;
592 page
= alloc_page(gfp
);
596 mapping
= dma_map_page(&pdev
->dev
, page
, 0, PAGE_SIZE
,
598 if (dma_mapping_error(&pdev
->dev
, mapping
)) {
603 if (unlikely(test_bit(sw_prod
, rxr
->rx_agg_bmap
)))
604 sw_prod
= bnxt_find_next_agg_idx(rxr
, sw_prod
);
606 __set_bit(sw_prod
, rxr
->rx_agg_bmap
);
607 rx_agg_buf
= &rxr
->rx_agg_ring
[sw_prod
];
608 rxr
->rx_sw_agg_prod
= NEXT_RX_AGG(sw_prod
);
610 rx_agg_buf
->page
= page
;
611 rx_agg_buf
->mapping
= mapping
;
612 rxbd
->rx_bd_haddr
= cpu_to_le64(mapping
);
613 rxbd
->rx_bd_opaque
= sw_prod
;
617 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi
*bnapi
, u16 cp_cons
,
620 struct bnxt
*bp
= bnapi
->bp
;
621 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
622 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
623 u16 prod
= rxr
->rx_agg_prod
;
624 u16 sw_prod
= rxr
->rx_sw_agg_prod
;
627 for (i
= 0; i
< agg_bufs
; i
++) {
629 struct rx_agg_cmp
*agg
;
630 struct bnxt_sw_rx_agg_bd
*cons_rx_buf
, *prod_rx_buf
;
631 struct rx_bd
*prod_bd
;
634 agg
= (struct rx_agg_cmp
*)
635 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
636 cons
= agg
->rx_agg_cmp_opaque
;
637 __clear_bit(cons
, rxr
->rx_agg_bmap
);
639 if (unlikely(test_bit(sw_prod
, rxr
->rx_agg_bmap
)))
640 sw_prod
= bnxt_find_next_agg_idx(rxr
, sw_prod
);
642 __set_bit(sw_prod
, rxr
->rx_agg_bmap
);
643 prod_rx_buf
= &rxr
->rx_agg_ring
[sw_prod
];
644 cons_rx_buf
= &rxr
->rx_agg_ring
[cons
];
646 /* It is possible for sw_prod to be equal to cons, so
647 * set cons_rx_buf->page to NULL first.
649 page
= cons_rx_buf
->page
;
650 cons_rx_buf
->page
= NULL
;
651 prod_rx_buf
->page
= page
;
653 prod_rx_buf
->mapping
= cons_rx_buf
->mapping
;
655 prod_bd
= &rxr
->rx_agg_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
657 prod_bd
->rx_bd_haddr
= cpu_to_le64(cons_rx_buf
->mapping
);
658 prod_bd
->rx_bd_opaque
= sw_prod
;
660 prod
= NEXT_RX_AGG(prod
);
661 sw_prod
= NEXT_RX_AGG(sw_prod
);
662 cp_cons
= NEXT_CMP(cp_cons
);
664 rxr
->rx_agg_prod
= prod
;
665 rxr
->rx_sw_agg_prod
= sw_prod
;
668 static struct sk_buff
*bnxt_rx_skb(struct bnxt
*bp
,
669 struct bnxt_rx_ring_info
*rxr
, u16 cons
,
670 u16 prod
, u8
*data
, dma_addr_t dma_addr
,
676 err
= bnxt_alloc_rx_data(bp
, rxr
, prod
, GFP_ATOMIC
);
678 bnxt_reuse_rx_data(rxr
, cons
, data
);
682 skb
= build_skb(data
, 0);
683 dma_unmap_single(&bp
->pdev
->dev
, dma_addr
, bp
->rx_buf_use_size
,
690 skb_reserve(skb
, BNXT_RX_OFFSET
);
695 static struct sk_buff
*bnxt_rx_pages(struct bnxt
*bp
, struct bnxt_napi
*bnapi
,
696 struct sk_buff
*skb
, u16 cp_cons
,
699 struct pci_dev
*pdev
= bp
->pdev
;
700 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
701 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
702 u16 prod
= rxr
->rx_agg_prod
;
705 for (i
= 0; i
< agg_bufs
; i
++) {
707 struct rx_agg_cmp
*agg
;
708 struct bnxt_sw_rx_agg_bd
*cons_rx_buf
;
712 agg
= (struct rx_agg_cmp
*)
713 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
714 cons
= agg
->rx_agg_cmp_opaque
;
715 frag_len
= (le32_to_cpu(agg
->rx_agg_cmp_len_flags_type
) &
716 RX_AGG_CMP_LEN
) >> RX_AGG_CMP_LEN_SHIFT
;
718 cons_rx_buf
= &rxr
->rx_agg_ring
[cons
];
719 skb_fill_page_desc(skb
, i
, cons_rx_buf
->page
, 0, frag_len
);
720 __clear_bit(cons
, rxr
->rx_agg_bmap
);
722 /* It is possible for bnxt_alloc_rx_page() to allocate
723 * a sw_prod index that equals the cons index, so we
724 * need to clear the cons entry now.
726 mapping
= dma_unmap_addr(cons_rx_buf
, mapping
);
727 page
= cons_rx_buf
->page
;
728 cons_rx_buf
->page
= NULL
;
730 if (bnxt_alloc_rx_page(bp
, rxr
, prod
, GFP_ATOMIC
) != 0) {
731 struct skb_shared_info
*shinfo
;
732 unsigned int nr_frags
;
734 shinfo
= skb_shinfo(skb
);
735 nr_frags
= --shinfo
->nr_frags
;
736 __skb_frag_set_page(&shinfo
->frags
[nr_frags
], NULL
);
740 cons_rx_buf
->page
= page
;
742 /* Update prod since possibly some pages have been
745 rxr
->rx_agg_prod
= prod
;
746 bnxt_reuse_rx_agg_bufs(bnapi
, cp_cons
, agg_bufs
- i
);
750 dma_unmap_page(&pdev
->dev
, mapping
, PAGE_SIZE
,
753 skb
->data_len
+= frag_len
;
754 skb
->len
+= frag_len
;
755 skb
->truesize
+= PAGE_SIZE
;
757 prod
= NEXT_RX_AGG(prod
);
758 cp_cons
= NEXT_CMP(cp_cons
);
760 rxr
->rx_agg_prod
= prod
;
764 static int bnxt_agg_bufs_valid(struct bnxt
*bp
, struct bnxt_cp_ring_info
*cpr
,
765 u8 agg_bufs
, u32
*raw_cons
)
768 struct rx_agg_cmp
*agg
;
770 *raw_cons
= ADV_RAW_CMP(*raw_cons
, agg_bufs
);
771 last
= RING_CMP(*raw_cons
);
772 agg
= (struct rx_agg_cmp
*)
773 &cpr
->cp_desc_ring
[CP_RING(last
)][CP_IDX(last
)];
774 return RX_AGG_CMP_VALID(agg
, *raw_cons
);
777 static inline struct sk_buff
*bnxt_copy_skb(struct bnxt_napi
*bnapi
, u8
*data
,
781 struct bnxt
*bp
= bnapi
->bp
;
782 struct pci_dev
*pdev
= bp
->pdev
;
785 skb
= napi_alloc_skb(&bnapi
->napi
, len
);
789 dma_sync_single_for_cpu(&pdev
->dev
, mapping
,
790 bp
->rx_copy_thresh
, PCI_DMA_FROMDEVICE
);
792 memcpy(skb
->data
- BNXT_RX_OFFSET
, data
, len
+ BNXT_RX_OFFSET
);
794 dma_sync_single_for_device(&pdev
->dev
, mapping
,
802 static void bnxt_tpa_start(struct bnxt
*bp
, struct bnxt_rx_ring_info
*rxr
,
803 struct rx_tpa_start_cmp
*tpa_start
,
804 struct rx_tpa_start_cmp_ext
*tpa_start1
)
806 u8 agg_id
= TPA_START_AGG_ID(tpa_start
);
808 struct bnxt_tpa_info
*tpa_info
;
809 struct bnxt_sw_rx_bd
*cons_rx_buf
, *prod_rx_buf
;
810 struct rx_bd
*prod_bd
;
813 cons
= tpa_start
->rx_tpa_start_cmp_opaque
;
815 cons_rx_buf
= &rxr
->rx_buf_ring
[cons
];
816 prod_rx_buf
= &rxr
->rx_buf_ring
[prod
];
817 tpa_info
= &rxr
->rx_tpa
[agg_id
];
819 prod_rx_buf
->data
= tpa_info
->data
;
821 mapping
= tpa_info
->mapping
;
822 dma_unmap_addr_set(prod_rx_buf
, mapping
, mapping
);
824 prod_bd
= &rxr
->rx_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
826 prod_bd
->rx_bd_haddr
= cpu_to_le64(mapping
);
828 tpa_info
->data
= cons_rx_buf
->data
;
829 cons_rx_buf
->data
= NULL
;
830 tpa_info
->mapping
= dma_unmap_addr(cons_rx_buf
, mapping
);
833 le32_to_cpu(tpa_start
->rx_tpa_start_cmp_len_flags_type
) >>
834 RX_TPA_START_CMP_LEN_SHIFT
;
835 if (likely(TPA_START_HASH_VALID(tpa_start
))) {
836 u32 hash_type
= TPA_START_HASH_TYPE(tpa_start
);
838 tpa_info
->hash_type
= PKT_HASH_TYPE_L4
;
839 tpa_info
->gso_type
= SKB_GSO_TCPV4
;
840 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
842 tpa_info
->gso_type
= SKB_GSO_TCPV6
;
844 le32_to_cpu(tpa_start
->rx_tpa_start_cmp_rss_hash
);
846 tpa_info
->hash_type
= PKT_HASH_TYPE_NONE
;
847 tpa_info
->gso_type
= 0;
848 if (netif_msg_rx_err(bp
))
849 netdev_warn(bp
->dev
, "TPA packet without valid hash\n");
851 tpa_info
->flags2
= le32_to_cpu(tpa_start1
->rx_tpa_start_cmp_flags2
);
852 tpa_info
->metadata
= le32_to_cpu(tpa_start1
->rx_tpa_start_cmp_metadata
);
854 rxr
->rx_prod
= NEXT_RX(prod
);
855 cons
= NEXT_RX(cons
);
856 cons_rx_buf
= &rxr
->rx_buf_ring
[cons
];
858 bnxt_reuse_rx_data(rxr
, cons
, cons_rx_buf
->data
);
859 rxr
->rx_prod
= NEXT_RX(rxr
->rx_prod
);
860 cons_rx_buf
->data
= NULL
;
863 static void bnxt_abort_tpa(struct bnxt
*bp
, struct bnxt_napi
*bnapi
,
864 u16 cp_cons
, u32 agg_bufs
)
867 bnxt_reuse_rx_agg_bufs(bnapi
, cp_cons
, agg_bufs
);
870 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
871 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
873 static inline struct sk_buff
*bnxt_gro_skb(struct bnxt_tpa_info
*tpa_info
,
874 struct rx_tpa_end_cmp
*tpa_end
,
875 struct rx_tpa_end_cmp_ext
*tpa_end1
,
880 int payload_off
, tcp_opt_len
= 0;
884 segs
= TPA_END_TPA_SEGS(tpa_end
);
888 NAPI_GRO_CB(skb
)->count
= segs
;
889 skb_shinfo(skb
)->gso_size
=
890 le32_to_cpu(tpa_end1
->rx_tpa_end_cmp_seg_len
);
891 skb_shinfo(skb
)->gso_type
= tpa_info
->gso_type
;
892 payload_off
= (le32_to_cpu(tpa_end
->rx_tpa_end_cmp_misc_v1
) &
893 RX_TPA_END_CMP_PAYLOAD_OFFSET
) >>
894 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT
;
895 if (TPA_END_GRO_TS(tpa_end
))
898 if (tpa_info
->gso_type
== SKB_GSO_TCPV4
) {
901 nw_off
= payload_off
- BNXT_IPV4_HDR_SIZE
- tcp_opt_len
-
903 skb_set_network_header(skb
, nw_off
);
905 skb_set_transport_header(skb
, nw_off
+ sizeof(struct iphdr
));
906 len
= skb
->len
- skb_transport_offset(skb
);
908 th
->check
= ~tcp_v4_check(len
, iph
->saddr
, iph
->daddr
, 0);
909 } else if (tpa_info
->gso_type
== SKB_GSO_TCPV6
) {
912 nw_off
= payload_off
- BNXT_IPV6_HDR_SIZE
- tcp_opt_len
-
914 skb_set_network_header(skb
, nw_off
);
916 skb_set_transport_header(skb
, nw_off
+ sizeof(struct ipv6hdr
));
917 len
= skb
->len
- skb_transport_offset(skb
);
919 th
->check
= ~tcp_v6_check(len
, &iph
->saddr
, &iph
->daddr
, 0);
921 dev_kfree_skb_any(skb
);
924 tcp_gro_complete(skb
);
926 if (nw_off
) { /* tunnel */
927 struct udphdr
*uh
= NULL
;
929 if (skb
->protocol
== htons(ETH_P_IP
)) {
930 struct iphdr
*iph
= (struct iphdr
*)skb
->data
;
932 if (iph
->protocol
== IPPROTO_UDP
)
933 uh
= (struct udphdr
*)(iph
+ 1);
935 struct ipv6hdr
*iph
= (struct ipv6hdr
*)skb
->data
;
937 if (iph
->nexthdr
== IPPROTO_UDP
)
938 uh
= (struct udphdr
*)(iph
+ 1);
942 skb_shinfo(skb
)->gso_type
|=
943 SKB_GSO_UDP_TUNNEL_CSUM
;
945 skb_shinfo(skb
)->gso_type
|= SKB_GSO_UDP_TUNNEL
;
952 static inline struct sk_buff
*bnxt_tpa_end(struct bnxt
*bp
,
953 struct bnxt_napi
*bnapi
,
955 struct rx_tpa_end_cmp
*tpa_end
,
956 struct rx_tpa_end_cmp_ext
*tpa_end1
,
959 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
960 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
961 u8 agg_id
= TPA_END_AGG_ID(tpa_end
);
963 u16 cp_cons
= RING_CMP(*raw_cons
);
965 struct bnxt_tpa_info
*tpa_info
;
969 tpa_info
= &rxr
->rx_tpa
[agg_id
];
970 data
= tpa_info
->data
;
973 mapping
= tpa_info
->mapping
;
975 agg_bufs
= (le32_to_cpu(tpa_end
->rx_tpa_end_cmp_misc_v1
) &
976 RX_TPA_END_CMP_AGG_BUFS
) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT
;
979 if (!bnxt_agg_bufs_valid(bp
, cpr
, agg_bufs
, raw_cons
))
980 return ERR_PTR(-EBUSY
);
983 cp_cons
= NEXT_CMP(cp_cons
);
986 if (unlikely(agg_bufs
> MAX_SKB_FRAGS
)) {
987 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
988 netdev_warn(bp
->dev
, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
989 agg_bufs
, (int)MAX_SKB_FRAGS
);
993 if (len
<= bp
->rx_copy_thresh
) {
994 skb
= bnxt_copy_skb(bnapi
, data
, len
, mapping
);
996 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
1001 dma_addr_t new_mapping
;
1003 new_data
= __bnxt_alloc_rx_data(bp
, &new_mapping
, GFP_ATOMIC
);
1005 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
1009 tpa_info
->data
= new_data
;
1010 tpa_info
->mapping
= new_mapping
;
1012 skb
= build_skb(data
, 0);
1013 dma_unmap_single(&bp
->pdev
->dev
, mapping
, bp
->rx_buf_use_size
,
1014 PCI_DMA_FROMDEVICE
);
1018 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
1021 skb_reserve(skb
, BNXT_RX_OFFSET
);
1026 skb
= bnxt_rx_pages(bp
, bnapi
, skb
, cp_cons
, agg_bufs
);
1028 /* Page reuse already handled by bnxt_rx_pages(). */
1032 skb
->protocol
= eth_type_trans(skb
, bp
->dev
);
1034 if (tpa_info
->hash_type
!= PKT_HASH_TYPE_NONE
)
1035 skb_set_hash(skb
, tpa_info
->rss_hash
, tpa_info
->hash_type
);
1037 if (tpa_info
->flags2
& RX_CMP_FLAGS2_META_FORMAT_VLAN
) {
1038 netdev_features_t features
= skb
->dev
->features
;
1039 u16 vlan_proto
= tpa_info
->metadata
>>
1040 RX_CMP_FLAGS2_METADATA_TPID_SFT
;
1042 if (((features
& NETIF_F_HW_VLAN_CTAG_RX
) &&
1043 vlan_proto
== ETH_P_8021Q
) ||
1044 ((features
& NETIF_F_HW_VLAN_STAG_RX
) &&
1045 vlan_proto
== ETH_P_8021AD
)) {
1046 __vlan_hwaccel_put_tag(skb
, htons(vlan_proto
),
1047 tpa_info
->metadata
&
1048 RX_CMP_FLAGS2_METADATA_VID_MASK
);
1052 skb_checksum_none_assert(skb
);
1053 if (likely(tpa_info
->flags2
& RX_TPA_START_CMP_FLAGS2_L4_CS_CALC
)) {
1054 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1056 (tpa_info
->flags2
& RX_CMP_FLAGS2_T_L4_CS_CALC
) >> 3;
1059 if (TPA_END_GRO(tpa_end
))
1060 skb
= bnxt_gro_skb(tpa_info
, tpa_end
, tpa_end1
, skb
);
1065 /* returns the following:
1066 * 1 - 1 packet successfully received
1067 * 0 - successful TPA_START, packet not completed yet
1068 * -EBUSY - completion ring does not have all the agg buffers yet
1069 * -ENOMEM - packet aborted due to out of memory
1070 * -EIO - packet aborted due to hw error indicated in BD
1072 static int bnxt_rx_pkt(struct bnxt
*bp
, struct bnxt_napi
*bnapi
, u32
*raw_cons
,
1075 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1076 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
1077 struct net_device
*dev
= bp
->dev
;
1078 struct rx_cmp
*rxcmp
;
1079 struct rx_cmp_ext
*rxcmp1
;
1080 u32 tmp_raw_cons
= *raw_cons
;
1081 u16 cons
, prod
, cp_cons
= RING_CMP(tmp_raw_cons
);
1082 struct bnxt_sw_rx_bd
*rx_buf
;
1084 u8
*data
, agg_bufs
, cmp_type
;
1085 dma_addr_t dma_addr
;
1086 struct sk_buff
*skb
;
1089 rxcmp
= (struct rx_cmp
*)
1090 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
1092 tmp_raw_cons
= NEXT_RAW_CMP(tmp_raw_cons
);
1093 cp_cons
= RING_CMP(tmp_raw_cons
);
1094 rxcmp1
= (struct rx_cmp_ext
*)
1095 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
1097 if (!RX_CMP_VALID(rxcmp1
, tmp_raw_cons
))
1100 cmp_type
= RX_CMP_TYPE(rxcmp
);
1102 prod
= rxr
->rx_prod
;
1104 if (cmp_type
== CMP_TYPE_RX_L2_TPA_START_CMP
) {
1105 bnxt_tpa_start(bp
, rxr
, (struct rx_tpa_start_cmp
*)rxcmp
,
1106 (struct rx_tpa_start_cmp_ext
*)rxcmp1
);
1108 goto next_rx_no_prod
;
1110 } else if (cmp_type
== CMP_TYPE_RX_L2_TPA_END_CMP
) {
1111 skb
= bnxt_tpa_end(bp
, bnapi
, &tmp_raw_cons
,
1112 (struct rx_tpa_end_cmp
*)rxcmp
,
1113 (struct rx_tpa_end_cmp_ext
*)rxcmp1
,
1116 if (unlikely(IS_ERR(skb
)))
1121 skb_record_rx_queue(skb
, bnapi
->index
);
1122 skb_mark_napi_id(skb
, &bnapi
->napi
);
1123 if (bnxt_busy_polling(bnapi
))
1124 netif_receive_skb(skb
);
1126 napi_gro_receive(&bnapi
->napi
, skb
);
1129 goto next_rx_no_prod
;
1132 cons
= rxcmp
->rx_cmp_opaque
;
1133 rx_buf
= &rxr
->rx_buf_ring
[cons
];
1134 data
= rx_buf
->data
;
1137 agg_bufs
= (le32_to_cpu(rxcmp
->rx_cmp_misc_v1
) & RX_CMP_AGG_BUFS
) >>
1138 RX_CMP_AGG_BUFS_SHIFT
;
1141 if (!bnxt_agg_bufs_valid(bp
, cpr
, agg_bufs
, &tmp_raw_cons
))
1144 cp_cons
= NEXT_CMP(cp_cons
);
1148 rx_buf
->data
= NULL
;
1149 if (rxcmp1
->rx_cmp_cfa_code_errors_v2
& RX_CMP_L2_ERRORS
) {
1150 bnxt_reuse_rx_data(rxr
, cons
, data
);
1152 bnxt_reuse_rx_agg_bufs(bnapi
, cp_cons
, agg_bufs
);
1158 len
= le32_to_cpu(rxcmp
->rx_cmp_len_flags_type
) >> RX_CMP_LEN_SHIFT
;
1159 dma_addr
= dma_unmap_addr(rx_buf
, mapping
);
1161 if (len
<= bp
->rx_copy_thresh
) {
1162 skb
= bnxt_copy_skb(bnapi
, data
, len
, dma_addr
);
1163 bnxt_reuse_rx_data(rxr
, cons
, data
);
1169 skb
= bnxt_rx_skb(bp
, rxr
, cons
, prod
, data
, dma_addr
, len
);
1177 skb
= bnxt_rx_pages(bp
, bnapi
, skb
, cp_cons
, agg_bufs
);
1184 if (RX_CMP_HASH_VALID(rxcmp
)) {
1185 u32 hash_type
= RX_CMP_HASH_TYPE(rxcmp
);
1186 enum pkt_hash_types type
= PKT_HASH_TYPE_L4
;
1188 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1189 if (hash_type
!= 1 && hash_type
!= 3)
1190 type
= PKT_HASH_TYPE_L3
;
1191 skb_set_hash(skb
, le32_to_cpu(rxcmp
->rx_cmp_rss_hash
), type
);
1194 skb
->protocol
= eth_type_trans(skb
, dev
);
1196 if (rxcmp1
->rx_cmp_flags2
&
1197 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN
)) {
1198 netdev_features_t features
= skb
->dev
->features
;
1199 u32 meta_data
= le32_to_cpu(rxcmp1
->rx_cmp_meta_data
);
1200 u16 vlan_proto
= meta_data
>> RX_CMP_FLAGS2_METADATA_TPID_SFT
;
1202 if (((features
& NETIF_F_HW_VLAN_CTAG_RX
) &&
1203 vlan_proto
== ETH_P_8021Q
) ||
1204 ((features
& NETIF_F_HW_VLAN_STAG_RX
) &&
1205 vlan_proto
== ETH_P_8021AD
))
1206 __vlan_hwaccel_put_tag(skb
, htons(vlan_proto
),
1208 RX_CMP_FLAGS2_METADATA_VID_MASK
);
1211 skb_checksum_none_assert(skb
);
1212 if (RX_CMP_L4_CS_OK(rxcmp1
)) {
1213 if (dev
->features
& NETIF_F_RXCSUM
) {
1214 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1215 skb
->csum_level
= RX_CMP_ENCAP(rxcmp1
);
1218 if (rxcmp1
->rx_cmp_cfa_code_errors_v2
& RX_CMP_L4_CS_ERR_BITS
) {
1219 if (dev
->features
& NETIF_F_RXCSUM
)
1220 cpr
->rx_l4_csum_errors
++;
1224 skb_record_rx_queue(skb
, bnapi
->index
);
1225 skb_mark_napi_id(skb
, &bnapi
->napi
);
1226 if (bnxt_busy_polling(bnapi
))
1227 netif_receive_skb(skb
);
1229 napi_gro_receive(&bnapi
->napi
, skb
);
1233 rxr
->rx_prod
= NEXT_RX(prod
);
1236 *raw_cons
= tmp_raw_cons
;
1241 #define BNXT_GET_EVENT_PORT(data) \
1243 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
1245 #define BNXT_EVENT_POLICY_MASK \
1246 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK
1248 #define BNXT_EVENT_POLICY_SFT \
1249 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT
1251 #define BNXT_GET_EVENT_POLICY(data) \
1252 (((data) & BNXT_EVENT_POLICY_MASK) >> BNXT_EVENT_POLICY_SFT)
1254 static int bnxt_async_event_process(struct bnxt
*bp
,
1255 struct hwrm_async_event_cmpl
*cmpl
)
1257 u16 event_id
= le16_to_cpu(cmpl
->event_id
);
1259 /* TODO CHIMP_FW: Define event id's for link change, error etc */
1261 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE
: {
1262 u32 data1
= le32_to_cpu(cmpl
->event_data1
);
1263 struct bnxt_link_info
*link_info
= &bp
->link_info
;
1266 goto async_event_process_exit
;
1267 if (data1
& 0x20000) {
1268 u16 fw_speed
= link_info
->force_link_speed
;
1269 u32 speed
= bnxt_fw_to_ethtool_speed(fw_speed
);
1271 netdev_warn(bp
->dev
, "Link speed %d no longer supported\n",
1276 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE
:
1277 set_bit(BNXT_LINK_CHNG_SP_EVENT
, &bp
->sp_event
);
1279 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD
:
1280 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT
, &bp
->sp_event
);
1282 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED
: {
1283 u32 data1
= le32_to_cpu(cmpl
->event_data1
);
1284 u16 port_id
= BNXT_GET_EVENT_PORT(data1
);
1289 if (bp
->pf
.port_id
!= port_id
)
1292 bp
->link_info
.last_port_module_event
=
1293 BNXT_GET_EVENT_POLICY(data1
);
1295 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT
, &bp
->sp_event
);
1299 netdev_err(bp
->dev
, "unhandled ASYNC event (id 0x%x)\n",
1301 goto async_event_process_exit
;
1303 schedule_work(&bp
->sp_task
);
1304 async_event_process_exit
:
1308 static int bnxt_hwrm_handler(struct bnxt
*bp
, struct tx_cmp
*txcmp
)
1310 u16 cmpl_type
= TX_CMP_TYPE(txcmp
), vf_id
, seq_id
;
1311 struct hwrm_cmpl
*h_cmpl
= (struct hwrm_cmpl
*)txcmp
;
1312 struct hwrm_fwd_req_cmpl
*fwd_req_cmpl
=
1313 (struct hwrm_fwd_req_cmpl
*)txcmp
;
1315 switch (cmpl_type
) {
1316 case CMPL_BASE_TYPE_HWRM_DONE
:
1317 seq_id
= le16_to_cpu(h_cmpl
->sequence_id
);
1318 if (seq_id
== bp
->hwrm_intr_seq_id
)
1319 bp
->hwrm_intr_seq_id
= HWRM_SEQ_ID_INVALID
;
1321 netdev_err(bp
->dev
, "Invalid hwrm seq id %d\n", seq_id
);
1324 case CMPL_BASE_TYPE_HWRM_FWD_REQ
:
1325 vf_id
= le16_to_cpu(fwd_req_cmpl
->source_id
);
1327 if ((vf_id
< bp
->pf
.first_vf_id
) ||
1328 (vf_id
>= bp
->pf
.first_vf_id
+ bp
->pf
.active_vfs
)) {
1329 netdev_err(bp
->dev
, "Msg contains invalid VF id %x\n",
1334 set_bit(vf_id
- bp
->pf
.first_vf_id
, bp
->pf
.vf_event_bmap
);
1335 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT
, &bp
->sp_event
);
1336 schedule_work(&bp
->sp_task
);
1339 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT
:
1340 bnxt_async_event_process(bp
,
1341 (struct hwrm_async_event_cmpl
*)txcmp
);
1350 static irqreturn_t
bnxt_msix(int irq
, void *dev_instance
)
1352 struct bnxt_napi
*bnapi
= dev_instance
;
1353 struct bnxt
*bp
= bnapi
->bp
;
1354 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1355 u32 cons
= RING_CMP(cpr
->cp_raw_cons
);
1357 prefetch(&cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)]);
1358 napi_schedule(&bnapi
->napi
);
1362 static inline int bnxt_has_work(struct bnxt
*bp
, struct bnxt_cp_ring_info
*cpr
)
1364 u32 raw_cons
= cpr
->cp_raw_cons
;
1365 u16 cons
= RING_CMP(raw_cons
);
1366 struct tx_cmp
*txcmp
;
1368 txcmp
= &cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)];
1370 return TX_CMP_VALID(txcmp
, raw_cons
);
1373 static irqreturn_t
bnxt_inta(int irq
, void *dev_instance
)
1375 struct bnxt_napi
*bnapi
= dev_instance
;
1376 struct bnxt
*bp
= bnapi
->bp
;
1377 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1378 u32 cons
= RING_CMP(cpr
->cp_raw_cons
);
1381 prefetch(&cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)]);
1383 if (!bnxt_has_work(bp
, cpr
)) {
1384 int_status
= readl(bp
->bar0
+ BNXT_CAG_REG_LEGACY_INT_STATUS
);
1385 /* return if erroneous interrupt */
1386 if (!(int_status
& (0x10000 << cpr
->cp_ring_struct
.fw_ring_id
)))
1390 /* disable ring IRQ */
1391 BNXT_CP_DB_IRQ_DIS(cpr
->cp_doorbell
);
1393 /* Return here if interrupt is shared and is disabled. */
1394 if (unlikely(atomic_read(&bp
->intr_sem
) != 0))
1397 napi_schedule(&bnapi
->napi
);
1401 static int bnxt_poll_work(struct bnxt
*bp
, struct bnxt_napi
*bnapi
, int budget
)
1403 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1404 u32 raw_cons
= cpr
->cp_raw_cons
;
1408 bool rx_event
= false;
1409 bool agg_event
= false;
1410 struct tx_cmp
*txcmp
;
1415 cons
= RING_CMP(raw_cons
);
1416 txcmp
= &cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)];
1418 if (!TX_CMP_VALID(txcmp
, raw_cons
))
1421 if (TX_CMP_TYPE(txcmp
) == CMP_TYPE_TX_L2_CMP
) {
1423 /* return full budget so NAPI will complete. */
1424 if (unlikely(tx_pkts
> bp
->tx_wake_thresh
))
1426 } else if ((TX_CMP_TYPE(txcmp
) & 0x30) == 0x10) {
1427 rc
= bnxt_rx_pkt(bp
, bnapi
, &raw_cons
, &agg_event
);
1428 if (likely(rc
>= 0))
1430 else if (rc
== -EBUSY
) /* partial completion */
1433 } else if (unlikely((TX_CMP_TYPE(txcmp
) ==
1434 CMPL_BASE_TYPE_HWRM_DONE
) ||
1435 (TX_CMP_TYPE(txcmp
) ==
1436 CMPL_BASE_TYPE_HWRM_FWD_REQ
) ||
1437 (TX_CMP_TYPE(txcmp
) ==
1438 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT
))) {
1439 bnxt_hwrm_handler(bp
, txcmp
);
1441 raw_cons
= NEXT_RAW_CMP(raw_cons
);
1443 if (rx_pkts
== budget
)
1447 cpr
->cp_raw_cons
= raw_cons
;
1448 /* ACK completion ring before freeing tx ring and producing new
1449 * buffers in rx/agg rings to prevent overflowing the completion
1452 BNXT_CP_DB(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
1455 bnxt_tx_int(bp
, bnapi
, tx_pkts
);
1458 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
1460 writel(DB_KEY_RX
| rxr
->rx_prod
, rxr
->rx_doorbell
);
1461 writel(DB_KEY_RX
| rxr
->rx_prod
, rxr
->rx_doorbell
);
1463 writel(DB_KEY_RX
| rxr
->rx_agg_prod
,
1464 rxr
->rx_agg_doorbell
);
1465 writel(DB_KEY_RX
| rxr
->rx_agg_prod
,
1466 rxr
->rx_agg_doorbell
);
1472 static int bnxt_poll(struct napi_struct
*napi
, int budget
)
1474 struct bnxt_napi
*bnapi
= container_of(napi
, struct bnxt_napi
, napi
);
1475 struct bnxt
*bp
= bnapi
->bp
;
1476 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1479 if (!bnxt_lock_napi(bnapi
))
1483 work_done
+= bnxt_poll_work(bp
, bnapi
, budget
- work_done
);
1485 if (work_done
>= budget
)
1488 if (!bnxt_has_work(bp
, cpr
)) {
1489 napi_complete(napi
);
1490 BNXT_CP_DB_REARM(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
1495 bnxt_unlock_napi(bnapi
);
1499 #ifdef CONFIG_NET_RX_BUSY_POLL
1500 static int bnxt_busy_poll(struct napi_struct
*napi
)
1502 struct bnxt_napi
*bnapi
= container_of(napi
, struct bnxt_napi
, napi
);
1503 struct bnxt
*bp
= bnapi
->bp
;
1504 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1505 int rx_work
, budget
= 4;
1507 if (atomic_read(&bp
->intr_sem
) != 0)
1508 return LL_FLUSH_FAILED
;
1510 if (!bnxt_lock_poll(bnapi
))
1511 return LL_FLUSH_BUSY
;
1513 rx_work
= bnxt_poll_work(bp
, bnapi
, budget
);
1515 BNXT_CP_DB_REARM(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
1517 bnxt_unlock_poll(bnapi
);
1522 static void bnxt_free_tx_skbs(struct bnxt
*bp
)
1525 struct pci_dev
*pdev
= bp
->pdev
;
1530 max_idx
= bp
->tx_nr_pages
* TX_DESC_CNT
;
1531 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
1532 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
1535 for (j
= 0; j
< max_idx
;) {
1536 struct bnxt_sw_tx_bd
*tx_buf
= &txr
->tx_buf_ring
[j
];
1537 struct sk_buff
*skb
= tx_buf
->skb
;
1547 if (tx_buf
->is_push
) {
1553 dma_unmap_single(&pdev
->dev
,
1554 dma_unmap_addr(tx_buf
, mapping
),
1558 last
= tx_buf
->nr_frags
;
1560 for (k
= 0; k
< last
; k
++, j
++) {
1561 int ring_idx
= j
& bp
->tx_ring_mask
;
1562 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[k
];
1564 tx_buf
= &txr
->tx_buf_ring
[ring_idx
];
1567 dma_unmap_addr(tx_buf
, mapping
),
1568 skb_frag_size(frag
), PCI_DMA_TODEVICE
);
1572 netdev_tx_reset_queue(netdev_get_tx_queue(bp
->dev
, i
));
1576 static void bnxt_free_rx_skbs(struct bnxt
*bp
)
1578 int i
, max_idx
, max_agg_idx
;
1579 struct pci_dev
*pdev
= bp
->pdev
;
1584 max_idx
= bp
->rx_nr_pages
* RX_DESC_CNT
;
1585 max_agg_idx
= bp
->rx_agg_nr_pages
* RX_DESC_CNT
;
1586 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
1587 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
1591 for (j
= 0; j
< MAX_TPA
; j
++) {
1592 struct bnxt_tpa_info
*tpa_info
=
1594 u8
*data
= tpa_info
->data
;
1601 dma_unmap_addr(tpa_info
, mapping
),
1602 bp
->rx_buf_use_size
,
1603 PCI_DMA_FROMDEVICE
);
1605 tpa_info
->data
= NULL
;
1611 for (j
= 0; j
< max_idx
; j
++) {
1612 struct bnxt_sw_rx_bd
*rx_buf
= &rxr
->rx_buf_ring
[j
];
1613 u8
*data
= rx_buf
->data
;
1618 dma_unmap_single(&pdev
->dev
,
1619 dma_unmap_addr(rx_buf
, mapping
),
1620 bp
->rx_buf_use_size
,
1621 PCI_DMA_FROMDEVICE
);
1623 rx_buf
->data
= NULL
;
1628 for (j
= 0; j
< max_agg_idx
; j
++) {
1629 struct bnxt_sw_rx_agg_bd
*rx_agg_buf
=
1630 &rxr
->rx_agg_ring
[j
];
1631 struct page
*page
= rx_agg_buf
->page
;
1636 dma_unmap_page(&pdev
->dev
,
1637 dma_unmap_addr(rx_agg_buf
, mapping
),
1638 PAGE_SIZE
, PCI_DMA_FROMDEVICE
);
1640 rx_agg_buf
->page
= NULL
;
1641 __clear_bit(j
, rxr
->rx_agg_bmap
);
1648 static void bnxt_free_skbs(struct bnxt
*bp
)
1650 bnxt_free_tx_skbs(bp
);
1651 bnxt_free_rx_skbs(bp
);
1654 static void bnxt_free_ring(struct bnxt
*bp
, struct bnxt_ring_struct
*ring
)
1656 struct pci_dev
*pdev
= bp
->pdev
;
1659 for (i
= 0; i
< ring
->nr_pages
; i
++) {
1660 if (!ring
->pg_arr
[i
])
1663 dma_free_coherent(&pdev
->dev
, ring
->page_size
,
1664 ring
->pg_arr
[i
], ring
->dma_arr
[i
]);
1666 ring
->pg_arr
[i
] = NULL
;
1669 dma_free_coherent(&pdev
->dev
, ring
->nr_pages
* 8,
1670 ring
->pg_tbl
, ring
->pg_tbl_map
);
1671 ring
->pg_tbl
= NULL
;
1673 if (ring
->vmem_size
&& *ring
->vmem
) {
1679 static int bnxt_alloc_ring(struct bnxt
*bp
, struct bnxt_ring_struct
*ring
)
1682 struct pci_dev
*pdev
= bp
->pdev
;
1684 if (ring
->nr_pages
> 1) {
1685 ring
->pg_tbl
= dma_alloc_coherent(&pdev
->dev
,
1693 for (i
= 0; i
< ring
->nr_pages
; i
++) {
1694 ring
->pg_arr
[i
] = dma_alloc_coherent(&pdev
->dev
,
1698 if (!ring
->pg_arr
[i
])
1701 if (ring
->nr_pages
> 1)
1702 ring
->pg_tbl
[i
] = cpu_to_le64(ring
->dma_arr
[i
]);
1705 if (ring
->vmem_size
) {
1706 *ring
->vmem
= vzalloc(ring
->vmem_size
);
1713 static void bnxt_free_rx_rings(struct bnxt
*bp
)
1720 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
1721 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
1722 struct bnxt_ring_struct
*ring
;
1727 kfree(rxr
->rx_agg_bmap
);
1728 rxr
->rx_agg_bmap
= NULL
;
1730 ring
= &rxr
->rx_ring_struct
;
1731 bnxt_free_ring(bp
, ring
);
1733 ring
= &rxr
->rx_agg_ring_struct
;
1734 bnxt_free_ring(bp
, ring
);
1738 static int bnxt_alloc_rx_rings(struct bnxt
*bp
)
1740 int i
, rc
, agg_rings
= 0, tpa_rings
= 0;
1745 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
)
1748 if (bp
->flags
& BNXT_FLAG_TPA
)
1751 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
1752 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
1753 struct bnxt_ring_struct
*ring
;
1755 ring
= &rxr
->rx_ring_struct
;
1757 rc
= bnxt_alloc_ring(bp
, ring
);
1764 ring
= &rxr
->rx_agg_ring_struct
;
1765 rc
= bnxt_alloc_ring(bp
, ring
);
1769 rxr
->rx_agg_bmap_size
= bp
->rx_agg_ring_mask
+ 1;
1770 mem_size
= rxr
->rx_agg_bmap_size
/ 8;
1771 rxr
->rx_agg_bmap
= kzalloc(mem_size
, GFP_KERNEL
);
1772 if (!rxr
->rx_agg_bmap
)
1776 rxr
->rx_tpa
= kcalloc(MAX_TPA
,
1777 sizeof(struct bnxt_tpa_info
),
1787 static void bnxt_free_tx_rings(struct bnxt
*bp
)
1790 struct pci_dev
*pdev
= bp
->pdev
;
1795 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
1796 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
1797 struct bnxt_ring_struct
*ring
;
1800 dma_free_coherent(&pdev
->dev
, bp
->tx_push_size
,
1801 txr
->tx_push
, txr
->tx_push_mapping
);
1802 txr
->tx_push
= NULL
;
1805 ring
= &txr
->tx_ring_struct
;
1807 bnxt_free_ring(bp
, ring
);
1811 static int bnxt_alloc_tx_rings(struct bnxt
*bp
)
1814 struct pci_dev
*pdev
= bp
->pdev
;
1816 bp
->tx_push_size
= 0;
1817 if (bp
->tx_push_thresh
) {
1820 push_size
= L1_CACHE_ALIGN(sizeof(struct tx_push_bd
) +
1821 bp
->tx_push_thresh
);
1823 if (push_size
> 256) {
1825 bp
->tx_push_thresh
= 0;
1828 bp
->tx_push_size
= push_size
;
1831 for (i
= 0, j
= 0; i
< bp
->tx_nr_rings
; i
++) {
1832 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
1833 struct bnxt_ring_struct
*ring
;
1835 ring
= &txr
->tx_ring_struct
;
1837 rc
= bnxt_alloc_ring(bp
, ring
);
1841 if (bp
->tx_push_size
) {
1844 /* One pre-allocated DMA buffer to backup
1847 txr
->tx_push
= dma_alloc_coherent(&pdev
->dev
,
1849 &txr
->tx_push_mapping
,
1855 mapping
= txr
->tx_push_mapping
+
1856 sizeof(struct tx_push_bd
);
1857 txr
->data_mapping
= cpu_to_le64(mapping
);
1859 memset(txr
->tx_push
, 0, sizeof(struct tx_push_bd
));
1861 ring
->queue_id
= bp
->q_info
[j
].queue_id
;
1862 if (i
% bp
->tx_nr_rings_per_tc
== (bp
->tx_nr_rings_per_tc
- 1))
1868 static void bnxt_free_cp_rings(struct bnxt
*bp
)
1875 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
1876 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
1877 struct bnxt_cp_ring_info
*cpr
;
1878 struct bnxt_ring_struct
*ring
;
1883 cpr
= &bnapi
->cp_ring
;
1884 ring
= &cpr
->cp_ring_struct
;
1886 bnxt_free_ring(bp
, ring
);
1890 static int bnxt_alloc_cp_rings(struct bnxt
*bp
)
1894 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
1895 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
1896 struct bnxt_cp_ring_info
*cpr
;
1897 struct bnxt_ring_struct
*ring
;
1902 cpr
= &bnapi
->cp_ring
;
1903 ring
= &cpr
->cp_ring_struct
;
1905 rc
= bnxt_alloc_ring(bp
, ring
);
1912 static void bnxt_init_ring_struct(struct bnxt
*bp
)
1916 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
1917 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
1918 struct bnxt_cp_ring_info
*cpr
;
1919 struct bnxt_rx_ring_info
*rxr
;
1920 struct bnxt_tx_ring_info
*txr
;
1921 struct bnxt_ring_struct
*ring
;
1926 cpr
= &bnapi
->cp_ring
;
1927 ring
= &cpr
->cp_ring_struct
;
1928 ring
->nr_pages
= bp
->cp_nr_pages
;
1929 ring
->page_size
= HW_CMPD_RING_SIZE
;
1930 ring
->pg_arr
= (void **)cpr
->cp_desc_ring
;
1931 ring
->dma_arr
= cpr
->cp_desc_mapping
;
1932 ring
->vmem_size
= 0;
1934 rxr
= bnapi
->rx_ring
;
1938 ring
= &rxr
->rx_ring_struct
;
1939 ring
->nr_pages
= bp
->rx_nr_pages
;
1940 ring
->page_size
= HW_RXBD_RING_SIZE
;
1941 ring
->pg_arr
= (void **)rxr
->rx_desc_ring
;
1942 ring
->dma_arr
= rxr
->rx_desc_mapping
;
1943 ring
->vmem_size
= SW_RXBD_RING_SIZE
* bp
->rx_nr_pages
;
1944 ring
->vmem
= (void **)&rxr
->rx_buf_ring
;
1946 ring
= &rxr
->rx_agg_ring_struct
;
1947 ring
->nr_pages
= bp
->rx_agg_nr_pages
;
1948 ring
->page_size
= HW_RXBD_RING_SIZE
;
1949 ring
->pg_arr
= (void **)rxr
->rx_agg_desc_ring
;
1950 ring
->dma_arr
= rxr
->rx_agg_desc_mapping
;
1951 ring
->vmem_size
= SW_RXBD_AGG_RING_SIZE
* bp
->rx_agg_nr_pages
;
1952 ring
->vmem
= (void **)&rxr
->rx_agg_ring
;
1955 txr
= bnapi
->tx_ring
;
1959 ring
= &txr
->tx_ring_struct
;
1960 ring
->nr_pages
= bp
->tx_nr_pages
;
1961 ring
->page_size
= HW_RXBD_RING_SIZE
;
1962 ring
->pg_arr
= (void **)txr
->tx_desc_ring
;
1963 ring
->dma_arr
= txr
->tx_desc_mapping
;
1964 ring
->vmem_size
= SW_TXBD_RING_SIZE
* bp
->tx_nr_pages
;
1965 ring
->vmem
= (void **)&txr
->tx_buf_ring
;
1969 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct
*ring
, u32 type
)
1973 struct rx_bd
**rx_buf_ring
;
1975 rx_buf_ring
= (struct rx_bd
**)ring
->pg_arr
;
1976 for (i
= 0, prod
= 0; i
< ring
->nr_pages
; i
++) {
1980 rxbd
= rx_buf_ring
[i
];
1984 for (j
= 0; j
< RX_DESC_CNT
; j
++, rxbd
++, prod
++) {
1985 rxbd
->rx_bd_len_flags_type
= cpu_to_le32(type
);
1986 rxbd
->rx_bd_opaque
= prod
;
1991 static int bnxt_init_one_rx_ring(struct bnxt
*bp
, int ring_nr
)
1993 struct net_device
*dev
= bp
->dev
;
1994 struct bnxt_rx_ring_info
*rxr
;
1995 struct bnxt_ring_struct
*ring
;
1999 type
= (bp
->rx_buf_use_size
<< RX_BD_LEN_SHIFT
) |
2000 RX_BD_TYPE_RX_PACKET_BD
| RX_BD_FLAGS_EOP
;
2002 if (NET_IP_ALIGN
== 2)
2003 type
|= RX_BD_FLAGS_SOP
;
2005 rxr
= &bp
->rx_ring
[ring_nr
];
2006 ring
= &rxr
->rx_ring_struct
;
2007 bnxt_init_rxbd_pages(ring
, type
);
2009 prod
= rxr
->rx_prod
;
2010 for (i
= 0; i
< bp
->rx_ring_size
; i
++) {
2011 if (bnxt_alloc_rx_data(bp
, rxr
, prod
, GFP_KERNEL
) != 0) {
2012 netdev_warn(dev
, "init'ed rx ring %d with %d/%d skbs only\n",
2013 ring_nr
, i
, bp
->rx_ring_size
);
2016 prod
= NEXT_RX(prod
);
2018 rxr
->rx_prod
= prod
;
2019 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
2021 ring
= &rxr
->rx_agg_ring_struct
;
2022 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
2024 if (!(bp
->flags
& BNXT_FLAG_AGG_RINGS
))
2027 type
= ((u32
)PAGE_SIZE
<< RX_BD_LEN_SHIFT
) |
2028 RX_BD_TYPE_RX_AGG_BD
| RX_BD_FLAGS_SOP
;
2030 bnxt_init_rxbd_pages(ring
, type
);
2032 prod
= rxr
->rx_agg_prod
;
2033 for (i
= 0; i
< bp
->rx_agg_ring_size
; i
++) {
2034 if (bnxt_alloc_rx_page(bp
, rxr
, prod
, GFP_KERNEL
) != 0) {
2035 netdev_warn(dev
, "init'ed rx ring %d with %d/%d pages only\n",
2036 ring_nr
, i
, bp
->rx_ring_size
);
2039 prod
= NEXT_RX_AGG(prod
);
2041 rxr
->rx_agg_prod
= prod
;
2043 if (bp
->flags
& BNXT_FLAG_TPA
) {
2048 for (i
= 0; i
< MAX_TPA
; i
++) {
2049 data
= __bnxt_alloc_rx_data(bp
, &mapping
,
2054 rxr
->rx_tpa
[i
].data
= data
;
2055 rxr
->rx_tpa
[i
].mapping
= mapping
;
2058 netdev_err(bp
->dev
, "No resource allocated for LRO/GRO\n");
2066 static int bnxt_init_rx_rings(struct bnxt
*bp
)
2070 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
2071 rc
= bnxt_init_one_rx_ring(bp
, i
);
2079 static int bnxt_init_tx_rings(struct bnxt
*bp
)
2083 bp
->tx_wake_thresh
= max_t(int, bp
->tx_ring_size
/ 2,
2086 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
2087 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
2088 struct bnxt_ring_struct
*ring
= &txr
->tx_ring_struct
;
2090 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
2096 static void bnxt_free_ring_grps(struct bnxt
*bp
)
2098 kfree(bp
->grp_info
);
2099 bp
->grp_info
= NULL
;
2102 static int bnxt_init_ring_grps(struct bnxt
*bp
, bool irq_re_init
)
2107 bp
->grp_info
= kcalloc(bp
->cp_nr_rings
,
2108 sizeof(struct bnxt_ring_grp_info
),
2113 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2115 bp
->grp_info
[i
].fw_stats_ctx
= INVALID_HW_RING_ID
;
2116 bp
->grp_info
[i
].fw_grp_id
= INVALID_HW_RING_ID
;
2117 bp
->grp_info
[i
].rx_fw_ring_id
= INVALID_HW_RING_ID
;
2118 bp
->grp_info
[i
].agg_fw_ring_id
= INVALID_HW_RING_ID
;
2119 bp
->grp_info
[i
].cp_fw_ring_id
= INVALID_HW_RING_ID
;
2124 static void bnxt_free_vnics(struct bnxt
*bp
)
2126 kfree(bp
->vnic_info
);
2127 bp
->vnic_info
= NULL
;
2131 static int bnxt_alloc_vnics(struct bnxt
*bp
)
2135 #ifdef CONFIG_RFS_ACCEL
2136 if (bp
->flags
& BNXT_FLAG_RFS
)
2137 num_vnics
+= bp
->rx_nr_rings
;
2140 bp
->vnic_info
= kcalloc(num_vnics
, sizeof(struct bnxt_vnic_info
),
2145 bp
->nr_vnics
= num_vnics
;
2149 static void bnxt_init_vnics(struct bnxt
*bp
)
2153 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
2154 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[i
];
2156 vnic
->fw_vnic_id
= INVALID_HW_RING_ID
;
2157 vnic
->fw_rss_cos_lb_ctx
= INVALID_HW_RING_ID
;
2158 vnic
->fw_l2_ctx_id
= INVALID_HW_RING_ID
;
2160 if (bp
->vnic_info
[i
].rss_hash_key
) {
2162 prandom_bytes(vnic
->rss_hash_key
,
2165 memcpy(vnic
->rss_hash_key
,
2166 bp
->vnic_info
[0].rss_hash_key
,
2172 static int bnxt_calc_nr_ring_pages(u32 ring_size
, int desc_per_pg
)
2176 pages
= ring_size
/ desc_per_pg
;
2183 while (pages
& (pages
- 1))
2189 static void bnxt_set_tpa_flags(struct bnxt
*bp
)
2191 bp
->flags
&= ~BNXT_FLAG_TPA
;
2192 if (bp
->dev
->features
& NETIF_F_LRO
)
2193 bp
->flags
|= BNXT_FLAG_LRO
;
2194 if ((bp
->dev
->features
& NETIF_F_GRO
) && (bp
->pdev
->revision
> 0))
2195 bp
->flags
|= BNXT_FLAG_GRO
;
2198 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2201 void bnxt_set_ring_params(struct bnxt
*bp
)
2203 u32 ring_size
, rx_size
, rx_space
;
2204 u32 agg_factor
= 0, agg_ring_size
= 0;
2206 /* 8 for CRC and VLAN */
2207 rx_size
= SKB_DATA_ALIGN(bp
->dev
->mtu
+ ETH_HLEN
+ NET_IP_ALIGN
+ 8);
2209 rx_space
= rx_size
+ NET_SKB_PAD
+
2210 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
2212 bp
->rx_copy_thresh
= BNXT_RX_COPY_THRESH
;
2213 ring_size
= bp
->rx_ring_size
;
2214 bp
->rx_agg_ring_size
= 0;
2215 bp
->rx_agg_nr_pages
= 0;
2217 if (bp
->flags
& BNXT_FLAG_TPA
)
2220 bp
->flags
&= ~BNXT_FLAG_JUMBO
;
2221 if (rx_space
> PAGE_SIZE
) {
2224 bp
->flags
|= BNXT_FLAG_JUMBO
;
2225 jumbo_factor
= PAGE_ALIGN(bp
->dev
->mtu
- 40) >> PAGE_SHIFT
;
2226 if (jumbo_factor
> agg_factor
)
2227 agg_factor
= jumbo_factor
;
2229 agg_ring_size
= ring_size
* agg_factor
;
2231 if (agg_ring_size
) {
2232 bp
->rx_agg_nr_pages
= bnxt_calc_nr_ring_pages(agg_ring_size
,
2234 if (bp
->rx_agg_nr_pages
> MAX_RX_AGG_PAGES
) {
2235 u32 tmp
= agg_ring_size
;
2237 bp
->rx_agg_nr_pages
= MAX_RX_AGG_PAGES
;
2238 agg_ring_size
= MAX_RX_AGG_PAGES
* RX_DESC_CNT
- 1;
2239 netdev_warn(bp
->dev
, "rx agg ring size %d reduced to %d.\n",
2240 tmp
, agg_ring_size
);
2242 bp
->rx_agg_ring_size
= agg_ring_size
;
2243 bp
->rx_agg_ring_mask
= (bp
->rx_agg_nr_pages
* RX_DESC_CNT
) - 1;
2244 rx_size
= SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH
+ NET_IP_ALIGN
);
2245 rx_space
= rx_size
+ NET_SKB_PAD
+
2246 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
2249 bp
->rx_buf_use_size
= rx_size
;
2250 bp
->rx_buf_size
= rx_space
;
2252 bp
->rx_nr_pages
= bnxt_calc_nr_ring_pages(ring_size
, RX_DESC_CNT
);
2253 bp
->rx_ring_mask
= (bp
->rx_nr_pages
* RX_DESC_CNT
) - 1;
2255 ring_size
= bp
->tx_ring_size
;
2256 bp
->tx_nr_pages
= bnxt_calc_nr_ring_pages(ring_size
, TX_DESC_CNT
);
2257 bp
->tx_ring_mask
= (bp
->tx_nr_pages
* TX_DESC_CNT
) - 1;
2259 ring_size
= bp
->rx_ring_size
* (2 + agg_factor
) + bp
->tx_ring_size
;
2260 bp
->cp_ring_size
= ring_size
;
2262 bp
->cp_nr_pages
= bnxt_calc_nr_ring_pages(ring_size
, CP_DESC_CNT
);
2263 if (bp
->cp_nr_pages
> MAX_CP_PAGES
) {
2264 bp
->cp_nr_pages
= MAX_CP_PAGES
;
2265 bp
->cp_ring_size
= MAX_CP_PAGES
* CP_DESC_CNT
- 1;
2266 netdev_warn(bp
->dev
, "completion ring size %d reduced to %d.\n",
2267 ring_size
, bp
->cp_ring_size
);
2269 bp
->cp_bit
= bp
->cp_nr_pages
* CP_DESC_CNT
;
2270 bp
->cp_ring_mask
= bp
->cp_bit
- 1;
2273 static void bnxt_free_vnic_attributes(struct bnxt
*bp
)
2276 struct bnxt_vnic_info
*vnic
;
2277 struct pci_dev
*pdev
= bp
->pdev
;
2282 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
2283 vnic
= &bp
->vnic_info
[i
];
2285 kfree(vnic
->fw_grp_ids
);
2286 vnic
->fw_grp_ids
= NULL
;
2288 kfree(vnic
->uc_list
);
2289 vnic
->uc_list
= NULL
;
2291 if (vnic
->mc_list
) {
2292 dma_free_coherent(&pdev
->dev
, vnic
->mc_list_size
,
2293 vnic
->mc_list
, vnic
->mc_list_mapping
);
2294 vnic
->mc_list
= NULL
;
2297 if (vnic
->rss_table
) {
2298 dma_free_coherent(&pdev
->dev
, PAGE_SIZE
,
2300 vnic
->rss_table_dma_addr
);
2301 vnic
->rss_table
= NULL
;
2304 vnic
->rss_hash_key
= NULL
;
2309 static int bnxt_alloc_vnic_attributes(struct bnxt
*bp
)
2311 int i
, rc
= 0, size
;
2312 struct bnxt_vnic_info
*vnic
;
2313 struct pci_dev
*pdev
= bp
->pdev
;
2316 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
2317 vnic
= &bp
->vnic_info
[i
];
2319 if (vnic
->flags
& BNXT_VNIC_UCAST_FLAG
) {
2320 int mem_size
= (BNXT_MAX_UC_ADDRS
- 1) * ETH_ALEN
;
2323 vnic
->uc_list
= kmalloc(mem_size
, GFP_KERNEL
);
2324 if (!vnic
->uc_list
) {
2331 if (vnic
->flags
& BNXT_VNIC_MCAST_FLAG
) {
2332 vnic
->mc_list_size
= BNXT_MAX_MC_ADDRS
* ETH_ALEN
;
2334 dma_alloc_coherent(&pdev
->dev
,
2336 &vnic
->mc_list_mapping
,
2338 if (!vnic
->mc_list
) {
2344 if (vnic
->flags
& BNXT_VNIC_RSS_FLAG
)
2345 max_rings
= bp
->rx_nr_rings
;
2349 vnic
->fw_grp_ids
= kcalloc(max_rings
, sizeof(u16
), GFP_KERNEL
);
2350 if (!vnic
->fw_grp_ids
) {
2355 /* Allocate rss table and hash key */
2356 vnic
->rss_table
= dma_alloc_coherent(&pdev
->dev
, PAGE_SIZE
,
2357 &vnic
->rss_table_dma_addr
,
2359 if (!vnic
->rss_table
) {
2364 size
= L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE
* sizeof(u16
));
2366 vnic
->rss_hash_key
= ((void *)vnic
->rss_table
) + size
;
2367 vnic
->rss_hash_key_dma_addr
= vnic
->rss_table_dma_addr
+ size
;
2375 static void bnxt_free_hwrm_resources(struct bnxt
*bp
)
2377 struct pci_dev
*pdev
= bp
->pdev
;
2379 dma_free_coherent(&pdev
->dev
, PAGE_SIZE
, bp
->hwrm_cmd_resp_addr
,
2380 bp
->hwrm_cmd_resp_dma_addr
);
2382 bp
->hwrm_cmd_resp_addr
= NULL
;
2383 if (bp
->hwrm_dbg_resp_addr
) {
2384 dma_free_coherent(&pdev
->dev
, HWRM_DBG_REG_BUF_SIZE
,
2385 bp
->hwrm_dbg_resp_addr
,
2386 bp
->hwrm_dbg_resp_dma_addr
);
2388 bp
->hwrm_dbg_resp_addr
= NULL
;
2392 static int bnxt_alloc_hwrm_resources(struct bnxt
*bp
)
2394 struct pci_dev
*pdev
= bp
->pdev
;
2396 bp
->hwrm_cmd_resp_addr
= dma_alloc_coherent(&pdev
->dev
, PAGE_SIZE
,
2397 &bp
->hwrm_cmd_resp_dma_addr
,
2399 if (!bp
->hwrm_cmd_resp_addr
)
2401 bp
->hwrm_dbg_resp_addr
= dma_alloc_coherent(&pdev
->dev
,
2402 HWRM_DBG_REG_BUF_SIZE
,
2403 &bp
->hwrm_dbg_resp_dma_addr
,
2405 if (!bp
->hwrm_dbg_resp_addr
)
2406 netdev_warn(bp
->dev
, "fail to alloc debug register dma mem\n");
2411 static void bnxt_free_stats(struct bnxt
*bp
)
2414 struct pci_dev
*pdev
= bp
->pdev
;
2416 if (bp
->hw_rx_port_stats
) {
2417 dma_free_coherent(&pdev
->dev
, bp
->hw_port_stats_size
,
2418 bp
->hw_rx_port_stats
,
2419 bp
->hw_rx_port_stats_map
);
2420 bp
->hw_rx_port_stats
= NULL
;
2421 bp
->flags
&= ~BNXT_FLAG_PORT_STATS
;
2427 size
= sizeof(struct ctx_hw_stats
);
2429 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2430 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2431 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
2433 if (cpr
->hw_stats
) {
2434 dma_free_coherent(&pdev
->dev
, size
, cpr
->hw_stats
,
2436 cpr
->hw_stats
= NULL
;
2441 static int bnxt_alloc_stats(struct bnxt
*bp
)
2444 struct pci_dev
*pdev
= bp
->pdev
;
2446 size
= sizeof(struct ctx_hw_stats
);
2448 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2449 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2450 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
2452 cpr
->hw_stats
= dma_alloc_coherent(&pdev
->dev
, size
,
2458 cpr
->hw_stats_ctx_id
= INVALID_STATS_CTX_ID
;
2462 bp
->hw_port_stats_size
= sizeof(struct rx_port_stats
) +
2463 sizeof(struct tx_port_stats
) + 1024;
2465 bp
->hw_rx_port_stats
=
2466 dma_alloc_coherent(&pdev
->dev
, bp
->hw_port_stats_size
,
2467 &bp
->hw_rx_port_stats_map
,
2469 if (!bp
->hw_rx_port_stats
)
2472 bp
->hw_tx_port_stats
= (void *)(bp
->hw_rx_port_stats
+ 1) +
2474 bp
->hw_tx_port_stats_map
= bp
->hw_rx_port_stats_map
+
2475 sizeof(struct rx_port_stats
) + 512;
2476 bp
->flags
|= BNXT_FLAG_PORT_STATS
;
2481 static void bnxt_clear_ring_indices(struct bnxt
*bp
)
2488 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2489 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2490 struct bnxt_cp_ring_info
*cpr
;
2491 struct bnxt_rx_ring_info
*rxr
;
2492 struct bnxt_tx_ring_info
*txr
;
2497 cpr
= &bnapi
->cp_ring
;
2498 cpr
->cp_raw_cons
= 0;
2500 txr
= bnapi
->tx_ring
;
2506 rxr
= bnapi
->rx_ring
;
2509 rxr
->rx_agg_prod
= 0;
2510 rxr
->rx_sw_agg_prod
= 0;
2515 static void bnxt_free_ntp_fltrs(struct bnxt
*bp
, bool irq_reinit
)
2517 #ifdef CONFIG_RFS_ACCEL
2520 /* Under rtnl_lock and all our NAPIs have been disabled. It's
2521 * safe to delete the hash table.
2523 for (i
= 0; i
< BNXT_NTP_FLTR_HASH_SIZE
; i
++) {
2524 struct hlist_head
*head
;
2525 struct hlist_node
*tmp
;
2526 struct bnxt_ntuple_filter
*fltr
;
2528 head
= &bp
->ntp_fltr_hash_tbl
[i
];
2529 hlist_for_each_entry_safe(fltr
, tmp
, head
, hash
) {
2530 hlist_del(&fltr
->hash
);
2535 kfree(bp
->ntp_fltr_bmap
);
2536 bp
->ntp_fltr_bmap
= NULL
;
2538 bp
->ntp_fltr_count
= 0;
2542 static int bnxt_alloc_ntp_fltrs(struct bnxt
*bp
)
2544 #ifdef CONFIG_RFS_ACCEL
2547 if (!(bp
->flags
& BNXT_FLAG_RFS
))
2550 for (i
= 0; i
< BNXT_NTP_FLTR_HASH_SIZE
; i
++)
2551 INIT_HLIST_HEAD(&bp
->ntp_fltr_hash_tbl
[i
]);
2553 bp
->ntp_fltr_count
= 0;
2554 bp
->ntp_fltr_bmap
= kzalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR
),
2557 if (!bp
->ntp_fltr_bmap
)
2566 static void bnxt_free_mem(struct bnxt
*bp
, bool irq_re_init
)
2568 bnxt_free_vnic_attributes(bp
);
2569 bnxt_free_tx_rings(bp
);
2570 bnxt_free_rx_rings(bp
);
2571 bnxt_free_cp_rings(bp
);
2572 bnxt_free_ntp_fltrs(bp
, irq_re_init
);
2574 bnxt_free_stats(bp
);
2575 bnxt_free_ring_grps(bp
);
2576 bnxt_free_vnics(bp
);
2584 bnxt_clear_ring_indices(bp
);
2588 static int bnxt_alloc_mem(struct bnxt
*bp
, bool irq_re_init
)
2590 int i
, j
, rc
, size
, arr_size
;
2594 /* Allocate bnapi mem pointer array and mem block for
2597 arr_size
= L1_CACHE_ALIGN(sizeof(struct bnxt_napi
*) *
2599 size
= L1_CACHE_ALIGN(sizeof(struct bnxt_napi
));
2600 bnapi
= kzalloc(arr_size
+ size
* bp
->cp_nr_rings
, GFP_KERNEL
);
2606 for (i
= 0; i
< bp
->cp_nr_rings
; i
++, bnapi
+= size
) {
2607 bp
->bnapi
[i
] = bnapi
;
2608 bp
->bnapi
[i
]->index
= i
;
2609 bp
->bnapi
[i
]->bp
= bp
;
2612 bp
->rx_ring
= kcalloc(bp
->rx_nr_rings
,
2613 sizeof(struct bnxt_rx_ring_info
),
2618 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
2619 bp
->rx_ring
[i
].bnapi
= bp
->bnapi
[i
];
2620 bp
->bnapi
[i
]->rx_ring
= &bp
->rx_ring
[i
];
2623 bp
->tx_ring
= kcalloc(bp
->tx_nr_rings
,
2624 sizeof(struct bnxt_tx_ring_info
),
2629 if (bp
->flags
& BNXT_FLAG_SHARED_RINGS
)
2632 j
= bp
->rx_nr_rings
;
2634 for (i
= 0; i
< bp
->tx_nr_rings
; i
++, j
++) {
2635 bp
->tx_ring
[i
].bnapi
= bp
->bnapi
[j
];
2636 bp
->bnapi
[j
]->tx_ring
= &bp
->tx_ring
[i
];
2639 rc
= bnxt_alloc_stats(bp
);
2643 rc
= bnxt_alloc_ntp_fltrs(bp
);
2647 rc
= bnxt_alloc_vnics(bp
);
2652 bnxt_init_ring_struct(bp
);
2654 rc
= bnxt_alloc_rx_rings(bp
);
2658 rc
= bnxt_alloc_tx_rings(bp
);
2662 rc
= bnxt_alloc_cp_rings(bp
);
2666 bp
->vnic_info
[0].flags
|= BNXT_VNIC_RSS_FLAG
| BNXT_VNIC_MCAST_FLAG
|
2667 BNXT_VNIC_UCAST_FLAG
;
2668 rc
= bnxt_alloc_vnic_attributes(bp
);
2674 bnxt_free_mem(bp
, true);
2678 void bnxt_hwrm_cmd_hdr_init(struct bnxt
*bp
, void *request
, u16 req_type
,
2679 u16 cmpl_ring
, u16 target_id
)
2681 struct input
*req
= request
;
2683 req
->req_type
= cpu_to_le16(req_type
);
2684 req
->cmpl_ring
= cpu_to_le16(cmpl_ring
);
2685 req
->target_id
= cpu_to_le16(target_id
);
2686 req
->resp_addr
= cpu_to_le64(bp
->hwrm_cmd_resp_dma_addr
);
2689 static int bnxt_hwrm_do_send_msg(struct bnxt
*bp
, void *msg
, u32 msg_len
,
2690 int timeout
, bool silent
)
2692 int i
, intr_process
, rc
;
2693 struct input
*req
= msg
;
2695 __le32
*resp_len
, *valid
;
2696 u16 cp_ring_id
, len
= 0;
2697 struct hwrm_err_output
*resp
= bp
->hwrm_cmd_resp_addr
;
2699 req
->seq_id
= cpu_to_le16(bp
->hwrm_cmd_seq
++);
2700 memset(resp
, 0, PAGE_SIZE
);
2701 cp_ring_id
= le16_to_cpu(req
->cmpl_ring
);
2702 intr_process
= (cp_ring_id
== INVALID_HW_RING_ID
) ? 0 : 1;
2704 /* Write request msg to hwrm channel */
2705 __iowrite32_copy(bp
->bar0
, data
, msg_len
/ 4);
2707 for (i
= msg_len
; i
< BNXT_HWRM_MAX_REQ_LEN
; i
+= 4)
2708 writel(0, bp
->bar0
+ i
);
2710 /* currently supports only one outstanding message */
2712 bp
->hwrm_intr_seq_id
= le16_to_cpu(req
->seq_id
);
2714 /* Ring channel doorbell */
2715 writel(1, bp
->bar0
+ 0x100);
2718 timeout
= DFLT_HWRM_CMD_TIMEOUT
;
2722 /* Wait until hwrm response cmpl interrupt is processed */
2723 while (bp
->hwrm_intr_seq_id
!= HWRM_SEQ_ID_INVALID
&&
2725 usleep_range(600, 800);
2728 if (bp
->hwrm_intr_seq_id
!= HWRM_SEQ_ID_INVALID
) {
2729 netdev_err(bp
->dev
, "Resp cmpl intr err msg: 0x%x\n",
2730 le16_to_cpu(req
->req_type
));
2734 /* Check if response len is updated */
2735 resp_len
= bp
->hwrm_cmd_resp_addr
+ HWRM_RESP_LEN_OFFSET
;
2736 for (i
= 0; i
< timeout
; i
++) {
2737 len
= (le32_to_cpu(*resp_len
) & HWRM_RESP_LEN_MASK
) >>
2741 usleep_range(600, 800);
2745 netdev_err(bp
->dev
, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
2746 timeout
, le16_to_cpu(req
->req_type
),
2747 le16_to_cpu(req
->seq_id
), *resp_len
);
2751 /* Last word of resp contains valid bit */
2752 valid
= bp
->hwrm_cmd_resp_addr
+ len
- 4;
2753 for (i
= 0; i
< timeout
; i
++) {
2754 if (le32_to_cpu(*valid
) & HWRM_RESP_VALID_MASK
)
2756 usleep_range(600, 800);
2760 netdev_err(bp
->dev
, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
2761 timeout
, le16_to_cpu(req
->req_type
),
2762 le16_to_cpu(req
->seq_id
), len
, *valid
);
2767 rc
= le16_to_cpu(resp
->error_code
);
2769 netdev_err(bp
->dev
, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
2770 le16_to_cpu(resp
->req_type
),
2771 le16_to_cpu(resp
->seq_id
), rc
);
2775 int _hwrm_send_message(struct bnxt
*bp
, void *msg
, u32 msg_len
, int timeout
)
2777 return bnxt_hwrm_do_send_msg(bp
, msg
, msg_len
, timeout
, false);
2780 int hwrm_send_message(struct bnxt
*bp
, void *msg
, u32 msg_len
, int timeout
)
2784 mutex_lock(&bp
->hwrm_cmd_lock
);
2785 rc
= _hwrm_send_message(bp
, msg
, msg_len
, timeout
);
2786 mutex_unlock(&bp
->hwrm_cmd_lock
);
2790 int hwrm_send_message_silent(struct bnxt
*bp
, void *msg
, u32 msg_len
,
2795 mutex_lock(&bp
->hwrm_cmd_lock
);
2796 rc
= bnxt_hwrm_do_send_msg(bp
, msg
, msg_len
, timeout
, true);
2797 mutex_unlock(&bp
->hwrm_cmd_lock
);
2801 static int bnxt_hwrm_func_drv_rgtr(struct bnxt
*bp
)
2803 struct hwrm_func_drv_rgtr_input req
= {0};
2805 DECLARE_BITMAP(async_events_bmap
, 256);
2806 u32
*events
= (u32
*)async_events_bmap
;
2808 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_DRV_RGTR
, -1, -1);
2811 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE
|
2812 FUNC_DRV_RGTR_REQ_ENABLES_VER
|
2813 FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD
);
2815 memset(async_events_bmap
, 0, sizeof(async_events_bmap
));
2816 for (i
= 0; i
< ARRAY_SIZE(bnxt_async_events_arr
); i
++)
2817 __set_bit(bnxt_async_events_arr
[i
], async_events_bmap
);
2819 for (i
= 0; i
< 8; i
++)
2820 req
.async_event_fwd
[i
] |= cpu_to_le32(events
[i
]);
2822 req
.os_type
= cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX
);
2823 req
.ver_maj
= DRV_VER_MAJ
;
2824 req
.ver_min
= DRV_VER_MIN
;
2825 req
.ver_upd
= DRV_VER_UPD
;
2828 DECLARE_BITMAP(vf_req_snif_bmap
, 256);
2829 u32
*data
= (u32
*)vf_req_snif_bmap
;
2831 memset(vf_req_snif_bmap
, 0, sizeof(vf_req_snif_bmap
));
2832 for (i
= 0; i
< ARRAY_SIZE(bnxt_vf_req_snif
); i
++)
2833 __set_bit(bnxt_vf_req_snif
[i
], vf_req_snif_bmap
);
2835 for (i
= 0; i
< 8; i
++)
2836 req
.vf_req_fwd
[i
] = cpu_to_le32(data
[i
]);
2839 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD
);
2842 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2845 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt
*bp
)
2847 struct hwrm_func_drv_unrgtr_input req
= {0};
2849 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_DRV_UNRGTR
, -1, -1);
2850 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2853 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt
*bp
, u8 tunnel_type
)
2856 struct hwrm_tunnel_dst_port_free_input req
= {0};
2858 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_TUNNEL_DST_PORT_FREE
, -1, -1);
2859 req
.tunnel_type
= tunnel_type
;
2861 switch (tunnel_type
) {
2862 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
:
2863 req
.tunnel_dst_port_id
= bp
->vxlan_fw_dst_port_id
;
2865 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
:
2866 req
.tunnel_dst_port_id
= bp
->nge_fw_dst_port_id
;
2872 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2874 netdev_err(bp
->dev
, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
2879 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt
*bp
, __be16 port
,
2883 struct hwrm_tunnel_dst_port_alloc_input req
= {0};
2884 struct hwrm_tunnel_dst_port_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
2886 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_TUNNEL_DST_PORT_ALLOC
, -1, -1);
2888 req
.tunnel_type
= tunnel_type
;
2889 req
.tunnel_dst_port_val
= port
;
2891 mutex_lock(&bp
->hwrm_cmd_lock
);
2892 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2894 netdev_err(bp
->dev
, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
2899 if (tunnel_type
& TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN
)
2900 bp
->vxlan_fw_dst_port_id
= resp
->tunnel_dst_port_id
;
2902 else if (tunnel_type
& TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE
)
2903 bp
->nge_fw_dst_port_id
= resp
->tunnel_dst_port_id
;
2905 mutex_unlock(&bp
->hwrm_cmd_lock
);
2909 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt
*bp
, u16 vnic_id
)
2911 struct hwrm_cfa_l2_set_rx_mask_input req
= {0};
2912 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
2914 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_L2_SET_RX_MASK
, -1, -1);
2915 req
.vnic_id
= cpu_to_le32(vnic
->fw_vnic_id
);
2917 req
.num_mc_entries
= cpu_to_le32(vnic
->mc_list_count
);
2918 req
.mc_tbl_addr
= cpu_to_le64(vnic
->mc_list_mapping
);
2919 req
.mask
= cpu_to_le32(vnic
->rx_mask
);
2920 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2923 #ifdef CONFIG_RFS_ACCEL
2924 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt
*bp
,
2925 struct bnxt_ntuple_filter
*fltr
)
2927 struct hwrm_cfa_ntuple_filter_free_input req
= {0};
2929 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_NTUPLE_FILTER_FREE
, -1, -1);
2930 req
.ntuple_filter_id
= fltr
->filter_id
;
2931 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2934 #define BNXT_NTP_FLTR_FLAGS \
2935 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
2936 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
2937 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
2938 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
2939 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
2940 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
2941 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
2942 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
2943 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
2944 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
2945 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
2946 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
2947 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
2948 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
2950 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt
*bp
,
2951 struct bnxt_ntuple_filter
*fltr
)
2954 struct hwrm_cfa_ntuple_filter_alloc_input req
= {0};
2955 struct hwrm_cfa_ntuple_filter_alloc_output
*resp
=
2956 bp
->hwrm_cmd_resp_addr
;
2957 struct flow_keys
*keys
= &fltr
->fkeys
;
2958 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[fltr
->rxq
+ 1];
2960 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_NTUPLE_FILTER_ALLOC
, -1, -1);
2961 req
.l2_filter_id
= bp
->vnic_info
[0].fw_l2_filter_id
[0];
2963 req
.enables
= cpu_to_le32(BNXT_NTP_FLTR_FLAGS
);
2965 req
.ethertype
= htons(ETH_P_IP
);
2966 memcpy(req
.src_macaddr
, fltr
->src_mac_addr
, ETH_ALEN
);
2967 req
.ip_addr_type
= CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4
;
2968 req
.ip_protocol
= keys
->basic
.ip_proto
;
2970 req
.src_ipaddr
[0] = keys
->addrs
.v4addrs
.src
;
2971 req
.src_ipaddr_mask
[0] = cpu_to_be32(0xffffffff);
2972 req
.dst_ipaddr
[0] = keys
->addrs
.v4addrs
.dst
;
2973 req
.dst_ipaddr_mask
[0] = cpu_to_be32(0xffffffff);
2975 req
.src_port
= keys
->ports
.src
;
2976 req
.src_port_mask
= cpu_to_be16(0xffff);
2977 req
.dst_port
= keys
->ports
.dst
;
2978 req
.dst_port_mask
= cpu_to_be16(0xffff);
2980 req
.dst_id
= cpu_to_le16(vnic
->fw_vnic_id
);
2981 mutex_lock(&bp
->hwrm_cmd_lock
);
2982 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2984 fltr
->filter_id
= resp
->ntuple_filter_id
;
2985 mutex_unlock(&bp
->hwrm_cmd_lock
);
2990 static int bnxt_hwrm_set_vnic_filter(struct bnxt
*bp
, u16 vnic_id
, u16 idx
,
2994 struct hwrm_cfa_l2_filter_alloc_input req
= {0};
2995 struct hwrm_cfa_l2_filter_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
2997 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_L2_FILTER_ALLOC
, -1, -1);
2998 req
.flags
= cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX
|
2999 CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST
);
3000 req
.dst_id
= cpu_to_le16(bp
->vnic_info
[vnic_id
].fw_vnic_id
);
3002 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR
|
3003 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID
|
3004 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK
);
3005 memcpy(req
.l2_addr
, mac_addr
, ETH_ALEN
);
3006 req
.l2_addr_mask
[0] = 0xff;
3007 req
.l2_addr_mask
[1] = 0xff;
3008 req
.l2_addr_mask
[2] = 0xff;
3009 req
.l2_addr_mask
[3] = 0xff;
3010 req
.l2_addr_mask
[4] = 0xff;
3011 req
.l2_addr_mask
[5] = 0xff;
3013 mutex_lock(&bp
->hwrm_cmd_lock
);
3014 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3016 bp
->vnic_info
[vnic_id
].fw_l2_filter_id
[idx
] =
3018 mutex_unlock(&bp
->hwrm_cmd_lock
);
3022 static int bnxt_hwrm_clear_vnic_filter(struct bnxt
*bp
)
3024 u16 i
, j
, num_of_vnics
= 1; /* only vnic 0 supported */
3027 /* Any associated ntuple filters will also be cleared by firmware. */
3028 mutex_lock(&bp
->hwrm_cmd_lock
);
3029 for (i
= 0; i
< num_of_vnics
; i
++) {
3030 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[i
];
3032 for (j
= 0; j
< vnic
->uc_filter_count
; j
++) {
3033 struct hwrm_cfa_l2_filter_free_input req
= {0};
3035 bnxt_hwrm_cmd_hdr_init(bp
, &req
,
3036 HWRM_CFA_L2_FILTER_FREE
, -1, -1);
3038 req
.l2_filter_id
= vnic
->fw_l2_filter_id
[j
];
3040 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3043 vnic
->uc_filter_count
= 0;
3045 mutex_unlock(&bp
->hwrm_cmd_lock
);
3050 static int bnxt_hwrm_vnic_set_tpa(struct bnxt
*bp
, u16 vnic_id
, u32 tpa_flags
)
3052 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
3053 struct hwrm_vnic_tpa_cfg_input req
= {0};
3055 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_TPA_CFG
, -1, -1);
3058 u16 mss
= bp
->dev
->mtu
- 40;
3059 u32 nsegs
, n
, segs
= 0, flags
;
3061 flags
= VNIC_TPA_CFG_REQ_FLAGS_TPA
|
3062 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA
|
3063 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE
|
3064 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN
|
3065 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ
;
3066 if (tpa_flags
& BNXT_FLAG_GRO
)
3067 flags
|= VNIC_TPA_CFG_REQ_FLAGS_GRO
;
3069 req
.flags
= cpu_to_le32(flags
);
3072 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS
|
3073 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS
|
3074 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN
);
3076 /* Number of segs are log2 units, and first packet is not
3077 * included as part of this units.
3079 if (mss
<= PAGE_SIZE
) {
3080 n
= PAGE_SIZE
/ mss
;
3081 nsegs
= (MAX_SKB_FRAGS
- 1) * n
;
3083 n
= mss
/ PAGE_SIZE
;
3084 if (mss
& (PAGE_SIZE
- 1))
3086 nsegs
= (MAX_SKB_FRAGS
- n
) / n
;
3089 segs
= ilog2(nsegs
);
3090 req
.max_agg_segs
= cpu_to_le16(segs
);
3091 req
.max_aggs
= cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX
);
3093 req
.min_agg_len
= cpu_to_le32(512);
3095 req
.vnic_id
= cpu_to_le16(vnic
->fw_vnic_id
);
3097 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3100 static int bnxt_hwrm_vnic_set_rss(struct bnxt
*bp
, u16 vnic_id
, bool set_rss
)
3102 u32 i
, j
, max_rings
;
3103 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
3104 struct hwrm_vnic_rss_cfg_input req
= {0};
3106 if (vnic
->fw_rss_cos_lb_ctx
== INVALID_HW_RING_ID
)
3109 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_RSS_CFG
, -1, -1);
3111 vnic
->hash_type
= BNXT_RSS_HASH_TYPE_FLAG_IPV4
|
3112 BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV4
|
3113 BNXT_RSS_HASH_TYPE_FLAG_IPV6
|
3114 BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV6
;
3116 req
.hash_type
= cpu_to_le32(vnic
->hash_type
);
3118 if (vnic
->flags
& BNXT_VNIC_RSS_FLAG
)
3119 max_rings
= bp
->rx_nr_rings
;
3123 /* Fill the RSS indirection table with ring group ids */
3124 for (i
= 0, j
= 0; i
< HW_HASH_INDEX_SIZE
; i
++, j
++) {
3127 vnic
->rss_table
[i
] = cpu_to_le16(vnic
->fw_grp_ids
[j
]);
3130 req
.ring_grp_tbl_addr
= cpu_to_le64(vnic
->rss_table_dma_addr
);
3131 req
.hash_key_tbl_addr
=
3132 cpu_to_le64(vnic
->rss_hash_key_dma_addr
);
3134 req
.rss_ctx_idx
= cpu_to_le16(vnic
->fw_rss_cos_lb_ctx
);
3135 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3138 static int bnxt_hwrm_vnic_set_hds(struct bnxt
*bp
, u16 vnic_id
)
3140 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
3141 struct hwrm_vnic_plcmodes_cfg_input req
= {0};
3143 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_PLCMODES_CFG
, -1, -1);
3144 req
.flags
= cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT
|
3145 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4
|
3146 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6
);
3148 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID
|
3149 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID
);
3150 /* thresholds not implemented in firmware yet */
3151 req
.jumbo_thresh
= cpu_to_le16(bp
->rx_copy_thresh
);
3152 req
.hds_threshold
= cpu_to_le16(bp
->rx_copy_thresh
);
3153 req
.vnic_id
= cpu_to_le32(vnic
->fw_vnic_id
);
3154 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3157 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt
*bp
, u16 vnic_id
)
3159 struct hwrm_vnic_rss_cos_lb_ctx_free_input req
= {0};
3161 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_RSS_COS_LB_CTX_FREE
, -1, -1);
3162 req
.rss_cos_lb_ctx_id
=
3163 cpu_to_le16(bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
);
3165 hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3166 bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
= INVALID_HW_RING_ID
;
3169 static void bnxt_hwrm_vnic_ctx_free(struct bnxt
*bp
)
3173 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
3174 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[i
];
3176 if (vnic
->fw_rss_cos_lb_ctx
!= INVALID_HW_RING_ID
)
3177 bnxt_hwrm_vnic_ctx_free_one(bp
, i
);
3179 bp
->rsscos_nr_ctxs
= 0;
3182 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt
*bp
, u16 vnic_id
)
3185 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req
= {0};
3186 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output
*resp
=
3187 bp
->hwrm_cmd_resp_addr
;
3189 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC
, -1,
3192 mutex_lock(&bp
->hwrm_cmd_lock
);
3193 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3195 bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
=
3196 le16_to_cpu(resp
->rss_cos_lb_ctx_id
);
3197 mutex_unlock(&bp
->hwrm_cmd_lock
);
3202 static int bnxt_hwrm_vnic_cfg(struct bnxt
*bp
, u16 vnic_id
)
3204 unsigned int ring
= 0, grp_idx
;
3205 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
3206 struct hwrm_vnic_cfg_input req
= {0};
3208 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_CFG
, -1, -1);
3209 /* Only RSS support for now TBD: COS & LB */
3210 req
.enables
= cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP
|
3211 VNIC_CFG_REQ_ENABLES_RSS_RULE
);
3212 req
.rss_rule
= cpu_to_le16(vnic
->fw_rss_cos_lb_ctx
);
3213 req
.cos_rule
= cpu_to_le16(0xffff);
3214 if (vnic
->flags
& BNXT_VNIC_RSS_FLAG
)
3216 else if (vnic
->flags
& BNXT_VNIC_RFS_FLAG
)
3219 grp_idx
= bp
->rx_ring
[ring
].bnapi
->index
;
3220 req
.vnic_id
= cpu_to_le16(vnic
->fw_vnic_id
);
3221 req
.dflt_ring_grp
= cpu_to_le16(bp
->grp_info
[grp_idx
].fw_grp_id
);
3223 req
.lb_rule
= cpu_to_le16(0xffff);
3224 req
.mru
= cpu_to_le16(bp
->dev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+
3227 if (bp
->flags
& BNXT_FLAG_STRIP_VLAN
)
3228 req
.flags
|= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE
);
3230 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3233 static int bnxt_hwrm_vnic_free_one(struct bnxt
*bp
, u16 vnic_id
)
3237 if (bp
->vnic_info
[vnic_id
].fw_vnic_id
!= INVALID_HW_RING_ID
) {
3238 struct hwrm_vnic_free_input req
= {0};
3240 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_FREE
, -1, -1);
3242 cpu_to_le32(bp
->vnic_info
[vnic_id
].fw_vnic_id
);
3244 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3247 bp
->vnic_info
[vnic_id
].fw_vnic_id
= INVALID_HW_RING_ID
;
3252 static void bnxt_hwrm_vnic_free(struct bnxt
*bp
)
3256 for (i
= 0; i
< bp
->nr_vnics
; i
++)
3257 bnxt_hwrm_vnic_free_one(bp
, i
);
3260 static int bnxt_hwrm_vnic_alloc(struct bnxt
*bp
, u16 vnic_id
,
3261 unsigned int start_rx_ring_idx
,
3262 unsigned int nr_rings
)
3265 unsigned int i
, j
, grp_idx
, end_idx
= start_rx_ring_idx
+ nr_rings
;
3266 struct hwrm_vnic_alloc_input req
= {0};
3267 struct hwrm_vnic_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3269 /* map ring groups to this vnic */
3270 for (i
= start_rx_ring_idx
, j
= 0; i
< end_idx
; i
++, j
++) {
3271 grp_idx
= bp
->rx_ring
[i
].bnapi
->index
;
3272 if (bp
->grp_info
[grp_idx
].fw_grp_id
== INVALID_HW_RING_ID
) {
3273 netdev_err(bp
->dev
, "Not enough ring groups avail:%x req:%x\n",
3277 bp
->vnic_info
[vnic_id
].fw_grp_ids
[j
] =
3278 bp
->grp_info
[grp_idx
].fw_grp_id
;
3281 bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
= INVALID_HW_RING_ID
;
3283 req
.flags
= cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT
);
3285 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_ALLOC
, -1, -1);
3287 mutex_lock(&bp
->hwrm_cmd_lock
);
3288 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3290 bp
->vnic_info
[vnic_id
].fw_vnic_id
= le32_to_cpu(resp
->vnic_id
);
3291 mutex_unlock(&bp
->hwrm_cmd_lock
);
3295 static int bnxt_hwrm_ring_grp_alloc(struct bnxt
*bp
)
3300 mutex_lock(&bp
->hwrm_cmd_lock
);
3301 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3302 struct hwrm_ring_grp_alloc_input req
= {0};
3303 struct hwrm_ring_grp_alloc_output
*resp
=
3304 bp
->hwrm_cmd_resp_addr
;
3305 unsigned int grp_idx
= bp
->rx_ring
[i
].bnapi
->index
;
3307 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_GRP_ALLOC
, -1, -1);
3309 req
.cr
= cpu_to_le16(bp
->grp_info
[grp_idx
].cp_fw_ring_id
);
3310 req
.rr
= cpu_to_le16(bp
->grp_info
[grp_idx
].rx_fw_ring_id
);
3311 req
.ar
= cpu_to_le16(bp
->grp_info
[grp_idx
].agg_fw_ring_id
);
3312 req
.sc
= cpu_to_le16(bp
->grp_info
[grp_idx
].fw_stats_ctx
);
3314 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3319 bp
->grp_info
[grp_idx
].fw_grp_id
=
3320 le32_to_cpu(resp
->ring_group_id
);
3322 mutex_unlock(&bp
->hwrm_cmd_lock
);
3326 static int bnxt_hwrm_ring_grp_free(struct bnxt
*bp
)
3330 struct hwrm_ring_grp_free_input req
= {0};
3335 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_GRP_FREE
, -1, -1);
3337 mutex_lock(&bp
->hwrm_cmd_lock
);
3338 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3339 if (bp
->grp_info
[i
].fw_grp_id
== INVALID_HW_RING_ID
)
3342 cpu_to_le32(bp
->grp_info
[i
].fw_grp_id
);
3344 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3348 bp
->grp_info
[i
].fw_grp_id
= INVALID_HW_RING_ID
;
3350 mutex_unlock(&bp
->hwrm_cmd_lock
);
3354 static int hwrm_ring_alloc_send_msg(struct bnxt
*bp
,
3355 struct bnxt_ring_struct
*ring
,
3356 u32 ring_type
, u32 map_index
,
3359 int rc
= 0, err
= 0;
3360 struct hwrm_ring_alloc_input req
= {0};
3361 struct hwrm_ring_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3364 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_ALLOC
, -1, -1);
3367 if (ring
->nr_pages
> 1) {
3368 req
.page_tbl_addr
= cpu_to_le64(ring
->pg_tbl_map
);
3369 /* Page size is in log2 units */
3370 req
.page_size
= BNXT_PAGE_SHIFT
;
3371 req
.page_tbl_depth
= 1;
3373 req
.page_tbl_addr
= cpu_to_le64(ring
->dma_arr
[0]);
3376 /* Association of ring index with doorbell index and MSIX number */
3377 req
.logical_id
= cpu_to_le16(map_index
);
3379 switch (ring_type
) {
3380 case HWRM_RING_ALLOC_TX
:
3381 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_TX
;
3382 /* Association of transmit ring with completion ring */
3384 cpu_to_le16(bp
->grp_info
[map_index
].cp_fw_ring_id
);
3385 req
.length
= cpu_to_le32(bp
->tx_ring_mask
+ 1);
3386 req
.stat_ctx_id
= cpu_to_le32(stats_ctx_id
);
3387 req
.queue_id
= cpu_to_le16(ring
->queue_id
);
3389 case HWRM_RING_ALLOC_RX
:
3390 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_RX
;
3391 req
.length
= cpu_to_le32(bp
->rx_ring_mask
+ 1);
3393 case HWRM_RING_ALLOC_AGG
:
3394 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_RX
;
3395 req
.length
= cpu_to_le32(bp
->rx_agg_ring_mask
+ 1);
3397 case HWRM_RING_ALLOC_CMPL
:
3398 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_CMPL
;
3399 req
.length
= cpu_to_le32(bp
->cp_ring_mask
+ 1);
3400 if (bp
->flags
& BNXT_FLAG_USING_MSIX
)
3401 req
.int_mode
= RING_ALLOC_REQ_INT_MODE_MSIX
;
3404 netdev_err(bp
->dev
, "hwrm alloc invalid ring type %d\n",
3409 mutex_lock(&bp
->hwrm_cmd_lock
);
3410 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3411 err
= le16_to_cpu(resp
->error_code
);
3412 ring_id
= le16_to_cpu(resp
->ring_id
);
3413 mutex_unlock(&bp
->hwrm_cmd_lock
);
3416 switch (ring_type
) {
3417 case RING_FREE_REQ_RING_TYPE_CMPL
:
3418 netdev_err(bp
->dev
, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
3422 case RING_FREE_REQ_RING_TYPE_RX
:
3423 netdev_err(bp
->dev
, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
3427 case RING_FREE_REQ_RING_TYPE_TX
:
3428 netdev_err(bp
->dev
, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
3433 netdev_err(bp
->dev
, "Invalid ring\n");
3437 ring
->fw_ring_id
= ring_id
;
3441 static int bnxt_hwrm_ring_alloc(struct bnxt
*bp
)
3445 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3446 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3447 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3448 struct bnxt_ring_struct
*ring
= &cpr
->cp_ring_struct
;
3450 cpr
->cp_doorbell
= bp
->bar1
+ i
* 0x80;
3451 rc
= hwrm_ring_alloc_send_msg(bp
, ring
, HWRM_RING_ALLOC_CMPL
, i
,
3452 INVALID_STATS_CTX_ID
);
3455 BNXT_CP_DB(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
3456 bp
->grp_info
[i
].cp_fw_ring_id
= ring
->fw_ring_id
;
3459 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
3460 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
3461 struct bnxt_ring_struct
*ring
= &txr
->tx_ring_struct
;
3462 u32 map_idx
= txr
->bnapi
->index
;
3463 u16 fw_stats_ctx
= bp
->grp_info
[map_idx
].fw_stats_ctx
;
3465 rc
= hwrm_ring_alloc_send_msg(bp
, ring
, HWRM_RING_ALLOC_TX
,
3466 map_idx
, fw_stats_ctx
);
3469 txr
->tx_doorbell
= bp
->bar1
+ map_idx
* 0x80;
3472 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3473 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
3474 struct bnxt_ring_struct
*ring
= &rxr
->rx_ring_struct
;
3475 u32 map_idx
= rxr
->bnapi
->index
;
3477 rc
= hwrm_ring_alloc_send_msg(bp
, ring
, HWRM_RING_ALLOC_RX
,
3478 map_idx
, INVALID_STATS_CTX_ID
);
3481 rxr
->rx_doorbell
= bp
->bar1
+ map_idx
* 0x80;
3482 writel(DB_KEY_RX
| rxr
->rx_prod
, rxr
->rx_doorbell
);
3483 bp
->grp_info
[map_idx
].rx_fw_ring_id
= ring
->fw_ring_id
;
3486 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
) {
3487 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3488 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
3489 struct bnxt_ring_struct
*ring
=
3490 &rxr
->rx_agg_ring_struct
;
3491 u32 grp_idx
= rxr
->bnapi
->index
;
3492 u32 map_idx
= grp_idx
+ bp
->rx_nr_rings
;
3494 rc
= hwrm_ring_alloc_send_msg(bp
, ring
,
3495 HWRM_RING_ALLOC_AGG
,
3497 INVALID_STATS_CTX_ID
);
3501 rxr
->rx_agg_doorbell
= bp
->bar1
+ map_idx
* 0x80;
3502 writel(DB_KEY_RX
| rxr
->rx_agg_prod
,
3503 rxr
->rx_agg_doorbell
);
3504 bp
->grp_info
[grp_idx
].agg_fw_ring_id
= ring
->fw_ring_id
;
3511 static int hwrm_ring_free_send_msg(struct bnxt
*bp
,
3512 struct bnxt_ring_struct
*ring
,
3513 u32 ring_type
, int cmpl_ring_id
)
3516 struct hwrm_ring_free_input req
= {0};
3517 struct hwrm_ring_free_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3520 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_FREE
, cmpl_ring_id
, -1);
3521 req
.ring_type
= ring_type
;
3522 req
.ring_id
= cpu_to_le16(ring
->fw_ring_id
);
3524 mutex_lock(&bp
->hwrm_cmd_lock
);
3525 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3526 error_code
= le16_to_cpu(resp
->error_code
);
3527 mutex_unlock(&bp
->hwrm_cmd_lock
);
3529 if (rc
|| error_code
) {
3530 switch (ring_type
) {
3531 case RING_FREE_REQ_RING_TYPE_CMPL
:
3532 netdev_err(bp
->dev
, "hwrm_ring_free cp failed. rc:%d\n",
3535 case RING_FREE_REQ_RING_TYPE_RX
:
3536 netdev_err(bp
->dev
, "hwrm_ring_free rx failed. rc:%d\n",
3539 case RING_FREE_REQ_RING_TYPE_TX
:
3540 netdev_err(bp
->dev
, "hwrm_ring_free tx failed. rc:%d\n",
3544 netdev_err(bp
->dev
, "Invalid ring\n");
3551 static void bnxt_hwrm_ring_free(struct bnxt
*bp
, bool close_path
)
3558 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
3559 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
3560 struct bnxt_ring_struct
*ring
= &txr
->tx_ring_struct
;
3561 u32 grp_idx
= txr
->bnapi
->index
;
3562 u32 cmpl_ring_id
= bp
->grp_info
[grp_idx
].cp_fw_ring_id
;
3564 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
3565 hwrm_ring_free_send_msg(bp
, ring
,
3566 RING_FREE_REQ_RING_TYPE_TX
,
3567 close_path
? cmpl_ring_id
:
3568 INVALID_HW_RING_ID
);
3569 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
3573 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3574 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
3575 struct bnxt_ring_struct
*ring
= &rxr
->rx_ring_struct
;
3576 u32 grp_idx
= rxr
->bnapi
->index
;
3577 u32 cmpl_ring_id
= bp
->grp_info
[grp_idx
].cp_fw_ring_id
;
3579 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
3580 hwrm_ring_free_send_msg(bp
, ring
,
3581 RING_FREE_REQ_RING_TYPE_RX
,
3582 close_path
? cmpl_ring_id
:
3583 INVALID_HW_RING_ID
);
3584 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
3585 bp
->grp_info
[grp_idx
].rx_fw_ring_id
=
3590 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3591 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
3592 struct bnxt_ring_struct
*ring
= &rxr
->rx_agg_ring_struct
;
3593 u32 grp_idx
= rxr
->bnapi
->index
;
3594 u32 cmpl_ring_id
= bp
->grp_info
[grp_idx
].cp_fw_ring_id
;
3596 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
3597 hwrm_ring_free_send_msg(bp
, ring
,
3598 RING_FREE_REQ_RING_TYPE_RX
,
3599 close_path
? cmpl_ring_id
:
3600 INVALID_HW_RING_ID
);
3601 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
3602 bp
->grp_info
[grp_idx
].agg_fw_ring_id
=
3607 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3608 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3609 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3610 struct bnxt_ring_struct
*ring
= &cpr
->cp_ring_struct
;
3612 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
3613 hwrm_ring_free_send_msg(bp
, ring
,
3614 RING_FREE_REQ_RING_TYPE_CMPL
,
3615 INVALID_HW_RING_ID
);
3616 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
3617 bp
->grp_info
[i
].cp_fw_ring_id
= INVALID_HW_RING_ID
;
3622 static void bnxt_hwrm_set_coal_params(struct bnxt
*bp
, u32 max_bufs
,
3623 u32 buf_tmrs
, u16 flags
,
3624 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input
*req
)
3626 req
->flags
= cpu_to_le16(flags
);
3627 req
->num_cmpl_dma_aggr
= cpu_to_le16((u16
)max_bufs
);
3628 req
->num_cmpl_dma_aggr_during_int
= cpu_to_le16(max_bufs
>> 16);
3629 req
->cmpl_aggr_dma_tmr
= cpu_to_le16((u16
)buf_tmrs
);
3630 req
->cmpl_aggr_dma_tmr_during_int
= cpu_to_le16(buf_tmrs
>> 16);
3631 /* Minimum time between 2 interrupts set to buf_tmr x 2 */
3632 req
->int_lat_tmr_min
= cpu_to_le16((u16
)buf_tmrs
* 2);
3633 req
->int_lat_tmr_max
= cpu_to_le16((u16
)buf_tmrs
* 4);
3634 req
->num_cmpl_aggr_int
= cpu_to_le16((u16
)max_bufs
* 4);
3637 int bnxt_hwrm_set_coal(struct bnxt
*bp
)
3640 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx
= {0},
3642 u16 max_buf
, max_buf_irq
;
3643 u16 buf_tmr
, buf_tmr_irq
;
3646 bnxt_hwrm_cmd_hdr_init(bp
, &req_rx
,
3647 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS
, -1, -1);
3648 bnxt_hwrm_cmd_hdr_init(bp
, &req_tx
,
3649 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS
, -1, -1);
3651 /* Each rx completion (2 records) should be DMAed immediately.
3652 * DMA 1/4 of the completion buffers at a time.
3654 max_buf
= min_t(u16
, bp
->rx_coal_bufs
/ 4, 2);
3655 /* max_buf must not be zero */
3656 max_buf
= clamp_t(u16
, max_buf
, 1, 63);
3657 max_buf_irq
= clamp_t(u16
, bp
->rx_coal_bufs_irq
, 1, 63);
3658 buf_tmr
= BNXT_USEC_TO_COAL_TIMER(bp
->rx_coal_ticks
);
3659 /* buf timer set to 1/4 of interrupt timer */
3660 buf_tmr
= max_t(u16
, buf_tmr
/ 4, 1);
3661 buf_tmr_irq
= BNXT_USEC_TO_COAL_TIMER(bp
->rx_coal_ticks_irq
);
3662 buf_tmr_irq
= max_t(u16
, buf_tmr_irq
, 1);
3664 flags
= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET
;
3666 /* RING_IDLE generates more IRQs for lower latency. Enable it only
3667 * if coal_ticks is less than 25 us.
3669 if (bp
->rx_coal_ticks
< 25)
3670 flags
|= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE
;
3672 bnxt_hwrm_set_coal_params(bp
, max_buf_irq
<< 16 | max_buf
,
3673 buf_tmr_irq
<< 16 | buf_tmr
, flags
, &req_rx
);
3675 /* max_buf must not be zero */
3676 max_buf
= clamp_t(u16
, bp
->tx_coal_bufs
, 1, 63);
3677 max_buf_irq
= clamp_t(u16
, bp
->tx_coal_bufs_irq
, 1, 63);
3678 buf_tmr
= BNXT_USEC_TO_COAL_TIMER(bp
->tx_coal_ticks
);
3679 /* buf timer set to 1/4 of interrupt timer */
3680 buf_tmr
= max_t(u16
, buf_tmr
/ 4, 1);
3681 buf_tmr_irq
= BNXT_USEC_TO_COAL_TIMER(bp
->tx_coal_ticks_irq
);
3682 buf_tmr_irq
= max_t(u16
, buf_tmr_irq
, 1);
3684 flags
= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET
;
3685 bnxt_hwrm_set_coal_params(bp
, max_buf_irq
<< 16 | max_buf
,
3686 buf_tmr_irq
<< 16 | buf_tmr
, flags
, &req_tx
);
3688 mutex_lock(&bp
->hwrm_cmd_lock
);
3689 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3690 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3693 if (!bnapi
->rx_ring
)
3695 req
->ring_id
= cpu_to_le16(bp
->grp_info
[i
].cp_fw_ring_id
);
3697 rc
= _hwrm_send_message(bp
, req
, sizeof(*req
),
3702 mutex_unlock(&bp
->hwrm_cmd_lock
);
3706 static int bnxt_hwrm_stat_ctx_free(struct bnxt
*bp
)
3709 struct hwrm_stat_ctx_free_input req
= {0};
3714 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_STAT_CTX_FREE
, -1, -1);
3716 mutex_lock(&bp
->hwrm_cmd_lock
);
3717 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3718 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3719 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3721 if (cpr
->hw_stats_ctx_id
!= INVALID_STATS_CTX_ID
) {
3722 req
.stat_ctx_id
= cpu_to_le32(cpr
->hw_stats_ctx_id
);
3724 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3729 cpr
->hw_stats_ctx_id
= INVALID_STATS_CTX_ID
;
3732 mutex_unlock(&bp
->hwrm_cmd_lock
);
3736 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt
*bp
)
3739 struct hwrm_stat_ctx_alloc_input req
= {0};
3740 struct hwrm_stat_ctx_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3742 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_STAT_CTX_ALLOC
, -1, -1);
3744 req
.update_period_ms
= cpu_to_le32(1000);
3746 mutex_lock(&bp
->hwrm_cmd_lock
);
3747 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3748 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3749 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3751 req
.stats_dma_addr
= cpu_to_le64(cpr
->hw_stats_map
);
3753 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3758 cpr
->hw_stats_ctx_id
= le32_to_cpu(resp
->stat_ctx_id
);
3760 bp
->grp_info
[i
].fw_stats_ctx
= cpr
->hw_stats_ctx_id
;
3762 mutex_unlock(&bp
->hwrm_cmd_lock
);
3766 int bnxt_hwrm_func_qcaps(struct bnxt
*bp
)
3769 struct hwrm_func_qcaps_input req
= {0};
3770 struct hwrm_func_qcaps_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3772 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_QCAPS
, -1, -1);
3773 req
.fid
= cpu_to_le16(0xffff);
3775 mutex_lock(&bp
->hwrm_cmd_lock
);
3776 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3778 goto hwrm_func_qcaps_exit
;
3781 struct bnxt_pf_info
*pf
= &bp
->pf
;
3783 pf
->fw_fid
= le16_to_cpu(resp
->fid
);
3784 pf
->port_id
= le16_to_cpu(resp
->port_id
);
3785 memcpy(pf
->mac_addr
, resp
->mac_address
, ETH_ALEN
);
3786 memcpy(bp
->dev
->dev_addr
, pf
->mac_addr
, ETH_ALEN
);
3787 pf
->max_rsscos_ctxs
= le16_to_cpu(resp
->max_rsscos_ctx
);
3788 pf
->max_cp_rings
= le16_to_cpu(resp
->max_cmpl_rings
);
3789 pf
->max_tx_rings
= le16_to_cpu(resp
->max_tx_rings
);
3790 pf
->max_rx_rings
= le16_to_cpu(resp
->max_rx_rings
);
3791 pf
->max_hw_ring_grps
= le32_to_cpu(resp
->max_hw_ring_grps
);
3792 if (!pf
->max_hw_ring_grps
)
3793 pf
->max_hw_ring_grps
= pf
->max_tx_rings
;
3794 pf
->max_l2_ctxs
= le16_to_cpu(resp
->max_l2_ctxs
);
3795 pf
->max_vnics
= le16_to_cpu(resp
->max_vnics
);
3796 pf
->max_stat_ctxs
= le16_to_cpu(resp
->max_stat_ctx
);
3797 pf
->first_vf_id
= le16_to_cpu(resp
->first_vf_id
);
3798 pf
->max_vfs
= le16_to_cpu(resp
->max_vfs
);
3799 pf
->max_encap_records
= le32_to_cpu(resp
->max_encap_records
);
3800 pf
->max_decap_records
= le32_to_cpu(resp
->max_decap_records
);
3801 pf
->max_tx_em_flows
= le32_to_cpu(resp
->max_tx_em_flows
);
3802 pf
->max_tx_wm_flows
= le32_to_cpu(resp
->max_tx_wm_flows
);
3803 pf
->max_rx_em_flows
= le32_to_cpu(resp
->max_rx_em_flows
);
3804 pf
->max_rx_wm_flows
= le32_to_cpu(resp
->max_rx_wm_flows
);
3806 #ifdef CONFIG_BNXT_SRIOV
3807 struct bnxt_vf_info
*vf
= &bp
->vf
;
3809 vf
->fw_fid
= le16_to_cpu(resp
->fid
);
3810 memcpy(vf
->mac_addr
, resp
->mac_address
, ETH_ALEN
);
3811 if (is_valid_ether_addr(vf
->mac_addr
))
3812 /* overwrite netdev dev_adr with admin VF MAC */
3813 memcpy(bp
->dev
->dev_addr
, vf
->mac_addr
, ETH_ALEN
);
3815 random_ether_addr(bp
->dev
->dev_addr
);
3817 vf
->max_rsscos_ctxs
= le16_to_cpu(resp
->max_rsscos_ctx
);
3818 vf
->max_cp_rings
= le16_to_cpu(resp
->max_cmpl_rings
);
3819 vf
->max_tx_rings
= le16_to_cpu(resp
->max_tx_rings
);
3820 vf
->max_rx_rings
= le16_to_cpu(resp
->max_rx_rings
);
3821 vf
->max_hw_ring_grps
= le32_to_cpu(resp
->max_hw_ring_grps
);
3822 if (!vf
->max_hw_ring_grps
)
3823 vf
->max_hw_ring_grps
= vf
->max_tx_rings
;
3824 vf
->max_l2_ctxs
= le16_to_cpu(resp
->max_l2_ctxs
);
3825 vf
->max_vnics
= le16_to_cpu(resp
->max_vnics
);
3826 vf
->max_stat_ctxs
= le16_to_cpu(resp
->max_stat_ctx
);
3830 bp
->tx_push_thresh
= 0;
3832 cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED
))
3833 bp
->tx_push_thresh
= BNXT_TX_PUSH_THRESH
;
3835 hwrm_func_qcaps_exit
:
3836 mutex_unlock(&bp
->hwrm_cmd_lock
);
3840 static int bnxt_hwrm_func_reset(struct bnxt
*bp
)
3842 struct hwrm_func_reset_input req
= {0};
3844 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_RESET
, -1, -1);
3847 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_RESET_TIMEOUT
);
3850 static int bnxt_hwrm_queue_qportcfg(struct bnxt
*bp
)
3853 struct hwrm_queue_qportcfg_input req
= {0};
3854 struct hwrm_queue_qportcfg_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3857 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_QUEUE_QPORTCFG
, -1, -1);
3859 mutex_lock(&bp
->hwrm_cmd_lock
);
3860 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3864 if (!resp
->max_configurable_queues
) {
3868 bp
->max_tc
= resp
->max_configurable_queues
;
3869 if (bp
->max_tc
> BNXT_MAX_QUEUE
)
3870 bp
->max_tc
= BNXT_MAX_QUEUE
;
3872 qptr
= &resp
->queue_id0
;
3873 for (i
= 0; i
< bp
->max_tc
; i
++) {
3874 bp
->q_info
[i
].queue_id
= *qptr
++;
3875 bp
->q_info
[i
].queue_profile
= *qptr
++;
3879 mutex_unlock(&bp
->hwrm_cmd_lock
);
3883 static int bnxt_hwrm_ver_get(struct bnxt
*bp
)
3886 struct hwrm_ver_get_input req
= {0};
3887 struct hwrm_ver_get_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3889 bp
->hwrm_max_req_len
= HWRM_MAX_REQ_LEN
;
3890 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VER_GET
, -1, -1);
3891 req
.hwrm_intf_maj
= HWRM_VERSION_MAJOR
;
3892 req
.hwrm_intf_min
= HWRM_VERSION_MINOR
;
3893 req
.hwrm_intf_upd
= HWRM_VERSION_UPDATE
;
3894 mutex_lock(&bp
->hwrm_cmd_lock
);
3895 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3897 goto hwrm_ver_get_exit
;
3899 memcpy(&bp
->ver_resp
, resp
, sizeof(struct hwrm_ver_get_output
));
3901 bp
->hwrm_spec_code
= resp
->hwrm_intf_maj
<< 16 |
3902 resp
->hwrm_intf_min
<< 8 | resp
->hwrm_intf_upd
;
3903 if (resp
->hwrm_intf_maj
< 1) {
3904 netdev_warn(bp
->dev
, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
3905 resp
->hwrm_intf_maj
, resp
->hwrm_intf_min
,
3906 resp
->hwrm_intf_upd
);
3907 netdev_warn(bp
->dev
, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
3909 snprintf(bp
->fw_ver_str
, BC_HWRM_STR_LEN
, "%d.%d.%d/%d.%d.%d",
3910 resp
->hwrm_fw_maj
, resp
->hwrm_fw_min
, resp
->hwrm_fw_bld
,
3911 resp
->hwrm_intf_maj
, resp
->hwrm_intf_min
, resp
->hwrm_intf_upd
);
3913 bp
->hwrm_cmd_timeout
= le16_to_cpu(resp
->def_req_timeout
);
3914 if (!bp
->hwrm_cmd_timeout
)
3915 bp
->hwrm_cmd_timeout
= DFLT_HWRM_CMD_TIMEOUT
;
3917 if (resp
->hwrm_intf_maj
>= 1)
3918 bp
->hwrm_max_req_len
= le16_to_cpu(resp
->max_req_win_len
);
3921 mutex_unlock(&bp
->hwrm_cmd_lock
);
3925 static int bnxt_hwrm_port_qstats(struct bnxt
*bp
)
3928 struct bnxt_pf_info
*pf
= &bp
->pf
;
3929 struct hwrm_port_qstats_input req
= {0};
3931 if (!(bp
->flags
& BNXT_FLAG_PORT_STATS
))
3934 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_QSTATS
, -1, -1);
3935 req
.port_id
= cpu_to_le16(pf
->port_id
);
3936 req
.tx_stat_host_addr
= cpu_to_le64(bp
->hw_tx_port_stats_map
);
3937 req
.rx_stat_host_addr
= cpu_to_le64(bp
->hw_rx_port_stats_map
);
3938 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3942 static void bnxt_hwrm_free_tunnel_ports(struct bnxt
*bp
)
3944 if (bp
->vxlan_port_cnt
) {
3945 bnxt_hwrm_tunnel_dst_port_free(
3946 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
);
3948 bp
->vxlan_port_cnt
= 0;
3949 if (bp
->nge_port_cnt
) {
3950 bnxt_hwrm_tunnel_dst_port_free(
3951 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
);
3953 bp
->nge_port_cnt
= 0;
3956 static int bnxt_set_tpa(struct bnxt
*bp
, bool set_tpa
)
3962 tpa_flags
= bp
->flags
& BNXT_FLAG_TPA
;
3963 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
3964 rc
= bnxt_hwrm_vnic_set_tpa(bp
, i
, tpa_flags
);
3966 netdev_err(bp
->dev
, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
3974 static void bnxt_hwrm_clear_vnic_rss(struct bnxt
*bp
)
3978 for (i
= 0; i
< bp
->nr_vnics
; i
++)
3979 bnxt_hwrm_vnic_set_rss(bp
, i
, false);
3982 static void bnxt_hwrm_resource_free(struct bnxt
*bp
, bool close_path
,
3985 if (bp
->vnic_info
) {
3986 bnxt_hwrm_clear_vnic_filter(bp
);
3987 /* clear all RSS setting before free vnic ctx */
3988 bnxt_hwrm_clear_vnic_rss(bp
);
3989 bnxt_hwrm_vnic_ctx_free(bp
);
3990 /* before free the vnic, undo the vnic tpa settings */
3991 if (bp
->flags
& BNXT_FLAG_TPA
)
3992 bnxt_set_tpa(bp
, false);
3993 bnxt_hwrm_vnic_free(bp
);
3995 bnxt_hwrm_ring_free(bp
, close_path
);
3996 bnxt_hwrm_ring_grp_free(bp
);
3998 bnxt_hwrm_stat_ctx_free(bp
);
3999 bnxt_hwrm_free_tunnel_ports(bp
);
4003 static int bnxt_setup_vnic(struct bnxt
*bp
, u16 vnic_id
)
4007 /* allocate context for vnic */
4008 rc
= bnxt_hwrm_vnic_ctx_alloc(bp
, vnic_id
);
4010 netdev_err(bp
->dev
, "hwrm vnic %d alloc failure rc: %x\n",
4012 goto vnic_setup_err
;
4014 bp
->rsscos_nr_ctxs
++;
4016 /* configure default vnic, ring grp */
4017 rc
= bnxt_hwrm_vnic_cfg(bp
, vnic_id
);
4019 netdev_err(bp
->dev
, "hwrm vnic %d cfg failure rc: %x\n",
4021 goto vnic_setup_err
;
4024 /* Enable RSS hashing on vnic */
4025 rc
= bnxt_hwrm_vnic_set_rss(bp
, vnic_id
, true);
4027 netdev_err(bp
->dev
, "hwrm vnic %d set rss failure rc: %x\n",
4029 goto vnic_setup_err
;
4032 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
) {
4033 rc
= bnxt_hwrm_vnic_set_hds(bp
, vnic_id
);
4035 netdev_err(bp
->dev
, "hwrm vnic %d set hds failure rc: %x\n",
4044 static int bnxt_alloc_rfs_vnics(struct bnxt
*bp
)
4046 #ifdef CONFIG_RFS_ACCEL
4049 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
4050 u16 vnic_id
= i
+ 1;
4053 if (vnic_id
>= bp
->nr_vnics
)
4056 bp
->vnic_info
[vnic_id
].flags
|= BNXT_VNIC_RFS_FLAG
;
4057 rc
= bnxt_hwrm_vnic_alloc(bp
, vnic_id
, ring_id
, 1);
4059 netdev_err(bp
->dev
, "hwrm vnic %d alloc failure rc: %x\n",
4063 rc
= bnxt_setup_vnic(bp
, vnic_id
);
4073 static int bnxt_cfg_rx_mode(struct bnxt
*);
4075 static int bnxt_init_chip(struct bnxt
*bp
, bool irq_re_init
)
4080 rc
= bnxt_hwrm_stat_ctx_alloc(bp
);
4082 netdev_err(bp
->dev
, "hwrm stat ctx alloc failure rc: %x\n",
4088 rc
= bnxt_hwrm_ring_alloc(bp
);
4090 netdev_err(bp
->dev
, "hwrm ring alloc failure rc: %x\n", rc
);
4094 rc
= bnxt_hwrm_ring_grp_alloc(bp
);
4096 netdev_err(bp
->dev
, "hwrm_ring_grp alloc failure: %x\n", rc
);
4100 /* default vnic 0 */
4101 rc
= bnxt_hwrm_vnic_alloc(bp
, 0, 0, bp
->rx_nr_rings
);
4103 netdev_err(bp
->dev
, "hwrm vnic alloc failure rc: %x\n", rc
);
4107 rc
= bnxt_setup_vnic(bp
, 0);
4111 if (bp
->flags
& BNXT_FLAG_RFS
) {
4112 rc
= bnxt_alloc_rfs_vnics(bp
);
4117 if (bp
->flags
& BNXT_FLAG_TPA
) {
4118 rc
= bnxt_set_tpa(bp
, true);
4124 bnxt_update_vf_mac(bp
);
4126 /* Filter for default vnic 0 */
4127 rc
= bnxt_hwrm_set_vnic_filter(bp
, 0, 0, bp
->dev
->dev_addr
);
4129 netdev_err(bp
->dev
, "HWRM vnic filter failure rc: %x\n", rc
);
4132 bp
->vnic_info
[0].uc_filter_count
= 1;
4134 bp
->vnic_info
[0].rx_mask
= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST
;
4136 if ((bp
->dev
->flags
& IFF_PROMISC
) && BNXT_PF(bp
))
4137 bp
->vnic_info
[0].rx_mask
|=
4138 CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
;
4140 rc
= bnxt_cfg_rx_mode(bp
);
4144 rc
= bnxt_hwrm_set_coal(bp
);
4146 netdev_warn(bp
->dev
, "HWRM set coalescing failure rc: %x\n",
4152 bnxt_hwrm_resource_free(bp
, 0, true);
4157 static int bnxt_shutdown_nic(struct bnxt
*bp
, bool irq_re_init
)
4159 bnxt_hwrm_resource_free(bp
, 1, irq_re_init
);
4163 static int bnxt_init_nic(struct bnxt
*bp
, bool irq_re_init
)
4165 bnxt_init_rx_rings(bp
);
4166 bnxt_init_tx_rings(bp
);
4167 bnxt_init_ring_grps(bp
, irq_re_init
);
4168 bnxt_init_vnics(bp
);
4170 return bnxt_init_chip(bp
, irq_re_init
);
4173 static void bnxt_disable_int(struct bnxt
*bp
)
4180 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4181 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4182 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
4184 BNXT_CP_DB(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
4188 static void bnxt_enable_int(struct bnxt
*bp
)
4192 atomic_set(&bp
->intr_sem
, 0);
4193 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4194 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4195 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
4197 BNXT_CP_DB_REARM(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
4201 static int bnxt_set_real_num_queues(struct bnxt
*bp
)
4204 struct net_device
*dev
= bp
->dev
;
4206 rc
= netif_set_real_num_tx_queues(dev
, bp
->tx_nr_rings
);
4210 rc
= netif_set_real_num_rx_queues(dev
, bp
->rx_nr_rings
);
4214 #ifdef CONFIG_RFS_ACCEL
4215 if (bp
->flags
& BNXT_FLAG_RFS
)
4216 dev
->rx_cpu_rmap
= alloc_irq_cpu_rmap(bp
->rx_nr_rings
);
4222 static int bnxt_trim_rings(struct bnxt
*bp
, int *rx
, int *tx
, int max
,
4225 int _rx
= *rx
, _tx
= *tx
;
4228 *rx
= min_t(int, _rx
, max
);
4229 *tx
= min_t(int, _tx
, max
);
4234 while (_rx
+ _tx
> max
) {
4235 if (_rx
> _tx
&& _rx
> 1)
4246 static int bnxt_setup_msix(struct bnxt
*bp
)
4248 struct msix_entry
*msix_ent
;
4249 struct net_device
*dev
= bp
->dev
;
4250 int i
, total_vecs
, rc
= 0, min
= 1;
4251 const int len
= sizeof(bp
->irq_tbl
[0].name
);
4253 bp
->flags
&= ~BNXT_FLAG_USING_MSIX
;
4254 total_vecs
= bp
->cp_nr_rings
;
4256 msix_ent
= kcalloc(total_vecs
, sizeof(struct msix_entry
), GFP_KERNEL
);
4260 for (i
= 0; i
< total_vecs
; i
++) {
4261 msix_ent
[i
].entry
= i
;
4262 msix_ent
[i
].vector
= 0;
4265 if (!(bp
->flags
& BNXT_FLAG_SHARED_RINGS
))
4268 total_vecs
= pci_enable_msix_range(bp
->pdev
, msix_ent
, min
, total_vecs
);
4269 if (total_vecs
< 0) {
4271 goto msix_setup_exit
;
4274 bp
->irq_tbl
= kcalloc(total_vecs
, sizeof(struct bnxt_irq
), GFP_KERNEL
);
4278 /* Trim rings based upon num of vectors allocated */
4279 rc
= bnxt_trim_rings(bp
, &bp
->rx_nr_rings
, &bp
->tx_nr_rings
,
4280 total_vecs
, min
== 1);
4282 goto msix_setup_exit
;
4284 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
;
4285 tcs
= netdev_get_num_tc(dev
);
4287 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
/ tcs
;
4288 if (bp
->tx_nr_rings_per_tc
== 0) {
4289 netdev_reset_tc(dev
);
4290 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
;
4294 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
* tcs
;
4295 for (i
= 0; i
< tcs
; i
++) {
4296 count
= bp
->tx_nr_rings_per_tc
;
4298 netdev_set_tc_queue(dev
, i
, count
, off
);
4302 bp
->cp_nr_rings
= total_vecs
;
4304 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4307 bp
->irq_tbl
[i
].vector
= msix_ent
[i
].vector
;
4308 if (bp
->flags
& BNXT_FLAG_SHARED_RINGS
)
4310 else if (i
< bp
->rx_nr_rings
)
4315 snprintf(bp
->irq_tbl
[i
].name
, len
,
4316 "%s-%s-%d", dev
->name
, attr
, i
);
4317 bp
->irq_tbl
[i
].handler
= bnxt_msix
;
4319 rc
= bnxt_set_real_num_queues(bp
);
4321 goto msix_setup_exit
;
4324 goto msix_setup_exit
;
4326 bp
->flags
|= BNXT_FLAG_USING_MSIX
;
4331 netdev_err(bp
->dev
, "bnxt_setup_msix err: %x\n", rc
);
4332 pci_disable_msix(bp
->pdev
);
4337 static int bnxt_setup_inta(struct bnxt
*bp
)
4340 const int len
= sizeof(bp
->irq_tbl
[0].name
);
4342 if (netdev_get_num_tc(bp
->dev
))
4343 netdev_reset_tc(bp
->dev
);
4345 bp
->irq_tbl
= kcalloc(1, sizeof(struct bnxt_irq
), GFP_KERNEL
);
4350 bp
->rx_nr_rings
= 1;
4351 bp
->tx_nr_rings
= 1;
4352 bp
->cp_nr_rings
= 1;
4353 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
;
4354 bp
->flags
|= BNXT_FLAG_SHARED_RINGS
;
4355 bp
->irq_tbl
[0].vector
= bp
->pdev
->irq
;
4356 snprintf(bp
->irq_tbl
[0].name
, len
,
4357 "%s-%s-%d", bp
->dev
->name
, "TxRx", 0);
4358 bp
->irq_tbl
[0].handler
= bnxt_inta
;
4359 rc
= bnxt_set_real_num_queues(bp
);
4363 static int bnxt_setup_int_mode(struct bnxt
*bp
)
4367 if (bp
->flags
& BNXT_FLAG_MSIX_CAP
)
4368 rc
= bnxt_setup_msix(bp
);
4370 if (!(bp
->flags
& BNXT_FLAG_USING_MSIX
)) {
4371 /* fallback to INTA */
4372 rc
= bnxt_setup_inta(bp
);
4377 static void bnxt_free_irq(struct bnxt
*bp
)
4379 struct bnxt_irq
*irq
;
4382 #ifdef CONFIG_RFS_ACCEL
4383 free_irq_cpu_rmap(bp
->dev
->rx_cpu_rmap
);
4384 bp
->dev
->rx_cpu_rmap
= NULL
;
4389 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4390 irq
= &bp
->irq_tbl
[i
];
4392 free_irq(irq
->vector
, bp
->bnapi
[i
]);
4395 if (bp
->flags
& BNXT_FLAG_USING_MSIX
)
4396 pci_disable_msix(bp
->pdev
);
4401 static int bnxt_request_irq(struct bnxt
*bp
)
4404 unsigned long flags
= 0;
4405 #ifdef CONFIG_RFS_ACCEL
4406 struct cpu_rmap
*rmap
= bp
->dev
->rx_cpu_rmap
;
4409 if (!(bp
->flags
& BNXT_FLAG_USING_MSIX
))
4410 flags
= IRQF_SHARED
;
4412 for (i
= 0, j
= 0; i
< bp
->cp_nr_rings
; i
++) {
4413 struct bnxt_irq
*irq
= &bp
->irq_tbl
[i
];
4414 #ifdef CONFIG_RFS_ACCEL
4415 if (rmap
&& bp
->bnapi
[i
]->rx_ring
) {
4416 rc
= irq_cpu_rmap_add(rmap
, irq
->vector
);
4418 netdev_warn(bp
->dev
, "failed adding irq rmap for ring %d\n",
4423 rc
= request_irq(irq
->vector
, irq
->handler
, flags
, irq
->name
,
4433 static void bnxt_del_napi(struct bnxt
*bp
)
4440 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4441 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4443 napi_hash_del(&bnapi
->napi
);
4444 netif_napi_del(&bnapi
->napi
);
4448 static void bnxt_init_napi(struct bnxt
*bp
)
4451 struct bnxt_napi
*bnapi
;
4453 if (bp
->flags
& BNXT_FLAG_USING_MSIX
) {
4454 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4455 bnapi
= bp
->bnapi
[i
];
4456 netif_napi_add(bp
->dev
, &bnapi
->napi
,
4460 bnapi
= bp
->bnapi
[0];
4461 netif_napi_add(bp
->dev
, &bnapi
->napi
, bnxt_poll
, 64);
4465 static void bnxt_disable_napi(struct bnxt
*bp
)
4472 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4473 napi_disable(&bp
->bnapi
[i
]->napi
);
4474 bnxt_disable_poll(bp
->bnapi
[i
]);
4478 static void bnxt_enable_napi(struct bnxt
*bp
)
4482 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4483 bnxt_enable_poll(bp
->bnapi
[i
]);
4484 napi_enable(&bp
->bnapi
[i
]->napi
);
4488 static void bnxt_tx_disable(struct bnxt
*bp
)
4491 struct bnxt_tx_ring_info
*txr
;
4492 struct netdev_queue
*txq
;
4495 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
4496 txr
= &bp
->tx_ring
[i
];
4497 txq
= netdev_get_tx_queue(bp
->dev
, i
);
4498 __netif_tx_lock(txq
, smp_processor_id());
4499 txr
->dev_state
= BNXT_DEV_STATE_CLOSING
;
4500 __netif_tx_unlock(txq
);
4503 /* Stop all TX queues */
4504 netif_tx_disable(bp
->dev
);
4505 netif_carrier_off(bp
->dev
);
4508 static void bnxt_tx_enable(struct bnxt
*bp
)
4511 struct bnxt_tx_ring_info
*txr
;
4512 struct netdev_queue
*txq
;
4514 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
4515 txr
= &bp
->tx_ring
[i
];
4516 txq
= netdev_get_tx_queue(bp
->dev
, i
);
4519 netif_tx_wake_all_queues(bp
->dev
);
4520 if (bp
->link_info
.link_up
)
4521 netif_carrier_on(bp
->dev
);
4524 static void bnxt_report_link(struct bnxt
*bp
)
4526 if (bp
->link_info
.link_up
) {
4528 const char *flow_ctrl
;
4531 netif_carrier_on(bp
->dev
);
4532 if (bp
->link_info
.duplex
== BNXT_LINK_DUPLEX_FULL
)
4536 if (bp
->link_info
.pause
== BNXT_LINK_PAUSE_BOTH
)
4537 flow_ctrl
= "ON - receive & transmit";
4538 else if (bp
->link_info
.pause
== BNXT_LINK_PAUSE_TX
)
4539 flow_ctrl
= "ON - transmit";
4540 else if (bp
->link_info
.pause
== BNXT_LINK_PAUSE_RX
)
4541 flow_ctrl
= "ON - receive";
4544 speed
= bnxt_fw_to_ethtool_speed(bp
->link_info
.link_speed
);
4545 netdev_info(bp
->dev
, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
4546 speed
, duplex
, flow_ctrl
);
4547 if (bp
->flags
& BNXT_FLAG_EEE_CAP
)
4548 netdev_info(bp
->dev
, "EEE is %s\n",
4549 bp
->eee
.eee_active
? "active" :
4552 netif_carrier_off(bp
->dev
);
4553 netdev_err(bp
->dev
, "NIC Link is Down\n");
4557 static int bnxt_hwrm_phy_qcaps(struct bnxt
*bp
)
4560 struct hwrm_port_phy_qcaps_input req
= {0};
4561 struct hwrm_port_phy_qcaps_output
*resp
= bp
->hwrm_cmd_resp_addr
;
4563 if (bp
->hwrm_spec_code
< 0x10201)
4566 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_QCAPS
, -1, -1);
4568 mutex_lock(&bp
->hwrm_cmd_lock
);
4569 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4571 goto hwrm_phy_qcaps_exit
;
4573 if (resp
->eee_supported
& PORT_PHY_QCAPS_RESP_EEE_SUPPORTED
) {
4574 struct ethtool_eee
*eee
= &bp
->eee
;
4575 u16 fw_speeds
= le16_to_cpu(resp
->supported_speeds_eee_mode
);
4577 bp
->flags
|= BNXT_FLAG_EEE_CAP
;
4578 eee
->supported
= _bnxt_fw_to_ethtool_adv_spds(fw_speeds
, 0);
4579 bp
->lpi_tmr_lo
= le32_to_cpu(resp
->tx_lpi_timer_low
) &
4580 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK
;
4581 bp
->lpi_tmr_hi
= le32_to_cpu(resp
->valid_tx_lpi_timer_high
) &
4582 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK
;
4585 hwrm_phy_qcaps_exit
:
4586 mutex_unlock(&bp
->hwrm_cmd_lock
);
4590 static int bnxt_update_link(struct bnxt
*bp
, bool chng_link_state
)
4593 struct bnxt_link_info
*link_info
= &bp
->link_info
;
4594 struct hwrm_port_phy_qcfg_input req
= {0};
4595 struct hwrm_port_phy_qcfg_output
*resp
= bp
->hwrm_cmd_resp_addr
;
4596 u8 link_up
= link_info
->link_up
;
4598 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_QCFG
, -1, -1);
4600 mutex_lock(&bp
->hwrm_cmd_lock
);
4601 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4603 mutex_unlock(&bp
->hwrm_cmd_lock
);
4607 memcpy(&link_info
->phy_qcfg_resp
, resp
, sizeof(*resp
));
4608 link_info
->phy_link_status
= resp
->link
;
4609 link_info
->duplex
= resp
->duplex
;
4610 link_info
->pause
= resp
->pause
;
4611 link_info
->auto_mode
= resp
->auto_mode
;
4612 link_info
->auto_pause_setting
= resp
->auto_pause
;
4613 link_info
->lp_pause
= resp
->link_partner_adv_pause
;
4614 link_info
->force_pause_setting
= resp
->force_pause
;
4615 link_info
->duplex_setting
= resp
->duplex
;
4616 if (link_info
->phy_link_status
== BNXT_LINK_LINK
)
4617 link_info
->link_speed
= le16_to_cpu(resp
->link_speed
);
4619 link_info
->link_speed
= 0;
4620 link_info
->force_link_speed
= le16_to_cpu(resp
->force_link_speed
);
4621 link_info
->support_speeds
= le16_to_cpu(resp
->support_speeds
);
4622 link_info
->auto_link_speeds
= le16_to_cpu(resp
->auto_link_speed_mask
);
4623 link_info
->lp_auto_link_speeds
=
4624 le16_to_cpu(resp
->link_partner_adv_speeds
);
4625 link_info
->preemphasis
= le32_to_cpu(resp
->preemphasis
);
4626 link_info
->phy_ver
[0] = resp
->phy_maj
;
4627 link_info
->phy_ver
[1] = resp
->phy_min
;
4628 link_info
->phy_ver
[2] = resp
->phy_bld
;
4629 link_info
->media_type
= resp
->media_type
;
4630 link_info
->phy_type
= resp
->phy_type
;
4631 link_info
->transceiver
= resp
->xcvr_pkg_type
;
4632 link_info
->phy_addr
= resp
->eee_config_phy_addr
&
4633 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK
;
4635 if (bp
->flags
& BNXT_FLAG_EEE_CAP
) {
4636 struct ethtool_eee
*eee
= &bp
->eee
;
4639 eee
->eee_active
= 0;
4640 if (resp
->eee_config_phy_addr
&
4641 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE
) {
4642 eee
->eee_active
= 1;
4643 fw_speeds
= le16_to_cpu(
4644 resp
->link_partner_adv_eee_link_speed_mask
);
4645 eee
->lp_advertised
=
4646 _bnxt_fw_to_ethtool_adv_spds(fw_speeds
, 0);
4649 /* Pull initial EEE config */
4650 if (!chng_link_state
) {
4651 if (resp
->eee_config_phy_addr
&
4652 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED
)
4653 eee
->eee_enabled
= 1;
4655 fw_speeds
= le16_to_cpu(resp
->adv_eee_link_speed_mask
);
4657 _bnxt_fw_to_ethtool_adv_spds(fw_speeds
, 0);
4659 if (resp
->eee_config_phy_addr
&
4660 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI
) {
4663 eee
->tx_lpi_enabled
= 1;
4664 tmr
= resp
->xcvr_identifier_type_tx_lpi_timer
;
4665 eee
->tx_lpi_timer
= le32_to_cpu(tmr
) &
4666 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK
;
4670 /* TODO: need to add more logic to report VF link */
4671 if (chng_link_state
) {
4672 if (link_info
->phy_link_status
== BNXT_LINK_LINK
)
4673 link_info
->link_up
= 1;
4675 link_info
->link_up
= 0;
4676 if (link_up
!= link_info
->link_up
)
4677 bnxt_report_link(bp
);
4679 /* alwasy link down if not require to update link state */
4680 link_info
->link_up
= 0;
4682 mutex_unlock(&bp
->hwrm_cmd_lock
);
4687 bnxt_hwrm_set_pause_common(struct bnxt
*bp
, struct hwrm_port_phy_cfg_input
*req
)
4689 if (bp
->link_info
.autoneg
& BNXT_AUTONEG_FLOW_CTRL
) {
4690 if (bp
->hwrm_spec_code
>= 0x10201)
4692 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE
;
4693 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_RX
)
4694 req
->auto_pause
|= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX
;
4695 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_TX
)
4696 req
->auto_pause
|= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX
;
4698 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE
);
4700 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_RX
)
4701 req
->force_pause
|= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX
;
4702 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_TX
)
4703 req
->force_pause
|= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX
;
4705 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE
);
4706 if (bp
->hwrm_spec_code
>= 0x10201) {
4707 req
->auto_pause
= req
->force_pause
;
4708 req
->enables
|= cpu_to_le32(
4709 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE
);
4714 static void bnxt_hwrm_set_link_common(struct bnxt
*bp
,
4715 struct hwrm_port_phy_cfg_input
*req
)
4717 u8 autoneg
= bp
->link_info
.autoneg
;
4718 u16 fw_link_speed
= bp
->link_info
.req_link_speed
;
4719 u32 advertising
= bp
->link_info
.advertising
;
4721 if (autoneg
& BNXT_AUTONEG_SPEED
) {
4723 PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK
;
4725 req
->enables
|= cpu_to_le32(
4726 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK
);
4727 req
->auto_link_speed_mask
= cpu_to_le16(advertising
);
4729 req
->enables
|= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE
);
4731 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG
);
4733 req
->force_link_speed
= cpu_to_le16(fw_link_speed
);
4734 req
->flags
|= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE
);
4737 /* tell chimp that the setting takes effect immediately */
4738 req
->flags
|= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY
);
4741 int bnxt_hwrm_set_pause(struct bnxt
*bp
)
4743 struct hwrm_port_phy_cfg_input req
= {0};
4746 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_CFG
, -1, -1);
4747 bnxt_hwrm_set_pause_common(bp
, &req
);
4749 if ((bp
->link_info
.autoneg
& BNXT_AUTONEG_FLOW_CTRL
) ||
4750 bp
->link_info
.force_link_chng
)
4751 bnxt_hwrm_set_link_common(bp
, &req
);
4753 mutex_lock(&bp
->hwrm_cmd_lock
);
4754 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4755 if (!rc
&& !(bp
->link_info
.autoneg
& BNXT_AUTONEG_FLOW_CTRL
)) {
4756 /* since changing of pause setting doesn't trigger any link
4757 * change event, the driver needs to update the current pause
4758 * result upon successfully return of the phy_cfg command
4760 bp
->link_info
.pause
=
4761 bp
->link_info
.force_pause_setting
= bp
->link_info
.req_flow_ctrl
;
4762 bp
->link_info
.auto_pause_setting
= 0;
4763 if (!bp
->link_info
.force_link_chng
)
4764 bnxt_report_link(bp
);
4766 bp
->link_info
.force_link_chng
= false;
4767 mutex_unlock(&bp
->hwrm_cmd_lock
);
4771 static void bnxt_hwrm_set_eee(struct bnxt
*bp
,
4772 struct hwrm_port_phy_cfg_input
*req
)
4774 struct ethtool_eee
*eee
= &bp
->eee
;
4776 if (eee
->eee_enabled
) {
4778 u32 flags
= PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE
;
4780 if (eee
->tx_lpi_enabled
)
4781 flags
|= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE
;
4783 flags
|= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE
;
4785 req
->flags
|= cpu_to_le32(flags
);
4786 eee_speeds
= bnxt_get_fw_auto_link_speeds(eee
->advertised
);
4787 req
->eee_link_speed_mask
= cpu_to_le16(eee_speeds
);
4788 req
->tx_lpi_timer
= cpu_to_le32(eee
->tx_lpi_timer
);
4790 req
->flags
|= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE
);
4794 int bnxt_hwrm_set_link_setting(struct bnxt
*bp
, bool set_pause
, bool set_eee
)
4796 struct hwrm_port_phy_cfg_input req
= {0};
4798 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_CFG
, -1, -1);
4800 bnxt_hwrm_set_pause_common(bp
, &req
);
4802 bnxt_hwrm_set_link_common(bp
, &req
);
4805 bnxt_hwrm_set_eee(bp
, &req
);
4806 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4809 static int bnxt_hwrm_shutdown_link(struct bnxt
*bp
)
4811 struct hwrm_port_phy_cfg_input req
= {0};
4816 if (pci_num_vf(bp
->pdev
))
4819 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_CFG
, -1, -1);
4820 req
.flags
= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DOWN
);
4821 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4824 static bool bnxt_eee_config_ok(struct bnxt
*bp
)
4826 struct ethtool_eee
*eee
= &bp
->eee
;
4827 struct bnxt_link_info
*link_info
= &bp
->link_info
;
4829 if (!(bp
->flags
& BNXT_FLAG_EEE_CAP
))
4832 if (eee
->eee_enabled
) {
4834 _bnxt_fw_to_ethtool_adv_spds(link_info
->advertising
, 0);
4836 if (!(link_info
->autoneg
& BNXT_AUTONEG_SPEED
)) {
4837 eee
->eee_enabled
= 0;
4840 if (eee
->advertised
& ~advertising
) {
4841 eee
->advertised
= advertising
& eee
->supported
;
4848 static int bnxt_update_phy_setting(struct bnxt
*bp
)
4851 bool update_link
= false;
4852 bool update_pause
= false;
4853 bool update_eee
= false;
4854 struct bnxt_link_info
*link_info
= &bp
->link_info
;
4856 rc
= bnxt_update_link(bp
, true);
4858 netdev_err(bp
->dev
, "failed to update link (rc: %x)\n",
4862 if ((link_info
->autoneg
& BNXT_AUTONEG_FLOW_CTRL
) &&
4863 (link_info
->auto_pause_setting
& BNXT_LINK_PAUSE_BOTH
) !=
4864 link_info
->req_flow_ctrl
)
4865 update_pause
= true;
4866 if (!(link_info
->autoneg
& BNXT_AUTONEG_FLOW_CTRL
) &&
4867 link_info
->force_pause_setting
!= link_info
->req_flow_ctrl
)
4868 update_pause
= true;
4869 if (!(link_info
->autoneg
& BNXT_AUTONEG_SPEED
)) {
4870 if (BNXT_AUTO_MODE(link_info
->auto_mode
))
4872 if (link_info
->req_link_speed
!= link_info
->force_link_speed
)
4874 if (link_info
->req_duplex
!= link_info
->duplex_setting
)
4877 if (link_info
->auto_mode
== BNXT_LINK_AUTO_NONE
)
4879 if (link_info
->advertising
!= link_info
->auto_link_speeds
)
4883 if (!bnxt_eee_config_ok(bp
))
4887 rc
= bnxt_hwrm_set_link_setting(bp
, update_pause
, update_eee
);
4888 else if (update_pause
)
4889 rc
= bnxt_hwrm_set_pause(bp
);
4891 netdev_err(bp
->dev
, "failed to update phy setting (rc: %x)\n",
4899 /* Common routine to pre-map certain register block to different GRC window.
4900 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
4901 * in PF and 3 windows in VF that can be customized to map in different
4904 static void bnxt_preset_reg_win(struct bnxt
*bp
)
4907 /* CAG registers map to GRC window #4 */
4908 writel(BNXT_CAG_REG_BASE
,
4909 bp
->bar0
+ BNXT_GRCPF_REG_WINDOW_BASE_OUT
+ 12);
4913 static int __bnxt_open_nic(struct bnxt
*bp
, bool irq_re_init
, bool link_re_init
)
4917 bnxt_preset_reg_win(bp
);
4918 netif_carrier_off(bp
->dev
);
4920 rc
= bnxt_setup_int_mode(bp
);
4922 netdev_err(bp
->dev
, "bnxt_setup_int_mode err: %x\n",
4927 if ((bp
->flags
& BNXT_FLAG_RFS
) &&
4928 !(bp
->flags
& BNXT_FLAG_USING_MSIX
)) {
4929 /* disable RFS if falling back to INTA */
4930 bp
->dev
->hw_features
&= ~NETIF_F_NTUPLE
;
4931 bp
->flags
&= ~BNXT_FLAG_RFS
;
4934 rc
= bnxt_alloc_mem(bp
, irq_re_init
);
4936 netdev_err(bp
->dev
, "bnxt_alloc_mem err: %x\n", rc
);
4937 goto open_err_free_mem
;
4942 rc
= bnxt_request_irq(bp
);
4944 netdev_err(bp
->dev
, "bnxt_request_irq err: %x\n", rc
);
4949 bnxt_enable_napi(bp
);
4951 rc
= bnxt_init_nic(bp
, irq_re_init
);
4953 netdev_err(bp
->dev
, "bnxt_init_nic err: %x\n", rc
);
4958 rc
= bnxt_update_phy_setting(bp
);
4960 netdev_warn(bp
->dev
, "failed to update phy settings\n");
4964 #if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE)
4965 vxlan_get_rx_port(bp
->dev
);
4967 if (!bnxt_hwrm_tunnel_dst_port_alloc(
4969 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
))
4970 bp
->nge_port_cnt
= 1;
4973 set_bit(BNXT_STATE_OPEN
, &bp
->state
);
4974 bnxt_enable_int(bp
);
4975 /* Enable TX queues */
4977 mod_timer(&bp
->timer
, jiffies
+ bp
->current_interval
);
4978 bnxt_update_link(bp
, true);
4983 bnxt_disable_napi(bp
);
4989 bnxt_free_mem(bp
, true);
4993 /* rtnl_lock held */
4994 int bnxt_open_nic(struct bnxt
*bp
, bool irq_re_init
, bool link_re_init
)
4998 rc
= __bnxt_open_nic(bp
, irq_re_init
, link_re_init
);
5000 netdev_err(bp
->dev
, "nic open fail (rc: %x)\n", rc
);
5006 static int bnxt_open(struct net_device
*dev
)
5008 struct bnxt
*bp
= netdev_priv(dev
);
5011 rc
= bnxt_hwrm_func_reset(bp
);
5013 netdev_err(bp
->dev
, "hwrm chip reset failure rc: %x\n",
5018 return __bnxt_open_nic(bp
, true, true);
5021 static void bnxt_disable_int_sync(struct bnxt
*bp
)
5025 atomic_inc(&bp
->intr_sem
);
5026 if (!netif_running(bp
->dev
))
5029 bnxt_disable_int(bp
);
5030 for (i
= 0; i
< bp
->cp_nr_rings
; i
++)
5031 synchronize_irq(bp
->irq_tbl
[i
].vector
);
5034 int bnxt_close_nic(struct bnxt
*bp
, bool irq_re_init
, bool link_re_init
)
5038 #ifdef CONFIG_BNXT_SRIOV
5039 if (bp
->sriov_cfg
) {
5040 rc
= wait_event_interruptible_timeout(bp
->sriov_cfg_wait
,
5042 BNXT_SRIOV_CFG_WAIT_TMO
);
5044 netdev_warn(bp
->dev
, "timeout waiting for SRIOV config operation to complete!\n");
5047 /* Change device state to avoid TX queue wake up's */
5048 bnxt_tx_disable(bp
);
5050 clear_bit(BNXT_STATE_OPEN
, &bp
->state
);
5051 smp_mb__after_atomic();
5052 while (test_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
))
5055 /* Flush rings before disabling interrupts */
5056 bnxt_shutdown_nic(bp
, irq_re_init
);
5058 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
5060 bnxt_disable_napi(bp
);
5061 bnxt_disable_int_sync(bp
);
5062 del_timer_sync(&bp
->timer
);
5069 bnxt_free_mem(bp
, irq_re_init
);
5073 static int bnxt_close(struct net_device
*dev
)
5075 struct bnxt
*bp
= netdev_priv(dev
);
5077 bnxt_close_nic(bp
, true, true);
5078 bnxt_hwrm_shutdown_link(bp
);
5082 /* rtnl_lock held */
5083 static int bnxt_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
5089 if (!netif_running(dev
))
5096 if (!netif_running(dev
))
5108 static struct rtnl_link_stats64
*
5109 bnxt_get_stats64(struct net_device
*dev
, struct rtnl_link_stats64
*stats
)
5112 struct bnxt
*bp
= netdev_priv(dev
);
5114 memset(stats
, 0, sizeof(struct rtnl_link_stats64
));
5119 /* TODO check if we need to synchronize with bnxt_close path */
5120 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
5121 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
5122 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
5123 struct ctx_hw_stats
*hw_stats
= cpr
->hw_stats
;
5125 stats
->rx_packets
+= le64_to_cpu(hw_stats
->rx_ucast_pkts
);
5126 stats
->rx_packets
+= le64_to_cpu(hw_stats
->rx_mcast_pkts
);
5127 stats
->rx_packets
+= le64_to_cpu(hw_stats
->rx_bcast_pkts
);
5129 stats
->tx_packets
+= le64_to_cpu(hw_stats
->tx_ucast_pkts
);
5130 stats
->tx_packets
+= le64_to_cpu(hw_stats
->tx_mcast_pkts
);
5131 stats
->tx_packets
+= le64_to_cpu(hw_stats
->tx_bcast_pkts
);
5133 stats
->rx_bytes
+= le64_to_cpu(hw_stats
->rx_ucast_bytes
);
5134 stats
->rx_bytes
+= le64_to_cpu(hw_stats
->rx_mcast_bytes
);
5135 stats
->rx_bytes
+= le64_to_cpu(hw_stats
->rx_bcast_bytes
);
5137 stats
->tx_bytes
+= le64_to_cpu(hw_stats
->tx_ucast_bytes
);
5138 stats
->tx_bytes
+= le64_to_cpu(hw_stats
->tx_mcast_bytes
);
5139 stats
->tx_bytes
+= le64_to_cpu(hw_stats
->tx_bcast_bytes
);
5141 stats
->rx_missed_errors
+=
5142 le64_to_cpu(hw_stats
->rx_discard_pkts
);
5144 stats
->multicast
+= le64_to_cpu(hw_stats
->rx_mcast_pkts
);
5146 stats
->tx_dropped
+= le64_to_cpu(hw_stats
->tx_drop_pkts
);
5149 if (bp
->flags
& BNXT_FLAG_PORT_STATS
) {
5150 struct rx_port_stats
*rx
= bp
->hw_rx_port_stats
;
5151 struct tx_port_stats
*tx
= bp
->hw_tx_port_stats
;
5153 stats
->rx_crc_errors
= le64_to_cpu(rx
->rx_fcs_err_frames
);
5154 stats
->rx_frame_errors
= le64_to_cpu(rx
->rx_align_err_frames
);
5155 stats
->rx_length_errors
= le64_to_cpu(rx
->rx_undrsz_frames
) +
5156 le64_to_cpu(rx
->rx_ovrsz_frames
) +
5157 le64_to_cpu(rx
->rx_runt_frames
);
5158 stats
->rx_errors
= le64_to_cpu(rx
->rx_false_carrier_frames
) +
5159 le64_to_cpu(rx
->rx_jbr_frames
);
5160 stats
->collisions
= le64_to_cpu(tx
->tx_total_collisions
);
5161 stats
->tx_fifo_errors
= le64_to_cpu(tx
->tx_fifo_underruns
);
5162 stats
->tx_errors
= le64_to_cpu(tx
->tx_err
);
5168 static bool bnxt_mc_list_updated(struct bnxt
*bp
, u32
*rx_mask
)
5170 struct net_device
*dev
= bp
->dev
;
5171 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
5172 struct netdev_hw_addr
*ha
;
5175 bool update
= false;
5178 netdev_for_each_mc_addr(ha
, dev
) {
5179 if (mc_count
>= BNXT_MAX_MC_ADDRS
) {
5180 *rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
;
5181 vnic
->mc_list_count
= 0;
5185 if (!ether_addr_equal(haddr
, vnic
->mc_list
+ off
)) {
5186 memcpy(vnic
->mc_list
+ off
, haddr
, ETH_ALEN
);
5193 *rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST
;
5195 if (mc_count
!= vnic
->mc_list_count
) {
5196 vnic
->mc_list_count
= mc_count
;
5202 static bool bnxt_uc_list_updated(struct bnxt
*bp
)
5204 struct net_device
*dev
= bp
->dev
;
5205 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
5206 struct netdev_hw_addr
*ha
;
5209 if (netdev_uc_count(dev
) != (vnic
->uc_filter_count
- 1))
5212 netdev_for_each_uc_addr(ha
, dev
) {
5213 if (!ether_addr_equal(ha
->addr
, vnic
->uc_list
+ off
))
5221 static void bnxt_set_rx_mode(struct net_device
*dev
)
5223 struct bnxt
*bp
= netdev_priv(dev
);
5224 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
5225 u32 mask
= vnic
->rx_mask
;
5226 bool mc_update
= false;
5229 if (!netif_running(dev
))
5232 mask
&= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
|
5233 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST
|
5234 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
);
5236 /* Only allow PF to be in promiscuous mode */
5237 if ((dev
->flags
& IFF_PROMISC
) && BNXT_PF(bp
))
5238 mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
;
5240 uc_update
= bnxt_uc_list_updated(bp
);
5242 if (dev
->flags
& IFF_ALLMULTI
) {
5243 mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
;
5244 vnic
->mc_list_count
= 0;
5246 mc_update
= bnxt_mc_list_updated(bp
, &mask
);
5249 if (mask
!= vnic
->rx_mask
|| uc_update
|| mc_update
) {
5250 vnic
->rx_mask
= mask
;
5252 set_bit(BNXT_RX_MASK_SP_EVENT
, &bp
->sp_event
);
5253 schedule_work(&bp
->sp_task
);
5257 static int bnxt_cfg_rx_mode(struct bnxt
*bp
)
5259 struct net_device
*dev
= bp
->dev
;
5260 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
5261 struct netdev_hw_addr
*ha
;
5265 netif_addr_lock_bh(dev
);
5266 uc_update
= bnxt_uc_list_updated(bp
);
5267 netif_addr_unlock_bh(dev
);
5272 mutex_lock(&bp
->hwrm_cmd_lock
);
5273 for (i
= 1; i
< vnic
->uc_filter_count
; i
++) {
5274 struct hwrm_cfa_l2_filter_free_input req
= {0};
5276 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_L2_FILTER_FREE
, -1,
5279 req
.l2_filter_id
= vnic
->fw_l2_filter_id
[i
];
5281 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
5284 mutex_unlock(&bp
->hwrm_cmd_lock
);
5286 vnic
->uc_filter_count
= 1;
5288 netif_addr_lock_bh(dev
);
5289 if (netdev_uc_count(dev
) > (BNXT_MAX_UC_ADDRS
- 1)) {
5290 vnic
->rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
;
5292 netdev_for_each_uc_addr(ha
, dev
) {
5293 memcpy(vnic
->uc_list
+ off
, ha
->addr
, ETH_ALEN
);
5295 vnic
->uc_filter_count
++;
5298 netif_addr_unlock_bh(dev
);
5300 for (i
= 1, off
= 0; i
< vnic
->uc_filter_count
; i
++, off
+= ETH_ALEN
) {
5301 rc
= bnxt_hwrm_set_vnic_filter(bp
, 0, i
, vnic
->uc_list
+ off
);
5303 netdev_err(bp
->dev
, "HWRM vnic filter failure rc: %x\n",
5305 vnic
->uc_filter_count
= i
;
5311 rc
= bnxt_hwrm_cfa_l2_set_rx_mask(bp
, 0);
5313 netdev_err(bp
->dev
, "HWRM cfa l2 rx mask failure rc: %x\n",
5319 static bool bnxt_rfs_capable(struct bnxt
*bp
)
5321 #ifdef CONFIG_RFS_ACCEL
5322 struct bnxt_pf_info
*pf
= &bp
->pf
;
5325 if (BNXT_VF(bp
) || !(bp
->flags
& BNXT_FLAG_MSIX_CAP
))
5328 vnics
= 1 + bp
->rx_nr_rings
;
5329 if (vnics
> pf
->max_rsscos_ctxs
|| vnics
> pf
->max_vnics
)
5338 static netdev_features_t
bnxt_fix_features(struct net_device
*dev
,
5339 netdev_features_t features
)
5341 struct bnxt
*bp
= netdev_priv(dev
);
5343 if (!bnxt_rfs_capable(bp
))
5344 features
&= ~NETIF_F_NTUPLE
;
5348 static int bnxt_set_features(struct net_device
*dev
, netdev_features_t features
)
5350 struct bnxt
*bp
= netdev_priv(dev
);
5351 u32 flags
= bp
->flags
;
5354 bool re_init
= false;
5355 bool update_tpa
= false;
5357 flags
&= ~BNXT_FLAG_ALL_CONFIG_FEATS
;
5358 if ((features
& NETIF_F_GRO
) && (bp
->pdev
->revision
> 0))
5359 flags
|= BNXT_FLAG_GRO
;
5360 if (features
& NETIF_F_LRO
)
5361 flags
|= BNXT_FLAG_LRO
;
5363 if (features
& NETIF_F_HW_VLAN_CTAG_RX
)
5364 flags
|= BNXT_FLAG_STRIP_VLAN
;
5366 if (features
& NETIF_F_NTUPLE
)
5367 flags
|= BNXT_FLAG_RFS
;
5369 changes
= flags
^ bp
->flags
;
5370 if (changes
& BNXT_FLAG_TPA
) {
5372 if ((bp
->flags
& BNXT_FLAG_TPA
) == 0 ||
5373 (flags
& BNXT_FLAG_TPA
) == 0)
5377 if (changes
& ~BNXT_FLAG_TPA
)
5380 if (flags
!= bp
->flags
) {
5381 u32 old_flags
= bp
->flags
;
5385 if (!test_bit(BNXT_STATE_OPEN
, &bp
->state
)) {
5387 bnxt_set_ring_params(bp
);
5392 bnxt_close_nic(bp
, false, false);
5394 bnxt_set_ring_params(bp
);
5396 return bnxt_open_nic(bp
, false, false);
5399 rc
= bnxt_set_tpa(bp
,
5400 (flags
& BNXT_FLAG_TPA
) ?
5403 bp
->flags
= old_flags
;
5409 static void bnxt_dump_tx_sw_state(struct bnxt_napi
*bnapi
)
5411 struct bnxt_tx_ring_info
*txr
= bnapi
->tx_ring
;
5412 int i
= bnapi
->index
;
5417 netdev_info(bnapi
->bp
->dev
, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
5418 i
, txr
->tx_ring_struct
.fw_ring_id
, txr
->tx_prod
,
5422 static void bnxt_dump_rx_sw_state(struct bnxt_napi
*bnapi
)
5424 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
5425 int i
= bnapi
->index
;
5430 netdev_info(bnapi
->bp
->dev
, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
5431 i
, rxr
->rx_ring_struct
.fw_ring_id
, rxr
->rx_prod
,
5432 rxr
->rx_agg_ring_struct
.fw_ring_id
, rxr
->rx_agg_prod
,
5433 rxr
->rx_sw_agg_prod
);
5436 static void bnxt_dump_cp_sw_state(struct bnxt_napi
*bnapi
)
5438 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
5439 int i
= bnapi
->index
;
5441 netdev_info(bnapi
->bp
->dev
, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
5442 i
, cpr
->cp_ring_struct
.fw_ring_id
, cpr
->cp_raw_cons
);
5445 static void bnxt_dbg_dump_states(struct bnxt
*bp
)
5448 struct bnxt_napi
*bnapi
;
5450 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
5451 bnapi
= bp
->bnapi
[i
];
5452 if (netif_msg_drv(bp
)) {
5453 bnxt_dump_tx_sw_state(bnapi
);
5454 bnxt_dump_rx_sw_state(bnapi
);
5455 bnxt_dump_cp_sw_state(bnapi
);
5460 static void bnxt_reset_task(struct bnxt
*bp
)
5462 bnxt_dbg_dump_states(bp
);
5463 if (netif_running(bp
->dev
)) {
5464 bnxt_close_nic(bp
, false, false);
5465 bnxt_open_nic(bp
, false, false);
5469 static void bnxt_tx_timeout(struct net_device
*dev
)
5471 struct bnxt
*bp
= netdev_priv(dev
);
5473 netdev_err(bp
->dev
, "TX timeout detected, starting reset task!\n");
5474 set_bit(BNXT_RESET_TASK_SP_EVENT
, &bp
->sp_event
);
5475 schedule_work(&bp
->sp_task
);
5478 #ifdef CONFIG_NET_POLL_CONTROLLER
5479 static void bnxt_poll_controller(struct net_device
*dev
)
5481 struct bnxt
*bp
= netdev_priv(dev
);
5484 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
5485 struct bnxt_irq
*irq
= &bp
->irq_tbl
[i
];
5487 disable_irq(irq
->vector
);
5488 irq
->handler(irq
->vector
, bp
->bnapi
[i
]);
5489 enable_irq(irq
->vector
);
5494 static void bnxt_timer(unsigned long data
)
5496 struct bnxt
*bp
= (struct bnxt
*)data
;
5497 struct net_device
*dev
= bp
->dev
;
5499 if (!netif_running(dev
))
5502 if (atomic_read(&bp
->intr_sem
) != 0)
5503 goto bnxt_restart_timer
;
5505 if (bp
->link_info
.link_up
&& (bp
->flags
& BNXT_FLAG_PORT_STATS
)) {
5506 set_bit(BNXT_PERIODIC_STATS_SP_EVENT
, &bp
->sp_event
);
5507 schedule_work(&bp
->sp_task
);
5510 mod_timer(&bp
->timer
, jiffies
+ bp
->current_interval
);
5513 static void bnxt_port_module_event(struct bnxt
*bp
)
5515 struct bnxt_link_info
*link_info
= &bp
->link_info
;
5516 struct hwrm_port_phy_qcfg_output
*resp
= &link_info
->phy_qcfg_resp
;
5518 if (bnxt_update_link(bp
, true))
5521 if (link_info
->last_port_module_event
!= 0) {
5522 netdev_warn(bp
->dev
, "Unqualified SFP+ module detected on port %d\n",
5524 if (bp
->hwrm_spec_code
>= 0x10201) {
5525 netdev_warn(bp
->dev
, "Module part number %s\n",
5526 resp
->phy_vendor_partnumber
);
5529 if (link_info
->last_port_module_event
== 1)
5530 netdev_warn(bp
->dev
, "TX is disabled\n");
5531 if (link_info
->last_port_module_event
== 3)
5532 netdev_warn(bp
->dev
, "Shutdown SFP+ module\n");
5535 static void bnxt_cfg_ntp_filters(struct bnxt
*);
5537 static void bnxt_sp_task(struct work_struct
*work
)
5539 struct bnxt
*bp
= container_of(work
, struct bnxt
, sp_task
);
5542 set_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
5543 smp_mb__after_atomic();
5544 if (!test_bit(BNXT_STATE_OPEN
, &bp
->state
)) {
5545 clear_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
5549 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT
, &bp
->sp_event
))
5550 bnxt_cfg_rx_mode(bp
);
5552 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT
, &bp
->sp_event
))
5553 bnxt_cfg_ntp_filters(bp
);
5554 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT
, &bp
->sp_event
)) {
5555 rc
= bnxt_update_link(bp
, true);
5557 netdev_err(bp
->dev
, "SP task can't update link (rc: %x)\n",
5560 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT
, &bp
->sp_event
))
5561 bnxt_hwrm_exec_fwd_req(bp
);
5562 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT
, &bp
->sp_event
)) {
5563 bnxt_hwrm_tunnel_dst_port_alloc(
5565 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
);
5567 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT
, &bp
->sp_event
)) {
5568 bnxt_hwrm_tunnel_dst_port_free(
5569 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
);
5571 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT
, &bp
->sp_event
)) {
5572 /* bnxt_reset_task() calls bnxt_close_nic() which waits
5573 * for BNXT_STATE_IN_SP_TASK to clear.
5575 clear_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
5577 bnxt_reset_task(bp
);
5578 set_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
5582 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT
, &bp
->sp_event
))
5583 bnxt_port_module_event(bp
);
5585 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT
, &bp
->sp_event
))
5586 bnxt_hwrm_port_qstats(bp
);
5588 smp_mb__before_atomic();
5589 clear_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
5592 static int bnxt_init_board(struct pci_dev
*pdev
, struct net_device
*dev
)
5595 struct bnxt
*bp
= netdev_priv(dev
);
5597 SET_NETDEV_DEV(dev
, &pdev
->dev
);
5599 /* enable device (incl. PCI PM wakeup), and bus-mastering */
5600 rc
= pci_enable_device(pdev
);
5602 dev_err(&pdev
->dev
, "Cannot enable PCI device, aborting\n");
5606 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
5608 "Cannot find PCI device base address, aborting\n");
5610 goto init_err_disable
;
5613 rc
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
5615 dev_err(&pdev
->dev
, "Cannot obtain PCI resources, aborting\n");
5616 goto init_err_disable
;
5619 if (dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(64)) != 0 &&
5620 dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(32)) != 0) {
5621 dev_err(&pdev
->dev
, "System does not support DMA, aborting\n");
5622 goto init_err_disable
;
5625 pci_set_master(pdev
);
5630 bp
->bar0
= pci_ioremap_bar(pdev
, 0);
5632 dev_err(&pdev
->dev
, "Cannot map device registers, aborting\n");
5634 goto init_err_release
;
5637 bp
->bar1
= pci_ioremap_bar(pdev
, 2);
5639 dev_err(&pdev
->dev
, "Cannot map doorbell registers, aborting\n");
5641 goto init_err_release
;
5644 bp
->bar2
= pci_ioremap_bar(pdev
, 4);
5646 dev_err(&pdev
->dev
, "Cannot map bar4 registers, aborting\n");
5648 goto init_err_release
;
5651 pci_enable_pcie_error_reporting(pdev
);
5653 INIT_WORK(&bp
->sp_task
, bnxt_sp_task
);
5655 spin_lock_init(&bp
->ntp_fltr_lock
);
5657 bp
->rx_ring_size
= BNXT_DEFAULT_RX_RING_SIZE
;
5658 bp
->tx_ring_size
= BNXT_DEFAULT_TX_RING_SIZE
;
5660 /* tick values in micro seconds */
5661 bp
->rx_coal_ticks
= 12;
5662 bp
->rx_coal_bufs
= 30;
5663 bp
->rx_coal_ticks_irq
= 1;
5664 bp
->rx_coal_bufs_irq
= 2;
5666 bp
->tx_coal_ticks
= 25;
5667 bp
->tx_coal_bufs
= 30;
5668 bp
->tx_coal_ticks_irq
= 2;
5669 bp
->tx_coal_bufs_irq
= 2;
5671 init_timer(&bp
->timer
);
5672 bp
->timer
.data
= (unsigned long)bp
;
5673 bp
->timer
.function
= bnxt_timer
;
5674 bp
->current_interval
= BNXT_TIMER_INTERVAL
;
5676 clear_bit(BNXT_STATE_OPEN
, &bp
->state
);
5682 pci_iounmap(pdev
, bp
->bar2
);
5687 pci_iounmap(pdev
, bp
->bar1
);
5692 pci_iounmap(pdev
, bp
->bar0
);
5696 pci_release_regions(pdev
);
5699 pci_disable_device(pdev
);
5705 /* rtnl_lock held */
5706 static int bnxt_change_mac_addr(struct net_device
*dev
, void *p
)
5708 struct sockaddr
*addr
= p
;
5709 struct bnxt
*bp
= netdev_priv(dev
);
5712 if (!is_valid_ether_addr(addr
->sa_data
))
5713 return -EADDRNOTAVAIL
;
5715 rc
= bnxt_approve_mac(bp
, addr
->sa_data
);
5719 if (ether_addr_equal(addr
->sa_data
, dev
->dev_addr
))
5722 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
5723 if (netif_running(dev
)) {
5724 bnxt_close_nic(bp
, false, false);
5725 rc
= bnxt_open_nic(bp
, false, false);
5731 /* rtnl_lock held */
5732 static int bnxt_change_mtu(struct net_device
*dev
, int new_mtu
)
5734 struct bnxt
*bp
= netdev_priv(dev
);
5736 if (new_mtu
< 60 || new_mtu
> 9000)
5739 if (netif_running(dev
))
5740 bnxt_close_nic(bp
, false, false);
5743 bnxt_set_ring_params(bp
);
5745 if (netif_running(dev
))
5746 return bnxt_open_nic(bp
, false, false);
5751 static int bnxt_setup_tc(struct net_device
*dev
, u32 handle
, __be16 proto
,
5752 struct tc_to_netdev
*ntc
)
5754 struct bnxt
*bp
= netdev_priv(dev
);
5757 if (ntc
->type
!= TC_SETUP_MQPRIO
)
5762 if (tc
> bp
->max_tc
) {
5763 netdev_err(dev
, "too many traffic classes requested: %d Max supported is %d\n",
5768 if (netdev_get_num_tc(dev
) == tc
)
5772 int max_rx_rings
, max_tx_rings
, rc
;
5775 if (bp
->flags
& BNXT_FLAG_SHARED_RINGS
)
5778 rc
= bnxt_get_max_rings(bp
, &max_rx_rings
, &max_tx_rings
, sh
);
5779 if (rc
|| bp
->tx_nr_rings_per_tc
* tc
> max_tx_rings
)
5783 /* Needs to close the device and do hw resource re-allocations */
5784 if (netif_running(bp
->dev
))
5785 bnxt_close_nic(bp
, true, false);
5788 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
* tc
;
5789 netdev_set_num_tc(dev
, tc
);
5791 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
;
5792 netdev_reset_tc(dev
);
5794 bp
->cp_nr_rings
= max_t(int, bp
->tx_nr_rings
, bp
->rx_nr_rings
);
5795 bp
->num_stat_ctxs
= bp
->cp_nr_rings
;
5797 if (netif_running(bp
->dev
))
5798 return bnxt_open_nic(bp
, true, false);
5803 #ifdef CONFIG_RFS_ACCEL
5804 static bool bnxt_fltr_match(struct bnxt_ntuple_filter
*f1
,
5805 struct bnxt_ntuple_filter
*f2
)
5807 struct flow_keys
*keys1
= &f1
->fkeys
;
5808 struct flow_keys
*keys2
= &f2
->fkeys
;
5810 if (keys1
->addrs
.v4addrs
.src
== keys2
->addrs
.v4addrs
.src
&&
5811 keys1
->addrs
.v4addrs
.dst
== keys2
->addrs
.v4addrs
.dst
&&
5812 keys1
->ports
.ports
== keys2
->ports
.ports
&&
5813 keys1
->basic
.ip_proto
== keys2
->basic
.ip_proto
&&
5814 keys1
->basic
.n_proto
== keys2
->basic
.n_proto
&&
5815 ether_addr_equal(f1
->src_mac_addr
, f2
->src_mac_addr
))
5821 static int bnxt_rx_flow_steer(struct net_device
*dev
, const struct sk_buff
*skb
,
5822 u16 rxq_index
, u32 flow_id
)
5824 struct bnxt
*bp
= netdev_priv(dev
);
5825 struct bnxt_ntuple_filter
*fltr
, *new_fltr
;
5826 struct flow_keys
*fkeys
;
5827 struct ethhdr
*eth
= (struct ethhdr
*)skb_mac_header(skb
);
5828 int rc
= 0, idx
, bit_id
;
5829 struct hlist_head
*head
;
5831 if (skb
->encapsulation
)
5832 return -EPROTONOSUPPORT
;
5834 new_fltr
= kzalloc(sizeof(*new_fltr
), GFP_ATOMIC
);
5838 fkeys
= &new_fltr
->fkeys
;
5839 if (!skb_flow_dissect_flow_keys(skb
, fkeys
, 0)) {
5840 rc
= -EPROTONOSUPPORT
;
5844 if ((fkeys
->basic
.n_proto
!= htons(ETH_P_IP
)) ||
5845 ((fkeys
->basic
.ip_proto
!= IPPROTO_TCP
) &&
5846 (fkeys
->basic
.ip_proto
!= IPPROTO_UDP
))) {
5847 rc
= -EPROTONOSUPPORT
;
5851 memcpy(new_fltr
->src_mac_addr
, eth
->h_source
, ETH_ALEN
);
5853 idx
= skb_get_hash_raw(skb
) & BNXT_NTP_FLTR_HASH_MASK
;
5854 head
= &bp
->ntp_fltr_hash_tbl
[idx
];
5856 hlist_for_each_entry_rcu(fltr
, head
, hash
) {
5857 if (bnxt_fltr_match(fltr
, new_fltr
)) {
5865 spin_lock_bh(&bp
->ntp_fltr_lock
);
5866 bit_id
= bitmap_find_free_region(bp
->ntp_fltr_bmap
,
5867 BNXT_NTP_FLTR_MAX_FLTR
, 0);
5869 spin_unlock_bh(&bp
->ntp_fltr_lock
);
5874 new_fltr
->sw_id
= (u16
)bit_id
;
5875 new_fltr
->flow_id
= flow_id
;
5876 new_fltr
->rxq
= rxq_index
;
5877 hlist_add_head_rcu(&new_fltr
->hash
, head
);
5878 bp
->ntp_fltr_count
++;
5879 spin_unlock_bh(&bp
->ntp_fltr_lock
);
5881 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT
, &bp
->sp_event
);
5882 schedule_work(&bp
->sp_task
);
5884 return new_fltr
->sw_id
;
5891 static void bnxt_cfg_ntp_filters(struct bnxt
*bp
)
5895 for (i
= 0; i
< BNXT_NTP_FLTR_HASH_SIZE
; i
++) {
5896 struct hlist_head
*head
;
5897 struct hlist_node
*tmp
;
5898 struct bnxt_ntuple_filter
*fltr
;
5901 head
= &bp
->ntp_fltr_hash_tbl
[i
];
5902 hlist_for_each_entry_safe(fltr
, tmp
, head
, hash
) {
5905 if (test_bit(BNXT_FLTR_VALID
, &fltr
->state
)) {
5906 if (rps_may_expire_flow(bp
->dev
, fltr
->rxq
,
5909 bnxt_hwrm_cfa_ntuple_filter_free(bp
,
5914 rc
= bnxt_hwrm_cfa_ntuple_filter_alloc(bp
,
5919 set_bit(BNXT_FLTR_VALID
, &fltr
->state
);
5923 spin_lock_bh(&bp
->ntp_fltr_lock
);
5924 hlist_del_rcu(&fltr
->hash
);
5925 bp
->ntp_fltr_count
--;
5926 spin_unlock_bh(&bp
->ntp_fltr_lock
);
5928 clear_bit(fltr
->sw_id
, bp
->ntp_fltr_bmap
);
5933 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT
, &bp
->sp_event
))
5934 netdev_info(bp
->dev
, "Receive PF driver unload event!");
5939 static void bnxt_cfg_ntp_filters(struct bnxt
*bp
)
5943 #endif /* CONFIG_RFS_ACCEL */
5945 static void bnxt_add_vxlan_port(struct net_device
*dev
, sa_family_t sa_family
,
5948 struct bnxt
*bp
= netdev_priv(dev
);
5950 if (!netif_running(dev
))
5953 if (sa_family
!= AF_INET6
&& sa_family
!= AF_INET
)
5956 if (bp
->vxlan_port_cnt
&& bp
->vxlan_port
!= port
)
5959 bp
->vxlan_port_cnt
++;
5960 if (bp
->vxlan_port_cnt
== 1) {
5961 bp
->vxlan_port
= port
;
5962 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT
, &bp
->sp_event
);
5963 schedule_work(&bp
->sp_task
);
5967 static void bnxt_del_vxlan_port(struct net_device
*dev
, sa_family_t sa_family
,
5970 struct bnxt
*bp
= netdev_priv(dev
);
5972 if (!netif_running(dev
))
5975 if (sa_family
!= AF_INET6
&& sa_family
!= AF_INET
)
5978 if (bp
->vxlan_port_cnt
&& bp
->vxlan_port
== port
) {
5979 bp
->vxlan_port_cnt
--;
5981 if (bp
->vxlan_port_cnt
== 0) {
5982 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT
, &bp
->sp_event
);
5983 schedule_work(&bp
->sp_task
);
5988 static const struct net_device_ops bnxt_netdev_ops
= {
5989 .ndo_open
= bnxt_open
,
5990 .ndo_start_xmit
= bnxt_start_xmit
,
5991 .ndo_stop
= bnxt_close
,
5992 .ndo_get_stats64
= bnxt_get_stats64
,
5993 .ndo_set_rx_mode
= bnxt_set_rx_mode
,
5994 .ndo_do_ioctl
= bnxt_ioctl
,
5995 .ndo_validate_addr
= eth_validate_addr
,
5996 .ndo_set_mac_address
= bnxt_change_mac_addr
,
5997 .ndo_change_mtu
= bnxt_change_mtu
,
5998 .ndo_fix_features
= bnxt_fix_features
,
5999 .ndo_set_features
= bnxt_set_features
,
6000 .ndo_tx_timeout
= bnxt_tx_timeout
,
6001 #ifdef CONFIG_BNXT_SRIOV
6002 .ndo_get_vf_config
= bnxt_get_vf_config
,
6003 .ndo_set_vf_mac
= bnxt_set_vf_mac
,
6004 .ndo_set_vf_vlan
= bnxt_set_vf_vlan
,
6005 .ndo_set_vf_rate
= bnxt_set_vf_bw
,
6006 .ndo_set_vf_link_state
= bnxt_set_vf_link_state
,
6007 .ndo_set_vf_spoofchk
= bnxt_set_vf_spoofchk
,
6009 #ifdef CONFIG_NET_POLL_CONTROLLER
6010 .ndo_poll_controller
= bnxt_poll_controller
,
6012 .ndo_setup_tc
= bnxt_setup_tc
,
6013 #ifdef CONFIG_RFS_ACCEL
6014 .ndo_rx_flow_steer
= bnxt_rx_flow_steer
,
6016 .ndo_add_vxlan_port
= bnxt_add_vxlan_port
,
6017 .ndo_del_vxlan_port
= bnxt_del_vxlan_port
,
6018 #ifdef CONFIG_NET_RX_BUSY_POLL
6019 .ndo_busy_poll
= bnxt_busy_poll
,
6023 static void bnxt_remove_one(struct pci_dev
*pdev
)
6025 struct net_device
*dev
= pci_get_drvdata(pdev
);
6026 struct bnxt
*bp
= netdev_priv(dev
);
6029 bnxt_sriov_disable(bp
);
6031 pci_disable_pcie_error_reporting(pdev
);
6032 unregister_netdev(dev
);
6033 cancel_work_sync(&bp
->sp_task
);
6036 bnxt_hwrm_func_drv_unrgtr(bp
);
6037 bnxt_free_hwrm_resources(bp
);
6038 pci_iounmap(pdev
, bp
->bar2
);
6039 pci_iounmap(pdev
, bp
->bar1
);
6040 pci_iounmap(pdev
, bp
->bar0
);
6043 pci_release_regions(pdev
);
6044 pci_disable_device(pdev
);
6047 static int bnxt_probe_phy(struct bnxt
*bp
)
6050 struct bnxt_link_info
*link_info
= &bp
->link_info
;
6052 rc
= bnxt_hwrm_phy_qcaps(bp
);
6054 netdev_err(bp
->dev
, "Probe phy can't get phy capabilities (rc: %x)\n",
6059 rc
= bnxt_update_link(bp
, false);
6061 netdev_err(bp
->dev
, "Probe phy can't update link (rc: %x)\n",
6066 /*initialize the ethool setting copy with NVM settings */
6067 if (BNXT_AUTO_MODE(link_info
->auto_mode
)) {
6068 link_info
->autoneg
= BNXT_AUTONEG_SPEED
;
6069 if (bp
->hwrm_spec_code
>= 0x10201) {
6070 if (link_info
->auto_pause_setting
&
6071 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE
)
6072 link_info
->autoneg
|= BNXT_AUTONEG_FLOW_CTRL
;
6074 link_info
->autoneg
|= BNXT_AUTONEG_FLOW_CTRL
;
6076 link_info
->advertising
= link_info
->auto_link_speeds
;
6078 link_info
->req_link_speed
= link_info
->force_link_speed
;
6079 link_info
->req_duplex
= link_info
->duplex_setting
;
6081 if (link_info
->autoneg
& BNXT_AUTONEG_FLOW_CTRL
)
6082 link_info
->req_flow_ctrl
=
6083 link_info
->auto_pause_setting
& BNXT_LINK_PAUSE_BOTH
;
6085 link_info
->req_flow_ctrl
= link_info
->force_pause_setting
;
6089 static int bnxt_get_max_irq(struct pci_dev
*pdev
)
6093 if (!pdev
->msix_cap
)
6096 pci_read_config_word(pdev
, pdev
->msix_cap
+ PCI_MSIX_FLAGS
, &ctrl
);
6097 return (ctrl
& PCI_MSIX_FLAGS_QSIZE
) + 1;
6100 static void _bnxt_get_max_rings(struct bnxt
*bp
, int *max_rx
, int *max_tx
,
6103 int max_ring_grps
= 0;
6105 #ifdef CONFIG_BNXT_SRIOV
6107 *max_tx
= bp
->vf
.max_tx_rings
;
6108 *max_rx
= bp
->vf
.max_rx_rings
;
6109 *max_cp
= min_t(int, bp
->vf
.max_irqs
, bp
->vf
.max_cp_rings
);
6110 *max_cp
= min_t(int, *max_cp
, bp
->vf
.max_stat_ctxs
);
6111 max_ring_grps
= bp
->vf
.max_hw_ring_grps
;
6115 *max_tx
= bp
->pf
.max_tx_rings
;
6116 *max_rx
= bp
->pf
.max_rx_rings
;
6117 *max_cp
= min_t(int, bp
->pf
.max_irqs
, bp
->pf
.max_cp_rings
);
6118 *max_cp
= min_t(int, *max_cp
, bp
->pf
.max_stat_ctxs
);
6119 max_ring_grps
= bp
->pf
.max_hw_ring_grps
;
6122 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
)
6124 *max_rx
= min_t(int, *max_rx
, max_ring_grps
);
6127 int bnxt_get_max_rings(struct bnxt
*bp
, int *max_rx
, int *max_tx
, bool shared
)
6131 _bnxt_get_max_rings(bp
, &rx
, &tx
, &cp
);
6132 if (!rx
|| !tx
|| !cp
)
6137 return bnxt_trim_rings(bp
, max_rx
, max_tx
, cp
, shared
);
6140 static int bnxt_set_dflt_rings(struct bnxt
*bp
)
6142 int dflt_rings
, max_rx_rings
, max_tx_rings
, rc
;
6146 bp
->flags
|= BNXT_FLAG_SHARED_RINGS
;
6147 dflt_rings
= netif_get_num_default_rss_queues();
6148 rc
= bnxt_get_max_rings(bp
, &max_rx_rings
, &max_tx_rings
, sh
);
6151 bp
->rx_nr_rings
= min_t(int, dflt_rings
, max_rx_rings
);
6152 bp
->tx_nr_rings_per_tc
= min_t(int, dflt_rings
, max_tx_rings
);
6153 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
;
6154 bp
->cp_nr_rings
= sh
? max_t(int, bp
->tx_nr_rings
, bp
->rx_nr_rings
) :
6155 bp
->tx_nr_rings
+ bp
->rx_nr_rings
;
6156 bp
->num_stat_ctxs
= bp
->cp_nr_rings
;
6160 static int bnxt_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
6162 static int version_printed
;
6163 struct net_device
*dev
;
6167 if (version_printed
++ == 0)
6168 pr_info("%s", version
);
6170 max_irqs
= bnxt_get_max_irq(pdev
);
6171 dev
= alloc_etherdev_mq(sizeof(*bp
), max_irqs
);
6175 bp
= netdev_priv(dev
);
6177 if (bnxt_vf_pciid(ent
->driver_data
))
6178 bp
->flags
|= BNXT_FLAG_VF
;
6181 bp
->flags
|= BNXT_FLAG_MSIX_CAP
;
6183 rc
= bnxt_init_board(pdev
, dev
);
6187 dev
->netdev_ops
= &bnxt_netdev_ops
;
6188 dev
->watchdog_timeo
= BNXT_TX_TIMEOUT
;
6189 dev
->ethtool_ops
= &bnxt_ethtool_ops
;
6191 pci_set_drvdata(pdev
, dev
);
6193 dev
->hw_features
= NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
| NETIF_F_SG
|
6194 NETIF_F_TSO
| NETIF_F_TSO6
|
6195 NETIF_F_GSO_UDP_TUNNEL
| NETIF_F_GSO_GRE
|
6196 NETIF_F_GSO_IPIP
| NETIF_F_GSO_SIT
|
6198 NETIF_F_RXCSUM
| NETIF_F_LRO
| NETIF_F_GRO
;
6200 dev
->hw_enc_features
=
6201 NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
| NETIF_F_SG
|
6202 NETIF_F_TSO
| NETIF_F_TSO6
|
6203 NETIF_F_GSO_UDP_TUNNEL
| NETIF_F_GSO_GRE
|
6204 NETIF_F_GSO_IPIP
| NETIF_F_GSO_SIT
;
6205 dev
->vlan_features
= dev
->hw_features
| NETIF_F_HIGHDMA
;
6206 dev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_RX
| NETIF_F_HW_VLAN_CTAG_TX
|
6207 NETIF_F_HW_VLAN_STAG_RX
| NETIF_F_HW_VLAN_STAG_TX
;
6208 dev
->features
|= dev
->hw_features
| NETIF_F_HIGHDMA
;
6209 dev
->priv_flags
|= IFF_UNICAST_FLT
;
6211 #ifdef CONFIG_BNXT_SRIOV
6212 init_waitqueue_head(&bp
->sriov_cfg_wait
);
6214 rc
= bnxt_alloc_hwrm_resources(bp
);
6218 mutex_init(&bp
->hwrm_cmd_lock
);
6219 bnxt_hwrm_ver_get(bp
);
6221 rc
= bnxt_hwrm_func_drv_rgtr(bp
);
6225 /* Get the MAX capabilities for this function */
6226 rc
= bnxt_hwrm_func_qcaps(bp
);
6228 netdev_err(bp
->dev
, "hwrm query capability failure rc: %x\n",
6234 rc
= bnxt_hwrm_queue_qportcfg(bp
);
6236 netdev_err(bp
->dev
, "hwrm query qportcfg failure rc: %x\n",
6242 bnxt_set_tpa_flags(bp
);
6243 bnxt_set_ring_params(bp
);
6245 bp
->pf
.max_irqs
= max_irqs
;
6246 #if defined(CONFIG_BNXT_SRIOV)
6248 bp
->vf
.max_irqs
= max_irqs
;
6250 bnxt_set_dflt_rings(bp
);
6253 dev
->hw_features
|= NETIF_F_NTUPLE
;
6254 if (bnxt_rfs_capable(bp
)) {
6255 bp
->flags
|= BNXT_FLAG_RFS
;
6256 dev
->features
|= NETIF_F_NTUPLE
;
6260 if (dev
->hw_features
& NETIF_F_HW_VLAN_CTAG_RX
)
6261 bp
->flags
|= BNXT_FLAG_STRIP_VLAN
;
6263 rc
= bnxt_probe_phy(bp
);
6267 rc
= register_netdev(dev
);
6271 netdev_info(dev
, "%s found at mem %lx, node addr %pM\n",
6272 board_info
[ent
->driver_data
].name
,
6273 (long)pci_resource_start(pdev
, 0), dev
->dev_addr
);
6278 pci_iounmap(pdev
, bp
->bar0
);
6279 pci_release_regions(pdev
);
6280 pci_disable_device(pdev
);
6288 * bnxt_io_error_detected - called when PCI error is detected
6289 * @pdev: Pointer to PCI device
6290 * @state: The current pci connection state
6292 * This function is called after a PCI bus error affecting
6293 * this device has been detected.
6295 static pci_ers_result_t
bnxt_io_error_detected(struct pci_dev
*pdev
,
6296 pci_channel_state_t state
)
6298 struct net_device
*netdev
= pci_get_drvdata(pdev
);
6300 netdev_info(netdev
, "PCI I/O error detected\n");
6303 netif_device_detach(netdev
);
6305 if (state
== pci_channel_io_perm_failure
) {
6307 return PCI_ERS_RESULT_DISCONNECT
;
6310 if (netif_running(netdev
))
6313 pci_disable_device(pdev
);
6316 /* Request a slot slot reset. */
6317 return PCI_ERS_RESULT_NEED_RESET
;
6321 * bnxt_io_slot_reset - called after the pci bus has been reset.
6322 * @pdev: Pointer to PCI device
6324 * Restart the card from scratch, as if from a cold-boot.
6325 * At this point, the card has exprienced a hard reset,
6326 * followed by fixups by BIOS, and has its config space
6327 * set up identically to what it was at cold boot.
6329 static pci_ers_result_t
bnxt_io_slot_reset(struct pci_dev
*pdev
)
6331 struct net_device
*netdev
= pci_get_drvdata(pdev
);
6332 struct bnxt
*bp
= netdev_priv(netdev
);
6334 pci_ers_result_t result
= PCI_ERS_RESULT_DISCONNECT
;
6336 netdev_info(bp
->dev
, "PCI Slot Reset\n");
6340 if (pci_enable_device(pdev
)) {
6342 "Cannot re-enable PCI device after reset.\n");
6344 pci_set_master(pdev
);
6346 if (netif_running(netdev
))
6347 err
= bnxt_open(netdev
);
6350 result
= PCI_ERS_RESULT_RECOVERED
;
6353 if (result
!= PCI_ERS_RESULT_RECOVERED
&& netif_running(netdev
))
6358 err
= pci_cleanup_aer_uncorrect_error_status(pdev
);
6361 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
6362 err
); /* non-fatal, continue */
6365 return PCI_ERS_RESULT_RECOVERED
;
6369 * bnxt_io_resume - called when traffic can start flowing again.
6370 * @pdev: Pointer to PCI device
6372 * This callback is called when the error recovery driver tells
6373 * us that its OK to resume normal operation.
6375 static void bnxt_io_resume(struct pci_dev
*pdev
)
6377 struct net_device
*netdev
= pci_get_drvdata(pdev
);
6381 netif_device_attach(netdev
);
6386 static const struct pci_error_handlers bnxt_err_handler
= {
6387 .error_detected
= bnxt_io_error_detected
,
6388 .slot_reset
= bnxt_io_slot_reset
,
6389 .resume
= bnxt_io_resume
6392 static struct pci_driver bnxt_pci_driver
= {
6393 .name
= DRV_MODULE_NAME
,
6394 .id_table
= bnxt_pci_tbl
,
6395 .probe
= bnxt_init_one
,
6396 .remove
= bnxt_remove_one
,
6397 .err_handler
= &bnxt_err_handler
,
6398 #if defined(CONFIG_BNXT_SRIOV)
6399 .sriov_configure
= bnxt_sriov_configure
,
6403 module_pci_driver(bnxt_pci_driver
);