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[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / broadcom / bnxt / bnxt.c
1 /* Broadcom NetXtreme-C/E network driver.
2 *
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2018 Broadcom Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
9 */
10
11 #include <linux/module.h>
12
13 #include <linux/stringify.h>
14 #include <linux/kernel.h>
15 #include <linux/timer.h>
16 #include <linux/errno.h>
17 #include <linux/ioport.h>
18 #include <linux/slab.h>
19 #include <linux/vmalloc.h>
20 #include <linux/interrupt.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
23 #include <linux/etherdevice.h>
24 #include <linux/skbuff.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/bitops.h>
27 #include <linux/io.h>
28 #include <linux/irq.h>
29 #include <linux/delay.h>
30 #include <asm/byteorder.h>
31 #include <asm/page.h>
32 #include <linux/time.h>
33 #include <linux/mii.h>
34 #include <linux/if.h>
35 #include <linux/if_vlan.h>
36 #include <linux/if_bridge.h>
37 #include <linux/rtc.h>
38 #include <linux/bpf.h>
39 #include <net/ip.h>
40 #include <net/tcp.h>
41 #include <net/udp.h>
42 #include <net/checksum.h>
43 #include <net/ip6_checksum.h>
44 #include <net/udp_tunnel.h>
45 #include <linux/workqueue.h>
46 #include <linux/prefetch.h>
47 #include <linux/cache.h>
48 #include <linux/log2.h>
49 #include <linux/aer.h>
50 #include <linux/bitmap.h>
51 #include <linux/cpu_rmap.h>
52 #include <linux/cpumask.h>
53 #include <net/pkt_cls.h>
54
55 #include "bnxt_hsi.h"
56 #include "bnxt.h"
57 #include "bnxt_ulp.h"
58 #include "bnxt_sriov.h"
59 #include "bnxt_ethtool.h"
60 #include "bnxt_dcb.h"
61 #include "bnxt_xdp.h"
62 #include "bnxt_vfr.h"
63 #include "bnxt_tc.h"
64 #include "bnxt_devlink.h"
65
66 #define BNXT_TX_TIMEOUT (5 * HZ)
67
68 static const char version[] =
69 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
70
71 MODULE_LICENSE("GPL");
72 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
73 MODULE_VERSION(DRV_MODULE_VERSION);
74
75 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
76 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
77 #define BNXT_RX_COPY_THRESH 256
78
79 #define BNXT_TX_PUSH_THRESH 164
80
81 enum board_idx {
82 BCM57301,
83 BCM57302,
84 BCM57304,
85 BCM57417_NPAR,
86 BCM58700,
87 BCM57311,
88 BCM57312,
89 BCM57402,
90 BCM57404,
91 BCM57406,
92 BCM57402_NPAR,
93 BCM57407,
94 BCM57412,
95 BCM57414,
96 BCM57416,
97 BCM57417,
98 BCM57412_NPAR,
99 BCM57314,
100 BCM57417_SFP,
101 BCM57416_SFP,
102 BCM57404_NPAR,
103 BCM57406_NPAR,
104 BCM57407_SFP,
105 BCM57407_NPAR,
106 BCM57414_NPAR,
107 BCM57416_NPAR,
108 BCM57452,
109 BCM57454,
110 BCM5745x_NPAR,
111 BCM58802,
112 BCM58804,
113 BCM58808,
114 NETXTREME_E_VF,
115 NETXTREME_C_VF,
116 NETXTREME_S_VF,
117 };
118
119 /* indexed by enum above */
120 static const struct {
121 char *name;
122 } board_info[] = {
123 [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
124 [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
125 [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
126 [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
127 [BCM58700] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
128 [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
129 [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
130 [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
131 [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
132 [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
133 [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
134 [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
135 [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
136 [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
137 [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
138 [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
139 [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
140 [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
141 [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
142 [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
143 [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
144 [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
145 [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
146 [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
147 [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
148 [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
149 [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" },
150 [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
151 [BCM5745x_NPAR] = { "Broadcom BCM5745x NetXtreme-E Ethernet Partition" },
152 [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" },
153 [BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
154 [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
155 [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" },
156 [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" },
157 [NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" },
158 };
159
160 static const struct pci_device_id bnxt_pci_tbl[] = {
161 { PCI_VDEVICE(BROADCOM, 0x1604), .driver_data = BCM5745x_NPAR },
162 { PCI_VDEVICE(BROADCOM, 0x1605), .driver_data = BCM5745x_NPAR },
163 { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 },
164 { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR },
165 { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
166 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
167 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
168 { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR },
169 { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 },
170 { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 },
171 { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 },
172 { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
173 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
174 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
175 { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR },
176 { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 },
177 { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 },
178 { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 },
179 { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 },
180 { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 },
181 { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR },
182 { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
183 { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP },
184 { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP },
185 { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR },
186 { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR },
187 { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP },
188 { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR },
189 { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR },
190 { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR },
191 { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR },
192 { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR },
193 { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR },
194 { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 },
195 { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 },
196 { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 },
197 { PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 },
198 #ifdef CONFIG_BNXT_SRIOV
199 { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF },
200 { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF },
201 { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF },
202 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF },
203 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF },
204 { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF },
205 { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF },
206 { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF },
207 { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF },
208 #endif
209 { 0 }
210 };
211
212 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
213
214 static const u16 bnxt_vf_req_snif[] = {
215 HWRM_FUNC_CFG,
216 HWRM_FUNC_VF_CFG,
217 HWRM_PORT_PHY_QCFG,
218 HWRM_CFA_L2_FILTER_ALLOC,
219 };
220
221 static const u16 bnxt_async_events_arr[] = {
222 ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
223 ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
224 ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
225 ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
226 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
227 };
228
229 static struct workqueue_struct *bnxt_pf_wq;
230
231 static bool bnxt_vf_pciid(enum board_idx idx)
232 {
233 return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF ||
234 idx == NETXTREME_S_VF);
235 }
236
237 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
238 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
239 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
240
241 #define BNXT_CP_DB_REARM(db, raw_cons) \
242 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
243
244 #define BNXT_CP_DB(db, raw_cons) \
245 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
246
247 #define BNXT_CP_DB_IRQ_DIS(db) \
248 writel(DB_CP_IRQ_DIS_FLAGS, db)
249
250 const u16 bnxt_lhint_arr[] = {
251 TX_BD_FLAGS_LHINT_512_AND_SMALLER,
252 TX_BD_FLAGS_LHINT_512_TO_1023,
253 TX_BD_FLAGS_LHINT_1024_TO_2047,
254 TX_BD_FLAGS_LHINT_1024_TO_2047,
255 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
256 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
257 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
258 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
259 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
260 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
261 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
262 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
263 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
264 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
265 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
266 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
267 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
268 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
269 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
270 };
271
272 static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb)
273 {
274 struct metadata_dst *md_dst = skb_metadata_dst(skb);
275
276 if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX)
277 return 0;
278
279 return md_dst->u.port_info.port_id;
280 }
281
282 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
283 {
284 struct bnxt *bp = netdev_priv(dev);
285 struct tx_bd *txbd;
286 struct tx_bd_ext *txbd1;
287 struct netdev_queue *txq;
288 int i;
289 dma_addr_t mapping;
290 unsigned int length, pad = 0;
291 u32 len, free_size, vlan_tag_flags, cfa_action, flags;
292 u16 prod, last_frag;
293 struct pci_dev *pdev = bp->pdev;
294 struct bnxt_tx_ring_info *txr;
295 struct bnxt_sw_tx_bd *tx_buf;
296
297 i = skb_get_queue_mapping(skb);
298 if (unlikely(i >= bp->tx_nr_rings)) {
299 dev_kfree_skb_any(skb);
300 return NETDEV_TX_OK;
301 }
302
303 txq = netdev_get_tx_queue(dev, i);
304 txr = &bp->tx_ring[bp->tx_ring_map[i]];
305 prod = txr->tx_prod;
306
307 free_size = bnxt_tx_avail(bp, txr);
308 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
309 netif_tx_stop_queue(txq);
310 return NETDEV_TX_BUSY;
311 }
312
313 length = skb->len;
314 len = skb_headlen(skb);
315 last_frag = skb_shinfo(skb)->nr_frags;
316
317 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
318
319 txbd->tx_bd_opaque = prod;
320
321 tx_buf = &txr->tx_buf_ring[prod];
322 tx_buf->skb = skb;
323 tx_buf->nr_frags = last_frag;
324
325 vlan_tag_flags = 0;
326 cfa_action = bnxt_xmit_get_cfa_action(skb);
327 if (skb_vlan_tag_present(skb)) {
328 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
329 skb_vlan_tag_get(skb);
330 /* Currently supports 8021Q, 8021AD vlan offloads
331 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
332 */
333 if (skb->vlan_proto == htons(ETH_P_8021Q))
334 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
335 }
336
337 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
338 struct tx_push_buffer *tx_push_buf = txr->tx_push;
339 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
340 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
341 void *pdata = tx_push_buf->data;
342 u64 *end;
343 int j, push_len;
344
345 /* Set COAL_NOW to be ready quickly for the next push */
346 tx_push->tx_bd_len_flags_type =
347 cpu_to_le32((length << TX_BD_LEN_SHIFT) |
348 TX_BD_TYPE_LONG_TX_BD |
349 TX_BD_FLAGS_LHINT_512_AND_SMALLER |
350 TX_BD_FLAGS_COAL_NOW |
351 TX_BD_FLAGS_PACKET_END |
352 (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
353
354 if (skb->ip_summed == CHECKSUM_PARTIAL)
355 tx_push1->tx_bd_hsize_lflags =
356 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
357 else
358 tx_push1->tx_bd_hsize_lflags = 0;
359
360 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
361 tx_push1->tx_bd_cfa_action =
362 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
363
364 end = pdata + length;
365 end = PTR_ALIGN(end, 8) - 1;
366 *end = 0;
367
368 skb_copy_from_linear_data(skb, pdata, len);
369 pdata += len;
370 for (j = 0; j < last_frag; j++) {
371 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
372 void *fptr;
373
374 fptr = skb_frag_address_safe(frag);
375 if (!fptr)
376 goto normal_tx;
377
378 memcpy(pdata, fptr, skb_frag_size(frag));
379 pdata += skb_frag_size(frag);
380 }
381
382 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
383 txbd->tx_bd_haddr = txr->data_mapping;
384 prod = NEXT_TX(prod);
385 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
386 memcpy(txbd, tx_push1, sizeof(*txbd));
387 prod = NEXT_TX(prod);
388 tx_push->doorbell =
389 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
390 txr->tx_prod = prod;
391
392 tx_buf->is_push = 1;
393 netdev_tx_sent_queue(txq, skb->len);
394 wmb(); /* Sync is_push and byte queue before pushing data */
395
396 push_len = (length + sizeof(*tx_push) + 7) / 8;
397 if (push_len > 16) {
398 __iowrite64_copy(txr->tx_doorbell, tx_push_buf, 16);
399 __iowrite32_copy(txr->tx_doorbell + 4, tx_push_buf + 1,
400 (push_len - 16) << 1);
401 } else {
402 __iowrite64_copy(txr->tx_doorbell, tx_push_buf,
403 push_len);
404 }
405
406 goto tx_done;
407 }
408
409 normal_tx:
410 if (length < BNXT_MIN_PKT_SIZE) {
411 pad = BNXT_MIN_PKT_SIZE - length;
412 if (skb_pad(skb, pad)) {
413 /* SKB already freed. */
414 tx_buf->skb = NULL;
415 return NETDEV_TX_OK;
416 }
417 length = BNXT_MIN_PKT_SIZE;
418 }
419
420 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
421
422 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
423 dev_kfree_skb_any(skb);
424 tx_buf->skb = NULL;
425 return NETDEV_TX_OK;
426 }
427
428 dma_unmap_addr_set(tx_buf, mapping, mapping);
429 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
430 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
431
432 txbd->tx_bd_haddr = cpu_to_le64(mapping);
433
434 prod = NEXT_TX(prod);
435 txbd1 = (struct tx_bd_ext *)
436 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
437
438 txbd1->tx_bd_hsize_lflags = 0;
439 if (skb_is_gso(skb)) {
440 u32 hdr_len;
441
442 if (skb->encapsulation)
443 hdr_len = skb_inner_network_offset(skb) +
444 skb_inner_network_header_len(skb) +
445 inner_tcp_hdrlen(skb);
446 else
447 hdr_len = skb_transport_offset(skb) +
448 tcp_hdrlen(skb);
449
450 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
451 TX_BD_FLAGS_T_IPID |
452 (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
453 length = skb_shinfo(skb)->gso_size;
454 txbd1->tx_bd_mss = cpu_to_le32(length);
455 length += hdr_len;
456 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
457 txbd1->tx_bd_hsize_lflags =
458 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
459 txbd1->tx_bd_mss = 0;
460 }
461
462 length >>= 9;
463 flags |= bnxt_lhint_arr[length];
464 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
465
466 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
467 txbd1->tx_bd_cfa_action =
468 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
469 for (i = 0; i < last_frag; i++) {
470 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
471
472 prod = NEXT_TX(prod);
473 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
474
475 len = skb_frag_size(frag);
476 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
477 DMA_TO_DEVICE);
478
479 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
480 goto tx_dma_error;
481
482 tx_buf = &txr->tx_buf_ring[prod];
483 dma_unmap_addr_set(tx_buf, mapping, mapping);
484
485 txbd->tx_bd_haddr = cpu_to_le64(mapping);
486
487 flags = len << TX_BD_LEN_SHIFT;
488 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
489 }
490
491 flags &= ~TX_BD_LEN;
492 txbd->tx_bd_len_flags_type =
493 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
494 TX_BD_FLAGS_PACKET_END);
495
496 netdev_tx_sent_queue(txq, skb->len);
497
498 /* Sync BD data before updating doorbell */
499 wmb();
500
501 prod = NEXT_TX(prod);
502 txr->tx_prod = prod;
503
504 if (!skb->xmit_more || netif_xmit_stopped(txq))
505 bnxt_db_write(bp, txr->tx_doorbell, DB_KEY_TX | prod);
506
507 tx_done:
508
509 mmiowb();
510
511 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
512 if (skb->xmit_more && !tx_buf->is_push)
513 bnxt_db_write(bp, txr->tx_doorbell, DB_KEY_TX | prod);
514
515 netif_tx_stop_queue(txq);
516
517 /* netif_tx_stop_queue() must be done before checking
518 * tx index in bnxt_tx_avail() below, because in
519 * bnxt_tx_int(), we update tx index before checking for
520 * netif_tx_queue_stopped().
521 */
522 smp_mb();
523 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
524 netif_tx_wake_queue(txq);
525 }
526 return NETDEV_TX_OK;
527
528 tx_dma_error:
529 last_frag = i;
530
531 /* start back at beginning and unmap skb */
532 prod = txr->tx_prod;
533 tx_buf = &txr->tx_buf_ring[prod];
534 tx_buf->skb = NULL;
535 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
536 skb_headlen(skb), PCI_DMA_TODEVICE);
537 prod = NEXT_TX(prod);
538
539 /* unmap remaining mapped pages */
540 for (i = 0; i < last_frag; i++) {
541 prod = NEXT_TX(prod);
542 tx_buf = &txr->tx_buf_ring[prod];
543 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
544 skb_frag_size(&skb_shinfo(skb)->frags[i]),
545 PCI_DMA_TODEVICE);
546 }
547
548 dev_kfree_skb_any(skb);
549 return NETDEV_TX_OK;
550 }
551
552 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
553 {
554 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
555 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index);
556 u16 cons = txr->tx_cons;
557 struct pci_dev *pdev = bp->pdev;
558 int i;
559 unsigned int tx_bytes = 0;
560
561 for (i = 0; i < nr_pkts; i++) {
562 struct bnxt_sw_tx_bd *tx_buf;
563 struct sk_buff *skb;
564 int j, last;
565
566 tx_buf = &txr->tx_buf_ring[cons];
567 cons = NEXT_TX(cons);
568 skb = tx_buf->skb;
569 tx_buf->skb = NULL;
570
571 if (tx_buf->is_push) {
572 tx_buf->is_push = 0;
573 goto next_tx_int;
574 }
575
576 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
577 skb_headlen(skb), PCI_DMA_TODEVICE);
578 last = tx_buf->nr_frags;
579
580 for (j = 0; j < last; j++) {
581 cons = NEXT_TX(cons);
582 tx_buf = &txr->tx_buf_ring[cons];
583 dma_unmap_page(
584 &pdev->dev,
585 dma_unmap_addr(tx_buf, mapping),
586 skb_frag_size(&skb_shinfo(skb)->frags[j]),
587 PCI_DMA_TODEVICE);
588 }
589
590 next_tx_int:
591 cons = NEXT_TX(cons);
592
593 tx_bytes += skb->len;
594 dev_kfree_skb_any(skb);
595 }
596
597 netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
598 txr->tx_cons = cons;
599
600 /* Need to make the tx_cons update visible to bnxt_start_xmit()
601 * before checking for netif_tx_queue_stopped(). Without the
602 * memory barrier, there is a small possibility that bnxt_start_xmit()
603 * will miss it and cause the queue to be stopped forever.
604 */
605 smp_mb();
606
607 if (unlikely(netif_tx_queue_stopped(txq)) &&
608 (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
609 __netif_tx_lock(txq, smp_processor_id());
610 if (netif_tx_queue_stopped(txq) &&
611 bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
612 txr->dev_state != BNXT_DEV_STATE_CLOSING)
613 netif_tx_wake_queue(txq);
614 __netif_tx_unlock(txq);
615 }
616 }
617
618 static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping,
619 gfp_t gfp)
620 {
621 struct device *dev = &bp->pdev->dev;
622 struct page *page;
623
624 page = alloc_page(gfp);
625 if (!page)
626 return NULL;
627
628 *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir,
629 DMA_ATTR_WEAK_ORDERING);
630 if (dma_mapping_error(dev, *mapping)) {
631 __free_page(page);
632 return NULL;
633 }
634 *mapping += bp->rx_dma_offset;
635 return page;
636 }
637
638 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
639 gfp_t gfp)
640 {
641 u8 *data;
642 struct pci_dev *pdev = bp->pdev;
643
644 data = kmalloc(bp->rx_buf_size, gfp);
645 if (!data)
646 return NULL;
647
648 *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset,
649 bp->rx_buf_use_size, bp->rx_dir,
650 DMA_ATTR_WEAK_ORDERING);
651
652 if (dma_mapping_error(&pdev->dev, *mapping)) {
653 kfree(data);
654 data = NULL;
655 }
656 return data;
657 }
658
659 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
660 u16 prod, gfp_t gfp)
661 {
662 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
663 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
664 dma_addr_t mapping;
665
666 if (BNXT_RX_PAGE_MODE(bp)) {
667 struct page *page = __bnxt_alloc_rx_page(bp, &mapping, gfp);
668
669 if (!page)
670 return -ENOMEM;
671
672 rx_buf->data = page;
673 rx_buf->data_ptr = page_address(page) + bp->rx_offset;
674 } else {
675 u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
676
677 if (!data)
678 return -ENOMEM;
679
680 rx_buf->data = data;
681 rx_buf->data_ptr = data + bp->rx_offset;
682 }
683 rx_buf->mapping = mapping;
684
685 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
686 return 0;
687 }
688
689 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data)
690 {
691 u16 prod = rxr->rx_prod;
692 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
693 struct rx_bd *cons_bd, *prod_bd;
694
695 prod_rx_buf = &rxr->rx_buf_ring[prod];
696 cons_rx_buf = &rxr->rx_buf_ring[cons];
697
698 prod_rx_buf->data = data;
699 prod_rx_buf->data_ptr = cons_rx_buf->data_ptr;
700
701 prod_rx_buf->mapping = cons_rx_buf->mapping;
702
703 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
704 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
705
706 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
707 }
708
709 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
710 {
711 u16 next, max = rxr->rx_agg_bmap_size;
712
713 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
714 if (next >= max)
715 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
716 return next;
717 }
718
719 static inline int bnxt_alloc_rx_page(struct bnxt *bp,
720 struct bnxt_rx_ring_info *rxr,
721 u16 prod, gfp_t gfp)
722 {
723 struct rx_bd *rxbd =
724 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
725 struct bnxt_sw_rx_agg_bd *rx_agg_buf;
726 struct pci_dev *pdev = bp->pdev;
727 struct page *page;
728 dma_addr_t mapping;
729 u16 sw_prod = rxr->rx_sw_agg_prod;
730 unsigned int offset = 0;
731
732 if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
733 page = rxr->rx_page;
734 if (!page) {
735 page = alloc_page(gfp);
736 if (!page)
737 return -ENOMEM;
738 rxr->rx_page = page;
739 rxr->rx_page_offset = 0;
740 }
741 offset = rxr->rx_page_offset;
742 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
743 if (rxr->rx_page_offset == PAGE_SIZE)
744 rxr->rx_page = NULL;
745 else
746 get_page(page);
747 } else {
748 page = alloc_page(gfp);
749 if (!page)
750 return -ENOMEM;
751 }
752
753 mapping = dma_map_page_attrs(&pdev->dev, page, offset,
754 BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE,
755 DMA_ATTR_WEAK_ORDERING);
756 if (dma_mapping_error(&pdev->dev, mapping)) {
757 __free_page(page);
758 return -EIO;
759 }
760
761 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
762 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
763
764 __set_bit(sw_prod, rxr->rx_agg_bmap);
765 rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
766 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
767
768 rx_agg_buf->page = page;
769 rx_agg_buf->offset = offset;
770 rx_agg_buf->mapping = mapping;
771 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
772 rxbd->rx_bd_opaque = sw_prod;
773 return 0;
774 }
775
776 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons,
777 u32 agg_bufs)
778 {
779 struct bnxt *bp = bnapi->bp;
780 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
781 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
782 u16 prod = rxr->rx_agg_prod;
783 u16 sw_prod = rxr->rx_sw_agg_prod;
784 u32 i;
785
786 for (i = 0; i < agg_bufs; i++) {
787 u16 cons;
788 struct rx_agg_cmp *agg;
789 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
790 struct rx_bd *prod_bd;
791 struct page *page;
792
793 agg = (struct rx_agg_cmp *)
794 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
795 cons = agg->rx_agg_cmp_opaque;
796 __clear_bit(cons, rxr->rx_agg_bmap);
797
798 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
799 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
800
801 __set_bit(sw_prod, rxr->rx_agg_bmap);
802 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
803 cons_rx_buf = &rxr->rx_agg_ring[cons];
804
805 /* It is possible for sw_prod to be equal to cons, so
806 * set cons_rx_buf->page to NULL first.
807 */
808 page = cons_rx_buf->page;
809 cons_rx_buf->page = NULL;
810 prod_rx_buf->page = page;
811 prod_rx_buf->offset = cons_rx_buf->offset;
812
813 prod_rx_buf->mapping = cons_rx_buf->mapping;
814
815 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
816
817 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
818 prod_bd->rx_bd_opaque = sw_prod;
819
820 prod = NEXT_RX_AGG(prod);
821 sw_prod = NEXT_RX_AGG(sw_prod);
822 cp_cons = NEXT_CMP(cp_cons);
823 }
824 rxr->rx_agg_prod = prod;
825 rxr->rx_sw_agg_prod = sw_prod;
826 }
827
828 static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp,
829 struct bnxt_rx_ring_info *rxr,
830 u16 cons, void *data, u8 *data_ptr,
831 dma_addr_t dma_addr,
832 unsigned int offset_and_len)
833 {
834 unsigned int payload = offset_and_len >> 16;
835 unsigned int len = offset_and_len & 0xffff;
836 struct skb_frag_struct *frag;
837 struct page *page = data;
838 u16 prod = rxr->rx_prod;
839 struct sk_buff *skb;
840 int off, err;
841
842 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
843 if (unlikely(err)) {
844 bnxt_reuse_rx_data(rxr, cons, data);
845 return NULL;
846 }
847 dma_addr -= bp->rx_dma_offset;
848 dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir,
849 DMA_ATTR_WEAK_ORDERING);
850
851 if (unlikely(!payload))
852 payload = eth_get_headlen(data_ptr, len);
853
854 skb = napi_alloc_skb(&rxr->bnapi->napi, payload);
855 if (!skb) {
856 __free_page(page);
857 return NULL;
858 }
859
860 off = (void *)data_ptr - page_address(page);
861 skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE);
862 memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN,
863 payload + NET_IP_ALIGN);
864
865 frag = &skb_shinfo(skb)->frags[0];
866 skb_frag_size_sub(frag, payload);
867 frag->page_offset += payload;
868 skb->data_len -= payload;
869 skb->tail += payload;
870
871 return skb;
872 }
873
874 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
875 struct bnxt_rx_ring_info *rxr, u16 cons,
876 void *data, u8 *data_ptr,
877 dma_addr_t dma_addr,
878 unsigned int offset_and_len)
879 {
880 u16 prod = rxr->rx_prod;
881 struct sk_buff *skb;
882 int err;
883
884 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
885 if (unlikely(err)) {
886 bnxt_reuse_rx_data(rxr, cons, data);
887 return NULL;
888 }
889
890 skb = build_skb(data, 0);
891 dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
892 bp->rx_dir, DMA_ATTR_WEAK_ORDERING);
893 if (!skb) {
894 kfree(data);
895 return NULL;
896 }
897
898 skb_reserve(skb, bp->rx_offset);
899 skb_put(skb, offset_and_len & 0xffff);
900 return skb;
901 }
902
903 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi,
904 struct sk_buff *skb, u16 cp_cons,
905 u32 agg_bufs)
906 {
907 struct pci_dev *pdev = bp->pdev;
908 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
909 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
910 u16 prod = rxr->rx_agg_prod;
911 u32 i;
912
913 for (i = 0; i < agg_bufs; i++) {
914 u16 cons, frag_len;
915 struct rx_agg_cmp *agg;
916 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
917 struct page *page;
918 dma_addr_t mapping;
919
920 agg = (struct rx_agg_cmp *)
921 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
922 cons = agg->rx_agg_cmp_opaque;
923 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
924 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
925
926 cons_rx_buf = &rxr->rx_agg_ring[cons];
927 skb_fill_page_desc(skb, i, cons_rx_buf->page,
928 cons_rx_buf->offset, frag_len);
929 __clear_bit(cons, rxr->rx_agg_bmap);
930
931 /* It is possible for bnxt_alloc_rx_page() to allocate
932 * a sw_prod index that equals the cons index, so we
933 * need to clear the cons entry now.
934 */
935 mapping = cons_rx_buf->mapping;
936 page = cons_rx_buf->page;
937 cons_rx_buf->page = NULL;
938
939 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
940 struct skb_shared_info *shinfo;
941 unsigned int nr_frags;
942
943 shinfo = skb_shinfo(skb);
944 nr_frags = --shinfo->nr_frags;
945 __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
946
947 dev_kfree_skb(skb);
948
949 cons_rx_buf->page = page;
950
951 /* Update prod since possibly some pages have been
952 * allocated already.
953 */
954 rxr->rx_agg_prod = prod;
955 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i);
956 return NULL;
957 }
958
959 dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
960 PCI_DMA_FROMDEVICE,
961 DMA_ATTR_WEAK_ORDERING);
962
963 skb->data_len += frag_len;
964 skb->len += frag_len;
965 skb->truesize += PAGE_SIZE;
966
967 prod = NEXT_RX_AGG(prod);
968 cp_cons = NEXT_CMP(cp_cons);
969 }
970 rxr->rx_agg_prod = prod;
971 return skb;
972 }
973
974 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
975 u8 agg_bufs, u32 *raw_cons)
976 {
977 u16 last;
978 struct rx_agg_cmp *agg;
979
980 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
981 last = RING_CMP(*raw_cons);
982 agg = (struct rx_agg_cmp *)
983 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
984 return RX_AGG_CMP_VALID(agg, *raw_cons);
985 }
986
987 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
988 unsigned int len,
989 dma_addr_t mapping)
990 {
991 struct bnxt *bp = bnapi->bp;
992 struct pci_dev *pdev = bp->pdev;
993 struct sk_buff *skb;
994
995 skb = napi_alloc_skb(&bnapi->napi, len);
996 if (!skb)
997 return NULL;
998
999 dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh,
1000 bp->rx_dir);
1001
1002 memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN,
1003 len + NET_IP_ALIGN);
1004
1005 dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh,
1006 bp->rx_dir);
1007
1008 skb_put(skb, len);
1009 return skb;
1010 }
1011
1012 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_napi *bnapi,
1013 u32 *raw_cons, void *cmp)
1014 {
1015 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1016 struct rx_cmp *rxcmp = cmp;
1017 u32 tmp_raw_cons = *raw_cons;
1018 u8 cmp_type, agg_bufs = 0;
1019
1020 cmp_type = RX_CMP_TYPE(rxcmp);
1021
1022 if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1023 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
1024 RX_CMP_AGG_BUFS) >>
1025 RX_CMP_AGG_BUFS_SHIFT;
1026 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1027 struct rx_tpa_end_cmp *tpa_end = cmp;
1028
1029 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1030 RX_TPA_END_CMP_AGG_BUFS) >>
1031 RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1032 }
1033
1034 if (agg_bufs) {
1035 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1036 return -EBUSY;
1037 }
1038 *raw_cons = tmp_raw_cons;
1039 return 0;
1040 }
1041
1042 static void bnxt_queue_sp_work(struct bnxt *bp)
1043 {
1044 if (BNXT_PF(bp))
1045 queue_work(bnxt_pf_wq, &bp->sp_task);
1046 else
1047 schedule_work(&bp->sp_task);
1048 }
1049
1050 static void bnxt_cancel_sp_work(struct bnxt *bp)
1051 {
1052 if (BNXT_PF(bp))
1053 flush_workqueue(bnxt_pf_wq);
1054 else
1055 cancel_work_sync(&bp->sp_task);
1056 }
1057
1058 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
1059 {
1060 if (!rxr->bnapi->in_reset) {
1061 rxr->bnapi->in_reset = true;
1062 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
1063 bnxt_queue_sp_work(bp);
1064 }
1065 rxr->rx_next_cons = 0xffff;
1066 }
1067
1068 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1069 struct rx_tpa_start_cmp *tpa_start,
1070 struct rx_tpa_start_cmp_ext *tpa_start1)
1071 {
1072 u8 agg_id = TPA_START_AGG_ID(tpa_start);
1073 u16 cons, prod;
1074 struct bnxt_tpa_info *tpa_info;
1075 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
1076 struct rx_bd *prod_bd;
1077 dma_addr_t mapping;
1078
1079 cons = tpa_start->rx_tpa_start_cmp_opaque;
1080 prod = rxr->rx_prod;
1081 cons_rx_buf = &rxr->rx_buf_ring[cons];
1082 prod_rx_buf = &rxr->rx_buf_ring[prod];
1083 tpa_info = &rxr->rx_tpa[agg_id];
1084
1085 if (unlikely(cons != rxr->rx_next_cons)) {
1086 bnxt_sched_reset(bp, rxr);
1087 return;
1088 }
1089 /* Store cfa_code in tpa_info to use in tpa_end
1090 * completion processing.
1091 */
1092 tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1);
1093 prod_rx_buf->data = tpa_info->data;
1094 prod_rx_buf->data_ptr = tpa_info->data_ptr;
1095
1096 mapping = tpa_info->mapping;
1097 prod_rx_buf->mapping = mapping;
1098
1099 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1100
1101 prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
1102
1103 tpa_info->data = cons_rx_buf->data;
1104 tpa_info->data_ptr = cons_rx_buf->data_ptr;
1105 cons_rx_buf->data = NULL;
1106 tpa_info->mapping = cons_rx_buf->mapping;
1107
1108 tpa_info->len =
1109 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
1110 RX_TPA_START_CMP_LEN_SHIFT;
1111 if (likely(TPA_START_HASH_VALID(tpa_start))) {
1112 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
1113
1114 tpa_info->hash_type = PKT_HASH_TYPE_L4;
1115 tpa_info->gso_type = SKB_GSO_TCPV4;
1116 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1117 if (hash_type == 3)
1118 tpa_info->gso_type = SKB_GSO_TCPV6;
1119 tpa_info->rss_hash =
1120 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
1121 } else {
1122 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
1123 tpa_info->gso_type = 0;
1124 if (netif_msg_rx_err(bp))
1125 netdev_warn(bp->dev, "TPA packet without valid hash\n");
1126 }
1127 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
1128 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
1129 tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
1130
1131 rxr->rx_prod = NEXT_RX(prod);
1132 cons = NEXT_RX(cons);
1133 rxr->rx_next_cons = NEXT_RX(cons);
1134 cons_rx_buf = &rxr->rx_buf_ring[cons];
1135
1136 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
1137 rxr->rx_prod = NEXT_RX(rxr->rx_prod);
1138 cons_rx_buf->data = NULL;
1139 }
1140
1141 static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi,
1142 u16 cp_cons, u32 agg_bufs)
1143 {
1144 if (agg_bufs)
1145 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1146 }
1147
1148 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info,
1149 int payload_off, int tcp_ts,
1150 struct sk_buff *skb)
1151 {
1152 #ifdef CONFIG_INET
1153 struct tcphdr *th;
1154 int len, nw_off;
1155 u16 outer_ip_off, inner_ip_off, inner_mac_off;
1156 u32 hdr_info = tpa_info->hdr_info;
1157 bool loopback = false;
1158
1159 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1160 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1161 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1162
1163 /* If the packet is an internal loopback packet, the offsets will
1164 * have an extra 4 bytes.
1165 */
1166 if (inner_mac_off == 4) {
1167 loopback = true;
1168 } else if (inner_mac_off > 4) {
1169 __be16 proto = *((__be16 *)(skb->data + inner_ip_off -
1170 ETH_HLEN - 2));
1171
1172 /* We only support inner iPv4/ipv6. If we don't see the
1173 * correct protocol ID, it must be a loopback packet where
1174 * the offsets are off by 4.
1175 */
1176 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6))
1177 loopback = true;
1178 }
1179 if (loopback) {
1180 /* internal loopback packet, subtract all offsets by 4 */
1181 inner_ip_off -= 4;
1182 inner_mac_off -= 4;
1183 outer_ip_off -= 4;
1184 }
1185
1186 nw_off = inner_ip_off - ETH_HLEN;
1187 skb_set_network_header(skb, nw_off);
1188 if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) {
1189 struct ipv6hdr *iph = ipv6_hdr(skb);
1190
1191 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1192 len = skb->len - skb_transport_offset(skb);
1193 th = tcp_hdr(skb);
1194 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1195 } else {
1196 struct iphdr *iph = ip_hdr(skb);
1197
1198 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1199 len = skb->len - skb_transport_offset(skb);
1200 th = tcp_hdr(skb);
1201 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1202 }
1203
1204 if (inner_mac_off) { /* tunnel */
1205 struct udphdr *uh = NULL;
1206 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1207 ETH_HLEN - 2));
1208
1209 if (proto == htons(ETH_P_IP)) {
1210 struct iphdr *iph = (struct iphdr *)skb->data;
1211
1212 if (iph->protocol == IPPROTO_UDP)
1213 uh = (struct udphdr *)(iph + 1);
1214 } else {
1215 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1216
1217 if (iph->nexthdr == IPPROTO_UDP)
1218 uh = (struct udphdr *)(iph + 1);
1219 }
1220 if (uh) {
1221 if (uh->check)
1222 skb_shinfo(skb)->gso_type |=
1223 SKB_GSO_UDP_TUNNEL_CSUM;
1224 else
1225 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1226 }
1227 }
1228 #endif
1229 return skb;
1230 }
1231
1232 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
1233 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1234
1235 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info,
1236 int payload_off, int tcp_ts,
1237 struct sk_buff *skb)
1238 {
1239 #ifdef CONFIG_INET
1240 struct tcphdr *th;
1241 int len, nw_off, tcp_opt_len = 0;
1242
1243 if (tcp_ts)
1244 tcp_opt_len = 12;
1245
1246 if (tpa_info->gso_type == SKB_GSO_TCPV4) {
1247 struct iphdr *iph;
1248
1249 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
1250 ETH_HLEN;
1251 skb_set_network_header(skb, nw_off);
1252 iph = ip_hdr(skb);
1253 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1254 len = skb->len - skb_transport_offset(skb);
1255 th = tcp_hdr(skb);
1256 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1257 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
1258 struct ipv6hdr *iph;
1259
1260 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
1261 ETH_HLEN;
1262 skb_set_network_header(skb, nw_off);
1263 iph = ipv6_hdr(skb);
1264 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1265 len = skb->len - skb_transport_offset(skb);
1266 th = tcp_hdr(skb);
1267 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1268 } else {
1269 dev_kfree_skb_any(skb);
1270 return NULL;
1271 }
1272
1273 if (nw_off) { /* tunnel */
1274 struct udphdr *uh = NULL;
1275
1276 if (skb->protocol == htons(ETH_P_IP)) {
1277 struct iphdr *iph = (struct iphdr *)skb->data;
1278
1279 if (iph->protocol == IPPROTO_UDP)
1280 uh = (struct udphdr *)(iph + 1);
1281 } else {
1282 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1283
1284 if (iph->nexthdr == IPPROTO_UDP)
1285 uh = (struct udphdr *)(iph + 1);
1286 }
1287 if (uh) {
1288 if (uh->check)
1289 skb_shinfo(skb)->gso_type |=
1290 SKB_GSO_UDP_TUNNEL_CSUM;
1291 else
1292 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1293 }
1294 }
1295 #endif
1296 return skb;
1297 }
1298
1299 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp,
1300 struct bnxt_tpa_info *tpa_info,
1301 struct rx_tpa_end_cmp *tpa_end,
1302 struct rx_tpa_end_cmp_ext *tpa_end1,
1303 struct sk_buff *skb)
1304 {
1305 #ifdef CONFIG_INET
1306 int payload_off;
1307 u16 segs;
1308
1309 segs = TPA_END_TPA_SEGS(tpa_end);
1310 if (segs == 1)
1311 return skb;
1312
1313 NAPI_GRO_CB(skb)->count = segs;
1314 skb_shinfo(skb)->gso_size =
1315 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1316 skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1317 payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1318 RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
1319 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
1320 skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
1321 if (likely(skb))
1322 tcp_gro_complete(skb);
1323 #endif
1324 return skb;
1325 }
1326
1327 /* Given the cfa_code of a received packet determine which
1328 * netdev (vf-rep or PF) the packet is destined to.
1329 */
1330 static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code)
1331 {
1332 struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code);
1333
1334 /* if vf-rep dev is NULL, the must belongs to the PF */
1335 return dev ? dev : bp->dev;
1336 }
1337
1338 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
1339 struct bnxt_napi *bnapi,
1340 u32 *raw_cons,
1341 struct rx_tpa_end_cmp *tpa_end,
1342 struct rx_tpa_end_cmp_ext *tpa_end1,
1343 u8 *event)
1344 {
1345 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1346 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1347 u8 agg_id = TPA_END_AGG_ID(tpa_end);
1348 u8 *data_ptr, agg_bufs;
1349 u16 cp_cons = RING_CMP(*raw_cons);
1350 unsigned int len;
1351 struct bnxt_tpa_info *tpa_info;
1352 dma_addr_t mapping;
1353 struct sk_buff *skb;
1354 void *data;
1355
1356 if (unlikely(bnapi->in_reset)) {
1357 int rc = bnxt_discard_rx(bp, bnapi, raw_cons, tpa_end);
1358
1359 if (rc < 0)
1360 return ERR_PTR(-EBUSY);
1361 return NULL;
1362 }
1363
1364 tpa_info = &rxr->rx_tpa[agg_id];
1365 data = tpa_info->data;
1366 data_ptr = tpa_info->data_ptr;
1367 prefetch(data_ptr);
1368 len = tpa_info->len;
1369 mapping = tpa_info->mapping;
1370
1371 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1372 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1373
1374 if (agg_bufs) {
1375 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1376 return ERR_PTR(-EBUSY);
1377
1378 *event |= BNXT_AGG_EVENT;
1379 cp_cons = NEXT_CMP(cp_cons);
1380 }
1381
1382 if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) {
1383 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1384 if (agg_bufs > MAX_SKB_FRAGS)
1385 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1386 agg_bufs, (int)MAX_SKB_FRAGS);
1387 return NULL;
1388 }
1389
1390 if (len <= bp->rx_copy_thresh) {
1391 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping);
1392 if (!skb) {
1393 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1394 return NULL;
1395 }
1396 } else {
1397 u8 *new_data;
1398 dma_addr_t new_mapping;
1399
1400 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1401 if (!new_data) {
1402 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1403 return NULL;
1404 }
1405
1406 tpa_info->data = new_data;
1407 tpa_info->data_ptr = new_data + bp->rx_offset;
1408 tpa_info->mapping = new_mapping;
1409
1410 skb = build_skb(data, 0);
1411 dma_unmap_single_attrs(&bp->pdev->dev, mapping,
1412 bp->rx_buf_use_size, bp->rx_dir,
1413 DMA_ATTR_WEAK_ORDERING);
1414
1415 if (!skb) {
1416 kfree(data);
1417 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1418 return NULL;
1419 }
1420 skb_reserve(skb, bp->rx_offset);
1421 skb_put(skb, len);
1422 }
1423
1424 if (agg_bufs) {
1425 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1426 if (!skb) {
1427 /* Page reuse already handled by bnxt_rx_pages(). */
1428 return NULL;
1429 }
1430 }
1431
1432 skb->protocol =
1433 eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code));
1434
1435 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1436 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1437
1438 if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1439 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1440 u16 vlan_proto = tpa_info->metadata >>
1441 RX_CMP_FLAGS2_METADATA_TPID_SFT;
1442 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1443
1444 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1445 }
1446
1447 skb_checksum_none_assert(skb);
1448 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1449 skb->ip_summed = CHECKSUM_UNNECESSARY;
1450 skb->csum_level =
1451 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1452 }
1453
1454 if (TPA_END_GRO(tpa_end))
1455 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb);
1456
1457 return skb;
1458 }
1459
1460 static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi,
1461 struct sk_buff *skb)
1462 {
1463 if (skb->dev != bp->dev) {
1464 /* this packet belongs to a vf-rep */
1465 bnxt_vf_rep_rx(bp, skb);
1466 return;
1467 }
1468 skb_record_rx_queue(skb, bnapi->index);
1469 napi_gro_receive(&bnapi->napi, skb);
1470 }
1471
1472 /* returns the following:
1473 * 1 - 1 packet successfully received
1474 * 0 - successful TPA_START, packet not completed yet
1475 * -EBUSY - completion ring does not have all the agg buffers yet
1476 * -ENOMEM - packet aborted due to out of memory
1477 * -EIO - packet aborted due to hw error indicated in BD
1478 */
1479 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons,
1480 u8 *event)
1481 {
1482 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1483 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1484 struct net_device *dev = bp->dev;
1485 struct rx_cmp *rxcmp;
1486 struct rx_cmp_ext *rxcmp1;
1487 u32 tmp_raw_cons = *raw_cons;
1488 u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1489 struct bnxt_sw_rx_bd *rx_buf;
1490 unsigned int len;
1491 u8 *data_ptr, agg_bufs, cmp_type;
1492 dma_addr_t dma_addr;
1493 struct sk_buff *skb;
1494 void *data;
1495 int rc = 0;
1496 u32 misc;
1497
1498 rxcmp = (struct rx_cmp *)
1499 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1500
1501 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1502 cp_cons = RING_CMP(tmp_raw_cons);
1503 rxcmp1 = (struct rx_cmp_ext *)
1504 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1505
1506 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1507 return -EBUSY;
1508
1509 cmp_type = RX_CMP_TYPE(rxcmp);
1510
1511 prod = rxr->rx_prod;
1512
1513 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1514 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1515 (struct rx_tpa_start_cmp_ext *)rxcmp1);
1516
1517 *event |= BNXT_RX_EVENT;
1518 goto next_rx_no_prod_no_len;
1519
1520 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1521 skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons,
1522 (struct rx_tpa_end_cmp *)rxcmp,
1523 (struct rx_tpa_end_cmp_ext *)rxcmp1, event);
1524
1525 if (IS_ERR(skb))
1526 return -EBUSY;
1527
1528 rc = -ENOMEM;
1529 if (likely(skb)) {
1530 bnxt_deliver_skb(bp, bnapi, skb);
1531 rc = 1;
1532 }
1533 *event |= BNXT_RX_EVENT;
1534 goto next_rx_no_prod_no_len;
1535 }
1536
1537 cons = rxcmp->rx_cmp_opaque;
1538 rx_buf = &rxr->rx_buf_ring[cons];
1539 data = rx_buf->data;
1540 data_ptr = rx_buf->data_ptr;
1541 if (unlikely(cons != rxr->rx_next_cons)) {
1542 int rc1 = bnxt_discard_rx(bp, bnapi, raw_cons, rxcmp);
1543
1544 bnxt_sched_reset(bp, rxr);
1545 return rc1;
1546 }
1547 prefetch(data_ptr);
1548
1549 misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1);
1550 agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT;
1551
1552 if (agg_bufs) {
1553 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1554 return -EBUSY;
1555
1556 cp_cons = NEXT_CMP(cp_cons);
1557 *event |= BNXT_AGG_EVENT;
1558 }
1559 *event |= BNXT_RX_EVENT;
1560
1561 rx_buf->data = NULL;
1562 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1563 bnxt_reuse_rx_data(rxr, cons, data);
1564 if (agg_bufs)
1565 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1566
1567 rc = -EIO;
1568 goto next_rx;
1569 }
1570
1571 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1572 dma_addr = rx_buf->mapping;
1573
1574 if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) {
1575 rc = 1;
1576 goto next_rx;
1577 }
1578
1579 if (len <= bp->rx_copy_thresh) {
1580 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr);
1581 bnxt_reuse_rx_data(rxr, cons, data);
1582 if (!skb) {
1583 rc = -ENOMEM;
1584 goto next_rx;
1585 }
1586 } else {
1587 u32 payload;
1588
1589 if (rx_buf->data_ptr == data_ptr)
1590 payload = misc & RX_CMP_PAYLOAD_OFFSET;
1591 else
1592 payload = 0;
1593 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr,
1594 payload | len);
1595 if (!skb) {
1596 rc = -ENOMEM;
1597 goto next_rx;
1598 }
1599 }
1600
1601 if (agg_bufs) {
1602 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1603 if (!skb) {
1604 rc = -ENOMEM;
1605 goto next_rx;
1606 }
1607 }
1608
1609 if (RX_CMP_HASH_VALID(rxcmp)) {
1610 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1611 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1612
1613 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1614 if (hash_type != 1 && hash_type != 3)
1615 type = PKT_HASH_TYPE_L3;
1616 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1617 }
1618
1619 cfa_code = RX_CMP_CFA_CODE(rxcmp1);
1620 skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code));
1621
1622 if ((rxcmp1->rx_cmp_flags2 &
1623 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
1624 (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1625 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1626 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1627 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1628
1629 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1630 }
1631
1632 skb_checksum_none_assert(skb);
1633 if (RX_CMP_L4_CS_OK(rxcmp1)) {
1634 if (dev->features & NETIF_F_RXCSUM) {
1635 skb->ip_summed = CHECKSUM_UNNECESSARY;
1636 skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1637 }
1638 } else {
1639 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1640 if (dev->features & NETIF_F_RXCSUM)
1641 cpr->rx_l4_csum_errors++;
1642 }
1643 }
1644
1645 bnxt_deliver_skb(bp, bnapi, skb);
1646 rc = 1;
1647
1648 next_rx:
1649 rxr->rx_prod = NEXT_RX(prod);
1650 rxr->rx_next_cons = NEXT_RX(cons);
1651
1652 cpr->rx_packets += 1;
1653 cpr->rx_bytes += len;
1654
1655 next_rx_no_prod_no_len:
1656 *raw_cons = tmp_raw_cons;
1657
1658 return rc;
1659 }
1660
1661 /* In netpoll mode, if we are using a combined completion ring, we need to
1662 * discard the rx packets and recycle the buffers.
1663 */
1664 static int bnxt_force_rx_discard(struct bnxt *bp, struct bnxt_napi *bnapi,
1665 u32 *raw_cons, u8 *event)
1666 {
1667 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1668 u32 tmp_raw_cons = *raw_cons;
1669 struct rx_cmp_ext *rxcmp1;
1670 struct rx_cmp *rxcmp;
1671 u16 cp_cons;
1672 u8 cmp_type;
1673
1674 cp_cons = RING_CMP(tmp_raw_cons);
1675 rxcmp = (struct rx_cmp *)
1676 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1677
1678 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1679 cp_cons = RING_CMP(tmp_raw_cons);
1680 rxcmp1 = (struct rx_cmp_ext *)
1681 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1682
1683 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1684 return -EBUSY;
1685
1686 cmp_type = RX_CMP_TYPE(rxcmp);
1687 if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1688 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1689 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1690 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1691 struct rx_tpa_end_cmp_ext *tpa_end1;
1692
1693 tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1;
1694 tpa_end1->rx_tpa_end_cmp_errors_v2 |=
1695 cpu_to_le32(RX_TPA_END_CMP_ERRORS);
1696 }
1697 return bnxt_rx_pkt(bp, bnapi, raw_cons, event);
1698 }
1699
1700 #define BNXT_GET_EVENT_PORT(data) \
1701 ((data) & \
1702 ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
1703
1704 static int bnxt_async_event_process(struct bnxt *bp,
1705 struct hwrm_async_event_cmpl *cmpl)
1706 {
1707 u16 event_id = le16_to_cpu(cmpl->event_id);
1708
1709 /* TODO CHIMP_FW: Define event id's for link change, error etc */
1710 switch (event_id) {
1711 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
1712 u32 data1 = le32_to_cpu(cmpl->event_data1);
1713 struct bnxt_link_info *link_info = &bp->link_info;
1714
1715 if (BNXT_VF(bp))
1716 goto async_event_process_exit;
1717
1718 /* print unsupported speed warning in forced speed mode only */
1719 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED) &&
1720 (data1 & 0x20000)) {
1721 u16 fw_speed = link_info->force_link_speed;
1722 u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
1723
1724 if (speed != SPEED_UNKNOWN)
1725 netdev_warn(bp->dev, "Link speed %d no longer supported\n",
1726 speed);
1727 }
1728 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event);
1729 /* fall thru */
1730 }
1731 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
1732 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
1733 break;
1734 case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
1735 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
1736 break;
1737 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
1738 u32 data1 = le32_to_cpu(cmpl->event_data1);
1739 u16 port_id = BNXT_GET_EVENT_PORT(data1);
1740
1741 if (BNXT_VF(bp))
1742 break;
1743
1744 if (bp->pf.port_id != port_id)
1745 break;
1746
1747 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
1748 break;
1749 }
1750 case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE:
1751 if (BNXT_PF(bp))
1752 goto async_event_process_exit;
1753 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
1754 break;
1755 default:
1756 goto async_event_process_exit;
1757 }
1758 bnxt_queue_sp_work(bp);
1759 async_event_process_exit:
1760 bnxt_ulp_async_events(bp, cmpl);
1761 return 0;
1762 }
1763
1764 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1765 {
1766 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1767 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1768 struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1769 (struct hwrm_fwd_req_cmpl *)txcmp;
1770
1771 switch (cmpl_type) {
1772 case CMPL_BASE_TYPE_HWRM_DONE:
1773 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1774 if (seq_id == bp->hwrm_intr_seq_id)
1775 bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID;
1776 else
1777 netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1778 break;
1779
1780 case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1781 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1782
1783 if ((vf_id < bp->pf.first_vf_id) ||
1784 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1785 netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1786 vf_id);
1787 return -EINVAL;
1788 }
1789
1790 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1791 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1792 bnxt_queue_sp_work(bp);
1793 break;
1794
1795 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1796 bnxt_async_event_process(bp,
1797 (struct hwrm_async_event_cmpl *)txcmp);
1798
1799 default:
1800 break;
1801 }
1802
1803 return 0;
1804 }
1805
1806 static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1807 {
1808 struct bnxt_napi *bnapi = dev_instance;
1809 struct bnxt *bp = bnapi->bp;
1810 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1811 u32 cons = RING_CMP(cpr->cp_raw_cons);
1812
1813 cpr->event_ctr++;
1814 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1815 napi_schedule(&bnapi->napi);
1816 return IRQ_HANDLED;
1817 }
1818
1819 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1820 {
1821 u32 raw_cons = cpr->cp_raw_cons;
1822 u16 cons = RING_CMP(raw_cons);
1823 struct tx_cmp *txcmp;
1824
1825 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1826
1827 return TX_CMP_VALID(txcmp, raw_cons);
1828 }
1829
1830 static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1831 {
1832 struct bnxt_napi *bnapi = dev_instance;
1833 struct bnxt *bp = bnapi->bp;
1834 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1835 u32 cons = RING_CMP(cpr->cp_raw_cons);
1836 u32 int_status;
1837
1838 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1839
1840 if (!bnxt_has_work(bp, cpr)) {
1841 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
1842 /* return if erroneous interrupt */
1843 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1844 return IRQ_NONE;
1845 }
1846
1847 /* disable ring IRQ */
1848 BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell);
1849
1850 /* Return here if interrupt is shared and is disabled. */
1851 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1852 return IRQ_HANDLED;
1853
1854 napi_schedule(&bnapi->napi);
1855 return IRQ_HANDLED;
1856 }
1857
1858 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
1859 {
1860 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1861 u32 raw_cons = cpr->cp_raw_cons;
1862 u32 cons;
1863 int tx_pkts = 0;
1864 int rx_pkts = 0;
1865 u8 event = 0;
1866 struct tx_cmp *txcmp;
1867
1868 while (1) {
1869 int rc;
1870
1871 cons = RING_CMP(raw_cons);
1872 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1873
1874 if (!TX_CMP_VALID(txcmp, raw_cons))
1875 break;
1876
1877 /* The valid test of the entry must be done first before
1878 * reading any further.
1879 */
1880 dma_rmb();
1881 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1882 tx_pkts++;
1883 /* return full budget so NAPI will complete. */
1884 if (unlikely(tx_pkts > bp->tx_wake_thresh))
1885 rx_pkts = budget;
1886 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1887 if (likely(budget))
1888 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event);
1889 else
1890 rc = bnxt_force_rx_discard(bp, bnapi, &raw_cons,
1891 &event);
1892 if (likely(rc >= 0))
1893 rx_pkts += rc;
1894 /* Increment rx_pkts when rc is -ENOMEM to count towards
1895 * the NAPI budget. Otherwise, we may potentially loop
1896 * here forever if we consistently cannot allocate
1897 * buffers.
1898 */
1899 else if (rc == -ENOMEM && budget)
1900 rx_pkts++;
1901 else if (rc == -EBUSY) /* partial completion */
1902 break;
1903 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1904 CMPL_BASE_TYPE_HWRM_DONE) ||
1905 (TX_CMP_TYPE(txcmp) ==
1906 CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1907 (TX_CMP_TYPE(txcmp) ==
1908 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1909 bnxt_hwrm_handler(bp, txcmp);
1910 }
1911 raw_cons = NEXT_RAW_CMP(raw_cons);
1912
1913 if (rx_pkts == budget)
1914 break;
1915 }
1916
1917 if (event & BNXT_TX_EVENT) {
1918 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
1919 void __iomem *db = txr->tx_doorbell;
1920 u16 prod = txr->tx_prod;
1921
1922 /* Sync BD data before updating doorbell */
1923 wmb();
1924
1925 bnxt_db_write(bp, db, DB_KEY_TX | prod);
1926 }
1927
1928 cpr->cp_raw_cons = raw_cons;
1929 /* ACK completion ring before freeing tx ring and producing new
1930 * buffers in rx/agg rings to prevent overflowing the completion
1931 * ring.
1932 */
1933 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1934
1935 if (tx_pkts)
1936 bnapi->tx_int(bp, bnapi, tx_pkts);
1937
1938 if (event & BNXT_RX_EVENT) {
1939 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1940
1941 bnxt_db_write(bp, rxr->rx_doorbell, DB_KEY_RX | rxr->rx_prod);
1942 if (event & BNXT_AGG_EVENT)
1943 bnxt_db_write(bp, rxr->rx_agg_doorbell,
1944 DB_KEY_RX | rxr->rx_agg_prod);
1945 }
1946 return rx_pkts;
1947 }
1948
1949 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget)
1950 {
1951 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1952 struct bnxt *bp = bnapi->bp;
1953 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1954 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1955 struct tx_cmp *txcmp;
1956 struct rx_cmp_ext *rxcmp1;
1957 u32 cp_cons, tmp_raw_cons;
1958 u32 raw_cons = cpr->cp_raw_cons;
1959 u32 rx_pkts = 0;
1960 u8 event = 0;
1961
1962 while (1) {
1963 int rc;
1964
1965 cp_cons = RING_CMP(raw_cons);
1966 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1967
1968 if (!TX_CMP_VALID(txcmp, raw_cons))
1969 break;
1970
1971 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1972 tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
1973 cp_cons = RING_CMP(tmp_raw_cons);
1974 rxcmp1 = (struct rx_cmp_ext *)
1975 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1976
1977 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1978 break;
1979
1980 /* force an error to recycle the buffer */
1981 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1982 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1983
1984 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event);
1985 if (likely(rc == -EIO) && budget)
1986 rx_pkts++;
1987 else if (rc == -EBUSY) /* partial completion */
1988 break;
1989 } else if (unlikely(TX_CMP_TYPE(txcmp) ==
1990 CMPL_BASE_TYPE_HWRM_DONE)) {
1991 bnxt_hwrm_handler(bp, txcmp);
1992 } else {
1993 netdev_err(bp->dev,
1994 "Invalid completion received on special ring\n");
1995 }
1996 raw_cons = NEXT_RAW_CMP(raw_cons);
1997
1998 if (rx_pkts == budget)
1999 break;
2000 }
2001
2002 cpr->cp_raw_cons = raw_cons;
2003 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
2004 bnxt_db_write(bp, rxr->rx_doorbell, DB_KEY_RX | rxr->rx_prod);
2005
2006 if (event & BNXT_AGG_EVENT)
2007 bnxt_db_write(bp, rxr->rx_agg_doorbell,
2008 DB_KEY_RX | rxr->rx_agg_prod);
2009
2010 if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) {
2011 napi_complete_done(napi, rx_pkts);
2012 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
2013 }
2014 return rx_pkts;
2015 }
2016
2017 static int bnxt_poll(struct napi_struct *napi, int budget)
2018 {
2019 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2020 struct bnxt *bp = bnapi->bp;
2021 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2022 int work_done = 0;
2023
2024 while (1) {
2025 work_done += bnxt_poll_work(bp, bnapi, budget - work_done);
2026
2027 if (work_done >= budget)
2028 break;
2029
2030 if (!bnxt_has_work(bp, cpr)) {
2031 if (napi_complete_done(napi, work_done))
2032 BNXT_CP_DB_REARM(cpr->cp_doorbell,
2033 cpr->cp_raw_cons);
2034 break;
2035 }
2036 }
2037 if (bp->flags & BNXT_FLAG_DIM) {
2038 struct net_dim_sample dim_sample;
2039
2040 net_dim_sample(cpr->event_ctr,
2041 cpr->rx_packets,
2042 cpr->rx_bytes,
2043 &dim_sample);
2044 net_dim(&cpr->dim, dim_sample);
2045 }
2046 mmiowb();
2047 return work_done;
2048 }
2049
2050 static void bnxt_free_tx_skbs(struct bnxt *bp)
2051 {
2052 int i, max_idx;
2053 struct pci_dev *pdev = bp->pdev;
2054
2055 if (!bp->tx_ring)
2056 return;
2057
2058 max_idx = bp->tx_nr_pages * TX_DESC_CNT;
2059 for (i = 0; i < bp->tx_nr_rings; i++) {
2060 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2061 int j;
2062
2063 for (j = 0; j < max_idx;) {
2064 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
2065 struct sk_buff *skb = tx_buf->skb;
2066 int k, last;
2067
2068 if (!skb) {
2069 j++;
2070 continue;
2071 }
2072
2073 tx_buf->skb = NULL;
2074
2075 if (tx_buf->is_push) {
2076 dev_kfree_skb(skb);
2077 j += 2;
2078 continue;
2079 }
2080
2081 dma_unmap_single(&pdev->dev,
2082 dma_unmap_addr(tx_buf, mapping),
2083 skb_headlen(skb),
2084 PCI_DMA_TODEVICE);
2085
2086 last = tx_buf->nr_frags;
2087 j += 2;
2088 for (k = 0; k < last; k++, j++) {
2089 int ring_idx = j & bp->tx_ring_mask;
2090 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
2091
2092 tx_buf = &txr->tx_buf_ring[ring_idx];
2093 dma_unmap_page(
2094 &pdev->dev,
2095 dma_unmap_addr(tx_buf, mapping),
2096 skb_frag_size(frag), PCI_DMA_TODEVICE);
2097 }
2098 dev_kfree_skb(skb);
2099 }
2100 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
2101 }
2102 }
2103
2104 static void bnxt_free_rx_skbs(struct bnxt *bp)
2105 {
2106 int i, max_idx, max_agg_idx;
2107 struct pci_dev *pdev = bp->pdev;
2108
2109 if (!bp->rx_ring)
2110 return;
2111
2112 max_idx = bp->rx_nr_pages * RX_DESC_CNT;
2113 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
2114 for (i = 0; i < bp->rx_nr_rings; i++) {
2115 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2116 int j;
2117
2118 if (rxr->rx_tpa) {
2119 for (j = 0; j < MAX_TPA; j++) {
2120 struct bnxt_tpa_info *tpa_info =
2121 &rxr->rx_tpa[j];
2122 u8 *data = tpa_info->data;
2123
2124 if (!data)
2125 continue;
2126
2127 dma_unmap_single_attrs(&pdev->dev,
2128 tpa_info->mapping,
2129 bp->rx_buf_use_size,
2130 bp->rx_dir,
2131 DMA_ATTR_WEAK_ORDERING);
2132
2133 tpa_info->data = NULL;
2134
2135 kfree(data);
2136 }
2137 }
2138
2139 for (j = 0; j < max_idx; j++) {
2140 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
2141 dma_addr_t mapping = rx_buf->mapping;
2142 void *data = rx_buf->data;
2143
2144 if (!data)
2145 continue;
2146
2147 rx_buf->data = NULL;
2148
2149 if (BNXT_RX_PAGE_MODE(bp)) {
2150 mapping -= bp->rx_dma_offset;
2151 dma_unmap_page_attrs(&pdev->dev, mapping,
2152 PAGE_SIZE, bp->rx_dir,
2153 DMA_ATTR_WEAK_ORDERING);
2154 __free_page(data);
2155 } else {
2156 dma_unmap_single_attrs(&pdev->dev, mapping,
2157 bp->rx_buf_use_size,
2158 bp->rx_dir,
2159 DMA_ATTR_WEAK_ORDERING);
2160 kfree(data);
2161 }
2162 }
2163
2164 for (j = 0; j < max_agg_idx; j++) {
2165 struct bnxt_sw_rx_agg_bd *rx_agg_buf =
2166 &rxr->rx_agg_ring[j];
2167 struct page *page = rx_agg_buf->page;
2168
2169 if (!page)
2170 continue;
2171
2172 dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping,
2173 BNXT_RX_PAGE_SIZE,
2174 PCI_DMA_FROMDEVICE,
2175 DMA_ATTR_WEAK_ORDERING);
2176
2177 rx_agg_buf->page = NULL;
2178 __clear_bit(j, rxr->rx_agg_bmap);
2179
2180 __free_page(page);
2181 }
2182 if (rxr->rx_page) {
2183 __free_page(rxr->rx_page);
2184 rxr->rx_page = NULL;
2185 }
2186 }
2187 }
2188
2189 static void bnxt_free_skbs(struct bnxt *bp)
2190 {
2191 bnxt_free_tx_skbs(bp);
2192 bnxt_free_rx_skbs(bp);
2193 }
2194
2195 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
2196 {
2197 struct pci_dev *pdev = bp->pdev;
2198 int i;
2199
2200 for (i = 0; i < ring->nr_pages; i++) {
2201 if (!ring->pg_arr[i])
2202 continue;
2203
2204 dma_free_coherent(&pdev->dev, ring->page_size,
2205 ring->pg_arr[i], ring->dma_arr[i]);
2206
2207 ring->pg_arr[i] = NULL;
2208 }
2209 if (ring->pg_tbl) {
2210 dma_free_coherent(&pdev->dev, ring->nr_pages * 8,
2211 ring->pg_tbl, ring->pg_tbl_map);
2212 ring->pg_tbl = NULL;
2213 }
2214 if (ring->vmem_size && *ring->vmem) {
2215 vfree(*ring->vmem);
2216 *ring->vmem = NULL;
2217 }
2218 }
2219
2220 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
2221 {
2222 int i;
2223 struct pci_dev *pdev = bp->pdev;
2224
2225 if (ring->nr_pages > 1) {
2226 ring->pg_tbl = dma_alloc_coherent(&pdev->dev,
2227 ring->nr_pages * 8,
2228 &ring->pg_tbl_map,
2229 GFP_KERNEL);
2230 if (!ring->pg_tbl)
2231 return -ENOMEM;
2232 }
2233
2234 for (i = 0; i < ring->nr_pages; i++) {
2235 ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
2236 ring->page_size,
2237 &ring->dma_arr[i],
2238 GFP_KERNEL);
2239 if (!ring->pg_arr[i])
2240 return -ENOMEM;
2241
2242 if (ring->nr_pages > 1)
2243 ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]);
2244 }
2245
2246 if (ring->vmem_size) {
2247 *ring->vmem = vzalloc(ring->vmem_size);
2248 if (!(*ring->vmem))
2249 return -ENOMEM;
2250 }
2251 return 0;
2252 }
2253
2254 static void bnxt_free_rx_rings(struct bnxt *bp)
2255 {
2256 int i;
2257
2258 if (!bp->rx_ring)
2259 return;
2260
2261 for (i = 0; i < bp->rx_nr_rings; i++) {
2262 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2263 struct bnxt_ring_struct *ring;
2264
2265 if (rxr->xdp_prog)
2266 bpf_prog_put(rxr->xdp_prog);
2267
2268 if (xdp_rxq_info_is_reg(&rxr->xdp_rxq))
2269 xdp_rxq_info_unreg(&rxr->xdp_rxq);
2270
2271 kfree(rxr->rx_tpa);
2272 rxr->rx_tpa = NULL;
2273
2274 kfree(rxr->rx_agg_bmap);
2275 rxr->rx_agg_bmap = NULL;
2276
2277 ring = &rxr->rx_ring_struct;
2278 bnxt_free_ring(bp, ring);
2279
2280 ring = &rxr->rx_agg_ring_struct;
2281 bnxt_free_ring(bp, ring);
2282 }
2283 }
2284
2285 static int bnxt_alloc_rx_rings(struct bnxt *bp)
2286 {
2287 int i, rc, agg_rings = 0, tpa_rings = 0;
2288
2289 if (!bp->rx_ring)
2290 return -ENOMEM;
2291
2292 if (bp->flags & BNXT_FLAG_AGG_RINGS)
2293 agg_rings = 1;
2294
2295 if (bp->flags & BNXT_FLAG_TPA)
2296 tpa_rings = 1;
2297
2298 for (i = 0; i < bp->rx_nr_rings; i++) {
2299 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2300 struct bnxt_ring_struct *ring;
2301
2302 ring = &rxr->rx_ring_struct;
2303
2304 rc = xdp_rxq_info_reg(&rxr->xdp_rxq, bp->dev, i);
2305 if (rc < 0)
2306 return rc;
2307
2308 rc = bnxt_alloc_ring(bp, ring);
2309 if (rc)
2310 return rc;
2311
2312 if (agg_rings) {
2313 u16 mem_size;
2314
2315 ring = &rxr->rx_agg_ring_struct;
2316 rc = bnxt_alloc_ring(bp, ring);
2317 if (rc)
2318 return rc;
2319
2320 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
2321 mem_size = rxr->rx_agg_bmap_size / 8;
2322 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
2323 if (!rxr->rx_agg_bmap)
2324 return -ENOMEM;
2325
2326 if (tpa_rings) {
2327 rxr->rx_tpa = kcalloc(MAX_TPA,
2328 sizeof(struct bnxt_tpa_info),
2329 GFP_KERNEL);
2330 if (!rxr->rx_tpa)
2331 return -ENOMEM;
2332 }
2333 }
2334 }
2335 return 0;
2336 }
2337
2338 static void bnxt_free_tx_rings(struct bnxt *bp)
2339 {
2340 int i;
2341 struct pci_dev *pdev = bp->pdev;
2342
2343 if (!bp->tx_ring)
2344 return;
2345
2346 for (i = 0; i < bp->tx_nr_rings; i++) {
2347 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2348 struct bnxt_ring_struct *ring;
2349
2350 if (txr->tx_push) {
2351 dma_free_coherent(&pdev->dev, bp->tx_push_size,
2352 txr->tx_push, txr->tx_push_mapping);
2353 txr->tx_push = NULL;
2354 }
2355
2356 ring = &txr->tx_ring_struct;
2357
2358 bnxt_free_ring(bp, ring);
2359 }
2360 }
2361
2362 static int bnxt_alloc_tx_rings(struct bnxt *bp)
2363 {
2364 int i, j, rc;
2365 struct pci_dev *pdev = bp->pdev;
2366
2367 bp->tx_push_size = 0;
2368 if (bp->tx_push_thresh) {
2369 int push_size;
2370
2371 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
2372 bp->tx_push_thresh);
2373
2374 if (push_size > 256) {
2375 push_size = 0;
2376 bp->tx_push_thresh = 0;
2377 }
2378
2379 bp->tx_push_size = push_size;
2380 }
2381
2382 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
2383 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2384 struct bnxt_ring_struct *ring;
2385
2386 ring = &txr->tx_ring_struct;
2387
2388 rc = bnxt_alloc_ring(bp, ring);
2389 if (rc)
2390 return rc;
2391
2392 if (bp->tx_push_size) {
2393 dma_addr_t mapping;
2394
2395 /* One pre-allocated DMA buffer to backup
2396 * TX push operation
2397 */
2398 txr->tx_push = dma_alloc_coherent(&pdev->dev,
2399 bp->tx_push_size,
2400 &txr->tx_push_mapping,
2401 GFP_KERNEL);
2402
2403 if (!txr->tx_push)
2404 return -ENOMEM;
2405
2406 mapping = txr->tx_push_mapping +
2407 sizeof(struct tx_push_bd);
2408 txr->data_mapping = cpu_to_le64(mapping);
2409
2410 memset(txr->tx_push, 0, sizeof(struct tx_push_bd));
2411 }
2412 ring->queue_id = bp->q_info[j].queue_id;
2413 if (i < bp->tx_nr_rings_xdp)
2414 continue;
2415 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
2416 j++;
2417 }
2418 return 0;
2419 }
2420
2421 static void bnxt_free_cp_rings(struct bnxt *bp)
2422 {
2423 int i;
2424
2425 if (!bp->bnapi)
2426 return;
2427
2428 for (i = 0; i < bp->cp_nr_rings; i++) {
2429 struct bnxt_napi *bnapi = bp->bnapi[i];
2430 struct bnxt_cp_ring_info *cpr;
2431 struct bnxt_ring_struct *ring;
2432
2433 if (!bnapi)
2434 continue;
2435
2436 cpr = &bnapi->cp_ring;
2437 ring = &cpr->cp_ring_struct;
2438
2439 bnxt_free_ring(bp, ring);
2440 }
2441 }
2442
2443 static int bnxt_alloc_cp_rings(struct bnxt *bp)
2444 {
2445 int i, rc;
2446
2447 for (i = 0; i < bp->cp_nr_rings; i++) {
2448 struct bnxt_napi *bnapi = bp->bnapi[i];
2449 struct bnxt_cp_ring_info *cpr;
2450 struct bnxt_ring_struct *ring;
2451
2452 if (!bnapi)
2453 continue;
2454
2455 cpr = &bnapi->cp_ring;
2456 ring = &cpr->cp_ring_struct;
2457
2458 rc = bnxt_alloc_ring(bp, ring);
2459 if (rc)
2460 return rc;
2461 }
2462 return 0;
2463 }
2464
2465 static void bnxt_init_ring_struct(struct bnxt *bp)
2466 {
2467 int i;
2468
2469 for (i = 0; i < bp->cp_nr_rings; i++) {
2470 struct bnxt_napi *bnapi = bp->bnapi[i];
2471 struct bnxt_cp_ring_info *cpr;
2472 struct bnxt_rx_ring_info *rxr;
2473 struct bnxt_tx_ring_info *txr;
2474 struct bnxt_ring_struct *ring;
2475
2476 if (!bnapi)
2477 continue;
2478
2479 cpr = &bnapi->cp_ring;
2480 ring = &cpr->cp_ring_struct;
2481 ring->nr_pages = bp->cp_nr_pages;
2482 ring->page_size = HW_CMPD_RING_SIZE;
2483 ring->pg_arr = (void **)cpr->cp_desc_ring;
2484 ring->dma_arr = cpr->cp_desc_mapping;
2485 ring->vmem_size = 0;
2486
2487 rxr = bnapi->rx_ring;
2488 if (!rxr)
2489 goto skip_rx;
2490
2491 ring = &rxr->rx_ring_struct;
2492 ring->nr_pages = bp->rx_nr_pages;
2493 ring->page_size = HW_RXBD_RING_SIZE;
2494 ring->pg_arr = (void **)rxr->rx_desc_ring;
2495 ring->dma_arr = rxr->rx_desc_mapping;
2496 ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
2497 ring->vmem = (void **)&rxr->rx_buf_ring;
2498
2499 ring = &rxr->rx_agg_ring_struct;
2500 ring->nr_pages = bp->rx_agg_nr_pages;
2501 ring->page_size = HW_RXBD_RING_SIZE;
2502 ring->pg_arr = (void **)rxr->rx_agg_desc_ring;
2503 ring->dma_arr = rxr->rx_agg_desc_mapping;
2504 ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
2505 ring->vmem = (void **)&rxr->rx_agg_ring;
2506
2507 skip_rx:
2508 txr = bnapi->tx_ring;
2509 if (!txr)
2510 continue;
2511
2512 ring = &txr->tx_ring_struct;
2513 ring->nr_pages = bp->tx_nr_pages;
2514 ring->page_size = HW_RXBD_RING_SIZE;
2515 ring->pg_arr = (void **)txr->tx_desc_ring;
2516 ring->dma_arr = txr->tx_desc_mapping;
2517 ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
2518 ring->vmem = (void **)&txr->tx_buf_ring;
2519 }
2520 }
2521
2522 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
2523 {
2524 int i;
2525 u32 prod;
2526 struct rx_bd **rx_buf_ring;
2527
2528 rx_buf_ring = (struct rx_bd **)ring->pg_arr;
2529 for (i = 0, prod = 0; i < ring->nr_pages; i++) {
2530 int j;
2531 struct rx_bd *rxbd;
2532
2533 rxbd = rx_buf_ring[i];
2534 if (!rxbd)
2535 continue;
2536
2537 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
2538 rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
2539 rxbd->rx_bd_opaque = prod;
2540 }
2541 }
2542 }
2543
2544 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
2545 {
2546 struct net_device *dev = bp->dev;
2547 struct bnxt_rx_ring_info *rxr;
2548 struct bnxt_ring_struct *ring;
2549 u32 prod, type;
2550 int i;
2551
2552 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
2553 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
2554
2555 if (NET_IP_ALIGN == 2)
2556 type |= RX_BD_FLAGS_SOP;
2557
2558 rxr = &bp->rx_ring[ring_nr];
2559 ring = &rxr->rx_ring_struct;
2560 bnxt_init_rxbd_pages(ring, type);
2561
2562 if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) {
2563 rxr->xdp_prog = bpf_prog_add(bp->xdp_prog, 1);
2564 if (IS_ERR(rxr->xdp_prog)) {
2565 int rc = PTR_ERR(rxr->xdp_prog);
2566
2567 rxr->xdp_prog = NULL;
2568 return rc;
2569 }
2570 }
2571 prod = rxr->rx_prod;
2572 for (i = 0; i < bp->rx_ring_size; i++) {
2573 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
2574 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
2575 ring_nr, i, bp->rx_ring_size);
2576 break;
2577 }
2578 prod = NEXT_RX(prod);
2579 }
2580 rxr->rx_prod = prod;
2581 ring->fw_ring_id = INVALID_HW_RING_ID;
2582
2583 ring = &rxr->rx_agg_ring_struct;
2584 ring->fw_ring_id = INVALID_HW_RING_ID;
2585
2586 if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
2587 return 0;
2588
2589 type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
2590 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
2591
2592 bnxt_init_rxbd_pages(ring, type);
2593
2594 prod = rxr->rx_agg_prod;
2595 for (i = 0; i < bp->rx_agg_ring_size; i++) {
2596 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
2597 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
2598 ring_nr, i, bp->rx_ring_size);
2599 break;
2600 }
2601 prod = NEXT_RX_AGG(prod);
2602 }
2603 rxr->rx_agg_prod = prod;
2604
2605 if (bp->flags & BNXT_FLAG_TPA) {
2606 if (rxr->rx_tpa) {
2607 u8 *data;
2608 dma_addr_t mapping;
2609
2610 for (i = 0; i < MAX_TPA; i++) {
2611 data = __bnxt_alloc_rx_data(bp, &mapping,
2612 GFP_KERNEL);
2613 if (!data)
2614 return -ENOMEM;
2615
2616 rxr->rx_tpa[i].data = data;
2617 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset;
2618 rxr->rx_tpa[i].mapping = mapping;
2619 }
2620 } else {
2621 netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2622 return -ENOMEM;
2623 }
2624 }
2625
2626 return 0;
2627 }
2628
2629 static void bnxt_init_cp_rings(struct bnxt *bp)
2630 {
2631 int i;
2632
2633 for (i = 0; i < bp->cp_nr_rings; i++) {
2634 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
2635 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
2636
2637 ring->fw_ring_id = INVALID_HW_RING_ID;
2638 cpr->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
2639 cpr->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
2640 }
2641 }
2642
2643 static int bnxt_init_rx_rings(struct bnxt *bp)
2644 {
2645 int i, rc = 0;
2646
2647 if (BNXT_RX_PAGE_MODE(bp)) {
2648 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM;
2649 bp->rx_dma_offset = XDP_PACKET_HEADROOM;
2650 } else {
2651 bp->rx_offset = BNXT_RX_OFFSET;
2652 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET;
2653 }
2654
2655 for (i = 0; i < bp->rx_nr_rings; i++) {
2656 rc = bnxt_init_one_rx_ring(bp, i);
2657 if (rc)
2658 break;
2659 }
2660
2661 return rc;
2662 }
2663
2664 static int bnxt_init_tx_rings(struct bnxt *bp)
2665 {
2666 u16 i;
2667
2668 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2669 MAX_SKB_FRAGS + 1);
2670
2671 for (i = 0; i < bp->tx_nr_rings; i++) {
2672 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2673 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2674
2675 ring->fw_ring_id = INVALID_HW_RING_ID;
2676 }
2677
2678 return 0;
2679 }
2680
2681 static void bnxt_free_ring_grps(struct bnxt *bp)
2682 {
2683 kfree(bp->grp_info);
2684 bp->grp_info = NULL;
2685 }
2686
2687 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2688 {
2689 int i;
2690
2691 if (irq_re_init) {
2692 bp->grp_info = kcalloc(bp->cp_nr_rings,
2693 sizeof(struct bnxt_ring_grp_info),
2694 GFP_KERNEL);
2695 if (!bp->grp_info)
2696 return -ENOMEM;
2697 }
2698 for (i = 0; i < bp->cp_nr_rings; i++) {
2699 if (irq_re_init)
2700 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
2701 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
2702 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
2703 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
2704 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
2705 }
2706 return 0;
2707 }
2708
2709 static void bnxt_free_vnics(struct bnxt *bp)
2710 {
2711 kfree(bp->vnic_info);
2712 bp->vnic_info = NULL;
2713 bp->nr_vnics = 0;
2714 }
2715
2716 static int bnxt_alloc_vnics(struct bnxt *bp)
2717 {
2718 int num_vnics = 1;
2719
2720 #ifdef CONFIG_RFS_ACCEL
2721 if (bp->flags & BNXT_FLAG_RFS)
2722 num_vnics += bp->rx_nr_rings;
2723 #endif
2724
2725 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
2726 num_vnics++;
2727
2728 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
2729 GFP_KERNEL);
2730 if (!bp->vnic_info)
2731 return -ENOMEM;
2732
2733 bp->nr_vnics = num_vnics;
2734 return 0;
2735 }
2736
2737 static void bnxt_init_vnics(struct bnxt *bp)
2738 {
2739 int i;
2740
2741 for (i = 0; i < bp->nr_vnics; i++) {
2742 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2743
2744 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2745 vnic->fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
2746 vnic->fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
2747 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
2748
2749 if (bp->vnic_info[i].rss_hash_key) {
2750 if (i == 0)
2751 prandom_bytes(vnic->rss_hash_key,
2752 HW_HASH_KEY_SIZE);
2753 else
2754 memcpy(vnic->rss_hash_key,
2755 bp->vnic_info[0].rss_hash_key,
2756 HW_HASH_KEY_SIZE);
2757 }
2758 }
2759 }
2760
2761 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
2762 {
2763 int pages;
2764
2765 pages = ring_size / desc_per_pg;
2766
2767 if (!pages)
2768 return 1;
2769
2770 pages++;
2771
2772 while (pages & (pages - 1))
2773 pages++;
2774
2775 return pages;
2776 }
2777
2778 void bnxt_set_tpa_flags(struct bnxt *bp)
2779 {
2780 bp->flags &= ~BNXT_FLAG_TPA;
2781 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
2782 return;
2783 if (bp->dev->features & NETIF_F_LRO)
2784 bp->flags |= BNXT_FLAG_LRO;
2785 else if (bp->dev->features & NETIF_F_GRO_HW)
2786 bp->flags |= BNXT_FLAG_GRO;
2787 }
2788
2789 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2790 * be set on entry.
2791 */
2792 void bnxt_set_ring_params(struct bnxt *bp)
2793 {
2794 u32 ring_size, rx_size, rx_space;
2795 u32 agg_factor = 0, agg_ring_size = 0;
2796
2797 /* 8 for CRC and VLAN */
2798 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
2799
2800 rx_space = rx_size + NET_SKB_PAD +
2801 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2802
2803 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
2804 ring_size = bp->rx_ring_size;
2805 bp->rx_agg_ring_size = 0;
2806 bp->rx_agg_nr_pages = 0;
2807
2808 if (bp->flags & BNXT_FLAG_TPA)
2809 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
2810
2811 bp->flags &= ~BNXT_FLAG_JUMBO;
2812 if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) {
2813 u32 jumbo_factor;
2814
2815 bp->flags |= BNXT_FLAG_JUMBO;
2816 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
2817 if (jumbo_factor > agg_factor)
2818 agg_factor = jumbo_factor;
2819 }
2820 agg_ring_size = ring_size * agg_factor;
2821
2822 if (agg_ring_size) {
2823 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
2824 RX_DESC_CNT);
2825 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
2826 u32 tmp = agg_ring_size;
2827
2828 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
2829 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
2830 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
2831 tmp, agg_ring_size);
2832 }
2833 bp->rx_agg_ring_size = agg_ring_size;
2834 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
2835 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
2836 rx_space = rx_size + NET_SKB_PAD +
2837 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2838 }
2839
2840 bp->rx_buf_use_size = rx_size;
2841 bp->rx_buf_size = rx_space;
2842
2843 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
2844 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
2845
2846 ring_size = bp->tx_ring_size;
2847 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
2848 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
2849
2850 ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
2851 bp->cp_ring_size = ring_size;
2852
2853 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
2854 if (bp->cp_nr_pages > MAX_CP_PAGES) {
2855 bp->cp_nr_pages = MAX_CP_PAGES;
2856 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
2857 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
2858 ring_size, bp->cp_ring_size);
2859 }
2860 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
2861 bp->cp_ring_mask = bp->cp_bit - 1;
2862 }
2863
2864 /* Changing allocation mode of RX rings.
2865 * TODO: Update when extending xdp_rxq_info to support allocation modes.
2866 */
2867 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode)
2868 {
2869 if (page_mode) {
2870 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU)
2871 return -EOPNOTSUPP;
2872 bp->dev->max_mtu =
2873 min_t(u16, bp->max_mtu, BNXT_MAX_PAGE_MODE_MTU);
2874 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
2875 bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE;
2876 bp->rx_dir = DMA_BIDIRECTIONAL;
2877 bp->rx_skb_func = bnxt_rx_page_skb;
2878 /* Disable LRO or GRO_HW */
2879 netdev_update_features(bp->dev);
2880 } else {
2881 bp->dev->max_mtu = bp->max_mtu;
2882 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE;
2883 bp->rx_dir = DMA_FROM_DEVICE;
2884 bp->rx_skb_func = bnxt_rx_skb;
2885 }
2886 return 0;
2887 }
2888
2889 static void bnxt_free_vnic_attributes(struct bnxt *bp)
2890 {
2891 int i;
2892 struct bnxt_vnic_info *vnic;
2893 struct pci_dev *pdev = bp->pdev;
2894
2895 if (!bp->vnic_info)
2896 return;
2897
2898 for (i = 0; i < bp->nr_vnics; i++) {
2899 vnic = &bp->vnic_info[i];
2900
2901 kfree(vnic->fw_grp_ids);
2902 vnic->fw_grp_ids = NULL;
2903
2904 kfree(vnic->uc_list);
2905 vnic->uc_list = NULL;
2906
2907 if (vnic->mc_list) {
2908 dma_free_coherent(&pdev->dev, vnic->mc_list_size,
2909 vnic->mc_list, vnic->mc_list_mapping);
2910 vnic->mc_list = NULL;
2911 }
2912
2913 if (vnic->rss_table) {
2914 dma_free_coherent(&pdev->dev, PAGE_SIZE,
2915 vnic->rss_table,
2916 vnic->rss_table_dma_addr);
2917 vnic->rss_table = NULL;
2918 }
2919
2920 vnic->rss_hash_key = NULL;
2921 vnic->flags = 0;
2922 }
2923 }
2924
2925 static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
2926 {
2927 int i, rc = 0, size;
2928 struct bnxt_vnic_info *vnic;
2929 struct pci_dev *pdev = bp->pdev;
2930 int max_rings;
2931
2932 for (i = 0; i < bp->nr_vnics; i++) {
2933 vnic = &bp->vnic_info[i];
2934
2935 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
2936 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
2937
2938 if (mem_size > 0) {
2939 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
2940 if (!vnic->uc_list) {
2941 rc = -ENOMEM;
2942 goto out;
2943 }
2944 }
2945 }
2946
2947 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
2948 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
2949 vnic->mc_list =
2950 dma_alloc_coherent(&pdev->dev,
2951 vnic->mc_list_size,
2952 &vnic->mc_list_mapping,
2953 GFP_KERNEL);
2954 if (!vnic->mc_list) {
2955 rc = -ENOMEM;
2956 goto out;
2957 }
2958 }
2959
2960 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
2961 max_rings = bp->rx_nr_rings;
2962 else
2963 max_rings = 1;
2964
2965 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
2966 if (!vnic->fw_grp_ids) {
2967 rc = -ENOMEM;
2968 goto out;
2969 }
2970
2971 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
2972 !(vnic->flags & BNXT_VNIC_RSS_FLAG))
2973 continue;
2974
2975 /* Allocate rss table and hash key */
2976 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2977 &vnic->rss_table_dma_addr,
2978 GFP_KERNEL);
2979 if (!vnic->rss_table) {
2980 rc = -ENOMEM;
2981 goto out;
2982 }
2983
2984 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
2985
2986 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
2987 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
2988 }
2989 return 0;
2990
2991 out:
2992 return rc;
2993 }
2994
2995 static void bnxt_free_hwrm_resources(struct bnxt *bp)
2996 {
2997 struct pci_dev *pdev = bp->pdev;
2998
2999 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
3000 bp->hwrm_cmd_resp_dma_addr);
3001
3002 bp->hwrm_cmd_resp_addr = NULL;
3003 if (bp->hwrm_dbg_resp_addr) {
3004 dma_free_coherent(&pdev->dev, HWRM_DBG_REG_BUF_SIZE,
3005 bp->hwrm_dbg_resp_addr,
3006 bp->hwrm_dbg_resp_dma_addr);
3007
3008 bp->hwrm_dbg_resp_addr = NULL;
3009 }
3010 }
3011
3012 static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
3013 {
3014 struct pci_dev *pdev = bp->pdev;
3015
3016 bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3017 &bp->hwrm_cmd_resp_dma_addr,
3018 GFP_KERNEL);
3019 if (!bp->hwrm_cmd_resp_addr)
3020 return -ENOMEM;
3021 bp->hwrm_dbg_resp_addr = dma_alloc_coherent(&pdev->dev,
3022 HWRM_DBG_REG_BUF_SIZE,
3023 &bp->hwrm_dbg_resp_dma_addr,
3024 GFP_KERNEL);
3025 if (!bp->hwrm_dbg_resp_addr)
3026 netdev_warn(bp->dev, "fail to alloc debug register dma mem\n");
3027
3028 return 0;
3029 }
3030
3031 static void bnxt_free_hwrm_short_cmd_req(struct bnxt *bp)
3032 {
3033 if (bp->hwrm_short_cmd_req_addr) {
3034 struct pci_dev *pdev = bp->pdev;
3035
3036 dma_free_coherent(&pdev->dev, BNXT_HWRM_MAX_REQ_LEN,
3037 bp->hwrm_short_cmd_req_addr,
3038 bp->hwrm_short_cmd_req_dma_addr);
3039 bp->hwrm_short_cmd_req_addr = NULL;
3040 }
3041 }
3042
3043 static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt *bp)
3044 {
3045 struct pci_dev *pdev = bp->pdev;
3046
3047 bp->hwrm_short_cmd_req_addr =
3048 dma_alloc_coherent(&pdev->dev, BNXT_HWRM_MAX_REQ_LEN,
3049 &bp->hwrm_short_cmd_req_dma_addr,
3050 GFP_KERNEL);
3051 if (!bp->hwrm_short_cmd_req_addr)
3052 return -ENOMEM;
3053
3054 return 0;
3055 }
3056
3057 static void bnxt_free_stats(struct bnxt *bp)
3058 {
3059 u32 size, i;
3060 struct pci_dev *pdev = bp->pdev;
3061
3062 if (bp->hw_rx_port_stats) {
3063 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size,
3064 bp->hw_rx_port_stats,
3065 bp->hw_rx_port_stats_map);
3066 bp->hw_rx_port_stats = NULL;
3067 bp->flags &= ~BNXT_FLAG_PORT_STATS;
3068 }
3069
3070 if (!bp->bnapi)
3071 return;
3072
3073 size = sizeof(struct ctx_hw_stats);
3074
3075 for (i = 0; i < bp->cp_nr_rings; i++) {
3076 struct bnxt_napi *bnapi = bp->bnapi[i];
3077 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3078
3079 if (cpr->hw_stats) {
3080 dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
3081 cpr->hw_stats_map);
3082 cpr->hw_stats = NULL;
3083 }
3084 }
3085 }
3086
3087 static int bnxt_alloc_stats(struct bnxt *bp)
3088 {
3089 u32 size, i;
3090 struct pci_dev *pdev = bp->pdev;
3091
3092 size = sizeof(struct ctx_hw_stats);
3093
3094 for (i = 0; i < bp->cp_nr_rings; i++) {
3095 struct bnxt_napi *bnapi = bp->bnapi[i];
3096 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3097
3098 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
3099 &cpr->hw_stats_map,
3100 GFP_KERNEL);
3101 if (!cpr->hw_stats)
3102 return -ENOMEM;
3103
3104 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
3105 }
3106
3107 if (BNXT_PF(bp) && bp->chip_num != CHIP_NUM_58700) {
3108 bp->hw_port_stats_size = sizeof(struct rx_port_stats) +
3109 sizeof(struct tx_port_stats) + 1024;
3110
3111 bp->hw_rx_port_stats =
3112 dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size,
3113 &bp->hw_rx_port_stats_map,
3114 GFP_KERNEL);
3115 if (!bp->hw_rx_port_stats)
3116 return -ENOMEM;
3117
3118 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) +
3119 512;
3120 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map +
3121 sizeof(struct rx_port_stats) + 512;
3122 bp->flags |= BNXT_FLAG_PORT_STATS;
3123 }
3124 return 0;
3125 }
3126
3127 static void bnxt_clear_ring_indices(struct bnxt *bp)
3128 {
3129 int i;
3130
3131 if (!bp->bnapi)
3132 return;
3133
3134 for (i = 0; i < bp->cp_nr_rings; i++) {
3135 struct bnxt_napi *bnapi = bp->bnapi[i];
3136 struct bnxt_cp_ring_info *cpr;
3137 struct bnxt_rx_ring_info *rxr;
3138 struct bnxt_tx_ring_info *txr;
3139
3140 if (!bnapi)
3141 continue;
3142
3143 cpr = &bnapi->cp_ring;
3144 cpr->cp_raw_cons = 0;
3145
3146 txr = bnapi->tx_ring;
3147 if (txr) {
3148 txr->tx_prod = 0;
3149 txr->tx_cons = 0;
3150 }
3151
3152 rxr = bnapi->rx_ring;
3153 if (rxr) {
3154 rxr->rx_prod = 0;
3155 rxr->rx_agg_prod = 0;
3156 rxr->rx_sw_agg_prod = 0;
3157 rxr->rx_next_cons = 0;
3158 }
3159 }
3160 }
3161
3162 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
3163 {
3164 #ifdef CONFIG_RFS_ACCEL
3165 int i;
3166
3167 /* Under rtnl_lock and all our NAPIs have been disabled. It's
3168 * safe to delete the hash table.
3169 */
3170 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
3171 struct hlist_head *head;
3172 struct hlist_node *tmp;
3173 struct bnxt_ntuple_filter *fltr;
3174
3175 head = &bp->ntp_fltr_hash_tbl[i];
3176 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
3177 hlist_del(&fltr->hash);
3178 kfree(fltr);
3179 }
3180 }
3181 if (irq_reinit) {
3182 kfree(bp->ntp_fltr_bmap);
3183 bp->ntp_fltr_bmap = NULL;
3184 }
3185 bp->ntp_fltr_count = 0;
3186 #endif
3187 }
3188
3189 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
3190 {
3191 #ifdef CONFIG_RFS_ACCEL
3192 int i, rc = 0;
3193
3194 if (!(bp->flags & BNXT_FLAG_RFS))
3195 return 0;
3196
3197 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
3198 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
3199
3200 bp->ntp_fltr_count = 0;
3201 bp->ntp_fltr_bmap = kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
3202 sizeof(long),
3203 GFP_KERNEL);
3204
3205 if (!bp->ntp_fltr_bmap)
3206 rc = -ENOMEM;
3207
3208 return rc;
3209 #else
3210 return 0;
3211 #endif
3212 }
3213
3214 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
3215 {
3216 bnxt_free_vnic_attributes(bp);
3217 bnxt_free_tx_rings(bp);
3218 bnxt_free_rx_rings(bp);
3219 bnxt_free_cp_rings(bp);
3220 bnxt_free_ntp_fltrs(bp, irq_re_init);
3221 if (irq_re_init) {
3222 bnxt_free_stats(bp);
3223 bnxt_free_ring_grps(bp);
3224 bnxt_free_vnics(bp);
3225 kfree(bp->tx_ring_map);
3226 bp->tx_ring_map = NULL;
3227 kfree(bp->tx_ring);
3228 bp->tx_ring = NULL;
3229 kfree(bp->rx_ring);
3230 bp->rx_ring = NULL;
3231 kfree(bp->bnapi);
3232 bp->bnapi = NULL;
3233 } else {
3234 bnxt_clear_ring_indices(bp);
3235 }
3236 }
3237
3238 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
3239 {
3240 int i, j, rc, size, arr_size;
3241 void *bnapi;
3242
3243 if (irq_re_init) {
3244 /* Allocate bnapi mem pointer array and mem block for
3245 * all queues
3246 */
3247 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
3248 bp->cp_nr_rings);
3249 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
3250 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
3251 if (!bnapi)
3252 return -ENOMEM;
3253
3254 bp->bnapi = bnapi;
3255 bnapi += arr_size;
3256 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
3257 bp->bnapi[i] = bnapi;
3258 bp->bnapi[i]->index = i;
3259 bp->bnapi[i]->bp = bp;
3260 }
3261
3262 bp->rx_ring = kcalloc(bp->rx_nr_rings,
3263 sizeof(struct bnxt_rx_ring_info),
3264 GFP_KERNEL);
3265 if (!bp->rx_ring)
3266 return -ENOMEM;
3267
3268 for (i = 0; i < bp->rx_nr_rings; i++) {
3269 bp->rx_ring[i].bnapi = bp->bnapi[i];
3270 bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
3271 }
3272
3273 bp->tx_ring = kcalloc(bp->tx_nr_rings,
3274 sizeof(struct bnxt_tx_ring_info),
3275 GFP_KERNEL);
3276 if (!bp->tx_ring)
3277 return -ENOMEM;
3278
3279 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16),
3280 GFP_KERNEL);
3281
3282 if (!bp->tx_ring_map)
3283 return -ENOMEM;
3284
3285 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
3286 j = 0;
3287 else
3288 j = bp->rx_nr_rings;
3289
3290 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
3291 bp->tx_ring[i].bnapi = bp->bnapi[j];
3292 bp->bnapi[j]->tx_ring = &bp->tx_ring[i];
3293 bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i;
3294 if (i >= bp->tx_nr_rings_xdp) {
3295 bp->tx_ring[i].txq_index = i -
3296 bp->tx_nr_rings_xdp;
3297 bp->bnapi[j]->tx_int = bnxt_tx_int;
3298 } else {
3299 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP;
3300 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp;
3301 }
3302 }
3303
3304 rc = bnxt_alloc_stats(bp);
3305 if (rc)
3306 goto alloc_mem_err;
3307
3308 rc = bnxt_alloc_ntp_fltrs(bp);
3309 if (rc)
3310 goto alloc_mem_err;
3311
3312 rc = bnxt_alloc_vnics(bp);
3313 if (rc)
3314 goto alloc_mem_err;
3315 }
3316
3317 bnxt_init_ring_struct(bp);
3318
3319 rc = bnxt_alloc_rx_rings(bp);
3320 if (rc)
3321 goto alloc_mem_err;
3322
3323 rc = bnxt_alloc_tx_rings(bp);
3324 if (rc)
3325 goto alloc_mem_err;
3326
3327 rc = bnxt_alloc_cp_rings(bp);
3328 if (rc)
3329 goto alloc_mem_err;
3330
3331 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
3332 BNXT_VNIC_UCAST_FLAG;
3333 rc = bnxt_alloc_vnic_attributes(bp);
3334 if (rc)
3335 goto alloc_mem_err;
3336 return 0;
3337
3338 alloc_mem_err:
3339 bnxt_free_mem(bp, true);
3340 return rc;
3341 }
3342
3343 static void bnxt_disable_int(struct bnxt *bp)
3344 {
3345 int i;
3346
3347 if (!bp->bnapi)
3348 return;
3349
3350 for (i = 0; i < bp->cp_nr_rings; i++) {
3351 struct bnxt_napi *bnapi = bp->bnapi[i];
3352 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3353 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3354
3355 if (ring->fw_ring_id != INVALID_HW_RING_ID)
3356 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
3357 }
3358 }
3359
3360 static void bnxt_disable_int_sync(struct bnxt *bp)
3361 {
3362 int i;
3363
3364 atomic_inc(&bp->intr_sem);
3365
3366 bnxt_disable_int(bp);
3367 for (i = 0; i < bp->cp_nr_rings; i++)
3368 synchronize_irq(bp->irq_tbl[i].vector);
3369 }
3370
3371 static void bnxt_enable_int(struct bnxt *bp)
3372 {
3373 int i;
3374
3375 atomic_set(&bp->intr_sem, 0);
3376 for (i = 0; i < bp->cp_nr_rings; i++) {
3377 struct bnxt_napi *bnapi = bp->bnapi[i];
3378 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3379
3380 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
3381 }
3382 }
3383
3384 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
3385 u16 cmpl_ring, u16 target_id)
3386 {
3387 struct input *req = request;
3388
3389 req->req_type = cpu_to_le16(req_type);
3390 req->cmpl_ring = cpu_to_le16(cmpl_ring);
3391 req->target_id = cpu_to_le16(target_id);
3392 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
3393 }
3394
3395 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
3396 int timeout, bool silent)
3397 {
3398 int i, intr_process, rc, tmo_count;
3399 struct input *req = msg;
3400 u32 *data = msg;
3401 __le32 *resp_len, *valid;
3402 u16 cp_ring_id, len = 0;
3403 struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
3404 u16 max_req_len = BNXT_HWRM_MAX_REQ_LEN;
3405 struct hwrm_short_input short_input = {0};
3406
3407 req->seq_id = cpu_to_le16(bp->hwrm_cmd_seq++);
3408 memset(resp, 0, PAGE_SIZE);
3409 cp_ring_id = le16_to_cpu(req->cmpl_ring);
3410 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
3411
3412 if (bp->flags & BNXT_FLAG_SHORT_CMD) {
3413 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
3414
3415 memcpy(short_cmd_req, req, msg_len);
3416 memset(short_cmd_req + msg_len, 0, BNXT_HWRM_MAX_REQ_LEN -
3417 msg_len);
3418
3419 short_input.req_type = req->req_type;
3420 short_input.signature =
3421 cpu_to_le16(SHORT_REQ_SIGNATURE_SHORT_CMD);
3422 short_input.size = cpu_to_le16(msg_len);
3423 short_input.req_addr =
3424 cpu_to_le64(bp->hwrm_short_cmd_req_dma_addr);
3425
3426 data = (u32 *)&short_input;
3427 msg_len = sizeof(short_input);
3428
3429 /* Sync memory write before updating doorbell */
3430 wmb();
3431
3432 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
3433 }
3434
3435 /* Write request msg to hwrm channel */
3436 __iowrite32_copy(bp->bar0, data, msg_len / 4);
3437
3438 for (i = msg_len; i < max_req_len; i += 4)
3439 writel(0, bp->bar0 + i);
3440
3441 /* currently supports only one outstanding message */
3442 if (intr_process)
3443 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
3444
3445 /* Ring channel doorbell */
3446 writel(1, bp->bar0 + 0x100);
3447
3448 if (!timeout)
3449 timeout = DFLT_HWRM_CMD_TIMEOUT;
3450
3451 i = 0;
3452 tmo_count = timeout * 40;
3453 if (intr_process) {
3454 /* Wait until hwrm response cmpl interrupt is processed */
3455 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID &&
3456 i++ < tmo_count) {
3457 usleep_range(25, 40);
3458 }
3459
3460 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) {
3461 netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
3462 le16_to_cpu(req->req_type));
3463 return -1;
3464 }
3465 } else {
3466 /* Check if response len is updated */
3467 resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET;
3468 for (i = 0; i < tmo_count; i++) {
3469 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3470 HWRM_RESP_LEN_SFT;
3471 if (len)
3472 break;
3473 usleep_range(25, 40);
3474 }
3475
3476 if (i >= tmo_count) {
3477 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
3478 timeout, le16_to_cpu(req->req_type),
3479 le16_to_cpu(req->seq_id), len);
3480 return -1;
3481 }
3482
3483 /* Last word of resp contains valid bit */
3484 valid = bp->hwrm_cmd_resp_addr + len - 4;
3485 for (i = 0; i < 5; i++) {
3486 if (le32_to_cpu(*valid) & HWRM_RESP_VALID_MASK)
3487 break;
3488 udelay(1);
3489 }
3490
3491 if (i >= 5) {
3492 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
3493 timeout, le16_to_cpu(req->req_type),
3494 le16_to_cpu(req->seq_id), len, *valid);
3495 return -1;
3496 }
3497 }
3498
3499 rc = le16_to_cpu(resp->error_code);
3500 if (rc && !silent)
3501 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
3502 le16_to_cpu(resp->req_type),
3503 le16_to_cpu(resp->seq_id), rc);
3504 return rc;
3505 }
3506
3507 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3508 {
3509 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
3510 }
3511
3512 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
3513 int timeout)
3514 {
3515 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3516 }
3517
3518 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3519 {
3520 int rc;
3521
3522 mutex_lock(&bp->hwrm_cmd_lock);
3523 rc = _hwrm_send_message(bp, msg, msg_len, timeout);
3524 mutex_unlock(&bp->hwrm_cmd_lock);
3525 return rc;
3526 }
3527
3528 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
3529 int timeout)
3530 {
3531 int rc;
3532
3533 mutex_lock(&bp->hwrm_cmd_lock);
3534 rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3535 mutex_unlock(&bp->hwrm_cmd_lock);
3536 return rc;
3537 }
3538
3539 int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap,
3540 int bmap_size)
3541 {
3542 struct hwrm_func_drv_rgtr_input req = {0};
3543 DECLARE_BITMAP(async_events_bmap, 256);
3544 u32 *events = (u32 *)async_events_bmap;
3545 int i;
3546
3547 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3548
3549 req.enables =
3550 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
3551
3552 memset(async_events_bmap, 0, sizeof(async_events_bmap));
3553 for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++)
3554 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
3555
3556 if (bmap && bmap_size) {
3557 for (i = 0; i < bmap_size; i++) {
3558 if (test_bit(i, bmap))
3559 __set_bit(i, async_events_bmap);
3560 }
3561 }
3562
3563 for (i = 0; i < 8; i++)
3564 req.async_event_fwd[i] |= cpu_to_le32(events[i]);
3565
3566 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3567 }
3568
3569 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
3570 {
3571 struct hwrm_func_drv_rgtr_input req = {0};
3572
3573 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3574
3575 req.enables =
3576 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
3577 FUNC_DRV_RGTR_REQ_ENABLES_VER);
3578
3579 req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
3580 req.ver_maj = DRV_VER_MAJ;
3581 req.ver_min = DRV_VER_MIN;
3582 req.ver_upd = DRV_VER_UPD;
3583
3584 if (BNXT_PF(bp)) {
3585 u32 data[8];
3586 int i;
3587
3588 memset(data, 0, sizeof(data));
3589 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) {
3590 u16 cmd = bnxt_vf_req_snif[i];
3591 unsigned int bit, idx;
3592
3593 idx = cmd / 32;
3594 bit = cmd % 32;
3595 data[idx] |= 1 << bit;
3596 }
3597
3598 for (i = 0; i < 8; i++)
3599 req.vf_req_fwd[i] = cpu_to_le32(data[i]);
3600
3601 req.enables |=
3602 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
3603 }
3604
3605 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3606 }
3607
3608 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
3609 {
3610 struct hwrm_func_drv_unrgtr_input req = {0};
3611
3612 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
3613 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3614 }
3615
3616 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
3617 {
3618 u32 rc = 0;
3619 struct hwrm_tunnel_dst_port_free_input req = {0};
3620
3621 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
3622 req.tunnel_type = tunnel_type;
3623
3624 switch (tunnel_type) {
3625 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
3626 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
3627 break;
3628 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
3629 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
3630 break;
3631 default:
3632 break;
3633 }
3634
3635 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3636 if (rc)
3637 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
3638 rc);
3639 return rc;
3640 }
3641
3642 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
3643 u8 tunnel_type)
3644 {
3645 u32 rc = 0;
3646 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3647 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3648
3649 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
3650
3651 req.tunnel_type = tunnel_type;
3652 req.tunnel_dst_port_val = port;
3653
3654 mutex_lock(&bp->hwrm_cmd_lock);
3655 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3656 if (rc) {
3657 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
3658 rc);
3659 goto err_out;
3660 }
3661
3662 switch (tunnel_type) {
3663 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN:
3664 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3665 break;
3666 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE:
3667 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
3668 break;
3669 default:
3670 break;
3671 }
3672
3673 err_out:
3674 mutex_unlock(&bp->hwrm_cmd_lock);
3675 return rc;
3676 }
3677
3678 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
3679 {
3680 struct hwrm_cfa_l2_set_rx_mask_input req = {0};
3681 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3682
3683 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
3684 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3685
3686 req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
3687 req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
3688 req.mask = cpu_to_le32(vnic->rx_mask);
3689 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3690 }
3691
3692 #ifdef CONFIG_RFS_ACCEL
3693 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
3694 struct bnxt_ntuple_filter *fltr)
3695 {
3696 struct hwrm_cfa_ntuple_filter_free_input req = {0};
3697
3698 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
3699 req.ntuple_filter_id = fltr->filter_id;
3700 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3701 }
3702
3703 #define BNXT_NTP_FLTR_FLAGS \
3704 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
3705 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
3706 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
3707 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
3708 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
3709 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
3710 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
3711 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
3712 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
3713 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
3714 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
3715 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
3716 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
3717 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
3718
3719 #define BNXT_NTP_TUNNEL_FLTR_FLAG \
3720 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE
3721
3722 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
3723 struct bnxt_ntuple_filter *fltr)
3724 {
3725 int rc = 0;
3726 struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
3727 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3728 bp->hwrm_cmd_resp_addr;
3729 struct flow_keys *keys = &fltr->fkeys;
3730 struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1];
3731
3732 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
3733 req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx];
3734
3735 req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
3736
3737 req.ethertype = htons(ETH_P_IP);
3738 memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
3739 req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
3740 req.ip_protocol = keys->basic.ip_proto;
3741
3742 if (keys->basic.n_proto == htons(ETH_P_IPV6)) {
3743 int i;
3744
3745 req.ethertype = htons(ETH_P_IPV6);
3746 req.ip_addr_type =
3747 CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6;
3748 *(struct in6_addr *)&req.src_ipaddr[0] =
3749 keys->addrs.v6addrs.src;
3750 *(struct in6_addr *)&req.dst_ipaddr[0] =
3751 keys->addrs.v6addrs.dst;
3752 for (i = 0; i < 4; i++) {
3753 req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
3754 req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
3755 }
3756 } else {
3757 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
3758 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3759 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
3760 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3761 }
3762 if (keys->control.flags & FLOW_DIS_ENCAPSULATION) {
3763 req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG);
3764 req.tunnel_type =
3765 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL;
3766 }
3767
3768 req.src_port = keys->ports.src;
3769 req.src_port_mask = cpu_to_be16(0xffff);
3770 req.dst_port = keys->ports.dst;
3771 req.dst_port_mask = cpu_to_be16(0xffff);
3772
3773 req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
3774 mutex_lock(&bp->hwrm_cmd_lock);
3775 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3776 if (!rc)
3777 fltr->filter_id = resp->ntuple_filter_id;
3778 mutex_unlock(&bp->hwrm_cmd_lock);
3779 return rc;
3780 }
3781 #endif
3782
3783 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
3784 u8 *mac_addr)
3785 {
3786 u32 rc = 0;
3787 struct hwrm_cfa_l2_filter_alloc_input req = {0};
3788 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3789
3790 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
3791 req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX);
3792 if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
3793 req.flags |=
3794 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
3795 req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
3796 req.enables =
3797 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
3798 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
3799 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
3800 memcpy(req.l2_addr, mac_addr, ETH_ALEN);
3801 req.l2_addr_mask[0] = 0xff;
3802 req.l2_addr_mask[1] = 0xff;
3803 req.l2_addr_mask[2] = 0xff;
3804 req.l2_addr_mask[3] = 0xff;
3805 req.l2_addr_mask[4] = 0xff;
3806 req.l2_addr_mask[5] = 0xff;
3807
3808 mutex_lock(&bp->hwrm_cmd_lock);
3809 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3810 if (!rc)
3811 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
3812 resp->l2_filter_id;
3813 mutex_unlock(&bp->hwrm_cmd_lock);
3814 return rc;
3815 }
3816
3817 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
3818 {
3819 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
3820 int rc = 0;
3821
3822 /* Any associated ntuple filters will also be cleared by firmware. */
3823 mutex_lock(&bp->hwrm_cmd_lock);
3824 for (i = 0; i < num_of_vnics; i++) {
3825 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3826
3827 for (j = 0; j < vnic->uc_filter_count; j++) {
3828 struct hwrm_cfa_l2_filter_free_input req = {0};
3829
3830 bnxt_hwrm_cmd_hdr_init(bp, &req,
3831 HWRM_CFA_L2_FILTER_FREE, -1, -1);
3832
3833 req.l2_filter_id = vnic->fw_l2_filter_id[j];
3834
3835 rc = _hwrm_send_message(bp, &req, sizeof(req),
3836 HWRM_CMD_TIMEOUT);
3837 }
3838 vnic->uc_filter_count = 0;
3839 }
3840 mutex_unlock(&bp->hwrm_cmd_lock);
3841
3842 return rc;
3843 }
3844
3845 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
3846 {
3847 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3848 struct hwrm_vnic_tpa_cfg_input req = {0};
3849
3850 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
3851 return 0;
3852
3853 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
3854
3855 if (tpa_flags) {
3856 u16 mss = bp->dev->mtu - 40;
3857 u32 nsegs, n, segs = 0, flags;
3858
3859 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
3860 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
3861 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
3862 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
3863 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
3864 if (tpa_flags & BNXT_FLAG_GRO)
3865 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
3866
3867 req.flags = cpu_to_le32(flags);
3868
3869 req.enables =
3870 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
3871 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
3872 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
3873
3874 /* Number of segs are log2 units, and first packet is not
3875 * included as part of this units.
3876 */
3877 if (mss <= BNXT_RX_PAGE_SIZE) {
3878 n = BNXT_RX_PAGE_SIZE / mss;
3879 nsegs = (MAX_SKB_FRAGS - 1) * n;
3880 } else {
3881 n = mss / BNXT_RX_PAGE_SIZE;
3882 if (mss & (BNXT_RX_PAGE_SIZE - 1))
3883 n++;
3884 nsegs = (MAX_SKB_FRAGS - n) / n;
3885 }
3886
3887 segs = ilog2(nsegs);
3888 req.max_agg_segs = cpu_to_le16(segs);
3889 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
3890
3891 req.min_agg_len = cpu_to_le32(512);
3892 }
3893 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3894
3895 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3896 }
3897
3898 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
3899 {
3900 u32 i, j, max_rings;
3901 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3902 struct hwrm_vnic_rss_cfg_input req = {0};
3903
3904 if (vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)
3905 return 0;
3906
3907 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
3908 if (set_rss) {
3909 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
3910 if (vnic->flags & BNXT_VNIC_RSS_FLAG) {
3911 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
3912 max_rings = bp->rx_nr_rings - 1;
3913 else
3914 max_rings = bp->rx_nr_rings;
3915 } else {
3916 max_rings = 1;
3917 }
3918
3919 /* Fill the RSS indirection table with ring group ids */
3920 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
3921 if (j == max_rings)
3922 j = 0;
3923 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
3924 }
3925
3926 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
3927 req.hash_key_tbl_addr =
3928 cpu_to_le64(vnic->rss_hash_key_dma_addr);
3929 }
3930 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
3931 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3932 }
3933
3934 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
3935 {
3936 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3937 struct hwrm_vnic_plcmodes_cfg_input req = {0};
3938
3939 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
3940 req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
3941 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
3942 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
3943 req.enables =
3944 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
3945 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
3946 /* thresholds not implemented in firmware yet */
3947 req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
3948 req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
3949 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3950 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3951 }
3952
3953 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id,
3954 u16 ctx_idx)
3955 {
3956 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
3957
3958 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
3959 req.rss_cos_lb_ctx_id =
3960 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]);
3961
3962 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3963 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID;
3964 }
3965
3966 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
3967 {
3968 int i, j;
3969
3970 for (i = 0; i < bp->nr_vnics; i++) {
3971 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3972
3973 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) {
3974 if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID)
3975 bnxt_hwrm_vnic_ctx_free_one(bp, i, j);
3976 }
3977 }
3978 bp->rsscos_nr_ctxs = 0;
3979 }
3980
3981 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx)
3982 {
3983 int rc;
3984 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
3985 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
3986 bp->hwrm_cmd_resp_addr;
3987
3988 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
3989 -1);
3990
3991 mutex_lock(&bp->hwrm_cmd_lock);
3992 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3993 if (!rc)
3994 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] =
3995 le16_to_cpu(resp->rss_cos_lb_ctx_id);
3996 mutex_unlock(&bp->hwrm_cmd_lock);
3997
3998 return rc;
3999 }
4000
4001 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
4002 {
4003 unsigned int ring = 0, grp_idx;
4004 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4005 struct hwrm_vnic_cfg_input req = {0};
4006 u16 def_vlan = 0;
4007
4008 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
4009
4010 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP);
4011 /* Only RSS support for now TBD: COS & LB */
4012 if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) {
4013 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
4014 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
4015 VNIC_CFG_REQ_ENABLES_MRU);
4016 } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) {
4017 req.rss_rule =
4018 cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]);
4019 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
4020 VNIC_CFG_REQ_ENABLES_MRU);
4021 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE);
4022 } else {
4023 req.rss_rule = cpu_to_le16(0xffff);
4024 }
4025
4026 if (BNXT_CHIP_TYPE_NITRO_A0(bp) &&
4027 (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) {
4028 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]);
4029 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE);
4030 } else {
4031 req.cos_rule = cpu_to_le16(0xffff);
4032 }
4033
4034 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
4035 ring = 0;
4036 else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
4037 ring = vnic_id - 1;
4038 else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp))
4039 ring = bp->rx_nr_rings - 1;
4040
4041 grp_idx = bp->rx_ring[ring].bnapi->index;
4042 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4043 req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
4044
4045 req.lb_rule = cpu_to_le16(0xffff);
4046 req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
4047 VLAN_HLEN);
4048
4049 #ifdef CONFIG_BNXT_SRIOV
4050 if (BNXT_VF(bp))
4051 def_vlan = bp->vf.vlan;
4052 #endif
4053 if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
4054 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
4055 if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP))
4056 req.flags |=
4057 cpu_to_le32(VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE);
4058
4059 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4060 }
4061
4062 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
4063 {
4064 u32 rc = 0;
4065
4066 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
4067 struct hwrm_vnic_free_input req = {0};
4068
4069 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
4070 req.vnic_id =
4071 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
4072
4073 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4074 if (rc)
4075 return rc;
4076 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
4077 }
4078 return rc;
4079 }
4080
4081 static void bnxt_hwrm_vnic_free(struct bnxt *bp)
4082 {
4083 u16 i;
4084
4085 for (i = 0; i < bp->nr_vnics; i++)
4086 bnxt_hwrm_vnic_free_one(bp, i);
4087 }
4088
4089 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
4090 unsigned int start_rx_ring_idx,
4091 unsigned int nr_rings)
4092 {
4093 int rc = 0;
4094 unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
4095 struct hwrm_vnic_alloc_input req = {0};
4096 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4097
4098 /* map ring groups to this vnic */
4099 for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
4100 grp_idx = bp->rx_ring[i].bnapi->index;
4101 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
4102 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
4103 j, nr_rings);
4104 break;
4105 }
4106 bp->vnic_info[vnic_id].fw_grp_ids[j] =
4107 bp->grp_info[grp_idx].fw_grp_id;
4108 }
4109
4110 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
4111 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
4112 if (vnic_id == 0)
4113 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
4114
4115 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
4116
4117 mutex_lock(&bp->hwrm_cmd_lock);
4118 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4119 if (!rc)
4120 bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id);
4121 mutex_unlock(&bp->hwrm_cmd_lock);
4122 return rc;
4123 }
4124
4125 static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
4126 {
4127 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4128 struct hwrm_vnic_qcaps_input req = {0};
4129 int rc;
4130
4131 if (bp->hwrm_spec_code < 0x10600)
4132 return 0;
4133
4134 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1);
4135 mutex_lock(&bp->hwrm_cmd_lock);
4136 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4137 if (!rc) {
4138 if (resp->flags &
4139 cpu_to_le32(VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP))
4140 bp->flags |= BNXT_FLAG_NEW_RSS_CAP;
4141 }
4142 mutex_unlock(&bp->hwrm_cmd_lock);
4143 return rc;
4144 }
4145
4146 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
4147 {
4148 u16 i;
4149 u32 rc = 0;
4150
4151 mutex_lock(&bp->hwrm_cmd_lock);
4152 for (i = 0; i < bp->rx_nr_rings; i++) {
4153 struct hwrm_ring_grp_alloc_input req = {0};
4154 struct hwrm_ring_grp_alloc_output *resp =
4155 bp->hwrm_cmd_resp_addr;
4156 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
4157
4158 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
4159
4160 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
4161 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
4162 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
4163 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
4164
4165 rc = _hwrm_send_message(bp, &req, sizeof(req),
4166 HWRM_CMD_TIMEOUT);
4167 if (rc)
4168 break;
4169
4170 bp->grp_info[grp_idx].fw_grp_id =
4171 le32_to_cpu(resp->ring_group_id);
4172 }
4173 mutex_unlock(&bp->hwrm_cmd_lock);
4174 return rc;
4175 }
4176
4177 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
4178 {
4179 u16 i;
4180 u32 rc = 0;
4181 struct hwrm_ring_grp_free_input req = {0};
4182
4183 if (!bp->grp_info)
4184 return 0;
4185
4186 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
4187
4188 mutex_lock(&bp->hwrm_cmd_lock);
4189 for (i = 0; i < bp->cp_nr_rings; i++) {
4190 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
4191 continue;
4192 req.ring_group_id =
4193 cpu_to_le32(bp->grp_info[i].fw_grp_id);
4194
4195 rc = _hwrm_send_message(bp, &req, sizeof(req),
4196 HWRM_CMD_TIMEOUT);
4197 if (rc)
4198 break;
4199 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
4200 }
4201 mutex_unlock(&bp->hwrm_cmd_lock);
4202 return rc;
4203 }
4204
4205 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
4206 struct bnxt_ring_struct *ring,
4207 u32 ring_type, u32 map_index,
4208 u32 stats_ctx_id)
4209 {
4210 int rc = 0, err = 0;
4211 struct hwrm_ring_alloc_input req = {0};
4212 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4213 u16 ring_id;
4214
4215 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
4216
4217 req.enables = 0;
4218 if (ring->nr_pages > 1) {
4219 req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map);
4220 /* Page size is in log2 units */
4221 req.page_size = BNXT_PAGE_SHIFT;
4222 req.page_tbl_depth = 1;
4223 } else {
4224 req.page_tbl_addr = cpu_to_le64(ring->dma_arr[0]);
4225 }
4226 req.fbo = 0;
4227 /* Association of ring index with doorbell index and MSIX number */
4228 req.logical_id = cpu_to_le16(map_index);
4229
4230 switch (ring_type) {
4231 case HWRM_RING_ALLOC_TX:
4232 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
4233 /* Association of transmit ring with completion ring */
4234 req.cmpl_ring_id =
4235 cpu_to_le16(bp->grp_info[map_index].cp_fw_ring_id);
4236 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
4237 req.stat_ctx_id = cpu_to_le32(stats_ctx_id);
4238 req.queue_id = cpu_to_le16(ring->queue_id);
4239 break;
4240 case HWRM_RING_ALLOC_RX:
4241 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4242 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
4243 break;
4244 case HWRM_RING_ALLOC_AGG:
4245 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4246 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
4247 break;
4248 case HWRM_RING_ALLOC_CMPL:
4249 req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL;
4250 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
4251 if (bp->flags & BNXT_FLAG_USING_MSIX)
4252 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
4253 break;
4254 default:
4255 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
4256 ring_type);
4257 return -1;
4258 }
4259
4260 mutex_lock(&bp->hwrm_cmd_lock);
4261 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4262 err = le16_to_cpu(resp->error_code);
4263 ring_id = le16_to_cpu(resp->ring_id);
4264 mutex_unlock(&bp->hwrm_cmd_lock);
4265
4266 if (rc || err) {
4267 switch (ring_type) {
4268 case RING_FREE_REQ_RING_TYPE_L2_CMPL:
4269 netdev_err(bp->dev, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
4270 rc, err);
4271 return -1;
4272
4273 case RING_FREE_REQ_RING_TYPE_RX:
4274 netdev_err(bp->dev, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
4275 rc, err);
4276 return -1;
4277
4278 case RING_FREE_REQ_RING_TYPE_TX:
4279 netdev_err(bp->dev, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
4280 rc, err);
4281 return -1;
4282
4283 default:
4284 netdev_err(bp->dev, "Invalid ring\n");
4285 return -1;
4286 }
4287 }
4288 ring->fw_ring_id = ring_id;
4289 return rc;
4290 }
4291
4292 static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx)
4293 {
4294 int rc;
4295
4296 if (BNXT_PF(bp)) {
4297 struct hwrm_func_cfg_input req = {0};
4298
4299 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
4300 req.fid = cpu_to_le16(0xffff);
4301 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4302 req.async_event_cr = cpu_to_le16(idx);
4303 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4304 } else {
4305 struct hwrm_func_vf_cfg_input req = {0};
4306
4307 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1);
4308 req.enables =
4309 cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4310 req.async_event_cr = cpu_to_le16(idx);
4311 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4312 }
4313 return rc;
4314 }
4315
4316 static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
4317 {
4318 int i, rc = 0;
4319
4320 for (i = 0; i < bp->cp_nr_rings; i++) {
4321 struct bnxt_napi *bnapi = bp->bnapi[i];
4322 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4323 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4324
4325 cpr->cp_doorbell = bp->bar1 + i * 0x80;
4326 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL, i,
4327 INVALID_STATS_CTX_ID);
4328 if (rc)
4329 goto err_out;
4330 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
4331 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
4332
4333 if (!i) {
4334 rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id);
4335 if (rc)
4336 netdev_warn(bp->dev, "Failed to set async event completion ring.\n");
4337 }
4338 }
4339
4340 for (i = 0; i < bp->tx_nr_rings; i++) {
4341 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
4342 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
4343 u32 map_idx = txr->bnapi->index;
4344 u16 fw_stats_ctx = bp->grp_info[map_idx].fw_stats_ctx;
4345
4346 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_TX,
4347 map_idx, fw_stats_ctx);
4348 if (rc)
4349 goto err_out;
4350 txr->tx_doorbell = bp->bar1 + map_idx * 0x80;
4351 }
4352
4353 for (i = 0; i < bp->rx_nr_rings; i++) {
4354 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4355 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
4356 u32 map_idx = rxr->bnapi->index;
4357
4358 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_RX,
4359 map_idx, INVALID_STATS_CTX_ID);
4360 if (rc)
4361 goto err_out;
4362 rxr->rx_doorbell = bp->bar1 + map_idx * 0x80;
4363 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
4364 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
4365 }
4366
4367 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
4368 for (i = 0; i < bp->rx_nr_rings; i++) {
4369 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4370 struct bnxt_ring_struct *ring =
4371 &rxr->rx_agg_ring_struct;
4372 u32 grp_idx = rxr->bnapi->index;
4373 u32 map_idx = grp_idx + bp->rx_nr_rings;
4374
4375 rc = hwrm_ring_alloc_send_msg(bp, ring,
4376 HWRM_RING_ALLOC_AGG,
4377 map_idx,
4378 INVALID_STATS_CTX_ID);
4379 if (rc)
4380 goto err_out;
4381
4382 rxr->rx_agg_doorbell = bp->bar1 + map_idx * 0x80;
4383 writel(DB_KEY_RX | rxr->rx_agg_prod,
4384 rxr->rx_agg_doorbell);
4385 bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
4386 }
4387 }
4388 err_out:
4389 return rc;
4390 }
4391
4392 static int hwrm_ring_free_send_msg(struct bnxt *bp,
4393 struct bnxt_ring_struct *ring,
4394 u32 ring_type, int cmpl_ring_id)
4395 {
4396 int rc;
4397 struct hwrm_ring_free_input req = {0};
4398 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
4399 u16 error_code;
4400
4401 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
4402 req.ring_type = ring_type;
4403 req.ring_id = cpu_to_le16(ring->fw_ring_id);
4404
4405 mutex_lock(&bp->hwrm_cmd_lock);
4406 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4407 error_code = le16_to_cpu(resp->error_code);
4408 mutex_unlock(&bp->hwrm_cmd_lock);
4409
4410 if (rc || error_code) {
4411 switch (ring_type) {
4412 case RING_FREE_REQ_RING_TYPE_L2_CMPL:
4413 netdev_err(bp->dev, "hwrm_ring_free cp failed. rc:%d\n",
4414 rc);
4415 return rc;
4416 case RING_FREE_REQ_RING_TYPE_RX:
4417 netdev_err(bp->dev, "hwrm_ring_free rx failed. rc:%d\n",
4418 rc);
4419 return rc;
4420 case RING_FREE_REQ_RING_TYPE_TX:
4421 netdev_err(bp->dev, "hwrm_ring_free tx failed. rc:%d\n",
4422 rc);
4423 return rc;
4424 default:
4425 netdev_err(bp->dev, "Invalid ring\n");
4426 return -1;
4427 }
4428 }
4429 return 0;
4430 }
4431
4432 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
4433 {
4434 int i;
4435
4436 if (!bp->bnapi)
4437 return;
4438
4439 for (i = 0; i < bp->tx_nr_rings; i++) {
4440 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
4441 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
4442 u32 grp_idx = txr->bnapi->index;
4443 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4444
4445 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4446 hwrm_ring_free_send_msg(bp, ring,
4447 RING_FREE_REQ_RING_TYPE_TX,
4448 close_path ? cmpl_ring_id :
4449 INVALID_HW_RING_ID);
4450 ring->fw_ring_id = INVALID_HW_RING_ID;
4451 }
4452 }
4453
4454 for (i = 0; i < bp->rx_nr_rings; i++) {
4455 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4456 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
4457 u32 grp_idx = rxr->bnapi->index;
4458 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4459
4460 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4461 hwrm_ring_free_send_msg(bp, ring,
4462 RING_FREE_REQ_RING_TYPE_RX,
4463 close_path ? cmpl_ring_id :
4464 INVALID_HW_RING_ID);
4465 ring->fw_ring_id = INVALID_HW_RING_ID;
4466 bp->grp_info[grp_idx].rx_fw_ring_id =
4467 INVALID_HW_RING_ID;
4468 }
4469 }
4470
4471 for (i = 0; i < bp->rx_nr_rings; i++) {
4472 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4473 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
4474 u32 grp_idx = rxr->bnapi->index;
4475 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4476
4477 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4478 hwrm_ring_free_send_msg(bp, ring,
4479 RING_FREE_REQ_RING_TYPE_RX,
4480 close_path ? cmpl_ring_id :
4481 INVALID_HW_RING_ID);
4482 ring->fw_ring_id = INVALID_HW_RING_ID;
4483 bp->grp_info[grp_idx].agg_fw_ring_id =
4484 INVALID_HW_RING_ID;
4485 }
4486 }
4487
4488 /* The completion rings are about to be freed. After that the
4489 * IRQ doorbell will not work anymore. So we need to disable
4490 * IRQ here.
4491 */
4492 bnxt_disable_int_sync(bp);
4493
4494 for (i = 0; i < bp->cp_nr_rings; i++) {
4495 struct bnxt_napi *bnapi = bp->bnapi[i];
4496 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4497 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4498
4499 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4500 hwrm_ring_free_send_msg(bp, ring,
4501 RING_FREE_REQ_RING_TYPE_L2_CMPL,
4502 INVALID_HW_RING_ID);
4503 ring->fw_ring_id = INVALID_HW_RING_ID;
4504 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
4505 }
4506 }
4507 }
4508
4509 static int bnxt_hwrm_get_rings(struct bnxt *bp)
4510 {
4511 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4512 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
4513 struct hwrm_func_qcfg_input req = {0};
4514 int rc;
4515
4516 if (bp->hwrm_spec_code < 0x10601)
4517 return 0;
4518
4519 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
4520 req.fid = cpu_to_le16(0xffff);
4521 mutex_lock(&bp->hwrm_cmd_lock);
4522 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4523 if (rc) {
4524 mutex_unlock(&bp->hwrm_cmd_lock);
4525 return -EIO;
4526 }
4527
4528 hw_resc->resv_tx_rings = le16_to_cpu(resp->alloc_tx_rings);
4529 if (bp->flags & BNXT_FLAG_NEW_RM) {
4530 u16 cp, stats;
4531
4532 hw_resc->resv_rx_rings = le16_to_cpu(resp->alloc_rx_rings);
4533 hw_resc->resv_hw_ring_grps =
4534 le32_to_cpu(resp->alloc_hw_ring_grps);
4535 hw_resc->resv_vnics = le16_to_cpu(resp->alloc_vnics);
4536 cp = le16_to_cpu(resp->alloc_cmpl_rings);
4537 stats = le16_to_cpu(resp->alloc_stat_ctx);
4538 cp = min_t(u16, cp, stats);
4539 hw_resc->resv_cp_rings = cp;
4540 }
4541 mutex_unlock(&bp->hwrm_cmd_lock);
4542 return 0;
4543 }
4544
4545 /* Caller must hold bp->hwrm_cmd_lock */
4546 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings)
4547 {
4548 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4549 struct hwrm_func_qcfg_input req = {0};
4550 int rc;
4551
4552 if (bp->hwrm_spec_code < 0x10601)
4553 return 0;
4554
4555 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
4556 req.fid = cpu_to_le16(fid);
4557 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4558 if (!rc)
4559 *tx_rings = le16_to_cpu(resp->alloc_tx_rings);
4560
4561 return rc;
4562 }
4563
4564 static void
4565 __bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, struct hwrm_func_cfg_input *req,
4566 int tx_rings, int rx_rings, int ring_grps,
4567 int cp_rings, int vnics)
4568 {
4569 u32 enables = 0;
4570
4571 bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_CFG, -1, -1);
4572 req->fid = cpu_to_le16(0xffff);
4573 enables |= tx_rings ? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
4574 req->num_tx_rings = cpu_to_le16(tx_rings);
4575 if (bp->flags & BNXT_FLAG_NEW_RM) {
4576 enables |= rx_rings ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0;
4577 enables |= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
4578 FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
4579 enables |= ring_grps ?
4580 FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0;
4581 enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0;
4582
4583 req->num_rx_rings = cpu_to_le16(rx_rings);
4584 req->num_hw_ring_grps = cpu_to_le16(ring_grps);
4585 req->num_cmpl_rings = cpu_to_le16(cp_rings);
4586 req->num_stat_ctxs = req->num_cmpl_rings;
4587 req->num_vnics = cpu_to_le16(vnics);
4588 }
4589 req->enables = cpu_to_le32(enables);
4590 }
4591
4592 static void
4593 __bnxt_hwrm_reserve_vf_rings(struct bnxt *bp,
4594 struct hwrm_func_vf_cfg_input *req, int tx_rings,
4595 int rx_rings, int ring_grps, int cp_rings,
4596 int vnics)
4597 {
4598 u32 enables = 0;
4599
4600 bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_VF_CFG, -1, -1);
4601 enables |= tx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
4602 enables |= rx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS : 0;
4603 enables |= cp_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
4604 FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
4605 enables |= ring_grps ? FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0;
4606 enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0;
4607
4608 req->num_tx_rings = cpu_to_le16(tx_rings);
4609 req->num_rx_rings = cpu_to_le16(rx_rings);
4610 req->num_hw_ring_grps = cpu_to_le16(ring_grps);
4611 req->num_cmpl_rings = cpu_to_le16(cp_rings);
4612 req->num_stat_ctxs = req->num_cmpl_rings;
4613 req->num_vnics = cpu_to_le16(vnics);
4614
4615 req->enables = cpu_to_le32(enables);
4616 }
4617
4618 static int
4619 bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4620 int ring_grps, int cp_rings, int vnics)
4621 {
4622 struct hwrm_func_cfg_input req = {0};
4623 int rc;
4624
4625 __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
4626 cp_rings, vnics);
4627 if (!req.enables)
4628 return 0;
4629
4630 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4631 if (rc)
4632 return -ENOMEM;
4633
4634 if (bp->hwrm_spec_code < 0x10601)
4635 bp->hw_resc.resv_tx_rings = tx_rings;
4636
4637 rc = bnxt_hwrm_get_rings(bp);
4638 return rc;
4639 }
4640
4641 static int
4642 bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4643 int ring_grps, int cp_rings, int vnics)
4644 {
4645 struct hwrm_func_vf_cfg_input req = {0};
4646 int rc;
4647
4648 if (!(bp->flags & BNXT_FLAG_NEW_RM)) {
4649 bp->hw_resc.resv_tx_rings = tx_rings;
4650 return 0;
4651 }
4652
4653 __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
4654 cp_rings, vnics);
4655 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4656 if (rc)
4657 return -ENOMEM;
4658
4659 rc = bnxt_hwrm_get_rings(bp);
4660 return rc;
4661 }
4662
4663 static int bnxt_hwrm_reserve_rings(struct bnxt *bp, int tx, int rx, int grp,
4664 int cp, int vnic)
4665 {
4666 if (BNXT_PF(bp))
4667 return bnxt_hwrm_reserve_pf_rings(bp, tx, rx, grp, cp, vnic);
4668 else
4669 return bnxt_hwrm_reserve_vf_rings(bp, tx, rx, grp, cp, vnic);
4670 }
4671
4672 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
4673 bool shared);
4674
4675 static int __bnxt_reserve_rings(struct bnxt *bp)
4676 {
4677 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
4678 int tx = bp->tx_nr_rings;
4679 int rx = bp->rx_nr_rings;
4680 int cp = bp->cp_nr_rings;
4681 int grp, rx_rings, rc;
4682 bool sh = false;
4683 int vnic = 1;
4684
4685 if (bp->hwrm_spec_code < 0x10601)
4686 return 0;
4687
4688 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
4689 sh = true;
4690 if (bp->flags & BNXT_FLAG_RFS)
4691 vnic = rx + 1;
4692 if (bp->flags & BNXT_FLAG_AGG_RINGS)
4693 rx <<= 1;
4694
4695 grp = bp->rx_nr_rings;
4696 if (tx == hw_resc->resv_tx_rings &&
4697 (!(bp->flags & BNXT_FLAG_NEW_RM) ||
4698 (rx == hw_resc->resv_rx_rings &&
4699 grp == hw_resc->resv_hw_ring_grps &&
4700 cp == hw_resc->resv_cp_rings && vnic == hw_resc->resv_vnics)))
4701 return 0;
4702
4703 rc = bnxt_hwrm_reserve_rings(bp, tx, rx, grp, cp, vnic);
4704 if (rc)
4705 return rc;
4706
4707 tx = hw_resc->resv_tx_rings;
4708 if (bp->flags & BNXT_FLAG_NEW_RM) {
4709 rx = hw_resc->resv_rx_rings;
4710 cp = hw_resc->resv_cp_rings;
4711 grp = hw_resc->resv_hw_ring_grps;
4712 vnic = hw_resc->resv_vnics;
4713 }
4714
4715 rx_rings = rx;
4716 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
4717 if (rx >= 2) {
4718 rx_rings = rx >> 1;
4719 } else {
4720 if (netif_running(bp->dev))
4721 return -ENOMEM;
4722
4723 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
4724 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
4725 bp->dev->hw_features &= ~NETIF_F_LRO;
4726 bp->dev->features &= ~NETIF_F_LRO;
4727 bnxt_set_ring_params(bp);
4728 }
4729 }
4730 rx_rings = min_t(int, rx_rings, grp);
4731 rc = bnxt_trim_rings(bp, &rx_rings, &tx, cp, sh);
4732 if (bp->flags & BNXT_FLAG_AGG_RINGS)
4733 rx = rx_rings << 1;
4734 cp = sh ? max_t(int, tx, rx_rings) : tx + rx_rings;
4735 bp->tx_nr_rings = tx;
4736 bp->rx_nr_rings = rx_rings;
4737 bp->cp_nr_rings = cp;
4738
4739 if (!tx || !rx || !cp || !grp || !vnic)
4740 return -ENOMEM;
4741
4742 return rc;
4743 }
4744
4745 static bool bnxt_need_reserve_rings(struct bnxt *bp)
4746 {
4747 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
4748 int rx = bp->rx_nr_rings;
4749 int vnic = 1;
4750
4751 if (bp->hwrm_spec_code < 0x10601)
4752 return false;
4753
4754 if (hw_resc->resv_tx_rings != bp->tx_nr_rings)
4755 return true;
4756
4757 if (bp->flags & BNXT_FLAG_RFS)
4758 vnic = rx + 1;
4759 if (bp->flags & BNXT_FLAG_AGG_RINGS)
4760 rx <<= 1;
4761 if ((bp->flags & BNXT_FLAG_NEW_RM) &&
4762 (hw_resc->resv_rx_rings != rx ||
4763 hw_resc->resv_cp_rings != bp->cp_nr_rings ||
4764 hw_resc->resv_vnics != vnic))
4765 return true;
4766 return false;
4767 }
4768
4769 static int bnxt_hwrm_check_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4770 int ring_grps, int cp_rings, int vnics)
4771 {
4772 struct hwrm_func_vf_cfg_input req = {0};
4773 u32 flags;
4774 int rc;
4775
4776 if (!(bp->flags & BNXT_FLAG_NEW_RM))
4777 return 0;
4778
4779 __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
4780 cp_rings, vnics);
4781 flags = FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST |
4782 FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST |
4783 FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
4784 FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST |
4785 FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
4786 FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST;
4787
4788 req.flags = cpu_to_le32(flags);
4789 rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4790 if (rc)
4791 return -ENOMEM;
4792 return 0;
4793 }
4794
4795 static int bnxt_hwrm_check_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4796 int ring_grps, int cp_rings, int vnics)
4797 {
4798 struct hwrm_func_cfg_input req = {0};
4799 u32 flags;
4800 int rc;
4801
4802 __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
4803 cp_rings, vnics);
4804 flags = FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST;
4805 if (bp->flags & BNXT_FLAG_NEW_RM)
4806 flags |= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST |
4807 FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
4808 FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST |
4809 FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
4810 FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST;
4811
4812 req.flags = cpu_to_le32(flags);
4813 rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4814 if (rc)
4815 return -ENOMEM;
4816 return 0;
4817 }
4818
4819 static int bnxt_hwrm_check_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4820 int ring_grps, int cp_rings, int vnics)
4821 {
4822 if (bp->hwrm_spec_code < 0x10801)
4823 return 0;
4824
4825 if (BNXT_PF(bp))
4826 return bnxt_hwrm_check_pf_rings(bp, tx_rings, rx_rings,
4827 ring_grps, cp_rings, vnics);
4828
4829 return bnxt_hwrm_check_vf_rings(bp, tx_rings, rx_rings, ring_grps,
4830 cp_rings, vnics);
4831 }
4832
4833 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4834 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4835 {
4836 u16 val, tmr, max, flags;
4837
4838 max = hw_coal->bufs_per_record * 128;
4839 if (hw_coal->budget)
4840 max = hw_coal->bufs_per_record * hw_coal->budget;
4841
4842 val = clamp_t(u16, hw_coal->coal_bufs, 1, max);
4843 req->num_cmpl_aggr_int = cpu_to_le16(val);
4844
4845 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4846 val = min_t(u16, val, 63);
4847 req->num_cmpl_dma_aggr = cpu_to_le16(val);
4848
4849 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4850 val = clamp_t(u16, hw_coal->coal_bufs_irq, 1, 63);
4851 req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val);
4852
4853 tmr = BNXT_USEC_TO_COAL_TIMER(hw_coal->coal_ticks);
4854 tmr = max_t(u16, tmr, 1);
4855 req->int_lat_tmr_max = cpu_to_le16(tmr);
4856
4857 /* min timer set to 1/2 of interrupt timer */
4858 val = tmr / 2;
4859 req->int_lat_tmr_min = cpu_to_le16(val);
4860
4861 /* buf timer set to 1/4 of interrupt timer */
4862 val = max_t(u16, tmr / 4, 1);
4863 req->cmpl_aggr_dma_tmr = cpu_to_le16(val);
4864
4865 tmr = BNXT_USEC_TO_COAL_TIMER(hw_coal->coal_ticks_irq);
4866 tmr = max_t(u16, tmr, 1);
4867 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(tmr);
4868
4869 flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
4870 if (hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh)
4871 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
4872 req->flags = cpu_to_le16(flags);
4873 }
4874
4875 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi)
4876 {
4877 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0};
4878 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4879 struct bnxt_coal coal;
4880 unsigned int grp_idx;
4881
4882 /* Tick values in micro seconds.
4883 * 1 coal_buf x bufs_per_record = 1 completion record.
4884 */
4885 memcpy(&coal, &bp->rx_coal, sizeof(struct bnxt_coal));
4886
4887 coal.coal_ticks = cpr->rx_ring_coal.coal_ticks;
4888 coal.coal_bufs = cpr->rx_ring_coal.coal_bufs;
4889
4890 if (!bnapi->rx_ring)
4891 return -ENODEV;
4892
4893 bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
4894 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
4895
4896 bnxt_hwrm_set_coal_params(&coal, &req_rx);
4897
4898 grp_idx = bnapi->index;
4899 req_rx.ring_id = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
4900
4901 return hwrm_send_message(bp, &req_rx, sizeof(req_rx),
4902 HWRM_CMD_TIMEOUT);
4903 }
4904
4905 int bnxt_hwrm_set_coal(struct bnxt *bp)
4906 {
4907 int i, rc = 0;
4908 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
4909 req_tx = {0}, *req;
4910
4911 bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
4912 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
4913 bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
4914 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
4915
4916 bnxt_hwrm_set_coal_params(&bp->rx_coal, &req_rx);
4917 bnxt_hwrm_set_coal_params(&bp->tx_coal, &req_tx);
4918
4919 mutex_lock(&bp->hwrm_cmd_lock);
4920 for (i = 0; i < bp->cp_nr_rings; i++) {
4921 struct bnxt_napi *bnapi = bp->bnapi[i];
4922
4923 req = &req_rx;
4924 if (!bnapi->rx_ring)
4925 req = &req_tx;
4926 req->ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id);
4927
4928 rc = _hwrm_send_message(bp, req, sizeof(*req),
4929 HWRM_CMD_TIMEOUT);
4930 if (rc)
4931 break;
4932 }
4933 mutex_unlock(&bp->hwrm_cmd_lock);
4934 return rc;
4935 }
4936
4937 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
4938 {
4939 int rc = 0, i;
4940 struct hwrm_stat_ctx_free_input req = {0};
4941
4942 if (!bp->bnapi)
4943 return 0;
4944
4945 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4946 return 0;
4947
4948 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
4949
4950 mutex_lock(&bp->hwrm_cmd_lock);
4951 for (i = 0; i < bp->cp_nr_rings; i++) {
4952 struct bnxt_napi *bnapi = bp->bnapi[i];
4953 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4954
4955 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
4956 req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
4957
4958 rc = _hwrm_send_message(bp, &req, sizeof(req),
4959 HWRM_CMD_TIMEOUT);
4960 if (rc)
4961 break;
4962
4963 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
4964 }
4965 }
4966 mutex_unlock(&bp->hwrm_cmd_lock);
4967 return rc;
4968 }
4969
4970 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
4971 {
4972 int rc = 0, i;
4973 struct hwrm_stat_ctx_alloc_input req = {0};
4974 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4975
4976 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4977 return 0;
4978
4979 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
4980
4981 req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000);
4982
4983 mutex_lock(&bp->hwrm_cmd_lock);
4984 for (i = 0; i < bp->cp_nr_rings; i++) {
4985 struct bnxt_napi *bnapi = bp->bnapi[i];
4986 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4987
4988 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
4989
4990 rc = _hwrm_send_message(bp, &req, sizeof(req),
4991 HWRM_CMD_TIMEOUT);
4992 if (rc)
4993 break;
4994
4995 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
4996
4997 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
4998 }
4999 mutex_unlock(&bp->hwrm_cmd_lock);
5000 return rc;
5001 }
5002
5003 static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
5004 {
5005 struct hwrm_func_qcfg_input req = {0};
5006 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5007 u16 flags;
5008 int rc;
5009
5010 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
5011 req.fid = cpu_to_le16(0xffff);
5012 mutex_lock(&bp->hwrm_cmd_lock);
5013 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5014 if (rc)
5015 goto func_qcfg_exit;
5016
5017 #ifdef CONFIG_BNXT_SRIOV
5018 if (BNXT_VF(bp)) {
5019 struct bnxt_vf_info *vf = &bp->vf;
5020
5021 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
5022 }
5023 #endif
5024 flags = le16_to_cpu(resp->flags);
5025 if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED |
5026 FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) {
5027 bp->flags |= BNXT_FLAG_FW_LLDP_AGENT;
5028 if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED)
5029 bp->flags |= BNXT_FLAG_FW_DCBX_AGENT;
5030 }
5031 if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST))
5032 bp->flags |= BNXT_FLAG_MULTI_HOST;
5033
5034 switch (resp->port_partition_type) {
5035 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
5036 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
5037 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0:
5038 bp->port_partition_type = resp->port_partition_type;
5039 break;
5040 }
5041 if (bp->hwrm_spec_code < 0x10707 ||
5042 resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB)
5043 bp->br_mode = BRIDGE_MODE_VEB;
5044 else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA)
5045 bp->br_mode = BRIDGE_MODE_VEPA;
5046 else
5047 bp->br_mode = BRIDGE_MODE_UNDEF;
5048
5049 bp->max_mtu = le16_to_cpu(resp->max_mtu_configured);
5050 if (!bp->max_mtu)
5051 bp->max_mtu = BNXT_MAX_MTU;
5052
5053 func_qcfg_exit:
5054 mutex_unlock(&bp->hwrm_cmd_lock);
5055 return rc;
5056 }
5057
5058 static int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
5059 {
5060 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5061 struct hwrm_func_resource_qcaps_input req = {0};
5062 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5063 int rc;
5064
5065 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESOURCE_QCAPS, -1, -1);
5066 req.fid = cpu_to_le16(0xffff);
5067
5068 mutex_lock(&bp->hwrm_cmd_lock);
5069 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5070 if (rc) {
5071 rc = -EIO;
5072 goto hwrm_func_resc_qcaps_exit;
5073 }
5074
5075 hw_resc->min_rsscos_ctxs = le16_to_cpu(resp->min_rsscos_ctx);
5076 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
5077 hw_resc->min_cp_rings = le16_to_cpu(resp->min_cmpl_rings);
5078 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
5079 hw_resc->min_tx_rings = le16_to_cpu(resp->min_tx_rings);
5080 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
5081 hw_resc->min_rx_rings = le16_to_cpu(resp->min_rx_rings);
5082 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
5083 hw_resc->min_hw_ring_grps = le16_to_cpu(resp->min_hw_ring_grps);
5084 hw_resc->max_hw_ring_grps = le16_to_cpu(resp->max_hw_ring_grps);
5085 hw_resc->min_l2_ctxs = le16_to_cpu(resp->min_l2_ctxs);
5086 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
5087 hw_resc->min_vnics = le16_to_cpu(resp->min_vnics);
5088 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
5089 hw_resc->min_stat_ctxs = le16_to_cpu(resp->min_stat_ctx);
5090 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
5091
5092 if (BNXT_PF(bp)) {
5093 struct bnxt_pf_info *pf = &bp->pf;
5094
5095 pf->vf_resv_strategy =
5096 le16_to_cpu(resp->vf_reservation_strategy);
5097 if (pf->vf_resv_strategy > BNXT_VF_RESV_STRATEGY_MINIMAL)
5098 pf->vf_resv_strategy = BNXT_VF_RESV_STRATEGY_MAXIMAL;
5099 }
5100 hwrm_func_resc_qcaps_exit:
5101 mutex_unlock(&bp->hwrm_cmd_lock);
5102 return rc;
5103 }
5104
5105 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
5106 {
5107 int rc = 0;
5108 struct hwrm_func_qcaps_input req = {0};
5109 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5110 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5111 u32 flags;
5112
5113 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
5114 req.fid = cpu_to_le16(0xffff);
5115
5116 mutex_lock(&bp->hwrm_cmd_lock);
5117 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5118 if (rc)
5119 goto hwrm_func_qcaps_exit;
5120
5121 flags = le32_to_cpu(resp->flags);
5122 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED)
5123 bp->flags |= BNXT_FLAG_ROCEV1_CAP;
5124 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED)
5125 bp->flags |= BNXT_FLAG_ROCEV2_CAP;
5126
5127 bp->tx_push_thresh = 0;
5128 if (flags & FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED)
5129 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
5130
5131 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
5132 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
5133 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
5134 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
5135 hw_resc->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
5136 if (!hw_resc->max_hw_ring_grps)
5137 hw_resc->max_hw_ring_grps = hw_resc->max_tx_rings;
5138 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
5139 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
5140 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
5141
5142 if (BNXT_PF(bp)) {
5143 struct bnxt_pf_info *pf = &bp->pf;
5144
5145 pf->fw_fid = le16_to_cpu(resp->fid);
5146 pf->port_id = le16_to_cpu(resp->port_id);
5147 bp->dev->dev_port = pf->port_id;
5148 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
5149 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
5150 pf->max_vfs = le16_to_cpu(resp->max_vfs);
5151 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
5152 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
5153 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
5154 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
5155 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
5156 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
5157 if (flags & FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED)
5158 bp->flags |= BNXT_FLAG_WOL_CAP;
5159 } else {
5160 #ifdef CONFIG_BNXT_SRIOV
5161 struct bnxt_vf_info *vf = &bp->vf;
5162
5163 vf->fw_fid = le16_to_cpu(resp->fid);
5164 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
5165 #endif
5166 }
5167
5168 hwrm_func_qcaps_exit:
5169 mutex_unlock(&bp->hwrm_cmd_lock);
5170 return rc;
5171 }
5172
5173 static int bnxt_hwrm_func_qcaps(struct bnxt *bp)
5174 {
5175 int rc;
5176
5177 rc = __bnxt_hwrm_func_qcaps(bp);
5178 if (rc)
5179 return rc;
5180 if (bp->hwrm_spec_code >= 0x10803) {
5181 rc = bnxt_hwrm_func_resc_qcaps(bp);
5182 if (!rc)
5183 bp->flags |= BNXT_FLAG_NEW_RM;
5184 }
5185 return 0;
5186 }
5187
5188 static int bnxt_hwrm_func_reset(struct bnxt *bp)
5189 {
5190 struct hwrm_func_reset_input req = {0};
5191
5192 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
5193 req.enables = 0;
5194
5195 return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
5196 }
5197
5198 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
5199 {
5200 int rc = 0;
5201 struct hwrm_queue_qportcfg_input req = {0};
5202 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
5203 u8 i, *qptr;
5204
5205 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
5206
5207 mutex_lock(&bp->hwrm_cmd_lock);
5208 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5209 if (rc)
5210 goto qportcfg_exit;
5211
5212 if (!resp->max_configurable_queues) {
5213 rc = -EINVAL;
5214 goto qportcfg_exit;
5215 }
5216 bp->max_tc = resp->max_configurable_queues;
5217 bp->max_lltc = resp->max_configurable_lossless_queues;
5218 if (bp->max_tc > BNXT_MAX_QUEUE)
5219 bp->max_tc = BNXT_MAX_QUEUE;
5220
5221 if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG)
5222 bp->max_tc = 1;
5223
5224 if (bp->max_lltc > bp->max_tc)
5225 bp->max_lltc = bp->max_tc;
5226
5227 qptr = &resp->queue_id0;
5228 for (i = 0; i < bp->max_tc; i++) {
5229 bp->q_info[i].queue_id = *qptr++;
5230 bp->q_info[i].queue_profile = *qptr++;
5231 }
5232
5233 qportcfg_exit:
5234 mutex_unlock(&bp->hwrm_cmd_lock);
5235 return rc;
5236 }
5237
5238 static int bnxt_hwrm_ver_get(struct bnxt *bp)
5239 {
5240 int rc;
5241 struct hwrm_ver_get_input req = {0};
5242 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
5243 u32 dev_caps_cfg;
5244
5245 bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
5246 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
5247 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
5248 req.hwrm_intf_min = HWRM_VERSION_MINOR;
5249 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
5250 mutex_lock(&bp->hwrm_cmd_lock);
5251 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5252 if (rc)
5253 goto hwrm_ver_get_exit;
5254
5255 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
5256
5257 bp->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 |
5258 resp->hwrm_intf_min_8b << 8 |
5259 resp->hwrm_intf_upd_8b;
5260 if (resp->hwrm_intf_maj_8b < 1) {
5261 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
5262 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
5263 resp->hwrm_intf_upd_8b);
5264 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
5265 }
5266 snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d.%d",
5267 resp->hwrm_fw_maj_8b, resp->hwrm_fw_min_8b,
5268 resp->hwrm_fw_bld_8b, resp->hwrm_fw_rsvd_8b);
5269
5270 bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
5271 if (!bp->hwrm_cmd_timeout)
5272 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
5273
5274 if (resp->hwrm_intf_maj_8b >= 1)
5275 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
5276
5277 bp->chip_num = le16_to_cpu(resp->chip_num);
5278 if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev &&
5279 !resp->chip_metal)
5280 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0;
5281
5282 dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg);
5283 if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
5284 (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED))
5285 bp->flags |= BNXT_FLAG_SHORT_CMD;
5286
5287 hwrm_ver_get_exit:
5288 mutex_unlock(&bp->hwrm_cmd_lock);
5289 return rc;
5290 }
5291
5292 int bnxt_hwrm_fw_set_time(struct bnxt *bp)
5293 {
5294 struct hwrm_fw_set_time_input req = {0};
5295 struct tm tm;
5296 time64_t now = ktime_get_real_seconds();
5297
5298 if (bp->hwrm_spec_code < 0x10400)
5299 return -EOPNOTSUPP;
5300
5301 time64_to_tm(now, 0, &tm);
5302 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1);
5303 req.year = cpu_to_le16(1900 + tm.tm_year);
5304 req.month = 1 + tm.tm_mon;
5305 req.day = tm.tm_mday;
5306 req.hour = tm.tm_hour;
5307 req.minute = tm.tm_min;
5308 req.second = tm.tm_sec;
5309 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5310 }
5311
5312 static int bnxt_hwrm_port_qstats(struct bnxt *bp)
5313 {
5314 int rc;
5315 struct bnxt_pf_info *pf = &bp->pf;
5316 struct hwrm_port_qstats_input req = {0};
5317
5318 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
5319 return 0;
5320
5321 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
5322 req.port_id = cpu_to_le16(pf->port_id);
5323 req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map);
5324 req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map);
5325 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5326 return rc;
5327 }
5328
5329 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
5330 {
5331 if (bp->vxlan_port_cnt) {
5332 bnxt_hwrm_tunnel_dst_port_free(
5333 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
5334 }
5335 bp->vxlan_port_cnt = 0;
5336 if (bp->nge_port_cnt) {
5337 bnxt_hwrm_tunnel_dst_port_free(
5338 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
5339 }
5340 bp->nge_port_cnt = 0;
5341 }
5342
5343 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
5344 {
5345 int rc, i;
5346 u32 tpa_flags = 0;
5347
5348 if (set_tpa)
5349 tpa_flags = bp->flags & BNXT_FLAG_TPA;
5350 for (i = 0; i < bp->nr_vnics; i++) {
5351 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
5352 if (rc) {
5353 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
5354 i, rc);
5355 return rc;
5356 }
5357 }
5358 return 0;
5359 }
5360
5361 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
5362 {
5363 int i;
5364
5365 for (i = 0; i < bp->nr_vnics; i++)
5366 bnxt_hwrm_vnic_set_rss(bp, i, false);
5367 }
5368
5369 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
5370 bool irq_re_init)
5371 {
5372 if (bp->vnic_info) {
5373 bnxt_hwrm_clear_vnic_filter(bp);
5374 /* clear all RSS setting before free vnic ctx */
5375 bnxt_hwrm_clear_vnic_rss(bp);
5376 bnxt_hwrm_vnic_ctx_free(bp);
5377 /* before free the vnic, undo the vnic tpa settings */
5378 if (bp->flags & BNXT_FLAG_TPA)
5379 bnxt_set_tpa(bp, false);
5380 bnxt_hwrm_vnic_free(bp);
5381 }
5382 bnxt_hwrm_ring_free(bp, close_path);
5383 bnxt_hwrm_ring_grp_free(bp);
5384 if (irq_re_init) {
5385 bnxt_hwrm_stat_ctx_free(bp);
5386 bnxt_hwrm_free_tunnel_ports(bp);
5387 }
5388 }
5389
5390 static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode)
5391 {
5392 struct hwrm_func_cfg_input req = {0};
5393 int rc;
5394
5395 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
5396 req.fid = cpu_to_le16(0xffff);
5397 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE);
5398 if (br_mode == BRIDGE_MODE_VEB)
5399 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB;
5400 else if (br_mode == BRIDGE_MODE_VEPA)
5401 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA;
5402 else
5403 return -EINVAL;
5404 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5405 if (rc)
5406 rc = -EIO;
5407 return rc;
5408 }
5409
5410 static int bnxt_hwrm_set_cache_line_size(struct bnxt *bp, int size)
5411 {
5412 struct hwrm_func_cfg_input req = {0};
5413 int rc;
5414
5415 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10803)
5416 return 0;
5417
5418 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
5419 req.fid = cpu_to_le16(0xffff);
5420 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE);
5421 req.cache_linesize = FUNC_QCFG_RESP_CACHE_LINESIZE_CACHE_LINESIZE_64;
5422 if (size == 128)
5423 req.cache_linesize =
5424 FUNC_QCFG_RESP_CACHE_LINESIZE_CACHE_LINESIZE_128;
5425
5426 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5427 if (rc)
5428 rc = -EIO;
5429 return rc;
5430 }
5431
5432 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
5433 {
5434 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5435 int rc;
5436
5437 if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG)
5438 goto skip_rss_ctx;
5439
5440 /* allocate context for vnic */
5441 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0);
5442 if (rc) {
5443 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
5444 vnic_id, rc);
5445 goto vnic_setup_err;
5446 }
5447 bp->rsscos_nr_ctxs++;
5448
5449 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
5450 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1);
5451 if (rc) {
5452 netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
5453 vnic_id, rc);
5454 goto vnic_setup_err;
5455 }
5456 bp->rsscos_nr_ctxs++;
5457 }
5458
5459 skip_rss_ctx:
5460 /* configure default vnic, ring grp */
5461 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
5462 if (rc) {
5463 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
5464 vnic_id, rc);
5465 goto vnic_setup_err;
5466 }
5467
5468 /* Enable RSS hashing on vnic */
5469 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
5470 if (rc) {
5471 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
5472 vnic_id, rc);
5473 goto vnic_setup_err;
5474 }
5475
5476 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
5477 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
5478 if (rc) {
5479 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
5480 vnic_id, rc);
5481 }
5482 }
5483
5484 vnic_setup_err:
5485 return rc;
5486 }
5487
5488 static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
5489 {
5490 #ifdef CONFIG_RFS_ACCEL
5491 int i, rc = 0;
5492
5493 for (i = 0; i < bp->rx_nr_rings; i++) {
5494 struct bnxt_vnic_info *vnic;
5495 u16 vnic_id = i + 1;
5496 u16 ring_id = i;
5497
5498 if (vnic_id >= bp->nr_vnics)
5499 break;
5500
5501 vnic = &bp->vnic_info[vnic_id];
5502 vnic->flags |= BNXT_VNIC_RFS_FLAG;
5503 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
5504 vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG;
5505 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
5506 if (rc) {
5507 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
5508 vnic_id, rc);
5509 break;
5510 }
5511 rc = bnxt_setup_vnic(bp, vnic_id);
5512 if (rc)
5513 break;
5514 }
5515 return rc;
5516 #else
5517 return 0;
5518 #endif
5519 }
5520
5521 /* Allow PF and VF with default VLAN to be in promiscuous mode */
5522 static bool bnxt_promisc_ok(struct bnxt *bp)
5523 {
5524 #ifdef CONFIG_BNXT_SRIOV
5525 if (BNXT_VF(bp) && !bp->vf.vlan)
5526 return false;
5527 #endif
5528 return true;
5529 }
5530
5531 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp)
5532 {
5533 unsigned int rc = 0;
5534
5535 rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1);
5536 if (rc) {
5537 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
5538 rc);
5539 return rc;
5540 }
5541
5542 rc = bnxt_hwrm_vnic_cfg(bp, 1);
5543 if (rc) {
5544 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
5545 rc);
5546 return rc;
5547 }
5548 return rc;
5549 }
5550
5551 static int bnxt_cfg_rx_mode(struct bnxt *);
5552 static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
5553
5554 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
5555 {
5556 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5557 int rc = 0;
5558 unsigned int rx_nr_rings = bp->rx_nr_rings;
5559
5560 if (irq_re_init) {
5561 rc = bnxt_hwrm_stat_ctx_alloc(bp);
5562 if (rc) {
5563 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
5564 rc);
5565 goto err_out;
5566 }
5567 }
5568
5569 rc = bnxt_hwrm_ring_alloc(bp);
5570 if (rc) {
5571 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
5572 goto err_out;
5573 }
5574
5575 rc = bnxt_hwrm_ring_grp_alloc(bp);
5576 if (rc) {
5577 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
5578 goto err_out;
5579 }
5580
5581 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5582 rx_nr_rings--;
5583
5584 /* default vnic 0 */
5585 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings);
5586 if (rc) {
5587 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
5588 goto err_out;
5589 }
5590
5591 rc = bnxt_setup_vnic(bp, 0);
5592 if (rc)
5593 goto err_out;
5594
5595 if (bp->flags & BNXT_FLAG_RFS) {
5596 rc = bnxt_alloc_rfs_vnics(bp);
5597 if (rc)
5598 goto err_out;
5599 }
5600
5601 if (bp->flags & BNXT_FLAG_TPA) {
5602 rc = bnxt_set_tpa(bp, true);
5603 if (rc)
5604 goto err_out;
5605 }
5606
5607 if (BNXT_VF(bp))
5608 bnxt_update_vf_mac(bp);
5609
5610 /* Filter for default vnic 0 */
5611 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
5612 if (rc) {
5613 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
5614 goto err_out;
5615 }
5616 vnic->uc_filter_count = 1;
5617
5618 vnic->rx_mask = CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
5619
5620 if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
5621 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
5622
5623 if (bp->dev->flags & IFF_ALLMULTI) {
5624 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
5625 vnic->mc_list_count = 0;
5626 } else {
5627 u32 mask = 0;
5628
5629 bnxt_mc_list_updated(bp, &mask);
5630 vnic->rx_mask |= mask;
5631 }
5632
5633 rc = bnxt_cfg_rx_mode(bp);
5634 if (rc)
5635 goto err_out;
5636
5637 rc = bnxt_hwrm_set_coal(bp);
5638 if (rc)
5639 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
5640 rc);
5641
5642 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
5643 rc = bnxt_setup_nitroa0_vnic(bp);
5644 if (rc)
5645 netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n",
5646 rc);
5647 }
5648
5649 if (BNXT_VF(bp)) {
5650 bnxt_hwrm_func_qcfg(bp);
5651 netdev_update_features(bp->dev);
5652 }
5653
5654 return 0;
5655
5656 err_out:
5657 bnxt_hwrm_resource_free(bp, 0, true);
5658
5659 return rc;
5660 }
5661
5662 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
5663 {
5664 bnxt_hwrm_resource_free(bp, 1, irq_re_init);
5665 return 0;
5666 }
5667
5668 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
5669 {
5670 bnxt_init_cp_rings(bp);
5671 bnxt_init_rx_rings(bp);
5672 bnxt_init_tx_rings(bp);
5673 bnxt_init_ring_grps(bp, irq_re_init);
5674 bnxt_init_vnics(bp);
5675
5676 return bnxt_init_chip(bp, irq_re_init);
5677 }
5678
5679 static int bnxt_set_real_num_queues(struct bnxt *bp)
5680 {
5681 int rc;
5682 struct net_device *dev = bp->dev;
5683
5684 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings -
5685 bp->tx_nr_rings_xdp);
5686 if (rc)
5687 return rc;
5688
5689 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
5690 if (rc)
5691 return rc;
5692
5693 #ifdef CONFIG_RFS_ACCEL
5694 if (bp->flags & BNXT_FLAG_RFS)
5695 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
5696 #endif
5697
5698 return rc;
5699 }
5700
5701 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
5702 bool shared)
5703 {
5704 int _rx = *rx, _tx = *tx;
5705
5706 if (shared) {
5707 *rx = min_t(int, _rx, max);
5708 *tx = min_t(int, _tx, max);
5709 } else {
5710 if (max < 2)
5711 return -ENOMEM;
5712
5713 while (_rx + _tx > max) {
5714 if (_rx > _tx && _rx > 1)
5715 _rx--;
5716 else if (_tx > 1)
5717 _tx--;
5718 }
5719 *rx = _rx;
5720 *tx = _tx;
5721 }
5722 return 0;
5723 }
5724
5725 static void bnxt_setup_msix(struct bnxt *bp)
5726 {
5727 const int len = sizeof(bp->irq_tbl[0].name);
5728 struct net_device *dev = bp->dev;
5729 int tcs, i;
5730
5731 tcs = netdev_get_num_tc(dev);
5732 if (tcs > 1) {
5733 int i, off, count;
5734
5735 for (i = 0; i < tcs; i++) {
5736 count = bp->tx_nr_rings_per_tc;
5737 off = i * count;
5738 netdev_set_tc_queue(dev, i, count, off);
5739 }
5740 }
5741
5742 for (i = 0; i < bp->cp_nr_rings; i++) {
5743 char *attr;
5744
5745 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
5746 attr = "TxRx";
5747 else if (i < bp->rx_nr_rings)
5748 attr = "rx";
5749 else
5750 attr = "tx";
5751
5752 snprintf(bp->irq_tbl[i].name, len, "%s-%s-%d", dev->name, attr,
5753 i);
5754 bp->irq_tbl[i].handler = bnxt_msix;
5755 }
5756 }
5757
5758 static void bnxt_setup_inta(struct bnxt *bp)
5759 {
5760 const int len = sizeof(bp->irq_tbl[0].name);
5761
5762 if (netdev_get_num_tc(bp->dev))
5763 netdev_reset_tc(bp->dev);
5764
5765 snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx",
5766 0);
5767 bp->irq_tbl[0].handler = bnxt_inta;
5768 }
5769
5770 static int bnxt_setup_int_mode(struct bnxt *bp)
5771 {
5772 int rc;
5773
5774 if (bp->flags & BNXT_FLAG_USING_MSIX)
5775 bnxt_setup_msix(bp);
5776 else
5777 bnxt_setup_inta(bp);
5778
5779 rc = bnxt_set_real_num_queues(bp);
5780 return rc;
5781 }
5782
5783 #ifdef CONFIG_RFS_ACCEL
5784 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp)
5785 {
5786 return bp->hw_resc.max_rsscos_ctxs;
5787 }
5788
5789 static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp)
5790 {
5791 return bp->hw_resc.max_vnics;
5792 }
5793 #endif
5794
5795 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp)
5796 {
5797 return bp->hw_resc.max_stat_ctxs;
5798 }
5799
5800 void bnxt_set_max_func_stat_ctxs(struct bnxt *bp, unsigned int max)
5801 {
5802 bp->hw_resc.max_stat_ctxs = max;
5803 }
5804
5805 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp)
5806 {
5807 return bp->hw_resc.max_cp_rings;
5808 }
5809
5810 void bnxt_set_max_func_cp_rings(struct bnxt *bp, unsigned int max)
5811 {
5812 bp->hw_resc.max_cp_rings = max;
5813 }
5814
5815 static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp)
5816 {
5817 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5818
5819 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_cp_rings);
5820 }
5821
5822 void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs)
5823 {
5824 bp->hw_resc.max_irqs = max_irqs;
5825 }
5826
5827 static int bnxt_init_msix(struct bnxt *bp)
5828 {
5829 int i, total_vecs, rc = 0, min = 1;
5830 struct msix_entry *msix_ent;
5831
5832 total_vecs = bnxt_get_max_func_irqs(bp);
5833 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
5834 if (!msix_ent)
5835 return -ENOMEM;
5836
5837 for (i = 0; i < total_vecs; i++) {
5838 msix_ent[i].entry = i;
5839 msix_ent[i].vector = 0;
5840 }
5841
5842 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
5843 min = 2;
5844
5845 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
5846 if (total_vecs < 0) {
5847 rc = -ENODEV;
5848 goto msix_setup_exit;
5849 }
5850
5851 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
5852 if (bp->irq_tbl) {
5853 for (i = 0; i < total_vecs; i++)
5854 bp->irq_tbl[i].vector = msix_ent[i].vector;
5855
5856 bp->total_irqs = total_vecs;
5857 /* Trim rings based upon num of vectors allocated */
5858 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
5859 total_vecs, min == 1);
5860 if (rc)
5861 goto msix_setup_exit;
5862
5863 bp->cp_nr_rings = (min == 1) ?
5864 max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
5865 bp->tx_nr_rings + bp->rx_nr_rings;
5866
5867 } else {
5868 rc = -ENOMEM;
5869 goto msix_setup_exit;
5870 }
5871 bp->flags |= BNXT_FLAG_USING_MSIX;
5872 kfree(msix_ent);
5873 return 0;
5874
5875 msix_setup_exit:
5876 netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc);
5877 kfree(bp->irq_tbl);
5878 bp->irq_tbl = NULL;
5879 pci_disable_msix(bp->pdev);
5880 kfree(msix_ent);
5881 return rc;
5882 }
5883
5884 static int bnxt_init_inta(struct bnxt *bp)
5885 {
5886 bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
5887 if (!bp->irq_tbl)
5888 return -ENOMEM;
5889
5890 bp->total_irqs = 1;
5891 bp->rx_nr_rings = 1;
5892 bp->tx_nr_rings = 1;
5893 bp->cp_nr_rings = 1;
5894 bp->flags |= BNXT_FLAG_SHARED_RINGS;
5895 bp->irq_tbl[0].vector = bp->pdev->irq;
5896 return 0;
5897 }
5898
5899 static int bnxt_init_int_mode(struct bnxt *bp)
5900 {
5901 int rc = 0;
5902
5903 if (bp->flags & BNXT_FLAG_MSIX_CAP)
5904 rc = bnxt_init_msix(bp);
5905
5906 if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
5907 /* fallback to INTA */
5908 rc = bnxt_init_inta(bp);
5909 }
5910 return rc;
5911 }
5912
5913 static void bnxt_clear_int_mode(struct bnxt *bp)
5914 {
5915 if (bp->flags & BNXT_FLAG_USING_MSIX)
5916 pci_disable_msix(bp->pdev);
5917
5918 kfree(bp->irq_tbl);
5919 bp->irq_tbl = NULL;
5920 bp->flags &= ~BNXT_FLAG_USING_MSIX;
5921 }
5922
5923 static int bnxt_reserve_rings(struct bnxt *bp)
5924 {
5925 int orig_cp = bp->hw_resc.resv_cp_rings;
5926 int tcs = netdev_get_num_tc(bp->dev);
5927 int rc;
5928
5929 if (!bnxt_need_reserve_rings(bp))
5930 return 0;
5931
5932 rc = __bnxt_reserve_rings(bp);
5933 if (rc) {
5934 netdev_err(bp->dev, "ring reservation failure rc: %d\n", rc);
5935 return rc;
5936 }
5937 if ((bp->flags & BNXT_FLAG_NEW_RM) && bp->cp_nr_rings > orig_cp) {
5938 bnxt_clear_int_mode(bp);
5939 rc = bnxt_init_int_mode(bp);
5940 if (rc)
5941 return rc;
5942 }
5943 if (tcs && (bp->tx_nr_rings_per_tc * tcs != bp->tx_nr_rings)) {
5944 netdev_err(bp->dev, "tx ring reservation failure\n");
5945 netdev_reset_tc(bp->dev);
5946 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
5947 return -ENOMEM;
5948 }
5949 bp->num_stat_ctxs = bp->cp_nr_rings;
5950 return 0;
5951 }
5952
5953 static void bnxt_free_irq(struct bnxt *bp)
5954 {
5955 struct bnxt_irq *irq;
5956 int i;
5957
5958 #ifdef CONFIG_RFS_ACCEL
5959 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
5960 bp->dev->rx_cpu_rmap = NULL;
5961 #endif
5962 if (!bp->irq_tbl)
5963 return;
5964
5965 for (i = 0; i < bp->cp_nr_rings; i++) {
5966 irq = &bp->irq_tbl[i];
5967 if (irq->requested) {
5968 if (irq->have_cpumask) {
5969 irq_set_affinity_hint(irq->vector, NULL);
5970 free_cpumask_var(irq->cpu_mask);
5971 irq->have_cpumask = 0;
5972 }
5973 free_irq(irq->vector, bp->bnapi[i]);
5974 }
5975
5976 irq->requested = 0;
5977 }
5978 }
5979
5980 static int bnxt_request_irq(struct bnxt *bp)
5981 {
5982 int i, j, rc = 0;
5983 unsigned long flags = 0;
5984 #ifdef CONFIG_RFS_ACCEL
5985 struct cpu_rmap *rmap = bp->dev->rx_cpu_rmap;
5986 #endif
5987
5988 if (!(bp->flags & BNXT_FLAG_USING_MSIX))
5989 flags = IRQF_SHARED;
5990
5991 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
5992 struct bnxt_irq *irq = &bp->irq_tbl[i];
5993 #ifdef CONFIG_RFS_ACCEL
5994 if (rmap && bp->bnapi[i]->rx_ring) {
5995 rc = irq_cpu_rmap_add(rmap, irq->vector);
5996 if (rc)
5997 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
5998 j);
5999 j++;
6000 }
6001 #endif
6002 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
6003 bp->bnapi[i]);
6004 if (rc)
6005 break;
6006
6007 irq->requested = 1;
6008
6009 if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) {
6010 int numa_node = dev_to_node(&bp->pdev->dev);
6011
6012 irq->have_cpumask = 1;
6013 cpumask_set_cpu(cpumask_local_spread(i, numa_node),
6014 irq->cpu_mask);
6015 rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask);
6016 if (rc) {
6017 netdev_warn(bp->dev,
6018 "Set affinity failed, IRQ = %d\n",
6019 irq->vector);
6020 break;
6021 }
6022 }
6023 }
6024 return rc;
6025 }
6026
6027 static void bnxt_del_napi(struct bnxt *bp)
6028 {
6029 int i;
6030
6031 if (!bp->bnapi)
6032 return;
6033
6034 for (i = 0; i < bp->cp_nr_rings; i++) {
6035 struct bnxt_napi *bnapi = bp->bnapi[i];
6036
6037 napi_hash_del(&bnapi->napi);
6038 netif_napi_del(&bnapi->napi);
6039 }
6040 /* We called napi_hash_del() before netif_napi_del(), we need
6041 * to respect an RCU grace period before freeing napi structures.
6042 */
6043 synchronize_net();
6044 }
6045
6046 static void bnxt_init_napi(struct bnxt *bp)
6047 {
6048 int i;
6049 unsigned int cp_nr_rings = bp->cp_nr_rings;
6050 struct bnxt_napi *bnapi;
6051
6052 if (bp->flags & BNXT_FLAG_USING_MSIX) {
6053 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
6054 cp_nr_rings--;
6055 for (i = 0; i < cp_nr_rings; i++) {
6056 bnapi = bp->bnapi[i];
6057 netif_napi_add(bp->dev, &bnapi->napi,
6058 bnxt_poll, 64);
6059 }
6060 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
6061 bnapi = bp->bnapi[cp_nr_rings];
6062 netif_napi_add(bp->dev, &bnapi->napi,
6063 bnxt_poll_nitroa0, 64);
6064 }
6065 } else {
6066 bnapi = bp->bnapi[0];
6067 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
6068 }
6069 }
6070
6071 static void bnxt_disable_napi(struct bnxt *bp)
6072 {
6073 int i;
6074
6075 if (!bp->bnapi)
6076 return;
6077
6078 for (i = 0; i < bp->cp_nr_rings; i++) {
6079 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
6080
6081 if (bp->bnapi[i]->rx_ring)
6082 cancel_work_sync(&cpr->dim.work);
6083
6084 napi_disable(&bp->bnapi[i]->napi);
6085 }
6086 }
6087
6088 static void bnxt_enable_napi(struct bnxt *bp)
6089 {
6090 int i;
6091
6092 for (i = 0; i < bp->cp_nr_rings; i++) {
6093 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
6094 bp->bnapi[i]->in_reset = false;
6095
6096 if (bp->bnapi[i]->rx_ring) {
6097 INIT_WORK(&cpr->dim.work, bnxt_dim_work);
6098 cpr->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
6099 }
6100 napi_enable(&bp->bnapi[i]->napi);
6101 }
6102 }
6103
6104 void bnxt_tx_disable(struct bnxt *bp)
6105 {
6106 int i;
6107 struct bnxt_tx_ring_info *txr;
6108
6109 if (bp->tx_ring) {
6110 for (i = 0; i < bp->tx_nr_rings; i++) {
6111 txr = &bp->tx_ring[i];
6112 txr->dev_state = BNXT_DEV_STATE_CLOSING;
6113 }
6114 }
6115 /* Stop all TX queues */
6116 netif_tx_disable(bp->dev);
6117 netif_carrier_off(bp->dev);
6118 }
6119
6120 void bnxt_tx_enable(struct bnxt *bp)
6121 {
6122 int i;
6123 struct bnxt_tx_ring_info *txr;
6124
6125 for (i = 0; i < bp->tx_nr_rings; i++) {
6126 txr = &bp->tx_ring[i];
6127 txr->dev_state = 0;
6128 }
6129 netif_tx_wake_all_queues(bp->dev);
6130 if (bp->link_info.link_up)
6131 netif_carrier_on(bp->dev);
6132 }
6133
6134 static void bnxt_report_link(struct bnxt *bp)
6135 {
6136 if (bp->link_info.link_up) {
6137 const char *duplex;
6138 const char *flow_ctrl;
6139 u32 speed;
6140 u16 fec;
6141
6142 netif_carrier_on(bp->dev);
6143 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
6144 duplex = "full";
6145 else
6146 duplex = "half";
6147 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
6148 flow_ctrl = "ON - receive & transmit";
6149 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
6150 flow_ctrl = "ON - transmit";
6151 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
6152 flow_ctrl = "ON - receive";
6153 else
6154 flow_ctrl = "none";
6155 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
6156 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n",
6157 speed, duplex, flow_ctrl);
6158 if (bp->flags & BNXT_FLAG_EEE_CAP)
6159 netdev_info(bp->dev, "EEE is %s\n",
6160 bp->eee.eee_active ? "active" :
6161 "not active");
6162 fec = bp->link_info.fec_cfg;
6163 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED))
6164 netdev_info(bp->dev, "FEC autoneg %s encodings: %s\n",
6165 (fec & BNXT_FEC_AUTONEG) ? "on" : "off",
6166 (fec & BNXT_FEC_ENC_BASE_R) ? "BaseR" :
6167 (fec & BNXT_FEC_ENC_RS) ? "RS" : "None");
6168 } else {
6169 netif_carrier_off(bp->dev);
6170 netdev_err(bp->dev, "NIC Link is Down\n");
6171 }
6172 }
6173
6174 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
6175 {
6176 int rc = 0;
6177 struct hwrm_port_phy_qcaps_input req = {0};
6178 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6179 struct bnxt_link_info *link_info = &bp->link_info;
6180
6181 if (bp->hwrm_spec_code < 0x10201)
6182 return 0;
6183
6184 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
6185
6186 mutex_lock(&bp->hwrm_cmd_lock);
6187 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6188 if (rc)
6189 goto hwrm_phy_qcaps_exit;
6190
6191 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) {
6192 struct ethtool_eee *eee = &bp->eee;
6193 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
6194
6195 bp->flags |= BNXT_FLAG_EEE_CAP;
6196 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
6197 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
6198 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
6199 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
6200 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
6201 }
6202 if (resp->supported_speeds_auto_mode)
6203 link_info->support_auto_speeds =
6204 le16_to_cpu(resp->supported_speeds_auto_mode);
6205
6206 bp->port_count = resp->port_cnt;
6207
6208 hwrm_phy_qcaps_exit:
6209 mutex_unlock(&bp->hwrm_cmd_lock);
6210 return rc;
6211 }
6212
6213 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
6214 {
6215 int rc = 0;
6216 struct bnxt_link_info *link_info = &bp->link_info;
6217 struct hwrm_port_phy_qcfg_input req = {0};
6218 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
6219 u8 link_up = link_info->link_up;
6220 u16 diff;
6221
6222 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
6223
6224 mutex_lock(&bp->hwrm_cmd_lock);
6225 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6226 if (rc) {
6227 mutex_unlock(&bp->hwrm_cmd_lock);
6228 return rc;
6229 }
6230
6231 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
6232 link_info->phy_link_status = resp->link;
6233 link_info->duplex = resp->duplex_cfg;
6234 if (bp->hwrm_spec_code >= 0x10800)
6235 link_info->duplex = resp->duplex_state;
6236 link_info->pause = resp->pause;
6237 link_info->auto_mode = resp->auto_mode;
6238 link_info->auto_pause_setting = resp->auto_pause;
6239 link_info->lp_pause = resp->link_partner_adv_pause;
6240 link_info->force_pause_setting = resp->force_pause;
6241 link_info->duplex_setting = resp->duplex_cfg;
6242 if (link_info->phy_link_status == BNXT_LINK_LINK)
6243 link_info->link_speed = le16_to_cpu(resp->link_speed);
6244 else
6245 link_info->link_speed = 0;
6246 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
6247 link_info->support_speeds = le16_to_cpu(resp->support_speeds);
6248 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
6249 link_info->lp_auto_link_speeds =
6250 le16_to_cpu(resp->link_partner_adv_speeds);
6251 link_info->preemphasis = le32_to_cpu(resp->preemphasis);
6252 link_info->phy_ver[0] = resp->phy_maj;
6253 link_info->phy_ver[1] = resp->phy_min;
6254 link_info->phy_ver[2] = resp->phy_bld;
6255 link_info->media_type = resp->media_type;
6256 link_info->phy_type = resp->phy_type;
6257 link_info->transceiver = resp->xcvr_pkg_type;
6258 link_info->phy_addr = resp->eee_config_phy_addr &
6259 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
6260 link_info->module_status = resp->module_status;
6261
6262 if (bp->flags & BNXT_FLAG_EEE_CAP) {
6263 struct ethtool_eee *eee = &bp->eee;
6264 u16 fw_speeds;
6265
6266 eee->eee_active = 0;
6267 if (resp->eee_config_phy_addr &
6268 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
6269 eee->eee_active = 1;
6270 fw_speeds = le16_to_cpu(
6271 resp->link_partner_adv_eee_link_speed_mask);
6272 eee->lp_advertised =
6273 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
6274 }
6275
6276 /* Pull initial EEE config */
6277 if (!chng_link_state) {
6278 if (resp->eee_config_phy_addr &
6279 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
6280 eee->eee_enabled = 1;
6281
6282 fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
6283 eee->advertised =
6284 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
6285
6286 if (resp->eee_config_phy_addr &
6287 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
6288 __le32 tmr;
6289
6290 eee->tx_lpi_enabled = 1;
6291 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
6292 eee->tx_lpi_timer = le32_to_cpu(tmr) &
6293 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
6294 }
6295 }
6296 }
6297
6298 link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED;
6299 if (bp->hwrm_spec_code >= 0x10504)
6300 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg);
6301
6302 /* TODO: need to add more logic to report VF link */
6303 if (chng_link_state) {
6304 if (link_info->phy_link_status == BNXT_LINK_LINK)
6305 link_info->link_up = 1;
6306 else
6307 link_info->link_up = 0;
6308 if (link_up != link_info->link_up)
6309 bnxt_report_link(bp);
6310 } else {
6311 /* alwasy link down if not require to update link state */
6312 link_info->link_up = 0;
6313 }
6314 mutex_unlock(&bp->hwrm_cmd_lock);
6315
6316 diff = link_info->support_auto_speeds ^ link_info->advertising;
6317 if ((link_info->support_auto_speeds | diff) !=
6318 link_info->support_auto_speeds) {
6319 /* An advertised speed is no longer supported, so we need to
6320 * update the advertisement settings. Caller holds RTNL
6321 * so we can modify link settings.
6322 */
6323 link_info->advertising = link_info->support_auto_speeds;
6324 if (link_info->autoneg & BNXT_AUTONEG_SPEED)
6325 bnxt_hwrm_set_link_setting(bp, true, false);
6326 }
6327 return 0;
6328 }
6329
6330 static void bnxt_get_port_module_status(struct bnxt *bp)
6331 {
6332 struct bnxt_link_info *link_info = &bp->link_info;
6333 struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
6334 u8 module_status;
6335
6336 if (bnxt_update_link(bp, true))
6337 return;
6338
6339 module_status = link_info->module_status;
6340 switch (module_status) {
6341 case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX:
6342 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
6343 case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG:
6344 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
6345 bp->pf.port_id);
6346 if (bp->hwrm_spec_code >= 0x10201) {
6347 netdev_warn(bp->dev, "Module part number %s\n",
6348 resp->phy_vendor_partnumber);
6349 }
6350 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX)
6351 netdev_warn(bp->dev, "TX is disabled\n");
6352 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN)
6353 netdev_warn(bp->dev, "SFP+ module is shutdown\n");
6354 }
6355 }
6356
6357 static void
6358 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
6359 {
6360 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
6361 if (bp->hwrm_spec_code >= 0x10201)
6362 req->auto_pause =
6363 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
6364 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
6365 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
6366 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
6367 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
6368 req->enables |=
6369 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
6370 } else {
6371 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
6372 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
6373 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
6374 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
6375 req->enables |=
6376 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
6377 if (bp->hwrm_spec_code >= 0x10201) {
6378 req->auto_pause = req->force_pause;
6379 req->enables |= cpu_to_le32(
6380 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
6381 }
6382 }
6383 }
6384
6385 static void bnxt_hwrm_set_link_common(struct bnxt *bp,
6386 struct hwrm_port_phy_cfg_input *req)
6387 {
6388 u8 autoneg = bp->link_info.autoneg;
6389 u16 fw_link_speed = bp->link_info.req_link_speed;
6390 u16 advertising = bp->link_info.advertising;
6391
6392 if (autoneg & BNXT_AUTONEG_SPEED) {
6393 req->auto_mode |=
6394 PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
6395
6396 req->enables |= cpu_to_le32(
6397 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
6398 req->auto_link_speed_mask = cpu_to_le16(advertising);
6399
6400 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
6401 req->flags |=
6402 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
6403 } else {
6404 req->force_link_speed = cpu_to_le16(fw_link_speed);
6405 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
6406 }
6407
6408 /* tell chimp that the setting takes effect immediately */
6409 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
6410 }
6411
6412 int bnxt_hwrm_set_pause(struct bnxt *bp)
6413 {
6414 struct hwrm_port_phy_cfg_input req = {0};
6415 int rc;
6416
6417 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
6418 bnxt_hwrm_set_pause_common(bp, &req);
6419
6420 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
6421 bp->link_info.force_link_chng)
6422 bnxt_hwrm_set_link_common(bp, &req);
6423
6424 mutex_lock(&bp->hwrm_cmd_lock);
6425 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6426 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
6427 /* since changing of pause setting doesn't trigger any link
6428 * change event, the driver needs to update the current pause
6429 * result upon successfully return of the phy_cfg command
6430 */
6431 bp->link_info.pause =
6432 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
6433 bp->link_info.auto_pause_setting = 0;
6434 if (!bp->link_info.force_link_chng)
6435 bnxt_report_link(bp);
6436 }
6437 bp->link_info.force_link_chng = false;
6438 mutex_unlock(&bp->hwrm_cmd_lock);
6439 return rc;
6440 }
6441
6442 static void bnxt_hwrm_set_eee(struct bnxt *bp,
6443 struct hwrm_port_phy_cfg_input *req)
6444 {
6445 struct ethtool_eee *eee = &bp->eee;
6446
6447 if (eee->eee_enabled) {
6448 u16 eee_speeds;
6449 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
6450
6451 if (eee->tx_lpi_enabled)
6452 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
6453 else
6454 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
6455
6456 req->flags |= cpu_to_le32(flags);
6457 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
6458 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
6459 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
6460 } else {
6461 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
6462 }
6463 }
6464
6465 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
6466 {
6467 struct hwrm_port_phy_cfg_input req = {0};
6468
6469 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
6470 if (set_pause)
6471 bnxt_hwrm_set_pause_common(bp, &req);
6472
6473 bnxt_hwrm_set_link_common(bp, &req);
6474
6475 if (set_eee)
6476 bnxt_hwrm_set_eee(bp, &req);
6477 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6478 }
6479
6480 static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
6481 {
6482 struct hwrm_port_phy_cfg_input req = {0};
6483
6484 if (!BNXT_SINGLE_PF(bp))
6485 return 0;
6486
6487 if (pci_num_vf(bp->pdev))
6488 return 0;
6489
6490 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
6491 req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN);
6492 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6493 }
6494
6495 static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
6496 {
6497 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6498 struct hwrm_port_led_qcaps_input req = {0};
6499 struct bnxt_pf_info *pf = &bp->pf;
6500 int rc;
6501
6502 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601)
6503 return 0;
6504
6505 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1);
6506 req.port_id = cpu_to_le16(pf->port_id);
6507 mutex_lock(&bp->hwrm_cmd_lock);
6508 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6509 if (rc) {
6510 mutex_unlock(&bp->hwrm_cmd_lock);
6511 return rc;
6512 }
6513 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
6514 int i;
6515
6516 bp->num_leds = resp->num_leds;
6517 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) *
6518 bp->num_leds);
6519 for (i = 0; i < bp->num_leds; i++) {
6520 struct bnxt_led_info *led = &bp->leds[i];
6521 __le16 caps = led->led_state_caps;
6522
6523 if (!led->led_group_id ||
6524 !BNXT_LED_ALT_BLINK_CAP(caps)) {
6525 bp->num_leds = 0;
6526 break;
6527 }
6528 }
6529 }
6530 mutex_unlock(&bp->hwrm_cmd_lock);
6531 return 0;
6532 }
6533
6534 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp)
6535 {
6536 struct hwrm_wol_filter_alloc_input req = {0};
6537 struct hwrm_wol_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
6538 int rc;
6539
6540 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_ALLOC, -1, -1);
6541 req.port_id = cpu_to_le16(bp->pf.port_id);
6542 req.wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT;
6543 req.enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS);
6544 memcpy(req.mac_address, bp->dev->dev_addr, ETH_ALEN);
6545 mutex_lock(&bp->hwrm_cmd_lock);
6546 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6547 if (!rc)
6548 bp->wol_filter_id = resp->wol_filter_id;
6549 mutex_unlock(&bp->hwrm_cmd_lock);
6550 return rc;
6551 }
6552
6553 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp)
6554 {
6555 struct hwrm_wol_filter_free_input req = {0};
6556 int rc;
6557
6558 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1);
6559 req.port_id = cpu_to_le16(bp->pf.port_id);
6560 req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID);
6561 req.wol_filter_id = bp->wol_filter_id;
6562 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6563 return rc;
6564 }
6565
6566 static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle)
6567 {
6568 struct hwrm_wol_filter_qcfg_input req = {0};
6569 struct hwrm_wol_filter_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
6570 u16 next_handle = 0;
6571 int rc;
6572
6573 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_QCFG, -1, -1);
6574 req.port_id = cpu_to_le16(bp->pf.port_id);
6575 req.handle = cpu_to_le16(handle);
6576 mutex_lock(&bp->hwrm_cmd_lock);
6577 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6578 if (!rc) {
6579 next_handle = le16_to_cpu(resp->next_handle);
6580 if (next_handle != 0) {
6581 if (resp->wol_type ==
6582 WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) {
6583 bp->wol = 1;
6584 bp->wol_filter_id = resp->wol_filter_id;
6585 }
6586 }
6587 }
6588 mutex_unlock(&bp->hwrm_cmd_lock);
6589 return next_handle;
6590 }
6591
6592 static void bnxt_get_wol_settings(struct bnxt *bp)
6593 {
6594 u16 handle = 0;
6595
6596 if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP))
6597 return;
6598
6599 do {
6600 handle = bnxt_hwrm_get_wol_fltrs(bp, handle);
6601 } while (handle && handle != 0xffff);
6602 }
6603
6604 static bool bnxt_eee_config_ok(struct bnxt *bp)
6605 {
6606 struct ethtool_eee *eee = &bp->eee;
6607 struct bnxt_link_info *link_info = &bp->link_info;
6608
6609 if (!(bp->flags & BNXT_FLAG_EEE_CAP))
6610 return true;
6611
6612 if (eee->eee_enabled) {
6613 u32 advertising =
6614 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
6615
6616 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
6617 eee->eee_enabled = 0;
6618 return false;
6619 }
6620 if (eee->advertised & ~advertising) {
6621 eee->advertised = advertising & eee->supported;
6622 return false;
6623 }
6624 }
6625 return true;
6626 }
6627
6628 static int bnxt_update_phy_setting(struct bnxt *bp)
6629 {
6630 int rc;
6631 bool update_link = false;
6632 bool update_pause = false;
6633 bool update_eee = false;
6634 struct bnxt_link_info *link_info = &bp->link_info;
6635
6636 rc = bnxt_update_link(bp, true);
6637 if (rc) {
6638 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
6639 rc);
6640 return rc;
6641 }
6642 if (!BNXT_SINGLE_PF(bp))
6643 return 0;
6644
6645 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
6646 (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
6647 link_info->req_flow_ctrl)
6648 update_pause = true;
6649 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
6650 link_info->force_pause_setting != link_info->req_flow_ctrl)
6651 update_pause = true;
6652 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
6653 if (BNXT_AUTO_MODE(link_info->auto_mode))
6654 update_link = true;
6655 if (link_info->req_link_speed != link_info->force_link_speed)
6656 update_link = true;
6657 if (link_info->req_duplex != link_info->duplex_setting)
6658 update_link = true;
6659 } else {
6660 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
6661 update_link = true;
6662 if (link_info->advertising != link_info->auto_link_speeds)
6663 update_link = true;
6664 }
6665
6666 /* The last close may have shutdown the link, so need to call
6667 * PHY_CFG to bring it back up.
6668 */
6669 if (!netif_carrier_ok(bp->dev))
6670 update_link = true;
6671
6672 if (!bnxt_eee_config_ok(bp))
6673 update_eee = true;
6674
6675 if (update_link)
6676 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
6677 else if (update_pause)
6678 rc = bnxt_hwrm_set_pause(bp);
6679 if (rc) {
6680 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
6681 rc);
6682 return rc;
6683 }
6684
6685 return rc;
6686 }
6687
6688 /* Common routine to pre-map certain register block to different GRC window.
6689 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
6690 * in PF and 3 windows in VF that can be customized to map in different
6691 * register blocks.
6692 */
6693 static void bnxt_preset_reg_win(struct bnxt *bp)
6694 {
6695 if (BNXT_PF(bp)) {
6696 /* CAG registers map to GRC window #4 */
6697 writel(BNXT_CAG_REG_BASE,
6698 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
6699 }
6700 }
6701
6702 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
6703 {
6704 int rc = 0;
6705
6706 bnxt_preset_reg_win(bp);
6707 netif_carrier_off(bp->dev);
6708 if (irq_re_init) {
6709 rc = bnxt_reserve_rings(bp);
6710 if (rc)
6711 return rc;
6712
6713 rc = bnxt_setup_int_mode(bp);
6714 if (rc) {
6715 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
6716 rc);
6717 return rc;
6718 }
6719 }
6720 if ((bp->flags & BNXT_FLAG_RFS) &&
6721 !(bp->flags & BNXT_FLAG_USING_MSIX)) {
6722 /* disable RFS if falling back to INTA */
6723 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
6724 bp->flags &= ~BNXT_FLAG_RFS;
6725 }
6726
6727 rc = bnxt_alloc_mem(bp, irq_re_init);
6728 if (rc) {
6729 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
6730 goto open_err_free_mem;
6731 }
6732
6733 if (irq_re_init) {
6734 bnxt_init_napi(bp);
6735 rc = bnxt_request_irq(bp);
6736 if (rc) {
6737 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
6738 goto open_err;
6739 }
6740 }
6741
6742 bnxt_enable_napi(bp);
6743
6744 rc = bnxt_init_nic(bp, irq_re_init);
6745 if (rc) {
6746 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
6747 goto open_err;
6748 }
6749
6750 if (link_re_init) {
6751 mutex_lock(&bp->link_lock);
6752 rc = bnxt_update_phy_setting(bp);
6753 mutex_unlock(&bp->link_lock);
6754 if (rc)
6755 netdev_warn(bp->dev, "failed to update phy settings\n");
6756 }
6757
6758 if (irq_re_init)
6759 udp_tunnel_get_rx_info(bp->dev);
6760
6761 set_bit(BNXT_STATE_OPEN, &bp->state);
6762 bnxt_enable_int(bp);
6763 /* Enable TX queues */
6764 bnxt_tx_enable(bp);
6765 mod_timer(&bp->timer, jiffies + bp->current_interval);
6766 /* Poll link status and check for SFP+ module status */
6767 bnxt_get_port_module_status(bp);
6768
6769 /* VF-reps may need to be re-opened after the PF is re-opened */
6770 if (BNXT_PF(bp))
6771 bnxt_vf_reps_open(bp);
6772 return 0;
6773
6774 open_err:
6775 bnxt_disable_napi(bp);
6776 bnxt_del_napi(bp);
6777
6778 open_err_free_mem:
6779 bnxt_free_skbs(bp);
6780 bnxt_free_irq(bp);
6781 bnxt_free_mem(bp, true);
6782 return rc;
6783 }
6784
6785 /* rtnl_lock held */
6786 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
6787 {
6788 int rc = 0;
6789
6790 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
6791 if (rc) {
6792 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
6793 dev_close(bp->dev);
6794 }
6795 return rc;
6796 }
6797
6798 /* rtnl_lock held, open the NIC half way by allocating all resources, but
6799 * NAPI, IRQ, and TX are not enabled. This is mainly used for offline
6800 * self tests.
6801 */
6802 int bnxt_half_open_nic(struct bnxt *bp)
6803 {
6804 int rc = 0;
6805
6806 rc = bnxt_alloc_mem(bp, false);
6807 if (rc) {
6808 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
6809 goto half_open_err;
6810 }
6811 rc = bnxt_init_nic(bp, false);
6812 if (rc) {
6813 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
6814 goto half_open_err;
6815 }
6816 return 0;
6817
6818 half_open_err:
6819 bnxt_free_skbs(bp);
6820 bnxt_free_mem(bp, false);
6821 dev_close(bp->dev);
6822 return rc;
6823 }
6824
6825 /* rtnl_lock held, this call can only be made after a previous successful
6826 * call to bnxt_half_open_nic().
6827 */
6828 void bnxt_half_close_nic(struct bnxt *bp)
6829 {
6830 bnxt_hwrm_resource_free(bp, false, false);
6831 bnxt_free_skbs(bp);
6832 bnxt_free_mem(bp, false);
6833 }
6834
6835 static int bnxt_open(struct net_device *dev)
6836 {
6837 struct bnxt *bp = netdev_priv(dev);
6838
6839 return __bnxt_open_nic(bp, true, true);
6840 }
6841
6842 static bool bnxt_drv_busy(struct bnxt *bp)
6843 {
6844 return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) ||
6845 test_bit(BNXT_STATE_READ_STATS, &bp->state));
6846 }
6847
6848 static void __bnxt_close_nic(struct bnxt *bp, bool irq_re_init,
6849 bool link_re_init)
6850 {
6851 /* Close the VF-reps before closing PF */
6852 if (BNXT_PF(bp))
6853 bnxt_vf_reps_close(bp);
6854
6855 /* Change device state to avoid TX queue wake up's */
6856 bnxt_tx_disable(bp);
6857
6858 clear_bit(BNXT_STATE_OPEN, &bp->state);
6859 smp_mb__after_atomic();
6860 while (bnxt_drv_busy(bp))
6861 msleep(20);
6862
6863 /* Flush rings and and disable interrupts */
6864 bnxt_shutdown_nic(bp, irq_re_init);
6865
6866 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
6867
6868 bnxt_disable_napi(bp);
6869 del_timer_sync(&bp->timer);
6870 bnxt_free_skbs(bp);
6871
6872 if (irq_re_init) {
6873 bnxt_free_irq(bp);
6874 bnxt_del_napi(bp);
6875 }
6876 bnxt_free_mem(bp, irq_re_init);
6877 }
6878
6879 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
6880 {
6881 int rc = 0;
6882
6883 #ifdef CONFIG_BNXT_SRIOV
6884 if (bp->sriov_cfg) {
6885 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
6886 !bp->sriov_cfg,
6887 BNXT_SRIOV_CFG_WAIT_TMO);
6888 if (rc)
6889 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
6890 }
6891 #endif
6892 __bnxt_close_nic(bp, irq_re_init, link_re_init);
6893 return rc;
6894 }
6895
6896 static int bnxt_close(struct net_device *dev)
6897 {
6898 struct bnxt *bp = netdev_priv(dev);
6899
6900 bnxt_close_nic(bp, true, true);
6901 bnxt_hwrm_shutdown_link(bp);
6902 return 0;
6903 }
6904
6905 /* rtnl_lock held */
6906 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6907 {
6908 switch (cmd) {
6909 case SIOCGMIIPHY:
6910 /* fallthru */
6911 case SIOCGMIIREG: {
6912 if (!netif_running(dev))
6913 return -EAGAIN;
6914
6915 return 0;
6916 }
6917
6918 case SIOCSMIIREG:
6919 if (!netif_running(dev))
6920 return -EAGAIN;
6921
6922 return 0;
6923
6924 default:
6925 /* do nothing */
6926 break;
6927 }
6928 return -EOPNOTSUPP;
6929 }
6930
6931 static void
6932 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6933 {
6934 u32 i;
6935 struct bnxt *bp = netdev_priv(dev);
6936
6937 set_bit(BNXT_STATE_READ_STATS, &bp->state);
6938 /* Make sure bnxt_close_nic() sees that we are reading stats before
6939 * we check the BNXT_STATE_OPEN flag.
6940 */
6941 smp_mb__after_atomic();
6942 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
6943 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
6944 return;
6945 }
6946
6947 /* TODO check if we need to synchronize with bnxt_close path */
6948 for (i = 0; i < bp->cp_nr_rings; i++) {
6949 struct bnxt_napi *bnapi = bp->bnapi[i];
6950 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6951 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
6952
6953 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
6954 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
6955 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
6956
6957 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
6958 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
6959 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
6960
6961 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
6962 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
6963 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
6964
6965 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
6966 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
6967 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
6968
6969 stats->rx_missed_errors +=
6970 le64_to_cpu(hw_stats->rx_discard_pkts);
6971
6972 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
6973
6974 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
6975 }
6976
6977 if (bp->flags & BNXT_FLAG_PORT_STATS) {
6978 struct rx_port_stats *rx = bp->hw_rx_port_stats;
6979 struct tx_port_stats *tx = bp->hw_tx_port_stats;
6980
6981 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames);
6982 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames);
6983 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) +
6984 le64_to_cpu(rx->rx_ovrsz_frames) +
6985 le64_to_cpu(rx->rx_runt_frames);
6986 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) +
6987 le64_to_cpu(rx->rx_jbr_frames);
6988 stats->collisions = le64_to_cpu(tx->tx_total_collisions);
6989 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns);
6990 stats->tx_errors = le64_to_cpu(tx->tx_err);
6991 }
6992 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
6993 }
6994
6995 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
6996 {
6997 struct net_device *dev = bp->dev;
6998 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6999 struct netdev_hw_addr *ha;
7000 u8 *haddr;
7001 int mc_count = 0;
7002 bool update = false;
7003 int off = 0;
7004
7005 netdev_for_each_mc_addr(ha, dev) {
7006 if (mc_count >= BNXT_MAX_MC_ADDRS) {
7007 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
7008 vnic->mc_list_count = 0;
7009 return false;
7010 }
7011 haddr = ha->addr;
7012 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
7013 memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
7014 update = true;
7015 }
7016 off += ETH_ALEN;
7017 mc_count++;
7018 }
7019 if (mc_count)
7020 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
7021
7022 if (mc_count != vnic->mc_list_count) {
7023 vnic->mc_list_count = mc_count;
7024 update = true;
7025 }
7026 return update;
7027 }
7028
7029 static bool bnxt_uc_list_updated(struct bnxt *bp)
7030 {
7031 struct net_device *dev = bp->dev;
7032 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7033 struct netdev_hw_addr *ha;
7034 int off = 0;
7035
7036 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
7037 return true;
7038
7039 netdev_for_each_uc_addr(ha, dev) {
7040 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
7041 return true;
7042
7043 off += ETH_ALEN;
7044 }
7045 return false;
7046 }
7047
7048 static void bnxt_set_rx_mode(struct net_device *dev)
7049 {
7050 struct bnxt *bp = netdev_priv(dev);
7051 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7052 u32 mask = vnic->rx_mask;
7053 bool mc_update = false;
7054 bool uc_update;
7055
7056 if (!netif_running(dev))
7057 return;
7058
7059 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
7060 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
7061 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST);
7062
7063 if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
7064 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
7065
7066 uc_update = bnxt_uc_list_updated(bp);
7067
7068 if (dev->flags & IFF_ALLMULTI) {
7069 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
7070 vnic->mc_list_count = 0;
7071 } else {
7072 mc_update = bnxt_mc_list_updated(bp, &mask);
7073 }
7074
7075 if (mask != vnic->rx_mask || uc_update || mc_update) {
7076 vnic->rx_mask = mask;
7077
7078 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
7079 bnxt_queue_sp_work(bp);
7080 }
7081 }
7082
7083 static int bnxt_cfg_rx_mode(struct bnxt *bp)
7084 {
7085 struct net_device *dev = bp->dev;
7086 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7087 struct netdev_hw_addr *ha;
7088 int i, off = 0, rc;
7089 bool uc_update;
7090
7091 netif_addr_lock_bh(dev);
7092 uc_update = bnxt_uc_list_updated(bp);
7093 netif_addr_unlock_bh(dev);
7094
7095 if (!uc_update)
7096 goto skip_uc;
7097
7098 mutex_lock(&bp->hwrm_cmd_lock);
7099 for (i = 1; i < vnic->uc_filter_count; i++) {
7100 struct hwrm_cfa_l2_filter_free_input req = {0};
7101
7102 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
7103 -1);
7104
7105 req.l2_filter_id = vnic->fw_l2_filter_id[i];
7106
7107 rc = _hwrm_send_message(bp, &req, sizeof(req),
7108 HWRM_CMD_TIMEOUT);
7109 }
7110 mutex_unlock(&bp->hwrm_cmd_lock);
7111
7112 vnic->uc_filter_count = 1;
7113
7114 netif_addr_lock_bh(dev);
7115 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
7116 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
7117 } else {
7118 netdev_for_each_uc_addr(ha, dev) {
7119 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
7120 off += ETH_ALEN;
7121 vnic->uc_filter_count++;
7122 }
7123 }
7124 netif_addr_unlock_bh(dev);
7125
7126 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
7127 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
7128 if (rc) {
7129 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
7130 rc);
7131 vnic->uc_filter_count = i;
7132 return rc;
7133 }
7134 }
7135
7136 skip_uc:
7137 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
7138 if (rc)
7139 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n",
7140 rc);
7141
7142 return rc;
7143 }
7144
7145 /* If the chip and firmware supports RFS */
7146 static bool bnxt_rfs_supported(struct bnxt *bp)
7147 {
7148 if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
7149 return true;
7150 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
7151 return true;
7152 return false;
7153 }
7154
7155 /* If runtime conditions support RFS */
7156 static bool bnxt_rfs_capable(struct bnxt *bp)
7157 {
7158 #ifdef CONFIG_RFS_ACCEL
7159 int vnics, max_vnics, max_rss_ctxs;
7160
7161 if (!(bp->flags & BNXT_FLAG_MSIX_CAP))
7162 return false;
7163
7164 vnics = 1 + bp->rx_nr_rings;
7165 max_vnics = bnxt_get_max_func_vnics(bp);
7166 max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp);
7167
7168 /* RSS contexts not a limiting factor */
7169 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
7170 max_rss_ctxs = max_vnics;
7171 if (vnics > max_vnics || vnics > max_rss_ctxs) {
7172 if (bp->rx_nr_rings > 1)
7173 netdev_warn(bp->dev,
7174 "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
7175 min(max_rss_ctxs - 1, max_vnics - 1));
7176 return false;
7177 }
7178
7179 if (!(bp->flags & BNXT_FLAG_NEW_RM))
7180 return true;
7181
7182 if (vnics == bp->hw_resc.resv_vnics)
7183 return true;
7184
7185 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, vnics);
7186 if (vnics <= bp->hw_resc.resv_vnics)
7187 return true;
7188
7189 netdev_warn(bp->dev, "Unable to reserve resources to support NTUPLE filters.\n");
7190 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 1);
7191 return false;
7192 #else
7193 return false;
7194 #endif
7195 }
7196
7197 static netdev_features_t bnxt_fix_features(struct net_device *dev,
7198 netdev_features_t features)
7199 {
7200 struct bnxt *bp = netdev_priv(dev);
7201
7202 if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp))
7203 features &= ~NETIF_F_NTUPLE;
7204
7205 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
7206 features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
7207
7208 if (!(features & NETIF_F_GRO))
7209 features &= ~NETIF_F_GRO_HW;
7210
7211 if (features & NETIF_F_GRO_HW)
7212 features &= ~NETIF_F_LRO;
7213
7214 /* Both CTAG and STAG VLAN accelaration on the RX side have to be
7215 * turned on or off together.
7216 */
7217 if ((features & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) !=
7218 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) {
7219 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
7220 features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
7221 NETIF_F_HW_VLAN_STAG_RX);
7222 else
7223 features |= NETIF_F_HW_VLAN_CTAG_RX |
7224 NETIF_F_HW_VLAN_STAG_RX;
7225 }
7226 #ifdef CONFIG_BNXT_SRIOV
7227 if (BNXT_VF(bp)) {
7228 if (bp->vf.vlan) {
7229 features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
7230 NETIF_F_HW_VLAN_STAG_RX);
7231 }
7232 }
7233 #endif
7234 return features;
7235 }
7236
7237 static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
7238 {
7239 struct bnxt *bp = netdev_priv(dev);
7240 u32 flags = bp->flags;
7241 u32 changes;
7242 int rc = 0;
7243 bool re_init = false;
7244 bool update_tpa = false;
7245
7246 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
7247 if (features & NETIF_F_GRO_HW)
7248 flags |= BNXT_FLAG_GRO;
7249 else if (features & NETIF_F_LRO)
7250 flags |= BNXT_FLAG_LRO;
7251
7252 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
7253 flags &= ~BNXT_FLAG_TPA;
7254
7255 if (features & NETIF_F_HW_VLAN_CTAG_RX)
7256 flags |= BNXT_FLAG_STRIP_VLAN;
7257
7258 if (features & NETIF_F_NTUPLE)
7259 flags |= BNXT_FLAG_RFS;
7260
7261 changes = flags ^ bp->flags;
7262 if (changes & BNXT_FLAG_TPA) {
7263 update_tpa = true;
7264 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
7265 (flags & BNXT_FLAG_TPA) == 0)
7266 re_init = true;
7267 }
7268
7269 if (changes & ~BNXT_FLAG_TPA)
7270 re_init = true;
7271
7272 if (flags != bp->flags) {
7273 u32 old_flags = bp->flags;
7274
7275 bp->flags = flags;
7276
7277 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
7278 if (update_tpa)
7279 bnxt_set_ring_params(bp);
7280 return rc;
7281 }
7282
7283 if (re_init) {
7284 bnxt_close_nic(bp, false, false);
7285 if (update_tpa)
7286 bnxt_set_ring_params(bp);
7287
7288 return bnxt_open_nic(bp, false, false);
7289 }
7290 if (update_tpa) {
7291 rc = bnxt_set_tpa(bp,
7292 (flags & BNXT_FLAG_TPA) ?
7293 true : false);
7294 if (rc)
7295 bp->flags = old_flags;
7296 }
7297 }
7298 return rc;
7299 }
7300
7301 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
7302 {
7303 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
7304 int i = bnapi->index;
7305
7306 if (!txr)
7307 return;
7308
7309 netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
7310 i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
7311 txr->tx_cons);
7312 }
7313
7314 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
7315 {
7316 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
7317 int i = bnapi->index;
7318
7319 if (!rxr)
7320 return;
7321
7322 netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
7323 i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
7324 rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
7325 rxr->rx_sw_agg_prod);
7326 }
7327
7328 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
7329 {
7330 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
7331 int i = bnapi->index;
7332
7333 netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
7334 i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
7335 }
7336
7337 static void bnxt_dbg_dump_states(struct bnxt *bp)
7338 {
7339 int i;
7340 struct bnxt_napi *bnapi;
7341
7342 for (i = 0; i < bp->cp_nr_rings; i++) {
7343 bnapi = bp->bnapi[i];
7344 if (netif_msg_drv(bp)) {
7345 bnxt_dump_tx_sw_state(bnapi);
7346 bnxt_dump_rx_sw_state(bnapi);
7347 bnxt_dump_cp_sw_state(bnapi);
7348 }
7349 }
7350 }
7351
7352 static void bnxt_reset_task(struct bnxt *bp, bool silent)
7353 {
7354 if (!silent)
7355 bnxt_dbg_dump_states(bp);
7356 if (netif_running(bp->dev)) {
7357 int rc;
7358
7359 if (!silent)
7360 bnxt_ulp_stop(bp);
7361 bnxt_close_nic(bp, false, false);
7362 rc = bnxt_open_nic(bp, false, false);
7363 if (!silent && !rc)
7364 bnxt_ulp_start(bp);
7365 }
7366 }
7367
7368 static void bnxt_tx_timeout(struct net_device *dev)
7369 {
7370 struct bnxt *bp = netdev_priv(dev);
7371
7372 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n");
7373 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
7374 bnxt_queue_sp_work(bp);
7375 }
7376
7377 #ifdef CONFIG_NET_POLL_CONTROLLER
7378 static void bnxt_poll_controller(struct net_device *dev)
7379 {
7380 struct bnxt *bp = netdev_priv(dev);
7381 int i;
7382
7383 /* Only process tx rings/combined rings in netpoll mode. */
7384 for (i = 0; i < bp->tx_nr_rings; i++) {
7385 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
7386
7387 napi_schedule(&txr->bnapi->napi);
7388 }
7389 }
7390 #endif
7391
7392 static void bnxt_timer(struct timer_list *t)
7393 {
7394 struct bnxt *bp = from_timer(bp, t, timer);
7395 struct net_device *dev = bp->dev;
7396
7397 if (!netif_running(dev))
7398 return;
7399
7400 if (atomic_read(&bp->intr_sem) != 0)
7401 goto bnxt_restart_timer;
7402
7403 if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS) &&
7404 bp->stats_coal_ticks) {
7405 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
7406 bnxt_queue_sp_work(bp);
7407 }
7408
7409 if (bnxt_tc_flower_enabled(bp)) {
7410 set_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event);
7411 bnxt_queue_sp_work(bp);
7412 }
7413 bnxt_restart_timer:
7414 mod_timer(&bp->timer, jiffies + bp->current_interval);
7415 }
7416
7417 static void bnxt_rtnl_lock_sp(struct bnxt *bp)
7418 {
7419 /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK
7420 * set. If the device is being closed, bnxt_close() may be holding
7421 * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we
7422 * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
7423 */
7424 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7425 rtnl_lock();
7426 }
7427
7428 static void bnxt_rtnl_unlock_sp(struct bnxt *bp)
7429 {
7430 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7431 rtnl_unlock();
7432 }
7433
7434 /* Only called from bnxt_sp_task() */
7435 static void bnxt_reset(struct bnxt *bp, bool silent)
7436 {
7437 bnxt_rtnl_lock_sp(bp);
7438 if (test_bit(BNXT_STATE_OPEN, &bp->state))
7439 bnxt_reset_task(bp, silent);
7440 bnxt_rtnl_unlock_sp(bp);
7441 }
7442
7443 static void bnxt_cfg_ntp_filters(struct bnxt *);
7444
7445 static void bnxt_sp_task(struct work_struct *work)
7446 {
7447 struct bnxt *bp = container_of(work, struct bnxt, sp_task);
7448
7449 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7450 smp_mb__after_atomic();
7451 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
7452 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7453 return;
7454 }
7455
7456 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
7457 bnxt_cfg_rx_mode(bp);
7458
7459 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
7460 bnxt_cfg_ntp_filters(bp);
7461 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
7462 bnxt_hwrm_exec_fwd_req(bp);
7463 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
7464 bnxt_hwrm_tunnel_dst_port_alloc(
7465 bp, bp->vxlan_port,
7466 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
7467 }
7468 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
7469 bnxt_hwrm_tunnel_dst_port_free(
7470 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
7471 }
7472 if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) {
7473 bnxt_hwrm_tunnel_dst_port_alloc(
7474 bp, bp->nge_port,
7475 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
7476 }
7477 if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) {
7478 bnxt_hwrm_tunnel_dst_port_free(
7479 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
7480 }
7481 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event))
7482 bnxt_hwrm_port_qstats(bp);
7483
7484 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
7485 int rc;
7486
7487 mutex_lock(&bp->link_lock);
7488 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT,
7489 &bp->sp_event))
7490 bnxt_hwrm_phy_qcaps(bp);
7491
7492 rc = bnxt_update_link(bp, true);
7493 mutex_unlock(&bp->link_lock);
7494 if (rc)
7495 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
7496 rc);
7497 }
7498 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) {
7499 mutex_lock(&bp->link_lock);
7500 bnxt_get_port_module_status(bp);
7501 mutex_unlock(&bp->link_lock);
7502 }
7503
7504 if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event))
7505 bnxt_tc_flow_stats_work(bp);
7506
7507 /* These functions below will clear BNXT_STATE_IN_SP_TASK. They
7508 * must be the last functions to be called before exiting.
7509 */
7510 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
7511 bnxt_reset(bp, false);
7512
7513 if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
7514 bnxt_reset(bp, true);
7515
7516 smp_mb__before_atomic();
7517 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7518 }
7519
7520 /* Under rtnl_lock */
7521 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
7522 int tx_xdp)
7523 {
7524 int max_rx, max_tx, tx_sets = 1;
7525 int tx_rings_needed;
7526 int rx_rings = rx;
7527 int cp, vnics, rc;
7528
7529 if (tcs)
7530 tx_sets = tcs;
7531
7532 rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh);
7533 if (rc)
7534 return rc;
7535
7536 if (max_rx < rx)
7537 return -ENOMEM;
7538
7539 tx_rings_needed = tx * tx_sets + tx_xdp;
7540 if (max_tx < tx_rings_needed)
7541 return -ENOMEM;
7542
7543 vnics = 1;
7544 if (bp->flags & BNXT_FLAG_RFS)
7545 vnics += rx_rings;
7546
7547 if (bp->flags & BNXT_FLAG_AGG_RINGS)
7548 rx_rings <<= 1;
7549 cp = sh ? max_t(int, tx_rings_needed, rx) : tx_rings_needed + rx;
7550 return bnxt_hwrm_check_rings(bp, tx_rings_needed, rx_rings, rx, cp,
7551 vnics);
7552 }
7553
7554 static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev)
7555 {
7556 if (bp->bar2) {
7557 pci_iounmap(pdev, bp->bar2);
7558 bp->bar2 = NULL;
7559 }
7560
7561 if (bp->bar1) {
7562 pci_iounmap(pdev, bp->bar1);
7563 bp->bar1 = NULL;
7564 }
7565
7566 if (bp->bar0) {
7567 pci_iounmap(pdev, bp->bar0);
7568 bp->bar0 = NULL;
7569 }
7570 }
7571
7572 static void bnxt_cleanup_pci(struct bnxt *bp)
7573 {
7574 bnxt_unmap_bars(bp, bp->pdev);
7575 pci_release_regions(bp->pdev);
7576 pci_disable_device(bp->pdev);
7577 }
7578
7579 static void bnxt_init_dflt_coal(struct bnxt *bp)
7580 {
7581 struct bnxt_coal *coal;
7582
7583 /* Tick values in micro seconds.
7584 * 1 coal_buf x bufs_per_record = 1 completion record.
7585 */
7586 coal = &bp->rx_coal;
7587 coal->coal_ticks = 14;
7588 coal->coal_bufs = 30;
7589 coal->coal_ticks_irq = 1;
7590 coal->coal_bufs_irq = 2;
7591 coal->idle_thresh = 25;
7592 coal->bufs_per_record = 2;
7593 coal->budget = 64; /* NAPI budget */
7594
7595 coal = &bp->tx_coal;
7596 coal->coal_ticks = 28;
7597 coal->coal_bufs = 30;
7598 coal->coal_ticks_irq = 2;
7599 coal->coal_bufs_irq = 2;
7600 coal->bufs_per_record = 1;
7601
7602 bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS;
7603 }
7604
7605 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
7606 {
7607 int rc;
7608 struct bnxt *bp = netdev_priv(dev);
7609
7610 SET_NETDEV_DEV(dev, &pdev->dev);
7611
7612 /* enable device (incl. PCI PM wakeup), and bus-mastering */
7613 rc = pci_enable_device(pdev);
7614 if (rc) {
7615 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
7616 goto init_err;
7617 }
7618
7619 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
7620 dev_err(&pdev->dev,
7621 "Cannot find PCI device base address, aborting\n");
7622 rc = -ENODEV;
7623 goto init_err_disable;
7624 }
7625
7626 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7627 if (rc) {
7628 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
7629 goto init_err_disable;
7630 }
7631
7632 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
7633 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
7634 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
7635 goto init_err_disable;
7636 }
7637
7638 pci_set_master(pdev);
7639
7640 bp->dev = dev;
7641 bp->pdev = pdev;
7642
7643 bp->bar0 = pci_ioremap_bar(pdev, 0);
7644 if (!bp->bar0) {
7645 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
7646 rc = -ENOMEM;
7647 goto init_err_release;
7648 }
7649
7650 bp->bar1 = pci_ioremap_bar(pdev, 2);
7651 if (!bp->bar1) {
7652 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
7653 rc = -ENOMEM;
7654 goto init_err_release;
7655 }
7656
7657 bp->bar2 = pci_ioremap_bar(pdev, 4);
7658 if (!bp->bar2) {
7659 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
7660 rc = -ENOMEM;
7661 goto init_err_release;
7662 }
7663
7664 pci_enable_pcie_error_reporting(pdev);
7665
7666 INIT_WORK(&bp->sp_task, bnxt_sp_task);
7667
7668 spin_lock_init(&bp->ntp_fltr_lock);
7669
7670 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
7671 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
7672
7673 bnxt_init_dflt_coal(bp);
7674
7675 timer_setup(&bp->timer, bnxt_timer, 0);
7676 bp->current_interval = BNXT_TIMER_INTERVAL;
7677
7678 clear_bit(BNXT_STATE_OPEN, &bp->state);
7679 return 0;
7680
7681 init_err_release:
7682 bnxt_unmap_bars(bp, pdev);
7683 pci_release_regions(pdev);
7684
7685 init_err_disable:
7686 pci_disable_device(pdev);
7687
7688 init_err:
7689 return rc;
7690 }
7691
7692 /* rtnl_lock held */
7693 static int bnxt_change_mac_addr(struct net_device *dev, void *p)
7694 {
7695 struct sockaddr *addr = p;
7696 struct bnxt *bp = netdev_priv(dev);
7697 int rc = 0;
7698
7699 if (!is_valid_ether_addr(addr->sa_data))
7700 return -EADDRNOTAVAIL;
7701
7702 if (ether_addr_equal(addr->sa_data, dev->dev_addr))
7703 return 0;
7704
7705 rc = bnxt_approve_mac(bp, addr->sa_data);
7706 if (rc)
7707 return rc;
7708
7709 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7710 if (netif_running(dev)) {
7711 bnxt_close_nic(bp, false, false);
7712 rc = bnxt_open_nic(bp, false, false);
7713 }
7714
7715 return rc;
7716 }
7717
7718 /* rtnl_lock held */
7719 static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
7720 {
7721 struct bnxt *bp = netdev_priv(dev);
7722
7723 if (netif_running(dev))
7724 bnxt_close_nic(bp, false, false);
7725
7726 dev->mtu = new_mtu;
7727 bnxt_set_ring_params(bp);
7728
7729 if (netif_running(dev))
7730 return bnxt_open_nic(bp, false, false);
7731
7732 return 0;
7733 }
7734
7735 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc)
7736 {
7737 struct bnxt *bp = netdev_priv(dev);
7738 bool sh = false;
7739 int rc;
7740
7741 if (tc > bp->max_tc) {
7742 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n",
7743 tc, bp->max_tc);
7744 return -EINVAL;
7745 }
7746
7747 if (netdev_get_num_tc(dev) == tc)
7748 return 0;
7749
7750 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
7751 sh = true;
7752
7753 rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings,
7754 sh, tc, bp->tx_nr_rings_xdp);
7755 if (rc)
7756 return rc;
7757
7758 /* Needs to close the device and do hw resource re-allocations */
7759 if (netif_running(bp->dev))
7760 bnxt_close_nic(bp, true, false);
7761
7762 if (tc) {
7763 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
7764 netdev_set_num_tc(dev, tc);
7765 } else {
7766 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
7767 netdev_reset_tc(dev);
7768 }
7769 bp->tx_nr_rings += bp->tx_nr_rings_xdp;
7770 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
7771 bp->tx_nr_rings + bp->rx_nr_rings;
7772 bp->num_stat_ctxs = bp->cp_nr_rings;
7773
7774 if (netif_running(bp->dev))
7775 return bnxt_open_nic(bp, true, false);
7776
7777 return 0;
7778 }
7779
7780 static int bnxt_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
7781 void *cb_priv)
7782 {
7783 struct bnxt *bp = cb_priv;
7784
7785 if (!bnxt_tc_flower_enabled(bp) ||
7786 !tc_cls_can_offload_and_chain0(bp->dev, type_data))
7787 return -EOPNOTSUPP;
7788
7789 switch (type) {
7790 case TC_SETUP_CLSFLOWER:
7791 return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, type_data);
7792 default:
7793 return -EOPNOTSUPP;
7794 }
7795 }
7796
7797 static int bnxt_setup_tc_block(struct net_device *dev,
7798 struct tc_block_offload *f)
7799 {
7800 struct bnxt *bp = netdev_priv(dev);
7801
7802 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
7803 return -EOPNOTSUPP;
7804
7805 switch (f->command) {
7806 case TC_BLOCK_BIND:
7807 return tcf_block_cb_register(f->block, bnxt_setup_tc_block_cb,
7808 bp, bp);
7809 case TC_BLOCK_UNBIND:
7810 tcf_block_cb_unregister(f->block, bnxt_setup_tc_block_cb, bp);
7811 return 0;
7812 default:
7813 return -EOPNOTSUPP;
7814 }
7815 }
7816
7817 static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type,
7818 void *type_data)
7819 {
7820 switch (type) {
7821 case TC_SETUP_BLOCK:
7822 return bnxt_setup_tc_block(dev, type_data);
7823 case TC_SETUP_QDISC_MQPRIO: {
7824 struct tc_mqprio_qopt *mqprio = type_data;
7825
7826 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
7827
7828 return bnxt_setup_mq_tc(dev, mqprio->num_tc);
7829 }
7830 default:
7831 return -EOPNOTSUPP;
7832 }
7833 }
7834
7835 #ifdef CONFIG_RFS_ACCEL
7836 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
7837 struct bnxt_ntuple_filter *f2)
7838 {
7839 struct flow_keys *keys1 = &f1->fkeys;
7840 struct flow_keys *keys2 = &f2->fkeys;
7841
7842 if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
7843 keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
7844 keys1->ports.ports == keys2->ports.ports &&
7845 keys1->basic.ip_proto == keys2->basic.ip_proto &&
7846 keys1->basic.n_proto == keys2->basic.n_proto &&
7847 keys1->control.flags == keys2->control.flags &&
7848 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) &&
7849 ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr))
7850 return true;
7851
7852 return false;
7853 }
7854
7855 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
7856 u16 rxq_index, u32 flow_id)
7857 {
7858 struct bnxt *bp = netdev_priv(dev);
7859 struct bnxt_ntuple_filter *fltr, *new_fltr;
7860 struct flow_keys *fkeys;
7861 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
7862 int rc = 0, idx, bit_id, l2_idx = 0;
7863 struct hlist_head *head;
7864
7865 if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) {
7866 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7867 int off = 0, j;
7868
7869 netif_addr_lock_bh(dev);
7870 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) {
7871 if (ether_addr_equal(eth->h_dest,
7872 vnic->uc_list + off)) {
7873 l2_idx = j + 1;
7874 break;
7875 }
7876 }
7877 netif_addr_unlock_bh(dev);
7878 if (!l2_idx)
7879 return -EINVAL;
7880 }
7881 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
7882 if (!new_fltr)
7883 return -ENOMEM;
7884
7885 fkeys = &new_fltr->fkeys;
7886 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
7887 rc = -EPROTONOSUPPORT;
7888 goto err_free;
7889 }
7890
7891 if ((fkeys->basic.n_proto != htons(ETH_P_IP) &&
7892 fkeys->basic.n_proto != htons(ETH_P_IPV6)) ||
7893 ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
7894 (fkeys->basic.ip_proto != IPPROTO_UDP))) {
7895 rc = -EPROTONOSUPPORT;
7896 goto err_free;
7897 }
7898 if (fkeys->basic.n_proto == htons(ETH_P_IPV6) &&
7899 bp->hwrm_spec_code < 0x10601) {
7900 rc = -EPROTONOSUPPORT;
7901 goto err_free;
7902 }
7903 if ((fkeys->control.flags & FLOW_DIS_ENCAPSULATION) &&
7904 bp->hwrm_spec_code < 0x10601) {
7905 rc = -EPROTONOSUPPORT;
7906 goto err_free;
7907 }
7908
7909 memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN);
7910 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
7911
7912 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
7913 head = &bp->ntp_fltr_hash_tbl[idx];
7914 rcu_read_lock();
7915 hlist_for_each_entry_rcu(fltr, head, hash) {
7916 if (bnxt_fltr_match(fltr, new_fltr)) {
7917 rcu_read_unlock();
7918 rc = 0;
7919 goto err_free;
7920 }
7921 }
7922 rcu_read_unlock();
7923
7924 spin_lock_bh(&bp->ntp_fltr_lock);
7925 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
7926 BNXT_NTP_FLTR_MAX_FLTR, 0);
7927 if (bit_id < 0) {
7928 spin_unlock_bh(&bp->ntp_fltr_lock);
7929 rc = -ENOMEM;
7930 goto err_free;
7931 }
7932
7933 new_fltr->sw_id = (u16)bit_id;
7934 new_fltr->flow_id = flow_id;
7935 new_fltr->l2_fltr_idx = l2_idx;
7936 new_fltr->rxq = rxq_index;
7937 hlist_add_head_rcu(&new_fltr->hash, head);
7938 bp->ntp_fltr_count++;
7939 spin_unlock_bh(&bp->ntp_fltr_lock);
7940
7941 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
7942 bnxt_queue_sp_work(bp);
7943
7944 return new_fltr->sw_id;
7945
7946 err_free:
7947 kfree(new_fltr);
7948 return rc;
7949 }
7950
7951 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
7952 {
7953 int i;
7954
7955 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
7956 struct hlist_head *head;
7957 struct hlist_node *tmp;
7958 struct bnxt_ntuple_filter *fltr;
7959 int rc;
7960
7961 head = &bp->ntp_fltr_hash_tbl[i];
7962 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
7963 bool del = false;
7964
7965 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
7966 if (rps_may_expire_flow(bp->dev, fltr->rxq,
7967 fltr->flow_id,
7968 fltr->sw_id)) {
7969 bnxt_hwrm_cfa_ntuple_filter_free(bp,
7970 fltr);
7971 del = true;
7972 }
7973 } else {
7974 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
7975 fltr);
7976 if (rc)
7977 del = true;
7978 else
7979 set_bit(BNXT_FLTR_VALID, &fltr->state);
7980 }
7981
7982 if (del) {
7983 spin_lock_bh(&bp->ntp_fltr_lock);
7984 hlist_del_rcu(&fltr->hash);
7985 bp->ntp_fltr_count--;
7986 spin_unlock_bh(&bp->ntp_fltr_lock);
7987 synchronize_rcu();
7988 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
7989 kfree(fltr);
7990 }
7991 }
7992 }
7993 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
7994 netdev_info(bp->dev, "Receive PF driver unload event!");
7995 }
7996
7997 #else
7998
7999 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
8000 {
8001 }
8002
8003 #endif /* CONFIG_RFS_ACCEL */
8004
8005 static void bnxt_udp_tunnel_add(struct net_device *dev,
8006 struct udp_tunnel_info *ti)
8007 {
8008 struct bnxt *bp = netdev_priv(dev);
8009
8010 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
8011 return;
8012
8013 if (!netif_running(dev))
8014 return;
8015
8016 switch (ti->type) {
8017 case UDP_TUNNEL_TYPE_VXLAN:
8018 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port)
8019 return;
8020
8021 bp->vxlan_port_cnt++;
8022 if (bp->vxlan_port_cnt == 1) {
8023 bp->vxlan_port = ti->port;
8024 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
8025 bnxt_queue_sp_work(bp);
8026 }
8027 break;
8028 case UDP_TUNNEL_TYPE_GENEVE:
8029 if (bp->nge_port_cnt && bp->nge_port != ti->port)
8030 return;
8031
8032 bp->nge_port_cnt++;
8033 if (bp->nge_port_cnt == 1) {
8034 bp->nge_port = ti->port;
8035 set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event);
8036 }
8037 break;
8038 default:
8039 return;
8040 }
8041
8042 bnxt_queue_sp_work(bp);
8043 }
8044
8045 static void bnxt_udp_tunnel_del(struct net_device *dev,
8046 struct udp_tunnel_info *ti)
8047 {
8048 struct bnxt *bp = netdev_priv(dev);
8049
8050 if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
8051 return;
8052
8053 if (!netif_running(dev))
8054 return;
8055
8056 switch (ti->type) {
8057 case UDP_TUNNEL_TYPE_VXLAN:
8058 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port)
8059 return;
8060 bp->vxlan_port_cnt--;
8061
8062 if (bp->vxlan_port_cnt != 0)
8063 return;
8064
8065 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
8066 break;
8067 case UDP_TUNNEL_TYPE_GENEVE:
8068 if (!bp->nge_port_cnt || bp->nge_port != ti->port)
8069 return;
8070 bp->nge_port_cnt--;
8071
8072 if (bp->nge_port_cnt != 0)
8073 return;
8074
8075 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event);
8076 break;
8077 default:
8078 return;
8079 }
8080
8081 bnxt_queue_sp_work(bp);
8082 }
8083
8084 static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
8085 struct net_device *dev, u32 filter_mask,
8086 int nlflags)
8087 {
8088 struct bnxt *bp = netdev_priv(dev);
8089
8090 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0,
8091 nlflags, filter_mask, NULL);
8092 }
8093
8094 static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
8095 u16 flags)
8096 {
8097 struct bnxt *bp = netdev_priv(dev);
8098 struct nlattr *attr, *br_spec;
8099 int rem, rc = 0;
8100
8101 if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp))
8102 return -EOPNOTSUPP;
8103
8104 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
8105 if (!br_spec)
8106 return -EINVAL;
8107
8108 nla_for_each_nested(attr, br_spec, rem) {
8109 u16 mode;
8110
8111 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8112 continue;
8113
8114 if (nla_len(attr) < sizeof(mode))
8115 return -EINVAL;
8116
8117 mode = nla_get_u16(attr);
8118 if (mode == bp->br_mode)
8119 break;
8120
8121 rc = bnxt_hwrm_set_br_mode(bp, mode);
8122 if (!rc)
8123 bp->br_mode = mode;
8124 break;
8125 }
8126 return rc;
8127 }
8128
8129 static int bnxt_get_phys_port_name(struct net_device *dev, char *buf,
8130 size_t len)
8131 {
8132 struct bnxt *bp = netdev_priv(dev);
8133 int rc;
8134
8135 /* The PF and it's VF-reps only support the switchdev framework */
8136 if (!BNXT_PF(bp))
8137 return -EOPNOTSUPP;
8138
8139 rc = snprintf(buf, len, "p%d", bp->pf.port_id);
8140
8141 if (rc >= len)
8142 return -EOPNOTSUPP;
8143 return 0;
8144 }
8145
8146 int bnxt_port_attr_get(struct bnxt *bp, struct switchdev_attr *attr)
8147 {
8148 if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV)
8149 return -EOPNOTSUPP;
8150
8151 /* The PF and it's VF-reps only support the switchdev framework */
8152 if (!BNXT_PF(bp))
8153 return -EOPNOTSUPP;
8154
8155 switch (attr->id) {
8156 case SWITCHDEV_ATTR_ID_PORT_PARENT_ID:
8157 attr->u.ppid.id_len = sizeof(bp->switch_id);
8158 memcpy(attr->u.ppid.id, bp->switch_id, attr->u.ppid.id_len);
8159 break;
8160 default:
8161 return -EOPNOTSUPP;
8162 }
8163 return 0;
8164 }
8165
8166 static int bnxt_swdev_port_attr_get(struct net_device *dev,
8167 struct switchdev_attr *attr)
8168 {
8169 return bnxt_port_attr_get(netdev_priv(dev), attr);
8170 }
8171
8172 static const struct switchdev_ops bnxt_switchdev_ops = {
8173 .switchdev_port_attr_get = bnxt_swdev_port_attr_get
8174 };
8175
8176 static const struct net_device_ops bnxt_netdev_ops = {
8177 .ndo_open = bnxt_open,
8178 .ndo_start_xmit = bnxt_start_xmit,
8179 .ndo_stop = bnxt_close,
8180 .ndo_get_stats64 = bnxt_get_stats64,
8181 .ndo_set_rx_mode = bnxt_set_rx_mode,
8182 .ndo_do_ioctl = bnxt_ioctl,
8183 .ndo_validate_addr = eth_validate_addr,
8184 .ndo_set_mac_address = bnxt_change_mac_addr,
8185 .ndo_change_mtu = bnxt_change_mtu,
8186 .ndo_fix_features = bnxt_fix_features,
8187 .ndo_set_features = bnxt_set_features,
8188 .ndo_tx_timeout = bnxt_tx_timeout,
8189 #ifdef CONFIG_BNXT_SRIOV
8190 .ndo_get_vf_config = bnxt_get_vf_config,
8191 .ndo_set_vf_mac = bnxt_set_vf_mac,
8192 .ndo_set_vf_vlan = bnxt_set_vf_vlan,
8193 .ndo_set_vf_rate = bnxt_set_vf_bw,
8194 .ndo_set_vf_link_state = bnxt_set_vf_link_state,
8195 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk,
8196 #endif
8197 #ifdef CONFIG_NET_POLL_CONTROLLER
8198 .ndo_poll_controller = bnxt_poll_controller,
8199 #endif
8200 .ndo_setup_tc = bnxt_setup_tc,
8201 #ifdef CONFIG_RFS_ACCEL
8202 .ndo_rx_flow_steer = bnxt_rx_flow_steer,
8203 #endif
8204 .ndo_udp_tunnel_add = bnxt_udp_tunnel_add,
8205 .ndo_udp_tunnel_del = bnxt_udp_tunnel_del,
8206 .ndo_bpf = bnxt_xdp,
8207 .ndo_bridge_getlink = bnxt_bridge_getlink,
8208 .ndo_bridge_setlink = bnxt_bridge_setlink,
8209 .ndo_get_phys_port_name = bnxt_get_phys_port_name
8210 };
8211
8212 static void bnxt_remove_one(struct pci_dev *pdev)
8213 {
8214 struct net_device *dev = pci_get_drvdata(pdev);
8215 struct bnxt *bp = netdev_priv(dev);
8216
8217 if (BNXT_PF(bp)) {
8218 bnxt_sriov_disable(bp);
8219 bnxt_dl_unregister(bp);
8220 }
8221
8222 pci_disable_pcie_error_reporting(pdev);
8223 unregister_netdev(dev);
8224 bnxt_shutdown_tc(bp);
8225 bnxt_cancel_sp_work(bp);
8226 bp->sp_event = 0;
8227
8228 bnxt_clear_int_mode(bp);
8229 bnxt_hwrm_func_drv_unrgtr(bp);
8230 bnxt_free_hwrm_resources(bp);
8231 bnxt_free_hwrm_short_cmd_req(bp);
8232 bnxt_ethtool_free(bp);
8233 bnxt_dcb_free(bp);
8234 kfree(bp->edev);
8235 bp->edev = NULL;
8236 bnxt_cleanup_pci(bp);
8237 free_netdev(dev);
8238 }
8239
8240 static int bnxt_probe_phy(struct bnxt *bp)
8241 {
8242 int rc = 0;
8243 struct bnxt_link_info *link_info = &bp->link_info;
8244
8245 rc = bnxt_hwrm_phy_qcaps(bp);
8246 if (rc) {
8247 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
8248 rc);
8249 return rc;
8250 }
8251 mutex_init(&bp->link_lock);
8252
8253 rc = bnxt_update_link(bp, false);
8254 if (rc) {
8255 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
8256 rc);
8257 return rc;
8258 }
8259
8260 /* Older firmware does not have supported_auto_speeds, so assume
8261 * that all supported speeds can be autonegotiated.
8262 */
8263 if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
8264 link_info->support_auto_speeds = link_info->support_speeds;
8265
8266 /*initialize the ethool setting copy with NVM settings */
8267 if (BNXT_AUTO_MODE(link_info->auto_mode)) {
8268 link_info->autoneg = BNXT_AUTONEG_SPEED;
8269 if (bp->hwrm_spec_code >= 0x10201) {
8270 if (link_info->auto_pause_setting &
8271 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
8272 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
8273 } else {
8274 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
8275 }
8276 link_info->advertising = link_info->auto_link_speeds;
8277 } else {
8278 link_info->req_link_speed = link_info->force_link_speed;
8279 link_info->req_duplex = link_info->duplex_setting;
8280 }
8281 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
8282 link_info->req_flow_ctrl =
8283 link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
8284 else
8285 link_info->req_flow_ctrl = link_info->force_pause_setting;
8286 return rc;
8287 }
8288
8289 static int bnxt_get_max_irq(struct pci_dev *pdev)
8290 {
8291 u16 ctrl;
8292
8293 if (!pdev->msix_cap)
8294 return 1;
8295
8296 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
8297 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
8298 }
8299
8300 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
8301 int *max_cp)
8302 {
8303 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
8304 int max_ring_grps = 0;
8305
8306 *max_tx = hw_resc->max_tx_rings;
8307 *max_rx = hw_resc->max_rx_rings;
8308 *max_cp = min_t(int, hw_resc->max_irqs, hw_resc->max_cp_rings);
8309 *max_cp = min_t(int, *max_cp, hw_resc->max_stat_ctxs);
8310 max_ring_grps = hw_resc->max_hw_ring_grps;
8311 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) {
8312 *max_cp -= 1;
8313 *max_rx -= 2;
8314 }
8315 if (bp->flags & BNXT_FLAG_AGG_RINGS)
8316 *max_rx >>= 1;
8317 *max_rx = min_t(int, *max_rx, max_ring_grps);
8318 }
8319
8320 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
8321 {
8322 int rx, tx, cp;
8323
8324 _bnxt_get_max_rings(bp, &rx, &tx, &cp);
8325 if (!rx || !tx || !cp)
8326 return -ENOMEM;
8327
8328 *max_rx = rx;
8329 *max_tx = tx;
8330 return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
8331 }
8332
8333 static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx,
8334 bool shared)
8335 {
8336 int rc;
8337
8338 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
8339 if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) {
8340 /* Not enough rings, try disabling agg rings. */
8341 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
8342 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
8343 if (rc)
8344 return rc;
8345 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
8346 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
8347 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
8348 bnxt_set_ring_params(bp);
8349 }
8350
8351 if (bp->flags & BNXT_FLAG_ROCE_CAP) {
8352 int max_cp, max_stat, max_irq;
8353
8354 /* Reserve minimum resources for RoCE */
8355 max_cp = bnxt_get_max_func_cp_rings(bp);
8356 max_stat = bnxt_get_max_func_stat_ctxs(bp);
8357 max_irq = bnxt_get_max_func_irqs(bp);
8358 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS ||
8359 max_irq <= BNXT_MIN_ROCE_CP_RINGS ||
8360 max_stat <= BNXT_MIN_ROCE_STAT_CTXS)
8361 return 0;
8362
8363 max_cp -= BNXT_MIN_ROCE_CP_RINGS;
8364 max_irq -= BNXT_MIN_ROCE_CP_RINGS;
8365 max_stat -= BNXT_MIN_ROCE_STAT_CTXS;
8366 max_cp = min_t(int, max_cp, max_irq);
8367 max_cp = min_t(int, max_cp, max_stat);
8368 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared);
8369 if (rc)
8370 rc = 0;
8371 }
8372 return rc;
8373 }
8374
8375 /* In initial default shared ring setting, each shared ring must have a
8376 * RX/TX ring pair.
8377 */
8378 static void bnxt_trim_dflt_sh_rings(struct bnxt *bp)
8379 {
8380 bp->cp_nr_rings = min_t(int, bp->tx_nr_rings_per_tc, bp->rx_nr_rings);
8381 bp->rx_nr_rings = bp->cp_nr_rings;
8382 bp->tx_nr_rings_per_tc = bp->cp_nr_rings;
8383 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
8384 }
8385
8386 static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh)
8387 {
8388 int dflt_rings, max_rx_rings, max_tx_rings, rc;
8389
8390 if (sh)
8391 bp->flags |= BNXT_FLAG_SHARED_RINGS;
8392 dflt_rings = netif_get_num_default_rss_queues();
8393 /* Reduce default rings to reduce memory usage on multi-port cards */
8394 if (bp->port_count > 1)
8395 dflt_rings = min_t(int, dflt_rings, 4);
8396 rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh);
8397 if (rc)
8398 return rc;
8399 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
8400 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
8401 if (sh)
8402 bnxt_trim_dflt_sh_rings(bp);
8403 else
8404 bp->cp_nr_rings = bp->tx_nr_rings_per_tc + bp->rx_nr_rings;
8405 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
8406
8407 rc = __bnxt_reserve_rings(bp);
8408 if (rc)
8409 netdev_warn(bp->dev, "Unable to reserve tx rings\n");
8410 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
8411 if (sh)
8412 bnxt_trim_dflt_sh_rings(bp);
8413
8414 /* Rings may have been trimmed, re-reserve the trimmed rings. */
8415 if (bnxt_need_reserve_rings(bp)) {
8416 rc = __bnxt_reserve_rings(bp);
8417 if (rc)
8418 netdev_warn(bp->dev, "2nd rings reservation failed.\n");
8419 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
8420 }
8421 bp->num_stat_ctxs = bp->cp_nr_rings;
8422 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
8423 bp->rx_nr_rings++;
8424 bp->cp_nr_rings++;
8425 }
8426 return rc;
8427 }
8428
8429 int bnxt_restore_pf_fw_resources(struct bnxt *bp)
8430 {
8431 int rc;
8432
8433 ASSERT_RTNL();
8434 if (bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP))
8435 return 0;
8436
8437 bnxt_hwrm_func_qcaps(bp);
8438
8439 if (netif_running(bp->dev))
8440 __bnxt_close_nic(bp, true, false);
8441
8442 bnxt_clear_int_mode(bp);
8443 rc = bnxt_init_int_mode(bp);
8444
8445 if (netif_running(bp->dev)) {
8446 if (rc)
8447 dev_close(bp->dev);
8448 else
8449 rc = bnxt_open_nic(bp, true, false);
8450 }
8451
8452 return rc;
8453 }
8454
8455 static int bnxt_init_mac_addr(struct bnxt *bp)
8456 {
8457 int rc = 0;
8458
8459 if (BNXT_PF(bp)) {
8460 memcpy(bp->dev->dev_addr, bp->pf.mac_addr, ETH_ALEN);
8461 } else {
8462 #ifdef CONFIG_BNXT_SRIOV
8463 struct bnxt_vf_info *vf = &bp->vf;
8464
8465 if (is_valid_ether_addr(vf->mac_addr)) {
8466 /* overwrite netdev dev_addr with admin VF MAC */
8467 memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
8468 } else {
8469 eth_hw_addr_random(bp->dev);
8470 rc = bnxt_approve_mac(bp, bp->dev->dev_addr);
8471 }
8472 #endif
8473 }
8474 return rc;
8475 }
8476
8477 static void bnxt_parse_log_pcie_link(struct bnxt *bp)
8478 {
8479 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
8480 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
8481
8482 if (pcie_get_minimum_link(pci_physfn(bp->pdev), &speed, &width) ||
8483 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
8484 netdev_info(bp->dev, "Failed to determine PCIe Link Info\n");
8485 else
8486 netdev_info(bp->dev, "PCIe: Speed %s Width x%d\n",
8487 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
8488 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
8489 speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
8490 "Unknown", width);
8491 }
8492
8493 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8494 {
8495 static int version_printed;
8496 struct net_device *dev;
8497 struct bnxt *bp;
8498 int rc, max_irqs;
8499
8500 if (pci_is_bridge(pdev))
8501 return -ENODEV;
8502
8503 if (version_printed++ == 0)
8504 pr_info("%s", version);
8505
8506 max_irqs = bnxt_get_max_irq(pdev);
8507 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
8508 if (!dev)
8509 return -ENOMEM;
8510
8511 bp = netdev_priv(dev);
8512
8513 if (bnxt_vf_pciid(ent->driver_data))
8514 bp->flags |= BNXT_FLAG_VF;
8515
8516 if (pdev->msix_cap)
8517 bp->flags |= BNXT_FLAG_MSIX_CAP;
8518
8519 rc = bnxt_init_board(pdev, dev);
8520 if (rc < 0)
8521 goto init_err_free;
8522
8523 dev->netdev_ops = &bnxt_netdev_ops;
8524 dev->watchdog_timeo = BNXT_TX_TIMEOUT;
8525 dev->ethtool_ops = &bnxt_ethtool_ops;
8526 SWITCHDEV_SET_OPS(dev, &bnxt_switchdev_ops);
8527 pci_set_drvdata(pdev, dev);
8528
8529 rc = bnxt_alloc_hwrm_resources(bp);
8530 if (rc)
8531 goto init_err_pci_clean;
8532
8533 mutex_init(&bp->hwrm_cmd_lock);
8534 rc = bnxt_hwrm_ver_get(bp);
8535 if (rc)
8536 goto init_err_pci_clean;
8537
8538 if (bp->flags & BNXT_FLAG_SHORT_CMD) {
8539 rc = bnxt_alloc_hwrm_short_cmd_req(bp);
8540 if (rc)
8541 goto init_err_pci_clean;
8542 }
8543
8544 rc = bnxt_hwrm_func_reset(bp);
8545 if (rc)
8546 goto init_err_pci_clean;
8547
8548 bnxt_hwrm_fw_set_time(bp);
8549
8550 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
8551 NETIF_F_TSO | NETIF_F_TSO6 |
8552 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
8553 NETIF_F_GSO_IPXIP4 |
8554 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
8555 NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
8556 NETIF_F_RXCSUM | NETIF_F_GRO;
8557
8558 if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
8559 dev->hw_features |= NETIF_F_LRO;
8560
8561 dev->hw_enc_features =
8562 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
8563 NETIF_F_TSO | NETIF_F_TSO6 |
8564 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
8565 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
8566 NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;
8567 dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
8568 NETIF_F_GSO_GRE_CSUM;
8569 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
8570 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
8571 NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
8572 if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
8573 dev->hw_features |= NETIF_F_GRO_HW;
8574 dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
8575 if (dev->features & NETIF_F_GRO_HW)
8576 dev->features &= ~NETIF_F_LRO;
8577 dev->priv_flags |= IFF_UNICAST_FLT;
8578
8579 #ifdef CONFIG_BNXT_SRIOV
8580 init_waitqueue_head(&bp->sriov_cfg_wait);
8581 mutex_init(&bp->sriov_lock);
8582 #endif
8583 bp->gro_func = bnxt_gro_func_5730x;
8584 if (BNXT_CHIP_P4_PLUS(bp))
8585 bp->gro_func = bnxt_gro_func_5731x;
8586 else
8587 bp->flags |= BNXT_FLAG_DOUBLE_DB;
8588
8589 rc = bnxt_hwrm_func_drv_rgtr(bp);
8590 if (rc)
8591 goto init_err_pci_clean;
8592
8593 rc = bnxt_hwrm_func_rgtr_async_events(bp, NULL, 0);
8594 if (rc)
8595 goto init_err_pci_clean;
8596
8597 bp->ulp_probe = bnxt_ulp_probe;
8598
8599 /* Get the MAX capabilities for this function */
8600 rc = bnxt_hwrm_func_qcaps(bp);
8601 if (rc) {
8602 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
8603 rc);
8604 rc = -1;
8605 goto init_err_pci_clean;
8606 }
8607 rc = bnxt_init_mac_addr(bp);
8608 if (rc) {
8609 dev_err(&pdev->dev, "Unable to initialize mac address.\n");
8610 rc = -EADDRNOTAVAIL;
8611 goto init_err_pci_clean;
8612 }
8613 rc = bnxt_hwrm_queue_qportcfg(bp);
8614 if (rc) {
8615 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
8616 rc);
8617 rc = -1;
8618 goto init_err_pci_clean;
8619 }
8620
8621 bnxt_hwrm_func_qcfg(bp);
8622 bnxt_hwrm_port_led_qcaps(bp);
8623 bnxt_ethtool_init(bp);
8624 bnxt_dcb_init(bp);
8625
8626 /* MTU range: 60 - FW defined max */
8627 dev->min_mtu = ETH_ZLEN;
8628 dev->max_mtu = bp->max_mtu;
8629
8630 rc = bnxt_probe_phy(bp);
8631 if (rc)
8632 goto init_err_pci_clean;
8633
8634 bnxt_set_rx_skb_mode(bp, false);
8635 bnxt_set_tpa_flags(bp);
8636 bnxt_set_ring_params(bp);
8637 bnxt_set_max_func_irqs(bp, max_irqs);
8638 rc = bnxt_set_dflt_rings(bp, true);
8639 if (rc) {
8640 netdev_err(bp->dev, "Not enough rings available.\n");
8641 rc = -ENOMEM;
8642 goto init_err_pci_clean;
8643 }
8644
8645 /* Default RSS hash cfg. */
8646 bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 |
8647 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 |
8648 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |
8649 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
8650 if (BNXT_CHIP_P4_PLUS(bp) && bp->hwrm_spec_code >= 0x10501) {
8651 bp->flags |= BNXT_FLAG_UDP_RSS_CAP;
8652 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 |
8653 VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
8654 }
8655
8656 bnxt_hwrm_vnic_qcaps(bp);
8657 if (bnxt_rfs_supported(bp)) {
8658 dev->hw_features |= NETIF_F_NTUPLE;
8659 if (bnxt_rfs_capable(bp)) {
8660 bp->flags |= BNXT_FLAG_RFS;
8661 dev->features |= NETIF_F_NTUPLE;
8662 }
8663 }
8664
8665 if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
8666 bp->flags |= BNXT_FLAG_STRIP_VLAN;
8667
8668 rc = bnxt_init_int_mode(bp);
8669 if (rc)
8670 goto init_err_pci_clean;
8671
8672 /* No TC has been set yet and rings may have been trimmed due to
8673 * limited MSIX, so we re-initialize the TX rings per TC.
8674 */
8675 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
8676
8677 bnxt_get_wol_settings(bp);
8678 if (bp->flags & BNXT_FLAG_WOL_CAP)
8679 device_set_wakeup_enable(&pdev->dev, bp->wol);
8680 else
8681 device_set_wakeup_capable(&pdev->dev, false);
8682
8683 bnxt_hwrm_set_cache_line_size(bp, cache_line_size());
8684
8685 if (BNXT_PF(bp)) {
8686 if (!bnxt_pf_wq) {
8687 bnxt_pf_wq =
8688 create_singlethread_workqueue("bnxt_pf_wq");
8689 if (!bnxt_pf_wq) {
8690 dev_err(&pdev->dev, "Unable to create workqueue.\n");
8691 goto init_err_pci_clean;
8692 }
8693 }
8694 bnxt_init_tc(bp);
8695 }
8696
8697 rc = register_netdev(dev);
8698 if (rc)
8699 goto init_err_cleanup_tc;
8700
8701 if (BNXT_PF(bp))
8702 bnxt_dl_register(bp);
8703
8704 netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
8705 board_info[ent->driver_data].name,
8706 (long)pci_resource_start(pdev, 0), dev->dev_addr);
8707
8708 bnxt_parse_log_pcie_link(bp);
8709
8710 return 0;
8711
8712 init_err_cleanup_tc:
8713 bnxt_shutdown_tc(bp);
8714 bnxt_clear_int_mode(bp);
8715
8716 init_err_pci_clean:
8717 bnxt_cleanup_pci(bp);
8718
8719 init_err_free:
8720 free_netdev(dev);
8721 return rc;
8722 }
8723
8724 static void bnxt_shutdown(struct pci_dev *pdev)
8725 {
8726 struct net_device *dev = pci_get_drvdata(pdev);
8727 struct bnxt *bp;
8728
8729 if (!dev)
8730 return;
8731
8732 rtnl_lock();
8733 bp = netdev_priv(dev);
8734 if (!bp)
8735 goto shutdown_exit;
8736
8737 if (netif_running(dev))
8738 dev_close(dev);
8739
8740 bnxt_ulp_shutdown(bp);
8741
8742 if (system_state == SYSTEM_POWER_OFF) {
8743 bnxt_clear_int_mode(bp);
8744 pci_wake_from_d3(pdev, bp->wol);
8745 pci_set_power_state(pdev, PCI_D3hot);
8746 }
8747
8748 shutdown_exit:
8749 rtnl_unlock();
8750 }
8751
8752 #ifdef CONFIG_PM_SLEEP
8753 static int bnxt_suspend(struct device *device)
8754 {
8755 struct pci_dev *pdev = to_pci_dev(device);
8756 struct net_device *dev = pci_get_drvdata(pdev);
8757 struct bnxt *bp = netdev_priv(dev);
8758 int rc = 0;
8759
8760 rtnl_lock();
8761 if (netif_running(dev)) {
8762 netif_device_detach(dev);
8763 rc = bnxt_close(dev);
8764 }
8765 bnxt_hwrm_func_drv_unrgtr(bp);
8766 rtnl_unlock();
8767 return rc;
8768 }
8769
8770 static int bnxt_resume(struct device *device)
8771 {
8772 struct pci_dev *pdev = to_pci_dev(device);
8773 struct net_device *dev = pci_get_drvdata(pdev);
8774 struct bnxt *bp = netdev_priv(dev);
8775 int rc = 0;
8776
8777 rtnl_lock();
8778 if (bnxt_hwrm_ver_get(bp) || bnxt_hwrm_func_drv_rgtr(bp)) {
8779 rc = -ENODEV;
8780 goto resume_exit;
8781 }
8782 rc = bnxt_hwrm_func_reset(bp);
8783 if (rc) {
8784 rc = -EBUSY;
8785 goto resume_exit;
8786 }
8787 bnxt_get_wol_settings(bp);
8788 if (netif_running(dev)) {
8789 rc = bnxt_open(dev);
8790 if (!rc)
8791 netif_device_attach(dev);
8792 }
8793
8794 resume_exit:
8795 rtnl_unlock();
8796 return rc;
8797 }
8798
8799 static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume);
8800 #define BNXT_PM_OPS (&bnxt_pm_ops)
8801
8802 #else
8803
8804 #define BNXT_PM_OPS NULL
8805
8806 #endif /* CONFIG_PM_SLEEP */
8807
8808 /**
8809 * bnxt_io_error_detected - called when PCI error is detected
8810 * @pdev: Pointer to PCI device
8811 * @state: The current pci connection state
8812 *
8813 * This function is called after a PCI bus error affecting
8814 * this device has been detected.
8815 */
8816 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
8817 pci_channel_state_t state)
8818 {
8819 struct net_device *netdev = pci_get_drvdata(pdev);
8820 struct bnxt *bp = netdev_priv(netdev);
8821
8822 netdev_info(netdev, "PCI I/O error detected\n");
8823
8824 rtnl_lock();
8825 netif_device_detach(netdev);
8826
8827 bnxt_ulp_stop(bp);
8828
8829 if (state == pci_channel_io_perm_failure) {
8830 rtnl_unlock();
8831 return PCI_ERS_RESULT_DISCONNECT;
8832 }
8833
8834 if (netif_running(netdev))
8835 bnxt_close(netdev);
8836
8837 pci_disable_device(pdev);
8838 rtnl_unlock();
8839
8840 /* Request a slot slot reset. */
8841 return PCI_ERS_RESULT_NEED_RESET;
8842 }
8843
8844 /**
8845 * bnxt_io_slot_reset - called after the pci bus has been reset.
8846 * @pdev: Pointer to PCI device
8847 *
8848 * Restart the card from scratch, as if from a cold-boot.
8849 * At this point, the card has exprienced a hard reset,
8850 * followed by fixups by BIOS, and has its config space
8851 * set up identically to what it was at cold boot.
8852 */
8853 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
8854 {
8855 struct net_device *netdev = pci_get_drvdata(pdev);
8856 struct bnxt *bp = netdev_priv(netdev);
8857 int err = 0;
8858 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
8859
8860 netdev_info(bp->dev, "PCI Slot Reset\n");
8861
8862 rtnl_lock();
8863
8864 if (pci_enable_device(pdev)) {
8865 dev_err(&pdev->dev,
8866 "Cannot re-enable PCI device after reset.\n");
8867 } else {
8868 pci_set_master(pdev);
8869
8870 err = bnxt_hwrm_func_reset(bp);
8871 if (!err && netif_running(netdev))
8872 err = bnxt_open(netdev);
8873
8874 if (!err) {
8875 result = PCI_ERS_RESULT_RECOVERED;
8876 bnxt_ulp_start(bp);
8877 }
8878 }
8879
8880 if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev))
8881 dev_close(netdev);
8882
8883 rtnl_unlock();
8884
8885 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8886 if (err) {
8887 dev_err(&pdev->dev,
8888 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
8889 err); /* non-fatal, continue */
8890 }
8891
8892 return PCI_ERS_RESULT_RECOVERED;
8893 }
8894
8895 /**
8896 * bnxt_io_resume - called when traffic can start flowing again.
8897 * @pdev: Pointer to PCI device
8898 *
8899 * This callback is called when the error recovery driver tells
8900 * us that its OK to resume normal operation.
8901 */
8902 static void bnxt_io_resume(struct pci_dev *pdev)
8903 {
8904 struct net_device *netdev = pci_get_drvdata(pdev);
8905
8906 rtnl_lock();
8907
8908 netif_device_attach(netdev);
8909
8910 rtnl_unlock();
8911 }
8912
8913 static const struct pci_error_handlers bnxt_err_handler = {
8914 .error_detected = bnxt_io_error_detected,
8915 .slot_reset = bnxt_io_slot_reset,
8916 .resume = bnxt_io_resume
8917 };
8918
8919 static struct pci_driver bnxt_pci_driver = {
8920 .name = DRV_MODULE_NAME,
8921 .id_table = bnxt_pci_tbl,
8922 .probe = bnxt_init_one,
8923 .remove = bnxt_remove_one,
8924 .shutdown = bnxt_shutdown,
8925 .driver.pm = BNXT_PM_OPS,
8926 .err_handler = &bnxt_err_handler,
8927 #if defined(CONFIG_BNXT_SRIOV)
8928 .sriov_configure = bnxt_sriov_configure,
8929 #endif
8930 };
8931
8932 static int __init bnxt_init(void)
8933 {
8934 return pci_register_driver(&bnxt_pci_driver);
8935 }
8936
8937 static void __exit bnxt_exit(void)
8938 {
8939 pci_unregister_driver(&bnxt_pci_driver);
8940 if (bnxt_pf_wq)
8941 destroy_workqueue(bnxt_pf_wq);
8942 }
8943
8944 module_init(bnxt_init);
8945 module_exit(bnxt_exit);
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