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Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / broadcom / bnxt / bnxt_hsi.h
1 /* Broadcom NetXtreme-C/E network driver.
2 *
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2014-2018 Broadcom Limited
5 * Copyright (c) 2018-2019 Broadcom Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation.
10 *
11 * DO NOT MODIFY!!! This file is automatically generated.
12 */
13
14 #ifndef _BNXT_HSI_H_
15 #define _BNXT_HSI_H_
16
17 /* hwrm_cmd_hdr (size:128b/16B) */
18 struct hwrm_cmd_hdr {
19 __le16 req_type;
20 __le16 cmpl_ring;
21 __le16 seq_id;
22 __le16 target_id;
23 __le64 resp_addr;
24 };
25
26 /* hwrm_resp_hdr (size:64b/8B) */
27 struct hwrm_resp_hdr {
28 __le16 error_code;
29 __le16 req_type;
30 __le16 seq_id;
31 __le16 resp_len;
32 };
33
34 #define CMD_DISCR_TLV_ENCAP 0x8000UL
35 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP
36
37
38 #define TLV_TYPE_HWRM_REQUEST 0x1UL
39 #define TLV_TYPE_HWRM_RESPONSE 0x2UL
40 #define TLV_TYPE_ROCE_SP_COMMAND 0x3UL
41 #define TLV_TYPE_QUERY_ROCE_CC_GEN1 0x4UL
42 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 0x5UL
43 #define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY 0x8001UL
44 #define TLV_TYPE_ENGINE_CKV_IV 0x8003UL
45 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG 0x8004UL
46 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT 0x8005UL
47 #define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS 0x8006UL
48 #define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY 0x8007UL
49 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE 0x8008UL
50 #define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY 0x8009UL
51 #define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 0x800aUL
52 #define TLV_TYPE_LAST TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS
53
54
55 /* tlv (size:64b/8B) */
56 struct tlv {
57 __le16 cmd_discr;
58 u8 reserved_8b;
59 u8 flags;
60 #define TLV_FLAGS_MORE 0x1UL
61 #define TLV_FLAGS_MORE_LAST 0x0UL
62 #define TLV_FLAGS_MORE_NOT_LAST 0x1UL
63 #define TLV_FLAGS_REQUIRED 0x2UL
64 #define TLV_FLAGS_REQUIRED_NO (0x0UL << 1)
65 #define TLV_FLAGS_REQUIRED_YES (0x1UL << 1)
66 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES
67 __le16 tlv_type;
68 __le16 length;
69 };
70
71 /* input (size:128b/16B) */
72 struct input {
73 __le16 req_type;
74 __le16 cmpl_ring;
75 __le16 seq_id;
76 __le16 target_id;
77 __le64 resp_addr;
78 };
79
80 /* output (size:64b/8B) */
81 struct output {
82 __le16 error_code;
83 __le16 req_type;
84 __le16 seq_id;
85 __le16 resp_len;
86 };
87
88 /* hwrm_short_input (size:128b/16B) */
89 struct hwrm_short_input {
90 __le16 req_type;
91 __le16 signature;
92 #define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL
93 #define SHORT_REQ_SIGNATURE_LAST SHORT_REQ_SIGNATURE_SHORT_CMD
94 __le16 target_id;
95 #define SHORT_REQ_TARGET_ID_DEFAULT 0x0UL
96 #define SHORT_REQ_TARGET_ID_TOOLS 0xfffdUL
97 #define SHORT_REQ_TARGET_ID_LAST SHORT_REQ_TARGET_ID_TOOLS
98 __le16 size;
99 __le64 req_addr;
100 };
101
102 /* cmd_nums (size:64b/8B) */
103 struct cmd_nums {
104 __le16 req_type;
105 #define HWRM_VER_GET 0x0UL
106 #define HWRM_ERROR_RECOVERY_QCFG 0xcUL
107 #define HWRM_FUNC_DRV_IF_CHANGE 0xdUL
108 #define HWRM_FUNC_BUF_UNRGTR 0xeUL
109 #define HWRM_FUNC_VF_CFG 0xfUL
110 #define HWRM_RESERVED1 0x10UL
111 #define HWRM_FUNC_RESET 0x11UL
112 #define HWRM_FUNC_GETFID 0x12UL
113 #define HWRM_FUNC_VF_ALLOC 0x13UL
114 #define HWRM_FUNC_VF_FREE 0x14UL
115 #define HWRM_FUNC_QCAPS 0x15UL
116 #define HWRM_FUNC_QCFG 0x16UL
117 #define HWRM_FUNC_CFG 0x17UL
118 #define HWRM_FUNC_QSTATS 0x18UL
119 #define HWRM_FUNC_CLR_STATS 0x19UL
120 #define HWRM_FUNC_DRV_UNRGTR 0x1aUL
121 #define HWRM_FUNC_VF_RESC_FREE 0x1bUL
122 #define HWRM_FUNC_VF_VNIC_IDS_QUERY 0x1cUL
123 #define HWRM_FUNC_DRV_RGTR 0x1dUL
124 #define HWRM_FUNC_DRV_QVER 0x1eUL
125 #define HWRM_FUNC_BUF_RGTR 0x1fUL
126 #define HWRM_PORT_PHY_CFG 0x20UL
127 #define HWRM_PORT_MAC_CFG 0x21UL
128 #define HWRM_PORT_TS_QUERY 0x22UL
129 #define HWRM_PORT_QSTATS 0x23UL
130 #define HWRM_PORT_LPBK_QSTATS 0x24UL
131 #define HWRM_PORT_CLR_STATS 0x25UL
132 #define HWRM_PORT_LPBK_CLR_STATS 0x26UL
133 #define HWRM_PORT_PHY_QCFG 0x27UL
134 #define HWRM_PORT_MAC_QCFG 0x28UL
135 #define HWRM_PORT_MAC_PTP_QCFG 0x29UL
136 #define HWRM_PORT_PHY_QCAPS 0x2aUL
137 #define HWRM_PORT_PHY_I2C_WRITE 0x2bUL
138 #define HWRM_PORT_PHY_I2C_READ 0x2cUL
139 #define HWRM_PORT_LED_CFG 0x2dUL
140 #define HWRM_PORT_LED_QCFG 0x2eUL
141 #define HWRM_PORT_LED_QCAPS 0x2fUL
142 #define HWRM_QUEUE_QPORTCFG 0x30UL
143 #define HWRM_QUEUE_QCFG 0x31UL
144 #define HWRM_QUEUE_CFG 0x32UL
145 #define HWRM_FUNC_VLAN_CFG 0x33UL
146 #define HWRM_FUNC_VLAN_QCFG 0x34UL
147 #define HWRM_QUEUE_PFCENABLE_QCFG 0x35UL
148 #define HWRM_QUEUE_PFCENABLE_CFG 0x36UL
149 #define HWRM_QUEUE_PRI2COS_QCFG 0x37UL
150 #define HWRM_QUEUE_PRI2COS_CFG 0x38UL
151 #define HWRM_QUEUE_COS2BW_QCFG 0x39UL
152 #define HWRM_QUEUE_COS2BW_CFG 0x3aUL
153 #define HWRM_QUEUE_DSCP_QCAPS 0x3bUL
154 #define HWRM_QUEUE_DSCP2PRI_QCFG 0x3cUL
155 #define HWRM_QUEUE_DSCP2PRI_CFG 0x3dUL
156 #define HWRM_VNIC_ALLOC 0x40UL
157 #define HWRM_VNIC_FREE 0x41UL
158 #define HWRM_VNIC_CFG 0x42UL
159 #define HWRM_VNIC_QCFG 0x43UL
160 #define HWRM_VNIC_TPA_CFG 0x44UL
161 #define HWRM_VNIC_TPA_QCFG 0x45UL
162 #define HWRM_VNIC_RSS_CFG 0x46UL
163 #define HWRM_VNIC_RSS_QCFG 0x47UL
164 #define HWRM_VNIC_PLCMODES_CFG 0x48UL
165 #define HWRM_VNIC_PLCMODES_QCFG 0x49UL
166 #define HWRM_VNIC_QCAPS 0x4aUL
167 #define HWRM_RING_ALLOC 0x50UL
168 #define HWRM_RING_FREE 0x51UL
169 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS 0x52UL
170 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS 0x53UL
171 #define HWRM_RING_AGGINT_QCAPS 0x54UL
172 #define HWRM_RING_RESET 0x5eUL
173 #define HWRM_RING_GRP_ALLOC 0x60UL
174 #define HWRM_RING_GRP_FREE 0x61UL
175 #define HWRM_RESERVED5 0x64UL
176 #define HWRM_RESERVED6 0x65UL
177 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC 0x70UL
178 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE 0x71UL
179 #define HWRM_QUEUE_MPLS_QCAPS 0x80UL
180 #define HWRM_QUEUE_MPLSTC2PRI_QCFG 0x81UL
181 #define HWRM_QUEUE_MPLSTC2PRI_CFG 0x82UL
182 #define HWRM_CFA_L2_FILTER_ALLOC 0x90UL
183 #define HWRM_CFA_L2_FILTER_FREE 0x91UL
184 #define HWRM_CFA_L2_FILTER_CFG 0x92UL
185 #define HWRM_CFA_L2_SET_RX_MASK 0x93UL
186 #define HWRM_CFA_VLAN_ANTISPOOF_CFG 0x94UL
187 #define HWRM_CFA_TUNNEL_FILTER_ALLOC 0x95UL
188 #define HWRM_CFA_TUNNEL_FILTER_FREE 0x96UL
189 #define HWRM_CFA_ENCAP_RECORD_ALLOC 0x97UL
190 #define HWRM_CFA_ENCAP_RECORD_FREE 0x98UL
191 #define HWRM_CFA_NTUPLE_FILTER_ALLOC 0x99UL
192 #define HWRM_CFA_NTUPLE_FILTER_FREE 0x9aUL
193 #define HWRM_CFA_NTUPLE_FILTER_CFG 0x9bUL
194 #define HWRM_CFA_EM_FLOW_ALLOC 0x9cUL
195 #define HWRM_CFA_EM_FLOW_FREE 0x9dUL
196 #define HWRM_CFA_EM_FLOW_CFG 0x9eUL
197 #define HWRM_TUNNEL_DST_PORT_QUERY 0xa0UL
198 #define HWRM_TUNNEL_DST_PORT_ALLOC 0xa1UL
199 #define HWRM_TUNNEL_DST_PORT_FREE 0xa2UL
200 #define HWRM_STAT_CTX_ENG_QUERY 0xafUL
201 #define HWRM_STAT_CTX_ALLOC 0xb0UL
202 #define HWRM_STAT_CTX_FREE 0xb1UL
203 #define HWRM_STAT_CTX_QUERY 0xb2UL
204 #define HWRM_STAT_CTX_CLR_STATS 0xb3UL
205 #define HWRM_PORT_QSTATS_EXT 0xb4UL
206 #define HWRM_PORT_PHY_MDIO_WRITE 0xb5UL
207 #define HWRM_PORT_PHY_MDIO_READ 0xb6UL
208 #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE 0xb7UL
209 #define HWRM_PORT_PHY_MDIO_BUS_RELEASE 0xb8UL
210 #define HWRM_FW_RESET 0xc0UL
211 #define HWRM_FW_QSTATUS 0xc1UL
212 #define HWRM_FW_HEALTH_CHECK 0xc2UL
213 #define HWRM_FW_SYNC 0xc3UL
214 #define HWRM_FW_STATE_QCAPS 0xc4UL
215 #define HWRM_FW_STATE_QUIESCE 0xc5UL
216 #define HWRM_FW_STATE_BACKUP 0xc6UL
217 #define HWRM_FW_STATE_RESTORE 0xc7UL
218 #define HWRM_FW_SET_TIME 0xc8UL
219 #define HWRM_FW_GET_TIME 0xc9UL
220 #define HWRM_FW_SET_STRUCTURED_DATA 0xcaUL
221 #define HWRM_FW_GET_STRUCTURED_DATA 0xcbUL
222 #define HWRM_FW_IPC_MAILBOX 0xccUL
223 #define HWRM_EXEC_FWD_RESP 0xd0UL
224 #define HWRM_REJECT_FWD_RESP 0xd1UL
225 #define HWRM_FWD_RESP 0xd2UL
226 #define HWRM_FWD_ASYNC_EVENT_CMPL 0xd3UL
227 #define HWRM_OEM_CMD 0xd4UL
228 #define HWRM_PORT_PRBS_TEST 0xd5UL
229 #define HWRM_PORT_SFP_SIDEBAND_CFG 0xd6UL
230 #define HWRM_PORT_SFP_SIDEBAND_QCFG 0xd7UL
231 #define HWRM_FW_STATE_UNQUIESCE 0xd8UL
232 #define HWRM_PORT_DSC_DUMP 0xd9UL
233 #define HWRM_TEMP_MONITOR_QUERY 0xe0UL
234 #define HWRM_REG_POWER_QUERY 0xe1UL
235 #define HWRM_CORE_FREQUENCY_QUERY 0xe2UL
236 #define HWRM_WOL_FILTER_ALLOC 0xf0UL
237 #define HWRM_WOL_FILTER_FREE 0xf1UL
238 #define HWRM_WOL_FILTER_QCFG 0xf2UL
239 #define HWRM_WOL_REASON_QCFG 0xf3UL
240 #define HWRM_CFA_METER_QCAPS 0xf4UL
241 #define HWRM_CFA_METER_PROFILE_ALLOC 0xf5UL
242 #define HWRM_CFA_METER_PROFILE_FREE 0xf6UL
243 #define HWRM_CFA_METER_PROFILE_CFG 0xf7UL
244 #define HWRM_CFA_METER_INSTANCE_ALLOC 0xf8UL
245 #define HWRM_CFA_METER_INSTANCE_FREE 0xf9UL
246 #define HWRM_CFA_METER_INSTANCE_CFG 0xfaUL
247 #define HWRM_CFA_VFR_ALLOC 0xfdUL
248 #define HWRM_CFA_VFR_FREE 0xfeUL
249 #define HWRM_CFA_VF_PAIR_ALLOC 0x100UL
250 #define HWRM_CFA_VF_PAIR_FREE 0x101UL
251 #define HWRM_CFA_VF_PAIR_INFO 0x102UL
252 #define HWRM_CFA_FLOW_ALLOC 0x103UL
253 #define HWRM_CFA_FLOW_FREE 0x104UL
254 #define HWRM_CFA_FLOW_FLUSH 0x105UL
255 #define HWRM_CFA_FLOW_STATS 0x106UL
256 #define HWRM_CFA_FLOW_INFO 0x107UL
257 #define HWRM_CFA_DECAP_FILTER_ALLOC 0x108UL
258 #define HWRM_CFA_DECAP_FILTER_FREE 0x109UL
259 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG 0x10aUL
260 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC 0x10bUL
261 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE 0x10cUL
262 #define HWRM_CFA_PAIR_ALLOC 0x10dUL
263 #define HWRM_CFA_PAIR_FREE 0x10eUL
264 #define HWRM_CFA_PAIR_INFO 0x10fUL
265 #define HWRM_FW_IPC_MSG 0x110UL
266 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO 0x111UL
267 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE 0x112UL
268 #define HWRM_CFA_FLOW_AGING_TIMER_RESET 0x113UL
269 #define HWRM_CFA_FLOW_AGING_CFG 0x114UL
270 #define HWRM_CFA_FLOW_AGING_QCFG 0x115UL
271 #define HWRM_CFA_FLOW_AGING_QCAPS 0x116UL
272 #define HWRM_CFA_CTX_MEM_RGTR 0x117UL
273 #define HWRM_CFA_CTX_MEM_UNRGTR 0x118UL
274 #define HWRM_CFA_CTX_MEM_QCTX 0x119UL
275 #define HWRM_CFA_CTX_MEM_QCAPS 0x11aUL
276 #define HWRM_CFA_COUNTER_QCAPS 0x11bUL
277 #define HWRM_CFA_COUNTER_CFG 0x11cUL
278 #define HWRM_CFA_COUNTER_QCFG 0x11dUL
279 #define HWRM_CFA_COUNTER_QSTATS 0x11eUL
280 #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG 0x11fUL
281 #define HWRM_CFA_EEM_QCAPS 0x120UL
282 #define HWRM_CFA_EEM_CFG 0x121UL
283 #define HWRM_CFA_EEM_QCFG 0x122UL
284 #define HWRM_CFA_EEM_OP 0x123UL
285 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS 0x124UL
286 #define HWRM_CFA_TFLIB 0x125UL
287 #define HWRM_ENGINE_CKV_STATUS 0x12eUL
288 #define HWRM_ENGINE_CKV_CKEK_ADD 0x12fUL
289 #define HWRM_ENGINE_CKV_CKEK_DELETE 0x130UL
290 #define HWRM_ENGINE_CKV_KEY_ADD 0x131UL
291 #define HWRM_ENGINE_CKV_KEY_DELETE 0x132UL
292 #define HWRM_ENGINE_CKV_FLUSH 0x133UL
293 #define HWRM_ENGINE_CKV_RNG_GET 0x134UL
294 #define HWRM_ENGINE_CKV_KEY_GEN 0x135UL
295 #define HWRM_ENGINE_CKV_KEY_LABEL_CFG 0x136UL
296 #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG 0x137UL
297 #define HWRM_ENGINE_QG_CONFIG_QUERY 0x13cUL
298 #define HWRM_ENGINE_QG_QUERY 0x13dUL
299 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY 0x13eUL
300 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY 0x13fUL
301 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC 0x140UL
302 #define HWRM_ENGINE_QG_METER_PROFILE_FREE 0x141UL
303 #define HWRM_ENGINE_QG_METER_QUERY 0x142UL
304 #define HWRM_ENGINE_QG_METER_BIND 0x143UL
305 #define HWRM_ENGINE_QG_METER_UNBIND 0x144UL
306 #define HWRM_ENGINE_QG_FUNC_BIND 0x145UL
307 #define HWRM_ENGINE_SG_CONFIG_QUERY 0x146UL
308 #define HWRM_ENGINE_SG_QUERY 0x147UL
309 #define HWRM_ENGINE_SG_METER_QUERY 0x148UL
310 #define HWRM_ENGINE_SG_METER_CONFIG 0x149UL
311 #define HWRM_ENGINE_SG_QG_BIND 0x14aUL
312 #define HWRM_ENGINE_QG_SG_UNBIND 0x14bUL
313 #define HWRM_ENGINE_CONFIG_QUERY 0x154UL
314 #define HWRM_ENGINE_STATS_CONFIG 0x155UL
315 #define HWRM_ENGINE_STATS_CLEAR 0x156UL
316 #define HWRM_ENGINE_STATS_QUERY 0x157UL
317 #define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR 0x158UL
318 #define HWRM_ENGINE_RQ_ALLOC 0x15eUL
319 #define HWRM_ENGINE_RQ_FREE 0x15fUL
320 #define HWRM_ENGINE_CQ_ALLOC 0x160UL
321 #define HWRM_ENGINE_CQ_FREE 0x161UL
322 #define HWRM_ENGINE_NQ_ALLOC 0x162UL
323 #define HWRM_ENGINE_NQ_FREE 0x163UL
324 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS 0x164UL
325 #define HWRM_ENGINE_FUNC_QCFG 0x165UL
326 #define HWRM_FUNC_RESOURCE_QCAPS 0x190UL
327 #define HWRM_FUNC_VF_RESOURCE_CFG 0x191UL
328 #define HWRM_FUNC_BACKING_STORE_QCAPS 0x192UL
329 #define HWRM_FUNC_BACKING_STORE_CFG 0x193UL
330 #define HWRM_FUNC_BACKING_STORE_QCFG 0x194UL
331 #define HWRM_FUNC_VF_BW_CFG 0x195UL
332 #define HWRM_FUNC_VF_BW_QCFG 0x196UL
333 #define HWRM_FUNC_HOST_PF_IDS_QUERY 0x197UL
334 #define HWRM_SELFTEST_QLIST 0x200UL
335 #define HWRM_SELFTEST_EXEC 0x201UL
336 #define HWRM_SELFTEST_IRQ 0x202UL
337 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA 0x203UL
338 #define HWRM_PCIE_QSTATS 0x204UL
339 #define HWRM_MFG_FRU_WRITE_CONTROL 0x205UL
340 #define HWRM_MFG_TIMERS_QUERY 0x206UL
341 #define HWRM_MFG_OTP_CFG 0x207UL
342 #define HWRM_MFG_OTP_QCFG 0x208UL
343 #define HWRM_MFG_HDMA_TEST 0x209UL
344 #define HWRM_DBG_READ_DIRECT 0xff10UL
345 #define HWRM_DBG_READ_INDIRECT 0xff11UL
346 #define HWRM_DBG_WRITE_DIRECT 0xff12UL
347 #define HWRM_DBG_WRITE_INDIRECT 0xff13UL
348 #define HWRM_DBG_DUMP 0xff14UL
349 #define HWRM_DBG_ERASE_NVM 0xff15UL
350 #define HWRM_DBG_CFG 0xff16UL
351 #define HWRM_DBG_COREDUMP_LIST 0xff17UL
352 #define HWRM_DBG_COREDUMP_INITIATE 0xff18UL
353 #define HWRM_DBG_COREDUMP_RETRIEVE 0xff19UL
354 #define HWRM_DBG_FW_CLI 0xff1aUL
355 #define HWRM_DBG_I2C_CMD 0xff1bUL
356 #define HWRM_DBG_RING_INFO_GET 0xff1cUL
357 #define HWRM_DBG_CRASHDUMP_HEADER 0xff1dUL
358 #define HWRM_DBG_CRASHDUMP_ERASE 0xff1eUL
359 #define HWRM_NVM_FACTORY_DEFAULTS 0xffeeUL
360 #define HWRM_NVM_VALIDATE_OPTION 0xffefUL
361 #define HWRM_NVM_FLUSH 0xfff0UL
362 #define HWRM_NVM_GET_VARIABLE 0xfff1UL
363 #define HWRM_NVM_SET_VARIABLE 0xfff2UL
364 #define HWRM_NVM_INSTALL_UPDATE 0xfff3UL
365 #define HWRM_NVM_MODIFY 0xfff4UL
366 #define HWRM_NVM_VERIFY_UPDATE 0xfff5UL
367 #define HWRM_NVM_GET_DEV_INFO 0xfff6UL
368 #define HWRM_NVM_ERASE_DIR_ENTRY 0xfff7UL
369 #define HWRM_NVM_MOD_DIR_ENTRY 0xfff8UL
370 #define HWRM_NVM_FIND_DIR_ENTRY 0xfff9UL
371 #define HWRM_NVM_GET_DIR_ENTRIES 0xfffaUL
372 #define HWRM_NVM_GET_DIR_INFO 0xfffbUL
373 #define HWRM_NVM_RAW_DUMP 0xfffcUL
374 #define HWRM_NVM_READ 0xfffdUL
375 #define HWRM_NVM_WRITE 0xfffeUL
376 #define HWRM_NVM_RAW_WRITE_BLK 0xffffUL
377 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK
378 __le16 unused_0[3];
379 };
380
381 /* ret_codes (size:64b/8B) */
382 struct ret_codes {
383 __le16 error_code;
384 #define HWRM_ERR_CODE_SUCCESS 0x0UL
385 #define HWRM_ERR_CODE_FAIL 0x1UL
386 #define HWRM_ERR_CODE_INVALID_PARAMS 0x2UL
387 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED 0x3UL
388 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR 0x4UL
389 #define HWRM_ERR_CODE_INVALID_FLAGS 0x5UL
390 #define HWRM_ERR_CODE_INVALID_ENABLES 0x6UL
391 #define HWRM_ERR_CODE_UNSUPPORTED_TLV 0x7UL
392 #define HWRM_ERR_CODE_NO_BUFFER 0x8UL
393 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR 0x9UL
394 #define HWRM_ERR_CODE_HOT_RESET_PROGRESS 0xaUL
395 #define HWRM_ERR_CODE_HOT_RESET_FAIL 0xbUL
396 #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC 0xcUL
397 #define HWRM_ERR_CODE_KEY_HASH_COLLISION 0xdUL
398 #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS 0xeUL
399 #define HWRM_ERR_CODE_HWRM_ERROR 0xfUL
400 #define HWRM_ERR_CODE_BUSY 0x10UL
401 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE 0x8000UL
402 #define HWRM_ERR_CODE_UNKNOWN_ERR 0xfffeUL
403 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED 0xffffUL
404 #define HWRM_ERR_CODE_LAST HWRM_ERR_CODE_CMD_NOT_SUPPORTED
405 __le16 unused_0[3];
406 };
407
408 /* hwrm_err_output (size:128b/16B) */
409 struct hwrm_err_output {
410 __le16 error_code;
411 __le16 req_type;
412 __le16 seq_id;
413 __le16 resp_len;
414 __le32 opaque_0;
415 __le16 opaque_1;
416 u8 cmd_err;
417 u8 valid;
418 };
419 #define HWRM_NA_SIGNATURE ((__le32)(-1))
420 #define HWRM_MAX_REQ_LEN 128
421 #define HWRM_MAX_RESP_LEN 704
422 #define HW_HASH_INDEX_SIZE 0x80
423 #define HW_HASH_KEY_SIZE 40
424 #define HWRM_RESP_VALID_KEY 1
425 #define HWRM_TARGET_ID_BONO 0xFFF8
426 #define HWRM_TARGET_ID_KONG 0xFFF9
427 #define HWRM_TARGET_ID_APE 0xFFFA
428 #define HWRM_TARGET_ID_TOOLS 0xFFFD
429 #define HWRM_VERSION_MAJOR 1
430 #define HWRM_VERSION_MINOR 10
431 #define HWRM_VERSION_UPDATE 1
432 #define HWRM_VERSION_RSVD 12
433 #define HWRM_VERSION_STR "1.10.1.12"
434
435 /* hwrm_ver_get_input (size:192b/24B) */
436 struct hwrm_ver_get_input {
437 __le16 req_type;
438 __le16 cmpl_ring;
439 __le16 seq_id;
440 __le16 target_id;
441 __le64 resp_addr;
442 u8 hwrm_intf_maj;
443 u8 hwrm_intf_min;
444 u8 hwrm_intf_upd;
445 u8 unused_0[5];
446 };
447
448 /* hwrm_ver_get_output (size:1408b/176B) */
449 struct hwrm_ver_get_output {
450 __le16 error_code;
451 __le16 req_type;
452 __le16 seq_id;
453 __le16 resp_len;
454 u8 hwrm_intf_maj_8b;
455 u8 hwrm_intf_min_8b;
456 u8 hwrm_intf_upd_8b;
457 u8 hwrm_intf_rsvd_8b;
458 u8 hwrm_fw_maj_8b;
459 u8 hwrm_fw_min_8b;
460 u8 hwrm_fw_bld_8b;
461 u8 hwrm_fw_rsvd_8b;
462 u8 mgmt_fw_maj_8b;
463 u8 mgmt_fw_min_8b;
464 u8 mgmt_fw_bld_8b;
465 u8 mgmt_fw_rsvd_8b;
466 u8 netctrl_fw_maj_8b;
467 u8 netctrl_fw_min_8b;
468 u8 netctrl_fw_bld_8b;
469 u8 netctrl_fw_rsvd_8b;
470 __le32 dev_caps_cfg;
471 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL
472 #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL
473 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL
474 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL
475 #define VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED 0x10UL
476 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED 0x20UL
477 #define VER_GET_RESP_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED 0x40UL
478 #define VER_GET_RESP_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED 0x80UL
479 #define VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED 0x100UL
480 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED 0x200UL
481 #define VER_GET_RESP_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED 0x400UL
482 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_EEM_SUPPORTED 0x800UL
483 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED 0x1000UL
484 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED 0x2000UL
485 u8 roce_fw_maj_8b;
486 u8 roce_fw_min_8b;
487 u8 roce_fw_bld_8b;
488 u8 roce_fw_rsvd_8b;
489 char hwrm_fw_name[16];
490 char mgmt_fw_name[16];
491 char netctrl_fw_name[16];
492 char active_pkg_name[16];
493 char roce_fw_name[16];
494 __le16 chip_num;
495 u8 chip_rev;
496 u8 chip_metal;
497 u8 chip_bond_id;
498 u8 chip_platform_type;
499 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC 0x0UL
500 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA 0x1UL
501 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL
502 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_LAST VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM
503 __le16 max_req_win_len;
504 __le16 max_resp_len;
505 __le16 def_req_timeout;
506 u8 flags;
507 #define VER_GET_RESP_FLAGS_DEV_NOT_RDY 0x1UL
508 #define VER_GET_RESP_FLAGS_EXT_VER_AVAIL 0x2UL
509 u8 unused_0[2];
510 u8 always_1;
511 __le16 hwrm_intf_major;
512 __le16 hwrm_intf_minor;
513 __le16 hwrm_intf_build;
514 __le16 hwrm_intf_patch;
515 __le16 hwrm_fw_major;
516 __le16 hwrm_fw_minor;
517 __le16 hwrm_fw_build;
518 __le16 hwrm_fw_patch;
519 __le16 mgmt_fw_major;
520 __le16 mgmt_fw_minor;
521 __le16 mgmt_fw_build;
522 __le16 mgmt_fw_patch;
523 __le16 netctrl_fw_major;
524 __le16 netctrl_fw_minor;
525 __le16 netctrl_fw_build;
526 __le16 netctrl_fw_patch;
527 __le16 roce_fw_major;
528 __le16 roce_fw_minor;
529 __le16 roce_fw_build;
530 __le16 roce_fw_patch;
531 __le16 max_ext_req_len;
532 u8 unused_1[5];
533 u8 valid;
534 };
535
536 /* eject_cmpl (size:128b/16B) */
537 struct eject_cmpl {
538 __le16 type;
539 #define EJECT_CMPL_TYPE_MASK 0x3fUL
540 #define EJECT_CMPL_TYPE_SFT 0
541 #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL
542 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT
543 #define EJECT_CMPL_FLAGS_MASK 0xffc0UL
544 #define EJECT_CMPL_FLAGS_SFT 6
545 #define EJECT_CMPL_FLAGS_ERROR 0x40UL
546 __le16 len;
547 __le32 opaque;
548 __le16 v;
549 #define EJECT_CMPL_V 0x1UL
550 #define EJECT_CMPL_ERRORS_MASK 0xfffeUL
551 #define EJECT_CMPL_ERRORS_SFT 1
552 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK 0xeUL
553 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
554 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0UL << 1)
555 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1UL << 1)
556 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3UL << 1)
557 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH (0x5UL << 1)
558 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
559 __le16 reserved16;
560 __le32 unused_2;
561 };
562
563 /* hwrm_cmpl (size:128b/16B) */
564 struct hwrm_cmpl {
565 __le16 type;
566 #define CMPL_TYPE_MASK 0x3fUL
567 #define CMPL_TYPE_SFT 0
568 #define CMPL_TYPE_HWRM_DONE 0x20UL
569 #define CMPL_TYPE_LAST CMPL_TYPE_HWRM_DONE
570 __le16 sequence_id;
571 __le32 unused_1;
572 __le32 v;
573 #define CMPL_V 0x1UL
574 __le32 unused_3;
575 };
576
577 /* hwrm_fwd_req_cmpl (size:128b/16B) */
578 struct hwrm_fwd_req_cmpl {
579 __le16 req_len_type;
580 #define FWD_REQ_CMPL_TYPE_MASK 0x3fUL
581 #define FWD_REQ_CMPL_TYPE_SFT 0
582 #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 0x22UL
583 #define FWD_REQ_CMPL_TYPE_LAST FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ
584 #define FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL
585 #define FWD_REQ_CMPL_REQ_LEN_SFT 6
586 __le16 source_id;
587 __le32 unused0;
588 __le32 req_buf_addr_v[2];
589 #define FWD_REQ_CMPL_V 0x1UL
590 #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL
591 #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1
592 };
593
594 /* hwrm_fwd_resp_cmpl (size:128b/16B) */
595 struct hwrm_fwd_resp_cmpl {
596 __le16 type;
597 #define FWD_RESP_CMPL_TYPE_MASK 0x3fUL
598 #define FWD_RESP_CMPL_TYPE_SFT 0
599 #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 0x24UL
600 #define FWD_RESP_CMPL_TYPE_LAST FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP
601 __le16 source_id;
602 __le16 resp_len;
603 __le16 unused_1;
604 __le32 resp_buf_addr_v[2];
605 #define FWD_RESP_CMPL_V 0x1UL
606 #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL
607 #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1
608 };
609
610 /* hwrm_async_event_cmpl (size:128b/16B) */
611 struct hwrm_async_event_cmpl {
612 __le16 type;
613 #define ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL
614 #define ASYNC_EVENT_CMPL_TYPE_SFT 0
615 #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 0x2eUL
616 #define ASYNC_EVENT_CMPL_TYPE_LAST ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT
617 __le16 event_id;
618 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL
619 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE 0x1UL
620 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE 0x2UL
621 #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL
622 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL
623 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL
624 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL
625 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL
626 #define ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY 0x8UL
627 #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY 0x9UL
628 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL
629 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL
630 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL
631 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD 0x20UL
632 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD 0x21UL
633 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR 0x30UL
634 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL
635 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL
636 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL
637 #define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE 0x34UL
638 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE 0x35UL
639 #define ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED 0x36UL
640 #define ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION 0x37UL
641 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL
642 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL
643 #define ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE 0x3aUL
644 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE 0x3bUL
645 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE 0x3cUL
646 #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE 0x3dUL
647 #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE 0x3eUL
648 #define ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE 0x3fUL
649 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE 0x40UL
650 #define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG 0xfeUL
651 #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL
652 #define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
653 __le32 event_data2;
654 u8 opaque_v;
655 #define ASYNC_EVENT_CMPL_V 0x1UL
656 #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL
657 #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1
658 u8 timestamp_lo;
659 __le16 timestamp_hi;
660 __le32 event_data1;
661 };
662
663 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */
664 struct hwrm_async_event_cmpl_link_status_change {
665 __le16 type;
666 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL
667 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0
668 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
669 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
670 __le16 event_id;
671 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL
672 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE
673 __le32 event_data2;
674 u8 opaque_v;
675 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL
676 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL
677 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1
678 u8 timestamp_lo;
679 __le16 timestamp_hi;
680 __le32 event_data1;
681 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL
682 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN 0x0UL
683 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 0x1UL
684 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP
685 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL
686 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1
687 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL
688 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4
689 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK 0xff00000UL
690 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT 20
691 };
692
693 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */
694 struct hwrm_async_event_cmpl_port_conn_not_allowed {
695 __le16 type;
696 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL
697 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0
698 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL
699 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
700 __le16 event_id;
701 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL
702 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED
703 __le32 event_data2;
704 u8 opaque_v;
705 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL
706 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL
707 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1
708 u8 timestamp_lo;
709 __le16 timestamp_hi;
710 __le32 event_data1;
711 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL
712 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0
713 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL
714 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16
715 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16)
716 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16)
717 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16)
718 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16)
719 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN
720 };
721
722 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */
723 struct hwrm_async_event_cmpl_link_speed_cfg_change {
724 __le16 type;
725 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL
726 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0
727 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
728 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
729 __le16 event_id;
730 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL
731 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE
732 __le32 event_data2;
733 u8 opaque_v;
734 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL
735 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL
736 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1
737 u8 timestamp_lo;
738 __le16 timestamp_hi;
739 __le32 event_data1;
740 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL
741 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0
742 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL
743 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL
744 };
745
746 /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */
747 struct hwrm_async_event_cmpl_reset_notify {
748 __le16 type;
749 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK 0x3fUL
750 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0
751 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 0x2eUL
752 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT
753 __le16 event_id;
754 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 0x8UL
755 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY
756 __le32 event_data2;
757 u8 opaque_v;
758 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_V 0x1UL
759 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK 0xfeUL
760 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1
761 u8 timestamp_lo;
762 __le16 timestamp_hi;
763 __le32 event_data1;
764 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK 0xffUL
765 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT 0
766 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE 0x1UL
767 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 0x2UL
768 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN
769 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK 0xff00UL
770 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT 8
771 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST (0x1UL << 8)
772 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL (0x2UL << 8)
773 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL (0x3UL << 8)
774 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL
775 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK 0xffff0000UL
776 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT 16
777 };
778
779 /* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */
780 struct hwrm_async_event_cmpl_error_recovery {
781 __le16 type;
782 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK 0x3fUL
783 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0
784 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 0x2eUL
785 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT
786 __le16 event_id;
787 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 0x9UL
788 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY
789 __le32 event_data2;
790 u8 opaque_v;
791 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_V 0x1UL
792 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK 0xfeUL
793 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1
794 u8 timestamp_lo;
795 __le16 timestamp_hi;
796 __le32 event_data1;
797 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK 0xffUL
798 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT 0
799 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC 0x1UL
800 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED 0x2UL
801 };
802
803 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */
804 struct hwrm_async_event_cmpl_vf_cfg_change {
805 __le16 type;
806 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL
807 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0
808 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
809 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
810 __le16 event_id;
811 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL
812 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE
813 __le32 event_data2;
814 u8 opaque_v;
815 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL
816 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL
817 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1
818 u8 timestamp_lo;
819 __le16 timestamp_hi;
820 __le32 event_data1;
821 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL
822 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL
823 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL
824 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL
825 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE 0x10UL
826 };
827
828 /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */
829 struct hwrm_async_event_cmpl_default_vnic_change {
830 __le16 type;
831 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK 0x3fUL
832 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT 0
833 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
834 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT
835 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK 0xffc0UL
836 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT 6
837 __le16 event_id;
838 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 0x35UL
839 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION
840 __le32 event_data2;
841 u8 opaque_v;
842 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V 0x1UL
843 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK 0xfeUL
844 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1
845 u8 timestamp_lo;
846 __le16 timestamp_hi;
847 __le32 event_data1;
848 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK 0x3UL
849 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT 0
850 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC 0x1UL
851 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 0x2UL
852 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE
853 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK 0x3fcUL
854 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT 2
855 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK 0x3fffc00UL
856 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT 10
857 };
858
859 /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */
860 struct hwrm_async_event_cmpl_hw_flow_aged {
861 __le16 type;
862 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK 0x3fUL
863 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0
864 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 0x2eUL
865 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT
866 __le16 event_id;
867 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 0x36UL
868 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED
869 __le32 event_data2;
870 u8 opaque_v;
871 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_V 0x1UL
872 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK 0xfeUL
873 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1
874 u8 timestamp_lo;
875 __le16 timestamp_hi;
876 __le32 event_data1;
877 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK 0x7fffffffUL
878 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT 0
879 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION 0x80000000UL
880 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX (0x0UL << 31)
881 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX (0x1UL << 31)
882 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX
883 };
884
885 /* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */
886 struct hwrm_async_event_cmpl_eem_cache_flush_req {
887 __le16 type;
888 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK 0x3fUL
889 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT 0
890 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 0x2eUL
891 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT
892 __le16 event_id;
893 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL
894 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ
895 __le32 event_data2;
896 u8 opaque_v;
897 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V 0x1UL
898 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK 0xfeUL
899 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1
900 u8 timestamp_lo;
901 __le16 timestamp_hi;
902 __le32 event_data1;
903 };
904
905 /* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */
906 struct hwrm_async_event_cmpl_eem_cache_flush_done {
907 __le16 type;
908 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK 0x3fUL
909 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT 0
910 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
911 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT
912 __le16 event_id;
913 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL
914 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE
915 __le32 event_data2;
916 u8 opaque_v;
917 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V 0x1UL
918 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK 0xfeUL
919 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1
920 u8 timestamp_lo;
921 __le16 timestamp_hi;
922 __le32 event_data1;
923 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK 0xffffUL
924 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT 0
925 };
926
927 /* hwrm_func_reset_input (size:192b/24B) */
928 struct hwrm_func_reset_input {
929 __le16 req_type;
930 __le16 cmpl_ring;
931 __le16 seq_id;
932 __le16 target_id;
933 __le64 resp_addr;
934 __le32 enables;
935 #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL
936 __le16 vf_id;
937 u8 func_reset_level;
938 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL 0x0UL
939 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL
940 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL
941 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 0x3UL
942 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_LAST FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF
943 u8 unused_0;
944 };
945
946 /* hwrm_func_reset_output (size:128b/16B) */
947 struct hwrm_func_reset_output {
948 __le16 error_code;
949 __le16 req_type;
950 __le16 seq_id;
951 __le16 resp_len;
952 u8 unused_0[7];
953 u8 valid;
954 };
955
956 /* hwrm_func_getfid_input (size:192b/24B) */
957 struct hwrm_func_getfid_input {
958 __le16 req_type;
959 __le16 cmpl_ring;
960 __le16 seq_id;
961 __le16 target_id;
962 __le64 resp_addr;
963 __le32 enables;
964 #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL
965 __le16 pci_id;
966 u8 unused_0[2];
967 };
968
969 /* hwrm_func_getfid_output (size:128b/16B) */
970 struct hwrm_func_getfid_output {
971 __le16 error_code;
972 __le16 req_type;
973 __le16 seq_id;
974 __le16 resp_len;
975 __le16 fid;
976 u8 unused_0[5];
977 u8 valid;
978 };
979
980 /* hwrm_func_vf_alloc_input (size:192b/24B) */
981 struct hwrm_func_vf_alloc_input {
982 __le16 req_type;
983 __le16 cmpl_ring;
984 __le16 seq_id;
985 __le16 target_id;
986 __le64 resp_addr;
987 __le32 enables;
988 #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL
989 __le16 first_vf_id;
990 __le16 num_vfs;
991 };
992
993 /* hwrm_func_vf_alloc_output (size:128b/16B) */
994 struct hwrm_func_vf_alloc_output {
995 __le16 error_code;
996 __le16 req_type;
997 __le16 seq_id;
998 __le16 resp_len;
999 __le16 first_vf_id;
1000 u8 unused_0[5];
1001 u8 valid;
1002 };
1003
1004 /* hwrm_func_vf_free_input (size:192b/24B) */
1005 struct hwrm_func_vf_free_input {
1006 __le16 req_type;
1007 __le16 cmpl_ring;
1008 __le16 seq_id;
1009 __le16 target_id;
1010 __le64 resp_addr;
1011 __le32 enables;
1012 #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL
1013 __le16 first_vf_id;
1014 __le16 num_vfs;
1015 };
1016
1017 /* hwrm_func_vf_free_output (size:128b/16B) */
1018 struct hwrm_func_vf_free_output {
1019 __le16 error_code;
1020 __le16 req_type;
1021 __le16 seq_id;
1022 __le16 resp_len;
1023 u8 unused_0[7];
1024 u8 valid;
1025 };
1026
1027 /* hwrm_func_vf_cfg_input (size:448b/56B) */
1028 struct hwrm_func_vf_cfg_input {
1029 __le16 req_type;
1030 __le16 cmpl_ring;
1031 __le16 seq_id;
1032 __le16 target_id;
1033 __le64 resp_addr;
1034 __le32 enables;
1035 #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL
1036 #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL
1037 #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL
1038 #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL
1039 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x10UL
1040 #define FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x20UL
1041 #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS 0x40UL
1042 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS 0x80UL
1043 #define FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS 0x100UL
1044 #define FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS 0x200UL
1045 #define FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x400UL
1046 #define FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x800UL
1047 __le16 mtu;
1048 __le16 guest_vlan;
1049 __le16 async_event_cr;
1050 u8 dflt_mac_addr[6];
1051 __le32 flags;
1052 #define FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x1UL
1053 #define FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x2UL
1054 #define FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x4UL
1055 #define FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x8UL
1056 #define FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x10UL
1057 #define FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x20UL
1058 #define FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x40UL
1059 #define FUNC_VF_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x80UL
1060 __le16 num_rsscos_ctxs;
1061 __le16 num_cmpl_rings;
1062 __le16 num_tx_rings;
1063 __le16 num_rx_rings;
1064 __le16 num_l2_ctxs;
1065 __le16 num_vnics;
1066 __le16 num_stat_ctxs;
1067 __le16 num_hw_ring_grps;
1068 u8 unused_0[4];
1069 };
1070
1071 /* hwrm_func_vf_cfg_output (size:128b/16B) */
1072 struct hwrm_func_vf_cfg_output {
1073 __le16 error_code;
1074 __le16 req_type;
1075 __le16 seq_id;
1076 __le16 resp_len;
1077 u8 unused_0[7];
1078 u8 valid;
1079 };
1080
1081 /* hwrm_func_qcaps_input (size:192b/24B) */
1082 struct hwrm_func_qcaps_input {
1083 __le16 req_type;
1084 __le16 cmpl_ring;
1085 __le16 seq_id;
1086 __le16 target_id;
1087 __le64 resp_addr;
1088 __le16 fid;
1089 u8 unused_0[6];
1090 };
1091
1092 /* hwrm_func_qcaps_output (size:640b/80B) */
1093 struct hwrm_func_qcaps_output {
1094 __le16 error_code;
1095 __le16 req_type;
1096 __le16 seq_id;
1097 __le16 resp_len;
1098 __le16 fid;
1099 __le16 port_id;
1100 __le32 flags;
1101 #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL
1102 #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL
1103 #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL
1104 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL
1105 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL
1106 #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL
1107 #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL
1108 #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL
1109 #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL
1110 #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL
1111 #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL
1112 #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL
1113 #define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED 0x1000UL
1114 #define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED 0x2000UL
1115 #define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED 0x4000UL
1116 #define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED 0x8000UL
1117 #define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED 0x10000UL
1118 #define FUNC_QCAPS_RESP_FLAGS_ADOPTED_PF_SUPPORTED 0x20000UL
1119 #define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED 0x40000UL
1120 #define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED 0x80000UL
1121 #define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE 0x100000UL
1122 #define FUNC_QCAPS_RESP_FLAGS_DYNAMIC_TX_RING_ALLOC 0x200000UL
1123 #define FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE 0x400000UL
1124 #define FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE 0x800000UL
1125 #define FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED 0x1000000UL
1126 #define FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD 0x2000000UL
1127 #define FUNC_QCAPS_RESP_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED 0x4000000UL
1128 #define FUNC_QCAPS_RESP_FLAGS_VLAN_ACCELERATION_TX_DISABLED 0x8000000UL
1129 u8 mac_address[6];
1130 __le16 max_rsscos_ctx;
1131 __le16 max_cmpl_rings;
1132 __le16 max_tx_rings;
1133 __le16 max_rx_rings;
1134 __le16 max_l2_ctxs;
1135 __le16 max_vnics;
1136 __le16 first_vf_id;
1137 __le16 max_vfs;
1138 __le16 max_stat_ctx;
1139 __le32 max_encap_records;
1140 __le32 max_decap_records;
1141 __le32 max_tx_em_flows;
1142 __le32 max_tx_wm_flows;
1143 __le32 max_rx_em_flows;
1144 __le32 max_rx_wm_flows;
1145 __le32 max_mcast_filters;
1146 __le32 max_flow_id;
1147 __le32 max_hw_ring_grps;
1148 __le16 max_sp_tx_rings;
1149 u8 unused_0;
1150 u8 valid;
1151 };
1152
1153 /* hwrm_func_qcfg_input (size:192b/24B) */
1154 struct hwrm_func_qcfg_input {
1155 __le16 req_type;
1156 __le16 cmpl_ring;
1157 __le16 seq_id;
1158 __le16 target_id;
1159 __le64 resp_addr;
1160 __le16 fid;
1161 u8 unused_0[6];
1162 };
1163
1164 /* hwrm_func_qcfg_output (size:704b/88B) */
1165 struct hwrm_func_qcfg_output {
1166 __le16 error_code;
1167 __le16 req_type;
1168 __le16 seq_id;
1169 __le16 resp_len;
1170 __le16 fid;
1171 __le16 port_id;
1172 __le16 vlan;
1173 __le16 flags;
1174 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED 0x1UL
1175 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED 0x2UL
1176 #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED 0x4UL
1177 #define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED 0x8UL
1178 #define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED 0x10UL
1179 #define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL
1180 #define FUNC_QCFG_RESP_FLAGS_TRUSTED_VF 0x40UL
1181 #define FUNC_QCFG_RESP_FLAGS_SECURE_MODE_ENABLED 0x80UL
1182 #define FUNC_QCFG_RESP_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x100UL
1183 u8 mac_address[6];
1184 __le16 pci_id;
1185 __le16 alloc_rsscos_ctx;
1186 __le16 alloc_cmpl_rings;
1187 __le16 alloc_tx_rings;
1188 __le16 alloc_rx_rings;
1189 __le16 alloc_l2_ctx;
1190 __le16 alloc_vnics;
1191 __le16 mtu;
1192 __le16 mru;
1193 __le16 stat_ctx_id;
1194 u8 port_partition_type;
1195 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF 0x0UL
1196 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS 0x1UL
1197 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL
1198 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL
1199 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL
1200 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL
1201 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_LAST FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN
1202 u8 port_pf_cnt;
1203 #define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL
1204 #define FUNC_QCFG_RESP_PORT_PF_CNT_LAST FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL
1205 __le16 dflt_vnic_id;
1206 __le16 max_mtu_configured;
1207 __le32 min_bw;
1208 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK 0xfffffffUL
1209 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT 0
1210 #define FUNC_QCFG_RESP_MIN_BW_SCALE 0x10000000UL
1211 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS (0x0UL << 28)
1212 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES (0x1UL << 28)
1213 #define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES
1214 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
1215 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT 29
1216 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
1217 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
1218 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
1219 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
1220 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
1221 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
1222 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID
1223 __le32 max_bw;
1224 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK 0xfffffffUL
1225 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT 0
1226 #define FUNC_QCFG_RESP_MAX_BW_SCALE 0x10000000UL
1227 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS (0x0UL << 28)
1228 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES (0x1UL << 28)
1229 #define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES
1230 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
1231 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT 29
1232 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
1233 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
1234 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
1235 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
1236 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
1237 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
1238 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID
1239 u8 evb_mode;
1240 #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL
1241 #define FUNC_QCFG_RESP_EVB_MODE_VEB 0x1UL
1242 #define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL
1243 #define FUNC_QCFG_RESP_EVB_MODE_LAST FUNC_QCFG_RESP_EVB_MODE_VEPA
1244 u8 options;
1245 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_MASK 0x3UL
1246 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SFT 0
1247 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL
1248 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL
1249 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_LAST FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128
1250 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL
1251 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_SFT 2
1252 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2)
1253 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2)
1254 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2)
1255 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO
1256 #define FUNC_QCFG_RESP_OPTIONS_RSVD_MASK 0xf0UL
1257 #define FUNC_QCFG_RESP_OPTIONS_RSVD_SFT 4
1258 __le16 alloc_vfs;
1259 __le32 alloc_mcast_filters;
1260 __le32 alloc_hw_ring_grps;
1261 __le16 alloc_sp_tx_rings;
1262 __le16 alloc_stat_ctx;
1263 __le16 alloc_msix;
1264 __le16 registered_vfs;
1265 __le16 l2_doorbell_bar_size_kb;
1266 u8 unused_1;
1267 u8 always_1;
1268 __le32 reset_addr_poll;
1269 __le16 legacy_l2_db_size_kb;
1270 u8 unused_2[1];
1271 u8 valid;
1272 };
1273
1274 /* hwrm_func_cfg_input (size:704b/88B) */
1275 struct hwrm_func_cfg_input {
1276 __le16 req_type;
1277 __le16 cmpl_ring;
1278 __le16 seq_id;
1279 __le16 target_id;
1280 __le64 resp_addr;
1281 __le16 fid;
1282 __le16 num_msix;
1283 __le32 flags;
1284 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE 0x1UL
1285 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE 0x2UL
1286 #define FUNC_CFG_REQ_FLAGS_RSVD_MASK 0x1fcUL
1287 #define FUNC_CFG_REQ_FLAGS_RSVD_SFT 2
1288 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE 0x200UL
1289 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE 0x400UL
1290 #define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST 0x800UL
1291 #define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC 0x1000UL
1292 #define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x2000UL
1293 #define FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x4000UL
1294 #define FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x8000UL
1295 #define FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x10000UL
1296 #define FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x20000UL
1297 #define FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x40000UL
1298 #define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x80000UL
1299 #define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x100000UL
1300 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_ENABLE 0x200000UL
1301 #define FUNC_CFG_REQ_FLAGS_DYNAMIC_TX_RING_ALLOC 0x400000UL
1302 #define FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST 0x800000UL
1303 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_DISABLE 0x1000000UL
1304 #define FUNC_CFG_REQ_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x2000000UL
1305 __le32 enables;
1306 #define FUNC_CFG_REQ_ENABLES_MTU 0x1UL
1307 #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL
1308 #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL
1309 #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL
1310 #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL
1311 #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL
1312 #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL
1313 #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL
1314 #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL
1315 #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL
1316 #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL
1317 #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL
1318 #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL
1319 #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL
1320 #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL
1321 #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL
1322 #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL
1323 #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL
1324 #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL
1325 #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL
1326 #define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE 0x100000UL
1327 #define FUNC_CFG_REQ_ENABLES_NUM_MSIX 0x200000UL
1328 #define FUNC_CFG_REQ_ENABLES_ADMIN_LINK_STATE 0x400000UL
1329 __le16 mtu;
1330 __le16 mru;
1331 __le16 num_rsscos_ctxs;
1332 __le16 num_cmpl_rings;
1333 __le16 num_tx_rings;
1334 __le16 num_rx_rings;
1335 __le16 num_l2_ctxs;
1336 __le16 num_vnics;
1337 __le16 num_stat_ctxs;
1338 __le16 num_hw_ring_grps;
1339 u8 dflt_mac_addr[6];
1340 __le16 dflt_vlan;
1341 __be32 dflt_ip_addr[4];
1342 __le32 min_bw;
1343 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK 0xfffffffUL
1344 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT 0
1345 #define FUNC_CFG_REQ_MIN_BW_SCALE 0x10000000UL
1346 #define FUNC_CFG_REQ_MIN_BW_SCALE_BITS (0x0UL << 28)
1347 #define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES (0x1UL << 28)
1348 #define FUNC_CFG_REQ_MIN_BW_SCALE_LAST FUNC_CFG_REQ_MIN_BW_SCALE_BYTES
1349 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
1350 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT 29
1351 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
1352 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
1353 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
1354 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
1355 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
1356 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
1357 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID
1358 __le32 max_bw;
1359 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL
1360 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT 0
1361 #define FUNC_CFG_REQ_MAX_BW_SCALE 0x10000000UL
1362 #define FUNC_CFG_REQ_MAX_BW_SCALE_BITS (0x0UL << 28)
1363 #define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28)
1364 #define FUNC_CFG_REQ_MAX_BW_SCALE_LAST FUNC_CFG_REQ_MAX_BW_SCALE_BYTES
1365 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
1366 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29
1367 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
1368 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
1369 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
1370 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
1371 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
1372 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
1373 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID
1374 __le16 async_event_cr;
1375 u8 vlan_antispoof_mode;
1376 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK 0x0UL
1377 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN 0x1UL
1378 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE 0x2UL
1379 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL
1380 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_LAST FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN
1381 u8 allowed_vlan_pris;
1382 u8 evb_mode;
1383 #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL
1384 #define FUNC_CFG_REQ_EVB_MODE_VEB 0x1UL
1385 #define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL
1386 #define FUNC_CFG_REQ_EVB_MODE_LAST FUNC_CFG_REQ_EVB_MODE_VEPA
1387 u8 options;
1388 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_MASK 0x3UL
1389 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SFT 0
1390 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL
1391 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL
1392 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_LAST FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128
1393 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL
1394 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_SFT 2
1395 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2)
1396 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2)
1397 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2)
1398 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO
1399 #define FUNC_CFG_REQ_OPTIONS_RSVD_MASK 0xf0UL
1400 #define FUNC_CFG_REQ_OPTIONS_RSVD_SFT 4
1401 __le16 num_mcast_filters;
1402 };
1403
1404 /* hwrm_func_cfg_output (size:128b/16B) */
1405 struct hwrm_func_cfg_output {
1406 __le16 error_code;
1407 __le16 req_type;
1408 __le16 seq_id;
1409 __le16 resp_len;
1410 u8 unused_0[7];
1411 u8 valid;
1412 };
1413
1414 /* hwrm_func_qstats_input (size:192b/24B) */
1415 struct hwrm_func_qstats_input {
1416 __le16 req_type;
1417 __le16 cmpl_ring;
1418 __le16 seq_id;
1419 __le16 target_id;
1420 __le64 resp_addr;
1421 __le16 fid;
1422 u8 flags;
1423 #define FUNC_QSTATS_REQ_FLAGS_UNUSED 0x0UL
1424 #define FUNC_QSTATS_REQ_FLAGS_ROCE_ONLY 0x1UL
1425 #define FUNC_QSTATS_REQ_FLAGS_LAST FUNC_QSTATS_REQ_FLAGS_ROCE_ONLY
1426 u8 unused_0[5];
1427 };
1428
1429 /* hwrm_func_qstats_output (size:1408b/176B) */
1430 struct hwrm_func_qstats_output {
1431 __le16 error_code;
1432 __le16 req_type;
1433 __le16 seq_id;
1434 __le16 resp_len;
1435 __le64 tx_ucast_pkts;
1436 __le64 tx_mcast_pkts;
1437 __le64 tx_bcast_pkts;
1438 __le64 tx_discard_pkts;
1439 __le64 tx_drop_pkts;
1440 __le64 tx_ucast_bytes;
1441 __le64 tx_mcast_bytes;
1442 __le64 tx_bcast_bytes;
1443 __le64 rx_ucast_pkts;
1444 __le64 rx_mcast_pkts;
1445 __le64 rx_bcast_pkts;
1446 __le64 rx_discard_pkts;
1447 __le64 rx_drop_pkts;
1448 __le64 rx_ucast_bytes;
1449 __le64 rx_mcast_bytes;
1450 __le64 rx_bcast_bytes;
1451 __le64 rx_agg_pkts;
1452 __le64 rx_agg_bytes;
1453 __le64 rx_agg_events;
1454 __le64 rx_agg_aborts;
1455 u8 unused_0[7];
1456 u8 valid;
1457 };
1458
1459 /* hwrm_func_clr_stats_input (size:192b/24B) */
1460 struct hwrm_func_clr_stats_input {
1461 __le16 req_type;
1462 __le16 cmpl_ring;
1463 __le16 seq_id;
1464 __le16 target_id;
1465 __le64 resp_addr;
1466 __le16 fid;
1467 u8 unused_0[6];
1468 };
1469
1470 /* hwrm_func_clr_stats_output (size:128b/16B) */
1471 struct hwrm_func_clr_stats_output {
1472 __le16 error_code;
1473 __le16 req_type;
1474 __le16 seq_id;
1475 __le16 resp_len;
1476 u8 unused_0[7];
1477 u8 valid;
1478 };
1479
1480 /* hwrm_func_vf_resc_free_input (size:192b/24B) */
1481 struct hwrm_func_vf_resc_free_input {
1482 __le16 req_type;
1483 __le16 cmpl_ring;
1484 __le16 seq_id;
1485 __le16 target_id;
1486 __le64 resp_addr;
1487 __le16 vf_id;
1488 u8 unused_0[6];
1489 };
1490
1491 /* hwrm_func_vf_resc_free_output (size:128b/16B) */
1492 struct hwrm_func_vf_resc_free_output {
1493 __le16 error_code;
1494 __le16 req_type;
1495 __le16 seq_id;
1496 __le16 resp_len;
1497 u8 unused_0[7];
1498 u8 valid;
1499 };
1500
1501 /* hwrm_func_drv_rgtr_input (size:896b/112B) */
1502 struct hwrm_func_drv_rgtr_input {
1503 __le16 req_type;
1504 __le16 cmpl_ring;
1505 __le16 seq_id;
1506 __le16 target_id;
1507 __le64 resp_addr;
1508 __le32 flags;
1509 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL
1510 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL
1511 #define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE 0x4UL
1512 #define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE 0x8UL
1513 #define FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT 0x10UL
1514 #define FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT 0x20UL
1515 #define FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT 0x40UL
1516 __le32 enables;
1517 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL
1518 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL
1519 #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL
1520 #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL
1521 #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL
1522 __le16 os_type;
1523 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN 0x0UL
1524 #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL
1525 #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS 0xeUL
1526 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS 0x12UL
1527 #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS 0x1dUL
1528 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX 0x24UL
1529 #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD 0x2aUL
1530 #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI 0x68UL
1531 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 0x73UL
1532 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL
1533 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 0x8000UL
1534 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LAST FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI
1535 u8 ver_maj_8b;
1536 u8 ver_min_8b;
1537 u8 ver_upd_8b;
1538 u8 unused_0[3];
1539 __le32 timestamp;
1540 u8 unused_1[4];
1541 __le32 vf_req_fwd[8];
1542 __le32 async_event_fwd[8];
1543 __le16 ver_maj;
1544 __le16 ver_min;
1545 __le16 ver_upd;
1546 __le16 ver_patch;
1547 };
1548
1549 /* hwrm_func_drv_rgtr_output (size:128b/16B) */
1550 struct hwrm_func_drv_rgtr_output {
1551 __le16 error_code;
1552 __le16 req_type;
1553 __le16 seq_id;
1554 __le16 resp_len;
1555 __le32 flags;
1556 #define FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED 0x1UL
1557 u8 unused_0[3];
1558 u8 valid;
1559 };
1560
1561 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */
1562 struct hwrm_func_drv_unrgtr_input {
1563 __le16 req_type;
1564 __le16 cmpl_ring;
1565 __le16 seq_id;
1566 __le16 target_id;
1567 __le64 resp_addr;
1568 __le32 flags;
1569 #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL
1570 u8 unused_0[4];
1571 };
1572
1573 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */
1574 struct hwrm_func_drv_unrgtr_output {
1575 __le16 error_code;
1576 __le16 req_type;
1577 __le16 seq_id;
1578 __le16 resp_len;
1579 u8 unused_0[7];
1580 u8 valid;
1581 };
1582
1583 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */
1584 struct hwrm_func_buf_rgtr_input {
1585 __le16 req_type;
1586 __le16 cmpl_ring;
1587 __le16 seq_id;
1588 __le16 target_id;
1589 __le64 resp_addr;
1590 __le32 enables;
1591 #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL
1592 #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL
1593 __le16 vf_id;
1594 __le16 req_buf_num_pages;
1595 __le16 req_buf_page_size;
1596 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL
1597 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K 0xcUL
1598 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K 0xdUL
1599 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL
1600 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M 0x15UL
1601 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M 0x16UL
1602 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 0x1eUL
1603 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_LAST FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G
1604 __le16 req_buf_len;
1605 __le16 resp_buf_len;
1606 u8 unused_0[2];
1607 __le64 req_buf_page_addr0;
1608 __le64 req_buf_page_addr1;
1609 __le64 req_buf_page_addr2;
1610 __le64 req_buf_page_addr3;
1611 __le64 req_buf_page_addr4;
1612 __le64 req_buf_page_addr5;
1613 __le64 req_buf_page_addr6;
1614 __le64 req_buf_page_addr7;
1615 __le64 req_buf_page_addr8;
1616 __le64 req_buf_page_addr9;
1617 __le64 error_buf_addr;
1618 __le64 resp_buf_addr;
1619 };
1620
1621 /* hwrm_func_buf_rgtr_output (size:128b/16B) */
1622 struct hwrm_func_buf_rgtr_output {
1623 __le16 error_code;
1624 __le16 req_type;
1625 __le16 seq_id;
1626 __le16 resp_len;
1627 u8 unused_0[7];
1628 u8 valid;
1629 };
1630
1631 /* hwrm_func_drv_qver_input (size:192b/24B) */
1632 struct hwrm_func_drv_qver_input {
1633 __le16 req_type;
1634 __le16 cmpl_ring;
1635 __le16 seq_id;
1636 __le16 target_id;
1637 __le64 resp_addr;
1638 __le32 reserved;
1639 __le16 fid;
1640 u8 unused_0[2];
1641 };
1642
1643 /* hwrm_func_drv_qver_output (size:256b/32B) */
1644 struct hwrm_func_drv_qver_output {
1645 __le16 error_code;
1646 __le16 req_type;
1647 __le16 seq_id;
1648 __le16 resp_len;
1649 __le16 os_type;
1650 #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN 0x0UL
1651 #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER 0x1UL
1652 #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS 0xeUL
1653 #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS 0x12UL
1654 #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS 0x1dUL
1655 #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX 0x24UL
1656 #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD 0x2aUL
1657 #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI 0x68UL
1658 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 0x73UL
1659 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL
1660 #define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 0x8000UL
1661 #define FUNC_DRV_QVER_RESP_OS_TYPE_LAST FUNC_DRV_QVER_RESP_OS_TYPE_UEFI
1662 u8 ver_maj_8b;
1663 u8 ver_min_8b;
1664 u8 ver_upd_8b;
1665 u8 unused_0[3];
1666 __le16 ver_maj;
1667 __le16 ver_min;
1668 __le16 ver_upd;
1669 __le16 ver_patch;
1670 u8 unused_1[7];
1671 u8 valid;
1672 };
1673
1674 /* hwrm_func_resource_qcaps_input (size:192b/24B) */
1675 struct hwrm_func_resource_qcaps_input {
1676 __le16 req_type;
1677 __le16 cmpl_ring;
1678 __le16 seq_id;
1679 __le16 target_id;
1680 __le64 resp_addr;
1681 __le16 fid;
1682 u8 unused_0[6];
1683 };
1684
1685 /* hwrm_func_resource_qcaps_output (size:448b/56B) */
1686 struct hwrm_func_resource_qcaps_output {
1687 __le16 error_code;
1688 __le16 req_type;
1689 __le16 seq_id;
1690 __le16 resp_len;
1691 __le16 max_vfs;
1692 __le16 max_msix;
1693 __le16 vf_reservation_strategy;
1694 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MAXIMAL 0x0UL
1695 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL 0x1UL
1696 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 0x2UL
1697 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_LAST FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC
1698 __le16 min_rsscos_ctx;
1699 __le16 max_rsscos_ctx;
1700 __le16 min_cmpl_rings;
1701 __le16 max_cmpl_rings;
1702 __le16 min_tx_rings;
1703 __le16 max_tx_rings;
1704 __le16 min_rx_rings;
1705 __le16 max_rx_rings;
1706 __le16 min_l2_ctxs;
1707 __le16 max_l2_ctxs;
1708 __le16 min_vnics;
1709 __le16 max_vnics;
1710 __le16 min_stat_ctx;
1711 __le16 max_stat_ctx;
1712 __le16 min_hw_ring_grps;
1713 __le16 max_hw_ring_grps;
1714 __le16 max_tx_scheduler_inputs;
1715 __le16 flags;
1716 #define FUNC_RESOURCE_QCAPS_RESP_FLAGS_MIN_GUARANTEED 0x1UL
1717 u8 unused_0[5];
1718 u8 valid;
1719 };
1720
1721 /* hwrm_func_vf_resource_cfg_input (size:448b/56B) */
1722 struct hwrm_func_vf_resource_cfg_input {
1723 __le16 req_type;
1724 __le16 cmpl_ring;
1725 __le16 seq_id;
1726 __le16 target_id;
1727 __le64 resp_addr;
1728 __le16 vf_id;
1729 __le16 max_msix;
1730 __le16 min_rsscos_ctx;
1731 __le16 max_rsscos_ctx;
1732 __le16 min_cmpl_rings;
1733 __le16 max_cmpl_rings;
1734 __le16 min_tx_rings;
1735 __le16 max_tx_rings;
1736 __le16 min_rx_rings;
1737 __le16 max_rx_rings;
1738 __le16 min_l2_ctxs;
1739 __le16 max_l2_ctxs;
1740 __le16 min_vnics;
1741 __le16 max_vnics;
1742 __le16 min_stat_ctx;
1743 __le16 max_stat_ctx;
1744 __le16 min_hw_ring_grps;
1745 __le16 max_hw_ring_grps;
1746 __le16 flags;
1747 #define FUNC_VF_RESOURCE_CFG_REQ_FLAGS_MIN_GUARANTEED 0x1UL
1748 u8 unused_0[2];
1749 };
1750
1751 /* hwrm_func_vf_resource_cfg_output (size:256b/32B) */
1752 struct hwrm_func_vf_resource_cfg_output {
1753 __le16 error_code;
1754 __le16 req_type;
1755 __le16 seq_id;
1756 __le16 resp_len;
1757 __le16 reserved_rsscos_ctx;
1758 __le16 reserved_cmpl_rings;
1759 __le16 reserved_tx_rings;
1760 __le16 reserved_rx_rings;
1761 __le16 reserved_l2_ctxs;
1762 __le16 reserved_vnics;
1763 __le16 reserved_stat_ctx;
1764 __le16 reserved_hw_ring_grps;
1765 u8 unused_0[7];
1766 u8 valid;
1767 };
1768
1769 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */
1770 struct hwrm_func_backing_store_qcaps_input {
1771 __le16 req_type;
1772 __le16 cmpl_ring;
1773 __le16 seq_id;
1774 __le16 target_id;
1775 __le64 resp_addr;
1776 };
1777
1778 /* hwrm_func_backing_store_qcaps_output (size:640b/80B) */
1779 struct hwrm_func_backing_store_qcaps_output {
1780 __le16 error_code;
1781 __le16 req_type;
1782 __le16 seq_id;
1783 __le16 resp_len;
1784 __le32 qp_max_entries;
1785 __le16 qp_min_qp1_entries;
1786 __le16 qp_max_l2_entries;
1787 __le16 qp_entry_size;
1788 __le16 srq_max_l2_entries;
1789 __le32 srq_max_entries;
1790 __le16 srq_entry_size;
1791 __le16 cq_max_l2_entries;
1792 __le32 cq_max_entries;
1793 __le16 cq_entry_size;
1794 __le16 vnic_max_vnic_entries;
1795 __le16 vnic_max_ring_table_entries;
1796 __le16 vnic_entry_size;
1797 __le32 stat_max_entries;
1798 __le16 stat_entry_size;
1799 __le16 tqm_entry_size;
1800 __le32 tqm_min_entries_per_ring;
1801 __le32 tqm_max_entries_per_ring;
1802 __le32 mrav_max_entries;
1803 __le16 mrav_entry_size;
1804 __le16 tim_entry_size;
1805 __le32 tim_max_entries;
1806 __le16 mrav_num_entries_units;
1807 u8 tqm_entries_multiple;
1808 u8 ctx_kind_initializer;
1809 __le32 rsvd;
1810 __le16 rsvd1;
1811 u8 rsvd2;
1812 u8 valid;
1813 };
1814
1815 /* hwrm_func_backing_store_cfg_input (size:2048b/256B) */
1816 struct hwrm_func_backing_store_cfg_input {
1817 __le16 req_type;
1818 __le16 cmpl_ring;
1819 __le16 seq_id;
1820 __le16 target_id;
1821 __le64 resp_addr;
1822 __le32 flags;
1823 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE 0x1UL
1824 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT 0x2UL
1825 __le32 enables;
1826 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP 0x1UL
1827 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ 0x2UL
1828 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ 0x4UL
1829 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC 0x8UL
1830 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT 0x10UL
1831 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP 0x20UL
1832 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING0 0x40UL
1833 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING1 0x80UL
1834 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING2 0x100UL
1835 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING3 0x200UL
1836 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING4 0x400UL
1837 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING5 0x800UL
1838 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING6 0x1000UL
1839 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING7 0x2000UL
1840 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV 0x4000UL
1841 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM 0x8000UL
1842 u8 qpc_pg_size_qpc_lvl;
1843 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_MASK 0xfUL
1844 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_SFT 0
1845 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_0 0x0UL
1846 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_1 0x1UL
1847 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 0x2UL
1848 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2
1849 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_MASK 0xf0UL
1850 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_SFT 4
1851 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K (0x0UL << 4)
1852 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8K (0x1UL << 4)
1853 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K (0x2UL << 4)
1854 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_2M (0x3UL << 4)
1855 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8M (0x4UL << 4)
1856 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G (0x5UL << 4)
1857 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G
1858 u8 srq_pg_size_srq_lvl;
1859 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_MASK 0xfUL
1860 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_SFT 0
1861 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_0 0x0UL
1862 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_1 0x1UL
1863 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 0x2UL
1864 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2
1865 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_MASK 0xf0UL
1866 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_SFT 4
1867 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_4K (0x0UL << 4)
1868 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K (0x1UL << 4)
1869 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_64K (0x2UL << 4)
1870 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_2M (0x3UL << 4)
1871 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8M (0x4UL << 4)
1872 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G (0x5UL << 4)
1873 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G
1874 u8 cq_pg_size_cq_lvl;
1875 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_MASK 0xfUL
1876 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_SFT 0
1877 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_0 0x0UL
1878 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_1 0x1UL
1879 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 0x2UL
1880 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2
1881 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_MASK 0xf0UL
1882 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_SFT 4
1883 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_4K (0x0UL << 4)
1884 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8K (0x1UL << 4)
1885 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_64K (0x2UL << 4)
1886 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_2M (0x3UL << 4)
1887 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8M (0x4UL << 4)
1888 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G (0x5UL << 4)
1889 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G
1890 u8 vnic_pg_size_vnic_lvl;
1891 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_MASK 0xfUL
1892 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_SFT 0
1893 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_0 0x0UL
1894 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_1 0x1UL
1895 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 0x2UL
1896 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2
1897 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_MASK 0xf0UL
1898 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_SFT 4
1899 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_4K (0x0UL << 4)
1900 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8K (0x1UL << 4)
1901 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_64K (0x2UL << 4)
1902 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_2M (0x3UL << 4)
1903 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8M (0x4UL << 4)
1904 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G (0x5UL << 4)
1905 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G
1906 u8 stat_pg_size_stat_lvl;
1907 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_MASK 0xfUL
1908 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_SFT 0
1909 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_0 0x0UL
1910 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_1 0x1UL
1911 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 0x2UL
1912 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2
1913 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_MASK 0xf0UL
1914 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_SFT 4
1915 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_4K (0x0UL << 4)
1916 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8K (0x1UL << 4)
1917 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_64K (0x2UL << 4)
1918 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_2M (0x3UL << 4)
1919 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8M (0x4UL << 4)
1920 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G (0x5UL << 4)
1921 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G
1922 u8 tqm_sp_pg_size_tqm_sp_lvl;
1923 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_MASK 0xfUL
1924 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_SFT 0
1925 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_0 0x0UL
1926 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_1 0x1UL
1927 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 0x2UL
1928 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2
1929 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_MASK 0xf0UL
1930 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_SFT 4
1931 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_4K (0x0UL << 4)
1932 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8K (0x1UL << 4)
1933 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_64K (0x2UL << 4)
1934 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_2M (0x3UL << 4)
1935 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8M (0x4UL << 4)
1936 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G (0x5UL << 4)
1937 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G
1938 u8 tqm_ring0_pg_size_tqm_ring0_lvl;
1939 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_MASK 0xfUL
1940 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_SFT 0
1941 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_0 0x0UL
1942 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_1 0x1UL
1943 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 0x2UL
1944 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2
1945 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_MASK 0xf0UL
1946 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_SFT 4
1947 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_4K (0x0UL << 4)
1948 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8K (0x1UL << 4)
1949 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_64K (0x2UL << 4)
1950 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_2M (0x3UL << 4)
1951 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8M (0x4UL << 4)
1952 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G (0x5UL << 4)
1953 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G
1954 u8 tqm_ring1_pg_size_tqm_ring1_lvl;
1955 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_MASK 0xfUL
1956 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_SFT 0
1957 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_0 0x0UL
1958 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_1 0x1UL
1959 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 0x2UL
1960 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2
1961 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_MASK 0xf0UL
1962 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_SFT 4
1963 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_4K (0x0UL << 4)
1964 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8K (0x1UL << 4)
1965 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_64K (0x2UL << 4)
1966 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_2M (0x3UL << 4)
1967 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8M (0x4UL << 4)
1968 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G (0x5UL << 4)
1969 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G
1970 u8 tqm_ring2_pg_size_tqm_ring2_lvl;
1971 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_MASK 0xfUL
1972 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_SFT 0
1973 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_0 0x0UL
1974 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_1 0x1UL
1975 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 0x2UL
1976 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2
1977 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_MASK 0xf0UL
1978 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_SFT 4
1979 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_4K (0x0UL << 4)
1980 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8K (0x1UL << 4)
1981 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_64K (0x2UL << 4)
1982 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_2M (0x3UL << 4)
1983 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8M (0x4UL << 4)
1984 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G (0x5UL << 4)
1985 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G
1986 u8 tqm_ring3_pg_size_tqm_ring3_lvl;
1987 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_MASK 0xfUL
1988 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_SFT 0
1989 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_0 0x0UL
1990 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_1 0x1UL
1991 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 0x2UL
1992 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2
1993 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_MASK 0xf0UL
1994 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_SFT 4
1995 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_4K (0x0UL << 4)
1996 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8K (0x1UL << 4)
1997 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_64K (0x2UL << 4)
1998 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_2M (0x3UL << 4)
1999 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8M (0x4UL << 4)
2000 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G (0x5UL << 4)
2001 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G
2002 u8 tqm_ring4_pg_size_tqm_ring4_lvl;
2003 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_MASK 0xfUL
2004 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_SFT 0
2005 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_0 0x0UL
2006 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_1 0x1UL
2007 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 0x2UL
2008 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2
2009 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_MASK 0xf0UL
2010 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_SFT 4
2011 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_4K (0x0UL << 4)
2012 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8K (0x1UL << 4)
2013 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_64K (0x2UL << 4)
2014 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_2M (0x3UL << 4)
2015 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8M (0x4UL << 4)
2016 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G (0x5UL << 4)
2017 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G
2018 u8 tqm_ring5_pg_size_tqm_ring5_lvl;
2019 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_MASK 0xfUL
2020 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_SFT 0
2021 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_0 0x0UL
2022 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_1 0x1UL
2023 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 0x2UL
2024 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2
2025 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_MASK 0xf0UL
2026 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_SFT 4
2027 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_4K (0x0UL << 4)
2028 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8K (0x1UL << 4)
2029 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_64K (0x2UL << 4)
2030 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_2M (0x3UL << 4)
2031 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8M (0x4UL << 4)
2032 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G (0x5UL << 4)
2033 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G
2034 u8 tqm_ring6_pg_size_tqm_ring6_lvl;
2035 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_MASK 0xfUL
2036 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_SFT 0
2037 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_0 0x0UL
2038 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_1 0x1UL
2039 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 0x2UL
2040 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2
2041 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_MASK 0xf0UL
2042 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_SFT 4
2043 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_4K (0x0UL << 4)
2044 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8K (0x1UL << 4)
2045 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_64K (0x2UL << 4)
2046 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_2M (0x3UL << 4)
2047 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8M (0x4UL << 4)
2048 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G (0x5UL << 4)
2049 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G
2050 u8 tqm_ring7_pg_size_tqm_ring7_lvl;
2051 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_MASK 0xfUL
2052 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_SFT 0
2053 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_0 0x0UL
2054 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_1 0x1UL
2055 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 0x2UL
2056 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2
2057 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_MASK 0xf0UL
2058 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_SFT 4
2059 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_4K (0x0UL << 4)
2060 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8K (0x1UL << 4)
2061 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_64K (0x2UL << 4)
2062 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_2M (0x3UL << 4)
2063 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8M (0x4UL << 4)
2064 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G (0x5UL << 4)
2065 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G
2066 u8 mrav_pg_size_mrav_lvl;
2067 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_MASK 0xfUL
2068 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_SFT 0
2069 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_0 0x0UL
2070 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_1 0x1UL
2071 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 0x2UL
2072 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2
2073 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_MASK 0xf0UL
2074 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_SFT 4
2075 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_4K (0x0UL << 4)
2076 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8K (0x1UL << 4)
2077 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_64K (0x2UL << 4)
2078 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_2M (0x3UL << 4)
2079 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8M (0x4UL << 4)
2080 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G (0x5UL << 4)
2081 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G
2082 u8 tim_pg_size_tim_lvl;
2083 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_MASK 0xfUL
2084 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_SFT 0
2085 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_0 0x0UL
2086 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_1 0x1UL
2087 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 0x2UL
2088 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2
2089 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_MASK 0xf0UL
2090 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_SFT 4
2091 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_4K (0x0UL << 4)
2092 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8K (0x1UL << 4)
2093 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_64K (0x2UL << 4)
2094 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_2M (0x3UL << 4)
2095 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8M (0x4UL << 4)
2096 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G (0x5UL << 4)
2097 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G
2098 __le64 qpc_page_dir;
2099 __le64 srq_page_dir;
2100 __le64 cq_page_dir;
2101 __le64 vnic_page_dir;
2102 __le64 stat_page_dir;
2103 __le64 tqm_sp_page_dir;
2104 __le64 tqm_ring0_page_dir;
2105 __le64 tqm_ring1_page_dir;
2106 __le64 tqm_ring2_page_dir;
2107 __le64 tqm_ring3_page_dir;
2108 __le64 tqm_ring4_page_dir;
2109 __le64 tqm_ring5_page_dir;
2110 __le64 tqm_ring6_page_dir;
2111 __le64 tqm_ring7_page_dir;
2112 __le64 mrav_page_dir;
2113 __le64 tim_page_dir;
2114 __le32 qp_num_entries;
2115 __le32 srq_num_entries;
2116 __le32 cq_num_entries;
2117 __le32 stat_num_entries;
2118 __le32 tqm_sp_num_entries;
2119 __le32 tqm_ring0_num_entries;
2120 __le32 tqm_ring1_num_entries;
2121 __le32 tqm_ring2_num_entries;
2122 __le32 tqm_ring3_num_entries;
2123 __le32 tqm_ring4_num_entries;
2124 __le32 tqm_ring5_num_entries;
2125 __le32 tqm_ring6_num_entries;
2126 __le32 tqm_ring7_num_entries;
2127 __le32 mrav_num_entries;
2128 __le32 tim_num_entries;
2129 __le16 qp_num_qp1_entries;
2130 __le16 qp_num_l2_entries;
2131 __le16 qp_entry_size;
2132 __le16 srq_num_l2_entries;
2133 __le16 srq_entry_size;
2134 __le16 cq_num_l2_entries;
2135 __le16 cq_entry_size;
2136 __le16 vnic_num_vnic_entries;
2137 __le16 vnic_num_ring_table_entries;
2138 __le16 vnic_entry_size;
2139 __le16 stat_entry_size;
2140 __le16 tqm_entry_size;
2141 __le16 mrav_entry_size;
2142 __le16 tim_entry_size;
2143 };
2144
2145 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */
2146 struct hwrm_func_backing_store_cfg_output {
2147 __le16 error_code;
2148 __le16 req_type;
2149 __le16 seq_id;
2150 __le16 resp_len;
2151 u8 unused_0[7];
2152 u8 valid;
2153 };
2154
2155 /* hwrm_error_recovery_qcfg_input (size:192b/24B) */
2156 struct hwrm_error_recovery_qcfg_input {
2157 __le16 req_type;
2158 __le16 cmpl_ring;
2159 __le16 seq_id;
2160 __le16 target_id;
2161 __le64 resp_addr;
2162 u8 unused_0[8];
2163 };
2164
2165 /* hwrm_error_recovery_qcfg_output (size:1664b/208B) */
2166 struct hwrm_error_recovery_qcfg_output {
2167 __le16 error_code;
2168 __le16 req_type;
2169 __le16 seq_id;
2170 __le16 resp_len;
2171 __le32 flags;
2172 #define ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST 0x1UL
2173 #define ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU 0x2UL
2174 __le32 driver_polling_freq;
2175 __le32 master_func_wait_period;
2176 __le32 normal_func_wait_period;
2177 __le32 master_func_wait_period_after_reset;
2178 __le32 max_bailout_time_after_reset;
2179 __le32 fw_health_status_reg;
2180 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK 0x3UL
2181 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT 0
2182 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG 0x0UL
2183 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC 0x1UL
2184 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 0x2UL
2185 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 0x3UL
2186 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1
2187 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_MASK 0xfffffffcUL
2188 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SFT 2
2189 __le32 fw_heartbeat_reg;
2190 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_MASK 0x3UL
2191 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_SFT 0
2192 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG 0x0UL
2193 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_GRC 0x1UL
2194 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 0x2UL
2195 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 0x3UL
2196 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1
2197 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_MASK 0xfffffffcUL
2198 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SFT 2
2199 __le32 fw_reset_cnt_reg;
2200 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_MASK 0x3UL
2201 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_SFT 0
2202 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL
2203 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_GRC 0x1UL
2204 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 0x2UL
2205 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 0x3UL
2206 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1
2207 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_MASK 0xfffffffcUL
2208 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SFT 2
2209 __le32 reset_inprogress_reg;
2210 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_MASK 0x3UL
2211 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_SFT 0
2212 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG 0x0UL
2213 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_GRC 0x1UL
2214 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 0x2UL
2215 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 0x3UL
2216 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1
2217 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_MASK 0xfffffffcUL
2218 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SFT 2
2219 __le32 reset_inprogress_reg_mask;
2220 u8 unused_0[3];
2221 u8 reg_array_cnt;
2222 __le32 reset_reg[16];
2223 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_MASK 0x3UL
2224 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_SFT 0
2225 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_PCIE_CFG 0x0UL
2226 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_GRC 0x1UL
2227 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR0 0x2UL
2228 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 0x3UL
2229 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1
2230 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_MASK 0xfffffffcUL
2231 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SFT 2
2232 __le32 reset_reg_val[16];
2233 u8 delay_after_reset[16];
2234 u8 unused_1[7];
2235 u8 valid;
2236 };
2237
2238 /* hwrm_func_drv_if_change_input (size:192b/24B) */
2239 struct hwrm_func_drv_if_change_input {
2240 __le16 req_type;
2241 __le16 cmpl_ring;
2242 __le16 seq_id;
2243 __le16 target_id;
2244 __le64 resp_addr;
2245 __le32 flags;
2246 #define FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP 0x1UL
2247 __le32 unused;
2248 };
2249
2250 /* hwrm_func_drv_if_change_output (size:128b/16B) */
2251 struct hwrm_func_drv_if_change_output {
2252 __le16 error_code;
2253 __le16 req_type;
2254 __le16 seq_id;
2255 __le16 resp_len;
2256 __le32 flags;
2257 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE 0x1UL
2258 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE 0x2UL
2259 u8 unused_0[3];
2260 u8 valid;
2261 };
2262
2263 /* hwrm_port_phy_cfg_input (size:448b/56B) */
2264 struct hwrm_port_phy_cfg_input {
2265 __le16 req_type;
2266 __le16 cmpl_ring;
2267 __le16 seq_id;
2268 __le16 target_id;
2269 __le64 resp_addr;
2270 __le32 flags;
2271 #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL
2272 #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED 0x2UL
2273 #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL
2274 #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL
2275 #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL
2276 #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL
2277 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL
2278 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL
2279 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL
2280 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL
2281 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL
2282 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL
2283 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL
2284 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL
2285 #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL
2286 __le32 enables;
2287 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL
2288 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL
2289 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL
2290 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL
2291 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL
2292 #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL
2293 #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL
2294 #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL
2295 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL
2296 #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL
2297 #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL
2298 __le16 port_id;
2299 __le16 force_link_speed;
2300 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL
2301 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL
2302 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB 0x14UL
2303 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL
2304 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL
2305 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB 0xc8UL
2306 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL
2307 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL
2308 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL
2309 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL
2310 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_200GB 0x7d0UL
2311 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 0xffffUL
2312 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB
2313 u8 auto_mode;
2314 #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE 0x0UL
2315 #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS 0x1UL
2316 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED 0x2UL
2317 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL
2318 #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL
2319 #define PORT_PHY_CFG_REQ_AUTO_MODE_LAST PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK
2320 u8 auto_duplex;
2321 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL
2322 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL
2323 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL
2324 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_LAST PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH
2325 u8 auto_pause;
2326 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL
2327 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL
2328 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL
2329 u8 unused_0;
2330 __le16 auto_link_speed;
2331 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL
2332 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB 0xaUL
2333 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB 0x14UL
2334 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL
2335 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB 0x64UL
2336 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB 0xc8UL
2337 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB 0xfaUL
2338 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB 0x190UL
2339 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB 0x1f4UL
2340 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL
2341 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_200GB 0x7d0UL
2342 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 0xffffUL
2343 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_LAST PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB
2344 __le16 auto_link_speed_mask;
2345 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL
2346 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL
2347 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL
2348 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL
2349 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL
2350 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL
2351 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL
2352 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL
2353 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL
2354 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL
2355 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL
2356 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL
2357 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL
2358 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL
2359 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_200GB 0x4000UL
2360 u8 wirespeed;
2361 #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL
2362 #define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL
2363 #define PORT_PHY_CFG_REQ_WIRESPEED_LAST PORT_PHY_CFG_REQ_WIRESPEED_ON
2364 u8 lpbk;
2365 #define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL
2366 #define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL
2367 #define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL
2368 #define PORT_PHY_CFG_REQ_LPBK_EXTERNAL 0x3UL
2369 #define PORT_PHY_CFG_REQ_LPBK_LAST PORT_PHY_CFG_REQ_LPBK_EXTERNAL
2370 u8 force_pause;
2371 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL
2372 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL
2373 u8 unused_1;
2374 __le32 preemphasis;
2375 __le16 eee_link_speed_mask;
2376 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL
2377 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL
2378 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL
2379 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL
2380 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL
2381 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL
2382 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL
2383 u8 unused_2[2];
2384 __le32 tx_lpi_timer;
2385 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL
2386 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0
2387 __le32 unused_3;
2388 };
2389
2390 /* hwrm_port_phy_cfg_output (size:128b/16B) */
2391 struct hwrm_port_phy_cfg_output {
2392 __le16 error_code;
2393 __le16 req_type;
2394 __le16 seq_id;
2395 __le16 resp_len;
2396 u8 unused_0[7];
2397 u8 valid;
2398 };
2399
2400 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */
2401 struct hwrm_port_phy_cfg_cmd_err {
2402 u8 code;
2403 #define PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL
2404 #define PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED 0x1UL
2405 #define PORT_PHY_CFG_CMD_ERR_CODE_RETRY 0x2UL
2406 #define PORT_PHY_CFG_CMD_ERR_CODE_LAST PORT_PHY_CFG_CMD_ERR_CODE_RETRY
2407 u8 unused_0[7];
2408 };
2409
2410 /* hwrm_port_phy_qcfg_input (size:192b/24B) */
2411 struct hwrm_port_phy_qcfg_input {
2412 __le16 req_type;
2413 __le16 cmpl_ring;
2414 __le16 seq_id;
2415 __le16 target_id;
2416 __le64 resp_addr;
2417 __le16 port_id;
2418 u8 unused_0[6];
2419 };
2420
2421 /* hwrm_port_phy_qcfg_output (size:768b/96B) */
2422 struct hwrm_port_phy_qcfg_output {
2423 __le16 error_code;
2424 __le16 req_type;
2425 __le16 seq_id;
2426 __le16 resp_len;
2427 u8 link;
2428 #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL
2429 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL
2430 #define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL
2431 #define PORT_PHY_QCFG_RESP_LINK_LAST PORT_PHY_QCFG_RESP_LINK_LINK
2432 u8 unused_0;
2433 __le16 link_speed;
2434 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL
2435 #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL
2436 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL
2437 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL
2438 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL
2439 #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL
2440 #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL
2441 #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL
2442 #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL
2443 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL
2444 #define PORT_PHY_QCFG_RESP_LINK_SPEED_200GB 0x7d0UL
2445 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL
2446 #define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB
2447 u8 duplex_cfg;
2448 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF 0x0UL
2449 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 0x1UL
2450 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_LAST PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL
2451 u8 pause;
2452 #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL
2453 #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL
2454 __le16 support_speeds;
2455 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL
2456 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL
2457 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL
2458 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL
2459 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL
2460 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL
2461 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL
2462 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL
2463 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL
2464 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL
2465 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL
2466 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL
2467 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL
2468 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL
2469 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_200GB 0x4000UL
2470 __le16 force_link_speed;
2471 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL
2472 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB 0xaUL
2473 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB 0x14UL
2474 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL
2475 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB 0x64UL
2476 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB 0xc8UL
2477 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB 0xfaUL
2478 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB 0x190UL
2479 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB 0x1f4UL
2480 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL
2481 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_200GB 0x7d0UL
2482 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 0xffffUL
2483 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB
2484 u8 auto_mode;
2485 #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 0x0UL
2486 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 0x1UL
2487 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 0x2UL
2488 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL
2489 #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 0x4UL
2490 #define PORT_PHY_QCFG_RESP_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
2491 u8 auto_pause;
2492 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL
2493 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL
2494 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL
2495 __le16 auto_link_speed;
2496 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL
2497 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB 0xaUL
2498 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB 0x14UL
2499 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL
2500 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB 0x64UL
2501 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB 0xc8UL
2502 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB 0xfaUL
2503 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB 0x190UL
2504 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB 0x1f4UL
2505 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL
2506 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_200GB 0x7d0UL
2507 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 0xffffUL
2508 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB
2509 __le16 auto_link_speed_mask;
2510 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL
2511 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL
2512 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL
2513 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL
2514 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL
2515 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL
2516 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL
2517 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL
2518 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL
2519 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL
2520 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL
2521 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL
2522 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL
2523 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL
2524 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_200GB 0x4000UL
2525 u8 wirespeed;
2526 #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL
2527 #define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL
2528 #define PORT_PHY_QCFG_RESP_WIRESPEED_LAST PORT_PHY_QCFG_RESP_WIRESPEED_ON
2529 u8 lpbk;
2530 #define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL
2531 #define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL
2532 #define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL
2533 #define PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 0x3UL
2534 #define PORT_PHY_QCFG_RESP_LPBK_LAST PORT_PHY_QCFG_RESP_LPBK_EXTERNAL
2535 u8 force_pause;
2536 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL
2537 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL
2538 u8 module_status;
2539 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE 0x0UL
2540 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX 0x1UL
2541 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG 0x2UL
2542 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL
2543 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL
2544 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT 0x5UL
2545 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL
2546 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_LAST PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE
2547 __le32 preemphasis;
2548 u8 phy_maj;
2549 u8 phy_min;
2550 u8 phy_bld;
2551 u8 phy_type;
2552 #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN 0x0UL
2553 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR 0x1UL
2554 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 0x2UL
2555 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR 0x3UL
2556 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR 0x4UL
2557 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 0x5UL
2558 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX 0x6UL
2559 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR 0x7UL
2560 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET 0x8UL
2561 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE 0x9UL
2562 #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY 0xaUL
2563 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L 0xbUL
2564 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S 0xcUL
2565 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N 0xdUL
2566 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR 0xeUL
2567 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4 0xfUL
2568 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4 0x10UL
2569 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4 0x11UL
2570 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4 0x12UL
2571 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10 0x13UL
2572 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4 0x14UL
2573 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4 0x15UL
2574 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4 0x16UL
2575 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4 0x17UL
2576 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL
2577 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET 0x19UL
2578 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX 0x1aUL
2579 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX 0x1bUL
2580 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4 0x1cUL
2581 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4 0x1dUL
2582 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4 0x1eUL
2583 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 0x1fUL
2584 #define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4
2585 u8 media_type;
2586 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL
2587 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL
2588 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL
2589 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL
2590 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE
2591 u8 xcvr_pkg_type;
2592 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL
2593 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL
2594 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL
2595 u8 eee_config_phy_addr;
2596 #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL
2597 #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0
2598 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL
2599 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5
2600 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL
2601 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL
2602 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL
2603 u8 parallel_detect;
2604 #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL
2605 __le16 link_partner_adv_speeds;
2606 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL
2607 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL
2608 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL
2609 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL
2610 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL
2611 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL
2612 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL
2613 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL
2614 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL
2615 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL
2616 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL
2617 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL
2618 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL
2619 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL
2620 u8 link_partner_adv_auto_mode;
2621 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE 0x0UL
2622 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS 0x1UL
2623 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED 0x2UL
2624 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL
2625 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 0x4UL
2626 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK
2627 u8 link_partner_adv_pause;
2628 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL
2629 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL
2630 __le16 adv_eee_link_speed_mask;
2631 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL
2632 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL
2633 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL
2634 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL
2635 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL
2636 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL
2637 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL
2638 __le16 link_partner_adv_eee_link_speed_mask;
2639 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL
2640 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL
2641 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL
2642 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL
2643 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL
2644 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL
2645 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL
2646 __le32 xcvr_identifier_type_tx_lpi_timer;
2647 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL
2648 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0
2649 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL
2650 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24
2651 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24)
2652 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24)
2653 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24)
2654 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24)
2655 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24)
2656 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28
2657 __le16 fec_cfg;
2658 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL
2659 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL
2660 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL
2661 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL
2662 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL
2663 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL
2664 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL
2665 u8 duplex_state;
2666 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL
2667 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL
2668 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_LAST PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL
2669 u8 option_flags;
2670 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT 0x1UL
2671 char phy_vendor_name[16];
2672 char phy_vendor_partnumber[16];
2673 u8 unused_2[7];
2674 u8 valid;
2675 };
2676
2677 /* hwrm_port_mac_cfg_input (size:384b/48B) */
2678 struct hwrm_port_mac_cfg_input {
2679 __le16 req_type;
2680 __le16 cmpl_ring;
2681 __le16 seq_id;
2682 __le16 target_id;
2683 __le64 resp_addr;
2684 __le32 flags;
2685 #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL
2686 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE 0x2UL
2687 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL
2688 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL
2689 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL
2690 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL
2691 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL
2692 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL
2693 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL
2694 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL
2695 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL
2696 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL
2697 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL
2698 #define PORT_MAC_CFG_REQ_FLAGS_PTP_ONE_STEP_TX_TS 0x2000UL
2699 __le32 enables;
2700 #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL
2701 #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL
2702 #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI 0x4UL
2703 #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL
2704 #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL
2705 #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL
2706 #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL
2707 #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL
2708 #define PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB 0x200UL
2709 __le16 port_id;
2710 u8 ipg;
2711 u8 lpbk;
2712 #define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL
2713 #define PORT_MAC_CFG_REQ_LPBK_LOCAL 0x1UL
2714 #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL
2715 #define PORT_MAC_CFG_REQ_LPBK_LAST PORT_MAC_CFG_REQ_LPBK_REMOTE
2716 u8 vlan_pri2cos_map_pri;
2717 u8 reserved1;
2718 u8 tunnel_pri2cos_map_pri;
2719 u8 dscp2pri_map_pri;
2720 __le16 rx_ts_capture_ptp_msg_type;
2721 __le16 tx_ts_capture_ptp_msg_type;
2722 u8 cos_field_cfg;
2723 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1 0x1UL
2724 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL
2725 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1
2726 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1)
2727 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1)
2728 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1)
2729 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1)
2730 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
2731 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL
2732 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3
2733 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3)
2734 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3)
2735 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3)
2736 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3)
2737 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
2738 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL
2739 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5
2740 u8 unused_0[3];
2741 __s32 ptp_freq_adj_ppb;
2742 u8 unused_1[4];
2743 };
2744
2745 /* hwrm_port_mac_cfg_output (size:128b/16B) */
2746 struct hwrm_port_mac_cfg_output {
2747 __le16 error_code;
2748 __le16 req_type;
2749 __le16 seq_id;
2750 __le16 resp_len;
2751 __le16 mru;
2752 __le16 mtu;
2753 u8 ipg;
2754 u8 lpbk;
2755 #define PORT_MAC_CFG_RESP_LPBK_NONE 0x0UL
2756 #define PORT_MAC_CFG_RESP_LPBK_LOCAL 0x1UL
2757 #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL
2758 #define PORT_MAC_CFG_RESP_LPBK_LAST PORT_MAC_CFG_RESP_LPBK_REMOTE
2759 u8 unused_0;
2760 u8 valid;
2761 };
2762
2763 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */
2764 struct hwrm_port_mac_ptp_qcfg_input {
2765 __le16 req_type;
2766 __le16 cmpl_ring;
2767 __le16 seq_id;
2768 __le16 target_id;
2769 __le64 resp_addr;
2770 __le16 port_id;
2771 u8 unused_0[6];
2772 };
2773
2774 /* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */
2775 struct hwrm_port_mac_ptp_qcfg_output {
2776 __le16 error_code;
2777 __le16 req_type;
2778 __le16 seq_id;
2779 __le16 resp_len;
2780 u8 flags;
2781 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS 0x1UL
2782 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_ONE_STEP_TX_TS 0x4UL
2783 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS 0x8UL
2784 u8 unused_0[3];
2785 __le32 rx_ts_reg_off_lower;
2786 __le32 rx_ts_reg_off_upper;
2787 __le32 rx_ts_reg_off_seq_id;
2788 __le32 rx_ts_reg_off_src_id_0;
2789 __le32 rx_ts_reg_off_src_id_1;
2790 __le32 rx_ts_reg_off_src_id_2;
2791 __le32 rx_ts_reg_off_domain_id;
2792 __le32 rx_ts_reg_off_fifo;
2793 __le32 rx_ts_reg_off_fifo_adv;
2794 __le32 rx_ts_reg_off_granularity;
2795 __le32 tx_ts_reg_off_lower;
2796 __le32 tx_ts_reg_off_upper;
2797 __le32 tx_ts_reg_off_seq_id;
2798 __le32 tx_ts_reg_off_fifo;
2799 __le32 tx_ts_reg_off_granularity;
2800 u8 unused_1[7];
2801 u8 valid;
2802 };
2803
2804 /* tx_port_stats (size:3264b/408B) */
2805 struct tx_port_stats {
2806 __le64 tx_64b_frames;
2807 __le64 tx_65b_127b_frames;
2808 __le64 tx_128b_255b_frames;
2809 __le64 tx_256b_511b_frames;
2810 __le64 tx_512b_1023b_frames;
2811 __le64 tx_1024b_1518b_frames;
2812 __le64 tx_good_vlan_frames;
2813 __le64 tx_1519b_2047b_frames;
2814 __le64 tx_2048b_4095b_frames;
2815 __le64 tx_4096b_9216b_frames;
2816 __le64 tx_9217b_16383b_frames;
2817 __le64 tx_good_frames;
2818 __le64 tx_total_frames;
2819 __le64 tx_ucast_frames;
2820 __le64 tx_mcast_frames;
2821 __le64 tx_bcast_frames;
2822 __le64 tx_pause_frames;
2823 __le64 tx_pfc_frames;
2824 __le64 tx_jabber_frames;
2825 __le64 tx_fcs_err_frames;
2826 __le64 tx_control_frames;
2827 __le64 tx_oversz_frames;
2828 __le64 tx_single_dfrl_frames;
2829 __le64 tx_multi_dfrl_frames;
2830 __le64 tx_single_coll_frames;
2831 __le64 tx_multi_coll_frames;
2832 __le64 tx_late_coll_frames;
2833 __le64 tx_excessive_coll_frames;
2834 __le64 tx_frag_frames;
2835 __le64 tx_err;
2836 __le64 tx_tagged_frames;
2837 __le64 tx_dbl_tagged_frames;
2838 __le64 tx_runt_frames;
2839 __le64 tx_fifo_underruns;
2840 __le64 tx_pfc_ena_frames_pri0;
2841 __le64 tx_pfc_ena_frames_pri1;
2842 __le64 tx_pfc_ena_frames_pri2;
2843 __le64 tx_pfc_ena_frames_pri3;
2844 __le64 tx_pfc_ena_frames_pri4;
2845 __le64 tx_pfc_ena_frames_pri5;
2846 __le64 tx_pfc_ena_frames_pri6;
2847 __le64 tx_pfc_ena_frames_pri7;
2848 __le64 tx_eee_lpi_events;
2849 __le64 tx_eee_lpi_duration;
2850 __le64 tx_llfc_logical_msgs;
2851 __le64 tx_hcfc_msgs;
2852 __le64 tx_total_collisions;
2853 __le64 tx_bytes;
2854 __le64 tx_xthol_frames;
2855 __le64 tx_stat_discard;
2856 __le64 tx_stat_error;
2857 };
2858
2859 /* rx_port_stats (size:4224b/528B) */
2860 struct rx_port_stats {
2861 __le64 rx_64b_frames;
2862 __le64 rx_65b_127b_frames;
2863 __le64 rx_128b_255b_frames;
2864 __le64 rx_256b_511b_frames;
2865 __le64 rx_512b_1023b_frames;
2866 __le64 rx_1024b_1518b_frames;
2867 __le64 rx_good_vlan_frames;
2868 __le64 rx_1519b_2047b_frames;
2869 __le64 rx_2048b_4095b_frames;
2870 __le64 rx_4096b_9216b_frames;
2871 __le64 rx_9217b_16383b_frames;
2872 __le64 rx_total_frames;
2873 __le64 rx_ucast_frames;
2874 __le64 rx_mcast_frames;
2875 __le64 rx_bcast_frames;
2876 __le64 rx_fcs_err_frames;
2877 __le64 rx_ctrl_frames;
2878 __le64 rx_pause_frames;
2879 __le64 rx_pfc_frames;
2880 __le64 rx_unsupported_opcode_frames;
2881 __le64 rx_unsupported_da_pausepfc_frames;
2882 __le64 rx_wrong_sa_frames;
2883 __le64 rx_align_err_frames;
2884 __le64 rx_oor_len_frames;
2885 __le64 rx_code_err_frames;
2886 __le64 rx_false_carrier_frames;
2887 __le64 rx_ovrsz_frames;
2888 __le64 rx_jbr_frames;
2889 __le64 rx_mtu_err_frames;
2890 __le64 rx_match_crc_frames;
2891 __le64 rx_promiscuous_frames;
2892 __le64 rx_tagged_frames;
2893 __le64 rx_double_tagged_frames;
2894 __le64 rx_trunc_frames;
2895 __le64 rx_good_frames;
2896 __le64 rx_pfc_xon2xoff_frames_pri0;
2897 __le64 rx_pfc_xon2xoff_frames_pri1;
2898 __le64 rx_pfc_xon2xoff_frames_pri2;
2899 __le64 rx_pfc_xon2xoff_frames_pri3;
2900 __le64 rx_pfc_xon2xoff_frames_pri4;
2901 __le64 rx_pfc_xon2xoff_frames_pri5;
2902 __le64 rx_pfc_xon2xoff_frames_pri6;
2903 __le64 rx_pfc_xon2xoff_frames_pri7;
2904 __le64 rx_pfc_ena_frames_pri0;
2905 __le64 rx_pfc_ena_frames_pri1;
2906 __le64 rx_pfc_ena_frames_pri2;
2907 __le64 rx_pfc_ena_frames_pri3;
2908 __le64 rx_pfc_ena_frames_pri4;
2909 __le64 rx_pfc_ena_frames_pri5;
2910 __le64 rx_pfc_ena_frames_pri6;
2911 __le64 rx_pfc_ena_frames_pri7;
2912 __le64 rx_sch_crc_err_frames;
2913 __le64 rx_undrsz_frames;
2914 __le64 rx_frag_frames;
2915 __le64 rx_eee_lpi_events;
2916 __le64 rx_eee_lpi_duration;
2917 __le64 rx_llfc_physical_msgs;
2918 __le64 rx_llfc_logical_msgs;
2919 __le64 rx_llfc_msgs_with_crc_err;
2920 __le64 rx_hcfc_msgs;
2921 __le64 rx_hcfc_msgs_with_crc_err;
2922 __le64 rx_bytes;
2923 __le64 rx_runt_bytes;
2924 __le64 rx_runt_frames;
2925 __le64 rx_stat_discard;
2926 __le64 rx_stat_err;
2927 };
2928
2929 /* hwrm_port_qstats_input (size:320b/40B) */
2930 struct hwrm_port_qstats_input {
2931 __le16 req_type;
2932 __le16 cmpl_ring;
2933 __le16 seq_id;
2934 __le16 target_id;
2935 __le64 resp_addr;
2936 __le16 port_id;
2937 u8 unused_0[6];
2938 __le64 tx_stat_host_addr;
2939 __le64 rx_stat_host_addr;
2940 };
2941
2942 /* hwrm_port_qstats_output (size:128b/16B) */
2943 struct hwrm_port_qstats_output {
2944 __le16 error_code;
2945 __le16 req_type;
2946 __le16 seq_id;
2947 __le16 resp_len;
2948 __le16 tx_stat_size;
2949 __le16 rx_stat_size;
2950 u8 unused_0[3];
2951 u8 valid;
2952 };
2953
2954 /* tx_port_stats_ext (size:2048b/256B) */
2955 struct tx_port_stats_ext {
2956 __le64 tx_bytes_cos0;
2957 __le64 tx_bytes_cos1;
2958 __le64 tx_bytes_cos2;
2959 __le64 tx_bytes_cos3;
2960 __le64 tx_bytes_cos4;
2961 __le64 tx_bytes_cos5;
2962 __le64 tx_bytes_cos6;
2963 __le64 tx_bytes_cos7;
2964 __le64 tx_packets_cos0;
2965 __le64 tx_packets_cos1;
2966 __le64 tx_packets_cos2;
2967 __le64 tx_packets_cos3;
2968 __le64 tx_packets_cos4;
2969 __le64 tx_packets_cos5;
2970 __le64 tx_packets_cos6;
2971 __le64 tx_packets_cos7;
2972 __le64 pfc_pri0_tx_duration_us;
2973 __le64 pfc_pri0_tx_transitions;
2974 __le64 pfc_pri1_tx_duration_us;
2975 __le64 pfc_pri1_tx_transitions;
2976 __le64 pfc_pri2_tx_duration_us;
2977 __le64 pfc_pri2_tx_transitions;
2978 __le64 pfc_pri3_tx_duration_us;
2979 __le64 pfc_pri3_tx_transitions;
2980 __le64 pfc_pri4_tx_duration_us;
2981 __le64 pfc_pri4_tx_transitions;
2982 __le64 pfc_pri5_tx_duration_us;
2983 __le64 pfc_pri5_tx_transitions;
2984 __le64 pfc_pri6_tx_duration_us;
2985 __le64 pfc_pri6_tx_transitions;
2986 __le64 pfc_pri7_tx_duration_us;
2987 __le64 pfc_pri7_tx_transitions;
2988 };
2989
2990 /* rx_port_stats_ext (size:3648b/456B) */
2991 struct rx_port_stats_ext {
2992 __le64 link_down_events;
2993 __le64 continuous_pause_events;
2994 __le64 resume_pause_events;
2995 __le64 continuous_roce_pause_events;
2996 __le64 resume_roce_pause_events;
2997 __le64 rx_bytes_cos0;
2998 __le64 rx_bytes_cos1;
2999 __le64 rx_bytes_cos2;
3000 __le64 rx_bytes_cos3;
3001 __le64 rx_bytes_cos4;
3002 __le64 rx_bytes_cos5;
3003 __le64 rx_bytes_cos6;
3004 __le64 rx_bytes_cos7;
3005 __le64 rx_packets_cos0;
3006 __le64 rx_packets_cos1;
3007 __le64 rx_packets_cos2;
3008 __le64 rx_packets_cos3;
3009 __le64 rx_packets_cos4;
3010 __le64 rx_packets_cos5;
3011 __le64 rx_packets_cos6;
3012 __le64 rx_packets_cos7;
3013 __le64 pfc_pri0_rx_duration_us;
3014 __le64 pfc_pri0_rx_transitions;
3015 __le64 pfc_pri1_rx_duration_us;
3016 __le64 pfc_pri1_rx_transitions;
3017 __le64 pfc_pri2_rx_duration_us;
3018 __le64 pfc_pri2_rx_transitions;
3019 __le64 pfc_pri3_rx_duration_us;
3020 __le64 pfc_pri3_rx_transitions;
3021 __le64 pfc_pri4_rx_duration_us;
3022 __le64 pfc_pri4_rx_transitions;
3023 __le64 pfc_pri5_rx_duration_us;
3024 __le64 pfc_pri5_rx_transitions;
3025 __le64 pfc_pri6_rx_duration_us;
3026 __le64 pfc_pri6_rx_transitions;
3027 __le64 pfc_pri7_rx_duration_us;
3028 __le64 pfc_pri7_rx_transitions;
3029 __le64 rx_bits;
3030 __le64 rx_buffer_passed_threshold;
3031 __le64 rx_pcs_symbol_err;
3032 __le64 rx_corrected_bits;
3033 __le64 rx_discard_bytes_cos0;
3034 __le64 rx_discard_bytes_cos1;
3035 __le64 rx_discard_bytes_cos2;
3036 __le64 rx_discard_bytes_cos3;
3037 __le64 rx_discard_bytes_cos4;
3038 __le64 rx_discard_bytes_cos5;
3039 __le64 rx_discard_bytes_cos6;
3040 __le64 rx_discard_bytes_cos7;
3041 __le64 rx_discard_packets_cos0;
3042 __le64 rx_discard_packets_cos1;
3043 __le64 rx_discard_packets_cos2;
3044 __le64 rx_discard_packets_cos3;
3045 __le64 rx_discard_packets_cos4;
3046 __le64 rx_discard_packets_cos5;
3047 __le64 rx_discard_packets_cos6;
3048 __le64 rx_discard_packets_cos7;
3049 };
3050
3051 /* hwrm_port_qstats_ext_input (size:320b/40B) */
3052 struct hwrm_port_qstats_ext_input {
3053 __le16 req_type;
3054 __le16 cmpl_ring;
3055 __le16 seq_id;
3056 __le16 target_id;
3057 __le64 resp_addr;
3058 __le16 port_id;
3059 __le16 tx_stat_size;
3060 __le16 rx_stat_size;
3061 u8 unused_0[2];
3062 __le64 tx_stat_host_addr;
3063 __le64 rx_stat_host_addr;
3064 };
3065
3066 /* hwrm_port_qstats_ext_output (size:128b/16B) */
3067 struct hwrm_port_qstats_ext_output {
3068 __le16 error_code;
3069 __le16 req_type;
3070 __le16 seq_id;
3071 __le16 resp_len;
3072 __le16 tx_stat_size;
3073 __le16 rx_stat_size;
3074 __le16 total_active_cos_queues;
3075 u8 flags;
3076 #define PORT_QSTATS_EXT_RESP_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED 0x1UL
3077 u8 valid;
3078 };
3079
3080 /* hwrm_port_lpbk_qstats_input (size:128b/16B) */
3081 struct hwrm_port_lpbk_qstats_input {
3082 __le16 req_type;
3083 __le16 cmpl_ring;
3084 __le16 seq_id;
3085 __le16 target_id;
3086 __le64 resp_addr;
3087 };
3088
3089 /* hwrm_port_lpbk_qstats_output (size:768b/96B) */
3090 struct hwrm_port_lpbk_qstats_output {
3091 __le16 error_code;
3092 __le16 req_type;
3093 __le16 seq_id;
3094 __le16 resp_len;
3095 __le64 lpbk_ucast_frames;
3096 __le64 lpbk_mcast_frames;
3097 __le64 lpbk_bcast_frames;
3098 __le64 lpbk_ucast_bytes;
3099 __le64 lpbk_mcast_bytes;
3100 __le64 lpbk_bcast_bytes;
3101 __le64 tx_stat_discard;
3102 __le64 tx_stat_error;
3103 __le64 rx_stat_discard;
3104 __le64 rx_stat_error;
3105 u8 unused_0[7];
3106 u8 valid;
3107 };
3108
3109 /* hwrm_port_clr_stats_input (size:192b/24B) */
3110 struct hwrm_port_clr_stats_input {
3111 __le16 req_type;
3112 __le16 cmpl_ring;
3113 __le16 seq_id;
3114 __le16 target_id;
3115 __le64 resp_addr;
3116 __le16 port_id;
3117 u8 flags;
3118 #define PORT_CLR_STATS_REQ_FLAGS_ROCE_COUNTERS 0x1UL
3119 u8 unused_0[5];
3120 };
3121
3122 /* hwrm_port_clr_stats_output (size:128b/16B) */
3123 struct hwrm_port_clr_stats_output {
3124 __le16 error_code;
3125 __le16 req_type;
3126 __le16 seq_id;
3127 __le16 resp_len;
3128 u8 unused_0[7];
3129 u8 valid;
3130 };
3131
3132 /* hwrm_port_lpbk_clr_stats_input (size:128b/16B) */
3133 struct hwrm_port_lpbk_clr_stats_input {
3134 __le16 req_type;
3135 __le16 cmpl_ring;
3136 __le16 seq_id;
3137 __le16 target_id;
3138 __le64 resp_addr;
3139 };
3140
3141 /* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */
3142 struct hwrm_port_lpbk_clr_stats_output {
3143 __le16 error_code;
3144 __le16 req_type;
3145 __le16 seq_id;
3146 __le16 resp_len;
3147 u8 unused_0[7];
3148 u8 valid;
3149 };
3150
3151 /* hwrm_port_ts_query_input (size:192b/24B) */
3152 struct hwrm_port_ts_query_input {
3153 __le16 req_type;
3154 __le16 cmpl_ring;
3155 __le16 seq_id;
3156 __le16 target_id;
3157 __le64 resp_addr;
3158 __le32 flags;
3159 #define PORT_TS_QUERY_REQ_FLAGS_PATH 0x1UL
3160 #define PORT_TS_QUERY_REQ_FLAGS_PATH_TX 0x0UL
3161 #define PORT_TS_QUERY_REQ_FLAGS_PATH_RX 0x1UL
3162 #define PORT_TS_QUERY_REQ_FLAGS_PATH_LAST PORT_TS_QUERY_REQ_FLAGS_PATH_RX
3163 #define PORT_TS_QUERY_REQ_FLAGS_CURRENT_TIME 0x2UL
3164 __le16 port_id;
3165 u8 unused_0[2];
3166 };
3167
3168 /* hwrm_port_ts_query_output (size:192b/24B) */
3169 struct hwrm_port_ts_query_output {
3170 __le16 error_code;
3171 __le16 req_type;
3172 __le16 seq_id;
3173 __le16 resp_len;
3174 __le64 ptp_msg_ts;
3175 __le16 ptp_msg_seqid;
3176 u8 unused_0[5];
3177 u8 valid;
3178 };
3179
3180 /* hwrm_port_phy_qcaps_input (size:192b/24B) */
3181 struct hwrm_port_phy_qcaps_input {
3182 __le16 req_type;
3183 __le16 cmpl_ring;
3184 __le16 seq_id;
3185 __le16 target_id;
3186 __le64 resp_addr;
3187 __le16 port_id;
3188 u8 unused_0[6];
3189 };
3190
3191 /* hwrm_port_phy_qcaps_output (size:192b/24B) */
3192 struct hwrm_port_phy_qcaps_output {
3193 __le16 error_code;
3194 __le16 req_type;
3195 __le16 seq_id;
3196 __le16 resp_len;
3197 u8 flags;
3198 #define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED 0x1UL
3199 #define PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED 0x2UL
3200 #define PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED 0x4UL
3201 #define PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED 0x8UL
3202 #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_MASK 0xf0UL
3203 #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_SFT 4
3204 u8 port_cnt;
3205 #define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL
3206 #define PORT_PHY_QCAPS_RESP_PORT_CNT_1 0x1UL
3207 #define PORT_PHY_QCAPS_RESP_PORT_CNT_2 0x2UL
3208 #define PORT_PHY_QCAPS_RESP_PORT_CNT_3 0x3UL
3209 #define PORT_PHY_QCAPS_RESP_PORT_CNT_4 0x4UL
3210 #define PORT_PHY_QCAPS_RESP_PORT_CNT_LAST PORT_PHY_QCAPS_RESP_PORT_CNT_4
3211 __le16 supported_speeds_force_mode;
3212 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL
3213 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL
3214 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL
3215 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL
3216 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL
3217 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL
3218 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL
3219 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL
3220 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL
3221 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL
3222 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL
3223 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL
3224 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL
3225 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL
3226 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_200GB 0x4000UL
3227 __le16 supported_speeds_auto_mode;
3228 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL
3229 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL
3230 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL
3231 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL
3232 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL
3233 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL
3234 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL
3235 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL
3236 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL
3237 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL
3238 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL
3239 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL
3240 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL
3241 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL
3242 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_200GB 0x4000UL
3243 __le16 supported_speeds_eee_mode;
3244 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL
3245 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL
3246 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL
3247 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL
3248 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL
3249 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL
3250 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL
3251 __le32 tx_lpi_timer_low;
3252 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL
3253 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0
3254 #define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL
3255 #define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24
3256 __le32 valid_tx_lpi_timer_high;
3257 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL
3258 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0
3259 #define PORT_PHY_QCAPS_RESP_VALID_MASK 0xff000000UL
3260 #define PORT_PHY_QCAPS_RESP_VALID_SFT 24
3261 };
3262
3263 /* hwrm_port_phy_i2c_read_input (size:320b/40B) */
3264 struct hwrm_port_phy_i2c_read_input {
3265 __le16 req_type;
3266 __le16 cmpl_ring;
3267 __le16 seq_id;
3268 __le16 target_id;
3269 __le64 resp_addr;
3270 __le32 flags;
3271 __le32 enables;
3272 #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL
3273 __le16 port_id;
3274 u8 i2c_slave_addr;
3275 u8 unused_0;
3276 __le16 page_number;
3277 __le16 page_offset;
3278 u8 data_length;
3279 u8 unused_1[7];
3280 };
3281
3282 /* hwrm_port_phy_i2c_read_output (size:640b/80B) */
3283 struct hwrm_port_phy_i2c_read_output {
3284 __le16 error_code;
3285 __le16 req_type;
3286 __le16 seq_id;
3287 __le16 resp_len;
3288 __le32 data[16];
3289 u8 unused_0[7];
3290 u8 valid;
3291 };
3292
3293 /* hwrm_port_phy_mdio_write_input (size:320b/40B) */
3294 struct hwrm_port_phy_mdio_write_input {
3295 __le16 req_type;
3296 __le16 cmpl_ring;
3297 __le16 seq_id;
3298 __le16 target_id;
3299 __le64 resp_addr;
3300 __le32 unused_0[2];
3301 __le16 port_id;
3302 u8 phy_addr;
3303 u8 dev_addr;
3304 __le16 reg_addr;
3305 __le16 reg_data;
3306 u8 cl45_mdio;
3307 u8 unused_1[7];
3308 };
3309
3310 /* hwrm_port_phy_mdio_write_output (size:128b/16B) */
3311 struct hwrm_port_phy_mdio_write_output {
3312 __le16 error_code;
3313 __le16 req_type;
3314 __le16 seq_id;
3315 __le16 resp_len;
3316 u8 unused_0[7];
3317 u8 valid;
3318 };
3319
3320 /* hwrm_port_phy_mdio_read_input (size:256b/32B) */
3321 struct hwrm_port_phy_mdio_read_input {
3322 __le16 req_type;
3323 __le16 cmpl_ring;
3324 __le16 seq_id;
3325 __le16 target_id;
3326 __le64 resp_addr;
3327 __le32 unused_0[2];
3328 __le16 port_id;
3329 u8 phy_addr;
3330 u8 dev_addr;
3331 __le16 reg_addr;
3332 u8 cl45_mdio;
3333 u8 unused_1;
3334 };
3335
3336 /* hwrm_port_phy_mdio_read_output (size:128b/16B) */
3337 struct hwrm_port_phy_mdio_read_output {
3338 __le16 error_code;
3339 __le16 req_type;
3340 __le16 seq_id;
3341 __le16 resp_len;
3342 __le16 reg_data;
3343 u8 unused_0[5];
3344 u8 valid;
3345 };
3346
3347 /* hwrm_port_led_cfg_input (size:512b/64B) */
3348 struct hwrm_port_led_cfg_input {
3349 __le16 req_type;
3350 __le16 cmpl_ring;
3351 __le16 seq_id;
3352 __le16 target_id;
3353 __le64 resp_addr;
3354 __le32 enables;
3355 #define PORT_LED_CFG_REQ_ENABLES_LED0_ID 0x1UL
3356 #define PORT_LED_CFG_REQ_ENABLES_LED0_STATE 0x2UL
3357 #define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR 0x4UL
3358 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON 0x8UL
3359 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF 0x10UL
3360 #define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID 0x20UL
3361 #define PORT_LED_CFG_REQ_ENABLES_LED1_ID 0x40UL
3362 #define PORT_LED_CFG_REQ_ENABLES_LED1_STATE 0x80UL
3363 #define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR 0x100UL
3364 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON 0x200UL
3365 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF 0x400UL
3366 #define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID 0x800UL
3367 #define PORT_LED_CFG_REQ_ENABLES_LED2_ID 0x1000UL
3368 #define PORT_LED_CFG_REQ_ENABLES_LED2_STATE 0x2000UL
3369 #define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR 0x4000UL
3370 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON 0x8000UL
3371 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF 0x10000UL
3372 #define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID 0x20000UL
3373 #define PORT_LED_CFG_REQ_ENABLES_LED3_ID 0x40000UL
3374 #define PORT_LED_CFG_REQ_ENABLES_LED3_STATE 0x80000UL
3375 #define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR 0x100000UL
3376 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON 0x200000UL
3377 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF 0x400000UL
3378 #define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID 0x800000UL
3379 __le16 port_id;
3380 u8 num_leds;
3381 u8 rsvd;
3382 u8 led0_id;
3383 u8 led0_state;
3384 #define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT 0x0UL
3385 #define PORT_LED_CFG_REQ_LED0_STATE_OFF 0x1UL
3386 #define PORT_LED_CFG_REQ_LED0_STATE_ON 0x2UL
3387 #define PORT_LED_CFG_REQ_LED0_STATE_BLINK 0x3UL
3388 #define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL
3389 #define PORT_LED_CFG_REQ_LED0_STATE_LAST PORT_LED_CFG_REQ_LED0_STATE_BLINKALT
3390 u8 led0_color;
3391 #define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT 0x0UL
3392 #define PORT_LED_CFG_REQ_LED0_COLOR_AMBER 0x1UL
3393 #define PORT_LED_CFG_REQ_LED0_COLOR_GREEN 0x2UL
3394 #define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL
3395 #define PORT_LED_CFG_REQ_LED0_COLOR_LAST PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER
3396 u8 unused_0;
3397 __le16 led0_blink_on;
3398 __le16 led0_blink_off;
3399 u8 led0_group_id;
3400 u8 rsvd0;
3401 u8 led1_id;
3402 u8 led1_state;
3403 #define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT 0x0UL
3404 #define PORT_LED_CFG_REQ_LED1_STATE_OFF 0x1UL
3405 #define PORT_LED_CFG_REQ_LED1_STATE_ON 0x2UL
3406 #define PORT_LED_CFG_REQ_LED1_STATE_BLINK 0x3UL
3407 #define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL
3408 #define PORT_LED_CFG_REQ_LED1_STATE_LAST PORT_LED_CFG_REQ_LED1_STATE_BLINKALT
3409 u8 led1_color;
3410 #define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT 0x0UL
3411 #define PORT_LED_CFG_REQ_LED1_COLOR_AMBER 0x1UL
3412 #define PORT_LED_CFG_REQ_LED1_COLOR_GREEN 0x2UL
3413 #define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL
3414 #define PORT_LED_CFG_REQ_LED1_COLOR_LAST PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER
3415 u8 unused_1;
3416 __le16 led1_blink_on;
3417 __le16 led1_blink_off;
3418 u8 led1_group_id;
3419 u8 rsvd1;
3420 u8 led2_id;
3421 u8 led2_state;
3422 #define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT 0x0UL
3423 #define PORT_LED_CFG_REQ_LED2_STATE_OFF 0x1UL
3424 #define PORT_LED_CFG_REQ_LED2_STATE_ON 0x2UL
3425 #define PORT_LED_CFG_REQ_LED2_STATE_BLINK 0x3UL
3426 #define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL
3427 #define PORT_LED_CFG_REQ_LED2_STATE_LAST PORT_LED_CFG_REQ_LED2_STATE_BLINKALT
3428 u8 led2_color;
3429 #define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT 0x0UL
3430 #define PORT_LED_CFG_REQ_LED2_COLOR_AMBER 0x1UL
3431 #define PORT_LED_CFG_REQ_LED2_COLOR_GREEN 0x2UL
3432 #define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL
3433 #define PORT_LED_CFG_REQ_LED2_COLOR_LAST PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER
3434 u8 unused_2;
3435 __le16 led2_blink_on;
3436 __le16 led2_blink_off;
3437 u8 led2_group_id;
3438 u8 rsvd2;
3439 u8 led3_id;
3440 u8 led3_state;
3441 #define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT 0x0UL
3442 #define PORT_LED_CFG_REQ_LED3_STATE_OFF 0x1UL
3443 #define PORT_LED_CFG_REQ_LED3_STATE_ON 0x2UL
3444 #define PORT_LED_CFG_REQ_LED3_STATE_BLINK 0x3UL
3445 #define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL
3446 #define PORT_LED_CFG_REQ_LED3_STATE_LAST PORT_LED_CFG_REQ_LED3_STATE_BLINKALT
3447 u8 led3_color;
3448 #define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT 0x0UL
3449 #define PORT_LED_CFG_REQ_LED3_COLOR_AMBER 0x1UL
3450 #define PORT_LED_CFG_REQ_LED3_COLOR_GREEN 0x2UL
3451 #define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL
3452 #define PORT_LED_CFG_REQ_LED3_COLOR_LAST PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER
3453 u8 unused_3;
3454 __le16 led3_blink_on;
3455 __le16 led3_blink_off;
3456 u8 led3_group_id;
3457 u8 rsvd3;
3458 };
3459
3460 /* hwrm_port_led_cfg_output (size:128b/16B) */
3461 struct hwrm_port_led_cfg_output {
3462 __le16 error_code;
3463 __le16 req_type;
3464 __le16 seq_id;
3465 __le16 resp_len;
3466 u8 unused_0[7];
3467 u8 valid;
3468 };
3469
3470 /* hwrm_port_led_qcfg_input (size:192b/24B) */
3471 struct hwrm_port_led_qcfg_input {
3472 __le16 req_type;
3473 __le16 cmpl_ring;
3474 __le16 seq_id;
3475 __le16 target_id;
3476 __le64 resp_addr;
3477 __le16 port_id;
3478 u8 unused_0[6];
3479 };
3480
3481 /* hwrm_port_led_qcfg_output (size:448b/56B) */
3482 struct hwrm_port_led_qcfg_output {
3483 __le16 error_code;
3484 __le16 req_type;
3485 __le16 seq_id;
3486 __le16 resp_len;
3487 u8 num_leds;
3488 u8 led0_id;
3489 u8 led0_type;
3490 #define PORT_LED_QCFG_RESP_LED0_TYPE_SPEED 0x0UL
3491 #define PORT_LED_QCFG_RESP_LED0_TYPE_ACTIVITY 0x1UL
3492 #define PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 0xffUL
3493 #define PORT_LED_QCFG_RESP_LED0_TYPE_LAST PORT_LED_QCFG_RESP_LED0_TYPE_INVALID
3494 u8 led0_state;
3495 #define PORT_LED_QCFG_RESP_LED0_STATE_DEFAULT 0x0UL
3496 #define PORT_LED_QCFG_RESP_LED0_STATE_OFF 0x1UL
3497 #define PORT_LED_QCFG_RESP_LED0_STATE_ON 0x2UL
3498 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINK 0x3UL
3499 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 0x4UL
3500 #define PORT_LED_QCFG_RESP_LED0_STATE_LAST PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT
3501 u8 led0_color;
3502 #define PORT_LED_QCFG_RESP_LED0_COLOR_DEFAULT 0x0UL
3503 #define PORT_LED_QCFG_RESP_LED0_COLOR_AMBER 0x1UL
3504 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREEN 0x2UL
3505 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 0x3UL
3506 #define PORT_LED_QCFG_RESP_LED0_COLOR_LAST PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER
3507 u8 unused_0;
3508 __le16 led0_blink_on;
3509 __le16 led0_blink_off;
3510 u8 led0_group_id;
3511 u8 led1_id;
3512 u8 led1_type;
3513 #define PORT_LED_QCFG_RESP_LED1_TYPE_SPEED 0x0UL
3514 #define PORT_LED_QCFG_RESP_LED1_TYPE_ACTIVITY 0x1UL
3515 #define PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 0xffUL
3516 #define PORT_LED_QCFG_RESP_LED1_TYPE_LAST PORT_LED_QCFG_RESP_LED1_TYPE_INVALID
3517 u8 led1_state;
3518 #define PORT_LED_QCFG_RESP_LED1_STATE_DEFAULT 0x0UL
3519 #define PORT_LED_QCFG_RESP_LED1_STATE_OFF 0x1UL
3520 #define PORT_LED_QCFG_RESP_LED1_STATE_ON 0x2UL
3521 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINK 0x3UL
3522 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 0x4UL
3523 #define PORT_LED_QCFG_RESP_LED1_STATE_LAST PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT
3524 u8 led1_color;
3525 #define PORT_LED_QCFG_RESP_LED1_COLOR_DEFAULT 0x0UL
3526 #define PORT_LED_QCFG_RESP_LED1_COLOR_AMBER 0x1UL
3527 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREEN 0x2UL
3528 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 0x3UL
3529 #define PORT_LED_QCFG_RESP_LED1_COLOR_LAST PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER
3530 u8 unused_1;
3531 __le16 led1_blink_on;
3532 __le16 led1_blink_off;
3533 u8 led1_group_id;
3534 u8 led2_id;
3535 u8 led2_type;
3536 #define PORT_LED_QCFG_RESP_LED2_TYPE_SPEED 0x0UL
3537 #define PORT_LED_QCFG_RESP_LED2_TYPE_ACTIVITY 0x1UL
3538 #define PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 0xffUL
3539 #define PORT_LED_QCFG_RESP_LED2_TYPE_LAST PORT_LED_QCFG_RESP_LED2_TYPE_INVALID
3540 u8 led2_state;
3541 #define PORT_LED_QCFG_RESP_LED2_STATE_DEFAULT 0x0UL
3542 #define PORT_LED_QCFG_RESP_LED2_STATE_OFF 0x1UL
3543 #define PORT_LED_QCFG_RESP_LED2_STATE_ON 0x2UL
3544 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINK 0x3UL
3545 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 0x4UL
3546 #define PORT_LED_QCFG_RESP_LED2_STATE_LAST PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT
3547 u8 led2_color;
3548 #define PORT_LED_QCFG_RESP_LED2_COLOR_DEFAULT 0x0UL
3549 #define PORT_LED_QCFG_RESP_LED2_COLOR_AMBER 0x1UL
3550 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREEN 0x2UL
3551 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 0x3UL
3552 #define PORT_LED_QCFG_RESP_LED2_COLOR_LAST PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER
3553 u8 unused_2;
3554 __le16 led2_blink_on;
3555 __le16 led2_blink_off;
3556 u8 led2_group_id;
3557 u8 led3_id;
3558 u8 led3_type;
3559 #define PORT_LED_QCFG_RESP_LED3_TYPE_SPEED 0x0UL
3560 #define PORT_LED_QCFG_RESP_LED3_TYPE_ACTIVITY 0x1UL
3561 #define PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 0xffUL
3562 #define PORT_LED_QCFG_RESP_LED3_TYPE_LAST PORT_LED_QCFG_RESP_LED3_TYPE_INVALID
3563 u8 led3_state;
3564 #define PORT_LED_QCFG_RESP_LED3_STATE_DEFAULT 0x0UL
3565 #define PORT_LED_QCFG_RESP_LED3_STATE_OFF 0x1UL
3566 #define PORT_LED_QCFG_RESP_LED3_STATE_ON 0x2UL
3567 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINK 0x3UL
3568 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 0x4UL
3569 #define PORT_LED_QCFG_RESP_LED3_STATE_LAST PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT
3570 u8 led3_color;
3571 #define PORT_LED_QCFG_RESP_LED3_COLOR_DEFAULT 0x0UL
3572 #define PORT_LED_QCFG_RESP_LED3_COLOR_AMBER 0x1UL
3573 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREEN 0x2UL
3574 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 0x3UL
3575 #define PORT_LED_QCFG_RESP_LED3_COLOR_LAST PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER
3576 u8 unused_3;
3577 __le16 led3_blink_on;
3578 __le16 led3_blink_off;
3579 u8 led3_group_id;
3580 u8 unused_4[6];
3581 u8 valid;
3582 };
3583
3584 /* hwrm_port_led_qcaps_input (size:192b/24B) */
3585 struct hwrm_port_led_qcaps_input {
3586 __le16 req_type;
3587 __le16 cmpl_ring;
3588 __le16 seq_id;
3589 __le16 target_id;
3590 __le64 resp_addr;
3591 __le16 port_id;
3592 u8 unused_0[6];
3593 };
3594
3595 /* hwrm_port_led_qcaps_output (size:384b/48B) */
3596 struct hwrm_port_led_qcaps_output {
3597 __le16 error_code;
3598 __le16 req_type;
3599 __le16 seq_id;
3600 __le16 resp_len;
3601 u8 num_leds;
3602 u8 unused[3];
3603 u8 led0_id;
3604 u8 led0_type;
3605 #define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED 0x0UL
3606 #define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL
3607 #define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 0xffUL
3608 #define PORT_LED_QCAPS_RESP_LED0_TYPE_LAST PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID
3609 u8 led0_group_id;
3610 u8 unused_0;
3611 __le16 led0_state_caps;
3612 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED 0x1UL
3613 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED 0x2UL
3614 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED 0x4UL
3615 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED 0x8UL
3616 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL
3617 __le16 led0_color_caps;
3618 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD 0x1UL
3619 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED 0x2UL
3620 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED 0x4UL
3621 u8 led1_id;
3622 u8 led1_type;
3623 #define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED 0x0UL
3624 #define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL
3625 #define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 0xffUL
3626 #define PORT_LED_QCAPS_RESP_LED1_TYPE_LAST PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID
3627 u8 led1_group_id;
3628 u8 unused_1;
3629 __le16 led1_state_caps;
3630 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED 0x1UL
3631 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED 0x2UL
3632 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED 0x4UL
3633 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED 0x8UL
3634 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL
3635 __le16 led1_color_caps;
3636 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD 0x1UL
3637 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED 0x2UL
3638 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED 0x4UL
3639 u8 led2_id;
3640 u8 led2_type;
3641 #define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED 0x0UL
3642 #define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL
3643 #define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 0xffUL
3644 #define PORT_LED_QCAPS_RESP_LED2_TYPE_LAST PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID
3645 u8 led2_group_id;
3646 u8 unused_2;
3647 __le16 led2_state_caps;
3648 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED 0x1UL
3649 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED 0x2UL
3650 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED 0x4UL
3651 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED 0x8UL
3652 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL
3653 __le16 led2_color_caps;
3654 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD 0x1UL
3655 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED 0x2UL
3656 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED 0x4UL
3657 u8 led3_id;
3658 u8 led3_type;
3659 #define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED 0x0UL
3660 #define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL
3661 #define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 0xffUL
3662 #define PORT_LED_QCAPS_RESP_LED3_TYPE_LAST PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID
3663 u8 led3_group_id;
3664 u8 unused_3;
3665 __le16 led3_state_caps;
3666 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED 0x1UL
3667 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED 0x2UL
3668 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED 0x4UL
3669 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED 0x8UL
3670 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL
3671 __le16 led3_color_caps;
3672 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD 0x1UL
3673 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED 0x2UL
3674 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED 0x4UL
3675 u8 unused_4[3];
3676 u8 valid;
3677 };
3678
3679 /* hwrm_queue_qportcfg_input (size:192b/24B) */
3680 struct hwrm_queue_qportcfg_input {
3681 __le16 req_type;
3682 __le16 cmpl_ring;
3683 __le16 seq_id;
3684 __le16 target_id;
3685 __le64 resp_addr;
3686 __le32 flags;
3687 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL
3688 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX 0x0UL
3689 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 0x1UL
3690 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX
3691 __le16 port_id;
3692 u8 drv_qmap_cap;
3693 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_DISABLED 0x0UL
3694 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 0x1UL
3695 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_LAST QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED
3696 u8 unused_0;
3697 };
3698
3699 /* hwrm_queue_qportcfg_output (size:256b/32B) */
3700 struct hwrm_queue_qportcfg_output {
3701 __le16 error_code;
3702 __le16 req_type;
3703 __le16 seq_id;
3704 __le16 resp_len;
3705 u8 max_configurable_queues;
3706 u8 max_configurable_lossless_queues;
3707 u8 queue_cfg_allowed;
3708 u8 queue_cfg_info;
3709 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL
3710 u8 queue_pfcenable_cfg_allowed;
3711 u8 queue_pri2cos_cfg_allowed;
3712 u8 queue_cos2bw_cfg_allowed;
3713 u8 queue_id0;
3714 u8 queue_id0_service_profile;
3715 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL
3716 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS 0x1UL
3717 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
3718 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
3719 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
3720 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 0xffUL
3721 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN
3722 u8 queue_id1;
3723 u8 queue_id1_service_profile;
3724 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL
3725 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS 0x1UL
3726 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
3727 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
3728 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
3729 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 0xffUL
3730 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN
3731 u8 queue_id2;
3732 u8 queue_id2_service_profile;
3733 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL
3734 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS 0x1UL
3735 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
3736 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
3737 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
3738 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 0xffUL
3739 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN
3740 u8 queue_id3;
3741 u8 queue_id3_service_profile;
3742 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL
3743 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS 0x1UL
3744 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
3745 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
3746 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
3747 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 0xffUL
3748 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN
3749 u8 queue_id4;
3750 u8 queue_id4_service_profile;
3751 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL
3752 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS 0x1UL
3753 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
3754 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
3755 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
3756 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 0xffUL
3757 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN
3758 u8 queue_id5;
3759 u8 queue_id5_service_profile;
3760 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL
3761 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS 0x1UL
3762 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
3763 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
3764 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
3765 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 0xffUL
3766 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN
3767 u8 queue_id6;
3768 u8 queue_id6_service_profile;
3769 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL
3770 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS 0x1UL
3771 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
3772 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
3773 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
3774 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 0xffUL
3775 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN
3776 u8 queue_id7;
3777 u8 queue_id7_service_profile;
3778 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL
3779 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS 0x1UL
3780 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
3781 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
3782 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
3783 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL
3784 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN
3785 u8 valid;
3786 };
3787
3788 /* hwrm_queue_cfg_input (size:320b/40B) */
3789 struct hwrm_queue_cfg_input {
3790 __le16 req_type;
3791 __le16 cmpl_ring;
3792 __le16 seq_id;
3793 __le16 target_id;
3794 __le64 resp_addr;
3795 __le32 flags;
3796 #define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL
3797 #define QUEUE_CFG_REQ_FLAGS_PATH_SFT 0
3798 #define QUEUE_CFG_REQ_FLAGS_PATH_TX 0x0UL
3799 #define QUEUE_CFG_REQ_FLAGS_PATH_RX 0x1UL
3800 #define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL
3801 #define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_BIDIR
3802 __le32 enables;
3803 #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL
3804 #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL
3805 __le32 queue_id;
3806 __le32 dflt_len;
3807 u8 service_profile;
3808 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY 0x0UL
3809 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL
3810 #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 0xffUL
3811 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LAST QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN
3812 u8 unused_0[7];
3813 };
3814
3815 /* hwrm_queue_cfg_output (size:128b/16B) */
3816 struct hwrm_queue_cfg_output {
3817 __le16 error_code;
3818 __le16 req_type;
3819 __le16 seq_id;
3820 __le16 resp_len;
3821 u8 unused_0[7];
3822 u8 valid;
3823 };
3824
3825 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */
3826 struct hwrm_queue_pfcenable_qcfg_input {
3827 __le16 req_type;
3828 __le16 cmpl_ring;
3829 __le16 seq_id;
3830 __le16 target_id;
3831 __le64 resp_addr;
3832 __le16 port_id;
3833 u8 unused_0[6];
3834 };
3835
3836 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */
3837 struct hwrm_queue_pfcenable_qcfg_output {
3838 __le16 error_code;
3839 __le16 req_type;
3840 __le16 seq_id;
3841 __le16 resp_len;
3842 __le32 flags;
3843 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED 0x1UL
3844 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED 0x2UL
3845 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED 0x4UL
3846 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED 0x8UL
3847 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED 0x10UL
3848 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED 0x20UL
3849 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED 0x40UL
3850 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED 0x80UL
3851 u8 unused_0[3];
3852 u8 valid;
3853 };
3854
3855 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */
3856 struct hwrm_queue_pfcenable_cfg_input {
3857 __le16 req_type;
3858 __le16 cmpl_ring;
3859 __le16 seq_id;
3860 __le16 target_id;
3861 __le64 resp_addr;
3862 __le32 flags;
3863 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL
3864 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL
3865 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL
3866 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL
3867 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL
3868 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL
3869 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL
3870 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL
3871 __le16 port_id;
3872 u8 unused_0[2];
3873 };
3874
3875 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */
3876 struct hwrm_queue_pfcenable_cfg_output {
3877 __le16 error_code;
3878 __le16 req_type;
3879 __le16 seq_id;
3880 __le16 resp_len;
3881 u8 unused_0[7];
3882 u8 valid;
3883 };
3884
3885 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */
3886 struct hwrm_queue_pri2cos_qcfg_input {
3887 __le16 req_type;
3888 __le16 cmpl_ring;
3889 __le16 seq_id;
3890 __le16 target_id;
3891 __le64 resp_addr;
3892 __le32 flags;
3893 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH 0x1UL
3894 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX 0x0UL
3895 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 0x1UL
3896 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX
3897 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN 0x2UL
3898 u8 port_id;
3899 u8 unused_0[3];
3900 };
3901
3902 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */
3903 struct hwrm_queue_pri2cos_qcfg_output {
3904 __le16 error_code;
3905 __le16 req_type;
3906 __le16 seq_id;
3907 __le16 resp_len;
3908 u8 pri0_cos_queue_id;
3909 u8 pri1_cos_queue_id;
3910 u8 pri2_cos_queue_id;
3911 u8 pri3_cos_queue_id;
3912 u8 pri4_cos_queue_id;
3913 u8 pri5_cos_queue_id;
3914 u8 pri6_cos_queue_id;
3915 u8 pri7_cos_queue_id;
3916 u8 queue_cfg_info;
3917 #define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL
3918 u8 unused_0[6];
3919 u8 valid;
3920 };
3921
3922 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */
3923 struct hwrm_queue_pri2cos_cfg_input {
3924 __le16 req_type;
3925 __le16 cmpl_ring;
3926 __le16 seq_id;
3927 __le16 target_id;
3928 __le64 resp_addr;
3929 __le32 flags;
3930 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL
3931 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT 0
3932 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX 0x0UL
3933 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX 0x1UL
3934 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL
3935 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR
3936 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x4UL
3937 __le32 enables;
3938 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID 0x1UL
3939 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID 0x2UL
3940 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID 0x4UL
3941 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID 0x8UL
3942 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID 0x10UL
3943 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID 0x20UL
3944 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID 0x40UL
3945 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID 0x80UL
3946 u8 port_id;
3947 u8 pri0_cos_queue_id;
3948 u8 pri1_cos_queue_id;
3949 u8 pri2_cos_queue_id;
3950 u8 pri3_cos_queue_id;
3951 u8 pri4_cos_queue_id;
3952 u8 pri5_cos_queue_id;
3953 u8 pri6_cos_queue_id;
3954 u8 pri7_cos_queue_id;
3955 u8 unused_0[7];
3956 };
3957
3958 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */
3959 struct hwrm_queue_pri2cos_cfg_output {
3960 __le16 error_code;
3961 __le16 req_type;
3962 __le16 seq_id;
3963 __le16 resp_len;
3964 u8 unused_0[7];
3965 u8 valid;
3966 };
3967
3968 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */
3969 struct hwrm_queue_cos2bw_qcfg_input {
3970 __le16 req_type;
3971 __le16 cmpl_ring;
3972 __le16 seq_id;
3973 __le16 target_id;
3974 __le64 resp_addr;
3975 __le16 port_id;
3976 u8 unused_0[6];
3977 };
3978
3979 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */
3980 struct hwrm_queue_cos2bw_qcfg_output {
3981 __le16 error_code;
3982 __le16 req_type;
3983 __le16 seq_id;
3984 __le16 resp_len;
3985 u8 queue_id0;
3986 u8 unused_0;
3987 __le16 unused_1;
3988 __le32 queue_id0_min_bw;
3989 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL
3990 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0
3991 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL
3992 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28)
3993 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28)
3994 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES
3995 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
3996 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29
3997 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
3998 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
3999 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4000 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4001 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4002 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4003 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
4004 __le32 queue_id0_max_bw;
4005 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL
4006 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0
4007 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL
4008 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28)
4009 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28)
4010 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES
4011 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4012 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29
4013 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4014 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4015 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4016 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4017 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4018 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4019 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
4020 u8 queue_id0_tsa_assign;
4021 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL
4022 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL
4023 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4024 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL
4025 u8 queue_id0_pri_lvl;
4026 u8 queue_id0_bw_weight;
4027 u8 queue_id1;
4028 __le32 queue_id1_min_bw;
4029 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL
4030 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0
4031 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL
4032 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28)
4033 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28)
4034 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES
4035 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4036 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29
4037 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4038 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4039 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4040 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4041 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4042 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4043 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
4044 __le32 queue_id1_max_bw;
4045 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL
4046 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0
4047 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL
4048 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28)
4049 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28)
4050 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES
4051 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4052 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29
4053 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4054 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4055 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4056 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4057 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4058 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4059 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
4060 u8 queue_id1_tsa_assign;
4061 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL
4062 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL
4063 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4064 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL
4065 u8 queue_id1_pri_lvl;
4066 u8 queue_id1_bw_weight;
4067 u8 queue_id2;
4068 __le32 queue_id2_min_bw;
4069 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL
4070 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0
4071 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL
4072 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28)
4073 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28)
4074 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES
4075 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4076 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29
4077 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4078 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4079 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4080 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4081 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4082 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4083 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
4084 __le32 queue_id2_max_bw;
4085 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL
4086 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0
4087 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL
4088 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28)
4089 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28)
4090 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES
4091 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4092 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29
4093 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4094 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4095 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4096 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4097 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4098 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4099 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
4100 u8 queue_id2_tsa_assign;
4101 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL
4102 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL
4103 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4104 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL
4105 u8 queue_id2_pri_lvl;
4106 u8 queue_id2_bw_weight;
4107 u8 queue_id3;
4108 __le32 queue_id3_min_bw;
4109 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL
4110 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0
4111 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL
4112 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28)
4113 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28)
4114 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES
4115 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4116 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29
4117 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4118 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4119 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4120 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4121 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4122 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4123 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
4124 __le32 queue_id3_max_bw;
4125 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL
4126 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0
4127 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL
4128 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28)
4129 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28)
4130 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES
4131 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4132 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29
4133 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4134 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4135 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4136 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4137 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4138 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4139 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
4140 u8 queue_id3_tsa_assign;
4141 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL
4142 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL
4143 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4144 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL
4145 u8 queue_id3_pri_lvl;
4146 u8 queue_id3_bw_weight;
4147 u8 queue_id4;
4148 __le32 queue_id4_min_bw;
4149 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL
4150 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0
4151 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL
4152 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28)
4153 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28)
4154 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES
4155 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4156 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29
4157 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4158 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4159 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4160 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4161 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4162 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4163 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
4164 __le32 queue_id4_max_bw;
4165 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL
4166 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0
4167 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL
4168 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28)
4169 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28)
4170 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES
4171 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4172 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29
4173 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4174 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4175 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4176 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4177 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4178 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4179 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
4180 u8 queue_id4_tsa_assign;
4181 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL
4182 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL
4183 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4184 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL
4185 u8 queue_id4_pri_lvl;
4186 u8 queue_id4_bw_weight;
4187 u8 queue_id5;
4188 __le32 queue_id5_min_bw;
4189 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL
4190 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0
4191 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL
4192 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28)
4193 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28)
4194 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES
4195 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4196 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29
4197 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4198 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4199 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4200 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4201 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4202 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4203 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
4204 __le32 queue_id5_max_bw;
4205 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL
4206 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0
4207 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL
4208 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28)
4209 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28)
4210 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES
4211 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4212 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29
4213 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4214 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4215 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4216 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4217 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4218 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4219 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
4220 u8 queue_id5_tsa_assign;
4221 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL
4222 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL
4223 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4224 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL
4225 u8 queue_id5_pri_lvl;
4226 u8 queue_id5_bw_weight;
4227 u8 queue_id6;
4228 __le32 queue_id6_min_bw;
4229 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL
4230 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0
4231 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL
4232 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28)
4233 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28)
4234 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES
4235 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4236 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29
4237 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4238 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4239 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4240 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4241 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4242 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4243 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
4244 __le32 queue_id6_max_bw;
4245 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL
4246 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0
4247 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL
4248 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28)
4249 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28)
4250 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES
4251 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4252 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29
4253 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4254 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4255 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4256 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4257 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4258 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4259 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
4260 u8 queue_id6_tsa_assign;
4261 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL
4262 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL
4263 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4264 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL
4265 u8 queue_id6_pri_lvl;
4266 u8 queue_id6_bw_weight;
4267 u8 queue_id7;
4268 __le32 queue_id7_min_bw;
4269 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL
4270 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0
4271 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL
4272 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28)
4273 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28)
4274 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES
4275 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4276 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29
4277 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4278 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4279 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4280 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4281 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4282 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4283 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
4284 __le32 queue_id7_max_bw;
4285 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL
4286 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0
4287 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL
4288 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28)
4289 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28)
4290 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES
4291 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4292 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29
4293 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4294 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4295 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4296 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4297 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4298 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4299 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
4300 u8 queue_id7_tsa_assign;
4301 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL
4302 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL
4303 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4304 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL
4305 u8 queue_id7_pri_lvl;
4306 u8 queue_id7_bw_weight;
4307 u8 unused_2[4];
4308 u8 valid;
4309 };
4310
4311 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */
4312 struct hwrm_queue_cos2bw_cfg_input {
4313 __le16 req_type;
4314 __le16 cmpl_ring;
4315 __le16 seq_id;
4316 __le16 target_id;
4317 __le64 resp_addr;
4318 __le32 flags;
4319 __le32 enables;
4320 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL
4321 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL
4322 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL
4323 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL
4324 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL
4325 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL
4326 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL
4327 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL
4328 __le16 port_id;
4329 u8 queue_id0;
4330 u8 unused_0;
4331 __le32 queue_id0_min_bw;
4332 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL
4333 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0
4334 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL
4335 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28)
4336 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28)
4337 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES
4338 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4339 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29
4340 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4341 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4342 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4343 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4344 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4345 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4346 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
4347 __le32 queue_id0_max_bw;
4348 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL
4349 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0
4350 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL
4351 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28)
4352 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28)
4353 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES
4354 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4355 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29
4356 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4357 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4358 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4359 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4360 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4361 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4362 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
4363 u8 queue_id0_tsa_assign;
4364 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL
4365 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL
4366 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4367 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL
4368 u8 queue_id0_pri_lvl;
4369 u8 queue_id0_bw_weight;
4370 u8 queue_id1;
4371 __le32 queue_id1_min_bw;
4372 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL
4373 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0
4374 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL
4375 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28)
4376 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28)
4377 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES
4378 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4379 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29
4380 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4381 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4382 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4383 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4384 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4385 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4386 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
4387 __le32 queue_id1_max_bw;
4388 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL
4389 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0
4390 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL
4391 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28)
4392 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28)
4393 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES
4394 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4395 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29
4396 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4397 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4398 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4399 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4400 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4401 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4402 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
4403 u8 queue_id1_tsa_assign;
4404 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL
4405 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL
4406 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4407 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL
4408 u8 queue_id1_pri_lvl;
4409 u8 queue_id1_bw_weight;
4410 u8 queue_id2;
4411 __le32 queue_id2_min_bw;
4412 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL
4413 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0
4414 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL
4415 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28)
4416 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28)
4417 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES
4418 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4419 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29
4420 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4421 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4422 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4423 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4424 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4425 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4426 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
4427 __le32 queue_id2_max_bw;
4428 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL
4429 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0
4430 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL
4431 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28)
4432 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28)
4433 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES
4434 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4435 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29
4436 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4437 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4438 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4439 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4440 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4441 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4442 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
4443 u8 queue_id2_tsa_assign;
4444 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL
4445 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL
4446 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4447 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL
4448 u8 queue_id2_pri_lvl;
4449 u8 queue_id2_bw_weight;
4450 u8 queue_id3;
4451 __le32 queue_id3_min_bw;
4452 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL
4453 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0
4454 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL
4455 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28)
4456 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28)
4457 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES
4458 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4459 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29
4460 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4461 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4462 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4463 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4464 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4465 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4466 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
4467 __le32 queue_id3_max_bw;
4468 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL
4469 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0
4470 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL
4471 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28)
4472 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28)
4473 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES
4474 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4475 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29
4476 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4477 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4478 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4479 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4480 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4481 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4482 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
4483 u8 queue_id3_tsa_assign;
4484 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL
4485 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL
4486 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4487 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL
4488 u8 queue_id3_pri_lvl;
4489 u8 queue_id3_bw_weight;
4490 u8 queue_id4;
4491 __le32 queue_id4_min_bw;
4492 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL
4493 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0
4494 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL
4495 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28)
4496 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28)
4497 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES
4498 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4499 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29
4500 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4501 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4502 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4503 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4504 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4505 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4506 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
4507 __le32 queue_id4_max_bw;
4508 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL
4509 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0
4510 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL
4511 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28)
4512 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28)
4513 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES
4514 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4515 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29
4516 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4517 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4518 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4519 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4520 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4521 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4522 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
4523 u8 queue_id4_tsa_assign;
4524 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL
4525 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL
4526 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4527 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL
4528 u8 queue_id4_pri_lvl;
4529 u8 queue_id4_bw_weight;
4530 u8 queue_id5;
4531 __le32 queue_id5_min_bw;
4532 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL
4533 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0
4534 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL
4535 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28)
4536 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28)
4537 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES
4538 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4539 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29
4540 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4541 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4542 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4543 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4544 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4545 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4546 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
4547 __le32 queue_id5_max_bw;
4548 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL
4549 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0
4550 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL
4551 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28)
4552 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28)
4553 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES
4554 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4555 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29
4556 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4557 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4558 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4559 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4560 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4561 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4562 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
4563 u8 queue_id5_tsa_assign;
4564 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL
4565 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL
4566 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4567 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL
4568 u8 queue_id5_pri_lvl;
4569 u8 queue_id5_bw_weight;
4570 u8 queue_id6;
4571 __le32 queue_id6_min_bw;
4572 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL
4573 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0
4574 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL
4575 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28)
4576 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28)
4577 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES
4578 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4579 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29
4580 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4581 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4582 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4583 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4584 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4585 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4586 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
4587 __le32 queue_id6_max_bw;
4588 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL
4589 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0
4590 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL
4591 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28)
4592 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28)
4593 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES
4594 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4595 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29
4596 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4597 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4598 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4599 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4600 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4601 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4602 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
4603 u8 queue_id6_tsa_assign;
4604 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL
4605 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL
4606 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4607 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL
4608 u8 queue_id6_pri_lvl;
4609 u8 queue_id6_bw_weight;
4610 u8 queue_id7;
4611 __le32 queue_id7_min_bw;
4612 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL
4613 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0
4614 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL
4615 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28)
4616 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28)
4617 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES
4618 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4619 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29
4620 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4621 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4622 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4623 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4624 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4625 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4626 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
4627 __le32 queue_id7_max_bw;
4628 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL
4629 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0
4630 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL
4631 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28)
4632 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28)
4633 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES
4634 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
4635 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29
4636 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
4637 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
4638 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
4639 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
4640 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
4641 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
4642 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
4643 u8 queue_id7_tsa_assign;
4644 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL
4645 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL
4646 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL
4647 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL
4648 u8 queue_id7_pri_lvl;
4649 u8 queue_id7_bw_weight;
4650 u8 unused_1[5];
4651 };
4652
4653 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */
4654 struct hwrm_queue_cos2bw_cfg_output {
4655 __le16 error_code;
4656 __le16 req_type;
4657 __le16 seq_id;
4658 __le16 resp_len;
4659 u8 unused_0[7];
4660 u8 valid;
4661 };
4662
4663 /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */
4664 struct hwrm_queue_dscp_qcaps_input {
4665 __le16 req_type;
4666 __le16 cmpl_ring;
4667 __le16 seq_id;
4668 __le16 target_id;
4669 __le64 resp_addr;
4670 u8 port_id;
4671 u8 unused_0[7];
4672 };
4673
4674 /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */
4675 struct hwrm_queue_dscp_qcaps_output {
4676 __le16 error_code;
4677 __le16 req_type;
4678 __le16 seq_id;
4679 __le16 resp_len;
4680 u8 num_dscp_bits;
4681 u8 unused_0;
4682 __le16 max_entries;
4683 u8 unused_1[3];
4684 u8 valid;
4685 };
4686
4687 /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */
4688 struct hwrm_queue_dscp2pri_qcfg_input {
4689 __le16 req_type;
4690 __le16 cmpl_ring;
4691 __le16 seq_id;
4692 __le16 target_id;
4693 __le64 resp_addr;
4694 __le64 dest_data_addr;
4695 u8 port_id;
4696 u8 unused_0;
4697 __le16 dest_data_buffer_size;
4698 u8 unused_1[4];
4699 };
4700
4701 /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */
4702 struct hwrm_queue_dscp2pri_qcfg_output {
4703 __le16 error_code;
4704 __le16 req_type;
4705 __le16 seq_id;
4706 __le16 resp_len;
4707 __le16 entry_cnt;
4708 u8 default_pri;
4709 u8 unused_0[4];
4710 u8 valid;
4711 };
4712
4713 /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */
4714 struct hwrm_queue_dscp2pri_cfg_input {
4715 __le16 req_type;
4716 __le16 cmpl_ring;
4717 __le16 seq_id;
4718 __le16 target_id;
4719 __le64 resp_addr;
4720 __le64 src_data_addr;
4721 __le32 flags;
4722 #define QUEUE_DSCP2PRI_CFG_REQ_FLAGS_USE_HW_DEFAULT_PRI 0x1UL
4723 __le32 enables;
4724 #define QUEUE_DSCP2PRI_CFG_REQ_ENABLES_DEFAULT_PRI 0x1UL
4725 u8 port_id;
4726 u8 default_pri;
4727 __le16 entry_cnt;
4728 u8 unused_0[4];
4729 };
4730
4731 /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */
4732 struct hwrm_queue_dscp2pri_cfg_output {
4733 __le16 error_code;
4734 __le16 req_type;
4735 __le16 seq_id;
4736 __le16 resp_len;
4737 u8 unused_0[7];
4738 u8 valid;
4739 };
4740
4741 /* hwrm_vnic_alloc_input (size:192b/24B) */
4742 struct hwrm_vnic_alloc_input {
4743 __le16 req_type;
4744 __le16 cmpl_ring;
4745 __le16 seq_id;
4746 __le16 target_id;
4747 __le64 resp_addr;
4748 __le32 flags;
4749 #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL
4750 u8 unused_0[4];
4751 };
4752
4753 /* hwrm_vnic_alloc_output (size:128b/16B) */
4754 struct hwrm_vnic_alloc_output {
4755 __le16 error_code;
4756 __le16 req_type;
4757 __le16 seq_id;
4758 __le16 resp_len;
4759 __le32 vnic_id;
4760 u8 unused_0[3];
4761 u8 valid;
4762 };
4763
4764 /* hwrm_vnic_free_input (size:192b/24B) */
4765 struct hwrm_vnic_free_input {
4766 __le16 req_type;
4767 __le16 cmpl_ring;
4768 __le16 seq_id;
4769 __le16 target_id;
4770 __le64 resp_addr;
4771 __le32 vnic_id;
4772 u8 unused_0[4];
4773 };
4774
4775 /* hwrm_vnic_free_output (size:128b/16B) */
4776 struct hwrm_vnic_free_output {
4777 __le16 error_code;
4778 __le16 req_type;
4779 __le16 seq_id;
4780 __le16 resp_len;
4781 u8 unused_0[7];
4782 u8 valid;
4783 };
4784
4785 /* hwrm_vnic_cfg_input (size:384b/48B) */
4786 struct hwrm_vnic_cfg_input {
4787 __le16 req_type;
4788 __le16 cmpl_ring;
4789 __le16 seq_id;
4790 __le16 target_id;
4791 __le64 resp_addr;
4792 __le32 flags;
4793 #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL
4794 #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL
4795 #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL
4796 #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL
4797 #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL
4798 #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL
4799 #define VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE 0x40UL
4800 __le32 enables;
4801 #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL
4802 #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL
4803 #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL
4804 #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL
4805 #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL
4806 #define VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID 0x20UL
4807 #define VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID 0x40UL
4808 #define VNIC_CFG_REQ_ENABLES_QUEUE_ID 0x80UL
4809 __le16 vnic_id;
4810 __le16 dflt_ring_grp;
4811 __le16 rss_rule;
4812 __le16 cos_rule;
4813 __le16 lb_rule;
4814 __le16 mru;
4815 __le16 default_rx_ring_id;
4816 __le16 default_cmpl_ring_id;
4817 __le16 queue_id;
4818 u8 unused0[6];
4819 };
4820
4821 /* hwrm_vnic_cfg_output (size:128b/16B) */
4822 struct hwrm_vnic_cfg_output {
4823 __le16 error_code;
4824 __le16 req_type;
4825 __le16 seq_id;
4826 __le16 resp_len;
4827 u8 unused_0[7];
4828 u8 valid;
4829 };
4830
4831 /* hwrm_vnic_qcaps_input (size:192b/24B) */
4832 struct hwrm_vnic_qcaps_input {
4833 __le16 req_type;
4834 __le16 cmpl_ring;
4835 __le16 seq_id;
4836 __le16 target_id;
4837 __le64 resp_addr;
4838 __le32 enables;
4839 u8 unused_0[4];
4840 };
4841
4842 /* hwrm_vnic_qcaps_output (size:192b/24B) */
4843 struct hwrm_vnic_qcaps_output {
4844 __le16 error_code;
4845 __le16 req_type;
4846 __le16 seq_id;
4847 __le16 resp_len;
4848 __le16 mru;
4849 u8 unused_0[2];
4850 __le32 flags;
4851 #define VNIC_QCAPS_RESP_FLAGS_UNUSED 0x1UL
4852 #define VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP 0x2UL
4853 #define VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP 0x4UL
4854 #define VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP 0x8UL
4855 #define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP 0x10UL
4856 #define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP 0x20UL
4857 #define VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP 0x40UL
4858 #define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_CAP 0x80UL
4859 #define VNIC_QCAPS_RESP_FLAGS_COS_ASSIGNMENT_CAP 0x100UL
4860 __le16 max_aggs_supported;
4861 u8 unused_1[5];
4862 u8 valid;
4863 };
4864
4865 /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */
4866 struct hwrm_vnic_tpa_cfg_input {
4867 __le16 req_type;
4868 __le16 cmpl_ring;
4869 __le16 seq_id;
4870 __le16 target_id;
4871 __le64 resp_addr;
4872 __le32 flags;
4873 #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL
4874 #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL
4875 #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL
4876 #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL
4877 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL
4878 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL
4879 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL
4880 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL
4881 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_PACK_AS_GRO 0x100UL
4882 __le32 enables;
4883 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL
4884 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL
4885 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL
4886 #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL
4887 __le16 vnic_id;
4888 __le16 max_agg_segs;
4889 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 0x0UL
4890 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 0x1UL
4891 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 0x2UL
4892 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 0x3UL
4893 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL
4894 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_LAST VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX
4895 __le16 max_aggs;
4896 #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 0x0UL
4897 #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 0x1UL
4898 #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 0x2UL
4899 #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 0x3UL
4900 #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 0x4UL
4901 #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL
4902 #define VNIC_TPA_CFG_REQ_MAX_AGGS_LAST VNIC_TPA_CFG_REQ_MAX_AGGS_MAX
4903 u8 unused_0[2];
4904 __le32 max_agg_timer;
4905 __le32 min_agg_len;
4906 };
4907
4908 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */
4909 struct hwrm_vnic_tpa_cfg_output {
4910 __le16 error_code;
4911 __le16 req_type;
4912 __le16 seq_id;
4913 __le16 resp_len;
4914 u8 unused_0[7];
4915 u8 valid;
4916 };
4917
4918 /* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */
4919 struct hwrm_vnic_tpa_qcfg_input {
4920 __le16 req_type;
4921 __le16 cmpl_ring;
4922 __le16 seq_id;
4923 __le16 target_id;
4924 __le64 resp_addr;
4925 __le16 vnic_id;
4926 u8 unused_0[6];
4927 };
4928
4929 /* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */
4930 struct hwrm_vnic_tpa_qcfg_output {
4931 __le16 error_code;
4932 __le16 req_type;
4933 __le16 seq_id;
4934 __le16 resp_len;
4935 __le32 flags;
4936 #define VNIC_TPA_QCFG_RESP_FLAGS_TPA 0x1UL
4937 #define VNIC_TPA_QCFG_RESP_FLAGS_ENCAP_TPA 0x2UL
4938 #define VNIC_TPA_QCFG_RESP_FLAGS_RSC_WND_UPDATE 0x4UL
4939 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO 0x8UL
4940 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_ECN 0x10UL
4941 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL
4942 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_IPID_CHECK 0x40UL
4943 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_TTL_CHECK 0x80UL
4944 __le16 max_agg_segs;
4945 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_1 0x0UL
4946 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_2 0x1UL
4947 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_4 0x2UL
4948 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_8 0x3UL
4949 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 0x1fUL
4950 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX
4951 __le16 max_aggs;
4952 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_1 0x0UL
4953 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_2 0x1UL
4954 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_4 0x2UL
4955 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_8 0x3UL
4956 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_16 0x4UL
4957 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 0x7UL
4958 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX
4959 __le32 max_agg_timer;
4960 __le32 min_agg_len;
4961 u8 unused_0[7];
4962 u8 valid;
4963 };
4964
4965 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */
4966 struct hwrm_vnic_rss_cfg_input {
4967 __le16 req_type;
4968 __le16 cmpl_ring;
4969 __le16 seq_id;
4970 __le16 target_id;
4971 __le64 resp_addr;
4972 __le32 hash_type;
4973 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL
4974 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL
4975 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL
4976 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL
4977 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL
4978 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL
4979 __le16 vnic_id;
4980 u8 ring_table_pair_index;
4981 u8 hash_mode_flags;
4982 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT 0x1UL
4983 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_4 0x2UL
4984 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_2 0x4UL
4985 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_4 0x8UL
4986 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_2 0x10UL
4987 __le64 ring_grp_tbl_addr;
4988 __le64 hash_key_tbl_addr;
4989 __le16 rss_ctx_idx;
4990 u8 unused_1[6];
4991 };
4992
4993 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */
4994 struct hwrm_vnic_rss_cfg_output {
4995 __le16 error_code;
4996 __le16 req_type;
4997 __le16 seq_id;
4998 __le16 resp_len;
4999 u8 unused_0[7];
5000 u8 valid;
5001 };
5002
5003 /* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */
5004 struct hwrm_vnic_rss_cfg_cmd_err {
5005 u8 code;
5006 #define VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL
5007 #define VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 0x1UL
5008 #define VNIC_RSS_CFG_CMD_ERR_CODE_LAST VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY
5009 u8 unused_0[7];
5010 };
5011
5012 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */
5013 struct hwrm_vnic_plcmodes_cfg_input {
5014 __le16 req_type;
5015 __le16 cmpl_ring;
5016 __le16 seq_id;
5017 __le16 target_id;
5018 __le64 resp_addr;
5019 __le32 flags;
5020 #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL
5021 #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL
5022 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL
5023 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL
5024 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL
5025 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL
5026 __le32 enables;
5027 #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL
5028 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL
5029 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL
5030 __le32 vnic_id;
5031 __le16 jumbo_thresh;
5032 __le16 hds_offset;
5033 __le16 hds_threshold;
5034 u8 unused_0[6];
5035 };
5036
5037 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */
5038 struct hwrm_vnic_plcmodes_cfg_output {
5039 __le16 error_code;
5040 __le16 req_type;
5041 __le16 seq_id;
5042 __le16 resp_len;
5043 u8 unused_0[7];
5044 u8 valid;
5045 };
5046
5047 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */
5048 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
5049 __le16 req_type;
5050 __le16 cmpl_ring;
5051 __le16 seq_id;
5052 __le16 target_id;
5053 __le64 resp_addr;
5054 };
5055
5056 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */
5057 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {
5058 __le16 error_code;
5059 __le16 req_type;
5060 __le16 seq_id;
5061 __le16 resp_len;
5062 __le16 rss_cos_lb_ctx_id;
5063 u8 unused_0[5];
5064 u8 valid;
5065 };
5066
5067 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */
5068 struct hwrm_vnic_rss_cos_lb_ctx_free_input {
5069 __le16 req_type;
5070 __le16 cmpl_ring;
5071 __le16 seq_id;
5072 __le16 target_id;
5073 __le64 resp_addr;
5074 __le16 rss_cos_lb_ctx_id;
5075 u8 unused_0[6];
5076 };
5077
5078 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */
5079 struct hwrm_vnic_rss_cos_lb_ctx_free_output {
5080 __le16 error_code;
5081 __le16 req_type;
5082 __le16 seq_id;
5083 __le16 resp_len;
5084 u8 unused_0[7];
5085 u8 valid;
5086 };
5087
5088 /* hwrm_ring_alloc_input (size:704b/88B) */
5089 struct hwrm_ring_alloc_input {
5090 __le16 req_type;
5091 __le16 cmpl_ring;
5092 __le16 seq_id;
5093 __le16 target_id;
5094 __le64 resp_addr;
5095 __le32 enables;
5096 #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL
5097 #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL
5098 #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL
5099 #define RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID 0x40UL
5100 #define RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID 0x80UL
5101 #define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID 0x100UL
5102 u8 ring_type;
5103 #define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL
5104 #define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL
5105 #define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL
5106 #define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL
5107 #define RING_ALLOC_REQ_RING_TYPE_RX_AGG 0x4UL
5108 #define RING_ALLOC_REQ_RING_TYPE_NQ 0x5UL
5109 #define RING_ALLOC_REQ_RING_TYPE_LAST RING_ALLOC_REQ_RING_TYPE_NQ
5110 u8 unused_0;
5111 __le16 flags;
5112 #define RING_ALLOC_REQ_FLAGS_RX_SOP_PAD 0x1UL
5113 __le64 page_tbl_addr;
5114 __le32 fbo;
5115 u8 page_size;
5116 u8 page_tbl_depth;
5117 u8 unused_1[2];
5118 __le32 length;
5119 __le16 logical_id;
5120 __le16 cmpl_ring_id;
5121 __le16 queue_id;
5122 __le16 rx_buf_size;
5123 __le16 rx_ring_id;
5124 __le16 nq_ring_id;
5125 __le16 ring_arb_cfg;
5126 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK 0xfUL
5127 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT 0
5128 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP 0x1UL
5129 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 0x2UL
5130 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ
5131 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK 0xf0UL
5132 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT 4
5133 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL
5134 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8
5135 __le16 unused_3;
5136 __le32 reserved3;
5137 __le32 stat_ctx_id;
5138 __le32 reserved4;
5139 __le32 max_bw;
5140 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL
5141 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT 0
5142 #define RING_ALLOC_REQ_MAX_BW_SCALE 0x10000000UL
5143 #define RING_ALLOC_REQ_MAX_BW_SCALE_BITS (0x0UL << 28)
5144 #define RING_ALLOC_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28)
5145 #define RING_ALLOC_REQ_MAX_BW_SCALE_LAST RING_ALLOC_REQ_MAX_BW_SCALE_BYTES
5146 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
5147 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29
5148 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
5149 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
5150 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
5151 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
5152 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
5153 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
5154 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID
5155 u8 int_mode;
5156 #define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL
5157 #define RING_ALLOC_REQ_INT_MODE_RSVD 0x1UL
5158 #define RING_ALLOC_REQ_INT_MODE_MSIX 0x2UL
5159 #define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL
5160 #define RING_ALLOC_REQ_INT_MODE_LAST RING_ALLOC_REQ_INT_MODE_POLL
5161 u8 unused_4[3];
5162 __le64 cq_handle;
5163 };
5164
5165 /* hwrm_ring_alloc_output (size:128b/16B) */
5166 struct hwrm_ring_alloc_output {
5167 __le16 error_code;
5168 __le16 req_type;
5169 __le16 seq_id;
5170 __le16 resp_len;
5171 __le16 ring_id;
5172 __le16 logical_ring_id;
5173 u8 unused_0[3];
5174 u8 valid;
5175 };
5176
5177 /* hwrm_ring_free_input (size:192b/24B) */
5178 struct hwrm_ring_free_input {
5179 __le16 req_type;
5180 __le16 cmpl_ring;
5181 __le16 seq_id;
5182 __le16 target_id;
5183 __le64 resp_addr;
5184 u8 ring_type;
5185 #define RING_FREE_REQ_RING_TYPE_L2_CMPL 0x0UL
5186 #define RING_FREE_REQ_RING_TYPE_TX 0x1UL
5187 #define RING_FREE_REQ_RING_TYPE_RX 0x2UL
5188 #define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL
5189 #define RING_FREE_REQ_RING_TYPE_RX_AGG 0x4UL
5190 #define RING_FREE_REQ_RING_TYPE_NQ 0x5UL
5191 #define RING_FREE_REQ_RING_TYPE_LAST RING_FREE_REQ_RING_TYPE_NQ
5192 u8 unused_0;
5193 __le16 ring_id;
5194 u8 unused_1[4];
5195 };
5196
5197 /* hwrm_ring_free_output (size:128b/16B) */
5198 struct hwrm_ring_free_output {
5199 __le16 error_code;
5200 __le16 req_type;
5201 __le16 seq_id;
5202 __le16 resp_len;
5203 u8 unused_0[7];
5204 u8 valid;
5205 };
5206
5207 /* hwrm_ring_reset_input (size:192b/24B) */
5208 struct hwrm_ring_reset_input {
5209 __le16 req_type;
5210 __le16 cmpl_ring;
5211 __le16 seq_id;
5212 __le16 target_id;
5213 __le64 resp_addr;
5214 u8 ring_type;
5215 #define RING_RESET_REQ_RING_TYPE_L2_CMPL 0x0UL
5216 #define RING_RESET_REQ_RING_TYPE_TX 0x1UL
5217 #define RING_RESET_REQ_RING_TYPE_RX 0x2UL
5218 #define RING_RESET_REQ_RING_TYPE_ROCE_CMPL 0x3UL
5219 #define RING_RESET_REQ_RING_TYPE_LAST RING_RESET_REQ_RING_TYPE_ROCE_CMPL
5220 u8 unused_0;
5221 __le16 ring_id;
5222 u8 unused_1[4];
5223 };
5224
5225 /* hwrm_ring_reset_output (size:128b/16B) */
5226 struct hwrm_ring_reset_output {
5227 __le16 error_code;
5228 __le16 req_type;
5229 __le16 seq_id;
5230 __le16 resp_len;
5231 u8 unused_0[4];
5232 u8 consumer_idx[3];
5233 u8 valid;
5234 };
5235
5236 /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */
5237 struct hwrm_ring_aggint_qcaps_input {
5238 __le16 req_type;
5239 __le16 cmpl_ring;
5240 __le16 seq_id;
5241 __le16 target_id;
5242 __le64 resp_addr;
5243 };
5244
5245 /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */
5246 struct hwrm_ring_aggint_qcaps_output {
5247 __le16 error_code;
5248 __le16 req_type;
5249 __le16 seq_id;
5250 __le16 resp_len;
5251 __le32 cmpl_params;
5252 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN 0x1UL
5253 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX 0x2UL
5254 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET 0x4UL
5255 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE 0x8UL
5256 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR 0x10UL
5257 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT 0x20UL
5258 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR 0x40UL
5259 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT 0x80UL
5260 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT 0x100UL
5261 __le32 nq_params;
5262 #define RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN 0x1UL
5263 __le16 num_cmpl_dma_aggr_min;
5264 __le16 num_cmpl_dma_aggr_max;
5265 __le16 num_cmpl_dma_aggr_during_int_min;
5266 __le16 num_cmpl_dma_aggr_during_int_max;
5267 __le16 cmpl_aggr_dma_tmr_min;
5268 __le16 cmpl_aggr_dma_tmr_max;
5269 __le16 cmpl_aggr_dma_tmr_during_int_min;
5270 __le16 cmpl_aggr_dma_tmr_during_int_max;
5271 __le16 int_lat_tmr_min_min;
5272 __le16 int_lat_tmr_min_max;
5273 __le16 int_lat_tmr_max_min;
5274 __le16 int_lat_tmr_max_max;
5275 __le16 num_cmpl_aggr_int_min;
5276 __le16 num_cmpl_aggr_int_max;
5277 __le16 timer_units;
5278 u8 unused_0[1];
5279 u8 valid;
5280 };
5281
5282 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */
5283 struct hwrm_ring_cmpl_ring_qaggint_params_input {
5284 __le16 req_type;
5285 __le16 cmpl_ring;
5286 __le16 seq_id;
5287 __le16 target_id;
5288 __le64 resp_addr;
5289 __le16 ring_id;
5290 u8 unused_0[6];
5291 };
5292
5293 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */
5294 struct hwrm_ring_cmpl_ring_qaggint_params_output {
5295 __le16 error_code;
5296 __le16 req_type;
5297 __le16 seq_id;
5298 __le16 resp_len;
5299 __le16 flags;
5300 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL
5301 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL
5302 __le16 num_cmpl_dma_aggr;
5303 __le16 num_cmpl_dma_aggr_during_int;
5304 __le16 cmpl_aggr_dma_tmr;
5305 __le16 cmpl_aggr_dma_tmr_during_int;
5306 __le16 int_lat_tmr_min;
5307 __le16 int_lat_tmr_max;
5308 __le16 num_cmpl_aggr_int;
5309 u8 unused_0[7];
5310 u8 valid;
5311 };
5312
5313 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */
5314 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
5315 __le16 req_type;
5316 __le16 cmpl_ring;
5317 __le16 seq_id;
5318 __le16 target_id;
5319 __le64 resp_addr;
5320 __le16 ring_id;
5321 __le16 flags;
5322 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL
5323 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL
5324 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL
5325 __le16 num_cmpl_dma_aggr;
5326 __le16 num_cmpl_dma_aggr_during_int;
5327 __le16 cmpl_aggr_dma_tmr;
5328 __le16 cmpl_aggr_dma_tmr_during_int;
5329 __le16 int_lat_tmr_min;
5330 __le16 int_lat_tmr_max;
5331 __le16 num_cmpl_aggr_int;
5332 __le16 enables;
5333 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR 0x1UL
5334 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT 0x2UL
5335 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR 0x4UL
5336 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN 0x8UL
5337 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX 0x10UL
5338 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT 0x20UL
5339 u8 unused_0[4];
5340 };
5341
5342 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */
5343 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {
5344 __le16 error_code;
5345 __le16 req_type;
5346 __le16 seq_id;
5347 __le16 resp_len;
5348 u8 unused_0[7];
5349 u8 valid;
5350 };
5351
5352 /* hwrm_ring_grp_alloc_input (size:192b/24B) */
5353 struct hwrm_ring_grp_alloc_input {
5354 __le16 req_type;
5355 __le16 cmpl_ring;
5356 __le16 seq_id;
5357 __le16 target_id;
5358 __le64 resp_addr;
5359 __le16 cr;
5360 __le16 rr;
5361 __le16 ar;
5362 __le16 sc;
5363 };
5364
5365 /* hwrm_ring_grp_alloc_output (size:128b/16B) */
5366 struct hwrm_ring_grp_alloc_output {
5367 __le16 error_code;
5368 __le16 req_type;
5369 __le16 seq_id;
5370 __le16 resp_len;
5371 __le32 ring_group_id;
5372 u8 unused_0[3];
5373 u8 valid;
5374 };
5375
5376 /* hwrm_ring_grp_free_input (size:192b/24B) */
5377 struct hwrm_ring_grp_free_input {
5378 __le16 req_type;
5379 __le16 cmpl_ring;
5380 __le16 seq_id;
5381 __le16 target_id;
5382 __le64 resp_addr;
5383 __le32 ring_group_id;
5384 u8 unused_0[4];
5385 };
5386
5387 /* hwrm_ring_grp_free_output (size:128b/16B) */
5388 struct hwrm_ring_grp_free_output {
5389 __le16 error_code;
5390 __le16 req_type;
5391 __le16 seq_id;
5392 __le16 resp_len;
5393 u8 unused_0[7];
5394 u8 valid;
5395 };
5396 #define DEFAULT_FLOW_ID 0xFFFFFFFFUL
5397 #define ROCEV1_FLOW_ID 0xFFFFFFFEUL
5398 #define ROCEV2_FLOW_ID 0xFFFFFFFDUL
5399 #define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL
5400
5401 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */
5402 struct hwrm_cfa_l2_filter_alloc_input {
5403 __le16 req_type;
5404 __le16 cmpl_ring;
5405 __le16 seq_id;
5406 __le16 target_id;
5407 __le64 resp_addr;
5408 __le32 flags;
5409 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL
5410 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX 0x0UL
5411 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 0x1UL
5412 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX
5413 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL
5414 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL
5415 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL
5416 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_MASK 0x30UL
5417 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_SFT 4
5418 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 4)
5419 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 4)
5420 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 4)
5421 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE
5422 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_XDP_DISABLE 0x40UL
5423 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_SOURCE_VALID 0x80UL
5424 __le32 enables;
5425 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL
5426 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL
5427 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL
5428 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL
5429 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL
5430 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL
5431 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL
5432 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL
5433 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL
5434 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL
5435 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL
5436 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL
5437 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL
5438 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL
5439 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL
5440 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL
5441 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL
5442 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_NUM_VLANS 0x20000UL
5443 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_NUM_VLANS 0x40000UL
5444 u8 l2_addr[6];
5445 u8 num_vlans;
5446 u8 t_num_vlans;
5447 u8 l2_addr_mask[6];
5448 __le16 l2_ovlan;
5449 __le16 l2_ovlan_mask;
5450 __le16 l2_ivlan;
5451 __le16 l2_ivlan_mask;
5452 u8 unused_1[2];
5453 u8 t_l2_addr[6];
5454 u8 unused_2[2];
5455 u8 t_l2_addr_mask[6];
5456 __le16 t_l2_ovlan;
5457 __le16 t_l2_ovlan_mask;
5458 __le16 t_l2_ivlan;
5459 __le16 t_l2_ivlan_mask;
5460 u8 src_type;
5461 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL
5462 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF 0x1UL
5463 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF 0x2UL
5464 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC 0x3UL
5465 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG 0x4UL
5466 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE 0x5UL
5467 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO 0x6UL
5468 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 0x7UL
5469 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG
5470 u8 unused_3;
5471 __le32 src_id;
5472 u8 tunnel_type;
5473 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
5474 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
5475 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
5476 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
5477 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
5478 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
5479 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
5480 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
5481 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
5482 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
5483 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
5484 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
5485 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
5486 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
5487 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
5488 u8 unused_4;
5489 __le16 dst_id;
5490 __le16 mirror_vnic_id;
5491 u8 pri_hint;
5492 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL
5493 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL
5494 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL
5495 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX 0x3UL
5496 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 0x4UL
5497 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN
5498 u8 unused_5;
5499 __le32 unused_6;
5500 __le64 l2_filter_id_hint;
5501 };
5502
5503 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */
5504 struct hwrm_cfa_l2_filter_alloc_output {
5505 __le16 error_code;
5506 __le16 req_type;
5507 __le16 seq_id;
5508 __le16 resp_len;
5509 __le64 l2_filter_id;
5510 __le32 flow_id;
5511 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL
5512 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0
5513 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL
5514 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30)
5515 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30)
5516 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT
5517 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL
5518 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31)
5519 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31)
5520 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX
5521 u8 unused_0[3];
5522 u8 valid;
5523 };
5524
5525 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */
5526 struct hwrm_cfa_l2_filter_free_input {
5527 __le16 req_type;
5528 __le16 cmpl_ring;
5529 __le16 seq_id;
5530 __le16 target_id;
5531 __le64 resp_addr;
5532 __le64 l2_filter_id;
5533 };
5534
5535 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */
5536 struct hwrm_cfa_l2_filter_free_output {
5537 __le16 error_code;
5538 __le16 req_type;
5539 __le16 seq_id;
5540 __le16 resp_len;
5541 u8 unused_0[7];
5542 u8 valid;
5543 };
5544
5545 /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */
5546 struct hwrm_cfa_l2_filter_cfg_input {
5547 __le16 req_type;
5548 __le16 cmpl_ring;
5549 __le16 seq_id;
5550 __le16 target_id;
5551 __le64 resp_addr;
5552 __le32 flags;
5553 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL
5554 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX 0x0UL
5555 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 0x1UL
5556 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX
5557 #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL
5558 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_MASK 0xcUL
5559 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_SFT 2
5560 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 2)
5561 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 2)
5562 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 2)
5563 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE
5564 __le32 enables;
5565 #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL
5566 #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL
5567 __le64 l2_filter_id;
5568 __le32 dst_id;
5569 __le32 new_mirror_vnic_id;
5570 };
5571
5572 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */
5573 struct hwrm_cfa_l2_filter_cfg_output {
5574 __le16 error_code;
5575 __le16 req_type;
5576 __le16 seq_id;
5577 __le16 resp_len;
5578 u8 unused_0[7];
5579 u8 valid;
5580 };
5581
5582 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */
5583 struct hwrm_cfa_l2_set_rx_mask_input {
5584 __le16 req_type;
5585 __le16 cmpl_ring;
5586 __le16 seq_id;
5587 __le16 target_id;
5588 __le64 resp_addr;
5589 __le32 vnic_id;
5590 __le32 mask;
5591 #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL
5592 #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL
5593 #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL
5594 #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL
5595 #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL
5596 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY 0x40UL
5597 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN 0x80UL
5598 #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN 0x100UL
5599 __le64 mc_tbl_addr;
5600 __le32 num_mc_entries;
5601 u8 unused_0[4];
5602 __le64 vlan_tag_tbl_addr;
5603 __le32 num_vlan_tags;
5604 u8 unused_1[4];
5605 };
5606
5607 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */
5608 struct hwrm_cfa_l2_set_rx_mask_output {
5609 __le16 error_code;
5610 __le16 req_type;
5611 __le16 seq_id;
5612 __le16 resp_len;
5613 u8 unused_0[7];
5614 u8 valid;
5615 };
5616
5617 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */
5618 struct hwrm_cfa_l2_set_rx_mask_cmd_err {
5619 u8 code;
5620 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN 0x0UL
5621 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 0x1UL
5622 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR
5623 u8 unused_0[7];
5624 };
5625
5626 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */
5627 struct hwrm_cfa_tunnel_filter_alloc_input {
5628 __le16 req_type;
5629 __le16 cmpl_ring;
5630 __le16 seq_id;
5631 __le16 target_id;
5632 __le64 resp_addr;
5633 __le32 flags;
5634 #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL
5635 __le32 enables;
5636 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL
5637 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL
5638 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL
5639 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL
5640 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL
5641 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL
5642 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL
5643 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL
5644 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL
5645 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL
5646 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL
5647 __le64 l2_filter_id;
5648 u8 l2_addr[6];
5649 __le16 l2_ivlan;
5650 __le32 l3_addr[4];
5651 __le32 t_l3_addr[4];
5652 u8 l3_addr_type;
5653 u8 t_l3_addr_type;
5654 u8 tunnel_type;
5655 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
5656 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
5657 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
5658 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
5659 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
5660 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
5661 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
5662 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
5663 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
5664 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
5665 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
5666 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
5667 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
5668 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
5669 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
5670 u8 tunnel_flags;
5671 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR 0x1UL
5672 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 0x2UL
5673 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 0x4UL
5674 __le32 vni;
5675 __le32 dst_vnic_id;
5676 __le32 mirror_vnic_id;
5677 };
5678
5679 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */
5680 struct hwrm_cfa_tunnel_filter_alloc_output {
5681 __le16 error_code;
5682 __le16 req_type;
5683 __le16 seq_id;
5684 __le16 resp_len;
5685 __le64 tunnel_filter_id;
5686 __le32 flow_id;
5687 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL
5688 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0
5689 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL
5690 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30)
5691 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30)
5692 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT
5693 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL
5694 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31)
5695 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31)
5696 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX
5697 u8 unused_0[3];
5698 u8 valid;
5699 };
5700
5701 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */
5702 struct hwrm_cfa_tunnel_filter_free_input {
5703 __le16 req_type;
5704 __le16 cmpl_ring;
5705 __le16 seq_id;
5706 __le16 target_id;
5707 __le64 resp_addr;
5708 __le64 tunnel_filter_id;
5709 };
5710
5711 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */
5712 struct hwrm_cfa_tunnel_filter_free_output {
5713 __le16 error_code;
5714 __le16 req_type;
5715 __le16 seq_id;
5716 __le16 resp_len;
5717 u8 unused_0[7];
5718 u8 valid;
5719 };
5720
5721 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */
5722 struct hwrm_vxlan_ipv4_hdr {
5723 u8 ver_hlen;
5724 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK 0xfUL
5725 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0
5726 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK 0xf0UL
5727 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4
5728 u8 tos;
5729 __be16 ip_id;
5730 __be16 flags_frag_offset;
5731 u8 ttl;
5732 u8 protocol;
5733 __be32 src_ip_addr;
5734 __be32 dest_ip_addr;
5735 };
5736
5737 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */
5738 struct hwrm_vxlan_ipv6_hdr {
5739 __be32 ver_tc_flow_label;
5740 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT 0x1cUL
5741 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK 0xf0000000UL
5742 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT 0x14UL
5743 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK 0xff00000UL
5744 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT 0x0UL
5745 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 0xfffffUL
5746 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK
5747 __be16 payload_len;
5748 u8 next_hdr;
5749 u8 ttl;
5750 __be32 src_ip_addr[4];
5751 __be32 dest_ip_addr[4];
5752 };
5753
5754 /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */
5755 struct hwrm_cfa_encap_data_vxlan {
5756 u8 src_mac_addr[6];
5757 __le16 unused_0;
5758 u8 dst_mac_addr[6];
5759 u8 num_vlan_tags;
5760 u8 unused_1;
5761 __be16 ovlan_tpid;
5762 __be16 ovlan_tci;
5763 __be16 ivlan_tpid;
5764 __be16 ivlan_tci;
5765 __le32 l3[10];
5766 #define CFA_ENCAP_DATA_VXLAN_L3_VER_MASK 0xfUL
5767 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 0x4UL
5768 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 0x6UL
5769 #define CFA_ENCAP_DATA_VXLAN_L3_LAST CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6
5770 __be16 src_port;
5771 __be16 dst_port;
5772 __be32 vni;
5773 u8 hdr_rsvd0[3];
5774 u8 hdr_rsvd1;
5775 u8 hdr_flags;
5776 u8 unused[3];
5777 };
5778
5779 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */
5780 struct hwrm_cfa_encap_record_alloc_input {
5781 __le16 req_type;
5782 __le16 cmpl_ring;
5783 __le16 seq_id;
5784 __le16 target_id;
5785 __le64 resp_addr;
5786 __le32 flags;
5787 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL
5788 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_EXTERNAL 0x2UL
5789 u8 encap_type;
5790 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL
5791 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL
5792 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL
5793 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL
5794 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL
5795 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL
5796 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL
5797 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL
5798 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_V4 0x9UL
5799 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE_V1 0xaUL
5800 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE 0xbUL
5801 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 0xcUL
5802 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6
5803 u8 unused_0[3];
5804 __le32 encap_data[20];
5805 };
5806
5807 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */
5808 struct hwrm_cfa_encap_record_alloc_output {
5809 __le16 error_code;
5810 __le16 req_type;
5811 __le16 seq_id;
5812 __le16 resp_len;
5813 __le32 encap_record_id;
5814 u8 unused_0[3];
5815 u8 valid;
5816 };
5817
5818 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */
5819 struct hwrm_cfa_encap_record_free_input {
5820 __le16 req_type;
5821 __le16 cmpl_ring;
5822 __le16 seq_id;
5823 __le16 target_id;
5824 __le64 resp_addr;
5825 __le32 encap_record_id;
5826 u8 unused_0[4];
5827 };
5828
5829 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */
5830 struct hwrm_cfa_encap_record_free_output {
5831 __le16 error_code;
5832 __le16 req_type;
5833 __le16 seq_id;
5834 __le16 resp_len;
5835 u8 unused_0[7];
5836 u8 valid;
5837 };
5838
5839 /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */
5840 struct hwrm_cfa_ntuple_filter_alloc_input {
5841 __le16 req_type;
5842 __le16 cmpl_ring;
5843 __le16 seq_id;
5844 __le16 target_id;
5845 __le64 resp_addr;
5846 __le32 flags;
5847 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL
5848 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL
5849 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER 0x4UL
5850 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_FID 0x8UL
5851 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_ARP_REPLY 0x10UL
5852 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_RFS_RING_IDX 0x20UL
5853 __le32 enables;
5854 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL
5855 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL
5856 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL
5857 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL
5858 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL
5859 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL
5860 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL
5861 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL
5862 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL
5863 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL
5864 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL
5865 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL
5866 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL
5867 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL
5868 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL
5869 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL
5870 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL
5871 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL
5872 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL
5873 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_RFS_RING_TBL_IDX 0x80000UL
5874 __le64 l2_filter_id;
5875 u8 src_macaddr[6];
5876 __be16 ethertype;
5877 u8 ip_addr_type;
5878 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL
5879 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL
5880 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL
5881 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6
5882 u8 ip_protocol;
5883 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL
5884 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL
5885 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL
5886 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP
5887 __le16 dst_id;
5888 __le16 mirror_vnic_id;
5889 u8 tunnel_type;
5890 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
5891 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
5892 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
5893 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
5894 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
5895 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
5896 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
5897 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
5898 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
5899 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
5900 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
5901 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
5902 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
5903 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
5904 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
5905 u8 pri_hint;
5906 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL
5907 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE 0x1UL
5908 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW 0x2UL
5909 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST 0x3UL
5910 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 0x4UL
5911 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST
5912 __be32 src_ipaddr[4];
5913 __be32 src_ipaddr_mask[4];
5914 __be32 dst_ipaddr[4];
5915 __be32 dst_ipaddr_mask[4];
5916 __be16 src_port;
5917 __be16 src_port_mask;
5918 __be16 dst_port;
5919 __be16 dst_port_mask;
5920 __le64 ntuple_filter_id_hint;
5921 };
5922
5923 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */
5924 struct hwrm_cfa_ntuple_filter_alloc_output {
5925 __le16 error_code;
5926 __le16 req_type;
5927 __le16 seq_id;
5928 __le16 resp_len;
5929 __le64 ntuple_filter_id;
5930 __le32 flow_id;
5931 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL
5932 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0
5933 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL
5934 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30)
5935 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30)
5936 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT
5937 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL
5938 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31)
5939 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31)
5940 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX
5941 u8 unused_0[3];
5942 u8 valid;
5943 };
5944
5945 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */
5946 struct hwrm_cfa_ntuple_filter_alloc_cmd_err {
5947 u8 code;
5948 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL
5949 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 0x1UL
5950 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR
5951 u8 unused_0[7];
5952 };
5953
5954 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */
5955 struct hwrm_cfa_ntuple_filter_free_input {
5956 __le16 req_type;
5957 __le16 cmpl_ring;
5958 __le16 seq_id;
5959 __le16 target_id;
5960 __le64 resp_addr;
5961 __le64 ntuple_filter_id;
5962 };
5963
5964 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */
5965 struct hwrm_cfa_ntuple_filter_free_output {
5966 __le16 error_code;
5967 __le16 req_type;
5968 __le16 seq_id;
5969 __le16 resp_len;
5970 u8 unused_0[7];
5971 u8 valid;
5972 };
5973
5974 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */
5975 struct hwrm_cfa_ntuple_filter_cfg_input {
5976 __le16 req_type;
5977 __le16 cmpl_ring;
5978 __le16 seq_id;
5979 __le16 target_id;
5980 __le64 resp_addr;
5981 __le32 enables;
5982 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL
5983 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL
5984 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID 0x4UL
5985 __le32 flags;
5986 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_FID 0x1UL
5987 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_RFS_RING_IDX 0x2UL
5988 __le64 ntuple_filter_id;
5989 __le32 new_dst_id;
5990 __le32 new_mirror_vnic_id;
5991 __le16 new_meter_instance_id;
5992 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL
5993 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_LAST CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID
5994 u8 unused_1[6];
5995 };
5996
5997 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */
5998 struct hwrm_cfa_ntuple_filter_cfg_output {
5999 __le16 error_code;
6000 __le16 req_type;
6001 __le16 seq_id;
6002 __le16 resp_len;
6003 u8 unused_0[7];
6004 u8 valid;
6005 };
6006
6007 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
6008 struct hwrm_cfa_decap_filter_alloc_input {
6009 __le16 req_type;
6010 __le16 cmpl_ring;
6011 __le16 seq_id;
6012 __le16 target_id;
6013 __le64 resp_addr;
6014 __le32 flags;
6015 #define CFA_DECAP_FILTER_ALLOC_REQ_FLAGS_OVS_TUNNEL 0x1UL
6016 __le32 enables;
6017 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x1UL
6018 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_ID 0x2UL
6019 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x4UL
6020 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x8UL
6021 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_OVLAN_VID 0x10UL
6022 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IVLAN_VID 0x20UL
6023 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_OVLAN_VID 0x40UL
6024 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_IVLAN_VID 0x80UL
6025 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x100UL
6026 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x200UL
6027 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x400UL
6028 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x800UL
6029 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x1000UL
6030 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x2000UL
6031 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x4000UL
6032 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL
6033 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL
6034 __be32 tunnel_id;
6035 u8 tunnel_type;
6036 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
6037 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
6038 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
6039 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
6040 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
6041 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
6042 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
6043 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
6044 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
6045 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
6046 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
6047 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
6048 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
6049 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
6050 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
6051 u8 unused_0;
6052 __le16 unused_1;
6053 u8 src_macaddr[6];
6054 u8 unused_2[2];
6055 u8 dst_macaddr[6];
6056 __be16 ovlan_vid;
6057 __be16 ivlan_vid;
6058 __be16 t_ovlan_vid;
6059 __be16 t_ivlan_vid;
6060 __be16 ethertype;
6061 u8 ip_addr_type;
6062 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL
6063 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL
6064 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL
6065 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6
6066 u8 ip_protocol;
6067 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL
6068 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL
6069 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL
6070 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP
6071 __le16 unused_3;
6072 __le32 unused_4;
6073 __be32 src_ipaddr[4];
6074 __be32 dst_ipaddr[4];
6075 __be16 src_port;
6076 __be16 dst_port;
6077 __le16 dst_id;
6078 __le16 l2_ctxt_ref_id;
6079 };
6080
6081 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */
6082 struct hwrm_cfa_decap_filter_alloc_output {
6083 __le16 error_code;
6084 __le16 req_type;
6085 __le16 seq_id;
6086 __le16 resp_len;
6087 __le32 decap_filter_id;
6088 u8 unused_0[3];
6089 u8 valid;
6090 };
6091
6092 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */
6093 struct hwrm_cfa_decap_filter_free_input {
6094 __le16 req_type;
6095 __le16 cmpl_ring;
6096 __le16 seq_id;
6097 __le16 target_id;
6098 __le64 resp_addr;
6099 __le32 decap_filter_id;
6100 u8 unused_0[4];
6101 };
6102
6103 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */
6104 struct hwrm_cfa_decap_filter_free_output {
6105 __le16 error_code;
6106 __le16 req_type;
6107 __le16 seq_id;
6108 __le16 resp_len;
6109 u8 unused_0[7];
6110 u8 valid;
6111 };
6112
6113 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */
6114 struct hwrm_cfa_flow_alloc_input {
6115 __le16 req_type;
6116 __le16 cmpl_ring;
6117 __le16 seq_id;
6118 __le16 target_id;
6119 __le64 resp_addr;
6120 __le16 flags;
6121 #define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL 0x1UL
6122 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK 0x6UL
6123 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT 1
6124 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE (0x0UL << 1)
6125 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE (0x1UL << 1)
6126 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO (0x2UL << 1)
6127 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO
6128 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK 0x38UL
6129 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT 3
6130 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2 (0x0UL << 3)
6131 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4 (0x1UL << 3)
6132 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 (0x2UL << 3)
6133 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6
6134 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_TX 0x40UL
6135 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_RX 0x80UL
6136 #define CFA_FLOW_ALLOC_REQ_FLAGS_MATCH_VXLAN_IP_VNI 0x100UL
6137 #define CFA_FLOW_ALLOC_REQ_FLAGS_VHOST_ID_USE_VLAN 0x200UL
6138 __le16 src_fid;
6139 __le32 tunnel_handle;
6140 __le16 action_flags;
6141 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD 0x1UL
6142 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE 0x2UL
6143 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP 0x4UL
6144 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER 0x8UL
6145 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL 0x10UL
6146 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC 0x20UL
6147 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST 0x40UL
6148 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS 0x80UL
6149 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE 0x100UL
6150 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT 0x200UL
6151 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL_IP 0x400UL
6152 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FLOW_AGING_ENABLED 0x800UL
6153 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_PRI_HINT 0x1000UL
6154 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC 0x2000UL
6155 __le16 dst_fid;
6156 __be16 l2_rewrite_vlan_tpid;
6157 __be16 l2_rewrite_vlan_tci;
6158 __le16 act_meter_id;
6159 __le16 ref_flow_handle;
6160 __be16 ethertype;
6161 __be16 outer_vlan_tci;
6162 __be16 dmac[3];
6163 __be16 inner_vlan_tci;
6164 __be16 smac[3];
6165 u8 ip_dst_mask_len;
6166 u8 ip_src_mask_len;
6167 __be32 ip_dst[4];
6168 __be32 ip_src[4];
6169 __be16 l4_src_port;
6170 __be16 l4_src_port_mask;
6171 __be16 l4_dst_port;
6172 __be16 l4_dst_port_mask;
6173 __be32 nat_ip_address[4];
6174 __be16 l2_rewrite_dmac[3];
6175 __be16 nat_port;
6176 __be16 l2_rewrite_smac[3];
6177 u8 ip_proto;
6178 u8 tunnel_type;
6179 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
6180 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
6181 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
6182 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
6183 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
6184 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
6185 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
6186 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
6187 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
6188 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
6189 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
6190 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
6191 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
6192 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
6193 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
6194 };
6195
6196 /* hwrm_cfa_flow_alloc_output (size:256b/32B) */
6197 struct hwrm_cfa_flow_alloc_output {
6198 __le16 error_code;
6199 __le16 req_type;
6200 __le16 seq_id;
6201 __le16 resp_len;
6202 __le16 flow_handle;
6203 u8 unused_0[2];
6204 __le32 flow_id;
6205 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL
6206 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_SFT 0
6207 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL
6208 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30)
6209 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30)
6210 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT
6211 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL
6212 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31)
6213 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31)
6214 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX
6215 __le64 ext_flow_handle;
6216 __le32 flow_counter_id;
6217 u8 unused_1[3];
6218 u8 valid;
6219 };
6220
6221 /* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */
6222 struct hwrm_cfa_flow_alloc_cmd_err {
6223 u8 code;
6224 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL
6225 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM 0x1UL
6226 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD 0x2UL
6227 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER 0x3UL
6228 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM 0x4UL
6229 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION 0x5UL
6230 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS 0x6UL
6231 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB 0x7UL
6232 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB
6233 u8 unused_0[7];
6234 };
6235
6236 /* hwrm_cfa_flow_free_input (size:256b/32B) */
6237 struct hwrm_cfa_flow_free_input {
6238 __le16 req_type;
6239 __le16 cmpl_ring;
6240 __le16 seq_id;
6241 __le16 target_id;
6242 __le64 resp_addr;
6243 __le16 flow_handle;
6244 __le16 unused_0;
6245 __le32 flow_counter_id;
6246 __le64 ext_flow_handle;
6247 };
6248
6249 /* hwrm_cfa_flow_free_output (size:256b/32B) */
6250 struct hwrm_cfa_flow_free_output {
6251 __le16 error_code;
6252 __le16 req_type;
6253 __le16 seq_id;
6254 __le16 resp_len;
6255 __le64 packet;
6256 __le64 byte;
6257 u8 unused_0[7];
6258 u8 valid;
6259 };
6260
6261 /* hwrm_cfa_flow_info_input (size:256b/32B) */
6262 struct hwrm_cfa_flow_info_input {
6263 __le16 req_type;
6264 __le16 cmpl_ring;
6265 __le16 seq_id;
6266 __le16 target_id;
6267 __le64 resp_addr;
6268 __le16 flow_handle;
6269 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_MASK 0xfffUL
6270 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_SFT 0
6271 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT 0x1000UL
6272 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT 0x2000UL
6273 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT 0x4000UL
6274 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_DIR_RX 0x8000UL
6275 u8 unused_0[6];
6276 __le64 ext_flow_handle;
6277 };
6278
6279 /* hwrm_cfa_flow_info_output (size:5632b/704B) */
6280 struct hwrm_cfa_flow_info_output {
6281 __le16 error_code;
6282 __le16 req_type;
6283 __le16 seq_id;
6284 __le16 resp_len;
6285 u8 flags;
6286 #define CFA_FLOW_INFO_RESP_FLAGS_PATH_TX 0x1UL
6287 #define CFA_FLOW_INFO_RESP_FLAGS_PATH_RX 0x2UL
6288 u8 profile;
6289 __le16 src_fid;
6290 __le16 dst_fid;
6291 __le16 l2_ctxt_id;
6292 __le64 em_info;
6293 __le64 tcam_info;
6294 __le64 vfp_tcam_info;
6295 __le16 ar_id;
6296 __le16 flow_handle;
6297 __le32 tunnel_handle;
6298 __le16 flow_timer;
6299 u8 unused_0[6];
6300 __le32 flow_key_data[130];
6301 __le32 flow_action_info[30];
6302 u8 unused_1[7];
6303 u8 valid;
6304 };
6305
6306 /* hwrm_cfa_flow_stats_input (size:640b/80B) */
6307 struct hwrm_cfa_flow_stats_input {
6308 __le16 req_type;
6309 __le16 cmpl_ring;
6310 __le16 seq_id;
6311 __le16 target_id;
6312 __le64 resp_addr;
6313 __le16 num_flows;
6314 __le16 flow_handle_0;
6315 __le16 flow_handle_1;
6316 __le16 flow_handle_2;
6317 __le16 flow_handle_3;
6318 __le16 flow_handle_4;
6319 __le16 flow_handle_5;
6320 __le16 flow_handle_6;
6321 __le16 flow_handle_7;
6322 __le16 flow_handle_8;
6323 __le16 flow_handle_9;
6324 u8 unused_0[2];
6325 __le32 flow_id_0;
6326 __le32 flow_id_1;
6327 __le32 flow_id_2;
6328 __le32 flow_id_3;
6329 __le32 flow_id_4;
6330 __le32 flow_id_5;
6331 __le32 flow_id_6;
6332 __le32 flow_id_7;
6333 __le32 flow_id_8;
6334 __le32 flow_id_9;
6335 };
6336
6337 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */
6338 struct hwrm_cfa_flow_stats_output {
6339 __le16 error_code;
6340 __le16 req_type;
6341 __le16 seq_id;
6342 __le16 resp_len;
6343 __le64 packet_0;
6344 __le64 packet_1;
6345 __le64 packet_2;
6346 __le64 packet_3;
6347 __le64 packet_4;
6348 __le64 packet_5;
6349 __le64 packet_6;
6350 __le64 packet_7;
6351 __le64 packet_8;
6352 __le64 packet_9;
6353 __le64 byte_0;
6354 __le64 byte_1;
6355 __le64 byte_2;
6356 __le64 byte_3;
6357 __le64 byte_4;
6358 __le64 byte_5;
6359 __le64 byte_6;
6360 __le64 byte_7;
6361 __le64 byte_8;
6362 __le64 byte_9;
6363 u8 unused_0[7];
6364 u8 valid;
6365 };
6366
6367 /* hwrm_cfa_vfr_alloc_input (size:448b/56B) */
6368 struct hwrm_cfa_vfr_alloc_input {
6369 __le16 req_type;
6370 __le16 cmpl_ring;
6371 __le16 seq_id;
6372 __le16 target_id;
6373 __le64 resp_addr;
6374 __le16 vf_id;
6375 __le16 reserved;
6376 u8 unused_0[4];
6377 char vfr_name[32];
6378 };
6379
6380 /* hwrm_cfa_vfr_alloc_output (size:128b/16B) */
6381 struct hwrm_cfa_vfr_alloc_output {
6382 __le16 error_code;
6383 __le16 req_type;
6384 __le16 seq_id;
6385 __le16 resp_len;
6386 __le16 rx_cfa_code;
6387 __le16 tx_cfa_action;
6388 u8 unused_0[3];
6389 u8 valid;
6390 };
6391
6392 /* hwrm_cfa_vfr_free_input (size:384b/48B) */
6393 struct hwrm_cfa_vfr_free_input {
6394 __le16 req_type;
6395 __le16 cmpl_ring;
6396 __le16 seq_id;
6397 __le16 target_id;
6398 __le64 resp_addr;
6399 char vfr_name[32];
6400 };
6401
6402 /* hwrm_cfa_vfr_free_output (size:128b/16B) */
6403 struct hwrm_cfa_vfr_free_output {
6404 __le16 error_code;
6405 __le16 req_type;
6406 __le16 seq_id;
6407 __le16 resp_len;
6408 u8 unused_0[7];
6409 u8 valid;
6410 };
6411
6412 /* hwrm_cfa_eem_qcaps_input (size:192b/24B) */
6413 struct hwrm_cfa_eem_qcaps_input {
6414 __le16 req_type;
6415 __le16 cmpl_ring;
6416 __le16 seq_id;
6417 __le16 target_id;
6418 __le64 resp_addr;
6419 __le32 flags;
6420 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_TX 0x1UL
6421 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_RX 0x2UL
6422 #define CFA_EEM_QCAPS_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL
6423 __le32 unused_0;
6424 };
6425
6426 /* hwrm_cfa_eem_qcaps_output (size:320b/40B) */
6427 struct hwrm_cfa_eem_qcaps_output {
6428 __le16 error_code;
6429 __le16 req_type;
6430 __le16 seq_id;
6431 __le16 resp_len;
6432 __le32 flags;
6433 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_TX 0x1UL
6434 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_RX 0x2UL
6435 #define CFA_EEM_QCAPS_RESP_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x4UL
6436 #define CFA_EEM_QCAPS_RESP_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x8UL
6437 __le32 unused_0;
6438 __le32 supported;
6439 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY0_TABLE 0x1UL
6440 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY1_TABLE 0x2UL
6441 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_RECORD_TABLE 0x4UL
6442 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE 0x8UL
6443 #define CFA_EEM_QCAPS_RESP_SUPPORTED_FID_TABLE 0x10UL
6444 __le32 max_entries_supported;
6445 __le16 key_entry_size;
6446 __le16 record_entry_size;
6447 __le16 efc_entry_size;
6448 __le16 fid_entry_size;
6449 u8 unused_1[7];
6450 u8 valid;
6451 };
6452
6453 /* hwrm_cfa_eem_cfg_input (size:384b/48B) */
6454 struct hwrm_cfa_eem_cfg_input {
6455 __le16 req_type;
6456 __le16 cmpl_ring;
6457 __le16 seq_id;
6458 __le16 target_id;
6459 __le64 resp_addr;
6460 __le32 flags;
6461 #define CFA_EEM_CFG_REQ_FLAGS_PATH_TX 0x1UL
6462 #define CFA_EEM_CFG_REQ_FLAGS_PATH_RX 0x2UL
6463 #define CFA_EEM_CFG_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL
6464 #define CFA_EEM_CFG_REQ_FLAGS_SECONDARY_PF 0x8UL
6465 __le16 group_id;
6466 __le16 unused_0;
6467 __le32 num_entries;
6468 __le32 unused_1;
6469 __le16 key0_ctx_id;
6470 __le16 key1_ctx_id;
6471 __le16 record_ctx_id;
6472 __le16 efc_ctx_id;
6473 __le16 fid_ctx_id;
6474 __le16 unused_2;
6475 __le32 unused_3;
6476 };
6477
6478 /* hwrm_cfa_eem_cfg_output (size:128b/16B) */
6479 struct hwrm_cfa_eem_cfg_output {
6480 __le16 error_code;
6481 __le16 req_type;
6482 __le16 seq_id;
6483 __le16 resp_len;
6484 u8 unused_0[7];
6485 u8 valid;
6486 };
6487
6488 /* hwrm_cfa_eem_qcfg_input (size:192b/24B) */
6489 struct hwrm_cfa_eem_qcfg_input {
6490 __le16 req_type;
6491 __le16 cmpl_ring;
6492 __le16 seq_id;
6493 __le16 target_id;
6494 __le64 resp_addr;
6495 __le32 flags;
6496 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_TX 0x1UL
6497 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_RX 0x2UL
6498 __le32 unused_0;
6499 };
6500
6501 /* hwrm_cfa_eem_qcfg_output (size:256b/32B) */
6502 struct hwrm_cfa_eem_qcfg_output {
6503 __le16 error_code;
6504 __le16 req_type;
6505 __le16 seq_id;
6506 __le16 resp_len;
6507 __le32 flags;
6508 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_TX 0x1UL
6509 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_RX 0x2UL
6510 #define CFA_EEM_QCFG_RESP_FLAGS_PREFERRED_OFFLOAD 0x4UL
6511 __le32 num_entries;
6512 __le16 key0_ctx_id;
6513 __le16 key1_ctx_id;
6514 __le16 record_ctx_id;
6515 __le16 efc_ctx_id;
6516 __le16 fid_ctx_id;
6517 u8 unused_2[5];
6518 u8 valid;
6519 };
6520
6521 /* hwrm_cfa_eem_op_input (size:192b/24B) */
6522 struct hwrm_cfa_eem_op_input {
6523 __le16 req_type;
6524 __le16 cmpl_ring;
6525 __le16 seq_id;
6526 __le16 target_id;
6527 __le64 resp_addr;
6528 __le32 flags;
6529 #define CFA_EEM_OP_REQ_FLAGS_PATH_TX 0x1UL
6530 #define CFA_EEM_OP_REQ_FLAGS_PATH_RX 0x2UL
6531 __le16 unused_0;
6532 __le16 op;
6533 #define CFA_EEM_OP_REQ_OP_RESERVED 0x0UL
6534 #define CFA_EEM_OP_REQ_OP_EEM_DISABLE 0x1UL
6535 #define CFA_EEM_OP_REQ_OP_EEM_ENABLE 0x2UL
6536 #define CFA_EEM_OP_REQ_OP_EEM_CLEANUP 0x3UL
6537 #define CFA_EEM_OP_REQ_OP_LAST CFA_EEM_OP_REQ_OP_EEM_CLEANUP
6538 };
6539
6540 /* hwrm_cfa_eem_op_output (size:128b/16B) */
6541 struct hwrm_cfa_eem_op_output {
6542 __le16 error_code;
6543 __le16 req_type;
6544 __le16 seq_id;
6545 __le16 resp_len;
6546 u8 unused_0[7];
6547 u8 valid;
6548 };
6549
6550 /* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */
6551 struct hwrm_cfa_adv_flow_mgnt_qcaps_input {
6552 __le16 req_type;
6553 __le16 cmpl_ring;
6554 __le16 seq_id;
6555 __le16 target_id;
6556 __le64 resp_addr;
6557 __le32 unused_0[4];
6558 };
6559
6560 /* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */
6561 struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
6562 __le16 error_code;
6563 __le16 req_type;
6564 __le16 seq_id;
6565 __le16 resp_len;
6566 __le32 flags;
6567 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_16BIT_SUPPORTED 0x1UL
6568 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_64BIT_SUPPORTED 0x2UL
6569 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_BATCH_DELETE_SUPPORTED 0x4UL
6570 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_RESET_ALL_SUPPORTED 0x8UL
6571 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED 0x10UL
6572 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TX_EEM_FLOW_SUPPORTED 0x20UL
6573 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RX_EEM_FLOW_SUPPORTED 0x40UL
6574 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED 0x80UL
6575 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_SUPPORTED 0x100UL
6576 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_UNTAGGED_VLAN_SUPPORTED 0x200UL
6577 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_XDP_SUPPORTED 0x400UL
6578 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED 0x800UL
6579 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED 0x1000UL
6580 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED 0x2000UL
6581 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED 0x4000UL
6582 u8 unused_0[3];
6583 u8 valid;
6584 };
6585
6586 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */
6587 struct hwrm_tunnel_dst_port_query_input {
6588 __le16 req_type;
6589 __le16 cmpl_ring;
6590 __le16 seq_id;
6591 __le16 target_id;
6592 __le64 resp_addr;
6593 u8 tunnel_type;
6594 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL
6595 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL
6596 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
6597 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
6598 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
6599 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
6600 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6
6601 u8 unused_0[7];
6602 };
6603
6604 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */
6605 struct hwrm_tunnel_dst_port_query_output {
6606 __le16 error_code;
6607 __le16 req_type;
6608 __le16 seq_id;
6609 __le16 resp_len;
6610 __le16 tunnel_dst_port_id;
6611 __be16 tunnel_dst_port_val;
6612 u8 unused_0[3];
6613 u8 valid;
6614 };
6615
6616 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */
6617 struct hwrm_tunnel_dst_port_alloc_input {
6618 __le16 req_type;
6619 __le16 cmpl_ring;
6620 __le16 seq_id;
6621 __le16 target_id;
6622 __le64 resp_addr;
6623 u8 tunnel_type;
6624 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
6625 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
6626 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
6627 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
6628 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
6629 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
6630 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6
6631 u8 unused_0;
6632 __be16 tunnel_dst_port_val;
6633 u8 unused_1[4];
6634 };
6635
6636 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */
6637 struct hwrm_tunnel_dst_port_alloc_output {
6638 __le16 error_code;
6639 __le16 req_type;
6640 __le16 seq_id;
6641 __le16 resp_len;
6642 __le16 tunnel_dst_port_id;
6643 u8 unused_0[5];
6644 u8 valid;
6645 };
6646
6647 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */
6648 struct hwrm_tunnel_dst_port_free_input {
6649 __le16 req_type;
6650 __le16 cmpl_ring;
6651 __le16 seq_id;
6652 __le16 target_id;
6653 __le64 resp_addr;
6654 u8 tunnel_type;
6655 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL
6656 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL
6657 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
6658 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
6659 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
6660 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
6661 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6
6662 u8 unused_0;
6663 __le16 tunnel_dst_port_id;
6664 u8 unused_1[4];
6665 };
6666
6667 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */
6668 struct hwrm_tunnel_dst_port_free_output {
6669 __le16 error_code;
6670 __le16 req_type;
6671 __le16 seq_id;
6672 __le16 resp_len;
6673 u8 unused_1[7];
6674 u8 valid;
6675 };
6676
6677 /* ctx_hw_stats (size:1280b/160B) */
6678 struct ctx_hw_stats {
6679 __le64 rx_ucast_pkts;
6680 __le64 rx_mcast_pkts;
6681 __le64 rx_bcast_pkts;
6682 __le64 rx_discard_pkts;
6683 __le64 rx_drop_pkts;
6684 __le64 rx_ucast_bytes;
6685 __le64 rx_mcast_bytes;
6686 __le64 rx_bcast_bytes;
6687 __le64 tx_ucast_pkts;
6688 __le64 tx_mcast_pkts;
6689 __le64 tx_bcast_pkts;
6690 __le64 tx_discard_pkts;
6691 __le64 tx_drop_pkts;
6692 __le64 tx_ucast_bytes;
6693 __le64 tx_mcast_bytes;
6694 __le64 tx_bcast_bytes;
6695 __le64 tpa_pkts;
6696 __le64 tpa_bytes;
6697 __le64 tpa_events;
6698 __le64 tpa_aborts;
6699 };
6700
6701 /* ctx_hw_stats_ext (size:1344b/168B) */
6702 struct ctx_hw_stats_ext {
6703 __le64 rx_ucast_pkts;
6704 __le64 rx_mcast_pkts;
6705 __le64 rx_bcast_pkts;
6706 __le64 rx_discard_pkts;
6707 __le64 rx_drop_pkts;
6708 __le64 rx_ucast_bytes;
6709 __le64 rx_mcast_bytes;
6710 __le64 rx_bcast_bytes;
6711 __le64 tx_ucast_pkts;
6712 __le64 tx_mcast_pkts;
6713 __le64 tx_bcast_pkts;
6714 __le64 tx_discard_pkts;
6715 __le64 tx_drop_pkts;
6716 __le64 tx_ucast_bytes;
6717 __le64 tx_mcast_bytes;
6718 __le64 tx_bcast_bytes;
6719 __le64 rx_tpa_eligible_pkt;
6720 __le64 rx_tpa_eligible_bytes;
6721 __le64 rx_tpa_pkt;
6722 __le64 rx_tpa_bytes;
6723 __le64 rx_tpa_errors;
6724 };
6725
6726 /* hwrm_stat_ctx_alloc_input (size:256b/32B) */
6727 struct hwrm_stat_ctx_alloc_input {
6728 __le16 req_type;
6729 __le16 cmpl_ring;
6730 __le16 seq_id;
6731 __le16 target_id;
6732 __le64 resp_addr;
6733 __le64 stats_dma_addr;
6734 __le32 update_period_ms;
6735 u8 stat_ctx_flags;
6736 #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE 0x1UL
6737 u8 unused_0;
6738 __le16 stats_dma_length;
6739 };
6740
6741 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */
6742 struct hwrm_stat_ctx_alloc_output {
6743 __le16 error_code;
6744 __le16 req_type;
6745 __le16 seq_id;
6746 __le16 resp_len;
6747 __le32 stat_ctx_id;
6748 u8 unused_0[3];
6749 u8 valid;
6750 };
6751
6752 /* hwrm_stat_ctx_free_input (size:192b/24B) */
6753 struct hwrm_stat_ctx_free_input {
6754 __le16 req_type;
6755 __le16 cmpl_ring;
6756 __le16 seq_id;
6757 __le16 target_id;
6758 __le64 resp_addr;
6759 __le32 stat_ctx_id;
6760 u8 unused_0[4];
6761 };
6762
6763 /* hwrm_stat_ctx_free_output (size:128b/16B) */
6764 struct hwrm_stat_ctx_free_output {
6765 __le16 error_code;
6766 __le16 req_type;
6767 __le16 seq_id;
6768 __le16 resp_len;
6769 __le32 stat_ctx_id;
6770 u8 unused_0[3];
6771 u8 valid;
6772 };
6773
6774 /* hwrm_stat_ctx_query_input (size:192b/24B) */
6775 struct hwrm_stat_ctx_query_input {
6776 __le16 req_type;
6777 __le16 cmpl_ring;
6778 __le16 seq_id;
6779 __le16 target_id;
6780 __le64 resp_addr;
6781 __le32 stat_ctx_id;
6782 u8 unused_0[4];
6783 };
6784
6785 /* hwrm_stat_ctx_query_output (size:1408b/176B) */
6786 struct hwrm_stat_ctx_query_output {
6787 __le16 error_code;
6788 __le16 req_type;
6789 __le16 seq_id;
6790 __le16 resp_len;
6791 __le64 tx_ucast_pkts;
6792 __le64 tx_mcast_pkts;
6793 __le64 tx_bcast_pkts;
6794 __le64 tx_err_pkts;
6795 __le64 tx_drop_pkts;
6796 __le64 tx_ucast_bytes;
6797 __le64 tx_mcast_bytes;
6798 __le64 tx_bcast_bytes;
6799 __le64 rx_ucast_pkts;
6800 __le64 rx_mcast_pkts;
6801 __le64 rx_bcast_pkts;
6802 __le64 rx_err_pkts;
6803 __le64 rx_drop_pkts;
6804 __le64 rx_ucast_bytes;
6805 __le64 rx_mcast_bytes;
6806 __le64 rx_bcast_bytes;
6807 __le64 rx_agg_pkts;
6808 __le64 rx_agg_bytes;
6809 __le64 rx_agg_events;
6810 __le64 rx_agg_aborts;
6811 u8 unused_0[7];
6812 u8 valid;
6813 };
6814
6815 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */
6816 struct hwrm_stat_ctx_clr_stats_input {
6817 __le16 req_type;
6818 __le16 cmpl_ring;
6819 __le16 seq_id;
6820 __le16 target_id;
6821 __le64 resp_addr;
6822 __le32 stat_ctx_id;
6823 u8 unused_0[4];
6824 };
6825
6826 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */
6827 struct hwrm_stat_ctx_clr_stats_output {
6828 __le16 error_code;
6829 __le16 req_type;
6830 __le16 seq_id;
6831 __le16 resp_len;
6832 u8 unused_0[7];
6833 u8 valid;
6834 };
6835
6836 /* hwrm_pcie_qstats_input (size:256b/32B) */
6837 struct hwrm_pcie_qstats_input {
6838 __le16 req_type;
6839 __le16 cmpl_ring;
6840 __le16 seq_id;
6841 __le16 target_id;
6842 __le64 resp_addr;
6843 __le16 pcie_stat_size;
6844 u8 unused_0[6];
6845 __le64 pcie_stat_host_addr;
6846 };
6847
6848 /* hwrm_pcie_qstats_output (size:128b/16B) */
6849 struct hwrm_pcie_qstats_output {
6850 __le16 error_code;
6851 __le16 req_type;
6852 __le16 seq_id;
6853 __le16 resp_len;
6854 __le16 pcie_stat_size;
6855 u8 unused_0[5];
6856 u8 valid;
6857 };
6858
6859 /* pcie_ctx_hw_stats (size:768b/96B) */
6860 struct pcie_ctx_hw_stats {
6861 __le64 pcie_pl_signal_integrity;
6862 __le64 pcie_dl_signal_integrity;
6863 __le64 pcie_tl_signal_integrity;
6864 __le64 pcie_link_integrity;
6865 __le64 pcie_tx_traffic_rate;
6866 __le64 pcie_rx_traffic_rate;
6867 __le64 pcie_tx_dllp_statistics;
6868 __le64 pcie_rx_dllp_statistics;
6869 __le64 pcie_equalization_time;
6870 __le32 pcie_ltssm_histogram[4];
6871 __le64 pcie_recovery_histogram;
6872 };
6873
6874 /* hwrm_fw_reset_input (size:192b/24B) */
6875 struct hwrm_fw_reset_input {
6876 __le16 req_type;
6877 __le16 cmpl_ring;
6878 __le16 seq_id;
6879 __le16 target_id;
6880 __le64 resp_addr;
6881 u8 embedded_proc_type;
6882 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL
6883 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL
6884 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL
6885 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL
6886 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL
6887 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL
6888 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL
6889 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT 0x7UL
6890 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 0x8UL
6891 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_LAST FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION
6892 u8 selfrst_status;
6893 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL
6894 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL
6895 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL
6896 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL
6897 #define FW_RESET_REQ_SELFRST_STATUS_LAST FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE
6898 u8 host_idx;
6899 u8 flags;
6900 #define FW_RESET_REQ_FLAGS_RESET_GRACEFUL 0x1UL
6901 u8 unused_0[4];
6902 };
6903
6904 /* hwrm_fw_reset_output (size:128b/16B) */
6905 struct hwrm_fw_reset_output {
6906 __le16 error_code;
6907 __le16 req_type;
6908 __le16 seq_id;
6909 __le16 resp_len;
6910 u8 selfrst_status;
6911 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL
6912 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL
6913 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL
6914 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL
6915 #define FW_RESET_RESP_SELFRST_STATUS_LAST FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE
6916 u8 unused_0[6];
6917 u8 valid;
6918 };
6919
6920 /* hwrm_fw_qstatus_input (size:192b/24B) */
6921 struct hwrm_fw_qstatus_input {
6922 __le16 req_type;
6923 __le16 cmpl_ring;
6924 __le16 seq_id;
6925 __le16 target_id;
6926 __le64 resp_addr;
6927 u8 embedded_proc_type;
6928 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL
6929 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL
6930 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL
6931 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL
6932 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL
6933 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL
6934 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL
6935 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_LAST FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP
6936 u8 unused_0[7];
6937 };
6938
6939 /* hwrm_fw_qstatus_output (size:128b/16B) */
6940 struct hwrm_fw_qstatus_output {
6941 __le16 error_code;
6942 __le16 req_type;
6943 __le16 seq_id;
6944 __le16 resp_len;
6945 u8 selfrst_status;
6946 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL
6947 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL
6948 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL
6949 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 0x3UL
6950 #define FW_QSTATUS_RESP_SELFRST_STATUS_LAST FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER
6951 u8 unused_0[6];
6952 u8 valid;
6953 };
6954
6955 /* hwrm_fw_set_time_input (size:256b/32B) */
6956 struct hwrm_fw_set_time_input {
6957 __le16 req_type;
6958 __le16 cmpl_ring;
6959 __le16 seq_id;
6960 __le16 target_id;
6961 __le64 resp_addr;
6962 __le16 year;
6963 #define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL
6964 #define FW_SET_TIME_REQ_YEAR_LAST FW_SET_TIME_REQ_YEAR_UNKNOWN
6965 u8 month;
6966 u8 day;
6967 u8 hour;
6968 u8 minute;
6969 u8 second;
6970 u8 unused_0;
6971 __le16 millisecond;
6972 __le16 zone;
6973 #define FW_SET_TIME_REQ_ZONE_UTC 0
6974 #define FW_SET_TIME_REQ_ZONE_UNKNOWN 65535
6975 #define FW_SET_TIME_REQ_ZONE_LAST FW_SET_TIME_REQ_ZONE_UNKNOWN
6976 u8 unused_1[4];
6977 };
6978
6979 /* hwrm_fw_set_time_output (size:128b/16B) */
6980 struct hwrm_fw_set_time_output {
6981 __le16 error_code;
6982 __le16 req_type;
6983 __le16 seq_id;
6984 __le16 resp_len;
6985 u8 unused_0[7];
6986 u8 valid;
6987 };
6988
6989 /* hwrm_struct_hdr (size:128b/16B) */
6990 struct hwrm_struct_hdr {
6991 __le16 struct_id;
6992 #define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL
6993 #define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL
6994 #define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL
6995 #define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL
6996 #define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL
6997 #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL
6998 #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL
6999 #define STRUCT_HDR_STRUCT_ID_POWER_BKUP 0x427UL
7000 #define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL
7001 #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL
7002 #define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL
7003 #define STRUCT_HDR_STRUCT_ID_LAST STRUCT_HDR_STRUCT_ID_RSS_V2
7004 __le16 len;
7005 u8 version;
7006 u8 count;
7007 __le16 subtype;
7008 __le16 next_offset;
7009 #define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL
7010 u8 unused_0[6];
7011 };
7012
7013 /* hwrm_struct_data_dcbx_app (size:64b/8B) */
7014 struct hwrm_struct_data_dcbx_app {
7015 __be16 protocol_id;
7016 u8 protocol_selector;
7017 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE 0x1UL
7018 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT 0x2UL
7019 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT 0x3UL
7020 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL
7021 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_LAST STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT
7022 u8 priority;
7023 u8 valid;
7024 u8 unused_0[3];
7025 };
7026
7027 /* hwrm_fw_set_structured_data_input (size:256b/32B) */
7028 struct hwrm_fw_set_structured_data_input {
7029 __le16 req_type;
7030 __le16 cmpl_ring;
7031 __le16 seq_id;
7032 __le16 target_id;
7033 __le64 resp_addr;
7034 __le64 src_data_addr;
7035 __le16 data_len;
7036 u8 hdr_cnt;
7037 u8 unused_0[5];
7038 };
7039
7040 /* hwrm_fw_set_structured_data_output (size:128b/16B) */
7041 struct hwrm_fw_set_structured_data_output {
7042 __le16 error_code;
7043 __le16 req_type;
7044 __le16 seq_id;
7045 __le16 resp_len;
7046 u8 unused_0[7];
7047 u8 valid;
7048 };
7049
7050 /* hwrm_fw_set_structured_data_cmd_err (size:64b/8B) */
7051 struct hwrm_fw_set_structured_data_cmd_err {
7052 u8 code;
7053 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL
7054 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT 0x1UL
7055 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT 0x2UL
7056 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL
7057 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID
7058 u8 unused_0[7];
7059 };
7060
7061 /* hwrm_fw_get_structured_data_input (size:256b/32B) */
7062 struct hwrm_fw_get_structured_data_input {
7063 __le16 req_type;
7064 __le16 cmpl_ring;
7065 __le16 seq_id;
7066 __le16 target_id;
7067 __le64 resp_addr;
7068 __le64 dest_data_addr;
7069 __le16 data_len;
7070 __le16 structure_id;
7071 __le16 subtype;
7072 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_UNUSED 0x0UL
7073 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL 0xffffUL
7074 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN 0x100UL
7075 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER 0x101UL
7076 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL
7077 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN 0x200UL
7078 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER 0x201UL
7079 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL 0x202UL
7080 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 0x300UL
7081 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_LAST FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL
7082 u8 count;
7083 u8 unused_0;
7084 };
7085
7086 /* hwrm_fw_get_structured_data_output (size:128b/16B) */
7087 struct hwrm_fw_get_structured_data_output {
7088 __le16 error_code;
7089 __le16 req_type;
7090 __le16 seq_id;
7091 __le16 resp_len;
7092 u8 hdr_cnt;
7093 u8 unused_0[6];
7094 u8 valid;
7095 };
7096
7097 /* hwrm_fw_get_structured_data_cmd_err (size:64b/8B) */
7098 struct hwrm_fw_get_structured_data_cmd_err {
7099 u8 code;
7100 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL
7101 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL
7102 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID
7103 u8 unused_0[7];
7104 };
7105
7106 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */
7107 struct hwrm_exec_fwd_resp_input {
7108 __le16 req_type;
7109 __le16 cmpl_ring;
7110 __le16 seq_id;
7111 __le16 target_id;
7112 __le64 resp_addr;
7113 __le32 encap_request[26];
7114 __le16 encap_resp_target_id;
7115 u8 unused_0[6];
7116 };
7117
7118 /* hwrm_exec_fwd_resp_output (size:128b/16B) */
7119 struct hwrm_exec_fwd_resp_output {
7120 __le16 error_code;
7121 __le16 req_type;
7122 __le16 seq_id;
7123 __le16 resp_len;
7124 u8 unused_0[7];
7125 u8 valid;
7126 };
7127
7128 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */
7129 struct hwrm_reject_fwd_resp_input {
7130 __le16 req_type;
7131 __le16 cmpl_ring;
7132 __le16 seq_id;
7133 __le16 target_id;
7134 __le64 resp_addr;
7135 __le32 encap_request[26];
7136 __le16 encap_resp_target_id;
7137 u8 unused_0[6];
7138 };
7139
7140 /* hwrm_reject_fwd_resp_output (size:128b/16B) */
7141 struct hwrm_reject_fwd_resp_output {
7142 __le16 error_code;
7143 __le16 req_type;
7144 __le16 seq_id;
7145 __le16 resp_len;
7146 u8 unused_0[7];
7147 u8 valid;
7148 };
7149
7150 /* hwrm_fwd_resp_input (size:1024b/128B) */
7151 struct hwrm_fwd_resp_input {
7152 __le16 req_type;
7153 __le16 cmpl_ring;
7154 __le16 seq_id;
7155 __le16 target_id;
7156 __le64 resp_addr;
7157 __le16 encap_resp_target_id;
7158 __le16 encap_resp_cmpl_ring;
7159 __le16 encap_resp_len;
7160 u8 unused_0;
7161 u8 unused_1;
7162 __le64 encap_resp_addr;
7163 __le32 encap_resp[24];
7164 };
7165
7166 /* hwrm_fwd_resp_output (size:128b/16B) */
7167 struct hwrm_fwd_resp_output {
7168 __le16 error_code;
7169 __le16 req_type;
7170 __le16 seq_id;
7171 __le16 resp_len;
7172 u8 unused_0[7];
7173 u8 valid;
7174 };
7175
7176 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */
7177 struct hwrm_fwd_async_event_cmpl_input {
7178 __le16 req_type;
7179 __le16 cmpl_ring;
7180 __le16 seq_id;
7181 __le16 target_id;
7182 __le64 resp_addr;
7183 __le16 encap_async_event_target_id;
7184 u8 unused_0[6];
7185 __le32 encap_async_event_cmpl[4];
7186 };
7187
7188 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */
7189 struct hwrm_fwd_async_event_cmpl_output {
7190 __le16 error_code;
7191 __le16 req_type;
7192 __le16 seq_id;
7193 __le16 resp_len;
7194 u8 unused_0[7];
7195 u8 valid;
7196 };
7197
7198 /* hwrm_temp_monitor_query_input (size:128b/16B) */
7199 struct hwrm_temp_monitor_query_input {
7200 __le16 req_type;
7201 __le16 cmpl_ring;
7202 __le16 seq_id;
7203 __le16 target_id;
7204 __le64 resp_addr;
7205 };
7206
7207 /* hwrm_temp_monitor_query_output (size:128b/16B) */
7208 struct hwrm_temp_monitor_query_output {
7209 __le16 error_code;
7210 __le16 req_type;
7211 __le16 seq_id;
7212 __le16 resp_len;
7213 u8 temp;
7214 u8 phy_temp;
7215 u8 om_temp;
7216 u8 flags;
7217 #define TEMP_MONITOR_QUERY_RESP_FLAGS_TEMP_NOT_AVAILABLE 0x1UL
7218 #define TEMP_MONITOR_QUERY_RESP_FLAGS_PHY_TEMP_NOT_AVAILABLE 0x2UL
7219 #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_NOT_PRESENT 0x4UL
7220 #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_TEMP_NOT_AVAILABLE 0x8UL
7221 u8 unused_0[3];
7222 u8 valid;
7223 };
7224
7225 /* hwrm_wol_filter_alloc_input (size:512b/64B) */
7226 struct hwrm_wol_filter_alloc_input {
7227 __le16 req_type;
7228 __le16 cmpl_ring;
7229 __le16 seq_id;
7230 __le16 target_id;
7231 __le64 resp_addr;
7232 __le32 flags;
7233 __le32 enables;
7234 #define WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS 0x1UL
7235 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_OFFSET 0x2UL
7236 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_SIZE 0x4UL
7237 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_ADDR 0x8UL
7238 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_ADDR 0x10UL
7239 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_SIZE 0x20UL
7240 __le16 port_id;
7241 u8 wol_type;
7242 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT 0x0UL
7243 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_BMP 0x1UL
7244 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 0xffUL
7245 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_LAST WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID
7246 u8 unused_0[5];
7247 u8 mac_address[6];
7248 __le16 pattern_offset;
7249 __le16 pattern_buf_size;
7250 __le16 pattern_mask_size;
7251 u8 unused_1[4];
7252 __le64 pattern_buf_addr;
7253 __le64 pattern_mask_addr;
7254 };
7255
7256 /* hwrm_wol_filter_alloc_output (size:128b/16B) */
7257 struct hwrm_wol_filter_alloc_output {
7258 __le16 error_code;
7259 __le16 req_type;
7260 __le16 seq_id;
7261 __le16 resp_len;
7262 u8 wol_filter_id;
7263 u8 unused_0[6];
7264 u8 valid;
7265 };
7266
7267 /* hwrm_wol_filter_free_input (size:256b/32B) */
7268 struct hwrm_wol_filter_free_input {
7269 __le16 req_type;
7270 __le16 cmpl_ring;
7271 __le16 seq_id;
7272 __le16 target_id;
7273 __le64 resp_addr;
7274 __le32 flags;
7275 #define WOL_FILTER_FREE_REQ_FLAGS_FREE_ALL_WOL_FILTERS 0x1UL
7276 __le32 enables;
7277 #define WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID 0x1UL
7278 __le16 port_id;
7279 u8 wol_filter_id;
7280 u8 unused_0[5];
7281 };
7282
7283 /* hwrm_wol_filter_free_output (size:128b/16B) */
7284 struct hwrm_wol_filter_free_output {
7285 __le16 error_code;
7286 __le16 req_type;
7287 __le16 seq_id;
7288 __le16 resp_len;
7289 u8 unused_0[7];
7290 u8 valid;
7291 };
7292
7293 /* hwrm_wol_filter_qcfg_input (size:448b/56B) */
7294 struct hwrm_wol_filter_qcfg_input {
7295 __le16 req_type;
7296 __le16 cmpl_ring;
7297 __le16 seq_id;
7298 __le16 target_id;
7299 __le64 resp_addr;
7300 __le16 port_id;
7301 __le16 handle;
7302 u8 unused_0[4];
7303 __le64 pattern_buf_addr;
7304 __le16 pattern_buf_size;
7305 u8 unused_1[6];
7306 __le64 pattern_mask_addr;
7307 __le16 pattern_mask_size;
7308 u8 unused_2[6];
7309 };
7310
7311 /* hwrm_wol_filter_qcfg_output (size:256b/32B) */
7312 struct hwrm_wol_filter_qcfg_output {
7313 __le16 error_code;
7314 __le16 req_type;
7315 __le16 seq_id;
7316 __le16 resp_len;
7317 __le16 next_handle;
7318 u8 wol_filter_id;
7319 u8 wol_type;
7320 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_MAGICPKT 0x0UL
7321 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_BMP 0x1UL
7322 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 0xffUL
7323 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_LAST WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID
7324 __le32 unused_0;
7325 u8 mac_address[6];
7326 __le16 pattern_offset;
7327 __le16 pattern_size;
7328 __le16 pattern_mask_size;
7329 u8 unused_1[3];
7330 u8 valid;
7331 };
7332
7333 /* hwrm_wol_reason_qcfg_input (size:320b/40B) */
7334 struct hwrm_wol_reason_qcfg_input {
7335 __le16 req_type;
7336 __le16 cmpl_ring;
7337 __le16 seq_id;
7338 __le16 target_id;
7339 __le64 resp_addr;
7340 __le16 port_id;
7341 u8 unused_0[6];
7342 __le64 wol_pkt_buf_addr;
7343 __le16 wol_pkt_buf_size;
7344 u8 unused_1[6];
7345 };
7346
7347 /* hwrm_wol_reason_qcfg_output (size:128b/16B) */
7348 struct hwrm_wol_reason_qcfg_output {
7349 __le16 error_code;
7350 __le16 req_type;
7351 __le16 seq_id;
7352 __le16 resp_len;
7353 u8 wol_filter_id;
7354 u8 wol_reason;
7355 #define WOL_REASON_QCFG_RESP_WOL_REASON_MAGICPKT 0x0UL
7356 #define WOL_REASON_QCFG_RESP_WOL_REASON_BMP 0x1UL
7357 #define WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 0xffUL
7358 #define WOL_REASON_QCFG_RESP_WOL_REASON_LAST WOL_REASON_QCFG_RESP_WOL_REASON_INVALID
7359 u8 wol_pkt_len;
7360 u8 unused_0[4];
7361 u8 valid;
7362 };
7363
7364 /* coredump_segment_record (size:128b/16B) */
7365 struct coredump_segment_record {
7366 __le16 component_id;
7367 __le16 segment_id;
7368 __le16 max_instances;
7369 u8 version_hi;
7370 u8 version_low;
7371 u8 seg_flags;
7372 u8 compress_flags;
7373 #define SFLAG_COMPRESSED_ZLIB 0x1UL
7374 u8 unused_0[6];
7375 };
7376
7377 /* hwrm_dbg_coredump_list_input (size:256b/32B) */
7378 struct hwrm_dbg_coredump_list_input {
7379 __le16 req_type;
7380 __le16 cmpl_ring;
7381 __le16 seq_id;
7382 __le16 target_id;
7383 __le64 resp_addr;
7384 __le64 host_dest_addr;
7385 __le32 host_buf_len;
7386 __le16 seq_no;
7387 u8 flags;
7388 #define DBG_COREDUMP_LIST_REQ_FLAGS_CRASHDUMP 0x1UL
7389 u8 unused_0[1];
7390 };
7391
7392 /* hwrm_dbg_coredump_list_output (size:128b/16B) */
7393 struct hwrm_dbg_coredump_list_output {
7394 __le16 error_code;
7395 __le16 req_type;
7396 __le16 seq_id;
7397 __le16 resp_len;
7398 u8 flags;
7399 #define DBG_COREDUMP_LIST_RESP_FLAGS_MORE 0x1UL
7400 u8 unused_0;
7401 __le16 total_segments;
7402 __le16 data_len;
7403 u8 unused_1;
7404 u8 valid;
7405 };
7406
7407 /* hwrm_dbg_coredump_initiate_input (size:256b/32B) */
7408 struct hwrm_dbg_coredump_initiate_input {
7409 __le16 req_type;
7410 __le16 cmpl_ring;
7411 __le16 seq_id;
7412 __le16 target_id;
7413 __le64 resp_addr;
7414 __le16 component_id;
7415 __le16 segment_id;
7416 __le16 instance;
7417 __le16 unused_0;
7418 u8 seg_flags;
7419 u8 unused_1[7];
7420 };
7421
7422 /* hwrm_dbg_coredump_initiate_output (size:128b/16B) */
7423 struct hwrm_dbg_coredump_initiate_output {
7424 __le16 error_code;
7425 __le16 req_type;
7426 __le16 seq_id;
7427 __le16 resp_len;
7428 u8 unused_0[7];
7429 u8 valid;
7430 };
7431
7432 /* coredump_data_hdr (size:128b/16B) */
7433 struct coredump_data_hdr {
7434 __le32 address;
7435 __le32 flags_length;
7436 __le32 instance;
7437 __le32 next_offset;
7438 };
7439
7440 /* hwrm_dbg_coredump_retrieve_input (size:448b/56B) */
7441 struct hwrm_dbg_coredump_retrieve_input {
7442 __le16 req_type;
7443 __le16 cmpl_ring;
7444 __le16 seq_id;
7445 __le16 target_id;
7446 __le64 resp_addr;
7447 __le64 host_dest_addr;
7448 __le32 host_buf_len;
7449 __le32 unused_0;
7450 __le16 component_id;
7451 __le16 segment_id;
7452 __le16 instance;
7453 __le16 unused_1;
7454 u8 seg_flags;
7455 u8 unused_2;
7456 __le16 unused_3;
7457 __le32 unused_4;
7458 __le32 seq_no;
7459 __le32 unused_5;
7460 };
7461
7462 /* hwrm_dbg_coredump_retrieve_output (size:128b/16B) */
7463 struct hwrm_dbg_coredump_retrieve_output {
7464 __le16 error_code;
7465 __le16 req_type;
7466 __le16 seq_id;
7467 __le16 resp_len;
7468 u8 flags;
7469 #define DBG_COREDUMP_RETRIEVE_RESP_FLAGS_MORE 0x1UL
7470 u8 unused_0;
7471 __le16 data_len;
7472 u8 unused_1[3];
7473 u8 valid;
7474 };
7475
7476 /* hwrm_dbg_ring_info_get_input (size:192b/24B) */
7477 struct hwrm_dbg_ring_info_get_input {
7478 __le16 req_type;
7479 __le16 cmpl_ring;
7480 __le16 seq_id;
7481 __le16 target_id;
7482 __le64 resp_addr;
7483 u8 ring_type;
7484 #define DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL 0x0UL
7485 #define DBG_RING_INFO_GET_REQ_RING_TYPE_TX 0x1UL
7486 #define DBG_RING_INFO_GET_REQ_RING_TYPE_RX 0x2UL
7487 #define DBG_RING_INFO_GET_REQ_RING_TYPE_LAST DBG_RING_INFO_GET_REQ_RING_TYPE_RX
7488 u8 unused_0[3];
7489 __le32 fw_ring_id;
7490 };
7491
7492 /* hwrm_dbg_ring_info_get_output (size:192b/24B) */
7493 struct hwrm_dbg_ring_info_get_output {
7494 __le16 error_code;
7495 __le16 req_type;
7496 __le16 seq_id;
7497 __le16 resp_len;
7498 __le32 producer_index;
7499 __le32 consumer_index;
7500 u8 unused_0[7];
7501 u8 valid;
7502 };
7503
7504 /* hwrm_nvm_read_input (size:320b/40B) */
7505 struct hwrm_nvm_read_input {
7506 __le16 req_type;
7507 __le16 cmpl_ring;
7508 __le16 seq_id;
7509 __le16 target_id;
7510 __le64 resp_addr;
7511 __le64 host_dest_addr;
7512 __le16 dir_idx;
7513 u8 unused_0[2];
7514 __le32 offset;
7515 __le32 len;
7516 u8 unused_1[4];
7517 };
7518
7519 /* hwrm_nvm_read_output (size:128b/16B) */
7520 struct hwrm_nvm_read_output {
7521 __le16 error_code;
7522 __le16 req_type;
7523 __le16 seq_id;
7524 __le16 resp_len;
7525 u8 unused_0[7];
7526 u8 valid;
7527 };
7528
7529 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */
7530 struct hwrm_nvm_get_dir_entries_input {
7531 __le16 req_type;
7532 __le16 cmpl_ring;
7533 __le16 seq_id;
7534 __le16 target_id;
7535 __le64 resp_addr;
7536 __le64 host_dest_addr;
7537 };
7538
7539 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */
7540 struct hwrm_nvm_get_dir_entries_output {
7541 __le16 error_code;
7542 __le16 req_type;
7543 __le16 seq_id;
7544 __le16 resp_len;
7545 u8 unused_0[7];
7546 u8 valid;
7547 };
7548
7549 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */
7550 struct hwrm_nvm_get_dir_info_input {
7551 __le16 req_type;
7552 __le16 cmpl_ring;
7553 __le16 seq_id;
7554 __le16 target_id;
7555 __le64 resp_addr;
7556 };
7557
7558 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */
7559 struct hwrm_nvm_get_dir_info_output {
7560 __le16 error_code;
7561 __le16 req_type;
7562 __le16 seq_id;
7563 __le16 resp_len;
7564 __le32 entries;
7565 __le32 entry_length;
7566 u8 unused_0[7];
7567 u8 valid;
7568 };
7569
7570 /* hwrm_nvm_write_input (size:384b/48B) */
7571 struct hwrm_nvm_write_input {
7572 __le16 req_type;
7573 __le16 cmpl_ring;
7574 __le16 seq_id;
7575 __le16 target_id;
7576 __le64 resp_addr;
7577 __le64 host_src_addr;
7578 __le16 dir_type;
7579 __le16 dir_ordinal;
7580 __le16 dir_ext;
7581 __le16 dir_attr;
7582 __le32 dir_data_length;
7583 __le16 option;
7584 __le16 flags;
7585 #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL
7586 __le32 dir_item_length;
7587 __le32 unused_0;
7588 };
7589
7590 /* hwrm_nvm_write_output (size:128b/16B) */
7591 struct hwrm_nvm_write_output {
7592 __le16 error_code;
7593 __le16 req_type;
7594 __le16 seq_id;
7595 __le16 resp_len;
7596 __le32 dir_item_length;
7597 __le16 dir_idx;
7598 u8 unused_0;
7599 u8 valid;
7600 };
7601
7602 /* hwrm_nvm_write_cmd_err (size:64b/8B) */
7603 struct hwrm_nvm_write_cmd_err {
7604 u8 code;
7605 #define NVM_WRITE_CMD_ERR_CODE_UNKNOWN 0x0UL
7606 #define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL
7607 #define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL
7608 #define NVM_WRITE_CMD_ERR_CODE_LAST NVM_WRITE_CMD_ERR_CODE_NO_SPACE
7609 u8 unused_0[7];
7610 };
7611
7612 /* hwrm_nvm_modify_input (size:320b/40B) */
7613 struct hwrm_nvm_modify_input {
7614 __le16 req_type;
7615 __le16 cmpl_ring;
7616 __le16 seq_id;
7617 __le16 target_id;
7618 __le64 resp_addr;
7619 __le64 host_src_addr;
7620 __le16 dir_idx;
7621 u8 unused_0[2];
7622 __le32 offset;
7623 __le32 len;
7624 u8 unused_1[4];
7625 };
7626
7627 /* hwrm_nvm_modify_output (size:128b/16B) */
7628 struct hwrm_nvm_modify_output {
7629 __le16 error_code;
7630 __le16 req_type;
7631 __le16 seq_id;
7632 __le16 resp_len;
7633 u8 unused_0[7];
7634 u8 valid;
7635 };
7636
7637 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */
7638 struct hwrm_nvm_find_dir_entry_input {
7639 __le16 req_type;
7640 __le16 cmpl_ring;
7641 __le16 seq_id;
7642 __le16 target_id;
7643 __le64 resp_addr;
7644 __le32 enables;
7645 #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL
7646 __le16 dir_idx;
7647 __le16 dir_type;
7648 __le16 dir_ordinal;
7649 __le16 dir_ext;
7650 u8 opt_ordinal;
7651 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL
7652 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0
7653 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ 0x0UL
7654 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE 0x1UL
7655 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 0x2UL
7656 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_LAST NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT
7657 u8 unused_0[3];
7658 };
7659
7660 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */
7661 struct hwrm_nvm_find_dir_entry_output {
7662 __le16 error_code;
7663 __le16 req_type;
7664 __le16 seq_id;
7665 __le16 resp_len;
7666 __le32 dir_item_length;
7667 __le32 dir_data_length;
7668 __le32 fw_ver;
7669 __le16 dir_ordinal;
7670 __le16 dir_idx;
7671 u8 unused_0[7];
7672 u8 valid;
7673 };
7674
7675 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */
7676 struct hwrm_nvm_erase_dir_entry_input {
7677 __le16 req_type;
7678 __le16 cmpl_ring;
7679 __le16 seq_id;
7680 __le16 target_id;
7681 __le64 resp_addr;
7682 __le16 dir_idx;
7683 u8 unused_0[6];
7684 };
7685
7686 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */
7687 struct hwrm_nvm_erase_dir_entry_output {
7688 __le16 error_code;
7689 __le16 req_type;
7690 __le16 seq_id;
7691 __le16 resp_len;
7692 u8 unused_0[7];
7693 u8 valid;
7694 };
7695
7696 /* hwrm_nvm_get_dev_info_input (size:128b/16B) */
7697 struct hwrm_nvm_get_dev_info_input {
7698 __le16 req_type;
7699 __le16 cmpl_ring;
7700 __le16 seq_id;
7701 __le16 target_id;
7702 __le64 resp_addr;
7703 };
7704
7705 /* hwrm_nvm_get_dev_info_output (size:256b/32B) */
7706 struct hwrm_nvm_get_dev_info_output {
7707 __le16 error_code;
7708 __le16 req_type;
7709 __le16 seq_id;
7710 __le16 resp_len;
7711 __le16 manufacturer_id;
7712 __le16 device_id;
7713 __le32 sector_size;
7714 __le32 nvram_size;
7715 __le32 reserved_size;
7716 __le32 available_size;
7717 u8 nvm_cfg_ver_maj;
7718 u8 nvm_cfg_ver_min;
7719 u8 nvm_cfg_ver_upd;
7720 u8 valid;
7721 };
7722
7723 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */
7724 struct hwrm_nvm_mod_dir_entry_input {
7725 __le16 req_type;
7726 __le16 cmpl_ring;
7727 __le16 seq_id;
7728 __le16 target_id;
7729 __le64 resp_addr;
7730 __le32 enables;
7731 #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL
7732 __le16 dir_idx;
7733 __le16 dir_ordinal;
7734 __le16 dir_ext;
7735 __le16 dir_attr;
7736 __le32 checksum;
7737 };
7738
7739 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */
7740 struct hwrm_nvm_mod_dir_entry_output {
7741 __le16 error_code;
7742 __le16 req_type;
7743 __le16 seq_id;
7744 __le16 resp_len;
7745 u8 unused_0[7];
7746 u8 valid;
7747 };
7748
7749 /* hwrm_nvm_verify_update_input (size:192b/24B) */
7750 struct hwrm_nvm_verify_update_input {
7751 __le16 req_type;
7752 __le16 cmpl_ring;
7753 __le16 seq_id;
7754 __le16 target_id;
7755 __le64 resp_addr;
7756 __le16 dir_type;
7757 __le16 dir_ordinal;
7758 __le16 dir_ext;
7759 u8 unused_0[2];
7760 };
7761
7762 /* hwrm_nvm_verify_update_output (size:128b/16B) */
7763 struct hwrm_nvm_verify_update_output {
7764 __le16 error_code;
7765 __le16 req_type;
7766 __le16 seq_id;
7767 __le16 resp_len;
7768 u8 unused_0[7];
7769 u8 valid;
7770 };
7771
7772 /* hwrm_nvm_install_update_input (size:192b/24B) */
7773 struct hwrm_nvm_install_update_input {
7774 __le16 req_type;
7775 __le16 cmpl_ring;
7776 __le16 seq_id;
7777 __le16 target_id;
7778 __le64 resp_addr;
7779 __le32 install_type;
7780 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL
7781 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 0xffffffffUL
7782 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_LAST NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL
7783 __le16 flags;
7784 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE 0x1UL
7785 #define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG 0x2UL
7786 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG 0x4UL
7787 u8 unused_0[2];
7788 };
7789
7790 /* hwrm_nvm_install_update_output (size:192b/24B) */
7791 struct hwrm_nvm_install_update_output {
7792 __le16 error_code;
7793 __le16 req_type;
7794 __le16 seq_id;
7795 __le16 resp_len;
7796 __le64 installed_items;
7797 u8 result;
7798 #define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL
7799 #define NVM_INSTALL_UPDATE_RESP_RESULT_LAST NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS
7800 u8 problem_item;
7801 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE 0x0UL
7802 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL
7803 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_LAST NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE
7804 u8 reset_required;
7805 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE 0x0UL
7806 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI 0x1UL
7807 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL
7808 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_LAST NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER
7809 u8 unused_0[4];
7810 u8 valid;
7811 };
7812
7813 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */
7814 struct hwrm_nvm_install_update_cmd_err {
7815 u8 code;
7816 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN 0x0UL
7817 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR 0x1UL
7818 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL
7819 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE
7820 u8 unused_0[7];
7821 };
7822
7823 /* hwrm_nvm_get_variable_input (size:320b/40B) */
7824 struct hwrm_nvm_get_variable_input {
7825 __le16 req_type;
7826 __le16 cmpl_ring;
7827 __le16 seq_id;
7828 __le16 target_id;
7829 __le64 resp_addr;
7830 __le64 dest_data_addr;
7831 __le16 data_len;
7832 __le16 option_num;
7833 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL
7834 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL
7835 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_LAST NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF
7836 __le16 dimensions;
7837 __le16 index_0;
7838 __le16 index_1;
7839 __le16 index_2;
7840 __le16 index_3;
7841 u8 flags;
7842 #define NVM_GET_VARIABLE_REQ_FLAGS_FACTORY_DFLT 0x1UL
7843 u8 unused_0;
7844 };
7845
7846 /* hwrm_nvm_get_variable_output (size:128b/16B) */
7847 struct hwrm_nvm_get_variable_output {
7848 __le16 error_code;
7849 __le16 req_type;
7850 __le16 seq_id;
7851 __le16 resp_len;
7852 __le16 data_len;
7853 __le16 option_num;
7854 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_0 0x0UL
7855 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 0xffffUL
7856 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_LAST NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF
7857 u8 unused_0[3];
7858 u8 valid;
7859 };
7860
7861 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */
7862 struct hwrm_nvm_get_variable_cmd_err {
7863 u8 code;
7864 #define NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL
7865 #define NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL
7866 #define NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL
7867 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL
7868 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LAST NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT
7869 u8 unused_0[7];
7870 };
7871
7872 /* hwrm_nvm_set_variable_input (size:320b/40B) */
7873 struct hwrm_nvm_set_variable_input {
7874 __le16 req_type;
7875 __le16 cmpl_ring;
7876 __le16 seq_id;
7877 __le16 target_id;
7878 __le64 resp_addr;
7879 __le64 src_data_addr;
7880 __le16 data_len;
7881 __le16 option_num;
7882 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL
7883 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL
7884 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_LAST NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF
7885 __le16 dimensions;
7886 __le16 index_0;
7887 __le16 index_1;
7888 __le16 index_2;
7889 __le16 index_3;
7890 u8 flags;
7891 #define NVM_SET_VARIABLE_REQ_FLAGS_FORCE_FLUSH 0x1UL
7892 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_MASK 0xeUL
7893 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_SFT 1
7894 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_NONE (0x0UL << 1)
7895 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1 (0x1UL << 1)
7896 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_AES256 (0x2UL << 1)
7897 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH (0x3UL << 1)
7898 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_LAST NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH
7899 #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_MASK 0x70UL
7900 #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_SFT 4
7901 #define NVM_SET_VARIABLE_REQ_FLAGS_FACTORY_DEFAULT 0x80UL
7902 u8 unused_0;
7903 };
7904
7905 /* hwrm_nvm_set_variable_output (size:128b/16B) */
7906 struct hwrm_nvm_set_variable_output {
7907 __le16 error_code;
7908 __le16 req_type;
7909 __le16 seq_id;
7910 __le16 resp_len;
7911 u8 unused_0[7];
7912 u8 valid;
7913 };
7914
7915 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */
7916 struct hwrm_nvm_set_variable_cmd_err {
7917 u8 code;
7918 #define NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL
7919 #define NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL
7920 #define NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL
7921 #define NVM_SET_VARIABLE_CMD_ERR_CODE_LAST NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR
7922 u8 unused_0[7];
7923 };
7924
7925 /* hwrm_selftest_qlist_input (size:128b/16B) */
7926 struct hwrm_selftest_qlist_input {
7927 __le16 req_type;
7928 __le16 cmpl_ring;
7929 __le16 seq_id;
7930 __le16 target_id;
7931 __le64 resp_addr;
7932 };
7933
7934 /* hwrm_selftest_qlist_output (size:2240b/280B) */
7935 struct hwrm_selftest_qlist_output {
7936 __le16 error_code;
7937 __le16 req_type;
7938 __le16 seq_id;
7939 __le16 resp_len;
7940 u8 num_tests;
7941 u8 available_tests;
7942 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_NVM_TEST 0x1UL
7943 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_LINK_TEST 0x2UL
7944 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_REGISTER_TEST 0x4UL
7945 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_MEMORY_TEST 0x8UL
7946 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_PCIE_SERDES_TEST 0x10UL
7947 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_ETHERNET_SERDES_TEST 0x20UL
7948 u8 offline_tests;
7949 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_NVM_TEST 0x1UL
7950 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_LINK_TEST 0x2UL
7951 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_REGISTER_TEST 0x4UL
7952 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_MEMORY_TEST 0x8UL
7953 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_PCIE_SERDES_TEST 0x10UL
7954 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_ETHERNET_SERDES_TEST 0x20UL
7955 u8 unused_0;
7956 __le16 test_timeout;
7957 u8 unused_1[2];
7958 char test0_name[32];
7959 char test1_name[32];
7960 char test2_name[32];
7961 char test3_name[32];
7962 char test4_name[32];
7963 char test5_name[32];
7964 char test6_name[32];
7965 char test7_name[32];
7966 u8 unused_2[7];
7967 u8 valid;
7968 };
7969
7970 /* hwrm_selftest_exec_input (size:192b/24B) */
7971 struct hwrm_selftest_exec_input {
7972 __le16 req_type;
7973 __le16 cmpl_ring;
7974 __le16 seq_id;
7975 __le16 target_id;
7976 __le64 resp_addr;
7977 u8 flags;
7978 #define SELFTEST_EXEC_REQ_FLAGS_NVM_TEST 0x1UL
7979 #define SELFTEST_EXEC_REQ_FLAGS_LINK_TEST 0x2UL
7980 #define SELFTEST_EXEC_REQ_FLAGS_REGISTER_TEST 0x4UL
7981 #define SELFTEST_EXEC_REQ_FLAGS_MEMORY_TEST 0x8UL
7982 #define SELFTEST_EXEC_REQ_FLAGS_PCIE_SERDES_TEST 0x10UL
7983 #define SELFTEST_EXEC_REQ_FLAGS_ETHERNET_SERDES_TEST 0x20UL
7984 u8 unused_0[7];
7985 };
7986
7987 /* hwrm_selftest_exec_output (size:128b/16B) */
7988 struct hwrm_selftest_exec_output {
7989 __le16 error_code;
7990 __le16 req_type;
7991 __le16 seq_id;
7992 __le16 resp_len;
7993 u8 requested_tests;
7994 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_NVM_TEST 0x1UL
7995 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_LINK_TEST 0x2UL
7996 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_REGISTER_TEST 0x4UL
7997 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_MEMORY_TEST 0x8UL
7998 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_PCIE_SERDES_TEST 0x10UL
7999 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_ETHERNET_SERDES_TEST 0x20UL
8000 u8 test_success;
8001 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_NVM_TEST 0x1UL
8002 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_LINK_TEST 0x2UL
8003 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_REGISTER_TEST 0x4UL
8004 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_MEMORY_TEST 0x8UL
8005 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_PCIE_SERDES_TEST 0x10UL
8006 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_ETHERNET_SERDES_TEST 0x20UL
8007 u8 unused_0[5];
8008 u8 valid;
8009 };
8010
8011 /* hwrm_selftest_irq_input (size:128b/16B) */
8012 struct hwrm_selftest_irq_input {
8013 __le16 req_type;
8014 __le16 cmpl_ring;
8015 __le16 seq_id;
8016 __le16 target_id;
8017 __le64 resp_addr;
8018 };
8019
8020 /* hwrm_selftest_irq_output (size:128b/16B) */
8021 struct hwrm_selftest_irq_output {
8022 __le16 error_code;
8023 __le16 req_type;
8024 __le16 seq_id;
8025 __le16 resp_len;
8026 u8 unused_0[7];
8027 u8 valid;
8028 };
8029
8030 #endif /* _BNXT_HSI_H_ */
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