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net: bcmgenet: Add support for adaptive RX coalescing
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / broadcom / genet / bcmgenet.c
1 /*
2 * Broadcom GENET (Gigabit Ethernet) controller driver
3 *
4 * Copyright (c) 2014-2017 Broadcom
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #define pr_fmt(fmt) "bcmgenet: " fmt
12
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/sched.h>
16 #include <linux/types.h>
17 #include <linux/fcntl.h>
18 #include <linux/interrupt.h>
19 #include <linux/string.h>
20 #include <linux/if_ether.h>
21 #include <linux/init.h>
22 #include <linux/errno.h>
23 #include <linux/delay.h>
24 #include <linux/platform_device.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm.h>
27 #include <linux/clk.h>
28 #include <linux/of.h>
29 #include <linux/of_address.h>
30 #include <linux/of_irq.h>
31 #include <linux/of_net.h>
32 #include <linux/of_platform.h>
33 #include <net/arp.h>
34
35 #include <linux/mii.h>
36 #include <linux/ethtool.h>
37 #include <linux/netdevice.h>
38 #include <linux/inetdevice.h>
39 #include <linux/etherdevice.h>
40 #include <linux/skbuff.h>
41 #include <linux/in.h>
42 #include <linux/ip.h>
43 #include <linux/ipv6.h>
44 #include <linux/phy.h>
45 #include <linux/platform_data/bcmgenet.h>
46
47 #include <asm/unaligned.h>
48
49 #include "bcmgenet.h"
50
51 /* Maximum number of hardware queues, downsized if needed */
52 #define GENET_MAX_MQ_CNT 4
53
54 /* Default highest priority queue for multi queue support */
55 #define GENET_Q0_PRIORITY 0
56
57 #define GENET_Q16_RX_BD_CNT \
58 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q)
59 #define GENET_Q16_TX_BD_CNT \
60 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q)
61
62 #define RX_BUF_LENGTH 2048
63 #define SKB_ALIGNMENT 32
64
65 /* Tx/Rx DMA register offset, skip 256 descriptors */
66 #define WORDS_PER_BD(p) (p->hw_params->words_per_bd)
67 #define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32))
68
69 #define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \
70 TOTAL_DESC * DMA_DESC_SIZE)
71
72 #define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \
73 TOTAL_DESC * DMA_DESC_SIZE)
74
75 static inline void bcmgenet_writel(u32 value, void __iomem *offset)
76 {
77 /* MIPS chips strapped for BE will automagically configure the
78 * peripheral registers for CPU-native byte order.
79 */
80 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
81 __raw_writel(value, offset);
82 else
83 writel_relaxed(value, offset);
84 }
85
86 static inline u32 bcmgenet_readl(void __iomem *offset)
87 {
88 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
89 return __raw_readl(offset);
90 else
91 return readl_relaxed(offset);
92 }
93
94 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
95 void __iomem *d, u32 value)
96 {
97 bcmgenet_writel(value, d + DMA_DESC_LENGTH_STATUS);
98 }
99
100 static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
101 void __iomem *d)
102 {
103 return bcmgenet_readl(d + DMA_DESC_LENGTH_STATUS);
104 }
105
106 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
107 void __iomem *d,
108 dma_addr_t addr)
109 {
110 bcmgenet_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
111
112 /* Register writes to GISB bus can take couple hundred nanoseconds
113 * and are done for each packet, save these expensive writes unless
114 * the platform is explicitly configured for 64-bits/LPAE.
115 */
116 #ifdef CONFIG_PHYS_ADDR_T_64BIT
117 if (priv->hw_params->flags & GENET_HAS_40BITS)
118 bcmgenet_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
119 #endif
120 }
121
122 /* Combined address + length/status setter */
123 static inline void dmadesc_set(struct bcmgenet_priv *priv,
124 void __iomem *d, dma_addr_t addr, u32 val)
125 {
126 dmadesc_set_addr(priv, d, addr);
127 dmadesc_set_length_status(priv, d, val);
128 }
129
130 static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
131 void __iomem *d)
132 {
133 dma_addr_t addr;
134
135 addr = bcmgenet_readl(d + DMA_DESC_ADDRESS_LO);
136
137 /* Register writes to GISB bus can take couple hundred nanoseconds
138 * and are done for each packet, save these expensive writes unless
139 * the platform is explicitly configured for 64-bits/LPAE.
140 */
141 #ifdef CONFIG_PHYS_ADDR_T_64BIT
142 if (priv->hw_params->flags & GENET_HAS_40BITS)
143 addr |= (u64)bcmgenet_readl(d + DMA_DESC_ADDRESS_HI) << 32;
144 #endif
145 return addr;
146 }
147
148 #define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x"
149
150 #define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
151 NETIF_MSG_LINK)
152
153 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
154 {
155 if (GENET_IS_V1(priv))
156 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
157 else
158 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
159 }
160
161 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
162 {
163 if (GENET_IS_V1(priv))
164 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
165 else
166 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
167 }
168
169 /* These macros are defined to deal with register map change
170 * between GENET1.1 and GENET2. Only those currently being used
171 * by driver are defined.
172 */
173 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
174 {
175 if (GENET_IS_V1(priv))
176 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
177 else
178 return bcmgenet_readl(priv->base +
179 priv->hw_params->tbuf_offset + TBUF_CTRL);
180 }
181
182 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
183 {
184 if (GENET_IS_V1(priv))
185 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
186 else
187 bcmgenet_writel(val, priv->base +
188 priv->hw_params->tbuf_offset + TBUF_CTRL);
189 }
190
191 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
192 {
193 if (GENET_IS_V1(priv))
194 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
195 else
196 return bcmgenet_readl(priv->base +
197 priv->hw_params->tbuf_offset + TBUF_BP_MC);
198 }
199
200 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
201 {
202 if (GENET_IS_V1(priv))
203 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
204 else
205 bcmgenet_writel(val, priv->base +
206 priv->hw_params->tbuf_offset + TBUF_BP_MC);
207 }
208
209 /* RX/TX DMA register accessors */
210 enum dma_reg {
211 DMA_RING_CFG = 0,
212 DMA_CTRL,
213 DMA_STATUS,
214 DMA_SCB_BURST_SIZE,
215 DMA_ARB_CTRL,
216 DMA_PRIORITY_0,
217 DMA_PRIORITY_1,
218 DMA_PRIORITY_2,
219 DMA_INDEX2RING_0,
220 DMA_INDEX2RING_1,
221 DMA_INDEX2RING_2,
222 DMA_INDEX2RING_3,
223 DMA_INDEX2RING_4,
224 DMA_INDEX2RING_5,
225 DMA_INDEX2RING_6,
226 DMA_INDEX2RING_7,
227 DMA_RING0_TIMEOUT,
228 DMA_RING1_TIMEOUT,
229 DMA_RING2_TIMEOUT,
230 DMA_RING3_TIMEOUT,
231 DMA_RING4_TIMEOUT,
232 DMA_RING5_TIMEOUT,
233 DMA_RING6_TIMEOUT,
234 DMA_RING7_TIMEOUT,
235 DMA_RING8_TIMEOUT,
236 DMA_RING9_TIMEOUT,
237 DMA_RING10_TIMEOUT,
238 DMA_RING11_TIMEOUT,
239 DMA_RING12_TIMEOUT,
240 DMA_RING13_TIMEOUT,
241 DMA_RING14_TIMEOUT,
242 DMA_RING15_TIMEOUT,
243 DMA_RING16_TIMEOUT,
244 };
245
246 static const u8 bcmgenet_dma_regs_v3plus[] = {
247 [DMA_RING_CFG] = 0x00,
248 [DMA_CTRL] = 0x04,
249 [DMA_STATUS] = 0x08,
250 [DMA_SCB_BURST_SIZE] = 0x0C,
251 [DMA_ARB_CTRL] = 0x2C,
252 [DMA_PRIORITY_0] = 0x30,
253 [DMA_PRIORITY_1] = 0x34,
254 [DMA_PRIORITY_2] = 0x38,
255 [DMA_RING0_TIMEOUT] = 0x2C,
256 [DMA_RING1_TIMEOUT] = 0x30,
257 [DMA_RING2_TIMEOUT] = 0x34,
258 [DMA_RING3_TIMEOUT] = 0x38,
259 [DMA_RING4_TIMEOUT] = 0x3c,
260 [DMA_RING5_TIMEOUT] = 0x40,
261 [DMA_RING6_TIMEOUT] = 0x44,
262 [DMA_RING7_TIMEOUT] = 0x48,
263 [DMA_RING8_TIMEOUT] = 0x4c,
264 [DMA_RING9_TIMEOUT] = 0x50,
265 [DMA_RING10_TIMEOUT] = 0x54,
266 [DMA_RING11_TIMEOUT] = 0x58,
267 [DMA_RING12_TIMEOUT] = 0x5c,
268 [DMA_RING13_TIMEOUT] = 0x60,
269 [DMA_RING14_TIMEOUT] = 0x64,
270 [DMA_RING15_TIMEOUT] = 0x68,
271 [DMA_RING16_TIMEOUT] = 0x6C,
272 [DMA_INDEX2RING_0] = 0x70,
273 [DMA_INDEX2RING_1] = 0x74,
274 [DMA_INDEX2RING_2] = 0x78,
275 [DMA_INDEX2RING_3] = 0x7C,
276 [DMA_INDEX2RING_4] = 0x80,
277 [DMA_INDEX2RING_5] = 0x84,
278 [DMA_INDEX2RING_6] = 0x88,
279 [DMA_INDEX2RING_7] = 0x8C,
280 };
281
282 static const u8 bcmgenet_dma_regs_v2[] = {
283 [DMA_RING_CFG] = 0x00,
284 [DMA_CTRL] = 0x04,
285 [DMA_STATUS] = 0x08,
286 [DMA_SCB_BURST_SIZE] = 0x0C,
287 [DMA_ARB_CTRL] = 0x30,
288 [DMA_PRIORITY_0] = 0x34,
289 [DMA_PRIORITY_1] = 0x38,
290 [DMA_PRIORITY_2] = 0x3C,
291 [DMA_RING0_TIMEOUT] = 0x2C,
292 [DMA_RING1_TIMEOUT] = 0x30,
293 [DMA_RING2_TIMEOUT] = 0x34,
294 [DMA_RING3_TIMEOUT] = 0x38,
295 [DMA_RING4_TIMEOUT] = 0x3c,
296 [DMA_RING5_TIMEOUT] = 0x40,
297 [DMA_RING6_TIMEOUT] = 0x44,
298 [DMA_RING7_TIMEOUT] = 0x48,
299 [DMA_RING8_TIMEOUT] = 0x4c,
300 [DMA_RING9_TIMEOUT] = 0x50,
301 [DMA_RING10_TIMEOUT] = 0x54,
302 [DMA_RING11_TIMEOUT] = 0x58,
303 [DMA_RING12_TIMEOUT] = 0x5c,
304 [DMA_RING13_TIMEOUT] = 0x60,
305 [DMA_RING14_TIMEOUT] = 0x64,
306 [DMA_RING15_TIMEOUT] = 0x68,
307 [DMA_RING16_TIMEOUT] = 0x6C,
308 };
309
310 static const u8 bcmgenet_dma_regs_v1[] = {
311 [DMA_CTRL] = 0x00,
312 [DMA_STATUS] = 0x04,
313 [DMA_SCB_BURST_SIZE] = 0x0C,
314 [DMA_ARB_CTRL] = 0x30,
315 [DMA_PRIORITY_0] = 0x34,
316 [DMA_PRIORITY_1] = 0x38,
317 [DMA_PRIORITY_2] = 0x3C,
318 [DMA_RING0_TIMEOUT] = 0x2C,
319 [DMA_RING1_TIMEOUT] = 0x30,
320 [DMA_RING2_TIMEOUT] = 0x34,
321 [DMA_RING3_TIMEOUT] = 0x38,
322 [DMA_RING4_TIMEOUT] = 0x3c,
323 [DMA_RING5_TIMEOUT] = 0x40,
324 [DMA_RING6_TIMEOUT] = 0x44,
325 [DMA_RING7_TIMEOUT] = 0x48,
326 [DMA_RING8_TIMEOUT] = 0x4c,
327 [DMA_RING9_TIMEOUT] = 0x50,
328 [DMA_RING10_TIMEOUT] = 0x54,
329 [DMA_RING11_TIMEOUT] = 0x58,
330 [DMA_RING12_TIMEOUT] = 0x5c,
331 [DMA_RING13_TIMEOUT] = 0x60,
332 [DMA_RING14_TIMEOUT] = 0x64,
333 [DMA_RING15_TIMEOUT] = 0x68,
334 [DMA_RING16_TIMEOUT] = 0x6C,
335 };
336
337 /* Set at runtime once bcmgenet version is known */
338 static const u8 *bcmgenet_dma_regs;
339
340 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
341 {
342 return netdev_priv(dev_get_drvdata(dev));
343 }
344
345 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
346 enum dma_reg r)
347 {
348 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +
349 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
350 }
351
352 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
353 u32 val, enum dma_reg r)
354 {
355 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +
356 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
357 }
358
359 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
360 enum dma_reg r)
361 {
362 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +
363 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
364 }
365
366 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
367 u32 val, enum dma_reg r)
368 {
369 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +
370 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
371 }
372
373 /* RDMA/TDMA ring registers and accessors
374 * we merge the common fields and just prefix with T/D the registers
375 * having different meaning depending on the direction
376 */
377 enum dma_ring_reg {
378 TDMA_READ_PTR = 0,
379 RDMA_WRITE_PTR = TDMA_READ_PTR,
380 TDMA_READ_PTR_HI,
381 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
382 TDMA_CONS_INDEX,
383 RDMA_PROD_INDEX = TDMA_CONS_INDEX,
384 TDMA_PROD_INDEX,
385 RDMA_CONS_INDEX = TDMA_PROD_INDEX,
386 DMA_RING_BUF_SIZE,
387 DMA_START_ADDR,
388 DMA_START_ADDR_HI,
389 DMA_END_ADDR,
390 DMA_END_ADDR_HI,
391 DMA_MBUF_DONE_THRESH,
392 TDMA_FLOW_PERIOD,
393 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
394 TDMA_WRITE_PTR,
395 RDMA_READ_PTR = TDMA_WRITE_PTR,
396 TDMA_WRITE_PTR_HI,
397 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
398 };
399
400 /* GENET v4 supports 40-bits pointer addressing
401 * for obvious reasons the LO and HI word parts
402 * are contiguous, but this offsets the other
403 * registers.
404 */
405 static const u8 genet_dma_ring_regs_v4[] = {
406 [TDMA_READ_PTR] = 0x00,
407 [TDMA_READ_PTR_HI] = 0x04,
408 [TDMA_CONS_INDEX] = 0x08,
409 [TDMA_PROD_INDEX] = 0x0C,
410 [DMA_RING_BUF_SIZE] = 0x10,
411 [DMA_START_ADDR] = 0x14,
412 [DMA_START_ADDR_HI] = 0x18,
413 [DMA_END_ADDR] = 0x1C,
414 [DMA_END_ADDR_HI] = 0x20,
415 [DMA_MBUF_DONE_THRESH] = 0x24,
416 [TDMA_FLOW_PERIOD] = 0x28,
417 [TDMA_WRITE_PTR] = 0x2C,
418 [TDMA_WRITE_PTR_HI] = 0x30,
419 };
420
421 static const u8 genet_dma_ring_regs_v123[] = {
422 [TDMA_READ_PTR] = 0x00,
423 [TDMA_CONS_INDEX] = 0x04,
424 [TDMA_PROD_INDEX] = 0x08,
425 [DMA_RING_BUF_SIZE] = 0x0C,
426 [DMA_START_ADDR] = 0x10,
427 [DMA_END_ADDR] = 0x14,
428 [DMA_MBUF_DONE_THRESH] = 0x18,
429 [TDMA_FLOW_PERIOD] = 0x1C,
430 [TDMA_WRITE_PTR] = 0x20,
431 };
432
433 /* Set at runtime once GENET version is known */
434 static const u8 *genet_dma_ring_regs;
435
436 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
437 unsigned int ring,
438 enum dma_ring_reg r)
439 {
440 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +
441 (DMA_RING_SIZE * ring) +
442 genet_dma_ring_regs[r]);
443 }
444
445 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
446 unsigned int ring, u32 val,
447 enum dma_ring_reg r)
448 {
449 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +
450 (DMA_RING_SIZE * ring) +
451 genet_dma_ring_regs[r]);
452 }
453
454 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
455 unsigned int ring,
456 enum dma_ring_reg r)
457 {
458 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +
459 (DMA_RING_SIZE * ring) +
460 genet_dma_ring_regs[r]);
461 }
462
463 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
464 unsigned int ring, u32 val,
465 enum dma_ring_reg r)
466 {
467 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +
468 (DMA_RING_SIZE * ring) +
469 genet_dma_ring_regs[r]);
470 }
471
472 static int bcmgenet_begin(struct net_device *dev)
473 {
474 struct bcmgenet_priv *priv = netdev_priv(dev);
475
476 /* Turn on the clock */
477 return clk_prepare_enable(priv->clk);
478 }
479
480 static void bcmgenet_complete(struct net_device *dev)
481 {
482 struct bcmgenet_priv *priv = netdev_priv(dev);
483
484 /* Turn off the clock */
485 clk_disable_unprepare(priv->clk);
486 }
487
488 static int bcmgenet_get_link_ksettings(struct net_device *dev,
489 struct ethtool_link_ksettings *cmd)
490 {
491 if (!netif_running(dev))
492 return -EINVAL;
493
494 if (!dev->phydev)
495 return -ENODEV;
496
497 phy_ethtool_ksettings_get(dev->phydev, cmd);
498
499 return 0;
500 }
501
502 static int bcmgenet_set_link_ksettings(struct net_device *dev,
503 const struct ethtool_link_ksettings *cmd)
504 {
505 if (!netif_running(dev))
506 return -EINVAL;
507
508 if (!dev->phydev)
509 return -ENODEV;
510
511 return phy_ethtool_ksettings_set(dev->phydev, cmd);
512 }
513
514 static int bcmgenet_set_rx_csum(struct net_device *dev,
515 netdev_features_t wanted)
516 {
517 struct bcmgenet_priv *priv = netdev_priv(dev);
518 u32 rbuf_chk_ctrl;
519 bool rx_csum_en;
520
521 rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
522
523 rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
524
525 /* enable rx checksumming */
526 if (rx_csum_en)
527 rbuf_chk_ctrl |= RBUF_RXCHK_EN;
528 else
529 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
530 priv->desc_rxchk_en = rx_csum_en;
531
532 /* If UniMAC forwards CRC, we need to skip over it to get
533 * a valid CHK bit to be set in the per-packet status word
534 */
535 if (rx_csum_en && priv->crc_fwd_en)
536 rbuf_chk_ctrl |= RBUF_SKIP_FCS;
537 else
538 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
539
540 bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
541
542 return 0;
543 }
544
545 static int bcmgenet_set_tx_csum(struct net_device *dev,
546 netdev_features_t wanted)
547 {
548 struct bcmgenet_priv *priv = netdev_priv(dev);
549 bool desc_64b_en;
550 u32 tbuf_ctrl, rbuf_ctrl;
551
552 tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
553 rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
554
555 desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
556
557 /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
558 if (desc_64b_en) {
559 tbuf_ctrl |= RBUF_64B_EN;
560 rbuf_ctrl |= RBUF_64B_EN;
561 } else {
562 tbuf_ctrl &= ~RBUF_64B_EN;
563 rbuf_ctrl &= ~RBUF_64B_EN;
564 }
565 priv->desc_64b_en = desc_64b_en;
566
567 bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
568 bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
569
570 return 0;
571 }
572
573 static int bcmgenet_set_features(struct net_device *dev,
574 netdev_features_t features)
575 {
576 netdev_features_t changed = features ^ dev->features;
577 netdev_features_t wanted = dev->wanted_features;
578 int ret = 0;
579
580 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
581 ret = bcmgenet_set_tx_csum(dev, wanted);
582 if (changed & (NETIF_F_RXCSUM))
583 ret = bcmgenet_set_rx_csum(dev, wanted);
584
585 return ret;
586 }
587
588 static u32 bcmgenet_get_msglevel(struct net_device *dev)
589 {
590 struct bcmgenet_priv *priv = netdev_priv(dev);
591
592 return priv->msg_enable;
593 }
594
595 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
596 {
597 struct bcmgenet_priv *priv = netdev_priv(dev);
598
599 priv->msg_enable = level;
600 }
601
602 static int bcmgenet_get_coalesce(struct net_device *dev,
603 struct ethtool_coalesce *ec)
604 {
605 struct bcmgenet_priv *priv = netdev_priv(dev);
606 struct bcmgenet_rx_ring *ring;
607 unsigned int i;
608
609 ec->tx_max_coalesced_frames =
610 bcmgenet_tdma_ring_readl(priv, DESC_INDEX,
611 DMA_MBUF_DONE_THRESH);
612 ec->rx_max_coalesced_frames =
613 bcmgenet_rdma_ring_readl(priv, DESC_INDEX,
614 DMA_MBUF_DONE_THRESH);
615 ec->rx_coalesce_usecs =
616 bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT) * 8192 / 1000;
617
618 for (i = 0; i < priv->hw_params->rx_queues; i++) {
619 ring = &priv->rx_rings[i];
620 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim;
621 }
622 ring = &priv->rx_rings[DESC_INDEX];
623 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim;
624
625 return 0;
626 }
627
628 static void bcmgenet_set_rx_coalesce(struct bcmgenet_rx_ring *ring)
629 {
630 struct bcmgenet_priv *priv = ring->priv;
631 unsigned int i = ring->index;
632 u32 reg;
633
634 bcmgenet_rdma_ring_writel(priv, i, ring->dim.coal_pkts,
635 DMA_MBUF_DONE_THRESH);
636
637 reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i);
638 reg &= ~DMA_TIMEOUT_MASK;
639 reg |= DIV_ROUND_UP(ring->dim.coal_usecs * 1000, 8192);
640 bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i);
641 }
642
643 static int bcmgenet_set_coalesce(struct net_device *dev,
644 struct ethtool_coalesce *ec)
645 {
646 struct bcmgenet_priv *priv = netdev_priv(dev);
647 struct bcmgenet_rx_ring *ring;
648 unsigned int i;
649
650 /* Base system clock is 125Mhz, DMA timeout is this reference clock
651 * divided by 1024, which yields roughly 8.192us, our maximum value
652 * has to fit in the DMA_TIMEOUT_MASK (16 bits)
653 */
654 if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
655 ec->tx_max_coalesced_frames == 0 ||
656 ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
657 ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1)
658 return -EINVAL;
659
660 if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0)
661 return -EINVAL;
662
663 /* GENET TDMA hardware does not support a configurable timeout, but will
664 * always generate an interrupt either after MBDONE packets have been
665 * transmitted, or when the ring is empty.
666 */
667 if (ec->tx_coalesce_usecs || ec->tx_coalesce_usecs_high ||
668 ec->tx_coalesce_usecs_irq || ec->tx_coalesce_usecs_low ||
669 ec->use_adaptive_tx_coalesce)
670 return -EOPNOTSUPP;
671
672 /* Program all TX queues with the same values, as there is no
673 * ethtool knob to do coalescing on a per-queue basis
674 */
675 for (i = 0; i < priv->hw_params->tx_queues; i++)
676 bcmgenet_tdma_ring_writel(priv, i,
677 ec->tx_max_coalesced_frames,
678 DMA_MBUF_DONE_THRESH);
679 bcmgenet_tdma_ring_writel(priv, DESC_INDEX,
680 ec->tx_max_coalesced_frames,
681 DMA_MBUF_DONE_THRESH);
682
683 for (i = 0; i < priv->hw_params->rx_queues; i++) {
684 ring = &priv->rx_rings[i];
685 ring->dim.coal_usecs = ec->rx_coalesce_usecs;
686 ring->dim.coal_pkts = ec->rx_max_coalesced_frames;
687 if (!ec->use_adaptive_rx_coalesce && ring->dim.use_dim) {
688 ring->dim.coal_pkts = 1;
689 ring->dim.coal_usecs = 0;
690 }
691 ring->dim.use_dim = ec->use_adaptive_rx_coalesce;
692 bcmgenet_set_rx_coalesce(ring);
693 }
694
695 ring = &priv->rx_rings[DESC_INDEX];
696 ring->dim.coal_usecs = ec->rx_coalesce_usecs;
697 ring->dim.coal_pkts = ec->rx_max_coalesced_frames;
698 if (!ec->use_adaptive_rx_coalesce && ring->dim.use_dim) {
699 ring->dim.coal_pkts = 1;
700 ring->dim.coal_usecs = 0;
701 }
702 ring->dim.use_dim = ec->use_adaptive_rx_coalesce;
703 bcmgenet_set_rx_coalesce(ring);
704
705 return 0;
706 }
707
708 /* standard ethtool support functions. */
709 enum bcmgenet_stat_type {
710 BCMGENET_STAT_NETDEV = -1,
711 BCMGENET_STAT_MIB_RX,
712 BCMGENET_STAT_MIB_TX,
713 BCMGENET_STAT_RUNT,
714 BCMGENET_STAT_MISC,
715 BCMGENET_STAT_SOFT,
716 };
717
718 struct bcmgenet_stats {
719 char stat_string[ETH_GSTRING_LEN];
720 int stat_sizeof;
721 int stat_offset;
722 enum bcmgenet_stat_type type;
723 /* reg offset from UMAC base for misc counters */
724 u16 reg_offset;
725 };
726
727 #define STAT_NETDEV(m) { \
728 .stat_string = __stringify(m), \
729 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
730 .stat_offset = offsetof(struct net_device_stats, m), \
731 .type = BCMGENET_STAT_NETDEV, \
732 }
733
734 #define STAT_GENET_MIB(str, m, _type) { \
735 .stat_string = str, \
736 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
737 .stat_offset = offsetof(struct bcmgenet_priv, m), \
738 .type = _type, \
739 }
740
741 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
742 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
743 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
744 #define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT)
745
746 #define STAT_GENET_MISC(str, m, offset) { \
747 .stat_string = str, \
748 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
749 .stat_offset = offsetof(struct bcmgenet_priv, m), \
750 .type = BCMGENET_STAT_MISC, \
751 .reg_offset = offset, \
752 }
753
754 #define STAT_GENET_Q(num) \
755 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_packets", \
756 tx_rings[num].packets), \
757 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_bytes", \
758 tx_rings[num].bytes), \
759 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_bytes", \
760 rx_rings[num].bytes), \
761 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_packets", \
762 rx_rings[num].packets), \
763 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_errors", \
764 rx_rings[num].errors), \
765 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_dropped", \
766 rx_rings[num].dropped)
767
768 /* There is a 0xC gap between the end of RX and beginning of TX stats and then
769 * between the end of TX stats and the beginning of the RX RUNT
770 */
771 #define BCMGENET_STAT_OFFSET 0xc
772
773 /* Hardware counters must be kept in sync because the order/offset
774 * is important here (order in structure declaration = order in hardware)
775 */
776 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
777 /* general stats */
778 STAT_NETDEV(rx_packets),
779 STAT_NETDEV(tx_packets),
780 STAT_NETDEV(rx_bytes),
781 STAT_NETDEV(tx_bytes),
782 STAT_NETDEV(rx_errors),
783 STAT_NETDEV(tx_errors),
784 STAT_NETDEV(rx_dropped),
785 STAT_NETDEV(tx_dropped),
786 STAT_NETDEV(multicast),
787 /* UniMAC RSV counters */
788 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
789 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
790 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
791 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
792 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
793 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
794 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
795 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
796 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
797 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
798 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
799 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
800 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
801 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
802 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
803 STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
804 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
805 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
806 STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
807 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
808 STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
809 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
810 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
811 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
812 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
813 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
814 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
815 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
816 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
817 /* UniMAC TSV counters */
818 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
819 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
820 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
821 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
822 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
823 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
824 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
825 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
826 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
827 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
828 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
829 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
830 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
831 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
832 STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
833 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
834 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
835 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
836 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
837 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
838 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
839 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
840 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
841 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
842 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
843 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
844 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
845 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
846 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
847 /* UniMAC RUNT counters */
848 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
849 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
850 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
851 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
852 /* Misc UniMAC counters */
853 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
854 UMAC_RBUF_OVFL_CNT_V1),
855 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt,
856 UMAC_RBUF_ERR_CNT_V1),
857 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
858 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
859 STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed),
860 STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed),
861 /* Per TX queues */
862 STAT_GENET_Q(0),
863 STAT_GENET_Q(1),
864 STAT_GENET_Q(2),
865 STAT_GENET_Q(3),
866 STAT_GENET_Q(16),
867 };
868
869 #define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats)
870
871 static void bcmgenet_get_drvinfo(struct net_device *dev,
872 struct ethtool_drvinfo *info)
873 {
874 strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
875 strlcpy(info->version, "v2.0", sizeof(info->version));
876 }
877
878 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
879 {
880 switch (string_set) {
881 case ETH_SS_STATS:
882 return BCMGENET_STATS_LEN;
883 default:
884 return -EOPNOTSUPP;
885 }
886 }
887
888 static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
889 u8 *data)
890 {
891 int i;
892
893 switch (stringset) {
894 case ETH_SS_STATS:
895 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
896 memcpy(data + i * ETH_GSTRING_LEN,
897 bcmgenet_gstrings_stats[i].stat_string,
898 ETH_GSTRING_LEN);
899 }
900 break;
901 }
902 }
903
904 static u32 bcmgenet_update_stat_misc(struct bcmgenet_priv *priv, u16 offset)
905 {
906 u16 new_offset;
907 u32 val;
908
909 switch (offset) {
910 case UMAC_RBUF_OVFL_CNT_V1:
911 if (GENET_IS_V2(priv))
912 new_offset = RBUF_OVFL_CNT_V2;
913 else
914 new_offset = RBUF_OVFL_CNT_V3PLUS;
915
916 val = bcmgenet_rbuf_readl(priv, new_offset);
917 /* clear if overflowed */
918 if (val == ~0)
919 bcmgenet_rbuf_writel(priv, 0, new_offset);
920 break;
921 case UMAC_RBUF_ERR_CNT_V1:
922 if (GENET_IS_V2(priv))
923 new_offset = RBUF_ERR_CNT_V2;
924 else
925 new_offset = RBUF_ERR_CNT_V3PLUS;
926
927 val = bcmgenet_rbuf_readl(priv, new_offset);
928 /* clear if overflowed */
929 if (val == ~0)
930 bcmgenet_rbuf_writel(priv, 0, new_offset);
931 break;
932 default:
933 val = bcmgenet_umac_readl(priv, offset);
934 /* clear if overflowed */
935 if (val == ~0)
936 bcmgenet_umac_writel(priv, 0, offset);
937 break;
938 }
939
940 return val;
941 }
942
943 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
944 {
945 int i, j = 0;
946
947 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
948 const struct bcmgenet_stats *s;
949 u8 offset = 0;
950 u32 val = 0;
951 char *p;
952
953 s = &bcmgenet_gstrings_stats[i];
954 switch (s->type) {
955 case BCMGENET_STAT_NETDEV:
956 case BCMGENET_STAT_SOFT:
957 continue;
958 case BCMGENET_STAT_RUNT:
959 offset += BCMGENET_STAT_OFFSET;
960 /* fall through */
961 case BCMGENET_STAT_MIB_TX:
962 offset += BCMGENET_STAT_OFFSET;
963 /* fall through */
964 case BCMGENET_STAT_MIB_RX:
965 val = bcmgenet_umac_readl(priv,
966 UMAC_MIB_START + j + offset);
967 offset = 0; /* Reset Offset */
968 break;
969 case BCMGENET_STAT_MISC:
970 if (GENET_IS_V1(priv)) {
971 val = bcmgenet_umac_readl(priv, s->reg_offset);
972 /* clear if overflowed */
973 if (val == ~0)
974 bcmgenet_umac_writel(priv, 0,
975 s->reg_offset);
976 } else {
977 val = bcmgenet_update_stat_misc(priv,
978 s->reg_offset);
979 }
980 break;
981 }
982
983 j += s->stat_sizeof;
984 p = (char *)priv + s->stat_offset;
985 *(u32 *)p = val;
986 }
987 }
988
989 static void bcmgenet_get_ethtool_stats(struct net_device *dev,
990 struct ethtool_stats *stats,
991 u64 *data)
992 {
993 struct bcmgenet_priv *priv = netdev_priv(dev);
994 int i;
995
996 if (netif_running(dev))
997 bcmgenet_update_mib_counters(priv);
998
999 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
1000 const struct bcmgenet_stats *s;
1001 char *p;
1002
1003 s = &bcmgenet_gstrings_stats[i];
1004 if (s->type == BCMGENET_STAT_NETDEV)
1005 p = (char *)&dev->stats;
1006 else
1007 p = (char *)priv;
1008 p += s->stat_offset;
1009 if (sizeof(unsigned long) != sizeof(u32) &&
1010 s->stat_sizeof == sizeof(unsigned long))
1011 data[i] = *(unsigned long *)p;
1012 else
1013 data[i] = *(u32 *)p;
1014 }
1015 }
1016
1017 static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable)
1018 {
1019 struct bcmgenet_priv *priv = netdev_priv(dev);
1020 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
1021 u32 reg;
1022
1023 if (enable && !priv->clk_eee_enabled) {
1024 clk_prepare_enable(priv->clk_eee);
1025 priv->clk_eee_enabled = true;
1026 }
1027
1028 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
1029 if (enable)
1030 reg |= EEE_EN;
1031 else
1032 reg &= ~EEE_EN;
1033 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
1034
1035 /* Enable EEE and switch to a 27Mhz clock automatically */
1036 reg = bcmgenet_readl(priv->base + off);
1037 if (enable)
1038 reg |= TBUF_EEE_EN | TBUF_PM_EN;
1039 else
1040 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
1041 bcmgenet_writel(reg, priv->base + off);
1042
1043 /* Do the same for thing for RBUF */
1044 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
1045 if (enable)
1046 reg |= RBUF_EEE_EN | RBUF_PM_EN;
1047 else
1048 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
1049 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
1050
1051 if (!enable && priv->clk_eee_enabled) {
1052 clk_disable_unprepare(priv->clk_eee);
1053 priv->clk_eee_enabled = false;
1054 }
1055
1056 priv->eee.eee_enabled = enable;
1057 priv->eee.eee_active = enable;
1058 }
1059
1060 static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e)
1061 {
1062 struct bcmgenet_priv *priv = netdev_priv(dev);
1063 struct ethtool_eee *p = &priv->eee;
1064
1065 if (GENET_IS_V1(priv))
1066 return -EOPNOTSUPP;
1067
1068 if (!dev->phydev)
1069 return -ENODEV;
1070
1071 e->eee_enabled = p->eee_enabled;
1072 e->eee_active = p->eee_active;
1073 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
1074
1075 return phy_ethtool_get_eee(dev->phydev, e);
1076 }
1077
1078 static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e)
1079 {
1080 struct bcmgenet_priv *priv = netdev_priv(dev);
1081 struct ethtool_eee *p = &priv->eee;
1082 int ret = 0;
1083
1084 if (GENET_IS_V1(priv))
1085 return -EOPNOTSUPP;
1086
1087 if (!dev->phydev)
1088 return -ENODEV;
1089
1090 p->eee_enabled = e->eee_enabled;
1091
1092 if (!p->eee_enabled) {
1093 bcmgenet_eee_enable_set(dev, false);
1094 } else {
1095 ret = phy_init_eee(dev->phydev, 0);
1096 if (ret) {
1097 netif_err(priv, hw, dev, "EEE initialization failed\n");
1098 return ret;
1099 }
1100
1101 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
1102 bcmgenet_eee_enable_set(dev, true);
1103 }
1104
1105 return phy_ethtool_set_eee(dev->phydev, e);
1106 }
1107
1108 /* standard ethtool support functions. */
1109 static const struct ethtool_ops bcmgenet_ethtool_ops = {
1110 .begin = bcmgenet_begin,
1111 .complete = bcmgenet_complete,
1112 .get_strings = bcmgenet_get_strings,
1113 .get_sset_count = bcmgenet_get_sset_count,
1114 .get_ethtool_stats = bcmgenet_get_ethtool_stats,
1115 .get_drvinfo = bcmgenet_get_drvinfo,
1116 .get_link = ethtool_op_get_link,
1117 .get_msglevel = bcmgenet_get_msglevel,
1118 .set_msglevel = bcmgenet_set_msglevel,
1119 .get_wol = bcmgenet_get_wol,
1120 .set_wol = bcmgenet_set_wol,
1121 .get_eee = bcmgenet_get_eee,
1122 .set_eee = bcmgenet_set_eee,
1123 .nway_reset = phy_ethtool_nway_reset,
1124 .get_coalesce = bcmgenet_get_coalesce,
1125 .set_coalesce = bcmgenet_set_coalesce,
1126 .get_link_ksettings = bcmgenet_get_link_ksettings,
1127 .set_link_ksettings = bcmgenet_set_link_ksettings,
1128 };
1129
1130 /* Power down the unimac, based on mode. */
1131 static int bcmgenet_power_down(struct bcmgenet_priv *priv,
1132 enum bcmgenet_power_mode mode)
1133 {
1134 int ret = 0;
1135 u32 reg;
1136
1137 switch (mode) {
1138 case GENET_POWER_CABLE_SENSE:
1139 phy_detach(priv->dev->phydev);
1140 break;
1141
1142 case GENET_POWER_WOL_MAGIC:
1143 ret = bcmgenet_wol_power_down_cfg(priv, mode);
1144 break;
1145
1146 case GENET_POWER_PASSIVE:
1147 /* Power down LED */
1148 if (priv->hw_params->flags & GENET_HAS_EXT) {
1149 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1150 if (GENET_IS_V5(priv))
1151 reg |= EXT_PWR_DOWN_PHY_EN |
1152 EXT_PWR_DOWN_PHY_RD |
1153 EXT_PWR_DOWN_PHY_SD |
1154 EXT_PWR_DOWN_PHY_RX |
1155 EXT_PWR_DOWN_PHY_TX |
1156 EXT_IDDQ_GLBL_PWR;
1157 else
1158 reg |= EXT_PWR_DOWN_PHY;
1159
1160 reg |= (EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
1161 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1162
1163 bcmgenet_phy_power_set(priv->dev, false);
1164 }
1165 break;
1166 default:
1167 break;
1168 }
1169
1170 return 0;
1171 }
1172
1173 static void bcmgenet_power_up(struct bcmgenet_priv *priv,
1174 enum bcmgenet_power_mode mode)
1175 {
1176 u32 reg;
1177
1178 if (!(priv->hw_params->flags & GENET_HAS_EXT))
1179 return;
1180
1181 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1182
1183 switch (mode) {
1184 case GENET_POWER_PASSIVE:
1185 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
1186 if (GENET_IS_V5(priv)) {
1187 reg &= ~(EXT_PWR_DOWN_PHY_EN |
1188 EXT_PWR_DOWN_PHY_RD |
1189 EXT_PWR_DOWN_PHY_SD |
1190 EXT_PWR_DOWN_PHY_RX |
1191 EXT_PWR_DOWN_PHY_TX |
1192 EXT_IDDQ_GLBL_PWR);
1193 reg |= EXT_PHY_RESET;
1194 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1195 mdelay(1);
1196
1197 reg &= ~EXT_PHY_RESET;
1198 } else {
1199 reg &= ~EXT_PWR_DOWN_PHY;
1200 reg |= EXT_PWR_DN_EN_LD;
1201 }
1202 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1203 bcmgenet_phy_power_set(priv->dev, true);
1204 break;
1205
1206 case GENET_POWER_CABLE_SENSE:
1207 /* enable APD */
1208 if (!GENET_IS_V5(priv)) {
1209 reg |= EXT_PWR_DN_EN_LD;
1210 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1211 }
1212 break;
1213 case GENET_POWER_WOL_MAGIC:
1214 bcmgenet_wol_power_up_cfg(priv, mode);
1215 return;
1216 default:
1217 break;
1218 }
1219 }
1220
1221 /* ioctl handle special commands that are not present in ethtool. */
1222 static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1223 {
1224 if (!netif_running(dev))
1225 return -EINVAL;
1226
1227 if (!dev->phydev)
1228 return -ENODEV;
1229
1230 return phy_mii_ioctl(dev->phydev, rq, cmd);
1231 }
1232
1233 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
1234 struct bcmgenet_tx_ring *ring)
1235 {
1236 struct enet_cb *tx_cb_ptr;
1237
1238 tx_cb_ptr = ring->cbs;
1239 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1240
1241 /* Advancing local write pointer */
1242 if (ring->write_ptr == ring->end_ptr)
1243 ring->write_ptr = ring->cb_ptr;
1244 else
1245 ring->write_ptr++;
1246
1247 return tx_cb_ptr;
1248 }
1249
1250 static struct enet_cb *bcmgenet_put_txcb(struct bcmgenet_priv *priv,
1251 struct bcmgenet_tx_ring *ring)
1252 {
1253 struct enet_cb *tx_cb_ptr;
1254
1255 tx_cb_ptr = ring->cbs;
1256 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1257
1258 /* Rewinding local write pointer */
1259 if (ring->write_ptr == ring->cb_ptr)
1260 ring->write_ptr = ring->end_ptr;
1261 else
1262 ring->write_ptr--;
1263
1264 return tx_cb_ptr;
1265 }
1266
1267 static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring)
1268 {
1269 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1270 INTRL2_CPU_MASK_SET);
1271 }
1272
1273 static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring)
1274 {
1275 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1276 INTRL2_CPU_MASK_CLEAR);
1277 }
1278
1279 static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring)
1280 {
1281 bcmgenet_intrl2_1_writel(ring->priv,
1282 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1283 INTRL2_CPU_MASK_SET);
1284 }
1285
1286 static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring)
1287 {
1288 bcmgenet_intrl2_1_writel(ring->priv,
1289 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1290 INTRL2_CPU_MASK_CLEAR);
1291 }
1292
1293 static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring)
1294 {
1295 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1296 INTRL2_CPU_MASK_SET);
1297 }
1298
1299 static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring)
1300 {
1301 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1302 INTRL2_CPU_MASK_CLEAR);
1303 }
1304
1305 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring)
1306 {
1307 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1308 INTRL2_CPU_MASK_CLEAR);
1309 }
1310
1311 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring)
1312 {
1313 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1314 INTRL2_CPU_MASK_SET);
1315 }
1316
1317 /* Simple helper to free a transmit control block's resources
1318 * Returns an skb when the last transmit control block associated with the
1319 * skb is freed. The skb should be freed by the caller if necessary.
1320 */
1321 static struct sk_buff *bcmgenet_free_tx_cb(struct device *dev,
1322 struct enet_cb *cb)
1323 {
1324 struct sk_buff *skb;
1325
1326 skb = cb->skb;
1327
1328 if (skb) {
1329 cb->skb = NULL;
1330 if (cb == GENET_CB(skb)->first_cb)
1331 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr),
1332 dma_unmap_len(cb, dma_len),
1333 DMA_TO_DEVICE);
1334 else
1335 dma_unmap_page(dev, dma_unmap_addr(cb, dma_addr),
1336 dma_unmap_len(cb, dma_len),
1337 DMA_TO_DEVICE);
1338 dma_unmap_addr_set(cb, dma_addr, 0);
1339
1340 if (cb == GENET_CB(skb)->last_cb)
1341 return skb;
1342
1343 } else if (dma_unmap_addr(cb, dma_addr)) {
1344 dma_unmap_page(dev,
1345 dma_unmap_addr(cb, dma_addr),
1346 dma_unmap_len(cb, dma_len),
1347 DMA_TO_DEVICE);
1348 dma_unmap_addr_set(cb, dma_addr, 0);
1349 }
1350
1351 return 0;
1352 }
1353
1354 /* Simple helper to free a receive control block's resources */
1355 static struct sk_buff *bcmgenet_free_rx_cb(struct device *dev,
1356 struct enet_cb *cb)
1357 {
1358 struct sk_buff *skb;
1359
1360 skb = cb->skb;
1361 cb->skb = NULL;
1362
1363 if (dma_unmap_addr(cb, dma_addr)) {
1364 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr),
1365 dma_unmap_len(cb, dma_len), DMA_FROM_DEVICE);
1366 dma_unmap_addr_set(cb, dma_addr, 0);
1367 }
1368
1369 return skb;
1370 }
1371
1372 /* Unlocked version of the reclaim routine */
1373 static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev,
1374 struct bcmgenet_tx_ring *ring)
1375 {
1376 struct bcmgenet_priv *priv = netdev_priv(dev);
1377 unsigned int txbds_processed = 0;
1378 unsigned int bytes_compl = 0;
1379 unsigned int pkts_compl = 0;
1380 unsigned int txbds_ready;
1381 unsigned int c_index;
1382 struct sk_buff *skb;
1383
1384 /* Clear status before servicing to reduce spurious interrupts */
1385 if (ring->index == DESC_INDEX)
1386 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_TXDMA_DONE,
1387 INTRL2_CPU_CLEAR);
1388 else
1389 bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
1390 INTRL2_CPU_CLEAR);
1391
1392 /* Compute how many buffers are transmitted since last xmit call */
1393 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX)
1394 & DMA_C_INDEX_MASK;
1395 txbds_ready = (c_index - ring->c_index) & DMA_C_INDEX_MASK;
1396
1397 netif_dbg(priv, tx_done, dev,
1398 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
1399 __func__, ring->index, ring->c_index, c_index, txbds_ready);
1400
1401 /* Reclaim transmitted buffers */
1402 while (txbds_processed < txbds_ready) {
1403 skb = bcmgenet_free_tx_cb(&priv->pdev->dev,
1404 &priv->tx_cbs[ring->clean_ptr]);
1405 if (skb) {
1406 pkts_compl++;
1407 bytes_compl += GENET_CB(skb)->bytes_sent;
1408 dev_consume_skb_any(skb);
1409 }
1410
1411 txbds_processed++;
1412 if (likely(ring->clean_ptr < ring->end_ptr))
1413 ring->clean_ptr++;
1414 else
1415 ring->clean_ptr = ring->cb_ptr;
1416 }
1417
1418 ring->free_bds += txbds_processed;
1419 ring->c_index = c_index;
1420
1421 ring->packets += pkts_compl;
1422 ring->bytes += bytes_compl;
1423
1424 netdev_tx_completed_queue(netdev_get_tx_queue(dev, ring->queue),
1425 pkts_compl, bytes_compl);
1426
1427 return txbds_processed;
1428 }
1429
1430 static unsigned int bcmgenet_tx_reclaim(struct net_device *dev,
1431 struct bcmgenet_tx_ring *ring)
1432 {
1433 unsigned int released;
1434
1435 spin_lock_bh(&ring->lock);
1436 released = __bcmgenet_tx_reclaim(dev, ring);
1437 spin_unlock_bh(&ring->lock);
1438
1439 return released;
1440 }
1441
1442 static int bcmgenet_tx_poll(struct napi_struct *napi, int budget)
1443 {
1444 struct bcmgenet_tx_ring *ring =
1445 container_of(napi, struct bcmgenet_tx_ring, napi);
1446 unsigned int work_done = 0;
1447 struct netdev_queue *txq;
1448
1449 spin_lock(&ring->lock);
1450 work_done = __bcmgenet_tx_reclaim(ring->priv->dev, ring);
1451 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
1452 txq = netdev_get_tx_queue(ring->priv->dev, ring->queue);
1453 netif_tx_wake_queue(txq);
1454 }
1455 spin_unlock(&ring->lock);
1456
1457 if (work_done == 0) {
1458 napi_complete(napi);
1459 ring->int_enable(ring);
1460
1461 return 0;
1462 }
1463
1464 return budget;
1465 }
1466
1467 static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1468 {
1469 struct bcmgenet_priv *priv = netdev_priv(dev);
1470 int i;
1471
1472 if (netif_is_multiqueue(dev)) {
1473 for (i = 0; i < priv->hw_params->tx_queues; i++)
1474 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
1475 }
1476
1477 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
1478 }
1479
1480 /* Reallocate the SKB to put enough headroom in front of it and insert
1481 * the transmit checksum offsets in the descriptors
1482 */
1483 static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev,
1484 struct sk_buff *skb)
1485 {
1486 struct status_64 *status = NULL;
1487 struct sk_buff *new_skb;
1488 u16 offset;
1489 u8 ip_proto;
1490 u16 ip_ver;
1491 u32 tx_csum_info;
1492
1493 if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1494 /* If 64 byte status block enabled, must make sure skb has
1495 * enough headroom for us to insert 64B status block.
1496 */
1497 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1498 dev_kfree_skb(skb);
1499 if (!new_skb) {
1500 dev->stats.tx_dropped++;
1501 return NULL;
1502 }
1503 skb = new_skb;
1504 }
1505
1506 skb_push(skb, sizeof(*status));
1507 status = (struct status_64 *)skb->data;
1508
1509 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1510 ip_ver = htons(skb->protocol);
1511 switch (ip_ver) {
1512 case ETH_P_IP:
1513 ip_proto = ip_hdr(skb)->protocol;
1514 break;
1515 case ETH_P_IPV6:
1516 ip_proto = ipv6_hdr(skb)->nexthdr;
1517 break;
1518 default:
1519 return skb;
1520 }
1521
1522 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1523 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1524 (offset + skb->csum_offset);
1525
1526 /* Set the length valid bit for TCP and UDP and just set
1527 * the special UDP flag for IPv4, else just set to 0.
1528 */
1529 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1530 tx_csum_info |= STATUS_TX_CSUM_LV;
1531 if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
1532 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
1533 } else {
1534 tx_csum_info = 0;
1535 }
1536
1537 status->tx_csum_info = tx_csum_info;
1538 }
1539
1540 return skb;
1541 }
1542
1543 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1544 {
1545 struct bcmgenet_priv *priv = netdev_priv(dev);
1546 struct device *kdev = &priv->pdev->dev;
1547 struct bcmgenet_tx_ring *ring = NULL;
1548 struct enet_cb *tx_cb_ptr;
1549 struct netdev_queue *txq;
1550 int nr_frags, index;
1551 dma_addr_t mapping;
1552 unsigned int size;
1553 skb_frag_t *frag;
1554 u32 len_stat;
1555 int ret;
1556 int i;
1557
1558 index = skb_get_queue_mapping(skb);
1559 /* Mapping strategy:
1560 * queue_mapping = 0, unclassified, packet xmited through ring16
1561 * queue_mapping = 1, goes to ring 0. (highest priority queue
1562 * queue_mapping = 2, goes to ring 1.
1563 * queue_mapping = 3, goes to ring 2.
1564 * queue_mapping = 4, goes to ring 3.
1565 */
1566 if (index == 0)
1567 index = DESC_INDEX;
1568 else
1569 index -= 1;
1570
1571 ring = &priv->tx_rings[index];
1572 txq = netdev_get_tx_queue(dev, ring->queue);
1573
1574 nr_frags = skb_shinfo(skb)->nr_frags;
1575
1576 spin_lock(&ring->lock);
1577 if (ring->free_bds <= (nr_frags + 1)) {
1578 if (!netif_tx_queue_stopped(txq)) {
1579 netif_tx_stop_queue(txq);
1580 netdev_err(dev,
1581 "%s: tx ring %d full when queue %d awake\n",
1582 __func__, index, ring->queue);
1583 }
1584 ret = NETDEV_TX_BUSY;
1585 goto out;
1586 }
1587
1588 if (skb_padto(skb, ETH_ZLEN)) {
1589 ret = NETDEV_TX_OK;
1590 goto out;
1591 }
1592
1593 /* Retain how many bytes will be sent on the wire, without TSB inserted
1594 * by transmit checksum offload
1595 */
1596 GENET_CB(skb)->bytes_sent = skb->len;
1597
1598 /* set the SKB transmit checksum */
1599 if (priv->desc_64b_en) {
1600 skb = bcmgenet_put_tx_csum(dev, skb);
1601 if (!skb) {
1602 ret = NETDEV_TX_OK;
1603 goto out;
1604 }
1605 }
1606
1607 for (i = 0; i <= nr_frags; i++) {
1608 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1609
1610 BUG_ON(!tx_cb_ptr);
1611
1612 if (!i) {
1613 /* Transmit single SKB or head of fragment list */
1614 GENET_CB(skb)->first_cb = tx_cb_ptr;
1615 size = skb_headlen(skb);
1616 mapping = dma_map_single(kdev, skb->data, size,
1617 DMA_TO_DEVICE);
1618 } else {
1619 /* xmit fragment */
1620 frag = &skb_shinfo(skb)->frags[i - 1];
1621 size = skb_frag_size(frag);
1622 mapping = skb_frag_dma_map(kdev, frag, 0, size,
1623 DMA_TO_DEVICE);
1624 }
1625
1626 ret = dma_mapping_error(kdev, mapping);
1627 if (ret) {
1628 priv->mib.tx_dma_failed++;
1629 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
1630 ret = NETDEV_TX_OK;
1631 goto out_unmap_frags;
1632 }
1633 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1634 dma_unmap_len_set(tx_cb_ptr, dma_len, size);
1635
1636 tx_cb_ptr->skb = skb;
1637
1638 len_stat = (size << DMA_BUFLENGTH_SHIFT) |
1639 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT);
1640
1641 if (!i) {
1642 len_stat |= DMA_TX_APPEND_CRC | DMA_SOP;
1643 if (skb->ip_summed == CHECKSUM_PARTIAL)
1644 len_stat |= DMA_TX_DO_CSUM;
1645 }
1646 if (i == nr_frags)
1647 len_stat |= DMA_EOP;
1648
1649 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, len_stat);
1650 }
1651
1652 GENET_CB(skb)->last_cb = tx_cb_ptr;
1653 skb_tx_timestamp(skb);
1654
1655 /* Decrement total BD count and advance our write pointer */
1656 ring->free_bds -= nr_frags + 1;
1657 ring->prod_index += nr_frags + 1;
1658 ring->prod_index &= DMA_P_INDEX_MASK;
1659
1660 netdev_tx_sent_queue(txq, GENET_CB(skb)->bytes_sent);
1661
1662 if (ring->free_bds <= (MAX_SKB_FRAGS + 1))
1663 netif_tx_stop_queue(txq);
1664
1665 if (!skb->xmit_more || netif_xmit_stopped(txq))
1666 /* Packets are ready, update producer index */
1667 bcmgenet_tdma_ring_writel(priv, ring->index,
1668 ring->prod_index, TDMA_PROD_INDEX);
1669 out:
1670 spin_unlock(&ring->lock);
1671
1672 return ret;
1673
1674 out_unmap_frags:
1675 /* Back up for failed control block mapping */
1676 bcmgenet_put_txcb(priv, ring);
1677
1678 /* Unmap successfully mapped control blocks */
1679 while (i-- > 0) {
1680 tx_cb_ptr = bcmgenet_put_txcb(priv, ring);
1681 bcmgenet_free_tx_cb(kdev, tx_cb_ptr);
1682 }
1683
1684 dev_kfree_skb(skb);
1685 goto out;
1686 }
1687
1688 static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv,
1689 struct enet_cb *cb)
1690 {
1691 struct device *kdev = &priv->pdev->dev;
1692 struct sk_buff *skb;
1693 struct sk_buff *rx_skb;
1694 dma_addr_t mapping;
1695
1696 /* Allocate a new Rx skb */
1697 skb = netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT);
1698 if (!skb) {
1699 priv->mib.alloc_rx_buff_failed++;
1700 netif_err(priv, rx_err, priv->dev,
1701 "%s: Rx skb allocation failed\n", __func__);
1702 return NULL;
1703 }
1704
1705 /* DMA-map the new Rx skb */
1706 mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len,
1707 DMA_FROM_DEVICE);
1708 if (dma_mapping_error(kdev, mapping)) {
1709 priv->mib.rx_dma_failed++;
1710 dev_kfree_skb_any(skb);
1711 netif_err(priv, rx_err, priv->dev,
1712 "%s: Rx skb DMA mapping failed\n", __func__);
1713 return NULL;
1714 }
1715
1716 /* Grab the current Rx skb from the ring and DMA-unmap it */
1717 rx_skb = bcmgenet_free_rx_cb(kdev, cb);
1718
1719 /* Put the new Rx skb on the ring */
1720 cb->skb = skb;
1721 dma_unmap_addr_set(cb, dma_addr, mapping);
1722 dma_unmap_len_set(cb, dma_len, priv->rx_buf_len);
1723 dmadesc_set_addr(priv, cb->bd_addr, mapping);
1724
1725 /* Return the current Rx skb to caller */
1726 return rx_skb;
1727 }
1728
1729 /* bcmgenet_desc_rx - descriptor based rx process.
1730 * this could be called from bottom half, or from NAPI polling method.
1731 */
1732 static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring,
1733 unsigned int budget)
1734 {
1735 struct bcmgenet_priv *priv = ring->priv;
1736 struct net_device *dev = priv->dev;
1737 struct enet_cb *cb;
1738 struct sk_buff *skb;
1739 u32 dma_length_status;
1740 unsigned long dma_flag;
1741 int len;
1742 unsigned int rxpktprocessed = 0, rxpkttoprocess;
1743 unsigned int bytes_processed = 0;
1744 unsigned int p_index, mask;
1745 unsigned int discards;
1746 unsigned int chksum_ok = 0;
1747
1748 /* Clear status before servicing to reduce spurious interrupts */
1749 if (ring->index == DESC_INDEX) {
1750 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_DONE,
1751 INTRL2_CPU_CLEAR);
1752 } else {
1753 mask = 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index);
1754 bcmgenet_intrl2_1_writel(priv,
1755 mask,
1756 INTRL2_CPU_CLEAR);
1757 }
1758
1759 p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX);
1760
1761 discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) &
1762 DMA_P_INDEX_DISCARD_CNT_MASK;
1763 if (discards > ring->old_discards) {
1764 discards = discards - ring->old_discards;
1765 ring->errors += discards;
1766 ring->old_discards += discards;
1767
1768 /* Clear HW register when we reach 75% of maximum 0xFFFF */
1769 if (ring->old_discards >= 0xC000) {
1770 ring->old_discards = 0;
1771 bcmgenet_rdma_ring_writel(priv, ring->index, 0,
1772 RDMA_PROD_INDEX);
1773 }
1774 }
1775
1776 p_index &= DMA_P_INDEX_MASK;
1777 rxpkttoprocess = (p_index - ring->c_index) & DMA_C_INDEX_MASK;
1778
1779 netif_dbg(priv, rx_status, dev,
1780 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1781
1782 while ((rxpktprocessed < rxpkttoprocess) &&
1783 (rxpktprocessed < budget)) {
1784 cb = &priv->rx_cbs[ring->read_ptr];
1785 skb = bcmgenet_rx_refill(priv, cb);
1786
1787 if (unlikely(!skb)) {
1788 ring->dropped++;
1789 goto next;
1790 }
1791
1792 if (!priv->desc_64b_en) {
1793 dma_length_status =
1794 dmadesc_get_length_status(priv, cb->bd_addr);
1795 } else {
1796 struct status_64 *status;
1797
1798 status = (struct status_64 *)skb->data;
1799 dma_length_status = status->length_status;
1800 }
1801
1802 /* DMA flags and length are still valid no matter how
1803 * we got the Receive Status Vector (64B RSB or register)
1804 */
1805 dma_flag = dma_length_status & 0xffff;
1806 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1807
1808 netif_dbg(priv, rx_status, dev,
1809 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
1810 __func__, p_index, ring->c_index,
1811 ring->read_ptr, dma_length_status);
1812
1813 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1814 netif_err(priv, rx_status, dev,
1815 "dropping fragmented packet!\n");
1816 ring->errors++;
1817 dev_kfree_skb_any(skb);
1818 goto next;
1819 }
1820
1821 /* report errors */
1822 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1823 DMA_RX_OV |
1824 DMA_RX_NO |
1825 DMA_RX_LG |
1826 DMA_RX_RXER))) {
1827 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
1828 (unsigned int)dma_flag);
1829 if (dma_flag & DMA_RX_CRC_ERROR)
1830 dev->stats.rx_crc_errors++;
1831 if (dma_flag & DMA_RX_OV)
1832 dev->stats.rx_over_errors++;
1833 if (dma_flag & DMA_RX_NO)
1834 dev->stats.rx_frame_errors++;
1835 if (dma_flag & DMA_RX_LG)
1836 dev->stats.rx_length_errors++;
1837 dev->stats.rx_errors++;
1838 dev_kfree_skb_any(skb);
1839 goto next;
1840 } /* error packet */
1841
1842 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
1843 priv->desc_rxchk_en;
1844
1845 skb_put(skb, len);
1846 if (priv->desc_64b_en) {
1847 skb_pull(skb, 64);
1848 len -= 64;
1849 }
1850
1851 if (likely(chksum_ok))
1852 skb->ip_summed = CHECKSUM_UNNECESSARY;
1853
1854 /* remove hardware 2bytes added for IP alignment */
1855 skb_pull(skb, 2);
1856 len -= 2;
1857
1858 if (priv->crc_fwd_en) {
1859 skb_trim(skb, len - ETH_FCS_LEN);
1860 len -= ETH_FCS_LEN;
1861 }
1862
1863 bytes_processed += len;
1864
1865 /*Finish setting up the received SKB and send it to the kernel*/
1866 skb->protocol = eth_type_trans(skb, priv->dev);
1867 ring->packets++;
1868 ring->bytes += len;
1869 if (dma_flag & DMA_RX_MULT)
1870 dev->stats.multicast++;
1871
1872 /* Notify kernel */
1873 napi_gro_receive(&ring->napi, skb);
1874 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1875
1876 next:
1877 rxpktprocessed++;
1878 if (likely(ring->read_ptr < ring->end_ptr))
1879 ring->read_ptr++;
1880 else
1881 ring->read_ptr = ring->cb_ptr;
1882
1883 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK;
1884 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX);
1885 }
1886
1887 ring->dim.bytes = bytes_processed;
1888 ring->dim.packets = rxpktprocessed;
1889
1890 return rxpktprocessed;
1891 }
1892
1893 /* Rx NAPI polling method */
1894 static int bcmgenet_rx_poll(struct napi_struct *napi, int budget)
1895 {
1896 struct bcmgenet_rx_ring *ring = container_of(napi,
1897 struct bcmgenet_rx_ring, napi);
1898 struct net_dim_sample dim_sample;
1899 unsigned int work_done;
1900
1901 work_done = bcmgenet_desc_rx(ring, budget);
1902
1903 if (work_done < budget) {
1904 napi_complete_done(napi, work_done);
1905 ring->int_enable(ring);
1906 }
1907
1908 if (ring->dim.use_dim) {
1909 net_dim_sample(ring->dim.event_ctr, ring->dim.packets,
1910 ring->dim.bytes, &dim_sample);
1911 net_dim(&ring->dim.dim, dim_sample);
1912 }
1913
1914 return work_done;
1915 }
1916
1917 static void bcmgenet_dim_work(struct work_struct *work)
1918 {
1919 struct net_dim *dim = container_of(work, struct net_dim, work);
1920 struct bcmgenet_net_dim *ndim =
1921 container_of(dim, struct bcmgenet_net_dim, dim);
1922 struct bcmgenet_rx_ring *ring =
1923 container_of(ndim, struct bcmgenet_rx_ring, dim);
1924 struct net_dim_cq_moder cur_profile =
1925 net_dim_get_profile(dim->mode, dim->profile_ix);
1926
1927 ring->dim.coal_usecs = cur_profile.usec;
1928 ring->dim.coal_pkts = cur_profile.pkts;
1929
1930 bcmgenet_set_rx_coalesce(ring);
1931 dim->state = NET_DIM_START_MEASURE;
1932 }
1933
1934 /* Assign skb to RX DMA descriptor. */
1935 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv,
1936 struct bcmgenet_rx_ring *ring)
1937 {
1938 struct enet_cb *cb;
1939 struct sk_buff *skb;
1940 int i;
1941
1942 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1943
1944 /* loop here for each buffer needing assign */
1945 for (i = 0; i < ring->size; i++) {
1946 cb = ring->cbs + i;
1947 skb = bcmgenet_rx_refill(priv, cb);
1948 if (skb)
1949 dev_consume_skb_any(skb);
1950 if (!cb->skb)
1951 return -ENOMEM;
1952 }
1953
1954 return 0;
1955 }
1956
1957 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1958 {
1959 struct sk_buff *skb;
1960 struct enet_cb *cb;
1961 int i;
1962
1963 for (i = 0; i < priv->num_rx_bds; i++) {
1964 cb = &priv->rx_cbs[i];
1965
1966 skb = bcmgenet_free_rx_cb(&priv->pdev->dev, cb);
1967 if (skb)
1968 dev_consume_skb_any(skb);
1969 }
1970 }
1971
1972 static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
1973 {
1974 u32 reg;
1975
1976 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1977 if (enable)
1978 reg |= mask;
1979 else
1980 reg &= ~mask;
1981 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1982
1983 /* UniMAC stops on a packet boundary, wait for a full-size packet
1984 * to be processed
1985 */
1986 if (enable == 0)
1987 usleep_range(1000, 2000);
1988 }
1989
1990 static void reset_umac(struct bcmgenet_priv *priv)
1991 {
1992 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1993 bcmgenet_rbuf_ctrl_set(priv, 0);
1994 udelay(10);
1995
1996 /* disable MAC while updating its registers */
1997 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1998
1999 /* issue soft reset with (rg)mii loopback to ensure a stable rxclk */
2000 bcmgenet_umac_writel(priv, CMD_SW_RESET | CMD_LCL_LOOP_EN, UMAC_CMD);
2001 udelay(2);
2002 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
2003 }
2004
2005 static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
2006 {
2007 /* Mask all interrupts.*/
2008 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
2009 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
2010 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
2011 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
2012 }
2013
2014 static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv)
2015 {
2016 u32 int0_enable = 0;
2017
2018 /* Monitor cable plug/unplugged event for internal PHY, external PHY
2019 * and MoCA PHY
2020 */
2021 if (priv->internal_phy) {
2022 int0_enable |= UMAC_IRQ_LINK_EVENT;
2023 } else if (priv->ext_phy) {
2024 int0_enable |= UMAC_IRQ_LINK_EVENT;
2025 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
2026 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
2027 int0_enable |= UMAC_IRQ_LINK_EVENT;
2028 }
2029 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2030 }
2031
2032 static void init_umac(struct bcmgenet_priv *priv)
2033 {
2034 struct device *kdev = &priv->pdev->dev;
2035 u32 reg;
2036 u32 int0_enable = 0;
2037
2038 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
2039
2040 reset_umac(priv);
2041
2042 /* clear tx/rx counter */
2043 bcmgenet_umac_writel(priv,
2044 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
2045 UMAC_MIB_CTRL);
2046 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
2047
2048 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
2049
2050 /* init rx registers, enable ip header optimization */
2051 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
2052 reg |= RBUF_ALIGN_2B;
2053 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
2054
2055 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
2056 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
2057
2058 bcmgenet_intr_disable(priv);
2059
2060 /* Configure backpressure vectors for MoCA */
2061 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
2062 reg = bcmgenet_bp_mc_get(priv);
2063 reg |= BIT(priv->hw_params->bp_in_en_shift);
2064
2065 /* bp_mask: back pressure mask */
2066 if (netif_is_multiqueue(priv->dev))
2067 reg |= priv->hw_params->bp_in_mask;
2068 else
2069 reg &= ~priv->hw_params->bp_in_mask;
2070 bcmgenet_bp_mc_set(priv, reg);
2071 }
2072
2073 /* Enable MDIO interrupts on GENET v3+ */
2074 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
2075 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
2076
2077 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2078
2079 dev_dbg(kdev, "done init umac\n");
2080 }
2081
2082 static void bcmgenet_init_dim(struct bcmgenet_net_dim *dim,
2083 void (*cb)(struct work_struct *work))
2084 {
2085 INIT_WORK(&dim->dim.work, cb);
2086 dim->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2087 dim->event_ctr = 0;
2088 dim->packets = 0;
2089 dim->bytes = 0;
2090 }
2091
2092 /* Initialize a Tx ring along with corresponding hardware registers */
2093 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
2094 unsigned int index, unsigned int size,
2095 unsigned int start_ptr, unsigned int end_ptr)
2096 {
2097 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
2098 u32 words_per_bd = WORDS_PER_BD(priv);
2099 u32 flow_period_val = 0;
2100
2101 spin_lock_init(&ring->lock);
2102 ring->priv = priv;
2103 ring->index = index;
2104 if (index == DESC_INDEX) {
2105 ring->queue = 0;
2106 ring->int_enable = bcmgenet_tx_ring16_int_enable;
2107 ring->int_disable = bcmgenet_tx_ring16_int_disable;
2108 } else {
2109 ring->queue = index + 1;
2110 ring->int_enable = bcmgenet_tx_ring_int_enable;
2111 ring->int_disable = bcmgenet_tx_ring_int_disable;
2112 }
2113 ring->cbs = priv->tx_cbs + start_ptr;
2114 ring->size = size;
2115 ring->clean_ptr = start_ptr;
2116 ring->c_index = 0;
2117 ring->free_bds = size;
2118 ring->write_ptr = start_ptr;
2119 ring->cb_ptr = start_ptr;
2120 ring->end_ptr = end_ptr - 1;
2121 ring->prod_index = 0;
2122
2123 /* Set flow period for ring != 16 */
2124 if (index != DESC_INDEX)
2125 flow_period_val = ENET_MAX_MTU_SIZE << 16;
2126
2127 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
2128 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
2129 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
2130 /* Disable rate control for now */
2131 bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
2132 TDMA_FLOW_PERIOD);
2133 bcmgenet_tdma_ring_writel(priv, index,
2134 ((size << DMA_RING_SIZE_SHIFT) |
2135 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
2136
2137 /* Set start and end address, read and write pointers */
2138 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2139 DMA_START_ADDR);
2140 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2141 TDMA_READ_PTR);
2142 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2143 TDMA_WRITE_PTR);
2144 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
2145 DMA_END_ADDR);
2146
2147 /* Initialize Tx NAPI */
2148 netif_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll,
2149 NAPI_POLL_WEIGHT);
2150 }
2151
2152 /* Initialize a RDMA ring */
2153 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
2154 unsigned int index, unsigned int size,
2155 unsigned int start_ptr, unsigned int end_ptr)
2156 {
2157 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index];
2158 u32 words_per_bd = WORDS_PER_BD(priv);
2159 int ret;
2160
2161 ring->priv = priv;
2162 ring->index = index;
2163 if (index == DESC_INDEX) {
2164 ring->int_enable = bcmgenet_rx_ring16_int_enable;
2165 ring->int_disable = bcmgenet_rx_ring16_int_disable;
2166 } else {
2167 ring->int_enable = bcmgenet_rx_ring_int_enable;
2168 ring->int_disable = bcmgenet_rx_ring_int_disable;
2169 }
2170 ring->cbs = priv->rx_cbs + start_ptr;
2171 ring->size = size;
2172 ring->c_index = 0;
2173 ring->read_ptr = start_ptr;
2174 ring->cb_ptr = start_ptr;
2175 ring->end_ptr = end_ptr - 1;
2176
2177 ret = bcmgenet_alloc_rx_buffers(priv, ring);
2178 if (ret)
2179 return ret;
2180
2181 bcmgenet_init_dim(&ring->dim, bcmgenet_dim_work);
2182
2183 /* Initialize Rx NAPI */
2184 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll,
2185 NAPI_POLL_WEIGHT);
2186
2187 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
2188 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
2189 bcmgenet_rdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
2190 bcmgenet_rdma_ring_writel(priv, index,
2191 ((size << DMA_RING_SIZE_SHIFT) |
2192 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
2193 bcmgenet_rdma_ring_writel(priv, index,
2194 (DMA_FC_THRESH_LO <<
2195 DMA_XOFF_THRESHOLD_SHIFT) |
2196 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
2197
2198 /* Set start and end address, read and write pointers */
2199 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2200 DMA_START_ADDR);
2201 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2202 RDMA_READ_PTR);
2203 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2204 RDMA_WRITE_PTR);
2205 bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
2206 DMA_END_ADDR);
2207
2208 return ret;
2209 }
2210
2211 static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv)
2212 {
2213 unsigned int i;
2214 struct bcmgenet_tx_ring *ring;
2215
2216 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2217 ring = &priv->tx_rings[i];
2218 napi_enable(&ring->napi);
2219 ring->int_enable(ring);
2220 }
2221
2222 ring = &priv->tx_rings[DESC_INDEX];
2223 napi_enable(&ring->napi);
2224 ring->int_enable(ring);
2225 }
2226
2227 static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv)
2228 {
2229 unsigned int i;
2230 struct bcmgenet_tx_ring *ring;
2231
2232 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2233 ring = &priv->tx_rings[i];
2234 napi_disable(&ring->napi);
2235 }
2236
2237 ring = &priv->tx_rings[DESC_INDEX];
2238 napi_disable(&ring->napi);
2239 }
2240
2241 static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv)
2242 {
2243 unsigned int i;
2244 struct bcmgenet_tx_ring *ring;
2245
2246 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2247 ring = &priv->tx_rings[i];
2248 netif_napi_del(&ring->napi);
2249 }
2250
2251 ring = &priv->tx_rings[DESC_INDEX];
2252 netif_napi_del(&ring->napi);
2253 }
2254
2255 /* Initialize Tx queues
2256 *
2257 * Queues 0-3 are priority-based, each one has 32 descriptors,
2258 * with queue 0 being the highest priority queue.
2259 *
2260 * Queue 16 is the default Tx queue with
2261 * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors.
2262 *
2263 * The transmit control block pool is then partitioned as follows:
2264 * - Tx queue 0 uses tx_cbs[0..31]
2265 * - Tx queue 1 uses tx_cbs[32..63]
2266 * - Tx queue 2 uses tx_cbs[64..95]
2267 * - Tx queue 3 uses tx_cbs[96..127]
2268 * - Tx queue 16 uses tx_cbs[128..255]
2269 */
2270 static void bcmgenet_init_tx_queues(struct net_device *dev)
2271 {
2272 struct bcmgenet_priv *priv = netdev_priv(dev);
2273 u32 i, dma_enable;
2274 u32 dma_ctrl, ring_cfg;
2275 u32 dma_priority[3] = {0, 0, 0};
2276
2277 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
2278 dma_enable = dma_ctrl & DMA_EN;
2279 dma_ctrl &= ~DMA_EN;
2280 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2281
2282 dma_ctrl = 0;
2283 ring_cfg = 0;
2284
2285 /* Enable strict priority arbiter mode */
2286 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
2287
2288 /* Initialize Tx priority queues */
2289 for (i = 0; i < priv->hw_params->tx_queues; i++) {
2290 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q,
2291 i * priv->hw_params->tx_bds_per_q,
2292 (i + 1) * priv->hw_params->tx_bds_per_q);
2293 ring_cfg |= (1 << i);
2294 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2295 dma_priority[DMA_PRIO_REG_INDEX(i)] |=
2296 ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i));
2297 }
2298
2299 /* Initialize Tx default queue 16 */
2300 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT,
2301 priv->hw_params->tx_queues *
2302 priv->hw_params->tx_bds_per_q,
2303 TOTAL_DESC);
2304 ring_cfg |= (1 << DESC_INDEX);
2305 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2306 dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |=
2307 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) <<
2308 DMA_PRIO_REG_SHIFT(DESC_INDEX));
2309
2310 /* Set Tx queue priorities */
2311 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
2312 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
2313 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
2314
2315 /* Enable Tx queues */
2316 bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG);
2317
2318 /* Enable Tx DMA */
2319 if (dma_enable)
2320 dma_ctrl |= DMA_EN;
2321 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2322 }
2323
2324 static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv)
2325 {
2326 unsigned int i;
2327 struct bcmgenet_rx_ring *ring;
2328
2329 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2330 ring = &priv->rx_rings[i];
2331 napi_enable(&ring->napi);
2332 ring->int_enable(ring);
2333 }
2334
2335 ring = &priv->rx_rings[DESC_INDEX];
2336 napi_enable(&ring->napi);
2337 ring->int_enable(ring);
2338 }
2339
2340 static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv)
2341 {
2342 unsigned int i;
2343 struct bcmgenet_rx_ring *ring;
2344
2345 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2346 ring = &priv->rx_rings[i];
2347 napi_disable(&ring->napi);
2348 cancel_work_sync(&ring->dim.dim.work);
2349 }
2350
2351 ring = &priv->rx_rings[DESC_INDEX];
2352 napi_disable(&ring->napi);
2353 cancel_work_sync(&ring->dim.dim.work);
2354 }
2355
2356 static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv)
2357 {
2358 unsigned int i;
2359 struct bcmgenet_rx_ring *ring;
2360
2361 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2362 ring = &priv->rx_rings[i];
2363 netif_napi_del(&ring->napi);
2364 }
2365
2366 ring = &priv->rx_rings[DESC_INDEX];
2367 netif_napi_del(&ring->napi);
2368 }
2369
2370 /* Initialize Rx queues
2371 *
2372 * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be
2373 * used to direct traffic to these queues.
2374 *
2375 * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors.
2376 */
2377 static int bcmgenet_init_rx_queues(struct net_device *dev)
2378 {
2379 struct bcmgenet_priv *priv = netdev_priv(dev);
2380 u32 i;
2381 u32 dma_enable;
2382 u32 dma_ctrl;
2383 u32 ring_cfg;
2384 int ret;
2385
2386 dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL);
2387 dma_enable = dma_ctrl & DMA_EN;
2388 dma_ctrl &= ~DMA_EN;
2389 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2390
2391 dma_ctrl = 0;
2392 ring_cfg = 0;
2393
2394 /* Initialize Rx priority queues */
2395 for (i = 0; i < priv->hw_params->rx_queues; i++) {
2396 ret = bcmgenet_init_rx_ring(priv, i,
2397 priv->hw_params->rx_bds_per_q,
2398 i * priv->hw_params->rx_bds_per_q,
2399 (i + 1) *
2400 priv->hw_params->rx_bds_per_q);
2401 if (ret)
2402 return ret;
2403
2404 ring_cfg |= (1 << i);
2405 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2406 }
2407
2408 /* Initialize Rx default queue 16 */
2409 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT,
2410 priv->hw_params->rx_queues *
2411 priv->hw_params->rx_bds_per_q,
2412 TOTAL_DESC);
2413 if (ret)
2414 return ret;
2415
2416 ring_cfg |= (1 << DESC_INDEX);
2417 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2418
2419 /* Enable rings */
2420 bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG);
2421
2422 /* Configure ring as descriptor ring and re-enable DMA if enabled */
2423 if (dma_enable)
2424 dma_ctrl |= DMA_EN;
2425 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2426
2427 return 0;
2428 }
2429
2430 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
2431 {
2432 int ret = 0;
2433 int timeout = 0;
2434 u32 reg;
2435 u32 dma_ctrl;
2436 int i;
2437
2438 /* Disable TDMA to stop add more frames in TX DMA */
2439 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2440 reg &= ~DMA_EN;
2441 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2442
2443 /* Check TDMA status register to confirm TDMA is disabled */
2444 while (timeout++ < DMA_TIMEOUT_VAL) {
2445 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2446 if (reg & DMA_DISABLED)
2447 break;
2448
2449 udelay(1);
2450 }
2451
2452 if (timeout == DMA_TIMEOUT_VAL) {
2453 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
2454 ret = -ETIMEDOUT;
2455 }
2456
2457 /* Wait 10ms for packet drain in both tx and rx dma */
2458 usleep_range(10000, 20000);
2459
2460 /* Disable RDMA */
2461 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2462 reg &= ~DMA_EN;
2463 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2464
2465 timeout = 0;
2466 /* Check RDMA status register to confirm RDMA is disabled */
2467 while (timeout++ < DMA_TIMEOUT_VAL) {
2468 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
2469 if (reg & DMA_DISABLED)
2470 break;
2471
2472 udelay(1);
2473 }
2474
2475 if (timeout == DMA_TIMEOUT_VAL) {
2476 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
2477 ret = -ETIMEDOUT;
2478 }
2479
2480 dma_ctrl = 0;
2481 for (i = 0; i < priv->hw_params->rx_queues; i++)
2482 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2483 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2484 reg &= ~dma_ctrl;
2485 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2486
2487 dma_ctrl = 0;
2488 for (i = 0; i < priv->hw_params->tx_queues; i++)
2489 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2490 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2491 reg &= ~dma_ctrl;
2492 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2493
2494 return ret;
2495 }
2496
2497 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
2498 {
2499 struct netdev_queue *txq;
2500 struct sk_buff *skb;
2501 struct enet_cb *cb;
2502 int i;
2503
2504 bcmgenet_fini_rx_napi(priv);
2505 bcmgenet_fini_tx_napi(priv);
2506
2507 for (i = 0; i < priv->num_tx_bds; i++) {
2508 cb = priv->tx_cbs + i;
2509 skb = bcmgenet_free_tx_cb(&priv->pdev->dev, cb);
2510 if (skb)
2511 dev_kfree_skb(skb);
2512 }
2513
2514 for (i = 0; i < priv->hw_params->tx_queues; i++) {
2515 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[i].queue);
2516 netdev_tx_reset_queue(txq);
2517 }
2518
2519 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[DESC_INDEX].queue);
2520 netdev_tx_reset_queue(txq);
2521
2522 bcmgenet_free_rx_buffers(priv);
2523 kfree(priv->rx_cbs);
2524 kfree(priv->tx_cbs);
2525 }
2526
2527 /* init_edma: Initialize DMA control register */
2528 static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
2529 {
2530 int ret;
2531 unsigned int i;
2532 struct enet_cb *cb;
2533
2534 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
2535
2536 /* Initialize common Rx ring structures */
2537 priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
2538 priv->num_rx_bds = TOTAL_DESC;
2539 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
2540 GFP_KERNEL);
2541 if (!priv->rx_cbs)
2542 return -ENOMEM;
2543
2544 for (i = 0; i < priv->num_rx_bds; i++) {
2545 cb = priv->rx_cbs + i;
2546 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE;
2547 }
2548
2549 /* Initialize common TX ring structures */
2550 priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
2551 priv->num_tx_bds = TOTAL_DESC;
2552 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
2553 GFP_KERNEL);
2554 if (!priv->tx_cbs) {
2555 kfree(priv->rx_cbs);
2556 return -ENOMEM;
2557 }
2558
2559 for (i = 0; i < priv->num_tx_bds; i++) {
2560 cb = priv->tx_cbs + i;
2561 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE;
2562 }
2563
2564 /* Init rDma */
2565 bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2566
2567 /* Initialize Rx queues */
2568 ret = bcmgenet_init_rx_queues(priv->dev);
2569 if (ret) {
2570 netdev_err(priv->dev, "failed to initialize Rx queues\n");
2571 bcmgenet_free_rx_buffers(priv);
2572 kfree(priv->rx_cbs);
2573 kfree(priv->tx_cbs);
2574 return ret;
2575 }
2576
2577 /* Init tDma */
2578 bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2579
2580 /* Initialize Tx queues */
2581 bcmgenet_init_tx_queues(priv->dev);
2582
2583 return 0;
2584 }
2585
2586 /* Interrupt bottom half */
2587 static void bcmgenet_irq_task(struct work_struct *work)
2588 {
2589 unsigned int status;
2590 struct bcmgenet_priv *priv = container_of(
2591 work, struct bcmgenet_priv, bcmgenet_irq_work);
2592
2593 netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
2594
2595 spin_lock_irq(&priv->lock);
2596 status = priv->irq0_stat;
2597 priv->irq0_stat = 0;
2598 spin_unlock_irq(&priv->lock);
2599
2600 /* Link UP/DOWN event */
2601 if (status & UMAC_IRQ_LINK_EVENT) {
2602 priv->dev->phydev->link = !!(status & UMAC_IRQ_LINK_UP);
2603 phy_mac_interrupt(priv->dev->phydev);
2604 }
2605 }
2606
2607 /* bcmgenet_isr1: handle Rx and Tx priority queues */
2608 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
2609 {
2610 struct bcmgenet_priv *priv = dev_id;
2611 struct bcmgenet_rx_ring *rx_ring;
2612 struct bcmgenet_tx_ring *tx_ring;
2613 unsigned int index, status;
2614
2615 /* Read irq status */
2616 status = bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
2617 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
2618
2619 /* clear interrupts */
2620 bcmgenet_intrl2_1_writel(priv, status, INTRL2_CPU_CLEAR);
2621
2622 netif_dbg(priv, intr, priv->dev,
2623 "%s: IRQ=0x%x\n", __func__, status);
2624
2625 /* Check Rx priority queue interrupts */
2626 for (index = 0; index < priv->hw_params->rx_queues; index++) {
2627 if (!(status & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index)))
2628 continue;
2629
2630 rx_ring = &priv->rx_rings[index];
2631 rx_ring->dim.event_ctr++;
2632
2633 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2634 rx_ring->int_disable(rx_ring);
2635 __napi_schedule_irqoff(&rx_ring->napi);
2636 }
2637 }
2638
2639 /* Check Tx priority queue interrupts */
2640 for (index = 0; index < priv->hw_params->tx_queues; index++) {
2641 if (!(status & BIT(index)))
2642 continue;
2643
2644 tx_ring = &priv->tx_rings[index];
2645
2646 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2647 tx_ring->int_disable(tx_ring);
2648 __napi_schedule_irqoff(&tx_ring->napi);
2649 }
2650 }
2651
2652 return IRQ_HANDLED;
2653 }
2654
2655 /* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */
2656 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
2657 {
2658 struct bcmgenet_priv *priv = dev_id;
2659 struct bcmgenet_rx_ring *rx_ring;
2660 struct bcmgenet_tx_ring *tx_ring;
2661 unsigned int status;
2662 unsigned long flags;
2663
2664 /* Read irq status */
2665 status = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
2666 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
2667
2668 /* clear interrupts */
2669 bcmgenet_intrl2_0_writel(priv, status, INTRL2_CPU_CLEAR);
2670
2671 netif_dbg(priv, intr, priv->dev,
2672 "IRQ=0x%x\n", status);
2673
2674 if (status & UMAC_IRQ_RXDMA_DONE) {
2675 rx_ring = &priv->rx_rings[DESC_INDEX];
2676 rx_ring->dim.event_ctr++;
2677
2678 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2679 rx_ring->int_disable(rx_ring);
2680 __napi_schedule_irqoff(&rx_ring->napi);
2681 }
2682 }
2683
2684 if (status & UMAC_IRQ_TXDMA_DONE) {
2685 tx_ring = &priv->tx_rings[DESC_INDEX];
2686
2687 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2688 tx_ring->int_disable(tx_ring);
2689 __napi_schedule_irqoff(&tx_ring->napi);
2690 }
2691 }
2692
2693 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
2694 status & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
2695 wake_up(&priv->wq);
2696 }
2697
2698 /* all other interested interrupts handled in bottom half */
2699 status &= UMAC_IRQ_LINK_EVENT;
2700 if (status) {
2701 /* Save irq status for bottom-half processing. */
2702 spin_lock_irqsave(&priv->lock, flags);
2703 priv->irq0_stat |= status;
2704 spin_unlock_irqrestore(&priv->lock, flags);
2705
2706 schedule_work(&priv->bcmgenet_irq_work);
2707 }
2708
2709 return IRQ_HANDLED;
2710 }
2711
2712 static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
2713 {
2714 struct bcmgenet_priv *priv = dev_id;
2715
2716 pm_wakeup_event(&priv->pdev->dev, 0);
2717
2718 return IRQ_HANDLED;
2719 }
2720
2721 #ifdef CONFIG_NET_POLL_CONTROLLER
2722 static void bcmgenet_poll_controller(struct net_device *dev)
2723 {
2724 struct bcmgenet_priv *priv = netdev_priv(dev);
2725
2726 /* Invoke the main RX/TX interrupt handler */
2727 disable_irq(priv->irq0);
2728 bcmgenet_isr0(priv->irq0, priv);
2729 enable_irq(priv->irq0);
2730
2731 /* And the interrupt handler for RX/TX priority queues */
2732 disable_irq(priv->irq1);
2733 bcmgenet_isr1(priv->irq1, priv);
2734 enable_irq(priv->irq1);
2735 }
2736 #endif
2737
2738 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
2739 {
2740 u32 reg;
2741
2742 reg = bcmgenet_rbuf_ctrl_get(priv);
2743 reg |= BIT(1);
2744 bcmgenet_rbuf_ctrl_set(priv, reg);
2745 udelay(10);
2746
2747 reg &= ~BIT(1);
2748 bcmgenet_rbuf_ctrl_set(priv, reg);
2749 udelay(10);
2750 }
2751
2752 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
2753 unsigned char *addr)
2754 {
2755 bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
2756 (addr[2] << 8) | addr[3], UMAC_MAC0);
2757 bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
2758 }
2759
2760 /* Returns a reusable dma control register value */
2761 static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
2762 {
2763 u32 reg;
2764 u32 dma_ctrl;
2765
2766 /* disable DMA */
2767 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2768 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2769 reg &= ~dma_ctrl;
2770 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2771
2772 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2773 reg &= ~dma_ctrl;
2774 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2775
2776 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
2777 udelay(10);
2778 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
2779
2780 return dma_ctrl;
2781 }
2782
2783 static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
2784 {
2785 u32 reg;
2786
2787 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2788 reg |= dma_ctrl;
2789 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2790
2791 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2792 reg |= dma_ctrl;
2793 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2794 }
2795
2796 /* bcmgenet_hfb_clear
2797 *
2798 * Clear Hardware Filter Block and disable all filtering.
2799 */
2800 static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv)
2801 {
2802 u32 i;
2803
2804 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL);
2805 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS);
2806 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4);
2807
2808 for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++)
2809 bcmgenet_rdma_writel(priv, 0x0, i);
2810
2811 for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++)
2812 bcmgenet_hfb_reg_writel(priv, 0x0,
2813 HFB_FLT_LEN_V3PLUS + i * sizeof(u32));
2814
2815 for (i = 0; i < priv->hw_params->hfb_filter_cnt *
2816 priv->hw_params->hfb_filter_size; i++)
2817 bcmgenet_hfb_writel(priv, 0x0, i * sizeof(u32));
2818 }
2819
2820 static void bcmgenet_hfb_init(struct bcmgenet_priv *priv)
2821 {
2822 if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
2823 return;
2824
2825 bcmgenet_hfb_clear(priv);
2826 }
2827
2828 static void bcmgenet_netif_start(struct net_device *dev)
2829 {
2830 struct bcmgenet_priv *priv = netdev_priv(dev);
2831
2832 /* Start the network engine */
2833 bcmgenet_enable_rx_napi(priv);
2834
2835 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
2836
2837 netif_tx_start_all_queues(dev);
2838 bcmgenet_enable_tx_napi(priv);
2839
2840 /* Monitor link interrupts now */
2841 bcmgenet_link_intr_enable(priv);
2842
2843 phy_start(dev->phydev);
2844 }
2845
2846 static int bcmgenet_open(struct net_device *dev)
2847 {
2848 struct bcmgenet_priv *priv = netdev_priv(dev);
2849 unsigned long dma_ctrl;
2850 u32 reg;
2851 int ret;
2852
2853 netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
2854
2855 /* Turn on the clock */
2856 clk_prepare_enable(priv->clk);
2857
2858 /* If this is an internal GPHY, power it back on now, before UniMAC is
2859 * brought out of reset as absolutely no UniMAC activity is allowed
2860 */
2861 if (priv->internal_phy)
2862 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2863
2864 /* take MAC out of reset */
2865 bcmgenet_umac_reset(priv);
2866
2867 init_umac(priv);
2868
2869 /* Make sure we reflect the value of CRC_CMD_FWD */
2870 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2871 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2872
2873 bcmgenet_set_hw_addr(priv, dev->dev_addr);
2874
2875 if (priv->internal_phy) {
2876 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2877 reg |= EXT_ENERGY_DET_MASK;
2878 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2879 }
2880
2881 /* Disable RX/TX DMA and flush TX queues */
2882 dma_ctrl = bcmgenet_dma_disable(priv);
2883
2884 /* Reinitialize TDMA and RDMA and SW housekeeping */
2885 ret = bcmgenet_init_dma(priv);
2886 if (ret) {
2887 netdev_err(dev, "failed to initialize DMA\n");
2888 goto err_clk_disable;
2889 }
2890
2891 /* Always enable ring 16 - descriptor ring */
2892 bcmgenet_enable_dma(priv, dma_ctrl);
2893
2894 /* HFB init */
2895 bcmgenet_hfb_init(priv);
2896
2897 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
2898 dev->name, priv);
2899 if (ret < 0) {
2900 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2901 goto err_fini_dma;
2902 }
2903
2904 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
2905 dev->name, priv);
2906 if (ret < 0) {
2907 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2908 goto err_irq0;
2909 }
2910
2911 ret = bcmgenet_mii_probe(dev);
2912 if (ret) {
2913 netdev_err(dev, "failed to connect to PHY\n");
2914 goto err_irq1;
2915 }
2916
2917 bcmgenet_netif_start(dev);
2918
2919 return 0;
2920
2921 err_irq1:
2922 free_irq(priv->irq1, priv);
2923 err_irq0:
2924 free_irq(priv->irq0, priv);
2925 err_fini_dma:
2926 bcmgenet_dma_teardown(priv);
2927 bcmgenet_fini_dma(priv);
2928 err_clk_disable:
2929 if (priv->internal_phy)
2930 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
2931 clk_disable_unprepare(priv->clk);
2932 return ret;
2933 }
2934
2935 static void bcmgenet_netif_stop(struct net_device *dev)
2936 {
2937 struct bcmgenet_priv *priv = netdev_priv(dev);
2938
2939 bcmgenet_disable_tx_napi(priv);
2940 netif_tx_stop_all_queues(dev);
2941
2942 /* Disable MAC receive */
2943 umac_enable_set(priv, CMD_RX_EN, false);
2944
2945 bcmgenet_dma_teardown(priv);
2946
2947 /* Disable MAC transmit. TX DMA disabled must be done before this */
2948 umac_enable_set(priv, CMD_TX_EN, false);
2949
2950 phy_stop(dev->phydev);
2951 bcmgenet_disable_rx_napi(priv);
2952 bcmgenet_intr_disable(priv);
2953
2954 /* Wait for pending work items to complete. Since interrupts are
2955 * disabled no new work will be scheduled.
2956 */
2957 cancel_work_sync(&priv->bcmgenet_irq_work);
2958
2959 priv->old_link = -1;
2960 priv->old_speed = -1;
2961 priv->old_duplex = -1;
2962 priv->old_pause = -1;
2963
2964 /* tx reclaim */
2965 bcmgenet_tx_reclaim_all(dev);
2966 bcmgenet_fini_dma(priv);
2967 }
2968
2969 static int bcmgenet_close(struct net_device *dev)
2970 {
2971 struct bcmgenet_priv *priv = netdev_priv(dev);
2972 int ret = 0;
2973
2974 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
2975
2976 bcmgenet_netif_stop(dev);
2977
2978 /* Really kill the PHY state machine and disconnect from it */
2979 phy_disconnect(dev->phydev);
2980
2981 free_irq(priv->irq0, priv);
2982 free_irq(priv->irq1, priv);
2983
2984 if (priv->internal_phy)
2985 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
2986
2987 clk_disable_unprepare(priv->clk);
2988
2989 return ret;
2990 }
2991
2992 static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring)
2993 {
2994 struct bcmgenet_priv *priv = ring->priv;
2995 u32 p_index, c_index, intsts, intmsk;
2996 struct netdev_queue *txq;
2997 unsigned int free_bds;
2998 bool txq_stopped;
2999
3000 if (!netif_msg_tx_err(priv))
3001 return;
3002
3003 txq = netdev_get_tx_queue(priv->dev, ring->queue);
3004
3005 spin_lock(&ring->lock);
3006 if (ring->index == DESC_INDEX) {
3007 intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
3008 intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE;
3009 } else {
3010 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
3011 intmsk = 1 << ring->index;
3012 }
3013 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
3014 p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX);
3015 txq_stopped = netif_tx_queue_stopped(txq);
3016 free_bds = ring->free_bds;
3017 spin_unlock(&ring->lock);
3018
3019 netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n"
3020 "TX queue status: %s, interrupts: %s\n"
3021 "(sw)free_bds: %d (sw)size: %d\n"
3022 "(sw)p_index: %d (hw)p_index: %d\n"
3023 "(sw)c_index: %d (hw)c_index: %d\n"
3024 "(sw)clean_p: %d (sw)write_p: %d\n"
3025 "(sw)cb_ptr: %d (sw)end_ptr: %d\n",
3026 ring->index, ring->queue,
3027 txq_stopped ? "stopped" : "active",
3028 intsts & intmsk ? "enabled" : "disabled",
3029 free_bds, ring->size,
3030 ring->prod_index, p_index & DMA_P_INDEX_MASK,
3031 ring->c_index, c_index & DMA_C_INDEX_MASK,
3032 ring->clean_ptr, ring->write_ptr,
3033 ring->cb_ptr, ring->end_ptr);
3034 }
3035
3036 static void bcmgenet_timeout(struct net_device *dev)
3037 {
3038 struct bcmgenet_priv *priv = netdev_priv(dev);
3039 u32 int0_enable = 0;
3040 u32 int1_enable = 0;
3041 unsigned int q;
3042
3043 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
3044
3045 for (q = 0; q < priv->hw_params->tx_queues; q++)
3046 bcmgenet_dump_tx_queue(&priv->tx_rings[q]);
3047 bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]);
3048
3049 bcmgenet_tx_reclaim_all(dev);
3050
3051 for (q = 0; q < priv->hw_params->tx_queues; q++)
3052 int1_enable |= (1 << q);
3053
3054 int0_enable = UMAC_IRQ_TXDMA_DONE;
3055
3056 /* Re-enable TX interrupts if disabled */
3057 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
3058 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
3059
3060 netif_trans_update(dev);
3061
3062 dev->stats.tx_errors++;
3063
3064 netif_tx_wake_all_queues(dev);
3065 }
3066
3067 #define MAX_MC_COUNT 16
3068
3069 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
3070 unsigned char *addr,
3071 int *i,
3072 int *mc)
3073 {
3074 u32 reg;
3075
3076 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
3077 UMAC_MDF_ADDR + (*i * 4));
3078 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
3079 addr[4] << 8 | addr[5],
3080 UMAC_MDF_ADDR + ((*i + 1) * 4));
3081 reg = bcmgenet_umac_readl(priv, UMAC_MDF_CTRL);
3082 reg |= (1 << (MAX_MC_COUNT - *mc));
3083 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
3084 *i += 2;
3085 (*mc)++;
3086 }
3087
3088 static void bcmgenet_set_rx_mode(struct net_device *dev)
3089 {
3090 struct bcmgenet_priv *priv = netdev_priv(dev);
3091 struct netdev_hw_addr *ha;
3092 int i, mc;
3093 u32 reg;
3094
3095 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
3096
3097 /* Promiscuous mode */
3098 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
3099 if (dev->flags & IFF_PROMISC) {
3100 reg |= CMD_PROMISC;
3101 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3102 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
3103 return;
3104 } else {
3105 reg &= ~CMD_PROMISC;
3106 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3107 }
3108
3109 /* UniMac doesn't support ALLMULTI */
3110 if (dev->flags & IFF_ALLMULTI) {
3111 netdev_warn(dev, "ALLMULTI is not supported\n");
3112 return;
3113 }
3114
3115 /* update MDF filter */
3116 i = 0;
3117 mc = 0;
3118 /* Broadcast */
3119 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i, &mc);
3120 /* my own address.*/
3121 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i, &mc);
3122 /* Unicast list*/
3123 if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc))
3124 return;
3125
3126 if (!netdev_uc_empty(dev))
3127 netdev_for_each_uc_addr(ha, dev)
3128 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
3129 /* Multicast */
3130 if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc))
3131 return;
3132
3133 netdev_for_each_mc_addr(ha, dev)
3134 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
3135 }
3136
3137 /* Set the hardware MAC address. */
3138 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
3139 {
3140 struct sockaddr *addr = p;
3141
3142 /* Setting the MAC address at the hardware level is not possible
3143 * without disabling the UniMAC RX/TX enable bits.
3144 */
3145 if (netif_running(dev))
3146 return -EBUSY;
3147
3148 ether_addr_copy(dev->dev_addr, addr->sa_data);
3149
3150 return 0;
3151 }
3152
3153 static struct net_device_stats *bcmgenet_get_stats(struct net_device *dev)
3154 {
3155 struct bcmgenet_priv *priv = netdev_priv(dev);
3156 unsigned long tx_bytes = 0, tx_packets = 0;
3157 unsigned long rx_bytes = 0, rx_packets = 0;
3158 unsigned long rx_errors = 0, rx_dropped = 0;
3159 struct bcmgenet_tx_ring *tx_ring;
3160 struct bcmgenet_rx_ring *rx_ring;
3161 unsigned int q;
3162
3163 for (q = 0; q < priv->hw_params->tx_queues; q++) {
3164 tx_ring = &priv->tx_rings[q];
3165 tx_bytes += tx_ring->bytes;
3166 tx_packets += tx_ring->packets;
3167 }
3168 tx_ring = &priv->tx_rings[DESC_INDEX];
3169 tx_bytes += tx_ring->bytes;
3170 tx_packets += tx_ring->packets;
3171
3172 for (q = 0; q < priv->hw_params->rx_queues; q++) {
3173 rx_ring = &priv->rx_rings[q];
3174
3175 rx_bytes += rx_ring->bytes;
3176 rx_packets += rx_ring->packets;
3177 rx_errors += rx_ring->errors;
3178 rx_dropped += rx_ring->dropped;
3179 }
3180 rx_ring = &priv->rx_rings[DESC_INDEX];
3181 rx_bytes += rx_ring->bytes;
3182 rx_packets += rx_ring->packets;
3183 rx_errors += rx_ring->errors;
3184 rx_dropped += rx_ring->dropped;
3185
3186 dev->stats.tx_bytes = tx_bytes;
3187 dev->stats.tx_packets = tx_packets;
3188 dev->stats.rx_bytes = rx_bytes;
3189 dev->stats.rx_packets = rx_packets;
3190 dev->stats.rx_errors = rx_errors;
3191 dev->stats.rx_missed_errors = rx_errors;
3192 return &dev->stats;
3193 }
3194
3195 static const struct net_device_ops bcmgenet_netdev_ops = {
3196 .ndo_open = bcmgenet_open,
3197 .ndo_stop = bcmgenet_close,
3198 .ndo_start_xmit = bcmgenet_xmit,
3199 .ndo_tx_timeout = bcmgenet_timeout,
3200 .ndo_set_rx_mode = bcmgenet_set_rx_mode,
3201 .ndo_set_mac_address = bcmgenet_set_mac_addr,
3202 .ndo_do_ioctl = bcmgenet_ioctl,
3203 .ndo_set_features = bcmgenet_set_features,
3204 #ifdef CONFIG_NET_POLL_CONTROLLER
3205 .ndo_poll_controller = bcmgenet_poll_controller,
3206 #endif
3207 .ndo_get_stats = bcmgenet_get_stats,
3208 };
3209
3210 /* Array of GENET hardware parameters/characteristics */
3211 static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
3212 [GENET_V1] = {
3213 .tx_queues = 0,
3214 .tx_bds_per_q = 0,
3215 .rx_queues = 0,
3216 .rx_bds_per_q = 0,
3217 .bp_in_en_shift = 16,
3218 .bp_in_mask = 0xffff,
3219 .hfb_filter_cnt = 16,
3220 .qtag_mask = 0x1F,
3221 .hfb_offset = 0x1000,
3222 .rdma_offset = 0x2000,
3223 .tdma_offset = 0x3000,
3224 .words_per_bd = 2,
3225 },
3226 [GENET_V2] = {
3227 .tx_queues = 4,
3228 .tx_bds_per_q = 32,
3229 .rx_queues = 0,
3230 .rx_bds_per_q = 0,
3231 .bp_in_en_shift = 16,
3232 .bp_in_mask = 0xffff,
3233 .hfb_filter_cnt = 16,
3234 .qtag_mask = 0x1F,
3235 .tbuf_offset = 0x0600,
3236 .hfb_offset = 0x1000,
3237 .hfb_reg_offset = 0x2000,
3238 .rdma_offset = 0x3000,
3239 .tdma_offset = 0x4000,
3240 .words_per_bd = 2,
3241 .flags = GENET_HAS_EXT,
3242 },
3243 [GENET_V3] = {
3244 .tx_queues = 4,
3245 .tx_bds_per_q = 32,
3246 .rx_queues = 0,
3247 .rx_bds_per_q = 0,
3248 .bp_in_en_shift = 17,
3249 .bp_in_mask = 0x1ffff,
3250 .hfb_filter_cnt = 48,
3251 .hfb_filter_size = 128,
3252 .qtag_mask = 0x3F,
3253 .tbuf_offset = 0x0600,
3254 .hfb_offset = 0x8000,
3255 .hfb_reg_offset = 0xfc00,
3256 .rdma_offset = 0x10000,
3257 .tdma_offset = 0x11000,
3258 .words_per_bd = 2,
3259 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR |
3260 GENET_HAS_MOCA_LINK_DET,
3261 },
3262 [GENET_V4] = {
3263 .tx_queues = 4,
3264 .tx_bds_per_q = 32,
3265 .rx_queues = 0,
3266 .rx_bds_per_q = 0,
3267 .bp_in_en_shift = 17,
3268 .bp_in_mask = 0x1ffff,
3269 .hfb_filter_cnt = 48,
3270 .hfb_filter_size = 128,
3271 .qtag_mask = 0x3F,
3272 .tbuf_offset = 0x0600,
3273 .hfb_offset = 0x8000,
3274 .hfb_reg_offset = 0xfc00,
3275 .rdma_offset = 0x2000,
3276 .tdma_offset = 0x4000,
3277 .words_per_bd = 3,
3278 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3279 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3280 },
3281 [GENET_V5] = {
3282 .tx_queues = 4,
3283 .tx_bds_per_q = 32,
3284 .rx_queues = 0,
3285 .rx_bds_per_q = 0,
3286 .bp_in_en_shift = 17,
3287 .bp_in_mask = 0x1ffff,
3288 .hfb_filter_cnt = 48,
3289 .hfb_filter_size = 128,
3290 .qtag_mask = 0x3F,
3291 .tbuf_offset = 0x0600,
3292 .hfb_offset = 0x8000,
3293 .hfb_reg_offset = 0xfc00,
3294 .rdma_offset = 0x2000,
3295 .tdma_offset = 0x4000,
3296 .words_per_bd = 3,
3297 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3298 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3299 },
3300 };
3301
3302 /* Infer hardware parameters from the detected GENET version */
3303 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
3304 {
3305 struct bcmgenet_hw_params *params;
3306 u32 reg;
3307 u8 major;
3308 u16 gphy_rev;
3309
3310 if (GENET_IS_V5(priv) || GENET_IS_V4(priv)) {
3311 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3312 genet_dma_ring_regs = genet_dma_ring_regs_v4;
3313 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3314 } else if (GENET_IS_V3(priv)) {
3315 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3316 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3317 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3318 } else if (GENET_IS_V2(priv)) {
3319 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
3320 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3321 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3322 } else if (GENET_IS_V1(priv)) {
3323 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
3324 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3325 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3326 }
3327
3328 /* enum genet_version starts at 1 */
3329 priv->hw_params = &bcmgenet_hw_params[priv->version];
3330 params = priv->hw_params;
3331
3332 /* Read GENET HW version */
3333 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
3334 major = (reg >> 24 & 0x0f);
3335 if (major == 6)
3336 major = 5;
3337 else if (major == 5)
3338 major = 4;
3339 else if (major == 0)
3340 major = 1;
3341 if (major != priv->version) {
3342 dev_err(&priv->pdev->dev,
3343 "GENET version mismatch, got: %d, configured for: %d\n",
3344 major, priv->version);
3345 }
3346
3347 /* Print the GENET core version */
3348 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
3349 major, (reg >> 16) & 0x0f, reg & 0xffff);
3350
3351 /* Store the integrated PHY revision for the MDIO probing function
3352 * to pass this information to the PHY driver. The PHY driver expects
3353 * to find the PHY major revision in bits 15:8 while the GENET register
3354 * stores that information in bits 7:0, account for that.
3355 *
3356 * On newer chips, starting with PHY revision G0, a new scheme is
3357 * deployed similar to the Starfighter 2 switch with GPHY major
3358 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
3359 * is reserved as well as special value 0x01ff, we have a small
3360 * heuristic to check for the new GPHY revision and re-arrange things
3361 * so the GPHY driver is happy.
3362 */
3363 gphy_rev = reg & 0xffff;
3364
3365 if (GENET_IS_V5(priv)) {
3366 /* The EPHY revision should come from the MDIO registers of
3367 * the PHY not from GENET.
3368 */
3369 if (gphy_rev != 0) {
3370 pr_warn("GENET is reporting EPHY revision: 0x%04x\n",
3371 gphy_rev);
3372 }
3373 /* This is reserved so should require special treatment */
3374 } else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
3375 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
3376 return;
3377 /* This is the good old scheme, just GPHY major, no minor nor patch */
3378 } else if ((gphy_rev & 0xf0) != 0) {
3379 priv->gphy_rev = gphy_rev << 8;
3380 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
3381 } else if ((gphy_rev & 0xff00) != 0) {
3382 priv->gphy_rev = gphy_rev;
3383 }
3384
3385 #ifdef CONFIG_PHYS_ADDR_T_64BIT
3386 if (!(params->flags & GENET_HAS_40BITS))
3387 pr_warn("GENET does not support 40-bits PA\n");
3388 #endif
3389
3390 pr_debug("Configuration for version: %d\n"
3391 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n"
3392 "BP << en: %2d, BP msk: 0x%05x\n"
3393 "HFB count: %2d, QTAQ msk: 0x%05x\n"
3394 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
3395 "RDMA: 0x%05x, TDMA: 0x%05x\n"
3396 "Words/BD: %d\n",
3397 priv->version,
3398 params->tx_queues, params->tx_bds_per_q,
3399 params->rx_queues, params->rx_bds_per_q,
3400 params->bp_in_en_shift, params->bp_in_mask,
3401 params->hfb_filter_cnt, params->qtag_mask,
3402 params->tbuf_offset, params->hfb_offset,
3403 params->hfb_reg_offset,
3404 params->rdma_offset, params->tdma_offset,
3405 params->words_per_bd);
3406 }
3407
3408 static const struct of_device_id bcmgenet_match[] = {
3409 { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
3410 { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
3411 { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
3412 { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
3413 { .compatible = "brcm,genet-v5", .data = (void *)GENET_V5 },
3414 { },
3415 };
3416 MODULE_DEVICE_TABLE(of, bcmgenet_match);
3417
3418 static int bcmgenet_probe(struct platform_device *pdev)
3419 {
3420 struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
3421 struct device_node *dn = pdev->dev.of_node;
3422 const struct of_device_id *of_id = NULL;
3423 struct bcmgenet_priv *priv;
3424 struct net_device *dev;
3425 const void *macaddr;
3426 struct resource *r;
3427 int err = -EIO;
3428 const char *phy_mode_str;
3429
3430 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */
3431 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1,
3432 GENET_MAX_MQ_CNT + 1);
3433 if (!dev) {
3434 dev_err(&pdev->dev, "can't allocate net device\n");
3435 return -ENOMEM;
3436 }
3437
3438 if (dn) {
3439 of_id = of_match_node(bcmgenet_match, dn);
3440 if (!of_id)
3441 return -EINVAL;
3442 }
3443
3444 priv = netdev_priv(dev);
3445 priv->irq0 = platform_get_irq(pdev, 0);
3446 priv->irq1 = platform_get_irq(pdev, 1);
3447 priv->wol_irq = platform_get_irq(pdev, 2);
3448 if (!priv->irq0 || !priv->irq1) {
3449 dev_err(&pdev->dev, "can't find IRQs\n");
3450 err = -EINVAL;
3451 goto err;
3452 }
3453
3454 if (dn) {
3455 macaddr = of_get_mac_address(dn);
3456 if (!macaddr) {
3457 dev_err(&pdev->dev, "can't find MAC address\n");
3458 err = -EINVAL;
3459 goto err;
3460 }
3461 } else {
3462 macaddr = pd->mac_address;
3463 }
3464
3465 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3466 priv->base = devm_ioremap_resource(&pdev->dev, r);
3467 if (IS_ERR(priv->base)) {
3468 err = PTR_ERR(priv->base);
3469 goto err;
3470 }
3471
3472 spin_lock_init(&priv->lock);
3473
3474 SET_NETDEV_DEV(dev, &pdev->dev);
3475 dev_set_drvdata(&pdev->dev, dev);
3476 ether_addr_copy(dev->dev_addr, macaddr);
3477 dev->watchdog_timeo = 2 * HZ;
3478 dev->ethtool_ops = &bcmgenet_ethtool_ops;
3479 dev->netdev_ops = &bcmgenet_netdev_ops;
3480
3481 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
3482
3483 /* Set hardware features */
3484 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
3485 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
3486
3487 /* Request the WOL interrupt and advertise suspend if available */
3488 priv->wol_irq_disabled = true;
3489 err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0,
3490 dev->name, priv);
3491 if (!err)
3492 device_set_wakeup_capable(&pdev->dev, 1);
3493
3494 /* Set the needed headroom to account for any possible
3495 * features enabling/disabling at runtime
3496 */
3497 dev->needed_headroom += 64;
3498
3499 netdev_boot_setup_check(dev);
3500
3501 priv->dev = dev;
3502 priv->pdev = pdev;
3503 if (of_id)
3504 priv->version = (enum bcmgenet_version)of_id->data;
3505 else
3506 priv->version = pd->genet_version;
3507
3508 priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
3509 if (IS_ERR(priv->clk)) {
3510 dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
3511 priv->clk = NULL;
3512 }
3513
3514 clk_prepare_enable(priv->clk);
3515
3516 bcmgenet_set_hw_params(priv);
3517
3518 /* Mii wait queue */
3519 init_waitqueue_head(&priv->wq);
3520 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
3521 priv->rx_buf_len = RX_BUF_LENGTH;
3522 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
3523
3524 priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
3525 if (IS_ERR(priv->clk_wol)) {
3526 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
3527 priv->clk_wol = NULL;
3528 }
3529
3530 priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee");
3531 if (IS_ERR(priv->clk_eee)) {
3532 dev_warn(&priv->pdev->dev, "failed to get enet-eee clock\n");
3533 priv->clk_eee = NULL;
3534 }
3535
3536 /* If this is an internal GPHY, power it on now, before UniMAC is
3537 * brought out of reset as absolutely no UniMAC activity is allowed
3538 */
3539 if (dn && !of_property_read_string(dn, "phy-mode", &phy_mode_str) &&
3540 !strcasecmp(phy_mode_str, "internal"))
3541 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3542
3543 reset_umac(priv);
3544
3545 err = bcmgenet_mii_init(dev);
3546 if (err)
3547 goto err_clk_disable;
3548
3549 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues
3550 * just the ring 16 descriptor based TX
3551 */
3552 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
3553 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
3554
3555 /* libphy will determine the link state */
3556 netif_carrier_off(dev);
3557
3558 /* Turn off the main clock, WOL clock is handled separately */
3559 clk_disable_unprepare(priv->clk);
3560
3561 err = register_netdev(dev);
3562 if (err)
3563 goto err;
3564
3565 return err;
3566
3567 err_clk_disable:
3568 clk_disable_unprepare(priv->clk);
3569 err:
3570 free_netdev(dev);
3571 return err;
3572 }
3573
3574 static int bcmgenet_remove(struct platform_device *pdev)
3575 {
3576 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
3577
3578 dev_set_drvdata(&pdev->dev, NULL);
3579 unregister_netdev(priv->dev);
3580 bcmgenet_mii_exit(priv->dev);
3581 free_netdev(priv->dev);
3582
3583 return 0;
3584 }
3585
3586 #ifdef CONFIG_PM_SLEEP
3587 static int bcmgenet_suspend(struct device *d)
3588 {
3589 struct net_device *dev = dev_get_drvdata(d);
3590 struct bcmgenet_priv *priv = netdev_priv(dev);
3591 int ret = 0;
3592
3593 if (!netif_running(dev))
3594 return 0;
3595
3596 bcmgenet_netif_stop(dev);
3597
3598 if (!device_may_wakeup(d))
3599 phy_suspend(dev->phydev);
3600
3601 netif_device_detach(dev);
3602
3603 /* Prepare the device for Wake-on-LAN and switch to the slow clock */
3604 if (device_may_wakeup(d) && priv->wolopts) {
3605 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
3606 clk_prepare_enable(priv->clk_wol);
3607 } else if (priv->internal_phy) {
3608 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3609 }
3610
3611 /* Turn off the clocks */
3612 clk_disable_unprepare(priv->clk);
3613
3614 return ret;
3615 }
3616
3617 static int bcmgenet_resume(struct device *d)
3618 {
3619 struct net_device *dev = dev_get_drvdata(d);
3620 struct bcmgenet_priv *priv = netdev_priv(dev);
3621 unsigned long dma_ctrl;
3622 int ret;
3623 u32 reg;
3624
3625 if (!netif_running(dev))
3626 return 0;
3627
3628 /* Turn on the clock */
3629 ret = clk_prepare_enable(priv->clk);
3630 if (ret)
3631 return ret;
3632
3633 /* If this is an internal GPHY, power it back on now, before UniMAC is
3634 * brought out of reset as absolutely no UniMAC activity is allowed
3635 */
3636 if (priv->internal_phy)
3637 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3638
3639 bcmgenet_umac_reset(priv);
3640
3641 init_umac(priv);
3642
3643 /* From WOL-enabled suspend, switch to regular clock */
3644 if (priv->wolopts)
3645 clk_disable_unprepare(priv->clk_wol);
3646
3647 phy_init_hw(dev->phydev);
3648
3649 /* Speed settings must be restored */
3650 bcmgenet_mii_config(priv->dev, false);
3651
3652 bcmgenet_set_hw_addr(priv, dev->dev_addr);
3653
3654 if (priv->internal_phy) {
3655 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
3656 reg |= EXT_ENERGY_DET_MASK;
3657 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
3658 }
3659
3660 if (priv->wolopts)
3661 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
3662
3663 /* Disable RX/TX DMA and flush TX queues */
3664 dma_ctrl = bcmgenet_dma_disable(priv);
3665
3666 /* Reinitialize TDMA and RDMA and SW housekeeping */
3667 ret = bcmgenet_init_dma(priv);
3668 if (ret) {
3669 netdev_err(dev, "failed to initialize DMA\n");
3670 goto out_clk_disable;
3671 }
3672
3673 /* Always enable ring 16 - descriptor ring */
3674 bcmgenet_enable_dma(priv, dma_ctrl);
3675
3676 netif_device_attach(dev);
3677
3678 if (!device_may_wakeup(d))
3679 phy_resume(dev->phydev);
3680
3681 if (priv->eee.eee_enabled)
3682 bcmgenet_eee_enable_set(dev, true);
3683
3684 bcmgenet_netif_start(dev);
3685
3686 return 0;
3687
3688 out_clk_disable:
3689 if (priv->internal_phy)
3690 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3691 clk_disable_unprepare(priv->clk);
3692 return ret;
3693 }
3694 #endif /* CONFIG_PM_SLEEP */
3695
3696 static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume);
3697
3698 static struct platform_driver bcmgenet_driver = {
3699 .probe = bcmgenet_probe,
3700 .remove = bcmgenet_remove,
3701 .driver = {
3702 .name = "bcmgenet",
3703 .of_match_table = bcmgenet_match,
3704 .pm = &bcmgenet_pm_ops,
3705 },
3706 };
3707 module_platform_driver(bcmgenet_driver);
3708
3709 MODULE_AUTHOR("Broadcom Corporation");
3710 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
3711 MODULE_ALIAS("platform:bcmgenet");
3712 MODULE_LICENSE("GPL");
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