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net: bcmgenet: Revert "Use stronger register read/writes to assure ordering"
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / broadcom / genet / bcmgenet.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Broadcom GENET (Gigabit Ethernet) controller driver
4 *
5 * Copyright (c) 2014-2020 Broadcom
6 */
7
8 #define pr_fmt(fmt) "bcmgenet: " fmt
9
10 #include <linux/acpi.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/sched.h>
14 #include <linux/types.h>
15 #include <linux/fcntl.h>
16 #include <linux/interrupt.h>
17 #include <linux/string.h>
18 #include <linux/if_ether.h>
19 #include <linux/init.h>
20 #include <linux/errno.h>
21 #include <linux/delay.h>
22 #include <linux/platform_device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/pm.h>
25 #include <linux/clk.h>
26 #include <net/arp.h>
27
28 #include <linux/mii.h>
29 #include <linux/ethtool.h>
30 #include <linux/netdevice.h>
31 #include <linux/inetdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/in.h>
35 #include <linux/ip.h>
36 #include <linux/ipv6.h>
37 #include <linux/phy.h>
38 #include <linux/platform_data/bcmgenet.h>
39
40 #include <asm/unaligned.h>
41
42 #include "bcmgenet.h"
43
44 /* Maximum number of hardware queues, downsized if needed */
45 #define GENET_MAX_MQ_CNT 4
46
47 /* Default highest priority queue for multi queue support */
48 #define GENET_Q0_PRIORITY 0
49
50 #define GENET_Q16_RX_BD_CNT \
51 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q)
52 #define GENET_Q16_TX_BD_CNT \
53 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q)
54
55 #define RX_BUF_LENGTH 2048
56 #define SKB_ALIGNMENT 32
57
58 /* Tx/Rx DMA register offset, skip 256 descriptors */
59 #define WORDS_PER_BD(p) (p->hw_params->words_per_bd)
60 #define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32))
61
62 #define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \
63 TOTAL_DESC * DMA_DESC_SIZE)
64
65 #define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \
66 TOTAL_DESC * DMA_DESC_SIZE)
67
68 /* Forward declarations */
69 static void bcmgenet_set_rx_mode(struct net_device *dev);
70
71 static inline void bcmgenet_writel(u32 value, void __iomem *offset)
72 {
73 /* MIPS chips strapped for BE will automagically configure the
74 * peripheral registers for CPU-native byte order.
75 */
76 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
77 __raw_writel(value, offset);
78 else
79 writel_relaxed(value, offset);
80 }
81
82 static inline u32 bcmgenet_readl(void __iomem *offset)
83 {
84 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
85 return __raw_readl(offset);
86 else
87 return readl_relaxed(offset);
88 }
89
90 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
91 void __iomem *d, u32 value)
92 {
93 bcmgenet_writel(value, d + DMA_DESC_LENGTH_STATUS);
94 }
95
96 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
97 void __iomem *d,
98 dma_addr_t addr)
99 {
100 bcmgenet_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
101
102 /* Register writes to GISB bus can take couple hundred nanoseconds
103 * and are done for each packet, save these expensive writes unless
104 * the platform is explicitly configured for 64-bits/LPAE.
105 */
106 #ifdef CONFIG_PHYS_ADDR_T_64BIT
107 if (priv->hw_params->flags & GENET_HAS_40BITS)
108 bcmgenet_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
109 #endif
110 }
111
112 /* Combined address + length/status setter */
113 static inline void dmadesc_set(struct bcmgenet_priv *priv,
114 void __iomem *d, dma_addr_t addr, u32 val)
115 {
116 dmadesc_set_addr(priv, d, addr);
117 dmadesc_set_length_status(priv, d, val);
118 }
119
120 static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
121 void __iomem *d)
122 {
123 dma_addr_t addr;
124
125 addr = bcmgenet_readl(d + DMA_DESC_ADDRESS_LO);
126
127 /* Register writes to GISB bus can take couple hundred nanoseconds
128 * and are done for each packet, save these expensive writes unless
129 * the platform is explicitly configured for 64-bits/LPAE.
130 */
131 #ifdef CONFIG_PHYS_ADDR_T_64BIT
132 if (priv->hw_params->flags & GENET_HAS_40BITS)
133 addr |= (u64)bcmgenet_readl(d + DMA_DESC_ADDRESS_HI) << 32;
134 #endif
135 return addr;
136 }
137
138 #define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x"
139
140 #define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
141 NETIF_MSG_LINK)
142
143 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
144 {
145 if (GENET_IS_V1(priv))
146 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
147 else
148 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
149 }
150
151 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
152 {
153 if (GENET_IS_V1(priv))
154 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
155 else
156 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
157 }
158
159 /* These macros are defined to deal with register map change
160 * between GENET1.1 and GENET2. Only those currently being used
161 * by driver are defined.
162 */
163 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
164 {
165 if (GENET_IS_V1(priv))
166 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
167 else
168 return bcmgenet_readl(priv->base +
169 priv->hw_params->tbuf_offset + TBUF_CTRL);
170 }
171
172 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
173 {
174 if (GENET_IS_V1(priv))
175 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
176 else
177 bcmgenet_writel(val, priv->base +
178 priv->hw_params->tbuf_offset + TBUF_CTRL);
179 }
180
181 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
182 {
183 if (GENET_IS_V1(priv))
184 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
185 else
186 return bcmgenet_readl(priv->base +
187 priv->hw_params->tbuf_offset + TBUF_BP_MC);
188 }
189
190 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
191 {
192 if (GENET_IS_V1(priv))
193 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
194 else
195 bcmgenet_writel(val, priv->base +
196 priv->hw_params->tbuf_offset + TBUF_BP_MC);
197 }
198
199 /* RX/TX DMA register accessors */
200 enum dma_reg {
201 DMA_RING_CFG = 0,
202 DMA_CTRL,
203 DMA_STATUS,
204 DMA_SCB_BURST_SIZE,
205 DMA_ARB_CTRL,
206 DMA_PRIORITY_0,
207 DMA_PRIORITY_1,
208 DMA_PRIORITY_2,
209 DMA_INDEX2RING_0,
210 DMA_INDEX2RING_1,
211 DMA_INDEX2RING_2,
212 DMA_INDEX2RING_3,
213 DMA_INDEX2RING_4,
214 DMA_INDEX2RING_5,
215 DMA_INDEX2RING_6,
216 DMA_INDEX2RING_7,
217 DMA_RING0_TIMEOUT,
218 DMA_RING1_TIMEOUT,
219 DMA_RING2_TIMEOUT,
220 DMA_RING3_TIMEOUT,
221 DMA_RING4_TIMEOUT,
222 DMA_RING5_TIMEOUT,
223 DMA_RING6_TIMEOUT,
224 DMA_RING7_TIMEOUT,
225 DMA_RING8_TIMEOUT,
226 DMA_RING9_TIMEOUT,
227 DMA_RING10_TIMEOUT,
228 DMA_RING11_TIMEOUT,
229 DMA_RING12_TIMEOUT,
230 DMA_RING13_TIMEOUT,
231 DMA_RING14_TIMEOUT,
232 DMA_RING15_TIMEOUT,
233 DMA_RING16_TIMEOUT,
234 };
235
236 static const u8 bcmgenet_dma_regs_v3plus[] = {
237 [DMA_RING_CFG] = 0x00,
238 [DMA_CTRL] = 0x04,
239 [DMA_STATUS] = 0x08,
240 [DMA_SCB_BURST_SIZE] = 0x0C,
241 [DMA_ARB_CTRL] = 0x2C,
242 [DMA_PRIORITY_0] = 0x30,
243 [DMA_PRIORITY_1] = 0x34,
244 [DMA_PRIORITY_2] = 0x38,
245 [DMA_RING0_TIMEOUT] = 0x2C,
246 [DMA_RING1_TIMEOUT] = 0x30,
247 [DMA_RING2_TIMEOUT] = 0x34,
248 [DMA_RING3_TIMEOUT] = 0x38,
249 [DMA_RING4_TIMEOUT] = 0x3c,
250 [DMA_RING5_TIMEOUT] = 0x40,
251 [DMA_RING6_TIMEOUT] = 0x44,
252 [DMA_RING7_TIMEOUT] = 0x48,
253 [DMA_RING8_TIMEOUT] = 0x4c,
254 [DMA_RING9_TIMEOUT] = 0x50,
255 [DMA_RING10_TIMEOUT] = 0x54,
256 [DMA_RING11_TIMEOUT] = 0x58,
257 [DMA_RING12_TIMEOUT] = 0x5c,
258 [DMA_RING13_TIMEOUT] = 0x60,
259 [DMA_RING14_TIMEOUT] = 0x64,
260 [DMA_RING15_TIMEOUT] = 0x68,
261 [DMA_RING16_TIMEOUT] = 0x6C,
262 [DMA_INDEX2RING_0] = 0x70,
263 [DMA_INDEX2RING_1] = 0x74,
264 [DMA_INDEX2RING_2] = 0x78,
265 [DMA_INDEX2RING_3] = 0x7C,
266 [DMA_INDEX2RING_4] = 0x80,
267 [DMA_INDEX2RING_5] = 0x84,
268 [DMA_INDEX2RING_6] = 0x88,
269 [DMA_INDEX2RING_7] = 0x8C,
270 };
271
272 static const u8 bcmgenet_dma_regs_v2[] = {
273 [DMA_RING_CFG] = 0x00,
274 [DMA_CTRL] = 0x04,
275 [DMA_STATUS] = 0x08,
276 [DMA_SCB_BURST_SIZE] = 0x0C,
277 [DMA_ARB_CTRL] = 0x30,
278 [DMA_PRIORITY_0] = 0x34,
279 [DMA_PRIORITY_1] = 0x38,
280 [DMA_PRIORITY_2] = 0x3C,
281 [DMA_RING0_TIMEOUT] = 0x2C,
282 [DMA_RING1_TIMEOUT] = 0x30,
283 [DMA_RING2_TIMEOUT] = 0x34,
284 [DMA_RING3_TIMEOUT] = 0x38,
285 [DMA_RING4_TIMEOUT] = 0x3c,
286 [DMA_RING5_TIMEOUT] = 0x40,
287 [DMA_RING6_TIMEOUT] = 0x44,
288 [DMA_RING7_TIMEOUT] = 0x48,
289 [DMA_RING8_TIMEOUT] = 0x4c,
290 [DMA_RING9_TIMEOUT] = 0x50,
291 [DMA_RING10_TIMEOUT] = 0x54,
292 [DMA_RING11_TIMEOUT] = 0x58,
293 [DMA_RING12_TIMEOUT] = 0x5c,
294 [DMA_RING13_TIMEOUT] = 0x60,
295 [DMA_RING14_TIMEOUT] = 0x64,
296 [DMA_RING15_TIMEOUT] = 0x68,
297 [DMA_RING16_TIMEOUT] = 0x6C,
298 };
299
300 static const u8 bcmgenet_dma_regs_v1[] = {
301 [DMA_CTRL] = 0x00,
302 [DMA_STATUS] = 0x04,
303 [DMA_SCB_BURST_SIZE] = 0x0C,
304 [DMA_ARB_CTRL] = 0x30,
305 [DMA_PRIORITY_0] = 0x34,
306 [DMA_PRIORITY_1] = 0x38,
307 [DMA_PRIORITY_2] = 0x3C,
308 [DMA_RING0_TIMEOUT] = 0x2C,
309 [DMA_RING1_TIMEOUT] = 0x30,
310 [DMA_RING2_TIMEOUT] = 0x34,
311 [DMA_RING3_TIMEOUT] = 0x38,
312 [DMA_RING4_TIMEOUT] = 0x3c,
313 [DMA_RING5_TIMEOUT] = 0x40,
314 [DMA_RING6_TIMEOUT] = 0x44,
315 [DMA_RING7_TIMEOUT] = 0x48,
316 [DMA_RING8_TIMEOUT] = 0x4c,
317 [DMA_RING9_TIMEOUT] = 0x50,
318 [DMA_RING10_TIMEOUT] = 0x54,
319 [DMA_RING11_TIMEOUT] = 0x58,
320 [DMA_RING12_TIMEOUT] = 0x5c,
321 [DMA_RING13_TIMEOUT] = 0x60,
322 [DMA_RING14_TIMEOUT] = 0x64,
323 [DMA_RING15_TIMEOUT] = 0x68,
324 [DMA_RING16_TIMEOUT] = 0x6C,
325 };
326
327 /* Set at runtime once bcmgenet version is known */
328 static const u8 *bcmgenet_dma_regs;
329
330 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
331 {
332 return netdev_priv(dev_get_drvdata(dev));
333 }
334
335 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
336 enum dma_reg r)
337 {
338 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +
339 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
340 }
341
342 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
343 u32 val, enum dma_reg r)
344 {
345 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +
346 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
347 }
348
349 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
350 enum dma_reg r)
351 {
352 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +
353 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
354 }
355
356 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
357 u32 val, enum dma_reg r)
358 {
359 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +
360 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
361 }
362
363 /* RDMA/TDMA ring registers and accessors
364 * we merge the common fields and just prefix with T/D the registers
365 * having different meaning depending on the direction
366 */
367 enum dma_ring_reg {
368 TDMA_READ_PTR = 0,
369 RDMA_WRITE_PTR = TDMA_READ_PTR,
370 TDMA_READ_PTR_HI,
371 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
372 TDMA_CONS_INDEX,
373 RDMA_PROD_INDEX = TDMA_CONS_INDEX,
374 TDMA_PROD_INDEX,
375 RDMA_CONS_INDEX = TDMA_PROD_INDEX,
376 DMA_RING_BUF_SIZE,
377 DMA_START_ADDR,
378 DMA_START_ADDR_HI,
379 DMA_END_ADDR,
380 DMA_END_ADDR_HI,
381 DMA_MBUF_DONE_THRESH,
382 TDMA_FLOW_PERIOD,
383 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
384 TDMA_WRITE_PTR,
385 RDMA_READ_PTR = TDMA_WRITE_PTR,
386 TDMA_WRITE_PTR_HI,
387 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
388 };
389
390 /* GENET v4 supports 40-bits pointer addressing
391 * for obvious reasons the LO and HI word parts
392 * are contiguous, but this offsets the other
393 * registers.
394 */
395 static const u8 genet_dma_ring_regs_v4[] = {
396 [TDMA_READ_PTR] = 0x00,
397 [TDMA_READ_PTR_HI] = 0x04,
398 [TDMA_CONS_INDEX] = 0x08,
399 [TDMA_PROD_INDEX] = 0x0C,
400 [DMA_RING_BUF_SIZE] = 0x10,
401 [DMA_START_ADDR] = 0x14,
402 [DMA_START_ADDR_HI] = 0x18,
403 [DMA_END_ADDR] = 0x1C,
404 [DMA_END_ADDR_HI] = 0x20,
405 [DMA_MBUF_DONE_THRESH] = 0x24,
406 [TDMA_FLOW_PERIOD] = 0x28,
407 [TDMA_WRITE_PTR] = 0x2C,
408 [TDMA_WRITE_PTR_HI] = 0x30,
409 };
410
411 static const u8 genet_dma_ring_regs_v123[] = {
412 [TDMA_READ_PTR] = 0x00,
413 [TDMA_CONS_INDEX] = 0x04,
414 [TDMA_PROD_INDEX] = 0x08,
415 [DMA_RING_BUF_SIZE] = 0x0C,
416 [DMA_START_ADDR] = 0x10,
417 [DMA_END_ADDR] = 0x14,
418 [DMA_MBUF_DONE_THRESH] = 0x18,
419 [TDMA_FLOW_PERIOD] = 0x1C,
420 [TDMA_WRITE_PTR] = 0x20,
421 };
422
423 /* Set at runtime once GENET version is known */
424 static const u8 *genet_dma_ring_regs;
425
426 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
427 unsigned int ring,
428 enum dma_ring_reg r)
429 {
430 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +
431 (DMA_RING_SIZE * ring) +
432 genet_dma_ring_regs[r]);
433 }
434
435 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
436 unsigned int ring, u32 val,
437 enum dma_ring_reg r)
438 {
439 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +
440 (DMA_RING_SIZE * ring) +
441 genet_dma_ring_regs[r]);
442 }
443
444 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
445 unsigned int ring,
446 enum dma_ring_reg r)
447 {
448 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +
449 (DMA_RING_SIZE * ring) +
450 genet_dma_ring_regs[r]);
451 }
452
453 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
454 unsigned int ring, u32 val,
455 enum dma_ring_reg r)
456 {
457 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +
458 (DMA_RING_SIZE * ring) +
459 genet_dma_ring_regs[r]);
460 }
461
462 static void bcmgenet_hfb_enable_filter(struct bcmgenet_priv *priv, u32 f_index)
463 {
464 u32 offset;
465 u32 reg;
466
467 offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32);
468 reg = bcmgenet_hfb_reg_readl(priv, offset);
469 reg |= (1 << (f_index % 32));
470 bcmgenet_hfb_reg_writel(priv, reg, offset);
471 reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL);
472 reg |= RBUF_HFB_EN;
473 bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL);
474 }
475
476 static void bcmgenet_hfb_disable_filter(struct bcmgenet_priv *priv, u32 f_index)
477 {
478 u32 offset, reg, reg1;
479
480 offset = HFB_FLT_ENABLE_V3PLUS;
481 reg = bcmgenet_hfb_reg_readl(priv, offset);
482 reg1 = bcmgenet_hfb_reg_readl(priv, offset + sizeof(u32));
483 if (f_index < 32) {
484 reg1 &= ~(1 << (f_index % 32));
485 bcmgenet_hfb_reg_writel(priv, reg1, offset + sizeof(u32));
486 } else {
487 reg &= ~(1 << (f_index % 32));
488 bcmgenet_hfb_reg_writel(priv, reg, offset);
489 }
490 if (!reg && !reg1) {
491 reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL);
492 reg &= ~RBUF_HFB_EN;
493 bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL);
494 }
495 }
496
497 static void bcmgenet_hfb_set_filter_rx_queue_mapping(struct bcmgenet_priv *priv,
498 u32 f_index, u32 rx_queue)
499 {
500 u32 offset;
501 u32 reg;
502
503 offset = f_index / 8;
504 reg = bcmgenet_rdma_readl(priv, DMA_INDEX2RING_0 + offset);
505 reg &= ~(0xF << (4 * (f_index % 8)));
506 reg |= ((rx_queue & 0xF) << (4 * (f_index % 8)));
507 bcmgenet_rdma_writel(priv, reg, DMA_INDEX2RING_0 + offset);
508 }
509
510 static void bcmgenet_hfb_set_filter_length(struct bcmgenet_priv *priv,
511 u32 f_index, u32 f_length)
512 {
513 u32 offset;
514 u32 reg;
515
516 offset = HFB_FLT_LEN_V3PLUS +
517 ((priv->hw_params->hfb_filter_cnt - 1 - f_index) / 4) *
518 sizeof(u32);
519 reg = bcmgenet_hfb_reg_readl(priv, offset);
520 reg &= ~(0xFF << (8 * (f_index % 4)));
521 reg |= ((f_length & 0xFF) << (8 * (f_index % 4)));
522 bcmgenet_hfb_reg_writel(priv, reg, offset);
523 }
524
525 static int bcmgenet_hfb_validate_mask(void *mask, size_t size)
526 {
527 while (size) {
528 switch (*(unsigned char *)mask++) {
529 case 0x00:
530 case 0x0f:
531 case 0xf0:
532 case 0xff:
533 size--;
534 continue;
535 default:
536 return -EINVAL;
537 }
538 }
539
540 return 0;
541 }
542
543 #define VALIDATE_MASK(x) \
544 bcmgenet_hfb_validate_mask(&(x), sizeof(x))
545
546 static int bcmgenet_hfb_insert_data(struct bcmgenet_priv *priv, u32 f_index,
547 u32 offset, void *val, void *mask,
548 size_t size)
549 {
550 u32 index, tmp;
551
552 index = f_index * priv->hw_params->hfb_filter_size + offset / 2;
553 tmp = bcmgenet_hfb_readl(priv, index * sizeof(u32));
554
555 while (size--) {
556 if (offset++ & 1) {
557 tmp &= ~0x300FF;
558 tmp |= (*(unsigned char *)val++);
559 switch ((*(unsigned char *)mask++)) {
560 case 0xFF:
561 tmp |= 0x30000;
562 break;
563 case 0xF0:
564 tmp |= 0x20000;
565 break;
566 case 0x0F:
567 tmp |= 0x10000;
568 break;
569 }
570 bcmgenet_hfb_writel(priv, tmp, index++ * sizeof(u32));
571 if (size)
572 tmp = bcmgenet_hfb_readl(priv,
573 index * sizeof(u32));
574 } else {
575 tmp &= ~0xCFF00;
576 tmp |= (*(unsigned char *)val++) << 8;
577 switch ((*(unsigned char *)mask++)) {
578 case 0xFF:
579 tmp |= 0xC0000;
580 break;
581 case 0xF0:
582 tmp |= 0x80000;
583 break;
584 case 0x0F:
585 tmp |= 0x40000;
586 break;
587 }
588 if (!size)
589 bcmgenet_hfb_writel(priv, tmp, index * sizeof(u32));
590 }
591 }
592
593 return 0;
594 }
595
596 static void bcmgenet_hfb_create_rxnfc_filter(struct bcmgenet_priv *priv,
597 struct bcmgenet_rxnfc_rule *rule)
598 {
599 struct ethtool_rx_flow_spec *fs = &rule->fs;
600 u32 offset = 0, f_length = 0, f;
601 u8 val_8, mask_8;
602 __be16 val_16;
603 u16 mask_16;
604 size_t size;
605
606 f = fs->location;
607 if (fs->flow_type & FLOW_MAC_EXT) {
608 bcmgenet_hfb_insert_data(priv, f, 0,
609 &fs->h_ext.h_dest, &fs->m_ext.h_dest,
610 sizeof(fs->h_ext.h_dest));
611 }
612
613 if (fs->flow_type & FLOW_EXT) {
614 if (fs->m_ext.vlan_etype ||
615 fs->m_ext.vlan_tci) {
616 bcmgenet_hfb_insert_data(priv, f, 12,
617 &fs->h_ext.vlan_etype,
618 &fs->m_ext.vlan_etype,
619 sizeof(fs->h_ext.vlan_etype));
620 bcmgenet_hfb_insert_data(priv, f, 14,
621 &fs->h_ext.vlan_tci,
622 &fs->m_ext.vlan_tci,
623 sizeof(fs->h_ext.vlan_tci));
624 offset += VLAN_HLEN;
625 f_length += DIV_ROUND_UP(VLAN_HLEN, 2);
626 }
627 }
628
629 switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
630 case ETHER_FLOW:
631 f_length += DIV_ROUND_UP(ETH_HLEN, 2);
632 bcmgenet_hfb_insert_data(priv, f, 0,
633 &fs->h_u.ether_spec.h_dest,
634 &fs->m_u.ether_spec.h_dest,
635 sizeof(fs->h_u.ether_spec.h_dest));
636 bcmgenet_hfb_insert_data(priv, f, ETH_ALEN,
637 &fs->h_u.ether_spec.h_source,
638 &fs->m_u.ether_spec.h_source,
639 sizeof(fs->h_u.ether_spec.h_source));
640 bcmgenet_hfb_insert_data(priv, f, (2 * ETH_ALEN) + offset,
641 &fs->h_u.ether_spec.h_proto,
642 &fs->m_u.ether_spec.h_proto,
643 sizeof(fs->h_u.ether_spec.h_proto));
644 break;
645 case IP_USER_FLOW:
646 f_length += DIV_ROUND_UP(ETH_HLEN + 20, 2);
647 /* Specify IP Ether Type */
648 val_16 = htons(ETH_P_IP);
649 mask_16 = 0xFFFF;
650 bcmgenet_hfb_insert_data(priv, f, (2 * ETH_ALEN) + offset,
651 &val_16, &mask_16, sizeof(val_16));
652 bcmgenet_hfb_insert_data(priv, f, 15 + offset,
653 &fs->h_u.usr_ip4_spec.tos,
654 &fs->m_u.usr_ip4_spec.tos,
655 sizeof(fs->h_u.usr_ip4_spec.tos));
656 bcmgenet_hfb_insert_data(priv, f, 23 + offset,
657 &fs->h_u.usr_ip4_spec.proto,
658 &fs->m_u.usr_ip4_spec.proto,
659 sizeof(fs->h_u.usr_ip4_spec.proto));
660 bcmgenet_hfb_insert_data(priv, f, 26 + offset,
661 &fs->h_u.usr_ip4_spec.ip4src,
662 &fs->m_u.usr_ip4_spec.ip4src,
663 sizeof(fs->h_u.usr_ip4_spec.ip4src));
664 bcmgenet_hfb_insert_data(priv, f, 30 + offset,
665 &fs->h_u.usr_ip4_spec.ip4dst,
666 &fs->m_u.usr_ip4_spec.ip4dst,
667 sizeof(fs->h_u.usr_ip4_spec.ip4dst));
668 if (!fs->m_u.usr_ip4_spec.l4_4_bytes)
669 break;
670
671 /* Only supports 20 byte IPv4 header */
672 val_8 = 0x45;
673 mask_8 = 0xFF;
674 bcmgenet_hfb_insert_data(priv, f, ETH_HLEN + offset,
675 &val_8, &mask_8,
676 sizeof(val_8));
677 size = sizeof(fs->h_u.usr_ip4_spec.l4_4_bytes);
678 bcmgenet_hfb_insert_data(priv, f,
679 ETH_HLEN + 20 + offset,
680 &fs->h_u.usr_ip4_spec.l4_4_bytes,
681 &fs->m_u.usr_ip4_spec.l4_4_bytes,
682 size);
683 f_length += DIV_ROUND_UP(size, 2);
684 break;
685 }
686
687 bcmgenet_hfb_set_filter_length(priv, f, 2 * f_length);
688 if (!fs->ring_cookie || fs->ring_cookie == RX_CLS_FLOW_WAKE) {
689 /* Ring 0 flows can be handled by the default Descriptor Ring
690 * We'll map them to ring 0, but don't enable the filter
691 */
692 bcmgenet_hfb_set_filter_rx_queue_mapping(priv, f, 0);
693 rule->state = BCMGENET_RXNFC_STATE_DISABLED;
694 } else {
695 /* Other Rx rings are direct mapped here */
696 bcmgenet_hfb_set_filter_rx_queue_mapping(priv, f,
697 fs->ring_cookie);
698 bcmgenet_hfb_enable_filter(priv, f);
699 rule->state = BCMGENET_RXNFC_STATE_ENABLED;
700 }
701 }
702
703 /* bcmgenet_hfb_clear
704 *
705 * Clear Hardware Filter Block and disable all filtering.
706 */
707 static void bcmgenet_hfb_clear_filter(struct bcmgenet_priv *priv, u32 f_index)
708 {
709 u32 base, i;
710
711 base = f_index * priv->hw_params->hfb_filter_size;
712 for (i = 0; i < priv->hw_params->hfb_filter_size; i++)
713 bcmgenet_hfb_writel(priv, 0x0, (base + i) * sizeof(u32));
714 }
715
716 static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv)
717 {
718 u32 i;
719
720 if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
721 return;
722
723 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL);
724 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS);
725 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4);
726
727 for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++)
728 bcmgenet_rdma_writel(priv, 0x0, i);
729
730 for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++)
731 bcmgenet_hfb_reg_writel(priv, 0x0,
732 HFB_FLT_LEN_V3PLUS + i * sizeof(u32));
733
734 for (i = 0; i < priv->hw_params->hfb_filter_cnt; i++)
735 bcmgenet_hfb_clear_filter(priv, i);
736 }
737
738 static void bcmgenet_hfb_init(struct bcmgenet_priv *priv)
739 {
740 int i;
741
742 INIT_LIST_HEAD(&priv->rxnfc_list);
743 if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
744 return;
745
746 for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) {
747 INIT_LIST_HEAD(&priv->rxnfc_rules[i].list);
748 priv->rxnfc_rules[i].state = BCMGENET_RXNFC_STATE_UNUSED;
749 }
750
751 bcmgenet_hfb_clear(priv);
752 }
753
754 static int bcmgenet_begin(struct net_device *dev)
755 {
756 struct bcmgenet_priv *priv = netdev_priv(dev);
757
758 /* Turn on the clock */
759 return clk_prepare_enable(priv->clk);
760 }
761
762 static void bcmgenet_complete(struct net_device *dev)
763 {
764 struct bcmgenet_priv *priv = netdev_priv(dev);
765
766 /* Turn off the clock */
767 clk_disable_unprepare(priv->clk);
768 }
769
770 static int bcmgenet_get_link_ksettings(struct net_device *dev,
771 struct ethtool_link_ksettings *cmd)
772 {
773 if (!netif_running(dev))
774 return -EINVAL;
775
776 if (!dev->phydev)
777 return -ENODEV;
778
779 phy_ethtool_ksettings_get(dev->phydev, cmd);
780
781 return 0;
782 }
783
784 static int bcmgenet_set_link_ksettings(struct net_device *dev,
785 const struct ethtool_link_ksettings *cmd)
786 {
787 if (!netif_running(dev))
788 return -EINVAL;
789
790 if (!dev->phydev)
791 return -ENODEV;
792
793 return phy_ethtool_ksettings_set(dev->phydev, cmd);
794 }
795
796 static int bcmgenet_set_features(struct net_device *dev,
797 netdev_features_t features)
798 {
799 struct bcmgenet_priv *priv = netdev_priv(dev);
800 u32 reg;
801 int ret;
802
803 ret = clk_prepare_enable(priv->clk);
804 if (ret)
805 return ret;
806
807 /* Make sure we reflect the value of CRC_CMD_FWD */
808 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
809 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
810
811 clk_disable_unprepare(priv->clk);
812
813 return ret;
814 }
815
816 static u32 bcmgenet_get_msglevel(struct net_device *dev)
817 {
818 struct bcmgenet_priv *priv = netdev_priv(dev);
819
820 return priv->msg_enable;
821 }
822
823 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
824 {
825 struct bcmgenet_priv *priv = netdev_priv(dev);
826
827 priv->msg_enable = level;
828 }
829
830 static int bcmgenet_get_coalesce(struct net_device *dev,
831 struct ethtool_coalesce *ec,
832 struct kernel_ethtool_coalesce *kernel_coal,
833 struct netlink_ext_ack *extack)
834 {
835 struct bcmgenet_priv *priv = netdev_priv(dev);
836 struct bcmgenet_rx_ring *ring;
837 unsigned int i;
838
839 ec->tx_max_coalesced_frames =
840 bcmgenet_tdma_ring_readl(priv, DESC_INDEX,
841 DMA_MBUF_DONE_THRESH);
842 ec->rx_max_coalesced_frames =
843 bcmgenet_rdma_ring_readl(priv, DESC_INDEX,
844 DMA_MBUF_DONE_THRESH);
845 ec->rx_coalesce_usecs =
846 bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT) * 8192 / 1000;
847
848 for (i = 0; i < priv->hw_params->rx_queues; i++) {
849 ring = &priv->rx_rings[i];
850 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim;
851 }
852 ring = &priv->rx_rings[DESC_INDEX];
853 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim;
854
855 return 0;
856 }
857
858 static void bcmgenet_set_rx_coalesce(struct bcmgenet_rx_ring *ring,
859 u32 usecs, u32 pkts)
860 {
861 struct bcmgenet_priv *priv = ring->priv;
862 unsigned int i = ring->index;
863 u32 reg;
864
865 bcmgenet_rdma_ring_writel(priv, i, pkts, DMA_MBUF_DONE_THRESH);
866
867 reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i);
868 reg &= ~DMA_TIMEOUT_MASK;
869 reg |= DIV_ROUND_UP(usecs * 1000, 8192);
870 bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i);
871 }
872
873 static void bcmgenet_set_ring_rx_coalesce(struct bcmgenet_rx_ring *ring,
874 struct ethtool_coalesce *ec)
875 {
876 struct dim_cq_moder moder;
877 u32 usecs, pkts;
878
879 ring->rx_coalesce_usecs = ec->rx_coalesce_usecs;
880 ring->rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
881 usecs = ring->rx_coalesce_usecs;
882 pkts = ring->rx_max_coalesced_frames;
883
884 if (ec->use_adaptive_rx_coalesce && !ring->dim.use_dim) {
885 moder = net_dim_get_def_rx_moderation(ring->dim.dim.mode);
886 usecs = moder.usec;
887 pkts = moder.pkts;
888 }
889
890 ring->dim.use_dim = ec->use_adaptive_rx_coalesce;
891 bcmgenet_set_rx_coalesce(ring, usecs, pkts);
892 }
893
894 static int bcmgenet_set_coalesce(struct net_device *dev,
895 struct ethtool_coalesce *ec,
896 struct kernel_ethtool_coalesce *kernel_coal,
897 struct netlink_ext_ack *extack)
898 {
899 struct bcmgenet_priv *priv = netdev_priv(dev);
900 unsigned int i;
901
902 /* Base system clock is 125Mhz, DMA timeout is this reference clock
903 * divided by 1024, which yields roughly 8.192us, our maximum value
904 * has to fit in the DMA_TIMEOUT_MASK (16 bits)
905 */
906 if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
907 ec->tx_max_coalesced_frames == 0 ||
908 ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
909 ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1)
910 return -EINVAL;
911
912 if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0)
913 return -EINVAL;
914
915 /* GENET TDMA hardware does not support a configurable timeout, but will
916 * always generate an interrupt either after MBDONE packets have been
917 * transmitted, or when the ring is empty.
918 */
919
920 /* Program all TX queues with the same values, as there is no
921 * ethtool knob to do coalescing on a per-queue basis
922 */
923 for (i = 0; i < priv->hw_params->tx_queues; i++)
924 bcmgenet_tdma_ring_writel(priv, i,
925 ec->tx_max_coalesced_frames,
926 DMA_MBUF_DONE_THRESH);
927 bcmgenet_tdma_ring_writel(priv, DESC_INDEX,
928 ec->tx_max_coalesced_frames,
929 DMA_MBUF_DONE_THRESH);
930
931 for (i = 0; i < priv->hw_params->rx_queues; i++)
932 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[i], ec);
933 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[DESC_INDEX], ec);
934
935 return 0;
936 }
937
938 /* standard ethtool support functions. */
939 enum bcmgenet_stat_type {
940 BCMGENET_STAT_NETDEV = -1,
941 BCMGENET_STAT_MIB_RX,
942 BCMGENET_STAT_MIB_TX,
943 BCMGENET_STAT_RUNT,
944 BCMGENET_STAT_MISC,
945 BCMGENET_STAT_SOFT,
946 };
947
948 struct bcmgenet_stats {
949 char stat_string[ETH_GSTRING_LEN];
950 int stat_sizeof;
951 int stat_offset;
952 enum bcmgenet_stat_type type;
953 /* reg offset from UMAC base for misc counters */
954 u16 reg_offset;
955 };
956
957 #define STAT_NETDEV(m) { \
958 .stat_string = __stringify(m), \
959 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
960 .stat_offset = offsetof(struct net_device_stats, m), \
961 .type = BCMGENET_STAT_NETDEV, \
962 }
963
964 #define STAT_GENET_MIB(str, m, _type) { \
965 .stat_string = str, \
966 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
967 .stat_offset = offsetof(struct bcmgenet_priv, m), \
968 .type = _type, \
969 }
970
971 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
972 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
973 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
974 #define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT)
975
976 #define STAT_GENET_MISC(str, m, offset) { \
977 .stat_string = str, \
978 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
979 .stat_offset = offsetof(struct bcmgenet_priv, m), \
980 .type = BCMGENET_STAT_MISC, \
981 .reg_offset = offset, \
982 }
983
984 #define STAT_GENET_Q(num) \
985 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_packets", \
986 tx_rings[num].packets), \
987 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_bytes", \
988 tx_rings[num].bytes), \
989 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_bytes", \
990 rx_rings[num].bytes), \
991 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_packets", \
992 rx_rings[num].packets), \
993 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_errors", \
994 rx_rings[num].errors), \
995 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_dropped", \
996 rx_rings[num].dropped)
997
998 /* There is a 0xC gap between the end of RX and beginning of TX stats and then
999 * between the end of TX stats and the beginning of the RX RUNT
1000 */
1001 #define BCMGENET_STAT_OFFSET 0xc
1002
1003 /* Hardware counters must be kept in sync because the order/offset
1004 * is important here (order in structure declaration = order in hardware)
1005 */
1006 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
1007 /* general stats */
1008 STAT_NETDEV(rx_packets),
1009 STAT_NETDEV(tx_packets),
1010 STAT_NETDEV(rx_bytes),
1011 STAT_NETDEV(tx_bytes),
1012 STAT_NETDEV(rx_errors),
1013 STAT_NETDEV(tx_errors),
1014 STAT_NETDEV(rx_dropped),
1015 STAT_NETDEV(tx_dropped),
1016 STAT_NETDEV(multicast),
1017 /* UniMAC RSV counters */
1018 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
1019 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
1020 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
1021 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
1022 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
1023 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
1024 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
1025 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
1026 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
1027 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
1028 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
1029 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
1030 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
1031 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
1032 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
1033 STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
1034 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
1035 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
1036 STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
1037 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
1038 STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
1039 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
1040 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
1041 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
1042 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
1043 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
1044 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
1045 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
1046 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
1047 /* UniMAC TSV counters */
1048 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
1049 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
1050 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
1051 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
1052 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
1053 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
1054 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
1055 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
1056 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
1057 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
1058 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
1059 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
1060 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
1061 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
1062 STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
1063 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
1064 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
1065 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
1066 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
1067 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
1068 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
1069 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
1070 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
1071 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
1072 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
1073 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
1074 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
1075 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
1076 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
1077 /* UniMAC RUNT counters */
1078 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
1079 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
1080 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
1081 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
1082 /* Misc UniMAC counters */
1083 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
1084 UMAC_RBUF_OVFL_CNT_V1),
1085 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt,
1086 UMAC_RBUF_ERR_CNT_V1),
1087 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
1088 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
1089 STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed),
1090 STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed),
1091 STAT_GENET_SOFT_MIB("tx_realloc_tsb", mib.tx_realloc_tsb),
1092 STAT_GENET_SOFT_MIB("tx_realloc_tsb_failed",
1093 mib.tx_realloc_tsb_failed),
1094 /* Per TX queues */
1095 STAT_GENET_Q(0),
1096 STAT_GENET_Q(1),
1097 STAT_GENET_Q(2),
1098 STAT_GENET_Q(3),
1099 STAT_GENET_Q(16),
1100 };
1101
1102 #define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats)
1103
1104 static void bcmgenet_get_drvinfo(struct net_device *dev,
1105 struct ethtool_drvinfo *info)
1106 {
1107 strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
1108 }
1109
1110 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
1111 {
1112 switch (string_set) {
1113 case ETH_SS_STATS:
1114 return BCMGENET_STATS_LEN;
1115 default:
1116 return -EOPNOTSUPP;
1117 }
1118 }
1119
1120 static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
1121 u8 *data)
1122 {
1123 int i;
1124
1125 switch (stringset) {
1126 case ETH_SS_STATS:
1127 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
1128 memcpy(data + i * ETH_GSTRING_LEN,
1129 bcmgenet_gstrings_stats[i].stat_string,
1130 ETH_GSTRING_LEN);
1131 }
1132 break;
1133 }
1134 }
1135
1136 static u32 bcmgenet_update_stat_misc(struct bcmgenet_priv *priv, u16 offset)
1137 {
1138 u16 new_offset;
1139 u32 val;
1140
1141 switch (offset) {
1142 case UMAC_RBUF_OVFL_CNT_V1:
1143 if (GENET_IS_V2(priv))
1144 new_offset = RBUF_OVFL_CNT_V2;
1145 else
1146 new_offset = RBUF_OVFL_CNT_V3PLUS;
1147
1148 val = bcmgenet_rbuf_readl(priv, new_offset);
1149 /* clear if overflowed */
1150 if (val == ~0)
1151 bcmgenet_rbuf_writel(priv, 0, new_offset);
1152 break;
1153 case UMAC_RBUF_ERR_CNT_V1:
1154 if (GENET_IS_V2(priv))
1155 new_offset = RBUF_ERR_CNT_V2;
1156 else
1157 new_offset = RBUF_ERR_CNT_V3PLUS;
1158
1159 val = bcmgenet_rbuf_readl(priv, new_offset);
1160 /* clear if overflowed */
1161 if (val == ~0)
1162 bcmgenet_rbuf_writel(priv, 0, new_offset);
1163 break;
1164 default:
1165 val = bcmgenet_umac_readl(priv, offset);
1166 /* clear if overflowed */
1167 if (val == ~0)
1168 bcmgenet_umac_writel(priv, 0, offset);
1169 break;
1170 }
1171
1172 return val;
1173 }
1174
1175 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
1176 {
1177 int i, j = 0;
1178
1179 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
1180 const struct bcmgenet_stats *s;
1181 u8 offset = 0;
1182 u32 val = 0;
1183 char *p;
1184
1185 s = &bcmgenet_gstrings_stats[i];
1186 switch (s->type) {
1187 case BCMGENET_STAT_NETDEV:
1188 case BCMGENET_STAT_SOFT:
1189 continue;
1190 case BCMGENET_STAT_RUNT:
1191 offset += BCMGENET_STAT_OFFSET;
1192 fallthrough;
1193 case BCMGENET_STAT_MIB_TX:
1194 offset += BCMGENET_STAT_OFFSET;
1195 fallthrough;
1196 case BCMGENET_STAT_MIB_RX:
1197 val = bcmgenet_umac_readl(priv,
1198 UMAC_MIB_START + j + offset);
1199 offset = 0; /* Reset Offset */
1200 break;
1201 case BCMGENET_STAT_MISC:
1202 if (GENET_IS_V1(priv)) {
1203 val = bcmgenet_umac_readl(priv, s->reg_offset);
1204 /* clear if overflowed */
1205 if (val == ~0)
1206 bcmgenet_umac_writel(priv, 0,
1207 s->reg_offset);
1208 } else {
1209 val = bcmgenet_update_stat_misc(priv,
1210 s->reg_offset);
1211 }
1212 break;
1213 }
1214
1215 j += s->stat_sizeof;
1216 p = (char *)priv + s->stat_offset;
1217 *(u32 *)p = val;
1218 }
1219 }
1220
1221 static void bcmgenet_get_ethtool_stats(struct net_device *dev,
1222 struct ethtool_stats *stats,
1223 u64 *data)
1224 {
1225 struct bcmgenet_priv *priv = netdev_priv(dev);
1226 int i;
1227
1228 if (netif_running(dev))
1229 bcmgenet_update_mib_counters(priv);
1230
1231 dev->netdev_ops->ndo_get_stats(dev);
1232
1233 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
1234 const struct bcmgenet_stats *s;
1235 char *p;
1236
1237 s = &bcmgenet_gstrings_stats[i];
1238 if (s->type == BCMGENET_STAT_NETDEV)
1239 p = (char *)&dev->stats;
1240 else
1241 p = (char *)priv;
1242 p += s->stat_offset;
1243 if (sizeof(unsigned long) != sizeof(u32) &&
1244 s->stat_sizeof == sizeof(unsigned long))
1245 data[i] = *(unsigned long *)p;
1246 else
1247 data[i] = *(u32 *)p;
1248 }
1249 }
1250
1251 static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable)
1252 {
1253 struct bcmgenet_priv *priv = netdev_priv(dev);
1254 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
1255 u32 reg;
1256
1257 if (enable && !priv->clk_eee_enabled) {
1258 clk_prepare_enable(priv->clk_eee);
1259 priv->clk_eee_enabled = true;
1260 }
1261
1262 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
1263 if (enable)
1264 reg |= EEE_EN;
1265 else
1266 reg &= ~EEE_EN;
1267 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
1268
1269 /* Enable EEE and switch to a 27Mhz clock automatically */
1270 reg = bcmgenet_readl(priv->base + off);
1271 if (enable)
1272 reg |= TBUF_EEE_EN | TBUF_PM_EN;
1273 else
1274 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
1275 bcmgenet_writel(reg, priv->base + off);
1276
1277 /* Do the same for thing for RBUF */
1278 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
1279 if (enable)
1280 reg |= RBUF_EEE_EN | RBUF_PM_EN;
1281 else
1282 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
1283 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
1284
1285 if (!enable && priv->clk_eee_enabled) {
1286 clk_disable_unprepare(priv->clk_eee);
1287 priv->clk_eee_enabled = false;
1288 }
1289
1290 priv->eee.eee_enabled = enable;
1291 priv->eee.eee_active = enable;
1292 }
1293
1294 static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e)
1295 {
1296 struct bcmgenet_priv *priv = netdev_priv(dev);
1297 struct ethtool_eee *p = &priv->eee;
1298
1299 if (GENET_IS_V1(priv))
1300 return -EOPNOTSUPP;
1301
1302 if (!dev->phydev)
1303 return -ENODEV;
1304
1305 e->eee_enabled = p->eee_enabled;
1306 e->eee_active = p->eee_active;
1307 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
1308
1309 return phy_ethtool_get_eee(dev->phydev, e);
1310 }
1311
1312 static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e)
1313 {
1314 struct bcmgenet_priv *priv = netdev_priv(dev);
1315 struct ethtool_eee *p = &priv->eee;
1316 int ret = 0;
1317
1318 if (GENET_IS_V1(priv))
1319 return -EOPNOTSUPP;
1320
1321 if (!dev->phydev)
1322 return -ENODEV;
1323
1324 p->eee_enabled = e->eee_enabled;
1325
1326 if (!p->eee_enabled) {
1327 bcmgenet_eee_enable_set(dev, false);
1328 } else {
1329 ret = phy_init_eee(dev->phydev, 0);
1330 if (ret) {
1331 netif_err(priv, hw, dev, "EEE initialization failed\n");
1332 return ret;
1333 }
1334
1335 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
1336 bcmgenet_eee_enable_set(dev, true);
1337 }
1338
1339 return phy_ethtool_set_eee(dev->phydev, e);
1340 }
1341
1342 static int bcmgenet_validate_flow(struct net_device *dev,
1343 struct ethtool_rxnfc *cmd)
1344 {
1345 struct ethtool_usrip4_spec *l4_mask;
1346 struct ethhdr *eth_mask;
1347
1348 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES) {
1349 netdev_err(dev, "rxnfc: Invalid location (%d)\n",
1350 cmd->fs.location);
1351 return -EINVAL;
1352 }
1353
1354 switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
1355 case IP_USER_FLOW:
1356 l4_mask = &cmd->fs.m_u.usr_ip4_spec;
1357 /* don't allow mask which isn't valid */
1358 if (VALIDATE_MASK(l4_mask->ip4src) ||
1359 VALIDATE_MASK(l4_mask->ip4dst) ||
1360 VALIDATE_MASK(l4_mask->l4_4_bytes) ||
1361 VALIDATE_MASK(l4_mask->proto) ||
1362 VALIDATE_MASK(l4_mask->ip_ver) ||
1363 VALIDATE_MASK(l4_mask->tos)) {
1364 netdev_err(dev, "rxnfc: Unsupported mask\n");
1365 return -EINVAL;
1366 }
1367 break;
1368 case ETHER_FLOW:
1369 eth_mask = &cmd->fs.m_u.ether_spec;
1370 /* don't allow mask which isn't valid */
1371 if (VALIDATE_MASK(eth_mask->h_dest) ||
1372 VALIDATE_MASK(eth_mask->h_source) ||
1373 VALIDATE_MASK(eth_mask->h_proto)) {
1374 netdev_err(dev, "rxnfc: Unsupported mask\n");
1375 return -EINVAL;
1376 }
1377 break;
1378 default:
1379 netdev_err(dev, "rxnfc: Unsupported flow type (0x%x)\n",
1380 cmd->fs.flow_type);
1381 return -EINVAL;
1382 }
1383
1384 if ((cmd->fs.flow_type & FLOW_EXT)) {
1385 /* don't allow mask which isn't valid */
1386 if (VALIDATE_MASK(cmd->fs.m_ext.vlan_etype) ||
1387 VALIDATE_MASK(cmd->fs.m_ext.vlan_tci)) {
1388 netdev_err(dev, "rxnfc: Unsupported mask\n");
1389 return -EINVAL;
1390 }
1391 if (cmd->fs.m_ext.data[0] || cmd->fs.m_ext.data[1]) {
1392 netdev_err(dev, "rxnfc: user-def not supported\n");
1393 return -EINVAL;
1394 }
1395 }
1396
1397 if ((cmd->fs.flow_type & FLOW_MAC_EXT)) {
1398 /* don't allow mask which isn't valid */
1399 if (VALIDATE_MASK(cmd->fs.m_ext.h_dest)) {
1400 netdev_err(dev, "rxnfc: Unsupported mask\n");
1401 return -EINVAL;
1402 }
1403 }
1404
1405 return 0;
1406 }
1407
1408 static int bcmgenet_insert_flow(struct net_device *dev,
1409 struct ethtool_rxnfc *cmd)
1410 {
1411 struct bcmgenet_priv *priv = netdev_priv(dev);
1412 struct bcmgenet_rxnfc_rule *loc_rule;
1413 int err;
1414
1415 if (priv->hw_params->hfb_filter_size < 128) {
1416 netdev_err(dev, "rxnfc: Not supported by this device\n");
1417 return -EINVAL;
1418 }
1419
1420 if (cmd->fs.ring_cookie > priv->hw_params->rx_queues &&
1421 cmd->fs.ring_cookie != RX_CLS_FLOW_WAKE) {
1422 netdev_err(dev, "rxnfc: Unsupported action (%llu)\n",
1423 cmd->fs.ring_cookie);
1424 return -EINVAL;
1425 }
1426
1427 err = bcmgenet_validate_flow(dev, cmd);
1428 if (err)
1429 return err;
1430
1431 loc_rule = &priv->rxnfc_rules[cmd->fs.location];
1432 if (loc_rule->state == BCMGENET_RXNFC_STATE_ENABLED)
1433 bcmgenet_hfb_disable_filter(priv, cmd->fs.location);
1434 if (loc_rule->state != BCMGENET_RXNFC_STATE_UNUSED) {
1435 list_del(&loc_rule->list);
1436 bcmgenet_hfb_clear_filter(priv, cmd->fs.location);
1437 }
1438 loc_rule->state = BCMGENET_RXNFC_STATE_UNUSED;
1439 memcpy(&loc_rule->fs, &cmd->fs,
1440 sizeof(struct ethtool_rx_flow_spec));
1441
1442 bcmgenet_hfb_create_rxnfc_filter(priv, loc_rule);
1443
1444 list_add_tail(&loc_rule->list, &priv->rxnfc_list);
1445
1446 return 0;
1447 }
1448
1449 static int bcmgenet_delete_flow(struct net_device *dev,
1450 struct ethtool_rxnfc *cmd)
1451 {
1452 struct bcmgenet_priv *priv = netdev_priv(dev);
1453 struct bcmgenet_rxnfc_rule *rule;
1454 int err = 0;
1455
1456 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES)
1457 return -EINVAL;
1458
1459 rule = &priv->rxnfc_rules[cmd->fs.location];
1460 if (rule->state == BCMGENET_RXNFC_STATE_UNUSED) {
1461 err = -ENOENT;
1462 goto out;
1463 }
1464
1465 if (rule->state == BCMGENET_RXNFC_STATE_ENABLED)
1466 bcmgenet_hfb_disable_filter(priv, cmd->fs.location);
1467 if (rule->state != BCMGENET_RXNFC_STATE_UNUSED) {
1468 list_del(&rule->list);
1469 bcmgenet_hfb_clear_filter(priv, cmd->fs.location);
1470 }
1471 rule->state = BCMGENET_RXNFC_STATE_UNUSED;
1472 memset(&rule->fs, 0, sizeof(struct ethtool_rx_flow_spec));
1473
1474 out:
1475 return err;
1476 }
1477
1478 static int bcmgenet_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1479 {
1480 struct bcmgenet_priv *priv = netdev_priv(dev);
1481 int err = 0;
1482
1483 switch (cmd->cmd) {
1484 case ETHTOOL_SRXCLSRLINS:
1485 err = bcmgenet_insert_flow(dev, cmd);
1486 break;
1487 case ETHTOOL_SRXCLSRLDEL:
1488 err = bcmgenet_delete_flow(dev, cmd);
1489 break;
1490 default:
1491 netdev_warn(priv->dev, "Unsupported ethtool command. (%d)\n",
1492 cmd->cmd);
1493 return -EINVAL;
1494 }
1495
1496 return err;
1497 }
1498
1499 static int bcmgenet_get_flow(struct net_device *dev, struct ethtool_rxnfc *cmd,
1500 int loc)
1501 {
1502 struct bcmgenet_priv *priv = netdev_priv(dev);
1503 struct bcmgenet_rxnfc_rule *rule;
1504 int err = 0;
1505
1506 if (loc < 0 || loc >= MAX_NUM_OF_FS_RULES)
1507 return -EINVAL;
1508
1509 rule = &priv->rxnfc_rules[loc];
1510 if (rule->state == BCMGENET_RXNFC_STATE_UNUSED)
1511 err = -ENOENT;
1512 else
1513 memcpy(&cmd->fs, &rule->fs,
1514 sizeof(struct ethtool_rx_flow_spec));
1515
1516 return err;
1517 }
1518
1519 static int bcmgenet_get_num_flows(struct bcmgenet_priv *priv)
1520 {
1521 struct list_head *pos;
1522 int res = 0;
1523
1524 list_for_each(pos, &priv->rxnfc_list)
1525 res++;
1526
1527 return res;
1528 }
1529
1530 static int bcmgenet_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
1531 u32 *rule_locs)
1532 {
1533 struct bcmgenet_priv *priv = netdev_priv(dev);
1534 struct bcmgenet_rxnfc_rule *rule;
1535 int err = 0;
1536 int i = 0;
1537
1538 switch (cmd->cmd) {
1539 case ETHTOOL_GRXRINGS:
1540 cmd->data = priv->hw_params->rx_queues ?: 1;
1541 break;
1542 case ETHTOOL_GRXCLSRLCNT:
1543 cmd->rule_cnt = bcmgenet_get_num_flows(priv);
1544 cmd->data = MAX_NUM_OF_FS_RULES;
1545 break;
1546 case ETHTOOL_GRXCLSRULE:
1547 err = bcmgenet_get_flow(dev, cmd, cmd->fs.location);
1548 break;
1549 case ETHTOOL_GRXCLSRLALL:
1550 list_for_each_entry(rule, &priv->rxnfc_list, list)
1551 if (i < cmd->rule_cnt)
1552 rule_locs[i++] = rule->fs.location;
1553 cmd->rule_cnt = i;
1554 cmd->data = MAX_NUM_OF_FS_RULES;
1555 break;
1556 default:
1557 err = -EOPNOTSUPP;
1558 break;
1559 }
1560
1561 return err;
1562 }
1563
1564 /* standard ethtool support functions. */
1565 static const struct ethtool_ops bcmgenet_ethtool_ops = {
1566 .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS |
1567 ETHTOOL_COALESCE_MAX_FRAMES |
1568 ETHTOOL_COALESCE_USE_ADAPTIVE_RX,
1569 .begin = bcmgenet_begin,
1570 .complete = bcmgenet_complete,
1571 .get_strings = bcmgenet_get_strings,
1572 .get_sset_count = bcmgenet_get_sset_count,
1573 .get_ethtool_stats = bcmgenet_get_ethtool_stats,
1574 .get_drvinfo = bcmgenet_get_drvinfo,
1575 .get_link = ethtool_op_get_link,
1576 .get_msglevel = bcmgenet_get_msglevel,
1577 .set_msglevel = bcmgenet_set_msglevel,
1578 .get_wol = bcmgenet_get_wol,
1579 .set_wol = bcmgenet_set_wol,
1580 .get_eee = bcmgenet_get_eee,
1581 .set_eee = bcmgenet_set_eee,
1582 .nway_reset = phy_ethtool_nway_reset,
1583 .get_coalesce = bcmgenet_get_coalesce,
1584 .set_coalesce = bcmgenet_set_coalesce,
1585 .get_link_ksettings = bcmgenet_get_link_ksettings,
1586 .set_link_ksettings = bcmgenet_set_link_ksettings,
1587 .get_ts_info = ethtool_op_get_ts_info,
1588 .get_rxnfc = bcmgenet_get_rxnfc,
1589 .set_rxnfc = bcmgenet_set_rxnfc,
1590 };
1591
1592 /* Power down the unimac, based on mode. */
1593 static int bcmgenet_power_down(struct bcmgenet_priv *priv,
1594 enum bcmgenet_power_mode mode)
1595 {
1596 int ret = 0;
1597 u32 reg;
1598
1599 switch (mode) {
1600 case GENET_POWER_CABLE_SENSE:
1601 phy_detach(priv->dev->phydev);
1602 break;
1603
1604 case GENET_POWER_WOL_MAGIC:
1605 ret = bcmgenet_wol_power_down_cfg(priv, mode);
1606 break;
1607
1608 case GENET_POWER_PASSIVE:
1609 /* Power down LED */
1610 if (priv->hw_params->flags & GENET_HAS_EXT) {
1611 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1612 if (GENET_IS_V5(priv))
1613 reg |= EXT_PWR_DOWN_PHY_EN |
1614 EXT_PWR_DOWN_PHY_RD |
1615 EXT_PWR_DOWN_PHY_SD |
1616 EXT_PWR_DOWN_PHY_RX |
1617 EXT_PWR_DOWN_PHY_TX |
1618 EXT_IDDQ_GLBL_PWR;
1619 else
1620 reg |= EXT_PWR_DOWN_PHY;
1621
1622 reg |= (EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
1623 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1624
1625 bcmgenet_phy_power_set(priv->dev, false);
1626 }
1627 break;
1628 default:
1629 break;
1630 }
1631
1632 return ret;
1633 }
1634
1635 static void bcmgenet_power_up(struct bcmgenet_priv *priv,
1636 enum bcmgenet_power_mode mode)
1637 {
1638 u32 reg;
1639
1640 if (!(priv->hw_params->flags & GENET_HAS_EXT))
1641 return;
1642
1643 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1644
1645 switch (mode) {
1646 case GENET_POWER_PASSIVE:
1647 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS |
1648 EXT_ENERGY_DET_MASK);
1649 if (GENET_IS_V5(priv)) {
1650 reg &= ~(EXT_PWR_DOWN_PHY_EN |
1651 EXT_PWR_DOWN_PHY_RD |
1652 EXT_PWR_DOWN_PHY_SD |
1653 EXT_PWR_DOWN_PHY_RX |
1654 EXT_PWR_DOWN_PHY_TX |
1655 EXT_IDDQ_GLBL_PWR);
1656 reg |= EXT_PHY_RESET;
1657 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1658 mdelay(1);
1659
1660 reg &= ~EXT_PHY_RESET;
1661 } else {
1662 reg &= ~EXT_PWR_DOWN_PHY;
1663 reg |= EXT_PWR_DN_EN_LD;
1664 }
1665 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1666 bcmgenet_phy_power_set(priv->dev, true);
1667 break;
1668
1669 case GENET_POWER_CABLE_SENSE:
1670 /* enable APD */
1671 if (!GENET_IS_V5(priv)) {
1672 reg |= EXT_PWR_DN_EN_LD;
1673 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1674 }
1675 break;
1676 case GENET_POWER_WOL_MAGIC:
1677 bcmgenet_wol_power_up_cfg(priv, mode);
1678 return;
1679 default:
1680 break;
1681 }
1682 }
1683
1684 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
1685 struct bcmgenet_tx_ring *ring)
1686 {
1687 struct enet_cb *tx_cb_ptr;
1688
1689 tx_cb_ptr = ring->cbs;
1690 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1691
1692 /* Advancing local write pointer */
1693 if (ring->write_ptr == ring->end_ptr)
1694 ring->write_ptr = ring->cb_ptr;
1695 else
1696 ring->write_ptr++;
1697
1698 return tx_cb_ptr;
1699 }
1700
1701 static struct enet_cb *bcmgenet_put_txcb(struct bcmgenet_priv *priv,
1702 struct bcmgenet_tx_ring *ring)
1703 {
1704 struct enet_cb *tx_cb_ptr;
1705
1706 tx_cb_ptr = ring->cbs;
1707 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1708
1709 /* Rewinding local write pointer */
1710 if (ring->write_ptr == ring->cb_ptr)
1711 ring->write_ptr = ring->end_ptr;
1712 else
1713 ring->write_ptr--;
1714
1715 return tx_cb_ptr;
1716 }
1717
1718 static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring)
1719 {
1720 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1721 INTRL2_CPU_MASK_SET);
1722 }
1723
1724 static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring)
1725 {
1726 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1727 INTRL2_CPU_MASK_CLEAR);
1728 }
1729
1730 static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring)
1731 {
1732 bcmgenet_intrl2_1_writel(ring->priv,
1733 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1734 INTRL2_CPU_MASK_SET);
1735 }
1736
1737 static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring)
1738 {
1739 bcmgenet_intrl2_1_writel(ring->priv,
1740 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1741 INTRL2_CPU_MASK_CLEAR);
1742 }
1743
1744 static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring)
1745 {
1746 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1747 INTRL2_CPU_MASK_SET);
1748 }
1749
1750 static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring)
1751 {
1752 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1753 INTRL2_CPU_MASK_CLEAR);
1754 }
1755
1756 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring)
1757 {
1758 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1759 INTRL2_CPU_MASK_CLEAR);
1760 }
1761
1762 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring)
1763 {
1764 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1765 INTRL2_CPU_MASK_SET);
1766 }
1767
1768 /* Simple helper to free a transmit control block's resources
1769 * Returns an skb when the last transmit control block associated with the
1770 * skb is freed. The skb should be freed by the caller if necessary.
1771 */
1772 static struct sk_buff *bcmgenet_free_tx_cb(struct device *dev,
1773 struct enet_cb *cb)
1774 {
1775 struct sk_buff *skb;
1776
1777 skb = cb->skb;
1778
1779 if (skb) {
1780 cb->skb = NULL;
1781 if (cb == GENET_CB(skb)->first_cb)
1782 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr),
1783 dma_unmap_len(cb, dma_len),
1784 DMA_TO_DEVICE);
1785 else
1786 dma_unmap_page(dev, dma_unmap_addr(cb, dma_addr),
1787 dma_unmap_len(cb, dma_len),
1788 DMA_TO_DEVICE);
1789 dma_unmap_addr_set(cb, dma_addr, 0);
1790
1791 if (cb == GENET_CB(skb)->last_cb)
1792 return skb;
1793
1794 } else if (dma_unmap_addr(cb, dma_addr)) {
1795 dma_unmap_page(dev,
1796 dma_unmap_addr(cb, dma_addr),
1797 dma_unmap_len(cb, dma_len),
1798 DMA_TO_DEVICE);
1799 dma_unmap_addr_set(cb, dma_addr, 0);
1800 }
1801
1802 return NULL;
1803 }
1804
1805 /* Simple helper to free a receive control block's resources */
1806 static struct sk_buff *bcmgenet_free_rx_cb(struct device *dev,
1807 struct enet_cb *cb)
1808 {
1809 struct sk_buff *skb;
1810
1811 skb = cb->skb;
1812 cb->skb = NULL;
1813
1814 if (dma_unmap_addr(cb, dma_addr)) {
1815 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr),
1816 dma_unmap_len(cb, dma_len), DMA_FROM_DEVICE);
1817 dma_unmap_addr_set(cb, dma_addr, 0);
1818 }
1819
1820 return skb;
1821 }
1822
1823 /* Unlocked version of the reclaim routine */
1824 static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev,
1825 struct bcmgenet_tx_ring *ring)
1826 {
1827 struct bcmgenet_priv *priv = netdev_priv(dev);
1828 unsigned int txbds_processed = 0;
1829 unsigned int bytes_compl = 0;
1830 unsigned int pkts_compl = 0;
1831 unsigned int txbds_ready;
1832 unsigned int c_index;
1833 struct sk_buff *skb;
1834
1835 /* Clear status before servicing to reduce spurious interrupts */
1836 if (ring->index == DESC_INDEX)
1837 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_TXDMA_DONE,
1838 INTRL2_CPU_CLEAR);
1839 else
1840 bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
1841 INTRL2_CPU_CLEAR);
1842
1843 /* Compute how many buffers are transmitted since last xmit call */
1844 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX)
1845 & DMA_C_INDEX_MASK;
1846 txbds_ready = (c_index - ring->c_index) & DMA_C_INDEX_MASK;
1847
1848 netif_dbg(priv, tx_done, dev,
1849 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
1850 __func__, ring->index, ring->c_index, c_index, txbds_ready);
1851
1852 /* Reclaim transmitted buffers */
1853 while (txbds_processed < txbds_ready) {
1854 skb = bcmgenet_free_tx_cb(&priv->pdev->dev,
1855 &priv->tx_cbs[ring->clean_ptr]);
1856 if (skb) {
1857 pkts_compl++;
1858 bytes_compl += GENET_CB(skb)->bytes_sent;
1859 dev_consume_skb_any(skb);
1860 }
1861
1862 txbds_processed++;
1863 if (likely(ring->clean_ptr < ring->end_ptr))
1864 ring->clean_ptr++;
1865 else
1866 ring->clean_ptr = ring->cb_ptr;
1867 }
1868
1869 ring->free_bds += txbds_processed;
1870 ring->c_index = c_index;
1871
1872 ring->packets += pkts_compl;
1873 ring->bytes += bytes_compl;
1874
1875 netdev_tx_completed_queue(netdev_get_tx_queue(dev, ring->queue),
1876 pkts_compl, bytes_compl);
1877
1878 return txbds_processed;
1879 }
1880
1881 static unsigned int bcmgenet_tx_reclaim(struct net_device *dev,
1882 struct bcmgenet_tx_ring *ring)
1883 {
1884 unsigned int released;
1885
1886 spin_lock_bh(&ring->lock);
1887 released = __bcmgenet_tx_reclaim(dev, ring);
1888 spin_unlock_bh(&ring->lock);
1889
1890 return released;
1891 }
1892
1893 static int bcmgenet_tx_poll(struct napi_struct *napi, int budget)
1894 {
1895 struct bcmgenet_tx_ring *ring =
1896 container_of(napi, struct bcmgenet_tx_ring, napi);
1897 unsigned int work_done = 0;
1898 struct netdev_queue *txq;
1899
1900 spin_lock(&ring->lock);
1901 work_done = __bcmgenet_tx_reclaim(ring->priv->dev, ring);
1902 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
1903 txq = netdev_get_tx_queue(ring->priv->dev, ring->queue);
1904 netif_tx_wake_queue(txq);
1905 }
1906 spin_unlock(&ring->lock);
1907
1908 if (work_done == 0) {
1909 napi_complete(napi);
1910 ring->int_enable(ring);
1911
1912 return 0;
1913 }
1914
1915 return budget;
1916 }
1917
1918 static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1919 {
1920 struct bcmgenet_priv *priv = netdev_priv(dev);
1921 int i;
1922
1923 if (netif_is_multiqueue(dev)) {
1924 for (i = 0; i < priv->hw_params->tx_queues; i++)
1925 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
1926 }
1927
1928 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
1929 }
1930
1931 /* Reallocate the SKB to put enough headroom in front of it and insert
1932 * the transmit checksum offsets in the descriptors
1933 */
1934 static struct sk_buff *bcmgenet_add_tsb(struct net_device *dev,
1935 struct sk_buff *skb)
1936 {
1937 struct bcmgenet_priv *priv = netdev_priv(dev);
1938 struct status_64 *status = NULL;
1939 struct sk_buff *new_skb;
1940 u16 offset;
1941 u8 ip_proto;
1942 __be16 ip_ver;
1943 u32 tx_csum_info;
1944
1945 if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1946 /* If 64 byte status block enabled, must make sure skb has
1947 * enough headroom for us to insert 64B status block.
1948 */
1949 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1950 if (!new_skb) {
1951 dev_kfree_skb_any(skb);
1952 priv->mib.tx_realloc_tsb_failed++;
1953 dev->stats.tx_dropped++;
1954 return NULL;
1955 }
1956 dev_consume_skb_any(skb);
1957 skb = new_skb;
1958 priv->mib.tx_realloc_tsb++;
1959 }
1960
1961 skb_push(skb, sizeof(*status));
1962 status = (struct status_64 *)skb->data;
1963
1964 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1965 ip_ver = skb->protocol;
1966 switch (ip_ver) {
1967 case htons(ETH_P_IP):
1968 ip_proto = ip_hdr(skb)->protocol;
1969 break;
1970 case htons(ETH_P_IPV6):
1971 ip_proto = ipv6_hdr(skb)->nexthdr;
1972 break;
1973 default:
1974 /* don't use UDP flag */
1975 ip_proto = 0;
1976 break;
1977 }
1978
1979 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1980 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1981 (offset + skb->csum_offset) |
1982 STATUS_TX_CSUM_LV;
1983
1984 /* Set the special UDP flag for UDP */
1985 if (ip_proto == IPPROTO_UDP)
1986 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
1987
1988 status->tx_csum_info = tx_csum_info;
1989 }
1990
1991 return skb;
1992 }
1993
1994 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1995 {
1996 struct bcmgenet_priv *priv = netdev_priv(dev);
1997 struct device *kdev = &priv->pdev->dev;
1998 struct bcmgenet_tx_ring *ring = NULL;
1999 struct enet_cb *tx_cb_ptr;
2000 struct netdev_queue *txq;
2001 int nr_frags, index;
2002 dma_addr_t mapping;
2003 unsigned int size;
2004 skb_frag_t *frag;
2005 u32 len_stat;
2006 int ret;
2007 int i;
2008
2009 index = skb_get_queue_mapping(skb);
2010 /* Mapping strategy:
2011 * queue_mapping = 0, unclassified, packet xmited through ring16
2012 * queue_mapping = 1, goes to ring 0. (highest priority queue
2013 * queue_mapping = 2, goes to ring 1.
2014 * queue_mapping = 3, goes to ring 2.
2015 * queue_mapping = 4, goes to ring 3.
2016 */
2017 if (index == 0)
2018 index = DESC_INDEX;
2019 else
2020 index -= 1;
2021
2022 ring = &priv->tx_rings[index];
2023 txq = netdev_get_tx_queue(dev, ring->queue);
2024
2025 nr_frags = skb_shinfo(skb)->nr_frags;
2026
2027 spin_lock(&ring->lock);
2028 if (ring->free_bds <= (nr_frags + 1)) {
2029 if (!netif_tx_queue_stopped(txq)) {
2030 netif_tx_stop_queue(txq);
2031 netdev_err(dev,
2032 "%s: tx ring %d full when queue %d awake\n",
2033 __func__, index, ring->queue);
2034 }
2035 ret = NETDEV_TX_BUSY;
2036 goto out;
2037 }
2038
2039 /* Retain how many bytes will be sent on the wire, without TSB inserted
2040 * by transmit checksum offload
2041 */
2042 GENET_CB(skb)->bytes_sent = skb->len;
2043
2044 /* add the Transmit Status Block */
2045 skb = bcmgenet_add_tsb(dev, skb);
2046 if (!skb) {
2047 ret = NETDEV_TX_OK;
2048 goto out;
2049 }
2050
2051 for (i = 0; i <= nr_frags; i++) {
2052 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
2053
2054 BUG_ON(!tx_cb_ptr);
2055
2056 if (!i) {
2057 /* Transmit single SKB or head of fragment list */
2058 GENET_CB(skb)->first_cb = tx_cb_ptr;
2059 size = skb_headlen(skb);
2060 mapping = dma_map_single(kdev, skb->data, size,
2061 DMA_TO_DEVICE);
2062 } else {
2063 /* xmit fragment */
2064 frag = &skb_shinfo(skb)->frags[i - 1];
2065 size = skb_frag_size(frag);
2066 mapping = skb_frag_dma_map(kdev, frag, 0, size,
2067 DMA_TO_DEVICE);
2068 }
2069
2070 ret = dma_mapping_error(kdev, mapping);
2071 if (ret) {
2072 priv->mib.tx_dma_failed++;
2073 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
2074 ret = NETDEV_TX_OK;
2075 goto out_unmap_frags;
2076 }
2077 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
2078 dma_unmap_len_set(tx_cb_ptr, dma_len, size);
2079
2080 tx_cb_ptr->skb = skb;
2081
2082 len_stat = (size << DMA_BUFLENGTH_SHIFT) |
2083 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT);
2084
2085 /* Note: if we ever change from DMA_TX_APPEND_CRC below we
2086 * will need to restore software padding of "runt" packets
2087 */
2088 if (!i) {
2089 len_stat |= DMA_TX_APPEND_CRC | DMA_SOP;
2090 if (skb->ip_summed == CHECKSUM_PARTIAL)
2091 len_stat |= DMA_TX_DO_CSUM;
2092 }
2093 if (i == nr_frags)
2094 len_stat |= DMA_EOP;
2095
2096 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, len_stat);
2097 }
2098
2099 GENET_CB(skb)->last_cb = tx_cb_ptr;
2100 skb_tx_timestamp(skb);
2101
2102 /* Decrement total BD count and advance our write pointer */
2103 ring->free_bds -= nr_frags + 1;
2104 ring->prod_index += nr_frags + 1;
2105 ring->prod_index &= DMA_P_INDEX_MASK;
2106
2107 netdev_tx_sent_queue(txq, GENET_CB(skb)->bytes_sent);
2108
2109 if (ring->free_bds <= (MAX_SKB_FRAGS + 1))
2110 netif_tx_stop_queue(txq);
2111
2112 if (!netdev_xmit_more() || netif_xmit_stopped(txq))
2113 /* Packets are ready, update producer index */
2114 bcmgenet_tdma_ring_writel(priv, ring->index,
2115 ring->prod_index, TDMA_PROD_INDEX);
2116 out:
2117 spin_unlock(&ring->lock);
2118
2119 return ret;
2120
2121 out_unmap_frags:
2122 /* Back up for failed control block mapping */
2123 bcmgenet_put_txcb(priv, ring);
2124
2125 /* Unmap successfully mapped control blocks */
2126 while (i-- > 0) {
2127 tx_cb_ptr = bcmgenet_put_txcb(priv, ring);
2128 bcmgenet_free_tx_cb(kdev, tx_cb_ptr);
2129 }
2130
2131 dev_kfree_skb(skb);
2132 goto out;
2133 }
2134
2135 static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv,
2136 struct enet_cb *cb)
2137 {
2138 struct device *kdev = &priv->pdev->dev;
2139 struct sk_buff *skb;
2140 struct sk_buff *rx_skb;
2141 dma_addr_t mapping;
2142
2143 /* Allocate a new Rx skb */
2144 skb = __netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT,
2145 GFP_ATOMIC | __GFP_NOWARN);
2146 if (!skb) {
2147 priv->mib.alloc_rx_buff_failed++;
2148 netif_err(priv, rx_err, priv->dev,
2149 "%s: Rx skb allocation failed\n", __func__);
2150 return NULL;
2151 }
2152
2153 /* DMA-map the new Rx skb */
2154 mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len,
2155 DMA_FROM_DEVICE);
2156 if (dma_mapping_error(kdev, mapping)) {
2157 priv->mib.rx_dma_failed++;
2158 dev_kfree_skb_any(skb);
2159 netif_err(priv, rx_err, priv->dev,
2160 "%s: Rx skb DMA mapping failed\n", __func__);
2161 return NULL;
2162 }
2163
2164 /* Grab the current Rx skb from the ring and DMA-unmap it */
2165 rx_skb = bcmgenet_free_rx_cb(kdev, cb);
2166
2167 /* Put the new Rx skb on the ring */
2168 cb->skb = skb;
2169 dma_unmap_addr_set(cb, dma_addr, mapping);
2170 dma_unmap_len_set(cb, dma_len, priv->rx_buf_len);
2171 dmadesc_set_addr(priv, cb->bd_addr, mapping);
2172
2173 /* Return the current Rx skb to caller */
2174 return rx_skb;
2175 }
2176
2177 /* bcmgenet_desc_rx - descriptor based rx process.
2178 * this could be called from bottom half, or from NAPI polling method.
2179 */
2180 static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring,
2181 unsigned int budget)
2182 {
2183 struct bcmgenet_priv *priv = ring->priv;
2184 struct net_device *dev = priv->dev;
2185 struct enet_cb *cb;
2186 struct sk_buff *skb;
2187 u32 dma_length_status;
2188 unsigned long dma_flag;
2189 int len;
2190 unsigned int rxpktprocessed = 0, rxpkttoprocess;
2191 unsigned int bytes_processed = 0;
2192 unsigned int p_index, mask;
2193 unsigned int discards;
2194
2195 /* Clear status before servicing to reduce spurious interrupts */
2196 if (ring->index == DESC_INDEX) {
2197 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_DONE,
2198 INTRL2_CPU_CLEAR);
2199 } else {
2200 mask = 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index);
2201 bcmgenet_intrl2_1_writel(priv,
2202 mask,
2203 INTRL2_CPU_CLEAR);
2204 }
2205
2206 p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX);
2207
2208 discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) &
2209 DMA_P_INDEX_DISCARD_CNT_MASK;
2210 if (discards > ring->old_discards) {
2211 discards = discards - ring->old_discards;
2212 ring->errors += discards;
2213 ring->old_discards += discards;
2214
2215 /* Clear HW register when we reach 75% of maximum 0xFFFF */
2216 if (ring->old_discards >= 0xC000) {
2217 ring->old_discards = 0;
2218 bcmgenet_rdma_ring_writel(priv, ring->index, 0,
2219 RDMA_PROD_INDEX);
2220 }
2221 }
2222
2223 p_index &= DMA_P_INDEX_MASK;
2224 rxpkttoprocess = (p_index - ring->c_index) & DMA_C_INDEX_MASK;
2225
2226 netif_dbg(priv, rx_status, dev,
2227 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
2228
2229 while ((rxpktprocessed < rxpkttoprocess) &&
2230 (rxpktprocessed < budget)) {
2231 struct status_64 *status;
2232 __be16 rx_csum;
2233
2234 cb = &priv->rx_cbs[ring->read_ptr];
2235 skb = bcmgenet_rx_refill(priv, cb);
2236
2237 if (unlikely(!skb)) {
2238 ring->dropped++;
2239 goto next;
2240 }
2241
2242 status = (struct status_64 *)skb->data;
2243 dma_length_status = status->length_status;
2244 if (dev->features & NETIF_F_RXCSUM) {
2245 rx_csum = (__force __be16)(status->rx_csum & 0xffff);
2246 if (rx_csum) {
2247 skb->csum = (__force __wsum)ntohs(rx_csum);
2248 skb->ip_summed = CHECKSUM_COMPLETE;
2249 }
2250 }
2251
2252 /* DMA flags and length are still valid no matter how
2253 * we got the Receive Status Vector (64B RSB or register)
2254 */
2255 dma_flag = dma_length_status & 0xffff;
2256 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
2257
2258 netif_dbg(priv, rx_status, dev,
2259 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
2260 __func__, p_index, ring->c_index,
2261 ring->read_ptr, dma_length_status);
2262
2263 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
2264 netif_err(priv, rx_status, dev,
2265 "dropping fragmented packet!\n");
2266 ring->errors++;
2267 dev_kfree_skb_any(skb);
2268 goto next;
2269 }
2270
2271 /* report errors */
2272 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
2273 DMA_RX_OV |
2274 DMA_RX_NO |
2275 DMA_RX_LG |
2276 DMA_RX_RXER))) {
2277 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
2278 (unsigned int)dma_flag);
2279 if (dma_flag & DMA_RX_CRC_ERROR)
2280 dev->stats.rx_crc_errors++;
2281 if (dma_flag & DMA_RX_OV)
2282 dev->stats.rx_over_errors++;
2283 if (dma_flag & DMA_RX_NO)
2284 dev->stats.rx_frame_errors++;
2285 if (dma_flag & DMA_RX_LG)
2286 dev->stats.rx_length_errors++;
2287 dev->stats.rx_errors++;
2288 dev_kfree_skb_any(skb);
2289 goto next;
2290 } /* error packet */
2291
2292 skb_put(skb, len);
2293
2294 /* remove RSB and hardware 2bytes added for IP alignment */
2295 skb_pull(skb, 66);
2296 len -= 66;
2297
2298 if (priv->crc_fwd_en) {
2299 skb_trim(skb, len - ETH_FCS_LEN);
2300 len -= ETH_FCS_LEN;
2301 }
2302
2303 bytes_processed += len;
2304
2305 /*Finish setting up the received SKB and send it to the kernel*/
2306 skb->protocol = eth_type_trans(skb, priv->dev);
2307 ring->packets++;
2308 ring->bytes += len;
2309 if (dma_flag & DMA_RX_MULT)
2310 dev->stats.multicast++;
2311
2312 /* Notify kernel */
2313 napi_gro_receive(&ring->napi, skb);
2314 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
2315
2316 next:
2317 rxpktprocessed++;
2318 if (likely(ring->read_ptr < ring->end_ptr))
2319 ring->read_ptr++;
2320 else
2321 ring->read_ptr = ring->cb_ptr;
2322
2323 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK;
2324 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX);
2325 }
2326
2327 ring->dim.bytes = bytes_processed;
2328 ring->dim.packets = rxpktprocessed;
2329
2330 return rxpktprocessed;
2331 }
2332
2333 /* Rx NAPI polling method */
2334 static int bcmgenet_rx_poll(struct napi_struct *napi, int budget)
2335 {
2336 struct bcmgenet_rx_ring *ring = container_of(napi,
2337 struct bcmgenet_rx_ring, napi);
2338 struct dim_sample dim_sample = {};
2339 unsigned int work_done;
2340
2341 work_done = bcmgenet_desc_rx(ring, budget);
2342
2343 if (work_done < budget) {
2344 napi_complete_done(napi, work_done);
2345 ring->int_enable(ring);
2346 }
2347
2348 if (ring->dim.use_dim) {
2349 dim_update_sample(ring->dim.event_ctr, ring->dim.packets,
2350 ring->dim.bytes, &dim_sample);
2351 net_dim(&ring->dim.dim, dim_sample);
2352 }
2353
2354 return work_done;
2355 }
2356
2357 static void bcmgenet_dim_work(struct work_struct *work)
2358 {
2359 struct dim *dim = container_of(work, struct dim, work);
2360 struct bcmgenet_net_dim *ndim =
2361 container_of(dim, struct bcmgenet_net_dim, dim);
2362 struct bcmgenet_rx_ring *ring =
2363 container_of(ndim, struct bcmgenet_rx_ring, dim);
2364 struct dim_cq_moder cur_profile =
2365 net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
2366
2367 bcmgenet_set_rx_coalesce(ring, cur_profile.usec, cur_profile.pkts);
2368 dim->state = DIM_START_MEASURE;
2369 }
2370
2371 /* Assign skb to RX DMA descriptor. */
2372 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv,
2373 struct bcmgenet_rx_ring *ring)
2374 {
2375 struct enet_cb *cb;
2376 struct sk_buff *skb;
2377 int i;
2378
2379 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
2380
2381 /* loop here for each buffer needing assign */
2382 for (i = 0; i < ring->size; i++) {
2383 cb = ring->cbs + i;
2384 skb = bcmgenet_rx_refill(priv, cb);
2385 if (skb)
2386 dev_consume_skb_any(skb);
2387 if (!cb->skb)
2388 return -ENOMEM;
2389 }
2390
2391 return 0;
2392 }
2393
2394 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
2395 {
2396 struct sk_buff *skb;
2397 struct enet_cb *cb;
2398 int i;
2399
2400 for (i = 0; i < priv->num_rx_bds; i++) {
2401 cb = &priv->rx_cbs[i];
2402
2403 skb = bcmgenet_free_rx_cb(&priv->pdev->dev, cb);
2404 if (skb)
2405 dev_consume_skb_any(skb);
2406 }
2407 }
2408
2409 static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
2410 {
2411 u32 reg;
2412
2413 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2414 if (reg & CMD_SW_RESET)
2415 return;
2416 if (enable)
2417 reg |= mask;
2418 else
2419 reg &= ~mask;
2420 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2421
2422 /* UniMAC stops on a packet boundary, wait for a full-size packet
2423 * to be processed
2424 */
2425 if (enable == 0)
2426 usleep_range(1000, 2000);
2427 }
2428
2429 static void reset_umac(struct bcmgenet_priv *priv)
2430 {
2431 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
2432 bcmgenet_rbuf_ctrl_set(priv, 0);
2433 udelay(10);
2434
2435 /* issue soft reset and disable MAC while updating its registers */
2436 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
2437 udelay(2);
2438 }
2439
2440 static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
2441 {
2442 /* Mask all interrupts.*/
2443 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
2444 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
2445 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
2446 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
2447 }
2448
2449 static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv)
2450 {
2451 u32 int0_enable = 0;
2452
2453 /* Monitor cable plug/unplugged event for internal PHY, external PHY
2454 * and MoCA PHY
2455 */
2456 if (priv->internal_phy) {
2457 int0_enable |= UMAC_IRQ_LINK_EVENT;
2458 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv))
2459 int0_enable |= UMAC_IRQ_PHY_DET_R;
2460 } else if (priv->ext_phy) {
2461 int0_enable |= UMAC_IRQ_LINK_EVENT;
2462 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
2463 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
2464 int0_enable |= UMAC_IRQ_LINK_EVENT;
2465 }
2466 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2467 }
2468
2469 static void init_umac(struct bcmgenet_priv *priv)
2470 {
2471 struct device *kdev = &priv->pdev->dev;
2472 u32 reg;
2473 u32 int0_enable = 0;
2474
2475 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
2476
2477 reset_umac(priv);
2478
2479 /* clear tx/rx counter */
2480 bcmgenet_umac_writel(priv,
2481 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
2482 UMAC_MIB_CTRL);
2483 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
2484
2485 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
2486
2487 /* init tx registers, enable TSB */
2488 reg = bcmgenet_tbuf_ctrl_get(priv);
2489 reg |= TBUF_64B_EN;
2490 bcmgenet_tbuf_ctrl_set(priv, reg);
2491
2492 /* init rx registers, enable ip header optimization and RSB */
2493 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
2494 reg |= RBUF_ALIGN_2B | RBUF_64B_EN;
2495 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
2496
2497 /* enable rx checksumming */
2498 reg = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
2499 reg |= RBUF_RXCHK_EN | RBUF_L3_PARSE_DIS;
2500 /* If UniMAC forwards CRC, we need to skip over it to get
2501 * a valid CHK bit to be set in the per-packet status word
2502 */
2503 if (priv->crc_fwd_en)
2504 reg |= RBUF_SKIP_FCS;
2505 else
2506 reg &= ~RBUF_SKIP_FCS;
2507 bcmgenet_rbuf_writel(priv, reg, RBUF_CHK_CTRL);
2508
2509 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
2510 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
2511
2512 bcmgenet_intr_disable(priv);
2513
2514 /* Configure backpressure vectors for MoCA */
2515 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
2516 reg = bcmgenet_bp_mc_get(priv);
2517 reg |= BIT(priv->hw_params->bp_in_en_shift);
2518
2519 /* bp_mask: back pressure mask */
2520 if (netif_is_multiqueue(priv->dev))
2521 reg |= priv->hw_params->bp_in_mask;
2522 else
2523 reg &= ~priv->hw_params->bp_in_mask;
2524 bcmgenet_bp_mc_set(priv, reg);
2525 }
2526
2527 /* Enable MDIO interrupts on GENET v3+ */
2528 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
2529 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
2530
2531 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2532
2533 dev_dbg(kdev, "done init umac\n");
2534 }
2535
2536 static void bcmgenet_init_dim(struct bcmgenet_rx_ring *ring,
2537 void (*cb)(struct work_struct *work))
2538 {
2539 struct bcmgenet_net_dim *dim = &ring->dim;
2540
2541 INIT_WORK(&dim->dim.work, cb);
2542 dim->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2543 dim->event_ctr = 0;
2544 dim->packets = 0;
2545 dim->bytes = 0;
2546 }
2547
2548 static void bcmgenet_init_rx_coalesce(struct bcmgenet_rx_ring *ring)
2549 {
2550 struct bcmgenet_net_dim *dim = &ring->dim;
2551 struct dim_cq_moder moder;
2552 u32 usecs, pkts;
2553
2554 usecs = ring->rx_coalesce_usecs;
2555 pkts = ring->rx_max_coalesced_frames;
2556
2557 /* If DIM was enabled, re-apply default parameters */
2558 if (dim->use_dim) {
2559 moder = net_dim_get_def_rx_moderation(dim->dim.mode);
2560 usecs = moder.usec;
2561 pkts = moder.pkts;
2562 }
2563
2564 bcmgenet_set_rx_coalesce(ring, usecs, pkts);
2565 }
2566
2567 /* Initialize a Tx ring along with corresponding hardware registers */
2568 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
2569 unsigned int index, unsigned int size,
2570 unsigned int start_ptr, unsigned int end_ptr)
2571 {
2572 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
2573 u32 words_per_bd = WORDS_PER_BD(priv);
2574 u32 flow_period_val = 0;
2575
2576 spin_lock_init(&ring->lock);
2577 ring->priv = priv;
2578 ring->index = index;
2579 if (index == DESC_INDEX) {
2580 ring->queue = 0;
2581 ring->int_enable = bcmgenet_tx_ring16_int_enable;
2582 ring->int_disable = bcmgenet_tx_ring16_int_disable;
2583 } else {
2584 ring->queue = index + 1;
2585 ring->int_enable = bcmgenet_tx_ring_int_enable;
2586 ring->int_disable = bcmgenet_tx_ring_int_disable;
2587 }
2588 ring->cbs = priv->tx_cbs + start_ptr;
2589 ring->size = size;
2590 ring->clean_ptr = start_ptr;
2591 ring->c_index = 0;
2592 ring->free_bds = size;
2593 ring->write_ptr = start_ptr;
2594 ring->cb_ptr = start_ptr;
2595 ring->end_ptr = end_ptr - 1;
2596 ring->prod_index = 0;
2597
2598 /* Set flow period for ring != 16 */
2599 if (index != DESC_INDEX)
2600 flow_period_val = ENET_MAX_MTU_SIZE << 16;
2601
2602 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
2603 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
2604 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
2605 /* Disable rate control for now */
2606 bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
2607 TDMA_FLOW_PERIOD);
2608 bcmgenet_tdma_ring_writel(priv, index,
2609 ((size << DMA_RING_SIZE_SHIFT) |
2610 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
2611
2612 /* Set start and end address, read and write pointers */
2613 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2614 DMA_START_ADDR);
2615 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2616 TDMA_READ_PTR);
2617 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2618 TDMA_WRITE_PTR);
2619 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
2620 DMA_END_ADDR);
2621
2622 /* Initialize Tx NAPI */
2623 netif_tx_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll,
2624 NAPI_POLL_WEIGHT);
2625 }
2626
2627 /* Initialize a RDMA ring */
2628 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
2629 unsigned int index, unsigned int size,
2630 unsigned int start_ptr, unsigned int end_ptr)
2631 {
2632 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index];
2633 u32 words_per_bd = WORDS_PER_BD(priv);
2634 int ret;
2635
2636 ring->priv = priv;
2637 ring->index = index;
2638 if (index == DESC_INDEX) {
2639 ring->int_enable = bcmgenet_rx_ring16_int_enable;
2640 ring->int_disable = bcmgenet_rx_ring16_int_disable;
2641 } else {
2642 ring->int_enable = bcmgenet_rx_ring_int_enable;
2643 ring->int_disable = bcmgenet_rx_ring_int_disable;
2644 }
2645 ring->cbs = priv->rx_cbs + start_ptr;
2646 ring->size = size;
2647 ring->c_index = 0;
2648 ring->read_ptr = start_ptr;
2649 ring->cb_ptr = start_ptr;
2650 ring->end_ptr = end_ptr - 1;
2651
2652 ret = bcmgenet_alloc_rx_buffers(priv, ring);
2653 if (ret)
2654 return ret;
2655
2656 bcmgenet_init_dim(ring, bcmgenet_dim_work);
2657 bcmgenet_init_rx_coalesce(ring);
2658
2659 /* Initialize Rx NAPI */
2660 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll,
2661 NAPI_POLL_WEIGHT);
2662
2663 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
2664 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
2665 bcmgenet_rdma_ring_writel(priv, index,
2666 ((size << DMA_RING_SIZE_SHIFT) |
2667 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
2668 bcmgenet_rdma_ring_writel(priv, index,
2669 (DMA_FC_THRESH_LO <<
2670 DMA_XOFF_THRESHOLD_SHIFT) |
2671 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
2672
2673 /* Set start and end address, read and write pointers */
2674 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2675 DMA_START_ADDR);
2676 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2677 RDMA_READ_PTR);
2678 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2679 RDMA_WRITE_PTR);
2680 bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
2681 DMA_END_ADDR);
2682
2683 return ret;
2684 }
2685
2686 static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv)
2687 {
2688 unsigned int i;
2689 struct bcmgenet_tx_ring *ring;
2690
2691 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2692 ring = &priv->tx_rings[i];
2693 napi_enable(&ring->napi);
2694 ring->int_enable(ring);
2695 }
2696
2697 ring = &priv->tx_rings[DESC_INDEX];
2698 napi_enable(&ring->napi);
2699 ring->int_enable(ring);
2700 }
2701
2702 static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv)
2703 {
2704 unsigned int i;
2705 struct bcmgenet_tx_ring *ring;
2706
2707 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2708 ring = &priv->tx_rings[i];
2709 napi_disable(&ring->napi);
2710 }
2711
2712 ring = &priv->tx_rings[DESC_INDEX];
2713 napi_disable(&ring->napi);
2714 }
2715
2716 static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv)
2717 {
2718 unsigned int i;
2719 struct bcmgenet_tx_ring *ring;
2720
2721 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2722 ring = &priv->tx_rings[i];
2723 netif_napi_del(&ring->napi);
2724 }
2725
2726 ring = &priv->tx_rings[DESC_INDEX];
2727 netif_napi_del(&ring->napi);
2728 }
2729
2730 /* Initialize Tx queues
2731 *
2732 * Queues 0-3 are priority-based, each one has 32 descriptors,
2733 * with queue 0 being the highest priority queue.
2734 *
2735 * Queue 16 is the default Tx queue with
2736 * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors.
2737 *
2738 * The transmit control block pool is then partitioned as follows:
2739 * - Tx queue 0 uses tx_cbs[0..31]
2740 * - Tx queue 1 uses tx_cbs[32..63]
2741 * - Tx queue 2 uses tx_cbs[64..95]
2742 * - Tx queue 3 uses tx_cbs[96..127]
2743 * - Tx queue 16 uses tx_cbs[128..255]
2744 */
2745 static void bcmgenet_init_tx_queues(struct net_device *dev)
2746 {
2747 struct bcmgenet_priv *priv = netdev_priv(dev);
2748 u32 i, dma_enable;
2749 u32 dma_ctrl, ring_cfg;
2750 u32 dma_priority[3] = {0, 0, 0};
2751
2752 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
2753 dma_enable = dma_ctrl & DMA_EN;
2754 dma_ctrl &= ~DMA_EN;
2755 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2756
2757 dma_ctrl = 0;
2758 ring_cfg = 0;
2759
2760 /* Enable strict priority arbiter mode */
2761 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
2762
2763 /* Initialize Tx priority queues */
2764 for (i = 0; i < priv->hw_params->tx_queues; i++) {
2765 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q,
2766 i * priv->hw_params->tx_bds_per_q,
2767 (i + 1) * priv->hw_params->tx_bds_per_q);
2768 ring_cfg |= (1 << i);
2769 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2770 dma_priority[DMA_PRIO_REG_INDEX(i)] |=
2771 ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i));
2772 }
2773
2774 /* Initialize Tx default queue 16 */
2775 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT,
2776 priv->hw_params->tx_queues *
2777 priv->hw_params->tx_bds_per_q,
2778 TOTAL_DESC);
2779 ring_cfg |= (1 << DESC_INDEX);
2780 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2781 dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |=
2782 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) <<
2783 DMA_PRIO_REG_SHIFT(DESC_INDEX));
2784
2785 /* Set Tx queue priorities */
2786 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
2787 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
2788 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
2789
2790 /* Enable Tx queues */
2791 bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG);
2792
2793 /* Enable Tx DMA */
2794 if (dma_enable)
2795 dma_ctrl |= DMA_EN;
2796 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2797 }
2798
2799 static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv)
2800 {
2801 unsigned int i;
2802 struct bcmgenet_rx_ring *ring;
2803
2804 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2805 ring = &priv->rx_rings[i];
2806 napi_enable(&ring->napi);
2807 ring->int_enable(ring);
2808 }
2809
2810 ring = &priv->rx_rings[DESC_INDEX];
2811 napi_enable(&ring->napi);
2812 ring->int_enable(ring);
2813 }
2814
2815 static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv)
2816 {
2817 unsigned int i;
2818 struct bcmgenet_rx_ring *ring;
2819
2820 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2821 ring = &priv->rx_rings[i];
2822 napi_disable(&ring->napi);
2823 cancel_work_sync(&ring->dim.dim.work);
2824 }
2825
2826 ring = &priv->rx_rings[DESC_INDEX];
2827 napi_disable(&ring->napi);
2828 cancel_work_sync(&ring->dim.dim.work);
2829 }
2830
2831 static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv)
2832 {
2833 unsigned int i;
2834 struct bcmgenet_rx_ring *ring;
2835
2836 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2837 ring = &priv->rx_rings[i];
2838 netif_napi_del(&ring->napi);
2839 }
2840
2841 ring = &priv->rx_rings[DESC_INDEX];
2842 netif_napi_del(&ring->napi);
2843 }
2844
2845 /* Initialize Rx queues
2846 *
2847 * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be
2848 * used to direct traffic to these queues.
2849 *
2850 * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors.
2851 */
2852 static int bcmgenet_init_rx_queues(struct net_device *dev)
2853 {
2854 struct bcmgenet_priv *priv = netdev_priv(dev);
2855 u32 i;
2856 u32 dma_enable;
2857 u32 dma_ctrl;
2858 u32 ring_cfg;
2859 int ret;
2860
2861 dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL);
2862 dma_enable = dma_ctrl & DMA_EN;
2863 dma_ctrl &= ~DMA_EN;
2864 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2865
2866 dma_ctrl = 0;
2867 ring_cfg = 0;
2868
2869 /* Initialize Rx priority queues */
2870 for (i = 0; i < priv->hw_params->rx_queues; i++) {
2871 ret = bcmgenet_init_rx_ring(priv, i,
2872 priv->hw_params->rx_bds_per_q,
2873 i * priv->hw_params->rx_bds_per_q,
2874 (i + 1) *
2875 priv->hw_params->rx_bds_per_q);
2876 if (ret)
2877 return ret;
2878
2879 ring_cfg |= (1 << i);
2880 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2881 }
2882
2883 /* Initialize Rx default queue 16 */
2884 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT,
2885 priv->hw_params->rx_queues *
2886 priv->hw_params->rx_bds_per_q,
2887 TOTAL_DESC);
2888 if (ret)
2889 return ret;
2890
2891 ring_cfg |= (1 << DESC_INDEX);
2892 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2893
2894 /* Enable rings */
2895 bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG);
2896
2897 /* Configure ring as descriptor ring and re-enable DMA if enabled */
2898 if (dma_enable)
2899 dma_ctrl |= DMA_EN;
2900 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2901
2902 return 0;
2903 }
2904
2905 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
2906 {
2907 int ret = 0;
2908 int timeout = 0;
2909 u32 reg;
2910 u32 dma_ctrl;
2911 int i;
2912
2913 /* Disable TDMA to stop add more frames in TX DMA */
2914 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2915 reg &= ~DMA_EN;
2916 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2917
2918 /* Check TDMA status register to confirm TDMA is disabled */
2919 while (timeout++ < DMA_TIMEOUT_VAL) {
2920 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2921 if (reg & DMA_DISABLED)
2922 break;
2923
2924 udelay(1);
2925 }
2926
2927 if (timeout == DMA_TIMEOUT_VAL) {
2928 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
2929 ret = -ETIMEDOUT;
2930 }
2931
2932 /* Wait 10ms for packet drain in both tx and rx dma */
2933 usleep_range(10000, 20000);
2934
2935 /* Disable RDMA */
2936 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2937 reg &= ~DMA_EN;
2938 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2939
2940 timeout = 0;
2941 /* Check RDMA status register to confirm RDMA is disabled */
2942 while (timeout++ < DMA_TIMEOUT_VAL) {
2943 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
2944 if (reg & DMA_DISABLED)
2945 break;
2946
2947 udelay(1);
2948 }
2949
2950 if (timeout == DMA_TIMEOUT_VAL) {
2951 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
2952 ret = -ETIMEDOUT;
2953 }
2954
2955 dma_ctrl = 0;
2956 for (i = 0; i < priv->hw_params->rx_queues; i++)
2957 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2958 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2959 reg &= ~dma_ctrl;
2960 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2961
2962 dma_ctrl = 0;
2963 for (i = 0; i < priv->hw_params->tx_queues; i++)
2964 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2965 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2966 reg &= ~dma_ctrl;
2967 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2968
2969 return ret;
2970 }
2971
2972 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
2973 {
2974 struct netdev_queue *txq;
2975 int i;
2976
2977 bcmgenet_fini_rx_napi(priv);
2978 bcmgenet_fini_tx_napi(priv);
2979
2980 for (i = 0; i < priv->num_tx_bds; i++)
2981 dev_kfree_skb(bcmgenet_free_tx_cb(&priv->pdev->dev,
2982 priv->tx_cbs + i));
2983
2984 for (i = 0; i < priv->hw_params->tx_queues; i++) {
2985 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[i].queue);
2986 netdev_tx_reset_queue(txq);
2987 }
2988
2989 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[DESC_INDEX].queue);
2990 netdev_tx_reset_queue(txq);
2991
2992 bcmgenet_free_rx_buffers(priv);
2993 kfree(priv->rx_cbs);
2994 kfree(priv->tx_cbs);
2995 }
2996
2997 /* init_edma: Initialize DMA control register */
2998 static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
2999 {
3000 int ret;
3001 unsigned int i;
3002 struct enet_cb *cb;
3003
3004 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
3005
3006 /* Initialize common Rx ring structures */
3007 priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
3008 priv->num_rx_bds = TOTAL_DESC;
3009 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
3010 GFP_KERNEL);
3011 if (!priv->rx_cbs)
3012 return -ENOMEM;
3013
3014 for (i = 0; i < priv->num_rx_bds; i++) {
3015 cb = priv->rx_cbs + i;
3016 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE;
3017 }
3018
3019 /* Initialize common TX ring structures */
3020 priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
3021 priv->num_tx_bds = TOTAL_DESC;
3022 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
3023 GFP_KERNEL);
3024 if (!priv->tx_cbs) {
3025 kfree(priv->rx_cbs);
3026 return -ENOMEM;
3027 }
3028
3029 for (i = 0; i < priv->num_tx_bds; i++) {
3030 cb = priv->tx_cbs + i;
3031 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE;
3032 }
3033
3034 /* Init rDma */
3035 bcmgenet_rdma_writel(priv, priv->dma_max_burst_length,
3036 DMA_SCB_BURST_SIZE);
3037
3038 /* Initialize Rx queues */
3039 ret = bcmgenet_init_rx_queues(priv->dev);
3040 if (ret) {
3041 netdev_err(priv->dev, "failed to initialize Rx queues\n");
3042 bcmgenet_free_rx_buffers(priv);
3043 kfree(priv->rx_cbs);
3044 kfree(priv->tx_cbs);
3045 return ret;
3046 }
3047
3048 /* Init tDma */
3049 bcmgenet_tdma_writel(priv, priv->dma_max_burst_length,
3050 DMA_SCB_BURST_SIZE);
3051
3052 /* Initialize Tx queues */
3053 bcmgenet_init_tx_queues(priv->dev);
3054
3055 return 0;
3056 }
3057
3058 /* Interrupt bottom half */
3059 static void bcmgenet_irq_task(struct work_struct *work)
3060 {
3061 unsigned int status;
3062 struct bcmgenet_priv *priv = container_of(
3063 work, struct bcmgenet_priv, bcmgenet_irq_work);
3064
3065 netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
3066
3067 spin_lock_irq(&priv->lock);
3068 status = priv->irq0_stat;
3069 priv->irq0_stat = 0;
3070 spin_unlock_irq(&priv->lock);
3071
3072 if (status & UMAC_IRQ_PHY_DET_R &&
3073 priv->dev->phydev->autoneg != AUTONEG_ENABLE) {
3074 phy_init_hw(priv->dev->phydev);
3075 genphy_config_aneg(priv->dev->phydev);
3076 }
3077
3078 /* Link UP/DOWN event */
3079 if (status & UMAC_IRQ_LINK_EVENT)
3080 phy_mac_interrupt(priv->dev->phydev);
3081
3082 }
3083
3084 /* bcmgenet_isr1: handle Rx and Tx priority queues */
3085 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
3086 {
3087 struct bcmgenet_priv *priv = dev_id;
3088 struct bcmgenet_rx_ring *rx_ring;
3089 struct bcmgenet_tx_ring *tx_ring;
3090 unsigned int index, status;
3091
3092 /* Read irq status */
3093 status = bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
3094 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
3095
3096 /* clear interrupts */
3097 bcmgenet_intrl2_1_writel(priv, status, INTRL2_CPU_CLEAR);
3098
3099 netif_dbg(priv, intr, priv->dev,
3100 "%s: IRQ=0x%x\n", __func__, status);
3101
3102 /* Check Rx priority queue interrupts */
3103 for (index = 0; index < priv->hw_params->rx_queues; index++) {
3104 if (!(status & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index)))
3105 continue;
3106
3107 rx_ring = &priv->rx_rings[index];
3108 rx_ring->dim.event_ctr++;
3109
3110 if (likely(napi_schedule_prep(&rx_ring->napi))) {
3111 rx_ring->int_disable(rx_ring);
3112 __napi_schedule_irqoff(&rx_ring->napi);
3113 }
3114 }
3115
3116 /* Check Tx priority queue interrupts */
3117 for (index = 0; index < priv->hw_params->tx_queues; index++) {
3118 if (!(status & BIT(index)))
3119 continue;
3120
3121 tx_ring = &priv->tx_rings[index];
3122
3123 if (likely(napi_schedule_prep(&tx_ring->napi))) {
3124 tx_ring->int_disable(tx_ring);
3125 __napi_schedule_irqoff(&tx_ring->napi);
3126 }
3127 }
3128
3129 return IRQ_HANDLED;
3130 }
3131
3132 /* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */
3133 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
3134 {
3135 struct bcmgenet_priv *priv = dev_id;
3136 struct bcmgenet_rx_ring *rx_ring;
3137 struct bcmgenet_tx_ring *tx_ring;
3138 unsigned int status;
3139 unsigned long flags;
3140
3141 /* Read irq status */
3142 status = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
3143 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
3144
3145 /* clear interrupts */
3146 bcmgenet_intrl2_0_writel(priv, status, INTRL2_CPU_CLEAR);
3147
3148 netif_dbg(priv, intr, priv->dev,
3149 "IRQ=0x%x\n", status);
3150
3151 if (status & UMAC_IRQ_RXDMA_DONE) {
3152 rx_ring = &priv->rx_rings[DESC_INDEX];
3153 rx_ring->dim.event_ctr++;
3154
3155 if (likely(napi_schedule_prep(&rx_ring->napi))) {
3156 rx_ring->int_disable(rx_ring);
3157 __napi_schedule_irqoff(&rx_ring->napi);
3158 }
3159 }
3160
3161 if (status & UMAC_IRQ_TXDMA_DONE) {
3162 tx_ring = &priv->tx_rings[DESC_INDEX];
3163
3164 if (likely(napi_schedule_prep(&tx_ring->napi))) {
3165 tx_ring->int_disable(tx_ring);
3166 __napi_schedule_irqoff(&tx_ring->napi);
3167 }
3168 }
3169
3170 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
3171 status & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
3172 wake_up(&priv->wq);
3173 }
3174
3175 /* all other interested interrupts handled in bottom half */
3176 status &= (UMAC_IRQ_LINK_EVENT | UMAC_IRQ_PHY_DET_R);
3177 if (status) {
3178 /* Save irq status for bottom-half processing. */
3179 spin_lock_irqsave(&priv->lock, flags);
3180 priv->irq0_stat |= status;
3181 spin_unlock_irqrestore(&priv->lock, flags);
3182
3183 schedule_work(&priv->bcmgenet_irq_work);
3184 }
3185
3186 return IRQ_HANDLED;
3187 }
3188
3189 static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
3190 {
3191 /* Acknowledge the interrupt */
3192 return IRQ_HANDLED;
3193 }
3194
3195 #ifdef CONFIG_NET_POLL_CONTROLLER
3196 static void bcmgenet_poll_controller(struct net_device *dev)
3197 {
3198 struct bcmgenet_priv *priv = netdev_priv(dev);
3199
3200 /* Invoke the main RX/TX interrupt handler */
3201 disable_irq(priv->irq0);
3202 bcmgenet_isr0(priv->irq0, priv);
3203 enable_irq(priv->irq0);
3204
3205 /* And the interrupt handler for RX/TX priority queues */
3206 disable_irq(priv->irq1);
3207 bcmgenet_isr1(priv->irq1, priv);
3208 enable_irq(priv->irq1);
3209 }
3210 #endif
3211
3212 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
3213 {
3214 u32 reg;
3215
3216 reg = bcmgenet_rbuf_ctrl_get(priv);
3217 reg |= BIT(1);
3218 bcmgenet_rbuf_ctrl_set(priv, reg);
3219 udelay(10);
3220
3221 reg &= ~BIT(1);
3222 bcmgenet_rbuf_ctrl_set(priv, reg);
3223 udelay(10);
3224 }
3225
3226 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
3227 unsigned char *addr)
3228 {
3229 bcmgenet_umac_writel(priv, get_unaligned_be32(&addr[0]), UMAC_MAC0);
3230 bcmgenet_umac_writel(priv, get_unaligned_be16(&addr[4]), UMAC_MAC1);
3231 }
3232
3233 static void bcmgenet_get_hw_addr(struct bcmgenet_priv *priv,
3234 unsigned char *addr)
3235 {
3236 u32 addr_tmp;
3237
3238 addr_tmp = bcmgenet_umac_readl(priv, UMAC_MAC0);
3239 put_unaligned_be32(addr_tmp, &addr[0]);
3240 addr_tmp = bcmgenet_umac_readl(priv, UMAC_MAC1);
3241 put_unaligned_be16(addr_tmp, &addr[4]);
3242 }
3243
3244 /* Returns a reusable dma control register value */
3245 static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
3246 {
3247 unsigned int i;
3248 u32 reg;
3249 u32 dma_ctrl;
3250
3251 /* disable DMA */
3252 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
3253 for (i = 0; i < priv->hw_params->tx_queues; i++)
3254 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
3255 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
3256 reg &= ~dma_ctrl;
3257 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
3258
3259 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
3260 for (i = 0; i < priv->hw_params->rx_queues; i++)
3261 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
3262 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
3263 reg &= ~dma_ctrl;
3264 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
3265
3266 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
3267 udelay(10);
3268 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
3269
3270 return dma_ctrl;
3271 }
3272
3273 static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
3274 {
3275 u32 reg;
3276
3277 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
3278 reg |= dma_ctrl;
3279 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
3280
3281 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
3282 reg |= dma_ctrl;
3283 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
3284 }
3285
3286 static void bcmgenet_netif_start(struct net_device *dev)
3287 {
3288 struct bcmgenet_priv *priv = netdev_priv(dev);
3289
3290 /* Start the network engine */
3291 bcmgenet_set_rx_mode(dev);
3292 bcmgenet_enable_rx_napi(priv);
3293
3294 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
3295
3296 bcmgenet_enable_tx_napi(priv);
3297
3298 /* Monitor link interrupts now */
3299 bcmgenet_link_intr_enable(priv);
3300
3301 phy_start(dev->phydev);
3302 }
3303
3304 static int bcmgenet_open(struct net_device *dev)
3305 {
3306 struct bcmgenet_priv *priv = netdev_priv(dev);
3307 unsigned long dma_ctrl;
3308 int ret;
3309
3310 netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
3311
3312 /* Turn on the clock */
3313 clk_prepare_enable(priv->clk);
3314
3315 /* If this is an internal GPHY, power it back on now, before UniMAC is
3316 * brought out of reset as absolutely no UniMAC activity is allowed
3317 */
3318 if (priv->internal_phy)
3319 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3320
3321 /* take MAC out of reset */
3322 bcmgenet_umac_reset(priv);
3323
3324 init_umac(priv);
3325
3326 /* Apply features again in case we changed them while interface was
3327 * down
3328 */
3329 bcmgenet_set_features(dev, dev->features);
3330
3331 bcmgenet_set_hw_addr(priv, dev->dev_addr);
3332
3333 /* Disable RX/TX DMA and flush TX queues */
3334 dma_ctrl = bcmgenet_dma_disable(priv);
3335
3336 /* Reinitialize TDMA and RDMA and SW housekeeping */
3337 ret = bcmgenet_init_dma(priv);
3338 if (ret) {
3339 netdev_err(dev, "failed to initialize DMA\n");
3340 goto err_clk_disable;
3341 }
3342
3343 /* Always enable ring 16 - descriptor ring */
3344 bcmgenet_enable_dma(priv, dma_ctrl);
3345
3346 /* HFB init */
3347 bcmgenet_hfb_init(priv);
3348
3349 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
3350 dev->name, priv);
3351 if (ret < 0) {
3352 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
3353 goto err_fini_dma;
3354 }
3355
3356 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
3357 dev->name, priv);
3358 if (ret < 0) {
3359 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
3360 goto err_irq0;
3361 }
3362
3363 ret = bcmgenet_mii_probe(dev);
3364 if (ret) {
3365 netdev_err(dev, "failed to connect to PHY\n");
3366 goto err_irq1;
3367 }
3368
3369 bcmgenet_netif_start(dev);
3370
3371 netif_tx_start_all_queues(dev);
3372
3373 return 0;
3374
3375 err_irq1:
3376 free_irq(priv->irq1, priv);
3377 err_irq0:
3378 free_irq(priv->irq0, priv);
3379 err_fini_dma:
3380 bcmgenet_dma_teardown(priv);
3381 bcmgenet_fini_dma(priv);
3382 err_clk_disable:
3383 if (priv->internal_phy)
3384 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3385 clk_disable_unprepare(priv->clk);
3386 return ret;
3387 }
3388
3389 static void bcmgenet_netif_stop(struct net_device *dev)
3390 {
3391 struct bcmgenet_priv *priv = netdev_priv(dev);
3392
3393 bcmgenet_disable_tx_napi(priv);
3394 netif_tx_disable(dev);
3395
3396 /* Disable MAC receive */
3397 umac_enable_set(priv, CMD_RX_EN, false);
3398
3399 bcmgenet_dma_teardown(priv);
3400
3401 /* Disable MAC transmit. TX DMA disabled must be done before this */
3402 umac_enable_set(priv, CMD_TX_EN, false);
3403
3404 phy_stop(dev->phydev);
3405 bcmgenet_disable_rx_napi(priv);
3406 bcmgenet_intr_disable(priv);
3407
3408 /* Wait for pending work items to complete. Since interrupts are
3409 * disabled no new work will be scheduled.
3410 */
3411 cancel_work_sync(&priv->bcmgenet_irq_work);
3412
3413 priv->old_link = -1;
3414 priv->old_speed = -1;
3415 priv->old_duplex = -1;
3416 priv->old_pause = -1;
3417
3418 /* tx reclaim */
3419 bcmgenet_tx_reclaim_all(dev);
3420 bcmgenet_fini_dma(priv);
3421 }
3422
3423 static int bcmgenet_close(struct net_device *dev)
3424 {
3425 struct bcmgenet_priv *priv = netdev_priv(dev);
3426 int ret = 0;
3427
3428 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
3429
3430 bcmgenet_netif_stop(dev);
3431
3432 /* Really kill the PHY state machine and disconnect from it */
3433 phy_disconnect(dev->phydev);
3434
3435 free_irq(priv->irq0, priv);
3436 free_irq(priv->irq1, priv);
3437
3438 if (priv->internal_phy)
3439 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3440
3441 clk_disable_unprepare(priv->clk);
3442
3443 return ret;
3444 }
3445
3446 static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring)
3447 {
3448 struct bcmgenet_priv *priv = ring->priv;
3449 u32 p_index, c_index, intsts, intmsk;
3450 struct netdev_queue *txq;
3451 unsigned int free_bds;
3452 bool txq_stopped;
3453
3454 if (!netif_msg_tx_err(priv))
3455 return;
3456
3457 txq = netdev_get_tx_queue(priv->dev, ring->queue);
3458
3459 spin_lock(&ring->lock);
3460 if (ring->index == DESC_INDEX) {
3461 intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
3462 intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE;
3463 } else {
3464 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
3465 intmsk = 1 << ring->index;
3466 }
3467 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
3468 p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX);
3469 txq_stopped = netif_tx_queue_stopped(txq);
3470 free_bds = ring->free_bds;
3471 spin_unlock(&ring->lock);
3472
3473 netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n"
3474 "TX queue status: %s, interrupts: %s\n"
3475 "(sw)free_bds: %d (sw)size: %d\n"
3476 "(sw)p_index: %d (hw)p_index: %d\n"
3477 "(sw)c_index: %d (hw)c_index: %d\n"
3478 "(sw)clean_p: %d (sw)write_p: %d\n"
3479 "(sw)cb_ptr: %d (sw)end_ptr: %d\n",
3480 ring->index, ring->queue,
3481 txq_stopped ? "stopped" : "active",
3482 intsts & intmsk ? "enabled" : "disabled",
3483 free_bds, ring->size,
3484 ring->prod_index, p_index & DMA_P_INDEX_MASK,
3485 ring->c_index, c_index & DMA_C_INDEX_MASK,
3486 ring->clean_ptr, ring->write_ptr,
3487 ring->cb_ptr, ring->end_ptr);
3488 }
3489
3490 static void bcmgenet_timeout(struct net_device *dev, unsigned int txqueue)
3491 {
3492 struct bcmgenet_priv *priv = netdev_priv(dev);
3493 u32 int0_enable = 0;
3494 u32 int1_enable = 0;
3495 unsigned int q;
3496
3497 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
3498
3499 for (q = 0; q < priv->hw_params->tx_queues; q++)
3500 bcmgenet_dump_tx_queue(&priv->tx_rings[q]);
3501 bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]);
3502
3503 bcmgenet_tx_reclaim_all(dev);
3504
3505 for (q = 0; q < priv->hw_params->tx_queues; q++)
3506 int1_enable |= (1 << q);
3507
3508 int0_enable = UMAC_IRQ_TXDMA_DONE;
3509
3510 /* Re-enable TX interrupts if disabled */
3511 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
3512 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
3513
3514 netif_trans_update(dev);
3515
3516 dev->stats.tx_errors++;
3517
3518 netif_tx_wake_all_queues(dev);
3519 }
3520
3521 #define MAX_MDF_FILTER 17
3522
3523 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
3524 unsigned char *addr,
3525 int *i)
3526 {
3527 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
3528 UMAC_MDF_ADDR + (*i * 4));
3529 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
3530 addr[4] << 8 | addr[5],
3531 UMAC_MDF_ADDR + ((*i + 1) * 4));
3532 *i += 2;
3533 }
3534
3535 static void bcmgenet_set_rx_mode(struct net_device *dev)
3536 {
3537 struct bcmgenet_priv *priv = netdev_priv(dev);
3538 struct netdev_hw_addr *ha;
3539 int i, nfilter;
3540 u32 reg;
3541
3542 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
3543
3544 /* Number of filters needed */
3545 nfilter = netdev_uc_count(dev) + netdev_mc_count(dev) + 2;
3546
3547 /*
3548 * Turn on promicuous mode for three scenarios
3549 * 1. IFF_PROMISC flag is set
3550 * 2. IFF_ALLMULTI flag is set
3551 * 3. The number of filters needed exceeds the number filters
3552 * supported by the hardware.
3553 */
3554 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
3555 if ((dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) ||
3556 (nfilter > MAX_MDF_FILTER)) {
3557 reg |= CMD_PROMISC;
3558 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3559 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
3560 return;
3561 } else {
3562 reg &= ~CMD_PROMISC;
3563 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3564 }
3565
3566 /* update MDF filter */
3567 i = 0;
3568 /* Broadcast */
3569 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i);
3570 /* my own address.*/
3571 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i);
3572
3573 /* Unicast */
3574 netdev_for_each_uc_addr(ha, dev)
3575 bcmgenet_set_mdf_addr(priv, ha->addr, &i);
3576
3577 /* Multicast */
3578 netdev_for_each_mc_addr(ha, dev)
3579 bcmgenet_set_mdf_addr(priv, ha->addr, &i);
3580
3581 /* Enable filters */
3582 reg = GENMASK(MAX_MDF_FILTER - 1, MAX_MDF_FILTER - nfilter);
3583 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
3584 }
3585
3586 /* Set the hardware MAC address. */
3587 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
3588 {
3589 struct sockaddr *addr = p;
3590
3591 /* Setting the MAC address at the hardware level is not possible
3592 * without disabling the UniMAC RX/TX enable bits.
3593 */
3594 if (netif_running(dev))
3595 return -EBUSY;
3596
3597 ether_addr_copy(dev->dev_addr, addr->sa_data);
3598
3599 return 0;
3600 }
3601
3602 static struct net_device_stats *bcmgenet_get_stats(struct net_device *dev)
3603 {
3604 struct bcmgenet_priv *priv = netdev_priv(dev);
3605 unsigned long tx_bytes = 0, tx_packets = 0;
3606 unsigned long rx_bytes = 0, rx_packets = 0;
3607 unsigned long rx_errors = 0, rx_dropped = 0;
3608 struct bcmgenet_tx_ring *tx_ring;
3609 struct bcmgenet_rx_ring *rx_ring;
3610 unsigned int q;
3611
3612 for (q = 0; q < priv->hw_params->tx_queues; q++) {
3613 tx_ring = &priv->tx_rings[q];
3614 tx_bytes += tx_ring->bytes;
3615 tx_packets += tx_ring->packets;
3616 }
3617 tx_ring = &priv->tx_rings[DESC_INDEX];
3618 tx_bytes += tx_ring->bytes;
3619 tx_packets += tx_ring->packets;
3620
3621 for (q = 0; q < priv->hw_params->rx_queues; q++) {
3622 rx_ring = &priv->rx_rings[q];
3623
3624 rx_bytes += rx_ring->bytes;
3625 rx_packets += rx_ring->packets;
3626 rx_errors += rx_ring->errors;
3627 rx_dropped += rx_ring->dropped;
3628 }
3629 rx_ring = &priv->rx_rings[DESC_INDEX];
3630 rx_bytes += rx_ring->bytes;
3631 rx_packets += rx_ring->packets;
3632 rx_errors += rx_ring->errors;
3633 rx_dropped += rx_ring->dropped;
3634
3635 dev->stats.tx_bytes = tx_bytes;
3636 dev->stats.tx_packets = tx_packets;
3637 dev->stats.rx_bytes = rx_bytes;
3638 dev->stats.rx_packets = rx_packets;
3639 dev->stats.rx_errors = rx_errors;
3640 dev->stats.rx_missed_errors = rx_errors;
3641 dev->stats.rx_dropped = rx_dropped;
3642 return &dev->stats;
3643 }
3644
3645 static int bcmgenet_change_carrier(struct net_device *dev, bool new_carrier)
3646 {
3647 struct bcmgenet_priv *priv = netdev_priv(dev);
3648
3649 if (!dev->phydev || !phy_is_pseudo_fixed_link(dev->phydev) ||
3650 priv->phy_interface != PHY_INTERFACE_MODE_MOCA)
3651 return -EOPNOTSUPP;
3652
3653 if (new_carrier)
3654 netif_carrier_on(dev);
3655 else
3656 netif_carrier_off(dev);
3657
3658 return 0;
3659 }
3660
3661 static const struct net_device_ops bcmgenet_netdev_ops = {
3662 .ndo_open = bcmgenet_open,
3663 .ndo_stop = bcmgenet_close,
3664 .ndo_start_xmit = bcmgenet_xmit,
3665 .ndo_tx_timeout = bcmgenet_timeout,
3666 .ndo_set_rx_mode = bcmgenet_set_rx_mode,
3667 .ndo_set_mac_address = bcmgenet_set_mac_addr,
3668 .ndo_eth_ioctl = phy_do_ioctl_running,
3669 .ndo_set_features = bcmgenet_set_features,
3670 #ifdef CONFIG_NET_POLL_CONTROLLER
3671 .ndo_poll_controller = bcmgenet_poll_controller,
3672 #endif
3673 .ndo_get_stats = bcmgenet_get_stats,
3674 .ndo_change_carrier = bcmgenet_change_carrier,
3675 };
3676
3677 /* Array of GENET hardware parameters/characteristics */
3678 static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
3679 [GENET_V1] = {
3680 .tx_queues = 0,
3681 .tx_bds_per_q = 0,
3682 .rx_queues = 0,
3683 .rx_bds_per_q = 0,
3684 .bp_in_en_shift = 16,
3685 .bp_in_mask = 0xffff,
3686 .hfb_filter_cnt = 16,
3687 .qtag_mask = 0x1F,
3688 .hfb_offset = 0x1000,
3689 .rdma_offset = 0x2000,
3690 .tdma_offset = 0x3000,
3691 .words_per_bd = 2,
3692 },
3693 [GENET_V2] = {
3694 .tx_queues = 4,
3695 .tx_bds_per_q = 32,
3696 .rx_queues = 0,
3697 .rx_bds_per_q = 0,
3698 .bp_in_en_shift = 16,
3699 .bp_in_mask = 0xffff,
3700 .hfb_filter_cnt = 16,
3701 .qtag_mask = 0x1F,
3702 .tbuf_offset = 0x0600,
3703 .hfb_offset = 0x1000,
3704 .hfb_reg_offset = 0x2000,
3705 .rdma_offset = 0x3000,
3706 .tdma_offset = 0x4000,
3707 .words_per_bd = 2,
3708 .flags = GENET_HAS_EXT,
3709 },
3710 [GENET_V3] = {
3711 .tx_queues = 4,
3712 .tx_bds_per_q = 32,
3713 .rx_queues = 0,
3714 .rx_bds_per_q = 0,
3715 .bp_in_en_shift = 17,
3716 .bp_in_mask = 0x1ffff,
3717 .hfb_filter_cnt = 48,
3718 .hfb_filter_size = 128,
3719 .qtag_mask = 0x3F,
3720 .tbuf_offset = 0x0600,
3721 .hfb_offset = 0x8000,
3722 .hfb_reg_offset = 0xfc00,
3723 .rdma_offset = 0x10000,
3724 .tdma_offset = 0x11000,
3725 .words_per_bd = 2,
3726 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR |
3727 GENET_HAS_MOCA_LINK_DET,
3728 },
3729 [GENET_V4] = {
3730 .tx_queues = 4,
3731 .tx_bds_per_q = 32,
3732 .rx_queues = 0,
3733 .rx_bds_per_q = 0,
3734 .bp_in_en_shift = 17,
3735 .bp_in_mask = 0x1ffff,
3736 .hfb_filter_cnt = 48,
3737 .hfb_filter_size = 128,
3738 .qtag_mask = 0x3F,
3739 .tbuf_offset = 0x0600,
3740 .hfb_offset = 0x8000,
3741 .hfb_reg_offset = 0xfc00,
3742 .rdma_offset = 0x2000,
3743 .tdma_offset = 0x4000,
3744 .words_per_bd = 3,
3745 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3746 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3747 },
3748 [GENET_V5] = {
3749 .tx_queues = 4,
3750 .tx_bds_per_q = 32,
3751 .rx_queues = 0,
3752 .rx_bds_per_q = 0,
3753 .bp_in_en_shift = 17,
3754 .bp_in_mask = 0x1ffff,
3755 .hfb_filter_cnt = 48,
3756 .hfb_filter_size = 128,
3757 .qtag_mask = 0x3F,
3758 .tbuf_offset = 0x0600,
3759 .hfb_offset = 0x8000,
3760 .hfb_reg_offset = 0xfc00,
3761 .rdma_offset = 0x2000,
3762 .tdma_offset = 0x4000,
3763 .words_per_bd = 3,
3764 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3765 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3766 },
3767 };
3768
3769 /* Infer hardware parameters from the detected GENET version */
3770 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
3771 {
3772 struct bcmgenet_hw_params *params;
3773 u32 reg;
3774 u8 major;
3775 u16 gphy_rev;
3776
3777 if (GENET_IS_V5(priv) || GENET_IS_V4(priv)) {
3778 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3779 genet_dma_ring_regs = genet_dma_ring_regs_v4;
3780 } else if (GENET_IS_V3(priv)) {
3781 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3782 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3783 } else if (GENET_IS_V2(priv)) {
3784 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
3785 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3786 } else if (GENET_IS_V1(priv)) {
3787 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
3788 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3789 }
3790
3791 /* enum genet_version starts at 1 */
3792 priv->hw_params = &bcmgenet_hw_params[priv->version];
3793 params = priv->hw_params;
3794
3795 /* Read GENET HW version */
3796 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
3797 major = (reg >> 24 & 0x0f);
3798 if (major == 6)
3799 major = 5;
3800 else if (major == 5)
3801 major = 4;
3802 else if (major == 0)
3803 major = 1;
3804 if (major != priv->version) {
3805 dev_err(&priv->pdev->dev,
3806 "GENET version mismatch, got: %d, configured for: %d\n",
3807 major, priv->version);
3808 }
3809
3810 /* Print the GENET core version */
3811 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
3812 major, (reg >> 16) & 0x0f, reg & 0xffff);
3813
3814 /* Store the integrated PHY revision for the MDIO probing function
3815 * to pass this information to the PHY driver. The PHY driver expects
3816 * to find the PHY major revision in bits 15:8 while the GENET register
3817 * stores that information in bits 7:0, account for that.
3818 *
3819 * On newer chips, starting with PHY revision G0, a new scheme is
3820 * deployed similar to the Starfighter 2 switch with GPHY major
3821 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
3822 * is reserved as well as special value 0x01ff, we have a small
3823 * heuristic to check for the new GPHY revision and re-arrange things
3824 * so the GPHY driver is happy.
3825 */
3826 gphy_rev = reg & 0xffff;
3827
3828 if (GENET_IS_V5(priv)) {
3829 /* The EPHY revision should come from the MDIO registers of
3830 * the PHY not from GENET.
3831 */
3832 if (gphy_rev != 0) {
3833 pr_warn("GENET is reporting EPHY revision: 0x%04x\n",
3834 gphy_rev);
3835 }
3836 /* This is reserved so should require special treatment */
3837 } else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
3838 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
3839 return;
3840 /* This is the good old scheme, just GPHY major, no minor nor patch */
3841 } else if ((gphy_rev & 0xf0) != 0) {
3842 priv->gphy_rev = gphy_rev << 8;
3843 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
3844 } else if ((gphy_rev & 0xff00) != 0) {
3845 priv->gphy_rev = gphy_rev;
3846 }
3847
3848 #ifdef CONFIG_PHYS_ADDR_T_64BIT
3849 if (!(params->flags & GENET_HAS_40BITS))
3850 pr_warn("GENET does not support 40-bits PA\n");
3851 #endif
3852
3853 pr_debug("Configuration for version: %d\n"
3854 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n"
3855 "BP << en: %2d, BP msk: 0x%05x\n"
3856 "HFB count: %2d, QTAQ msk: 0x%05x\n"
3857 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
3858 "RDMA: 0x%05x, TDMA: 0x%05x\n"
3859 "Words/BD: %d\n",
3860 priv->version,
3861 params->tx_queues, params->tx_bds_per_q,
3862 params->rx_queues, params->rx_bds_per_q,
3863 params->bp_in_en_shift, params->bp_in_mask,
3864 params->hfb_filter_cnt, params->qtag_mask,
3865 params->tbuf_offset, params->hfb_offset,
3866 params->hfb_reg_offset,
3867 params->rdma_offset, params->tdma_offset,
3868 params->words_per_bd);
3869 }
3870
3871 struct bcmgenet_plat_data {
3872 enum bcmgenet_version version;
3873 u32 dma_max_burst_length;
3874 };
3875
3876 static const struct bcmgenet_plat_data v1_plat_data = {
3877 .version = GENET_V1,
3878 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3879 };
3880
3881 static const struct bcmgenet_plat_data v2_plat_data = {
3882 .version = GENET_V2,
3883 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3884 };
3885
3886 static const struct bcmgenet_plat_data v3_plat_data = {
3887 .version = GENET_V3,
3888 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3889 };
3890
3891 static const struct bcmgenet_plat_data v4_plat_data = {
3892 .version = GENET_V4,
3893 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3894 };
3895
3896 static const struct bcmgenet_plat_data v5_plat_data = {
3897 .version = GENET_V5,
3898 .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3899 };
3900
3901 static const struct bcmgenet_plat_data bcm2711_plat_data = {
3902 .version = GENET_V5,
3903 .dma_max_burst_length = 0x08,
3904 };
3905
3906 static const struct of_device_id bcmgenet_match[] = {
3907 { .compatible = "brcm,genet-v1", .data = &v1_plat_data },
3908 { .compatible = "brcm,genet-v2", .data = &v2_plat_data },
3909 { .compatible = "brcm,genet-v3", .data = &v3_plat_data },
3910 { .compatible = "brcm,genet-v4", .data = &v4_plat_data },
3911 { .compatible = "brcm,genet-v5", .data = &v5_plat_data },
3912 { .compatible = "brcm,bcm2711-genet-v5", .data = &bcm2711_plat_data },
3913 { },
3914 };
3915 MODULE_DEVICE_TABLE(of, bcmgenet_match);
3916
3917 static int bcmgenet_probe(struct platform_device *pdev)
3918 {
3919 struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
3920 const struct bcmgenet_plat_data *pdata;
3921 struct bcmgenet_priv *priv;
3922 struct net_device *dev;
3923 unsigned int i;
3924 int err = -EIO;
3925
3926 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */
3927 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1,
3928 GENET_MAX_MQ_CNT + 1);
3929 if (!dev) {
3930 dev_err(&pdev->dev, "can't allocate net device\n");
3931 return -ENOMEM;
3932 }
3933
3934 priv = netdev_priv(dev);
3935 priv->irq0 = platform_get_irq(pdev, 0);
3936 if (priv->irq0 < 0) {
3937 err = priv->irq0;
3938 goto err;
3939 }
3940 priv->irq1 = platform_get_irq(pdev, 1);
3941 if (priv->irq1 < 0) {
3942 err = priv->irq1;
3943 goto err;
3944 }
3945 priv->wol_irq = platform_get_irq_optional(pdev, 2);
3946
3947 priv->base = devm_platform_ioremap_resource(pdev, 0);
3948 if (IS_ERR(priv->base)) {
3949 err = PTR_ERR(priv->base);
3950 goto err;
3951 }
3952
3953 spin_lock_init(&priv->lock);
3954
3955 SET_NETDEV_DEV(dev, &pdev->dev);
3956 dev_set_drvdata(&pdev->dev, dev);
3957 dev->watchdog_timeo = 2 * HZ;
3958 dev->ethtool_ops = &bcmgenet_ethtool_ops;
3959 dev->netdev_ops = &bcmgenet_netdev_ops;
3960
3961 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
3962
3963 /* Set default features */
3964 dev->features |= NETIF_F_SG | NETIF_F_HIGHDMA | NETIF_F_HW_CSUM |
3965 NETIF_F_RXCSUM;
3966 dev->hw_features |= dev->features;
3967 dev->vlan_features |= dev->features;
3968
3969 /* Request the WOL interrupt and advertise suspend if available */
3970 priv->wol_irq_disabled = true;
3971 if (priv->wol_irq > 0) {
3972 err = devm_request_irq(&pdev->dev, priv->wol_irq,
3973 bcmgenet_wol_isr, 0, dev->name, priv);
3974 if (!err)
3975 device_set_wakeup_capable(&pdev->dev, 1);
3976 }
3977
3978 /* Set the needed headroom to account for any possible
3979 * features enabling/disabling at runtime
3980 */
3981 dev->needed_headroom += 64;
3982
3983 priv->dev = dev;
3984 priv->pdev = pdev;
3985
3986 pdata = device_get_match_data(&pdev->dev);
3987 if (pdata) {
3988 priv->version = pdata->version;
3989 priv->dma_max_burst_length = pdata->dma_max_burst_length;
3990 } else {
3991 priv->version = pd->genet_version;
3992 priv->dma_max_burst_length = DMA_MAX_BURST_LENGTH;
3993 }
3994
3995 priv->clk = devm_clk_get_optional(&priv->pdev->dev, "enet");
3996 if (IS_ERR(priv->clk)) {
3997 dev_dbg(&priv->pdev->dev, "failed to get enet clock\n");
3998 err = PTR_ERR(priv->clk);
3999 goto err;
4000 }
4001
4002 err = clk_prepare_enable(priv->clk);
4003 if (err)
4004 goto err;
4005
4006 bcmgenet_set_hw_params(priv);
4007
4008 err = -EIO;
4009 if (priv->hw_params->flags & GENET_HAS_40BITS)
4010 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40));
4011 if (err)
4012 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
4013 if (err)
4014 goto err_clk_disable;
4015
4016 /* Mii wait queue */
4017 init_waitqueue_head(&priv->wq);
4018 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
4019 priv->rx_buf_len = RX_BUF_LENGTH;
4020 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
4021
4022 priv->clk_wol = devm_clk_get_optional(&priv->pdev->dev, "enet-wol");
4023 if (IS_ERR(priv->clk_wol)) {
4024 dev_dbg(&priv->pdev->dev, "failed to get enet-wol clock\n");
4025 err = PTR_ERR(priv->clk_wol);
4026 goto err_clk_disable;
4027 }
4028
4029 priv->clk_eee = devm_clk_get_optional(&priv->pdev->dev, "enet-eee");
4030 if (IS_ERR(priv->clk_eee)) {
4031 dev_dbg(&priv->pdev->dev, "failed to get enet-eee clock\n");
4032 err = PTR_ERR(priv->clk_eee);
4033 goto err_clk_disable;
4034 }
4035
4036 /* If this is an internal GPHY, power it on now, before UniMAC is
4037 * brought out of reset as absolutely no UniMAC activity is allowed
4038 */
4039 if (device_get_phy_mode(&pdev->dev) == PHY_INTERFACE_MODE_INTERNAL)
4040 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
4041
4042 if (pd && !IS_ERR_OR_NULL(pd->mac_address))
4043 ether_addr_copy(dev->dev_addr, pd->mac_address);
4044 else
4045 if (!device_get_mac_address(&pdev->dev, dev->dev_addr, ETH_ALEN))
4046 if (has_acpi_companion(&pdev->dev))
4047 bcmgenet_get_hw_addr(priv, dev->dev_addr);
4048
4049 if (!is_valid_ether_addr(dev->dev_addr)) {
4050 dev_warn(&pdev->dev, "using random Ethernet MAC\n");
4051 eth_hw_addr_random(dev);
4052 }
4053
4054 reset_umac(priv);
4055
4056 err = bcmgenet_mii_init(dev);
4057 if (err)
4058 goto err_clk_disable;
4059
4060 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues
4061 * just the ring 16 descriptor based TX
4062 */
4063 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
4064 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
4065
4066 /* Set default coalescing parameters */
4067 for (i = 0; i < priv->hw_params->rx_queues; i++)
4068 priv->rx_rings[i].rx_max_coalesced_frames = 1;
4069 priv->rx_rings[DESC_INDEX].rx_max_coalesced_frames = 1;
4070
4071 /* libphy will determine the link state */
4072 netif_carrier_off(dev);
4073
4074 /* Turn off the main clock, WOL clock is handled separately */
4075 clk_disable_unprepare(priv->clk);
4076
4077 err = register_netdev(dev);
4078 if (err) {
4079 bcmgenet_mii_exit(dev);
4080 goto err;
4081 }
4082
4083 return err;
4084
4085 err_clk_disable:
4086 clk_disable_unprepare(priv->clk);
4087 err:
4088 free_netdev(dev);
4089 return err;
4090 }
4091
4092 static int bcmgenet_remove(struct platform_device *pdev)
4093 {
4094 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
4095
4096 dev_set_drvdata(&pdev->dev, NULL);
4097 unregister_netdev(priv->dev);
4098 bcmgenet_mii_exit(priv->dev);
4099 free_netdev(priv->dev);
4100
4101 return 0;
4102 }
4103
4104 static void bcmgenet_shutdown(struct platform_device *pdev)
4105 {
4106 bcmgenet_remove(pdev);
4107 }
4108
4109 #ifdef CONFIG_PM_SLEEP
4110 static int bcmgenet_resume_noirq(struct device *d)
4111 {
4112 struct net_device *dev = dev_get_drvdata(d);
4113 struct bcmgenet_priv *priv = netdev_priv(dev);
4114 int ret;
4115 u32 reg;
4116
4117 if (!netif_running(dev))
4118 return 0;
4119
4120 /* Turn on the clock */
4121 ret = clk_prepare_enable(priv->clk);
4122 if (ret)
4123 return ret;
4124
4125 if (device_may_wakeup(d) && priv->wolopts) {
4126 /* Account for Wake-on-LAN events and clear those events
4127 * (Some devices need more time between enabling the clocks
4128 * and the interrupt register reflecting the wake event so
4129 * read the register twice)
4130 */
4131 reg = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT);
4132 reg = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT);
4133 if (reg & UMAC_IRQ_WAKE_EVENT)
4134 pm_wakeup_event(&priv->pdev->dev, 0);
4135 }
4136
4137 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_WAKE_EVENT, INTRL2_CPU_CLEAR);
4138
4139 return 0;
4140 }
4141
4142 static int bcmgenet_resume(struct device *d)
4143 {
4144 struct net_device *dev = dev_get_drvdata(d);
4145 struct bcmgenet_priv *priv = netdev_priv(dev);
4146 struct bcmgenet_rxnfc_rule *rule;
4147 unsigned long dma_ctrl;
4148 int ret;
4149
4150 if (!netif_running(dev))
4151 return 0;
4152
4153 /* From WOL-enabled suspend, switch to regular clock */
4154 if (device_may_wakeup(d) && priv->wolopts)
4155 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
4156
4157 /* If this is an internal GPHY, power it back on now, before UniMAC is
4158 * brought out of reset as absolutely no UniMAC activity is allowed
4159 */
4160 if (priv->internal_phy)
4161 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
4162
4163 bcmgenet_umac_reset(priv);
4164
4165 init_umac(priv);
4166
4167 phy_init_hw(dev->phydev);
4168
4169 /* Speed settings must be restored */
4170 genphy_config_aneg(dev->phydev);
4171 bcmgenet_mii_config(priv->dev, false);
4172
4173 /* Restore enabled features */
4174 bcmgenet_set_features(dev, dev->features);
4175
4176 bcmgenet_set_hw_addr(priv, dev->dev_addr);
4177
4178 /* Restore hardware filters */
4179 bcmgenet_hfb_clear(priv);
4180 list_for_each_entry(rule, &priv->rxnfc_list, list)
4181 if (rule->state != BCMGENET_RXNFC_STATE_UNUSED)
4182 bcmgenet_hfb_create_rxnfc_filter(priv, rule);
4183
4184 /* Disable RX/TX DMA and flush TX queues */
4185 dma_ctrl = bcmgenet_dma_disable(priv);
4186
4187 /* Reinitialize TDMA and RDMA and SW housekeeping */
4188 ret = bcmgenet_init_dma(priv);
4189 if (ret) {
4190 netdev_err(dev, "failed to initialize DMA\n");
4191 goto out_clk_disable;
4192 }
4193
4194 /* Always enable ring 16 - descriptor ring */
4195 bcmgenet_enable_dma(priv, dma_ctrl);
4196
4197 if (!device_may_wakeup(d))
4198 phy_resume(dev->phydev);
4199
4200 if (priv->eee.eee_enabled)
4201 bcmgenet_eee_enable_set(dev, true);
4202
4203 bcmgenet_netif_start(dev);
4204
4205 netif_device_attach(dev);
4206
4207 return 0;
4208
4209 out_clk_disable:
4210 if (priv->internal_phy)
4211 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
4212 clk_disable_unprepare(priv->clk);
4213 return ret;
4214 }
4215
4216 static int bcmgenet_suspend(struct device *d)
4217 {
4218 struct net_device *dev = dev_get_drvdata(d);
4219 struct bcmgenet_priv *priv = netdev_priv(dev);
4220
4221 if (!netif_running(dev))
4222 return 0;
4223
4224 netif_device_detach(dev);
4225
4226 bcmgenet_netif_stop(dev);
4227
4228 if (!device_may_wakeup(d))
4229 phy_suspend(dev->phydev);
4230
4231 /* Disable filtering */
4232 bcmgenet_hfb_reg_writel(priv, 0, HFB_CTRL);
4233
4234 return 0;
4235 }
4236
4237 static int bcmgenet_suspend_noirq(struct device *d)
4238 {
4239 struct net_device *dev = dev_get_drvdata(d);
4240 struct bcmgenet_priv *priv = netdev_priv(dev);
4241 int ret = 0;
4242
4243 if (!netif_running(dev))
4244 return 0;
4245
4246 /* Prepare the device for Wake-on-LAN and switch to the slow clock */
4247 if (device_may_wakeup(d) && priv->wolopts)
4248 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
4249 else if (priv->internal_phy)
4250 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
4251
4252 /* Let the framework handle resumption and leave the clocks on */
4253 if (ret)
4254 return ret;
4255
4256 /* Turn off the clocks */
4257 clk_disable_unprepare(priv->clk);
4258
4259 return 0;
4260 }
4261 #else
4262 #define bcmgenet_suspend NULL
4263 #define bcmgenet_suspend_noirq NULL
4264 #define bcmgenet_resume NULL
4265 #define bcmgenet_resume_noirq NULL
4266 #endif /* CONFIG_PM_SLEEP */
4267
4268 static const struct dev_pm_ops bcmgenet_pm_ops = {
4269 .suspend = bcmgenet_suspend,
4270 .suspend_noirq = bcmgenet_suspend_noirq,
4271 .resume = bcmgenet_resume,
4272 .resume_noirq = bcmgenet_resume_noirq,
4273 };
4274
4275 static const struct acpi_device_id genet_acpi_match[] = {
4276 { "BCM6E4E", (kernel_ulong_t)&bcm2711_plat_data },
4277 { },
4278 };
4279 MODULE_DEVICE_TABLE(acpi, genet_acpi_match);
4280
4281 static struct platform_driver bcmgenet_driver = {
4282 .probe = bcmgenet_probe,
4283 .remove = bcmgenet_remove,
4284 .shutdown = bcmgenet_shutdown,
4285 .driver = {
4286 .name = "bcmgenet",
4287 .of_match_table = bcmgenet_match,
4288 .pm = &bcmgenet_pm_ops,
4289 .acpi_match_table = genet_acpi_match,
4290 },
4291 };
4292 module_platform_driver(bcmgenet_driver);
4293
4294 MODULE_AUTHOR("Broadcom Corporation");
4295 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
4296 MODULE_ALIAS("platform:bcmgenet");
4297 MODULE_LICENSE("GPL");
4298 MODULE_SOFTDEP("pre: mdio-bcm-unimac");
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