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[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / broadcom / genet / bcmgenet.c
1 /*
2 * Broadcom GENET (Gigabit Ethernet) controller driver
3 *
4 * Copyright (c) 2014-2017 Broadcom
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #define pr_fmt(fmt) "bcmgenet: " fmt
12
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/sched.h>
16 #include <linux/types.h>
17 #include <linux/fcntl.h>
18 #include <linux/interrupt.h>
19 #include <linux/string.h>
20 #include <linux/if_ether.h>
21 #include <linux/init.h>
22 #include <linux/errno.h>
23 #include <linux/delay.h>
24 #include <linux/platform_device.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm.h>
27 #include <linux/clk.h>
28 #include <linux/of.h>
29 #include <linux/of_address.h>
30 #include <linux/of_irq.h>
31 #include <linux/of_net.h>
32 #include <linux/of_platform.h>
33 #include <net/arp.h>
34
35 #include <linux/mii.h>
36 #include <linux/ethtool.h>
37 #include <linux/netdevice.h>
38 #include <linux/inetdevice.h>
39 #include <linux/etherdevice.h>
40 #include <linux/skbuff.h>
41 #include <linux/in.h>
42 #include <linux/ip.h>
43 #include <linux/ipv6.h>
44 #include <linux/phy.h>
45 #include <linux/platform_data/bcmgenet.h>
46
47 #include <asm/unaligned.h>
48
49 #include "bcmgenet.h"
50
51 /* Maximum number of hardware queues, downsized if needed */
52 #define GENET_MAX_MQ_CNT 4
53
54 /* Default highest priority queue for multi queue support */
55 #define GENET_Q0_PRIORITY 0
56
57 #define GENET_Q16_RX_BD_CNT \
58 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q)
59 #define GENET_Q16_TX_BD_CNT \
60 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q)
61
62 #define RX_BUF_LENGTH 2048
63 #define SKB_ALIGNMENT 32
64
65 /* Tx/Rx DMA register offset, skip 256 descriptors */
66 #define WORDS_PER_BD(p) (p->hw_params->words_per_bd)
67 #define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32))
68
69 #define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \
70 TOTAL_DESC * DMA_DESC_SIZE)
71
72 #define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \
73 TOTAL_DESC * DMA_DESC_SIZE)
74
75 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
76 void __iomem *d, u32 value)
77 {
78 __raw_writel(value, d + DMA_DESC_LENGTH_STATUS);
79 }
80
81 static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
82 void __iomem *d)
83 {
84 return __raw_readl(d + DMA_DESC_LENGTH_STATUS);
85 }
86
87 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
88 void __iomem *d,
89 dma_addr_t addr)
90 {
91 __raw_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
92
93 /* Register writes to GISB bus can take couple hundred nanoseconds
94 * and are done for each packet, save these expensive writes unless
95 * the platform is explicitly configured for 64-bits/LPAE.
96 */
97 #ifdef CONFIG_PHYS_ADDR_T_64BIT
98 if (priv->hw_params->flags & GENET_HAS_40BITS)
99 __raw_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
100 #endif
101 }
102
103 /* Combined address + length/status setter */
104 static inline void dmadesc_set(struct bcmgenet_priv *priv,
105 void __iomem *d, dma_addr_t addr, u32 val)
106 {
107 dmadesc_set_addr(priv, d, addr);
108 dmadesc_set_length_status(priv, d, val);
109 }
110
111 static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
112 void __iomem *d)
113 {
114 dma_addr_t addr;
115
116 addr = __raw_readl(d + DMA_DESC_ADDRESS_LO);
117
118 /* Register writes to GISB bus can take couple hundred nanoseconds
119 * and are done for each packet, save these expensive writes unless
120 * the platform is explicitly configured for 64-bits/LPAE.
121 */
122 #ifdef CONFIG_PHYS_ADDR_T_64BIT
123 if (priv->hw_params->flags & GENET_HAS_40BITS)
124 addr |= (u64)__raw_readl(d + DMA_DESC_ADDRESS_HI) << 32;
125 #endif
126 return addr;
127 }
128
129 #define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x"
130
131 #define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
132 NETIF_MSG_LINK)
133
134 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
135 {
136 if (GENET_IS_V1(priv))
137 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
138 else
139 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
140 }
141
142 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
143 {
144 if (GENET_IS_V1(priv))
145 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
146 else
147 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
148 }
149
150 /* These macros are defined to deal with register map change
151 * between GENET1.1 and GENET2. Only those currently being used
152 * by driver are defined.
153 */
154 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
155 {
156 if (GENET_IS_V1(priv))
157 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
158 else
159 return __raw_readl(priv->base +
160 priv->hw_params->tbuf_offset + TBUF_CTRL);
161 }
162
163 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
164 {
165 if (GENET_IS_V1(priv))
166 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
167 else
168 __raw_writel(val, priv->base +
169 priv->hw_params->tbuf_offset + TBUF_CTRL);
170 }
171
172 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
173 {
174 if (GENET_IS_V1(priv))
175 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
176 else
177 return __raw_readl(priv->base +
178 priv->hw_params->tbuf_offset + TBUF_BP_MC);
179 }
180
181 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
182 {
183 if (GENET_IS_V1(priv))
184 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
185 else
186 __raw_writel(val, priv->base +
187 priv->hw_params->tbuf_offset + TBUF_BP_MC);
188 }
189
190 /* RX/TX DMA register accessors */
191 enum dma_reg {
192 DMA_RING_CFG = 0,
193 DMA_CTRL,
194 DMA_STATUS,
195 DMA_SCB_BURST_SIZE,
196 DMA_ARB_CTRL,
197 DMA_PRIORITY_0,
198 DMA_PRIORITY_1,
199 DMA_PRIORITY_2,
200 DMA_INDEX2RING_0,
201 DMA_INDEX2RING_1,
202 DMA_INDEX2RING_2,
203 DMA_INDEX2RING_3,
204 DMA_INDEX2RING_4,
205 DMA_INDEX2RING_5,
206 DMA_INDEX2RING_6,
207 DMA_INDEX2RING_7,
208 DMA_RING0_TIMEOUT,
209 DMA_RING1_TIMEOUT,
210 DMA_RING2_TIMEOUT,
211 DMA_RING3_TIMEOUT,
212 DMA_RING4_TIMEOUT,
213 DMA_RING5_TIMEOUT,
214 DMA_RING6_TIMEOUT,
215 DMA_RING7_TIMEOUT,
216 DMA_RING8_TIMEOUT,
217 DMA_RING9_TIMEOUT,
218 DMA_RING10_TIMEOUT,
219 DMA_RING11_TIMEOUT,
220 DMA_RING12_TIMEOUT,
221 DMA_RING13_TIMEOUT,
222 DMA_RING14_TIMEOUT,
223 DMA_RING15_TIMEOUT,
224 DMA_RING16_TIMEOUT,
225 };
226
227 static const u8 bcmgenet_dma_regs_v3plus[] = {
228 [DMA_RING_CFG] = 0x00,
229 [DMA_CTRL] = 0x04,
230 [DMA_STATUS] = 0x08,
231 [DMA_SCB_BURST_SIZE] = 0x0C,
232 [DMA_ARB_CTRL] = 0x2C,
233 [DMA_PRIORITY_0] = 0x30,
234 [DMA_PRIORITY_1] = 0x34,
235 [DMA_PRIORITY_2] = 0x38,
236 [DMA_RING0_TIMEOUT] = 0x2C,
237 [DMA_RING1_TIMEOUT] = 0x30,
238 [DMA_RING2_TIMEOUT] = 0x34,
239 [DMA_RING3_TIMEOUT] = 0x38,
240 [DMA_RING4_TIMEOUT] = 0x3c,
241 [DMA_RING5_TIMEOUT] = 0x40,
242 [DMA_RING6_TIMEOUT] = 0x44,
243 [DMA_RING7_TIMEOUT] = 0x48,
244 [DMA_RING8_TIMEOUT] = 0x4c,
245 [DMA_RING9_TIMEOUT] = 0x50,
246 [DMA_RING10_TIMEOUT] = 0x54,
247 [DMA_RING11_TIMEOUT] = 0x58,
248 [DMA_RING12_TIMEOUT] = 0x5c,
249 [DMA_RING13_TIMEOUT] = 0x60,
250 [DMA_RING14_TIMEOUT] = 0x64,
251 [DMA_RING15_TIMEOUT] = 0x68,
252 [DMA_RING16_TIMEOUT] = 0x6C,
253 [DMA_INDEX2RING_0] = 0x70,
254 [DMA_INDEX2RING_1] = 0x74,
255 [DMA_INDEX2RING_2] = 0x78,
256 [DMA_INDEX2RING_3] = 0x7C,
257 [DMA_INDEX2RING_4] = 0x80,
258 [DMA_INDEX2RING_5] = 0x84,
259 [DMA_INDEX2RING_6] = 0x88,
260 [DMA_INDEX2RING_7] = 0x8C,
261 };
262
263 static const u8 bcmgenet_dma_regs_v2[] = {
264 [DMA_RING_CFG] = 0x00,
265 [DMA_CTRL] = 0x04,
266 [DMA_STATUS] = 0x08,
267 [DMA_SCB_BURST_SIZE] = 0x0C,
268 [DMA_ARB_CTRL] = 0x30,
269 [DMA_PRIORITY_0] = 0x34,
270 [DMA_PRIORITY_1] = 0x38,
271 [DMA_PRIORITY_2] = 0x3C,
272 [DMA_RING0_TIMEOUT] = 0x2C,
273 [DMA_RING1_TIMEOUT] = 0x30,
274 [DMA_RING2_TIMEOUT] = 0x34,
275 [DMA_RING3_TIMEOUT] = 0x38,
276 [DMA_RING4_TIMEOUT] = 0x3c,
277 [DMA_RING5_TIMEOUT] = 0x40,
278 [DMA_RING6_TIMEOUT] = 0x44,
279 [DMA_RING7_TIMEOUT] = 0x48,
280 [DMA_RING8_TIMEOUT] = 0x4c,
281 [DMA_RING9_TIMEOUT] = 0x50,
282 [DMA_RING10_TIMEOUT] = 0x54,
283 [DMA_RING11_TIMEOUT] = 0x58,
284 [DMA_RING12_TIMEOUT] = 0x5c,
285 [DMA_RING13_TIMEOUT] = 0x60,
286 [DMA_RING14_TIMEOUT] = 0x64,
287 [DMA_RING15_TIMEOUT] = 0x68,
288 [DMA_RING16_TIMEOUT] = 0x6C,
289 };
290
291 static const u8 bcmgenet_dma_regs_v1[] = {
292 [DMA_CTRL] = 0x00,
293 [DMA_STATUS] = 0x04,
294 [DMA_SCB_BURST_SIZE] = 0x0C,
295 [DMA_ARB_CTRL] = 0x30,
296 [DMA_PRIORITY_0] = 0x34,
297 [DMA_PRIORITY_1] = 0x38,
298 [DMA_PRIORITY_2] = 0x3C,
299 [DMA_RING0_TIMEOUT] = 0x2C,
300 [DMA_RING1_TIMEOUT] = 0x30,
301 [DMA_RING2_TIMEOUT] = 0x34,
302 [DMA_RING3_TIMEOUT] = 0x38,
303 [DMA_RING4_TIMEOUT] = 0x3c,
304 [DMA_RING5_TIMEOUT] = 0x40,
305 [DMA_RING6_TIMEOUT] = 0x44,
306 [DMA_RING7_TIMEOUT] = 0x48,
307 [DMA_RING8_TIMEOUT] = 0x4c,
308 [DMA_RING9_TIMEOUT] = 0x50,
309 [DMA_RING10_TIMEOUT] = 0x54,
310 [DMA_RING11_TIMEOUT] = 0x58,
311 [DMA_RING12_TIMEOUT] = 0x5c,
312 [DMA_RING13_TIMEOUT] = 0x60,
313 [DMA_RING14_TIMEOUT] = 0x64,
314 [DMA_RING15_TIMEOUT] = 0x68,
315 [DMA_RING16_TIMEOUT] = 0x6C,
316 };
317
318 /* Set at runtime once bcmgenet version is known */
319 static const u8 *bcmgenet_dma_regs;
320
321 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
322 {
323 return netdev_priv(dev_get_drvdata(dev));
324 }
325
326 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
327 enum dma_reg r)
328 {
329 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
330 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
331 }
332
333 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
334 u32 val, enum dma_reg r)
335 {
336 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
337 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
338 }
339
340 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
341 enum dma_reg r)
342 {
343 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
344 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
345 }
346
347 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
348 u32 val, enum dma_reg r)
349 {
350 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
351 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
352 }
353
354 /* RDMA/TDMA ring registers and accessors
355 * we merge the common fields and just prefix with T/D the registers
356 * having different meaning depending on the direction
357 */
358 enum dma_ring_reg {
359 TDMA_READ_PTR = 0,
360 RDMA_WRITE_PTR = TDMA_READ_PTR,
361 TDMA_READ_PTR_HI,
362 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
363 TDMA_CONS_INDEX,
364 RDMA_PROD_INDEX = TDMA_CONS_INDEX,
365 TDMA_PROD_INDEX,
366 RDMA_CONS_INDEX = TDMA_PROD_INDEX,
367 DMA_RING_BUF_SIZE,
368 DMA_START_ADDR,
369 DMA_START_ADDR_HI,
370 DMA_END_ADDR,
371 DMA_END_ADDR_HI,
372 DMA_MBUF_DONE_THRESH,
373 TDMA_FLOW_PERIOD,
374 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
375 TDMA_WRITE_PTR,
376 RDMA_READ_PTR = TDMA_WRITE_PTR,
377 TDMA_WRITE_PTR_HI,
378 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
379 };
380
381 /* GENET v4 supports 40-bits pointer addressing
382 * for obvious reasons the LO and HI word parts
383 * are contiguous, but this offsets the other
384 * registers.
385 */
386 static const u8 genet_dma_ring_regs_v4[] = {
387 [TDMA_READ_PTR] = 0x00,
388 [TDMA_READ_PTR_HI] = 0x04,
389 [TDMA_CONS_INDEX] = 0x08,
390 [TDMA_PROD_INDEX] = 0x0C,
391 [DMA_RING_BUF_SIZE] = 0x10,
392 [DMA_START_ADDR] = 0x14,
393 [DMA_START_ADDR_HI] = 0x18,
394 [DMA_END_ADDR] = 0x1C,
395 [DMA_END_ADDR_HI] = 0x20,
396 [DMA_MBUF_DONE_THRESH] = 0x24,
397 [TDMA_FLOW_PERIOD] = 0x28,
398 [TDMA_WRITE_PTR] = 0x2C,
399 [TDMA_WRITE_PTR_HI] = 0x30,
400 };
401
402 static const u8 genet_dma_ring_regs_v123[] = {
403 [TDMA_READ_PTR] = 0x00,
404 [TDMA_CONS_INDEX] = 0x04,
405 [TDMA_PROD_INDEX] = 0x08,
406 [DMA_RING_BUF_SIZE] = 0x0C,
407 [DMA_START_ADDR] = 0x10,
408 [DMA_END_ADDR] = 0x14,
409 [DMA_MBUF_DONE_THRESH] = 0x18,
410 [TDMA_FLOW_PERIOD] = 0x1C,
411 [TDMA_WRITE_PTR] = 0x20,
412 };
413
414 /* Set at runtime once GENET version is known */
415 static const u8 *genet_dma_ring_regs;
416
417 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
418 unsigned int ring,
419 enum dma_ring_reg r)
420 {
421 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
422 (DMA_RING_SIZE * ring) +
423 genet_dma_ring_regs[r]);
424 }
425
426 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
427 unsigned int ring, u32 val,
428 enum dma_ring_reg r)
429 {
430 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
431 (DMA_RING_SIZE * ring) +
432 genet_dma_ring_regs[r]);
433 }
434
435 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
436 unsigned int ring,
437 enum dma_ring_reg r)
438 {
439 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
440 (DMA_RING_SIZE * ring) +
441 genet_dma_ring_regs[r]);
442 }
443
444 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
445 unsigned int ring, u32 val,
446 enum dma_ring_reg r)
447 {
448 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
449 (DMA_RING_SIZE * ring) +
450 genet_dma_ring_regs[r]);
451 }
452
453 static int bcmgenet_begin(struct net_device *dev)
454 {
455 struct bcmgenet_priv *priv = netdev_priv(dev);
456
457 /* Turn on the clock */
458 return clk_prepare_enable(priv->clk);
459 }
460
461 static void bcmgenet_complete(struct net_device *dev)
462 {
463 struct bcmgenet_priv *priv = netdev_priv(dev);
464
465 /* Turn off the clock */
466 clk_disable_unprepare(priv->clk);
467 }
468
469 static int bcmgenet_get_link_ksettings(struct net_device *dev,
470 struct ethtool_link_ksettings *cmd)
471 {
472 struct bcmgenet_priv *priv = netdev_priv(dev);
473
474 if (!netif_running(dev))
475 return -EINVAL;
476
477 if (!priv->phydev)
478 return -ENODEV;
479
480 phy_ethtool_ksettings_get(priv->phydev, cmd);
481
482 return 0;
483 }
484
485 static int bcmgenet_set_link_ksettings(struct net_device *dev,
486 const struct ethtool_link_ksettings *cmd)
487 {
488 struct bcmgenet_priv *priv = netdev_priv(dev);
489
490 if (!netif_running(dev))
491 return -EINVAL;
492
493 if (!priv->phydev)
494 return -ENODEV;
495
496 return phy_ethtool_ksettings_set(priv->phydev, cmd);
497 }
498
499 static int bcmgenet_set_rx_csum(struct net_device *dev,
500 netdev_features_t wanted)
501 {
502 struct bcmgenet_priv *priv = netdev_priv(dev);
503 u32 rbuf_chk_ctrl;
504 bool rx_csum_en;
505
506 rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
507
508 rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
509
510 /* enable rx checksumming */
511 if (rx_csum_en)
512 rbuf_chk_ctrl |= RBUF_RXCHK_EN;
513 else
514 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
515 priv->desc_rxchk_en = rx_csum_en;
516
517 /* If UniMAC forwards CRC, we need to skip over it to get
518 * a valid CHK bit to be set in the per-packet status word
519 */
520 if (rx_csum_en && priv->crc_fwd_en)
521 rbuf_chk_ctrl |= RBUF_SKIP_FCS;
522 else
523 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
524
525 bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
526
527 return 0;
528 }
529
530 static int bcmgenet_set_tx_csum(struct net_device *dev,
531 netdev_features_t wanted)
532 {
533 struct bcmgenet_priv *priv = netdev_priv(dev);
534 bool desc_64b_en;
535 u32 tbuf_ctrl, rbuf_ctrl;
536
537 tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
538 rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
539
540 desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
541
542 /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
543 if (desc_64b_en) {
544 tbuf_ctrl |= RBUF_64B_EN;
545 rbuf_ctrl |= RBUF_64B_EN;
546 } else {
547 tbuf_ctrl &= ~RBUF_64B_EN;
548 rbuf_ctrl &= ~RBUF_64B_EN;
549 }
550 priv->desc_64b_en = desc_64b_en;
551
552 bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
553 bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
554
555 return 0;
556 }
557
558 static int bcmgenet_set_features(struct net_device *dev,
559 netdev_features_t features)
560 {
561 netdev_features_t changed = features ^ dev->features;
562 netdev_features_t wanted = dev->wanted_features;
563 int ret = 0;
564
565 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
566 ret = bcmgenet_set_tx_csum(dev, wanted);
567 if (changed & (NETIF_F_RXCSUM))
568 ret = bcmgenet_set_rx_csum(dev, wanted);
569
570 return ret;
571 }
572
573 static u32 bcmgenet_get_msglevel(struct net_device *dev)
574 {
575 struct bcmgenet_priv *priv = netdev_priv(dev);
576
577 return priv->msg_enable;
578 }
579
580 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
581 {
582 struct bcmgenet_priv *priv = netdev_priv(dev);
583
584 priv->msg_enable = level;
585 }
586
587 static int bcmgenet_get_coalesce(struct net_device *dev,
588 struct ethtool_coalesce *ec)
589 {
590 struct bcmgenet_priv *priv = netdev_priv(dev);
591
592 ec->tx_max_coalesced_frames =
593 bcmgenet_tdma_ring_readl(priv, DESC_INDEX,
594 DMA_MBUF_DONE_THRESH);
595 ec->rx_max_coalesced_frames =
596 bcmgenet_rdma_ring_readl(priv, DESC_INDEX,
597 DMA_MBUF_DONE_THRESH);
598 ec->rx_coalesce_usecs =
599 bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT) * 8192 / 1000;
600
601 return 0;
602 }
603
604 static int bcmgenet_set_coalesce(struct net_device *dev,
605 struct ethtool_coalesce *ec)
606 {
607 struct bcmgenet_priv *priv = netdev_priv(dev);
608 unsigned int i;
609 u32 reg;
610
611 /* Base system clock is 125Mhz, DMA timeout is this reference clock
612 * divided by 1024, which yields roughly 8.192us, our maximum value
613 * has to fit in the DMA_TIMEOUT_MASK (16 bits)
614 */
615 if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
616 ec->tx_max_coalesced_frames == 0 ||
617 ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
618 ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1)
619 return -EINVAL;
620
621 if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0)
622 return -EINVAL;
623
624 /* GENET TDMA hardware does not support a configurable timeout, but will
625 * always generate an interrupt either after MBDONE packets have been
626 * transmitted, or when the ring is empty.
627 */
628 if (ec->tx_coalesce_usecs || ec->tx_coalesce_usecs_high ||
629 ec->tx_coalesce_usecs_irq || ec->tx_coalesce_usecs_low)
630 return -EOPNOTSUPP;
631
632 /* Program all TX queues with the same values, as there is no
633 * ethtool knob to do coalescing on a per-queue basis
634 */
635 for (i = 0; i < priv->hw_params->tx_queues; i++)
636 bcmgenet_tdma_ring_writel(priv, i,
637 ec->tx_max_coalesced_frames,
638 DMA_MBUF_DONE_THRESH);
639 bcmgenet_tdma_ring_writel(priv, DESC_INDEX,
640 ec->tx_max_coalesced_frames,
641 DMA_MBUF_DONE_THRESH);
642
643 for (i = 0; i < priv->hw_params->rx_queues; i++) {
644 bcmgenet_rdma_ring_writel(priv, i,
645 ec->rx_max_coalesced_frames,
646 DMA_MBUF_DONE_THRESH);
647
648 reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i);
649 reg &= ~DMA_TIMEOUT_MASK;
650 reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192);
651 bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i);
652 }
653
654 bcmgenet_rdma_ring_writel(priv, DESC_INDEX,
655 ec->rx_max_coalesced_frames,
656 DMA_MBUF_DONE_THRESH);
657
658 reg = bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT);
659 reg &= ~DMA_TIMEOUT_MASK;
660 reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192);
661 bcmgenet_rdma_writel(priv, reg, DMA_RING16_TIMEOUT);
662
663 return 0;
664 }
665
666 /* standard ethtool support functions. */
667 enum bcmgenet_stat_type {
668 BCMGENET_STAT_NETDEV = -1,
669 BCMGENET_STAT_MIB_RX,
670 BCMGENET_STAT_MIB_TX,
671 BCMGENET_STAT_RUNT,
672 BCMGENET_STAT_MISC,
673 BCMGENET_STAT_SOFT,
674 };
675
676 struct bcmgenet_stats {
677 char stat_string[ETH_GSTRING_LEN];
678 int stat_sizeof;
679 int stat_offset;
680 enum bcmgenet_stat_type type;
681 /* reg offset from UMAC base for misc counters */
682 u16 reg_offset;
683 };
684
685 #define STAT_NETDEV(m) { \
686 .stat_string = __stringify(m), \
687 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
688 .stat_offset = offsetof(struct net_device_stats, m), \
689 .type = BCMGENET_STAT_NETDEV, \
690 }
691
692 #define STAT_GENET_MIB(str, m, _type) { \
693 .stat_string = str, \
694 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
695 .stat_offset = offsetof(struct bcmgenet_priv, m), \
696 .type = _type, \
697 }
698
699 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
700 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
701 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
702 #define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT)
703
704 #define STAT_GENET_MISC(str, m, offset) { \
705 .stat_string = str, \
706 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
707 .stat_offset = offsetof(struct bcmgenet_priv, m), \
708 .type = BCMGENET_STAT_MISC, \
709 .reg_offset = offset, \
710 }
711
712 #define STAT_GENET_Q(num) \
713 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_packets", \
714 tx_rings[num].packets), \
715 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_bytes", \
716 tx_rings[num].bytes), \
717 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_bytes", \
718 rx_rings[num].bytes), \
719 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_packets", \
720 rx_rings[num].packets), \
721 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_errors", \
722 rx_rings[num].errors), \
723 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_dropped", \
724 rx_rings[num].dropped)
725
726 /* There is a 0xC gap between the end of RX and beginning of TX stats and then
727 * between the end of TX stats and the beginning of the RX RUNT
728 */
729 #define BCMGENET_STAT_OFFSET 0xc
730
731 /* Hardware counters must be kept in sync because the order/offset
732 * is important here (order in structure declaration = order in hardware)
733 */
734 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
735 /* general stats */
736 STAT_NETDEV(rx_packets),
737 STAT_NETDEV(tx_packets),
738 STAT_NETDEV(rx_bytes),
739 STAT_NETDEV(tx_bytes),
740 STAT_NETDEV(rx_errors),
741 STAT_NETDEV(tx_errors),
742 STAT_NETDEV(rx_dropped),
743 STAT_NETDEV(tx_dropped),
744 STAT_NETDEV(multicast),
745 /* UniMAC RSV counters */
746 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
747 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
748 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
749 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
750 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
751 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
752 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
753 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
754 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
755 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
756 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
757 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
758 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
759 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
760 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
761 STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
762 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
763 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
764 STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
765 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
766 STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
767 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
768 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
769 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
770 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
771 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
772 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
773 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
774 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
775 /* UniMAC TSV counters */
776 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
777 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
778 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
779 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
780 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
781 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
782 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
783 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
784 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
785 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
786 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
787 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
788 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
789 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
790 STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
791 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
792 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
793 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
794 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
795 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
796 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
797 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
798 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
799 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
800 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
801 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
802 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
803 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
804 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
805 /* UniMAC RUNT counters */
806 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
807 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
808 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
809 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
810 /* Misc UniMAC counters */
811 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
812 UMAC_RBUF_OVFL_CNT_V1),
813 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt,
814 UMAC_RBUF_ERR_CNT_V1),
815 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
816 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
817 STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed),
818 STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed),
819 /* Per TX queues */
820 STAT_GENET_Q(0),
821 STAT_GENET_Q(1),
822 STAT_GENET_Q(2),
823 STAT_GENET_Q(3),
824 STAT_GENET_Q(16),
825 };
826
827 #define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats)
828
829 static void bcmgenet_get_drvinfo(struct net_device *dev,
830 struct ethtool_drvinfo *info)
831 {
832 strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
833 strlcpy(info->version, "v2.0", sizeof(info->version));
834 }
835
836 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
837 {
838 switch (string_set) {
839 case ETH_SS_STATS:
840 return BCMGENET_STATS_LEN;
841 default:
842 return -EOPNOTSUPP;
843 }
844 }
845
846 static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
847 u8 *data)
848 {
849 int i;
850
851 switch (stringset) {
852 case ETH_SS_STATS:
853 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
854 memcpy(data + i * ETH_GSTRING_LEN,
855 bcmgenet_gstrings_stats[i].stat_string,
856 ETH_GSTRING_LEN);
857 }
858 break;
859 }
860 }
861
862 static u32 bcmgenet_update_stat_misc(struct bcmgenet_priv *priv, u16 offset)
863 {
864 u16 new_offset;
865 u32 val;
866
867 switch (offset) {
868 case UMAC_RBUF_OVFL_CNT_V1:
869 if (GENET_IS_V2(priv))
870 new_offset = RBUF_OVFL_CNT_V2;
871 else
872 new_offset = RBUF_OVFL_CNT_V3PLUS;
873
874 val = bcmgenet_rbuf_readl(priv, new_offset);
875 /* clear if overflowed */
876 if (val == ~0)
877 bcmgenet_rbuf_writel(priv, 0, new_offset);
878 break;
879 case UMAC_RBUF_ERR_CNT_V1:
880 if (GENET_IS_V2(priv))
881 new_offset = RBUF_ERR_CNT_V2;
882 else
883 new_offset = RBUF_ERR_CNT_V3PLUS;
884
885 val = bcmgenet_rbuf_readl(priv, new_offset);
886 /* clear if overflowed */
887 if (val == ~0)
888 bcmgenet_rbuf_writel(priv, 0, new_offset);
889 break;
890 default:
891 val = bcmgenet_umac_readl(priv, offset);
892 /* clear if overflowed */
893 if (val == ~0)
894 bcmgenet_umac_writel(priv, 0, offset);
895 break;
896 }
897
898 return val;
899 }
900
901 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
902 {
903 int i, j = 0;
904
905 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
906 const struct bcmgenet_stats *s;
907 u8 offset = 0;
908 u32 val = 0;
909 char *p;
910
911 s = &bcmgenet_gstrings_stats[i];
912 switch (s->type) {
913 case BCMGENET_STAT_NETDEV:
914 case BCMGENET_STAT_SOFT:
915 continue;
916 case BCMGENET_STAT_RUNT:
917 offset += BCMGENET_STAT_OFFSET;
918 /* fall through */
919 case BCMGENET_STAT_MIB_TX:
920 offset += BCMGENET_STAT_OFFSET;
921 /* fall through */
922 case BCMGENET_STAT_MIB_RX:
923 val = bcmgenet_umac_readl(priv,
924 UMAC_MIB_START + j + offset);
925 offset = 0; /* Reset Offset */
926 break;
927 case BCMGENET_STAT_MISC:
928 if (GENET_IS_V1(priv)) {
929 val = bcmgenet_umac_readl(priv, s->reg_offset);
930 /* clear if overflowed */
931 if (val == ~0)
932 bcmgenet_umac_writel(priv, 0,
933 s->reg_offset);
934 } else {
935 val = bcmgenet_update_stat_misc(priv,
936 s->reg_offset);
937 }
938 break;
939 }
940
941 j += s->stat_sizeof;
942 p = (char *)priv + s->stat_offset;
943 *(u32 *)p = val;
944 }
945 }
946
947 static void bcmgenet_get_ethtool_stats(struct net_device *dev,
948 struct ethtool_stats *stats,
949 u64 *data)
950 {
951 struct bcmgenet_priv *priv = netdev_priv(dev);
952 int i;
953
954 if (netif_running(dev))
955 bcmgenet_update_mib_counters(priv);
956
957 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
958 const struct bcmgenet_stats *s;
959 char *p;
960
961 s = &bcmgenet_gstrings_stats[i];
962 if (s->type == BCMGENET_STAT_NETDEV)
963 p = (char *)&dev->stats;
964 else
965 p = (char *)priv;
966 p += s->stat_offset;
967 if (sizeof(unsigned long) != sizeof(u32) &&
968 s->stat_sizeof == sizeof(unsigned long))
969 data[i] = *(unsigned long *)p;
970 else
971 data[i] = *(u32 *)p;
972 }
973 }
974
975 static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable)
976 {
977 struct bcmgenet_priv *priv = netdev_priv(dev);
978 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
979 u32 reg;
980
981 if (enable && !priv->clk_eee_enabled) {
982 clk_prepare_enable(priv->clk_eee);
983 priv->clk_eee_enabled = true;
984 }
985
986 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
987 if (enable)
988 reg |= EEE_EN;
989 else
990 reg &= ~EEE_EN;
991 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
992
993 /* Enable EEE and switch to a 27Mhz clock automatically */
994 reg = __raw_readl(priv->base + off);
995 if (enable)
996 reg |= TBUF_EEE_EN | TBUF_PM_EN;
997 else
998 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
999 __raw_writel(reg, priv->base + off);
1000
1001 /* Do the same for thing for RBUF */
1002 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
1003 if (enable)
1004 reg |= RBUF_EEE_EN | RBUF_PM_EN;
1005 else
1006 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
1007 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
1008
1009 if (!enable && priv->clk_eee_enabled) {
1010 clk_disable_unprepare(priv->clk_eee);
1011 priv->clk_eee_enabled = false;
1012 }
1013
1014 priv->eee.eee_enabled = enable;
1015 priv->eee.eee_active = enable;
1016 }
1017
1018 static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e)
1019 {
1020 struct bcmgenet_priv *priv = netdev_priv(dev);
1021 struct ethtool_eee *p = &priv->eee;
1022
1023 if (GENET_IS_V1(priv))
1024 return -EOPNOTSUPP;
1025
1026 e->eee_enabled = p->eee_enabled;
1027 e->eee_active = p->eee_active;
1028 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
1029
1030 return phy_ethtool_get_eee(priv->phydev, e);
1031 }
1032
1033 static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e)
1034 {
1035 struct bcmgenet_priv *priv = netdev_priv(dev);
1036 struct ethtool_eee *p = &priv->eee;
1037 int ret = 0;
1038
1039 if (GENET_IS_V1(priv))
1040 return -EOPNOTSUPP;
1041
1042 p->eee_enabled = e->eee_enabled;
1043
1044 if (!p->eee_enabled) {
1045 bcmgenet_eee_enable_set(dev, false);
1046 } else {
1047 ret = phy_init_eee(priv->phydev, 0);
1048 if (ret) {
1049 netif_err(priv, hw, dev, "EEE initialization failed\n");
1050 return ret;
1051 }
1052
1053 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
1054 bcmgenet_eee_enable_set(dev, true);
1055 }
1056
1057 return phy_ethtool_set_eee(priv->phydev, e);
1058 }
1059
1060 /* standard ethtool support functions. */
1061 static const struct ethtool_ops bcmgenet_ethtool_ops = {
1062 .begin = bcmgenet_begin,
1063 .complete = bcmgenet_complete,
1064 .get_strings = bcmgenet_get_strings,
1065 .get_sset_count = bcmgenet_get_sset_count,
1066 .get_ethtool_stats = bcmgenet_get_ethtool_stats,
1067 .get_drvinfo = bcmgenet_get_drvinfo,
1068 .get_link = ethtool_op_get_link,
1069 .get_msglevel = bcmgenet_get_msglevel,
1070 .set_msglevel = bcmgenet_set_msglevel,
1071 .get_wol = bcmgenet_get_wol,
1072 .set_wol = bcmgenet_set_wol,
1073 .get_eee = bcmgenet_get_eee,
1074 .set_eee = bcmgenet_set_eee,
1075 .nway_reset = phy_ethtool_nway_reset,
1076 .get_coalesce = bcmgenet_get_coalesce,
1077 .set_coalesce = bcmgenet_set_coalesce,
1078 .get_link_ksettings = bcmgenet_get_link_ksettings,
1079 .set_link_ksettings = bcmgenet_set_link_ksettings,
1080 };
1081
1082 /* Power down the unimac, based on mode. */
1083 static int bcmgenet_power_down(struct bcmgenet_priv *priv,
1084 enum bcmgenet_power_mode mode)
1085 {
1086 int ret = 0;
1087 u32 reg;
1088
1089 switch (mode) {
1090 case GENET_POWER_CABLE_SENSE:
1091 phy_detach(priv->phydev);
1092 break;
1093
1094 case GENET_POWER_WOL_MAGIC:
1095 ret = bcmgenet_wol_power_down_cfg(priv, mode);
1096 break;
1097
1098 case GENET_POWER_PASSIVE:
1099 /* Power down LED */
1100 if (priv->hw_params->flags & GENET_HAS_EXT) {
1101 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1102 if (GENET_IS_V5(priv))
1103 reg |= EXT_PWR_DOWN_PHY_EN |
1104 EXT_PWR_DOWN_PHY_RD |
1105 EXT_PWR_DOWN_PHY_SD |
1106 EXT_PWR_DOWN_PHY_RX |
1107 EXT_PWR_DOWN_PHY_TX |
1108 EXT_IDDQ_GLBL_PWR;
1109 else
1110 reg |= EXT_PWR_DOWN_PHY;
1111
1112 reg |= (EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
1113 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1114
1115 bcmgenet_phy_power_set(priv->dev, false);
1116 }
1117 break;
1118 default:
1119 break;
1120 }
1121
1122 return 0;
1123 }
1124
1125 static void bcmgenet_power_up(struct bcmgenet_priv *priv,
1126 enum bcmgenet_power_mode mode)
1127 {
1128 u32 reg;
1129
1130 if (!(priv->hw_params->flags & GENET_HAS_EXT))
1131 return;
1132
1133 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1134
1135 switch (mode) {
1136 case GENET_POWER_PASSIVE:
1137 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
1138 if (GENET_IS_V5(priv)) {
1139 reg &= ~(EXT_PWR_DOWN_PHY_EN |
1140 EXT_PWR_DOWN_PHY_RD |
1141 EXT_PWR_DOWN_PHY_SD |
1142 EXT_PWR_DOWN_PHY_RX |
1143 EXT_PWR_DOWN_PHY_TX |
1144 EXT_IDDQ_GLBL_PWR);
1145 reg |= EXT_PHY_RESET;
1146 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1147 mdelay(1);
1148
1149 reg &= ~EXT_PHY_RESET;
1150 } else {
1151 reg &= ~EXT_PWR_DOWN_PHY;
1152 reg |= EXT_PWR_DN_EN_LD;
1153 }
1154 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1155 bcmgenet_phy_power_set(priv->dev, true);
1156 bcmgenet_mii_reset(priv->dev);
1157 break;
1158
1159 case GENET_POWER_CABLE_SENSE:
1160 /* enable APD */
1161 if (!GENET_IS_V5(priv)) {
1162 reg |= EXT_PWR_DN_EN_LD;
1163 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1164 }
1165 break;
1166 case GENET_POWER_WOL_MAGIC:
1167 bcmgenet_wol_power_up_cfg(priv, mode);
1168 return;
1169 default:
1170 break;
1171 }
1172 }
1173
1174 /* ioctl handle special commands that are not present in ethtool. */
1175 static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1176 {
1177 struct bcmgenet_priv *priv = netdev_priv(dev);
1178
1179 if (!netif_running(dev))
1180 return -EINVAL;
1181
1182 if (!priv->phydev)
1183 return -ENODEV;
1184
1185 return phy_mii_ioctl(priv->phydev, rq, cmd);
1186 }
1187
1188 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
1189 struct bcmgenet_tx_ring *ring)
1190 {
1191 struct enet_cb *tx_cb_ptr;
1192
1193 tx_cb_ptr = ring->cbs;
1194 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1195
1196 /* Advancing local write pointer */
1197 if (ring->write_ptr == ring->end_ptr)
1198 ring->write_ptr = ring->cb_ptr;
1199 else
1200 ring->write_ptr++;
1201
1202 return tx_cb_ptr;
1203 }
1204
1205 /* Simple helper to free a control block's resources */
1206 static void bcmgenet_free_cb(struct enet_cb *cb)
1207 {
1208 dev_kfree_skb_any(cb->skb);
1209 cb->skb = NULL;
1210 dma_unmap_addr_set(cb, dma_addr, 0);
1211 }
1212
1213 static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring)
1214 {
1215 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1216 INTRL2_CPU_MASK_SET);
1217 }
1218
1219 static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring)
1220 {
1221 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1222 INTRL2_CPU_MASK_CLEAR);
1223 }
1224
1225 static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring)
1226 {
1227 bcmgenet_intrl2_1_writel(ring->priv,
1228 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1229 INTRL2_CPU_MASK_SET);
1230 }
1231
1232 static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring)
1233 {
1234 bcmgenet_intrl2_1_writel(ring->priv,
1235 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1236 INTRL2_CPU_MASK_CLEAR);
1237 }
1238
1239 static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring)
1240 {
1241 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1242 INTRL2_CPU_MASK_SET);
1243 }
1244
1245 static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring)
1246 {
1247 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1248 INTRL2_CPU_MASK_CLEAR);
1249 }
1250
1251 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring)
1252 {
1253 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1254 INTRL2_CPU_MASK_CLEAR);
1255 }
1256
1257 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring)
1258 {
1259 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1260 INTRL2_CPU_MASK_SET);
1261 }
1262
1263 /* Unlocked version of the reclaim routine */
1264 static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev,
1265 struct bcmgenet_tx_ring *ring)
1266 {
1267 struct bcmgenet_priv *priv = netdev_priv(dev);
1268 struct device *kdev = &priv->pdev->dev;
1269 struct enet_cb *tx_cb_ptr;
1270 unsigned int pkts_compl = 0;
1271 unsigned int bytes_compl = 0;
1272 unsigned int c_index;
1273 unsigned int txbds_ready;
1274 unsigned int txbds_processed = 0;
1275
1276 /* Clear status before servicing to reduce spurious interrupts */
1277 if (ring->index == DESC_INDEX)
1278 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_TXDMA_DONE,
1279 INTRL2_CPU_CLEAR);
1280 else
1281 bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
1282 INTRL2_CPU_CLEAR);
1283
1284 /* Compute how many buffers are transmitted since last xmit call */
1285 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX)
1286 & DMA_C_INDEX_MASK;
1287 txbds_ready = (c_index - ring->c_index) & DMA_C_INDEX_MASK;
1288
1289 netif_dbg(priv, tx_done, dev,
1290 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
1291 __func__, ring->index, ring->c_index, c_index, txbds_ready);
1292
1293 /* Reclaim transmitted buffers */
1294 while (txbds_processed < txbds_ready) {
1295 tx_cb_ptr = &priv->tx_cbs[ring->clean_ptr];
1296 if (tx_cb_ptr->skb) {
1297 pkts_compl++;
1298 bytes_compl += GENET_CB(tx_cb_ptr->skb)->bytes_sent;
1299 dma_unmap_single(kdev,
1300 dma_unmap_addr(tx_cb_ptr, dma_addr),
1301 dma_unmap_len(tx_cb_ptr, dma_len),
1302 DMA_TO_DEVICE);
1303 bcmgenet_free_cb(tx_cb_ptr);
1304 } else if (dma_unmap_addr(tx_cb_ptr, dma_addr)) {
1305 dma_unmap_page(kdev,
1306 dma_unmap_addr(tx_cb_ptr, dma_addr),
1307 dma_unmap_len(tx_cb_ptr, dma_len),
1308 DMA_TO_DEVICE);
1309 dma_unmap_addr_set(tx_cb_ptr, dma_addr, 0);
1310 }
1311
1312 txbds_processed++;
1313 if (likely(ring->clean_ptr < ring->end_ptr))
1314 ring->clean_ptr++;
1315 else
1316 ring->clean_ptr = ring->cb_ptr;
1317 }
1318
1319 ring->free_bds += txbds_processed;
1320 ring->c_index = c_index;
1321
1322 ring->packets += pkts_compl;
1323 ring->bytes += bytes_compl;
1324
1325 netdev_tx_completed_queue(netdev_get_tx_queue(dev, ring->queue),
1326 pkts_compl, bytes_compl);
1327
1328 return txbds_processed;
1329 }
1330
1331 static unsigned int bcmgenet_tx_reclaim(struct net_device *dev,
1332 struct bcmgenet_tx_ring *ring)
1333 {
1334 unsigned int released;
1335 unsigned long flags;
1336
1337 spin_lock_irqsave(&ring->lock, flags);
1338 released = __bcmgenet_tx_reclaim(dev, ring);
1339 spin_unlock_irqrestore(&ring->lock, flags);
1340
1341 return released;
1342 }
1343
1344 static int bcmgenet_tx_poll(struct napi_struct *napi, int budget)
1345 {
1346 struct bcmgenet_tx_ring *ring =
1347 container_of(napi, struct bcmgenet_tx_ring, napi);
1348 unsigned int work_done = 0;
1349 struct netdev_queue *txq;
1350 unsigned long flags;
1351
1352 spin_lock_irqsave(&ring->lock, flags);
1353 work_done = __bcmgenet_tx_reclaim(ring->priv->dev, ring);
1354 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
1355 txq = netdev_get_tx_queue(ring->priv->dev, ring->queue);
1356 netif_tx_wake_queue(txq);
1357 }
1358 spin_unlock_irqrestore(&ring->lock, flags);
1359
1360 if (work_done == 0) {
1361 napi_complete(napi);
1362 ring->int_enable(ring);
1363
1364 return 0;
1365 }
1366
1367 return budget;
1368 }
1369
1370 static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1371 {
1372 struct bcmgenet_priv *priv = netdev_priv(dev);
1373 int i;
1374
1375 if (netif_is_multiqueue(dev)) {
1376 for (i = 0; i < priv->hw_params->tx_queues; i++)
1377 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
1378 }
1379
1380 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
1381 }
1382
1383 /* Transmits a single SKB (either head of a fragment or a single SKB)
1384 * caller must hold priv->lock
1385 */
1386 static int bcmgenet_xmit_single(struct net_device *dev,
1387 struct sk_buff *skb,
1388 u16 dma_desc_flags,
1389 struct bcmgenet_tx_ring *ring)
1390 {
1391 struct bcmgenet_priv *priv = netdev_priv(dev);
1392 struct device *kdev = &priv->pdev->dev;
1393 struct enet_cb *tx_cb_ptr;
1394 unsigned int skb_len;
1395 dma_addr_t mapping;
1396 u32 length_status;
1397 int ret;
1398
1399 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1400
1401 if (unlikely(!tx_cb_ptr))
1402 BUG();
1403
1404 tx_cb_ptr->skb = skb;
1405
1406 skb_len = skb_headlen(skb);
1407
1408 mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE);
1409 ret = dma_mapping_error(kdev, mapping);
1410 if (ret) {
1411 priv->mib.tx_dma_failed++;
1412 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
1413 dev_kfree_skb(skb);
1414 return ret;
1415 }
1416
1417 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1418 dma_unmap_len_set(tx_cb_ptr, dma_len, skb_len);
1419 length_status = (skb_len << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1420 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT) |
1421 DMA_TX_APPEND_CRC;
1422
1423 if (skb->ip_summed == CHECKSUM_PARTIAL)
1424 length_status |= DMA_TX_DO_CSUM;
1425
1426 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, length_status);
1427
1428 return 0;
1429 }
1430
1431 /* Transmit a SKB fragment */
1432 static int bcmgenet_xmit_frag(struct net_device *dev,
1433 skb_frag_t *frag,
1434 u16 dma_desc_flags,
1435 struct bcmgenet_tx_ring *ring)
1436 {
1437 struct bcmgenet_priv *priv = netdev_priv(dev);
1438 struct device *kdev = &priv->pdev->dev;
1439 struct enet_cb *tx_cb_ptr;
1440 unsigned int frag_size;
1441 dma_addr_t mapping;
1442 int ret;
1443
1444 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1445
1446 if (unlikely(!tx_cb_ptr))
1447 BUG();
1448
1449 tx_cb_ptr->skb = NULL;
1450
1451 frag_size = skb_frag_size(frag);
1452
1453 mapping = skb_frag_dma_map(kdev, frag, 0, frag_size, DMA_TO_DEVICE);
1454 ret = dma_mapping_error(kdev, mapping);
1455 if (ret) {
1456 priv->mib.tx_dma_failed++;
1457 netif_err(priv, tx_err, dev, "%s: Tx DMA map failed\n",
1458 __func__);
1459 return ret;
1460 }
1461
1462 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1463 dma_unmap_len_set(tx_cb_ptr, dma_len, frag_size);
1464
1465 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping,
1466 (frag_size << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1467 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT));
1468
1469 return 0;
1470 }
1471
1472 /* Reallocate the SKB to put enough headroom in front of it and insert
1473 * the transmit checksum offsets in the descriptors
1474 */
1475 static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev,
1476 struct sk_buff *skb)
1477 {
1478 struct status_64 *status = NULL;
1479 struct sk_buff *new_skb;
1480 u16 offset;
1481 u8 ip_proto;
1482 u16 ip_ver;
1483 u32 tx_csum_info;
1484
1485 if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1486 /* If 64 byte status block enabled, must make sure skb has
1487 * enough headroom for us to insert 64B status block.
1488 */
1489 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1490 dev_kfree_skb(skb);
1491 if (!new_skb) {
1492 dev->stats.tx_dropped++;
1493 return NULL;
1494 }
1495 skb = new_skb;
1496 }
1497
1498 skb_push(skb, sizeof(*status));
1499 status = (struct status_64 *)skb->data;
1500
1501 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1502 ip_ver = htons(skb->protocol);
1503 switch (ip_ver) {
1504 case ETH_P_IP:
1505 ip_proto = ip_hdr(skb)->protocol;
1506 break;
1507 case ETH_P_IPV6:
1508 ip_proto = ipv6_hdr(skb)->nexthdr;
1509 break;
1510 default:
1511 return skb;
1512 }
1513
1514 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1515 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1516 (offset + skb->csum_offset);
1517
1518 /* Set the length valid bit for TCP and UDP and just set
1519 * the special UDP flag for IPv4, else just set to 0.
1520 */
1521 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1522 tx_csum_info |= STATUS_TX_CSUM_LV;
1523 if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
1524 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
1525 } else {
1526 tx_csum_info = 0;
1527 }
1528
1529 status->tx_csum_info = tx_csum_info;
1530 }
1531
1532 return skb;
1533 }
1534
1535 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1536 {
1537 struct bcmgenet_priv *priv = netdev_priv(dev);
1538 struct bcmgenet_tx_ring *ring = NULL;
1539 struct netdev_queue *txq;
1540 unsigned long flags = 0;
1541 int nr_frags, index;
1542 u16 dma_desc_flags;
1543 int ret;
1544 int i;
1545
1546 index = skb_get_queue_mapping(skb);
1547 /* Mapping strategy:
1548 * queue_mapping = 0, unclassified, packet xmited through ring16
1549 * queue_mapping = 1, goes to ring 0. (highest priority queue
1550 * queue_mapping = 2, goes to ring 1.
1551 * queue_mapping = 3, goes to ring 2.
1552 * queue_mapping = 4, goes to ring 3.
1553 */
1554 if (index == 0)
1555 index = DESC_INDEX;
1556 else
1557 index -= 1;
1558
1559 ring = &priv->tx_rings[index];
1560 txq = netdev_get_tx_queue(dev, ring->queue);
1561
1562 nr_frags = skb_shinfo(skb)->nr_frags;
1563
1564 spin_lock_irqsave(&ring->lock, flags);
1565 if (ring->free_bds <= (nr_frags + 1)) {
1566 if (!netif_tx_queue_stopped(txq)) {
1567 netif_tx_stop_queue(txq);
1568 netdev_err(dev,
1569 "%s: tx ring %d full when queue %d awake\n",
1570 __func__, index, ring->queue);
1571 }
1572 ret = NETDEV_TX_BUSY;
1573 goto out;
1574 }
1575
1576 if (skb_padto(skb, ETH_ZLEN)) {
1577 ret = NETDEV_TX_OK;
1578 goto out;
1579 }
1580
1581 /* Retain how many bytes will be sent on the wire, without TSB inserted
1582 * by transmit checksum offload
1583 */
1584 GENET_CB(skb)->bytes_sent = skb->len;
1585
1586 /* set the SKB transmit checksum */
1587 if (priv->desc_64b_en) {
1588 skb = bcmgenet_put_tx_csum(dev, skb);
1589 if (!skb) {
1590 ret = NETDEV_TX_OK;
1591 goto out;
1592 }
1593 }
1594
1595 dma_desc_flags = DMA_SOP;
1596 if (nr_frags == 0)
1597 dma_desc_flags |= DMA_EOP;
1598
1599 /* Transmit single SKB or head of fragment list */
1600 ret = bcmgenet_xmit_single(dev, skb, dma_desc_flags, ring);
1601 if (ret) {
1602 ret = NETDEV_TX_OK;
1603 goto out;
1604 }
1605
1606 /* xmit fragment */
1607 for (i = 0; i < nr_frags; i++) {
1608 ret = bcmgenet_xmit_frag(dev,
1609 &skb_shinfo(skb)->frags[i],
1610 (i == nr_frags - 1) ? DMA_EOP : 0,
1611 ring);
1612 if (ret) {
1613 ret = NETDEV_TX_OK;
1614 goto out;
1615 }
1616 }
1617
1618 skb_tx_timestamp(skb);
1619
1620 /* Decrement total BD count and advance our write pointer */
1621 ring->free_bds -= nr_frags + 1;
1622 ring->prod_index += nr_frags + 1;
1623 ring->prod_index &= DMA_P_INDEX_MASK;
1624
1625 netdev_tx_sent_queue(txq, GENET_CB(skb)->bytes_sent);
1626
1627 if (ring->free_bds <= (MAX_SKB_FRAGS + 1))
1628 netif_tx_stop_queue(txq);
1629
1630 if (!skb->xmit_more || netif_xmit_stopped(txq))
1631 /* Packets are ready, update producer index */
1632 bcmgenet_tdma_ring_writel(priv, ring->index,
1633 ring->prod_index, TDMA_PROD_INDEX);
1634 out:
1635 spin_unlock_irqrestore(&ring->lock, flags);
1636
1637 return ret;
1638 }
1639
1640 static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv,
1641 struct enet_cb *cb)
1642 {
1643 struct device *kdev = &priv->pdev->dev;
1644 struct sk_buff *skb;
1645 struct sk_buff *rx_skb;
1646 dma_addr_t mapping;
1647
1648 /* Allocate a new Rx skb */
1649 skb = netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT);
1650 if (!skb) {
1651 priv->mib.alloc_rx_buff_failed++;
1652 netif_err(priv, rx_err, priv->dev,
1653 "%s: Rx skb allocation failed\n", __func__);
1654 return NULL;
1655 }
1656
1657 /* DMA-map the new Rx skb */
1658 mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len,
1659 DMA_FROM_DEVICE);
1660 if (dma_mapping_error(kdev, mapping)) {
1661 priv->mib.rx_dma_failed++;
1662 dev_kfree_skb_any(skb);
1663 netif_err(priv, rx_err, priv->dev,
1664 "%s: Rx skb DMA mapping failed\n", __func__);
1665 return NULL;
1666 }
1667
1668 /* Grab the current Rx skb from the ring and DMA-unmap it */
1669 rx_skb = cb->skb;
1670 if (likely(rx_skb))
1671 dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr),
1672 priv->rx_buf_len, DMA_FROM_DEVICE);
1673
1674 /* Put the new Rx skb on the ring */
1675 cb->skb = skb;
1676 dma_unmap_addr_set(cb, dma_addr, mapping);
1677 dmadesc_set_addr(priv, cb->bd_addr, mapping);
1678
1679 /* Return the current Rx skb to caller */
1680 return rx_skb;
1681 }
1682
1683 /* bcmgenet_desc_rx - descriptor based rx process.
1684 * this could be called from bottom half, or from NAPI polling method.
1685 */
1686 static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring,
1687 unsigned int budget)
1688 {
1689 struct bcmgenet_priv *priv = ring->priv;
1690 struct net_device *dev = priv->dev;
1691 struct enet_cb *cb;
1692 struct sk_buff *skb;
1693 u32 dma_length_status;
1694 unsigned long dma_flag;
1695 int len;
1696 unsigned int rxpktprocessed = 0, rxpkttoprocess;
1697 unsigned int p_index, mask;
1698 unsigned int discards;
1699 unsigned int chksum_ok = 0;
1700
1701 /* Clear status before servicing to reduce spurious interrupts */
1702 if (ring->index == DESC_INDEX) {
1703 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_DONE,
1704 INTRL2_CPU_CLEAR);
1705 } else {
1706 mask = 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index);
1707 bcmgenet_intrl2_1_writel(priv,
1708 mask,
1709 INTRL2_CPU_CLEAR);
1710 }
1711
1712 p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX);
1713
1714 discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) &
1715 DMA_P_INDEX_DISCARD_CNT_MASK;
1716 if (discards > ring->old_discards) {
1717 discards = discards - ring->old_discards;
1718 ring->errors += discards;
1719 ring->old_discards += discards;
1720
1721 /* Clear HW register when we reach 75% of maximum 0xFFFF */
1722 if (ring->old_discards >= 0xC000) {
1723 ring->old_discards = 0;
1724 bcmgenet_rdma_ring_writel(priv, ring->index, 0,
1725 RDMA_PROD_INDEX);
1726 }
1727 }
1728
1729 p_index &= DMA_P_INDEX_MASK;
1730 rxpkttoprocess = (p_index - ring->c_index) & DMA_C_INDEX_MASK;
1731
1732 netif_dbg(priv, rx_status, dev,
1733 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1734
1735 while ((rxpktprocessed < rxpkttoprocess) &&
1736 (rxpktprocessed < budget)) {
1737 cb = &priv->rx_cbs[ring->read_ptr];
1738 skb = bcmgenet_rx_refill(priv, cb);
1739
1740 if (unlikely(!skb)) {
1741 ring->dropped++;
1742 goto next;
1743 }
1744
1745 if (!priv->desc_64b_en) {
1746 dma_length_status =
1747 dmadesc_get_length_status(priv, cb->bd_addr);
1748 } else {
1749 struct status_64 *status;
1750
1751 status = (struct status_64 *)skb->data;
1752 dma_length_status = status->length_status;
1753 }
1754
1755 /* DMA flags and length are still valid no matter how
1756 * we got the Receive Status Vector (64B RSB or register)
1757 */
1758 dma_flag = dma_length_status & 0xffff;
1759 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1760
1761 netif_dbg(priv, rx_status, dev,
1762 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
1763 __func__, p_index, ring->c_index,
1764 ring->read_ptr, dma_length_status);
1765
1766 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1767 netif_err(priv, rx_status, dev,
1768 "dropping fragmented packet!\n");
1769 ring->errors++;
1770 dev_kfree_skb_any(skb);
1771 goto next;
1772 }
1773
1774 /* report errors */
1775 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1776 DMA_RX_OV |
1777 DMA_RX_NO |
1778 DMA_RX_LG |
1779 DMA_RX_RXER))) {
1780 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
1781 (unsigned int)dma_flag);
1782 if (dma_flag & DMA_RX_CRC_ERROR)
1783 dev->stats.rx_crc_errors++;
1784 if (dma_flag & DMA_RX_OV)
1785 dev->stats.rx_over_errors++;
1786 if (dma_flag & DMA_RX_NO)
1787 dev->stats.rx_frame_errors++;
1788 if (dma_flag & DMA_RX_LG)
1789 dev->stats.rx_length_errors++;
1790 dev->stats.rx_errors++;
1791 dev_kfree_skb_any(skb);
1792 goto next;
1793 } /* error packet */
1794
1795 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
1796 priv->desc_rxchk_en;
1797
1798 skb_put(skb, len);
1799 if (priv->desc_64b_en) {
1800 skb_pull(skb, 64);
1801 len -= 64;
1802 }
1803
1804 if (likely(chksum_ok))
1805 skb->ip_summed = CHECKSUM_UNNECESSARY;
1806
1807 /* remove hardware 2bytes added for IP alignment */
1808 skb_pull(skb, 2);
1809 len -= 2;
1810
1811 if (priv->crc_fwd_en) {
1812 skb_trim(skb, len - ETH_FCS_LEN);
1813 len -= ETH_FCS_LEN;
1814 }
1815
1816 /*Finish setting up the received SKB and send it to the kernel*/
1817 skb->protocol = eth_type_trans(skb, priv->dev);
1818 ring->packets++;
1819 ring->bytes += len;
1820 if (dma_flag & DMA_RX_MULT)
1821 dev->stats.multicast++;
1822
1823 /* Notify kernel */
1824 napi_gro_receive(&ring->napi, skb);
1825 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1826
1827 next:
1828 rxpktprocessed++;
1829 if (likely(ring->read_ptr < ring->end_ptr))
1830 ring->read_ptr++;
1831 else
1832 ring->read_ptr = ring->cb_ptr;
1833
1834 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK;
1835 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX);
1836 }
1837
1838 return rxpktprocessed;
1839 }
1840
1841 /* Rx NAPI polling method */
1842 static int bcmgenet_rx_poll(struct napi_struct *napi, int budget)
1843 {
1844 struct bcmgenet_rx_ring *ring = container_of(napi,
1845 struct bcmgenet_rx_ring, napi);
1846 unsigned int work_done;
1847
1848 work_done = bcmgenet_desc_rx(ring, budget);
1849
1850 if (work_done < budget) {
1851 napi_complete_done(napi, work_done);
1852 ring->int_enable(ring);
1853 }
1854
1855 return work_done;
1856 }
1857
1858 /* Assign skb to RX DMA descriptor. */
1859 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv,
1860 struct bcmgenet_rx_ring *ring)
1861 {
1862 struct enet_cb *cb;
1863 struct sk_buff *skb;
1864 int i;
1865
1866 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1867
1868 /* loop here for each buffer needing assign */
1869 for (i = 0; i < ring->size; i++) {
1870 cb = ring->cbs + i;
1871 skb = bcmgenet_rx_refill(priv, cb);
1872 if (skb)
1873 dev_kfree_skb_any(skb);
1874 if (!cb->skb)
1875 return -ENOMEM;
1876 }
1877
1878 return 0;
1879 }
1880
1881 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1882 {
1883 struct device *kdev = &priv->pdev->dev;
1884 struct enet_cb *cb;
1885 int i;
1886
1887 for (i = 0; i < priv->num_rx_bds; i++) {
1888 cb = &priv->rx_cbs[i];
1889
1890 if (dma_unmap_addr(cb, dma_addr)) {
1891 dma_unmap_single(kdev,
1892 dma_unmap_addr(cb, dma_addr),
1893 priv->rx_buf_len, DMA_FROM_DEVICE);
1894 dma_unmap_addr_set(cb, dma_addr, 0);
1895 }
1896
1897 if (cb->skb)
1898 bcmgenet_free_cb(cb);
1899 }
1900 }
1901
1902 static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
1903 {
1904 u32 reg;
1905
1906 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1907 if (enable)
1908 reg |= mask;
1909 else
1910 reg &= ~mask;
1911 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1912
1913 /* UniMAC stops on a packet boundary, wait for a full-size packet
1914 * to be processed
1915 */
1916 if (enable == 0)
1917 usleep_range(1000, 2000);
1918 }
1919
1920 static int reset_umac(struct bcmgenet_priv *priv)
1921 {
1922 struct device *kdev = &priv->pdev->dev;
1923 unsigned int timeout = 0;
1924 u32 reg;
1925
1926 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1927 bcmgenet_rbuf_ctrl_set(priv, 0);
1928 udelay(10);
1929
1930 /* disable MAC while updating its registers */
1931 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1932
1933 /* issue soft reset, wait for it to complete */
1934 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
1935 while (timeout++ < 1000) {
1936 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1937 if (!(reg & CMD_SW_RESET))
1938 return 0;
1939
1940 udelay(1);
1941 }
1942
1943 if (timeout == 1000) {
1944 dev_err(kdev,
1945 "timeout waiting for MAC to come out of reset\n");
1946 return -ETIMEDOUT;
1947 }
1948
1949 return 0;
1950 }
1951
1952 static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
1953 {
1954 /* Mask all interrupts.*/
1955 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1956 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1957 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1958 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1959 }
1960
1961 static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv)
1962 {
1963 u32 int0_enable = 0;
1964
1965 /* Monitor cable plug/unplugged event for internal PHY, external PHY
1966 * and MoCA PHY
1967 */
1968 if (priv->internal_phy) {
1969 int0_enable |= UMAC_IRQ_LINK_EVENT;
1970 } else if (priv->ext_phy) {
1971 int0_enable |= UMAC_IRQ_LINK_EVENT;
1972 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1973 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
1974 int0_enable |= UMAC_IRQ_LINK_EVENT;
1975 }
1976 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
1977 }
1978
1979 static int init_umac(struct bcmgenet_priv *priv)
1980 {
1981 struct device *kdev = &priv->pdev->dev;
1982 int ret;
1983 u32 reg;
1984 u32 int0_enable = 0;
1985
1986 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
1987
1988 ret = reset_umac(priv);
1989 if (ret)
1990 return ret;
1991
1992 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1993 /* clear tx/rx counter */
1994 bcmgenet_umac_writel(priv,
1995 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
1996 UMAC_MIB_CTRL);
1997 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
1998
1999 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
2000
2001 /* init rx registers, enable ip header optimization */
2002 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
2003 reg |= RBUF_ALIGN_2B;
2004 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
2005
2006 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
2007 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
2008
2009 bcmgenet_intr_disable(priv);
2010
2011 /* Configure backpressure vectors for MoCA */
2012 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
2013 reg = bcmgenet_bp_mc_get(priv);
2014 reg |= BIT(priv->hw_params->bp_in_en_shift);
2015
2016 /* bp_mask: back pressure mask */
2017 if (netif_is_multiqueue(priv->dev))
2018 reg |= priv->hw_params->bp_in_mask;
2019 else
2020 reg &= ~priv->hw_params->bp_in_mask;
2021 bcmgenet_bp_mc_set(priv, reg);
2022 }
2023
2024 /* Enable MDIO interrupts on GENET v3+ */
2025 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
2026 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
2027
2028 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2029
2030 dev_dbg(kdev, "done init umac\n");
2031
2032 return 0;
2033 }
2034
2035 /* Initialize a Tx ring along with corresponding hardware registers */
2036 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
2037 unsigned int index, unsigned int size,
2038 unsigned int start_ptr, unsigned int end_ptr)
2039 {
2040 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
2041 u32 words_per_bd = WORDS_PER_BD(priv);
2042 u32 flow_period_val = 0;
2043
2044 spin_lock_init(&ring->lock);
2045 ring->priv = priv;
2046 ring->index = index;
2047 if (index == DESC_INDEX) {
2048 ring->queue = 0;
2049 ring->int_enable = bcmgenet_tx_ring16_int_enable;
2050 ring->int_disable = bcmgenet_tx_ring16_int_disable;
2051 } else {
2052 ring->queue = index + 1;
2053 ring->int_enable = bcmgenet_tx_ring_int_enable;
2054 ring->int_disable = bcmgenet_tx_ring_int_disable;
2055 }
2056 ring->cbs = priv->tx_cbs + start_ptr;
2057 ring->size = size;
2058 ring->clean_ptr = start_ptr;
2059 ring->c_index = 0;
2060 ring->free_bds = size;
2061 ring->write_ptr = start_ptr;
2062 ring->cb_ptr = start_ptr;
2063 ring->end_ptr = end_ptr - 1;
2064 ring->prod_index = 0;
2065
2066 /* Set flow period for ring != 16 */
2067 if (index != DESC_INDEX)
2068 flow_period_val = ENET_MAX_MTU_SIZE << 16;
2069
2070 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
2071 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
2072 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
2073 /* Disable rate control for now */
2074 bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
2075 TDMA_FLOW_PERIOD);
2076 bcmgenet_tdma_ring_writel(priv, index,
2077 ((size << DMA_RING_SIZE_SHIFT) |
2078 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
2079
2080 /* Set start and end address, read and write pointers */
2081 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2082 DMA_START_ADDR);
2083 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2084 TDMA_READ_PTR);
2085 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2086 TDMA_WRITE_PTR);
2087 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
2088 DMA_END_ADDR);
2089 }
2090
2091 /* Initialize a RDMA ring */
2092 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
2093 unsigned int index, unsigned int size,
2094 unsigned int start_ptr, unsigned int end_ptr)
2095 {
2096 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index];
2097 u32 words_per_bd = WORDS_PER_BD(priv);
2098 int ret;
2099
2100 ring->priv = priv;
2101 ring->index = index;
2102 if (index == DESC_INDEX) {
2103 ring->int_enable = bcmgenet_rx_ring16_int_enable;
2104 ring->int_disable = bcmgenet_rx_ring16_int_disable;
2105 } else {
2106 ring->int_enable = bcmgenet_rx_ring_int_enable;
2107 ring->int_disable = bcmgenet_rx_ring_int_disable;
2108 }
2109 ring->cbs = priv->rx_cbs + start_ptr;
2110 ring->size = size;
2111 ring->c_index = 0;
2112 ring->read_ptr = start_ptr;
2113 ring->cb_ptr = start_ptr;
2114 ring->end_ptr = end_ptr - 1;
2115
2116 ret = bcmgenet_alloc_rx_buffers(priv, ring);
2117 if (ret)
2118 return ret;
2119
2120 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
2121 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
2122 bcmgenet_rdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
2123 bcmgenet_rdma_ring_writel(priv, index,
2124 ((size << DMA_RING_SIZE_SHIFT) |
2125 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
2126 bcmgenet_rdma_ring_writel(priv, index,
2127 (DMA_FC_THRESH_LO <<
2128 DMA_XOFF_THRESHOLD_SHIFT) |
2129 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
2130
2131 /* Set start and end address, read and write pointers */
2132 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2133 DMA_START_ADDR);
2134 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2135 RDMA_READ_PTR);
2136 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2137 RDMA_WRITE_PTR);
2138 bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
2139 DMA_END_ADDR);
2140
2141 return ret;
2142 }
2143
2144 static void bcmgenet_init_tx_napi(struct bcmgenet_priv *priv)
2145 {
2146 unsigned int i;
2147 struct bcmgenet_tx_ring *ring;
2148
2149 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2150 ring = &priv->tx_rings[i];
2151 netif_tx_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64);
2152 }
2153
2154 ring = &priv->tx_rings[DESC_INDEX];
2155 netif_tx_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64);
2156 }
2157
2158 static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv)
2159 {
2160 unsigned int i;
2161 u32 int0_enable = UMAC_IRQ_TXDMA_DONE;
2162 u32 int1_enable = 0;
2163 struct bcmgenet_tx_ring *ring;
2164
2165 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2166 ring = &priv->tx_rings[i];
2167 napi_enable(&ring->napi);
2168 int1_enable |= (1 << i);
2169 }
2170
2171 ring = &priv->tx_rings[DESC_INDEX];
2172 napi_enable(&ring->napi);
2173
2174 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2175 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
2176 }
2177
2178 static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv)
2179 {
2180 unsigned int i;
2181 u32 int0_disable = UMAC_IRQ_TXDMA_DONE;
2182 u32 int1_disable = 0xffff;
2183 struct bcmgenet_tx_ring *ring;
2184
2185 bcmgenet_intrl2_0_writel(priv, int0_disable, INTRL2_CPU_MASK_SET);
2186 bcmgenet_intrl2_1_writel(priv, int1_disable, INTRL2_CPU_MASK_SET);
2187
2188 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2189 ring = &priv->tx_rings[i];
2190 napi_disable(&ring->napi);
2191 }
2192
2193 ring = &priv->tx_rings[DESC_INDEX];
2194 napi_disable(&ring->napi);
2195 }
2196
2197 static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv)
2198 {
2199 unsigned int i;
2200 struct bcmgenet_tx_ring *ring;
2201
2202 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2203 ring = &priv->tx_rings[i];
2204 netif_napi_del(&ring->napi);
2205 }
2206
2207 ring = &priv->tx_rings[DESC_INDEX];
2208 netif_napi_del(&ring->napi);
2209 }
2210
2211 /* Initialize Tx queues
2212 *
2213 * Queues 0-3 are priority-based, each one has 32 descriptors,
2214 * with queue 0 being the highest priority queue.
2215 *
2216 * Queue 16 is the default Tx queue with
2217 * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors.
2218 *
2219 * The transmit control block pool is then partitioned as follows:
2220 * - Tx queue 0 uses tx_cbs[0..31]
2221 * - Tx queue 1 uses tx_cbs[32..63]
2222 * - Tx queue 2 uses tx_cbs[64..95]
2223 * - Tx queue 3 uses tx_cbs[96..127]
2224 * - Tx queue 16 uses tx_cbs[128..255]
2225 */
2226 static void bcmgenet_init_tx_queues(struct net_device *dev)
2227 {
2228 struct bcmgenet_priv *priv = netdev_priv(dev);
2229 u32 i, dma_enable;
2230 u32 dma_ctrl, ring_cfg;
2231 u32 dma_priority[3] = {0, 0, 0};
2232
2233 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
2234 dma_enable = dma_ctrl & DMA_EN;
2235 dma_ctrl &= ~DMA_EN;
2236 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2237
2238 dma_ctrl = 0;
2239 ring_cfg = 0;
2240
2241 /* Enable strict priority arbiter mode */
2242 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
2243
2244 /* Initialize Tx priority queues */
2245 for (i = 0; i < priv->hw_params->tx_queues; i++) {
2246 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q,
2247 i * priv->hw_params->tx_bds_per_q,
2248 (i + 1) * priv->hw_params->tx_bds_per_q);
2249 ring_cfg |= (1 << i);
2250 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2251 dma_priority[DMA_PRIO_REG_INDEX(i)] |=
2252 ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i));
2253 }
2254
2255 /* Initialize Tx default queue 16 */
2256 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT,
2257 priv->hw_params->tx_queues *
2258 priv->hw_params->tx_bds_per_q,
2259 TOTAL_DESC);
2260 ring_cfg |= (1 << DESC_INDEX);
2261 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2262 dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |=
2263 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) <<
2264 DMA_PRIO_REG_SHIFT(DESC_INDEX));
2265
2266 /* Set Tx queue priorities */
2267 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
2268 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
2269 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
2270
2271 /* Initialize Tx NAPI */
2272 bcmgenet_init_tx_napi(priv);
2273
2274 /* Enable Tx queues */
2275 bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG);
2276
2277 /* Enable Tx DMA */
2278 if (dma_enable)
2279 dma_ctrl |= DMA_EN;
2280 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2281 }
2282
2283 static void bcmgenet_init_rx_napi(struct bcmgenet_priv *priv)
2284 {
2285 unsigned int i;
2286 struct bcmgenet_rx_ring *ring;
2287
2288 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2289 ring = &priv->rx_rings[i];
2290 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64);
2291 }
2292
2293 ring = &priv->rx_rings[DESC_INDEX];
2294 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64);
2295 }
2296
2297 static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv)
2298 {
2299 unsigned int i;
2300 u32 int0_enable = UMAC_IRQ_RXDMA_DONE;
2301 u32 int1_enable = 0;
2302 struct bcmgenet_rx_ring *ring;
2303
2304 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2305 ring = &priv->rx_rings[i];
2306 napi_enable(&ring->napi);
2307 int1_enable |= (1 << (UMAC_IRQ1_RX_INTR_SHIFT + i));
2308 }
2309
2310 ring = &priv->rx_rings[DESC_INDEX];
2311 napi_enable(&ring->napi);
2312
2313 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2314 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
2315 }
2316
2317 static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv)
2318 {
2319 unsigned int i;
2320 u32 int0_disable = UMAC_IRQ_RXDMA_DONE;
2321 u32 int1_disable = 0xffff << UMAC_IRQ1_RX_INTR_SHIFT;
2322 struct bcmgenet_rx_ring *ring;
2323
2324 bcmgenet_intrl2_0_writel(priv, int0_disable, INTRL2_CPU_MASK_SET);
2325 bcmgenet_intrl2_1_writel(priv, int1_disable, INTRL2_CPU_MASK_SET);
2326
2327 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2328 ring = &priv->rx_rings[i];
2329 napi_disable(&ring->napi);
2330 }
2331
2332 ring = &priv->rx_rings[DESC_INDEX];
2333 napi_disable(&ring->napi);
2334 }
2335
2336 static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv)
2337 {
2338 unsigned int i;
2339 struct bcmgenet_rx_ring *ring;
2340
2341 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2342 ring = &priv->rx_rings[i];
2343 netif_napi_del(&ring->napi);
2344 }
2345
2346 ring = &priv->rx_rings[DESC_INDEX];
2347 netif_napi_del(&ring->napi);
2348 }
2349
2350 /* Initialize Rx queues
2351 *
2352 * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be
2353 * used to direct traffic to these queues.
2354 *
2355 * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors.
2356 */
2357 static int bcmgenet_init_rx_queues(struct net_device *dev)
2358 {
2359 struct bcmgenet_priv *priv = netdev_priv(dev);
2360 u32 i;
2361 u32 dma_enable;
2362 u32 dma_ctrl;
2363 u32 ring_cfg;
2364 int ret;
2365
2366 dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL);
2367 dma_enable = dma_ctrl & DMA_EN;
2368 dma_ctrl &= ~DMA_EN;
2369 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2370
2371 dma_ctrl = 0;
2372 ring_cfg = 0;
2373
2374 /* Initialize Rx priority queues */
2375 for (i = 0; i < priv->hw_params->rx_queues; i++) {
2376 ret = bcmgenet_init_rx_ring(priv, i,
2377 priv->hw_params->rx_bds_per_q,
2378 i * priv->hw_params->rx_bds_per_q,
2379 (i + 1) *
2380 priv->hw_params->rx_bds_per_q);
2381 if (ret)
2382 return ret;
2383
2384 ring_cfg |= (1 << i);
2385 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2386 }
2387
2388 /* Initialize Rx default queue 16 */
2389 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT,
2390 priv->hw_params->rx_queues *
2391 priv->hw_params->rx_bds_per_q,
2392 TOTAL_DESC);
2393 if (ret)
2394 return ret;
2395
2396 ring_cfg |= (1 << DESC_INDEX);
2397 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2398
2399 /* Initialize Rx NAPI */
2400 bcmgenet_init_rx_napi(priv);
2401
2402 /* Enable rings */
2403 bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG);
2404
2405 /* Configure ring as descriptor ring and re-enable DMA if enabled */
2406 if (dma_enable)
2407 dma_ctrl |= DMA_EN;
2408 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2409
2410 return 0;
2411 }
2412
2413 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
2414 {
2415 int ret = 0;
2416 int timeout = 0;
2417 u32 reg;
2418 u32 dma_ctrl;
2419 int i;
2420
2421 /* Disable TDMA to stop add more frames in TX DMA */
2422 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2423 reg &= ~DMA_EN;
2424 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2425
2426 /* Check TDMA status register to confirm TDMA is disabled */
2427 while (timeout++ < DMA_TIMEOUT_VAL) {
2428 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2429 if (reg & DMA_DISABLED)
2430 break;
2431
2432 udelay(1);
2433 }
2434
2435 if (timeout == DMA_TIMEOUT_VAL) {
2436 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
2437 ret = -ETIMEDOUT;
2438 }
2439
2440 /* Wait 10ms for packet drain in both tx and rx dma */
2441 usleep_range(10000, 20000);
2442
2443 /* Disable RDMA */
2444 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2445 reg &= ~DMA_EN;
2446 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2447
2448 timeout = 0;
2449 /* Check RDMA status register to confirm RDMA is disabled */
2450 while (timeout++ < DMA_TIMEOUT_VAL) {
2451 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
2452 if (reg & DMA_DISABLED)
2453 break;
2454
2455 udelay(1);
2456 }
2457
2458 if (timeout == DMA_TIMEOUT_VAL) {
2459 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
2460 ret = -ETIMEDOUT;
2461 }
2462
2463 dma_ctrl = 0;
2464 for (i = 0; i < priv->hw_params->rx_queues; i++)
2465 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2466 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2467 reg &= ~dma_ctrl;
2468 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2469
2470 dma_ctrl = 0;
2471 for (i = 0; i < priv->hw_params->tx_queues; i++)
2472 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2473 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2474 reg &= ~dma_ctrl;
2475 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2476
2477 return ret;
2478 }
2479
2480 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
2481 {
2482 int i;
2483 struct netdev_queue *txq;
2484
2485 bcmgenet_fini_rx_napi(priv);
2486 bcmgenet_fini_tx_napi(priv);
2487
2488 /* disable DMA */
2489 bcmgenet_dma_teardown(priv);
2490
2491 for (i = 0; i < priv->num_tx_bds; i++) {
2492 if (priv->tx_cbs[i].skb != NULL) {
2493 dev_kfree_skb(priv->tx_cbs[i].skb);
2494 priv->tx_cbs[i].skb = NULL;
2495 }
2496 }
2497
2498 for (i = 0; i < priv->hw_params->tx_queues; i++) {
2499 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[i].queue);
2500 netdev_tx_reset_queue(txq);
2501 }
2502
2503 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[DESC_INDEX].queue);
2504 netdev_tx_reset_queue(txq);
2505
2506 bcmgenet_free_rx_buffers(priv);
2507 kfree(priv->rx_cbs);
2508 kfree(priv->tx_cbs);
2509 }
2510
2511 /* init_edma: Initialize DMA control register */
2512 static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
2513 {
2514 int ret;
2515 unsigned int i;
2516 struct enet_cb *cb;
2517
2518 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
2519
2520 /* Initialize common Rx ring structures */
2521 priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
2522 priv->num_rx_bds = TOTAL_DESC;
2523 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
2524 GFP_KERNEL);
2525 if (!priv->rx_cbs)
2526 return -ENOMEM;
2527
2528 for (i = 0; i < priv->num_rx_bds; i++) {
2529 cb = priv->rx_cbs + i;
2530 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE;
2531 }
2532
2533 /* Initialize common TX ring structures */
2534 priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
2535 priv->num_tx_bds = TOTAL_DESC;
2536 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
2537 GFP_KERNEL);
2538 if (!priv->tx_cbs) {
2539 kfree(priv->rx_cbs);
2540 return -ENOMEM;
2541 }
2542
2543 for (i = 0; i < priv->num_tx_bds; i++) {
2544 cb = priv->tx_cbs + i;
2545 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE;
2546 }
2547
2548 /* Init rDma */
2549 bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2550
2551 /* Initialize Rx queues */
2552 ret = bcmgenet_init_rx_queues(priv->dev);
2553 if (ret) {
2554 netdev_err(priv->dev, "failed to initialize Rx queues\n");
2555 bcmgenet_free_rx_buffers(priv);
2556 kfree(priv->rx_cbs);
2557 kfree(priv->tx_cbs);
2558 return ret;
2559 }
2560
2561 /* Init tDma */
2562 bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2563
2564 /* Initialize Tx queues */
2565 bcmgenet_init_tx_queues(priv->dev);
2566
2567 return 0;
2568 }
2569
2570 /* Interrupt bottom half */
2571 static void bcmgenet_irq_task(struct work_struct *work)
2572 {
2573 unsigned long flags;
2574 unsigned int status;
2575 struct bcmgenet_priv *priv = container_of(
2576 work, struct bcmgenet_priv, bcmgenet_irq_work);
2577
2578 netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
2579
2580 spin_lock_irqsave(&priv->lock, flags);
2581 status = priv->irq0_stat;
2582 priv->irq0_stat = 0;
2583 spin_unlock_irqrestore(&priv->lock, flags);
2584
2585 if (status & UMAC_IRQ_MPD_R) {
2586 netif_dbg(priv, wol, priv->dev,
2587 "magic packet detected, waking up\n");
2588 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
2589 }
2590
2591 /* Link UP/DOWN event */
2592 if (status & UMAC_IRQ_LINK_EVENT)
2593 phy_mac_interrupt(priv->phydev,
2594 !!(status & UMAC_IRQ_LINK_UP));
2595 }
2596
2597 /* bcmgenet_isr1: handle Rx and Tx priority queues */
2598 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
2599 {
2600 struct bcmgenet_priv *priv = dev_id;
2601 struct bcmgenet_rx_ring *rx_ring;
2602 struct bcmgenet_tx_ring *tx_ring;
2603 unsigned int index, status;
2604
2605 /* Read irq status */
2606 status = bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
2607 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
2608
2609 /* clear interrupts */
2610 bcmgenet_intrl2_1_writel(priv, status, INTRL2_CPU_CLEAR);
2611
2612 netif_dbg(priv, intr, priv->dev,
2613 "%s: IRQ=0x%x\n", __func__, status);
2614
2615 /* Check Rx priority queue interrupts */
2616 for (index = 0; index < priv->hw_params->rx_queues; index++) {
2617 if (!(status & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index)))
2618 continue;
2619
2620 rx_ring = &priv->rx_rings[index];
2621
2622 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2623 rx_ring->int_disable(rx_ring);
2624 __napi_schedule_irqoff(&rx_ring->napi);
2625 }
2626 }
2627
2628 /* Check Tx priority queue interrupts */
2629 for (index = 0; index < priv->hw_params->tx_queues; index++) {
2630 if (!(status & BIT(index)))
2631 continue;
2632
2633 tx_ring = &priv->tx_rings[index];
2634
2635 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2636 tx_ring->int_disable(tx_ring);
2637 __napi_schedule_irqoff(&tx_ring->napi);
2638 }
2639 }
2640
2641 return IRQ_HANDLED;
2642 }
2643
2644 /* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */
2645 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
2646 {
2647 struct bcmgenet_priv *priv = dev_id;
2648 struct bcmgenet_rx_ring *rx_ring;
2649 struct bcmgenet_tx_ring *tx_ring;
2650 unsigned int status;
2651 unsigned long flags;
2652
2653 /* Read irq status */
2654 status = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
2655 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
2656
2657 /* clear interrupts */
2658 bcmgenet_intrl2_0_writel(priv, status, INTRL2_CPU_CLEAR);
2659
2660 netif_dbg(priv, intr, priv->dev,
2661 "IRQ=0x%x\n", status);
2662
2663 if (status & UMAC_IRQ_RXDMA_DONE) {
2664 rx_ring = &priv->rx_rings[DESC_INDEX];
2665
2666 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2667 rx_ring->int_disable(rx_ring);
2668 __napi_schedule_irqoff(&rx_ring->napi);
2669 }
2670 }
2671
2672 if (status & UMAC_IRQ_TXDMA_DONE) {
2673 tx_ring = &priv->tx_rings[DESC_INDEX];
2674
2675 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2676 tx_ring->int_disable(tx_ring);
2677 __napi_schedule_irqoff(&tx_ring->napi);
2678 }
2679 }
2680
2681 if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R |
2682 UMAC_IRQ_PHY_DET_F |
2683 UMAC_IRQ_LINK_EVENT |
2684 UMAC_IRQ_HFB_SM |
2685 UMAC_IRQ_HFB_MM)) {
2686 /* all other interested interrupts handled in bottom half */
2687 schedule_work(&priv->bcmgenet_irq_work);
2688 }
2689
2690 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
2691 status & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
2692 wake_up(&priv->wq);
2693 }
2694
2695 /* all other interested interrupts handled in bottom half */
2696 status &= (UMAC_IRQ_LINK_EVENT |
2697 UMAC_IRQ_MPD_R);
2698 if (status) {
2699 /* Save irq status for bottom-half processing. */
2700 spin_lock_irqsave(&priv->lock, flags);
2701 priv->irq0_stat |= status;
2702 spin_unlock_irqrestore(&priv->lock, flags);
2703
2704 schedule_work(&priv->bcmgenet_irq_work);
2705 }
2706
2707 return IRQ_HANDLED;
2708 }
2709
2710 static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
2711 {
2712 struct bcmgenet_priv *priv = dev_id;
2713
2714 pm_wakeup_event(&priv->pdev->dev, 0);
2715
2716 return IRQ_HANDLED;
2717 }
2718
2719 #ifdef CONFIG_NET_POLL_CONTROLLER
2720 static void bcmgenet_poll_controller(struct net_device *dev)
2721 {
2722 struct bcmgenet_priv *priv = netdev_priv(dev);
2723
2724 /* Invoke the main RX/TX interrupt handler */
2725 disable_irq(priv->irq0);
2726 bcmgenet_isr0(priv->irq0, priv);
2727 enable_irq(priv->irq0);
2728
2729 /* And the interrupt handler for RX/TX priority queues */
2730 disable_irq(priv->irq1);
2731 bcmgenet_isr1(priv->irq1, priv);
2732 enable_irq(priv->irq1);
2733 }
2734 #endif
2735
2736 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
2737 {
2738 u32 reg;
2739
2740 reg = bcmgenet_rbuf_ctrl_get(priv);
2741 reg |= BIT(1);
2742 bcmgenet_rbuf_ctrl_set(priv, reg);
2743 udelay(10);
2744
2745 reg &= ~BIT(1);
2746 bcmgenet_rbuf_ctrl_set(priv, reg);
2747 udelay(10);
2748 }
2749
2750 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
2751 unsigned char *addr)
2752 {
2753 bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
2754 (addr[2] << 8) | addr[3], UMAC_MAC0);
2755 bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
2756 }
2757
2758 /* Returns a reusable dma control register value */
2759 static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
2760 {
2761 u32 reg;
2762 u32 dma_ctrl;
2763
2764 /* disable DMA */
2765 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2766 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2767 reg &= ~dma_ctrl;
2768 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2769
2770 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2771 reg &= ~dma_ctrl;
2772 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2773
2774 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
2775 udelay(10);
2776 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
2777
2778 return dma_ctrl;
2779 }
2780
2781 static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
2782 {
2783 u32 reg;
2784
2785 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2786 reg |= dma_ctrl;
2787 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2788
2789 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2790 reg |= dma_ctrl;
2791 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2792 }
2793
2794 /* bcmgenet_hfb_clear
2795 *
2796 * Clear Hardware Filter Block and disable all filtering.
2797 */
2798 static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv)
2799 {
2800 u32 i;
2801
2802 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL);
2803 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS);
2804 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4);
2805
2806 for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++)
2807 bcmgenet_rdma_writel(priv, 0x0, i);
2808
2809 for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++)
2810 bcmgenet_hfb_reg_writel(priv, 0x0,
2811 HFB_FLT_LEN_V3PLUS + i * sizeof(u32));
2812
2813 for (i = 0; i < priv->hw_params->hfb_filter_cnt *
2814 priv->hw_params->hfb_filter_size; i++)
2815 bcmgenet_hfb_writel(priv, 0x0, i * sizeof(u32));
2816 }
2817
2818 static void bcmgenet_hfb_init(struct bcmgenet_priv *priv)
2819 {
2820 if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
2821 return;
2822
2823 bcmgenet_hfb_clear(priv);
2824 }
2825
2826 static void bcmgenet_netif_start(struct net_device *dev)
2827 {
2828 struct bcmgenet_priv *priv = netdev_priv(dev);
2829
2830 /* Start the network engine */
2831 bcmgenet_enable_rx_napi(priv);
2832 bcmgenet_enable_tx_napi(priv);
2833
2834 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
2835
2836 netif_tx_start_all_queues(dev);
2837
2838 /* Monitor link interrupts now */
2839 bcmgenet_link_intr_enable(priv);
2840
2841 phy_start(priv->phydev);
2842 }
2843
2844 static int bcmgenet_open(struct net_device *dev)
2845 {
2846 struct bcmgenet_priv *priv = netdev_priv(dev);
2847 unsigned long dma_ctrl;
2848 u32 reg;
2849 int ret;
2850
2851 netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
2852
2853 /* Turn on the clock */
2854 clk_prepare_enable(priv->clk);
2855
2856 /* If this is an internal GPHY, power it back on now, before UniMAC is
2857 * brought out of reset as absolutely no UniMAC activity is allowed
2858 */
2859 if (priv->internal_phy)
2860 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2861
2862 /* take MAC out of reset */
2863 bcmgenet_umac_reset(priv);
2864
2865 ret = init_umac(priv);
2866 if (ret)
2867 goto err_clk_disable;
2868
2869 /* disable ethernet MAC while updating its registers */
2870 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
2871
2872 /* Make sure we reflect the value of CRC_CMD_FWD */
2873 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2874 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2875
2876 bcmgenet_set_hw_addr(priv, dev->dev_addr);
2877
2878 if (priv->internal_phy) {
2879 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2880 reg |= EXT_ENERGY_DET_MASK;
2881 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2882 }
2883
2884 /* Disable RX/TX DMA and flush TX queues */
2885 dma_ctrl = bcmgenet_dma_disable(priv);
2886
2887 /* Reinitialize TDMA and RDMA and SW housekeeping */
2888 ret = bcmgenet_init_dma(priv);
2889 if (ret) {
2890 netdev_err(dev, "failed to initialize DMA\n");
2891 goto err_clk_disable;
2892 }
2893
2894 /* Always enable ring 16 - descriptor ring */
2895 bcmgenet_enable_dma(priv, dma_ctrl);
2896
2897 /* HFB init */
2898 bcmgenet_hfb_init(priv);
2899
2900 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
2901 dev->name, priv);
2902 if (ret < 0) {
2903 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2904 goto err_fini_dma;
2905 }
2906
2907 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
2908 dev->name, priv);
2909 if (ret < 0) {
2910 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2911 goto err_irq0;
2912 }
2913
2914 ret = bcmgenet_mii_probe(dev);
2915 if (ret) {
2916 netdev_err(dev, "failed to connect to PHY\n");
2917 goto err_irq1;
2918 }
2919
2920 bcmgenet_netif_start(dev);
2921
2922 return 0;
2923
2924 err_irq1:
2925 free_irq(priv->irq1, priv);
2926 err_irq0:
2927 free_irq(priv->irq0, priv);
2928 err_fini_dma:
2929 bcmgenet_fini_dma(priv);
2930 err_clk_disable:
2931 if (priv->internal_phy)
2932 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
2933 clk_disable_unprepare(priv->clk);
2934 return ret;
2935 }
2936
2937 static void bcmgenet_netif_stop(struct net_device *dev)
2938 {
2939 struct bcmgenet_priv *priv = netdev_priv(dev);
2940
2941 netif_tx_stop_all_queues(dev);
2942 phy_stop(priv->phydev);
2943 bcmgenet_intr_disable(priv);
2944 bcmgenet_disable_rx_napi(priv);
2945 bcmgenet_disable_tx_napi(priv);
2946
2947 /* Wait for pending work items to complete. Since interrupts are
2948 * disabled no new work will be scheduled.
2949 */
2950 cancel_work_sync(&priv->bcmgenet_irq_work);
2951
2952 priv->old_link = -1;
2953 priv->old_speed = -1;
2954 priv->old_duplex = -1;
2955 priv->old_pause = -1;
2956 }
2957
2958 static int bcmgenet_close(struct net_device *dev)
2959 {
2960 struct bcmgenet_priv *priv = netdev_priv(dev);
2961 int ret;
2962
2963 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
2964
2965 bcmgenet_netif_stop(dev);
2966
2967 /* Really kill the PHY state machine and disconnect from it */
2968 phy_disconnect(priv->phydev);
2969
2970 /* Disable MAC receive */
2971 umac_enable_set(priv, CMD_RX_EN, false);
2972
2973 ret = bcmgenet_dma_teardown(priv);
2974 if (ret)
2975 return ret;
2976
2977 /* Disable MAC transmit. TX DMA disabled must be done before this */
2978 umac_enable_set(priv, CMD_TX_EN, false);
2979
2980 /* tx reclaim */
2981 bcmgenet_tx_reclaim_all(dev);
2982 bcmgenet_fini_dma(priv);
2983
2984 free_irq(priv->irq0, priv);
2985 free_irq(priv->irq1, priv);
2986
2987 if (priv->internal_phy)
2988 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
2989
2990 clk_disable_unprepare(priv->clk);
2991
2992 return ret;
2993 }
2994
2995 static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring)
2996 {
2997 struct bcmgenet_priv *priv = ring->priv;
2998 u32 p_index, c_index, intsts, intmsk;
2999 struct netdev_queue *txq;
3000 unsigned int free_bds;
3001 unsigned long flags;
3002 bool txq_stopped;
3003
3004 if (!netif_msg_tx_err(priv))
3005 return;
3006
3007 txq = netdev_get_tx_queue(priv->dev, ring->queue);
3008
3009 spin_lock_irqsave(&ring->lock, flags);
3010 if (ring->index == DESC_INDEX) {
3011 intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
3012 intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE;
3013 } else {
3014 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
3015 intmsk = 1 << ring->index;
3016 }
3017 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
3018 p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX);
3019 txq_stopped = netif_tx_queue_stopped(txq);
3020 free_bds = ring->free_bds;
3021 spin_unlock_irqrestore(&ring->lock, flags);
3022
3023 netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n"
3024 "TX queue status: %s, interrupts: %s\n"
3025 "(sw)free_bds: %d (sw)size: %d\n"
3026 "(sw)p_index: %d (hw)p_index: %d\n"
3027 "(sw)c_index: %d (hw)c_index: %d\n"
3028 "(sw)clean_p: %d (sw)write_p: %d\n"
3029 "(sw)cb_ptr: %d (sw)end_ptr: %d\n",
3030 ring->index, ring->queue,
3031 txq_stopped ? "stopped" : "active",
3032 intsts & intmsk ? "enabled" : "disabled",
3033 free_bds, ring->size,
3034 ring->prod_index, p_index & DMA_P_INDEX_MASK,
3035 ring->c_index, c_index & DMA_C_INDEX_MASK,
3036 ring->clean_ptr, ring->write_ptr,
3037 ring->cb_ptr, ring->end_ptr);
3038 }
3039
3040 static void bcmgenet_timeout(struct net_device *dev)
3041 {
3042 struct bcmgenet_priv *priv = netdev_priv(dev);
3043 u32 int0_enable = 0;
3044 u32 int1_enable = 0;
3045 unsigned int q;
3046
3047 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
3048
3049 for (q = 0; q < priv->hw_params->tx_queues; q++)
3050 bcmgenet_dump_tx_queue(&priv->tx_rings[q]);
3051 bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]);
3052
3053 bcmgenet_tx_reclaim_all(dev);
3054
3055 for (q = 0; q < priv->hw_params->tx_queues; q++)
3056 int1_enable |= (1 << q);
3057
3058 int0_enable = UMAC_IRQ_TXDMA_DONE;
3059
3060 /* Re-enable TX interrupts if disabled */
3061 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
3062 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
3063
3064 netif_trans_update(dev);
3065
3066 dev->stats.tx_errors++;
3067
3068 netif_tx_wake_all_queues(dev);
3069 }
3070
3071 #define MAX_MC_COUNT 16
3072
3073 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
3074 unsigned char *addr,
3075 int *i,
3076 int *mc)
3077 {
3078 u32 reg;
3079
3080 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
3081 UMAC_MDF_ADDR + (*i * 4));
3082 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
3083 addr[4] << 8 | addr[5],
3084 UMAC_MDF_ADDR + ((*i + 1) * 4));
3085 reg = bcmgenet_umac_readl(priv, UMAC_MDF_CTRL);
3086 reg |= (1 << (MAX_MC_COUNT - *mc));
3087 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
3088 *i += 2;
3089 (*mc)++;
3090 }
3091
3092 static void bcmgenet_set_rx_mode(struct net_device *dev)
3093 {
3094 struct bcmgenet_priv *priv = netdev_priv(dev);
3095 struct netdev_hw_addr *ha;
3096 int i, mc;
3097 u32 reg;
3098
3099 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
3100
3101 /* Promiscuous mode */
3102 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
3103 if (dev->flags & IFF_PROMISC) {
3104 reg |= CMD_PROMISC;
3105 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3106 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
3107 return;
3108 } else {
3109 reg &= ~CMD_PROMISC;
3110 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3111 }
3112
3113 /* UniMac doesn't support ALLMULTI */
3114 if (dev->flags & IFF_ALLMULTI) {
3115 netdev_warn(dev, "ALLMULTI is not supported\n");
3116 return;
3117 }
3118
3119 /* update MDF filter */
3120 i = 0;
3121 mc = 0;
3122 /* Broadcast */
3123 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i, &mc);
3124 /* my own address.*/
3125 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i, &mc);
3126 /* Unicast list*/
3127 if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc))
3128 return;
3129
3130 if (!netdev_uc_empty(dev))
3131 netdev_for_each_uc_addr(ha, dev)
3132 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
3133 /* Multicast */
3134 if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc))
3135 return;
3136
3137 netdev_for_each_mc_addr(ha, dev)
3138 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
3139 }
3140
3141 /* Set the hardware MAC address. */
3142 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
3143 {
3144 struct sockaddr *addr = p;
3145
3146 /* Setting the MAC address at the hardware level is not possible
3147 * without disabling the UniMAC RX/TX enable bits.
3148 */
3149 if (netif_running(dev))
3150 return -EBUSY;
3151
3152 ether_addr_copy(dev->dev_addr, addr->sa_data);
3153
3154 return 0;
3155 }
3156
3157 static struct net_device_stats *bcmgenet_get_stats(struct net_device *dev)
3158 {
3159 struct bcmgenet_priv *priv = netdev_priv(dev);
3160 unsigned long tx_bytes = 0, tx_packets = 0;
3161 unsigned long rx_bytes = 0, rx_packets = 0;
3162 unsigned long rx_errors = 0, rx_dropped = 0;
3163 struct bcmgenet_tx_ring *tx_ring;
3164 struct bcmgenet_rx_ring *rx_ring;
3165 unsigned int q;
3166
3167 for (q = 0; q < priv->hw_params->tx_queues; q++) {
3168 tx_ring = &priv->tx_rings[q];
3169 tx_bytes += tx_ring->bytes;
3170 tx_packets += tx_ring->packets;
3171 }
3172 tx_ring = &priv->tx_rings[DESC_INDEX];
3173 tx_bytes += tx_ring->bytes;
3174 tx_packets += tx_ring->packets;
3175
3176 for (q = 0; q < priv->hw_params->rx_queues; q++) {
3177 rx_ring = &priv->rx_rings[q];
3178
3179 rx_bytes += rx_ring->bytes;
3180 rx_packets += rx_ring->packets;
3181 rx_errors += rx_ring->errors;
3182 rx_dropped += rx_ring->dropped;
3183 }
3184 rx_ring = &priv->rx_rings[DESC_INDEX];
3185 rx_bytes += rx_ring->bytes;
3186 rx_packets += rx_ring->packets;
3187 rx_errors += rx_ring->errors;
3188 rx_dropped += rx_ring->dropped;
3189
3190 dev->stats.tx_bytes = tx_bytes;
3191 dev->stats.tx_packets = tx_packets;
3192 dev->stats.rx_bytes = rx_bytes;
3193 dev->stats.rx_packets = rx_packets;
3194 dev->stats.rx_errors = rx_errors;
3195 dev->stats.rx_missed_errors = rx_errors;
3196 return &dev->stats;
3197 }
3198
3199 static const struct net_device_ops bcmgenet_netdev_ops = {
3200 .ndo_open = bcmgenet_open,
3201 .ndo_stop = bcmgenet_close,
3202 .ndo_start_xmit = bcmgenet_xmit,
3203 .ndo_tx_timeout = bcmgenet_timeout,
3204 .ndo_set_rx_mode = bcmgenet_set_rx_mode,
3205 .ndo_set_mac_address = bcmgenet_set_mac_addr,
3206 .ndo_do_ioctl = bcmgenet_ioctl,
3207 .ndo_set_features = bcmgenet_set_features,
3208 #ifdef CONFIG_NET_POLL_CONTROLLER
3209 .ndo_poll_controller = bcmgenet_poll_controller,
3210 #endif
3211 .ndo_get_stats = bcmgenet_get_stats,
3212 };
3213
3214 /* Array of GENET hardware parameters/characteristics */
3215 static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
3216 [GENET_V1] = {
3217 .tx_queues = 0,
3218 .tx_bds_per_q = 0,
3219 .rx_queues = 0,
3220 .rx_bds_per_q = 0,
3221 .bp_in_en_shift = 16,
3222 .bp_in_mask = 0xffff,
3223 .hfb_filter_cnt = 16,
3224 .qtag_mask = 0x1F,
3225 .hfb_offset = 0x1000,
3226 .rdma_offset = 0x2000,
3227 .tdma_offset = 0x3000,
3228 .words_per_bd = 2,
3229 },
3230 [GENET_V2] = {
3231 .tx_queues = 4,
3232 .tx_bds_per_q = 32,
3233 .rx_queues = 0,
3234 .rx_bds_per_q = 0,
3235 .bp_in_en_shift = 16,
3236 .bp_in_mask = 0xffff,
3237 .hfb_filter_cnt = 16,
3238 .qtag_mask = 0x1F,
3239 .tbuf_offset = 0x0600,
3240 .hfb_offset = 0x1000,
3241 .hfb_reg_offset = 0x2000,
3242 .rdma_offset = 0x3000,
3243 .tdma_offset = 0x4000,
3244 .words_per_bd = 2,
3245 .flags = GENET_HAS_EXT,
3246 },
3247 [GENET_V3] = {
3248 .tx_queues = 4,
3249 .tx_bds_per_q = 32,
3250 .rx_queues = 0,
3251 .rx_bds_per_q = 0,
3252 .bp_in_en_shift = 17,
3253 .bp_in_mask = 0x1ffff,
3254 .hfb_filter_cnt = 48,
3255 .hfb_filter_size = 128,
3256 .qtag_mask = 0x3F,
3257 .tbuf_offset = 0x0600,
3258 .hfb_offset = 0x8000,
3259 .hfb_reg_offset = 0xfc00,
3260 .rdma_offset = 0x10000,
3261 .tdma_offset = 0x11000,
3262 .words_per_bd = 2,
3263 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR |
3264 GENET_HAS_MOCA_LINK_DET,
3265 },
3266 [GENET_V4] = {
3267 .tx_queues = 4,
3268 .tx_bds_per_q = 32,
3269 .rx_queues = 0,
3270 .rx_bds_per_q = 0,
3271 .bp_in_en_shift = 17,
3272 .bp_in_mask = 0x1ffff,
3273 .hfb_filter_cnt = 48,
3274 .hfb_filter_size = 128,
3275 .qtag_mask = 0x3F,
3276 .tbuf_offset = 0x0600,
3277 .hfb_offset = 0x8000,
3278 .hfb_reg_offset = 0xfc00,
3279 .rdma_offset = 0x2000,
3280 .tdma_offset = 0x4000,
3281 .words_per_bd = 3,
3282 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3283 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3284 },
3285 [GENET_V5] = {
3286 .tx_queues = 4,
3287 .tx_bds_per_q = 32,
3288 .rx_queues = 0,
3289 .rx_bds_per_q = 0,
3290 .bp_in_en_shift = 17,
3291 .bp_in_mask = 0x1ffff,
3292 .hfb_filter_cnt = 48,
3293 .hfb_filter_size = 128,
3294 .qtag_mask = 0x3F,
3295 .tbuf_offset = 0x0600,
3296 .hfb_offset = 0x8000,
3297 .hfb_reg_offset = 0xfc00,
3298 .rdma_offset = 0x2000,
3299 .tdma_offset = 0x4000,
3300 .words_per_bd = 3,
3301 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3302 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3303 },
3304 };
3305
3306 /* Infer hardware parameters from the detected GENET version */
3307 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
3308 {
3309 struct bcmgenet_hw_params *params;
3310 u32 reg;
3311 u8 major;
3312 u16 gphy_rev;
3313
3314 if (GENET_IS_V5(priv) || GENET_IS_V4(priv)) {
3315 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3316 genet_dma_ring_regs = genet_dma_ring_regs_v4;
3317 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3318 } else if (GENET_IS_V3(priv)) {
3319 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3320 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3321 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3322 } else if (GENET_IS_V2(priv)) {
3323 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
3324 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3325 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3326 } else if (GENET_IS_V1(priv)) {
3327 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
3328 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3329 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3330 }
3331
3332 /* enum genet_version starts at 1 */
3333 priv->hw_params = &bcmgenet_hw_params[priv->version];
3334 params = priv->hw_params;
3335
3336 /* Read GENET HW version */
3337 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
3338 major = (reg >> 24 & 0x0f);
3339 if (major == 6)
3340 major = 5;
3341 else if (major == 5)
3342 major = 4;
3343 else if (major == 0)
3344 major = 1;
3345 if (major != priv->version) {
3346 dev_err(&priv->pdev->dev,
3347 "GENET version mismatch, got: %d, configured for: %d\n",
3348 major, priv->version);
3349 }
3350
3351 /* Print the GENET core version */
3352 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
3353 major, (reg >> 16) & 0x0f, reg & 0xffff);
3354
3355 /* Store the integrated PHY revision for the MDIO probing function
3356 * to pass this information to the PHY driver. The PHY driver expects
3357 * to find the PHY major revision in bits 15:8 while the GENET register
3358 * stores that information in bits 7:0, account for that.
3359 *
3360 * On newer chips, starting with PHY revision G0, a new scheme is
3361 * deployed similar to the Starfighter 2 switch with GPHY major
3362 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
3363 * is reserved as well as special value 0x01ff, we have a small
3364 * heuristic to check for the new GPHY revision and re-arrange things
3365 * so the GPHY driver is happy.
3366 */
3367 gphy_rev = reg & 0xffff;
3368
3369 if (GENET_IS_V5(priv)) {
3370 /* The EPHY revision should come from the MDIO registers of
3371 * the PHY not from GENET.
3372 */
3373 if (gphy_rev != 0) {
3374 pr_warn("GENET is reporting EPHY revision: 0x%04x\n",
3375 gphy_rev);
3376 }
3377 /* This is reserved so should require special treatment */
3378 } else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
3379 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
3380 return;
3381 /* This is the good old scheme, just GPHY major, no minor nor patch */
3382 } else if ((gphy_rev & 0xf0) != 0) {
3383 priv->gphy_rev = gphy_rev << 8;
3384 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
3385 } else if ((gphy_rev & 0xff00) != 0) {
3386 priv->gphy_rev = gphy_rev;
3387 }
3388
3389 #ifdef CONFIG_PHYS_ADDR_T_64BIT
3390 if (!(params->flags & GENET_HAS_40BITS))
3391 pr_warn("GENET does not support 40-bits PA\n");
3392 #endif
3393
3394 pr_debug("Configuration for version: %d\n"
3395 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n"
3396 "BP << en: %2d, BP msk: 0x%05x\n"
3397 "HFB count: %2d, QTAQ msk: 0x%05x\n"
3398 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
3399 "RDMA: 0x%05x, TDMA: 0x%05x\n"
3400 "Words/BD: %d\n",
3401 priv->version,
3402 params->tx_queues, params->tx_bds_per_q,
3403 params->rx_queues, params->rx_bds_per_q,
3404 params->bp_in_en_shift, params->bp_in_mask,
3405 params->hfb_filter_cnt, params->qtag_mask,
3406 params->tbuf_offset, params->hfb_offset,
3407 params->hfb_reg_offset,
3408 params->rdma_offset, params->tdma_offset,
3409 params->words_per_bd);
3410 }
3411
3412 static const struct of_device_id bcmgenet_match[] = {
3413 { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
3414 { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
3415 { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
3416 { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
3417 { .compatible = "brcm,genet-v5", .data = (void *)GENET_V5 },
3418 { },
3419 };
3420 MODULE_DEVICE_TABLE(of, bcmgenet_match);
3421
3422 static int bcmgenet_probe(struct platform_device *pdev)
3423 {
3424 struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
3425 struct device_node *dn = pdev->dev.of_node;
3426 const struct of_device_id *of_id = NULL;
3427 struct bcmgenet_priv *priv;
3428 struct net_device *dev;
3429 const void *macaddr;
3430 struct resource *r;
3431 int err = -EIO;
3432 const char *phy_mode_str;
3433
3434 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */
3435 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1,
3436 GENET_MAX_MQ_CNT + 1);
3437 if (!dev) {
3438 dev_err(&pdev->dev, "can't allocate net device\n");
3439 return -ENOMEM;
3440 }
3441
3442 if (dn) {
3443 of_id = of_match_node(bcmgenet_match, dn);
3444 if (!of_id)
3445 return -EINVAL;
3446 }
3447
3448 priv = netdev_priv(dev);
3449 priv->irq0 = platform_get_irq(pdev, 0);
3450 priv->irq1 = platform_get_irq(pdev, 1);
3451 priv->wol_irq = platform_get_irq(pdev, 2);
3452 if (!priv->irq0 || !priv->irq1) {
3453 dev_err(&pdev->dev, "can't find IRQs\n");
3454 err = -EINVAL;
3455 goto err;
3456 }
3457
3458 if (dn) {
3459 macaddr = of_get_mac_address(dn);
3460 if (!macaddr) {
3461 dev_err(&pdev->dev, "can't find MAC address\n");
3462 err = -EINVAL;
3463 goto err;
3464 }
3465 } else {
3466 macaddr = pd->mac_address;
3467 }
3468
3469 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3470 priv->base = devm_ioremap_resource(&pdev->dev, r);
3471 if (IS_ERR(priv->base)) {
3472 err = PTR_ERR(priv->base);
3473 goto err;
3474 }
3475
3476 spin_lock_init(&priv->lock);
3477
3478 SET_NETDEV_DEV(dev, &pdev->dev);
3479 dev_set_drvdata(&pdev->dev, dev);
3480 ether_addr_copy(dev->dev_addr, macaddr);
3481 dev->watchdog_timeo = 2 * HZ;
3482 dev->ethtool_ops = &bcmgenet_ethtool_ops;
3483 dev->netdev_ops = &bcmgenet_netdev_ops;
3484
3485 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
3486
3487 /* Set hardware features */
3488 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
3489 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
3490
3491 /* Request the WOL interrupt and advertise suspend if available */
3492 priv->wol_irq_disabled = true;
3493 err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0,
3494 dev->name, priv);
3495 if (!err)
3496 device_set_wakeup_capable(&pdev->dev, 1);
3497
3498 /* Set the needed headroom to account for any possible
3499 * features enabling/disabling at runtime
3500 */
3501 dev->needed_headroom += 64;
3502
3503 netdev_boot_setup_check(dev);
3504
3505 priv->dev = dev;
3506 priv->pdev = pdev;
3507 if (of_id)
3508 priv->version = (enum bcmgenet_version)of_id->data;
3509 else
3510 priv->version = pd->genet_version;
3511
3512 priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
3513 if (IS_ERR(priv->clk)) {
3514 dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
3515 priv->clk = NULL;
3516 }
3517
3518 clk_prepare_enable(priv->clk);
3519
3520 bcmgenet_set_hw_params(priv);
3521
3522 /* Mii wait queue */
3523 init_waitqueue_head(&priv->wq);
3524 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
3525 priv->rx_buf_len = RX_BUF_LENGTH;
3526 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
3527
3528 priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
3529 if (IS_ERR(priv->clk_wol)) {
3530 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
3531 priv->clk_wol = NULL;
3532 }
3533
3534 priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee");
3535 if (IS_ERR(priv->clk_eee)) {
3536 dev_warn(&priv->pdev->dev, "failed to get enet-eee clock\n");
3537 priv->clk_eee = NULL;
3538 }
3539
3540 /* If this is an internal GPHY, power it on now, before UniMAC is
3541 * brought out of reset as absolutely no UniMAC activity is allowed
3542 */
3543 if (dn && !of_property_read_string(dn, "phy-mode", &phy_mode_str) &&
3544 !strcasecmp(phy_mode_str, "internal"))
3545 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3546
3547 err = reset_umac(priv);
3548 if (err)
3549 goto err_clk_disable;
3550
3551 err = bcmgenet_mii_init(dev);
3552 if (err)
3553 goto err_clk_disable;
3554
3555 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues
3556 * just the ring 16 descriptor based TX
3557 */
3558 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
3559 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
3560
3561 /* libphy will determine the link state */
3562 netif_carrier_off(dev);
3563
3564 /* Turn off the main clock, WOL clock is handled separately */
3565 clk_disable_unprepare(priv->clk);
3566
3567 err = register_netdev(dev);
3568 if (err)
3569 goto err;
3570
3571 return err;
3572
3573 err_clk_disable:
3574 clk_disable_unprepare(priv->clk);
3575 err:
3576 free_netdev(dev);
3577 return err;
3578 }
3579
3580 static int bcmgenet_remove(struct platform_device *pdev)
3581 {
3582 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
3583
3584 dev_set_drvdata(&pdev->dev, NULL);
3585 unregister_netdev(priv->dev);
3586 bcmgenet_mii_exit(priv->dev);
3587 free_netdev(priv->dev);
3588
3589 return 0;
3590 }
3591
3592 #ifdef CONFIG_PM_SLEEP
3593 static int bcmgenet_suspend(struct device *d)
3594 {
3595 struct net_device *dev = dev_get_drvdata(d);
3596 struct bcmgenet_priv *priv = netdev_priv(dev);
3597 int ret;
3598
3599 if (!netif_running(dev))
3600 return 0;
3601
3602 bcmgenet_netif_stop(dev);
3603
3604 if (!device_may_wakeup(d))
3605 phy_suspend(priv->phydev);
3606
3607 netif_device_detach(dev);
3608
3609 /* Disable MAC receive */
3610 umac_enable_set(priv, CMD_RX_EN, false);
3611
3612 ret = bcmgenet_dma_teardown(priv);
3613 if (ret)
3614 return ret;
3615
3616 /* Disable MAC transmit. TX DMA disabled must be done before this */
3617 umac_enable_set(priv, CMD_TX_EN, false);
3618
3619 /* tx reclaim */
3620 bcmgenet_tx_reclaim_all(dev);
3621 bcmgenet_fini_dma(priv);
3622
3623 /* Prepare the device for Wake-on-LAN and switch to the slow clock */
3624 if (device_may_wakeup(d) && priv->wolopts) {
3625 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
3626 clk_prepare_enable(priv->clk_wol);
3627 } else if (priv->internal_phy) {
3628 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3629 }
3630
3631 /* Turn off the clocks */
3632 clk_disable_unprepare(priv->clk);
3633
3634 return ret;
3635 }
3636
3637 static int bcmgenet_resume(struct device *d)
3638 {
3639 struct net_device *dev = dev_get_drvdata(d);
3640 struct bcmgenet_priv *priv = netdev_priv(dev);
3641 unsigned long dma_ctrl;
3642 int ret;
3643 u32 reg;
3644
3645 if (!netif_running(dev))
3646 return 0;
3647
3648 /* Turn on the clock */
3649 ret = clk_prepare_enable(priv->clk);
3650 if (ret)
3651 return ret;
3652
3653 /* If this is an internal GPHY, power it back on now, before UniMAC is
3654 * brought out of reset as absolutely no UniMAC activity is allowed
3655 */
3656 if (priv->internal_phy)
3657 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3658
3659 bcmgenet_umac_reset(priv);
3660
3661 ret = init_umac(priv);
3662 if (ret)
3663 goto out_clk_disable;
3664
3665 /* From WOL-enabled suspend, switch to regular clock */
3666 if (priv->wolopts)
3667 clk_disable_unprepare(priv->clk_wol);
3668
3669 phy_init_hw(priv->phydev);
3670 /* Speed settings must be restored */
3671 bcmgenet_mii_config(priv->dev);
3672
3673 /* disable ethernet MAC while updating its registers */
3674 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
3675
3676 bcmgenet_set_hw_addr(priv, dev->dev_addr);
3677
3678 if (priv->internal_phy) {
3679 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
3680 reg |= EXT_ENERGY_DET_MASK;
3681 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
3682 }
3683
3684 if (priv->wolopts)
3685 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
3686
3687 /* Disable RX/TX DMA and flush TX queues */
3688 dma_ctrl = bcmgenet_dma_disable(priv);
3689
3690 /* Reinitialize TDMA and RDMA and SW housekeeping */
3691 ret = bcmgenet_init_dma(priv);
3692 if (ret) {
3693 netdev_err(dev, "failed to initialize DMA\n");
3694 goto out_clk_disable;
3695 }
3696
3697 /* Always enable ring 16 - descriptor ring */
3698 bcmgenet_enable_dma(priv, dma_ctrl);
3699
3700 netif_device_attach(dev);
3701
3702 if (!device_may_wakeup(d))
3703 phy_resume(priv->phydev);
3704
3705 if (priv->eee.eee_enabled)
3706 bcmgenet_eee_enable_set(dev, true);
3707
3708 bcmgenet_netif_start(dev);
3709
3710 return 0;
3711
3712 out_clk_disable:
3713 if (priv->internal_phy)
3714 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3715 clk_disable_unprepare(priv->clk);
3716 return ret;
3717 }
3718 #endif /* CONFIG_PM_SLEEP */
3719
3720 static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume);
3721
3722 static struct platform_driver bcmgenet_driver = {
3723 .probe = bcmgenet_probe,
3724 .remove = bcmgenet_remove,
3725 .driver = {
3726 .name = "bcmgenet",
3727 .of_match_table = bcmgenet_match,
3728 .pm = &bcmgenet_pm_ops,
3729 },
3730 };
3731 module_platform_driver(bcmgenet_driver);
3732
3733 MODULE_AUTHOR("Broadcom Corporation");
3734 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
3735 MODULE_ALIAS("platform:bcmgenet");
3736 MODULE_LICENSE("GPL");
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