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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/sage/ceph...
[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / broadcom / genet / bcmgenet.c
1 /*
2 * Broadcom GENET (Gigabit Ethernet) controller driver
3 *
4 * Copyright (c) 2014 Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 */
19
20 #define pr_fmt(fmt) "bcmgenet: " fmt
21
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/sched.h>
25 #include <linux/types.h>
26 #include <linux/fcntl.h>
27 #include <linux/interrupt.h>
28 #include <linux/string.h>
29 #include <linux/if_ether.h>
30 #include <linux/init.h>
31 #include <linux/errno.h>
32 #include <linux/delay.h>
33 #include <linux/platform_device.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/pm.h>
36 #include <linux/clk.h>
37 #include <linux/version.h>
38 #include <linux/of.h>
39 #include <linux/of_address.h>
40 #include <linux/of_irq.h>
41 #include <linux/of_net.h>
42 #include <linux/of_platform.h>
43 #include <net/arp.h>
44
45 #include <linux/mii.h>
46 #include <linux/ethtool.h>
47 #include <linux/netdevice.h>
48 #include <linux/inetdevice.h>
49 #include <linux/etherdevice.h>
50 #include <linux/skbuff.h>
51 #include <linux/in.h>
52 #include <linux/ip.h>
53 #include <linux/ipv6.h>
54 #include <linux/phy.h>
55
56 #include <asm/unaligned.h>
57
58 #include "bcmgenet.h"
59
60 /* Maximum number of hardware queues, downsized if needed */
61 #define GENET_MAX_MQ_CNT 4
62
63 /* Default highest priority queue for multi queue support */
64 #define GENET_Q0_PRIORITY 0
65
66 #define GENET_DEFAULT_BD_CNT \
67 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->bds_cnt)
68
69 #define RX_BUF_LENGTH 2048
70 #define SKB_ALIGNMENT 32
71
72 /* Tx/Rx DMA register offset, skip 256 descriptors */
73 #define WORDS_PER_BD(p) (p->hw_params->words_per_bd)
74 #define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32))
75
76 #define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \
77 TOTAL_DESC * DMA_DESC_SIZE)
78
79 #define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \
80 TOTAL_DESC * DMA_DESC_SIZE)
81
82 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
83 void __iomem *d, u32 value)
84 {
85 __raw_writel(value, d + DMA_DESC_LENGTH_STATUS);
86 }
87
88 static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
89 void __iomem *d)
90 {
91 return __raw_readl(d + DMA_DESC_LENGTH_STATUS);
92 }
93
94 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
95 void __iomem *d,
96 dma_addr_t addr)
97 {
98 __raw_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
99
100 /* Register writes to GISB bus can take couple hundred nanoseconds
101 * and are done for each packet, save these expensive writes unless
102 * the platform is explicitely configured for 64-bits/LPAE.
103 */
104 #ifdef CONFIG_PHYS_ADDR_T_64BIT
105 if (priv->hw_params->flags & GENET_HAS_40BITS)
106 __raw_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
107 #endif
108 }
109
110 /* Combined address + length/status setter */
111 static inline void dmadesc_set(struct bcmgenet_priv *priv,
112 void __iomem *d, dma_addr_t addr, u32 val)
113 {
114 dmadesc_set_length_status(priv, d, val);
115 dmadesc_set_addr(priv, d, addr);
116 }
117
118 static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
119 void __iomem *d)
120 {
121 dma_addr_t addr;
122
123 addr = __raw_readl(d + DMA_DESC_ADDRESS_LO);
124
125 /* Register writes to GISB bus can take couple hundred nanoseconds
126 * and are done for each packet, save these expensive writes unless
127 * the platform is explicitely configured for 64-bits/LPAE.
128 */
129 #ifdef CONFIG_PHYS_ADDR_T_64BIT
130 if (priv->hw_params->flags & GENET_HAS_40BITS)
131 addr |= (u64)__raw_readl(d + DMA_DESC_ADDRESS_HI) << 32;
132 #endif
133 return addr;
134 }
135
136 #define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x"
137
138 #define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
139 NETIF_MSG_LINK)
140
141 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
142 {
143 if (GENET_IS_V1(priv))
144 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
145 else
146 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
147 }
148
149 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
150 {
151 if (GENET_IS_V1(priv))
152 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
153 else
154 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
155 }
156
157 /* These macros are defined to deal with register map change
158 * between GENET1.1 and GENET2. Only those currently being used
159 * by driver are defined.
160 */
161 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
162 {
163 if (GENET_IS_V1(priv))
164 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
165 else
166 return __raw_readl(priv->base +
167 priv->hw_params->tbuf_offset + TBUF_CTRL);
168 }
169
170 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
171 {
172 if (GENET_IS_V1(priv))
173 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
174 else
175 __raw_writel(val, priv->base +
176 priv->hw_params->tbuf_offset + TBUF_CTRL);
177 }
178
179 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
180 {
181 if (GENET_IS_V1(priv))
182 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
183 else
184 return __raw_readl(priv->base +
185 priv->hw_params->tbuf_offset + TBUF_BP_MC);
186 }
187
188 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
189 {
190 if (GENET_IS_V1(priv))
191 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
192 else
193 __raw_writel(val, priv->base +
194 priv->hw_params->tbuf_offset + TBUF_BP_MC);
195 }
196
197 /* RX/TX DMA register accessors */
198 enum dma_reg {
199 DMA_RING_CFG = 0,
200 DMA_CTRL,
201 DMA_STATUS,
202 DMA_SCB_BURST_SIZE,
203 DMA_ARB_CTRL,
204 DMA_PRIORITY,
205 DMA_RING_PRIORITY,
206 };
207
208 static const u8 bcmgenet_dma_regs_v3plus[] = {
209 [DMA_RING_CFG] = 0x00,
210 [DMA_CTRL] = 0x04,
211 [DMA_STATUS] = 0x08,
212 [DMA_SCB_BURST_SIZE] = 0x0C,
213 [DMA_ARB_CTRL] = 0x2C,
214 [DMA_PRIORITY] = 0x30,
215 [DMA_RING_PRIORITY] = 0x38,
216 };
217
218 static const u8 bcmgenet_dma_regs_v2[] = {
219 [DMA_RING_CFG] = 0x00,
220 [DMA_CTRL] = 0x04,
221 [DMA_STATUS] = 0x08,
222 [DMA_SCB_BURST_SIZE] = 0x0C,
223 [DMA_ARB_CTRL] = 0x30,
224 [DMA_PRIORITY] = 0x34,
225 [DMA_RING_PRIORITY] = 0x3C,
226 };
227
228 static const u8 bcmgenet_dma_regs_v1[] = {
229 [DMA_CTRL] = 0x00,
230 [DMA_STATUS] = 0x04,
231 [DMA_SCB_BURST_SIZE] = 0x0C,
232 [DMA_ARB_CTRL] = 0x30,
233 [DMA_PRIORITY] = 0x34,
234 [DMA_RING_PRIORITY] = 0x3C,
235 };
236
237 /* Set at runtime once bcmgenet version is known */
238 static const u8 *bcmgenet_dma_regs;
239
240 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
241 {
242 return netdev_priv(dev_get_drvdata(dev));
243 }
244
245 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
246 enum dma_reg r)
247 {
248 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
249 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
250 }
251
252 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
253 u32 val, enum dma_reg r)
254 {
255 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
256 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
257 }
258
259 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
260 enum dma_reg r)
261 {
262 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
263 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
264 }
265
266 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
267 u32 val, enum dma_reg r)
268 {
269 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
270 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
271 }
272
273 /* RDMA/TDMA ring registers and accessors
274 * we merge the common fields and just prefix with T/D the registers
275 * having different meaning depending on the direction
276 */
277 enum dma_ring_reg {
278 TDMA_READ_PTR = 0,
279 RDMA_WRITE_PTR = TDMA_READ_PTR,
280 TDMA_READ_PTR_HI,
281 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
282 TDMA_CONS_INDEX,
283 RDMA_PROD_INDEX = TDMA_CONS_INDEX,
284 TDMA_PROD_INDEX,
285 RDMA_CONS_INDEX = TDMA_PROD_INDEX,
286 DMA_RING_BUF_SIZE,
287 DMA_START_ADDR,
288 DMA_START_ADDR_HI,
289 DMA_END_ADDR,
290 DMA_END_ADDR_HI,
291 DMA_MBUF_DONE_THRESH,
292 TDMA_FLOW_PERIOD,
293 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
294 TDMA_WRITE_PTR,
295 RDMA_READ_PTR = TDMA_WRITE_PTR,
296 TDMA_WRITE_PTR_HI,
297 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
298 };
299
300 /* GENET v4 supports 40-bits pointer addressing
301 * for obvious reasons the LO and HI word parts
302 * are contiguous, but this offsets the other
303 * registers.
304 */
305 static const u8 genet_dma_ring_regs_v4[] = {
306 [TDMA_READ_PTR] = 0x00,
307 [TDMA_READ_PTR_HI] = 0x04,
308 [TDMA_CONS_INDEX] = 0x08,
309 [TDMA_PROD_INDEX] = 0x0C,
310 [DMA_RING_BUF_SIZE] = 0x10,
311 [DMA_START_ADDR] = 0x14,
312 [DMA_START_ADDR_HI] = 0x18,
313 [DMA_END_ADDR] = 0x1C,
314 [DMA_END_ADDR_HI] = 0x20,
315 [DMA_MBUF_DONE_THRESH] = 0x24,
316 [TDMA_FLOW_PERIOD] = 0x28,
317 [TDMA_WRITE_PTR] = 0x2C,
318 [TDMA_WRITE_PTR_HI] = 0x30,
319 };
320
321 static const u8 genet_dma_ring_regs_v123[] = {
322 [TDMA_READ_PTR] = 0x00,
323 [TDMA_CONS_INDEX] = 0x04,
324 [TDMA_PROD_INDEX] = 0x08,
325 [DMA_RING_BUF_SIZE] = 0x0C,
326 [DMA_START_ADDR] = 0x10,
327 [DMA_END_ADDR] = 0x14,
328 [DMA_MBUF_DONE_THRESH] = 0x18,
329 [TDMA_FLOW_PERIOD] = 0x1C,
330 [TDMA_WRITE_PTR] = 0x20,
331 };
332
333 /* Set at runtime once GENET version is known */
334 static const u8 *genet_dma_ring_regs;
335
336 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
337 unsigned int ring,
338 enum dma_ring_reg r)
339 {
340 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
341 (DMA_RING_SIZE * ring) +
342 genet_dma_ring_regs[r]);
343 }
344
345 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
346 unsigned int ring,
347 u32 val,
348 enum dma_ring_reg r)
349 {
350 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
351 (DMA_RING_SIZE * ring) +
352 genet_dma_ring_regs[r]);
353 }
354
355 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
356 unsigned int ring,
357 enum dma_ring_reg r)
358 {
359 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
360 (DMA_RING_SIZE * ring) +
361 genet_dma_ring_regs[r]);
362 }
363
364 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
365 unsigned int ring,
366 u32 val,
367 enum dma_ring_reg r)
368 {
369 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
370 (DMA_RING_SIZE * ring) +
371 genet_dma_ring_regs[r]);
372 }
373
374 static int bcmgenet_get_settings(struct net_device *dev,
375 struct ethtool_cmd *cmd)
376 {
377 struct bcmgenet_priv *priv = netdev_priv(dev);
378
379 if (!netif_running(dev))
380 return -EINVAL;
381
382 if (!priv->phydev)
383 return -ENODEV;
384
385 return phy_ethtool_gset(priv->phydev, cmd);
386 }
387
388 static int bcmgenet_set_settings(struct net_device *dev,
389 struct ethtool_cmd *cmd)
390 {
391 struct bcmgenet_priv *priv = netdev_priv(dev);
392
393 if (!netif_running(dev))
394 return -EINVAL;
395
396 if (!priv->phydev)
397 return -ENODEV;
398
399 return phy_ethtool_sset(priv->phydev, cmd);
400 }
401
402 static int bcmgenet_set_rx_csum(struct net_device *dev,
403 netdev_features_t wanted)
404 {
405 struct bcmgenet_priv *priv = netdev_priv(dev);
406 u32 rbuf_chk_ctrl;
407 bool rx_csum_en;
408
409 rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
410
411 rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
412
413 /* enable rx checksumming */
414 if (rx_csum_en)
415 rbuf_chk_ctrl |= RBUF_RXCHK_EN;
416 else
417 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
418 priv->desc_rxchk_en = rx_csum_en;
419
420 /* If UniMAC forwards CRC, we need to skip over it to get
421 * a valid CHK bit to be set in the per-packet status word
422 */
423 if (rx_csum_en && priv->crc_fwd_en)
424 rbuf_chk_ctrl |= RBUF_SKIP_FCS;
425 else
426 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
427
428 bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
429
430 return 0;
431 }
432
433 static int bcmgenet_set_tx_csum(struct net_device *dev,
434 netdev_features_t wanted)
435 {
436 struct bcmgenet_priv *priv = netdev_priv(dev);
437 bool desc_64b_en;
438 u32 tbuf_ctrl, rbuf_ctrl;
439
440 tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
441 rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
442
443 desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
444
445 /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
446 if (desc_64b_en) {
447 tbuf_ctrl |= RBUF_64B_EN;
448 rbuf_ctrl |= RBUF_64B_EN;
449 } else {
450 tbuf_ctrl &= ~RBUF_64B_EN;
451 rbuf_ctrl &= ~RBUF_64B_EN;
452 }
453 priv->desc_64b_en = desc_64b_en;
454
455 bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
456 bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
457
458 return 0;
459 }
460
461 static int bcmgenet_set_features(struct net_device *dev,
462 netdev_features_t features)
463 {
464 netdev_features_t changed = features ^ dev->features;
465 netdev_features_t wanted = dev->wanted_features;
466 int ret = 0;
467
468 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
469 ret = bcmgenet_set_tx_csum(dev, wanted);
470 if (changed & (NETIF_F_RXCSUM))
471 ret = bcmgenet_set_rx_csum(dev, wanted);
472
473 return ret;
474 }
475
476 static u32 bcmgenet_get_msglevel(struct net_device *dev)
477 {
478 struct bcmgenet_priv *priv = netdev_priv(dev);
479
480 return priv->msg_enable;
481 }
482
483 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
484 {
485 struct bcmgenet_priv *priv = netdev_priv(dev);
486
487 priv->msg_enable = level;
488 }
489
490 /* standard ethtool support functions. */
491 enum bcmgenet_stat_type {
492 BCMGENET_STAT_NETDEV = -1,
493 BCMGENET_STAT_MIB_RX,
494 BCMGENET_STAT_MIB_TX,
495 BCMGENET_STAT_RUNT,
496 BCMGENET_STAT_MISC,
497 };
498
499 struct bcmgenet_stats {
500 char stat_string[ETH_GSTRING_LEN];
501 int stat_sizeof;
502 int stat_offset;
503 enum bcmgenet_stat_type type;
504 /* reg offset from UMAC base for misc counters */
505 u16 reg_offset;
506 };
507
508 #define STAT_NETDEV(m) { \
509 .stat_string = __stringify(m), \
510 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
511 .stat_offset = offsetof(struct net_device_stats, m), \
512 .type = BCMGENET_STAT_NETDEV, \
513 }
514
515 #define STAT_GENET_MIB(str, m, _type) { \
516 .stat_string = str, \
517 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
518 .stat_offset = offsetof(struct bcmgenet_priv, m), \
519 .type = _type, \
520 }
521
522 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
523 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
524 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
525
526 #define STAT_GENET_MISC(str, m, offset) { \
527 .stat_string = str, \
528 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
529 .stat_offset = offsetof(struct bcmgenet_priv, m), \
530 .type = BCMGENET_STAT_MISC, \
531 .reg_offset = offset, \
532 }
533
534
535 /* There is a 0xC gap between the end of RX and beginning of TX stats and then
536 * between the end of TX stats and the beginning of the RX RUNT
537 */
538 #define BCMGENET_STAT_OFFSET 0xc
539
540 /* Hardware counters must be kept in sync because the order/offset
541 * is important here (order in structure declaration = order in hardware)
542 */
543 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
544 /* general stats */
545 STAT_NETDEV(rx_packets),
546 STAT_NETDEV(tx_packets),
547 STAT_NETDEV(rx_bytes),
548 STAT_NETDEV(tx_bytes),
549 STAT_NETDEV(rx_errors),
550 STAT_NETDEV(tx_errors),
551 STAT_NETDEV(rx_dropped),
552 STAT_NETDEV(tx_dropped),
553 STAT_NETDEV(multicast),
554 /* UniMAC RSV counters */
555 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
556 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
557 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
558 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
559 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
560 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
561 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
562 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
563 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
564 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
565 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
566 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
567 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
568 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
569 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
570 STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
571 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
572 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
573 STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
574 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
575 STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
576 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
577 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
578 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
579 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
580 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
581 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
582 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
583 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
584 /* UniMAC TSV counters */
585 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
586 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
587 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
588 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
589 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
590 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
591 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
592 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
593 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
594 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
595 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
596 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
597 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
598 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
599 STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
600 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
601 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
602 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
603 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
604 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
605 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
606 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
607 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
608 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
609 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
610 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
611 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
612 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
613 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
614 /* UniMAC RUNT counters */
615 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
616 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
617 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
618 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
619 /* Misc UniMAC counters */
620 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
621 UMAC_RBUF_OVFL_CNT),
622 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, UMAC_RBUF_ERR_CNT),
623 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
624 };
625
626 #define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats)
627
628 static void bcmgenet_get_drvinfo(struct net_device *dev,
629 struct ethtool_drvinfo *info)
630 {
631 strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
632 strlcpy(info->version, "v2.0", sizeof(info->version));
633 info->n_stats = BCMGENET_STATS_LEN;
634
635 }
636
637 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
638 {
639 switch (string_set) {
640 case ETH_SS_STATS:
641 return BCMGENET_STATS_LEN;
642 default:
643 return -EOPNOTSUPP;
644 }
645 }
646
647 static void bcmgenet_get_strings(struct net_device *dev,
648 u32 stringset, u8 *data)
649 {
650 int i;
651
652 switch (stringset) {
653 case ETH_SS_STATS:
654 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
655 memcpy(data + i * ETH_GSTRING_LEN,
656 bcmgenet_gstrings_stats[i].stat_string,
657 ETH_GSTRING_LEN);
658 }
659 break;
660 }
661 }
662
663 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
664 {
665 int i, j = 0;
666
667 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
668 const struct bcmgenet_stats *s;
669 u8 offset = 0;
670 u32 val = 0;
671 char *p;
672
673 s = &bcmgenet_gstrings_stats[i];
674 switch (s->type) {
675 case BCMGENET_STAT_NETDEV:
676 continue;
677 case BCMGENET_STAT_MIB_RX:
678 case BCMGENET_STAT_MIB_TX:
679 case BCMGENET_STAT_RUNT:
680 if (s->type != BCMGENET_STAT_MIB_RX)
681 offset = BCMGENET_STAT_OFFSET;
682 val = bcmgenet_umac_readl(priv, UMAC_MIB_START +
683 j + offset);
684 break;
685 case BCMGENET_STAT_MISC:
686 val = bcmgenet_umac_readl(priv, s->reg_offset);
687 /* clear if overflowed */
688 if (val == ~0)
689 bcmgenet_umac_writel(priv, 0, s->reg_offset);
690 break;
691 }
692
693 j += s->stat_sizeof;
694 p = (char *)priv + s->stat_offset;
695 *(u32 *)p = val;
696 }
697 }
698
699 static void bcmgenet_get_ethtool_stats(struct net_device *dev,
700 struct ethtool_stats *stats,
701 u64 *data)
702 {
703 struct bcmgenet_priv *priv = netdev_priv(dev);
704 int i;
705
706 if (netif_running(dev))
707 bcmgenet_update_mib_counters(priv);
708
709 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
710 const struct bcmgenet_stats *s;
711 char *p;
712
713 s = &bcmgenet_gstrings_stats[i];
714 if (s->type == BCMGENET_STAT_NETDEV)
715 p = (char *)&dev->stats;
716 else
717 p = (char *)priv;
718 p += s->stat_offset;
719 data[i] = *(u32 *)p;
720 }
721 }
722
723 /* standard ethtool support functions. */
724 static struct ethtool_ops bcmgenet_ethtool_ops = {
725 .get_strings = bcmgenet_get_strings,
726 .get_sset_count = bcmgenet_get_sset_count,
727 .get_ethtool_stats = bcmgenet_get_ethtool_stats,
728 .get_settings = bcmgenet_get_settings,
729 .set_settings = bcmgenet_set_settings,
730 .get_drvinfo = bcmgenet_get_drvinfo,
731 .get_link = ethtool_op_get_link,
732 .get_msglevel = bcmgenet_get_msglevel,
733 .set_msglevel = bcmgenet_set_msglevel,
734 };
735
736 /* Power down the unimac, based on mode. */
737 static void bcmgenet_power_down(struct bcmgenet_priv *priv,
738 enum bcmgenet_power_mode mode)
739 {
740 u32 reg;
741
742 switch (mode) {
743 case GENET_POWER_CABLE_SENSE:
744 phy_detach(priv->phydev);
745 break;
746
747 case GENET_POWER_PASSIVE:
748 /* Power down LED */
749 bcmgenet_mii_reset(priv->dev);
750 if (priv->hw_params->flags & GENET_HAS_EXT) {
751 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
752 reg |= (EXT_PWR_DOWN_PHY |
753 EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
754 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
755 }
756 break;
757 default:
758 break;
759 }
760 }
761
762 static void bcmgenet_power_up(struct bcmgenet_priv *priv,
763 enum bcmgenet_power_mode mode)
764 {
765 u32 reg;
766
767 if (!(priv->hw_params->flags & GENET_HAS_EXT))
768 return;
769
770 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
771
772 switch (mode) {
773 case GENET_POWER_PASSIVE:
774 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_PHY |
775 EXT_PWR_DOWN_BIAS);
776 /* fallthrough */
777 case GENET_POWER_CABLE_SENSE:
778 /* enable APD */
779 reg |= EXT_PWR_DN_EN_LD;
780 break;
781 default:
782 break;
783 }
784
785 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
786 bcmgenet_mii_reset(priv->dev);
787 }
788
789 /* ioctl handle special commands that are not present in ethtool. */
790 static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
791 {
792 struct bcmgenet_priv *priv = netdev_priv(dev);
793 int val = 0;
794
795 if (!netif_running(dev))
796 return -EINVAL;
797
798 switch (cmd) {
799 case SIOCGMIIPHY:
800 case SIOCGMIIREG:
801 case SIOCSMIIREG:
802 if (!priv->phydev)
803 val = -ENODEV;
804 else
805 val = phy_mii_ioctl(priv->phydev, rq, cmd);
806 break;
807
808 default:
809 val = -EINVAL;
810 break;
811 }
812
813 return val;
814 }
815
816 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
817 struct bcmgenet_tx_ring *ring)
818 {
819 struct enet_cb *tx_cb_ptr;
820
821 tx_cb_ptr = ring->cbs;
822 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
823 tx_cb_ptr->bd_addr = priv->tx_bds + ring->write_ptr * DMA_DESC_SIZE;
824 /* Advancing local write pointer */
825 if (ring->write_ptr == ring->end_ptr)
826 ring->write_ptr = ring->cb_ptr;
827 else
828 ring->write_ptr++;
829
830 return tx_cb_ptr;
831 }
832
833 /* Simple helper to free a control block's resources */
834 static void bcmgenet_free_cb(struct enet_cb *cb)
835 {
836 dev_kfree_skb_any(cb->skb);
837 cb->skb = NULL;
838 dma_unmap_addr_set(cb, dma_addr, 0);
839 }
840
841 static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_priv *priv,
842 struct bcmgenet_tx_ring *ring)
843 {
844 bcmgenet_intrl2_0_writel(priv,
845 UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE,
846 INTRL2_CPU_MASK_SET);
847 }
848
849 static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_priv *priv,
850 struct bcmgenet_tx_ring *ring)
851 {
852 bcmgenet_intrl2_0_writel(priv,
853 UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE,
854 INTRL2_CPU_MASK_CLEAR);
855 }
856
857 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_priv *priv,
858 struct bcmgenet_tx_ring *ring)
859 {
860 bcmgenet_intrl2_1_writel(priv,
861 (1 << ring->index), INTRL2_CPU_MASK_CLEAR);
862 priv->int1_mask &= ~(1 << ring->index);
863 }
864
865 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_priv *priv,
866 struct bcmgenet_tx_ring *ring)
867 {
868 bcmgenet_intrl2_1_writel(priv,
869 (1 << ring->index), INTRL2_CPU_MASK_SET);
870 priv->int1_mask |= (1 << ring->index);
871 }
872
873 /* Unlocked version of the reclaim routine */
874 static void __bcmgenet_tx_reclaim(struct net_device *dev,
875 struct bcmgenet_tx_ring *ring)
876 {
877 struct bcmgenet_priv *priv = netdev_priv(dev);
878 int last_tx_cn, last_c_index, num_tx_bds;
879 struct enet_cb *tx_cb_ptr;
880 struct netdev_queue *txq;
881 unsigned int c_index;
882
883 /* Compute how many buffers are transmited since last xmit call */
884 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
885 txq = netdev_get_tx_queue(dev, ring->queue);
886
887 last_c_index = ring->c_index;
888 num_tx_bds = ring->size;
889
890 c_index &= (num_tx_bds - 1);
891
892 if (c_index >= last_c_index)
893 last_tx_cn = c_index - last_c_index;
894 else
895 last_tx_cn = num_tx_bds - last_c_index + c_index;
896
897 netif_dbg(priv, tx_done, dev,
898 "%s ring=%d index=%d last_tx_cn=%d last_index=%d\n",
899 __func__, ring->index,
900 c_index, last_tx_cn, last_c_index);
901
902 /* Reclaim transmitted buffers */
903 while (last_tx_cn-- > 0) {
904 tx_cb_ptr = ring->cbs + last_c_index;
905 if (tx_cb_ptr->skb) {
906 dev->stats.tx_bytes += tx_cb_ptr->skb->len;
907 dma_unmap_single(&dev->dev,
908 dma_unmap_addr(tx_cb_ptr, dma_addr),
909 tx_cb_ptr->skb->len,
910 DMA_TO_DEVICE);
911 bcmgenet_free_cb(tx_cb_ptr);
912 } else if (dma_unmap_addr(tx_cb_ptr, dma_addr)) {
913 dev->stats.tx_bytes +=
914 dma_unmap_len(tx_cb_ptr, dma_len);
915 dma_unmap_page(&dev->dev,
916 dma_unmap_addr(tx_cb_ptr, dma_addr),
917 dma_unmap_len(tx_cb_ptr, dma_len),
918 DMA_TO_DEVICE);
919 dma_unmap_addr_set(tx_cb_ptr, dma_addr, 0);
920 }
921 dev->stats.tx_packets++;
922 ring->free_bds += 1;
923
924 last_c_index++;
925 last_c_index &= (num_tx_bds - 1);
926 }
927
928 if (ring->free_bds > (MAX_SKB_FRAGS + 1))
929 ring->int_disable(priv, ring);
930
931 if (netif_tx_queue_stopped(txq))
932 netif_tx_wake_queue(txq);
933
934 ring->c_index = c_index;
935 }
936
937 static void bcmgenet_tx_reclaim(struct net_device *dev,
938 struct bcmgenet_tx_ring *ring)
939 {
940 unsigned long flags;
941
942 spin_lock_irqsave(&ring->lock, flags);
943 __bcmgenet_tx_reclaim(dev, ring);
944 spin_unlock_irqrestore(&ring->lock, flags);
945 }
946
947 static void bcmgenet_tx_reclaim_all(struct net_device *dev)
948 {
949 struct bcmgenet_priv *priv = netdev_priv(dev);
950 int i;
951
952 if (netif_is_multiqueue(dev)) {
953 for (i = 0; i < priv->hw_params->tx_queues; i++)
954 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
955 }
956
957 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
958 }
959
960 /* Transmits a single SKB (either head of a fragment or a single SKB)
961 * caller must hold priv->lock
962 */
963 static int bcmgenet_xmit_single(struct net_device *dev,
964 struct sk_buff *skb,
965 u16 dma_desc_flags,
966 struct bcmgenet_tx_ring *ring)
967 {
968 struct bcmgenet_priv *priv = netdev_priv(dev);
969 struct device *kdev = &priv->pdev->dev;
970 struct enet_cb *tx_cb_ptr;
971 unsigned int skb_len;
972 dma_addr_t mapping;
973 u32 length_status;
974 int ret;
975
976 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
977
978 if (unlikely(!tx_cb_ptr))
979 BUG();
980
981 tx_cb_ptr->skb = skb;
982
983 skb_len = skb_headlen(skb) < ETH_ZLEN ? ETH_ZLEN : skb_headlen(skb);
984
985 mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE);
986 ret = dma_mapping_error(kdev, mapping);
987 if (ret) {
988 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
989 dev_kfree_skb(skb);
990 return ret;
991 }
992
993 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
994 dma_unmap_len_set(tx_cb_ptr, dma_len, skb->len);
995 length_status = (skb_len << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
996 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT) |
997 DMA_TX_APPEND_CRC;
998
999 if (skb->ip_summed == CHECKSUM_PARTIAL)
1000 length_status |= DMA_TX_DO_CSUM;
1001
1002 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, length_status);
1003
1004 /* Decrement total BD count and advance our write pointer */
1005 ring->free_bds -= 1;
1006 ring->prod_index += 1;
1007 ring->prod_index &= DMA_P_INDEX_MASK;
1008
1009 return 0;
1010 }
1011
1012 /* Transmit a SKB fragement */
1013 static int bcmgenet_xmit_frag(struct net_device *dev,
1014 skb_frag_t *frag,
1015 u16 dma_desc_flags,
1016 struct bcmgenet_tx_ring *ring)
1017 {
1018 struct bcmgenet_priv *priv = netdev_priv(dev);
1019 struct device *kdev = &priv->pdev->dev;
1020 struct enet_cb *tx_cb_ptr;
1021 dma_addr_t mapping;
1022 int ret;
1023
1024 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1025
1026 if (unlikely(!tx_cb_ptr))
1027 BUG();
1028 tx_cb_ptr->skb = NULL;
1029
1030 mapping = skb_frag_dma_map(kdev, frag, 0,
1031 skb_frag_size(frag), DMA_TO_DEVICE);
1032 ret = dma_mapping_error(kdev, mapping);
1033 if (ret) {
1034 netif_err(priv, tx_err, dev, "%s: Tx DMA map failed\n",
1035 __func__);
1036 return ret;
1037 }
1038
1039 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1040 dma_unmap_len_set(tx_cb_ptr, dma_len, frag->size);
1041
1042 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping,
1043 (frag->size << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1044 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT));
1045
1046
1047 ring->free_bds -= 1;
1048 ring->prod_index += 1;
1049 ring->prod_index &= DMA_P_INDEX_MASK;
1050
1051 return 0;
1052 }
1053
1054 /* Reallocate the SKB to put enough headroom in front of it and insert
1055 * the transmit checksum offsets in the descriptors
1056 */
1057 static int bcmgenet_put_tx_csum(struct net_device *dev, struct sk_buff *skb)
1058 {
1059 struct status_64 *status = NULL;
1060 struct sk_buff *new_skb;
1061 u16 offset;
1062 u8 ip_proto;
1063 u16 ip_ver;
1064 u32 tx_csum_info;
1065
1066 if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1067 /* If 64 byte status block enabled, must make sure skb has
1068 * enough headroom for us to insert 64B status block.
1069 */
1070 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1071 dev_kfree_skb(skb);
1072 if (!new_skb) {
1073 dev->stats.tx_errors++;
1074 dev->stats.tx_dropped++;
1075 return -ENOMEM;
1076 }
1077 skb = new_skb;
1078 }
1079
1080 skb_push(skb, sizeof(*status));
1081 status = (struct status_64 *)skb->data;
1082
1083 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1084 ip_ver = htons(skb->protocol);
1085 switch (ip_ver) {
1086 case ETH_P_IP:
1087 ip_proto = ip_hdr(skb)->protocol;
1088 break;
1089 case ETH_P_IPV6:
1090 ip_proto = ipv6_hdr(skb)->nexthdr;
1091 break;
1092 default:
1093 return 0;
1094 }
1095
1096 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1097 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1098 (offset + skb->csum_offset);
1099
1100 /* Set the length valid bit for TCP and UDP and just set
1101 * the special UDP flag for IPv4, else just set to 0.
1102 */
1103 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1104 tx_csum_info |= STATUS_TX_CSUM_LV;
1105 if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
1106 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
1107 } else
1108 tx_csum_info = 0;
1109
1110 status->tx_csum_info = tx_csum_info;
1111 }
1112
1113 return 0;
1114 }
1115
1116 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1117 {
1118 struct bcmgenet_priv *priv = netdev_priv(dev);
1119 struct bcmgenet_tx_ring *ring = NULL;
1120 struct netdev_queue *txq;
1121 unsigned long flags = 0;
1122 int nr_frags, index;
1123 u16 dma_desc_flags;
1124 int ret;
1125 int i;
1126
1127 index = skb_get_queue_mapping(skb);
1128 /* Mapping strategy:
1129 * queue_mapping = 0, unclassified, packet xmited through ring16
1130 * queue_mapping = 1, goes to ring 0. (highest priority queue
1131 * queue_mapping = 2, goes to ring 1.
1132 * queue_mapping = 3, goes to ring 2.
1133 * queue_mapping = 4, goes to ring 3.
1134 */
1135 if (index == 0)
1136 index = DESC_INDEX;
1137 else
1138 index -= 1;
1139
1140 nr_frags = skb_shinfo(skb)->nr_frags;
1141 ring = &priv->tx_rings[index];
1142 txq = netdev_get_tx_queue(dev, ring->queue);
1143
1144 spin_lock_irqsave(&ring->lock, flags);
1145 if (ring->free_bds <= nr_frags + 1) {
1146 netif_tx_stop_queue(txq);
1147 netdev_err(dev, "%s: tx ring %d full when queue %d awake\n",
1148 __func__, index, ring->queue);
1149 ret = NETDEV_TX_BUSY;
1150 goto out;
1151 }
1152
1153 /* set the SKB transmit checksum */
1154 if (priv->desc_64b_en) {
1155 ret = bcmgenet_put_tx_csum(dev, skb);
1156 if (ret) {
1157 ret = NETDEV_TX_OK;
1158 goto out;
1159 }
1160 }
1161
1162 dma_desc_flags = DMA_SOP;
1163 if (nr_frags == 0)
1164 dma_desc_flags |= DMA_EOP;
1165
1166 /* Transmit single SKB or head of fragment list */
1167 ret = bcmgenet_xmit_single(dev, skb, dma_desc_flags, ring);
1168 if (ret) {
1169 ret = NETDEV_TX_OK;
1170 goto out;
1171 }
1172
1173 /* xmit fragment */
1174 for (i = 0; i < nr_frags; i++) {
1175 ret = bcmgenet_xmit_frag(dev,
1176 &skb_shinfo(skb)->frags[i],
1177 (i == nr_frags - 1) ? DMA_EOP : 0, ring);
1178 if (ret) {
1179 ret = NETDEV_TX_OK;
1180 goto out;
1181 }
1182 }
1183
1184 skb_tx_timestamp(skb);
1185
1186 /* we kept a software copy of how much we should advance the TDMA
1187 * producer index, now write it down to the hardware
1188 */
1189 bcmgenet_tdma_ring_writel(priv, ring->index,
1190 ring->prod_index, TDMA_PROD_INDEX);
1191
1192 if (ring->free_bds <= (MAX_SKB_FRAGS + 1)) {
1193 netif_tx_stop_queue(txq);
1194 ring->int_enable(priv, ring);
1195 }
1196
1197 out:
1198 spin_unlock_irqrestore(&ring->lock, flags);
1199
1200 return ret;
1201 }
1202
1203
1204 static int bcmgenet_rx_refill(struct bcmgenet_priv *priv,
1205 struct enet_cb *cb)
1206 {
1207 struct device *kdev = &priv->pdev->dev;
1208 struct sk_buff *skb;
1209 dma_addr_t mapping;
1210 int ret;
1211
1212 skb = netdev_alloc_skb(priv->dev,
1213 priv->rx_buf_len + SKB_ALIGNMENT);
1214 if (!skb)
1215 return -ENOMEM;
1216
1217 /* a caller did not release this control block */
1218 WARN_ON(cb->skb != NULL);
1219 cb->skb = skb;
1220 mapping = dma_map_single(kdev, skb->data,
1221 priv->rx_buf_len, DMA_FROM_DEVICE);
1222 ret = dma_mapping_error(kdev, mapping);
1223 if (ret) {
1224 bcmgenet_free_cb(cb);
1225 netif_err(priv, rx_err, priv->dev,
1226 "%s DMA map failed\n", __func__);
1227 return ret;
1228 }
1229
1230 dma_unmap_addr_set(cb, dma_addr, mapping);
1231 /* assign packet, prepare descriptor, and advance pointer */
1232
1233 dmadesc_set_addr(priv, priv->rx_bd_assign_ptr, mapping);
1234
1235 /* turn on the newly assigned BD for DMA to use */
1236 priv->rx_bd_assign_index++;
1237 priv->rx_bd_assign_index &= (priv->num_rx_bds - 1);
1238
1239 priv->rx_bd_assign_ptr = priv->rx_bds +
1240 (priv->rx_bd_assign_index * DMA_DESC_SIZE);
1241
1242 return 0;
1243 }
1244
1245 /* bcmgenet_desc_rx - descriptor based rx process.
1246 * this could be called from bottom half, or from NAPI polling method.
1247 */
1248 static unsigned int bcmgenet_desc_rx(struct bcmgenet_priv *priv,
1249 unsigned int budget)
1250 {
1251 struct net_device *dev = priv->dev;
1252 struct enet_cb *cb;
1253 struct sk_buff *skb;
1254 u32 dma_length_status;
1255 unsigned long dma_flag;
1256 int len, err;
1257 unsigned int rxpktprocessed = 0, rxpkttoprocess;
1258 unsigned int p_index;
1259 unsigned int chksum_ok = 0;
1260
1261 p_index = bcmgenet_rdma_ring_readl(priv,
1262 DESC_INDEX, RDMA_PROD_INDEX);
1263 p_index &= DMA_P_INDEX_MASK;
1264
1265 if (p_index < priv->rx_c_index)
1266 rxpkttoprocess = (DMA_C_INDEX_MASK + 1) -
1267 priv->rx_c_index + p_index;
1268 else
1269 rxpkttoprocess = p_index - priv->rx_c_index;
1270
1271 netif_dbg(priv, rx_status, dev,
1272 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1273
1274 while ((rxpktprocessed < rxpkttoprocess) &&
1275 (rxpktprocessed < budget)) {
1276
1277 /* Unmap the packet contents such that we can use the
1278 * RSV from the 64 bytes descriptor when enabled and save
1279 * a 32-bits register read
1280 */
1281 cb = &priv->rx_cbs[priv->rx_read_ptr];
1282 skb = cb->skb;
1283 dma_unmap_single(&dev->dev, dma_unmap_addr(cb, dma_addr),
1284 priv->rx_buf_len, DMA_FROM_DEVICE);
1285
1286 if (!priv->desc_64b_en) {
1287 dma_length_status = dmadesc_get_length_status(priv,
1288 priv->rx_bds +
1289 (priv->rx_read_ptr *
1290 DMA_DESC_SIZE));
1291 } else {
1292 struct status_64 *status;
1293 status = (struct status_64 *)skb->data;
1294 dma_length_status = status->length_status;
1295 }
1296
1297 /* DMA flags and length are still valid no matter how
1298 * we got the Receive Status Vector (64B RSB or register)
1299 */
1300 dma_flag = dma_length_status & 0xffff;
1301 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1302
1303 netif_dbg(priv, rx_status, dev,
1304 "%s: p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
1305 __func__, p_index, priv->rx_c_index, priv->rx_read_ptr,
1306 dma_length_status);
1307
1308 rxpktprocessed++;
1309
1310 priv->rx_read_ptr++;
1311 priv->rx_read_ptr &= (priv->num_rx_bds - 1);
1312
1313 /* out of memory, just drop packets at the hardware level */
1314 if (unlikely(!skb)) {
1315 dev->stats.rx_dropped++;
1316 dev->stats.rx_errors++;
1317 goto refill;
1318 }
1319
1320 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1321 netif_err(priv, rx_status, dev,
1322 "Droping fragmented packet!\n");
1323 dev->stats.rx_dropped++;
1324 dev->stats.rx_errors++;
1325 dev_kfree_skb_any(cb->skb);
1326 cb->skb = NULL;
1327 goto refill;
1328 }
1329 /* report errors */
1330 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1331 DMA_RX_OV |
1332 DMA_RX_NO |
1333 DMA_RX_LG |
1334 DMA_RX_RXER))) {
1335 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
1336 (unsigned int)dma_flag);
1337 if (dma_flag & DMA_RX_CRC_ERROR)
1338 dev->stats.rx_crc_errors++;
1339 if (dma_flag & DMA_RX_OV)
1340 dev->stats.rx_over_errors++;
1341 if (dma_flag & DMA_RX_NO)
1342 dev->stats.rx_frame_errors++;
1343 if (dma_flag & DMA_RX_LG)
1344 dev->stats.rx_length_errors++;
1345 dev->stats.rx_dropped++;
1346 dev->stats.rx_errors++;
1347
1348 /* discard the packet and advance consumer index.*/
1349 dev_kfree_skb_any(cb->skb);
1350 cb->skb = NULL;
1351 goto refill;
1352 } /* error packet */
1353
1354 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
1355 priv->desc_rxchk_en;
1356
1357 skb_put(skb, len);
1358 if (priv->desc_64b_en) {
1359 skb_pull(skb, 64);
1360 len -= 64;
1361 }
1362
1363 if (likely(chksum_ok))
1364 skb->ip_summed = CHECKSUM_UNNECESSARY;
1365
1366 /* remove hardware 2bytes added for IP alignment */
1367 skb_pull(skb, 2);
1368 len -= 2;
1369
1370 if (priv->crc_fwd_en) {
1371 skb_trim(skb, len - ETH_FCS_LEN);
1372 len -= ETH_FCS_LEN;
1373 }
1374
1375 /*Finish setting up the received SKB and send it to the kernel*/
1376 skb->protocol = eth_type_trans(skb, priv->dev);
1377 dev->stats.rx_packets++;
1378 dev->stats.rx_bytes += len;
1379 if (dma_flag & DMA_RX_MULT)
1380 dev->stats.multicast++;
1381
1382 /* Notify kernel */
1383 napi_gro_receive(&priv->napi, skb);
1384 cb->skb = NULL;
1385 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1386
1387 /* refill RX path on the current control block */
1388 refill:
1389 err = bcmgenet_rx_refill(priv, cb);
1390 if (err)
1391 netif_err(priv, rx_err, dev, "Rx refill failed\n");
1392 }
1393
1394 return rxpktprocessed;
1395 }
1396
1397 /* Assign skb to RX DMA descriptor. */
1398 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv)
1399 {
1400 struct enet_cb *cb;
1401 int ret = 0;
1402 int i;
1403
1404 netif_dbg(priv, hw, priv->dev, "%s:\n", __func__);
1405
1406 /* loop here for each buffer needing assign */
1407 for (i = 0; i < priv->num_rx_bds; i++) {
1408 cb = &priv->rx_cbs[priv->rx_bd_assign_index];
1409 if (cb->skb)
1410 continue;
1411
1412 /* set the DMA descriptor length once and for all
1413 * it will only change if we support dynamically sizing
1414 * priv->rx_buf_len, but we do not
1415 */
1416 dmadesc_set_length_status(priv, priv->rx_bd_assign_ptr,
1417 priv->rx_buf_len << DMA_BUFLENGTH_SHIFT);
1418
1419 ret = bcmgenet_rx_refill(priv, cb);
1420 if (ret)
1421 break;
1422
1423 }
1424
1425 return ret;
1426 }
1427
1428 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1429 {
1430 struct enet_cb *cb;
1431 int i;
1432
1433 for (i = 0; i < priv->num_rx_bds; i++) {
1434 cb = &priv->rx_cbs[i];
1435
1436 if (dma_unmap_addr(cb, dma_addr)) {
1437 dma_unmap_single(&priv->dev->dev,
1438 dma_unmap_addr(cb, dma_addr),
1439 priv->rx_buf_len, DMA_FROM_DEVICE);
1440 dma_unmap_addr_set(cb, dma_addr, 0);
1441 }
1442
1443 if (cb->skb)
1444 bcmgenet_free_cb(cb);
1445 }
1446 }
1447
1448 static int reset_umac(struct bcmgenet_priv *priv)
1449 {
1450 struct device *kdev = &priv->pdev->dev;
1451 unsigned int timeout = 0;
1452 u32 reg;
1453
1454 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1455 bcmgenet_rbuf_ctrl_set(priv, 0);
1456 udelay(10);
1457
1458 /* disable MAC while updating its registers */
1459 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1460
1461 /* issue soft reset, wait for it to complete */
1462 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
1463 while (timeout++ < 1000) {
1464 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1465 if (!(reg & CMD_SW_RESET))
1466 return 0;
1467
1468 udelay(1);
1469 }
1470
1471 if (timeout == 1000) {
1472 dev_err(kdev,
1473 "timeout waiting for MAC to come out of resetn\n");
1474 return -ETIMEDOUT;
1475 }
1476
1477 return 0;
1478 }
1479
1480 static int init_umac(struct bcmgenet_priv *priv)
1481 {
1482 struct device *kdev = &priv->pdev->dev;
1483 int ret;
1484 u32 reg, cpu_mask_clear;
1485
1486 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
1487
1488 ret = reset_umac(priv);
1489 if (ret)
1490 return ret;
1491
1492 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1493 /* clear tx/rx counter */
1494 bcmgenet_umac_writel(priv,
1495 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT, UMAC_MIB_CTRL);
1496 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
1497
1498 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
1499
1500 /* init rx registers, enable ip header optimization */
1501 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
1502 reg |= RBUF_ALIGN_2B;
1503 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
1504
1505 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
1506 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
1507
1508 /* Mask all interrupts.*/
1509 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1510 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1511 bcmgenet_intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1512
1513 cpu_mask_clear = UMAC_IRQ_RXDMA_BDONE;
1514
1515 dev_dbg(kdev, "%s:Enabling RXDMA_BDONE interrupt\n", __func__);
1516
1517 /* Monitor cable plug/unpluged event for internal PHY */
1518 if (phy_is_internal(priv->phydev))
1519 cpu_mask_clear |= (UMAC_IRQ_LINK_DOWN | UMAC_IRQ_LINK_UP);
1520 else if (priv->ext_phy)
1521 cpu_mask_clear |= (UMAC_IRQ_LINK_DOWN | UMAC_IRQ_LINK_UP);
1522 else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1523 reg = bcmgenet_bp_mc_get(priv);
1524 reg |= BIT(priv->hw_params->bp_in_en_shift);
1525
1526 /* bp_mask: back pressure mask */
1527 if (netif_is_multiqueue(priv->dev))
1528 reg |= priv->hw_params->bp_in_mask;
1529 else
1530 reg &= ~priv->hw_params->bp_in_mask;
1531 bcmgenet_bp_mc_set(priv, reg);
1532 }
1533
1534 /* Enable MDIO interrupts on GENET v3+ */
1535 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
1536 cpu_mask_clear |= UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR;
1537
1538 bcmgenet_intrl2_0_writel(priv, cpu_mask_clear,
1539 INTRL2_CPU_MASK_CLEAR);
1540
1541 /* Enable rx/tx engine.*/
1542 dev_dbg(kdev, "done init umac\n");
1543
1544 return 0;
1545 }
1546
1547 /* Initialize all house-keeping variables for a TX ring, along
1548 * with corresponding hardware registers
1549 */
1550 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
1551 unsigned int index, unsigned int size,
1552 unsigned int write_ptr, unsigned int end_ptr)
1553 {
1554 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
1555 u32 words_per_bd = WORDS_PER_BD(priv);
1556 u32 flow_period_val = 0;
1557 unsigned int first_bd;
1558
1559 spin_lock_init(&ring->lock);
1560 ring->index = index;
1561 if (index == DESC_INDEX) {
1562 ring->queue = 0;
1563 ring->int_enable = bcmgenet_tx_ring16_int_enable;
1564 ring->int_disable = bcmgenet_tx_ring16_int_disable;
1565 } else {
1566 ring->queue = index + 1;
1567 ring->int_enable = bcmgenet_tx_ring_int_enable;
1568 ring->int_disable = bcmgenet_tx_ring_int_disable;
1569 }
1570 ring->cbs = priv->tx_cbs + write_ptr;
1571 ring->size = size;
1572 ring->c_index = 0;
1573 ring->free_bds = size;
1574 ring->write_ptr = write_ptr;
1575 ring->cb_ptr = write_ptr;
1576 ring->end_ptr = end_ptr - 1;
1577 ring->prod_index = 0;
1578
1579 /* Set flow period for ring != 16 */
1580 if (index != DESC_INDEX)
1581 flow_period_val = ENET_MAX_MTU_SIZE << 16;
1582
1583 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
1584 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
1585 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
1586 /* Disable rate control for now */
1587 bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
1588 TDMA_FLOW_PERIOD);
1589 /* Unclassified traffic goes to ring 16 */
1590 bcmgenet_tdma_ring_writel(priv, index,
1591 ((size << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH),
1592 DMA_RING_BUF_SIZE);
1593
1594 first_bd = write_ptr;
1595
1596 /* Set start and end address, read and write pointers */
1597 bcmgenet_tdma_ring_writel(priv, index, first_bd * words_per_bd,
1598 DMA_START_ADDR);
1599 bcmgenet_tdma_ring_writel(priv, index, first_bd * words_per_bd,
1600 TDMA_READ_PTR);
1601 bcmgenet_tdma_ring_writel(priv, index, first_bd,
1602 TDMA_WRITE_PTR);
1603 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
1604 DMA_END_ADDR);
1605 }
1606
1607 /* Initialize a RDMA ring */
1608 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
1609 unsigned int index, unsigned int size)
1610 {
1611 u32 words_per_bd = WORDS_PER_BD(priv);
1612 int ret;
1613
1614 priv->num_rx_bds = TOTAL_DESC;
1615 priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
1616 priv->rx_bd_assign_ptr = priv->rx_bds;
1617 priv->rx_bd_assign_index = 0;
1618 priv->rx_c_index = 0;
1619 priv->rx_read_ptr = 0;
1620 priv->rx_cbs = kzalloc(priv->num_rx_bds * sizeof(struct enet_cb),
1621 GFP_KERNEL);
1622 if (!priv->rx_cbs)
1623 return -ENOMEM;
1624
1625 ret = bcmgenet_alloc_rx_buffers(priv);
1626 if (ret) {
1627 kfree(priv->rx_cbs);
1628 return ret;
1629 }
1630
1631 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_WRITE_PTR);
1632 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
1633 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
1634 bcmgenet_rdma_ring_writel(priv, index,
1635 ((size << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH),
1636 DMA_RING_BUF_SIZE);
1637 bcmgenet_rdma_ring_writel(priv, index, 0, DMA_START_ADDR);
1638 bcmgenet_rdma_ring_writel(priv, index,
1639 words_per_bd * size - 1, DMA_END_ADDR);
1640 bcmgenet_rdma_ring_writel(priv, index,
1641 (DMA_FC_THRESH_LO << DMA_XOFF_THRESHOLD_SHIFT) |
1642 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
1643 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_READ_PTR);
1644
1645 return ret;
1646 }
1647
1648 /* init multi xmit queues, only available for GENET2+
1649 * the queue is partitioned as follows:
1650 *
1651 * queue 0 - 3 is priority based, each one has 32 descriptors,
1652 * with queue 0 being the highest priority queue.
1653 *
1654 * queue 16 is the default tx queue with GENET_DEFAULT_BD_CNT
1655 * descriptors: 256 - (number of tx queues * bds per queues) = 128
1656 * descriptors.
1657 *
1658 * The transmit control block pool is then partitioned as following:
1659 * - tx_cbs[0...127] are for queue 16
1660 * - tx_ring_cbs[0] points to tx_cbs[128..159]
1661 * - tx_ring_cbs[1] points to tx_cbs[160..191]
1662 * - tx_ring_cbs[2] points to tx_cbs[192..223]
1663 * - tx_ring_cbs[3] points to tx_cbs[224..255]
1664 */
1665 static void bcmgenet_init_multiq(struct net_device *dev)
1666 {
1667 struct bcmgenet_priv *priv = netdev_priv(dev);
1668 unsigned int i, dma_enable;
1669 u32 reg, dma_ctrl, ring_cfg = 0, dma_priority = 0;
1670
1671 if (!netif_is_multiqueue(dev)) {
1672 netdev_warn(dev, "called with non multi queue aware HW\n");
1673 return;
1674 }
1675
1676 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
1677 dma_enable = dma_ctrl & DMA_EN;
1678 dma_ctrl &= ~DMA_EN;
1679 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
1680
1681 /* Enable strict priority arbiter mode */
1682 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
1683
1684 for (i = 0; i < priv->hw_params->tx_queues; i++) {
1685 /* first 64 tx_cbs are reserved for default tx queue
1686 * (ring 16)
1687 */
1688 bcmgenet_init_tx_ring(priv, i, priv->hw_params->bds_cnt,
1689 i * priv->hw_params->bds_cnt,
1690 (i + 1) * priv->hw_params->bds_cnt);
1691
1692 /* Configure ring as decriptor ring and setup priority */
1693 ring_cfg |= 1 << i;
1694 dma_priority |= ((GENET_Q0_PRIORITY + i) <<
1695 (GENET_MAX_MQ_CNT + 1) * i);
1696 dma_ctrl |= 1 << (i + DMA_RING_BUF_EN_SHIFT);
1697 }
1698
1699 /* Enable rings */
1700 reg = bcmgenet_tdma_readl(priv, DMA_RING_CFG);
1701 reg |= ring_cfg;
1702 bcmgenet_tdma_writel(priv, reg, DMA_RING_CFG);
1703
1704 /* Use configured rings priority and set ring #16 priority */
1705 reg = bcmgenet_tdma_readl(priv, DMA_RING_PRIORITY);
1706 reg |= ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) << 20);
1707 reg |= dma_priority;
1708 bcmgenet_tdma_writel(priv, reg, DMA_PRIORITY);
1709
1710 /* Configure ring as descriptor ring and re-enable DMA if enabled */
1711 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
1712 reg |= dma_ctrl;
1713 if (dma_enable)
1714 reg |= DMA_EN;
1715 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
1716 }
1717
1718 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
1719 {
1720 int i;
1721
1722 /* disable DMA */
1723 bcmgenet_rdma_writel(priv, 0, DMA_CTRL);
1724 bcmgenet_tdma_writel(priv, 0, DMA_CTRL);
1725
1726 for (i = 0; i < priv->num_tx_bds; i++) {
1727 if (priv->tx_cbs[i].skb != NULL) {
1728 dev_kfree_skb(priv->tx_cbs[i].skb);
1729 priv->tx_cbs[i].skb = NULL;
1730 }
1731 }
1732
1733 bcmgenet_free_rx_buffers(priv);
1734 kfree(priv->rx_cbs);
1735 kfree(priv->tx_cbs);
1736 }
1737
1738 /* init_edma: Initialize DMA control register */
1739 static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
1740 {
1741 int ret;
1742
1743 netif_dbg(priv, hw, priv->dev, "bcmgenet: init_edma\n");
1744
1745 /* by default, enable ring 16 (descriptor based) */
1746 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, TOTAL_DESC);
1747 if (ret) {
1748 netdev_err(priv->dev, "failed to initialize RX ring\n");
1749 return ret;
1750 }
1751
1752 /* init rDma */
1753 bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
1754
1755 /* Init tDma */
1756 bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
1757
1758 /* Initialize commont TX ring structures */
1759 priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
1760 priv->num_tx_bds = TOTAL_DESC;
1761 priv->tx_cbs = kzalloc(priv->num_tx_bds * sizeof(struct enet_cb),
1762 GFP_KERNEL);
1763 if (!priv->tx_cbs) {
1764 bcmgenet_fini_dma(priv);
1765 return -ENOMEM;
1766 }
1767
1768 /* initialize multi xmit queue */
1769 bcmgenet_init_multiq(priv->dev);
1770
1771 /* initialize special ring 16 */
1772 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_DEFAULT_BD_CNT,
1773 priv->hw_params->tx_queues * priv->hw_params->bds_cnt,
1774 TOTAL_DESC);
1775
1776 return 0;
1777 }
1778
1779 /* NAPI polling method*/
1780 static int bcmgenet_poll(struct napi_struct *napi, int budget)
1781 {
1782 struct bcmgenet_priv *priv = container_of(napi,
1783 struct bcmgenet_priv, napi);
1784 unsigned int work_done;
1785
1786 /* tx reclaim */
1787 bcmgenet_tx_reclaim(priv->dev, &priv->tx_rings[DESC_INDEX]);
1788
1789 work_done = bcmgenet_desc_rx(priv, budget);
1790
1791 /* Advancing our consumer index*/
1792 priv->rx_c_index += work_done;
1793 priv->rx_c_index &= DMA_C_INDEX_MASK;
1794 bcmgenet_rdma_ring_writel(priv, DESC_INDEX,
1795 priv->rx_c_index, RDMA_CONS_INDEX);
1796 if (work_done < budget) {
1797 napi_complete(napi);
1798 bcmgenet_intrl2_0_writel(priv,
1799 UMAC_IRQ_RXDMA_BDONE, INTRL2_CPU_MASK_CLEAR);
1800 }
1801
1802 return work_done;
1803 }
1804
1805 /* Interrupt bottom half */
1806 static void bcmgenet_irq_task(struct work_struct *work)
1807 {
1808 struct bcmgenet_priv *priv = container_of(
1809 work, struct bcmgenet_priv, bcmgenet_irq_work);
1810
1811 netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
1812
1813 /* Link UP/DOWN event */
1814 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
1815 (priv->irq0_stat & (UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN))) {
1816 phy_mac_interrupt(priv->phydev,
1817 priv->irq0_stat & UMAC_IRQ_LINK_UP);
1818 priv->irq0_stat &= ~(UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN);
1819 }
1820 }
1821
1822 /* bcmgenet_isr1: interrupt handler for ring buffer. */
1823 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
1824 {
1825 struct bcmgenet_priv *priv = dev_id;
1826 unsigned int index;
1827
1828 /* Save irq status for bottom-half processing. */
1829 priv->irq1_stat =
1830 bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
1831 ~priv->int1_mask;
1832 /* clear inerrupts*/
1833 bcmgenet_intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
1834
1835 netif_dbg(priv, intr, priv->dev,
1836 "%s: IRQ=0x%x\n", __func__, priv->irq1_stat);
1837 /* Check the MBDONE interrupts.
1838 * packet is done, reclaim descriptors
1839 */
1840 if (priv->irq1_stat & 0x0000ffff) {
1841 index = 0;
1842 for (index = 0; index < 16; index++) {
1843 if (priv->irq1_stat & (1 << index))
1844 bcmgenet_tx_reclaim(priv->dev,
1845 &priv->tx_rings[index]);
1846 }
1847 }
1848 return IRQ_HANDLED;
1849 }
1850
1851 /* bcmgenet_isr0: Handle various interrupts. */
1852 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
1853 {
1854 struct bcmgenet_priv *priv = dev_id;
1855
1856 /* Save irq status for bottom-half processing. */
1857 priv->irq0_stat =
1858 bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
1859 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
1860 /* clear inerrupts*/
1861 bcmgenet_intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
1862
1863 netif_dbg(priv, intr, priv->dev,
1864 "IRQ=0x%x\n", priv->irq0_stat);
1865
1866 if (priv->irq0_stat & (UMAC_IRQ_RXDMA_BDONE | UMAC_IRQ_RXDMA_PDONE)) {
1867 /* We use NAPI(software interrupt throttling, if
1868 * Rx Descriptor throttling is not used.
1869 * Disable interrupt, will be enabled in the poll method.
1870 */
1871 if (likely(napi_schedule_prep(&priv->napi))) {
1872 bcmgenet_intrl2_0_writel(priv,
1873 UMAC_IRQ_RXDMA_BDONE, INTRL2_CPU_MASK_SET);
1874 __napi_schedule(&priv->napi);
1875 }
1876 }
1877 if (priv->irq0_stat &
1878 (UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE)) {
1879 /* Tx reclaim */
1880 bcmgenet_tx_reclaim(priv->dev, &priv->tx_rings[DESC_INDEX]);
1881 }
1882 if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R |
1883 UMAC_IRQ_PHY_DET_F |
1884 UMAC_IRQ_LINK_UP |
1885 UMAC_IRQ_LINK_DOWN |
1886 UMAC_IRQ_HFB_SM |
1887 UMAC_IRQ_HFB_MM |
1888 UMAC_IRQ_MPD_R)) {
1889 /* all other interested interrupts handled in bottom half */
1890 schedule_work(&priv->bcmgenet_irq_work);
1891 }
1892
1893 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
1894 priv->irq0_stat & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
1895 priv->irq0_stat &= ~(UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
1896 wake_up(&priv->wq);
1897 }
1898
1899 return IRQ_HANDLED;
1900 }
1901
1902 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
1903 {
1904 u32 reg;
1905
1906 reg = bcmgenet_rbuf_ctrl_get(priv);
1907 reg |= BIT(1);
1908 bcmgenet_rbuf_ctrl_set(priv, reg);
1909 udelay(10);
1910
1911 reg &= ~BIT(1);
1912 bcmgenet_rbuf_ctrl_set(priv, reg);
1913 udelay(10);
1914 }
1915
1916 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
1917 unsigned char *addr)
1918 {
1919 bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
1920 (addr[2] << 8) | addr[3], UMAC_MAC0);
1921 bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
1922 }
1923
1924 static int bcmgenet_wol_resume(struct bcmgenet_priv *priv)
1925 {
1926 int ret;
1927
1928 /* From WOL-enabled suspend, switch to regular clock */
1929 clk_disable(priv->clk_wol);
1930 /* init umac registers to synchronize s/w with h/w */
1931 ret = init_umac(priv);
1932 if (ret)
1933 return ret;
1934
1935 phy_init_hw(priv->phydev);
1936 /* Speed settings must be restored */
1937 bcmgenet_mii_config(priv->dev);
1938
1939 return 0;
1940 }
1941
1942 /* Returns a reusable dma control register value */
1943 static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
1944 {
1945 u32 reg;
1946 u32 dma_ctrl;
1947
1948 /* disable DMA */
1949 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
1950 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
1951 reg &= ~dma_ctrl;
1952 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
1953
1954 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
1955 reg &= ~dma_ctrl;
1956 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
1957
1958 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
1959 udelay(10);
1960 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
1961
1962 return dma_ctrl;
1963 }
1964
1965 static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
1966 {
1967 u32 reg;
1968
1969 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
1970 reg |= dma_ctrl;
1971 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
1972
1973 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
1974 reg |= dma_ctrl;
1975 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
1976 }
1977
1978 static int bcmgenet_open(struct net_device *dev)
1979 {
1980 struct bcmgenet_priv *priv = netdev_priv(dev);
1981 unsigned long dma_ctrl;
1982 u32 reg;
1983 int ret;
1984
1985 netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
1986
1987 /* Turn on the clock */
1988 if (!IS_ERR(priv->clk))
1989 clk_prepare_enable(priv->clk);
1990
1991 /* take MAC out of reset */
1992 bcmgenet_umac_reset(priv);
1993
1994 ret = init_umac(priv);
1995 if (ret)
1996 goto err_clk_disable;
1997
1998 /* disable ethernet MAC while updating its registers */
1999 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2000 reg &= ~(CMD_TX_EN | CMD_RX_EN);
2001 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2002
2003 bcmgenet_set_hw_addr(priv, dev->dev_addr);
2004
2005 if (priv->wol_enabled) {
2006 ret = bcmgenet_wol_resume(priv);
2007 if (ret)
2008 return ret;
2009 }
2010
2011 if (phy_is_internal(priv->phydev)) {
2012 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2013 reg |= EXT_ENERGY_DET_MASK;
2014 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2015 }
2016
2017 /* Disable RX/TX DMA and flush TX queues */
2018 dma_ctrl = bcmgenet_dma_disable(priv);
2019
2020 /* Reinitialize TDMA and RDMA and SW housekeeping */
2021 ret = bcmgenet_init_dma(priv);
2022 if (ret) {
2023 netdev_err(dev, "failed to initialize DMA\n");
2024 goto err_fini_dma;
2025 }
2026
2027 /* Always enable ring 16 - descriptor ring */
2028 bcmgenet_enable_dma(priv, dma_ctrl);
2029
2030 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
2031 dev->name, priv);
2032 if (ret < 0) {
2033 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2034 goto err_fini_dma;
2035 }
2036
2037 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
2038 dev->name, priv);
2039 if (ret < 0) {
2040 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2041 goto err_irq0;
2042 }
2043
2044 /* Start the network engine */
2045 napi_enable(&priv->napi);
2046
2047 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2048 reg |= (CMD_TX_EN | CMD_RX_EN);
2049 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2050
2051 /* Make sure we reflect the value of CRC_CMD_FWD */
2052 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2053
2054 device_set_wakeup_capable(&dev->dev, 1);
2055
2056 if (phy_is_internal(priv->phydev))
2057 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2058
2059 netif_tx_start_all_queues(dev);
2060
2061 phy_start(priv->phydev);
2062
2063 return 0;
2064
2065 err_irq0:
2066 free_irq(priv->irq0, dev);
2067 err_fini_dma:
2068 bcmgenet_fini_dma(priv);
2069 err_clk_disable:
2070 if (!IS_ERR(priv->clk))
2071 clk_disable_unprepare(priv->clk);
2072 return ret;
2073 }
2074
2075 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
2076 {
2077 int ret = 0;
2078 int timeout = 0;
2079 u32 reg;
2080
2081 /* Disable TDMA to stop add more frames in TX DMA */
2082 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2083 reg &= ~DMA_EN;
2084 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2085
2086 /* Check TDMA status register to confirm TDMA is disabled */
2087 while (timeout++ < DMA_TIMEOUT_VAL) {
2088 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2089 if (reg & DMA_DISABLED)
2090 break;
2091
2092 udelay(1);
2093 }
2094
2095 if (timeout == DMA_TIMEOUT_VAL) {
2096 netdev_warn(priv->dev,
2097 "Timed out while disabling TX DMA\n");
2098 ret = -ETIMEDOUT;
2099 }
2100
2101 /* Wait 10ms for packet drain in both tx and rx dma */
2102 usleep_range(10000, 20000);
2103
2104 /* Disable RDMA */
2105 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2106 reg &= ~DMA_EN;
2107 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2108
2109 timeout = 0;
2110 /* Check RDMA status register to confirm RDMA is disabled */
2111 while (timeout++ < DMA_TIMEOUT_VAL) {
2112 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
2113 if (reg & DMA_DISABLED)
2114 break;
2115
2116 udelay(1);
2117 }
2118
2119 if (timeout == DMA_TIMEOUT_VAL) {
2120 netdev_warn(priv->dev,
2121 "Timed out while disabling RX DMA\n");
2122 ret = -ETIMEDOUT;
2123 }
2124
2125 return ret;
2126 }
2127
2128 static int bcmgenet_close(struct net_device *dev)
2129 {
2130 struct bcmgenet_priv *priv = netdev_priv(dev);
2131 int ret;
2132 u32 reg;
2133
2134 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
2135
2136 phy_stop(priv->phydev);
2137
2138 /* Disable MAC receive */
2139 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2140 reg &= ~CMD_RX_EN;
2141 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2142
2143 netif_tx_stop_all_queues(dev);
2144
2145 ret = bcmgenet_dma_teardown(priv);
2146 if (ret)
2147 return ret;
2148
2149 /* Disable MAC transmit. TX DMA disabled have to done before this */
2150 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2151 reg &= ~CMD_TX_EN;
2152 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2153
2154 napi_disable(&priv->napi);
2155
2156 /* tx reclaim */
2157 bcmgenet_tx_reclaim_all(dev);
2158 bcmgenet_fini_dma(priv);
2159
2160 free_irq(priv->irq0, priv);
2161 free_irq(priv->irq1, priv);
2162
2163 /* Wait for pending work items to complete - we are stopping
2164 * the clock now. Since interrupts are disabled, no new work
2165 * will be scheduled.
2166 */
2167 cancel_work_sync(&priv->bcmgenet_irq_work);
2168
2169 if (phy_is_internal(priv->phydev))
2170 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
2171
2172 if (priv->wol_enabled)
2173 clk_enable(priv->clk_wol);
2174
2175 if (!IS_ERR(priv->clk))
2176 clk_disable_unprepare(priv->clk);
2177
2178 return 0;
2179 }
2180
2181 static void bcmgenet_timeout(struct net_device *dev)
2182 {
2183 struct bcmgenet_priv *priv = netdev_priv(dev);
2184
2185 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
2186
2187 dev->trans_start = jiffies;
2188
2189 dev->stats.tx_errors++;
2190
2191 netif_tx_wake_all_queues(dev);
2192 }
2193
2194 #define MAX_MC_COUNT 16
2195
2196 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
2197 unsigned char *addr,
2198 int *i,
2199 int *mc)
2200 {
2201 u32 reg;
2202
2203 bcmgenet_umac_writel(priv,
2204 addr[0] << 8 | addr[1], UMAC_MDF_ADDR + (*i * 4));
2205 bcmgenet_umac_writel(priv,
2206 addr[2] << 24 | addr[3] << 16 |
2207 addr[4] << 8 | addr[5],
2208 UMAC_MDF_ADDR + ((*i + 1) * 4));
2209 reg = bcmgenet_umac_readl(priv, UMAC_MDF_CTRL);
2210 reg |= (1 << (MAX_MC_COUNT - *mc));
2211 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
2212 *i += 2;
2213 (*mc)++;
2214 }
2215
2216 static void bcmgenet_set_rx_mode(struct net_device *dev)
2217 {
2218 struct bcmgenet_priv *priv = netdev_priv(dev);
2219 struct netdev_hw_addr *ha;
2220 int i, mc;
2221 u32 reg;
2222
2223 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
2224
2225 /* Promiscous mode */
2226 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2227 if (dev->flags & IFF_PROMISC) {
2228 reg |= CMD_PROMISC;
2229 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2230 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
2231 return;
2232 } else {
2233 reg &= ~CMD_PROMISC;
2234 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2235 }
2236
2237 /* UniMac doesn't support ALLMULTI */
2238 if (dev->flags & IFF_ALLMULTI) {
2239 netdev_warn(dev, "ALLMULTI is not supported\n");
2240 return;
2241 }
2242
2243 /* update MDF filter */
2244 i = 0;
2245 mc = 0;
2246 /* Broadcast */
2247 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i, &mc);
2248 /* my own address.*/
2249 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i, &mc);
2250 /* Unicast list*/
2251 if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc))
2252 return;
2253
2254 if (!netdev_uc_empty(dev))
2255 netdev_for_each_uc_addr(ha, dev)
2256 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2257 /* Multicast */
2258 if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc))
2259 return;
2260
2261 netdev_for_each_mc_addr(ha, dev)
2262 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2263 }
2264
2265 /* Set the hardware MAC address. */
2266 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
2267 {
2268 struct sockaddr *addr = p;
2269
2270 /* Setting the MAC address at the hardware level is not possible
2271 * without disabling the UniMAC RX/TX enable bits.
2272 */
2273 if (netif_running(dev))
2274 return -EBUSY;
2275
2276 ether_addr_copy(dev->dev_addr, addr->sa_data);
2277
2278 return 0;
2279 }
2280
2281 static const struct net_device_ops bcmgenet_netdev_ops = {
2282 .ndo_open = bcmgenet_open,
2283 .ndo_stop = bcmgenet_close,
2284 .ndo_start_xmit = bcmgenet_xmit,
2285 .ndo_tx_timeout = bcmgenet_timeout,
2286 .ndo_set_rx_mode = bcmgenet_set_rx_mode,
2287 .ndo_set_mac_address = bcmgenet_set_mac_addr,
2288 .ndo_do_ioctl = bcmgenet_ioctl,
2289 .ndo_set_features = bcmgenet_set_features,
2290 };
2291
2292 /* Array of GENET hardware parameters/characteristics */
2293 static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
2294 [GENET_V1] = {
2295 .tx_queues = 0,
2296 .rx_queues = 0,
2297 .bds_cnt = 0,
2298 .bp_in_en_shift = 16,
2299 .bp_in_mask = 0xffff,
2300 .hfb_filter_cnt = 16,
2301 .qtag_mask = 0x1F,
2302 .hfb_offset = 0x1000,
2303 .rdma_offset = 0x2000,
2304 .tdma_offset = 0x3000,
2305 .words_per_bd = 2,
2306 },
2307 [GENET_V2] = {
2308 .tx_queues = 4,
2309 .rx_queues = 4,
2310 .bds_cnt = 32,
2311 .bp_in_en_shift = 16,
2312 .bp_in_mask = 0xffff,
2313 .hfb_filter_cnt = 16,
2314 .qtag_mask = 0x1F,
2315 .tbuf_offset = 0x0600,
2316 .hfb_offset = 0x1000,
2317 .hfb_reg_offset = 0x2000,
2318 .rdma_offset = 0x3000,
2319 .tdma_offset = 0x4000,
2320 .words_per_bd = 2,
2321 .flags = GENET_HAS_EXT,
2322 },
2323 [GENET_V3] = {
2324 .tx_queues = 4,
2325 .rx_queues = 4,
2326 .bds_cnt = 32,
2327 .bp_in_en_shift = 17,
2328 .bp_in_mask = 0x1ffff,
2329 .hfb_filter_cnt = 48,
2330 .qtag_mask = 0x3F,
2331 .tbuf_offset = 0x0600,
2332 .hfb_offset = 0x8000,
2333 .hfb_reg_offset = 0xfc00,
2334 .rdma_offset = 0x10000,
2335 .tdma_offset = 0x11000,
2336 .words_per_bd = 2,
2337 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR,
2338 },
2339 [GENET_V4] = {
2340 .tx_queues = 4,
2341 .rx_queues = 4,
2342 .bds_cnt = 32,
2343 .bp_in_en_shift = 17,
2344 .bp_in_mask = 0x1ffff,
2345 .hfb_filter_cnt = 48,
2346 .qtag_mask = 0x3F,
2347 .tbuf_offset = 0x0600,
2348 .hfb_offset = 0x8000,
2349 .hfb_reg_offset = 0xfc00,
2350 .rdma_offset = 0x2000,
2351 .tdma_offset = 0x4000,
2352 .words_per_bd = 3,
2353 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | GENET_HAS_MDIO_INTR,
2354 },
2355 };
2356
2357 /* Infer hardware parameters from the detected GENET version */
2358 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
2359 {
2360 struct bcmgenet_hw_params *params;
2361 u32 reg;
2362 u8 major;
2363
2364 if (GENET_IS_V4(priv)) {
2365 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
2366 genet_dma_ring_regs = genet_dma_ring_regs_v4;
2367 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
2368 priv->version = GENET_V4;
2369 } else if (GENET_IS_V3(priv)) {
2370 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
2371 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2372 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
2373 priv->version = GENET_V3;
2374 } else if (GENET_IS_V2(priv)) {
2375 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
2376 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2377 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
2378 priv->version = GENET_V2;
2379 } else if (GENET_IS_V1(priv)) {
2380 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
2381 genet_dma_ring_regs = genet_dma_ring_regs_v123;
2382 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
2383 priv->version = GENET_V1;
2384 }
2385
2386 /* enum genet_version starts at 1 */
2387 priv->hw_params = &bcmgenet_hw_params[priv->version];
2388 params = priv->hw_params;
2389
2390 /* Read GENET HW version */
2391 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
2392 major = (reg >> 24 & 0x0f);
2393 if (major == 5)
2394 major = 4;
2395 else if (major == 0)
2396 major = 1;
2397 if (major != priv->version) {
2398 dev_err(&priv->pdev->dev,
2399 "GENET version mismatch, got: %d, configured for: %d\n",
2400 major, priv->version);
2401 }
2402
2403 /* Print the GENET core version */
2404 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
2405 major, (reg >> 16) & 0x0f, reg & 0xffff);
2406
2407 #ifdef CONFIG_PHYS_ADDR_T_64BIT
2408 if (!(params->flags & GENET_HAS_40BITS))
2409 pr_warn("GENET does not support 40-bits PA\n");
2410 #endif
2411
2412 pr_debug("Configuration for version: %d\n"
2413 "TXq: %1d, RXq: %1d, BDs: %1d\n"
2414 "BP << en: %2d, BP msk: 0x%05x\n"
2415 "HFB count: %2d, QTAQ msk: 0x%05x\n"
2416 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
2417 "RDMA: 0x%05x, TDMA: 0x%05x\n"
2418 "Words/BD: %d\n",
2419 priv->version,
2420 params->tx_queues, params->rx_queues, params->bds_cnt,
2421 params->bp_in_en_shift, params->bp_in_mask,
2422 params->hfb_filter_cnt, params->qtag_mask,
2423 params->tbuf_offset, params->hfb_offset,
2424 params->hfb_reg_offset,
2425 params->rdma_offset, params->tdma_offset,
2426 params->words_per_bd);
2427 }
2428
2429 static const struct of_device_id bcmgenet_match[] = {
2430 { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
2431 { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
2432 { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
2433 { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
2434 { },
2435 };
2436
2437 static int bcmgenet_probe(struct platform_device *pdev)
2438 {
2439 struct device_node *dn = pdev->dev.of_node;
2440 const struct of_device_id *of_id;
2441 struct bcmgenet_priv *priv;
2442 struct net_device *dev;
2443 const void *macaddr;
2444 struct resource *r;
2445 int err = -EIO;
2446
2447 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and a single RX queue */
2448 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1, 1);
2449 if (!dev) {
2450 dev_err(&pdev->dev, "can't allocate net device\n");
2451 return -ENOMEM;
2452 }
2453
2454 of_id = of_match_node(bcmgenet_match, dn);
2455 if (!of_id)
2456 return -EINVAL;
2457
2458 priv = netdev_priv(dev);
2459 priv->irq0 = platform_get_irq(pdev, 0);
2460 priv->irq1 = platform_get_irq(pdev, 1);
2461 if (!priv->irq0 || !priv->irq1) {
2462 dev_err(&pdev->dev, "can't find IRQs\n");
2463 err = -EINVAL;
2464 goto err;
2465 }
2466
2467 macaddr = of_get_mac_address(dn);
2468 if (!macaddr) {
2469 dev_err(&pdev->dev, "can't find MAC address\n");
2470 err = -EINVAL;
2471 goto err;
2472 }
2473
2474 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2475 priv->base = devm_ioremap_resource(&pdev->dev, r);
2476 if (IS_ERR(priv->base)) {
2477 err = PTR_ERR(priv->base);
2478 goto err;
2479 }
2480
2481 SET_NETDEV_DEV(dev, &pdev->dev);
2482 dev_set_drvdata(&pdev->dev, dev);
2483 ether_addr_copy(dev->dev_addr, macaddr);
2484 dev->watchdog_timeo = 2 * HZ;
2485 SET_ETHTOOL_OPS(dev, &bcmgenet_ethtool_ops);
2486 dev->netdev_ops = &bcmgenet_netdev_ops;
2487 netif_napi_add(dev, &priv->napi, bcmgenet_poll, 64);
2488
2489 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
2490
2491 /* Set hardware features */
2492 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
2493 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
2494
2495 /* Set the needed headroom to account for any possible
2496 * features enabling/disabling at runtime
2497 */
2498 dev->needed_headroom += 64;
2499
2500 netdev_boot_setup_check(dev);
2501
2502 priv->dev = dev;
2503 priv->pdev = pdev;
2504 priv->version = (enum bcmgenet_version)of_id->data;
2505
2506 bcmgenet_set_hw_params(priv);
2507
2508 /* Mii wait queue */
2509 init_waitqueue_head(&priv->wq);
2510 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
2511 priv->rx_buf_len = RX_BUF_LENGTH;
2512 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
2513
2514 priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
2515 if (IS_ERR(priv->clk))
2516 dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
2517
2518 priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
2519 if (IS_ERR(priv->clk_wol))
2520 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
2521
2522 if (!IS_ERR(priv->clk))
2523 clk_prepare_enable(priv->clk);
2524
2525 err = reset_umac(priv);
2526 if (err)
2527 goto err_clk_disable;
2528
2529 err = bcmgenet_mii_init(dev);
2530 if (err)
2531 goto err_clk_disable;
2532
2533 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues
2534 * just the ring 16 descriptor based TX
2535 */
2536 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
2537 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
2538
2539 err = register_netdev(dev);
2540 if (err)
2541 goto err_clk_disable;
2542
2543 /* Turn off the main clock, WOL clock is handled separately */
2544 if (!IS_ERR(priv->clk))
2545 clk_disable_unprepare(priv->clk);
2546
2547 return err;
2548
2549 err_clk_disable:
2550 if (!IS_ERR(priv->clk))
2551 clk_disable_unprepare(priv->clk);
2552 err:
2553 free_netdev(dev);
2554 return err;
2555 }
2556
2557 static int bcmgenet_remove(struct platform_device *pdev)
2558 {
2559 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
2560
2561 dev_set_drvdata(&pdev->dev, NULL);
2562 unregister_netdev(priv->dev);
2563 bcmgenet_mii_exit(priv->dev);
2564 free_netdev(priv->dev);
2565
2566 return 0;
2567 }
2568
2569
2570 static struct platform_driver bcmgenet_driver = {
2571 .probe = bcmgenet_probe,
2572 .remove = bcmgenet_remove,
2573 .driver = {
2574 .name = "bcmgenet",
2575 .owner = THIS_MODULE,
2576 .of_match_table = bcmgenet_match,
2577 },
2578 };
2579 module_platform_driver(bcmgenet_driver);
2580
2581 MODULE_AUTHOR("Broadcom Corporation");
2582 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
2583 MODULE_ALIAS("platform:bcmgenet");
2584 MODULE_LICENSE("GPL");
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