2 * Broadcom GENET (Gigabit Ethernet) controller driver
4 * Copyright (c) 2014 Broadcom Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 #define pr_fmt(fmt) "bcmgenet: " fmt
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/sched.h>
25 #include <linux/types.h>
26 #include <linux/fcntl.h>
27 #include <linux/interrupt.h>
28 #include <linux/string.h>
29 #include <linux/if_ether.h>
30 #include <linux/init.h>
31 #include <linux/errno.h>
32 #include <linux/delay.h>
33 #include <linux/platform_device.h>
34 #include <linux/dma-mapping.h>
36 #include <linux/clk.h>
38 #include <linux/of_address.h>
39 #include <linux/of_irq.h>
40 #include <linux/of_net.h>
41 #include <linux/of_platform.h>
44 #include <linux/mii.h>
45 #include <linux/ethtool.h>
46 #include <linux/netdevice.h>
47 #include <linux/inetdevice.h>
48 #include <linux/etherdevice.h>
49 #include <linux/skbuff.h>
52 #include <linux/ipv6.h>
53 #include <linux/phy.h>
55 #include <asm/unaligned.h>
59 /* Maximum number of hardware queues, downsized if needed */
60 #define GENET_MAX_MQ_CNT 4
62 /* Default highest priority queue for multi queue support */
63 #define GENET_Q0_PRIORITY 0
65 #define GENET_DEFAULT_BD_CNT \
66 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->bds_cnt)
68 #define RX_BUF_LENGTH 2048
69 #define SKB_ALIGNMENT 32
71 /* Tx/Rx DMA register offset, skip 256 descriptors */
72 #define WORDS_PER_BD(p) (p->hw_params->words_per_bd)
73 #define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32))
75 #define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \
76 TOTAL_DESC * DMA_DESC_SIZE)
78 #define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \
79 TOTAL_DESC * DMA_DESC_SIZE)
81 static inline void dmadesc_set_length_status(struct bcmgenet_priv
*priv
,
82 void __iomem
*d
, u32 value
)
84 __raw_writel(value
, d
+ DMA_DESC_LENGTH_STATUS
);
87 static inline u32
dmadesc_get_length_status(struct bcmgenet_priv
*priv
,
90 return __raw_readl(d
+ DMA_DESC_LENGTH_STATUS
);
93 static inline void dmadesc_set_addr(struct bcmgenet_priv
*priv
,
97 __raw_writel(lower_32_bits(addr
), d
+ DMA_DESC_ADDRESS_LO
);
99 /* Register writes to GISB bus can take couple hundred nanoseconds
100 * and are done for each packet, save these expensive writes unless
101 * the platform is explicitely configured for 64-bits/LPAE.
103 #ifdef CONFIG_PHYS_ADDR_T_64BIT
104 if (priv
->hw_params
->flags
& GENET_HAS_40BITS
)
105 __raw_writel(upper_32_bits(addr
), d
+ DMA_DESC_ADDRESS_HI
);
109 /* Combined address + length/status setter */
110 static inline void dmadesc_set(struct bcmgenet_priv
*priv
,
111 void __iomem
*d
, dma_addr_t addr
, u32 val
)
113 dmadesc_set_length_status(priv
, d
, val
);
114 dmadesc_set_addr(priv
, d
, addr
);
117 static inline dma_addr_t
dmadesc_get_addr(struct bcmgenet_priv
*priv
,
122 addr
= __raw_readl(d
+ DMA_DESC_ADDRESS_LO
);
124 /* Register writes to GISB bus can take couple hundred nanoseconds
125 * and are done for each packet, save these expensive writes unless
126 * the platform is explicitely configured for 64-bits/LPAE.
128 #ifdef CONFIG_PHYS_ADDR_T_64BIT
129 if (priv
->hw_params
->flags
& GENET_HAS_40BITS
)
130 addr
|= (u64
)__raw_readl(d
+ DMA_DESC_ADDRESS_HI
) << 32;
135 #define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x"
137 #define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
140 static inline u32
bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv
*priv
)
142 if (GENET_IS_V1(priv
))
143 return bcmgenet_rbuf_readl(priv
, RBUF_FLUSH_CTRL_V1
);
145 return bcmgenet_sys_readl(priv
, SYS_RBUF_FLUSH_CTRL
);
148 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv
*priv
, u32 val
)
150 if (GENET_IS_V1(priv
))
151 bcmgenet_rbuf_writel(priv
, val
, RBUF_FLUSH_CTRL_V1
);
153 bcmgenet_sys_writel(priv
, val
, SYS_RBUF_FLUSH_CTRL
);
156 /* These macros are defined to deal with register map change
157 * between GENET1.1 and GENET2. Only those currently being used
158 * by driver are defined.
160 static inline u32
bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv
*priv
)
162 if (GENET_IS_V1(priv
))
163 return bcmgenet_rbuf_readl(priv
, TBUF_CTRL_V1
);
165 return __raw_readl(priv
->base
+
166 priv
->hw_params
->tbuf_offset
+ TBUF_CTRL
);
169 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv
*priv
, u32 val
)
171 if (GENET_IS_V1(priv
))
172 bcmgenet_rbuf_writel(priv
, val
, TBUF_CTRL_V1
);
174 __raw_writel(val
, priv
->base
+
175 priv
->hw_params
->tbuf_offset
+ TBUF_CTRL
);
178 static inline u32
bcmgenet_bp_mc_get(struct bcmgenet_priv
*priv
)
180 if (GENET_IS_V1(priv
))
181 return bcmgenet_rbuf_readl(priv
, TBUF_BP_MC_V1
);
183 return __raw_readl(priv
->base
+
184 priv
->hw_params
->tbuf_offset
+ TBUF_BP_MC
);
187 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv
*priv
, u32 val
)
189 if (GENET_IS_V1(priv
))
190 bcmgenet_rbuf_writel(priv
, val
, TBUF_BP_MC_V1
);
192 __raw_writel(val
, priv
->base
+
193 priv
->hw_params
->tbuf_offset
+ TBUF_BP_MC
);
196 /* RX/TX DMA register accessors */
207 static const u8 bcmgenet_dma_regs_v3plus
[] = {
208 [DMA_RING_CFG
] = 0x00,
211 [DMA_SCB_BURST_SIZE
] = 0x0C,
212 [DMA_ARB_CTRL
] = 0x2C,
213 [DMA_PRIORITY
] = 0x30,
214 [DMA_RING_PRIORITY
] = 0x38,
217 static const u8 bcmgenet_dma_regs_v2
[] = {
218 [DMA_RING_CFG
] = 0x00,
221 [DMA_SCB_BURST_SIZE
] = 0x0C,
222 [DMA_ARB_CTRL
] = 0x30,
223 [DMA_PRIORITY
] = 0x34,
224 [DMA_RING_PRIORITY
] = 0x3C,
227 static const u8 bcmgenet_dma_regs_v1
[] = {
230 [DMA_SCB_BURST_SIZE
] = 0x0C,
231 [DMA_ARB_CTRL
] = 0x30,
232 [DMA_PRIORITY
] = 0x34,
233 [DMA_RING_PRIORITY
] = 0x3C,
236 /* Set at runtime once bcmgenet version is known */
237 static const u8
*bcmgenet_dma_regs
;
239 static inline struct bcmgenet_priv
*dev_to_priv(struct device
*dev
)
241 return netdev_priv(dev_get_drvdata(dev
));
244 static inline u32
bcmgenet_tdma_readl(struct bcmgenet_priv
*priv
,
247 return __raw_readl(priv
->base
+ GENET_TDMA_REG_OFF
+
248 DMA_RINGS_SIZE
+ bcmgenet_dma_regs
[r
]);
251 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv
*priv
,
252 u32 val
, enum dma_reg r
)
254 __raw_writel(val
, priv
->base
+ GENET_TDMA_REG_OFF
+
255 DMA_RINGS_SIZE
+ bcmgenet_dma_regs
[r
]);
258 static inline u32
bcmgenet_rdma_readl(struct bcmgenet_priv
*priv
,
261 return __raw_readl(priv
->base
+ GENET_RDMA_REG_OFF
+
262 DMA_RINGS_SIZE
+ bcmgenet_dma_regs
[r
]);
265 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv
*priv
,
266 u32 val
, enum dma_reg r
)
268 __raw_writel(val
, priv
->base
+ GENET_RDMA_REG_OFF
+
269 DMA_RINGS_SIZE
+ bcmgenet_dma_regs
[r
]);
272 /* RDMA/TDMA ring registers and accessors
273 * we merge the common fields and just prefix with T/D the registers
274 * having different meaning depending on the direction
278 RDMA_WRITE_PTR
= TDMA_READ_PTR
,
280 RDMA_WRITE_PTR_HI
= TDMA_READ_PTR_HI
,
282 RDMA_PROD_INDEX
= TDMA_CONS_INDEX
,
284 RDMA_CONS_INDEX
= TDMA_PROD_INDEX
,
290 DMA_MBUF_DONE_THRESH
,
292 RDMA_XON_XOFF_THRESH
= TDMA_FLOW_PERIOD
,
294 RDMA_READ_PTR
= TDMA_WRITE_PTR
,
296 RDMA_READ_PTR_HI
= TDMA_WRITE_PTR_HI
299 /* GENET v4 supports 40-bits pointer addressing
300 * for obvious reasons the LO and HI word parts
301 * are contiguous, but this offsets the other
304 static const u8 genet_dma_ring_regs_v4
[] = {
305 [TDMA_READ_PTR
] = 0x00,
306 [TDMA_READ_PTR_HI
] = 0x04,
307 [TDMA_CONS_INDEX
] = 0x08,
308 [TDMA_PROD_INDEX
] = 0x0C,
309 [DMA_RING_BUF_SIZE
] = 0x10,
310 [DMA_START_ADDR
] = 0x14,
311 [DMA_START_ADDR_HI
] = 0x18,
312 [DMA_END_ADDR
] = 0x1C,
313 [DMA_END_ADDR_HI
] = 0x20,
314 [DMA_MBUF_DONE_THRESH
] = 0x24,
315 [TDMA_FLOW_PERIOD
] = 0x28,
316 [TDMA_WRITE_PTR
] = 0x2C,
317 [TDMA_WRITE_PTR_HI
] = 0x30,
320 static const u8 genet_dma_ring_regs_v123
[] = {
321 [TDMA_READ_PTR
] = 0x00,
322 [TDMA_CONS_INDEX
] = 0x04,
323 [TDMA_PROD_INDEX
] = 0x08,
324 [DMA_RING_BUF_SIZE
] = 0x0C,
325 [DMA_START_ADDR
] = 0x10,
326 [DMA_END_ADDR
] = 0x14,
327 [DMA_MBUF_DONE_THRESH
] = 0x18,
328 [TDMA_FLOW_PERIOD
] = 0x1C,
329 [TDMA_WRITE_PTR
] = 0x20,
332 /* Set at runtime once GENET version is known */
333 static const u8
*genet_dma_ring_regs
;
335 static inline u32
bcmgenet_tdma_ring_readl(struct bcmgenet_priv
*priv
,
339 return __raw_readl(priv
->base
+ GENET_TDMA_REG_OFF
+
340 (DMA_RING_SIZE
* ring
) +
341 genet_dma_ring_regs
[r
]);
344 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv
*priv
,
349 __raw_writel(val
, priv
->base
+ GENET_TDMA_REG_OFF
+
350 (DMA_RING_SIZE
* ring
) +
351 genet_dma_ring_regs
[r
]);
354 static inline u32
bcmgenet_rdma_ring_readl(struct bcmgenet_priv
*priv
,
358 return __raw_readl(priv
->base
+ GENET_RDMA_REG_OFF
+
359 (DMA_RING_SIZE
* ring
) +
360 genet_dma_ring_regs
[r
]);
363 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv
*priv
,
368 __raw_writel(val
, priv
->base
+ GENET_RDMA_REG_OFF
+
369 (DMA_RING_SIZE
* ring
) +
370 genet_dma_ring_regs
[r
]);
373 static int bcmgenet_get_settings(struct net_device
*dev
,
374 struct ethtool_cmd
*cmd
)
376 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
378 if (!netif_running(dev
))
384 return phy_ethtool_gset(priv
->phydev
, cmd
);
387 static int bcmgenet_set_settings(struct net_device
*dev
,
388 struct ethtool_cmd
*cmd
)
390 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
392 if (!netif_running(dev
))
398 return phy_ethtool_sset(priv
->phydev
, cmd
);
401 static int bcmgenet_set_rx_csum(struct net_device
*dev
,
402 netdev_features_t wanted
)
404 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
408 rx_csum_en
= !!(wanted
& NETIF_F_RXCSUM
);
410 rbuf_chk_ctrl
= bcmgenet_rbuf_readl(priv
, RBUF_CHK_CTRL
);
412 /* enable rx checksumming */
414 rbuf_chk_ctrl
|= RBUF_RXCHK_EN
;
416 rbuf_chk_ctrl
&= ~RBUF_RXCHK_EN
;
417 priv
->desc_rxchk_en
= rx_csum_en
;
419 /* If UniMAC forwards CRC, we need to skip over it to get
420 * a valid CHK bit to be set in the per-packet status word
422 if (rx_csum_en
&& priv
->crc_fwd_en
)
423 rbuf_chk_ctrl
|= RBUF_SKIP_FCS
;
425 rbuf_chk_ctrl
&= ~RBUF_SKIP_FCS
;
427 bcmgenet_rbuf_writel(priv
, rbuf_chk_ctrl
, RBUF_CHK_CTRL
);
432 static int bcmgenet_set_tx_csum(struct net_device
*dev
,
433 netdev_features_t wanted
)
435 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
437 u32 tbuf_ctrl
, rbuf_ctrl
;
439 tbuf_ctrl
= bcmgenet_tbuf_ctrl_get(priv
);
440 rbuf_ctrl
= bcmgenet_rbuf_readl(priv
, RBUF_CTRL
);
442 desc_64b_en
= !!(wanted
& (NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
));
444 /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
446 tbuf_ctrl
|= RBUF_64B_EN
;
447 rbuf_ctrl
|= RBUF_64B_EN
;
449 tbuf_ctrl
&= ~RBUF_64B_EN
;
450 rbuf_ctrl
&= ~RBUF_64B_EN
;
452 priv
->desc_64b_en
= desc_64b_en
;
454 bcmgenet_tbuf_ctrl_set(priv
, tbuf_ctrl
);
455 bcmgenet_rbuf_writel(priv
, rbuf_ctrl
, RBUF_CTRL
);
460 static int bcmgenet_set_features(struct net_device
*dev
,
461 netdev_features_t features
)
463 netdev_features_t changed
= features
^ dev
->features
;
464 netdev_features_t wanted
= dev
->wanted_features
;
467 if (changed
& (NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
))
468 ret
= bcmgenet_set_tx_csum(dev
, wanted
);
469 if (changed
& (NETIF_F_RXCSUM
))
470 ret
= bcmgenet_set_rx_csum(dev
, wanted
);
475 static u32
bcmgenet_get_msglevel(struct net_device
*dev
)
477 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
479 return priv
->msg_enable
;
482 static void bcmgenet_set_msglevel(struct net_device
*dev
, u32 level
)
484 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
486 priv
->msg_enable
= level
;
489 /* standard ethtool support functions. */
490 enum bcmgenet_stat_type
{
491 BCMGENET_STAT_NETDEV
= -1,
492 BCMGENET_STAT_MIB_RX
,
493 BCMGENET_STAT_MIB_TX
,
498 struct bcmgenet_stats
{
499 char stat_string
[ETH_GSTRING_LEN
];
502 enum bcmgenet_stat_type type
;
503 /* reg offset from UMAC base for misc counters */
507 #define STAT_NETDEV(m) { \
508 .stat_string = __stringify(m), \
509 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
510 .stat_offset = offsetof(struct net_device_stats, m), \
511 .type = BCMGENET_STAT_NETDEV, \
514 #define STAT_GENET_MIB(str, m, _type) { \
515 .stat_string = str, \
516 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
517 .stat_offset = offsetof(struct bcmgenet_priv, m), \
521 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
522 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
523 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
525 #define STAT_GENET_MISC(str, m, offset) { \
526 .stat_string = str, \
527 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
528 .stat_offset = offsetof(struct bcmgenet_priv, m), \
529 .type = BCMGENET_STAT_MISC, \
530 .reg_offset = offset, \
534 /* There is a 0xC gap between the end of RX and beginning of TX stats and then
535 * between the end of TX stats and the beginning of the RX RUNT
537 #define BCMGENET_STAT_OFFSET 0xc
539 /* Hardware counters must be kept in sync because the order/offset
540 * is important here (order in structure declaration = order in hardware)
542 static const struct bcmgenet_stats bcmgenet_gstrings_stats
[] = {
544 STAT_NETDEV(rx_packets
),
545 STAT_NETDEV(tx_packets
),
546 STAT_NETDEV(rx_bytes
),
547 STAT_NETDEV(tx_bytes
),
548 STAT_NETDEV(rx_errors
),
549 STAT_NETDEV(tx_errors
),
550 STAT_NETDEV(rx_dropped
),
551 STAT_NETDEV(tx_dropped
),
552 STAT_NETDEV(multicast
),
553 /* UniMAC RSV counters */
554 STAT_GENET_MIB_RX("rx_64_octets", mib
.rx
.pkt_cnt
.cnt_64
),
555 STAT_GENET_MIB_RX("rx_65_127_oct", mib
.rx
.pkt_cnt
.cnt_127
),
556 STAT_GENET_MIB_RX("rx_128_255_oct", mib
.rx
.pkt_cnt
.cnt_255
),
557 STAT_GENET_MIB_RX("rx_256_511_oct", mib
.rx
.pkt_cnt
.cnt_511
),
558 STAT_GENET_MIB_RX("rx_512_1023_oct", mib
.rx
.pkt_cnt
.cnt_1023
),
559 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib
.rx
.pkt_cnt
.cnt_1518
),
560 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib
.rx
.pkt_cnt
.cnt_mgv
),
561 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib
.rx
.pkt_cnt
.cnt_2047
),
562 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib
.rx
.pkt_cnt
.cnt_4095
),
563 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib
.rx
.pkt_cnt
.cnt_9216
),
564 STAT_GENET_MIB_RX("rx_pkts", mib
.rx
.pkt
),
565 STAT_GENET_MIB_RX("rx_bytes", mib
.rx
.bytes
),
566 STAT_GENET_MIB_RX("rx_multicast", mib
.rx
.mca
),
567 STAT_GENET_MIB_RX("rx_broadcast", mib
.rx
.bca
),
568 STAT_GENET_MIB_RX("rx_fcs", mib
.rx
.fcs
),
569 STAT_GENET_MIB_RX("rx_control", mib
.rx
.cf
),
570 STAT_GENET_MIB_RX("rx_pause", mib
.rx
.pf
),
571 STAT_GENET_MIB_RX("rx_unknown", mib
.rx
.uo
),
572 STAT_GENET_MIB_RX("rx_align", mib
.rx
.aln
),
573 STAT_GENET_MIB_RX("rx_outrange", mib
.rx
.flr
),
574 STAT_GENET_MIB_RX("rx_code", mib
.rx
.cde
),
575 STAT_GENET_MIB_RX("rx_carrier", mib
.rx
.fcr
),
576 STAT_GENET_MIB_RX("rx_oversize", mib
.rx
.ovr
),
577 STAT_GENET_MIB_RX("rx_jabber", mib
.rx
.jbr
),
578 STAT_GENET_MIB_RX("rx_mtu_err", mib
.rx
.mtue
),
579 STAT_GENET_MIB_RX("rx_good_pkts", mib
.rx
.pok
),
580 STAT_GENET_MIB_RX("rx_unicast", mib
.rx
.uc
),
581 STAT_GENET_MIB_RX("rx_ppp", mib
.rx
.ppp
),
582 STAT_GENET_MIB_RX("rx_crc", mib
.rx
.rcrc
),
583 /* UniMAC TSV counters */
584 STAT_GENET_MIB_TX("tx_64_octets", mib
.tx
.pkt_cnt
.cnt_64
),
585 STAT_GENET_MIB_TX("tx_65_127_oct", mib
.tx
.pkt_cnt
.cnt_127
),
586 STAT_GENET_MIB_TX("tx_128_255_oct", mib
.tx
.pkt_cnt
.cnt_255
),
587 STAT_GENET_MIB_TX("tx_256_511_oct", mib
.tx
.pkt_cnt
.cnt_511
),
588 STAT_GENET_MIB_TX("tx_512_1023_oct", mib
.tx
.pkt_cnt
.cnt_1023
),
589 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib
.tx
.pkt_cnt
.cnt_1518
),
590 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib
.tx
.pkt_cnt
.cnt_mgv
),
591 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib
.tx
.pkt_cnt
.cnt_2047
),
592 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib
.tx
.pkt_cnt
.cnt_4095
),
593 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib
.tx
.pkt_cnt
.cnt_9216
),
594 STAT_GENET_MIB_TX("tx_pkts", mib
.tx
.pkts
),
595 STAT_GENET_MIB_TX("tx_multicast", mib
.tx
.mca
),
596 STAT_GENET_MIB_TX("tx_broadcast", mib
.tx
.bca
),
597 STAT_GENET_MIB_TX("tx_pause", mib
.tx
.pf
),
598 STAT_GENET_MIB_TX("tx_control", mib
.tx
.cf
),
599 STAT_GENET_MIB_TX("tx_fcs_err", mib
.tx
.fcs
),
600 STAT_GENET_MIB_TX("tx_oversize", mib
.tx
.ovr
),
601 STAT_GENET_MIB_TX("tx_defer", mib
.tx
.drf
),
602 STAT_GENET_MIB_TX("tx_excess_defer", mib
.tx
.edf
),
603 STAT_GENET_MIB_TX("tx_single_col", mib
.tx
.scl
),
604 STAT_GENET_MIB_TX("tx_multi_col", mib
.tx
.mcl
),
605 STAT_GENET_MIB_TX("tx_late_col", mib
.tx
.lcl
),
606 STAT_GENET_MIB_TX("tx_excess_col", mib
.tx
.ecl
),
607 STAT_GENET_MIB_TX("tx_frags", mib
.tx
.frg
),
608 STAT_GENET_MIB_TX("tx_total_col", mib
.tx
.ncl
),
609 STAT_GENET_MIB_TX("tx_jabber", mib
.tx
.jbr
),
610 STAT_GENET_MIB_TX("tx_bytes", mib
.tx
.bytes
),
611 STAT_GENET_MIB_TX("tx_good_pkts", mib
.tx
.pok
),
612 STAT_GENET_MIB_TX("tx_unicast", mib
.tx
.uc
),
613 /* UniMAC RUNT counters */
614 STAT_GENET_RUNT("rx_runt_pkts", mib
.rx_runt_cnt
),
615 STAT_GENET_RUNT("rx_runt_valid_fcs", mib
.rx_runt_fcs
),
616 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib
.rx_runt_fcs_align
),
617 STAT_GENET_RUNT("rx_runt_bytes", mib
.rx_runt_bytes
),
618 /* Misc UniMAC counters */
619 STAT_GENET_MISC("rbuf_ovflow_cnt", mib
.rbuf_ovflow_cnt
,
621 STAT_GENET_MISC("rbuf_err_cnt", mib
.rbuf_err_cnt
, UMAC_RBUF_ERR_CNT
),
622 STAT_GENET_MISC("mdf_err_cnt", mib
.mdf_err_cnt
, UMAC_MDF_ERR_CNT
),
625 #define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats)
627 static void bcmgenet_get_drvinfo(struct net_device
*dev
,
628 struct ethtool_drvinfo
*info
)
630 strlcpy(info
->driver
, "bcmgenet", sizeof(info
->driver
));
631 strlcpy(info
->version
, "v2.0", sizeof(info
->version
));
632 info
->n_stats
= BCMGENET_STATS_LEN
;
636 static int bcmgenet_get_sset_count(struct net_device
*dev
, int string_set
)
638 switch (string_set
) {
640 return BCMGENET_STATS_LEN
;
646 static void bcmgenet_get_strings(struct net_device
*dev
,
647 u32 stringset
, u8
*data
)
653 for (i
= 0; i
< BCMGENET_STATS_LEN
; i
++) {
654 memcpy(data
+ i
* ETH_GSTRING_LEN
,
655 bcmgenet_gstrings_stats
[i
].stat_string
,
662 static void bcmgenet_update_mib_counters(struct bcmgenet_priv
*priv
)
666 for (i
= 0; i
< BCMGENET_STATS_LEN
; i
++) {
667 const struct bcmgenet_stats
*s
;
672 s
= &bcmgenet_gstrings_stats
[i
];
674 case BCMGENET_STAT_NETDEV
:
676 case BCMGENET_STAT_MIB_RX
:
677 case BCMGENET_STAT_MIB_TX
:
678 case BCMGENET_STAT_RUNT
:
679 if (s
->type
!= BCMGENET_STAT_MIB_RX
)
680 offset
= BCMGENET_STAT_OFFSET
;
681 val
= bcmgenet_umac_readl(priv
, UMAC_MIB_START
+
684 case BCMGENET_STAT_MISC
:
685 val
= bcmgenet_umac_readl(priv
, s
->reg_offset
);
686 /* clear if overflowed */
688 bcmgenet_umac_writel(priv
, 0, s
->reg_offset
);
693 p
= (char *)priv
+ s
->stat_offset
;
698 static void bcmgenet_get_ethtool_stats(struct net_device
*dev
,
699 struct ethtool_stats
*stats
,
702 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
705 if (netif_running(dev
))
706 bcmgenet_update_mib_counters(priv
);
708 for (i
= 0; i
< BCMGENET_STATS_LEN
; i
++) {
709 const struct bcmgenet_stats
*s
;
712 s
= &bcmgenet_gstrings_stats
[i
];
713 if (s
->type
== BCMGENET_STAT_NETDEV
)
714 p
= (char *)&dev
->stats
;
722 /* standard ethtool support functions. */
723 static struct ethtool_ops bcmgenet_ethtool_ops
= {
724 .get_strings
= bcmgenet_get_strings
,
725 .get_sset_count
= bcmgenet_get_sset_count
,
726 .get_ethtool_stats
= bcmgenet_get_ethtool_stats
,
727 .get_settings
= bcmgenet_get_settings
,
728 .set_settings
= bcmgenet_set_settings
,
729 .get_drvinfo
= bcmgenet_get_drvinfo
,
730 .get_link
= ethtool_op_get_link
,
731 .get_msglevel
= bcmgenet_get_msglevel
,
732 .set_msglevel
= bcmgenet_set_msglevel
,
735 /* Power down the unimac, based on mode. */
736 static void bcmgenet_power_down(struct bcmgenet_priv
*priv
,
737 enum bcmgenet_power_mode mode
)
742 case GENET_POWER_CABLE_SENSE
:
743 phy_detach(priv
->phydev
);
746 case GENET_POWER_WOL_MAGIC
:
747 bcmgenet_wol_power_down_cfg(priv
, mode
);
750 case GENET_POWER_PASSIVE
:
752 bcmgenet_mii_reset(priv
->dev
);
753 if (priv
->hw_params
->flags
& GENET_HAS_EXT
) {
754 reg
= bcmgenet_ext_readl(priv
, EXT_EXT_PWR_MGMT
);
755 reg
|= (EXT_PWR_DOWN_PHY
|
756 EXT_PWR_DOWN_DLL
| EXT_PWR_DOWN_BIAS
);
757 bcmgenet_ext_writel(priv
, reg
, EXT_EXT_PWR_MGMT
);
765 static void bcmgenet_power_up(struct bcmgenet_priv
*priv
,
766 enum bcmgenet_power_mode mode
)
770 if (!(priv
->hw_params
->flags
& GENET_HAS_EXT
))
773 reg
= bcmgenet_ext_readl(priv
, EXT_EXT_PWR_MGMT
);
776 case GENET_POWER_PASSIVE
:
777 reg
&= ~(EXT_PWR_DOWN_DLL
| EXT_PWR_DOWN_PHY
|
780 case GENET_POWER_CABLE_SENSE
:
782 reg
|= EXT_PWR_DN_EN_LD
;
784 case GENET_POWER_WOL_MAGIC
:
785 bcmgenet_wol_power_up_cfg(priv
, mode
);
791 bcmgenet_ext_writel(priv
, reg
, EXT_EXT_PWR_MGMT
);
792 bcmgenet_mii_reset(priv
->dev
);
795 /* ioctl handle special commands that are not present in ethtool. */
796 static int bcmgenet_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
798 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
801 if (!netif_running(dev
))
811 val
= phy_mii_ioctl(priv
->phydev
, rq
, cmd
);
822 static struct enet_cb
*bcmgenet_get_txcb(struct bcmgenet_priv
*priv
,
823 struct bcmgenet_tx_ring
*ring
)
825 struct enet_cb
*tx_cb_ptr
;
827 tx_cb_ptr
= ring
->cbs
;
828 tx_cb_ptr
+= ring
->write_ptr
- ring
->cb_ptr
;
829 tx_cb_ptr
->bd_addr
= priv
->tx_bds
+ ring
->write_ptr
* DMA_DESC_SIZE
;
830 /* Advancing local write pointer */
831 if (ring
->write_ptr
== ring
->end_ptr
)
832 ring
->write_ptr
= ring
->cb_ptr
;
839 /* Simple helper to free a control block's resources */
840 static void bcmgenet_free_cb(struct enet_cb
*cb
)
842 dev_kfree_skb_any(cb
->skb
);
844 dma_unmap_addr_set(cb
, dma_addr
, 0);
847 static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_priv
*priv
,
848 struct bcmgenet_tx_ring
*ring
)
850 bcmgenet_intrl2_0_writel(priv
,
851 UMAC_IRQ_TXDMA_BDONE
| UMAC_IRQ_TXDMA_PDONE
,
852 INTRL2_CPU_MASK_SET
);
855 static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_priv
*priv
,
856 struct bcmgenet_tx_ring
*ring
)
858 bcmgenet_intrl2_0_writel(priv
,
859 UMAC_IRQ_TXDMA_BDONE
| UMAC_IRQ_TXDMA_PDONE
,
860 INTRL2_CPU_MASK_CLEAR
);
863 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_priv
*priv
,
864 struct bcmgenet_tx_ring
*ring
)
866 bcmgenet_intrl2_1_writel(priv
,
867 (1 << ring
->index
), INTRL2_CPU_MASK_CLEAR
);
868 priv
->int1_mask
&= ~(1 << ring
->index
);
871 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_priv
*priv
,
872 struct bcmgenet_tx_ring
*ring
)
874 bcmgenet_intrl2_1_writel(priv
,
875 (1 << ring
->index
), INTRL2_CPU_MASK_SET
);
876 priv
->int1_mask
|= (1 << ring
->index
);
879 /* Unlocked version of the reclaim routine */
880 static void __bcmgenet_tx_reclaim(struct net_device
*dev
,
881 struct bcmgenet_tx_ring
*ring
)
883 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
884 int last_tx_cn
, last_c_index
, num_tx_bds
;
885 struct enet_cb
*tx_cb_ptr
;
886 struct netdev_queue
*txq
;
887 unsigned int c_index
;
889 /* Compute how many buffers are transmited since last xmit call */
890 c_index
= bcmgenet_tdma_ring_readl(priv
, ring
->index
, TDMA_CONS_INDEX
);
891 txq
= netdev_get_tx_queue(dev
, ring
->queue
);
893 last_c_index
= ring
->c_index
;
894 num_tx_bds
= ring
->size
;
896 c_index
&= (num_tx_bds
- 1);
898 if (c_index
>= last_c_index
)
899 last_tx_cn
= c_index
- last_c_index
;
901 last_tx_cn
= num_tx_bds
- last_c_index
+ c_index
;
903 netif_dbg(priv
, tx_done
, dev
,
904 "%s ring=%d index=%d last_tx_cn=%d last_index=%d\n",
905 __func__
, ring
->index
,
906 c_index
, last_tx_cn
, last_c_index
);
908 /* Reclaim transmitted buffers */
909 while (last_tx_cn
-- > 0) {
910 tx_cb_ptr
= ring
->cbs
+ last_c_index
;
911 if (tx_cb_ptr
->skb
) {
912 dev
->stats
.tx_bytes
+= tx_cb_ptr
->skb
->len
;
913 dma_unmap_single(&dev
->dev
,
914 dma_unmap_addr(tx_cb_ptr
, dma_addr
),
917 bcmgenet_free_cb(tx_cb_ptr
);
918 } else if (dma_unmap_addr(tx_cb_ptr
, dma_addr
)) {
919 dev
->stats
.tx_bytes
+=
920 dma_unmap_len(tx_cb_ptr
, dma_len
);
921 dma_unmap_page(&dev
->dev
,
922 dma_unmap_addr(tx_cb_ptr
, dma_addr
),
923 dma_unmap_len(tx_cb_ptr
, dma_len
),
925 dma_unmap_addr_set(tx_cb_ptr
, dma_addr
, 0);
927 dev
->stats
.tx_packets
++;
931 last_c_index
&= (num_tx_bds
- 1);
934 if (ring
->free_bds
> (MAX_SKB_FRAGS
+ 1))
935 ring
->int_disable(priv
, ring
);
937 if (netif_tx_queue_stopped(txq
))
938 netif_tx_wake_queue(txq
);
940 ring
->c_index
= c_index
;
943 static void bcmgenet_tx_reclaim(struct net_device
*dev
,
944 struct bcmgenet_tx_ring
*ring
)
948 spin_lock_irqsave(&ring
->lock
, flags
);
949 __bcmgenet_tx_reclaim(dev
, ring
);
950 spin_unlock_irqrestore(&ring
->lock
, flags
);
953 static void bcmgenet_tx_reclaim_all(struct net_device
*dev
)
955 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
958 if (netif_is_multiqueue(dev
)) {
959 for (i
= 0; i
< priv
->hw_params
->tx_queues
; i
++)
960 bcmgenet_tx_reclaim(dev
, &priv
->tx_rings
[i
]);
963 bcmgenet_tx_reclaim(dev
, &priv
->tx_rings
[DESC_INDEX
]);
966 /* Transmits a single SKB (either head of a fragment or a single SKB)
967 * caller must hold priv->lock
969 static int bcmgenet_xmit_single(struct net_device
*dev
,
972 struct bcmgenet_tx_ring
*ring
)
974 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
975 struct device
*kdev
= &priv
->pdev
->dev
;
976 struct enet_cb
*tx_cb_ptr
;
977 unsigned int skb_len
;
982 tx_cb_ptr
= bcmgenet_get_txcb(priv
, ring
);
984 if (unlikely(!tx_cb_ptr
))
987 tx_cb_ptr
->skb
= skb
;
989 skb_len
= skb_headlen(skb
) < ETH_ZLEN
? ETH_ZLEN
: skb_headlen(skb
);
991 mapping
= dma_map_single(kdev
, skb
->data
, skb_len
, DMA_TO_DEVICE
);
992 ret
= dma_mapping_error(kdev
, mapping
);
994 netif_err(priv
, tx_err
, dev
, "Tx DMA map failed\n");
999 dma_unmap_addr_set(tx_cb_ptr
, dma_addr
, mapping
);
1000 dma_unmap_len_set(tx_cb_ptr
, dma_len
, skb
->len
);
1001 length_status
= (skb_len
<< DMA_BUFLENGTH_SHIFT
) | dma_desc_flags
|
1002 (priv
->hw_params
->qtag_mask
<< DMA_TX_QTAG_SHIFT
) |
1005 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
1006 length_status
|= DMA_TX_DO_CSUM
;
1008 dmadesc_set(priv
, tx_cb_ptr
->bd_addr
, mapping
, length_status
);
1010 /* Decrement total BD count and advance our write pointer */
1011 ring
->free_bds
-= 1;
1012 ring
->prod_index
+= 1;
1013 ring
->prod_index
&= DMA_P_INDEX_MASK
;
1018 /* Transmit a SKB fragement */
1019 static int bcmgenet_xmit_frag(struct net_device
*dev
,
1022 struct bcmgenet_tx_ring
*ring
)
1024 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
1025 struct device
*kdev
= &priv
->pdev
->dev
;
1026 struct enet_cb
*tx_cb_ptr
;
1030 tx_cb_ptr
= bcmgenet_get_txcb(priv
, ring
);
1032 if (unlikely(!tx_cb_ptr
))
1034 tx_cb_ptr
->skb
= NULL
;
1036 mapping
= skb_frag_dma_map(kdev
, frag
, 0,
1037 skb_frag_size(frag
), DMA_TO_DEVICE
);
1038 ret
= dma_mapping_error(kdev
, mapping
);
1040 netif_err(priv
, tx_err
, dev
, "%s: Tx DMA map failed\n",
1045 dma_unmap_addr_set(tx_cb_ptr
, dma_addr
, mapping
);
1046 dma_unmap_len_set(tx_cb_ptr
, dma_len
, frag
->size
);
1048 dmadesc_set(priv
, tx_cb_ptr
->bd_addr
, mapping
,
1049 (frag
->size
<< DMA_BUFLENGTH_SHIFT
) | dma_desc_flags
|
1050 (priv
->hw_params
->qtag_mask
<< DMA_TX_QTAG_SHIFT
));
1053 ring
->free_bds
-= 1;
1054 ring
->prod_index
+= 1;
1055 ring
->prod_index
&= DMA_P_INDEX_MASK
;
1060 /* Reallocate the SKB to put enough headroom in front of it and insert
1061 * the transmit checksum offsets in the descriptors
1063 static int bcmgenet_put_tx_csum(struct net_device
*dev
, struct sk_buff
*skb
)
1065 struct status_64
*status
= NULL
;
1066 struct sk_buff
*new_skb
;
1072 if (unlikely(skb_headroom(skb
) < sizeof(*status
))) {
1073 /* If 64 byte status block enabled, must make sure skb has
1074 * enough headroom for us to insert 64B status block.
1076 new_skb
= skb_realloc_headroom(skb
, sizeof(*status
));
1079 dev
->stats
.tx_errors
++;
1080 dev
->stats
.tx_dropped
++;
1086 skb_push(skb
, sizeof(*status
));
1087 status
= (struct status_64
*)skb
->data
;
1089 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
1090 ip_ver
= htons(skb
->protocol
);
1093 ip_proto
= ip_hdr(skb
)->protocol
;
1096 ip_proto
= ipv6_hdr(skb
)->nexthdr
;
1102 offset
= skb_checksum_start_offset(skb
) - sizeof(*status
);
1103 tx_csum_info
= (offset
<< STATUS_TX_CSUM_START_SHIFT
) |
1104 (offset
+ skb
->csum_offset
);
1106 /* Set the length valid bit for TCP and UDP and just set
1107 * the special UDP flag for IPv4, else just set to 0.
1109 if (ip_proto
== IPPROTO_TCP
|| ip_proto
== IPPROTO_UDP
) {
1110 tx_csum_info
|= STATUS_TX_CSUM_LV
;
1111 if (ip_proto
== IPPROTO_UDP
&& ip_ver
== ETH_P_IP
)
1112 tx_csum_info
|= STATUS_TX_CSUM_PROTO_UDP
;
1116 status
->tx_csum_info
= tx_csum_info
;
1122 static netdev_tx_t
bcmgenet_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1124 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
1125 struct bcmgenet_tx_ring
*ring
= NULL
;
1126 struct netdev_queue
*txq
;
1127 unsigned long flags
= 0;
1128 int nr_frags
, index
;
1133 index
= skb_get_queue_mapping(skb
);
1134 /* Mapping strategy:
1135 * queue_mapping = 0, unclassified, packet xmited through ring16
1136 * queue_mapping = 1, goes to ring 0. (highest priority queue
1137 * queue_mapping = 2, goes to ring 1.
1138 * queue_mapping = 3, goes to ring 2.
1139 * queue_mapping = 4, goes to ring 3.
1146 nr_frags
= skb_shinfo(skb
)->nr_frags
;
1147 ring
= &priv
->tx_rings
[index
];
1148 txq
= netdev_get_tx_queue(dev
, ring
->queue
);
1150 spin_lock_irqsave(&ring
->lock
, flags
);
1151 if (ring
->free_bds
<= nr_frags
+ 1) {
1152 netif_tx_stop_queue(txq
);
1153 netdev_err(dev
, "%s: tx ring %d full when queue %d awake\n",
1154 __func__
, index
, ring
->queue
);
1155 ret
= NETDEV_TX_BUSY
;
1159 /* set the SKB transmit checksum */
1160 if (priv
->desc_64b_en
) {
1161 ret
= bcmgenet_put_tx_csum(dev
, skb
);
1168 dma_desc_flags
= DMA_SOP
;
1170 dma_desc_flags
|= DMA_EOP
;
1172 /* Transmit single SKB or head of fragment list */
1173 ret
= bcmgenet_xmit_single(dev
, skb
, dma_desc_flags
, ring
);
1180 for (i
= 0; i
< nr_frags
; i
++) {
1181 ret
= bcmgenet_xmit_frag(dev
,
1182 &skb_shinfo(skb
)->frags
[i
],
1183 (i
== nr_frags
- 1) ? DMA_EOP
: 0, ring
);
1190 skb_tx_timestamp(skb
);
1192 /* we kept a software copy of how much we should advance the TDMA
1193 * producer index, now write it down to the hardware
1195 bcmgenet_tdma_ring_writel(priv
, ring
->index
,
1196 ring
->prod_index
, TDMA_PROD_INDEX
);
1198 if (ring
->free_bds
<= (MAX_SKB_FRAGS
+ 1)) {
1199 netif_tx_stop_queue(txq
);
1200 ring
->int_enable(priv
, ring
);
1204 spin_unlock_irqrestore(&ring
->lock
, flags
);
1210 static int bcmgenet_rx_refill(struct bcmgenet_priv
*priv
,
1213 struct device
*kdev
= &priv
->pdev
->dev
;
1214 struct sk_buff
*skb
;
1218 skb
= netdev_alloc_skb(priv
->dev
,
1219 priv
->rx_buf_len
+ SKB_ALIGNMENT
);
1223 /* a caller did not release this control block */
1224 WARN_ON(cb
->skb
!= NULL
);
1226 mapping
= dma_map_single(kdev
, skb
->data
,
1227 priv
->rx_buf_len
, DMA_FROM_DEVICE
);
1228 ret
= dma_mapping_error(kdev
, mapping
);
1230 bcmgenet_free_cb(cb
);
1231 netif_err(priv
, rx_err
, priv
->dev
,
1232 "%s DMA map failed\n", __func__
);
1236 dma_unmap_addr_set(cb
, dma_addr
, mapping
);
1237 /* assign packet, prepare descriptor, and advance pointer */
1239 dmadesc_set_addr(priv
, priv
->rx_bd_assign_ptr
, mapping
);
1241 /* turn on the newly assigned BD for DMA to use */
1242 priv
->rx_bd_assign_index
++;
1243 priv
->rx_bd_assign_index
&= (priv
->num_rx_bds
- 1);
1245 priv
->rx_bd_assign_ptr
= priv
->rx_bds
+
1246 (priv
->rx_bd_assign_index
* DMA_DESC_SIZE
);
1251 /* bcmgenet_desc_rx - descriptor based rx process.
1252 * this could be called from bottom half, or from NAPI polling method.
1254 static unsigned int bcmgenet_desc_rx(struct bcmgenet_priv
*priv
,
1255 unsigned int budget
)
1257 struct net_device
*dev
= priv
->dev
;
1259 struct sk_buff
*skb
;
1260 u32 dma_length_status
;
1261 unsigned long dma_flag
;
1263 unsigned int rxpktprocessed
= 0, rxpkttoprocess
;
1264 unsigned int p_index
;
1265 unsigned int chksum_ok
= 0;
1267 p_index
= bcmgenet_rdma_ring_readl(priv
,
1268 DESC_INDEX
, RDMA_PROD_INDEX
);
1269 p_index
&= DMA_P_INDEX_MASK
;
1271 if (p_index
< priv
->rx_c_index
)
1272 rxpkttoprocess
= (DMA_C_INDEX_MASK
+ 1) -
1273 priv
->rx_c_index
+ p_index
;
1275 rxpkttoprocess
= p_index
- priv
->rx_c_index
;
1277 netif_dbg(priv
, rx_status
, dev
,
1278 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess
);
1280 while ((rxpktprocessed
< rxpkttoprocess
) &&
1281 (rxpktprocessed
< budget
)) {
1283 /* Unmap the packet contents such that we can use the
1284 * RSV from the 64 bytes descriptor when enabled and save
1285 * a 32-bits register read
1287 cb
= &priv
->rx_cbs
[priv
->rx_read_ptr
];
1289 dma_unmap_single(&dev
->dev
, dma_unmap_addr(cb
, dma_addr
),
1290 priv
->rx_buf_len
, DMA_FROM_DEVICE
);
1292 if (!priv
->desc_64b_en
) {
1293 dma_length_status
= dmadesc_get_length_status(priv
,
1295 (priv
->rx_read_ptr
*
1298 struct status_64
*status
;
1299 status
= (struct status_64
*)skb
->data
;
1300 dma_length_status
= status
->length_status
;
1303 /* DMA flags and length are still valid no matter how
1304 * we got the Receive Status Vector (64B RSB or register)
1306 dma_flag
= dma_length_status
& 0xffff;
1307 len
= dma_length_status
>> DMA_BUFLENGTH_SHIFT
;
1309 netif_dbg(priv
, rx_status
, dev
,
1310 "%s: p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
1311 __func__
, p_index
, priv
->rx_c_index
, priv
->rx_read_ptr
,
1316 priv
->rx_read_ptr
++;
1317 priv
->rx_read_ptr
&= (priv
->num_rx_bds
- 1);
1319 /* out of memory, just drop packets at the hardware level */
1320 if (unlikely(!skb
)) {
1321 dev
->stats
.rx_dropped
++;
1322 dev
->stats
.rx_errors
++;
1326 if (unlikely(!(dma_flag
& DMA_EOP
) || !(dma_flag
& DMA_SOP
))) {
1327 netif_err(priv
, rx_status
, dev
,
1328 "Droping fragmented packet!\n");
1329 dev
->stats
.rx_dropped
++;
1330 dev
->stats
.rx_errors
++;
1331 dev_kfree_skb_any(cb
->skb
);
1336 if (unlikely(dma_flag
& (DMA_RX_CRC_ERROR
|
1341 netif_err(priv
, rx_status
, dev
, "dma_flag=0x%x\n",
1342 (unsigned int)dma_flag
);
1343 if (dma_flag
& DMA_RX_CRC_ERROR
)
1344 dev
->stats
.rx_crc_errors
++;
1345 if (dma_flag
& DMA_RX_OV
)
1346 dev
->stats
.rx_over_errors
++;
1347 if (dma_flag
& DMA_RX_NO
)
1348 dev
->stats
.rx_frame_errors
++;
1349 if (dma_flag
& DMA_RX_LG
)
1350 dev
->stats
.rx_length_errors
++;
1351 dev
->stats
.rx_dropped
++;
1352 dev
->stats
.rx_errors
++;
1354 /* discard the packet and advance consumer index.*/
1355 dev_kfree_skb_any(cb
->skb
);
1358 } /* error packet */
1360 chksum_ok
= (dma_flag
& priv
->dma_rx_chk_bit
) &&
1361 priv
->desc_rxchk_en
;
1364 if (priv
->desc_64b_en
) {
1369 if (likely(chksum_ok
))
1370 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1372 /* remove hardware 2bytes added for IP alignment */
1376 if (priv
->crc_fwd_en
) {
1377 skb_trim(skb
, len
- ETH_FCS_LEN
);
1381 /*Finish setting up the received SKB and send it to the kernel*/
1382 skb
->protocol
= eth_type_trans(skb
, priv
->dev
);
1383 dev
->stats
.rx_packets
++;
1384 dev
->stats
.rx_bytes
+= len
;
1385 if (dma_flag
& DMA_RX_MULT
)
1386 dev
->stats
.multicast
++;
1389 napi_gro_receive(&priv
->napi
, skb
);
1391 netif_dbg(priv
, rx_status
, dev
, "pushed up to kernel\n");
1393 /* refill RX path on the current control block */
1395 err
= bcmgenet_rx_refill(priv
, cb
);
1397 netif_err(priv
, rx_err
, dev
, "Rx refill failed\n");
1400 return rxpktprocessed
;
1403 /* Assign skb to RX DMA descriptor. */
1404 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv
*priv
)
1410 netif_dbg(priv
, hw
, priv
->dev
, "%s:\n", __func__
);
1412 /* loop here for each buffer needing assign */
1413 for (i
= 0; i
< priv
->num_rx_bds
; i
++) {
1414 cb
= &priv
->rx_cbs
[priv
->rx_bd_assign_index
];
1418 ret
= bcmgenet_rx_refill(priv
, cb
);
1427 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv
*priv
)
1432 for (i
= 0; i
< priv
->num_rx_bds
; i
++) {
1433 cb
= &priv
->rx_cbs
[i
];
1435 if (dma_unmap_addr(cb
, dma_addr
)) {
1436 dma_unmap_single(&priv
->dev
->dev
,
1437 dma_unmap_addr(cb
, dma_addr
),
1438 priv
->rx_buf_len
, DMA_FROM_DEVICE
);
1439 dma_unmap_addr_set(cb
, dma_addr
, 0);
1443 bcmgenet_free_cb(cb
);
1447 static void umac_enable_set(struct bcmgenet_priv
*priv
, u32 mask
,
1452 reg
= bcmgenet_umac_readl(priv
, UMAC_CMD
);
1457 bcmgenet_umac_writel(priv
, reg
, UMAC_CMD
);
1459 /* UniMAC stops on a packet boundary, wait for a full-size packet
1463 usleep_range(1000, 2000);
1466 static int reset_umac(struct bcmgenet_priv
*priv
)
1468 struct device
*kdev
= &priv
->pdev
->dev
;
1469 unsigned int timeout
= 0;
1472 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1473 bcmgenet_rbuf_ctrl_set(priv
, 0);
1476 /* disable MAC while updating its registers */
1477 bcmgenet_umac_writel(priv
, 0, UMAC_CMD
);
1479 /* issue soft reset, wait for it to complete */
1480 bcmgenet_umac_writel(priv
, CMD_SW_RESET
, UMAC_CMD
);
1481 while (timeout
++ < 1000) {
1482 reg
= bcmgenet_umac_readl(priv
, UMAC_CMD
);
1483 if (!(reg
& CMD_SW_RESET
))
1489 if (timeout
== 1000) {
1491 "timeout waiting for MAC to come out of resetn\n");
1498 static void bcmgenet_intr_disable(struct bcmgenet_priv
*priv
)
1500 /* Mask all interrupts.*/
1501 bcmgenet_intrl2_0_writel(priv
, 0xFFFFFFFF, INTRL2_CPU_MASK_SET
);
1502 bcmgenet_intrl2_0_writel(priv
, 0xFFFFFFFF, INTRL2_CPU_CLEAR
);
1503 bcmgenet_intrl2_0_writel(priv
, 0, INTRL2_CPU_MASK_CLEAR
);
1504 bcmgenet_intrl2_1_writel(priv
, 0xFFFFFFFF, INTRL2_CPU_MASK_SET
);
1505 bcmgenet_intrl2_1_writel(priv
, 0xFFFFFFFF, INTRL2_CPU_CLEAR
);
1506 bcmgenet_intrl2_1_writel(priv
, 0, INTRL2_CPU_MASK_CLEAR
);
1509 static int init_umac(struct bcmgenet_priv
*priv
)
1511 struct device
*kdev
= &priv
->pdev
->dev
;
1513 u32 reg
, cpu_mask_clear
;
1515 dev_dbg(&priv
->pdev
->dev
, "bcmgenet: init_umac\n");
1517 ret
= reset_umac(priv
);
1521 bcmgenet_umac_writel(priv
, 0, UMAC_CMD
);
1522 /* clear tx/rx counter */
1523 bcmgenet_umac_writel(priv
,
1524 MIB_RESET_RX
| MIB_RESET_TX
| MIB_RESET_RUNT
, UMAC_MIB_CTRL
);
1525 bcmgenet_umac_writel(priv
, 0, UMAC_MIB_CTRL
);
1527 bcmgenet_umac_writel(priv
, ENET_MAX_MTU_SIZE
, UMAC_MAX_FRAME_LEN
);
1529 /* init rx registers, enable ip header optimization */
1530 reg
= bcmgenet_rbuf_readl(priv
, RBUF_CTRL
);
1531 reg
|= RBUF_ALIGN_2B
;
1532 bcmgenet_rbuf_writel(priv
, reg
, RBUF_CTRL
);
1534 if (!GENET_IS_V1(priv
) && !GENET_IS_V2(priv
))
1535 bcmgenet_rbuf_writel(priv
, 1, RBUF_TBUF_SIZE_CTRL
);
1537 bcmgenet_intr_disable(priv
);
1539 cpu_mask_clear
= UMAC_IRQ_RXDMA_BDONE
;
1541 dev_dbg(kdev
, "%s:Enabling RXDMA_BDONE interrupt\n", __func__
);
1543 /* Monitor cable plug/unpluged event for internal PHY */
1544 if (phy_is_internal(priv
->phydev
))
1545 cpu_mask_clear
|= (UMAC_IRQ_LINK_DOWN
| UMAC_IRQ_LINK_UP
);
1546 else if (priv
->ext_phy
)
1547 cpu_mask_clear
|= (UMAC_IRQ_LINK_DOWN
| UMAC_IRQ_LINK_UP
);
1548 else if (priv
->phy_interface
== PHY_INTERFACE_MODE_MOCA
) {
1549 reg
= bcmgenet_bp_mc_get(priv
);
1550 reg
|= BIT(priv
->hw_params
->bp_in_en_shift
);
1552 /* bp_mask: back pressure mask */
1553 if (netif_is_multiqueue(priv
->dev
))
1554 reg
|= priv
->hw_params
->bp_in_mask
;
1556 reg
&= ~priv
->hw_params
->bp_in_mask
;
1557 bcmgenet_bp_mc_set(priv
, reg
);
1560 /* Enable MDIO interrupts on GENET v3+ */
1561 if (priv
->hw_params
->flags
& GENET_HAS_MDIO_INTR
)
1562 cpu_mask_clear
|= UMAC_IRQ_MDIO_DONE
| UMAC_IRQ_MDIO_ERROR
;
1564 bcmgenet_intrl2_0_writel(priv
, cpu_mask_clear
,
1565 INTRL2_CPU_MASK_CLEAR
);
1567 /* Enable rx/tx engine.*/
1568 dev_dbg(kdev
, "done init umac\n");
1573 /* Initialize all house-keeping variables for a TX ring, along
1574 * with corresponding hardware registers
1576 static void bcmgenet_init_tx_ring(struct bcmgenet_priv
*priv
,
1577 unsigned int index
, unsigned int size
,
1578 unsigned int write_ptr
, unsigned int end_ptr
)
1580 struct bcmgenet_tx_ring
*ring
= &priv
->tx_rings
[index
];
1581 u32 words_per_bd
= WORDS_PER_BD(priv
);
1582 u32 flow_period_val
= 0;
1583 unsigned int first_bd
;
1585 spin_lock_init(&ring
->lock
);
1586 ring
->index
= index
;
1587 if (index
== DESC_INDEX
) {
1589 ring
->int_enable
= bcmgenet_tx_ring16_int_enable
;
1590 ring
->int_disable
= bcmgenet_tx_ring16_int_disable
;
1592 ring
->queue
= index
+ 1;
1593 ring
->int_enable
= bcmgenet_tx_ring_int_enable
;
1594 ring
->int_disable
= bcmgenet_tx_ring_int_disable
;
1596 ring
->cbs
= priv
->tx_cbs
+ write_ptr
;
1599 ring
->free_bds
= size
;
1600 ring
->write_ptr
= write_ptr
;
1601 ring
->cb_ptr
= write_ptr
;
1602 ring
->end_ptr
= end_ptr
- 1;
1603 ring
->prod_index
= 0;
1605 /* Set flow period for ring != 16 */
1606 if (index
!= DESC_INDEX
)
1607 flow_period_val
= ENET_MAX_MTU_SIZE
<< 16;
1609 bcmgenet_tdma_ring_writel(priv
, index
, 0, TDMA_PROD_INDEX
);
1610 bcmgenet_tdma_ring_writel(priv
, index
, 0, TDMA_CONS_INDEX
);
1611 bcmgenet_tdma_ring_writel(priv
, index
, 1, DMA_MBUF_DONE_THRESH
);
1612 /* Disable rate control for now */
1613 bcmgenet_tdma_ring_writel(priv
, index
, flow_period_val
,
1615 /* Unclassified traffic goes to ring 16 */
1616 bcmgenet_tdma_ring_writel(priv
, index
,
1617 ((size
<< DMA_RING_SIZE_SHIFT
) | RX_BUF_LENGTH
),
1620 first_bd
= write_ptr
;
1622 /* Set start and end address, read and write pointers */
1623 bcmgenet_tdma_ring_writel(priv
, index
, first_bd
* words_per_bd
,
1625 bcmgenet_tdma_ring_writel(priv
, index
, first_bd
* words_per_bd
,
1627 bcmgenet_tdma_ring_writel(priv
, index
, first_bd
,
1629 bcmgenet_tdma_ring_writel(priv
, index
, end_ptr
* words_per_bd
- 1,
1633 /* Initialize a RDMA ring */
1634 static int bcmgenet_init_rx_ring(struct bcmgenet_priv
*priv
,
1635 unsigned int index
, unsigned int size
)
1637 u32 words_per_bd
= WORDS_PER_BD(priv
);
1640 priv
->num_rx_bds
= TOTAL_DESC
;
1641 priv
->rx_bds
= priv
->base
+ priv
->hw_params
->rdma_offset
;
1642 priv
->rx_bd_assign_ptr
= priv
->rx_bds
;
1643 priv
->rx_bd_assign_index
= 0;
1644 priv
->rx_c_index
= 0;
1645 priv
->rx_read_ptr
= 0;
1646 priv
->rx_cbs
= kzalloc(priv
->num_rx_bds
* sizeof(struct enet_cb
),
1651 ret
= bcmgenet_alloc_rx_buffers(priv
);
1653 kfree(priv
->rx_cbs
);
1657 bcmgenet_rdma_ring_writel(priv
, index
, 0, RDMA_WRITE_PTR
);
1658 bcmgenet_rdma_ring_writel(priv
, index
, 0, RDMA_PROD_INDEX
);
1659 bcmgenet_rdma_ring_writel(priv
, index
, 0, RDMA_CONS_INDEX
);
1660 bcmgenet_rdma_ring_writel(priv
, index
,
1661 ((size
<< DMA_RING_SIZE_SHIFT
) | RX_BUF_LENGTH
),
1663 bcmgenet_rdma_ring_writel(priv
, index
, 0, DMA_START_ADDR
);
1664 bcmgenet_rdma_ring_writel(priv
, index
,
1665 words_per_bd
* size
- 1, DMA_END_ADDR
);
1666 bcmgenet_rdma_ring_writel(priv
, index
,
1667 (DMA_FC_THRESH_LO
<< DMA_XOFF_THRESHOLD_SHIFT
) |
1668 DMA_FC_THRESH_HI
, RDMA_XON_XOFF_THRESH
);
1669 bcmgenet_rdma_ring_writel(priv
, index
, 0, RDMA_READ_PTR
);
1674 /* init multi xmit queues, only available for GENET2+
1675 * the queue is partitioned as follows:
1677 * queue 0 - 3 is priority based, each one has 32 descriptors,
1678 * with queue 0 being the highest priority queue.
1680 * queue 16 is the default tx queue with GENET_DEFAULT_BD_CNT
1681 * descriptors: 256 - (number of tx queues * bds per queues) = 128
1684 * The transmit control block pool is then partitioned as following:
1685 * - tx_cbs[0...127] are for queue 16
1686 * - tx_ring_cbs[0] points to tx_cbs[128..159]
1687 * - tx_ring_cbs[1] points to tx_cbs[160..191]
1688 * - tx_ring_cbs[2] points to tx_cbs[192..223]
1689 * - tx_ring_cbs[3] points to tx_cbs[224..255]
1691 static void bcmgenet_init_multiq(struct net_device
*dev
)
1693 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
1694 unsigned int i
, dma_enable
;
1695 u32 reg
, dma_ctrl
, ring_cfg
= 0, dma_priority
= 0;
1697 if (!netif_is_multiqueue(dev
)) {
1698 netdev_warn(dev
, "called with non multi queue aware HW\n");
1702 dma_ctrl
= bcmgenet_tdma_readl(priv
, DMA_CTRL
);
1703 dma_enable
= dma_ctrl
& DMA_EN
;
1704 dma_ctrl
&= ~DMA_EN
;
1705 bcmgenet_tdma_writel(priv
, dma_ctrl
, DMA_CTRL
);
1707 /* Enable strict priority arbiter mode */
1708 bcmgenet_tdma_writel(priv
, DMA_ARBITER_SP
, DMA_ARB_CTRL
);
1710 for (i
= 0; i
< priv
->hw_params
->tx_queues
; i
++) {
1711 /* first 64 tx_cbs are reserved for default tx queue
1714 bcmgenet_init_tx_ring(priv
, i
, priv
->hw_params
->bds_cnt
,
1715 i
* priv
->hw_params
->bds_cnt
,
1716 (i
+ 1) * priv
->hw_params
->bds_cnt
);
1718 /* Configure ring as decriptor ring and setup priority */
1720 dma_priority
|= ((GENET_Q0_PRIORITY
+ i
) <<
1721 (GENET_MAX_MQ_CNT
+ 1) * i
);
1722 dma_ctrl
|= 1 << (i
+ DMA_RING_BUF_EN_SHIFT
);
1726 reg
= bcmgenet_tdma_readl(priv
, DMA_RING_CFG
);
1728 bcmgenet_tdma_writel(priv
, reg
, DMA_RING_CFG
);
1730 /* Use configured rings priority and set ring #16 priority */
1731 reg
= bcmgenet_tdma_readl(priv
, DMA_RING_PRIORITY
);
1732 reg
|= ((GENET_Q0_PRIORITY
+ priv
->hw_params
->tx_queues
) << 20);
1733 reg
|= dma_priority
;
1734 bcmgenet_tdma_writel(priv
, reg
, DMA_PRIORITY
);
1736 /* Configure ring as descriptor ring and re-enable DMA if enabled */
1737 reg
= bcmgenet_tdma_readl(priv
, DMA_CTRL
);
1741 bcmgenet_tdma_writel(priv
, reg
, DMA_CTRL
);
1744 static void bcmgenet_fini_dma(struct bcmgenet_priv
*priv
)
1749 bcmgenet_rdma_writel(priv
, 0, DMA_CTRL
);
1750 bcmgenet_tdma_writel(priv
, 0, DMA_CTRL
);
1752 for (i
= 0; i
< priv
->num_tx_bds
; i
++) {
1753 if (priv
->tx_cbs
[i
].skb
!= NULL
) {
1754 dev_kfree_skb(priv
->tx_cbs
[i
].skb
);
1755 priv
->tx_cbs
[i
].skb
= NULL
;
1759 bcmgenet_free_rx_buffers(priv
);
1760 kfree(priv
->rx_cbs
);
1761 kfree(priv
->tx_cbs
);
1764 /* init_edma: Initialize DMA control register */
1765 static int bcmgenet_init_dma(struct bcmgenet_priv
*priv
)
1769 netif_dbg(priv
, hw
, priv
->dev
, "bcmgenet: init_edma\n");
1771 /* by default, enable ring 16 (descriptor based) */
1772 ret
= bcmgenet_init_rx_ring(priv
, DESC_INDEX
, TOTAL_DESC
);
1774 netdev_err(priv
->dev
, "failed to initialize RX ring\n");
1779 bcmgenet_rdma_writel(priv
, DMA_MAX_BURST_LENGTH
, DMA_SCB_BURST_SIZE
);
1782 bcmgenet_tdma_writel(priv
, DMA_MAX_BURST_LENGTH
, DMA_SCB_BURST_SIZE
);
1784 /* Initialize commont TX ring structures */
1785 priv
->tx_bds
= priv
->base
+ priv
->hw_params
->tdma_offset
;
1786 priv
->num_tx_bds
= TOTAL_DESC
;
1787 priv
->tx_cbs
= kzalloc(priv
->num_tx_bds
* sizeof(struct enet_cb
),
1789 if (!priv
->tx_cbs
) {
1790 bcmgenet_fini_dma(priv
);
1794 /* initialize multi xmit queue */
1795 bcmgenet_init_multiq(priv
->dev
);
1797 /* initialize special ring 16 */
1798 bcmgenet_init_tx_ring(priv
, DESC_INDEX
, GENET_DEFAULT_BD_CNT
,
1799 priv
->hw_params
->tx_queues
* priv
->hw_params
->bds_cnt
,
1805 /* NAPI polling method*/
1806 static int bcmgenet_poll(struct napi_struct
*napi
, int budget
)
1808 struct bcmgenet_priv
*priv
= container_of(napi
,
1809 struct bcmgenet_priv
, napi
);
1810 unsigned int work_done
;
1813 bcmgenet_tx_reclaim(priv
->dev
, &priv
->tx_rings
[DESC_INDEX
]);
1815 work_done
= bcmgenet_desc_rx(priv
, budget
);
1817 /* Advancing our consumer index*/
1818 priv
->rx_c_index
+= work_done
;
1819 priv
->rx_c_index
&= DMA_C_INDEX_MASK
;
1820 bcmgenet_rdma_ring_writel(priv
, DESC_INDEX
,
1821 priv
->rx_c_index
, RDMA_CONS_INDEX
);
1822 if (work_done
< budget
) {
1823 napi_complete(napi
);
1824 bcmgenet_intrl2_0_writel(priv
,
1825 UMAC_IRQ_RXDMA_BDONE
, INTRL2_CPU_MASK_CLEAR
);
1831 /* Interrupt bottom half */
1832 static void bcmgenet_irq_task(struct work_struct
*work
)
1834 struct bcmgenet_priv
*priv
= container_of(
1835 work
, struct bcmgenet_priv
, bcmgenet_irq_work
);
1837 netif_dbg(priv
, intr
, priv
->dev
, "%s\n", __func__
);
1839 if (priv
->irq0_stat
& UMAC_IRQ_MPD_R
) {
1840 priv
->irq0_stat
&= ~UMAC_IRQ_MPD_R
;
1841 netif_dbg(priv
, wol
, priv
->dev
,
1842 "magic packet detected, waking up\n");
1843 bcmgenet_power_up(priv
, GENET_POWER_WOL_MAGIC
);
1846 /* Link UP/DOWN event */
1847 if ((priv
->hw_params
->flags
& GENET_HAS_MDIO_INTR
) &&
1848 (priv
->irq0_stat
& (UMAC_IRQ_LINK_UP
|UMAC_IRQ_LINK_DOWN
))) {
1849 phy_mac_interrupt(priv
->phydev
,
1850 priv
->irq0_stat
& UMAC_IRQ_LINK_UP
);
1851 priv
->irq0_stat
&= ~(UMAC_IRQ_LINK_UP
|UMAC_IRQ_LINK_DOWN
);
1855 /* bcmgenet_isr1: interrupt handler for ring buffer. */
1856 static irqreturn_t
bcmgenet_isr1(int irq
, void *dev_id
)
1858 struct bcmgenet_priv
*priv
= dev_id
;
1861 /* Save irq status for bottom-half processing. */
1863 bcmgenet_intrl2_1_readl(priv
, INTRL2_CPU_STAT
) &
1865 /* clear inerrupts*/
1866 bcmgenet_intrl2_1_writel(priv
, priv
->irq1_stat
, INTRL2_CPU_CLEAR
);
1868 netif_dbg(priv
, intr
, priv
->dev
,
1869 "%s: IRQ=0x%x\n", __func__
, priv
->irq1_stat
);
1870 /* Check the MBDONE interrupts.
1871 * packet is done, reclaim descriptors
1873 if (priv
->irq1_stat
& 0x0000ffff) {
1875 for (index
= 0; index
< 16; index
++) {
1876 if (priv
->irq1_stat
& (1 << index
))
1877 bcmgenet_tx_reclaim(priv
->dev
,
1878 &priv
->tx_rings
[index
]);
1884 /* bcmgenet_isr0: Handle various interrupts. */
1885 static irqreturn_t
bcmgenet_isr0(int irq
, void *dev_id
)
1887 struct bcmgenet_priv
*priv
= dev_id
;
1889 /* Save irq status for bottom-half processing. */
1891 bcmgenet_intrl2_0_readl(priv
, INTRL2_CPU_STAT
) &
1892 ~bcmgenet_intrl2_0_readl(priv
, INTRL2_CPU_MASK_STATUS
);
1893 /* clear inerrupts*/
1894 bcmgenet_intrl2_0_writel(priv
, priv
->irq0_stat
, INTRL2_CPU_CLEAR
);
1896 netif_dbg(priv
, intr
, priv
->dev
,
1897 "IRQ=0x%x\n", priv
->irq0_stat
);
1899 if (priv
->irq0_stat
& (UMAC_IRQ_RXDMA_BDONE
| UMAC_IRQ_RXDMA_PDONE
)) {
1900 /* We use NAPI(software interrupt throttling, if
1901 * Rx Descriptor throttling is not used.
1902 * Disable interrupt, will be enabled in the poll method.
1904 if (likely(napi_schedule_prep(&priv
->napi
))) {
1905 bcmgenet_intrl2_0_writel(priv
,
1906 UMAC_IRQ_RXDMA_BDONE
, INTRL2_CPU_MASK_SET
);
1907 __napi_schedule(&priv
->napi
);
1910 if (priv
->irq0_stat
&
1911 (UMAC_IRQ_TXDMA_BDONE
| UMAC_IRQ_TXDMA_PDONE
)) {
1913 bcmgenet_tx_reclaim(priv
->dev
, &priv
->tx_rings
[DESC_INDEX
]);
1915 if (priv
->irq0_stat
& (UMAC_IRQ_PHY_DET_R
|
1916 UMAC_IRQ_PHY_DET_F
|
1918 UMAC_IRQ_LINK_DOWN
|
1922 /* all other interested interrupts handled in bottom half */
1923 schedule_work(&priv
->bcmgenet_irq_work
);
1926 if ((priv
->hw_params
->flags
& GENET_HAS_MDIO_INTR
) &&
1927 priv
->irq0_stat
& (UMAC_IRQ_MDIO_DONE
| UMAC_IRQ_MDIO_ERROR
)) {
1928 priv
->irq0_stat
&= ~(UMAC_IRQ_MDIO_DONE
| UMAC_IRQ_MDIO_ERROR
);
1935 static irqreturn_t
bcmgenet_wol_isr(int irq
, void *dev_id
)
1937 struct bcmgenet_priv
*priv
= dev_id
;
1939 pm_wakeup_event(&priv
->pdev
->dev
, 0);
1944 static void bcmgenet_umac_reset(struct bcmgenet_priv
*priv
)
1948 reg
= bcmgenet_rbuf_ctrl_get(priv
);
1950 bcmgenet_rbuf_ctrl_set(priv
, reg
);
1954 bcmgenet_rbuf_ctrl_set(priv
, reg
);
1958 static void bcmgenet_set_hw_addr(struct bcmgenet_priv
*priv
,
1959 unsigned char *addr
)
1961 bcmgenet_umac_writel(priv
, (addr
[0] << 24) | (addr
[1] << 16) |
1962 (addr
[2] << 8) | addr
[3], UMAC_MAC0
);
1963 bcmgenet_umac_writel(priv
, (addr
[4] << 8) | addr
[5], UMAC_MAC1
);
1966 static int bcmgenet_wol_resume(struct bcmgenet_priv
*priv
)
1968 /* From WOL-enabled suspend, switch to regular clock */
1969 clk_disable_unprepare(priv
->clk_wol
);
1971 phy_init_hw(priv
->phydev
);
1972 /* Speed settings must be restored */
1973 bcmgenet_mii_config(priv
->dev
);
1978 /* Returns a reusable dma control register value */
1979 static u32
bcmgenet_dma_disable(struct bcmgenet_priv
*priv
)
1985 dma_ctrl
= 1 << (DESC_INDEX
+ DMA_RING_BUF_EN_SHIFT
) | DMA_EN
;
1986 reg
= bcmgenet_tdma_readl(priv
, DMA_CTRL
);
1988 bcmgenet_tdma_writel(priv
, reg
, DMA_CTRL
);
1990 reg
= bcmgenet_rdma_readl(priv
, DMA_CTRL
);
1992 bcmgenet_rdma_writel(priv
, reg
, DMA_CTRL
);
1994 bcmgenet_umac_writel(priv
, 1, UMAC_TX_FLUSH
);
1996 bcmgenet_umac_writel(priv
, 0, UMAC_TX_FLUSH
);
2001 static void bcmgenet_enable_dma(struct bcmgenet_priv
*priv
, u32 dma_ctrl
)
2005 reg
= bcmgenet_rdma_readl(priv
, DMA_CTRL
);
2007 bcmgenet_rdma_writel(priv
, reg
, DMA_CTRL
);
2009 reg
= bcmgenet_tdma_readl(priv
, DMA_CTRL
);
2011 bcmgenet_tdma_writel(priv
, reg
, DMA_CTRL
);
2014 static void bcmgenet_netif_start(struct net_device
*dev
)
2016 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
2018 /* Start the network engine */
2019 napi_enable(&priv
->napi
);
2021 umac_enable_set(priv
, CMD_TX_EN
| CMD_RX_EN
, true);
2023 if (phy_is_internal(priv
->phydev
))
2024 bcmgenet_power_up(priv
, GENET_POWER_PASSIVE
);
2026 netif_tx_start_all_queues(dev
);
2028 phy_start(priv
->phydev
);
2031 static int bcmgenet_open(struct net_device
*dev
)
2033 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
2034 unsigned long dma_ctrl
;
2038 netif_dbg(priv
, ifup
, dev
, "bcmgenet_open\n");
2040 /* Turn on the clock */
2041 if (!IS_ERR(priv
->clk
))
2042 clk_prepare_enable(priv
->clk
);
2044 /* take MAC out of reset */
2045 bcmgenet_umac_reset(priv
);
2047 ret
= init_umac(priv
);
2049 goto err_clk_disable
;
2051 /* disable ethernet MAC while updating its registers */
2052 umac_enable_set(priv
, CMD_TX_EN
| CMD_RX_EN
, false);
2054 /* Make sure we reflect the value of CRC_CMD_FWD */
2055 reg
= bcmgenet_umac_readl(priv
, UMAC_CMD
);
2056 priv
->crc_fwd_en
= !!(reg
& CMD_CRC_FWD
);
2058 bcmgenet_set_hw_addr(priv
, dev
->dev_addr
);
2060 if (phy_is_internal(priv
->phydev
)) {
2061 reg
= bcmgenet_ext_readl(priv
, EXT_EXT_PWR_MGMT
);
2062 reg
|= EXT_ENERGY_DET_MASK
;
2063 bcmgenet_ext_writel(priv
, reg
, EXT_EXT_PWR_MGMT
);
2066 /* Disable RX/TX DMA and flush TX queues */
2067 dma_ctrl
= bcmgenet_dma_disable(priv
);
2069 /* Reinitialize TDMA and RDMA and SW housekeeping */
2070 ret
= bcmgenet_init_dma(priv
);
2072 netdev_err(dev
, "failed to initialize DMA\n");
2076 /* Always enable ring 16 - descriptor ring */
2077 bcmgenet_enable_dma(priv
, dma_ctrl
);
2079 ret
= request_irq(priv
->irq0
, bcmgenet_isr0
, IRQF_SHARED
,
2082 netdev_err(dev
, "can't request IRQ %d\n", priv
->irq0
);
2086 ret
= request_irq(priv
->irq1
, bcmgenet_isr1
, IRQF_SHARED
,
2089 netdev_err(dev
, "can't request IRQ %d\n", priv
->irq1
);
2093 bcmgenet_netif_start(dev
);
2098 free_irq(priv
->irq0
, dev
);
2100 bcmgenet_fini_dma(priv
);
2102 if (!IS_ERR(priv
->clk
))
2103 clk_disable_unprepare(priv
->clk
);
2107 static int bcmgenet_dma_teardown(struct bcmgenet_priv
*priv
)
2113 /* Disable TDMA to stop add more frames in TX DMA */
2114 reg
= bcmgenet_tdma_readl(priv
, DMA_CTRL
);
2116 bcmgenet_tdma_writel(priv
, reg
, DMA_CTRL
);
2118 /* Check TDMA status register to confirm TDMA is disabled */
2119 while (timeout
++ < DMA_TIMEOUT_VAL
) {
2120 reg
= bcmgenet_tdma_readl(priv
, DMA_STATUS
);
2121 if (reg
& DMA_DISABLED
)
2127 if (timeout
== DMA_TIMEOUT_VAL
) {
2128 netdev_warn(priv
->dev
,
2129 "Timed out while disabling TX DMA\n");
2133 /* Wait 10ms for packet drain in both tx and rx dma */
2134 usleep_range(10000, 20000);
2137 reg
= bcmgenet_rdma_readl(priv
, DMA_CTRL
);
2139 bcmgenet_rdma_writel(priv
, reg
, DMA_CTRL
);
2142 /* Check RDMA status register to confirm RDMA is disabled */
2143 while (timeout
++ < DMA_TIMEOUT_VAL
) {
2144 reg
= bcmgenet_rdma_readl(priv
, DMA_STATUS
);
2145 if (reg
& DMA_DISABLED
)
2151 if (timeout
== DMA_TIMEOUT_VAL
) {
2152 netdev_warn(priv
->dev
,
2153 "Timed out while disabling RX DMA\n");
2160 static void bcmgenet_netif_stop(struct net_device
*dev
)
2162 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
2164 netif_tx_stop_all_queues(dev
);
2165 napi_disable(&priv
->napi
);
2166 phy_stop(priv
->phydev
);
2168 bcmgenet_intr_disable(priv
);
2170 /* Wait for pending work items to complete. Since interrupts are
2171 * disabled no new work will be scheduled.
2173 cancel_work_sync(&priv
->bcmgenet_irq_work
);
2176 static int bcmgenet_close(struct net_device
*dev
)
2178 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
2181 netif_dbg(priv
, ifdown
, dev
, "bcmgenet_close\n");
2183 bcmgenet_netif_stop(dev
);
2185 /* Disable MAC receive */
2186 umac_enable_set(priv
, CMD_RX_EN
, false);
2188 ret
= bcmgenet_dma_teardown(priv
);
2192 /* Disable MAC transmit. TX DMA disabled have to done before this */
2193 umac_enable_set(priv
, CMD_TX_EN
, false);
2196 bcmgenet_tx_reclaim_all(dev
);
2197 bcmgenet_fini_dma(priv
);
2199 free_irq(priv
->irq0
, priv
);
2200 free_irq(priv
->irq1
, priv
);
2202 if (phy_is_internal(priv
->phydev
))
2203 bcmgenet_power_down(priv
, GENET_POWER_PASSIVE
);
2205 if (!IS_ERR(priv
->clk
))
2206 clk_disable_unprepare(priv
->clk
);
2211 static void bcmgenet_timeout(struct net_device
*dev
)
2213 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
2215 netif_dbg(priv
, tx_err
, dev
, "bcmgenet_timeout\n");
2217 dev
->trans_start
= jiffies
;
2219 dev
->stats
.tx_errors
++;
2221 netif_tx_wake_all_queues(dev
);
2224 #define MAX_MC_COUNT 16
2226 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv
*priv
,
2227 unsigned char *addr
,
2233 bcmgenet_umac_writel(priv
,
2234 addr
[0] << 8 | addr
[1], UMAC_MDF_ADDR
+ (*i
* 4));
2235 bcmgenet_umac_writel(priv
,
2236 addr
[2] << 24 | addr
[3] << 16 |
2237 addr
[4] << 8 | addr
[5],
2238 UMAC_MDF_ADDR
+ ((*i
+ 1) * 4));
2239 reg
= bcmgenet_umac_readl(priv
, UMAC_MDF_CTRL
);
2240 reg
|= (1 << (MAX_MC_COUNT
- *mc
));
2241 bcmgenet_umac_writel(priv
, reg
, UMAC_MDF_CTRL
);
2246 static void bcmgenet_set_rx_mode(struct net_device
*dev
)
2248 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
2249 struct netdev_hw_addr
*ha
;
2253 netif_dbg(priv
, hw
, dev
, "%s: %08X\n", __func__
, dev
->flags
);
2255 /* Promiscous mode */
2256 reg
= bcmgenet_umac_readl(priv
, UMAC_CMD
);
2257 if (dev
->flags
& IFF_PROMISC
) {
2259 bcmgenet_umac_writel(priv
, reg
, UMAC_CMD
);
2260 bcmgenet_umac_writel(priv
, 0, UMAC_MDF_CTRL
);
2263 reg
&= ~CMD_PROMISC
;
2264 bcmgenet_umac_writel(priv
, reg
, UMAC_CMD
);
2267 /* UniMac doesn't support ALLMULTI */
2268 if (dev
->flags
& IFF_ALLMULTI
) {
2269 netdev_warn(dev
, "ALLMULTI is not supported\n");
2273 /* update MDF filter */
2277 bcmgenet_set_mdf_addr(priv
, dev
->broadcast
, &i
, &mc
);
2278 /* my own address.*/
2279 bcmgenet_set_mdf_addr(priv
, dev
->dev_addr
, &i
, &mc
);
2281 if (netdev_uc_count(dev
) > (MAX_MC_COUNT
- mc
))
2284 if (!netdev_uc_empty(dev
))
2285 netdev_for_each_uc_addr(ha
, dev
)
2286 bcmgenet_set_mdf_addr(priv
, ha
->addr
, &i
, &mc
);
2288 if (netdev_mc_empty(dev
) || netdev_mc_count(dev
) >= (MAX_MC_COUNT
- mc
))
2291 netdev_for_each_mc_addr(ha
, dev
)
2292 bcmgenet_set_mdf_addr(priv
, ha
->addr
, &i
, &mc
);
2295 /* Set the hardware MAC address. */
2296 static int bcmgenet_set_mac_addr(struct net_device
*dev
, void *p
)
2298 struct sockaddr
*addr
= p
;
2300 /* Setting the MAC address at the hardware level is not possible
2301 * without disabling the UniMAC RX/TX enable bits.
2303 if (netif_running(dev
))
2306 ether_addr_copy(dev
->dev_addr
, addr
->sa_data
);
2311 static const struct net_device_ops bcmgenet_netdev_ops
= {
2312 .ndo_open
= bcmgenet_open
,
2313 .ndo_stop
= bcmgenet_close
,
2314 .ndo_start_xmit
= bcmgenet_xmit
,
2315 .ndo_tx_timeout
= bcmgenet_timeout
,
2316 .ndo_set_rx_mode
= bcmgenet_set_rx_mode
,
2317 .ndo_set_mac_address
= bcmgenet_set_mac_addr
,
2318 .ndo_do_ioctl
= bcmgenet_ioctl
,
2319 .ndo_set_features
= bcmgenet_set_features
,
2322 /* Array of GENET hardware parameters/characteristics */
2323 static struct bcmgenet_hw_params bcmgenet_hw_params
[] = {
2328 .bp_in_en_shift
= 16,
2329 .bp_in_mask
= 0xffff,
2330 .hfb_filter_cnt
= 16,
2332 .hfb_offset
= 0x1000,
2333 .rdma_offset
= 0x2000,
2334 .tdma_offset
= 0x3000,
2341 .bp_in_en_shift
= 16,
2342 .bp_in_mask
= 0xffff,
2343 .hfb_filter_cnt
= 16,
2345 .tbuf_offset
= 0x0600,
2346 .hfb_offset
= 0x1000,
2347 .hfb_reg_offset
= 0x2000,
2348 .rdma_offset
= 0x3000,
2349 .tdma_offset
= 0x4000,
2351 .flags
= GENET_HAS_EXT
,
2357 .bp_in_en_shift
= 17,
2358 .bp_in_mask
= 0x1ffff,
2359 .hfb_filter_cnt
= 48,
2361 .tbuf_offset
= 0x0600,
2362 .hfb_offset
= 0x8000,
2363 .hfb_reg_offset
= 0xfc00,
2364 .rdma_offset
= 0x10000,
2365 .tdma_offset
= 0x11000,
2367 .flags
= GENET_HAS_EXT
| GENET_HAS_MDIO_INTR
,
2373 .bp_in_en_shift
= 17,
2374 .bp_in_mask
= 0x1ffff,
2375 .hfb_filter_cnt
= 48,
2377 .tbuf_offset
= 0x0600,
2378 .hfb_offset
= 0x8000,
2379 .hfb_reg_offset
= 0xfc00,
2380 .rdma_offset
= 0x2000,
2381 .tdma_offset
= 0x4000,
2383 .flags
= GENET_HAS_40BITS
| GENET_HAS_EXT
| GENET_HAS_MDIO_INTR
,
2387 /* Infer hardware parameters from the detected GENET version */
2388 static void bcmgenet_set_hw_params(struct bcmgenet_priv
*priv
)
2390 struct bcmgenet_hw_params
*params
;
2394 if (GENET_IS_V4(priv
)) {
2395 bcmgenet_dma_regs
= bcmgenet_dma_regs_v3plus
;
2396 genet_dma_ring_regs
= genet_dma_ring_regs_v4
;
2397 priv
->dma_rx_chk_bit
= DMA_RX_CHK_V3PLUS
;
2398 priv
->version
= GENET_V4
;
2399 } else if (GENET_IS_V3(priv
)) {
2400 bcmgenet_dma_regs
= bcmgenet_dma_regs_v3plus
;
2401 genet_dma_ring_regs
= genet_dma_ring_regs_v123
;
2402 priv
->dma_rx_chk_bit
= DMA_RX_CHK_V3PLUS
;
2403 priv
->version
= GENET_V3
;
2404 } else if (GENET_IS_V2(priv
)) {
2405 bcmgenet_dma_regs
= bcmgenet_dma_regs_v2
;
2406 genet_dma_ring_regs
= genet_dma_ring_regs_v123
;
2407 priv
->dma_rx_chk_bit
= DMA_RX_CHK_V12
;
2408 priv
->version
= GENET_V2
;
2409 } else if (GENET_IS_V1(priv
)) {
2410 bcmgenet_dma_regs
= bcmgenet_dma_regs_v1
;
2411 genet_dma_ring_regs
= genet_dma_ring_regs_v123
;
2412 priv
->dma_rx_chk_bit
= DMA_RX_CHK_V12
;
2413 priv
->version
= GENET_V1
;
2416 /* enum genet_version starts at 1 */
2417 priv
->hw_params
= &bcmgenet_hw_params
[priv
->version
];
2418 params
= priv
->hw_params
;
2420 /* Read GENET HW version */
2421 reg
= bcmgenet_sys_readl(priv
, SYS_REV_CTRL
);
2422 major
= (reg
>> 24 & 0x0f);
2425 else if (major
== 0)
2427 if (major
!= priv
->version
) {
2428 dev_err(&priv
->pdev
->dev
,
2429 "GENET version mismatch, got: %d, configured for: %d\n",
2430 major
, priv
->version
);
2433 /* Print the GENET core version */
2434 dev_info(&priv
->pdev
->dev
, "GENET " GENET_VER_FMT
,
2435 major
, (reg
>> 16) & 0x0f, reg
& 0xffff);
2437 #ifdef CONFIG_PHYS_ADDR_T_64BIT
2438 if (!(params
->flags
& GENET_HAS_40BITS
))
2439 pr_warn("GENET does not support 40-bits PA\n");
2442 pr_debug("Configuration for version: %d\n"
2443 "TXq: %1d, RXq: %1d, BDs: %1d\n"
2444 "BP << en: %2d, BP msk: 0x%05x\n"
2445 "HFB count: %2d, QTAQ msk: 0x%05x\n"
2446 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
2447 "RDMA: 0x%05x, TDMA: 0x%05x\n"
2450 params
->tx_queues
, params
->rx_queues
, params
->bds_cnt
,
2451 params
->bp_in_en_shift
, params
->bp_in_mask
,
2452 params
->hfb_filter_cnt
, params
->qtag_mask
,
2453 params
->tbuf_offset
, params
->hfb_offset
,
2454 params
->hfb_reg_offset
,
2455 params
->rdma_offset
, params
->tdma_offset
,
2456 params
->words_per_bd
);
2459 static const struct of_device_id bcmgenet_match
[] = {
2460 { .compatible
= "brcm,genet-v1", .data
= (void *)GENET_V1
},
2461 { .compatible
= "brcm,genet-v2", .data
= (void *)GENET_V2
},
2462 { .compatible
= "brcm,genet-v3", .data
= (void *)GENET_V3
},
2463 { .compatible
= "brcm,genet-v4", .data
= (void *)GENET_V4
},
2467 static int bcmgenet_probe(struct platform_device
*pdev
)
2469 struct device_node
*dn
= pdev
->dev
.of_node
;
2470 const struct of_device_id
*of_id
;
2471 struct bcmgenet_priv
*priv
;
2472 struct net_device
*dev
;
2473 const void *macaddr
;
2477 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and a single RX queue */
2478 dev
= alloc_etherdev_mqs(sizeof(*priv
), GENET_MAX_MQ_CNT
+ 1, 1);
2480 dev_err(&pdev
->dev
, "can't allocate net device\n");
2484 of_id
= of_match_node(bcmgenet_match
, dn
);
2488 priv
= netdev_priv(dev
);
2489 priv
->irq0
= platform_get_irq(pdev
, 0);
2490 priv
->irq1
= platform_get_irq(pdev
, 1);
2491 priv
->wol_irq
= platform_get_irq(pdev
, 2);
2492 if (!priv
->irq0
|| !priv
->irq1
) {
2493 dev_err(&pdev
->dev
, "can't find IRQs\n");
2498 macaddr
= of_get_mac_address(dn
);
2500 dev_err(&pdev
->dev
, "can't find MAC address\n");
2505 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2506 priv
->base
= devm_ioremap_resource(&pdev
->dev
, r
);
2507 if (IS_ERR(priv
->base
)) {
2508 err
= PTR_ERR(priv
->base
);
2512 SET_NETDEV_DEV(dev
, &pdev
->dev
);
2513 dev_set_drvdata(&pdev
->dev
, dev
);
2514 ether_addr_copy(dev
->dev_addr
, macaddr
);
2515 dev
->watchdog_timeo
= 2 * HZ
;
2516 dev
->ethtool_ops
= &bcmgenet_ethtool_ops
;
2517 dev
->netdev_ops
= &bcmgenet_netdev_ops
;
2518 netif_napi_add(dev
, &priv
->napi
, bcmgenet_poll
, 64);
2520 priv
->msg_enable
= netif_msg_init(-1, GENET_MSG_DEFAULT
);
2522 /* Set hardware features */
2523 dev
->hw_features
|= NETIF_F_SG
| NETIF_F_IP_CSUM
|
2524 NETIF_F_IPV6_CSUM
| NETIF_F_RXCSUM
;
2526 /* Request the WOL interrupt and advertise suspend if available */
2527 priv
->wol_irq_disabled
= true;
2528 err
= devm_request_irq(&pdev
->dev
, priv
->wol_irq
, bcmgenet_wol_isr
, 0,
2531 device_set_wakeup_capable(&pdev
->dev
, 1);
2533 /* Set the needed headroom to account for any possible
2534 * features enabling/disabling at runtime
2536 dev
->needed_headroom
+= 64;
2538 netdev_boot_setup_check(dev
);
2542 priv
->version
= (enum bcmgenet_version
)of_id
->data
;
2544 bcmgenet_set_hw_params(priv
);
2546 /* Mii wait queue */
2547 init_waitqueue_head(&priv
->wq
);
2548 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
2549 priv
->rx_buf_len
= RX_BUF_LENGTH
;
2550 INIT_WORK(&priv
->bcmgenet_irq_work
, bcmgenet_irq_task
);
2552 priv
->clk
= devm_clk_get(&priv
->pdev
->dev
, "enet");
2553 if (IS_ERR(priv
->clk
))
2554 dev_warn(&priv
->pdev
->dev
, "failed to get enet clock\n");
2556 priv
->clk_wol
= devm_clk_get(&priv
->pdev
->dev
, "enet-wol");
2557 if (IS_ERR(priv
->clk_wol
))
2558 dev_warn(&priv
->pdev
->dev
, "failed to get enet-wol clock\n");
2560 if (!IS_ERR(priv
->clk
))
2561 clk_prepare_enable(priv
->clk
);
2563 err
= reset_umac(priv
);
2565 goto err_clk_disable
;
2567 err
= bcmgenet_mii_init(dev
);
2569 goto err_clk_disable
;
2571 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues
2572 * just the ring 16 descriptor based TX
2574 netif_set_real_num_tx_queues(priv
->dev
, priv
->hw_params
->tx_queues
+ 1);
2575 netif_set_real_num_rx_queues(priv
->dev
, priv
->hw_params
->rx_queues
+ 1);
2577 /* libphy will determine the link state */
2578 netif_carrier_off(dev
);
2580 /* Turn off the main clock, WOL clock is handled separately */
2581 if (!IS_ERR(priv
->clk
))
2582 clk_disable_unprepare(priv
->clk
);
2584 err
= register_netdev(dev
);
2591 if (!IS_ERR(priv
->clk
))
2592 clk_disable_unprepare(priv
->clk
);
2598 static int bcmgenet_remove(struct platform_device
*pdev
)
2600 struct bcmgenet_priv
*priv
= dev_to_priv(&pdev
->dev
);
2602 dev_set_drvdata(&pdev
->dev
, NULL
);
2603 unregister_netdev(priv
->dev
);
2604 bcmgenet_mii_exit(priv
->dev
);
2605 free_netdev(priv
->dev
);
2610 #ifdef CONFIG_PM_SLEEP
2611 static int bcmgenet_suspend(struct device
*d
)
2613 struct net_device
*dev
= dev_get_drvdata(d
);
2614 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
2617 if (!netif_running(dev
))
2620 bcmgenet_netif_stop(dev
);
2622 netif_device_detach(dev
);
2624 /* Disable MAC receive */
2625 umac_enable_set(priv
, CMD_RX_EN
, false);
2627 ret
= bcmgenet_dma_teardown(priv
);
2631 /* Disable MAC transmit. TX DMA disabled have to done before this */
2632 umac_enable_set(priv
, CMD_TX_EN
, false);
2635 bcmgenet_tx_reclaim_all(dev
);
2636 bcmgenet_fini_dma(priv
);
2638 /* Prepare the device for Wake-on-LAN and switch to the slow clock */
2639 if (device_may_wakeup(d
) && priv
->wolopts
) {
2640 bcmgenet_power_down(priv
, GENET_POWER_WOL_MAGIC
);
2641 clk_prepare_enable(priv
->clk_wol
);
2644 /* Turn off the clocks */
2645 clk_disable_unprepare(priv
->clk
);
2650 static int bcmgenet_resume(struct device
*d
)
2652 struct net_device
*dev
= dev_get_drvdata(d
);
2653 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
2654 unsigned long dma_ctrl
;
2658 if (!netif_running(dev
))
2661 /* Turn on the clock */
2662 ret
= clk_prepare_enable(priv
->clk
);
2666 bcmgenet_umac_reset(priv
);
2668 ret
= init_umac(priv
);
2670 goto out_clk_disable
;
2673 ret
= bcmgenet_wol_resume(priv
);
2676 goto out_clk_disable
;
2678 /* disable ethernet MAC while updating its registers */
2679 umac_enable_set(priv
, CMD_TX_EN
| CMD_RX_EN
, false);
2681 bcmgenet_set_hw_addr(priv
, dev
->dev_addr
);
2683 if (phy_is_internal(priv
->phydev
)) {
2684 reg
= bcmgenet_ext_readl(priv
, EXT_EXT_PWR_MGMT
);
2685 reg
|= EXT_ENERGY_DET_MASK
;
2686 bcmgenet_ext_writel(priv
, reg
, EXT_EXT_PWR_MGMT
);
2689 /* Disable RX/TX DMA and flush TX queues */
2690 dma_ctrl
= bcmgenet_dma_disable(priv
);
2692 /* Reinitialize TDMA and RDMA and SW housekeeping */
2693 ret
= bcmgenet_init_dma(priv
);
2695 netdev_err(dev
, "failed to initialize DMA\n");
2696 goto out_clk_disable
;
2699 /* Always enable ring 16 - descriptor ring */
2700 bcmgenet_enable_dma(priv
, dma_ctrl
);
2702 netif_device_attach(dev
);
2704 bcmgenet_netif_start(dev
);
2709 clk_disable_unprepare(priv
->clk
);
2712 #endif /* CONFIG_PM_SLEEP */
2714 static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops
, bcmgenet_suspend
, bcmgenet_resume
);
2716 static struct platform_driver bcmgenet_driver
= {
2717 .probe
= bcmgenet_probe
,
2718 .remove
= bcmgenet_remove
,
2721 .owner
= THIS_MODULE
,
2722 .of_match_table
= bcmgenet_match
,
2723 .pm
= &bcmgenet_pm_ops
,
2726 module_platform_driver(bcmgenet_driver
);
2728 MODULE_AUTHOR("Broadcom Corporation");
2729 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
2730 MODULE_ALIAS("platform:bcmgenet");
2731 MODULE_LICENSE("GPL");