2 * Broadcom GENET (Gigabit Ethernet) controller driver
4 * Copyright (c) 2014 Broadcom Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #define pr_fmt(fmt) "bcmgenet: " fmt
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/sched.h>
16 #include <linux/types.h>
17 #include <linux/fcntl.h>
18 #include <linux/interrupt.h>
19 #include <linux/string.h>
20 #include <linux/if_ether.h>
21 #include <linux/init.h>
22 #include <linux/errno.h>
23 #include <linux/delay.h>
24 #include <linux/platform_device.h>
25 #include <linux/dma-mapping.h>
27 #include <linux/clk.h>
29 #include <linux/of_address.h>
30 #include <linux/of_irq.h>
31 #include <linux/of_net.h>
32 #include <linux/of_platform.h>
35 #include <linux/mii.h>
36 #include <linux/ethtool.h>
37 #include <linux/netdevice.h>
38 #include <linux/inetdevice.h>
39 #include <linux/etherdevice.h>
40 #include <linux/skbuff.h>
43 #include <linux/ipv6.h>
44 #include <linux/phy.h>
46 #include <asm/unaligned.h>
50 /* Maximum number of hardware queues, downsized if needed */
51 #define GENET_MAX_MQ_CNT 4
53 /* Default highest priority queue for multi queue support */
54 #define GENET_Q0_PRIORITY 0
56 #define GENET_DEFAULT_BD_CNT \
57 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->bds_cnt)
59 #define RX_BUF_LENGTH 2048
60 #define SKB_ALIGNMENT 32
62 /* Tx/Rx DMA register offset, skip 256 descriptors */
63 #define WORDS_PER_BD(p) (p->hw_params->words_per_bd)
64 #define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32))
66 #define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \
67 TOTAL_DESC * DMA_DESC_SIZE)
69 #define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \
70 TOTAL_DESC * DMA_DESC_SIZE)
72 static inline void dmadesc_set_length_status(struct bcmgenet_priv
*priv
,
73 void __iomem
*d
, u32 value
)
75 __raw_writel(value
, d
+ DMA_DESC_LENGTH_STATUS
);
78 static inline u32
dmadesc_get_length_status(struct bcmgenet_priv
*priv
,
81 return __raw_readl(d
+ DMA_DESC_LENGTH_STATUS
);
84 static inline void dmadesc_set_addr(struct bcmgenet_priv
*priv
,
88 __raw_writel(lower_32_bits(addr
), d
+ DMA_DESC_ADDRESS_LO
);
90 /* Register writes to GISB bus can take couple hundred nanoseconds
91 * and are done for each packet, save these expensive writes unless
92 * the platform is explicitly configured for 64-bits/LPAE.
94 #ifdef CONFIG_PHYS_ADDR_T_64BIT
95 if (priv
->hw_params
->flags
& GENET_HAS_40BITS
)
96 __raw_writel(upper_32_bits(addr
), d
+ DMA_DESC_ADDRESS_HI
);
100 /* Combined address + length/status setter */
101 static inline void dmadesc_set(struct bcmgenet_priv
*priv
,
102 void __iomem
*d
, dma_addr_t addr
, u32 val
)
104 dmadesc_set_length_status(priv
, d
, val
);
105 dmadesc_set_addr(priv
, d
, addr
);
108 static inline dma_addr_t
dmadesc_get_addr(struct bcmgenet_priv
*priv
,
113 addr
= __raw_readl(d
+ DMA_DESC_ADDRESS_LO
);
115 /* Register writes to GISB bus can take couple hundred nanoseconds
116 * and are done for each packet, save these expensive writes unless
117 * the platform is explicitly configured for 64-bits/LPAE.
119 #ifdef CONFIG_PHYS_ADDR_T_64BIT
120 if (priv
->hw_params
->flags
& GENET_HAS_40BITS
)
121 addr
|= (u64
)__raw_readl(d
+ DMA_DESC_ADDRESS_HI
) << 32;
126 #define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x"
128 #define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
131 static inline u32
bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv
*priv
)
133 if (GENET_IS_V1(priv
))
134 return bcmgenet_rbuf_readl(priv
, RBUF_FLUSH_CTRL_V1
);
136 return bcmgenet_sys_readl(priv
, SYS_RBUF_FLUSH_CTRL
);
139 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv
*priv
, u32 val
)
141 if (GENET_IS_V1(priv
))
142 bcmgenet_rbuf_writel(priv
, val
, RBUF_FLUSH_CTRL_V1
);
144 bcmgenet_sys_writel(priv
, val
, SYS_RBUF_FLUSH_CTRL
);
147 /* These macros are defined to deal with register map change
148 * between GENET1.1 and GENET2. Only those currently being used
149 * by driver are defined.
151 static inline u32
bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv
*priv
)
153 if (GENET_IS_V1(priv
))
154 return bcmgenet_rbuf_readl(priv
, TBUF_CTRL_V1
);
156 return __raw_readl(priv
->base
+
157 priv
->hw_params
->tbuf_offset
+ TBUF_CTRL
);
160 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv
*priv
, u32 val
)
162 if (GENET_IS_V1(priv
))
163 bcmgenet_rbuf_writel(priv
, val
, TBUF_CTRL_V1
);
165 __raw_writel(val
, priv
->base
+
166 priv
->hw_params
->tbuf_offset
+ TBUF_CTRL
);
169 static inline u32
bcmgenet_bp_mc_get(struct bcmgenet_priv
*priv
)
171 if (GENET_IS_V1(priv
))
172 return bcmgenet_rbuf_readl(priv
, TBUF_BP_MC_V1
);
174 return __raw_readl(priv
->base
+
175 priv
->hw_params
->tbuf_offset
+ TBUF_BP_MC
);
178 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv
*priv
, u32 val
)
180 if (GENET_IS_V1(priv
))
181 bcmgenet_rbuf_writel(priv
, val
, TBUF_BP_MC_V1
);
183 __raw_writel(val
, priv
->base
+
184 priv
->hw_params
->tbuf_offset
+ TBUF_BP_MC
);
187 /* RX/TX DMA register accessors */
198 static const u8 bcmgenet_dma_regs_v3plus
[] = {
199 [DMA_RING_CFG
] = 0x00,
202 [DMA_SCB_BURST_SIZE
] = 0x0C,
203 [DMA_ARB_CTRL
] = 0x2C,
204 [DMA_PRIORITY
] = 0x30,
205 [DMA_RING_PRIORITY
] = 0x38,
208 static const u8 bcmgenet_dma_regs_v2
[] = {
209 [DMA_RING_CFG
] = 0x00,
212 [DMA_SCB_BURST_SIZE
] = 0x0C,
213 [DMA_ARB_CTRL
] = 0x30,
214 [DMA_PRIORITY
] = 0x34,
215 [DMA_RING_PRIORITY
] = 0x3C,
218 static const u8 bcmgenet_dma_regs_v1
[] = {
221 [DMA_SCB_BURST_SIZE
] = 0x0C,
222 [DMA_ARB_CTRL
] = 0x30,
223 [DMA_PRIORITY
] = 0x34,
224 [DMA_RING_PRIORITY
] = 0x3C,
227 /* Set at runtime once bcmgenet version is known */
228 static const u8
*bcmgenet_dma_regs
;
230 static inline struct bcmgenet_priv
*dev_to_priv(struct device
*dev
)
232 return netdev_priv(dev_get_drvdata(dev
));
235 static inline u32
bcmgenet_tdma_readl(struct bcmgenet_priv
*priv
,
238 return __raw_readl(priv
->base
+ GENET_TDMA_REG_OFF
+
239 DMA_RINGS_SIZE
+ bcmgenet_dma_regs
[r
]);
242 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv
*priv
,
243 u32 val
, enum dma_reg r
)
245 __raw_writel(val
, priv
->base
+ GENET_TDMA_REG_OFF
+
246 DMA_RINGS_SIZE
+ bcmgenet_dma_regs
[r
]);
249 static inline u32
bcmgenet_rdma_readl(struct bcmgenet_priv
*priv
,
252 return __raw_readl(priv
->base
+ GENET_RDMA_REG_OFF
+
253 DMA_RINGS_SIZE
+ bcmgenet_dma_regs
[r
]);
256 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv
*priv
,
257 u32 val
, enum dma_reg r
)
259 __raw_writel(val
, priv
->base
+ GENET_RDMA_REG_OFF
+
260 DMA_RINGS_SIZE
+ bcmgenet_dma_regs
[r
]);
263 /* RDMA/TDMA ring registers and accessors
264 * we merge the common fields and just prefix with T/D the registers
265 * having different meaning depending on the direction
269 RDMA_WRITE_PTR
= TDMA_READ_PTR
,
271 RDMA_WRITE_PTR_HI
= TDMA_READ_PTR_HI
,
273 RDMA_PROD_INDEX
= TDMA_CONS_INDEX
,
275 RDMA_CONS_INDEX
= TDMA_PROD_INDEX
,
281 DMA_MBUF_DONE_THRESH
,
283 RDMA_XON_XOFF_THRESH
= TDMA_FLOW_PERIOD
,
285 RDMA_READ_PTR
= TDMA_WRITE_PTR
,
287 RDMA_READ_PTR_HI
= TDMA_WRITE_PTR_HI
290 /* GENET v4 supports 40-bits pointer addressing
291 * for obvious reasons the LO and HI word parts
292 * are contiguous, but this offsets the other
295 static const u8 genet_dma_ring_regs_v4
[] = {
296 [TDMA_READ_PTR
] = 0x00,
297 [TDMA_READ_PTR_HI
] = 0x04,
298 [TDMA_CONS_INDEX
] = 0x08,
299 [TDMA_PROD_INDEX
] = 0x0C,
300 [DMA_RING_BUF_SIZE
] = 0x10,
301 [DMA_START_ADDR
] = 0x14,
302 [DMA_START_ADDR_HI
] = 0x18,
303 [DMA_END_ADDR
] = 0x1C,
304 [DMA_END_ADDR_HI
] = 0x20,
305 [DMA_MBUF_DONE_THRESH
] = 0x24,
306 [TDMA_FLOW_PERIOD
] = 0x28,
307 [TDMA_WRITE_PTR
] = 0x2C,
308 [TDMA_WRITE_PTR_HI
] = 0x30,
311 static const u8 genet_dma_ring_regs_v123
[] = {
312 [TDMA_READ_PTR
] = 0x00,
313 [TDMA_CONS_INDEX
] = 0x04,
314 [TDMA_PROD_INDEX
] = 0x08,
315 [DMA_RING_BUF_SIZE
] = 0x0C,
316 [DMA_START_ADDR
] = 0x10,
317 [DMA_END_ADDR
] = 0x14,
318 [DMA_MBUF_DONE_THRESH
] = 0x18,
319 [TDMA_FLOW_PERIOD
] = 0x1C,
320 [TDMA_WRITE_PTR
] = 0x20,
323 /* Set at runtime once GENET version is known */
324 static const u8
*genet_dma_ring_regs
;
326 static inline u32
bcmgenet_tdma_ring_readl(struct bcmgenet_priv
*priv
,
330 return __raw_readl(priv
->base
+ GENET_TDMA_REG_OFF
+
331 (DMA_RING_SIZE
* ring
) +
332 genet_dma_ring_regs
[r
]);
335 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv
*priv
,
336 unsigned int ring
, u32 val
,
339 __raw_writel(val
, priv
->base
+ GENET_TDMA_REG_OFF
+
340 (DMA_RING_SIZE
* ring
) +
341 genet_dma_ring_regs
[r
]);
344 static inline u32
bcmgenet_rdma_ring_readl(struct bcmgenet_priv
*priv
,
348 return __raw_readl(priv
->base
+ GENET_RDMA_REG_OFF
+
349 (DMA_RING_SIZE
* ring
) +
350 genet_dma_ring_regs
[r
]);
353 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv
*priv
,
354 unsigned int ring
, u32 val
,
357 __raw_writel(val
, priv
->base
+ GENET_RDMA_REG_OFF
+
358 (DMA_RING_SIZE
* ring
) +
359 genet_dma_ring_regs
[r
]);
362 static int bcmgenet_get_settings(struct net_device
*dev
,
363 struct ethtool_cmd
*cmd
)
365 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
367 if (!netif_running(dev
))
373 return phy_ethtool_gset(priv
->phydev
, cmd
);
376 static int bcmgenet_set_settings(struct net_device
*dev
,
377 struct ethtool_cmd
*cmd
)
379 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
381 if (!netif_running(dev
))
387 return phy_ethtool_sset(priv
->phydev
, cmd
);
390 static int bcmgenet_set_rx_csum(struct net_device
*dev
,
391 netdev_features_t wanted
)
393 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
397 rx_csum_en
= !!(wanted
& NETIF_F_RXCSUM
);
399 rbuf_chk_ctrl
= bcmgenet_rbuf_readl(priv
, RBUF_CHK_CTRL
);
401 /* enable rx checksumming */
403 rbuf_chk_ctrl
|= RBUF_RXCHK_EN
;
405 rbuf_chk_ctrl
&= ~RBUF_RXCHK_EN
;
406 priv
->desc_rxchk_en
= rx_csum_en
;
408 /* If UniMAC forwards CRC, we need to skip over it to get
409 * a valid CHK bit to be set in the per-packet status word
411 if (rx_csum_en
&& priv
->crc_fwd_en
)
412 rbuf_chk_ctrl
|= RBUF_SKIP_FCS
;
414 rbuf_chk_ctrl
&= ~RBUF_SKIP_FCS
;
416 bcmgenet_rbuf_writel(priv
, rbuf_chk_ctrl
, RBUF_CHK_CTRL
);
421 static int bcmgenet_set_tx_csum(struct net_device
*dev
,
422 netdev_features_t wanted
)
424 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
426 u32 tbuf_ctrl
, rbuf_ctrl
;
428 tbuf_ctrl
= bcmgenet_tbuf_ctrl_get(priv
);
429 rbuf_ctrl
= bcmgenet_rbuf_readl(priv
, RBUF_CTRL
);
431 desc_64b_en
= !!(wanted
& (NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
));
433 /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
435 tbuf_ctrl
|= RBUF_64B_EN
;
436 rbuf_ctrl
|= RBUF_64B_EN
;
438 tbuf_ctrl
&= ~RBUF_64B_EN
;
439 rbuf_ctrl
&= ~RBUF_64B_EN
;
441 priv
->desc_64b_en
= desc_64b_en
;
443 bcmgenet_tbuf_ctrl_set(priv
, tbuf_ctrl
);
444 bcmgenet_rbuf_writel(priv
, rbuf_ctrl
, RBUF_CTRL
);
449 static int bcmgenet_set_features(struct net_device
*dev
,
450 netdev_features_t features
)
452 netdev_features_t changed
= features
^ dev
->features
;
453 netdev_features_t wanted
= dev
->wanted_features
;
456 if (changed
& (NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
))
457 ret
= bcmgenet_set_tx_csum(dev
, wanted
);
458 if (changed
& (NETIF_F_RXCSUM
))
459 ret
= bcmgenet_set_rx_csum(dev
, wanted
);
464 static u32
bcmgenet_get_msglevel(struct net_device
*dev
)
466 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
468 return priv
->msg_enable
;
471 static void bcmgenet_set_msglevel(struct net_device
*dev
, u32 level
)
473 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
475 priv
->msg_enable
= level
;
478 /* standard ethtool support functions. */
479 enum bcmgenet_stat_type
{
480 BCMGENET_STAT_NETDEV
= -1,
481 BCMGENET_STAT_MIB_RX
,
482 BCMGENET_STAT_MIB_TX
,
487 struct bcmgenet_stats
{
488 char stat_string
[ETH_GSTRING_LEN
];
491 enum bcmgenet_stat_type type
;
492 /* reg offset from UMAC base for misc counters */
496 #define STAT_NETDEV(m) { \
497 .stat_string = __stringify(m), \
498 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
499 .stat_offset = offsetof(struct net_device_stats, m), \
500 .type = BCMGENET_STAT_NETDEV, \
503 #define STAT_GENET_MIB(str, m, _type) { \
504 .stat_string = str, \
505 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
506 .stat_offset = offsetof(struct bcmgenet_priv, m), \
510 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
511 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
512 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
514 #define STAT_GENET_MISC(str, m, offset) { \
515 .stat_string = str, \
516 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
517 .stat_offset = offsetof(struct bcmgenet_priv, m), \
518 .type = BCMGENET_STAT_MISC, \
519 .reg_offset = offset, \
523 /* There is a 0xC gap between the end of RX and beginning of TX stats and then
524 * between the end of TX stats and the beginning of the RX RUNT
526 #define BCMGENET_STAT_OFFSET 0xc
528 /* Hardware counters must be kept in sync because the order/offset
529 * is important here (order in structure declaration = order in hardware)
531 static const struct bcmgenet_stats bcmgenet_gstrings_stats
[] = {
533 STAT_NETDEV(rx_packets
),
534 STAT_NETDEV(tx_packets
),
535 STAT_NETDEV(rx_bytes
),
536 STAT_NETDEV(tx_bytes
),
537 STAT_NETDEV(rx_errors
),
538 STAT_NETDEV(tx_errors
),
539 STAT_NETDEV(rx_dropped
),
540 STAT_NETDEV(tx_dropped
),
541 STAT_NETDEV(multicast
),
542 /* UniMAC RSV counters */
543 STAT_GENET_MIB_RX("rx_64_octets", mib
.rx
.pkt_cnt
.cnt_64
),
544 STAT_GENET_MIB_RX("rx_65_127_oct", mib
.rx
.pkt_cnt
.cnt_127
),
545 STAT_GENET_MIB_RX("rx_128_255_oct", mib
.rx
.pkt_cnt
.cnt_255
),
546 STAT_GENET_MIB_RX("rx_256_511_oct", mib
.rx
.pkt_cnt
.cnt_511
),
547 STAT_GENET_MIB_RX("rx_512_1023_oct", mib
.rx
.pkt_cnt
.cnt_1023
),
548 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib
.rx
.pkt_cnt
.cnt_1518
),
549 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib
.rx
.pkt_cnt
.cnt_mgv
),
550 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib
.rx
.pkt_cnt
.cnt_2047
),
551 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib
.rx
.pkt_cnt
.cnt_4095
),
552 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib
.rx
.pkt_cnt
.cnt_9216
),
553 STAT_GENET_MIB_RX("rx_pkts", mib
.rx
.pkt
),
554 STAT_GENET_MIB_RX("rx_bytes", mib
.rx
.bytes
),
555 STAT_GENET_MIB_RX("rx_multicast", mib
.rx
.mca
),
556 STAT_GENET_MIB_RX("rx_broadcast", mib
.rx
.bca
),
557 STAT_GENET_MIB_RX("rx_fcs", mib
.rx
.fcs
),
558 STAT_GENET_MIB_RX("rx_control", mib
.rx
.cf
),
559 STAT_GENET_MIB_RX("rx_pause", mib
.rx
.pf
),
560 STAT_GENET_MIB_RX("rx_unknown", mib
.rx
.uo
),
561 STAT_GENET_MIB_RX("rx_align", mib
.rx
.aln
),
562 STAT_GENET_MIB_RX("rx_outrange", mib
.rx
.flr
),
563 STAT_GENET_MIB_RX("rx_code", mib
.rx
.cde
),
564 STAT_GENET_MIB_RX("rx_carrier", mib
.rx
.fcr
),
565 STAT_GENET_MIB_RX("rx_oversize", mib
.rx
.ovr
),
566 STAT_GENET_MIB_RX("rx_jabber", mib
.rx
.jbr
),
567 STAT_GENET_MIB_RX("rx_mtu_err", mib
.rx
.mtue
),
568 STAT_GENET_MIB_RX("rx_good_pkts", mib
.rx
.pok
),
569 STAT_GENET_MIB_RX("rx_unicast", mib
.rx
.uc
),
570 STAT_GENET_MIB_RX("rx_ppp", mib
.rx
.ppp
),
571 STAT_GENET_MIB_RX("rx_crc", mib
.rx
.rcrc
),
572 /* UniMAC TSV counters */
573 STAT_GENET_MIB_TX("tx_64_octets", mib
.tx
.pkt_cnt
.cnt_64
),
574 STAT_GENET_MIB_TX("tx_65_127_oct", mib
.tx
.pkt_cnt
.cnt_127
),
575 STAT_GENET_MIB_TX("tx_128_255_oct", mib
.tx
.pkt_cnt
.cnt_255
),
576 STAT_GENET_MIB_TX("tx_256_511_oct", mib
.tx
.pkt_cnt
.cnt_511
),
577 STAT_GENET_MIB_TX("tx_512_1023_oct", mib
.tx
.pkt_cnt
.cnt_1023
),
578 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib
.tx
.pkt_cnt
.cnt_1518
),
579 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib
.tx
.pkt_cnt
.cnt_mgv
),
580 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib
.tx
.pkt_cnt
.cnt_2047
),
581 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib
.tx
.pkt_cnt
.cnt_4095
),
582 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib
.tx
.pkt_cnt
.cnt_9216
),
583 STAT_GENET_MIB_TX("tx_pkts", mib
.tx
.pkts
),
584 STAT_GENET_MIB_TX("tx_multicast", mib
.tx
.mca
),
585 STAT_GENET_MIB_TX("tx_broadcast", mib
.tx
.bca
),
586 STAT_GENET_MIB_TX("tx_pause", mib
.tx
.pf
),
587 STAT_GENET_MIB_TX("tx_control", mib
.tx
.cf
),
588 STAT_GENET_MIB_TX("tx_fcs_err", mib
.tx
.fcs
),
589 STAT_GENET_MIB_TX("tx_oversize", mib
.tx
.ovr
),
590 STAT_GENET_MIB_TX("tx_defer", mib
.tx
.drf
),
591 STAT_GENET_MIB_TX("tx_excess_defer", mib
.tx
.edf
),
592 STAT_GENET_MIB_TX("tx_single_col", mib
.tx
.scl
),
593 STAT_GENET_MIB_TX("tx_multi_col", mib
.tx
.mcl
),
594 STAT_GENET_MIB_TX("tx_late_col", mib
.tx
.lcl
),
595 STAT_GENET_MIB_TX("tx_excess_col", mib
.tx
.ecl
),
596 STAT_GENET_MIB_TX("tx_frags", mib
.tx
.frg
),
597 STAT_GENET_MIB_TX("tx_total_col", mib
.tx
.ncl
),
598 STAT_GENET_MIB_TX("tx_jabber", mib
.tx
.jbr
),
599 STAT_GENET_MIB_TX("tx_bytes", mib
.tx
.bytes
),
600 STAT_GENET_MIB_TX("tx_good_pkts", mib
.tx
.pok
),
601 STAT_GENET_MIB_TX("tx_unicast", mib
.tx
.uc
),
602 /* UniMAC RUNT counters */
603 STAT_GENET_RUNT("rx_runt_pkts", mib
.rx_runt_cnt
),
604 STAT_GENET_RUNT("rx_runt_valid_fcs", mib
.rx_runt_fcs
),
605 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib
.rx_runt_fcs_align
),
606 STAT_GENET_RUNT("rx_runt_bytes", mib
.rx_runt_bytes
),
607 /* Misc UniMAC counters */
608 STAT_GENET_MISC("rbuf_ovflow_cnt", mib
.rbuf_ovflow_cnt
,
610 STAT_GENET_MISC("rbuf_err_cnt", mib
.rbuf_err_cnt
, UMAC_RBUF_ERR_CNT
),
611 STAT_GENET_MISC("mdf_err_cnt", mib
.mdf_err_cnt
, UMAC_MDF_ERR_CNT
),
614 #define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats)
616 static void bcmgenet_get_drvinfo(struct net_device
*dev
,
617 struct ethtool_drvinfo
*info
)
619 strlcpy(info
->driver
, "bcmgenet", sizeof(info
->driver
));
620 strlcpy(info
->version
, "v2.0", sizeof(info
->version
));
621 info
->n_stats
= BCMGENET_STATS_LEN
;
624 static int bcmgenet_get_sset_count(struct net_device
*dev
, int string_set
)
626 switch (string_set
) {
628 return BCMGENET_STATS_LEN
;
634 static void bcmgenet_get_strings(struct net_device
*dev
, u32 stringset
,
641 for (i
= 0; i
< BCMGENET_STATS_LEN
; i
++) {
642 memcpy(data
+ i
* ETH_GSTRING_LEN
,
643 bcmgenet_gstrings_stats
[i
].stat_string
,
650 static void bcmgenet_update_mib_counters(struct bcmgenet_priv
*priv
)
654 for (i
= 0; i
< BCMGENET_STATS_LEN
; i
++) {
655 const struct bcmgenet_stats
*s
;
660 s
= &bcmgenet_gstrings_stats
[i
];
662 case BCMGENET_STAT_NETDEV
:
664 case BCMGENET_STAT_MIB_RX
:
665 case BCMGENET_STAT_MIB_TX
:
666 case BCMGENET_STAT_RUNT
:
667 if (s
->type
!= BCMGENET_STAT_MIB_RX
)
668 offset
= BCMGENET_STAT_OFFSET
;
669 val
= bcmgenet_umac_readl(priv
,
670 UMAC_MIB_START
+ j
+ offset
);
672 case BCMGENET_STAT_MISC
:
673 val
= bcmgenet_umac_readl(priv
, s
->reg_offset
);
674 /* clear if overflowed */
676 bcmgenet_umac_writel(priv
, 0, s
->reg_offset
);
681 p
= (char *)priv
+ s
->stat_offset
;
686 static void bcmgenet_get_ethtool_stats(struct net_device
*dev
,
687 struct ethtool_stats
*stats
,
690 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
693 if (netif_running(dev
))
694 bcmgenet_update_mib_counters(priv
);
696 for (i
= 0; i
< BCMGENET_STATS_LEN
; i
++) {
697 const struct bcmgenet_stats
*s
;
700 s
= &bcmgenet_gstrings_stats
[i
];
701 if (s
->type
== BCMGENET_STAT_NETDEV
)
702 p
= (char *)&dev
->stats
;
710 /* standard ethtool support functions. */
711 static struct ethtool_ops bcmgenet_ethtool_ops
= {
712 .get_strings
= bcmgenet_get_strings
,
713 .get_sset_count
= bcmgenet_get_sset_count
,
714 .get_ethtool_stats
= bcmgenet_get_ethtool_stats
,
715 .get_settings
= bcmgenet_get_settings
,
716 .set_settings
= bcmgenet_set_settings
,
717 .get_drvinfo
= bcmgenet_get_drvinfo
,
718 .get_link
= ethtool_op_get_link
,
719 .get_msglevel
= bcmgenet_get_msglevel
,
720 .set_msglevel
= bcmgenet_set_msglevel
,
721 .get_wol
= bcmgenet_get_wol
,
722 .set_wol
= bcmgenet_set_wol
,
725 /* Power down the unimac, based on mode. */
726 static void bcmgenet_power_down(struct bcmgenet_priv
*priv
,
727 enum bcmgenet_power_mode mode
)
732 case GENET_POWER_CABLE_SENSE
:
733 phy_detach(priv
->phydev
);
736 case GENET_POWER_WOL_MAGIC
:
737 bcmgenet_wol_power_down_cfg(priv
, mode
);
740 case GENET_POWER_PASSIVE
:
742 if (priv
->hw_params
->flags
& GENET_HAS_EXT
) {
743 reg
= bcmgenet_ext_readl(priv
, EXT_EXT_PWR_MGMT
);
744 reg
|= (EXT_PWR_DOWN_PHY
|
745 EXT_PWR_DOWN_DLL
| EXT_PWR_DOWN_BIAS
);
746 bcmgenet_ext_writel(priv
, reg
, EXT_EXT_PWR_MGMT
);
754 static void bcmgenet_power_up(struct bcmgenet_priv
*priv
,
755 enum bcmgenet_power_mode mode
)
759 if (!(priv
->hw_params
->flags
& GENET_HAS_EXT
))
762 reg
= bcmgenet_ext_readl(priv
, EXT_EXT_PWR_MGMT
);
765 case GENET_POWER_PASSIVE
:
766 reg
&= ~(EXT_PWR_DOWN_DLL
| EXT_PWR_DOWN_PHY
|
769 case GENET_POWER_CABLE_SENSE
:
771 reg
|= EXT_PWR_DN_EN_LD
;
773 case GENET_POWER_WOL_MAGIC
:
774 bcmgenet_wol_power_up_cfg(priv
, mode
);
780 bcmgenet_ext_writel(priv
, reg
, EXT_EXT_PWR_MGMT
);
782 if (mode
== GENET_POWER_PASSIVE
)
783 bcmgenet_mii_reset(priv
->dev
);
786 /* ioctl handle special commands that are not present in ethtool. */
787 static int bcmgenet_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
789 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
792 if (!netif_running(dev
))
802 val
= phy_mii_ioctl(priv
->phydev
, rq
, cmd
);
813 static struct enet_cb
*bcmgenet_get_txcb(struct bcmgenet_priv
*priv
,
814 struct bcmgenet_tx_ring
*ring
)
816 struct enet_cb
*tx_cb_ptr
;
818 tx_cb_ptr
= ring
->cbs
;
819 tx_cb_ptr
+= ring
->write_ptr
- ring
->cb_ptr
;
820 tx_cb_ptr
->bd_addr
= priv
->tx_bds
+ ring
->write_ptr
* DMA_DESC_SIZE
;
821 /* Advancing local write pointer */
822 if (ring
->write_ptr
== ring
->end_ptr
)
823 ring
->write_ptr
= ring
->cb_ptr
;
830 /* Simple helper to free a control block's resources */
831 static void bcmgenet_free_cb(struct enet_cb
*cb
)
833 dev_kfree_skb_any(cb
->skb
);
835 dma_unmap_addr_set(cb
, dma_addr
, 0);
838 static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_priv
*priv
,
839 struct bcmgenet_tx_ring
*ring
)
841 bcmgenet_intrl2_0_writel(priv
,
842 UMAC_IRQ_TXDMA_BDONE
| UMAC_IRQ_TXDMA_PDONE
,
843 INTRL2_CPU_MASK_SET
);
846 static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_priv
*priv
,
847 struct bcmgenet_tx_ring
*ring
)
849 bcmgenet_intrl2_0_writel(priv
,
850 UMAC_IRQ_TXDMA_BDONE
| UMAC_IRQ_TXDMA_PDONE
,
851 INTRL2_CPU_MASK_CLEAR
);
854 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_priv
*priv
,
855 struct bcmgenet_tx_ring
*ring
)
857 bcmgenet_intrl2_1_writel(priv
, (1 << ring
->index
),
858 INTRL2_CPU_MASK_CLEAR
);
859 priv
->int1_mask
&= ~(1 << ring
->index
);
862 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_priv
*priv
,
863 struct bcmgenet_tx_ring
*ring
)
865 bcmgenet_intrl2_1_writel(priv
, (1 << ring
->index
),
866 INTRL2_CPU_MASK_SET
);
867 priv
->int1_mask
|= (1 << ring
->index
);
870 /* Unlocked version of the reclaim routine */
871 static void __bcmgenet_tx_reclaim(struct net_device
*dev
,
872 struct bcmgenet_tx_ring
*ring
)
874 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
875 int last_tx_cn
, last_c_index
, num_tx_bds
;
876 struct enet_cb
*tx_cb_ptr
;
877 struct netdev_queue
*txq
;
878 unsigned int bds_compl
;
879 unsigned int c_index
;
881 /* Compute how many buffers are transmitted since last xmit call */
882 c_index
= bcmgenet_tdma_ring_readl(priv
, ring
->index
, TDMA_CONS_INDEX
);
883 txq
= netdev_get_tx_queue(dev
, ring
->queue
);
885 last_c_index
= ring
->c_index
;
886 num_tx_bds
= ring
->size
;
888 c_index
&= (num_tx_bds
- 1);
890 if (c_index
>= last_c_index
)
891 last_tx_cn
= c_index
- last_c_index
;
893 last_tx_cn
= num_tx_bds
- last_c_index
+ c_index
;
895 netif_dbg(priv
, tx_done
, dev
,
896 "%s ring=%d index=%d last_tx_cn=%d last_index=%d\n",
897 __func__
, ring
->index
,
898 c_index
, last_tx_cn
, last_c_index
);
900 /* Reclaim transmitted buffers */
901 while (last_tx_cn
-- > 0) {
902 tx_cb_ptr
= ring
->cbs
+ last_c_index
;
904 if (tx_cb_ptr
->skb
) {
905 bds_compl
= skb_shinfo(tx_cb_ptr
->skb
)->nr_frags
+ 1;
906 dev
->stats
.tx_bytes
+= tx_cb_ptr
->skb
->len
;
907 dma_unmap_single(&dev
->dev
,
908 dma_unmap_addr(tx_cb_ptr
, dma_addr
),
911 bcmgenet_free_cb(tx_cb_ptr
);
912 } else if (dma_unmap_addr(tx_cb_ptr
, dma_addr
)) {
913 dev
->stats
.tx_bytes
+=
914 dma_unmap_len(tx_cb_ptr
, dma_len
);
915 dma_unmap_page(&dev
->dev
,
916 dma_unmap_addr(tx_cb_ptr
, dma_addr
),
917 dma_unmap_len(tx_cb_ptr
, dma_len
),
919 dma_unmap_addr_set(tx_cb_ptr
, dma_addr
, 0);
921 dev
->stats
.tx_packets
++;
922 ring
->free_bds
+= bds_compl
;
925 last_c_index
&= (num_tx_bds
- 1);
928 if (ring
->free_bds
> (MAX_SKB_FRAGS
+ 1))
929 ring
->int_disable(priv
, ring
);
931 if (netif_tx_queue_stopped(txq
))
932 netif_tx_wake_queue(txq
);
934 ring
->c_index
= c_index
;
937 static void bcmgenet_tx_reclaim(struct net_device
*dev
,
938 struct bcmgenet_tx_ring
*ring
)
942 spin_lock_irqsave(&ring
->lock
, flags
);
943 __bcmgenet_tx_reclaim(dev
, ring
);
944 spin_unlock_irqrestore(&ring
->lock
, flags
);
947 static void bcmgenet_tx_reclaim_all(struct net_device
*dev
)
949 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
952 if (netif_is_multiqueue(dev
)) {
953 for (i
= 0; i
< priv
->hw_params
->tx_queues
; i
++)
954 bcmgenet_tx_reclaim(dev
, &priv
->tx_rings
[i
]);
957 bcmgenet_tx_reclaim(dev
, &priv
->tx_rings
[DESC_INDEX
]);
960 /* Transmits a single SKB (either head of a fragment or a single SKB)
961 * caller must hold priv->lock
963 static int bcmgenet_xmit_single(struct net_device
*dev
,
966 struct bcmgenet_tx_ring
*ring
)
968 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
969 struct device
*kdev
= &priv
->pdev
->dev
;
970 struct enet_cb
*tx_cb_ptr
;
971 unsigned int skb_len
;
976 tx_cb_ptr
= bcmgenet_get_txcb(priv
, ring
);
978 if (unlikely(!tx_cb_ptr
))
981 tx_cb_ptr
->skb
= skb
;
983 skb_len
= skb_headlen(skb
) < ETH_ZLEN
? ETH_ZLEN
: skb_headlen(skb
);
985 mapping
= dma_map_single(kdev
, skb
->data
, skb_len
, DMA_TO_DEVICE
);
986 ret
= dma_mapping_error(kdev
, mapping
);
988 netif_err(priv
, tx_err
, dev
, "Tx DMA map failed\n");
993 dma_unmap_addr_set(tx_cb_ptr
, dma_addr
, mapping
);
994 dma_unmap_len_set(tx_cb_ptr
, dma_len
, skb
->len
);
995 length_status
= (skb_len
<< DMA_BUFLENGTH_SHIFT
) | dma_desc_flags
|
996 (priv
->hw_params
->qtag_mask
<< DMA_TX_QTAG_SHIFT
) |
999 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
1000 length_status
|= DMA_TX_DO_CSUM
;
1002 dmadesc_set(priv
, tx_cb_ptr
->bd_addr
, mapping
, length_status
);
1004 /* Decrement total BD count and advance our write pointer */
1005 ring
->free_bds
-= 1;
1006 ring
->prod_index
+= 1;
1007 ring
->prod_index
&= DMA_P_INDEX_MASK
;
1012 /* Transmit a SKB fragment */
1013 static int bcmgenet_xmit_frag(struct net_device
*dev
,
1016 struct bcmgenet_tx_ring
*ring
)
1018 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
1019 struct device
*kdev
= &priv
->pdev
->dev
;
1020 struct enet_cb
*tx_cb_ptr
;
1024 tx_cb_ptr
= bcmgenet_get_txcb(priv
, ring
);
1026 if (unlikely(!tx_cb_ptr
))
1028 tx_cb_ptr
->skb
= NULL
;
1030 mapping
= skb_frag_dma_map(kdev
, frag
, 0,
1031 skb_frag_size(frag
), DMA_TO_DEVICE
);
1032 ret
= dma_mapping_error(kdev
, mapping
);
1034 netif_err(priv
, tx_err
, dev
, "%s: Tx DMA map failed\n",
1039 dma_unmap_addr_set(tx_cb_ptr
, dma_addr
, mapping
);
1040 dma_unmap_len_set(tx_cb_ptr
, dma_len
, frag
->size
);
1042 dmadesc_set(priv
, tx_cb_ptr
->bd_addr
, mapping
,
1043 (frag
->size
<< DMA_BUFLENGTH_SHIFT
) | dma_desc_flags
|
1044 (priv
->hw_params
->qtag_mask
<< DMA_TX_QTAG_SHIFT
));
1047 ring
->free_bds
-= 1;
1048 ring
->prod_index
+= 1;
1049 ring
->prod_index
&= DMA_P_INDEX_MASK
;
1054 /* Reallocate the SKB to put enough headroom in front of it and insert
1055 * the transmit checksum offsets in the descriptors
1057 static int bcmgenet_put_tx_csum(struct net_device
*dev
, struct sk_buff
*skb
)
1059 struct status_64
*status
= NULL
;
1060 struct sk_buff
*new_skb
;
1066 if (unlikely(skb_headroom(skb
) < sizeof(*status
))) {
1067 /* If 64 byte status block enabled, must make sure skb has
1068 * enough headroom for us to insert 64B status block.
1070 new_skb
= skb_realloc_headroom(skb
, sizeof(*status
));
1073 dev
->stats
.tx_errors
++;
1074 dev
->stats
.tx_dropped
++;
1080 skb_push(skb
, sizeof(*status
));
1081 status
= (struct status_64
*)skb
->data
;
1083 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
1084 ip_ver
= htons(skb
->protocol
);
1087 ip_proto
= ip_hdr(skb
)->protocol
;
1090 ip_proto
= ipv6_hdr(skb
)->nexthdr
;
1096 offset
= skb_checksum_start_offset(skb
) - sizeof(*status
);
1097 tx_csum_info
= (offset
<< STATUS_TX_CSUM_START_SHIFT
) |
1098 (offset
+ skb
->csum_offset
);
1100 /* Set the length valid bit for TCP and UDP and just set
1101 * the special UDP flag for IPv4, else just set to 0.
1103 if (ip_proto
== IPPROTO_TCP
|| ip_proto
== IPPROTO_UDP
) {
1104 tx_csum_info
|= STATUS_TX_CSUM_LV
;
1105 if (ip_proto
== IPPROTO_UDP
&& ip_ver
== ETH_P_IP
)
1106 tx_csum_info
|= STATUS_TX_CSUM_PROTO_UDP
;
1111 status
->tx_csum_info
= tx_csum_info
;
1117 static netdev_tx_t
bcmgenet_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1119 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
1120 struct bcmgenet_tx_ring
*ring
= NULL
;
1121 struct netdev_queue
*txq
;
1122 unsigned long flags
= 0;
1123 int nr_frags
, index
;
1128 index
= skb_get_queue_mapping(skb
);
1129 /* Mapping strategy:
1130 * queue_mapping = 0, unclassified, packet xmited through ring16
1131 * queue_mapping = 1, goes to ring 0. (highest priority queue
1132 * queue_mapping = 2, goes to ring 1.
1133 * queue_mapping = 3, goes to ring 2.
1134 * queue_mapping = 4, goes to ring 3.
1141 nr_frags
= skb_shinfo(skb
)->nr_frags
;
1142 ring
= &priv
->tx_rings
[index
];
1143 txq
= netdev_get_tx_queue(dev
, ring
->queue
);
1145 spin_lock_irqsave(&ring
->lock
, flags
);
1146 if (ring
->free_bds
<= nr_frags
+ 1) {
1147 netif_tx_stop_queue(txq
);
1148 netdev_err(dev
, "%s: tx ring %d full when queue %d awake\n",
1149 __func__
, index
, ring
->queue
);
1150 ret
= NETDEV_TX_BUSY
;
1154 if (skb_padto(skb
, ETH_ZLEN
)) {
1159 /* set the SKB transmit checksum */
1160 if (priv
->desc_64b_en
) {
1161 ret
= bcmgenet_put_tx_csum(dev
, skb
);
1168 dma_desc_flags
= DMA_SOP
;
1170 dma_desc_flags
|= DMA_EOP
;
1172 /* Transmit single SKB or head of fragment list */
1173 ret
= bcmgenet_xmit_single(dev
, skb
, dma_desc_flags
, ring
);
1180 for (i
= 0; i
< nr_frags
; i
++) {
1181 ret
= bcmgenet_xmit_frag(dev
,
1182 &skb_shinfo(skb
)->frags
[i
],
1183 (i
== nr_frags
- 1) ? DMA_EOP
: 0,
1191 skb_tx_timestamp(skb
);
1193 /* we kept a software copy of how much we should advance the TDMA
1194 * producer index, now write it down to the hardware
1196 bcmgenet_tdma_ring_writel(priv
, ring
->index
,
1197 ring
->prod_index
, TDMA_PROD_INDEX
);
1199 if (ring
->free_bds
<= (MAX_SKB_FRAGS
+ 1)) {
1200 netif_tx_stop_queue(txq
);
1201 ring
->int_enable(priv
, ring
);
1205 spin_unlock_irqrestore(&ring
->lock
, flags
);
1211 static int bcmgenet_rx_refill(struct bcmgenet_priv
*priv
, struct enet_cb
*cb
)
1213 struct device
*kdev
= &priv
->pdev
->dev
;
1214 struct sk_buff
*skb
;
1218 skb
= netdev_alloc_skb(priv
->dev
, priv
->rx_buf_len
+ SKB_ALIGNMENT
);
1222 /* a caller did not release this control block */
1223 WARN_ON(cb
->skb
!= NULL
);
1225 mapping
= dma_map_single(kdev
, skb
->data
,
1226 priv
->rx_buf_len
, DMA_FROM_DEVICE
);
1227 ret
= dma_mapping_error(kdev
, mapping
);
1229 bcmgenet_free_cb(cb
);
1230 netif_err(priv
, rx_err
, priv
->dev
,
1231 "%s DMA map failed\n", __func__
);
1235 dma_unmap_addr_set(cb
, dma_addr
, mapping
);
1236 /* assign packet, prepare descriptor, and advance pointer */
1238 dmadesc_set_addr(priv
, priv
->rx_bd_assign_ptr
, mapping
);
1240 /* turn on the newly assigned BD for DMA to use */
1241 priv
->rx_bd_assign_index
++;
1242 priv
->rx_bd_assign_index
&= (priv
->num_rx_bds
- 1);
1244 priv
->rx_bd_assign_ptr
= priv
->rx_bds
+
1245 (priv
->rx_bd_assign_index
* DMA_DESC_SIZE
);
1250 /* bcmgenet_desc_rx - descriptor based rx process.
1251 * this could be called from bottom half, or from NAPI polling method.
1253 static unsigned int bcmgenet_desc_rx(struct bcmgenet_priv
*priv
,
1254 unsigned int budget
)
1256 struct net_device
*dev
= priv
->dev
;
1258 struct sk_buff
*skb
;
1259 u32 dma_length_status
;
1260 unsigned long dma_flag
;
1262 unsigned int rxpktprocessed
= 0, rxpkttoprocess
;
1263 unsigned int p_index
;
1264 unsigned int chksum_ok
= 0;
1266 p_index
= bcmgenet_rdma_ring_readl(priv
, DESC_INDEX
, RDMA_PROD_INDEX
);
1267 p_index
&= DMA_P_INDEX_MASK
;
1269 if (p_index
< priv
->rx_c_index
)
1270 rxpkttoprocess
= (DMA_C_INDEX_MASK
+ 1) -
1271 priv
->rx_c_index
+ p_index
;
1273 rxpkttoprocess
= p_index
- priv
->rx_c_index
;
1275 netif_dbg(priv
, rx_status
, dev
,
1276 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess
);
1278 while ((rxpktprocessed
< rxpkttoprocess
) &&
1279 (rxpktprocessed
< budget
)) {
1280 cb
= &priv
->rx_cbs
[priv
->rx_read_ptr
];
1285 priv
->rx_read_ptr
++;
1286 priv
->rx_read_ptr
&= (priv
->num_rx_bds
- 1);
1288 /* We do not have a backing SKB, so we do not have a
1289 * corresponding DMA mapping for this incoming packet since
1290 * bcmgenet_rx_refill always either has both skb and mapping or
1293 if (unlikely(!skb
)) {
1294 dev
->stats
.rx_dropped
++;
1295 dev
->stats
.rx_errors
++;
1299 /* Unmap the packet contents such that we can use the
1300 * RSV from the 64 bytes descriptor when enabled and save
1301 * a 32-bits register read
1303 dma_unmap_single(&dev
->dev
, dma_unmap_addr(cb
, dma_addr
),
1304 priv
->rx_buf_len
, DMA_FROM_DEVICE
);
1306 if (!priv
->desc_64b_en
) {
1308 dmadesc_get_length_status(priv
,
1310 (priv
->rx_read_ptr
*
1313 struct status_64
*status
;
1315 status
= (struct status_64
*)skb
->data
;
1316 dma_length_status
= status
->length_status
;
1319 /* DMA flags and length are still valid no matter how
1320 * we got the Receive Status Vector (64B RSB or register)
1322 dma_flag
= dma_length_status
& 0xffff;
1323 len
= dma_length_status
>> DMA_BUFLENGTH_SHIFT
;
1325 netif_dbg(priv
, rx_status
, dev
,
1326 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
1327 __func__
, p_index
, priv
->rx_c_index
,
1328 priv
->rx_read_ptr
, dma_length_status
);
1330 if (unlikely(!(dma_flag
& DMA_EOP
) || !(dma_flag
& DMA_SOP
))) {
1331 netif_err(priv
, rx_status
, dev
,
1332 "dropping fragmented packet!\n");
1333 dev
->stats
.rx_dropped
++;
1334 dev
->stats
.rx_errors
++;
1335 dev_kfree_skb_any(cb
->skb
);
1340 if (unlikely(dma_flag
& (DMA_RX_CRC_ERROR
|
1345 netif_err(priv
, rx_status
, dev
, "dma_flag=0x%x\n",
1346 (unsigned int)dma_flag
);
1347 if (dma_flag
& DMA_RX_CRC_ERROR
)
1348 dev
->stats
.rx_crc_errors
++;
1349 if (dma_flag
& DMA_RX_OV
)
1350 dev
->stats
.rx_over_errors
++;
1351 if (dma_flag
& DMA_RX_NO
)
1352 dev
->stats
.rx_frame_errors
++;
1353 if (dma_flag
& DMA_RX_LG
)
1354 dev
->stats
.rx_length_errors
++;
1355 dev
->stats
.rx_dropped
++;
1356 dev
->stats
.rx_errors
++;
1358 /* discard the packet and advance consumer index.*/
1359 dev_kfree_skb_any(cb
->skb
);
1362 } /* error packet */
1364 chksum_ok
= (dma_flag
& priv
->dma_rx_chk_bit
) &&
1365 priv
->desc_rxchk_en
;
1368 if (priv
->desc_64b_en
) {
1373 if (likely(chksum_ok
))
1374 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1376 /* remove hardware 2bytes added for IP alignment */
1380 if (priv
->crc_fwd_en
) {
1381 skb_trim(skb
, len
- ETH_FCS_LEN
);
1385 /*Finish setting up the received SKB and send it to the kernel*/
1386 skb
->protocol
= eth_type_trans(skb
, priv
->dev
);
1387 dev
->stats
.rx_packets
++;
1388 dev
->stats
.rx_bytes
+= len
;
1389 if (dma_flag
& DMA_RX_MULT
)
1390 dev
->stats
.multicast
++;
1393 napi_gro_receive(&priv
->napi
, skb
);
1395 netif_dbg(priv
, rx_status
, dev
, "pushed up to kernel\n");
1397 /* refill RX path on the current control block */
1399 err
= bcmgenet_rx_refill(priv
, cb
);
1401 netif_err(priv
, rx_err
, dev
, "Rx refill failed\n");
1404 return rxpktprocessed
;
1407 /* Assign skb to RX DMA descriptor. */
1408 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv
*priv
)
1414 netif_dbg(priv
, hw
, priv
->dev
, "%s:\n", __func__
);
1416 /* loop here for each buffer needing assign */
1417 for (i
= 0; i
< priv
->num_rx_bds
; i
++) {
1418 cb
= &priv
->rx_cbs
[priv
->rx_bd_assign_index
];
1422 ret
= bcmgenet_rx_refill(priv
, cb
);
1430 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv
*priv
)
1435 for (i
= 0; i
< priv
->num_rx_bds
; i
++) {
1436 cb
= &priv
->rx_cbs
[i
];
1438 if (dma_unmap_addr(cb
, dma_addr
)) {
1439 dma_unmap_single(&priv
->dev
->dev
,
1440 dma_unmap_addr(cb
, dma_addr
),
1441 priv
->rx_buf_len
, DMA_FROM_DEVICE
);
1442 dma_unmap_addr_set(cb
, dma_addr
, 0);
1446 bcmgenet_free_cb(cb
);
1450 static void umac_enable_set(struct bcmgenet_priv
*priv
, u32 mask
, bool enable
)
1454 reg
= bcmgenet_umac_readl(priv
, UMAC_CMD
);
1459 bcmgenet_umac_writel(priv
, reg
, UMAC_CMD
);
1461 /* UniMAC stops on a packet boundary, wait for a full-size packet
1465 usleep_range(1000, 2000);
1468 static int reset_umac(struct bcmgenet_priv
*priv
)
1470 struct device
*kdev
= &priv
->pdev
->dev
;
1471 unsigned int timeout
= 0;
1474 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1475 bcmgenet_rbuf_ctrl_set(priv
, 0);
1478 /* disable MAC while updating its registers */
1479 bcmgenet_umac_writel(priv
, 0, UMAC_CMD
);
1481 /* issue soft reset, wait for it to complete */
1482 bcmgenet_umac_writel(priv
, CMD_SW_RESET
, UMAC_CMD
);
1483 while (timeout
++ < 1000) {
1484 reg
= bcmgenet_umac_readl(priv
, UMAC_CMD
);
1485 if (!(reg
& CMD_SW_RESET
))
1491 if (timeout
== 1000) {
1493 "timeout waiting for MAC to come out of reset\n");
1500 static void bcmgenet_intr_disable(struct bcmgenet_priv
*priv
)
1502 /* Mask all interrupts.*/
1503 bcmgenet_intrl2_0_writel(priv
, 0xFFFFFFFF, INTRL2_CPU_MASK_SET
);
1504 bcmgenet_intrl2_0_writel(priv
, 0xFFFFFFFF, INTRL2_CPU_CLEAR
);
1505 bcmgenet_intrl2_0_writel(priv
, 0, INTRL2_CPU_MASK_CLEAR
);
1506 bcmgenet_intrl2_1_writel(priv
, 0xFFFFFFFF, INTRL2_CPU_MASK_SET
);
1507 bcmgenet_intrl2_1_writel(priv
, 0xFFFFFFFF, INTRL2_CPU_CLEAR
);
1508 bcmgenet_intrl2_1_writel(priv
, 0, INTRL2_CPU_MASK_CLEAR
);
1511 static int init_umac(struct bcmgenet_priv
*priv
)
1513 struct device
*kdev
= &priv
->pdev
->dev
;
1515 u32 reg
, cpu_mask_clear
;
1517 dev_dbg(&priv
->pdev
->dev
, "bcmgenet: init_umac\n");
1519 ret
= reset_umac(priv
);
1523 bcmgenet_umac_writel(priv
, 0, UMAC_CMD
);
1524 /* clear tx/rx counter */
1525 bcmgenet_umac_writel(priv
,
1526 MIB_RESET_RX
| MIB_RESET_TX
| MIB_RESET_RUNT
,
1528 bcmgenet_umac_writel(priv
, 0, UMAC_MIB_CTRL
);
1530 bcmgenet_umac_writel(priv
, ENET_MAX_MTU_SIZE
, UMAC_MAX_FRAME_LEN
);
1532 /* init rx registers, enable ip header optimization */
1533 reg
= bcmgenet_rbuf_readl(priv
, RBUF_CTRL
);
1534 reg
|= RBUF_ALIGN_2B
;
1535 bcmgenet_rbuf_writel(priv
, reg
, RBUF_CTRL
);
1537 if (!GENET_IS_V1(priv
) && !GENET_IS_V2(priv
))
1538 bcmgenet_rbuf_writel(priv
, 1, RBUF_TBUF_SIZE_CTRL
);
1540 bcmgenet_intr_disable(priv
);
1542 cpu_mask_clear
= UMAC_IRQ_RXDMA_BDONE
;
1544 dev_dbg(kdev
, "%s:Enabling RXDMA_BDONE interrupt\n", __func__
);
1546 /* Monitor cable plug/unplugged event for internal PHY */
1547 if (phy_is_internal(priv
->phydev
)) {
1548 cpu_mask_clear
|= (UMAC_IRQ_LINK_DOWN
| UMAC_IRQ_LINK_UP
);
1549 } else if (priv
->ext_phy
) {
1550 cpu_mask_clear
|= (UMAC_IRQ_LINK_DOWN
| UMAC_IRQ_LINK_UP
);
1551 } else if (priv
->phy_interface
== PHY_INTERFACE_MODE_MOCA
) {
1552 reg
= bcmgenet_bp_mc_get(priv
);
1553 reg
|= BIT(priv
->hw_params
->bp_in_en_shift
);
1555 /* bp_mask: back pressure mask */
1556 if (netif_is_multiqueue(priv
->dev
))
1557 reg
|= priv
->hw_params
->bp_in_mask
;
1559 reg
&= ~priv
->hw_params
->bp_in_mask
;
1560 bcmgenet_bp_mc_set(priv
, reg
);
1563 /* Enable MDIO interrupts on GENET v3+ */
1564 if (priv
->hw_params
->flags
& GENET_HAS_MDIO_INTR
)
1565 cpu_mask_clear
|= UMAC_IRQ_MDIO_DONE
| UMAC_IRQ_MDIO_ERROR
;
1567 bcmgenet_intrl2_0_writel(priv
, cpu_mask_clear
, INTRL2_CPU_MASK_CLEAR
);
1569 /* Enable rx/tx engine.*/
1570 dev_dbg(kdev
, "done init umac\n");
1575 /* Initialize all house-keeping variables for a TX ring, along
1576 * with corresponding hardware registers
1578 static void bcmgenet_init_tx_ring(struct bcmgenet_priv
*priv
,
1579 unsigned int index
, unsigned int size
,
1580 unsigned int write_ptr
, unsigned int end_ptr
)
1582 struct bcmgenet_tx_ring
*ring
= &priv
->tx_rings
[index
];
1583 u32 words_per_bd
= WORDS_PER_BD(priv
);
1584 u32 flow_period_val
= 0;
1585 unsigned int first_bd
;
1587 spin_lock_init(&ring
->lock
);
1588 ring
->index
= index
;
1589 if (index
== DESC_INDEX
) {
1591 ring
->int_enable
= bcmgenet_tx_ring16_int_enable
;
1592 ring
->int_disable
= bcmgenet_tx_ring16_int_disable
;
1594 ring
->queue
= index
+ 1;
1595 ring
->int_enable
= bcmgenet_tx_ring_int_enable
;
1596 ring
->int_disable
= bcmgenet_tx_ring_int_disable
;
1598 ring
->cbs
= priv
->tx_cbs
+ write_ptr
;
1601 ring
->free_bds
= size
;
1602 ring
->write_ptr
= write_ptr
;
1603 ring
->cb_ptr
= write_ptr
;
1604 ring
->end_ptr
= end_ptr
- 1;
1605 ring
->prod_index
= 0;
1607 /* Set flow period for ring != 16 */
1608 if (index
!= DESC_INDEX
)
1609 flow_period_val
= ENET_MAX_MTU_SIZE
<< 16;
1611 bcmgenet_tdma_ring_writel(priv
, index
, 0, TDMA_PROD_INDEX
);
1612 bcmgenet_tdma_ring_writel(priv
, index
, 0, TDMA_CONS_INDEX
);
1613 bcmgenet_tdma_ring_writel(priv
, index
, 1, DMA_MBUF_DONE_THRESH
);
1614 /* Disable rate control for now */
1615 bcmgenet_tdma_ring_writel(priv
, index
, flow_period_val
,
1617 /* Unclassified traffic goes to ring 16 */
1618 bcmgenet_tdma_ring_writel(priv
, index
,
1619 ((size
<< DMA_RING_SIZE_SHIFT
) |
1620 RX_BUF_LENGTH
), DMA_RING_BUF_SIZE
);
1622 first_bd
= write_ptr
;
1624 /* Set start and end address, read and write pointers */
1625 bcmgenet_tdma_ring_writel(priv
, index
, first_bd
* words_per_bd
,
1627 bcmgenet_tdma_ring_writel(priv
, index
, first_bd
* words_per_bd
,
1629 bcmgenet_tdma_ring_writel(priv
, index
, first_bd
,
1631 bcmgenet_tdma_ring_writel(priv
, index
, end_ptr
* words_per_bd
- 1,
1635 /* Initialize a RDMA ring */
1636 static int bcmgenet_init_rx_ring(struct bcmgenet_priv
*priv
,
1637 unsigned int index
, unsigned int size
)
1639 u32 words_per_bd
= WORDS_PER_BD(priv
);
1642 priv
->num_rx_bds
= TOTAL_DESC
;
1643 priv
->rx_bds
= priv
->base
+ priv
->hw_params
->rdma_offset
;
1644 priv
->rx_bd_assign_ptr
= priv
->rx_bds
;
1645 priv
->rx_bd_assign_index
= 0;
1646 priv
->rx_c_index
= 0;
1647 priv
->rx_read_ptr
= 0;
1648 priv
->rx_cbs
= kcalloc(priv
->num_rx_bds
, sizeof(struct enet_cb
),
1653 ret
= bcmgenet_alloc_rx_buffers(priv
);
1655 kfree(priv
->rx_cbs
);
1659 bcmgenet_rdma_ring_writel(priv
, index
, 0, RDMA_WRITE_PTR
);
1660 bcmgenet_rdma_ring_writel(priv
, index
, 0, RDMA_PROD_INDEX
);
1661 bcmgenet_rdma_ring_writel(priv
, index
, 0, RDMA_CONS_INDEX
);
1662 bcmgenet_rdma_ring_writel(priv
, index
,
1663 ((size
<< DMA_RING_SIZE_SHIFT
) |
1664 RX_BUF_LENGTH
), DMA_RING_BUF_SIZE
);
1665 bcmgenet_rdma_ring_writel(priv
, index
, 0, DMA_START_ADDR
);
1666 bcmgenet_rdma_ring_writel(priv
, index
,
1667 words_per_bd
* size
- 1, DMA_END_ADDR
);
1668 bcmgenet_rdma_ring_writel(priv
, index
,
1669 (DMA_FC_THRESH_LO
<<
1670 DMA_XOFF_THRESHOLD_SHIFT
) |
1671 DMA_FC_THRESH_HI
, RDMA_XON_XOFF_THRESH
);
1672 bcmgenet_rdma_ring_writel(priv
, index
, 0, RDMA_READ_PTR
);
1677 /* init multi xmit queues, only available for GENET2+
1678 * the queue is partitioned as follows:
1680 * queue 0 - 3 is priority based, each one has 32 descriptors,
1681 * with queue 0 being the highest priority queue.
1683 * queue 16 is the default tx queue with GENET_DEFAULT_BD_CNT
1684 * descriptors: 256 - (number of tx queues * bds per queues) = 128
1687 * The transmit control block pool is then partitioned as following:
1688 * - tx_cbs[0...127] are for queue 16
1689 * - tx_ring_cbs[0] points to tx_cbs[128..159]
1690 * - tx_ring_cbs[1] points to tx_cbs[160..191]
1691 * - tx_ring_cbs[2] points to tx_cbs[192..223]
1692 * - tx_ring_cbs[3] points to tx_cbs[224..255]
1694 static void bcmgenet_init_multiq(struct net_device
*dev
)
1696 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
1697 unsigned int i
, dma_enable
;
1698 u32 reg
, dma_ctrl
, ring_cfg
= 0, dma_priority
= 0;
1700 if (!netif_is_multiqueue(dev
)) {
1701 netdev_warn(dev
, "called with non multi queue aware HW\n");
1705 dma_ctrl
= bcmgenet_tdma_readl(priv
, DMA_CTRL
);
1706 dma_enable
= dma_ctrl
& DMA_EN
;
1707 dma_ctrl
&= ~DMA_EN
;
1708 bcmgenet_tdma_writel(priv
, dma_ctrl
, DMA_CTRL
);
1710 /* Enable strict priority arbiter mode */
1711 bcmgenet_tdma_writel(priv
, DMA_ARBITER_SP
, DMA_ARB_CTRL
);
1713 for (i
= 0; i
< priv
->hw_params
->tx_queues
; i
++) {
1714 /* first 64 tx_cbs are reserved for default tx queue
1717 bcmgenet_init_tx_ring(priv
, i
, priv
->hw_params
->bds_cnt
,
1718 i
* priv
->hw_params
->bds_cnt
,
1719 (i
+ 1) * priv
->hw_params
->bds_cnt
);
1721 /* Configure ring as descriptor ring and setup priority */
1723 dma_priority
|= ((GENET_Q0_PRIORITY
+ i
) <<
1724 (GENET_MAX_MQ_CNT
+ 1) * i
);
1725 dma_ctrl
|= 1 << (i
+ DMA_RING_BUF_EN_SHIFT
);
1729 reg
= bcmgenet_tdma_readl(priv
, DMA_RING_CFG
);
1731 bcmgenet_tdma_writel(priv
, reg
, DMA_RING_CFG
);
1733 /* Use configured rings priority and set ring #16 priority */
1734 reg
= bcmgenet_tdma_readl(priv
, DMA_RING_PRIORITY
);
1735 reg
|= ((GENET_Q0_PRIORITY
+ priv
->hw_params
->tx_queues
) << 20);
1736 reg
|= dma_priority
;
1737 bcmgenet_tdma_writel(priv
, reg
, DMA_PRIORITY
);
1739 /* Configure ring as descriptor ring and re-enable DMA if enabled */
1740 reg
= bcmgenet_tdma_readl(priv
, DMA_CTRL
);
1744 bcmgenet_tdma_writel(priv
, reg
, DMA_CTRL
);
1747 static int bcmgenet_dma_teardown(struct bcmgenet_priv
*priv
)
1753 /* Disable TDMA to stop add more frames in TX DMA */
1754 reg
= bcmgenet_tdma_readl(priv
, DMA_CTRL
);
1756 bcmgenet_tdma_writel(priv
, reg
, DMA_CTRL
);
1758 /* Check TDMA status register to confirm TDMA is disabled */
1759 while (timeout
++ < DMA_TIMEOUT_VAL
) {
1760 reg
= bcmgenet_tdma_readl(priv
, DMA_STATUS
);
1761 if (reg
& DMA_DISABLED
)
1767 if (timeout
== DMA_TIMEOUT_VAL
) {
1768 netdev_warn(priv
->dev
, "Timed out while disabling TX DMA\n");
1772 /* Wait 10ms for packet drain in both tx and rx dma */
1773 usleep_range(10000, 20000);
1776 reg
= bcmgenet_rdma_readl(priv
, DMA_CTRL
);
1778 bcmgenet_rdma_writel(priv
, reg
, DMA_CTRL
);
1781 /* Check RDMA status register to confirm RDMA is disabled */
1782 while (timeout
++ < DMA_TIMEOUT_VAL
) {
1783 reg
= bcmgenet_rdma_readl(priv
, DMA_STATUS
);
1784 if (reg
& DMA_DISABLED
)
1790 if (timeout
== DMA_TIMEOUT_VAL
) {
1791 netdev_warn(priv
->dev
, "Timed out while disabling RX DMA\n");
1798 static void bcmgenet_fini_dma(struct bcmgenet_priv
*priv
)
1803 bcmgenet_dma_teardown(priv
);
1805 for (i
= 0; i
< priv
->num_tx_bds
; i
++) {
1806 if (priv
->tx_cbs
[i
].skb
!= NULL
) {
1807 dev_kfree_skb(priv
->tx_cbs
[i
].skb
);
1808 priv
->tx_cbs
[i
].skb
= NULL
;
1812 bcmgenet_free_rx_buffers(priv
);
1813 kfree(priv
->rx_cbs
);
1814 kfree(priv
->tx_cbs
);
1817 /* init_edma: Initialize DMA control register */
1818 static int bcmgenet_init_dma(struct bcmgenet_priv
*priv
)
1822 netif_dbg(priv
, hw
, priv
->dev
, "bcmgenet: init_edma\n");
1824 /* by default, enable ring 16 (descriptor based) */
1825 ret
= bcmgenet_init_rx_ring(priv
, DESC_INDEX
, TOTAL_DESC
);
1827 netdev_err(priv
->dev
, "failed to initialize RX ring\n");
1832 bcmgenet_rdma_writel(priv
, DMA_MAX_BURST_LENGTH
, DMA_SCB_BURST_SIZE
);
1835 bcmgenet_tdma_writel(priv
, DMA_MAX_BURST_LENGTH
, DMA_SCB_BURST_SIZE
);
1837 /* Initialize common TX ring structures */
1838 priv
->tx_bds
= priv
->base
+ priv
->hw_params
->tdma_offset
;
1839 priv
->num_tx_bds
= TOTAL_DESC
;
1840 priv
->tx_cbs
= kcalloc(priv
->num_tx_bds
, sizeof(struct enet_cb
),
1842 if (!priv
->tx_cbs
) {
1843 bcmgenet_fini_dma(priv
);
1847 /* initialize multi xmit queue */
1848 bcmgenet_init_multiq(priv
->dev
);
1850 /* initialize special ring 16 */
1851 bcmgenet_init_tx_ring(priv
, DESC_INDEX
, GENET_DEFAULT_BD_CNT
,
1852 priv
->hw_params
->tx_queues
*
1853 priv
->hw_params
->bds_cnt
,
1859 /* NAPI polling method*/
1860 static int bcmgenet_poll(struct napi_struct
*napi
, int budget
)
1862 struct bcmgenet_priv
*priv
= container_of(napi
,
1863 struct bcmgenet_priv
, napi
);
1864 unsigned int work_done
;
1867 bcmgenet_tx_reclaim(priv
->dev
, &priv
->tx_rings
[DESC_INDEX
]);
1869 work_done
= bcmgenet_desc_rx(priv
, budget
);
1871 /* Advancing our consumer index*/
1872 priv
->rx_c_index
+= work_done
;
1873 priv
->rx_c_index
&= DMA_C_INDEX_MASK
;
1874 bcmgenet_rdma_ring_writel(priv
, DESC_INDEX
,
1875 priv
->rx_c_index
, RDMA_CONS_INDEX
);
1876 if (work_done
< budget
) {
1877 napi_complete(napi
);
1878 bcmgenet_intrl2_0_writel(priv
, UMAC_IRQ_RXDMA_BDONE
,
1879 INTRL2_CPU_MASK_CLEAR
);
1885 /* Interrupt bottom half */
1886 static void bcmgenet_irq_task(struct work_struct
*work
)
1888 struct bcmgenet_priv
*priv
= container_of(
1889 work
, struct bcmgenet_priv
, bcmgenet_irq_work
);
1891 netif_dbg(priv
, intr
, priv
->dev
, "%s\n", __func__
);
1893 if (priv
->irq0_stat
& UMAC_IRQ_MPD_R
) {
1894 priv
->irq0_stat
&= ~UMAC_IRQ_MPD_R
;
1895 netif_dbg(priv
, wol
, priv
->dev
,
1896 "magic packet detected, waking up\n");
1897 bcmgenet_power_up(priv
, GENET_POWER_WOL_MAGIC
);
1900 /* Link UP/DOWN event */
1901 if ((priv
->hw_params
->flags
& GENET_HAS_MDIO_INTR
) &&
1902 (priv
->irq0_stat
& (UMAC_IRQ_LINK_UP
|UMAC_IRQ_LINK_DOWN
))) {
1903 phy_mac_interrupt(priv
->phydev
,
1904 priv
->irq0_stat
& UMAC_IRQ_LINK_UP
);
1905 priv
->irq0_stat
&= ~(UMAC_IRQ_LINK_UP
|UMAC_IRQ_LINK_DOWN
);
1909 /* bcmgenet_isr1: interrupt handler for ring buffer. */
1910 static irqreturn_t
bcmgenet_isr1(int irq
, void *dev_id
)
1912 struct bcmgenet_priv
*priv
= dev_id
;
1915 /* Save irq status for bottom-half processing. */
1917 bcmgenet_intrl2_1_readl(priv
, INTRL2_CPU_STAT
) &
1919 /* clear interrupts */
1920 bcmgenet_intrl2_1_writel(priv
, priv
->irq1_stat
, INTRL2_CPU_CLEAR
);
1922 netif_dbg(priv
, intr
, priv
->dev
,
1923 "%s: IRQ=0x%x\n", __func__
, priv
->irq1_stat
);
1924 /* Check the MBDONE interrupts.
1925 * packet is done, reclaim descriptors
1927 if (priv
->irq1_stat
& 0x0000ffff) {
1929 for (index
= 0; index
< 16; index
++) {
1930 if (priv
->irq1_stat
& (1 << index
))
1931 bcmgenet_tx_reclaim(priv
->dev
,
1932 &priv
->tx_rings
[index
]);
1938 /* bcmgenet_isr0: Handle various interrupts. */
1939 static irqreturn_t
bcmgenet_isr0(int irq
, void *dev_id
)
1941 struct bcmgenet_priv
*priv
= dev_id
;
1943 /* Save irq status for bottom-half processing. */
1945 bcmgenet_intrl2_0_readl(priv
, INTRL2_CPU_STAT
) &
1946 ~bcmgenet_intrl2_0_readl(priv
, INTRL2_CPU_MASK_STATUS
);
1947 /* clear interrupts */
1948 bcmgenet_intrl2_0_writel(priv
, priv
->irq0_stat
, INTRL2_CPU_CLEAR
);
1950 netif_dbg(priv
, intr
, priv
->dev
,
1951 "IRQ=0x%x\n", priv
->irq0_stat
);
1953 if (priv
->irq0_stat
& (UMAC_IRQ_RXDMA_BDONE
| UMAC_IRQ_RXDMA_PDONE
)) {
1954 /* We use NAPI(software interrupt throttling, if
1955 * Rx Descriptor throttling is not used.
1956 * Disable interrupt, will be enabled in the poll method.
1958 if (likely(napi_schedule_prep(&priv
->napi
))) {
1959 bcmgenet_intrl2_0_writel(priv
, UMAC_IRQ_RXDMA_BDONE
,
1960 INTRL2_CPU_MASK_SET
);
1961 __napi_schedule(&priv
->napi
);
1964 if (priv
->irq0_stat
&
1965 (UMAC_IRQ_TXDMA_BDONE
| UMAC_IRQ_TXDMA_PDONE
)) {
1967 bcmgenet_tx_reclaim(priv
->dev
, &priv
->tx_rings
[DESC_INDEX
]);
1969 if (priv
->irq0_stat
& (UMAC_IRQ_PHY_DET_R
|
1970 UMAC_IRQ_PHY_DET_F
|
1972 UMAC_IRQ_LINK_DOWN
|
1976 /* all other interested interrupts handled in bottom half */
1977 schedule_work(&priv
->bcmgenet_irq_work
);
1980 if ((priv
->hw_params
->flags
& GENET_HAS_MDIO_INTR
) &&
1981 priv
->irq0_stat
& (UMAC_IRQ_MDIO_DONE
| UMAC_IRQ_MDIO_ERROR
)) {
1982 priv
->irq0_stat
&= ~(UMAC_IRQ_MDIO_DONE
| UMAC_IRQ_MDIO_ERROR
);
1989 static irqreturn_t
bcmgenet_wol_isr(int irq
, void *dev_id
)
1991 struct bcmgenet_priv
*priv
= dev_id
;
1993 pm_wakeup_event(&priv
->pdev
->dev
, 0);
1998 static void bcmgenet_umac_reset(struct bcmgenet_priv
*priv
)
2002 reg
= bcmgenet_rbuf_ctrl_get(priv
);
2004 bcmgenet_rbuf_ctrl_set(priv
, reg
);
2008 bcmgenet_rbuf_ctrl_set(priv
, reg
);
2012 static void bcmgenet_set_hw_addr(struct bcmgenet_priv
*priv
,
2013 unsigned char *addr
)
2015 bcmgenet_umac_writel(priv
, (addr
[0] << 24) | (addr
[1] << 16) |
2016 (addr
[2] << 8) | addr
[3], UMAC_MAC0
);
2017 bcmgenet_umac_writel(priv
, (addr
[4] << 8) | addr
[5], UMAC_MAC1
);
2020 static int bcmgenet_wol_resume(struct bcmgenet_priv
*priv
)
2022 /* From WOL-enabled suspend, switch to regular clock */
2024 clk_disable_unprepare(priv
->clk_wol
);
2026 phy_init_hw(priv
->phydev
);
2027 /* Speed settings must be restored */
2028 bcmgenet_mii_config(priv
->dev
);
2033 /* Returns a reusable dma control register value */
2034 static u32
bcmgenet_dma_disable(struct bcmgenet_priv
*priv
)
2040 dma_ctrl
= 1 << (DESC_INDEX
+ DMA_RING_BUF_EN_SHIFT
) | DMA_EN
;
2041 reg
= bcmgenet_tdma_readl(priv
, DMA_CTRL
);
2043 bcmgenet_tdma_writel(priv
, reg
, DMA_CTRL
);
2045 reg
= bcmgenet_rdma_readl(priv
, DMA_CTRL
);
2047 bcmgenet_rdma_writel(priv
, reg
, DMA_CTRL
);
2049 bcmgenet_umac_writel(priv
, 1, UMAC_TX_FLUSH
);
2051 bcmgenet_umac_writel(priv
, 0, UMAC_TX_FLUSH
);
2056 static void bcmgenet_enable_dma(struct bcmgenet_priv
*priv
, u32 dma_ctrl
)
2060 reg
= bcmgenet_rdma_readl(priv
, DMA_CTRL
);
2062 bcmgenet_rdma_writel(priv
, reg
, DMA_CTRL
);
2064 reg
= bcmgenet_tdma_readl(priv
, DMA_CTRL
);
2066 bcmgenet_tdma_writel(priv
, reg
, DMA_CTRL
);
2069 static void bcmgenet_netif_start(struct net_device
*dev
)
2071 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
2073 /* Start the network engine */
2074 napi_enable(&priv
->napi
);
2076 umac_enable_set(priv
, CMD_TX_EN
| CMD_RX_EN
, true);
2078 if (phy_is_internal(priv
->phydev
))
2079 bcmgenet_power_up(priv
, GENET_POWER_PASSIVE
);
2081 netif_tx_start_all_queues(dev
);
2083 phy_start(priv
->phydev
);
2086 static int bcmgenet_open(struct net_device
*dev
)
2088 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
2089 unsigned long dma_ctrl
;
2093 netif_dbg(priv
, ifup
, dev
, "bcmgenet_open\n");
2095 /* Turn on the clock */
2096 if (!IS_ERR(priv
->clk
))
2097 clk_prepare_enable(priv
->clk
);
2099 /* take MAC out of reset */
2100 bcmgenet_umac_reset(priv
);
2102 ret
= init_umac(priv
);
2104 goto err_clk_disable
;
2106 /* disable ethernet MAC while updating its registers */
2107 umac_enable_set(priv
, CMD_TX_EN
| CMD_RX_EN
, false);
2109 /* Make sure we reflect the value of CRC_CMD_FWD */
2110 reg
= bcmgenet_umac_readl(priv
, UMAC_CMD
);
2111 priv
->crc_fwd_en
= !!(reg
& CMD_CRC_FWD
);
2113 bcmgenet_set_hw_addr(priv
, dev
->dev_addr
);
2115 if (phy_is_internal(priv
->phydev
)) {
2116 reg
= bcmgenet_ext_readl(priv
, EXT_EXT_PWR_MGMT
);
2117 reg
|= EXT_ENERGY_DET_MASK
;
2118 bcmgenet_ext_writel(priv
, reg
, EXT_EXT_PWR_MGMT
);
2121 /* Disable RX/TX DMA and flush TX queues */
2122 dma_ctrl
= bcmgenet_dma_disable(priv
);
2124 /* Reinitialize TDMA and RDMA and SW housekeeping */
2125 ret
= bcmgenet_init_dma(priv
);
2127 netdev_err(dev
, "failed to initialize DMA\n");
2131 /* Always enable ring 16 - descriptor ring */
2132 bcmgenet_enable_dma(priv
, dma_ctrl
);
2134 ret
= request_irq(priv
->irq0
, bcmgenet_isr0
, IRQF_SHARED
,
2137 netdev_err(dev
, "can't request IRQ %d\n", priv
->irq0
);
2141 ret
= request_irq(priv
->irq1
, bcmgenet_isr1
, IRQF_SHARED
,
2144 netdev_err(dev
, "can't request IRQ %d\n", priv
->irq1
);
2148 bcmgenet_netif_start(dev
);
2153 free_irq(priv
->irq0
, dev
);
2155 bcmgenet_fini_dma(priv
);
2157 if (!IS_ERR(priv
->clk
))
2158 clk_disable_unprepare(priv
->clk
);
2162 static void bcmgenet_netif_stop(struct net_device
*dev
)
2164 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
2166 netif_tx_stop_all_queues(dev
);
2167 napi_disable(&priv
->napi
);
2168 phy_stop(priv
->phydev
);
2170 bcmgenet_intr_disable(priv
);
2172 /* Wait for pending work items to complete. Since interrupts are
2173 * disabled no new work will be scheduled.
2175 cancel_work_sync(&priv
->bcmgenet_irq_work
);
2177 priv
->old_pause
= -1;
2178 priv
->old_link
= -1;
2179 priv
->old_duplex
= -1;
2182 static int bcmgenet_close(struct net_device
*dev
)
2184 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
2187 netif_dbg(priv
, ifdown
, dev
, "bcmgenet_close\n");
2189 bcmgenet_netif_stop(dev
);
2191 /* Disable MAC receive */
2192 umac_enable_set(priv
, CMD_RX_EN
, false);
2194 ret
= bcmgenet_dma_teardown(priv
);
2198 /* Disable MAC transmit. TX DMA disabled have to done before this */
2199 umac_enable_set(priv
, CMD_TX_EN
, false);
2202 bcmgenet_tx_reclaim_all(dev
);
2203 bcmgenet_fini_dma(priv
);
2205 free_irq(priv
->irq0
, priv
);
2206 free_irq(priv
->irq1
, priv
);
2208 if (phy_is_internal(priv
->phydev
))
2209 bcmgenet_power_down(priv
, GENET_POWER_PASSIVE
);
2211 if (!IS_ERR(priv
->clk
))
2212 clk_disable_unprepare(priv
->clk
);
2217 static void bcmgenet_timeout(struct net_device
*dev
)
2219 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
2221 netif_dbg(priv
, tx_err
, dev
, "bcmgenet_timeout\n");
2223 dev
->trans_start
= jiffies
;
2225 dev
->stats
.tx_errors
++;
2227 netif_tx_wake_all_queues(dev
);
2230 #define MAX_MC_COUNT 16
2232 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv
*priv
,
2233 unsigned char *addr
,
2239 bcmgenet_umac_writel(priv
, addr
[0] << 8 | addr
[1],
2240 UMAC_MDF_ADDR
+ (*i
* 4));
2241 bcmgenet_umac_writel(priv
, addr
[2] << 24 | addr
[3] << 16 |
2242 addr
[4] << 8 | addr
[5],
2243 UMAC_MDF_ADDR
+ ((*i
+ 1) * 4));
2244 reg
= bcmgenet_umac_readl(priv
, UMAC_MDF_CTRL
);
2245 reg
|= (1 << (MAX_MC_COUNT
- *mc
));
2246 bcmgenet_umac_writel(priv
, reg
, UMAC_MDF_CTRL
);
2251 static void bcmgenet_set_rx_mode(struct net_device
*dev
)
2253 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
2254 struct netdev_hw_addr
*ha
;
2258 netif_dbg(priv
, hw
, dev
, "%s: %08X\n", __func__
, dev
->flags
);
2260 /* Promiscuous mode */
2261 reg
= bcmgenet_umac_readl(priv
, UMAC_CMD
);
2262 if (dev
->flags
& IFF_PROMISC
) {
2264 bcmgenet_umac_writel(priv
, reg
, UMAC_CMD
);
2265 bcmgenet_umac_writel(priv
, 0, UMAC_MDF_CTRL
);
2268 reg
&= ~CMD_PROMISC
;
2269 bcmgenet_umac_writel(priv
, reg
, UMAC_CMD
);
2272 /* UniMac doesn't support ALLMULTI */
2273 if (dev
->flags
& IFF_ALLMULTI
) {
2274 netdev_warn(dev
, "ALLMULTI is not supported\n");
2278 /* update MDF filter */
2282 bcmgenet_set_mdf_addr(priv
, dev
->broadcast
, &i
, &mc
);
2283 /* my own address.*/
2284 bcmgenet_set_mdf_addr(priv
, dev
->dev_addr
, &i
, &mc
);
2286 if (netdev_uc_count(dev
) > (MAX_MC_COUNT
- mc
))
2289 if (!netdev_uc_empty(dev
))
2290 netdev_for_each_uc_addr(ha
, dev
)
2291 bcmgenet_set_mdf_addr(priv
, ha
->addr
, &i
, &mc
);
2293 if (netdev_mc_empty(dev
) || netdev_mc_count(dev
) >= (MAX_MC_COUNT
- mc
))
2296 netdev_for_each_mc_addr(ha
, dev
)
2297 bcmgenet_set_mdf_addr(priv
, ha
->addr
, &i
, &mc
);
2300 /* Set the hardware MAC address. */
2301 static int bcmgenet_set_mac_addr(struct net_device
*dev
, void *p
)
2303 struct sockaddr
*addr
= p
;
2305 /* Setting the MAC address at the hardware level is not possible
2306 * without disabling the UniMAC RX/TX enable bits.
2308 if (netif_running(dev
))
2311 ether_addr_copy(dev
->dev_addr
, addr
->sa_data
);
2316 static const struct net_device_ops bcmgenet_netdev_ops
= {
2317 .ndo_open
= bcmgenet_open
,
2318 .ndo_stop
= bcmgenet_close
,
2319 .ndo_start_xmit
= bcmgenet_xmit
,
2320 .ndo_tx_timeout
= bcmgenet_timeout
,
2321 .ndo_set_rx_mode
= bcmgenet_set_rx_mode
,
2322 .ndo_set_mac_address
= bcmgenet_set_mac_addr
,
2323 .ndo_do_ioctl
= bcmgenet_ioctl
,
2324 .ndo_set_features
= bcmgenet_set_features
,
2327 /* Array of GENET hardware parameters/characteristics */
2328 static struct bcmgenet_hw_params bcmgenet_hw_params
[] = {
2333 .bp_in_en_shift
= 16,
2334 .bp_in_mask
= 0xffff,
2335 .hfb_filter_cnt
= 16,
2337 .hfb_offset
= 0x1000,
2338 .rdma_offset
= 0x2000,
2339 .tdma_offset
= 0x3000,
2346 .bp_in_en_shift
= 16,
2347 .bp_in_mask
= 0xffff,
2348 .hfb_filter_cnt
= 16,
2350 .tbuf_offset
= 0x0600,
2351 .hfb_offset
= 0x1000,
2352 .hfb_reg_offset
= 0x2000,
2353 .rdma_offset
= 0x3000,
2354 .tdma_offset
= 0x4000,
2356 .flags
= GENET_HAS_EXT
,
2362 .bp_in_en_shift
= 17,
2363 .bp_in_mask
= 0x1ffff,
2364 .hfb_filter_cnt
= 48,
2366 .tbuf_offset
= 0x0600,
2367 .hfb_offset
= 0x8000,
2368 .hfb_reg_offset
= 0xfc00,
2369 .rdma_offset
= 0x10000,
2370 .tdma_offset
= 0x11000,
2372 .flags
= GENET_HAS_EXT
| GENET_HAS_MDIO_INTR
,
2378 .bp_in_en_shift
= 17,
2379 .bp_in_mask
= 0x1ffff,
2380 .hfb_filter_cnt
= 48,
2382 .tbuf_offset
= 0x0600,
2383 .hfb_offset
= 0x8000,
2384 .hfb_reg_offset
= 0xfc00,
2385 .rdma_offset
= 0x2000,
2386 .tdma_offset
= 0x4000,
2388 .flags
= GENET_HAS_40BITS
| GENET_HAS_EXT
| GENET_HAS_MDIO_INTR
,
2392 /* Infer hardware parameters from the detected GENET version */
2393 static void bcmgenet_set_hw_params(struct bcmgenet_priv
*priv
)
2395 struct bcmgenet_hw_params
*params
;
2399 if (GENET_IS_V4(priv
)) {
2400 bcmgenet_dma_regs
= bcmgenet_dma_regs_v3plus
;
2401 genet_dma_ring_regs
= genet_dma_ring_regs_v4
;
2402 priv
->dma_rx_chk_bit
= DMA_RX_CHK_V3PLUS
;
2403 priv
->version
= GENET_V4
;
2404 } else if (GENET_IS_V3(priv
)) {
2405 bcmgenet_dma_regs
= bcmgenet_dma_regs_v3plus
;
2406 genet_dma_ring_regs
= genet_dma_ring_regs_v123
;
2407 priv
->dma_rx_chk_bit
= DMA_RX_CHK_V3PLUS
;
2408 priv
->version
= GENET_V3
;
2409 } else if (GENET_IS_V2(priv
)) {
2410 bcmgenet_dma_regs
= bcmgenet_dma_regs_v2
;
2411 genet_dma_ring_regs
= genet_dma_ring_regs_v123
;
2412 priv
->dma_rx_chk_bit
= DMA_RX_CHK_V12
;
2413 priv
->version
= GENET_V2
;
2414 } else if (GENET_IS_V1(priv
)) {
2415 bcmgenet_dma_regs
= bcmgenet_dma_regs_v1
;
2416 genet_dma_ring_regs
= genet_dma_ring_regs_v123
;
2417 priv
->dma_rx_chk_bit
= DMA_RX_CHK_V12
;
2418 priv
->version
= GENET_V1
;
2421 /* enum genet_version starts at 1 */
2422 priv
->hw_params
= &bcmgenet_hw_params
[priv
->version
];
2423 params
= priv
->hw_params
;
2425 /* Read GENET HW version */
2426 reg
= bcmgenet_sys_readl(priv
, SYS_REV_CTRL
);
2427 major
= (reg
>> 24 & 0x0f);
2430 else if (major
== 0)
2432 if (major
!= priv
->version
) {
2433 dev_err(&priv
->pdev
->dev
,
2434 "GENET version mismatch, got: %d, configured for: %d\n",
2435 major
, priv
->version
);
2438 /* Print the GENET core version */
2439 dev_info(&priv
->pdev
->dev
, "GENET " GENET_VER_FMT
,
2440 major
, (reg
>> 16) & 0x0f, reg
& 0xffff);
2442 #ifdef CONFIG_PHYS_ADDR_T_64BIT
2443 if (!(params
->flags
& GENET_HAS_40BITS
))
2444 pr_warn("GENET does not support 40-bits PA\n");
2447 pr_debug("Configuration for version: %d\n"
2448 "TXq: %1d, RXq: %1d, BDs: %1d\n"
2449 "BP << en: %2d, BP msk: 0x%05x\n"
2450 "HFB count: %2d, QTAQ msk: 0x%05x\n"
2451 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
2452 "RDMA: 0x%05x, TDMA: 0x%05x\n"
2455 params
->tx_queues
, params
->rx_queues
, params
->bds_cnt
,
2456 params
->bp_in_en_shift
, params
->bp_in_mask
,
2457 params
->hfb_filter_cnt
, params
->qtag_mask
,
2458 params
->tbuf_offset
, params
->hfb_offset
,
2459 params
->hfb_reg_offset
,
2460 params
->rdma_offset
, params
->tdma_offset
,
2461 params
->words_per_bd
);
2464 static const struct of_device_id bcmgenet_match
[] = {
2465 { .compatible
= "brcm,genet-v1", .data
= (void *)GENET_V1
},
2466 { .compatible
= "brcm,genet-v2", .data
= (void *)GENET_V2
},
2467 { .compatible
= "brcm,genet-v3", .data
= (void *)GENET_V3
},
2468 { .compatible
= "brcm,genet-v4", .data
= (void *)GENET_V4
},
2472 static int bcmgenet_probe(struct platform_device
*pdev
)
2474 struct device_node
*dn
= pdev
->dev
.of_node
;
2475 const struct of_device_id
*of_id
;
2476 struct bcmgenet_priv
*priv
;
2477 struct net_device
*dev
;
2478 const void *macaddr
;
2482 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and a single RX queue */
2483 dev
= alloc_etherdev_mqs(sizeof(*priv
), GENET_MAX_MQ_CNT
+ 1, 1);
2485 dev_err(&pdev
->dev
, "can't allocate net device\n");
2489 of_id
= of_match_node(bcmgenet_match
, dn
);
2493 priv
= netdev_priv(dev
);
2494 priv
->irq0
= platform_get_irq(pdev
, 0);
2495 priv
->irq1
= platform_get_irq(pdev
, 1);
2496 priv
->wol_irq
= platform_get_irq(pdev
, 2);
2497 if (!priv
->irq0
|| !priv
->irq1
) {
2498 dev_err(&pdev
->dev
, "can't find IRQs\n");
2503 macaddr
= of_get_mac_address(dn
);
2505 dev_err(&pdev
->dev
, "can't find MAC address\n");
2510 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2511 priv
->base
= devm_ioremap_resource(&pdev
->dev
, r
);
2512 if (IS_ERR(priv
->base
)) {
2513 err
= PTR_ERR(priv
->base
);
2517 SET_NETDEV_DEV(dev
, &pdev
->dev
);
2518 dev_set_drvdata(&pdev
->dev
, dev
);
2519 ether_addr_copy(dev
->dev_addr
, macaddr
);
2520 dev
->watchdog_timeo
= 2 * HZ
;
2521 dev
->ethtool_ops
= &bcmgenet_ethtool_ops
;
2522 dev
->netdev_ops
= &bcmgenet_netdev_ops
;
2523 netif_napi_add(dev
, &priv
->napi
, bcmgenet_poll
, 64);
2525 priv
->msg_enable
= netif_msg_init(-1, GENET_MSG_DEFAULT
);
2527 /* Set hardware features */
2528 dev
->hw_features
|= NETIF_F_SG
| NETIF_F_IP_CSUM
|
2529 NETIF_F_IPV6_CSUM
| NETIF_F_RXCSUM
;
2531 /* Request the WOL interrupt and advertise suspend if available */
2532 priv
->wol_irq_disabled
= true;
2533 err
= devm_request_irq(&pdev
->dev
, priv
->wol_irq
, bcmgenet_wol_isr
, 0,
2536 device_set_wakeup_capable(&pdev
->dev
, 1);
2538 /* Set the needed headroom to account for any possible
2539 * features enabling/disabling at runtime
2541 dev
->needed_headroom
+= 64;
2543 netdev_boot_setup_check(dev
);
2547 priv
->version
= (enum bcmgenet_version
)of_id
->data
;
2549 priv
->clk
= devm_clk_get(&priv
->pdev
->dev
, "enet");
2550 if (IS_ERR(priv
->clk
))
2551 dev_warn(&priv
->pdev
->dev
, "failed to get enet clock\n");
2553 if (!IS_ERR(priv
->clk
))
2554 clk_prepare_enable(priv
->clk
);
2556 bcmgenet_set_hw_params(priv
);
2558 /* Mii wait queue */
2559 init_waitqueue_head(&priv
->wq
);
2560 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
2561 priv
->rx_buf_len
= RX_BUF_LENGTH
;
2562 INIT_WORK(&priv
->bcmgenet_irq_work
, bcmgenet_irq_task
);
2564 priv
->clk_wol
= devm_clk_get(&priv
->pdev
->dev
, "enet-wol");
2565 if (IS_ERR(priv
->clk_wol
))
2566 dev_warn(&priv
->pdev
->dev
, "failed to get enet-wol clock\n");
2568 err
= reset_umac(priv
);
2570 goto err_clk_disable
;
2572 err
= bcmgenet_mii_init(dev
);
2574 goto err_clk_disable
;
2576 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues
2577 * just the ring 16 descriptor based TX
2579 netif_set_real_num_tx_queues(priv
->dev
, priv
->hw_params
->tx_queues
+ 1);
2580 netif_set_real_num_rx_queues(priv
->dev
, priv
->hw_params
->rx_queues
+ 1);
2582 /* libphy will determine the link state */
2583 netif_carrier_off(dev
);
2585 /* Turn off the main clock, WOL clock is handled separately */
2586 if (!IS_ERR(priv
->clk
))
2587 clk_disable_unprepare(priv
->clk
);
2589 err
= register_netdev(dev
);
2596 if (!IS_ERR(priv
->clk
))
2597 clk_disable_unprepare(priv
->clk
);
2603 static int bcmgenet_remove(struct platform_device
*pdev
)
2605 struct bcmgenet_priv
*priv
= dev_to_priv(&pdev
->dev
);
2607 dev_set_drvdata(&pdev
->dev
, NULL
);
2608 unregister_netdev(priv
->dev
);
2609 bcmgenet_mii_exit(priv
->dev
);
2610 free_netdev(priv
->dev
);
2615 #ifdef CONFIG_PM_SLEEP
2616 static int bcmgenet_suspend(struct device
*d
)
2618 struct net_device
*dev
= dev_get_drvdata(d
);
2619 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
2622 if (!netif_running(dev
))
2625 bcmgenet_netif_stop(dev
);
2627 phy_suspend(priv
->phydev
);
2629 netif_device_detach(dev
);
2631 /* Disable MAC receive */
2632 umac_enable_set(priv
, CMD_RX_EN
, false);
2634 ret
= bcmgenet_dma_teardown(priv
);
2638 /* Disable MAC transmit. TX DMA disabled have to done before this */
2639 umac_enable_set(priv
, CMD_TX_EN
, false);
2642 bcmgenet_tx_reclaim_all(dev
);
2643 bcmgenet_fini_dma(priv
);
2645 /* Prepare the device for Wake-on-LAN and switch to the slow clock */
2646 if (device_may_wakeup(d
) && priv
->wolopts
) {
2647 bcmgenet_power_down(priv
, GENET_POWER_WOL_MAGIC
);
2648 clk_prepare_enable(priv
->clk_wol
);
2651 /* Turn off the clocks */
2652 clk_disable_unprepare(priv
->clk
);
2657 static int bcmgenet_resume(struct device
*d
)
2659 struct net_device
*dev
= dev_get_drvdata(d
);
2660 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
2661 unsigned long dma_ctrl
;
2665 if (!netif_running(dev
))
2668 /* Turn on the clock */
2669 ret
= clk_prepare_enable(priv
->clk
);
2673 bcmgenet_umac_reset(priv
);
2675 ret
= init_umac(priv
);
2677 goto out_clk_disable
;
2679 ret
= bcmgenet_wol_resume(priv
);
2681 goto out_clk_disable
;
2683 /* disable ethernet MAC while updating its registers */
2684 umac_enable_set(priv
, CMD_TX_EN
| CMD_RX_EN
, false);
2686 bcmgenet_set_hw_addr(priv
, dev
->dev_addr
);
2688 if (phy_is_internal(priv
->phydev
)) {
2689 reg
= bcmgenet_ext_readl(priv
, EXT_EXT_PWR_MGMT
);
2690 reg
|= EXT_ENERGY_DET_MASK
;
2691 bcmgenet_ext_writel(priv
, reg
, EXT_EXT_PWR_MGMT
);
2695 bcmgenet_power_up(priv
, GENET_POWER_WOL_MAGIC
);
2697 /* Disable RX/TX DMA and flush TX queues */
2698 dma_ctrl
= bcmgenet_dma_disable(priv
);
2700 /* Reinitialize TDMA and RDMA and SW housekeeping */
2701 ret
= bcmgenet_init_dma(priv
);
2703 netdev_err(dev
, "failed to initialize DMA\n");
2704 goto out_clk_disable
;
2707 /* Always enable ring 16 - descriptor ring */
2708 bcmgenet_enable_dma(priv
, dma_ctrl
);
2710 netif_device_attach(dev
);
2712 phy_resume(priv
->phydev
);
2714 bcmgenet_netif_start(dev
);
2719 clk_disable_unprepare(priv
->clk
);
2722 #endif /* CONFIG_PM_SLEEP */
2724 static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops
, bcmgenet_suspend
, bcmgenet_resume
);
2726 static struct platform_driver bcmgenet_driver
= {
2727 .probe
= bcmgenet_probe
,
2728 .remove
= bcmgenet_remove
,
2731 .owner
= THIS_MODULE
,
2732 .of_match_table
= bcmgenet_match
,
2733 .pm
= &bcmgenet_pm_ops
,
2736 module_platform_driver(bcmgenet_driver
);
2738 MODULE_AUTHOR("Broadcom Corporation");
2739 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
2740 MODULE_ALIAS("platform:bcmgenet");
2741 MODULE_LICENSE("GPL");