1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2014-2017 Broadcom
9 #include <linux/skbuff.h>
10 #include <linux/netdevice.h>
11 #include <linux/spinlock.h>
12 #include <linux/clk.h>
13 #include <linux/mii.h>
14 #include <linux/if_vlan.h>
15 #include <linux/phy.h>
16 #include <linux/net_dim.h>
18 /* total number of Buffer Descriptors, same for Rx/Tx */
19 #define TOTAL_DESC 256
21 /* which ring is descriptor based */
24 /* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(6) + FCS(4) = 1528.
25 * 1536 is multiple of 256 bytes
27 #define ENET_BRCM_TAG_LEN 6
29 #define ENET_MAX_MTU_SIZE (ETH_DATA_LEN + ETH_HLEN + VLAN_HLEN + \
30 ENET_BRCM_TAG_LEN + ETH_FCS_LEN + ENET_PAD)
31 #define DMA_MAX_BURST_LENGTH 0x10
33 /* misc. configuration */
34 #define CLEAR_ALL_HFB 0xFF
35 #define DMA_FC_THRESH_HI (TOTAL_DESC >> 4)
36 #define DMA_FC_THRESH_LO 5
38 /* 64B receive/transmit status block */
40 u32 length_status
; /* length and peripheral status */
41 u32 ext_status
; /* Extended status*/
42 u32 rx_csum
; /* partial rx checksum */
43 u32 unused1
[9]; /* unused */
44 u32 tx_csum_info
; /* Tx checksum info. */
45 u32 unused2
[3]; /* unused */
49 #define STATUS_RX_EXT_MASK 0x1FFFFF
50 #define STATUS_RX_CSUM_MASK 0xFFFF
51 #define STATUS_RX_CSUM_OK 0x10000
52 #define STATUS_RX_CSUM_FR 0x20000
53 #define STATUS_RX_PROTO_TCP 0
54 #define STATUS_RX_PROTO_UDP 1
55 #define STATUS_RX_PROTO_ICMP 2
56 #define STATUS_RX_PROTO_OTHER 3
57 #define STATUS_RX_PROTO_MASK 3
58 #define STATUS_RX_PROTO_SHIFT 18
59 #define STATUS_FILTER_INDEX_MASK 0xFFFF
61 #define STATUS_TX_CSUM_START_MASK 0X7FFF
62 #define STATUS_TX_CSUM_START_SHIFT 16
63 #define STATUS_TX_CSUM_PROTO_UDP 0x8000
64 #define STATUS_TX_CSUM_OFFSET_MASK 0x7FFF
65 #define STATUS_TX_CSUM_LV 0x80000000
68 #define DMA_DESC_LENGTH_STATUS 0x00 /* in bytes of data in buffer */
69 #define DMA_DESC_ADDRESS_LO 0x04 /* lower bits of PA */
70 #define DMA_DESC_ADDRESS_HI 0x08 /* upper 32 bits of PA, GENETv4+ */
72 /* Rx/Tx common counter group */
73 struct bcmgenet_pkt_counters
{
74 u32 cnt_64
; /* RO Received/Transmited 64 bytes packet */
75 u32 cnt_127
; /* RO Rx/Tx 127 bytes packet */
76 u32 cnt_255
; /* RO Rx/Tx 65-255 bytes packet */
77 u32 cnt_511
; /* RO Rx/Tx 256-511 bytes packet */
78 u32 cnt_1023
; /* RO Rx/Tx 512-1023 bytes packet */
79 u32 cnt_1518
; /* RO Rx/Tx 1024-1518 bytes packet */
80 u32 cnt_mgv
; /* RO Rx/Tx 1519-1522 good VLAN packet */
81 u32 cnt_2047
; /* RO Rx/Tx 1522-2047 bytes packet*/
82 u32 cnt_4095
; /* RO Rx/Tx 2048-4095 bytes packet*/
83 u32 cnt_9216
; /* RO Rx/Tx 4096-9216 bytes packet*/
86 /* RSV, Receive Status Vector */
87 struct bcmgenet_rx_counters
{
88 struct bcmgenet_pkt_counters pkt_cnt
;
89 u32 pkt
; /* RO (0x428) Received pkt count*/
90 u32 bytes
; /* RO Received byte count */
91 u32 mca
; /* RO # of Received multicast pkt */
92 u32 bca
; /* RO # of Receive broadcast pkt */
93 u32 fcs
; /* RO # of Received FCS error */
94 u32 cf
; /* RO # of Received control frame pkt*/
95 u32 pf
; /* RO # of Received pause frame pkt */
96 u32 uo
; /* RO # of unknown op code pkt */
97 u32 aln
; /* RO # of alignment error count */
98 u32 flr
; /* RO # of frame length out of range count */
99 u32 cde
; /* RO # of code error pkt */
100 u32 fcr
; /* RO # of carrier sense error pkt */
101 u32 ovr
; /* RO # of oversize pkt*/
102 u32 jbr
; /* RO # of jabber count */
103 u32 mtue
; /* RO # of MTU error pkt*/
104 u32 pok
; /* RO # of Received good pkt */
105 u32 uc
; /* RO # of unicast pkt */
106 u32 ppp
; /* RO # of PPP pkt */
107 u32 rcrc
; /* RO (0x470),# of CRC match pkt */
110 /* TSV, Transmit Status Vector */
111 struct bcmgenet_tx_counters
{
112 struct bcmgenet_pkt_counters pkt_cnt
;
113 u32 pkts
; /* RO (0x4a8) Transmited pkt */
114 u32 mca
; /* RO # of xmited multicast pkt */
115 u32 bca
; /* RO # of xmited broadcast pkt */
116 u32 pf
; /* RO # of xmited pause frame count */
117 u32 cf
; /* RO # of xmited control frame count */
118 u32 fcs
; /* RO # of xmited FCS error count */
119 u32 ovr
; /* RO # of xmited oversize pkt */
120 u32 drf
; /* RO # of xmited deferral pkt */
121 u32 edf
; /* RO # of xmited Excessive deferral pkt*/
122 u32 scl
; /* RO # of xmited single collision pkt */
123 u32 mcl
; /* RO # of xmited multiple collision pkt*/
124 u32 lcl
; /* RO # of xmited late collision pkt */
125 u32 ecl
; /* RO # of xmited excessive collision pkt*/
126 u32 frg
; /* RO # of xmited fragments pkt*/
127 u32 ncl
; /* RO # of xmited total collision count */
128 u32 jbr
; /* RO # of xmited jabber count*/
129 u32 bytes
; /* RO # of xmited byte count */
130 u32 pok
; /* RO # of xmited good pkt */
131 u32 uc
; /* RO (0x0x4f0)# of xmited unitcast pkt */
134 struct bcmgenet_mib_counters
{
135 struct bcmgenet_rx_counters rx
;
136 struct bcmgenet_tx_counters tx
;
139 u32 rx_runt_fcs_align
;
144 u32 alloc_rx_buff_failed
;
149 #define UMAC_HD_BKP_CTRL 0x004
150 #define HD_FC_EN (1 << 0)
151 #define HD_FC_BKOFF_OK (1 << 1)
152 #define IPG_CONFIG_RX_SHIFT 2
153 #define IPG_CONFIG_RX_MASK 0x1F
155 #define UMAC_CMD 0x008
156 #define CMD_TX_EN (1 << 0)
157 #define CMD_RX_EN (1 << 1)
158 #define UMAC_SPEED_10 0
159 #define UMAC_SPEED_100 1
160 #define UMAC_SPEED_1000 2
161 #define UMAC_SPEED_2500 3
162 #define CMD_SPEED_SHIFT 2
163 #define CMD_SPEED_MASK 3
164 #define CMD_PROMISC (1 << 4)
165 #define CMD_PAD_EN (1 << 5)
166 #define CMD_CRC_FWD (1 << 6)
167 #define CMD_PAUSE_FWD (1 << 7)
168 #define CMD_RX_PAUSE_IGNORE (1 << 8)
169 #define CMD_TX_ADDR_INS (1 << 9)
170 #define CMD_HD_EN (1 << 10)
171 #define CMD_SW_RESET (1 << 13)
172 #define CMD_LCL_LOOP_EN (1 << 15)
173 #define CMD_AUTO_CONFIG (1 << 22)
174 #define CMD_CNTL_FRM_EN (1 << 23)
175 #define CMD_NO_LEN_CHK (1 << 24)
176 #define CMD_RMT_LOOP_EN (1 << 25)
177 #define CMD_PRBL_EN (1 << 27)
178 #define CMD_TX_PAUSE_IGNORE (1 << 28)
179 #define CMD_TX_RX_EN (1 << 29)
180 #define CMD_RUNT_FILTER_DIS (1 << 30)
182 #define UMAC_MAC0 0x00C
183 #define UMAC_MAC1 0x010
184 #define UMAC_MAX_FRAME_LEN 0x014
186 #define UMAC_MODE 0x44
187 #define MODE_LINK_STATUS (1 << 5)
189 #define UMAC_EEE_CTRL 0x064
190 #define EN_LPI_RX_PAUSE (1 << 0)
191 #define EN_LPI_TX_PFC (1 << 1)
192 #define EN_LPI_TX_PAUSE (1 << 2)
193 #define EEE_EN (1 << 3)
194 #define RX_FIFO_CHECK (1 << 4)
195 #define EEE_TX_CLK_DIS (1 << 5)
196 #define DIS_EEE_10M (1 << 6)
197 #define LP_IDLE_PREDICTION_MODE (1 << 7)
199 #define UMAC_EEE_LPI_TIMER 0x068
200 #define UMAC_EEE_WAKE_TIMER 0x06C
201 #define UMAC_EEE_REF_COUNT 0x070
202 #define EEE_REFERENCE_COUNT_MASK 0xffff
204 #define UMAC_TX_FLUSH 0x334
206 #define UMAC_MIB_START 0x400
208 #define UMAC_MDIO_CMD 0x614
209 #define MDIO_START_BUSY (1 << 29)
210 #define MDIO_READ_FAIL (1 << 28)
211 #define MDIO_RD (2 << 26)
212 #define MDIO_WR (1 << 26)
213 #define MDIO_PMD_SHIFT 21
214 #define MDIO_PMD_MASK 0x1F
215 #define MDIO_REG_SHIFT 16
216 #define MDIO_REG_MASK 0x1F
218 #define UMAC_RBUF_OVFL_CNT_V1 0x61C
219 #define RBUF_OVFL_CNT_V2 0x80
220 #define RBUF_OVFL_CNT_V3PLUS 0x94
222 #define UMAC_MPD_CTRL 0x620
223 #define MPD_EN (1 << 0)
224 #define MPD_PW_EN (1 << 27)
225 #define MPD_MSEQ_LEN_SHIFT 16
226 #define MPD_MSEQ_LEN_MASK 0xFF
228 #define UMAC_MPD_PW_MS 0x624
229 #define UMAC_MPD_PW_LS 0x628
230 #define UMAC_RBUF_ERR_CNT_V1 0x634
231 #define RBUF_ERR_CNT_V2 0x84
232 #define RBUF_ERR_CNT_V3PLUS 0x98
233 #define UMAC_MDF_ERR_CNT 0x638
234 #define UMAC_MDF_CTRL 0x650
235 #define UMAC_MDF_ADDR 0x654
236 #define UMAC_MIB_CTRL 0x580
237 #define MIB_RESET_RX (1 << 0)
238 #define MIB_RESET_RUNT (1 << 1)
239 #define MIB_RESET_TX (1 << 2)
241 #define RBUF_CTRL 0x00
242 #define RBUF_64B_EN (1 << 0)
243 #define RBUF_ALIGN_2B (1 << 1)
244 #define RBUF_BAD_DIS (1 << 2)
246 #define RBUF_STATUS 0x0C
247 #define RBUF_STATUS_WOL (1 << 0)
248 #define RBUF_STATUS_MPD_INTR_ACTIVE (1 << 1)
249 #define RBUF_STATUS_ACPI_INTR_ACTIVE (1 << 2)
251 #define RBUF_CHK_CTRL 0x14
252 #define RBUF_RXCHK_EN (1 << 0)
253 #define RBUF_SKIP_FCS (1 << 4)
255 #define RBUF_ENERGY_CTRL 0x9c
256 #define RBUF_EEE_EN (1 << 0)
257 #define RBUF_PM_EN (1 << 1)
259 #define RBUF_TBUF_SIZE_CTRL 0xb4
261 #define RBUF_HFB_CTRL_V1 0x38
262 #define RBUF_HFB_FILTER_EN_SHIFT 16
263 #define RBUF_HFB_FILTER_EN_MASK 0xffff0000
264 #define RBUF_HFB_EN (1 << 0)
265 #define RBUF_HFB_256B (1 << 1)
266 #define RBUF_ACPI_EN (1 << 2)
268 #define RBUF_HFB_LEN_V1 0x3C
269 #define RBUF_FLTR_LEN_MASK 0xFF
270 #define RBUF_FLTR_LEN_SHIFT 8
272 #define TBUF_CTRL 0x00
273 #define TBUF_BP_MC 0x0C
274 #define TBUF_ENERGY_CTRL 0x14
275 #define TBUF_EEE_EN (1 << 0)
276 #define TBUF_PM_EN (1 << 1)
278 #define TBUF_CTRL_V1 0x80
279 #define TBUF_BP_MC_V1 0xA0
281 #define HFB_CTRL 0x00
282 #define HFB_FLT_ENABLE_V3PLUS 0x04
283 #define HFB_FLT_LEN_V2 0x04
284 #define HFB_FLT_LEN_V3PLUS 0x1C
286 /* uniMac intrl2 registers */
287 #define INTRL2_CPU_STAT 0x00
288 #define INTRL2_CPU_SET 0x04
289 #define INTRL2_CPU_CLEAR 0x08
290 #define INTRL2_CPU_MASK_STATUS 0x0C
291 #define INTRL2_CPU_MASK_SET 0x10
292 #define INTRL2_CPU_MASK_CLEAR 0x14
294 /* INTRL2 instance 0 definitions */
295 #define UMAC_IRQ_SCB (1 << 0)
296 #define UMAC_IRQ_EPHY (1 << 1)
297 #define UMAC_IRQ_PHY_DET_R (1 << 2)
298 #define UMAC_IRQ_PHY_DET_F (1 << 3)
299 #define UMAC_IRQ_LINK_UP (1 << 4)
300 #define UMAC_IRQ_LINK_DOWN (1 << 5)
301 #define UMAC_IRQ_LINK_EVENT (UMAC_IRQ_LINK_UP | UMAC_IRQ_LINK_DOWN)
302 #define UMAC_IRQ_UMAC (1 << 6)
303 #define UMAC_IRQ_UMAC_TSV (1 << 7)
304 #define UMAC_IRQ_TBUF_UNDERRUN (1 << 8)
305 #define UMAC_IRQ_RBUF_OVERFLOW (1 << 9)
306 #define UMAC_IRQ_HFB_SM (1 << 10)
307 #define UMAC_IRQ_HFB_MM (1 << 11)
308 #define UMAC_IRQ_MPD_R (1 << 12)
309 #define UMAC_IRQ_RXDMA_MBDONE (1 << 13)
310 #define UMAC_IRQ_RXDMA_PDONE (1 << 14)
311 #define UMAC_IRQ_RXDMA_BDONE (1 << 15)
312 #define UMAC_IRQ_RXDMA_DONE UMAC_IRQ_RXDMA_MBDONE
313 #define UMAC_IRQ_TXDMA_MBDONE (1 << 16)
314 #define UMAC_IRQ_TXDMA_PDONE (1 << 17)
315 #define UMAC_IRQ_TXDMA_BDONE (1 << 18)
316 #define UMAC_IRQ_TXDMA_DONE UMAC_IRQ_TXDMA_MBDONE
318 /* Only valid for GENETv3+ */
319 #define UMAC_IRQ_MDIO_DONE (1 << 23)
320 #define UMAC_IRQ_MDIO_ERROR (1 << 24)
322 /* INTRL2 instance 1 definitions */
323 #define UMAC_IRQ1_TX_INTR_MASK 0xFFFF
324 #define UMAC_IRQ1_RX_INTR_MASK 0xFFFF
325 #define UMAC_IRQ1_RX_INTR_SHIFT 16
327 /* Register block offsets */
328 #define GENET_SYS_OFF 0x0000
329 #define GENET_GR_BRIDGE_OFF 0x0040
330 #define GENET_EXT_OFF 0x0080
331 #define GENET_INTRL2_0_OFF 0x0200
332 #define GENET_INTRL2_1_OFF 0x0240
333 #define GENET_RBUF_OFF 0x0300
334 #define GENET_UMAC_OFF 0x0800
336 /* SYS block offsets and register definitions */
337 #define SYS_REV_CTRL 0x00
338 #define SYS_PORT_CTRL 0x04
339 #define PORT_MODE_INT_EPHY 0
340 #define PORT_MODE_INT_GPHY 1
341 #define PORT_MODE_EXT_EPHY 2
342 #define PORT_MODE_EXT_GPHY 3
343 #define PORT_MODE_EXT_RVMII_25 (4 | BIT(4))
344 #define PORT_MODE_EXT_RVMII_50 4
345 #define LED_ACT_SOURCE_MAC (1 << 9)
347 #define SYS_RBUF_FLUSH_CTRL 0x08
348 #define SYS_TBUF_FLUSH_CTRL 0x0C
349 #define RBUF_FLUSH_CTRL_V1 0x04
351 /* Ext block register offsets and definitions */
352 #define EXT_EXT_PWR_MGMT 0x00
353 #define EXT_PWR_DOWN_BIAS (1 << 0)
354 #define EXT_PWR_DOWN_DLL (1 << 1)
355 #define EXT_PWR_DOWN_PHY (1 << 2)
356 #define EXT_PWR_DN_EN_LD (1 << 3)
357 #define EXT_ENERGY_DET (1 << 4)
358 #define EXT_IDDQ_FROM_PHY (1 << 5)
359 #define EXT_IDDQ_GLBL_PWR (1 << 7)
360 #define EXT_PHY_RESET (1 << 8)
361 #define EXT_ENERGY_DET_MASK (1 << 12)
362 #define EXT_PWR_DOWN_PHY_TX (1 << 16)
363 #define EXT_PWR_DOWN_PHY_RX (1 << 17)
364 #define EXT_PWR_DOWN_PHY_SD (1 << 18)
365 #define EXT_PWR_DOWN_PHY_RD (1 << 19)
366 #define EXT_PWR_DOWN_PHY_EN (1 << 20)
368 #define EXT_RGMII_OOB_CTRL 0x0C
369 #define RGMII_LINK (1 << 4)
370 #define OOB_DISABLE (1 << 5)
371 #define RGMII_MODE_EN (1 << 6)
372 #define ID_MODE_DIS (1 << 16)
374 #define EXT_GPHY_CTRL 0x1C
375 #define EXT_CFG_IDDQ_BIAS (1 << 0)
376 #define EXT_CFG_PWR_DOWN (1 << 1)
377 #define EXT_CK25_DIS (1 << 4)
378 #define EXT_GPHY_RESET (1 << 5)
381 #define DMA_RING_SIZE (0x40)
382 #define DMA_RINGS_SIZE (DMA_RING_SIZE * (DESC_INDEX + 1))
384 /* DMA registers common definitions */
385 #define DMA_RW_POINTER_MASK 0x1FF
386 #define DMA_P_INDEX_DISCARD_CNT_MASK 0xFFFF
387 #define DMA_P_INDEX_DISCARD_CNT_SHIFT 16
388 #define DMA_BUFFER_DONE_CNT_MASK 0xFFFF
389 #define DMA_BUFFER_DONE_CNT_SHIFT 16
390 #define DMA_P_INDEX_MASK 0xFFFF
391 #define DMA_C_INDEX_MASK 0xFFFF
393 /* DMA ring size register */
394 #define DMA_RING_SIZE_MASK 0xFFFF
395 #define DMA_RING_SIZE_SHIFT 16
396 #define DMA_RING_BUFFER_SIZE_MASK 0xFFFF
398 /* DMA interrupt threshold register */
399 #define DMA_INTR_THRESHOLD_MASK 0x01FF
401 /* DMA XON/XOFF register */
402 #define DMA_XON_THREHOLD_MASK 0xFFFF
403 #define DMA_XOFF_THRESHOLD_MASK 0xFFFF
404 #define DMA_XOFF_THRESHOLD_SHIFT 16
406 /* DMA flow period register */
407 #define DMA_FLOW_PERIOD_MASK 0xFFFF
408 #define DMA_MAX_PKT_SIZE_MASK 0xFFFF
409 #define DMA_MAX_PKT_SIZE_SHIFT 16
412 /* DMA control register */
413 #define DMA_EN (1 << 0)
414 #define DMA_RING_BUF_EN_SHIFT 0x01
415 #define DMA_RING_BUF_EN_MASK 0xFFFF
416 #define DMA_TSB_SWAP_EN (1 << 20)
418 /* DMA status register */
419 #define DMA_DISABLED (1 << 0)
420 #define DMA_DESC_RAM_INIT_BUSY (1 << 1)
422 /* DMA SCB burst size register */
423 #define DMA_SCB_BURST_SIZE_MASK 0x1F
425 /* DMA activity vector register */
426 #define DMA_ACTIVITY_VECTOR_MASK 0x1FFFF
428 /* DMA backpressure mask register */
429 #define DMA_BACKPRESSURE_MASK 0x1FFFF
430 #define DMA_PFC_ENABLE (1 << 31)
432 /* DMA backpressure status register */
433 #define DMA_BACKPRESSURE_STATUS_MASK 0x1FFFF
435 /* DMA override register */
436 #define DMA_LITTLE_ENDIAN_MODE (1 << 0)
437 #define DMA_REGISTER_MODE (1 << 1)
439 /* DMA timeout register */
440 #define DMA_TIMEOUT_MASK 0xFFFF
441 #define DMA_TIMEOUT_VAL 5000 /* micro seconds */
443 /* TDMA rate limiting control register */
444 #define DMA_RATE_LIMIT_EN_MASK 0xFFFF
446 /* TDMA arbitration control register */
447 #define DMA_ARBITER_MODE_MASK 0x03
448 #define DMA_RING_BUF_PRIORITY_MASK 0x1F
449 #define DMA_RING_BUF_PRIORITY_SHIFT 5
450 #define DMA_PRIO_REG_INDEX(q) ((q) / 6)
451 #define DMA_PRIO_REG_SHIFT(q) (((q) % 6) * DMA_RING_BUF_PRIORITY_SHIFT)
452 #define DMA_RATE_ADJ_MASK 0xFF
454 /* Tx/Rx Dma Descriptor common bits*/
455 #define DMA_BUFLENGTH_MASK 0x0fff
456 #define DMA_BUFLENGTH_SHIFT 16
457 #define DMA_OWN 0x8000
458 #define DMA_EOP 0x4000
459 #define DMA_SOP 0x2000
460 #define DMA_WRAP 0x1000
461 /* Tx specific Dma descriptor bits */
462 #define DMA_TX_UNDERRUN 0x0200
463 #define DMA_TX_APPEND_CRC 0x0040
464 #define DMA_TX_OW_CRC 0x0020
465 #define DMA_TX_DO_CSUM 0x0010
466 #define DMA_TX_QTAG_SHIFT 7
468 /* Rx Specific Dma descriptor bits */
469 #define DMA_RX_CHK_V3PLUS 0x8000
470 #define DMA_RX_CHK_V12 0x1000
471 #define DMA_RX_BRDCAST 0x0040
472 #define DMA_RX_MULT 0x0020
473 #define DMA_RX_LG 0x0010
474 #define DMA_RX_NO 0x0008
475 #define DMA_RX_RXER 0x0004
476 #define DMA_RX_CRC_ERROR 0x0002
477 #define DMA_RX_OV 0x0001
478 #define DMA_RX_FI_MASK 0x001F
479 #define DMA_RX_FI_SHIFT 0x0007
480 #define DMA_DESC_ALLOC_MASK 0x00FF
482 #define DMA_ARBITER_RR 0x00
483 #define DMA_ARBITER_WRR 0x01
484 #define DMA_ARBITER_SP 0x02
488 void __iomem
*bd_addr
;
489 DEFINE_DMA_UNMAP_ADDR(dma_addr
);
490 DEFINE_DMA_UNMAP_LEN(dma_len
);
493 /* power management mode */
494 enum bcmgenet_power_mode
{
495 GENET_POWER_CABLE_SENSE
= 0,
497 GENET_POWER_WOL_MAGIC
,
500 struct bcmgenet_priv
;
502 /* We support both runtime GENET detection and compile-time
503 * to optimize code-paths for a given hardware
505 enum bcmgenet_version
{
513 #define GENET_IS_V1(p) ((p)->version == GENET_V1)
514 #define GENET_IS_V2(p) ((p)->version == GENET_V2)
515 #define GENET_IS_V3(p) ((p)->version == GENET_V3)
516 #define GENET_IS_V4(p) ((p)->version == GENET_V4)
517 #define GENET_IS_V5(p) ((p)->version == GENET_V5)
520 #define GENET_HAS_40BITS (1 << 0)
521 #define GENET_HAS_EXT (1 << 1)
522 #define GENET_HAS_MDIO_INTR (1 << 2)
523 #define GENET_HAS_MOCA_LINK_DET (1 << 3)
525 /* BCMGENET hardware parameters, keep this structure nicely aligned
526 * since it is going to be used in hot paths
528 struct bcmgenet_hw_params
{
547 struct bcmgenet_skb_cb
{
548 struct enet_cb
*first_cb
; /* First control block of SKB */
549 struct enet_cb
*last_cb
; /* Last control block of SKB */
550 unsigned int bytes_sent
; /* bytes on the wire (no TSB) */
553 #define GENET_CB(skb) ((struct bcmgenet_skb_cb *)((skb)->cb))
555 struct bcmgenet_tx_ring
{
556 spinlock_t lock
; /* ring lock */
557 struct napi_struct napi
; /* NAPI per tx queue */
558 unsigned long packets
;
560 unsigned int index
; /* ring index */
561 unsigned int queue
; /* queue index */
562 struct enet_cb
*cbs
; /* tx ring buffer control block*/
563 unsigned int size
; /* size of each tx ring */
564 unsigned int clean_ptr
; /* Tx ring clean pointer */
565 unsigned int c_index
; /* last consumer index of each ring*/
566 unsigned int free_bds
; /* # of free bds for each ring */
567 unsigned int write_ptr
; /* Tx ring write pointer SW copy */
568 unsigned int prod_index
; /* Tx ring producer index SW copy */
569 unsigned int cb_ptr
; /* Tx ring initial CB ptr */
570 unsigned int end_ptr
; /* Tx ring end CB ptr */
571 void (*int_enable
)(struct bcmgenet_tx_ring
*);
572 void (*int_disable
)(struct bcmgenet_tx_ring
*);
573 struct bcmgenet_priv
*priv
;
576 struct bcmgenet_net_dim
{
579 unsigned long packets
;
584 struct bcmgenet_rx_ring
{
585 struct napi_struct napi
; /* Rx NAPI struct */
587 unsigned long packets
;
588 unsigned long errors
;
589 unsigned long dropped
;
590 unsigned int index
; /* Rx ring index */
591 struct enet_cb
*cbs
; /* Rx ring buffer control block */
592 unsigned int size
; /* Rx ring size */
593 unsigned int c_index
; /* Rx last consumer index */
594 unsigned int read_ptr
; /* Rx ring read pointer */
595 unsigned int cb_ptr
; /* Rx ring initial CB ptr */
596 unsigned int end_ptr
; /* Rx ring end CB ptr */
597 unsigned int old_discards
;
598 struct bcmgenet_net_dim dim
;
599 u32 rx_max_coalesced_frames
;
600 u32 rx_coalesce_usecs
;
601 void (*int_enable
)(struct bcmgenet_rx_ring
*);
602 void (*int_disable
)(struct bcmgenet_rx_ring
*);
603 struct bcmgenet_priv
*priv
;
607 struct bcmgenet_priv
{
609 enum bcmgenet_version version
;
610 struct net_device
*dev
;
612 /* transmit variables */
613 void __iomem
*tx_bds
;
614 struct enet_cb
*tx_cbs
;
615 unsigned int num_tx_bds
;
617 struct bcmgenet_tx_ring tx_rings
[DESC_INDEX
+ 1];
619 /* receive variables */
620 void __iomem
*rx_bds
;
621 struct enet_cb
*rx_cbs
;
622 unsigned int num_rx_bds
;
623 unsigned int rx_buf_len
;
625 struct bcmgenet_rx_ring rx_rings
[DESC_INDEX
+ 1];
627 /* other misc variables */
628 struct bcmgenet_hw_params
*hw_params
;
630 /* MDIO bus variables */
631 wait_queue_head_t wq
;
633 struct device_node
*phy_dn
;
634 struct device_node
*mdio_dn
;
635 struct mii_bus
*mii_bus
;
638 bool clk_eee_enabled
;
640 /* PHY device variables */
645 phy_interface_t phy_interface
;
649 /* Interrupt variables */
650 struct work_struct bcmgenet_irq_work
;
654 bool wol_irq_disabled
;
658 unsigned int irq0_stat
;
660 /* HW descriptors/checksum variables */
665 unsigned int dma_rx_chk_bit
;
670 struct platform_device
*pdev
;
671 struct platform_device
*mii_pdev
;
677 struct bcmgenet_mib_counters mib
;
679 struct ethtool_eee eee
;
682 #define GENET_IO_MACRO(name, offset) \
683 static inline u32 bcmgenet_##name##_readl(struct bcmgenet_priv *priv, \
686 /* MIPS chips strapped for BE will automagically configure the \
687 * peripheral registers for CPU-native byte order. \
689 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) \
690 return __raw_readl(priv->base + offset + off); \
692 return readl_relaxed(priv->base + offset + off); \
694 static inline void bcmgenet_##name##_writel(struct bcmgenet_priv *priv, \
697 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) \
698 __raw_writel(val, priv->base + offset + off); \
700 writel_relaxed(val, priv->base + offset + off); \
703 GENET_IO_MACRO(ext
, GENET_EXT_OFF
);
704 GENET_IO_MACRO(umac
, GENET_UMAC_OFF
);
705 GENET_IO_MACRO(sys
, GENET_SYS_OFF
);
707 /* interrupt l2 registers accessors */
708 GENET_IO_MACRO(intrl2_0
, GENET_INTRL2_0_OFF
);
709 GENET_IO_MACRO(intrl2_1
, GENET_INTRL2_1_OFF
);
711 /* HFB register accessors */
712 GENET_IO_MACRO(hfb
, priv
->hw_params
->hfb_offset
);
714 /* GENET v2+ HFB control and filter len helpers */
715 GENET_IO_MACRO(hfb_reg
, priv
->hw_params
->hfb_reg_offset
);
717 /* RBUF register accessors */
718 GENET_IO_MACRO(rbuf
, GENET_RBUF_OFF
);
721 int bcmgenet_mii_init(struct net_device
*dev
);
722 int bcmgenet_mii_config(struct net_device
*dev
, bool init
);
723 int bcmgenet_mii_probe(struct net_device
*dev
);
724 void bcmgenet_mii_exit(struct net_device
*dev
);
725 void bcmgenet_phy_power_set(struct net_device
*dev
, bool enable
);
726 void bcmgenet_mii_setup(struct net_device
*dev
);
728 /* Wake-on-LAN routines */
729 void bcmgenet_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
);
730 int bcmgenet_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
);
731 int bcmgenet_wol_power_down_cfg(struct bcmgenet_priv
*priv
,
732 enum bcmgenet_power_mode mode
);
733 void bcmgenet_wol_power_up_cfg(struct bcmgenet_priv
*priv
,
734 enum bcmgenet_power_mode mode
);
736 #endif /* __BCMGENET_H__ */