drivers/net/ethernet/broadcom/genet/bcmmii.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Broadcom GENET MDIO routines
   4  *
   5  * Copyright (c) 2014-2017 Broadcom
   6  */
   7
   8 #include <linux/acpi.h>
   9 #include <linux/types.h>
  10 #include <linux/delay.h>
  11 #include <linux/wait.h>
  12 #include <linux/mii.h>
  13 #include <linux/ethtool.h>
  14 #include <linux/bitops.h>
  15 #include <linux/netdevice.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/phy.h>
  18 #include <linux/phy_fixed.h>
  19 #include <linux/brcmphy.h>
  20 #include <linux/of.h>
  21 #include <linux/of_net.h>
  22 #include <linux/of_mdio.h>
  23 #include <linux/platform_data/bcmgenet.h>
  24 #include <linux/platform_data/mdio-bcm-unimac.h>
  25
  26 #include "bcmgenet.h"
  27
  28 /* setup netdev link state when PHY link status change and
  29  * update UMAC and RGMII block when link up
  30  */
  31 void bcmgenet_mii_setup(struct net_device *dev)
  32 {
  33         struct bcmgenet_priv *priv = netdev_priv(dev);
  34         struct phy_device *phydev = dev->phydev;
  35         u32 reg, cmd_bits = 0;
  36         bool status_changed = false;
  37
  38         if (priv->old_link != phydev->link) {
  39                 status_changed = true;
  40                 priv->old_link = phydev->link;
  41         }
  42
  43         if (phydev->link) {
  44                 /* check speed/duplex/pause changes */
  45                 if (priv->old_speed != phydev->speed) {
  46                         status_changed = true;
  47                         priv->old_speed = phydev->speed;
  48                 }
  49
  50                 if (priv->old_duplex != phydev->duplex) {
  51                         status_changed = true;
  52                         priv->old_duplex = phydev->duplex;
  53                 }
  54
  55                 if (priv->old_pause != phydev->pause) {
  56                         status_changed = true;
  57                         priv->old_pause = phydev->pause;
  58                 }
  59
  60                 /* done if nothing has changed */
  61                 if (!status_changed)
  62                         return;
  63
  64                 /* speed */
  65                 if (phydev->speed == SPEED_1000)
  66                         cmd_bits = UMAC_SPEED_1000;
  67                 else if (phydev->speed == SPEED_100)
  68                         cmd_bits = UMAC_SPEED_100;
  69                 else
  70                         cmd_bits = UMAC_SPEED_10;
  71                 cmd_bits <<= CMD_SPEED_SHIFT;
  72
  73                 /* duplex */
  74                 if (phydev->duplex != DUPLEX_FULL)
  75                         cmd_bits |= CMD_HD_EN;
  76
  77                 /* pause capability */
  78                 if (!phydev->pause)
  79                         cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE;
  80
  81                 /*
  82                  * Program UMAC and RGMII block based on established
  83                  * link speed, duplex, and pause. The speed set in
  84                  * umac->cmd tell RGMII block which clock to use for
  85                  * transmit -- 25MHz(100Mbps) or 125MHz(1Gbps).
  86                  * Receive clock is provided by the PHY.
  87                  */
  88                 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
  89                 reg &= ~OOB_DISABLE;
  90                 reg |= RGMII_LINK;
  91                 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
  92
  93                 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
  94                 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) |
  95                                CMD_HD_EN |
  96                                CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE);
  97                 reg |= cmd_bits;
  98                 if (reg & CMD_SW_RESET) {
  99                         reg &= ~CMD_SW_RESET;
 100                         bcmgenet_umac_writel(priv, reg, UMAC_CMD);
 101                         udelay(2);
 102                         reg |= CMD_TX_EN | CMD_RX_EN;
 103                 }
 104                 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
 105         } else {
 106                 /* done if nothing has changed */
 107                 if (!status_changed)
 108                         return;
 109
 110                 /* needed for MoCA fixed PHY to reflect correct link status */
 111                 netif_carrier_off(dev);
 112         }
 113
 114         phy_print_status(phydev);
 115 }
 116
 117
 118 static int bcmgenet_fixed_phy_link_update(struct net_device *dev,
 119                                           struct fixed_phy_status *status)
 120 {
 121         struct bcmgenet_priv *priv;
 122         u32 reg;
 123
 124         if (dev && dev->phydev && status) {
 125                 priv = netdev_priv(dev);
 126                 reg = bcmgenet_umac_readl(priv, UMAC_MODE);
 127                 status->link = !!(reg & MODE_LINK_STATUS);
 128         }
 129
 130         return 0;
 131 }
 132
 133 void bcmgenet_phy_power_set(struct net_device *dev, bool enable)
 134 {
 135         struct bcmgenet_priv *priv = netdev_priv(dev);
 136         u32 reg = 0;
 137
 138         /* EXT_GPHY_CTRL is only valid for GENETv4 and onward */
 139         if (GENET_IS_V4(priv)) {
 140                 reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL);
 141                 if (enable) {
 142                         reg &= ~EXT_CK25_DIS;
 143                         bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
 144                         mdelay(1);
 145
 146                         reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN);
 147                         reg |= EXT_GPHY_RESET;
 148                         bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
 149                         mdelay(1);
 150
 151                         reg &= ~EXT_GPHY_RESET;
 152                 } else {
 153                         reg |= EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN |
 154                                EXT_GPHY_RESET;
 155                         bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
 156                         mdelay(1);
 157                         reg |= EXT_CK25_DIS;
 158                 }
 159                 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
 160                 udelay(60);
 161         } else {
 162                 mdelay(1);
 163         }
 164 }
 165
 166 static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv)
 167 {
 168         u32 reg;
 169
 170         if (!GENET_IS_V5(priv)) {
 171                 /* Speed settings are set in bcmgenet_mii_setup() */
 172                 reg = bcmgenet_sys_readl(priv, SYS_PORT_CTRL);
 173                 reg |= LED_ACT_SOURCE_MAC;
 174                 bcmgenet_sys_writel(priv, reg, SYS_PORT_CTRL);
 175         }
 176
 177         if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
 178                 fixed_phy_set_link_update(priv->dev->phydev,
 179                                           bcmgenet_fixed_phy_link_update);
 180 }
 181
 182 int bcmgenet_mii_config(struct net_device *dev, bool init)
 183 {
 184         struct bcmgenet_priv *priv = netdev_priv(dev);
 185         struct phy_device *phydev = dev->phydev;
 186         struct device *kdev = &priv->pdev->dev;
 187         const char *phy_name = NULL;
 188         u32 id_mode_dis = 0;
 189         u32 port_ctrl;
 190         u32 reg;
 191
 192         switch (priv->phy_interface) {
 193         case PHY_INTERFACE_MODE_INTERNAL:
 194                 phy_name = "internal PHY";
 195                 fallthrough;
 196         case PHY_INTERFACE_MODE_MOCA:
 197                 /* Irrespective of the actually configured PHY speed (100 or
 198                  * 1000) GENETv4 only has an internal GPHY so we will just end
 199                  * up masking the Gigabit features from what we support, not
 200                  * switching to the EPHY
 201                  */
 202                 if (GENET_IS_V4(priv))
 203                         port_ctrl = PORT_MODE_INT_GPHY;
 204                 else
 205                         port_ctrl = PORT_MODE_INT_EPHY;
 206
 207                 if (!phy_name) {
 208                         phy_name = "MoCA";
 209                         bcmgenet_moca_phy_setup(priv);
 210                 }
 211                 break;
 212
 213         case PHY_INTERFACE_MODE_MII:
 214                 phy_name = "external MII";
 215                 phy_set_max_speed(phydev, SPEED_100);
 216                 port_ctrl = PORT_MODE_EXT_EPHY;
 217                 break;
 218
 219         case PHY_INTERFACE_MODE_REVMII:
 220                 phy_name = "external RvMII";
 221                 /* of_mdiobus_register took care of reading the 'max-speed'
 222                  * PHY property for us, effectively limiting the PHY supported
 223                  * capabilities, use that knowledge to also configure the
 224                  * Reverse MII interface correctly.
 225                  */
 226                 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
 227                                       dev->phydev->supported))
 228                         port_ctrl = PORT_MODE_EXT_RVMII_50;
 229                 else
 230                         port_ctrl = PORT_MODE_EXT_RVMII_25;
 231                 break;
 232
 233         case PHY_INTERFACE_MODE_RGMII:
 234                 /* RGMII_NO_ID: TXC transitions at the same time as TXD
 235                  *              (requires PCB or receiver-side delay)
 236                  *
 237                  * ID is implicitly disabled for 100Mbps (RG)MII operation.
 238                  */
 239                 phy_name = "external RGMII (no delay)";
 240                 id_mode_dis = BIT(16);
 241                 port_ctrl = PORT_MODE_EXT_GPHY;
 242                 break;
 243
 244         case PHY_INTERFACE_MODE_RGMII_TXID:
 245                 /* RGMII_TXID:  Add 2ns delay on TXC (90 degree shift) */
 246                 phy_name = "external RGMII (TX delay)";
 247                 port_ctrl = PORT_MODE_EXT_GPHY;
 248                 break;
 249
 250         case PHY_INTERFACE_MODE_RGMII_RXID:
 251                 phy_name = "external RGMII (RX delay)";
 252                 port_ctrl = PORT_MODE_EXT_GPHY;
 253                 break;
 254         default:
 255                 dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface);
 256                 return -EINVAL;
 257         }
 258
 259         bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
 260
 261         priv->ext_phy = !priv->internal_phy &&
 262                         (priv->phy_interface != PHY_INTERFACE_MODE_MOCA);
 263
 264         /* This is an external PHY (xMII), so we need to enable the RGMII
 265          * block for the interface to work
 266          */
 267         if (priv->ext_phy) {
 268                 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
 269                 reg &= ~ID_MODE_DIS;
 270                 reg |= id_mode_dis;
 271                 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv))
 272                         reg |= RGMII_MODE_EN_V123;
 273                 else
 274                         reg |= RGMII_MODE_EN;
 275                 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
 276         }
 277
 278         if (init)
 279                 dev_info(kdev, "configuring instance for %s\n", phy_name);
 280
 281         return 0;
 282 }
 283
 284 int bcmgenet_mii_probe(struct net_device *dev)
 285 {
 286         struct bcmgenet_priv *priv = netdev_priv(dev);
 287         struct device *kdev = &priv->pdev->dev;
 288         struct device_node *dn = kdev->of_node;
 289         struct phy_device *phydev;
 290         u32 phy_flags = 0;
 291         int ret;
 292
 293         /* Communicate the integrated PHY revision */
 294         if (priv->internal_phy)
 295                 phy_flags = priv->gphy_rev;
 296
 297         /* Initialize link state variables that bcmgenet_mii_setup() uses */
 298         priv->old_link = -1;
 299         priv->old_speed = -1;
 300         priv->old_duplex = -1;
 301         priv->old_pause = -1;
 302
 303         if (dn) {
 304                 phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup,
 305                                         phy_flags, priv->phy_interface);
 306                 if (!phydev) {
 307                         pr_err("could not attach to PHY\n");
 308                         return -ENODEV;
 309                 }
 310         } else {
 311                 if (has_acpi_companion(kdev)) {
 312                         char mdio_bus_id[MII_BUS_ID_SIZE];
 313                         struct mii_bus *unimacbus;
 314
 315                         snprintf(mdio_bus_id, MII_BUS_ID_SIZE, "%s-%d",
 316                                  UNIMAC_MDIO_DRV_NAME, priv->pdev->id);
 317
 318                         unimacbus = mdio_find_bus(mdio_bus_id);
 319                         if (!unimacbus) {
 320                                 pr_err("Unable to find mii\n");
 321                                 return -ENODEV;
 322                         }
 323                         phydev = phy_find_first(unimacbus);
 324                         put_device(&unimacbus->dev);
 325                         if (!phydev) {
 326                                 pr_err("Unable to find PHY\n");
 327                                 return -ENODEV;
 328                         }
 329                 } else {
 330                         phydev = dev->phydev;
 331                 }
 332                 phydev->dev_flags = phy_flags;
 333
 334                 ret = phy_connect_direct(dev, phydev, bcmgenet_mii_setup,
 335                                          priv->phy_interface);
 336                 if (ret) {
 337                         pr_err("could not attach to PHY\n");
 338                         return -ENODEV;
 339                 }
 340         }
 341
 342         /* Configure port multiplexer based on what the probed PHY device since
 343          * reading the 'max-speed' property determines the maximum supported
 344          * PHY speed which is needed for bcmgenet_mii_config() to configure
 345          * things appropriately.
 346          */
 347         ret = bcmgenet_mii_config(dev, true);
 348         if (ret) {
 349                 phy_disconnect(dev->phydev);
 350                 return ret;
 351         }
 352
 353         linkmode_copy(phydev->advertising, phydev->supported);
 354
 355         /* The internal PHY has its link interrupts routed to the
 356          * Ethernet MAC ISRs. On GENETv5 there is a hardware issue
 357          * that prevents the signaling of link UP interrupts when
 358          * the link operates at 10Mbps, so fallback to polling for
 359          * those versions of GENET.
 360          */
 361         if (priv->internal_phy && !GENET_IS_V5(priv))
 362                 dev->phydev->irq = PHY_IGNORE_INTERRUPT;
 363
 364         return 0;
 365 }
 366
 367 static struct device_node *bcmgenet_mii_of_find_mdio(struct bcmgenet_priv *priv)
 368 {
 369         struct device_node *dn = priv->pdev->dev.of_node;
 370         struct device *kdev = &priv->pdev->dev;
 371         char *compat;
 372
 373         compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version);
 374         if (!compat)
 375                 return NULL;
 376
 377         priv->mdio_dn = of_get_compatible_child(dn, compat);
 378         kfree(compat);
 379         if (!priv->mdio_dn) {
 380                 dev_err(kdev, "unable to find MDIO bus node\n");
 381                 return NULL;
 382         }
 383
 384         return priv->mdio_dn;
 385 }
 386
 387 static void bcmgenet_mii_pdata_init(struct bcmgenet_priv *priv,
 388                                     struct unimac_mdio_pdata *ppd)
 389 {
 390         struct device *kdev = &priv->pdev->dev;
 391         struct bcmgenet_platform_data *pd = kdev->platform_data;
 392
 393         if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) {
 394                 /*
 395                  * Internal or external PHY with MDIO access
 396                  */
 397                 if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR)
 398                         ppd->phy_mask = 1 << pd->phy_address;
 399                 else
 400                         ppd->phy_mask = 0;
 401         }
 402 }
 403
 404 static int bcmgenet_mii_wait(void *wait_func_data)
 405 {
 406         struct bcmgenet_priv *priv = wait_func_data;
 407
 408         wait_event_timeout(priv->wq,
 409                            !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD)
 410                            & MDIO_START_BUSY),
 411                            HZ / 100);
 412         return 0;
 413 }
 414
 415 static int bcmgenet_mii_register(struct bcmgenet_priv *priv)
 416 {
 417         struct platform_device *pdev = priv->pdev;
 418         struct bcmgenet_platform_data *pdata = pdev->dev.platform_data;
 419         struct device_node *dn = pdev->dev.of_node;
 420         struct unimac_mdio_pdata ppd;
 421         struct platform_device *ppdev;
 422         struct resource *pres, res;
 423         int id, ret;
 424
 425         pres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 426         memset(&res, 0, sizeof(res));
 427         memset(&ppd, 0, sizeof(ppd));
 428
 429         ppd.wait_func = bcmgenet_mii_wait;
 430         ppd.wait_func_data = priv;
 431         ppd.bus_name = "bcmgenet MII bus";
 432
 433         /* Unimac MDIO bus controller starts at UniMAC offset + MDIO_CMD
 434          * and is 2 * 32-bits word long, 8 bytes total.
 435          */
 436         res.start = pres->start + GENET_UMAC_OFF + UMAC_MDIO_CMD;
 437         res.end = res.start + 8;
 438         res.flags = IORESOURCE_MEM;
 439
 440         if (dn)
 441                 id = of_alias_get_id(dn, "eth");
 442         else
 443                 id = pdev->id;
 444
 445         ppdev = platform_device_alloc(UNIMAC_MDIO_DRV_NAME, id);
 446         if (!ppdev)
 447                 return -ENOMEM;
 448
 449         /* Retain this platform_device pointer for later cleanup */
 450         priv->mii_pdev = ppdev;
 451         ppdev->dev.parent = &pdev->dev;
 452         if (dn)
 453                 ppdev->dev.of_node = bcmgenet_mii_of_find_mdio(priv);
 454         else if (pdata)
 455                 bcmgenet_mii_pdata_init(priv, &ppd);
 456         else
 457                 ppd.phy_mask = ~0;
 458
 459         ret = platform_device_add_resources(ppdev, &res, 1);
 460         if (ret)
 461                 goto out;
 462
 463         ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd));
 464         if (ret)
 465                 goto out;
 466
 467         ret = platform_device_add(ppdev);
 468         if (ret)
 469                 goto out;
 470
 471         return 0;
 472 out:
 473         platform_device_put(ppdev);
 474         return ret;
 475 }
 476
 477 static int bcmgenet_phy_interface_init(struct bcmgenet_priv *priv)
 478 {
 479         struct device *kdev = &priv->pdev->dev;
 480         int phy_mode = device_get_phy_mode(kdev);
 481
 482         if (phy_mode < 0) {
 483                 dev_err(kdev, "invalid PHY mode property\n");
 484                 return phy_mode;
 485         }
 486
 487         priv->phy_interface = phy_mode;
 488
 489         /* We need to specifically look up whether this PHY interface is
 490          * internal or not *before* we even try to probe the PHY driver
 491          * over MDIO as we may have shut down the internal PHY for power
 492          * saving purposes.
 493          */
 494         if (priv->phy_interface == PHY_INTERFACE_MODE_INTERNAL)
 495                 priv->internal_phy = true;
 496
 497         return 0;
 498 }
 499
 500 static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv)
 501 {
 502         struct device_node *dn = priv->pdev->dev.of_node;
 503         struct phy_device *phydev;
 504         int ret;
 505
 506         /* Fetch the PHY phandle */
 507         priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0);
 508
 509         /* In the case of a fixed PHY, the DT node associated
 510          * to the PHY is the Ethernet MAC DT node.
 511          */
 512         if (!priv->phy_dn && of_phy_is_fixed_link(dn)) {
 513                 ret = of_phy_register_fixed_link(dn);
 514                 if (ret)
 515                         return ret;
 516
 517                 priv->phy_dn = of_node_get(dn);
 518         }
 519
 520         /* Get the link mode */
 521         ret = bcmgenet_phy_interface_init(priv);
 522         if (ret)
 523                 return ret;
 524
 525         /* Make sure we initialize MoCA PHYs with a link down */
 526         if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
 527                 phydev = of_phy_find_device(dn);
 528                 if (phydev) {
 529                         phydev->link = 0;
 530                         put_device(&phydev->mdio.dev);
 531                 }
 532         }
 533
 534         return 0;
 535 }
 536
 537 static int bcmgenet_mii_pd_init(struct bcmgenet_priv *priv)
 538 {
 539         struct device *kdev = &priv->pdev->dev;
 540         struct bcmgenet_platform_data *pd = kdev->platform_data;
 541         char phy_name[MII_BUS_ID_SIZE + 3];
 542         char mdio_bus_id[MII_BUS_ID_SIZE];
 543         struct phy_device *phydev;
 544
 545         snprintf(mdio_bus_id, MII_BUS_ID_SIZE, "%s-%d",
 546                  UNIMAC_MDIO_DRV_NAME, priv->pdev->id);
 547
 548         if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) {
 549                 snprintf(phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT,
 550                          mdio_bus_id, pd->phy_address);
 551
 552                 /*
 553                  * Internal or external PHY with MDIO access
 554                  */
 555                 phydev = phy_attach(priv->dev, phy_name, pd->phy_interface);
 556                 if (!phydev) {
 557                         dev_err(kdev, "failed to register PHY device\n");
 558                         return -ENODEV;
 559                 }
 560         } else {
 561                 /*
 562                  * MoCA port or no MDIO access.
 563                  * Use fixed PHY to represent the link layer.
 564                  */
 565                 struct fixed_phy_status fphy_status = {
 566                         .link = 1,
 567                         .speed = pd->phy_speed,
 568                         .duplex = pd->phy_duplex,
 569                         .pause = 0,
 570                         .asym_pause = 0,
 571                 };
 572
 573                 phydev = fixed_phy_register(PHY_POLL, &fphy_status, NULL);
 574                 if (!phydev || IS_ERR(phydev)) {
 575                         dev_err(kdev, "failed to register fixed PHY device\n");
 576                         return -ENODEV;
 577                 }
 578
 579                 /* Make sure we initialize MoCA PHYs with a link down */
 580                 phydev->link = 0;
 581
 582         }
 583
 584         priv->phy_interface = pd->phy_interface;
 585
 586         return 0;
 587 }
 588
 589 static int bcmgenet_mii_bus_init(struct bcmgenet_priv *priv)
 590 {
 591         struct device *kdev = &priv->pdev->dev;
 592         struct device_node *dn = kdev->of_node;
 593
 594         if (dn)
 595                 return bcmgenet_mii_of_init(priv);
 596         else if (has_acpi_companion(kdev))
 597                 return bcmgenet_phy_interface_init(priv);
 598         else
 599                 return bcmgenet_mii_pd_init(priv);
 600 }
 601
 602 int bcmgenet_mii_init(struct net_device *dev)
 603 {
 604         struct bcmgenet_priv *priv = netdev_priv(dev);
 605         int ret;
 606
 607         ret = bcmgenet_mii_register(priv);
 608         if (ret)
 609                 return ret;
 610
 611         ret = bcmgenet_mii_bus_init(priv);
 612         if (ret)
 613                 goto out;
 614
 615         return 0;
 616
 617 out:
 618         bcmgenet_mii_exit(dev);
 619         return ret;
 620 }
 621
 622 void bcmgenet_mii_exit(struct net_device *dev)
 623 {
 624         struct bcmgenet_priv *priv = netdev_priv(dev);
 625         struct device_node *dn = priv->pdev->dev.of_node;
 626
 627         if (of_phy_is_fixed_link(dn))
 628                 of_phy_deregister_fixed_link(dn);
 629         of_node_put(priv->phy_dn);
 630         platform_device_unregister(priv->mii_pdev);
 631 }