2 * Broadcom GENET MDIO routines
4 * Copyright (c) 2014 Broadcom Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
12 #include <linux/types.h>
13 #include <linux/delay.h>
14 #include <linux/wait.h>
15 #include <linux/mii.h>
16 #include <linux/ethtool.h>
17 #include <linux/bitops.h>
18 #include <linux/netdevice.h>
19 #include <linux/platform_device.h>
20 #include <linux/phy.h>
21 #include <linux/phy_fixed.h>
22 #include <linux/brcmphy.h>
24 #include <linux/of_net.h>
25 #include <linux/of_mdio.h>
26 #include <linux/platform_data/bcmgenet.h>
30 /* read a value from the MII */
31 static int bcmgenet_mii_read(struct mii_bus
*bus
, int phy_id
, int location
)
34 struct net_device
*dev
= bus
->priv
;
35 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
38 bcmgenet_umac_writel(priv
, (MDIO_RD
| (phy_id
<< MDIO_PMD_SHIFT
) |
39 (location
<< MDIO_REG_SHIFT
)), UMAC_MDIO_CMD
);
40 /* Start MDIO transaction*/
41 reg
= bcmgenet_umac_readl(priv
, UMAC_MDIO_CMD
);
42 reg
|= MDIO_START_BUSY
;
43 bcmgenet_umac_writel(priv
, reg
, UMAC_MDIO_CMD
);
44 wait_event_timeout(priv
->wq
,
45 !(bcmgenet_umac_readl(priv
, UMAC_MDIO_CMD
)
48 ret
= bcmgenet_umac_readl(priv
, UMAC_MDIO_CMD
);
50 if (ret
& MDIO_READ_FAIL
)
56 /* write a value to the MII */
57 static int bcmgenet_mii_write(struct mii_bus
*bus
, int phy_id
,
58 int location
, u16 val
)
60 struct net_device
*dev
= bus
->priv
;
61 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
64 bcmgenet_umac_writel(priv
, (MDIO_WR
| (phy_id
<< MDIO_PMD_SHIFT
) |
65 (location
<< MDIO_REG_SHIFT
) | (0xffff & val
)),
67 reg
= bcmgenet_umac_readl(priv
, UMAC_MDIO_CMD
);
68 reg
|= MDIO_START_BUSY
;
69 bcmgenet_umac_writel(priv
, reg
, UMAC_MDIO_CMD
);
70 wait_event_timeout(priv
->wq
,
71 !(bcmgenet_umac_readl(priv
, UMAC_MDIO_CMD
) &
78 /* setup netdev link state when PHY link status change and
79 * update UMAC and RGMII block when link up
81 void bcmgenet_mii_setup(struct net_device
*dev
)
83 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
84 struct phy_device
*phydev
= priv
->phydev
;
85 u32 reg
, cmd_bits
= 0;
86 bool status_changed
= false;
88 if (priv
->old_link
!= phydev
->link
) {
89 status_changed
= true;
90 priv
->old_link
= phydev
->link
;
94 /* check speed/duplex/pause changes */
95 if (priv
->old_speed
!= phydev
->speed
) {
96 status_changed
= true;
97 priv
->old_speed
= phydev
->speed
;
100 if (priv
->old_duplex
!= phydev
->duplex
) {
101 status_changed
= true;
102 priv
->old_duplex
= phydev
->duplex
;
105 if (priv
->old_pause
!= phydev
->pause
) {
106 status_changed
= true;
107 priv
->old_pause
= phydev
->pause
;
110 /* done if nothing has changed */
115 if (phydev
->speed
== SPEED_1000
)
116 cmd_bits
= UMAC_SPEED_1000
;
117 else if (phydev
->speed
== SPEED_100
)
118 cmd_bits
= UMAC_SPEED_100
;
120 cmd_bits
= UMAC_SPEED_10
;
121 cmd_bits
<<= CMD_SPEED_SHIFT
;
124 if (phydev
->duplex
!= DUPLEX_FULL
)
125 cmd_bits
|= CMD_HD_EN
;
127 /* pause capability */
129 cmd_bits
|= CMD_RX_PAUSE_IGNORE
| CMD_TX_PAUSE_IGNORE
;
132 * Program UMAC and RGMII block based on established
133 * link speed, duplex, and pause. The speed set in
134 * umac->cmd tell RGMII block which clock to use for
135 * transmit -- 25MHz(100Mbps) or 125MHz(1Gbps).
136 * Receive clock is provided by the PHY.
138 reg
= bcmgenet_ext_readl(priv
, EXT_RGMII_OOB_CTRL
);
141 bcmgenet_ext_writel(priv
, reg
, EXT_RGMII_OOB_CTRL
);
143 reg
= bcmgenet_umac_readl(priv
, UMAC_CMD
);
144 reg
&= ~((CMD_SPEED_MASK
<< CMD_SPEED_SHIFT
) |
146 CMD_RX_PAUSE_IGNORE
| CMD_TX_PAUSE_IGNORE
);
148 bcmgenet_umac_writel(priv
, reg
, UMAC_CMD
);
150 /* done if nothing has changed */
154 /* needed for MoCA fixed PHY to reflect correct link status */
155 netif_carrier_off(dev
);
158 phy_print_status(phydev
);
161 void bcmgenet_mii_reset(struct net_device
*dev
)
163 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
166 phy_init_hw(priv
->phydev
);
167 phy_start_aneg(priv
->phydev
);
171 void bcmgenet_phy_power_set(struct net_device
*dev
, bool enable
)
173 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
176 /* EXT_GPHY_CTRL is only valid for GENETv4 and onward */
177 if (!GENET_IS_V4(priv
))
180 reg
= bcmgenet_ext_readl(priv
, EXT_GPHY_CTRL
);
182 reg
&= ~EXT_CK25_DIS
;
183 bcmgenet_ext_writel(priv
, reg
, EXT_GPHY_CTRL
);
186 reg
&= ~(EXT_CFG_IDDQ_BIAS
| EXT_CFG_PWR_DOWN
);
187 reg
|= EXT_GPHY_RESET
;
188 bcmgenet_ext_writel(priv
, reg
, EXT_GPHY_CTRL
);
191 reg
&= ~EXT_GPHY_RESET
;
193 reg
|= EXT_CFG_IDDQ_BIAS
| EXT_CFG_PWR_DOWN
| EXT_GPHY_RESET
;
194 bcmgenet_ext_writel(priv
, reg
, EXT_GPHY_CTRL
);
198 bcmgenet_ext_writel(priv
, reg
, EXT_GPHY_CTRL
);
202 static void bcmgenet_internal_phy_setup(struct net_device
*dev
)
204 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
208 bcmgenet_phy_power_set(dev
, true);
210 reg
= bcmgenet_ext_readl(priv
, EXT_EXT_PWR_MGMT
);
211 reg
|= EXT_PWR_DN_EN_LD
;
212 bcmgenet_ext_writel(priv
, reg
, EXT_EXT_PWR_MGMT
);
213 bcmgenet_mii_reset(dev
);
216 static void bcmgenet_moca_phy_setup(struct bcmgenet_priv
*priv
)
220 /* Speed settings are set in bcmgenet_mii_setup() */
221 reg
= bcmgenet_sys_readl(priv
, SYS_PORT_CTRL
);
222 reg
|= LED_ACT_SOURCE_MAC
;
223 bcmgenet_sys_writel(priv
, reg
, SYS_PORT_CTRL
);
226 int bcmgenet_mii_config(struct net_device
*dev
, bool init
)
228 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
229 struct phy_device
*phydev
= priv
->phydev
;
230 struct device
*kdev
= &priv
->pdev
->dev
;
231 const char *phy_name
= NULL
;
236 priv
->ext_phy
= !phy_is_internal(priv
->phydev
) &&
237 (priv
->phy_interface
!= PHY_INTERFACE_MODE_MOCA
);
239 if (phy_is_internal(priv
->phydev
))
240 priv
->phy_interface
= PHY_INTERFACE_MODE_NA
;
242 switch (priv
->phy_interface
) {
243 case PHY_INTERFACE_MODE_NA
:
244 case PHY_INTERFACE_MODE_MOCA
:
245 /* Irrespective of the actually configured PHY speed (100 or
246 * 1000) GENETv4 only has an internal GPHY so we will just end
247 * up masking the Gigabit features from what we support, not
248 * switching to the EPHY
250 if (GENET_IS_V4(priv
))
251 port_ctrl
= PORT_MODE_INT_GPHY
;
253 port_ctrl
= PORT_MODE_INT_EPHY
;
255 bcmgenet_sys_writel(priv
, port_ctrl
, SYS_PORT_CTRL
);
257 if (phy_is_internal(priv
->phydev
)) {
258 phy_name
= "internal PHY";
259 bcmgenet_internal_phy_setup(dev
);
260 } else if (priv
->phy_interface
== PHY_INTERFACE_MODE_MOCA
) {
262 bcmgenet_moca_phy_setup(priv
);
266 case PHY_INTERFACE_MODE_MII
:
267 phy_name
= "external MII";
268 phydev
->supported
&= PHY_BASIC_FEATURES
;
269 bcmgenet_sys_writel(priv
,
270 PORT_MODE_EXT_EPHY
, SYS_PORT_CTRL
);
273 case PHY_INTERFACE_MODE_REVMII
:
274 phy_name
= "external RvMII";
275 /* of_mdiobus_register took care of reading the 'max-speed'
276 * PHY property for us, effectively limiting the PHY supported
277 * capabilities, use that knowledge to also configure the
278 * Reverse MII interface correctly.
280 if ((priv
->phydev
->supported
& PHY_BASIC_FEATURES
) ==
282 port_ctrl
= PORT_MODE_EXT_RVMII_25
;
284 port_ctrl
= PORT_MODE_EXT_RVMII_50
;
285 bcmgenet_sys_writel(priv
, port_ctrl
, SYS_PORT_CTRL
);
288 case PHY_INTERFACE_MODE_RGMII
:
289 /* RGMII_NO_ID: TXC transitions at the same time as TXD
290 * (requires PCB or receiver-side delay)
291 * RGMII: Add 2ns delay on TXC (90 degree shift)
293 * ID is implicitly disabled for 100Mbps (RG)MII operation.
295 id_mode_dis
= BIT(16);
297 case PHY_INTERFACE_MODE_RGMII_TXID
:
299 phy_name
= "external RGMII (no delay)";
301 phy_name
= "external RGMII (TX delay)";
302 reg
= bcmgenet_ext_readl(priv
, EXT_RGMII_OOB_CTRL
);
303 reg
|= RGMII_MODE_EN
| id_mode_dis
;
304 bcmgenet_ext_writel(priv
, reg
, EXT_RGMII_OOB_CTRL
);
305 bcmgenet_sys_writel(priv
,
306 PORT_MODE_EXT_GPHY
, SYS_PORT_CTRL
);
309 dev_err(kdev
, "unknown phy mode: %d\n", priv
->phy_interface
);
314 dev_info(kdev
, "configuring instance for %s\n", phy_name
);
319 static int bcmgenet_mii_probe(struct net_device
*dev
)
321 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
322 struct device_node
*dn
= priv
->pdev
->dev
.of_node
;
323 struct phy_device
*phydev
;
327 /* Communicate the integrated PHY revision */
328 phy_flags
= priv
->gphy_rev
;
330 /* Initialize link state variables that bcmgenet_mii_setup() uses */
332 priv
->old_speed
= -1;
333 priv
->old_duplex
= -1;
334 priv
->old_pause
= -1;
338 pr_info("PHY already attached\n");
342 /* In the case of a fixed PHY, the DT node associated
343 * to the PHY is the Ethernet MAC DT node.
345 if (!priv
->phy_dn
&& of_phy_is_fixed_link(dn
)) {
346 ret
= of_phy_register_fixed_link(dn
);
350 priv
->phy_dn
= of_node_get(dn
);
353 phydev
= of_phy_connect(dev
, priv
->phy_dn
, bcmgenet_mii_setup
,
354 phy_flags
, priv
->phy_interface
);
356 pr_err("could not attach to PHY\n");
360 phydev
= priv
->phydev
;
361 phydev
->dev_flags
= phy_flags
;
363 ret
= phy_connect_direct(dev
, phydev
, bcmgenet_mii_setup
,
364 priv
->phy_interface
);
366 pr_err("could not attach to PHY\n");
371 priv
->phydev
= phydev
;
373 /* Configure port multiplexer based on what the probed PHY device since
374 * reading the 'max-speed' property determines the maximum supported
375 * PHY speed which is needed for bcmgenet_mii_config() to configure
376 * things appropriately.
378 ret
= bcmgenet_mii_config(dev
, true);
380 phy_disconnect(priv
->phydev
);
384 phydev
->advertising
= phydev
->supported
;
386 /* The internal PHY has its link interrupts routed to the
389 if (phy_is_internal(priv
->phydev
))
390 priv
->mii_bus
->irq
[phydev
->addr
] = PHY_IGNORE_INTERRUPT
;
392 priv
->mii_bus
->irq
[phydev
->addr
] = PHY_POLL
;
394 pr_info("attached PHY at address %d [%s]\n",
395 phydev
->addr
, phydev
->drv
->name
);
400 static int bcmgenet_mii_alloc(struct bcmgenet_priv
*priv
)
407 priv
->mii_bus
= mdiobus_alloc();
408 if (!priv
->mii_bus
) {
409 pr_err("failed to allocate\n");
414 bus
->priv
= priv
->dev
;
415 bus
->name
= "bcmgenet MII bus";
416 bus
->parent
= &priv
->pdev
->dev
;
417 bus
->read
= bcmgenet_mii_read
;
418 bus
->write
= bcmgenet_mii_write
;
419 snprintf(bus
->id
, MII_BUS_ID_SIZE
, "%s-%d",
420 priv
->pdev
->name
, priv
->pdev
->id
);
422 bus
->irq
= kcalloc(PHY_MAX_ADDR
, sizeof(int), GFP_KERNEL
);
424 mdiobus_free(priv
->mii_bus
);
431 static int bcmgenet_mii_of_init(struct bcmgenet_priv
*priv
)
433 struct device_node
*dn
= priv
->pdev
->dev
.of_node
;
434 struct device
*kdev
= &priv
->pdev
->dev
;
435 struct device_node
*mdio_dn
;
439 compat
= kasprintf(GFP_KERNEL
, "brcm,genet-mdio-v%d", priv
->version
);
443 mdio_dn
= of_find_compatible_node(dn
, NULL
, compat
);
446 dev_err(kdev
, "unable to find MDIO bus node\n");
450 ret
= of_mdiobus_register(priv
->mii_bus
, mdio_dn
);
452 dev_err(kdev
, "failed to register MDIO bus\n");
456 /* Fetch the PHY phandle */
457 priv
->phy_dn
= of_parse_phandle(dn
, "phy-handle", 0);
459 /* Get the link mode */
460 priv
->phy_interface
= of_get_phy_mode(dn
);
465 static int bcmgenet_fixed_phy_link_update(struct net_device
*dev
,
466 struct fixed_phy_status
*status
)
468 if (dev
&& dev
->phydev
&& status
)
469 status
->link
= dev
->phydev
->link
;
474 static int bcmgenet_mii_pd_init(struct bcmgenet_priv
*priv
)
476 struct device
*kdev
= &priv
->pdev
->dev
;
477 struct bcmgenet_platform_data
*pd
= kdev
->platform_data
;
478 struct mii_bus
*mdio
= priv
->mii_bus
;
479 struct phy_device
*phydev
;
482 if (pd
->phy_interface
!= PHY_INTERFACE_MODE_MOCA
&& pd
->mdio_enabled
) {
484 * Internal or external PHY with MDIO access
486 if (pd
->phy_address
>= 0 && pd
->phy_address
< PHY_MAX_ADDR
)
487 mdio
->phy_mask
= ~(1 << pd
->phy_address
);
491 ret
= mdiobus_register(mdio
);
493 dev_err(kdev
, "failed to register MDIO bus\n");
497 if (pd
->phy_address
>= 0 && pd
->phy_address
< PHY_MAX_ADDR
)
498 phydev
= mdio
->phy_map
[pd
->phy_address
];
500 phydev
= phy_find_first(mdio
);
503 dev_err(kdev
, "failed to register PHY device\n");
504 mdiobus_unregister(mdio
);
509 * MoCA port or no MDIO access.
510 * Use fixed PHY to represent the link layer.
512 struct fixed_phy_status fphy_status
= {
514 .speed
= pd
->phy_speed
,
515 .duplex
= pd
->phy_duplex
,
520 phydev
= fixed_phy_register(PHY_POLL
, &fphy_status
, NULL
);
521 if (!phydev
|| IS_ERR(phydev
)) {
522 dev_err(kdev
, "failed to register fixed PHY device\n");
526 if (priv
->hw_params
->flags
& GENET_HAS_MOCA_LINK_DET
) {
527 ret
= fixed_phy_set_link_update(
528 phydev
, bcmgenet_fixed_phy_link_update
);
534 priv
->phydev
= phydev
;
535 priv
->phy_interface
= pd
->phy_interface
;
540 static int bcmgenet_mii_bus_init(struct bcmgenet_priv
*priv
)
542 struct device_node
*dn
= priv
->pdev
->dev
.of_node
;
545 return bcmgenet_mii_of_init(priv
);
547 return bcmgenet_mii_pd_init(priv
);
550 int bcmgenet_mii_init(struct net_device
*dev
)
552 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
555 ret
= bcmgenet_mii_alloc(priv
);
559 ret
= bcmgenet_mii_bus_init(priv
);
563 ret
= bcmgenet_mii_probe(dev
);
570 of_node_put(priv
->phy_dn
);
571 mdiobus_unregister(priv
->mii_bus
);
573 kfree(priv
->mii_bus
->irq
);
574 mdiobus_free(priv
->mii_bus
);
578 void bcmgenet_mii_exit(struct net_device
*dev
)
580 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
582 of_node_put(priv
->phy_dn
);
583 mdiobus_unregister(priv
->mii_bus
);
584 kfree(priv
->mii_bus
->irq
);
585 mdiobus_free(priv
->mii_bus
);