drivers/net/ethernet/broadcom/genet/bcmmii.c

   1 /*
   2  * Broadcom GENET MDIO routines
   3  *
   4  * Copyright (c) 2014 Broadcom Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11
  12 #include <linux/types.h>
  13 #include <linux/delay.h>
  14 #include <linux/wait.h>
  15 #include <linux/mii.h>
  16 #include <linux/ethtool.h>
  17 #include <linux/bitops.h>
  18 #include <linux/netdevice.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/phy.h>
  21 #include <linux/phy_fixed.h>
  22 #include <linux/brcmphy.h>
  23 #include <linux/of.h>
  24 #include <linux/of_net.h>
  25 #include <linux/of_mdio.h>
  26 #include <linux/platform_data/bcmgenet.h>
  27
  28 #include "bcmgenet.h"
  29
  30 /* read a value from the MII */
  31 static int bcmgenet_mii_read(struct mii_bus *bus, int phy_id, int location)
  32 {
  33         int ret;
  34         struct net_device *dev = bus->priv;
  35         struct bcmgenet_priv *priv = netdev_priv(dev);
  36         u32 reg;
  37
  38         bcmgenet_umac_writel(priv, (MDIO_RD | (phy_id << MDIO_PMD_SHIFT) |
  39                              (location << MDIO_REG_SHIFT)), UMAC_MDIO_CMD);
  40         /* Start MDIO transaction*/
  41         reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
  42         reg |= MDIO_START_BUSY;
  43         bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD);
  44         wait_event_timeout(priv->wq,
  45                            !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD)
  46                            & MDIO_START_BUSY),
  47                            HZ / 100);
  48         ret = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
  49
  50         /* Some broken devices are known not to release the line during
  51          * turn-around, e.g: Broadcom BCM53125 external switches, so check for
  52          * that condition here and ignore the MDIO controller read failure
  53          * indication.
  54          */
  55         if (!(bus->phy_ignore_ta_mask & 1 << phy_id) && (ret & MDIO_READ_FAIL))
  56                 return -EIO;
  57
  58         return ret & 0xffff;
  59 }
  60
  61 /* write a value to the MII */
  62 static int bcmgenet_mii_write(struct mii_bus *bus, int phy_id,
  63                               int location, u16 val)
  64 {
  65         struct net_device *dev = bus->priv;
  66         struct bcmgenet_priv *priv = netdev_priv(dev);
  67         u32 reg;
  68
  69         bcmgenet_umac_writel(priv, (MDIO_WR | (phy_id << MDIO_PMD_SHIFT) |
  70                              (location << MDIO_REG_SHIFT) | (0xffff & val)),
  71                              UMAC_MDIO_CMD);
  72         reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
  73         reg |= MDIO_START_BUSY;
  74         bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD);
  75         wait_event_timeout(priv->wq,
  76                            !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD) &
  77                            MDIO_START_BUSY),
  78                            HZ / 100);
  79
  80         return 0;
  81 }
  82
  83 /* setup netdev link state when PHY link status change and
  84  * update UMAC and RGMII block when link up
  85  */
  86 void bcmgenet_mii_setup(struct net_device *dev)
  87 {
  88         struct bcmgenet_priv *priv = netdev_priv(dev);
  89         struct phy_device *phydev = priv->phydev;
  90         u32 reg, cmd_bits = 0;
  91         bool status_changed = false;
  92
  93         if (priv->old_link != phydev->link) {
  94                 status_changed = true;
  95                 priv->old_link = phydev->link;
  96         }
  97
  98         if (phydev->link) {
  99                 /* check speed/duplex/pause changes */
 100                 if (priv->old_speed != phydev->speed) {
 101                         status_changed = true;
 102                         priv->old_speed = phydev->speed;
 103                 }
 104
 105                 if (priv->old_duplex != phydev->duplex) {
 106                         status_changed = true;
 107                         priv->old_duplex = phydev->duplex;
 108                 }
 109
 110                 if (priv->old_pause != phydev->pause) {
 111                         status_changed = true;
 112                         priv->old_pause = phydev->pause;
 113                 }
 114
 115                 /* done if nothing has changed */
 116                 if (!status_changed)
 117                         return;
 118
 119                 /* speed */
 120                 if (phydev->speed == SPEED_1000)
 121                         cmd_bits = UMAC_SPEED_1000;
 122                 else if (phydev->speed == SPEED_100)
 123                         cmd_bits = UMAC_SPEED_100;
 124                 else
 125                         cmd_bits = UMAC_SPEED_10;
 126                 cmd_bits <<= CMD_SPEED_SHIFT;
 127
 128                 /* duplex */
 129                 if (phydev->duplex != DUPLEX_FULL)
 130                         cmd_bits |= CMD_HD_EN;
 131
 132                 /* pause capability */
 133                 if (!phydev->pause)
 134                         cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE;
 135
 136                 /*
 137                  * Program UMAC and RGMII block based on established
 138                  * link speed, duplex, and pause. The speed set in
 139                  * umac->cmd tell RGMII block which clock to use for
 140                  * transmit -- 25MHz(100Mbps) or 125MHz(1Gbps).
 141                  * Receive clock is provided by the PHY.
 142                  */
 143                 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
 144                 reg &= ~OOB_DISABLE;
 145                 reg |= RGMII_LINK;
 146                 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
 147
 148                 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
 149                 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) |
 150                                CMD_HD_EN |
 151                                CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE);
 152                 reg |= cmd_bits;
 153                 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
 154         } else {
 155                 /* done if nothing has changed */
 156                 if (!status_changed)
 157                         return;
 158
 159                 /* needed for MoCA fixed PHY to reflect correct link status */
 160                 netif_carrier_off(dev);
 161         }
 162
 163         phy_print_status(phydev);
 164 }
 165
 166
 167 static int bcmgenet_fixed_phy_link_update(struct net_device *dev,
 168                                           struct fixed_phy_status *status)
 169 {
 170         if (dev && dev->phydev && status)
 171                 status->link = dev->phydev->link;
 172
 173         return 0;
 174 }
 175
 176 /* Perform a voluntary PHY software reset, since the EPHY is very finicky about
 177  * not doing it and will start corrupting packets
 178  */
 179 void bcmgenet_mii_reset(struct net_device *dev)
 180 {
 181         struct bcmgenet_priv *priv = netdev_priv(dev);
 182
 183         if (GENET_IS_V4(priv))
 184                 return;
 185
 186         if (priv->phydev) {
 187                 phy_init_hw(priv->phydev);
 188                 phy_start_aneg(priv->phydev);
 189         }
 190 }
 191
 192 void bcmgenet_phy_power_set(struct net_device *dev, bool enable)
 193 {
 194         struct bcmgenet_priv *priv = netdev_priv(dev);
 195         u32 reg = 0;
 196
 197         /* EXT_GPHY_CTRL is only valid for GENETv4 and onward */
 198         if (!GENET_IS_V4(priv))
 199                 return;
 200
 201         reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL);
 202         if (enable) {
 203                 reg &= ~EXT_CK25_DIS;
 204                 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
 205                 mdelay(1);
 206
 207                 reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN);
 208                 reg |= EXT_GPHY_RESET;
 209                 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
 210                 mdelay(1);
 211
 212                 reg &= ~EXT_GPHY_RESET;
 213         } else {
 214                 reg |= EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN | EXT_GPHY_RESET;
 215                 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
 216                 mdelay(1);
 217                 reg |= EXT_CK25_DIS;
 218         }
 219         bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
 220         udelay(60);
 221 }
 222
 223 static void bcmgenet_internal_phy_setup(struct net_device *dev)
 224 {
 225         struct bcmgenet_priv *priv = netdev_priv(dev);
 226         u32 reg;
 227
 228         /* Power up PHY */
 229         bcmgenet_phy_power_set(dev, true);
 230         /* enable APD */
 231         reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
 232         reg |= EXT_PWR_DN_EN_LD;
 233         bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
 234         bcmgenet_mii_reset(dev);
 235 }
 236
 237 static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv)
 238 {
 239         u32 reg;
 240
 241         /* Speed settings are set in bcmgenet_mii_setup() */
 242         reg = bcmgenet_sys_readl(priv, SYS_PORT_CTRL);
 243         reg |= LED_ACT_SOURCE_MAC;
 244         bcmgenet_sys_writel(priv, reg, SYS_PORT_CTRL);
 245
 246         if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
 247                 fixed_phy_set_link_update(priv->phydev,
 248                                           bcmgenet_fixed_phy_link_update);
 249 }
 250
 251 int bcmgenet_mii_config(struct net_device *dev)
 252 {
 253         struct bcmgenet_priv *priv = netdev_priv(dev);
 254         struct phy_device *phydev = priv->phydev;
 255         struct device *kdev = &priv->pdev->dev;
 256         const char *phy_name = NULL;
 257         u32 id_mode_dis = 0;
 258         u32 port_ctrl;
 259         u32 reg;
 260
 261         priv->ext_phy = !priv->internal_phy &&
 262                         (priv->phy_interface != PHY_INTERFACE_MODE_MOCA);
 263
 264         if (priv->internal_phy)
 265                 priv->phy_interface = PHY_INTERFACE_MODE_NA;
 266
 267         switch (priv->phy_interface) {
 268         case PHY_INTERFACE_MODE_NA:
 269         case PHY_INTERFACE_MODE_MOCA:
 270                 /* Irrespective of the actually configured PHY speed (100 or
 271                  * 1000) GENETv4 only has an internal GPHY so we will just end
 272                  * up masking the Gigabit features from what we support, not
 273                  * switching to the EPHY
 274                  */
 275                 if (GENET_IS_V4(priv))
 276                         port_ctrl = PORT_MODE_INT_GPHY;
 277                 else
 278                         port_ctrl = PORT_MODE_INT_EPHY;
 279
 280                 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
 281
 282                 if (priv->internal_phy) {
 283                         phy_name = "internal PHY";
 284                         bcmgenet_internal_phy_setup(dev);
 285                 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
 286                         phy_name = "MoCA";
 287                         bcmgenet_moca_phy_setup(priv);
 288                 }
 289                 break;
 290
 291         case PHY_INTERFACE_MODE_MII:
 292                 phy_name = "external MII";
 293                 phydev->supported &= PHY_BASIC_FEATURES;
 294                 bcmgenet_sys_writel(priv,
 295                                     PORT_MODE_EXT_EPHY, SYS_PORT_CTRL);
 296                 break;
 297
 298         case PHY_INTERFACE_MODE_REVMII:
 299                 phy_name = "external RvMII";
 300                 /* of_mdiobus_register took care of reading the 'max-speed'
 301                  * PHY property for us, effectively limiting the PHY supported
 302                  * capabilities, use that knowledge to also configure the
 303                  * Reverse MII interface correctly.
 304                  */
 305                 if ((priv->phydev->supported & PHY_BASIC_FEATURES) ==
 306                                 PHY_BASIC_FEATURES)
 307                         port_ctrl = PORT_MODE_EXT_RVMII_25;
 308                 else
 309                         port_ctrl = PORT_MODE_EXT_RVMII_50;
 310                 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
 311                 break;
 312
 313         case PHY_INTERFACE_MODE_RGMII:
 314                 /* RGMII_NO_ID: TXC transitions at the same time as TXD
 315                  *              (requires PCB or receiver-side delay)
 316                  * RGMII:       Add 2ns delay on TXC (90 degree shift)
 317                  *
 318                  * ID is implicitly disabled for 100Mbps (RG)MII operation.
 319                  */
 320                 id_mode_dis = BIT(16);
 321                 /* fall through */
 322         case PHY_INTERFACE_MODE_RGMII_TXID:
 323                 if (id_mode_dis)
 324                         phy_name = "external RGMII (no delay)";
 325                 else
 326                         phy_name = "external RGMII (TX delay)";
 327                 bcmgenet_sys_writel(priv,
 328                                     PORT_MODE_EXT_GPHY, SYS_PORT_CTRL);
 329                 break;
 330         default:
 331                 dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface);
 332                 return -EINVAL;
 333         }
 334
 335         /* This is an external PHY (xMII), so we need to enable the RGMII
 336          * block for the interface to work
 337          */
 338         if (priv->ext_phy) {
 339                 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
 340                 reg |= RGMII_MODE_EN | id_mode_dis;
 341                 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
 342         }
 343
 344         dev_info_once(kdev, "configuring instance for %s\n", phy_name);
 345
 346         return 0;
 347 }
 348
 349 int bcmgenet_mii_probe(struct net_device *dev)
 350 {
 351         struct bcmgenet_priv *priv = netdev_priv(dev);
 352         struct device_node *dn = priv->pdev->dev.of_node;
 353         struct phy_device *phydev;
 354         u32 phy_flags;
 355         int ret;
 356
 357         /* Communicate the integrated PHY revision */
 358         phy_flags = priv->gphy_rev;
 359
 360         /* Initialize link state variables that bcmgenet_mii_setup() uses */
 361         priv->old_link = -1;
 362         priv->old_speed = -1;
 363         priv->old_duplex = -1;
 364         priv->old_pause = -1;
 365
 366         if (dn) {
 367                 phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup,
 368                                         phy_flags, priv->phy_interface);
 369                 if (!phydev) {
 370                         pr_err("could not attach to PHY\n");
 371                         return -ENODEV;
 372                 }
 373         } else {
 374                 phydev = priv->phydev;
 375                 phydev->dev_flags = phy_flags;
 376
 377                 ret = phy_connect_direct(dev, phydev, bcmgenet_mii_setup,
 378                                          priv->phy_interface);
 379                 if (ret) {
 380                         pr_err("could not attach to PHY\n");
 381                         return -ENODEV;
 382                 }
 383         }
 384
 385         priv->phydev = phydev;
 386
 387         /* Configure port multiplexer based on what the probed PHY device since
 388          * reading the 'max-speed' property determines the maximum supported
 389          * PHY speed which is needed for bcmgenet_mii_config() to configure
 390          * things appropriately.
 391          */
 392         ret = bcmgenet_mii_config(dev);
 393         if (ret) {
 394                 phy_disconnect(priv->phydev);
 395                 return ret;
 396         }
 397
 398         phydev->advertising = phydev->supported;
 399
 400         /* The internal PHY has its link interrupts routed to the
 401          * Ethernet MAC ISRs
 402          */
 403         if (priv->internal_phy)
 404                 priv->phydev->irq = PHY_IGNORE_INTERRUPT;
 405
 406         return 0;
 407 }
 408
 409 /* Workaround for integrated BCM7xxx Gigabit PHYs which have a problem with
 410  * their internal MDIO management controller making them fail to successfully
 411  * be read from or written to for the first transaction.  We insert a dummy
 412  * BMSR read here to make sure that phy_get_device() and get_phy_id() can
 413  * correctly read the PHY MII_PHYSID1/2 registers and successfully register a
 414  * PHY device for this peripheral.
 415  *
 416  * Once the PHY driver is registered, we can workaround subsequent reads from
 417  * there (e.g: during system-wide power management).
 418  *
 419  * bus->reset is invoked before mdiobus_scan during mdiobus_register and is
 420  * therefore the right location to stick that workaround. Since we do not want
 421  * to read from non-existing PHYs, we either use bus->phy_mask or do a manual
 422  * Device Tree scan to limit the search area.
 423  */
 424 static int bcmgenet_mii_bus_reset(struct mii_bus *bus)
 425 {
 426         struct net_device *dev = bus->priv;
 427         struct bcmgenet_priv *priv = netdev_priv(dev);
 428         struct device_node *np = priv->mdio_dn;
 429         struct device_node *child = NULL;
 430         u32 read_mask = 0;
 431         int addr = 0;
 432
 433         if (!np) {
 434                 read_mask = 1 << priv->phy_addr;
 435         } else {
 436                 for_each_available_child_of_node(np, child) {
 437                         addr = of_mdio_parse_addr(&dev->dev, child);
 438                         if (addr < 0)
 439                                 continue;
 440
 441                         read_mask |= 1 << addr;
 442                 }
 443         }
 444
 445         for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
 446                 if (read_mask & 1 << addr) {
 447                         dev_dbg(&dev->dev, "Workaround for PHY @ %d\n", addr);
 448                         mdiobus_read(bus, addr, MII_BMSR);
 449                 }
 450         }
 451
 452         return 0;
 453 }
 454
 455 static int bcmgenet_mii_alloc(struct bcmgenet_priv *priv)
 456 {
 457         struct mii_bus *bus;
 458
 459         if (priv->mii_bus)
 460                 return 0;
 461
 462         priv->mii_bus = mdiobus_alloc();
 463         if (!priv->mii_bus) {
 464                 pr_err("failed to allocate\n");
 465                 return -ENOMEM;
 466         }
 467
 468         bus = priv->mii_bus;
 469         bus->priv = priv->dev;
 470         bus->name = "bcmgenet MII bus";
 471         bus->parent = &priv->pdev->dev;
 472         bus->read = bcmgenet_mii_read;
 473         bus->write = bcmgenet_mii_write;
 474         bus->reset = bcmgenet_mii_bus_reset;
 475         snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d",
 476                  priv->pdev->name, priv->pdev->id);
 477
 478         return 0;
 479 }
 480
 481 static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv)
 482 {
 483         struct device_node *dn = priv->pdev->dev.of_node;
 484         struct device *kdev = &priv->pdev->dev;
 485         const char *phy_mode_str = NULL;
 486         struct phy_device *phydev = NULL;
 487         char *compat;
 488         int phy_mode;
 489         int ret;
 490
 491         compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version);
 492         if (!compat)
 493                 return -ENOMEM;
 494
 495         priv->mdio_dn = of_find_compatible_node(dn, NULL, compat);
 496         kfree(compat);
 497         if (!priv->mdio_dn) {
 498                 dev_err(kdev, "unable to find MDIO bus node\n");
 499                 return -ENODEV;
 500         }
 501
 502         ret = of_mdiobus_register(priv->mii_bus, priv->mdio_dn);
 503         if (ret) {
 504                 dev_err(kdev, "failed to register MDIO bus\n");
 505                 return ret;
 506         }
 507
 508         /* Fetch the PHY phandle */
 509         priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0);
 510
 511         /* In the case of a fixed PHY, the DT node associated
 512          * to the PHY is the Ethernet MAC DT node.
 513          */
 514         if (!priv->phy_dn && of_phy_is_fixed_link(dn)) {
 515                 ret = of_phy_register_fixed_link(dn);
 516                 if (ret)
 517                         return ret;
 518
 519                 priv->phy_dn = of_node_get(dn);
 520         }
 521
 522         /* Get the link mode */
 523         phy_mode = of_get_phy_mode(dn);
 524         priv->phy_interface = phy_mode;
 525
 526         /* We need to specifically look up whether this PHY interface is internal
 527          * or not *before* we even try to probe the PHY driver over MDIO as we
 528          * may have shut down the internal PHY for power saving purposes.
 529          */
 530         if (phy_mode < 0) {
 531                 ret = of_property_read_string(dn, "phy-mode", &phy_mode_str);
 532                 if (ret < 0) {
 533                         dev_err(kdev, "invalid PHY mode property\n");
 534                         return ret;
 535                 }
 536
 537                 priv->phy_interface = PHY_INTERFACE_MODE_NA;
 538                 if (!strcasecmp(phy_mode_str, "internal"))
 539                         priv->internal_phy = true;
 540         }
 541
 542         /* Make sure we initialize MoCA PHYs with a link down */
 543         if (phy_mode == PHY_INTERFACE_MODE_MOCA) {
 544                 phydev = of_phy_find_device(dn);
 545                 if (phydev) {
 546                         phydev->link = 0;
 547                         put_device(&phydev->mdio.dev);
 548                 }
 549         }
 550
 551         return 0;
 552 }
 553
 554 static int bcmgenet_mii_pd_init(struct bcmgenet_priv *priv)
 555 {
 556         struct device *kdev = &priv->pdev->dev;
 557         struct bcmgenet_platform_data *pd = kdev->platform_data;
 558         struct mii_bus *mdio = priv->mii_bus;
 559         struct phy_device *phydev;
 560         int ret;
 561
 562         if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) {
 563                 /*
 564                  * Internal or external PHY with MDIO access
 565                  */
 566                 if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR)
 567                         mdio->phy_mask = ~(1 << pd->phy_address);
 568                 else
 569                         mdio->phy_mask = 0;
 570
 571                 ret = mdiobus_register(mdio);
 572                 if (ret) {
 573                         dev_err(kdev, "failed to register MDIO bus\n");
 574                         return ret;
 575                 }
 576
 577                 if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR)
 578                         phydev = mdiobus_get_phy(mdio, pd->phy_address);
 579                 else
 580                         phydev = phy_find_first(mdio);
 581
 582                 if (!phydev) {
 583                         dev_err(kdev, "failed to register PHY device\n");
 584                         mdiobus_unregister(mdio);
 585                         return -ENODEV;
 586                 }
 587         } else {
 588                 /*
 589                  * MoCA port or no MDIO access.
 590                  * Use fixed PHY to represent the link layer.
 591                  */
 592                 struct fixed_phy_status fphy_status = {
 593                         .link = 1,
 594                         .speed = pd->phy_speed,
 595                         .duplex = pd->phy_duplex,
 596                         .pause = 0,
 597                         .asym_pause = 0,
 598                 };
 599
 600                 phydev = fixed_phy_register(PHY_POLL, &fphy_status, -1, NULL);
 601                 if (!phydev || IS_ERR(phydev)) {
 602                         dev_err(kdev, "failed to register fixed PHY device\n");
 603                         return -ENODEV;
 604                 }
 605
 606                 /* Make sure we initialize MoCA PHYs with a link down */
 607                 phydev->link = 0;
 608
 609         }
 610
 611         priv->phydev = phydev;
 612         priv->phy_interface = pd->phy_interface;
 613
 614         return 0;
 615 }
 616
 617 static int bcmgenet_mii_bus_init(struct bcmgenet_priv *priv)
 618 {
 619         struct device_node *dn = priv->pdev->dev.of_node;
 620
 621         if (dn)
 622                 return bcmgenet_mii_of_init(priv);
 623         else
 624                 return bcmgenet_mii_pd_init(priv);
 625 }
 626
 627 int bcmgenet_mii_init(struct net_device *dev)
 628 {
 629         struct bcmgenet_priv *priv = netdev_priv(dev);
 630         struct device_node *dn = priv->pdev->dev.of_node;
 631         int ret;
 632
 633         ret = bcmgenet_mii_alloc(priv);
 634         if (ret)
 635                 return ret;
 636
 637         ret = bcmgenet_mii_bus_init(priv);
 638         if (ret)
 639                 goto out;
 640
 641         return 0;
 642
 643 out:
 644         if (of_phy_is_fixed_link(dn))
 645                 of_phy_deregister_fixed_link(dn);
 646         of_node_put(priv->phy_dn);
 647         mdiobus_unregister(priv->mii_bus);
 648         mdiobus_free(priv->mii_bus);
 649         return ret;
 650 }
 651
 652 void bcmgenet_mii_exit(struct net_device *dev)
 653 {
 654         struct bcmgenet_priv *priv = netdev_priv(dev);
 655         struct device_node *dn = priv->pdev->dev.of_node;
 656
 657         if (of_phy_is_fixed_link(dn))
 658                 of_phy_deregister_fixed_link(dn);
 659         of_node_put(priv->phy_dn);
 660         mdiobus_unregister(priv->mii_bus);
 661         mdiobus_free(priv->mii_bus);
 662 }