2 * Linux network driver for Brocade Converged Network Adapter.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
18 #include <linux/bitops.h>
19 #include <linux/netdevice.h>
20 #include <linux/skbuff.h>
21 #include <linux/etherdevice.h>
23 #include <linux/ethtool.h>
24 #include <linux/if_vlan.h>
25 #include <linux/if_ether.h>
27 #include <linux/prefetch.h>
33 static DEFINE_MUTEX(bnad_fwimg_mutex
);
38 static uint bnad_msix_disable
;
39 module_param(bnad_msix_disable
, uint
, 0444);
40 MODULE_PARM_DESC(bnad_msix_disable
, "Disable MSIX mode");
42 static uint bnad_ioc_auto_recover
= 1;
43 module_param(bnad_ioc_auto_recover
, uint
, 0444);
44 MODULE_PARM_DESC(bnad_ioc_auto_recover
, "Enable / Disable auto recovery");
49 u32 bnad_rxqs_per_cq
= 2;
51 static const u8 bnad_bcast_addr
[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
56 #define BNAD_TX_UNMAPQ_DEPTH (bnad->txq_depth * 2)
58 #define BNAD_RX_UNMAPQ_DEPTH (bnad->rxq_depth)
60 #define BNAD_GET_MBOX_IRQ(_bnad) \
61 (((_bnad)->cfg_flags & BNAD_CF_MSIX) ? \
62 ((_bnad)->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector) : \
63 ((_bnad)->pcidev->irq))
65 #define BNAD_FILL_UNMAPQ_MEM_REQ(_res_info, _num, _depth) \
67 (_res_info)->res_type = BNA_RES_T_MEM; \
68 (_res_info)->res_u.mem_info.mem_type = BNA_MEM_T_KVA; \
69 (_res_info)->res_u.mem_info.num = (_num); \
70 (_res_info)->res_u.mem_info.len = \
71 sizeof(struct bnad_unmap_q) + \
72 (sizeof(struct bnad_skb_unmap) * ((_depth) - 1)); \
75 #define BNAD_TXRX_SYNC_MDELAY 250 /* 250 msecs */
78 * Reinitialize completions in CQ, once Rx is taken down
81 bnad_cq_cmpl_init(struct bnad
*bnad
, struct bna_ccb
*ccb
)
83 struct bna_cq_entry
*cmpl
, *next_cmpl
;
84 unsigned int wi_range
, wis
= 0, ccb_prod
= 0;
87 BNA_CQ_QPGE_PTR_GET(ccb_prod
, ccb
->sw_qpt
, cmpl
,
90 for (i
= 0; i
< ccb
->q_depth
; i
++) {
92 if (likely(--wi_range
))
95 BNA_QE_INDX_ADD(ccb_prod
, wis
, ccb
->q_depth
);
97 BNA_CQ_QPGE_PTR_GET(ccb_prod
, ccb
->sw_qpt
,
106 bnad_pci_unmap_skb(struct device
*pdev
, struct bnad_skb_unmap
*array
,
107 u32 index
, u32 depth
, struct sk_buff
*skb
, u32 frag
)
110 array
[index
].skb
= NULL
;
112 dma_unmap_single(pdev
, dma_unmap_addr(&array
[index
], dma_addr
),
113 skb_headlen(skb
), DMA_TO_DEVICE
);
114 dma_unmap_addr_set(&array
[index
], dma_addr
, 0);
115 BNA_QE_INDX_ADD(index
, 1, depth
);
117 for (j
= 0; j
< frag
; j
++) {
118 dma_unmap_page(pdev
, dma_unmap_addr(&array
[index
], dma_addr
),
119 skb_shinfo(skb
)->frags
[j
].size
, DMA_TO_DEVICE
);
120 dma_unmap_addr_set(&array
[index
], dma_addr
, 0);
121 BNA_QE_INDX_ADD(index
, 1, depth
);
128 * Frees all pending Tx Bufs
129 * At this point no activity is expected on the Q,
130 * so DMA unmap & freeing is fine.
133 bnad_free_all_txbufs(struct bnad
*bnad
,
137 struct bnad_unmap_q
*unmap_q
= tcb
->unmap_q
;
138 struct bnad_skb_unmap
*unmap_array
;
139 struct sk_buff
*skb
= NULL
;
142 unmap_array
= unmap_q
->unmap_array
;
144 for (q
= 0; q
< unmap_q
->q_depth
; q
++) {
145 skb
= unmap_array
[q
].skb
;
150 unmap_cons
= bnad_pci_unmap_skb(&bnad
->pcidev
->dev
, unmap_array
,
151 unmap_cons
, unmap_q
->q_depth
, skb
,
152 skb_shinfo(skb
)->nr_frags
);
154 dev_kfree_skb_any(skb
);
158 /* Data Path Handlers */
161 * bnad_free_txbufs : Frees the Tx bufs on Tx completion
162 * Can be called in a) Interrupt context
167 bnad_free_txbufs(struct bnad
*bnad
,
170 u32 unmap_cons
, sent_packets
= 0, sent_bytes
= 0;
171 u16 wis
, updated_hw_cons
;
172 struct bnad_unmap_q
*unmap_q
= tcb
->unmap_q
;
173 struct bnad_skb_unmap
*unmap_array
;
177 * Just return if TX is stopped. This check is useful
178 * when bnad_free_txbufs() runs out of a tasklet scheduled
179 * before bnad_cb_tx_cleanup() cleared BNAD_TXQ_TX_STARTED bit
180 * but this routine runs actually after the cleanup has been
183 if (!test_bit(BNAD_TXQ_TX_STARTED
, &tcb
->flags
))
186 updated_hw_cons
= *(tcb
->hw_consumer_index
);
188 wis
= BNA_Q_INDEX_CHANGE(tcb
->consumer_index
,
189 updated_hw_cons
, tcb
->q_depth
);
191 BUG_ON(!(wis
<= BNA_QE_IN_USE_CNT(tcb
, tcb
->q_depth
)));
193 unmap_array
= unmap_q
->unmap_array
;
194 unmap_cons
= unmap_q
->consumer_index
;
196 prefetch(&unmap_array
[unmap_cons
+ 1]);
198 skb
= unmap_array
[unmap_cons
].skb
;
201 sent_bytes
+= skb
->len
;
202 wis
-= BNA_TXQ_WI_NEEDED(1 + skb_shinfo(skb
)->nr_frags
);
204 unmap_cons
= bnad_pci_unmap_skb(&bnad
->pcidev
->dev
, unmap_array
,
205 unmap_cons
, unmap_q
->q_depth
, skb
,
206 skb_shinfo(skb
)->nr_frags
);
208 dev_kfree_skb_any(skb
);
211 /* Update consumer pointers. */
212 tcb
->consumer_index
= updated_hw_cons
;
213 unmap_q
->consumer_index
= unmap_cons
;
215 tcb
->txq
->tx_packets
+= sent_packets
;
216 tcb
->txq
->tx_bytes
+= sent_bytes
;
221 /* Tx Free Tasklet function */
222 /* Frees for all the tcb's in all the Tx's */
224 * Scheduled from sending context, so that
225 * the fat Tx lock is not held for too long
226 * in the sending context.
229 bnad_tx_free_tasklet(unsigned long bnad_ptr
)
231 struct bnad
*bnad
= (struct bnad
*)bnad_ptr
;
236 for (i
= 0; i
< bnad
->num_tx
; i
++) {
237 for (j
= 0; j
< bnad
->num_txq_per_tx
; j
++) {
238 tcb
= bnad
->tx_info
[i
].tcb
[j
];
241 if (((u16
) (*tcb
->hw_consumer_index
) !=
242 tcb
->consumer_index
) &&
243 (!test_and_set_bit(BNAD_TXQ_FREE_SENT
,
245 acked
= bnad_free_txbufs(bnad
, tcb
);
246 if (likely(test_bit(BNAD_TXQ_TX_STARTED
,
248 bna_ib_ack(tcb
->i_dbell
, acked
);
249 smp_mb__before_clear_bit();
250 clear_bit(BNAD_TXQ_FREE_SENT
, &tcb
->flags
);
252 if (unlikely(!test_bit(BNAD_TXQ_TX_STARTED
,
255 if (netif_queue_stopped(bnad
->netdev
)) {
256 if (acked
&& netif_carrier_ok(bnad
->netdev
) &&
257 BNA_QE_FREE_CNT(tcb
, tcb
->q_depth
) >=
258 BNAD_NETIF_WAKE_THRESHOLD
) {
259 netif_wake_queue(bnad
->netdev
);
261 /* Counters for individual TxQs? */
262 BNAD_UPDATE_CTR(bnad
,
271 bnad_tx(struct bnad
*bnad
, struct bna_tcb
*tcb
)
273 struct net_device
*netdev
= bnad
->netdev
;
276 if (test_and_set_bit(BNAD_TXQ_FREE_SENT
, &tcb
->flags
))
279 sent
= bnad_free_txbufs(bnad
, tcb
);
281 if (netif_queue_stopped(netdev
) &&
282 netif_carrier_ok(netdev
) &&
283 BNA_QE_FREE_CNT(tcb
, tcb
->q_depth
) >=
284 BNAD_NETIF_WAKE_THRESHOLD
) {
285 if (test_bit(BNAD_TXQ_TX_STARTED
, &tcb
->flags
)) {
286 netif_wake_queue(netdev
);
287 BNAD_UPDATE_CTR(bnad
, netif_queue_wakeup
);
292 if (likely(test_bit(BNAD_TXQ_TX_STARTED
, &tcb
->flags
)))
293 bna_ib_ack(tcb
->i_dbell
, sent
);
295 smp_mb__before_clear_bit();
296 clear_bit(BNAD_TXQ_FREE_SENT
, &tcb
->flags
);
301 /* MSIX Tx Completion Handler */
303 bnad_msix_tx(int irq
, void *data
)
305 struct bna_tcb
*tcb
= (struct bna_tcb
*)data
;
306 struct bnad
*bnad
= tcb
->bnad
;
314 bnad_reset_rcb(struct bnad
*bnad
, struct bna_rcb
*rcb
)
316 struct bnad_unmap_q
*unmap_q
= rcb
->unmap_q
;
318 rcb
->producer_index
= 0;
319 rcb
->consumer_index
= 0;
321 unmap_q
->producer_index
= 0;
322 unmap_q
->consumer_index
= 0;
326 bnad_free_all_rxbufs(struct bnad
*bnad
, struct bna_rcb
*rcb
)
328 struct bnad_unmap_q
*unmap_q
;
329 struct bnad_skb_unmap
*unmap_array
;
333 unmap_q
= rcb
->unmap_q
;
334 unmap_array
= unmap_q
->unmap_array
;
335 for (unmap_cons
= 0; unmap_cons
< unmap_q
->q_depth
; unmap_cons
++) {
336 skb
= unmap_array
[unmap_cons
].skb
;
339 unmap_array
[unmap_cons
].skb
= NULL
;
340 dma_unmap_single(&bnad
->pcidev
->dev
,
341 dma_unmap_addr(&unmap_array
[unmap_cons
],
343 rcb
->rxq
->buffer_size
,
347 bnad_reset_rcb(bnad
, rcb
);
351 bnad_alloc_n_post_rxbufs(struct bnad
*bnad
, struct bna_rcb
*rcb
)
353 u16 to_alloc
, alloced
, unmap_prod
, wi_range
;
354 struct bnad_unmap_q
*unmap_q
= rcb
->unmap_q
;
355 struct bnad_skb_unmap
*unmap_array
;
356 struct bna_rxq_entry
*rxent
;
362 BNA_QE_FREE_CNT(unmap_q
, unmap_q
->q_depth
);
364 unmap_array
= unmap_q
->unmap_array
;
365 unmap_prod
= unmap_q
->producer_index
;
367 BNA_RXQ_QPGE_PTR_GET(unmap_prod
, rcb
->sw_qpt
, rxent
, wi_range
);
371 BNA_RXQ_QPGE_PTR_GET(unmap_prod
, rcb
->sw_qpt
, rxent
,
373 skb
= netdev_alloc_skb_ip_align(bnad
->netdev
,
374 rcb
->rxq
->buffer_size
);
375 if (unlikely(!skb
)) {
376 BNAD_UPDATE_CTR(bnad
, rxbuf_alloc_failed
);
377 rcb
->rxq
->rxbuf_alloc_failed
++;
380 unmap_array
[unmap_prod
].skb
= skb
;
381 dma_addr
= dma_map_single(&bnad
->pcidev
->dev
, skb
->data
,
382 rcb
->rxq
->buffer_size
,
384 dma_unmap_addr_set(&unmap_array
[unmap_prod
], dma_addr
,
386 BNA_SET_DMA_ADDR(dma_addr
, &rxent
->host_addr
);
387 BNA_QE_INDX_ADD(unmap_prod
, 1, unmap_q
->q_depth
);
395 if (likely(alloced
)) {
396 unmap_q
->producer_index
= unmap_prod
;
397 rcb
->producer_index
= unmap_prod
;
399 if (likely(test_bit(BNAD_RXQ_POST_OK
, &rcb
->flags
)))
400 bna_rxq_prod_indx_doorbell(rcb
);
405 bnad_refill_rxq(struct bnad
*bnad
, struct bna_rcb
*rcb
)
407 struct bnad_unmap_q
*unmap_q
= rcb
->unmap_q
;
409 if (!test_and_set_bit(BNAD_RXQ_REFILL
, &rcb
->flags
)) {
410 if (BNA_QE_FREE_CNT(unmap_q
, unmap_q
->q_depth
)
411 >> BNAD_RXQ_REFILL_THRESHOLD_SHIFT
)
412 bnad_alloc_n_post_rxbufs(bnad
, rcb
);
413 smp_mb__before_clear_bit();
414 clear_bit(BNAD_RXQ_REFILL
, &rcb
->flags
);
419 bnad_poll_cq(struct bnad
*bnad
, struct bna_ccb
*ccb
, int budget
)
421 struct bna_cq_entry
*cmpl
, *next_cmpl
;
422 struct bna_rcb
*rcb
= NULL
;
423 unsigned int wi_range
, packets
= 0, wis
= 0;
424 struct bnad_unmap_q
*unmap_q
;
425 struct bnad_skb_unmap
*unmap_array
;
427 u32 flags
, unmap_cons
;
428 struct bna_pkt_rate
*pkt_rt
= &ccb
->pkt_rate
;
429 struct bnad_rx_ctrl
*rx_ctrl
= (struct bnad_rx_ctrl
*)(ccb
->ctrl
);
431 set_bit(BNAD_FP_IN_RX_PATH
, &rx_ctrl
->flags
);
433 if (!test_bit(BNAD_RXQ_STARTED
, &ccb
->rcb
[0]->flags
)) {
434 clear_bit(BNAD_FP_IN_RX_PATH
, &rx_ctrl
->flags
);
438 prefetch(bnad
->netdev
);
439 BNA_CQ_QPGE_PTR_GET(ccb
->producer_index
, ccb
->sw_qpt
, cmpl
,
441 BUG_ON(!(wi_range
<= ccb
->q_depth
));
442 while (cmpl
->valid
&& packets
< budget
) {
444 BNA_UPDATE_PKT_CNT(pkt_rt
, ntohs(cmpl
->length
));
446 if (bna_is_small_rxq(cmpl
->rxq_id
))
451 unmap_q
= rcb
->unmap_q
;
452 unmap_array
= unmap_q
->unmap_array
;
453 unmap_cons
= unmap_q
->consumer_index
;
455 skb
= unmap_array
[unmap_cons
].skb
;
457 unmap_array
[unmap_cons
].skb
= NULL
;
458 dma_unmap_single(&bnad
->pcidev
->dev
,
459 dma_unmap_addr(&unmap_array
[unmap_cons
],
461 rcb
->rxq
->buffer_size
,
463 BNA_QE_INDX_ADD(unmap_q
->consumer_index
, 1, unmap_q
->q_depth
);
465 /* Should be more efficient ? Performance ? */
466 BNA_QE_INDX_ADD(rcb
->consumer_index
, 1, rcb
->q_depth
);
469 if (likely(--wi_range
))
470 next_cmpl
= cmpl
+ 1;
472 BNA_QE_INDX_ADD(ccb
->producer_index
, wis
, ccb
->q_depth
);
474 BNA_CQ_QPGE_PTR_GET(ccb
->producer_index
, ccb
->sw_qpt
,
475 next_cmpl
, wi_range
);
476 BUG_ON(!(wi_range
<= ccb
->q_depth
));
480 flags
= ntohl(cmpl
->flags
);
483 (BNA_CQ_EF_MAC_ERROR
| BNA_CQ_EF_FCS_ERROR
|
484 BNA_CQ_EF_TOO_LONG
))) {
485 dev_kfree_skb_any(skb
);
486 rcb
->rxq
->rx_packets_with_error
++;
490 skb_put(skb
, ntohs(cmpl
->length
));
492 ((bnad
->netdev
->features
& NETIF_F_RXCSUM
) &&
493 (((flags
& BNA_CQ_EF_IPV4
) &&
494 (flags
& BNA_CQ_EF_L3_CKSUM_OK
)) ||
495 (flags
& BNA_CQ_EF_IPV6
)) &&
496 (flags
& (BNA_CQ_EF_TCP
| BNA_CQ_EF_UDP
)) &&
497 (flags
& BNA_CQ_EF_L4_CKSUM_OK
)))
498 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
500 skb_checksum_none_assert(skb
);
502 rcb
->rxq
->rx_packets
++;
503 rcb
->rxq
->rx_bytes
+= skb
->len
;
504 skb
->protocol
= eth_type_trans(skb
, bnad
->netdev
);
506 if (flags
& BNA_CQ_EF_VLAN
)
507 __vlan_hwaccel_put_tag(skb
, ntohs(cmpl
->vlan_tag
));
509 if (skb
->ip_summed
== CHECKSUM_UNNECESSARY
)
510 napi_gro_receive(&rx_ctrl
->napi
, skb
);
512 netif_receive_skb(skb
);
520 BNA_QE_INDX_ADD(ccb
->producer_index
, wis
, ccb
->q_depth
);
522 if (likely(test_bit(BNAD_RXQ_STARTED
, &ccb
->rcb
[0]->flags
)))
523 bna_ib_ack_disable_irq(ccb
->i_dbell
, packets
);
525 bnad_refill_rxq(bnad
, ccb
->rcb
[0]);
527 bnad_refill_rxq(bnad
, ccb
->rcb
[1]);
529 clear_bit(BNAD_FP_IN_RX_PATH
, &rx_ctrl
->flags
);
535 bnad_netif_rx_schedule_poll(struct bnad
*bnad
, struct bna_ccb
*ccb
)
537 struct bnad_rx_ctrl
*rx_ctrl
= (struct bnad_rx_ctrl
*)(ccb
->ctrl
);
538 struct napi_struct
*napi
= &rx_ctrl
->napi
;
540 if (likely(napi_schedule_prep(napi
))) {
541 __napi_schedule(napi
);
542 rx_ctrl
->rx_schedule
++;
546 /* MSIX Rx Path Handler */
548 bnad_msix_rx(int irq
, void *data
)
550 struct bna_ccb
*ccb
= (struct bna_ccb
*)data
;
553 ((struct bnad_rx_ctrl
*)(ccb
->ctrl
))->rx_intr_ctr
++;
554 bnad_netif_rx_schedule_poll(ccb
->bnad
, ccb
);
560 /* Interrupt handlers */
562 /* Mbox Interrupt Handlers */
564 bnad_msix_mbox_handler(int irq
, void *data
)
568 struct bnad
*bnad
= (struct bnad
*)data
;
570 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
571 if (unlikely(test_bit(BNAD_RF_MBOX_IRQ_DISABLED
, &bnad
->run_flags
))) {
572 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
576 bna_intr_status_get(&bnad
->bna
, intr_status
);
578 if (BNA_IS_MBOX_ERR_INTR(&bnad
->bna
, intr_status
))
579 bna_mbox_handler(&bnad
->bna
, intr_status
);
581 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
587 bnad_isr(int irq
, void *data
)
592 struct bnad
*bnad
= (struct bnad
*)data
;
593 struct bnad_rx_info
*rx_info
;
594 struct bnad_rx_ctrl
*rx_ctrl
;
595 struct bna_tcb
*tcb
= NULL
;
597 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
598 if (unlikely(test_bit(BNAD_RF_MBOX_IRQ_DISABLED
, &bnad
->run_flags
))) {
599 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
603 bna_intr_status_get(&bnad
->bna
, intr_status
);
605 if (unlikely(!intr_status
)) {
606 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
610 if (BNA_IS_MBOX_ERR_INTR(&bnad
->bna
, intr_status
))
611 bna_mbox_handler(&bnad
->bna
, intr_status
);
613 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
615 if (!BNA_IS_INTX_DATA_INTR(intr_status
))
618 /* Process data interrupts */
620 for (i
= 0; i
< bnad
->num_tx
; i
++) {
621 for (j
= 0; j
< bnad
->num_txq_per_tx
; j
++) {
622 tcb
= bnad
->tx_info
[i
].tcb
[j
];
623 if (tcb
&& test_bit(BNAD_TXQ_TX_STARTED
, &tcb
->flags
))
624 bnad_tx(bnad
, bnad
->tx_info
[i
].tcb
[j
]);
628 for (i
= 0; i
< bnad
->num_rx
; i
++) {
629 rx_info
= &bnad
->rx_info
[i
];
632 for (j
= 0; j
< bnad
->num_rxp_per_rx
; j
++) {
633 rx_ctrl
= &rx_info
->rx_ctrl
[j
];
635 bnad_netif_rx_schedule_poll(bnad
,
643 * Called in interrupt / callback context
644 * with bna_lock held, so cfg_flags access is OK
647 bnad_enable_mbox_irq(struct bnad
*bnad
)
649 clear_bit(BNAD_RF_MBOX_IRQ_DISABLED
, &bnad
->run_flags
);
651 BNAD_UPDATE_CTR(bnad
, mbox_intr_enabled
);
655 * Called with bnad->bna_lock held b'cos of
656 * bnad->cfg_flags access.
659 bnad_disable_mbox_irq(struct bnad
*bnad
)
661 set_bit(BNAD_RF_MBOX_IRQ_DISABLED
, &bnad
->run_flags
);
663 BNAD_UPDATE_CTR(bnad
, mbox_intr_disabled
);
667 bnad_set_netdev_perm_addr(struct bnad
*bnad
)
669 struct net_device
*netdev
= bnad
->netdev
;
671 memcpy(netdev
->perm_addr
, &bnad
->perm_addr
, netdev
->addr_len
);
672 if (is_zero_ether_addr(netdev
->dev_addr
))
673 memcpy(netdev
->dev_addr
, &bnad
->perm_addr
, netdev
->addr_len
);
676 /* Control Path Handlers */
680 bnad_cb_mbox_intr_enable(struct bnad
*bnad
)
682 bnad_enable_mbox_irq(bnad
);
686 bnad_cb_mbox_intr_disable(struct bnad
*bnad
)
688 bnad_disable_mbox_irq(bnad
);
692 bnad_cb_ioceth_ready(struct bnad
*bnad
)
694 bnad
->bnad_completions
.ioc_comp_status
= BNA_CB_SUCCESS
;
695 complete(&bnad
->bnad_completions
.ioc_comp
);
699 bnad_cb_ioceth_failed(struct bnad
*bnad
)
701 bnad
->bnad_completions
.ioc_comp_status
= BNA_CB_FAIL
;
702 complete(&bnad
->bnad_completions
.ioc_comp
);
706 bnad_cb_ioceth_disabled(struct bnad
*bnad
)
708 bnad
->bnad_completions
.ioc_comp_status
= BNA_CB_SUCCESS
;
709 complete(&bnad
->bnad_completions
.ioc_comp
);
713 bnad_cb_enet_disabled(void *arg
)
715 struct bnad
*bnad
= (struct bnad
*)arg
;
717 netif_carrier_off(bnad
->netdev
);
718 complete(&bnad
->bnad_completions
.enet_comp
);
722 bnad_cb_ethport_link_status(struct bnad
*bnad
,
723 enum bna_link_status link_status
)
727 link_up
= (link_status
== BNA_LINK_UP
) || (link_status
== BNA_CEE_UP
);
729 if (link_status
== BNA_CEE_UP
) {
730 if (!test_bit(BNAD_RF_CEE_RUNNING
, &bnad
->run_flags
))
731 BNAD_UPDATE_CTR(bnad
, cee_toggle
);
732 set_bit(BNAD_RF_CEE_RUNNING
, &bnad
->run_flags
);
734 if (test_bit(BNAD_RF_CEE_RUNNING
, &bnad
->run_flags
))
735 BNAD_UPDATE_CTR(bnad
, cee_toggle
);
736 clear_bit(BNAD_RF_CEE_RUNNING
, &bnad
->run_flags
);
740 if (!netif_carrier_ok(bnad
->netdev
)) {
742 printk(KERN_WARNING
"bna: %s link up\n",
744 netif_carrier_on(bnad
->netdev
);
745 BNAD_UPDATE_CTR(bnad
, link_toggle
);
746 for (tx_id
= 0; tx_id
< bnad
->num_tx
; tx_id
++) {
747 for (tcb_id
= 0; tcb_id
< bnad
->num_txq_per_tx
;
749 struct bna_tcb
*tcb
=
750 bnad
->tx_info
[tx_id
].tcb
[tcb_id
];
757 if (test_bit(BNAD_TXQ_TX_STARTED
,
761 * Transmit Schedule */
762 printk(KERN_INFO
"bna: %s %d "
769 BNAD_UPDATE_CTR(bnad
,
775 BNAD_UPDATE_CTR(bnad
,
782 if (netif_carrier_ok(bnad
->netdev
)) {
783 printk(KERN_WARNING
"bna: %s link down\n",
785 netif_carrier_off(bnad
->netdev
);
786 BNAD_UPDATE_CTR(bnad
, link_toggle
);
792 bnad_cb_tx_disabled(void *arg
, struct bna_tx
*tx
)
794 struct bnad
*bnad
= (struct bnad
*)arg
;
796 complete(&bnad
->bnad_completions
.tx_comp
);
800 bnad_cb_tcb_setup(struct bnad
*bnad
, struct bna_tcb
*tcb
)
802 struct bnad_tx_info
*tx_info
=
803 (struct bnad_tx_info
*)tcb
->txq
->tx
->priv
;
804 struct bnad_unmap_q
*unmap_q
= tcb
->unmap_q
;
806 tx_info
->tcb
[tcb
->id
] = tcb
;
807 unmap_q
->producer_index
= 0;
808 unmap_q
->consumer_index
= 0;
809 unmap_q
->q_depth
= BNAD_TX_UNMAPQ_DEPTH
;
813 bnad_cb_tcb_destroy(struct bnad
*bnad
, struct bna_tcb
*tcb
)
815 struct bnad_tx_info
*tx_info
=
816 (struct bnad_tx_info
*)tcb
->txq
->tx
->priv
;
817 struct bnad_unmap_q
*unmap_q
= tcb
->unmap_q
;
819 while (test_and_set_bit(BNAD_TXQ_FREE_SENT
, &tcb
->flags
))
822 bnad_free_all_txbufs(bnad
, tcb
);
824 unmap_q
->producer_index
= 0;
825 unmap_q
->consumer_index
= 0;
827 smp_mb__before_clear_bit();
828 clear_bit(BNAD_TXQ_FREE_SENT
, &tcb
->flags
);
830 tx_info
->tcb
[tcb
->id
] = NULL
;
834 bnad_cb_rcb_setup(struct bnad
*bnad
, struct bna_rcb
*rcb
)
836 struct bnad_unmap_q
*unmap_q
= rcb
->unmap_q
;
838 unmap_q
->producer_index
= 0;
839 unmap_q
->consumer_index
= 0;
840 unmap_q
->q_depth
= BNAD_RX_UNMAPQ_DEPTH
;
844 bnad_cb_rcb_destroy(struct bnad
*bnad
, struct bna_rcb
*rcb
)
846 bnad_free_all_rxbufs(bnad
, rcb
);
850 bnad_cb_ccb_setup(struct bnad
*bnad
, struct bna_ccb
*ccb
)
852 struct bnad_rx_info
*rx_info
=
853 (struct bnad_rx_info
*)ccb
->cq
->rx
->priv
;
855 rx_info
->rx_ctrl
[ccb
->id
].ccb
= ccb
;
856 ccb
->ctrl
= &rx_info
->rx_ctrl
[ccb
->id
];
860 bnad_cb_ccb_destroy(struct bnad
*bnad
, struct bna_ccb
*ccb
)
862 struct bnad_rx_info
*rx_info
=
863 (struct bnad_rx_info
*)ccb
->cq
->rx
->priv
;
865 rx_info
->rx_ctrl
[ccb
->id
].ccb
= NULL
;
869 bnad_cb_tx_stall(struct bnad
*bnad
, struct bna_tx
*tx
)
871 struct bnad_tx_info
*tx_info
=
872 (struct bnad_tx_info
*)tx
->priv
;
877 for (i
= 0; i
< BNAD_MAX_TXQ_PER_TX
; i
++) {
878 tcb
= tx_info
->tcb
[i
];
882 clear_bit(BNAD_TXQ_TX_STARTED
, &tcb
->flags
);
883 netif_stop_subqueue(bnad
->netdev
, txq_id
);
884 printk(KERN_INFO
"bna: %s %d TXQ_STOPPED\n",
885 bnad
->netdev
->name
, txq_id
);
890 bnad_cb_tx_resume(struct bnad
*bnad
, struct bna_tx
*tx
)
892 struct bnad_tx_info
*tx_info
= (struct bnad_tx_info
*)tx
->priv
;
894 struct bnad_unmap_q
*unmap_q
;
898 for (i
= 0; i
< BNAD_MAX_TXQ_PER_TX
; i
++) {
899 tcb
= tx_info
->tcb
[i
];
904 unmap_q
= tcb
->unmap_q
;
906 if (test_bit(BNAD_TXQ_TX_STARTED
, &tcb
->flags
))
909 while (test_and_set_bit(BNAD_TXQ_FREE_SENT
, &tcb
->flags
))
912 bnad_free_all_txbufs(bnad
, tcb
);
914 unmap_q
->producer_index
= 0;
915 unmap_q
->consumer_index
= 0;
917 smp_mb__before_clear_bit();
918 clear_bit(BNAD_TXQ_FREE_SENT
, &tcb
->flags
);
920 set_bit(BNAD_TXQ_TX_STARTED
, &tcb
->flags
);
922 if (netif_carrier_ok(bnad
->netdev
)) {
923 printk(KERN_INFO
"bna: %s %d TXQ_STARTED\n",
924 bnad
->netdev
->name
, txq_id
);
925 netif_wake_subqueue(bnad
->netdev
, txq_id
);
926 BNAD_UPDATE_CTR(bnad
, netif_queue_wakeup
);
931 * Workaround for first ioceth enable failure & we
932 * get a 0 MAC address. We try to get the MAC address
935 if (is_zero_ether_addr(&bnad
->perm_addr
.mac
[0])) {
936 bna_enet_perm_mac_get(&bnad
->bna
.enet
, &bnad
->perm_addr
);
937 bnad_set_netdev_perm_addr(bnad
);
942 bnad_cb_tx_cleanup(struct bnad
*bnad
, struct bna_tx
*tx
)
944 struct bnad_tx_info
*tx_info
= (struct bnad_tx_info
*)tx
->priv
;
948 for (i
= 0; i
< BNAD_MAX_TXQ_PER_TX
; i
++) {
949 tcb
= tx_info
->tcb
[i
];
954 mdelay(BNAD_TXRX_SYNC_MDELAY
);
955 bna_tx_cleanup_complete(tx
);
959 bnad_cb_rx_stall(struct bnad
*bnad
, struct bna_rx
*rx
)
961 struct bnad_rx_info
*rx_info
= (struct bnad_rx_info
*)rx
->priv
;
963 struct bnad_rx_ctrl
*rx_ctrl
;
966 for (i
= 0; i
< BNAD_MAX_RXP_PER_RX
; i
++) {
967 rx_ctrl
= &rx_info
->rx_ctrl
[i
];
972 clear_bit(BNAD_RXQ_POST_OK
, &ccb
->rcb
[0]->flags
);
975 clear_bit(BNAD_RXQ_POST_OK
, &ccb
->rcb
[1]->flags
);
980 bnad_cb_rx_cleanup(struct bnad
*bnad
, struct bna_rx
*rx
)
982 struct bnad_rx_info
*rx_info
= (struct bnad_rx_info
*)rx
->priv
;
984 struct bnad_rx_ctrl
*rx_ctrl
;
987 mdelay(BNAD_TXRX_SYNC_MDELAY
);
989 for (i
= 0; i
< BNAD_MAX_RXP_PER_RX
; i
++) {
990 rx_ctrl
= &rx_info
->rx_ctrl
[i
];
995 clear_bit(BNAD_RXQ_STARTED
, &ccb
->rcb
[0]->flags
);
998 clear_bit(BNAD_RXQ_STARTED
, &ccb
->rcb
[1]->flags
);
1000 while (test_bit(BNAD_FP_IN_RX_PATH
, &rx_ctrl
->flags
))
1004 bna_rx_cleanup_complete(rx
);
1008 bnad_cb_rx_post(struct bnad
*bnad
, struct bna_rx
*rx
)
1010 struct bnad_rx_info
*rx_info
= (struct bnad_rx_info
*)rx
->priv
;
1011 struct bna_ccb
*ccb
;
1012 struct bna_rcb
*rcb
;
1013 struct bnad_rx_ctrl
*rx_ctrl
;
1014 struct bnad_unmap_q
*unmap_q
;
1018 for (i
= 0; i
< BNAD_MAX_RXP_PER_RX
; i
++) {
1019 rx_ctrl
= &rx_info
->rx_ctrl
[i
];
1024 bnad_cq_cmpl_init(bnad
, ccb
);
1026 for (j
= 0; j
< BNAD_MAX_RXQ_PER_RXP
; j
++) {
1030 bnad_free_all_rxbufs(bnad
, rcb
);
1032 set_bit(BNAD_RXQ_STARTED
, &rcb
->flags
);
1033 set_bit(BNAD_RXQ_POST_OK
, &rcb
->flags
);
1034 unmap_q
= rcb
->unmap_q
;
1036 /* Now allocate & post buffers for this RCB */
1037 /* !!Allocation in callback context */
1038 if (!test_and_set_bit(BNAD_RXQ_REFILL
, &rcb
->flags
)) {
1039 if (BNA_QE_FREE_CNT(unmap_q
, unmap_q
->q_depth
)
1040 >> BNAD_RXQ_REFILL_THRESHOLD_SHIFT
)
1041 bnad_alloc_n_post_rxbufs(bnad
, rcb
);
1042 smp_mb__before_clear_bit();
1043 clear_bit(BNAD_RXQ_REFILL
, &rcb
->flags
);
1050 bnad_cb_rx_disabled(void *arg
, struct bna_rx
*rx
)
1052 struct bnad
*bnad
= (struct bnad
*)arg
;
1054 complete(&bnad
->bnad_completions
.rx_comp
);
1058 bnad_cb_rx_mcast_add(struct bnad
*bnad
, struct bna_rx
*rx
)
1060 bnad
->bnad_completions
.mcast_comp_status
= BNA_CB_SUCCESS
;
1061 complete(&bnad
->bnad_completions
.mcast_comp
);
1065 bnad_cb_stats_get(struct bnad
*bnad
, enum bna_cb_status status
,
1066 struct bna_stats
*stats
)
1068 if (status
== BNA_CB_SUCCESS
)
1069 BNAD_UPDATE_CTR(bnad
, hw_stats_updates
);
1071 if (!netif_running(bnad
->netdev
) ||
1072 !test_bit(BNAD_RF_STATS_TIMER_RUNNING
, &bnad
->run_flags
))
1075 mod_timer(&bnad
->stats_timer
,
1076 jiffies
+ msecs_to_jiffies(BNAD_STATS_TIMER_FREQ
));
1080 bnad_cb_enet_mtu_set(struct bnad
*bnad
)
1082 bnad
->bnad_completions
.mtu_comp_status
= BNA_CB_SUCCESS
;
1083 complete(&bnad
->bnad_completions
.mtu_comp
);
1086 /* Resource allocation, free functions */
1089 bnad_mem_free(struct bnad
*bnad
,
1090 struct bna_mem_info
*mem_info
)
1095 if (mem_info
->mdl
== NULL
)
1098 for (i
= 0; i
< mem_info
->num
; i
++) {
1099 if (mem_info
->mdl
[i
].kva
!= NULL
) {
1100 if (mem_info
->mem_type
== BNA_MEM_T_DMA
) {
1101 BNA_GET_DMA_ADDR(&(mem_info
->mdl
[i
].dma
),
1103 dma_free_coherent(&bnad
->pcidev
->dev
,
1104 mem_info
->mdl
[i
].len
,
1105 mem_info
->mdl
[i
].kva
, dma_pa
);
1107 kfree(mem_info
->mdl
[i
].kva
);
1110 kfree(mem_info
->mdl
);
1111 mem_info
->mdl
= NULL
;
1115 bnad_mem_alloc(struct bnad
*bnad
,
1116 struct bna_mem_info
*mem_info
)
1121 if ((mem_info
->num
== 0) || (mem_info
->len
== 0)) {
1122 mem_info
->mdl
= NULL
;
1126 mem_info
->mdl
= kcalloc(mem_info
->num
, sizeof(struct bna_mem_descr
),
1128 if (mem_info
->mdl
== NULL
)
1131 if (mem_info
->mem_type
== BNA_MEM_T_DMA
) {
1132 for (i
= 0; i
< mem_info
->num
; i
++) {
1133 mem_info
->mdl
[i
].len
= mem_info
->len
;
1134 mem_info
->mdl
[i
].kva
=
1135 dma_alloc_coherent(&bnad
->pcidev
->dev
,
1136 mem_info
->len
, &dma_pa
,
1139 if (mem_info
->mdl
[i
].kva
== NULL
)
1142 BNA_SET_DMA_ADDR(dma_pa
,
1143 &(mem_info
->mdl
[i
].dma
));
1146 for (i
= 0; i
< mem_info
->num
; i
++) {
1147 mem_info
->mdl
[i
].len
= mem_info
->len
;
1148 mem_info
->mdl
[i
].kva
= kzalloc(mem_info
->len
,
1150 if (mem_info
->mdl
[i
].kva
== NULL
)
1158 bnad_mem_free(bnad
, mem_info
);
1162 /* Free IRQ for Mailbox */
1164 bnad_mbox_irq_free(struct bnad
*bnad
)
1167 unsigned long flags
;
1169 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1170 bnad_disable_mbox_irq(bnad
);
1171 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1173 irq
= BNAD_GET_MBOX_IRQ(bnad
);
1174 free_irq(irq
, bnad
);
1178 * Allocates IRQ for Mailbox, but keep it disabled
1179 * This will be enabled once we get the mbox enable callback
1183 bnad_mbox_irq_alloc(struct bnad
*bnad
)
1186 unsigned long irq_flags
, flags
;
1188 irq_handler_t irq_handler
;
1190 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1191 if (bnad
->cfg_flags
& BNAD_CF_MSIX
) {
1192 irq_handler
= (irq_handler_t
)bnad_msix_mbox_handler
;
1193 irq
= bnad
->msix_table
[BNAD_MAILBOX_MSIX_INDEX
].vector
;
1196 irq_handler
= (irq_handler_t
)bnad_isr
;
1197 irq
= bnad
->pcidev
->irq
;
1198 irq_flags
= IRQF_SHARED
;
1201 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1202 sprintf(bnad
->mbox_irq_name
, "%s", BNAD_NAME
);
1205 * Set the Mbox IRQ disable flag, so that the IRQ handler
1206 * called from request_irq() for SHARED IRQs do not execute
1208 set_bit(BNAD_RF_MBOX_IRQ_DISABLED
, &bnad
->run_flags
);
1210 BNAD_UPDATE_CTR(bnad
, mbox_intr_disabled
);
1212 err
= request_irq(irq
, irq_handler
, irq_flags
,
1213 bnad
->mbox_irq_name
, bnad
);
1219 bnad_txrx_irq_free(struct bnad
*bnad
, struct bna_intr_info
*intr_info
)
1221 kfree(intr_info
->idl
);
1222 intr_info
->idl
= NULL
;
1225 /* Allocates Interrupt Descriptor List for MSIX/INT-X vectors */
1227 bnad_txrx_irq_alloc(struct bnad
*bnad
, enum bnad_intr_source src
,
1228 u32 txrx_id
, struct bna_intr_info
*intr_info
)
1230 int i
, vector_start
= 0;
1232 unsigned long flags
;
1234 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1235 cfg_flags
= bnad
->cfg_flags
;
1236 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1238 if (cfg_flags
& BNAD_CF_MSIX
) {
1239 intr_info
->intr_type
= BNA_INTR_T_MSIX
;
1240 intr_info
->idl
= kcalloc(intr_info
->num
,
1241 sizeof(struct bna_intr_descr
),
1243 if (!intr_info
->idl
)
1248 vector_start
= BNAD_MAILBOX_MSIX_VECTORS
+ txrx_id
;
1252 vector_start
= BNAD_MAILBOX_MSIX_VECTORS
+
1253 (bnad
->num_tx
* bnad
->num_txq_per_tx
) +
1261 for (i
= 0; i
< intr_info
->num
; i
++)
1262 intr_info
->idl
[i
].vector
= vector_start
+ i
;
1264 intr_info
->intr_type
= BNA_INTR_T_INTX
;
1266 intr_info
->idl
= kcalloc(intr_info
->num
,
1267 sizeof(struct bna_intr_descr
),
1269 if (!intr_info
->idl
)
1274 intr_info
->idl
[0].vector
= BNAD_INTX_TX_IB_BITMASK
;
1278 intr_info
->idl
[0].vector
= BNAD_INTX_RX_IB_BITMASK
;
1286 * NOTE: Should be called for MSIX only
1287 * Unregisters Tx MSIX vector(s) from the kernel
1290 bnad_tx_msix_unregister(struct bnad
*bnad
, struct bnad_tx_info
*tx_info
,
1296 for (i
= 0; i
< num_txqs
; i
++) {
1297 if (tx_info
->tcb
[i
] == NULL
)
1300 vector_num
= tx_info
->tcb
[i
]->intr_vector
;
1301 free_irq(bnad
->msix_table
[vector_num
].vector
, tx_info
->tcb
[i
]);
1306 * NOTE: Should be called for MSIX only
1307 * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel
1310 bnad_tx_msix_register(struct bnad
*bnad
, struct bnad_tx_info
*tx_info
,
1311 u32 tx_id
, int num_txqs
)
1317 for (i
= 0; i
< num_txqs
; i
++) {
1318 vector_num
= tx_info
->tcb
[i
]->intr_vector
;
1319 sprintf(tx_info
->tcb
[i
]->name
, "%s TXQ %d", bnad
->netdev
->name
,
1320 tx_id
+ tx_info
->tcb
[i
]->id
);
1321 err
= request_irq(bnad
->msix_table
[vector_num
].vector
,
1322 (irq_handler_t
)bnad_msix_tx
, 0,
1323 tx_info
->tcb
[i
]->name
,
1333 bnad_tx_msix_unregister(bnad
, tx_info
, (i
- 1));
1338 * NOTE: Should be called for MSIX only
1339 * Unregisters Rx MSIX vector(s) from the kernel
1342 bnad_rx_msix_unregister(struct bnad
*bnad
, struct bnad_rx_info
*rx_info
,
1348 for (i
= 0; i
< num_rxps
; i
++) {
1349 if (rx_info
->rx_ctrl
[i
].ccb
== NULL
)
1352 vector_num
= rx_info
->rx_ctrl
[i
].ccb
->intr_vector
;
1353 free_irq(bnad
->msix_table
[vector_num
].vector
,
1354 rx_info
->rx_ctrl
[i
].ccb
);
1359 * NOTE: Should be called for MSIX only
1360 * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel
1363 bnad_rx_msix_register(struct bnad
*bnad
, struct bnad_rx_info
*rx_info
,
1364 u32 rx_id
, int num_rxps
)
1370 for (i
= 0; i
< num_rxps
; i
++) {
1371 vector_num
= rx_info
->rx_ctrl
[i
].ccb
->intr_vector
;
1372 sprintf(rx_info
->rx_ctrl
[i
].ccb
->name
, "%s CQ %d",
1374 rx_id
+ rx_info
->rx_ctrl
[i
].ccb
->id
);
1375 err
= request_irq(bnad
->msix_table
[vector_num
].vector
,
1376 (irq_handler_t
)bnad_msix_rx
, 0,
1377 rx_info
->rx_ctrl
[i
].ccb
->name
,
1378 rx_info
->rx_ctrl
[i
].ccb
);
1387 bnad_rx_msix_unregister(bnad
, rx_info
, (i
- 1));
1391 /* Free Tx object Resources */
1393 bnad_tx_res_free(struct bnad
*bnad
, struct bna_res_info
*res_info
)
1397 for (i
= 0; i
< BNA_TX_RES_T_MAX
; i
++) {
1398 if (res_info
[i
].res_type
== BNA_RES_T_MEM
)
1399 bnad_mem_free(bnad
, &res_info
[i
].res_u
.mem_info
);
1400 else if (res_info
[i
].res_type
== BNA_RES_T_INTR
)
1401 bnad_txrx_irq_free(bnad
, &res_info
[i
].res_u
.intr_info
);
1405 /* Allocates memory and interrupt resources for Tx object */
1407 bnad_tx_res_alloc(struct bnad
*bnad
, struct bna_res_info
*res_info
,
1412 for (i
= 0; i
< BNA_TX_RES_T_MAX
; i
++) {
1413 if (res_info
[i
].res_type
== BNA_RES_T_MEM
)
1414 err
= bnad_mem_alloc(bnad
,
1415 &res_info
[i
].res_u
.mem_info
);
1416 else if (res_info
[i
].res_type
== BNA_RES_T_INTR
)
1417 err
= bnad_txrx_irq_alloc(bnad
, BNAD_INTR_TX
, tx_id
,
1418 &res_info
[i
].res_u
.intr_info
);
1425 bnad_tx_res_free(bnad
, res_info
);
1429 /* Free Rx object Resources */
1431 bnad_rx_res_free(struct bnad
*bnad
, struct bna_res_info
*res_info
)
1435 for (i
= 0; i
< BNA_RX_RES_T_MAX
; i
++) {
1436 if (res_info
[i
].res_type
== BNA_RES_T_MEM
)
1437 bnad_mem_free(bnad
, &res_info
[i
].res_u
.mem_info
);
1438 else if (res_info
[i
].res_type
== BNA_RES_T_INTR
)
1439 bnad_txrx_irq_free(bnad
, &res_info
[i
].res_u
.intr_info
);
1443 /* Allocates memory and interrupt resources for Rx object */
1445 bnad_rx_res_alloc(struct bnad
*bnad
, struct bna_res_info
*res_info
,
1450 /* All memory needs to be allocated before setup_ccbs */
1451 for (i
= 0; i
< BNA_RX_RES_T_MAX
; i
++) {
1452 if (res_info
[i
].res_type
== BNA_RES_T_MEM
)
1453 err
= bnad_mem_alloc(bnad
,
1454 &res_info
[i
].res_u
.mem_info
);
1455 else if (res_info
[i
].res_type
== BNA_RES_T_INTR
)
1456 err
= bnad_txrx_irq_alloc(bnad
, BNAD_INTR_RX
, rx_id
,
1457 &res_info
[i
].res_u
.intr_info
);
1464 bnad_rx_res_free(bnad
, res_info
);
1468 /* Timer callbacks */
1471 bnad_ioc_timeout(unsigned long data
)
1473 struct bnad
*bnad
= (struct bnad
*)data
;
1474 unsigned long flags
;
1476 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1477 bfa_nw_ioc_timeout((void *) &bnad
->bna
.ioceth
.ioc
);
1478 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1482 bnad_ioc_hb_check(unsigned long data
)
1484 struct bnad
*bnad
= (struct bnad
*)data
;
1485 unsigned long flags
;
1487 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1488 bfa_nw_ioc_hb_check((void *) &bnad
->bna
.ioceth
.ioc
);
1489 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1493 bnad_iocpf_timeout(unsigned long data
)
1495 struct bnad
*bnad
= (struct bnad
*)data
;
1496 unsigned long flags
;
1498 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1499 bfa_nw_iocpf_timeout((void *) &bnad
->bna
.ioceth
.ioc
);
1500 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1504 bnad_iocpf_sem_timeout(unsigned long data
)
1506 struct bnad
*bnad
= (struct bnad
*)data
;
1507 unsigned long flags
;
1509 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1510 bfa_nw_iocpf_sem_timeout((void *) &bnad
->bna
.ioceth
.ioc
);
1511 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1515 * All timer routines use bnad->bna_lock to protect against
1516 * the following race, which may occur in case of no locking:
1524 /* b) Dynamic Interrupt Moderation Timer */
1526 bnad_dim_timeout(unsigned long data
)
1528 struct bnad
*bnad
= (struct bnad
*)data
;
1529 struct bnad_rx_info
*rx_info
;
1530 struct bnad_rx_ctrl
*rx_ctrl
;
1532 unsigned long flags
;
1534 if (!netif_carrier_ok(bnad
->netdev
))
1537 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1538 for (i
= 0; i
< bnad
->num_rx
; i
++) {
1539 rx_info
= &bnad
->rx_info
[i
];
1542 for (j
= 0; j
< bnad
->num_rxp_per_rx
; j
++) {
1543 rx_ctrl
= &rx_info
->rx_ctrl
[j
];
1546 bna_rx_dim_update(rx_ctrl
->ccb
);
1550 /* Check for BNAD_CF_DIM_ENABLED, does not eleminate a race */
1551 if (test_bit(BNAD_RF_DIM_TIMER_RUNNING
, &bnad
->run_flags
))
1552 mod_timer(&bnad
->dim_timer
,
1553 jiffies
+ msecs_to_jiffies(BNAD_DIM_TIMER_FREQ
));
1554 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1557 /* c) Statistics Timer */
1559 bnad_stats_timeout(unsigned long data
)
1561 struct bnad
*bnad
= (struct bnad
*)data
;
1562 unsigned long flags
;
1564 if (!netif_running(bnad
->netdev
) ||
1565 !test_bit(BNAD_RF_STATS_TIMER_RUNNING
, &bnad
->run_flags
))
1568 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1569 bna_hw_stats_get(&bnad
->bna
);
1570 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1574 * Set up timer for DIM
1575 * Called with bnad->bna_lock held
1578 bnad_dim_timer_start(struct bnad
*bnad
)
1580 if (bnad
->cfg_flags
& BNAD_CF_DIM_ENABLED
&&
1581 !test_bit(BNAD_RF_DIM_TIMER_RUNNING
, &bnad
->run_flags
)) {
1582 setup_timer(&bnad
->dim_timer
, bnad_dim_timeout
,
1583 (unsigned long)bnad
);
1584 set_bit(BNAD_RF_DIM_TIMER_RUNNING
, &bnad
->run_flags
);
1585 mod_timer(&bnad
->dim_timer
,
1586 jiffies
+ msecs_to_jiffies(BNAD_DIM_TIMER_FREQ
));
1591 * Set up timer for statistics
1592 * Called with mutex_lock(&bnad->conf_mutex) held
1595 bnad_stats_timer_start(struct bnad
*bnad
)
1597 unsigned long flags
;
1599 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1600 if (!test_and_set_bit(BNAD_RF_STATS_TIMER_RUNNING
, &bnad
->run_flags
)) {
1601 setup_timer(&bnad
->stats_timer
, bnad_stats_timeout
,
1602 (unsigned long)bnad
);
1603 mod_timer(&bnad
->stats_timer
,
1604 jiffies
+ msecs_to_jiffies(BNAD_STATS_TIMER_FREQ
));
1606 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1610 * Stops the stats timer
1611 * Called with mutex_lock(&bnad->conf_mutex) held
1614 bnad_stats_timer_stop(struct bnad
*bnad
)
1617 unsigned long flags
;
1619 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1620 if (test_and_clear_bit(BNAD_RF_STATS_TIMER_RUNNING
, &bnad
->run_flags
))
1622 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1624 del_timer_sync(&bnad
->stats_timer
);
1630 bnad_netdev_mc_list_get(struct net_device
*netdev
, u8
*mc_list
)
1632 int i
= 1; /* Index 0 has broadcast address */
1633 struct netdev_hw_addr
*mc_addr
;
1635 netdev_for_each_mc_addr(mc_addr
, netdev
) {
1636 memcpy(&mc_list
[i
* ETH_ALEN
], &mc_addr
->addr
[0],
1643 bnad_napi_poll_rx(struct napi_struct
*napi
, int budget
)
1645 struct bnad_rx_ctrl
*rx_ctrl
=
1646 container_of(napi
, struct bnad_rx_ctrl
, napi
);
1647 struct bnad
*bnad
= rx_ctrl
->bnad
;
1650 rx_ctrl
->rx_poll_ctr
++;
1652 if (!netif_carrier_ok(bnad
->netdev
))
1655 rcvd
= bnad_poll_cq(bnad
, rx_ctrl
->ccb
, budget
);
1660 napi_complete(napi
);
1662 rx_ctrl
->rx_complete
++;
1665 bnad_enable_rx_irq_unsafe(rx_ctrl
->ccb
);
1670 #define BNAD_NAPI_POLL_QUOTA 64
1672 bnad_napi_init(struct bnad
*bnad
, u32 rx_id
)
1674 struct bnad_rx_ctrl
*rx_ctrl
;
1677 /* Initialize & enable NAPI */
1678 for (i
= 0; i
< bnad
->num_rxp_per_rx
; i
++) {
1679 rx_ctrl
= &bnad
->rx_info
[rx_id
].rx_ctrl
[i
];
1680 netif_napi_add(bnad
->netdev
, &rx_ctrl
->napi
,
1681 bnad_napi_poll_rx
, BNAD_NAPI_POLL_QUOTA
);
1686 bnad_napi_enable(struct bnad
*bnad
, u32 rx_id
)
1688 struct bnad_rx_ctrl
*rx_ctrl
;
1691 /* Initialize & enable NAPI */
1692 for (i
= 0; i
< bnad
->num_rxp_per_rx
; i
++) {
1693 rx_ctrl
= &bnad
->rx_info
[rx_id
].rx_ctrl
[i
];
1695 napi_enable(&rx_ctrl
->napi
);
1700 bnad_napi_disable(struct bnad
*bnad
, u32 rx_id
)
1704 /* First disable and then clean up */
1705 for (i
= 0; i
< bnad
->num_rxp_per_rx
; i
++) {
1706 napi_disable(&bnad
->rx_info
[rx_id
].rx_ctrl
[i
].napi
);
1707 netif_napi_del(&bnad
->rx_info
[rx_id
].rx_ctrl
[i
].napi
);
1711 /* Should be held with conf_lock held */
1713 bnad_cleanup_tx(struct bnad
*bnad
, u32 tx_id
)
1715 struct bnad_tx_info
*tx_info
= &bnad
->tx_info
[tx_id
];
1716 struct bna_res_info
*res_info
= &bnad
->tx_res_info
[tx_id
].res_info
[0];
1717 unsigned long flags
;
1722 init_completion(&bnad
->bnad_completions
.tx_comp
);
1723 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1724 bna_tx_disable(tx_info
->tx
, BNA_HARD_CLEANUP
, bnad_cb_tx_disabled
);
1725 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1726 wait_for_completion(&bnad
->bnad_completions
.tx_comp
);
1728 if (tx_info
->tcb
[0]->intr_type
== BNA_INTR_T_MSIX
)
1729 bnad_tx_msix_unregister(bnad
, tx_info
,
1730 bnad
->num_txq_per_tx
);
1733 tasklet_kill(&bnad
->tx_free_tasklet
);
1735 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1736 bna_tx_destroy(tx_info
->tx
);
1737 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1742 bnad_tx_res_free(bnad
, res_info
);
1745 /* Should be held with conf_lock held */
1747 bnad_setup_tx(struct bnad
*bnad
, u32 tx_id
)
1750 struct bnad_tx_info
*tx_info
= &bnad
->tx_info
[tx_id
];
1751 struct bna_res_info
*res_info
= &bnad
->tx_res_info
[tx_id
].res_info
[0];
1752 struct bna_intr_info
*intr_info
=
1753 &res_info
[BNA_TX_RES_INTR_T_TXCMPL
].res_u
.intr_info
;
1754 struct bna_tx_config
*tx_config
= &bnad
->tx_config
[tx_id
];
1755 static const struct bna_tx_event_cbfn tx_cbfn
= {
1756 .tcb_setup_cbfn
= bnad_cb_tcb_setup
,
1757 .tcb_destroy_cbfn
= bnad_cb_tcb_destroy
,
1758 .tx_stall_cbfn
= bnad_cb_tx_stall
,
1759 .tx_resume_cbfn
= bnad_cb_tx_resume
,
1760 .tx_cleanup_cbfn
= bnad_cb_tx_cleanup
,
1764 unsigned long flags
;
1766 tx_info
->tx_id
= tx_id
;
1768 /* Initialize the Tx object configuration */
1769 tx_config
->num_txq
= bnad
->num_txq_per_tx
;
1770 tx_config
->txq_depth
= bnad
->txq_depth
;
1771 tx_config
->tx_type
= BNA_TX_T_REGULAR
;
1772 tx_config
->coalescing_timeo
= bnad
->tx_coalescing_timeo
;
1774 /* Get BNA's resource requirement for one tx object */
1775 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1776 bna_tx_res_req(bnad
->num_txq_per_tx
,
1777 bnad
->txq_depth
, res_info
);
1778 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1780 /* Fill Unmap Q memory requirements */
1781 BNAD_FILL_UNMAPQ_MEM_REQ(
1782 &res_info
[BNA_TX_RES_MEM_T_UNMAPQ
],
1783 bnad
->num_txq_per_tx
,
1784 BNAD_TX_UNMAPQ_DEPTH
);
1786 /* Allocate resources */
1787 err
= bnad_tx_res_alloc(bnad
, res_info
, tx_id
);
1791 /* Ask BNA to create one Tx object, supplying required resources */
1792 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1793 tx
= bna_tx_create(&bnad
->bna
, bnad
, tx_config
, &tx_cbfn
, res_info
,
1795 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1800 /* Register ISR for the Tx object */
1801 if (intr_info
->intr_type
== BNA_INTR_T_MSIX
) {
1802 err
= bnad_tx_msix_register(bnad
, tx_info
,
1803 tx_id
, bnad
->num_txq_per_tx
);
1808 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1810 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1815 bnad_tx_res_free(bnad
, res_info
);
1819 /* Setup the rx config for bna_rx_create */
1820 /* bnad decides the configuration */
1822 bnad_init_rx_config(struct bnad
*bnad
, struct bna_rx_config
*rx_config
)
1824 rx_config
->rx_type
= BNA_RX_T_REGULAR
;
1825 rx_config
->num_paths
= bnad
->num_rxp_per_rx
;
1826 rx_config
->coalescing_timeo
= bnad
->rx_coalescing_timeo
;
1828 if (bnad
->num_rxp_per_rx
> 1) {
1829 rx_config
->rss_status
= BNA_STATUS_T_ENABLED
;
1830 rx_config
->rss_config
.hash_type
=
1831 (BFI_ENET_RSS_IPV6
|
1832 BFI_ENET_RSS_IPV6_TCP
|
1834 BFI_ENET_RSS_IPV4_TCP
);
1835 rx_config
->rss_config
.hash_mask
=
1836 bnad
->num_rxp_per_rx
- 1;
1837 get_random_bytes(rx_config
->rss_config
.toeplitz_hash_key
,
1838 sizeof(rx_config
->rss_config
.toeplitz_hash_key
));
1840 rx_config
->rss_status
= BNA_STATUS_T_DISABLED
;
1841 memset(&rx_config
->rss_config
, 0,
1842 sizeof(rx_config
->rss_config
));
1844 rx_config
->rxp_type
= BNA_RXP_SLR
;
1845 rx_config
->q_depth
= bnad
->rxq_depth
;
1847 rx_config
->small_buff_size
= BFI_SMALL_RXBUF_SIZE
;
1849 rx_config
->vlan_strip_status
= BNA_STATUS_T_ENABLED
;
1853 bnad_rx_ctrl_init(struct bnad
*bnad
, u32 rx_id
)
1855 struct bnad_rx_info
*rx_info
= &bnad
->rx_info
[rx_id
];
1858 for (i
= 0; i
< bnad
->num_rxp_per_rx
; i
++)
1859 rx_info
->rx_ctrl
[i
].bnad
= bnad
;
1862 /* Called with mutex_lock(&bnad->conf_mutex) held */
1864 bnad_cleanup_rx(struct bnad
*bnad
, u32 rx_id
)
1866 struct bnad_rx_info
*rx_info
= &bnad
->rx_info
[rx_id
];
1867 struct bna_rx_config
*rx_config
= &bnad
->rx_config
[rx_id
];
1868 struct bna_res_info
*res_info
= &bnad
->rx_res_info
[rx_id
].res_info
[0];
1869 unsigned long flags
;
1876 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1877 if (bnad
->cfg_flags
& BNAD_CF_DIM_ENABLED
&&
1878 test_bit(BNAD_RF_DIM_TIMER_RUNNING
, &bnad
->run_flags
)) {
1879 clear_bit(BNAD_RF_DIM_TIMER_RUNNING
, &bnad
->run_flags
);
1882 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1884 del_timer_sync(&bnad
->dim_timer
);
1887 init_completion(&bnad
->bnad_completions
.rx_comp
);
1888 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1889 bna_rx_disable(rx_info
->rx
, BNA_HARD_CLEANUP
, bnad_cb_rx_disabled
);
1890 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1891 wait_for_completion(&bnad
->bnad_completions
.rx_comp
);
1893 if (rx_info
->rx_ctrl
[0].ccb
->intr_type
== BNA_INTR_T_MSIX
)
1894 bnad_rx_msix_unregister(bnad
, rx_info
, rx_config
->num_paths
);
1896 bnad_napi_disable(bnad
, rx_id
);
1898 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1899 bna_rx_destroy(rx_info
->rx
);
1903 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1905 bnad_rx_res_free(bnad
, res_info
);
1908 /* Called with mutex_lock(&bnad->conf_mutex) held */
1910 bnad_setup_rx(struct bnad
*bnad
, u32 rx_id
)
1913 struct bnad_rx_info
*rx_info
= &bnad
->rx_info
[rx_id
];
1914 struct bna_res_info
*res_info
= &bnad
->rx_res_info
[rx_id
].res_info
[0];
1915 struct bna_intr_info
*intr_info
=
1916 &res_info
[BNA_RX_RES_T_INTR
].res_u
.intr_info
;
1917 struct bna_rx_config
*rx_config
= &bnad
->rx_config
[rx_id
];
1918 static const struct bna_rx_event_cbfn rx_cbfn
= {
1919 .rcb_setup_cbfn
= bnad_cb_rcb_setup
,
1920 .rcb_destroy_cbfn
= bnad_cb_rcb_destroy
,
1921 .ccb_setup_cbfn
= bnad_cb_ccb_setup
,
1922 .ccb_destroy_cbfn
= bnad_cb_ccb_destroy
,
1923 .rx_stall_cbfn
= bnad_cb_rx_stall
,
1924 .rx_cleanup_cbfn
= bnad_cb_rx_cleanup
,
1925 .rx_post_cbfn
= bnad_cb_rx_post
,
1928 unsigned long flags
;
1930 rx_info
->rx_id
= rx_id
;
1932 /* Initialize the Rx object configuration */
1933 bnad_init_rx_config(bnad
, rx_config
);
1935 /* Get BNA's resource requirement for one Rx object */
1936 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1937 bna_rx_res_req(rx_config
, res_info
);
1938 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1940 /* Fill Unmap Q memory requirements */
1941 BNAD_FILL_UNMAPQ_MEM_REQ(
1942 &res_info
[BNA_RX_RES_MEM_T_UNMAPQ
],
1943 rx_config
->num_paths
+
1944 ((rx_config
->rxp_type
== BNA_RXP_SINGLE
) ? 0 :
1945 rx_config
->num_paths
), BNAD_RX_UNMAPQ_DEPTH
);
1947 /* Allocate resource */
1948 err
= bnad_rx_res_alloc(bnad
, res_info
, rx_id
);
1952 bnad_rx_ctrl_init(bnad
, rx_id
);
1954 /* Ask BNA to create one Rx object, supplying required resources */
1955 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1956 rx
= bna_rx_create(&bnad
->bna
, bnad
, rx_config
, &rx_cbfn
, res_info
,
1960 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1964 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1967 * Init NAPI, so that state is set to NAPI_STATE_SCHED,
1968 * so that IRQ handler cannot schedule NAPI at this point.
1970 bnad_napi_init(bnad
, rx_id
);
1972 /* Register ISR for the Rx object */
1973 if (intr_info
->intr_type
== BNA_INTR_T_MSIX
) {
1974 err
= bnad_rx_msix_register(bnad
, rx_info
, rx_id
,
1975 rx_config
->num_paths
);
1980 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1982 /* Set up Dynamic Interrupt Moderation Vector */
1983 if (bnad
->cfg_flags
& BNAD_CF_DIM_ENABLED
)
1984 bna_rx_dim_reconfig(&bnad
->bna
, bna_napi_dim_vector
);
1986 /* Enable VLAN filtering only on the default Rx */
1987 bna_rx_vlanfilter_enable(rx
);
1989 /* Start the DIM timer */
1990 bnad_dim_timer_start(bnad
);
1994 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1996 /* Enable scheduling of NAPI */
1997 bnad_napi_enable(bnad
, rx_id
);
2002 bnad_cleanup_rx(bnad
, rx_id
);
2006 /* Called with conf_lock & bnad->bna_lock held */
2008 bnad_tx_coalescing_timeo_set(struct bnad
*bnad
)
2010 struct bnad_tx_info
*tx_info
;
2012 tx_info
= &bnad
->tx_info
[0];
2016 bna_tx_coalescing_timeo_set(tx_info
->tx
, bnad
->tx_coalescing_timeo
);
2019 /* Called with conf_lock & bnad->bna_lock held */
2021 bnad_rx_coalescing_timeo_set(struct bnad
*bnad
)
2023 struct bnad_rx_info
*rx_info
;
2026 for (i
= 0; i
< bnad
->num_rx
; i
++) {
2027 rx_info
= &bnad
->rx_info
[i
];
2030 bna_rx_coalescing_timeo_set(rx_info
->rx
,
2031 bnad
->rx_coalescing_timeo
);
2036 * Called with bnad->bna_lock held
2039 bnad_mac_addr_set_locked(struct bnad
*bnad
, u8
*mac_addr
)
2043 if (!is_valid_ether_addr(mac_addr
))
2044 return -EADDRNOTAVAIL
;
2046 /* If datapath is down, pretend everything went through */
2047 if (!bnad
->rx_info
[0].rx
)
2050 ret
= bna_rx_ucast_set(bnad
->rx_info
[0].rx
, mac_addr
, NULL
);
2051 if (ret
!= BNA_CB_SUCCESS
)
2052 return -EADDRNOTAVAIL
;
2057 /* Should be called with conf_lock held */
2059 bnad_enable_default_bcast(struct bnad
*bnad
)
2061 struct bnad_rx_info
*rx_info
= &bnad
->rx_info
[0];
2063 unsigned long flags
;
2065 init_completion(&bnad
->bnad_completions
.mcast_comp
);
2067 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2068 ret
= bna_rx_mcast_add(rx_info
->rx
, (u8
*)bnad_bcast_addr
,
2069 bnad_cb_rx_mcast_add
);
2070 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2072 if (ret
== BNA_CB_SUCCESS
)
2073 wait_for_completion(&bnad
->bnad_completions
.mcast_comp
);
2077 if (bnad
->bnad_completions
.mcast_comp_status
!= BNA_CB_SUCCESS
)
2083 /* Called with mutex_lock(&bnad->conf_mutex) held */
2085 bnad_restore_vlans(struct bnad
*bnad
, u32 rx_id
)
2088 unsigned long flags
;
2090 for_each_set_bit(vid
, bnad
->active_vlans
, VLAN_N_VID
) {
2091 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2092 bna_rx_vlan_add(bnad
->rx_info
[rx_id
].rx
, vid
);
2093 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2097 /* Statistics utilities */
2099 bnad_netdev_qstats_fill(struct bnad
*bnad
, struct rtnl_link_stats64
*stats
)
2103 for (i
= 0; i
< bnad
->num_rx
; i
++) {
2104 for (j
= 0; j
< bnad
->num_rxp_per_rx
; j
++) {
2105 if (bnad
->rx_info
[i
].rx_ctrl
[j
].ccb
) {
2106 stats
->rx_packets
+= bnad
->rx_info
[i
].
2107 rx_ctrl
[j
].ccb
->rcb
[0]->rxq
->rx_packets
;
2108 stats
->rx_bytes
+= bnad
->rx_info
[i
].
2109 rx_ctrl
[j
].ccb
->rcb
[0]->rxq
->rx_bytes
;
2110 if (bnad
->rx_info
[i
].rx_ctrl
[j
].ccb
->rcb
[1] &&
2111 bnad
->rx_info
[i
].rx_ctrl
[j
].ccb
->
2113 stats
->rx_packets
+=
2114 bnad
->rx_info
[i
].rx_ctrl
[j
].
2115 ccb
->rcb
[1]->rxq
->rx_packets
;
2117 bnad
->rx_info
[i
].rx_ctrl
[j
].
2118 ccb
->rcb
[1]->rxq
->rx_bytes
;
2123 for (i
= 0; i
< bnad
->num_tx
; i
++) {
2124 for (j
= 0; j
< bnad
->num_txq_per_tx
; j
++) {
2125 if (bnad
->tx_info
[i
].tcb
[j
]) {
2126 stats
->tx_packets
+=
2127 bnad
->tx_info
[i
].tcb
[j
]->txq
->tx_packets
;
2129 bnad
->tx_info
[i
].tcb
[j
]->txq
->tx_bytes
;
2136 * Must be called with the bna_lock held.
2139 bnad_netdev_hwstats_fill(struct bnad
*bnad
, struct rtnl_link_stats64
*stats
)
2141 struct bfi_enet_stats_mac
*mac_stats
;
2145 mac_stats
= &bnad
->stats
.bna_stats
->hw_stats
.mac_stats
;
2147 mac_stats
->rx_fcs_error
+ mac_stats
->rx_alignment_error
+
2148 mac_stats
->rx_frame_length_error
+ mac_stats
->rx_code_error
+
2149 mac_stats
->rx_undersize
;
2150 stats
->tx_errors
= mac_stats
->tx_fcs_error
+
2151 mac_stats
->tx_undersize
;
2152 stats
->rx_dropped
= mac_stats
->rx_drop
;
2153 stats
->tx_dropped
= mac_stats
->tx_drop
;
2154 stats
->multicast
= mac_stats
->rx_multicast
;
2155 stats
->collisions
= mac_stats
->tx_total_collision
;
2157 stats
->rx_length_errors
= mac_stats
->rx_frame_length_error
;
2159 /* receive ring buffer overflow ?? */
2161 stats
->rx_crc_errors
= mac_stats
->rx_fcs_error
;
2162 stats
->rx_frame_errors
= mac_stats
->rx_alignment_error
;
2163 /* recv'r fifo overrun */
2164 bmap
= bna_rx_rid_mask(&bnad
->bna
);
2165 for (i
= 0; bmap
; i
++) {
2167 stats
->rx_fifo_errors
+=
2168 bnad
->stats
.bna_stats
->
2169 hw_stats
.rxf_stats
[i
].frame_drops
;
2177 bnad_mbox_irq_sync(struct bnad
*bnad
)
2180 unsigned long flags
;
2182 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2183 if (bnad
->cfg_flags
& BNAD_CF_MSIX
)
2184 irq
= bnad
->msix_table
[BNAD_MAILBOX_MSIX_INDEX
].vector
;
2186 irq
= bnad
->pcidev
->irq
;
2187 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2189 synchronize_irq(irq
);
2192 /* Utility used by bnad_start_xmit, for doing TSO */
2194 bnad_tso_prepare(struct bnad
*bnad
, struct sk_buff
*skb
)
2198 if (skb_header_cloned(skb
)) {
2199 err
= pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
);
2201 BNAD_UPDATE_CTR(bnad
, tso_err
);
2207 * For TSO, the TCP checksum field is seeded with pseudo-header sum
2208 * excluding the length field.
2210 if (skb
->protocol
== htons(ETH_P_IP
)) {
2211 struct iphdr
*iph
= ip_hdr(skb
);
2213 /* Do we really need these? */
2217 tcp_hdr(skb
)->check
=
2218 ~csum_tcpudp_magic(iph
->saddr
, iph
->daddr
, 0,
2220 BNAD_UPDATE_CTR(bnad
, tso4
);
2222 struct ipv6hdr
*ipv6h
= ipv6_hdr(skb
);
2224 ipv6h
->payload_len
= 0;
2225 tcp_hdr(skb
)->check
=
2226 ~csum_ipv6_magic(&ipv6h
->saddr
, &ipv6h
->daddr
, 0,
2228 BNAD_UPDATE_CTR(bnad
, tso6
);
2235 * Initialize Q numbers depending on Rx Paths
2236 * Called with bnad->bna_lock held, because of cfg_flags
2240 bnad_q_num_init(struct bnad
*bnad
)
2244 rxps
= min((uint
)num_online_cpus(),
2245 (uint
)(BNAD_MAX_RX
* BNAD_MAX_RXP_PER_RX
));
2247 if (!(bnad
->cfg_flags
& BNAD_CF_MSIX
))
2248 rxps
= 1; /* INTx */
2252 bnad
->num_rxp_per_rx
= rxps
;
2253 bnad
->num_txq_per_tx
= BNAD_TXQ_NUM
;
2257 * Adjusts the Q numbers, given a number of msix vectors
2258 * Give preference to RSS as opposed to Tx priority Queues,
2259 * in such a case, just use 1 Tx Q
2260 * Called with bnad->bna_lock held b'cos of cfg_flags access
2263 bnad_q_num_adjust(struct bnad
*bnad
, int msix_vectors
, int temp
)
2265 bnad
->num_txq_per_tx
= 1;
2266 if ((msix_vectors
>= (bnad
->num_tx
* bnad
->num_txq_per_tx
) +
2267 bnad_rxqs_per_cq
+ BNAD_MAILBOX_MSIX_VECTORS
) &&
2268 (bnad
->cfg_flags
& BNAD_CF_MSIX
)) {
2269 bnad
->num_rxp_per_rx
= msix_vectors
-
2270 (bnad
->num_tx
* bnad
->num_txq_per_tx
) -
2271 BNAD_MAILBOX_MSIX_VECTORS
;
2273 bnad
->num_rxp_per_rx
= 1;
2276 /* Enable / disable ioceth */
2278 bnad_ioceth_disable(struct bnad
*bnad
)
2280 unsigned long flags
;
2283 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2284 init_completion(&bnad
->bnad_completions
.ioc_comp
);
2285 bna_ioceth_disable(&bnad
->bna
.ioceth
, BNA_HARD_CLEANUP
);
2286 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2288 wait_for_completion_timeout(&bnad
->bnad_completions
.ioc_comp
,
2289 msecs_to_jiffies(BNAD_IOCETH_TIMEOUT
));
2291 err
= bnad
->bnad_completions
.ioc_comp_status
;
2296 bnad_ioceth_enable(struct bnad
*bnad
)
2299 unsigned long flags
;
2301 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2302 init_completion(&bnad
->bnad_completions
.ioc_comp
);
2303 bnad
->bnad_completions
.ioc_comp_status
= BNA_CB_WAITING
;
2304 bna_ioceth_enable(&bnad
->bna
.ioceth
);
2305 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2307 wait_for_completion_timeout(&bnad
->bnad_completions
.ioc_comp
,
2308 msecs_to_jiffies(BNAD_IOCETH_TIMEOUT
));
2310 err
= bnad
->bnad_completions
.ioc_comp_status
;
2315 /* Free BNA resources */
2317 bnad_res_free(struct bnad
*bnad
, struct bna_res_info
*res_info
,
2322 for (i
= 0; i
< res_val_max
; i
++)
2323 bnad_mem_free(bnad
, &res_info
[i
].res_u
.mem_info
);
2326 /* Allocates memory and interrupt resources for BNA */
2328 bnad_res_alloc(struct bnad
*bnad
, struct bna_res_info
*res_info
,
2333 for (i
= 0; i
< res_val_max
; i
++) {
2334 err
= bnad_mem_alloc(bnad
, &res_info
[i
].res_u
.mem_info
);
2341 bnad_res_free(bnad
, res_info
, res_val_max
);
2345 /* Interrupt enable / disable */
2347 bnad_enable_msix(struct bnad
*bnad
)
2350 unsigned long flags
;
2352 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2353 if (!(bnad
->cfg_flags
& BNAD_CF_MSIX
)) {
2354 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2357 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2359 if (bnad
->msix_table
)
2363 kcalloc(bnad
->msix_num
, sizeof(struct msix_entry
), GFP_KERNEL
);
2365 if (!bnad
->msix_table
)
2368 for (i
= 0; i
< bnad
->msix_num
; i
++)
2369 bnad
->msix_table
[i
].entry
= i
;
2371 ret
= pci_enable_msix(bnad
->pcidev
, bnad
->msix_table
, bnad
->msix_num
);
2373 /* Not enough MSI-X vectors. */
2374 pr_warn("BNA: %d MSI-X vectors allocated < %d requested\n",
2375 ret
, bnad
->msix_num
);
2377 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2378 /* ret = #of vectors that we got */
2379 bnad_q_num_adjust(bnad
, (ret
- BNAD_MAILBOX_MSIX_VECTORS
) / 2,
2380 (ret
- BNAD_MAILBOX_MSIX_VECTORS
) / 2);
2381 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2383 bnad
->msix_num
= BNAD_NUM_TXQ
+ BNAD_NUM_RXP
+
2384 BNAD_MAILBOX_MSIX_VECTORS
;
2386 if (bnad
->msix_num
> ret
)
2389 /* Try once more with adjusted numbers */
2390 /* If this fails, fall back to INTx */
2391 ret
= pci_enable_msix(bnad
->pcidev
, bnad
->msix_table
,
2399 pci_intx(bnad
->pcidev
, 0);
2404 pr_warn("BNA: MSI-X enable failed - operating in INTx mode\n");
2406 kfree(bnad
->msix_table
);
2407 bnad
->msix_table
= NULL
;
2409 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2410 bnad
->cfg_flags
&= ~BNAD_CF_MSIX
;
2411 bnad_q_num_init(bnad
);
2412 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2416 bnad_disable_msix(struct bnad
*bnad
)
2419 unsigned long flags
;
2421 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2422 cfg_flags
= bnad
->cfg_flags
;
2423 if (bnad
->cfg_flags
& BNAD_CF_MSIX
)
2424 bnad
->cfg_flags
&= ~BNAD_CF_MSIX
;
2425 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2427 if (cfg_flags
& BNAD_CF_MSIX
) {
2428 pci_disable_msix(bnad
->pcidev
);
2429 kfree(bnad
->msix_table
);
2430 bnad
->msix_table
= NULL
;
2434 /* Netdev entry points */
2436 bnad_open(struct net_device
*netdev
)
2439 struct bnad
*bnad
= netdev_priv(netdev
);
2440 struct bna_pause_config pause_config
;
2442 unsigned long flags
;
2444 mutex_lock(&bnad
->conf_mutex
);
2447 err
= bnad_setup_tx(bnad
, 0);
2452 err
= bnad_setup_rx(bnad
, 0);
2457 pause_config
.tx_pause
= 0;
2458 pause_config
.rx_pause
= 0;
2460 mtu
= ETH_HLEN
+ VLAN_HLEN
+ bnad
->netdev
->mtu
+ ETH_FCS_LEN
;
2462 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2463 bna_enet_mtu_set(&bnad
->bna
.enet
, mtu
, NULL
);
2464 bna_enet_pause_config(&bnad
->bna
.enet
, &pause_config
, NULL
);
2465 bna_enet_enable(&bnad
->bna
.enet
);
2466 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2468 /* Enable broadcast */
2469 bnad_enable_default_bcast(bnad
);
2471 /* Restore VLANs, if any */
2472 bnad_restore_vlans(bnad
, 0);
2474 /* Set the UCAST address */
2475 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2476 bnad_mac_addr_set_locked(bnad
, netdev
->dev_addr
);
2477 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2479 /* Start the stats timer */
2480 bnad_stats_timer_start(bnad
);
2482 mutex_unlock(&bnad
->conf_mutex
);
2487 bnad_cleanup_tx(bnad
, 0);
2490 mutex_unlock(&bnad
->conf_mutex
);
2495 bnad_stop(struct net_device
*netdev
)
2497 struct bnad
*bnad
= netdev_priv(netdev
);
2498 unsigned long flags
;
2500 mutex_lock(&bnad
->conf_mutex
);
2502 /* Stop the stats timer */
2503 bnad_stats_timer_stop(bnad
);
2505 init_completion(&bnad
->bnad_completions
.enet_comp
);
2507 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2508 bna_enet_disable(&bnad
->bna
.enet
, BNA_HARD_CLEANUP
,
2509 bnad_cb_enet_disabled
);
2510 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2512 wait_for_completion(&bnad
->bnad_completions
.enet_comp
);
2514 bnad_cleanup_tx(bnad
, 0);
2515 bnad_cleanup_rx(bnad
, 0);
2517 /* Synchronize mailbox IRQ */
2518 bnad_mbox_irq_sync(bnad
);
2520 mutex_unlock(&bnad
->conf_mutex
);
2527 * bnad_start_xmit : Netdev entry point for Transmit
2528 * Called under lock held by net_device
2531 bnad_start_xmit(struct sk_buff
*skb
, struct net_device
*netdev
)
2533 struct bnad
*bnad
= netdev_priv(netdev
);
2535 struct bna_tcb
*tcb
= bnad
->tx_info
[0].tcb
[txq_id
];
2537 u16 txq_prod
, vlan_tag
= 0;
2538 u32 unmap_prod
, wis
, wis_used
, wi_range
;
2539 u32 vectors
, vect_id
, i
, acked
;
2544 struct bnad_unmap_q
*unmap_q
= tcb
->unmap_q
;
2545 dma_addr_t dma_addr
;
2546 struct bna_txq_entry
*txqent
;
2549 if (unlikely(skb
->len
<= ETH_HLEN
)) {
2551 BNAD_UPDATE_CTR(bnad
, tx_skb_too_short
);
2552 return NETDEV_TX_OK
;
2554 if (unlikely(skb_headlen(skb
) > BFI_TX_MAX_DATA_PER_VECTOR
)) {
2556 BNAD_UPDATE_CTR(bnad
, tx_skb_headlen_too_long
);
2557 return NETDEV_TX_OK
;
2559 if (unlikely(skb_headlen(skb
) == 0)) {
2561 BNAD_UPDATE_CTR(bnad
, tx_skb_headlen_zero
);
2562 return NETDEV_TX_OK
;
2566 * Takes care of the Tx that is scheduled between clearing the flag
2567 * and the netif_tx_stop_all_queues() call.
2569 if (unlikely(!test_bit(BNAD_TXQ_TX_STARTED
, &tcb
->flags
))) {
2571 BNAD_UPDATE_CTR(bnad
, tx_skb_stopping
);
2572 return NETDEV_TX_OK
;
2575 vectors
= 1 + skb_shinfo(skb
)->nr_frags
;
2576 if (unlikely(vectors
> BFI_TX_MAX_VECTORS_PER_PKT
)) {
2578 BNAD_UPDATE_CTR(bnad
, tx_skb_max_vectors
);
2579 return NETDEV_TX_OK
;
2581 wis
= BNA_TXQ_WI_NEEDED(vectors
); /* 4 vectors per work item */
2583 if (unlikely(wis
> BNA_QE_FREE_CNT(tcb
, tcb
->q_depth
) ||
2584 vectors
> BNA_QE_FREE_CNT(unmap_q
, unmap_q
->q_depth
))) {
2585 if ((u16
) (*tcb
->hw_consumer_index
) !=
2586 tcb
->consumer_index
&&
2587 !test_and_set_bit(BNAD_TXQ_FREE_SENT
, &tcb
->flags
)) {
2588 acked
= bnad_free_txbufs(bnad
, tcb
);
2589 if (likely(test_bit(BNAD_TXQ_TX_STARTED
, &tcb
->flags
)))
2590 bna_ib_ack(tcb
->i_dbell
, acked
);
2591 smp_mb__before_clear_bit();
2592 clear_bit(BNAD_TXQ_FREE_SENT
, &tcb
->flags
);
2594 netif_stop_queue(netdev
);
2595 BNAD_UPDATE_CTR(bnad
, netif_queue_stop
);
2600 * Check again to deal with race condition between
2601 * netif_stop_queue here, and netif_wake_queue in
2602 * interrupt handler which is not inside netif tx lock.
2605 (wis
> BNA_QE_FREE_CNT(tcb
, tcb
->q_depth
) ||
2606 vectors
> BNA_QE_FREE_CNT(unmap_q
, unmap_q
->q_depth
))) {
2607 BNAD_UPDATE_CTR(bnad
, netif_queue_stop
);
2608 return NETDEV_TX_BUSY
;
2610 netif_wake_queue(netdev
);
2611 BNAD_UPDATE_CTR(bnad
, netif_queue_wakeup
);
2615 unmap_prod
= unmap_q
->producer_index
;
2618 txq_prod
= tcb
->producer_index
;
2619 BNA_TXQ_QPGE_PTR_GET(txq_prod
, tcb
->sw_qpt
, txqent
, wi_range
);
2620 txqent
->hdr
.wi
.reserved
= 0;
2621 txqent
->hdr
.wi
.num_vectors
= vectors
;
2623 if (vlan_tx_tag_present(skb
)) {
2624 vlan_tag
= (u16
) vlan_tx_tag_get(skb
);
2625 flags
|= (BNA_TXQ_WI_CF_INS_PRIO
| BNA_TXQ_WI_CF_INS_VLAN
);
2627 if (test_bit(BNAD_RF_CEE_RUNNING
, &bnad
->run_flags
)) {
2629 (tcb
->priority
& 0x7) << 13 | (vlan_tag
& 0x1fff);
2630 flags
|= (BNA_TXQ_WI_CF_INS_PRIO
| BNA_TXQ_WI_CF_INS_VLAN
);
2633 txqent
->hdr
.wi
.vlan_tag
= htons(vlan_tag
);
2635 if (skb_is_gso(skb
)) {
2636 gso_size
= skb_shinfo(skb
)->gso_size
;
2638 if (unlikely(gso_size
> netdev
->mtu
)) {
2640 BNAD_UPDATE_CTR(bnad
, tx_skb_mss_too_long
);
2641 return NETDEV_TX_OK
;
2643 if (unlikely((gso_size
+ skb_transport_offset(skb
) +
2644 tcp_hdrlen(skb
)) >= skb
->len
)) {
2645 txqent
->hdr
.wi
.opcode
=
2646 __constant_htons(BNA_TXQ_WI_SEND
);
2647 txqent
->hdr
.wi
.lso_mss
= 0;
2648 BNAD_UPDATE_CTR(bnad
, tx_skb_tso_too_short
);
2650 txqent
->hdr
.wi
.opcode
=
2651 __constant_htons(BNA_TXQ_WI_SEND_LSO
);
2652 txqent
->hdr
.wi
.lso_mss
= htons(gso_size
);
2655 err
= bnad_tso_prepare(bnad
, skb
);
2656 if (unlikely(err
)) {
2658 BNAD_UPDATE_CTR(bnad
, tx_skb_tso_prepare
);
2659 return NETDEV_TX_OK
;
2661 flags
|= (BNA_TXQ_WI_CF_IP_CKSUM
| BNA_TXQ_WI_CF_TCP_CKSUM
);
2662 txqent
->hdr
.wi
.l4_hdr_size_n_offset
=
2663 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
2664 (tcp_hdrlen(skb
) >> 2,
2665 skb_transport_offset(skb
)));
2667 txqent
->hdr
.wi
.opcode
= __constant_htons(BNA_TXQ_WI_SEND
);
2668 txqent
->hdr
.wi
.lso_mss
= 0;
2670 if (unlikely(skb
->len
> (netdev
->mtu
+ ETH_HLEN
))) {
2672 BNAD_UPDATE_CTR(bnad
, tx_skb_non_tso_too_long
);
2673 return NETDEV_TX_OK
;
2676 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
2679 if (skb
->protocol
== __constant_htons(ETH_P_IP
))
2680 proto
= ip_hdr(skb
)->protocol
;
2681 else if (skb
->protocol
==
2682 __constant_htons(ETH_P_IPV6
)) {
2683 /* nexthdr may not be TCP immediately. */
2684 proto
= ipv6_hdr(skb
)->nexthdr
;
2686 if (proto
== IPPROTO_TCP
) {
2687 flags
|= BNA_TXQ_WI_CF_TCP_CKSUM
;
2688 txqent
->hdr
.wi
.l4_hdr_size_n_offset
=
2689 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
2690 (0, skb_transport_offset(skb
)));
2692 BNAD_UPDATE_CTR(bnad
, tcpcsum_offload
);
2694 if (unlikely(skb_headlen(skb
) <
2695 skb_transport_offset(skb
) + tcp_hdrlen(skb
))) {
2697 BNAD_UPDATE_CTR(bnad
, tx_skb_tcp_hdr
);
2698 return NETDEV_TX_OK
;
2701 } else if (proto
== IPPROTO_UDP
) {
2702 flags
|= BNA_TXQ_WI_CF_UDP_CKSUM
;
2703 txqent
->hdr
.wi
.l4_hdr_size_n_offset
=
2704 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
2705 (0, skb_transport_offset(skb
)));
2707 BNAD_UPDATE_CTR(bnad
, udpcsum_offload
);
2708 if (unlikely(skb_headlen(skb
) <
2709 skb_transport_offset(skb
) +
2710 sizeof(struct udphdr
))) {
2712 BNAD_UPDATE_CTR(bnad
, tx_skb_udp_hdr
);
2713 return NETDEV_TX_OK
;
2717 BNAD_UPDATE_CTR(bnad
, tx_skb_csum_err
);
2718 return NETDEV_TX_OK
;
2721 txqent
->hdr
.wi
.l4_hdr_size_n_offset
= 0;
2725 txqent
->hdr
.wi
.flags
= htons(flags
);
2727 txqent
->hdr
.wi
.frame_length
= htonl(skb
->len
);
2729 unmap_q
->unmap_array
[unmap_prod
].skb
= skb
;
2730 len
= skb_headlen(skb
);
2731 txqent
->vector
[0].length
= htons(len
);
2732 dma_addr
= dma_map_single(&bnad
->pcidev
->dev
, skb
->data
,
2733 skb_headlen(skb
), DMA_TO_DEVICE
);
2734 dma_unmap_addr_set(&unmap_q
->unmap_array
[unmap_prod
], dma_addr
,
2737 BNA_SET_DMA_ADDR(dma_addr
, &txqent
->vector
[0].host_addr
);
2738 BNA_QE_INDX_ADD(unmap_prod
, 1, unmap_q
->q_depth
);
2743 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
2744 struct skb_frag_struct
*frag
= &skb_shinfo(skb
)->frags
[i
];
2745 u16 size
= frag
->size
;
2747 if (unlikely(size
== 0)) {
2748 unmap_prod
= unmap_q
->producer_index
;
2750 unmap_prod
= bnad_pci_unmap_skb(&bnad
->pcidev
->dev
,
2751 unmap_q
->unmap_array
,
2752 unmap_prod
, unmap_q
->q_depth
, skb
,
2755 BNAD_UPDATE_CTR(bnad
, tx_skb_frag_zero
);
2756 return NETDEV_TX_OK
;
2761 if (++vect_id
== BFI_TX_MAX_VECTORS_PER_WI
) {
2766 BNA_QE_INDX_ADD(txq_prod
, wis_used
,
2769 BNA_TXQ_QPGE_PTR_GET(txq_prod
, tcb
->sw_qpt
,
2773 txqent
->hdr
.wi_ext
.opcode
=
2774 __constant_htons(BNA_TXQ_WI_EXTENSION
);
2777 BUG_ON(!(size
<= BFI_TX_MAX_DATA_PER_VECTOR
));
2778 txqent
->vector
[vect_id
].length
= htons(size
);
2779 dma_addr
= skb_frag_dma_map(&bnad
->pcidev
->dev
, frag
,
2780 0, size
, DMA_TO_DEVICE
);
2781 dma_unmap_addr_set(&unmap_q
->unmap_array
[unmap_prod
], dma_addr
,
2783 BNA_SET_DMA_ADDR(dma_addr
, &txqent
->vector
[vect_id
].host_addr
);
2784 BNA_QE_INDX_ADD(unmap_prod
, 1, unmap_q
->q_depth
);
2787 if (unlikely(len
!= skb
->len
)) {
2788 unmap_prod
= unmap_q
->producer_index
;
2790 unmap_prod
= bnad_pci_unmap_skb(&bnad
->pcidev
->dev
,
2791 unmap_q
->unmap_array
, unmap_prod
,
2792 unmap_q
->q_depth
, skb
,
2793 skb_shinfo(skb
)->nr_frags
);
2795 BNAD_UPDATE_CTR(bnad
, tx_skb_len_mismatch
);
2796 return NETDEV_TX_OK
;
2799 unmap_q
->producer_index
= unmap_prod
;
2800 BNA_QE_INDX_ADD(txq_prod
, wis_used
, tcb
->q_depth
);
2801 tcb
->producer_index
= txq_prod
;
2805 if (unlikely(!test_bit(BNAD_TXQ_TX_STARTED
, &tcb
->flags
)))
2806 return NETDEV_TX_OK
;
2808 bna_txq_prod_indx_doorbell(tcb
);
2811 if ((u16
) (*tcb
->hw_consumer_index
) != tcb
->consumer_index
)
2812 tasklet_schedule(&bnad
->tx_free_tasklet
);
2814 return NETDEV_TX_OK
;
2818 * Used spin_lock to synchronize reading of stats structures, which
2819 * is written by BNA under the same lock.
2821 static struct rtnl_link_stats64
*
2822 bnad_get_stats64(struct net_device
*netdev
, struct rtnl_link_stats64
*stats
)
2824 struct bnad
*bnad
= netdev_priv(netdev
);
2825 unsigned long flags
;
2827 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2829 bnad_netdev_qstats_fill(bnad
, stats
);
2830 bnad_netdev_hwstats_fill(bnad
, stats
);
2832 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2838 bnad_set_rx_mode(struct net_device
*netdev
)
2840 struct bnad
*bnad
= netdev_priv(netdev
);
2841 u32 new_mask
, valid_mask
;
2842 unsigned long flags
;
2844 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2846 new_mask
= valid_mask
= 0;
2848 if (netdev
->flags
& IFF_PROMISC
) {
2849 if (!(bnad
->cfg_flags
& BNAD_CF_PROMISC
)) {
2850 new_mask
= BNAD_RXMODE_PROMISC_DEFAULT
;
2851 valid_mask
= BNAD_RXMODE_PROMISC_DEFAULT
;
2852 bnad
->cfg_flags
|= BNAD_CF_PROMISC
;
2855 if (bnad
->cfg_flags
& BNAD_CF_PROMISC
) {
2856 new_mask
= ~BNAD_RXMODE_PROMISC_DEFAULT
;
2857 valid_mask
= BNAD_RXMODE_PROMISC_DEFAULT
;
2858 bnad
->cfg_flags
&= ~BNAD_CF_PROMISC
;
2862 if (netdev
->flags
& IFF_ALLMULTI
) {
2863 if (!(bnad
->cfg_flags
& BNAD_CF_ALLMULTI
)) {
2864 new_mask
|= BNA_RXMODE_ALLMULTI
;
2865 valid_mask
|= BNA_RXMODE_ALLMULTI
;
2866 bnad
->cfg_flags
|= BNAD_CF_ALLMULTI
;
2869 if (bnad
->cfg_flags
& BNAD_CF_ALLMULTI
) {
2870 new_mask
&= ~BNA_RXMODE_ALLMULTI
;
2871 valid_mask
|= BNA_RXMODE_ALLMULTI
;
2872 bnad
->cfg_flags
&= ~BNAD_CF_ALLMULTI
;
2876 if (bnad
->rx_info
[0].rx
== NULL
)
2879 bna_rx_mode_set(bnad
->rx_info
[0].rx
, new_mask
, valid_mask
, NULL
);
2881 if (!netdev_mc_empty(netdev
)) {
2883 int mc_count
= netdev_mc_count(netdev
);
2885 /* Index 0 holds the broadcast address */
2887 kzalloc((mc_count
+ 1) * ETH_ALEN
,
2892 memcpy(&mcaddr_list
[0], &bnad_bcast_addr
[0], ETH_ALEN
);
2894 /* Copy rest of the MC addresses */
2895 bnad_netdev_mc_list_get(netdev
, mcaddr_list
);
2897 bna_rx_mcast_listset(bnad
->rx_info
[0].rx
, mc_count
+ 1,
2900 /* Should we enable BNAD_CF_ALLMULTI for err != 0 ? */
2904 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2908 * bna_lock is used to sync writes to netdev->addr
2909 * conf_lock cannot be used since this call may be made
2910 * in a non-blocking context.
2913 bnad_set_mac_address(struct net_device
*netdev
, void *mac_addr
)
2916 struct bnad
*bnad
= netdev_priv(netdev
);
2917 struct sockaddr
*sa
= (struct sockaddr
*)mac_addr
;
2918 unsigned long flags
;
2920 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2922 err
= bnad_mac_addr_set_locked(bnad
, sa
->sa_data
);
2925 memcpy(netdev
->dev_addr
, sa
->sa_data
, netdev
->addr_len
);
2927 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2933 bnad_mtu_set(struct bnad
*bnad
, int mtu
)
2935 unsigned long flags
;
2937 init_completion(&bnad
->bnad_completions
.mtu_comp
);
2939 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2940 bna_enet_mtu_set(&bnad
->bna
.enet
, mtu
, bnad_cb_enet_mtu_set
);
2941 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2943 wait_for_completion(&bnad
->bnad_completions
.mtu_comp
);
2945 return bnad
->bnad_completions
.mtu_comp_status
;
2949 bnad_change_mtu(struct net_device
*netdev
, int new_mtu
)
2951 int err
, mtu
= netdev
->mtu
;
2952 struct bnad
*bnad
= netdev_priv(netdev
);
2954 if (new_mtu
+ ETH_HLEN
< ETH_ZLEN
|| new_mtu
> BNAD_JUMBO_MTU
)
2957 mutex_lock(&bnad
->conf_mutex
);
2959 netdev
->mtu
= new_mtu
;
2961 mtu
= ETH_HLEN
+ VLAN_HLEN
+ new_mtu
+ ETH_FCS_LEN
;
2962 err
= bnad_mtu_set(bnad
, mtu
);
2966 mutex_unlock(&bnad
->conf_mutex
);
2971 bnad_vlan_rx_add_vid(struct net_device
*netdev
,
2974 struct bnad
*bnad
= netdev_priv(netdev
);
2975 unsigned long flags
;
2977 if (!bnad
->rx_info
[0].rx
)
2980 mutex_lock(&bnad
->conf_mutex
);
2982 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2983 bna_rx_vlan_add(bnad
->rx_info
[0].rx
, vid
);
2984 set_bit(vid
, bnad
->active_vlans
);
2985 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2987 mutex_unlock(&bnad
->conf_mutex
);
2991 bnad_vlan_rx_kill_vid(struct net_device
*netdev
,
2994 struct bnad
*bnad
= netdev_priv(netdev
);
2995 unsigned long flags
;
2997 if (!bnad
->rx_info
[0].rx
)
3000 mutex_lock(&bnad
->conf_mutex
);
3002 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3003 clear_bit(vid
, bnad
->active_vlans
);
3004 bna_rx_vlan_del(bnad
->rx_info
[0].rx
, vid
);
3005 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3007 mutex_unlock(&bnad
->conf_mutex
);
3010 #ifdef CONFIG_NET_POLL_CONTROLLER
3012 bnad_netpoll(struct net_device
*netdev
)
3014 struct bnad
*bnad
= netdev_priv(netdev
);
3015 struct bnad_rx_info
*rx_info
;
3016 struct bnad_rx_ctrl
*rx_ctrl
;
3020 if (!(bnad
->cfg_flags
& BNAD_CF_MSIX
)) {
3021 bna_intx_disable(&bnad
->bna
, curr_mask
);
3022 bnad_isr(bnad
->pcidev
->irq
, netdev
);
3023 bna_intx_enable(&bnad
->bna
, curr_mask
);
3026 * Tx processing may happen in sending context, so no need
3027 * to explicitly process completions here
3031 for (i
= 0; i
< bnad
->num_rx
; i
++) {
3032 rx_info
= &bnad
->rx_info
[i
];
3035 for (j
= 0; j
< bnad
->num_rxp_per_rx
; j
++) {
3036 rx_ctrl
= &rx_info
->rx_ctrl
[j
];
3038 bnad_netif_rx_schedule_poll(bnad
,
3046 static const struct net_device_ops bnad_netdev_ops
= {
3047 .ndo_open
= bnad_open
,
3048 .ndo_stop
= bnad_stop
,
3049 .ndo_start_xmit
= bnad_start_xmit
,
3050 .ndo_get_stats64
= bnad_get_stats64
,
3051 .ndo_set_rx_mode
= bnad_set_rx_mode
,
3052 .ndo_validate_addr
= eth_validate_addr
,
3053 .ndo_set_mac_address
= bnad_set_mac_address
,
3054 .ndo_change_mtu
= bnad_change_mtu
,
3055 .ndo_vlan_rx_add_vid
= bnad_vlan_rx_add_vid
,
3056 .ndo_vlan_rx_kill_vid
= bnad_vlan_rx_kill_vid
,
3057 #ifdef CONFIG_NET_POLL_CONTROLLER
3058 .ndo_poll_controller
= bnad_netpoll
3063 bnad_netdev_init(struct bnad
*bnad
, bool using_dac
)
3065 struct net_device
*netdev
= bnad
->netdev
;
3067 netdev
->hw_features
= NETIF_F_SG
| NETIF_F_RXCSUM
|
3068 NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
|
3069 NETIF_F_TSO
| NETIF_F_TSO6
| NETIF_F_HW_VLAN_TX
;
3071 netdev
->vlan_features
= NETIF_F_SG
| NETIF_F_HIGHDMA
|
3072 NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
|
3073 NETIF_F_TSO
| NETIF_F_TSO6
;
3075 netdev
->features
|= netdev
->hw_features
|
3076 NETIF_F_HW_VLAN_RX
| NETIF_F_HW_VLAN_FILTER
;
3079 netdev
->features
|= NETIF_F_HIGHDMA
;
3081 netdev
->mem_start
= bnad
->mmio_start
;
3082 netdev
->mem_end
= bnad
->mmio_start
+ bnad
->mmio_len
- 1;
3084 netdev
->netdev_ops
= &bnad_netdev_ops
;
3085 bnad_set_ethtool_ops(netdev
);
3089 * 1. Initialize the bnad structure
3090 * 2. Setup netdev pointer in pci_dev
3091 * 3. Initialze Tx free tasklet
3092 * 4. Initialize no. of TxQ & CQs & MSIX vectors
3095 bnad_init(struct bnad
*bnad
,
3096 struct pci_dev
*pdev
, struct net_device
*netdev
)
3098 unsigned long flags
;
3100 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
3101 pci_set_drvdata(pdev
, netdev
);
3103 bnad
->netdev
= netdev
;
3104 bnad
->pcidev
= pdev
;
3105 bnad
->mmio_start
= pci_resource_start(pdev
, 0);
3106 bnad
->mmio_len
= pci_resource_len(pdev
, 0);
3107 bnad
->bar0
= ioremap_nocache(bnad
->mmio_start
, bnad
->mmio_len
);
3109 dev_err(&pdev
->dev
, "ioremap for bar0 failed\n");
3110 pci_set_drvdata(pdev
, NULL
);
3113 pr_info("bar0 mapped to %p, len %llu\n", bnad
->bar0
,
3114 (unsigned long long) bnad
->mmio_len
);
3116 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3117 if (!bnad_msix_disable
)
3118 bnad
->cfg_flags
= BNAD_CF_MSIX
;
3120 bnad
->cfg_flags
|= BNAD_CF_DIM_ENABLED
;
3122 bnad_q_num_init(bnad
);
3123 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3125 bnad
->msix_num
= (bnad
->num_tx
* bnad
->num_txq_per_tx
) +
3126 (bnad
->num_rx
* bnad
->num_rxp_per_rx
) +
3127 BNAD_MAILBOX_MSIX_VECTORS
;
3129 bnad
->txq_depth
= BNAD_TXQ_DEPTH
;
3130 bnad
->rxq_depth
= BNAD_RXQ_DEPTH
;
3132 bnad
->tx_coalescing_timeo
= BFI_TX_COALESCING_TIMEO
;
3133 bnad
->rx_coalescing_timeo
= BFI_RX_COALESCING_TIMEO
;
3135 tasklet_init(&bnad
->tx_free_tasklet
, bnad_tx_free_tasklet
,
3136 (unsigned long)bnad
);
3142 * Must be called after bnad_pci_uninit()
3143 * so that iounmap() and pci_set_drvdata(NULL)
3144 * happens only after PCI uninitialization.
3147 bnad_uninit(struct bnad
*bnad
)
3150 iounmap(bnad
->bar0
);
3151 pci_set_drvdata(bnad
->pcidev
, NULL
);
3156 a) Per ioceth mutes used for serializing configuration
3157 changes from OS interface
3158 b) spin lock used to protect bna state machine
3161 bnad_lock_init(struct bnad
*bnad
)
3163 spin_lock_init(&bnad
->bna_lock
);
3164 mutex_init(&bnad
->conf_mutex
);
3168 bnad_lock_uninit(struct bnad
*bnad
)
3170 mutex_destroy(&bnad
->conf_mutex
);
3173 /* PCI Initialization */
3175 bnad_pci_init(struct bnad
*bnad
,
3176 struct pci_dev
*pdev
, bool *using_dac
)
3180 err
= pci_enable_device(pdev
);
3183 err
= pci_request_regions(pdev
, BNAD_NAME
);
3185 goto disable_device
;
3186 if (!dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(64)) &&
3187 !dma_set_coherent_mask(&pdev
->dev
, DMA_BIT_MASK(64))) {
3190 err
= dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(32));
3192 err
= dma_set_coherent_mask(&pdev
->dev
,
3195 goto release_regions
;
3199 pci_set_master(pdev
);
3203 pci_release_regions(pdev
);
3205 pci_disable_device(pdev
);
3211 bnad_pci_uninit(struct pci_dev
*pdev
)
3213 pci_release_regions(pdev
);
3214 pci_disable_device(pdev
);
3217 static int __devinit
3218 bnad_pci_probe(struct pci_dev
*pdev
,
3219 const struct pci_device_id
*pcidev_id
)
3225 struct net_device
*netdev
;
3226 struct bfa_pcidev pcidev_info
;
3227 unsigned long flags
;
3229 pr_info("bnad_pci_probe : (0x%p, 0x%p) PCI Func : (%d)\n",
3230 pdev
, pcidev_id
, PCI_FUNC(pdev
->devfn
));
3232 mutex_lock(&bnad_fwimg_mutex
);
3233 if (!cna_get_firmware_buf(pdev
)) {
3234 mutex_unlock(&bnad_fwimg_mutex
);
3235 pr_warn("Failed to load Firmware Image!\n");
3238 mutex_unlock(&bnad_fwimg_mutex
);
3241 * Allocates sizeof(struct net_device + struct bnad)
3242 * bnad = netdev->priv
3244 netdev
= alloc_etherdev(sizeof(struct bnad
));
3246 dev_err(&pdev
->dev
, "netdev allocation failed\n");
3250 bnad
= netdev_priv(netdev
);
3252 bnad_lock_init(bnad
);
3254 mutex_lock(&bnad
->conf_mutex
);
3256 * PCI initialization
3257 * Output : using_dac = 1 for 64 bit DMA
3258 * = 0 for 32 bit DMA
3260 err
= bnad_pci_init(bnad
, pdev
, &using_dac
);
3265 * Initialize bnad structure
3266 * Setup relation between pci_dev & netdev
3267 * Init Tx free tasklet
3269 err
= bnad_init(bnad
, pdev
, netdev
);
3273 /* Initialize netdev structure, set up ethtool ops */
3274 bnad_netdev_init(bnad
, using_dac
);
3276 /* Set link to down state */
3277 netif_carrier_off(netdev
);
3279 /* Get resource requirement form bna */
3280 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3281 bna_res_req(&bnad
->res_info
[0]);
3282 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3284 /* Allocate resources from bna */
3285 err
= bnad_res_alloc(bnad
, &bnad
->res_info
[0], BNA_RES_T_MAX
);
3291 /* Setup pcidev_info for bna_init() */
3292 pcidev_info
.pci_slot
= PCI_SLOT(bnad
->pcidev
->devfn
);
3293 pcidev_info
.pci_func
= PCI_FUNC(bnad
->pcidev
->devfn
);
3294 pcidev_info
.device_id
= bnad
->pcidev
->device
;
3295 pcidev_info
.pci_bar_kva
= bnad
->bar0
;
3297 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3298 bna_init(bna
, bnad
, &pcidev_info
, &bnad
->res_info
[0]);
3299 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3301 bnad
->stats
.bna_stats
= &bna
->stats
;
3303 bnad_enable_msix(bnad
);
3304 err
= bnad_mbox_irq_alloc(bnad
);
3310 setup_timer(&bnad
->bna
.ioceth
.ioc
.ioc_timer
, bnad_ioc_timeout
,
3311 ((unsigned long)bnad
));
3312 setup_timer(&bnad
->bna
.ioceth
.ioc
.hb_timer
, bnad_ioc_hb_check
,
3313 ((unsigned long)bnad
));
3314 setup_timer(&bnad
->bna
.ioceth
.ioc
.iocpf_timer
, bnad_iocpf_timeout
,
3315 ((unsigned long)bnad
));
3316 setup_timer(&bnad
->bna
.ioceth
.ioc
.sem_timer
, bnad_iocpf_sem_timeout
,
3317 ((unsigned long)bnad
));
3319 /* Now start the timer before calling IOC */
3320 mod_timer(&bnad
->bna
.ioceth
.ioc
.iocpf_timer
,
3321 jiffies
+ msecs_to_jiffies(BNA_IOC_TIMER_FREQ
));
3325 * If the call back comes with error, we bail out.
3326 * This is a catastrophic error.
3328 err
= bnad_ioceth_enable(bnad
);
3330 pr_err("BNA: Initialization failed err=%d\n",
3335 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3336 if (bna_num_txq_set(bna
, BNAD_NUM_TXQ
+ 1) ||
3337 bna_num_rxp_set(bna
, BNAD_NUM_RXP
+ 1)) {
3338 bnad_q_num_adjust(bnad
, bna_attr(bna
)->num_txq
- 1,
3339 bna_attr(bna
)->num_rxp
- 1);
3340 if (bna_num_txq_set(bna
, BNAD_NUM_TXQ
+ 1) ||
3341 bna_num_rxp_set(bna
, BNAD_NUM_RXP
+ 1))
3344 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3346 goto disable_ioceth
;
3348 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3349 bna_mod_res_req(&bnad
->bna
, &bnad
->mod_res_info
[0]);
3350 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3352 err
= bnad_res_alloc(bnad
, &bnad
->mod_res_info
[0], BNA_MOD_RES_T_MAX
);
3355 goto disable_ioceth
;
3358 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3359 bna_mod_init(&bnad
->bna
, &bnad
->mod_res_info
[0]);
3360 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3362 /* Get the burnt-in mac */
3363 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3364 bna_enet_perm_mac_get(&bna
->enet
, &bnad
->perm_addr
);
3365 bnad_set_netdev_perm_addr(bnad
);
3366 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3368 mutex_unlock(&bnad
->conf_mutex
);
3370 /* Finally, reguister with net_device layer */
3371 err
= register_netdev(netdev
);
3373 pr_err("BNA : Registering with netdev failed\n");
3376 set_bit(BNAD_RF_NETDEV_REGISTERED
, &bnad
->run_flags
);
3381 mutex_unlock(&bnad
->conf_mutex
);
3385 mutex_lock(&bnad
->conf_mutex
);
3386 bnad_res_free(bnad
, &bnad
->mod_res_info
[0], BNA_MOD_RES_T_MAX
);
3388 bnad_ioceth_disable(bnad
);
3389 del_timer_sync(&bnad
->bna
.ioceth
.ioc
.ioc_timer
);
3390 del_timer_sync(&bnad
->bna
.ioceth
.ioc
.sem_timer
);
3391 del_timer_sync(&bnad
->bna
.ioceth
.ioc
.hb_timer
);
3392 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3394 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3395 bnad_mbox_irq_free(bnad
);
3396 bnad_disable_msix(bnad
);
3398 bnad_res_free(bnad
, &bnad
->res_info
[0], BNA_RES_T_MAX
);
3402 bnad_pci_uninit(pdev
);
3404 mutex_unlock(&bnad
->conf_mutex
);
3405 bnad_lock_uninit(bnad
);
3406 free_netdev(netdev
);
3410 static void __devexit
3411 bnad_pci_remove(struct pci_dev
*pdev
)
3413 struct net_device
*netdev
= pci_get_drvdata(pdev
);
3416 unsigned long flags
;
3421 pr_info("%s bnad_pci_remove\n", netdev
->name
);
3422 bnad
= netdev_priv(netdev
);
3425 if (test_and_clear_bit(BNAD_RF_NETDEV_REGISTERED
, &bnad
->run_flags
))
3426 unregister_netdev(netdev
);
3428 mutex_lock(&bnad
->conf_mutex
);
3429 bnad_ioceth_disable(bnad
);
3430 del_timer_sync(&bnad
->bna
.ioceth
.ioc
.ioc_timer
);
3431 del_timer_sync(&bnad
->bna
.ioceth
.ioc
.sem_timer
);
3432 del_timer_sync(&bnad
->bna
.ioceth
.ioc
.hb_timer
);
3433 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3435 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3437 bnad_res_free(bnad
, &bnad
->mod_res_info
[0], BNA_MOD_RES_T_MAX
);
3438 bnad_res_free(bnad
, &bnad
->res_info
[0], BNA_RES_T_MAX
);
3439 bnad_mbox_irq_free(bnad
);
3440 bnad_disable_msix(bnad
);
3441 bnad_pci_uninit(pdev
);
3442 mutex_unlock(&bnad
->conf_mutex
);
3443 bnad_lock_uninit(bnad
);
3445 free_netdev(netdev
);
3448 static DEFINE_PCI_DEVICE_TABLE(bnad_pci_id_table
) = {
3450 PCI_DEVICE(PCI_VENDOR_ID_BROCADE
,
3451 PCI_DEVICE_ID_BROCADE_CT
),
3452 .class = PCI_CLASS_NETWORK_ETHERNET
<< 8,
3453 .class_mask
= 0xffff00
3456 PCI_DEVICE(PCI_VENDOR_ID_BROCADE
,
3457 BFA_PCI_DEVICE_ID_CT2
),
3458 .class = PCI_CLASS_NETWORK_ETHERNET
<< 8,
3459 .class_mask
= 0xffff00
3464 MODULE_DEVICE_TABLE(pci
, bnad_pci_id_table
);
3466 static struct pci_driver bnad_pci_driver
= {
3468 .id_table
= bnad_pci_id_table
,
3469 .probe
= bnad_pci_probe
,
3470 .remove
= __devexit_p(bnad_pci_remove
),
3474 bnad_module_init(void)
3478 pr_info("Brocade 10G Ethernet driver - version: %s\n",
3481 bfa_nw_ioc_auto_recover(bnad_ioc_auto_recover
);
3483 err
= pci_register_driver(&bnad_pci_driver
);
3485 pr_err("bna : PCI registration failed in module init "
3494 bnad_module_exit(void)
3496 pci_unregister_driver(&bnad_pci_driver
);
3499 release_firmware(bfi_fw
);
3502 module_init(bnad_module_init
);
3503 module_exit(bnad_module_exit
);
3505 MODULE_AUTHOR("Brocade");
3506 MODULE_LICENSE("GPL");
3507 MODULE_DESCRIPTION("Brocade 10G PCIe Ethernet driver");
3508 MODULE_VERSION(BNAD_VERSION
);
3509 MODULE_FIRMWARE(CNA_FW_FILE_CT
);
3510 MODULE_FIRMWARE(CNA_FW_FILE_CT2
);