2 * Linux network driver for QLogic BR-series Converged Network Adapter.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
14 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
15 * Copyright (c) 2014-2015 QLogic Corporation
19 #include <linux/bitops.h>
20 #include <linux/netdevice.h>
21 #include <linux/skbuff.h>
22 #include <linux/etherdevice.h>
24 #include <linux/ethtool.h>
25 #include <linux/if_vlan.h>
26 #include <linux/if_ether.h>
28 #include <linux/prefetch.h>
29 #include <linux/module.h>
35 static DEFINE_MUTEX(bnad_fwimg_mutex
);
40 static uint bnad_msix_disable
;
41 module_param(bnad_msix_disable
, uint
, 0444);
42 MODULE_PARM_DESC(bnad_msix_disable
, "Disable MSIX mode");
44 static uint bnad_ioc_auto_recover
= 1;
45 module_param(bnad_ioc_auto_recover
, uint
, 0444);
46 MODULE_PARM_DESC(bnad_ioc_auto_recover
, "Enable / Disable auto recovery");
48 static uint bna_debugfs_enable
= 1;
49 module_param(bna_debugfs_enable
, uint
, S_IRUGO
| S_IWUSR
);
50 MODULE_PARM_DESC(bna_debugfs_enable
, "Enables debugfs feature, default=1,"
51 " Range[false:0|true:1]");
56 static u32 bnad_rxqs_per_cq
= 2;
57 static atomic_t bna_id
;
58 static const u8 bnad_bcast_addr
[] __aligned(2) =
59 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
64 #define BNAD_GET_MBOX_IRQ(_bnad) \
65 (((_bnad)->cfg_flags & BNAD_CF_MSIX) ? \
66 ((_bnad)->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector) : \
67 ((_bnad)->pcidev->irq))
69 #define BNAD_FILL_UNMAPQ_MEM_REQ(_res_info, _num, _size) \
71 (_res_info)->res_type = BNA_RES_T_MEM; \
72 (_res_info)->res_u.mem_info.mem_type = BNA_MEM_T_KVA; \
73 (_res_info)->res_u.mem_info.num = (_num); \
74 (_res_info)->res_u.mem_info.len = (_size); \
78 * Reinitialize completions in CQ, once Rx is taken down
81 bnad_cq_cleanup(struct bnad
*bnad
, struct bna_ccb
*ccb
)
83 struct bna_cq_entry
*cmpl
;
86 for (i
= 0; i
< ccb
->q_depth
; i
++) {
87 cmpl
= &((struct bna_cq_entry
*)ccb
->sw_q
)[i
];
92 /* Tx Datapath functions */
95 /* Caller should ensure that the entry at unmap_q[index] is valid */
97 bnad_tx_buff_unmap(struct bnad
*bnad
,
98 struct bnad_tx_unmap
*unmap_q
,
99 u32 q_depth
, u32 index
)
101 struct bnad_tx_unmap
*unmap
;
105 unmap
= &unmap_q
[index
];
106 nvecs
= unmap
->nvecs
;
111 dma_unmap_single(&bnad
->pcidev
->dev
,
112 dma_unmap_addr(&unmap
->vectors
[0], dma_addr
),
113 skb_headlen(skb
), DMA_TO_DEVICE
);
114 dma_unmap_addr_set(&unmap
->vectors
[0], dma_addr
, 0);
120 if (vector
== BFI_TX_MAX_VECTORS_PER_WI
) {
122 BNA_QE_INDX_INC(index
, q_depth
);
123 unmap
= &unmap_q
[index
];
126 dma_unmap_page(&bnad
->pcidev
->dev
,
127 dma_unmap_addr(&unmap
->vectors
[vector
], dma_addr
),
128 dma_unmap_len(&unmap
->vectors
[vector
], dma_len
),
130 dma_unmap_addr_set(&unmap
->vectors
[vector
], dma_addr
, 0);
134 BNA_QE_INDX_INC(index
, q_depth
);
140 * Frees all pending Tx Bufs
141 * At this point no activity is expected on the Q,
142 * so DMA unmap & freeing is fine.
145 bnad_txq_cleanup(struct bnad
*bnad
, struct bna_tcb
*tcb
)
147 struct bnad_tx_unmap
*unmap_q
= tcb
->unmap_q
;
151 for (i
= 0; i
< tcb
->q_depth
; i
++) {
152 skb
= unmap_q
[i
].skb
;
155 bnad_tx_buff_unmap(bnad
, unmap_q
, tcb
->q_depth
, i
);
157 dev_kfree_skb_any(skb
);
162 * bnad_txcmpl_process : Frees the Tx bufs on Tx completion
163 * Can be called in a) Interrupt context
167 bnad_txcmpl_process(struct bnad
*bnad
, struct bna_tcb
*tcb
)
169 u32 sent_packets
= 0, sent_bytes
= 0;
170 u32 wis
, unmap_wis
, hw_cons
, cons
, q_depth
;
171 struct bnad_tx_unmap
*unmap_q
= tcb
->unmap_q
;
172 struct bnad_tx_unmap
*unmap
;
175 /* Just return if TX is stopped */
176 if (!test_bit(BNAD_TXQ_TX_STARTED
, &tcb
->flags
))
179 hw_cons
= *(tcb
->hw_consumer_index
);
181 cons
= tcb
->consumer_index
;
182 q_depth
= tcb
->q_depth
;
184 wis
= BNA_Q_INDEX_CHANGE(cons
, hw_cons
, q_depth
);
185 BUG_ON(!(wis
<= BNA_QE_IN_USE_CNT(tcb
, tcb
->q_depth
)));
188 unmap
= &unmap_q
[cons
];
193 sent_bytes
+= skb
->len
;
195 unmap_wis
= BNA_TXQ_WI_NEEDED(unmap
->nvecs
);
198 cons
= bnad_tx_buff_unmap(bnad
, unmap_q
, q_depth
, cons
);
199 dev_kfree_skb_any(skb
);
202 /* Update consumer pointers. */
203 tcb
->consumer_index
= hw_cons
;
205 tcb
->txq
->tx_packets
+= sent_packets
;
206 tcb
->txq
->tx_bytes
+= sent_bytes
;
212 bnad_tx_complete(struct bnad
*bnad
, struct bna_tcb
*tcb
)
214 struct net_device
*netdev
= bnad
->netdev
;
217 if (test_and_set_bit(BNAD_TXQ_FREE_SENT
, &tcb
->flags
))
220 sent
= bnad_txcmpl_process(bnad
, tcb
);
222 if (netif_queue_stopped(netdev
) &&
223 netif_carrier_ok(netdev
) &&
224 BNA_QE_FREE_CNT(tcb
, tcb
->q_depth
) >=
225 BNAD_NETIF_WAKE_THRESHOLD
) {
226 if (test_bit(BNAD_TXQ_TX_STARTED
, &tcb
->flags
)) {
227 netif_wake_queue(netdev
);
228 BNAD_UPDATE_CTR(bnad
, netif_queue_wakeup
);
233 if (likely(test_bit(BNAD_TXQ_TX_STARTED
, &tcb
->flags
)))
234 bna_ib_ack(tcb
->i_dbell
, sent
);
236 smp_mb__before_atomic();
237 clear_bit(BNAD_TXQ_FREE_SENT
, &tcb
->flags
);
242 /* MSIX Tx Completion Handler */
244 bnad_msix_tx(int irq
, void *data
)
246 struct bna_tcb
*tcb
= (struct bna_tcb
*)data
;
247 struct bnad
*bnad
= tcb
->bnad
;
249 bnad_tx_complete(bnad
, tcb
);
255 bnad_rxq_alloc_uninit(struct bnad
*bnad
, struct bna_rcb
*rcb
)
257 struct bnad_rx_unmap_q
*unmap_q
= rcb
->unmap_q
;
259 unmap_q
->reuse_pi
= -1;
260 unmap_q
->alloc_order
= -1;
261 unmap_q
->map_size
= 0;
262 unmap_q
->type
= BNAD_RXBUF_NONE
;
265 /* Default is page-based allocation. Multi-buffer support - TBD */
267 bnad_rxq_alloc_init(struct bnad
*bnad
, struct bna_rcb
*rcb
)
269 struct bnad_rx_unmap_q
*unmap_q
= rcb
->unmap_q
;
272 bnad_rxq_alloc_uninit(bnad
, rcb
);
274 order
= get_order(rcb
->rxq
->buffer_size
);
276 unmap_q
->type
= BNAD_RXBUF_PAGE
;
278 if (bna_is_small_rxq(rcb
->id
)) {
279 unmap_q
->alloc_order
= 0;
280 unmap_q
->map_size
= rcb
->rxq
->buffer_size
;
282 if (rcb
->rxq
->multi_buffer
) {
283 unmap_q
->alloc_order
= 0;
284 unmap_q
->map_size
= rcb
->rxq
->buffer_size
;
285 unmap_q
->type
= BNAD_RXBUF_MULTI_BUFF
;
287 unmap_q
->alloc_order
= order
;
289 (rcb
->rxq
->buffer_size
> 2048) ?
290 PAGE_SIZE
<< order
: 2048;
294 BUG_ON((PAGE_SIZE
<< order
) % unmap_q
->map_size
);
300 bnad_rxq_cleanup_page(struct bnad
*bnad
, struct bnad_rx_unmap
*unmap
)
305 dma_unmap_page(&bnad
->pcidev
->dev
,
306 dma_unmap_addr(&unmap
->vector
, dma_addr
),
307 unmap
->vector
.len
, DMA_FROM_DEVICE
);
308 put_page(unmap
->page
);
310 dma_unmap_addr_set(&unmap
->vector
, dma_addr
, 0);
311 unmap
->vector
.len
= 0;
315 bnad_rxq_cleanup_skb(struct bnad
*bnad
, struct bnad_rx_unmap
*unmap
)
320 dma_unmap_single(&bnad
->pcidev
->dev
,
321 dma_unmap_addr(&unmap
->vector
, dma_addr
),
322 unmap
->vector
.len
, DMA_FROM_DEVICE
);
323 dev_kfree_skb_any(unmap
->skb
);
325 dma_unmap_addr_set(&unmap
->vector
, dma_addr
, 0);
326 unmap
->vector
.len
= 0;
330 bnad_rxq_cleanup(struct bnad
*bnad
, struct bna_rcb
*rcb
)
332 struct bnad_rx_unmap_q
*unmap_q
= rcb
->unmap_q
;
335 for (i
= 0; i
< rcb
->q_depth
; i
++) {
336 struct bnad_rx_unmap
*unmap
= &unmap_q
->unmap
[i
];
338 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q
->type
))
339 bnad_rxq_cleanup_skb(bnad
, unmap
);
341 bnad_rxq_cleanup_page(bnad
, unmap
);
343 bnad_rxq_alloc_uninit(bnad
, rcb
);
347 bnad_rxq_refill_page(struct bnad
*bnad
, struct bna_rcb
*rcb
, u32 nalloc
)
349 u32 alloced
, prod
, q_depth
;
350 struct bnad_rx_unmap_q
*unmap_q
= rcb
->unmap_q
;
351 struct bnad_rx_unmap
*unmap
, *prev
;
352 struct bna_rxq_entry
*rxent
;
354 u32 page_offset
, alloc_size
;
357 prod
= rcb
->producer_index
;
358 q_depth
= rcb
->q_depth
;
360 alloc_size
= PAGE_SIZE
<< unmap_q
->alloc_order
;
364 unmap
= &unmap_q
->unmap
[prod
];
366 if (unmap_q
->reuse_pi
< 0) {
367 page
= alloc_pages(GFP_ATOMIC
| __GFP_COMP
,
368 unmap_q
->alloc_order
);
371 prev
= &unmap_q
->unmap
[unmap_q
->reuse_pi
];
373 page_offset
= prev
->page_offset
+ unmap_q
->map_size
;
377 if (unlikely(!page
)) {
378 BNAD_UPDATE_CTR(bnad
, rxbuf_alloc_failed
);
379 rcb
->rxq
->rxbuf_alloc_failed
++;
383 dma_addr
= dma_map_page(&bnad
->pcidev
->dev
, page
, page_offset
,
384 unmap_q
->map_size
, DMA_FROM_DEVICE
);
385 if (dma_mapping_error(&bnad
->pcidev
->dev
, dma_addr
)) {
387 BNAD_UPDATE_CTR(bnad
, rxbuf_map_failed
);
388 rcb
->rxq
->rxbuf_map_failed
++;
393 unmap
->page_offset
= page_offset
;
394 dma_unmap_addr_set(&unmap
->vector
, dma_addr
, dma_addr
);
395 unmap
->vector
.len
= unmap_q
->map_size
;
396 page_offset
+= unmap_q
->map_size
;
398 if (page_offset
< alloc_size
)
399 unmap_q
->reuse_pi
= prod
;
401 unmap_q
->reuse_pi
= -1;
403 rxent
= &((struct bna_rxq_entry
*)rcb
->sw_q
)[prod
];
404 BNA_SET_DMA_ADDR(dma_addr
, &rxent
->host_addr
);
405 BNA_QE_INDX_INC(prod
, q_depth
);
410 if (likely(alloced
)) {
411 rcb
->producer_index
= prod
;
413 if (likely(test_bit(BNAD_RXQ_POST_OK
, &rcb
->flags
)))
414 bna_rxq_prod_indx_doorbell(rcb
);
421 bnad_rxq_refill_skb(struct bnad
*bnad
, struct bna_rcb
*rcb
, u32 nalloc
)
423 u32 alloced
, prod
, q_depth
, buff_sz
;
424 struct bnad_rx_unmap_q
*unmap_q
= rcb
->unmap_q
;
425 struct bnad_rx_unmap
*unmap
;
426 struct bna_rxq_entry
*rxent
;
430 buff_sz
= rcb
->rxq
->buffer_size
;
431 prod
= rcb
->producer_index
;
432 q_depth
= rcb
->q_depth
;
436 unmap
= &unmap_q
->unmap
[prod
];
438 skb
= netdev_alloc_skb_ip_align(bnad
->netdev
, buff_sz
);
440 if (unlikely(!skb
)) {
441 BNAD_UPDATE_CTR(bnad
, rxbuf_alloc_failed
);
442 rcb
->rxq
->rxbuf_alloc_failed
++;
446 dma_addr
= dma_map_single(&bnad
->pcidev
->dev
, skb
->data
,
447 buff_sz
, DMA_FROM_DEVICE
);
448 if (dma_mapping_error(&bnad
->pcidev
->dev
, dma_addr
)) {
449 dev_kfree_skb_any(skb
);
450 BNAD_UPDATE_CTR(bnad
, rxbuf_map_failed
);
451 rcb
->rxq
->rxbuf_map_failed
++;
456 dma_unmap_addr_set(&unmap
->vector
, dma_addr
, dma_addr
);
457 unmap
->vector
.len
= buff_sz
;
459 rxent
= &((struct bna_rxq_entry
*)rcb
->sw_q
)[prod
];
460 BNA_SET_DMA_ADDR(dma_addr
, &rxent
->host_addr
);
461 BNA_QE_INDX_INC(prod
, q_depth
);
466 if (likely(alloced
)) {
467 rcb
->producer_index
= prod
;
469 if (likely(test_bit(BNAD_RXQ_POST_OK
, &rcb
->flags
)))
470 bna_rxq_prod_indx_doorbell(rcb
);
477 bnad_rxq_post(struct bnad
*bnad
, struct bna_rcb
*rcb
)
479 struct bnad_rx_unmap_q
*unmap_q
= rcb
->unmap_q
;
482 to_alloc
= BNA_QE_FREE_CNT(rcb
, rcb
->q_depth
);
483 if (!(to_alloc
>> BNAD_RXQ_REFILL_THRESHOLD_SHIFT
))
486 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q
->type
))
487 bnad_rxq_refill_skb(bnad
, rcb
, to_alloc
);
489 bnad_rxq_refill_page(bnad
, rcb
, to_alloc
);
492 #define flags_cksum_prot_mask (BNA_CQ_EF_IPV4 | BNA_CQ_EF_L3_CKSUM_OK | \
494 BNA_CQ_EF_TCP | BNA_CQ_EF_UDP | \
495 BNA_CQ_EF_L4_CKSUM_OK)
497 #define flags_tcp4 (BNA_CQ_EF_IPV4 | BNA_CQ_EF_L3_CKSUM_OK | \
498 BNA_CQ_EF_TCP | BNA_CQ_EF_L4_CKSUM_OK)
499 #define flags_tcp6 (BNA_CQ_EF_IPV6 | \
500 BNA_CQ_EF_TCP | BNA_CQ_EF_L4_CKSUM_OK)
501 #define flags_udp4 (BNA_CQ_EF_IPV4 | BNA_CQ_EF_L3_CKSUM_OK | \
502 BNA_CQ_EF_UDP | BNA_CQ_EF_L4_CKSUM_OK)
503 #define flags_udp6 (BNA_CQ_EF_IPV6 | \
504 BNA_CQ_EF_UDP | BNA_CQ_EF_L4_CKSUM_OK)
507 bnad_cq_drop_packet(struct bnad
*bnad
, struct bna_rcb
*rcb
,
508 u32 sop_ci
, u32 nvecs
)
510 struct bnad_rx_unmap_q
*unmap_q
;
511 struct bnad_rx_unmap
*unmap
;
514 unmap_q
= rcb
->unmap_q
;
515 for (vec
= 0, ci
= sop_ci
; vec
< nvecs
; vec
++) {
516 unmap
= &unmap_q
->unmap
[ci
];
517 BNA_QE_INDX_INC(ci
, rcb
->q_depth
);
519 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q
->type
))
520 bnad_rxq_cleanup_skb(bnad
, unmap
);
522 bnad_rxq_cleanup_page(bnad
, unmap
);
527 bnad_cq_setup_skb_frags(struct bna_ccb
*ccb
, struct sk_buff
*skb
, u32 nvecs
)
531 struct bnad_rx_unmap_q
*unmap_q
;
532 struct bna_cq_entry
*cq
, *cmpl
;
533 u32 ci
, pi
, totlen
= 0;
536 pi
= ccb
->producer_index
;
539 rcb
= bna_is_small_rxq(cmpl
->rxq_id
) ? ccb
->rcb
[1] : ccb
->rcb
[0];
540 unmap_q
= rcb
->unmap_q
;
542 ci
= rcb
->consumer_index
;
544 /* prefetch header */
545 prefetch(page_address(unmap_q
->unmap
[ci
].page
) +
546 unmap_q
->unmap
[ci
].page_offset
);
549 struct bnad_rx_unmap
*unmap
;
552 unmap
= &unmap_q
->unmap
[ci
];
553 BNA_QE_INDX_INC(ci
, rcb
->q_depth
);
555 dma_unmap_page(&bnad
->pcidev
->dev
,
556 dma_unmap_addr(&unmap
->vector
, dma_addr
),
557 unmap
->vector
.len
, DMA_FROM_DEVICE
);
559 len
= ntohs(cmpl
->length
);
560 skb
->truesize
+= unmap
->vector
.len
;
563 skb_fill_page_desc(skb
, skb_shinfo(skb
)->nr_frags
,
564 unmap
->page
, unmap
->page_offset
, len
);
567 unmap
->vector
.len
= 0;
569 BNA_QE_INDX_INC(pi
, ccb
->q_depth
);
574 skb
->data_len
+= totlen
;
578 bnad_cq_setup_skb(struct bnad
*bnad
, struct sk_buff
*skb
,
579 struct bnad_rx_unmap
*unmap
, u32 len
)
583 dma_unmap_single(&bnad
->pcidev
->dev
,
584 dma_unmap_addr(&unmap
->vector
, dma_addr
),
585 unmap
->vector
.len
, DMA_FROM_DEVICE
);
588 skb
->protocol
= eth_type_trans(skb
, bnad
->netdev
);
591 unmap
->vector
.len
= 0;
595 bnad_cq_process(struct bnad
*bnad
, struct bna_ccb
*ccb
, int budget
)
597 struct bna_cq_entry
*cq
, *cmpl
, *next_cmpl
;
598 struct bna_rcb
*rcb
= NULL
;
599 struct bnad_rx_unmap_q
*unmap_q
;
600 struct bnad_rx_unmap
*unmap
= NULL
;
601 struct sk_buff
*skb
= NULL
;
602 struct bna_pkt_rate
*pkt_rt
= &ccb
->pkt_rate
;
603 struct bnad_rx_ctrl
*rx_ctrl
= ccb
->ctrl
;
604 u32 packets
= 0, len
= 0, totlen
= 0;
605 u32 pi
, vec
, sop_ci
= 0, nvecs
= 0;
606 u32 flags
, masked_flags
;
608 prefetch(bnad
->netdev
);
612 while (packets
< budget
) {
613 cmpl
= &cq
[ccb
->producer_index
];
616 /* The 'valid' field is set by the adapter, only after writing
617 * the other fields of completion entry. Hence, do not load
618 * other fields of completion entry *before* the 'valid' is
619 * loaded. Adding the rmb() here prevents the compiler and/or
620 * CPU from reordering the reads which would potentially result
621 * in reading stale values in completion entry.
625 BNA_UPDATE_PKT_CNT(pkt_rt
, ntohs(cmpl
->length
));
627 if (bna_is_small_rxq(cmpl
->rxq_id
))
632 unmap_q
= rcb
->unmap_q
;
634 /* start of packet ci */
635 sop_ci
= rcb
->consumer_index
;
637 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q
->type
)) {
638 unmap
= &unmap_q
->unmap
[sop_ci
];
641 skb
= napi_get_frags(&rx_ctrl
->napi
);
647 flags
= ntohl(cmpl
->flags
);
648 len
= ntohs(cmpl
->length
);
652 /* Check all the completions for this frame.
653 * busy-wait doesn't help much, break here.
655 if (BNAD_RXBUF_IS_MULTI_BUFF(unmap_q
->type
) &&
656 (flags
& BNA_CQ_EF_EOP
) == 0) {
657 pi
= ccb
->producer_index
;
659 BNA_QE_INDX_INC(pi
, ccb
->q_depth
);
662 if (!next_cmpl
->valid
)
664 /* The 'valid' field is set by the adapter, only
665 * after writing the other fields of completion
666 * entry. Hence, do not load other fields of
667 * completion entry *before* the 'valid' is
668 * loaded. Adding the rmb() here prevents the
669 * compiler and/or CPU from reordering the reads
670 * which would potentially result in reading
671 * stale values in completion entry.
675 len
= ntohs(next_cmpl
->length
);
676 flags
= ntohl(next_cmpl
->flags
);
680 } while ((flags
& BNA_CQ_EF_EOP
) == 0);
682 if (!next_cmpl
->valid
)
687 /* TODO: BNA_CQ_EF_LOCAL ? */
688 if (unlikely(flags
& (BNA_CQ_EF_MAC_ERROR
|
689 BNA_CQ_EF_FCS_ERROR
|
690 BNA_CQ_EF_TOO_LONG
))) {
691 bnad_cq_drop_packet(bnad
, rcb
, sop_ci
, nvecs
);
692 rcb
->rxq
->rx_packets_with_error
++;
697 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q
->type
))
698 bnad_cq_setup_skb(bnad
, skb
, unmap
, len
);
700 bnad_cq_setup_skb_frags(ccb
, skb
, nvecs
);
702 rcb
->rxq
->rx_packets
++;
703 rcb
->rxq
->rx_bytes
+= totlen
;
704 ccb
->bytes_per_intr
+= totlen
;
706 masked_flags
= flags
& flags_cksum_prot_mask
;
709 ((bnad
->netdev
->features
& NETIF_F_RXCSUM
) &&
710 ((masked_flags
== flags_tcp4
) ||
711 (masked_flags
== flags_udp4
) ||
712 (masked_flags
== flags_tcp6
) ||
713 (masked_flags
== flags_udp6
))))
714 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
716 skb_checksum_none_assert(skb
);
718 if ((flags
& BNA_CQ_EF_VLAN
) &&
719 (bnad
->netdev
->features
& NETIF_F_HW_VLAN_CTAG_RX
))
720 __vlan_hwaccel_put_tag(skb
, htons(ETH_P_8021Q
), ntohs(cmpl
->vlan_tag
));
722 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q
->type
))
723 netif_receive_skb(skb
);
725 napi_gro_frags(&rx_ctrl
->napi
);
728 BNA_QE_INDX_ADD(rcb
->consumer_index
, nvecs
, rcb
->q_depth
);
729 for (vec
= 0; vec
< nvecs
; vec
++) {
730 cmpl
= &cq
[ccb
->producer_index
];
732 BNA_QE_INDX_INC(ccb
->producer_index
, ccb
->q_depth
);
736 napi_gro_flush(&rx_ctrl
->napi
, false);
737 if (likely(test_bit(BNAD_RXQ_STARTED
, &ccb
->rcb
[0]->flags
)))
738 bna_ib_ack_disable_irq(ccb
->i_dbell
, packets
);
740 bnad_rxq_post(bnad
, ccb
->rcb
[0]);
742 bnad_rxq_post(bnad
, ccb
->rcb
[1]);
748 bnad_netif_rx_schedule_poll(struct bnad
*bnad
, struct bna_ccb
*ccb
)
750 struct bnad_rx_ctrl
*rx_ctrl
= (struct bnad_rx_ctrl
*)(ccb
->ctrl
);
751 struct napi_struct
*napi
= &rx_ctrl
->napi
;
753 if (likely(napi_schedule_prep(napi
))) {
754 __napi_schedule(napi
);
755 rx_ctrl
->rx_schedule
++;
759 /* MSIX Rx Path Handler */
761 bnad_msix_rx(int irq
, void *data
)
763 struct bna_ccb
*ccb
= (struct bna_ccb
*)data
;
766 ((struct bnad_rx_ctrl
*)ccb
->ctrl
)->rx_intr_ctr
++;
767 bnad_netif_rx_schedule_poll(ccb
->bnad
, ccb
);
773 /* Interrupt handlers */
775 /* Mbox Interrupt Handlers */
777 bnad_msix_mbox_handler(int irq
, void *data
)
781 struct bnad
*bnad
= (struct bnad
*)data
;
783 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
784 if (unlikely(test_bit(BNAD_RF_MBOX_IRQ_DISABLED
, &bnad
->run_flags
))) {
785 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
789 bna_intr_status_get(&bnad
->bna
, intr_status
);
791 if (BNA_IS_MBOX_ERR_INTR(&bnad
->bna
, intr_status
))
792 bna_mbox_handler(&bnad
->bna
, intr_status
);
794 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
800 bnad_isr(int irq
, void *data
)
805 struct bnad
*bnad
= (struct bnad
*)data
;
806 struct bnad_rx_info
*rx_info
;
807 struct bnad_rx_ctrl
*rx_ctrl
;
808 struct bna_tcb
*tcb
= NULL
;
810 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
811 if (unlikely(test_bit(BNAD_RF_MBOX_IRQ_DISABLED
, &bnad
->run_flags
))) {
812 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
816 bna_intr_status_get(&bnad
->bna
, intr_status
);
818 if (unlikely(!intr_status
)) {
819 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
823 if (BNA_IS_MBOX_ERR_INTR(&bnad
->bna
, intr_status
))
824 bna_mbox_handler(&bnad
->bna
, intr_status
);
826 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
828 if (!BNA_IS_INTX_DATA_INTR(intr_status
))
831 /* Process data interrupts */
833 for (i
= 0; i
< bnad
->num_tx
; i
++) {
834 for (j
= 0; j
< bnad
->num_txq_per_tx
; j
++) {
835 tcb
= bnad
->tx_info
[i
].tcb
[j
];
836 if (tcb
&& test_bit(BNAD_TXQ_TX_STARTED
, &tcb
->flags
))
837 bnad_tx_complete(bnad
, bnad
->tx_info
[i
].tcb
[j
]);
841 for (i
= 0; i
< bnad
->num_rx
; i
++) {
842 rx_info
= &bnad
->rx_info
[i
];
845 for (j
= 0; j
< bnad
->num_rxp_per_rx
; j
++) {
846 rx_ctrl
= &rx_info
->rx_ctrl
[j
];
848 bnad_netif_rx_schedule_poll(bnad
,
856 * Called in interrupt / callback context
857 * with bna_lock held, so cfg_flags access is OK
860 bnad_enable_mbox_irq(struct bnad
*bnad
)
862 clear_bit(BNAD_RF_MBOX_IRQ_DISABLED
, &bnad
->run_flags
);
864 BNAD_UPDATE_CTR(bnad
, mbox_intr_enabled
);
868 * Called with bnad->bna_lock held b'cos of
869 * bnad->cfg_flags access.
872 bnad_disable_mbox_irq(struct bnad
*bnad
)
874 set_bit(BNAD_RF_MBOX_IRQ_DISABLED
, &bnad
->run_flags
);
876 BNAD_UPDATE_CTR(bnad
, mbox_intr_disabled
);
880 bnad_set_netdev_perm_addr(struct bnad
*bnad
)
882 struct net_device
*netdev
= bnad
->netdev
;
884 ether_addr_copy(netdev
->perm_addr
, bnad
->perm_addr
);
885 if (is_zero_ether_addr(netdev
->dev_addr
))
886 ether_addr_copy(netdev
->dev_addr
, bnad
->perm_addr
);
889 /* Control Path Handlers */
893 bnad_cb_mbox_intr_enable(struct bnad
*bnad
)
895 bnad_enable_mbox_irq(bnad
);
899 bnad_cb_mbox_intr_disable(struct bnad
*bnad
)
901 bnad_disable_mbox_irq(bnad
);
905 bnad_cb_ioceth_ready(struct bnad
*bnad
)
907 bnad
->bnad_completions
.ioc_comp_status
= BNA_CB_SUCCESS
;
908 complete(&bnad
->bnad_completions
.ioc_comp
);
912 bnad_cb_ioceth_failed(struct bnad
*bnad
)
914 bnad
->bnad_completions
.ioc_comp_status
= BNA_CB_FAIL
;
915 complete(&bnad
->bnad_completions
.ioc_comp
);
919 bnad_cb_ioceth_disabled(struct bnad
*bnad
)
921 bnad
->bnad_completions
.ioc_comp_status
= BNA_CB_SUCCESS
;
922 complete(&bnad
->bnad_completions
.ioc_comp
);
926 bnad_cb_enet_disabled(void *arg
)
928 struct bnad
*bnad
= (struct bnad
*)arg
;
930 netif_carrier_off(bnad
->netdev
);
931 complete(&bnad
->bnad_completions
.enet_comp
);
935 bnad_cb_ethport_link_status(struct bnad
*bnad
,
936 enum bna_link_status link_status
)
938 bool link_up
= false;
940 link_up
= (link_status
== BNA_LINK_UP
) || (link_status
== BNA_CEE_UP
);
942 if (link_status
== BNA_CEE_UP
) {
943 if (!test_bit(BNAD_RF_CEE_RUNNING
, &bnad
->run_flags
))
944 BNAD_UPDATE_CTR(bnad
, cee_toggle
);
945 set_bit(BNAD_RF_CEE_RUNNING
, &bnad
->run_flags
);
947 if (test_bit(BNAD_RF_CEE_RUNNING
, &bnad
->run_flags
))
948 BNAD_UPDATE_CTR(bnad
, cee_toggle
);
949 clear_bit(BNAD_RF_CEE_RUNNING
, &bnad
->run_flags
);
953 if (!netif_carrier_ok(bnad
->netdev
)) {
955 netdev_info(bnad
->netdev
, "link up\n");
956 netif_carrier_on(bnad
->netdev
);
957 BNAD_UPDATE_CTR(bnad
, link_toggle
);
958 for (tx_id
= 0; tx_id
< bnad
->num_tx
; tx_id
++) {
959 for (tcb_id
= 0; tcb_id
< bnad
->num_txq_per_tx
;
961 struct bna_tcb
*tcb
=
962 bnad
->tx_info
[tx_id
].tcb
[tcb_id
];
969 if (test_bit(BNAD_TXQ_TX_STARTED
,
973 * Transmit Schedule */
977 BNAD_UPDATE_CTR(bnad
,
983 BNAD_UPDATE_CTR(bnad
,
990 if (netif_carrier_ok(bnad
->netdev
)) {
991 netdev_info(bnad
->netdev
, "link down\n");
992 netif_carrier_off(bnad
->netdev
);
993 BNAD_UPDATE_CTR(bnad
, link_toggle
);
999 bnad_cb_tx_disabled(void *arg
, struct bna_tx
*tx
)
1001 struct bnad
*bnad
= (struct bnad
*)arg
;
1003 complete(&bnad
->bnad_completions
.tx_comp
);
1007 bnad_cb_tcb_setup(struct bnad
*bnad
, struct bna_tcb
*tcb
)
1009 struct bnad_tx_info
*tx_info
=
1010 (struct bnad_tx_info
*)tcb
->txq
->tx
->priv
;
1013 tx_info
->tcb
[tcb
->id
] = tcb
;
1017 bnad_cb_tcb_destroy(struct bnad
*bnad
, struct bna_tcb
*tcb
)
1019 struct bnad_tx_info
*tx_info
=
1020 (struct bnad_tx_info
*)tcb
->txq
->tx
->priv
;
1022 tx_info
->tcb
[tcb
->id
] = NULL
;
1027 bnad_cb_ccb_setup(struct bnad
*bnad
, struct bna_ccb
*ccb
)
1029 struct bnad_rx_info
*rx_info
=
1030 (struct bnad_rx_info
*)ccb
->cq
->rx
->priv
;
1032 rx_info
->rx_ctrl
[ccb
->id
].ccb
= ccb
;
1033 ccb
->ctrl
= &rx_info
->rx_ctrl
[ccb
->id
];
1037 bnad_cb_ccb_destroy(struct bnad
*bnad
, struct bna_ccb
*ccb
)
1039 struct bnad_rx_info
*rx_info
=
1040 (struct bnad_rx_info
*)ccb
->cq
->rx
->priv
;
1042 rx_info
->rx_ctrl
[ccb
->id
].ccb
= NULL
;
1046 bnad_cb_tx_stall(struct bnad
*bnad
, struct bna_tx
*tx
)
1048 struct bnad_tx_info
*tx_info
=
1049 (struct bnad_tx_info
*)tx
->priv
;
1050 struct bna_tcb
*tcb
;
1054 for (i
= 0; i
< BNAD_MAX_TXQ_PER_TX
; i
++) {
1055 tcb
= tx_info
->tcb
[i
];
1059 clear_bit(BNAD_TXQ_TX_STARTED
, &tcb
->flags
);
1060 netif_stop_subqueue(bnad
->netdev
, txq_id
);
1065 bnad_cb_tx_resume(struct bnad
*bnad
, struct bna_tx
*tx
)
1067 struct bnad_tx_info
*tx_info
= (struct bnad_tx_info
*)tx
->priv
;
1068 struct bna_tcb
*tcb
;
1072 for (i
= 0; i
< BNAD_MAX_TXQ_PER_TX
; i
++) {
1073 tcb
= tx_info
->tcb
[i
];
1078 BUG_ON(test_bit(BNAD_TXQ_TX_STARTED
, &tcb
->flags
));
1079 set_bit(BNAD_TXQ_TX_STARTED
, &tcb
->flags
);
1080 BUG_ON(*(tcb
->hw_consumer_index
) != 0);
1082 if (netif_carrier_ok(bnad
->netdev
)) {
1083 netif_wake_subqueue(bnad
->netdev
, txq_id
);
1084 BNAD_UPDATE_CTR(bnad
, netif_queue_wakeup
);
1089 * Workaround for first ioceth enable failure & we
1090 * get a 0 MAC address. We try to get the MAC address
1093 if (is_zero_ether_addr(bnad
->perm_addr
)) {
1094 bna_enet_perm_mac_get(&bnad
->bna
.enet
, bnad
->perm_addr
);
1095 bnad_set_netdev_perm_addr(bnad
);
1100 * Free all TxQs buffers and then notify TX_E_CLEANUP_DONE to Tx fsm.
1103 bnad_tx_cleanup(struct delayed_work
*work
)
1105 struct bnad_tx_info
*tx_info
=
1106 container_of(work
, struct bnad_tx_info
, tx_cleanup_work
);
1107 struct bnad
*bnad
= NULL
;
1108 struct bna_tcb
*tcb
;
1109 unsigned long flags
;
1112 for (i
= 0; i
< BNAD_MAX_TXQ_PER_TX
; i
++) {
1113 tcb
= tx_info
->tcb
[i
];
1119 if (test_and_set_bit(BNAD_TXQ_FREE_SENT
, &tcb
->flags
)) {
1124 bnad_txq_cleanup(bnad
, tcb
);
1126 smp_mb__before_atomic();
1127 clear_bit(BNAD_TXQ_FREE_SENT
, &tcb
->flags
);
1131 queue_delayed_work(bnad
->work_q
, &tx_info
->tx_cleanup_work
,
1132 msecs_to_jiffies(1));
1136 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1137 bna_tx_cleanup_complete(tx_info
->tx
);
1138 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1142 bnad_cb_tx_cleanup(struct bnad
*bnad
, struct bna_tx
*tx
)
1144 struct bnad_tx_info
*tx_info
= (struct bnad_tx_info
*)tx
->priv
;
1145 struct bna_tcb
*tcb
;
1148 for (i
= 0; i
< BNAD_MAX_TXQ_PER_TX
; i
++) {
1149 tcb
= tx_info
->tcb
[i
];
1154 queue_delayed_work(bnad
->work_q
, &tx_info
->tx_cleanup_work
, 0);
1158 bnad_cb_rx_stall(struct bnad
*bnad
, struct bna_rx
*rx
)
1160 struct bnad_rx_info
*rx_info
= (struct bnad_rx_info
*)rx
->priv
;
1161 struct bna_ccb
*ccb
;
1162 struct bnad_rx_ctrl
*rx_ctrl
;
1165 for (i
= 0; i
< BNAD_MAX_RXP_PER_RX
; i
++) {
1166 rx_ctrl
= &rx_info
->rx_ctrl
[i
];
1171 clear_bit(BNAD_RXQ_POST_OK
, &ccb
->rcb
[0]->flags
);
1174 clear_bit(BNAD_RXQ_POST_OK
, &ccb
->rcb
[1]->flags
);
1179 * Free all RxQs buffers and then notify RX_E_CLEANUP_DONE to Rx fsm.
1182 bnad_rx_cleanup(void *work
)
1184 struct bnad_rx_info
*rx_info
=
1185 container_of(work
, struct bnad_rx_info
, rx_cleanup_work
);
1186 struct bnad_rx_ctrl
*rx_ctrl
;
1187 struct bnad
*bnad
= NULL
;
1188 unsigned long flags
;
1191 for (i
= 0; i
< BNAD_MAX_RXP_PER_RX
; i
++) {
1192 rx_ctrl
= &rx_info
->rx_ctrl
[i
];
1197 bnad
= rx_ctrl
->ccb
->bnad
;
1200 * Wait till the poll handler has exited
1201 * and nothing can be scheduled anymore
1203 napi_disable(&rx_ctrl
->napi
);
1205 bnad_cq_cleanup(bnad
, rx_ctrl
->ccb
);
1206 bnad_rxq_cleanup(bnad
, rx_ctrl
->ccb
->rcb
[0]);
1207 if (rx_ctrl
->ccb
->rcb
[1])
1208 bnad_rxq_cleanup(bnad
, rx_ctrl
->ccb
->rcb
[1]);
1211 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1212 bna_rx_cleanup_complete(rx_info
->rx
);
1213 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1217 bnad_cb_rx_cleanup(struct bnad
*bnad
, struct bna_rx
*rx
)
1219 struct bnad_rx_info
*rx_info
= (struct bnad_rx_info
*)rx
->priv
;
1220 struct bna_ccb
*ccb
;
1221 struct bnad_rx_ctrl
*rx_ctrl
;
1224 for (i
= 0; i
< BNAD_MAX_RXP_PER_RX
; i
++) {
1225 rx_ctrl
= &rx_info
->rx_ctrl
[i
];
1230 clear_bit(BNAD_RXQ_STARTED
, &ccb
->rcb
[0]->flags
);
1233 clear_bit(BNAD_RXQ_STARTED
, &ccb
->rcb
[1]->flags
);
1236 queue_work(bnad
->work_q
, &rx_info
->rx_cleanup_work
);
1240 bnad_cb_rx_post(struct bnad
*bnad
, struct bna_rx
*rx
)
1242 struct bnad_rx_info
*rx_info
= (struct bnad_rx_info
*)rx
->priv
;
1243 struct bna_ccb
*ccb
;
1244 struct bna_rcb
*rcb
;
1245 struct bnad_rx_ctrl
*rx_ctrl
;
1248 for (i
= 0; i
< BNAD_MAX_RXP_PER_RX
; i
++) {
1249 rx_ctrl
= &rx_info
->rx_ctrl
[i
];
1254 napi_enable(&rx_ctrl
->napi
);
1256 for (j
= 0; j
< BNAD_MAX_RXQ_PER_RXP
; j
++) {
1261 bnad_rxq_alloc_init(bnad
, rcb
);
1262 set_bit(BNAD_RXQ_STARTED
, &rcb
->flags
);
1263 set_bit(BNAD_RXQ_POST_OK
, &rcb
->flags
);
1264 bnad_rxq_post(bnad
, rcb
);
1270 bnad_cb_rx_disabled(void *arg
, struct bna_rx
*rx
)
1272 struct bnad
*bnad
= (struct bnad
*)arg
;
1274 complete(&bnad
->bnad_completions
.rx_comp
);
1278 bnad_cb_rx_mcast_add(struct bnad
*bnad
, struct bna_rx
*rx
)
1280 bnad
->bnad_completions
.mcast_comp_status
= BNA_CB_SUCCESS
;
1281 complete(&bnad
->bnad_completions
.mcast_comp
);
1285 bnad_cb_stats_get(struct bnad
*bnad
, enum bna_cb_status status
,
1286 struct bna_stats
*stats
)
1288 if (status
== BNA_CB_SUCCESS
)
1289 BNAD_UPDATE_CTR(bnad
, hw_stats_updates
);
1291 if (!netif_running(bnad
->netdev
) ||
1292 !test_bit(BNAD_RF_STATS_TIMER_RUNNING
, &bnad
->run_flags
))
1295 mod_timer(&bnad
->stats_timer
,
1296 jiffies
+ msecs_to_jiffies(BNAD_STATS_TIMER_FREQ
));
1300 bnad_cb_enet_mtu_set(struct bnad
*bnad
)
1302 bnad
->bnad_completions
.mtu_comp_status
= BNA_CB_SUCCESS
;
1303 complete(&bnad
->bnad_completions
.mtu_comp
);
1307 bnad_cb_completion(void *arg
, enum bfa_status status
)
1309 struct bnad_iocmd_comp
*iocmd_comp
=
1310 (struct bnad_iocmd_comp
*)arg
;
1312 iocmd_comp
->comp_status
= (u32
) status
;
1313 complete(&iocmd_comp
->comp
);
1316 /* Resource allocation, free functions */
1319 bnad_mem_free(struct bnad
*bnad
,
1320 struct bna_mem_info
*mem_info
)
1325 if (mem_info
->mdl
== NULL
)
1328 for (i
= 0; i
< mem_info
->num
; i
++) {
1329 if (mem_info
->mdl
[i
].kva
!= NULL
) {
1330 if (mem_info
->mem_type
== BNA_MEM_T_DMA
) {
1331 BNA_GET_DMA_ADDR(&(mem_info
->mdl
[i
].dma
),
1333 dma_free_coherent(&bnad
->pcidev
->dev
,
1334 mem_info
->mdl
[i
].len
,
1335 mem_info
->mdl
[i
].kva
, dma_pa
);
1337 kfree(mem_info
->mdl
[i
].kva
);
1340 kfree(mem_info
->mdl
);
1341 mem_info
->mdl
= NULL
;
1345 bnad_mem_alloc(struct bnad
*bnad
,
1346 struct bna_mem_info
*mem_info
)
1351 if ((mem_info
->num
== 0) || (mem_info
->len
== 0)) {
1352 mem_info
->mdl
= NULL
;
1356 mem_info
->mdl
= kcalloc(mem_info
->num
, sizeof(struct bna_mem_descr
),
1358 if (mem_info
->mdl
== NULL
)
1361 if (mem_info
->mem_type
== BNA_MEM_T_DMA
) {
1362 for (i
= 0; i
< mem_info
->num
; i
++) {
1363 mem_info
->mdl
[i
].len
= mem_info
->len
;
1364 mem_info
->mdl
[i
].kva
=
1365 dma_alloc_coherent(&bnad
->pcidev
->dev
,
1366 mem_info
->len
, &dma_pa
,
1368 if (mem_info
->mdl
[i
].kva
== NULL
)
1371 BNA_SET_DMA_ADDR(dma_pa
,
1372 &(mem_info
->mdl
[i
].dma
));
1375 for (i
= 0; i
< mem_info
->num
; i
++) {
1376 mem_info
->mdl
[i
].len
= mem_info
->len
;
1377 mem_info
->mdl
[i
].kva
= kzalloc(mem_info
->len
,
1379 if (mem_info
->mdl
[i
].kva
== NULL
)
1387 bnad_mem_free(bnad
, mem_info
);
1391 /* Free IRQ for Mailbox */
1393 bnad_mbox_irq_free(struct bnad
*bnad
)
1396 unsigned long flags
;
1398 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1399 bnad_disable_mbox_irq(bnad
);
1400 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1402 irq
= BNAD_GET_MBOX_IRQ(bnad
);
1403 free_irq(irq
, bnad
);
1407 * Allocates IRQ for Mailbox, but keep it disabled
1408 * This will be enabled once we get the mbox enable callback
1412 bnad_mbox_irq_alloc(struct bnad
*bnad
)
1415 unsigned long irq_flags
, flags
;
1417 irq_handler_t irq_handler
;
1419 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1420 if (bnad
->cfg_flags
& BNAD_CF_MSIX
) {
1421 irq_handler
= (irq_handler_t
)bnad_msix_mbox_handler
;
1422 irq
= bnad
->msix_table
[BNAD_MAILBOX_MSIX_INDEX
].vector
;
1425 irq_handler
= (irq_handler_t
)bnad_isr
;
1426 irq
= bnad
->pcidev
->irq
;
1427 irq_flags
= IRQF_SHARED
;
1430 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1431 sprintf(bnad
->mbox_irq_name
, "%s", BNAD_NAME
);
1434 * Set the Mbox IRQ disable flag, so that the IRQ handler
1435 * called from request_irq() for SHARED IRQs do not execute
1437 set_bit(BNAD_RF_MBOX_IRQ_DISABLED
, &bnad
->run_flags
);
1439 BNAD_UPDATE_CTR(bnad
, mbox_intr_disabled
);
1441 err
= request_irq(irq
, irq_handler
, irq_flags
,
1442 bnad
->mbox_irq_name
, bnad
);
1448 bnad_txrx_irq_free(struct bnad
*bnad
, struct bna_intr_info
*intr_info
)
1450 kfree(intr_info
->idl
);
1451 intr_info
->idl
= NULL
;
1454 /* Allocates Interrupt Descriptor List for MSIX/INT-X vectors */
1456 bnad_txrx_irq_alloc(struct bnad
*bnad
, enum bnad_intr_source src
,
1457 u32 txrx_id
, struct bna_intr_info
*intr_info
)
1459 int i
, vector_start
= 0;
1461 unsigned long flags
;
1463 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1464 cfg_flags
= bnad
->cfg_flags
;
1465 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1467 if (cfg_flags
& BNAD_CF_MSIX
) {
1468 intr_info
->intr_type
= BNA_INTR_T_MSIX
;
1469 intr_info
->idl
= kcalloc(intr_info
->num
,
1470 sizeof(struct bna_intr_descr
),
1472 if (!intr_info
->idl
)
1477 vector_start
= BNAD_MAILBOX_MSIX_VECTORS
+ txrx_id
;
1481 vector_start
= BNAD_MAILBOX_MSIX_VECTORS
+
1482 (bnad
->num_tx
* bnad
->num_txq_per_tx
) +
1490 for (i
= 0; i
< intr_info
->num
; i
++)
1491 intr_info
->idl
[i
].vector
= vector_start
+ i
;
1493 intr_info
->intr_type
= BNA_INTR_T_INTX
;
1495 intr_info
->idl
= kcalloc(intr_info
->num
,
1496 sizeof(struct bna_intr_descr
),
1498 if (!intr_info
->idl
)
1503 intr_info
->idl
[0].vector
= BNAD_INTX_TX_IB_BITMASK
;
1507 intr_info
->idl
[0].vector
= BNAD_INTX_RX_IB_BITMASK
;
1514 /* NOTE: Should be called for MSIX only
1515 * Unregisters Tx MSIX vector(s) from the kernel
1518 bnad_tx_msix_unregister(struct bnad
*bnad
, struct bnad_tx_info
*tx_info
,
1524 for (i
= 0; i
< num_txqs
; i
++) {
1525 if (tx_info
->tcb
[i
] == NULL
)
1528 vector_num
= tx_info
->tcb
[i
]->intr_vector
;
1529 free_irq(bnad
->msix_table
[vector_num
].vector
, tx_info
->tcb
[i
]);
1533 /* NOTE: Should be called for MSIX only
1534 * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel
1537 bnad_tx_msix_register(struct bnad
*bnad
, struct bnad_tx_info
*tx_info
,
1538 u32 tx_id
, int num_txqs
)
1544 for (i
= 0; i
< num_txqs
; i
++) {
1545 vector_num
= tx_info
->tcb
[i
]->intr_vector
;
1546 sprintf(tx_info
->tcb
[i
]->name
, "%s TXQ %d", bnad
->netdev
->name
,
1547 tx_id
+ tx_info
->tcb
[i
]->id
);
1548 err
= request_irq(bnad
->msix_table
[vector_num
].vector
,
1549 (irq_handler_t
)bnad_msix_tx
, 0,
1550 tx_info
->tcb
[i
]->name
,
1560 bnad_tx_msix_unregister(bnad
, tx_info
, (i
- 1));
1564 /* NOTE: Should be called for MSIX only
1565 * Unregisters Rx MSIX vector(s) from the kernel
1568 bnad_rx_msix_unregister(struct bnad
*bnad
, struct bnad_rx_info
*rx_info
,
1574 for (i
= 0; i
< num_rxps
; i
++) {
1575 if (rx_info
->rx_ctrl
[i
].ccb
== NULL
)
1578 vector_num
= rx_info
->rx_ctrl
[i
].ccb
->intr_vector
;
1579 free_irq(bnad
->msix_table
[vector_num
].vector
,
1580 rx_info
->rx_ctrl
[i
].ccb
);
1584 /* NOTE: Should be called for MSIX only
1585 * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel
1588 bnad_rx_msix_register(struct bnad
*bnad
, struct bnad_rx_info
*rx_info
,
1589 u32 rx_id
, int num_rxps
)
1595 for (i
= 0; i
< num_rxps
; i
++) {
1596 vector_num
= rx_info
->rx_ctrl
[i
].ccb
->intr_vector
;
1597 sprintf(rx_info
->rx_ctrl
[i
].ccb
->name
, "%s CQ %d",
1599 rx_id
+ rx_info
->rx_ctrl
[i
].ccb
->id
);
1600 err
= request_irq(bnad
->msix_table
[vector_num
].vector
,
1601 (irq_handler_t
)bnad_msix_rx
, 0,
1602 rx_info
->rx_ctrl
[i
].ccb
->name
,
1603 rx_info
->rx_ctrl
[i
].ccb
);
1612 bnad_rx_msix_unregister(bnad
, rx_info
, (i
- 1));
1616 /* Free Tx object Resources */
1618 bnad_tx_res_free(struct bnad
*bnad
, struct bna_res_info
*res_info
)
1622 for (i
= 0; i
< BNA_TX_RES_T_MAX
; i
++) {
1623 if (res_info
[i
].res_type
== BNA_RES_T_MEM
)
1624 bnad_mem_free(bnad
, &res_info
[i
].res_u
.mem_info
);
1625 else if (res_info
[i
].res_type
== BNA_RES_T_INTR
)
1626 bnad_txrx_irq_free(bnad
, &res_info
[i
].res_u
.intr_info
);
1630 /* Allocates memory and interrupt resources for Tx object */
1632 bnad_tx_res_alloc(struct bnad
*bnad
, struct bna_res_info
*res_info
,
1637 for (i
= 0; i
< BNA_TX_RES_T_MAX
; i
++) {
1638 if (res_info
[i
].res_type
== BNA_RES_T_MEM
)
1639 err
= bnad_mem_alloc(bnad
,
1640 &res_info
[i
].res_u
.mem_info
);
1641 else if (res_info
[i
].res_type
== BNA_RES_T_INTR
)
1642 err
= bnad_txrx_irq_alloc(bnad
, BNAD_INTR_TX
, tx_id
,
1643 &res_info
[i
].res_u
.intr_info
);
1650 bnad_tx_res_free(bnad
, res_info
);
1654 /* Free Rx object Resources */
1656 bnad_rx_res_free(struct bnad
*bnad
, struct bna_res_info
*res_info
)
1660 for (i
= 0; i
< BNA_RX_RES_T_MAX
; i
++) {
1661 if (res_info
[i
].res_type
== BNA_RES_T_MEM
)
1662 bnad_mem_free(bnad
, &res_info
[i
].res_u
.mem_info
);
1663 else if (res_info
[i
].res_type
== BNA_RES_T_INTR
)
1664 bnad_txrx_irq_free(bnad
, &res_info
[i
].res_u
.intr_info
);
1668 /* Allocates memory and interrupt resources for Rx object */
1670 bnad_rx_res_alloc(struct bnad
*bnad
, struct bna_res_info
*res_info
,
1675 /* All memory needs to be allocated before setup_ccbs */
1676 for (i
= 0; i
< BNA_RX_RES_T_MAX
; i
++) {
1677 if (res_info
[i
].res_type
== BNA_RES_T_MEM
)
1678 err
= bnad_mem_alloc(bnad
,
1679 &res_info
[i
].res_u
.mem_info
);
1680 else if (res_info
[i
].res_type
== BNA_RES_T_INTR
)
1681 err
= bnad_txrx_irq_alloc(bnad
, BNAD_INTR_RX
, rx_id
,
1682 &res_info
[i
].res_u
.intr_info
);
1689 bnad_rx_res_free(bnad
, res_info
);
1693 /* Timer callbacks */
1696 bnad_ioc_timeout(unsigned long data
)
1698 struct bnad
*bnad
= (struct bnad
*)data
;
1699 unsigned long flags
;
1701 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1702 bfa_nw_ioc_timeout(&bnad
->bna
.ioceth
.ioc
);
1703 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1707 bnad_ioc_hb_check(unsigned long data
)
1709 struct bnad
*bnad
= (struct bnad
*)data
;
1710 unsigned long flags
;
1712 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1713 bfa_nw_ioc_hb_check(&bnad
->bna
.ioceth
.ioc
);
1714 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1718 bnad_iocpf_timeout(unsigned long data
)
1720 struct bnad
*bnad
= (struct bnad
*)data
;
1721 unsigned long flags
;
1723 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1724 bfa_nw_iocpf_timeout(&bnad
->bna
.ioceth
.ioc
);
1725 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1729 bnad_iocpf_sem_timeout(unsigned long data
)
1731 struct bnad
*bnad
= (struct bnad
*)data
;
1732 unsigned long flags
;
1734 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1735 bfa_nw_iocpf_sem_timeout(&bnad
->bna
.ioceth
.ioc
);
1736 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1740 * All timer routines use bnad->bna_lock to protect against
1741 * the following race, which may occur in case of no locking:
1749 /* b) Dynamic Interrupt Moderation Timer */
1751 bnad_dim_timeout(unsigned long data
)
1753 struct bnad
*bnad
= (struct bnad
*)data
;
1754 struct bnad_rx_info
*rx_info
;
1755 struct bnad_rx_ctrl
*rx_ctrl
;
1757 unsigned long flags
;
1759 if (!netif_carrier_ok(bnad
->netdev
))
1762 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1763 for (i
= 0; i
< bnad
->num_rx
; i
++) {
1764 rx_info
= &bnad
->rx_info
[i
];
1767 for (j
= 0; j
< bnad
->num_rxp_per_rx
; j
++) {
1768 rx_ctrl
= &rx_info
->rx_ctrl
[j
];
1771 bna_rx_dim_update(rx_ctrl
->ccb
);
1775 /* Check for BNAD_CF_DIM_ENABLED, does not eleminate a race */
1776 if (test_bit(BNAD_RF_DIM_TIMER_RUNNING
, &bnad
->run_flags
))
1777 mod_timer(&bnad
->dim_timer
,
1778 jiffies
+ msecs_to_jiffies(BNAD_DIM_TIMER_FREQ
));
1779 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1782 /* c) Statistics Timer */
1784 bnad_stats_timeout(unsigned long data
)
1786 struct bnad
*bnad
= (struct bnad
*)data
;
1787 unsigned long flags
;
1789 if (!netif_running(bnad
->netdev
) ||
1790 !test_bit(BNAD_RF_STATS_TIMER_RUNNING
, &bnad
->run_flags
))
1793 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1794 bna_hw_stats_get(&bnad
->bna
);
1795 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1799 * Set up timer for DIM
1800 * Called with bnad->bna_lock held
1803 bnad_dim_timer_start(struct bnad
*bnad
)
1805 if (bnad
->cfg_flags
& BNAD_CF_DIM_ENABLED
&&
1806 !test_bit(BNAD_RF_DIM_TIMER_RUNNING
, &bnad
->run_flags
)) {
1807 setup_timer(&bnad
->dim_timer
, bnad_dim_timeout
,
1808 (unsigned long)bnad
);
1809 set_bit(BNAD_RF_DIM_TIMER_RUNNING
, &bnad
->run_flags
);
1810 mod_timer(&bnad
->dim_timer
,
1811 jiffies
+ msecs_to_jiffies(BNAD_DIM_TIMER_FREQ
));
1816 * Set up timer for statistics
1817 * Called with mutex_lock(&bnad->conf_mutex) held
1820 bnad_stats_timer_start(struct bnad
*bnad
)
1822 unsigned long flags
;
1824 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1825 if (!test_and_set_bit(BNAD_RF_STATS_TIMER_RUNNING
, &bnad
->run_flags
)) {
1826 setup_timer(&bnad
->stats_timer
, bnad_stats_timeout
,
1827 (unsigned long)bnad
);
1828 mod_timer(&bnad
->stats_timer
,
1829 jiffies
+ msecs_to_jiffies(BNAD_STATS_TIMER_FREQ
));
1831 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1835 * Stops the stats timer
1836 * Called with mutex_lock(&bnad->conf_mutex) held
1839 bnad_stats_timer_stop(struct bnad
*bnad
)
1842 unsigned long flags
;
1844 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1845 if (test_and_clear_bit(BNAD_RF_STATS_TIMER_RUNNING
, &bnad
->run_flags
))
1847 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1849 del_timer_sync(&bnad
->stats_timer
);
1855 bnad_netdev_mc_list_get(struct net_device
*netdev
, u8
*mc_list
)
1857 int i
= 1; /* Index 0 has broadcast address */
1858 struct netdev_hw_addr
*mc_addr
;
1860 netdev_for_each_mc_addr(mc_addr
, netdev
) {
1861 ether_addr_copy(&mc_list
[i
* ETH_ALEN
], &mc_addr
->addr
[0]);
1867 bnad_napi_poll_rx(struct napi_struct
*napi
, int budget
)
1869 struct bnad_rx_ctrl
*rx_ctrl
=
1870 container_of(napi
, struct bnad_rx_ctrl
, napi
);
1871 struct bnad
*bnad
= rx_ctrl
->bnad
;
1874 rx_ctrl
->rx_poll_ctr
++;
1876 if (!netif_carrier_ok(bnad
->netdev
))
1879 rcvd
= bnad_cq_process(bnad
, rx_ctrl
->ccb
, budget
);
1884 napi_complete(napi
);
1886 rx_ctrl
->rx_complete
++;
1889 bnad_enable_rx_irq_unsafe(rx_ctrl
->ccb
);
1894 #define BNAD_NAPI_POLL_QUOTA 64
1896 bnad_napi_add(struct bnad
*bnad
, u32 rx_id
)
1898 struct bnad_rx_ctrl
*rx_ctrl
;
1901 /* Initialize & enable NAPI */
1902 for (i
= 0; i
< bnad
->num_rxp_per_rx
; i
++) {
1903 rx_ctrl
= &bnad
->rx_info
[rx_id
].rx_ctrl
[i
];
1904 netif_napi_add(bnad
->netdev
, &rx_ctrl
->napi
,
1905 bnad_napi_poll_rx
, BNAD_NAPI_POLL_QUOTA
);
1910 bnad_napi_delete(struct bnad
*bnad
, u32 rx_id
)
1914 /* First disable and then clean up */
1915 for (i
= 0; i
< bnad
->num_rxp_per_rx
; i
++)
1916 netif_napi_del(&bnad
->rx_info
[rx_id
].rx_ctrl
[i
].napi
);
1919 /* Should be held with conf_lock held */
1921 bnad_destroy_tx(struct bnad
*bnad
, u32 tx_id
)
1923 struct bnad_tx_info
*tx_info
= &bnad
->tx_info
[tx_id
];
1924 struct bna_res_info
*res_info
= &bnad
->tx_res_info
[tx_id
].res_info
[0];
1925 unsigned long flags
;
1930 init_completion(&bnad
->bnad_completions
.tx_comp
);
1931 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1932 bna_tx_disable(tx_info
->tx
, BNA_HARD_CLEANUP
, bnad_cb_tx_disabled
);
1933 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1934 wait_for_completion(&bnad
->bnad_completions
.tx_comp
);
1936 if (tx_info
->tcb
[0]->intr_type
== BNA_INTR_T_MSIX
)
1937 bnad_tx_msix_unregister(bnad
, tx_info
,
1938 bnad
->num_txq_per_tx
);
1940 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1941 bna_tx_destroy(tx_info
->tx
);
1942 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1947 bnad_tx_res_free(bnad
, res_info
);
1950 /* Should be held with conf_lock held */
1952 bnad_setup_tx(struct bnad
*bnad
, u32 tx_id
)
1955 struct bnad_tx_info
*tx_info
= &bnad
->tx_info
[tx_id
];
1956 struct bna_res_info
*res_info
= &bnad
->tx_res_info
[tx_id
].res_info
[0];
1957 struct bna_intr_info
*intr_info
=
1958 &res_info
[BNA_TX_RES_INTR_T_TXCMPL
].res_u
.intr_info
;
1959 struct bna_tx_config
*tx_config
= &bnad
->tx_config
[tx_id
];
1960 static const struct bna_tx_event_cbfn tx_cbfn
= {
1961 .tcb_setup_cbfn
= bnad_cb_tcb_setup
,
1962 .tcb_destroy_cbfn
= bnad_cb_tcb_destroy
,
1963 .tx_stall_cbfn
= bnad_cb_tx_stall
,
1964 .tx_resume_cbfn
= bnad_cb_tx_resume
,
1965 .tx_cleanup_cbfn
= bnad_cb_tx_cleanup
,
1969 unsigned long flags
;
1971 tx_info
->tx_id
= tx_id
;
1973 /* Initialize the Tx object configuration */
1974 tx_config
->num_txq
= bnad
->num_txq_per_tx
;
1975 tx_config
->txq_depth
= bnad
->txq_depth
;
1976 tx_config
->tx_type
= BNA_TX_T_REGULAR
;
1977 tx_config
->coalescing_timeo
= bnad
->tx_coalescing_timeo
;
1979 /* Get BNA's resource requirement for one tx object */
1980 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1981 bna_tx_res_req(bnad
->num_txq_per_tx
,
1982 bnad
->txq_depth
, res_info
);
1983 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1985 /* Fill Unmap Q memory requirements */
1986 BNAD_FILL_UNMAPQ_MEM_REQ(&res_info
[BNA_TX_RES_MEM_T_UNMAPQ
],
1987 bnad
->num_txq_per_tx
, (sizeof(struct bnad_tx_unmap
) *
1990 /* Allocate resources */
1991 err
= bnad_tx_res_alloc(bnad
, res_info
, tx_id
);
1995 /* Ask BNA to create one Tx object, supplying required resources */
1996 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1997 tx
= bna_tx_create(&bnad
->bna
, bnad
, tx_config
, &tx_cbfn
, res_info
,
1999 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2006 INIT_DELAYED_WORK(&tx_info
->tx_cleanup_work
,
2007 (work_func_t
)bnad_tx_cleanup
);
2009 /* Register ISR for the Tx object */
2010 if (intr_info
->intr_type
== BNA_INTR_T_MSIX
) {
2011 err
= bnad_tx_msix_register(bnad
, tx_info
,
2012 tx_id
, bnad
->num_txq_per_tx
);
2017 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2019 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2024 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2025 bna_tx_destroy(tx_info
->tx
);
2026 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2030 bnad_tx_res_free(bnad
, res_info
);
2034 /* Setup the rx config for bna_rx_create */
2035 /* bnad decides the configuration */
2037 bnad_init_rx_config(struct bnad
*bnad
, struct bna_rx_config
*rx_config
)
2039 memset(rx_config
, 0, sizeof(*rx_config
));
2040 rx_config
->rx_type
= BNA_RX_T_REGULAR
;
2041 rx_config
->num_paths
= bnad
->num_rxp_per_rx
;
2042 rx_config
->coalescing_timeo
= bnad
->rx_coalescing_timeo
;
2044 if (bnad
->num_rxp_per_rx
> 1) {
2045 rx_config
->rss_status
= BNA_STATUS_T_ENABLED
;
2046 rx_config
->rss_config
.hash_type
=
2047 (BFI_ENET_RSS_IPV6
|
2048 BFI_ENET_RSS_IPV6_TCP
|
2050 BFI_ENET_RSS_IPV4_TCP
);
2051 rx_config
->rss_config
.hash_mask
=
2052 bnad
->num_rxp_per_rx
- 1;
2053 netdev_rss_key_fill(rx_config
->rss_config
.toeplitz_hash_key
,
2054 sizeof(rx_config
->rss_config
.toeplitz_hash_key
));
2056 rx_config
->rss_status
= BNA_STATUS_T_DISABLED
;
2057 memset(&rx_config
->rss_config
, 0,
2058 sizeof(rx_config
->rss_config
));
2061 rx_config
->frame_size
= BNAD_FRAME_SIZE(bnad
->netdev
->mtu
);
2062 rx_config
->q0_multi_buf
= BNA_STATUS_T_DISABLED
;
2064 /* BNA_RXP_SINGLE - one data-buffer queue
2065 * BNA_RXP_SLR - one small-buffer and one large-buffer queues
2066 * BNA_RXP_HDS - one header-buffer and one data-buffer queues
2068 /* TODO: configurable param for queue type */
2069 rx_config
->rxp_type
= BNA_RXP_SLR
;
2071 if (BNAD_PCI_DEV_IS_CAT2(bnad
) &&
2072 rx_config
->frame_size
> 4096) {
2073 /* though size_routing_enable is set in SLR,
2074 * small packets may get routed to same rxq.
2075 * set buf_size to 2048 instead of PAGE_SIZE.
2077 rx_config
->q0_buf_size
= 2048;
2078 /* this should be in multiples of 2 */
2079 rx_config
->q0_num_vecs
= 4;
2080 rx_config
->q0_depth
= bnad
->rxq_depth
* rx_config
->q0_num_vecs
;
2081 rx_config
->q0_multi_buf
= BNA_STATUS_T_ENABLED
;
2083 rx_config
->q0_buf_size
= rx_config
->frame_size
;
2084 rx_config
->q0_num_vecs
= 1;
2085 rx_config
->q0_depth
= bnad
->rxq_depth
;
2088 /* initialize for q1 for BNA_RXP_SLR/BNA_RXP_HDS */
2089 if (rx_config
->rxp_type
== BNA_RXP_SLR
) {
2090 rx_config
->q1_depth
= bnad
->rxq_depth
;
2091 rx_config
->q1_buf_size
= BFI_SMALL_RXBUF_SIZE
;
2094 rx_config
->vlan_strip_status
=
2095 (bnad
->netdev
->features
& NETIF_F_HW_VLAN_CTAG_RX
) ?
2096 BNA_STATUS_T_ENABLED
: BNA_STATUS_T_DISABLED
;
2100 bnad_rx_ctrl_init(struct bnad
*bnad
, u32 rx_id
)
2102 struct bnad_rx_info
*rx_info
= &bnad
->rx_info
[rx_id
];
2105 for (i
= 0; i
< bnad
->num_rxp_per_rx
; i
++)
2106 rx_info
->rx_ctrl
[i
].bnad
= bnad
;
2109 /* Called with mutex_lock(&bnad->conf_mutex) held */
2111 bnad_reinit_rx(struct bnad
*bnad
)
2113 struct net_device
*netdev
= bnad
->netdev
;
2114 u32 err
= 0, current_err
= 0;
2115 u32 rx_id
= 0, count
= 0;
2116 unsigned long flags
;
2118 /* destroy and create new rx objects */
2119 for (rx_id
= 0; rx_id
< bnad
->num_rx
; rx_id
++) {
2120 if (!bnad
->rx_info
[rx_id
].rx
)
2122 bnad_destroy_rx(bnad
, rx_id
);
2125 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2126 bna_enet_mtu_set(&bnad
->bna
.enet
,
2127 BNAD_FRAME_SIZE(bnad
->netdev
->mtu
), NULL
);
2128 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2130 for (rx_id
= 0; rx_id
< bnad
->num_rx
; rx_id
++) {
2132 current_err
= bnad_setup_rx(bnad
, rx_id
);
2133 if (current_err
&& !err
) {
2135 netdev_err(netdev
, "RXQ:%u setup failed\n", rx_id
);
2139 /* restore rx configuration */
2140 if (bnad
->rx_info
[0].rx
&& !err
) {
2141 bnad_restore_vlans(bnad
, 0);
2142 bnad_enable_default_bcast(bnad
);
2143 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2144 bnad_mac_addr_set_locked(bnad
, netdev
->dev_addr
);
2145 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2146 bnad_set_rx_mode(netdev
);
2152 /* Called with bnad_conf_lock() held */
2154 bnad_destroy_rx(struct bnad
*bnad
, u32 rx_id
)
2156 struct bnad_rx_info
*rx_info
= &bnad
->rx_info
[rx_id
];
2157 struct bna_rx_config
*rx_config
= &bnad
->rx_config
[rx_id
];
2158 struct bna_res_info
*res_info
= &bnad
->rx_res_info
[rx_id
].res_info
[0];
2159 unsigned long flags
;
2166 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2167 if (bnad
->cfg_flags
& BNAD_CF_DIM_ENABLED
&&
2168 test_bit(BNAD_RF_DIM_TIMER_RUNNING
, &bnad
->run_flags
)) {
2169 clear_bit(BNAD_RF_DIM_TIMER_RUNNING
, &bnad
->run_flags
);
2172 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2174 del_timer_sync(&bnad
->dim_timer
);
2177 init_completion(&bnad
->bnad_completions
.rx_comp
);
2178 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2179 bna_rx_disable(rx_info
->rx
, BNA_HARD_CLEANUP
, bnad_cb_rx_disabled
);
2180 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2181 wait_for_completion(&bnad
->bnad_completions
.rx_comp
);
2183 if (rx_info
->rx_ctrl
[0].ccb
->intr_type
== BNA_INTR_T_MSIX
)
2184 bnad_rx_msix_unregister(bnad
, rx_info
, rx_config
->num_paths
);
2186 bnad_napi_delete(bnad
, rx_id
);
2188 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2189 bna_rx_destroy(rx_info
->rx
);
2193 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2195 bnad_rx_res_free(bnad
, res_info
);
2198 /* Called with mutex_lock(&bnad->conf_mutex) held */
2200 bnad_setup_rx(struct bnad
*bnad
, u32 rx_id
)
2203 struct bnad_rx_info
*rx_info
= &bnad
->rx_info
[rx_id
];
2204 struct bna_res_info
*res_info
= &bnad
->rx_res_info
[rx_id
].res_info
[0];
2205 struct bna_intr_info
*intr_info
=
2206 &res_info
[BNA_RX_RES_T_INTR
].res_u
.intr_info
;
2207 struct bna_rx_config
*rx_config
= &bnad
->rx_config
[rx_id
];
2208 static const struct bna_rx_event_cbfn rx_cbfn
= {
2209 .rcb_setup_cbfn
= NULL
,
2210 .rcb_destroy_cbfn
= NULL
,
2211 .ccb_setup_cbfn
= bnad_cb_ccb_setup
,
2212 .ccb_destroy_cbfn
= bnad_cb_ccb_destroy
,
2213 .rx_stall_cbfn
= bnad_cb_rx_stall
,
2214 .rx_cleanup_cbfn
= bnad_cb_rx_cleanup
,
2215 .rx_post_cbfn
= bnad_cb_rx_post
,
2218 unsigned long flags
;
2220 rx_info
->rx_id
= rx_id
;
2222 /* Initialize the Rx object configuration */
2223 bnad_init_rx_config(bnad
, rx_config
);
2225 /* Get BNA's resource requirement for one Rx object */
2226 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2227 bna_rx_res_req(rx_config
, res_info
);
2228 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2230 /* Fill Unmap Q memory requirements */
2231 BNAD_FILL_UNMAPQ_MEM_REQ(&res_info
[BNA_RX_RES_MEM_T_UNMAPDQ
],
2232 rx_config
->num_paths
,
2233 (rx_config
->q0_depth
*
2234 sizeof(struct bnad_rx_unmap
)) +
2235 sizeof(struct bnad_rx_unmap_q
));
2237 if (rx_config
->rxp_type
!= BNA_RXP_SINGLE
) {
2238 BNAD_FILL_UNMAPQ_MEM_REQ(&res_info
[BNA_RX_RES_MEM_T_UNMAPHQ
],
2239 rx_config
->num_paths
,
2240 (rx_config
->q1_depth
*
2241 sizeof(struct bnad_rx_unmap
) +
2242 sizeof(struct bnad_rx_unmap_q
)));
2244 /* Allocate resource */
2245 err
= bnad_rx_res_alloc(bnad
, res_info
, rx_id
);
2249 bnad_rx_ctrl_init(bnad
, rx_id
);
2251 /* Ask BNA to create one Rx object, supplying required resources */
2252 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2253 rx
= bna_rx_create(&bnad
->bna
, bnad
, rx_config
, &rx_cbfn
, res_info
,
2257 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2261 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2263 INIT_WORK(&rx_info
->rx_cleanup_work
,
2264 (work_func_t
)(bnad_rx_cleanup
));
2267 * Init NAPI, so that state is set to NAPI_STATE_SCHED,
2268 * so that IRQ handler cannot schedule NAPI at this point.
2270 bnad_napi_add(bnad
, rx_id
);
2272 /* Register ISR for the Rx object */
2273 if (intr_info
->intr_type
== BNA_INTR_T_MSIX
) {
2274 err
= bnad_rx_msix_register(bnad
, rx_info
, rx_id
,
2275 rx_config
->num_paths
);
2280 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2282 /* Set up Dynamic Interrupt Moderation Vector */
2283 if (bnad
->cfg_flags
& BNAD_CF_DIM_ENABLED
)
2284 bna_rx_dim_reconfig(&bnad
->bna
, bna_napi_dim_vector
);
2286 /* Enable VLAN filtering only on the default Rx */
2287 bna_rx_vlanfilter_enable(rx
);
2289 /* Start the DIM timer */
2290 bnad_dim_timer_start(bnad
);
2294 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2299 bnad_destroy_rx(bnad
, rx_id
);
2303 /* Called with conf_lock & bnad->bna_lock held */
2305 bnad_tx_coalescing_timeo_set(struct bnad
*bnad
)
2307 struct bnad_tx_info
*tx_info
;
2309 tx_info
= &bnad
->tx_info
[0];
2313 bna_tx_coalescing_timeo_set(tx_info
->tx
, bnad
->tx_coalescing_timeo
);
2316 /* Called with conf_lock & bnad->bna_lock held */
2318 bnad_rx_coalescing_timeo_set(struct bnad
*bnad
)
2320 struct bnad_rx_info
*rx_info
;
2323 for (i
= 0; i
< bnad
->num_rx
; i
++) {
2324 rx_info
= &bnad
->rx_info
[i
];
2327 bna_rx_coalescing_timeo_set(rx_info
->rx
,
2328 bnad
->rx_coalescing_timeo
);
2333 * Called with bnad->bna_lock held
2336 bnad_mac_addr_set_locked(struct bnad
*bnad
, const u8
*mac_addr
)
2340 if (!is_valid_ether_addr(mac_addr
))
2341 return -EADDRNOTAVAIL
;
2343 /* If datapath is down, pretend everything went through */
2344 if (!bnad
->rx_info
[0].rx
)
2347 ret
= bna_rx_ucast_set(bnad
->rx_info
[0].rx
, mac_addr
);
2348 if (ret
!= BNA_CB_SUCCESS
)
2349 return -EADDRNOTAVAIL
;
2354 /* Should be called with conf_lock held */
2356 bnad_enable_default_bcast(struct bnad
*bnad
)
2358 struct bnad_rx_info
*rx_info
= &bnad
->rx_info
[0];
2360 unsigned long flags
;
2362 init_completion(&bnad
->bnad_completions
.mcast_comp
);
2364 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2365 ret
= bna_rx_mcast_add(rx_info
->rx
, bnad_bcast_addr
,
2366 bnad_cb_rx_mcast_add
);
2367 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2369 if (ret
== BNA_CB_SUCCESS
)
2370 wait_for_completion(&bnad
->bnad_completions
.mcast_comp
);
2374 if (bnad
->bnad_completions
.mcast_comp_status
!= BNA_CB_SUCCESS
)
2380 /* Called with mutex_lock(&bnad->conf_mutex) held */
2382 bnad_restore_vlans(struct bnad
*bnad
, u32 rx_id
)
2385 unsigned long flags
;
2387 for_each_set_bit(vid
, bnad
->active_vlans
, VLAN_N_VID
) {
2388 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2389 bna_rx_vlan_add(bnad
->rx_info
[rx_id
].rx
, vid
);
2390 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2394 /* Statistics utilities */
2396 bnad_netdev_qstats_fill(struct bnad
*bnad
, struct rtnl_link_stats64
*stats
)
2400 for (i
= 0; i
< bnad
->num_rx
; i
++) {
2401 for (j
= 0; j
< bnad
->num_rxp_per_rx
; j
++) {
2402 if (bnad
->rx_info
[i
].rx_ctrl
[j
].ccb
) {
2403 stats
->rx_packets
+= bnad
->rx_info
[i
].
2404 rx_ctrl
[j
].ccb
->rcb
[0]->rxq
->rx_packets
;
2405 stats
->rx_bytes
+= bnad
->rx_info
[i
].
2406 rx_ctrl
[j
].ccb
->rcb
[0]->rxq
->rx_bytes
;
2407 if (bnad
->rx_info
[i
].rx_ctrl
[j
].ccb
->rcb
[1] &&
2408 bnad
->rx_info
[i
].rx_ctrl
[j
].ccb
->
2410 stats
->rx_packets
+=
2411 bnad
->rx_info
[i
].rx_ctrl
[j
].
2412 ccb
->rcb
[1]->rxq
->rx_packets
;
2414 bnad
->rx_info
[i
].rx_ctrl
[j
].
2415 ccb
->rcb
[1]->rxq
->rx_bytes
;
2420 for (i
= 0; i
< bnad
->num_tx
; i
++) {
2421 for (j
= 0; j
< bnad
->num_txq_per_tx
; j
++) {
2422 if (bnad
->tx_info
[i
].tcb
[j
]) {
2423 stats
->tx_packets
+=
2424 bnad
->tx_info
[i
].tcb
[j
]->txq
->tx_packets
;
2426 bnad
->tx_info
[i
].tcb
[j
]->txq
->tx_bytes
;
2433 * Must be called with the bna_lock held.
2436 bnad_netdev_hwstats_fill(struct bnad
*bnad
, struct rtnl_link_stats64
*stats
)
2438 struct bfi_enet_stats_mac
*mac_stats
;
2442 mac_stats
= &bnad
->stats
.bna_stats
->hw_stats
.mac_stats
;
2444 mac_stats
->rx_fcs_error
+ mac_stats
->rx_alignment_error
+
2445 mac_stats
->rx_frame_length_error
+ mac_stats
->rx_code_error
+
2446 mac_stats
->rx_undersize
;
2447 stats
->tx_errors
= mac_stats
->tx_fcs_error
+
2448 mac_stats
->tx_undersize
;
2449 stats
->rx_dropped
= mac_stats
->rx_drop
;
2450 stats
->tx_dropped
= mac_stats
->tx_drop
;
2451 stats
->multicast
= mac_stats
->rx_multicast
;
2452 stats
->collisions
= mac_stats
->tx_total_collision
;
2454 stats
->rx_length_errors
= mac_stats
->rx_frame_length_error
;
2456 /* receive ring buffer overflow ?? */
2458 stats
->rx_crc_errors
= mac_stats
->rx_fcs_error
;
2459 stats
->rx_frame_errors
= mac_stats
->rx_alignment_error
;
2460 /* recv'r fifo overrun */
2461 bmap
= bna_rx_rid_mask(&bnad
->bna
);
2462 for (i
= 0; bmap
; i
++) {
2464 stats
->rx_fifo_errors
+=
2465 bnad
->stats
.bna_stats
->
2466 hw_stats
.rxf_stats
[i
].frame_drops
;
2474 bnad_mbox_irq_sync(struct bnad
*bnad
)
2477 unsigned long flags
;
2479 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2480 if (bnad
->cfg_flags
& BNAD_CF_MSIX
)
2481 irq
= bnad
->msix_table
[BNAD_MAILBOX_MSIX_INDEX
].vector
;
2483 irq
= bnad
->pcidev
->irq
;
2484 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2486 synchronize_irq(irq
);
2489 /* Utility used by bnad_start_xmit, for doing TSO */
2491 bnad_tso_prepare(struct bnad
*bnad
, struct sk_buff
*skb
)
2495 err
= skb_cow_head(skb
, 0);
2497 BNAD_UPDATE_CTR(bnad
, tso_err
);
2502 * For TSO, the TCP checksum field is seeded with pseudo-header sum
2503 * excluding the length field.
2505 if (vlan_get_protocol(skb
) == htons(ETH_P_IP
)) {
2506 struct iphdr
*iph
= ip_hdr(skb
);
2508 /* Do we really need these? */
2512 tcp_hdr(skb
)->check
=
2513 ~csum_tcpudp_magic(iph
->saddr
, iph
->daddr
, 0,
2515 BNAD_UPDATE_CTR(bnad
, tso4
);
2517 struct ipv6hdr
*ipv6h
= ipv6_hdr(skb
);
2519 ipv6h
->payload_len
= 0;
2520 tcp_hdr(skb
)->check
=
2521 ~csum_ipv6_magic(&ipv6h
->saddr
, &ipv6h
->daddr
, 0,
2523 BNAD_UPDATE_CTR(bnad
, tso6
);
2530 * Initialize Q numbers depending on Rx Paths
2531 * Called with bnad->bna_lock held, because of cfg_flags
2535 bnad_q_num_init(struct bnad
*bnad
)
2539 rxps
= min((uint
)num_online_cpus(),
2540 (uint
)(BNAD_MAX_RX
* BNAD_MAX_RXP_PER_RX
));
2542 if (!(bnad
->cfg_flags
& BNAD_CF_MSIX
))
2543 rxps
= 1; /* INTx */
2547 bnad
->num_rxp_per_rx
= rxps
;
2548 bnad
->num_txq_per_tx
= BNAD_TXQ_NUM
;
2552 * Adjusts the Q numbers, given a number of msix vectors
2553 * Give preference to RSS as opposed to Tx priority Queues,
2554 * in such a case, just use 1 Tx Q
2555 * Called with bnad->bna_lock held b'cos of cfg_flags access
2558 bnad_q_num_adjust(struct bnad
*bnad
, int msix_vectors
, int temp
)
2560 bnad
->num_txq_per_tx
= 1;
2561 if ((msix_vectors
>= (bnad
->num_tx
* bnad
->num_txq_per_tx
) +
2562 bnad_rxqs_per_cq
+ BNAD_MAILBOX_MSIX_VECTORS
) &&
2563 (bnad
->cfg_flags
& BNAD_CF_MSIX
)) {
2564 bnad
->num_rxp_per_rx
= msix_vectors
-
2565 (bnad
->num_tx
* bnad
->num_txq_per_tx
) -
2566 BNAD_MAILBOX_MSIX_VECTORS
;
2568 bnad
->num_rxp_per_rx
= 1;
2571 /* Enable / disable ioceth */
2573 bnad_ioceth_disable(struct bnad
*bnad
)
2575 unsigned long flags
;
2578 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2579 init_completion(&bnad
->bnad_completions
.ioc_comp
);
2580 bna_ioceth_disable(&bnad
->bna
.ioceth
, BNA_HARD_CLEANUP
);
2581 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2583 wait_for_completion_timeout(&bnad
->bnad_completions
.ioc_comp
,
2584 msecs_to_jiffies(BNAD_IOCETH_TIMEOUT
));
2586 err
= bnad
->bnad_completions
.ioc_comp_status
;
2591 bnad_ioceth_enable(struct bnad
*bnad
)
2594 unsigned long flags
;
2596 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2597 init_completion(&bnad
->bnad_completions
.ioc_comp
);
2598 bnad
->bnad_completions
.ioc_comp_status
= BNA_CB_WAITING
;
2599 bna_ioceth_enable(&bnad
->bna
.ioceth
);
2600 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2602 wait_for_completion_timeout(&bnad
->bnad_completions
.ioc_comp
,
2603 msecs_to_jiffies(BNAD_IOCETH_TIMEOUT
));
2605 err
= bnad
->bnad_completions
.ioc_comp_status
;
2610 /* Free BNA resources */
2612 bnad_res_free(struct bnad
*bnad
, struct bna_res_info
*res_info
,
2617 for (i
= 0; i
< res_val_max
; i
++)
2618 bnad_mem_free(bnad
, &res_info
[i
].res_u
.mem_info
);
2621 /* Allocates memory and interrupt resources for BNA */
2623 bnad_res_alloc(struct bnad
*bnad
, struct bna_res_info
*res_info
,
2628 for (i
= 0; i
< res_val_max
; i
++) {
2629 err
= bnad_mem_alloc(bnad
, &res_info
[i
].res_u
.mem_info
);
2636 bnad_res_free(bnad
, res_info
, res_val_max
);
2640 /* Interrupt enable / disable */
2642 bnad_enable_msix(struct bnad
*bnad
)
2645 unsigned long flags
;
2647 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2648 if (!(bnad
->cfg_flags
& BNAD_CF_MSIX
)) {
2649 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2652 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2654 if (bnad
->msix_table
)
2658 kcalloc(bnad
->msix_num
, sizeof(struct msix_entry
), GFP_KERNEL
);
2660 if (!bnad
->msix_table
)
2663 for (i
= 0; i
< bnad
->msix_num
; i
++)
2664 bnad
->msix_table
[i
].entry
= i
;
2666 ret
= pci_enable_msix_range(bnad
->pcidev
, bnad
->msix_table
,
2670 } else if (ret
< bnad
->msix_num
) {
2671 dev_warn(&bnad
->pcidev
->dev
,
2672 "%d MSI-X vectors allocated < %d requested\n",
2673 ret
, bnad
->msix_num
);
2675 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2676 /* ret = #of vectors that we got */
2677 bnad_q_num_adjust(bnad
, (ret
- BNAD_MAILBOX_MSIX_VECTORS
) / 2,
2678 (ret
- BNAD_MAILBOX_MSIX_VECTORS
) / 2);
2679 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2681 bnad
->msix_num
= BNAD_NUM_TXQ
+ BNAD_NUM_RXP
+
2682 BNAD_MAILBOX_MSIX_VECTORS
;
2684 if (bnad
->msix_num
> ret
) {
2685 pci_disable_msix(bnad
->pcidev
);
2690 pci_intx(bnad
->pcidev
, 0);
2695 dev_warn(&bnad
->pcidev
->dev
,
2696 "MSI-X enable failed - operating in INTx mode\n");
2698 kfree(bnad
->msix_table
);
2699 bnad
->msix_table
= NULL
;
2701 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2702 bnad
->cfg_flags
&= ~BNAD_CF_MSIX
;
2703 bnad_q_num_init(bnad
);
2704 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2708 bnad_disable_msix(struct bnad
*bnad
)
2711 unsigned long flags
;
2713 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2714 cfg_flags
= bnad
->cfg_flags
;
2715 if (bnad
->cfg_flags
& BNAD_CF_MSIX
)
2716 bnad
->cfg_flags
&= ~BNAD_CF_MSIX
;
2717 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2719 if (cfg_flags
& BNAD_CF_MSIX
) {
2720 pci_disable_msix(bnad
->pcidev
);
2721 kfree(bnad
->msix_table
);
2722 bnad
->msix_table
= NULL
;
2726 /* Netdev entry points */
2728 bnad_open(struct net_device
*netdev
)
2731 struct bnad
*bnad
= netdev_priv(netdev
);
2732 struct bna_pause_config pause_config
;
2733 unsigned long flags
;
2735 mutex_lock(&bnad
->conf_mutex
);
2738 err
= bnad_setup_tx(bnad
, 0);
2743 err
= bnad_setup_rx(bnad
, 0);
2748 pause_config
.tx_pause
= 0;
2749 pause_config
.rx_pause
= 0;
2751 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2752 bna_enet_mtu_set(&bnad
->bna
.enet
,
2753 BNAD_FRAME_SIZE(bnad
->netdev
->mtu
), NULL
);
2754 bna_enet_pause_config(&bnad
->bna
.enet
, &pause_config
);
2755 bna_enet_enable(&bnad
->bna
.enet
);
2756 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2758 /* Enable broadcast */
2759 bnad_enable_default_bcast(bnad
);
2761 /* Restore VLANs, if any */
2762 bnad_restore_vlans(bnad
, 0);
2764 /* Set the UCAST address */
2765 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2766 bnad_mac_addr_set_locked(bnad
, netdev
->dev_addr
);
2767 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2769 /* Start the stats timer */
2770 bnad_stats_timer_start(bnad
);
2772 mutex_unlock(&bnad
->conf_mutex
);
2777 bnad_destroy_tx(bnad
, 0);
2780 mutex_unlock(&bnad
->conf_mutex
);
2785 bnad_stop(struct net_device
*netdev
)
2787 struct bnad
*bnad
= netdev_priv(netdev
);
2788 unsigned long flags
;
2790 mutex_lock(&bnad
->conf_mutex
);
2792 /* Stop the stats timer */
2793 bnad_stats_timer_stop(bnad
);
2795 init_completion(&bnad
->bnad_completions
.enet_comp
);
2797 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2798 bna_enet_disable(&bnad
->bna
.enet
, BNA_HARD_CLEANUP
,
2799 bnad_cb_enet_disabled
);
2800 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2802 wait_for_completion(&bnad
->bnad_completions
.enet_comp
);
2804 bnad_destroy_tx(bnad
, 0);
2805 bnad_destroy_rx(bnad
, 0);
2807 /* Synchronize mailbox IRQ */
2808 bnad_mbox_irq_sync(bnad
);
2810 mutex_unlock(&bnad
->conf_mutex
);
2816 /* Returns 0 for success */
2818 bnad_txq_wi_prepare(struct bnad
*bnad
, struct bna_tcb
*tcb
,
2819 struct sk_buff
*skb
, struct bna_txq_entry
*txqent
)
2825 if (skb_vlan_tag_present(skb
)) {
2826 vlan_tag
= (u16
)skb_vlan_tag_get(skb
);
2827 flags
|= (BNA_TXQ_WI_CF_INS_PRIO
| BNA_TXQ_WI_CF_INS_VLAN
);
2829 if (test_bit(BNAD_RF_CEE_RUNNING
, &bnad
->run_flags
)) {
2830 vlan_tag
= ((tcb
->priority
& 0x7) << VLAN_PRIO_SHIFT
)
2831 | (vlan_tag
& 0x1fff);
2832 flags
|= (BNA_TXQ_WI_CF_INS_PRIO
| BNA_TXQ_WI_CF_INS_VLAN
);
2834 txqent
->hdr
.wi
.vlan_tag
= htons(vlan_tag
);
2836 if (skb_is_gso(skb
)) {
2837 gso_size
= skb_shinfo(skb
)->gso_size
;
2838 if (unlikely(gso_size
> bnad
->netdev
->mtu
)) {
2839 BNAD_UPDATE_CTR(bnad
, tx_skb_mss_too_long
);
2842 if (unlikely((gso_size
+ skb_transport_offset(skb
) +
2843 tcp_hdrlen(skb
)) >= skb
->len
)) {
2844 txqent
->hdr
.wi
.opcode
= htons(BNA_TXQ_WI_SEND
);
2845 txqent
->hdr
.wi
.lso_mss
= 0;
2846 BNAD_UPDATE_CTR(bnad
, tx_skb_tso_too_short
);
2848 txqent
->hdr
.wi
.opcode
= htons(BNA_TXQ_WI_SEND_LSO
);
2849 txqent
->hdr
.wi
.lso_mss
= htons(gso_size
);
2852 if (bnad_tso_prepare(bnad
, skb
)) {
2853 BNAD_UPDATE_CTR(bnad
, tx_skb_tso_prepare
);
2857 flags
|= (BNA_TXQ_WI_CF_IP_CKSUM
| BNA_TXQ_WI_CF_TCP_CKSUM
);
2858 txqent
->hdr
.wi
.l4_hdr_size_n_offset
=
2859 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET(
2860 tcp_hdrlen(skb
) >> 2, skb_transport_offset(skb
)));
2862 txqent
->hdr
.wi
.opcode
= htons(BNA_TXQ_WI_SEND
);
2863 txqent
->hdr
.wi
.lso_mss
= 0;
2865 if (unlikely(skb
->len
> (bnad
->netdev
->mtu
+ VLAN_ETH_HLEN
))) {
2866 BNAD_UPDATE_CTR(bnad
, tx_skb_non_tso_too_long
);
2870 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
2871 __be16 net_proto
= vlan_get_protocol(skb
);
2874 if (net_proto
== htons(ETH_P_IP
))
2875 proto
= ip_hdr(skb
)->protocol
;
2876 #ifdef NETIF_F_IPV6_CSUM
2877 else if (net_proto
== htons(ETH_P_IPV6
)) {
2878 /* nexthdr may not be TCP immediately. */
2879 proto
= ipv6_hdr(skb
)->nexthdr
;
2882 if (proto
== IPPROTO_TCP
) {
2883 flags
|= BNA_TXQ_WI_CF_TCP_CKSUM
;
2884 txqent
->hdr
.wi
.l4_hdr_size_n_offset
=
2885 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
2886 (0, skb_transport_offset(skb
)));
2888 BNAD_UPDATE_CTR(bnad
, tcpcsum_offload
);
2890 if (unlikely(skb_headlen(skb
) <
2891 skb_transport_offset(skb
) +
2893 BNAD_UPDATE_CTR(bnad
, tx_skb_tcp_hdr
);
2896 } else if (proto
== IPPROTO_UDP
) {
2897 flags
|= BNA_TXQ_WI_CF_UDP_CKSUM
;
2898 txqent
->hdr
.wi
.l4_hdr_size_n_offset
=
2899 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
2900 (0, skb_transport_offset(skb
)));
2902 BNAD_UPDATE_CTR(bnad
, udpcsum_offload
);
2903 if (unlikely(skb_headlen(skb
) <
2904 skb_transport_offset(skb
) +
2905 sizeof(struct udphdr
))) {
2906 BNAD_UPDATE_CTR(bnad
, tx_skb_udp_hdr
);
2911 BNAD_UPDATE_CTR(bnad
, tx_skb_csum_err
);
2915 txqent
->hdr
.wi
.l4_hdr_size_n_offset
= 0;
2918 txqent
->hdr
.wi
.flags
= htons(flags
);
2919 txqent
->hdr
.wi
.frame_length
= htonl(skb
->len
);
2925 * bnad_start_xmit : Netdev entry point for Transmit
2926 * Called under lock held by net_device
2929 bnad_start_xmit(struct sk_buff
*skb
, struct net_device
*netdev
)
2931 struct bnad
*bnad
= netdev_priv(netdev
);
2933 struct bna_tcb
*tcb
= NULL
;
2934 struct bnad_tx_unmap
*unmap_q
, *unmap
, *head_unmap
;
2935 u32 prod
, q_depth
, vect_id
;
2936 u32 wis
, vectors
, len
;
2938 dma_addr_t dma_addr
;
2939 struct bna_txq_entry
*txqent
;
2941 len
= skb_headlen(skb
);
2943 /* Sanity checks for the skb */
2945 if (unlikely(skb
->len
<= ETH_HLEN
)) {
2946 dev_kfree_skb_any(skb
);
2947 BNAD_UPDATE_CTR(bnad
, tx_skb_too_short
);
2948 return NETDEV_TX_OK
;
2950 if (unlikely(len
> BFI_TX_MAX_DATA_PER_VECTOR
)) {
2951 dev_kfree_skb_any(skb
);
2952 BNAD_UPDATE_CTR(bnad
, tx_skb_headlen_zero
);
2953 return NETDEV_TX_OK
;
2955 if (unlikely(len
== 0)) {
2956 dev_kfree_skb_any(skb
);
2957 BNAD_UPDATE_CTR(bnad
, tx_skb_headlen_zero
);
2958 return NETDEV_TX_OK
;
2961 tcb
= bnad
->tx_info
[0].tcb
[txq_id
];
2964 * Takes care of the Tx that is scheduled between clearing the flag
2965 * and the netif_tx_stop_all_queues() call.
2967 if (unlikely(!tcb
|| !test_bit(BNAD_TXQ_TX_STARTED
, &tcb
->flags
))) {
2968 dev_kfree_skb_any(skb
);
2969 BNAD_UPDATE_CTR(bnad
, tx_skb_stopping
);
2970 return NETDEV_TX_OK
;
2973 q_depth
= tcb
->q_depth
;
2974 prod
= tcb
->producer_index
;
2975 unmap_q
= tcb
->unmap_q
;
2977 vectors
= 1 + skb_shinfo(skb
)->nr_frags
;
2978 wis
= BNA_TXQ_WI_NEEDED(vectors
); /* 4 vectors per work item */
2980 if (unlikely(vectors
> BFI_TX_MAX_VECTORS_PER_PKT
)) {
2981 dev_kfree_skb_any(skb
);
2982 BNAD_UPDATE_CTR(bnad
, tx_skb_max_vectors
);
2983 return NETDEV_TX_OK
;
2986 /* Check for available TxQ resources */
2987 if (unlikely(wis
> BNA_QE_FREE_CNT(tcb
, q_depth
))) {
2988 if ((*tcb
->hw_consumer_index
!= tcb
->consumer_index
) &&
2989 !test_and_set_bit(BNAD_TXQ_FREE_SENT
, &tcb
->flags
)) {
2991 sent
= bnad_txcmpl_process(bnad
, tcb
);
2992 if (likely(test_bit(BNAD_TXQ_TX_STARTED
, &tcb
->flags
)))
2993 bna_ib_ack(tcb
->i_dbell
, sent
);
2994 smp_mb__before_atomic();
2995 clear_bit(BNAD_TXQ_FREE_SENT
, &tcb
->flags
);
2997 netif_stop_queue(netdev
);
2998 BNAD_UPDATE_CTR(bnad
, netif_queue_stop
);
3003 * Check again to deal with race condition between
3004 * netif_stop_queue here, and netif_wake_queue in
3005 * interrupt handler which is not inside netif tx lock.
3007 if (likely(wis
> BNA_QE_FREE_CNT(tcb
, q_depth
))) {
3008 BNAD_UPDATE_CTR(bnad
, netif_queue_stop
);
3009 return NETDEV_TX_BUSY
;
3011 netif_wake_queue(netdev
);
3012 BNAD_UPDATE_CTR(bnad
, netif_queue_wakeup
);
3016 txqent
= &((struct bna_txq_entry
*)tcb
->sw_q
)[prod
];
3017 head_unmap
= &unmap_q
[prod
];
3019 /* Program the opcode, flags, frame_len, num_vectors in WI */
3020 if (bnad_txq_wi_prepare(bnad
, tcb
, skb
, txqent
)) {
3021 dev_kfree_skb_any(skb
);
3022 return NETDEV_TX_OK
;
3024 txqent
->hdr
.wi
.reserved
= 0;
3025 txqent
->hdr
.wi
.num_vectors
= vectors
;
3027 head_unmap
->skb
= skb
;
3028 head_unmap
->nvecs
= 0;
3030 /* Program the vectors */
3032 dma_addr
= dma_map_single(&bnad
->pcidev
->dev
, skb
->data
,
3033 len
, DMA_TO_DEVICE
);
3034 if (dma_mapping_error(&bnad
->pcidev
->dev
, dma_addr
)) {
3035 dev_kfree_skb_any(skb
);
3036 BNAD_UPDATE_CTR(bnad
, tx_skb_map_failed
);
3037 return NETDEV_TX_OK
;
3039 BNA_SET_DMA_ADDR(dma_addr
, &txqent
->vector
[0].host_addr
);
3040 txqent
->vector
[0].length
= htons(len
);
3041 dma_unmap_addr_set(&unmap
->vectors
[0], dma_addr
, dma_addr
);
3042 head_unmap
->nvecs
++;
3044 for (i
= 0, vect_id
= 0; i
< vectors
- 1; i
++) {
3045 const struct skb_frag_struct
*frag
= &skb_shinfo(skb
)->frags
[i
];
3046 u32 size
= skb_frag_size(frag
);
3048 if (unlikely(size
== 0)) {
3049 /* Undo the changes starting at tcb->producer_index */
3050 bnad_tx_buff_unmap(bnad
, unmap_q
, q_depth
,
3051 tcb
->producer_index
);
3052 dev_kfree_skb_any(skb
);
3053 BNAD_UPDATE_CTR(bnad
, tx_skb_frag_zero
);
3054 return NETDEV_TX_OK
;
3060 if (vect_id
== BFI_TX_MAX_VECTORS_PER_WI
) {
3062 BNA_QE_INDX_INC(prod
, q_depth
);
3063 txqent
= &((struct bna_txq_entry
*)tcb
->sw_q
)[prod
];
3064 txqent
->hdr
.wi_ext
.opcode
= htons(BNA_TXQ_WI_EXTENSION
);
3065 unmap
= &unmap_q
[prod
];
3068 dma_addr
= skb_frag_dma_map(&bnad
->pcidev
->dev
, frag
,
3069 0, size
, DMA_TO_DEVICE
);
3070 if (dma_mapping_error(&bnad
->pcidev
->dev
, dma_addr
)) {
3071 /* Undo the changes starting at tcb->producer_index */
3072 bnad_tx_buff_unmap(bnad
, unmap_q
, q_depth
,
3073 tcb
->producer_index
);
3074 dev_kfree_skb_any(skb
);
3075 BNAD_UPDATE_CTR(bnad
, tx_skb_map_failed
);
3076 return NETDEV_TX_OK
;
3079 dma_unmap_len_set(&unmap
->vectors
[vect_id
], dma_len
, size
);
3080 BNA_SET_DMA_ADDR(dma_addr
, &txqent
->vector
[vect_id
].host_addr
);
3081 txqent
->vector
[vect_id
].length
= htons(size
);
3082 dma_unmap_addr_set(&unmap
->vectors
[vect_id
], dma_addr
,
3084 head_unmap
->nvecs
++;
3087 if (unlikely(len
!= skb
->len
)) {
3088 /* Undo the changes starting at tcb->producer_index */
3089 bnad_tx_buff_unmap(bnad
, unmap_q
, q_depth
, tcb
->producer_index
);
3090 dev_kfree_skb_any(skb
);
3091 BNAD_UPDATE_CTR(bnad
, tx_skb_len_mismatch
);
3092 return NETDEV_TX_OK
;
3095 BNA_QE_INDX_INC(prod
, q_depth
);
3096 tcb
->producer_index
= prod
;
3100 if (unlikely(!test_bit(BNAD_TXQ_TX_STARTED
, &tcb
->flags
)))
3101 return NETDEV_TX_OK
;
3103 skb_tx_timestamp(skb
);
3105 bna_txq_prod_indx_doorbell(tcb
);
3107 return NETDEV_TX_OK
;
3111 * Used spin_lock to synchronize reading of stats structures, which
3112 * is written by BNA under the same lock.
3115 bnad_get_stats64(struct net_device
*netdev
, struct rtnl_link_stats64
*stats
)
3117 struct bnad
*bnad
= netdev_priv(netdev
);
3118 unsigned long flags
;
3120 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3122 bnad_netdev_qstats_fill(bnad
, stats
);
3123 bnad_netdev_hwstats_fill(bnad
, stats
);
3125 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3129 bnad_set_rx_ucast_fltr(struct bnad
*bnad
)
3131 struct net_device
*netdev
= bnad
->netdev
;
3132 int uc_count
= netdev_uc_count(netdev
);
3133 enum bna_cb_status ret
;
3135 struct netdev_hw_addr
*ha
;
3138 if (netdev_uc_empty(bnad
->netdev
)) {
3139 bna_rx_ucast_listset(bnad
->rx_info
[0].rx
, 0, NULL
);
3143 if (uc_count
> bna_attr(&bnad
->bna
)->num_ucmac
)
3146 mac_list
= kzalloc(uc_count
* ETH_ALEN
, GFP_ATOMIC
);
3147 if (mac_list
== NULL
)
3151 netdev_for_each_uc_addr(ha
, netdev
) {
3152 ether_addr_copy(&mac_list
[entry
* ETH_ALEN
], &ha
->addr
[0]);
3156 ret
= bna_rx_ucast_listset(bnad
->rx_info
[0].rx
, entry
, mac_list
);
3159 if (ret
!= BNA_CB_SUCCESS
)
3164 /* ucast packets not in UCAM are routed to default function */
3166 bnad
->cfg_flags
|= BNAD_CF_DEFAULT
;
3167 bna_rx_ucast_listset(bnad
->rx_info
[0].rx
, 0, NULL
);
3171 bnad_set_rx_mcast_fltr(struct bnad
*bnad
)
3173 struct net_device
*netdev
= bnad
->netdev
;
3174 int mc_count
= netdev_mc_count(netdev
);
3175 enum bna_cb_status ret
;
3178 if (netdev
->flags
& IFF_ALLMULTI
)
3181 if (netdev_mc_empty(netdev
))
3184 if (mc_count
> bna_attr(&bnad
->bna
)->num_mcmac
)
3187 mac_list
= kzalloc((mc_count
+ 1) * ETH_ALEN
, GFP_ATOMIC
);
3189 if (mac_list
== NULL
)
3192 ether_addr_copy(&mac_list
[0], &bnad_bcast_addr
[0]);
3194 /* copy rest of the MCAST addresses */
3195 bnad_netdev_mc_list_get(netdev
, mac_list
);
3196 ret
= bna_rx_mcast_listset(bnad
->rx_info
[0].rx
, mc_count
+ 1, mac_list
);
3199 if (ret
!= BNA_CB_SUCCESS
)
3205 bnad
->cfg_flags
|= BNAD_CF_ALLMULTI
;
3206 bna_rx_mcast_delall(bnad
->rx_info
[0].rx
);
3210 bnad_set_rx_mode(struct net_device
*netdev
)
3212 struct bnad
*bnad
= netdev_priv(netdev
);
3213 enum bna_rxmode new_mode
, mode_mask
;
3214 unsigned long flags
;
3216 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3218 if (bnad
->rx_info
[0].rx
== NULL
) {
3219 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3223 /* clear bnad flags to update it with new settings */
3224 bnad
->cfg_flags
&= ~(BNAD_CF_PROMISC
| BNAD_CF_DEFAULT
|
3228 if (netdev
->flags
& IFF_PROMISC
) {
3229 new_mode
|= BNAD_RXMODE_PROMISC_DEFAULT
;
3230 bnad
->cfg_flags
|= BNAD_CF_PROMISC
;
3232 bnad_set_rx_mcast_fltr(bnad
);
3234 if (bnad
->cfg_flags
& BNAD_CF_ALLMULTI
)
3235 new_mode
|= BNA_RXMODE_ALLMULTI
;
3237 bnad_set_rx_ucast_fltr(bnad
);
3239 if (bnad
->cfg_flags
& BNAD_CF_DEFAULT
)
3240 new_mode
|= BNA_RXMODE_DEFAULT
;
3243 mode_mask
= BNA_RXMODE_PROMISC
| BNA_RXMODE_DEFAULT
|
3244 BNA_RXMODE_ALLMULTI
;
3245 bna_rx_mode_set(bnad
->rx_info
[0].rx
, new_mode
, mode_mask
);
3247 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3251 * bna_lock is used to sync writes to netdev->addr
3252 * conf_lock cannot be used since this call may be made
3253 * in a non-blocking context.
3256 bnad_set_mac_address(struct net_device
*netdev
, void *addr
)
3259 struct bnad
*bnad
= netdev_priv(netdev
);
3260 struct sockaddr
*sa
= (struct sockaddr
*)addr
;
3261 unsigned long flags
;
3263 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3265 err
= bnad_mac_addr_set_locked(bnad
, sa
->sa_data
);
3267 ether_addr_copy(netdev
->dev_addr
, sa
->sa_data
);
3269 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3275 bnad_mtu_set(struct bnad
*bnad
, int frame_size
)
3277 unsigned long flags
;
3279 init_completion(&bnad
->bnad_completions
.mtu_comp
);
3281 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3282 bna_enet_mtu_set(&bnad
->bna
.enet
, frame_size
, bnad_cb_enet_mtu_set
);
3283 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3285 wait_for_completion(&bnad
->bnad_completions
.mtu_comp
);
3287 return bnad
->bnad_completions
.mtu_comp_status
;
3291 bnad_change_mtu(struct net_device
*netdev
, int new_mtu
)
3294 struct bnad
*bnad
= netdev_priv(netdev
);
3295 u32 rx_count
= 0, frame
, new_frame
;
3297 mutex_lock(&bnad
->conf_mutex
);
3300 netdev
->mtu
= new_mtu
;
3302 frame
= BNAD_FRAME_SIZE(mtu
);
3303 new_frame
= BNAD_FRAME_SIZE(new_mtu
);
3305 /* check if multi-buffer needs to be enabled */
3306 if (BNAD_PCI_DEV_IS_CAT2(bnad
) &&
3307 netif_running(bnad
->netdev
)) {
3308 /* only when transition is over 4K */
3309 if ((frame
<= 4096 && new_frame
> 4096) ||
3310 (frame
> 4096 && new_frame
<= 4096))
3311 rx_count
= bnad_reinit_rx(bnad
);
3314 /* rx_count > 0 - new rx created
3315 * - Linux set err = 0 and return
3317 err
= bnad_mtu_set(bnad
, new_frame
);
3321 mutex_unlock(&bnad
->conf_mutex
);
3326 bnad_vlan_rx_add_vid(struct net_device
*netdev
, __be16 proto
, u16 vid
)
3328 struct bnad
*bnad
= netdev_priv(netdev
);
3329 unsigned long flags
;
3331 if (!bnad
->rx_info
[0].rx
)
3334 mutex_lock(&bnad
->conf_mutex
);
3336 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3337 bna_rx_vlan_add(bnad
->rx_info
[0].rx
, vid
);
3338 set_bit(vid
, bnad
->active_vlans
);
3339 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3341 mutex_unlock(&bnad
->conf_mutex
);
3347 bnad_vlan_rx_kill_vid(struct net_device
*netdev
, __be16 proto
, u16 vid
)
3349 struct bnad
*bnad
= netdev_priv(netdev
);
3350 unsigned long flags
;
3352 if (!bnad
->rx_info
[0].rx
)
3355 mutex_lock(&bnad
->conf_mutex
);
3357 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3358 clear_bit(vid
, bnad
->active_vlans
);
3359 bna_rx_vlan_del(bnad
->rx_info
[0].rx
, vid
);
3360 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3362 mutex_unlock(&bnad
->conf_mutex
);
3367 static int bnad_set_features(struct net_device
*dev
, netdev_features_t features
)
3369 struct bnad
*bnad
= netdev_priv(dev
);
3370 netdev_features_t changed
= features
^ dev
->features
;
3372 if ((changed
& NETIF_F_HW_VLAN_CTAG_RX
) && netif_running(dev
)) {
3373 unsigned long flags
;
3375 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3377 if (features
& NETIF_F_HW_VLAN_CTAG_RX
)
3378 bna_rx_vlan_strip_enable(bnad
->rx_info
[0].rx
);
3380 bna_rx_vlan_strip_disable(bnad
->rx_info
[0].rx
);
3382 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3388 #ifdef CONFIG_NET_POLL_CONTROLLER
3390 bnad_netpoll(struct net_device
*netdev
)
3392 struct bnad
*bnad
= netdev_priv(netdev
);
3393 struct bnad_rx_info
*rx_info
;
3394 struct bnad_rx_ctrl
*rx_ctrl
;
3398 if (!(bnad
->cfg_flags
& BNAD_CF_MSIX
)) {
3399 bna_intx_disable(&bnad
->bna
, curr_mask
);
3400 bnad_isr(bnad
->pcidev
->irq
, netdev
);
3401 bna_intx_enable(&bnad
->bna
, curr_mask
);
3404 * Tx processing may happen in sending context, so no need
3405 * to explicitly process completions here
3409 for (i
= 0; i
< bnad
->num_rx
; i
++) {
3410 rx_info
= &bnad
->rx_info
[i
];
3413 for (j
= 0; j
< bnad
->num_rxp_per_rx
; j
++) {
3414 rx_ctrl
= &rx_info
->rx_ctrl
[j
];
3416 bnad_netif_rx_schedule_poll(bnad
,
3424 static const struct net_device_ops bnad_netdev_ops
= {
3425 .ndo_open
= bnad_open
,
3426 .ndo_stop
= bnad_stop
,
3427 .ndo_start_xmit
= bnad_start_xmit
,
3428 .ndo_get_stats64
= bnad_get_stats64
,
3429 .ndo_set_rx_mode
= bnad_set_rx_mode
,
3430 .ndo_validate_addr
= eth_validate_addr
,
3431 .ndo_set_mac_address
= bnad_set_mac_address
,
3432 .ndo_change_mtu
= bnad_change_mtu
,
3433 .ndo_vlan_rx_add_vid
= bnad_vlan_rx_add_vid
,
3434 .ndo_vlan_rx_kill_vid
= bnad_vlan_rx_kill_vid
,
3435 .ndo_set_features
= bnad_set_features
,
3436 #ifdef CONFIG_NET_POLL_CONTROLLER
3437 .ndo_poll_controller
= bnad_netpoll
3442 bnad_netdev_init(struct bnad
*bnad
, bool using_dac
)
3444 struct net_device
*netdev
= bnad
->netdev
;
3446 netdev
->hw_features
= NETIF_F_SG
| NETIF_F_RXCSUM
|
3447 NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
|
3448 NETIF_F_TSO
| NETIF_F_TSO6
| NETIF_F_HW_VLAN_CTAG_TX
|
3449 NETIF_F_HW_VLAN_CTAG_RX
;
3451 netdev
->vlan_features
= NETIF_F_SG
| NETIF_F_HIGHDMA
|
3452 NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
|
3453 NETIF_F_TSO
| NETIF_F_TSO6
;
3455 netdev
->features
|= netdev
->hw_features
| NETIF_F_HW_VLAN_CTAG_FILTER
;
3458 netdev
->features
|= NETIF_F_HIGHDMA
;
3460 netdev
->mem_start
= bnad
->mmio_start
;
3461 netdev
->mem_end
= bnad
->mmio_start
+ bnad
->mmio_len
- 1;
3463 /* MTU range: 46 - 9000 */
3464 netdev
->min_mtu
= ETH_ZLEN
- ETH_HLEN
;
3465 netdev
->max_mtu
= BNAD_JUMBO_MTU
;
3467 netdev
->netdev_ops
= &bnad_netdev_ops
;
3468 bnad_set_ethtool_ops(netdev
);
3472 * 1. Initialize the bnad structure
3473 * 2. Setup netdev pointer in pci_dev
3474 * 3. Initialize no. of TxQ & CQs & MSIX vectors
3475 * 4. Initialize work queue.
3478 bnad_init(struct bnad
*bnad
,
3479 struct pci_dev
*pdev
, struct net_device
*netdev
)
3481 unsigned long flags
;
3483 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
3484 pci_set_drvdata(pdev
, netdev
);
3486 bnad
->netdev
= netdev
;
3487 bnad
->pcidev
= pdev
;
3488 bnad
->mmio_start
= pci_resource_start(pdev
, 0);
3489 bnad
->mmio_len
= pci_resource_len(pdev
, 0);
3490 bnad
->bar0
= ioremap_nocache(bnad
->mmio_start
, bnad
->mmio_len
);
3492 dev_err(&pdev
->dev
, "ioremap for bar0 failed\n");
3495 dev_info(&pdev
->dev
, "bar0 mapped to %p, len %llu\n", bnad
->bar0
,
3496 (unsigned long long) bnad
->mmio_len
);
3498 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3499 if (!bnad_msix_disable
)
3500 bnad
->cfg_flags
= BNAD_CF_MSIX
;
3502 bnad
->cfg_flags
|= BNAD_CF_DIM_ENABLED
;
3504 bnad_q_num_init(bnad
);
3505 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3507 bnad
->msix_num
= (bnad
->num_tx
* bnad
->num_txq_per_tx
) +
3508 (bnad
->num_rx
* bnad
->num_rxp_per_rx
) +
3509 BNAD_MAILBOX_MSIX_VECTORS
;
3511 bnad
->txq_depth
= BNAD_TXQ_DEPTH
;
3512 bnad
->rxq_depth
= BNAD_RXQ_DEPTH
;
3514 bnad
->tx_coalescing_timeo
= BFI_TX_COALESCING_TIMEO
;
3515 bnad
->rx_coalescing_timeo
= BFI_RX_COALESCING_TIMEO
;
3517 sprintf(bnad
->wq_name
, "%s_wq_%d", BNAD_NAME
, bnad
->id
);
3518 bnad
->work_q
= create_singlethread_workqueue(bnad
->wq_name
);
3519 if (!bnad
->work_q
) {
3520 iounmap(bnad
->bar0
);
3528 * Must be called after bnad_pci_uninit()
3529 * so that iounmap() and pci_set_drvdata(NULL)
3530 * happens only after PCI uninitialization.
3533 bnad_uninit(struct bnad
*bnad
)
3536 flush_workqueue(bnad
->work_q
);
3537 destroy_workqueue(bnad
->work_q
);
3538 bnad
->work_q
= NULL
;
3542 iounmap(bnad
->bar0
);
3547 a) Per ioceth mutes used for serializing configuration
3548 changes from OS interface
3549 b) spin lock used to protect bna state machine
3552 bnad_lock_init(struct bnad
*bnad
)
3554 spin_lock_init(&bnad
->bna_lock
);
3555 mutex_init(&bnad
->conf_mutex
);
3559 bnad_lock_uninit(struct bnad
*bnad
)
3561 mutex_destroy(&bnad
->conf_mutex
);
3564 /* PCI Initialization */
3566 bnad_pci_init(struct bnad
*bnad
,
3567 struct pci_dev
*pdev
, bool *using_dac
)
3571 err
= pci_enable_device(pdev
);
3574 err
= pci_request_regions(pdev
, BNAD_NAME
);
3576 goto disable_device
;
3577 if (!dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(64))) {
3580 err
= dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(32));
3582 goto release_regions
;
3585 pci_set_master(pdev
);
3589 pci_release_regions(pdev
);
3591 pci_disable_device(pdev
);
3597 bnad_pci_uninit(struct pci_dev
*pdev
)
3599 pci_release_regions(pdev
);
3600 pci_disable_device(pdev
);
3604 bnad_pci_probe(struct pci_dev
*pdev
,
3605 const struct pci_device_id
*pcidev_id
)
3611 struct net_device
*netdev
;
3612 struct bfa_pcidev pcidev_info
;
3613 unsigned long flags
;
3615 mutex_lock(&bnad_fwimg_mutex
);
3616 if (!cna_get_firmware_buf(pdev
)) {
3617 mutex_unlock(&bnad_fwimg_mutex
);
3618 dev_err(&pdev
->dev
, "failed to load firmware image!\n");
3621 mutex_unlock(&bnad_fwimg_mutex
);
3624 * Allocates sizeof(struct net_device + struct bnad)
3625 * bnad = netdev->priv
3627 netdev
= alloc_etherdev(sizeof(struct bnad
));
3632 bnad
= netdev_priv(netdev
);
3633 bnad_lock_init(bnad
);
3634 bnad
->id
= atomic_inc_return(&bna_id
) - 1;
3636 mutex_lock(&bnad
->conf_mutex
);
3638 * PCI initialization
3639 * Output : using_dac = 1 for 64 bit DMA
3640 * = 0 for 32 bit DMA
3643 err
= bnad_pci_init(bnad
, pdev
, &using_dac
);
3648 * Initialize bnad structure
3649 * Setup relation between pci_dev & netdev
3651 err
= bnad_init(bnad
, pdev
, netdev
);
3655 /* Initialize netdev structure, set up ethtool ops */
3656 bnad_netdev_init(bnad
, using_dac
);
3658 /* Set link to down state */
3659 netif_carrier_off(netdev
);
3661 /* Setup the debugfs node for this bfad */
3662 if (bna_debugfs_enable
)
3663 bnad_debugfs_init(bnad
);
3665 /* Get resource requirement form bna */
3666 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3667 bna_res_req(&bnad
->res_info
[0]);
3668 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3670 /* Allocate resources from bna */
3671 err
= bnad_res_alloc(bnad
, &bnad
->res_info
[0], BNA_RES_T_MAX
);
3677 /* Setup pcidev_info for bna_init() */
3678 pcidev_info
.pci_slot
= PCI_SLOT(bnad
->pcidev
->devfn
);
3679 pcidev_info
.pci_func
= PCI_FUNC(bnad
->pcidev
->devfn
);
3680 pcidev_info
.device_id
= bnad
->pcidev
->device
;
3681 pcidev_info
.pci_bar_kva
= bnad
->bar0
;
3683 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3684 bna_init(bna
, bnad
, &pcidev_info
, &bnad
->res_info
[0]);
3685 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3687 bnad
->stats
.bna_stats
= &bna
->stats
;
3689 bnad_enable_msix(bnad
);
3690 err
= bnad_mbox_irq_alloc(bnad
);
3695 setup_timer(&bnad
->bna
.ioceth
.ioc
.ioc_timer
, bnad_ioc_timeout
,
3696 (unsigned long)bnad
);
3697 setup_timer(&bnad
->bna
.ioceth
.ioc
.hb_timer
, bnad_ioc_hb_check
,
3698 (unsigned long)bnad
);
3699 setup_timer(&bnad
->bna
.ioceth
.ioc
.iocpf_timer
, bnad_iocpf_timeout
,
3700 (unsigned long)bnad
);
3701 setup_timer(&bnad
->bna
.ioceth
.ioc
.sem_timer
, bnad_iocpf_sem_timeout
,
3702 (unsigned long)bnad
);
3706 * If the call back comes with error, we bail out.
3707 * This is a catastrophic error.
3709 err
= bnad_ioceth_enable(bnad
);
3711 dev_err(&pdev
->dev
, "initialization failed err=%d\n", err
);
3715 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3716 if (bna_num_txq_set(bna
, BNAD_NUM_TXQ
+ 1) ||
3717 bna_num_rxp_set(bna
, BNAD_NUM_RXP
+ 1)) {
3718 bnad_q_num_adjust(bnad
, bna_attr(bna
)->num_txq
- 1,
3719 bna_attr(bna
)->num_rxp
- 1);
3720 if (bna_num_txq_set(bna
, BNAD_NUM_TXQ
+ 1) ||
3721 bna_num_rxp_set(bna
, BNAD_NUM_RXP
+ 1))
3724 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3726 goto disable_ioceth
;
3728 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3729 bna_mod_res_req(&bnad
->bna
, &bnad
->mod_res_info
[0]);
3730 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3732 err
= bnad_res_alloc(bnad
, &bnad
->mod_res_info
[0], BNA_MOD_RES_T_MAX
);
3735 goto disable_ioceth
;
3738 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3739 bna_mod_init(&bnad
->bna
, &bnad
->mod_res_info
[0]);
3740 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3742 /* Get the burnt-in mac */
3743 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3744 bna_enet_perm_mac_get(&bna
->enet
, bnad
->perm_addr
);
3745 bnad_set_netdev_perm_addr(bnad
);
3746 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3748 mutex_unlock(&bnad
->conf_mutex
);
3750 /* Finally, reguister with net_device layer */
3751 err
= register_netdev(netdev
);
3753 dev_err(&pdev
->dev
, "registering net device failed\n");
3756 set_bit(BNAD_RF_NETDEV_REGISTERED
, &bnad
->run_flags
);
3761 mutex_unlock(&bnad
->conf_mutex
);
3765 mutex_lock(&bnad
->conf_mutex
);
3766 bnad_res_free(bnad
, &bnad
->mod_res_info
[0], BNA_MOD_RES_T_MAX
);
3768 bnad_ioceth_disable(bnad
);
3769 del_timer_sync(&bnad
->bna
.ioceth
.ioc
.ioc_timer
);
3770 del_timer_sync(&bnad
->bna
.ioceth
.ioc
.sem_timer
);
3771 del_timer_sync(&bnad
->bna
.ioceth
.ioc
.hb_timer
);
3772 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3774 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3775 bnad_mbox_irq_free(bnad
);
3776 bnad_disable_msix(bnad
);
3778 bnad_res_free(bnad
, &bnad
->res_info
[0], BNA_RES_T_MAX
);
3780 /* Remove the debugfs node for this bnad */
3781 kfree(bnad
->regdata
);
3782 bnad_debugfs_uninit(bnad
);
3785 bnad_pci_uninit(pdev
);
3787 mutex_unlock(&bnad
->conf_mutex
);
3788 bnad_lock_uninit(bnad
);
3789 free_netdev(netdev
);
3794 bnad_pci_remove(struct pci_dev
*pdev
)
3796 struct net_device
*netdev
= pci_get_drvdata(pdev
);
3799 unsigned long flags
;
3804 bnad
= netdev_priv(netdev
);
3807 if (test_and_clear_bit(BNAD_RF_NETDEV_REGISTERED
, &bnad
->run_flags
))
3808 unregister_netdev(netdev
);
3810 mutex_lock(&bnad
->conf_mutex
);
3811 bnad_ioceth_disable(bnad
);
3812 del_timer_sync(&bnad
->bna
.ioceth
.ioc
.ioc_timer
);
3813 del_timer_sync(&bnad
->bna
.ioceth
.ioc
.sem_timer
);
3814 del_timer_sync(&bnad
->bna
.ioceth
.ioc
.hb_timer
);
3815 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3817 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3819 bnad_res_free(bnad
, &bnad
->mod_res_info
[0], BNA_MOD_RES_T_MAX
);
3820 bnad_res_free(bnad
, &bnad
->res_info
[0], BNA_RES_T_MAX
);
3821 bnad_mbox_irq_free(bnad
);
3822 bnad_disable_msix(bnad
);
3823 bnad_pci_uninit(pdev
);
3824 mutex_unlock(&bnad
->conf_mutex
);
3825 bnad_lock_uninit(bnad
);
3826 /* Remove the debugfs node for this bnad */
3827 kfree(bnad
->regdata
);
3828 bnad_debugfs_uninit(bnad
);
3830 free_netdev(netdev
);
3833 static const struct pci_device_id bnad_pci_id_table
[] = {
3835 PCI_DEVICE(PCI_VENDOR_ID_BROCADE
,
3836 PCI_DEVICE_ID_BROCADE_CT
),
3837 .class = PCI_CLASS_NETWORK_ETHERNET
<< 8,
3838 .class_mask
= 0xffff00
3841 PCI_DEVICE(PCI_VENDOR_ID_BROCADE
,
3842 BFA_PCI_DEVICE_ID_CT2
),
3843 .class = PCI_CLASS_NETWORK_ETHERNET
<< 8,
3844 .class_mask
= 0xffff00
3849 MODULE_DEVICE_TABLE(pci
, bnad_pci_id_table
);
3851 static struct pci_driver bnad_pci_driver
= {
3853 .id_table
= bnad_pci_id_table
,
3854 .probe
= bnad_pci_probe
,
3855 .remove
= bnad_pci_remove
,
3859 bnad_module_init(void)
3863 pr_info("bna: QLogic BR-series 10G Ethernet driver - version: %s\n",
3866 bfa_nw_ioc_auto_recover(bnad_ioc_auto_recover
);
3868 err
= pci_register_driver(&bnad_pci_driver
);
3870 pr_err("bna: PCI driver registration failed err=%d\n", err
);
3878 bnad_module_exit(void)
3880 pci_unregister_driver(&bnad_pci_driver
);
3881 release_firmware(bfi_fw
);
3884 module_init(bnad_module_init
);
3885 module_exit(bnad_module_exit
);
3887 MODULE_AUTHOR("Brocade");
3888 MODULE_LICENSE("GPL");
3889 MODULE_DESCRIPTION("QLogic BR-series 10G PCIe Ethernet driver");
3890 MODULE_VERSION(BNAD_VERSION
);
3891 MODULE_FIRMWARE(CNA_FW_FILE_CT
);
3892 MODULE_FIRMWARE(CNA_FW_FILE_CT2
);