2 * Cadence MACB/GEM Ethernet Controller driver
4 * Copyright (C) 2004-2006 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12 #include <linux/clk.h>
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/kernel.h>
16 #include <linux/types.h>
17 #include <linux/circ_buf.h>
18 #include <linux/slab.h>
19 #include <linux/init.h>
21 #include <linux/gpio.h>
22 #include <linux/gpio/consumer.h>
23 #include <linux/interrupt.h>
24 #include <linux/netdevice.h>
25 #include <linux/etherdevice.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/platform_data/macb.h>
28 #include <linux/platform_device.h>
29 #include <linux/phy.h>
31 #include <linux/of_device.h>
32 #include <linux/of_gpio.h>
33 #include <linux/of_mdio.h>
34 #include <linux/of_net.h>
36 #include <linux/udp.h>
37 #include <linux/tcp.h>
40 #define MACB_RX_BUFFER_SIZE 128
41 #define RX_BUFFER_MULTIPLE 64 /* bytes */
43 #define DEFAULT_RX_RING_SIZE 512 /* must be power of 2 */
44 #define MIN_RX_RING_SIZE 64
45 #define MAX_RX_RING_SIZE 8192
46 #define RX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
49 #define DEFAULT_TX_RING_SIZE 512 /* must be power of 2 */
50 #define MIN_TX_RING_SIZE 64
51 #define MAX_TX_RING_SIZE 4096
52 #define TX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
55 /* level of occupied TX descriptors under which we wake up TX process */
56 #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
58 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
60 #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
63 #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP))
65 /* Max length of transmit frame must be a multiple of 8 bytes */
66 #define MACB_TX_LEN_ALIGN 8
67 #define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1)))
68 #define GEM_MAX_TX_LEN ((unsigned int)((1 << GEM_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1)))
70 #define GEM_MTU_MIN_SIZE ETH_MIN_MTU
71 #define MACB_NETIF_LSO (NETIF_F_TSO | NETIF_F_UFO)
73 #define MACB_WOL_HAS_MAGIC_PACKET (0x1 << 0)
74 #define MACB_WOL_ENABLED (0x1 << 1)
76 /* Graceful stop timeouts in us. We should allow up to
77 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
79 #define MACB_HALT_TIMEOUT 1230
81 /* DMA buffer descriptor might be different size
82 * depends on hardware configuration.
84 static unsigned int macb_dma_desc_get_size(struct macb
*bp
)
86 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
87 if (bp
->hw_dma_cap
== HW_DMA_CAP_64B
)
88 return sizeof(struct macb_dma_desc
) + sizeof(struct macb_dma_desc_64
);
90 return sizeof(struct macb_dma_desc
);
93 static unsigned int macb_adj_dma_desc_idx(struct macb
*bp
, unsigned int idx
)
95 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
96 /* Dma buffer descriptor is 4 words length (instead of 2 words)
99 if (bp
->hw_dma_cap
== HW_DMA_CAP_64B
)
105 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
106 static struct macb_dma_desc_64
*macb_64b_desc(struct macb
*bp
, struct macb_dma_desc
*desc
)
108 return (struct macb_dma_desc_64
*)((void *)desc
+ sizeof(struct macb_dma_desc
));
112 /* Ring buffer accessors */
113 static unsigned int macb_tx_ring_wrap(struct macb
*bp
, unsigned int index
)
115 return index
& (bp
->tx_ring_size
- 1);
118 static struct macb_dma_desc
*macb_tx_desc(struct macb_queue
*queue
,
121 index
= macb_tx_ring_wrap(queue
->bp
, index
);
122 index
= macb_adj_dma_desc_idx(queue
->bp
, index
);
123 return &queue
->tx_ring
[index
];
126 static struct macb_tx_skb
*macb_tx_skb(struct macb_queue
*queue
,
129 return &queue
->tx_skb
[macb_tx_ring_wrap(queue
->bp
, index
)];
132 static dma_addr_t
macb_tx_dma(struct macb_queue
*queue
, unsigned int index
)
136 offset
= macb_tx_ring_wrap(queue
->bp
, index
) *
137 macb_dma_desc_get_size(queue
->bp
);
139 return queue
->tx_ring_dma
+ offset
;
142 static unsigned int macb_rx_ring_wrap(struct macb
*bp
, unsigned int index
)
144 return index
& (bp
->rx_ring_size
- 1);
147 static struct macb_dma_desc
*macb_rx_desc(struct macb
*bp
, unsigned int index
)
149 index
= macb_rx_ring_wrap(bp
, index
);
150 index
= macb_adj_dma_desc_idx(bp
, index
);
151 return &bp
->rx_ring
[index
];
154 static void *macb_rx_buffer(struct macb
*bp
, unsigned int index
)
156 return bp
->rx_buffers
+ bp
->rx_buffer_size
*
157 macb_rx_ring_wrap(bp
, index
);
161 static u32
hw_readl_native(struct macb
*bp
, int offset
)
163 return __raw_readl(bp
->regs
+ offset
);
166 static void hw_writel_native(struct macb
*bp
, int offset
, u32 value
)
168 __raw_writel(value
, bp
->regs
+ offset
);
171 static u32
hw_readl(struct macb
*bp
, int offset
)
173 return readl_relaxed(bp
->regs
+ offset
);
176 static void hw_writel(struct macb
*bp
, int offset
, u32 value
)
178 writel_relaxed(value
, bp
->regs
+ offset
);
181 /* Find the CPU endianness by using the loopback bit of NCR register. When the
182 * CPU is in big endian we need to program swapped mode for management
185 static bool hw_is_native_io(void __iomem
*addr
)
187 u32 value
= MACB_BIT(LLB
);
189 __raw_writel(value
, addr
+ MACB_NCR
);
190 value
= __raw_readl(addr
+ MACB_NCR
);
192 /* Write 0 back to disable everything */
193 __raw_writel(0, addr
+ MACB_NCR
);
195 return value
== MACB_BIT(LLB
);
198 static bool hw_is_gem(void __iomem
*addr
, bool native_io
)
203 id
= __raw_readl(addr
+ MACB_MID
);
205 id
= readl_relaxed(addr
+ MACB_MID
);
207 return MACB_BFEXT(IDNUM
, id
) >= 0x2;
210 static void macb_set_hwaddr(struct macb
*bp
)
215 bottom
= cpu_to_le32(*((u32
*)bp
->dev
->dev_addr
));
216 macb_or_gem_writel(bp
, SA1B
, bottom
);
217 top
= cpu_to_le16(*((u16
*)(bp
->dev
->dev_addr
+ 4)));
218 macb_or_gem_writel(bp
, SA1T
, top
);
220 /* Clear unused address register sets */
221 macb_or_gem_writel(bp
, SA2B
, 0);
222 macb_or_gem_writel(bp
, SA2T
, 0);
223 macb_or_gem_writel(bp
, SA3B
, 0);
224 macb_or_gem_writel(bp
, SA3T
, 0);
225 macb_or_gem_writel(bp
, SA4B
, 0);
226 macb_or_gem_writel(bp
, SA4T
, 0);
229 static void macb_get_hwaddr(struct macb
*bp
)
231 struct macb_platform_data
*pdata
;
237 pdata
= dev_get_platdata(&bp
->pdev
->dev
);
239 /* Check all 4 address register for valid address */
240 for (i
= 0; i
< 4; i
++) {
241 bottom
= macb_or_gem_readl(bp
, SA1B
+ i
* 8);
242 top
= macb_or_gem_readl(bp
, SA1T
+ i
* 8);
244 if (pdata
&& pdata
->rev_eth_addr
) {
245 addr
[5] = bottom
& 0xff;
246 addr
[4] = (bottom
>> 8) & 0xff;
247 addr
[3] = (bottom
>> 16) & 0xff;
248 addr
[2] = (bottom
>> 24) & 0xff;
249 addr
[1] = top
& 0xff;
250 addr
[0] = (top
& 0xff00) >> 8;
252 addr
[0] = bottom
& 0xff;
253 addr
[1] = (bottom
>> 8) & 0xff;
254 addr
[2] = (bottom
>> 16) & 0xff;
255 addr
[3] = (bottom
>> 24) & 0xff;
256 addr
[4] = top
& 0xff;
257 addr
[5] = (top
>> 8) & 0xff;
260 if (is_valid_ether_addr(addr
)) {
261 memcpy(bp
->dev
->dev_addr
, addr
, sizeof(addr
));
266 dev_info(&bp
->pdev
->dev
, "invalid hw address, using random\n");
267 eth_hw_addr_random(bp
->dev
);
270 static int macb_mdio_read(struct mii_bus
*bus
, int mii_id
, int regnum
)
272 struct macb
*bp
= bus
->priv
;
275 macb_writel(bp
, MAN
, (MACB_BF(SOF
, MACB_MAN_SOF
)
276 | MACB_BF(RW
, MACB_MAN_READ
)
277 | MACB_BF(PHYA
, mii_id
)
278 | MACB_BF(REGA
, regnum
)
279 | MACB_BF(CODE
, MACB_MAN_CODE
)));
281 /* wait for end of transfer */
282 while (!MACB_BFEXT(IDLE
, macb_readl(bp
, NSR
)))
285 value
= MACB_BFEXT(DATA
, macb_readl(bp
, MAN
));
290 static int macb_mdio_write(struct mii_bus
*bus
, int mii_id
, int regnum
,
293 struct macb
*bp
= bus
->priv
;
295 macb_writel(bp
, MAN
, (MACB_BF(SOF
, MACB_MAN_SOF
)
296 | MACB_BF(RW
, MACB_MAN_WRITE
)
297 | MACB_BF(PHYA
, mii_id
)
298 | MACB_BF(REGA
, regnum
)
299 | MACB_BF(CODE
, MACB_MAN_CODE
)
300 | MACB_BF(DATA
, value
)));
302 /* wait for end of transfer */
303 while (!MACB_BFEXT(IDLE
, macb_readl(bp
, NSR
)))
310 * macb_set_tx_clk() - Set a clock to a new frequency
311 * @clk Pointer to the clock to change
312 * @rate New frequency in Hz
313 * @dev Pointer to the struct net_device
315 static void macb_set_tx_clk(struct clk
*clk
, int speed
, struct net_device
*dev
)
317 long ferr
, rate
, rate_rounded
;
336 rate_rounded
= clk_round_rate(clk
, rate
);
337 if (rate_rounded
< 0)
340 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
343 ferr
= abs(rate_rounded
- rate
);
344 ferr
= DIV_ROUND_UP(ferr
, rate
/ 100000);
346 netdev_warn(dev
, "unable to generate target frequency: %ld Hz\n",
349 if (clk_set_rate(clk
, rate_rounded
))
350 netdev_err(dev
, "adjusting tx_clk failed.\n");
353 static void macb_handle_link_change(struct net_device
*dev
)
355 struct macb
*bp
= netdev_priv(dev
);
356 struct phy_device
*phydev
= dev
->phydev
;
358 int status_change
= 0;
360 spin_lock_irqsave(&bp
->lock
, flags
);
363 if ((bp
->speed
!= phydev
->speed
) ||
364 (bp
->duplex
!= phydev
->duplex
)) {
367 reg
= macb_readl(bp
, NCFGR
);
368 reg
&= ~(MACB_BIT(SPD
) | MACB_BIT(FD
));
370 reg
&= ~GEM_BIT(GBE
);
374 if (phydev
->speed
== SPEED_100
)
375 reg
|= MACB_BIT(SPD
);
376 if (phydev
->speed
== SPEED_1000
&&
377 bp
->caps
& MACB_CAPS_GIGABIT_MODE_AVAILABLE
)
380 macb_or_gem_writel(bp
, NCFGR
, reg
);
382 bp
->speed
= phydev
->speed
;
383 bp
->duplex
= phydev
->duplex
;
388 if (phydev
->link
!= bp
->link
) {
393 bp
->link
= phydev
->link
;
398 spin_unlock_irqrestore(&bp
->lock
, flags
);
402 /* Update the TX clock rate if and only if the link is
403 * up and there has been a link change.
405 macb_set_tx_clk(bp
->tx_clk
, phydev
->speed
, dev
);
407 netif_carrier_on(dev
);
408 netdev_info(dev
, "link up (%d/%s)\n",
410 phydev
->duplex
== DUPLEX_FULL
?
413 netif_carrier_off(dev
);
414 netdev_info(dev
, "link down\n");
419 /* based on au1000_eth. c*/
420 static int macb_mii_probe(struct net_device
*dev
)
422 struct macb
*bp
= netdev_priv(dev
);
423 struct macb_platform_data
*pdata
;
424 struct phy_device
*phydev
;
428 phydev
= phy_find_first(bp
->mii_bus
);
430 netdev_err(dev
, "no PHY found\n");
434 pdata
= dev_get_platdata(&bp
->pdev
->dev
);
435 if (pdata
&& gpio_is_valid(pdata
->phy_irq_pin
)) {
436 ret
= devm_gpio_request(&bp
->pdev
->dev
, pdata
->phy_irq_pin
,
439 phy_irq
= gpio_to_irq(pdata
->phy_irq_pin
);
440 phydev
->irq
= (phy_irq
< 0) ? PHY_POLL
: phy_irq
;
443 phydev
->irq
= PHY_POLL
;
446 /* attach the mac to the phy */
447 ret
= phy_connect_direct(dev
, phydev
, &macb_handle_link_change
,
450 netdev_err(dev
, "Could not attach to PHY\n");
454 /* mask with MAC supported features */
455 if (macb_is_gem(bp
) && bp
->caps
& MACB_CAPS_GIGABIT_MODE_AVAILABLE
)
456 phydev
->supported
&= PHY_GBIT_FEATURES
;
458 phydev
->supported
&= PHY_BASIC_FEATURES
;
460 if (bp
->caps
& MACB_CAPS_NO_GIGABIT_HALF
)
461 phydev
->supported
&= ~SUPPORTED_1000baseT_Half
;
463 phydev
->advertising
= phydev
->supported
;
472 static int macb_mii_init(struct macb
*bp
)
474 struct macb_platform_data
*pdata
;
475 struct device_node
*np
;
478 /* Enable management port */
479 macb_writel(bp
, NCR
, MACB_BIT(MPE
));
481 bp
->mii_bus
= mdiobus_alloc();
487 bp
->mii_bus
->name
= "MACB_mii_bus";
488 bp
->mii_bus
->read
= &macb_mdio_read
;
489 bp
->mii_bus
->write
= &macb_mdio_write
;
490 snprintf(bp
->mii_bus
->id
, MII_BUS_ID_SIZE
, "%s-%x",
491 bp
->pdev
->name
, bp
->pdev
->id
);
492 bp
->mii_bus
->priv
= bp
;
493 bp
->mii_bus
->parent
= &bp
->pdev
->dev
;
494 pdata
= dev_get_platdata(&bp
->pdev
->dev
);
496 dev_set_drvdata(&bp
->dev
->dev
, bp
->mii_bus
);
498 np
= bp
->pdev
->dev
.of_node
;
500 /* try dt phy registration */
501 err
= of_mdiobus_register(bp
->mii_bus
, np
);
503 /* fallback to standard phy registration if no phy were
504 * found during dt phy registration
506 if (!err
&& !phy_find_first(bp
->mii_bus
)) {
507 for (i
= 0; i
< PHY_MAX_ADDR
; i
++) {
508 struct phy_device
*phydev
;
510 phydev
= mdiobus_scan(bp
->mii_bus
, i
);
511 if (IS_ERR(phydev
) &&
512 PTR_ERR(phydev
) != -ENODEV
) {
513 err
= PTR_ERR(phydev
);
519 goto err_out_unregister_bus
;
522 for (i
= 0; i
< PHY_MAX_ADDR
; i
++)
523 bp
->mii_bus
->irq
[i
] = PHY_POLL
;
526 bp
->mii_bus
->phy_mask
= pdata
->phy_mask
;
528 err
= mdiobus_register(bp
->mii_bus
);
532 goto err_out_free_mdiobus
;
534 err
= macb_mii_probe(bp
->dev
);
536 goto err_out_unregister_bus
;
540 err_out_unregister_bus
:
541 mdiobus_unregister(bp
->mii_bus
);
542 err_out_free_mdiobus
:
543 mdiobus_free(bp
->mii_bus
);
548 static void macb_update_stats(struct macb
*bp
)
550 u32
*p
= &bp
->hw_stats
.macb
.rx_pause_frames
;
551 u32
*end
= &bp
->hw_stats
.macb
.tx_pause_frames
+ 1;
552 int offset
= MACB_PFR
;
554 WARN_ON((unsigned long)(end
- p
- 1) != (MACB_TPF
- MACB_PFR
) / 4);
556 for (; p
< end
; p
++, offset
+= 4)
557 *p
+= bp
->macb_reg_readl(bp
, offset
);
560 static int macb_halt_tx(struct macb
*bp
)
562 unsigned long halt_time
, timeout
;
565 macb_writel(bp
, NCR
, macb_readl(bp
, NCR
) | MACB_BIT(THALT
));
567 timeout
= jiffies
+ usecs_to_jiffies(MACB_HALT_TIMEOUT
);
570 status
= macb_readl(bp
, TSR
);
571 if (!(status
& MACB_BIT(TGO
)))
574 usleep_range(10, 250);
575 } while (time_before(halt_time
, timeout
));
580 static void macb_tx_unmap(struct macb
*bp
, struct macb_tx_skb
*tx_skb
)
582 if (tx_skb
->mapping
) {
583 if (tx_skb
->mapped_as_page
)
584 dma_unmap_page(&bp
->pdev
->dev
, tx_skb
->mapping
,
585 tx_skb
->size
, DMA_TO_DEVICE
);
587 dma_unmap_single(&bp
->pdev
->dev
, tx_skb
->mapping
,
588 tx_skb
->size
, DMA_TO_DEVICE
);
593 dev_kfree_skb_any(tx_skb
->skb
);
598 static void macb_set_addr(struct macb
*bp
, struct macb_dma_desc
*desc
, dma_addr_t addr
)
600 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
601 struct macb_dma_desc_64
*desc_64
;
603 if (bp
->hw_dma_cap
== HW_DMA_CAP_64B
) {
604 desc_64
= macb_64b_desc(bp
, desc
);
605 desc_64
->addrh
= upper_32_bits(addr
);
608 desc
->addr
= lower_32_bits(addr
);
611 static dma_addr_t
macb_get_addr(struct macb
*bp
, struct macb_dma_desc
*desc
)
614 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
615 struct macb_dma_desc_64
*desc_64
;
617 if (bp
->hw_dma_cap
== HW_DMA_CAP_64B
) {
618 desc_64
= macb_64b_desc(bp
, desc
);
619 addr
= ((u64
)(desc_64
->addrh
) << 32);
622 addr
|= MACB_BF(RX_WADDR
, MACB_BFEXT(RX_WADDR
, desc
->addr
));
626 static void macb_tx_error_task(struct work_struct
*work
)
628 struct macb_queue
*queue
= container_of(work
, struct macb_queue
,
630 struct macb
*bp
= queue
->bp
;
631 struct macb_tx_skb
*tx_skb
;
632 struct macb_dma_desc
*desc
;
637 netdev_vdbg(bp
->dev
, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
638 (unsigned int)(queue
- bp
->queues
),
639 queue
->tx_tail
, queue
->tx_head
);
641 /* Prevent the queue IRQ handlers from running: each of them may call
642 * macb_tx_interrupt(), which in turn may call netif_wake_subqueue().
643 * As explained below, we have to halt the transmission before updating
644 * TBQP registers so we call netif_tx_stop_all_queues() to notify the
645 * network engine about the macb/gem being halted.
647 spin_lock_irqsave(&bp
->lock
, flags
);
649 /* Make sure nobody is trying to queue up new packets */
650 netif_tx_stop_all_queues(bp
->dev
);
652 /* Stop transmission now
653 * (in case we have just queued new packets)
654 * macb/gem must be halted to write TBQP register
656 if (macb_halt_tx(bp
))
657 /* Just complain for now, reinitializing TX path can be good */
658 netdev_err(bp
->dev
, "BUG: halt tx timed out\n");
660 /* Treat frames in TX queue including the ones that caused the error.
661 * Free transmit buffers in upper layer.
663 for (tail
= queue
->tx_tail
; tail
!= queue
->tx_head
; tail
++) {
666 desc
= macb_tx_desc(queue
, tail
);
668 tx_skb
= macb_tx_skb(queue
, tail
);
671 if (ctrl
& MACB_BIT(TX_USED
)) {
672 /* skb is set for the last buffer of the frame */
674 macb_tx_unmap(bp
, tx_skb
);
676 tx_skb
= macb_tx_skb(queue
, tail
);
680 /* ctrl still refers to the first buffer descriptor
681 * since it's the only one written back by the hardware
683 if (!(ctrl
& MACB_BIT(TX_BUF_EXHAUSTED
))) {
684 netdev_vdbg(bp
->dev
, "txerr skb %u (data %p) TX complete\n",
685 macb_tx_ring_wrap(bp
, tail
),
687 bp
->stats
.tx_packets
++;
688 bp
->stats
.tx_bytes
+= skb
->len
;
691 /* "Buffers exhausted mid-frame" errors may only happen
692 * if the driver is buggy, so complain loudly about
693 * those. Statistics are updated by hardware.
695 if (ctrl
& MACB_BIT(TX_BUF_EXHAUSTED
))
697 "BUG: TX buffers exhausted mid-frame\n");
699 desc
->ctrl
= ctrl
| MACB_BIT(TX_USED
);
702 macb_tx_unmap(bp
, tx_skb
);
705 /* Set end of TX queue */
706 desc
= macb_tx_desc(queue
, 0);
707 macb_set_addr(bp
, desc
, 0);
708 desc
->ctrl
= MACB_BIT(TX_USED
);
710 /* Make descriptor updates visible to hardware */
713 /* Reinitialize the TX desc queue */
714 queue_writel(queue
, TBQP
, lower_32_bits(queue
->tx_ring_dma
));
715 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
716 if (bp
->hw_dma_cap
== HW_DMA_CAP_64B
)
717 queue_writel(queue
, TBQPH
, upper_32_bits(queue
->tx_ring_dma
));
719 /* Make TX ring reflect state of hardware */
723 /* Housework before enabling TX IRQ */
724 macb_writel(bp
, TSR
, macb_readl(bp
, TSR
));
725 queue_writel(queue
, IER
, MACB_TX_INT_FLAGS
);
727 /* Now we are ready to start transmission again */
728 netif_tx_start_all_queues(bp
->dev
);
729 macb_writel(bp
, NCR
, macb_readl(bp
, NCR
) | MACB_BIT(TSTART
));
731 spin_unlock_irqrestore(&bp
->lock
, flags
);
734 static void macb_tx_interrupt(struct macb_queue
*queue
)
739 struct macb
*bp
= queue
->bp
;
740 u16 queue_index
= queue
- bp
->queues
;
742 status
= macb_readl(bp
, TSR
);
743 macb_writel(bp
, TSR
, status
);
745 if (bp
->caps
& MACB_CAPS_ISR_CLEAR_ON_WRITE
)
746 queue_writel(queue
, ISR
, MACB_BIT(TCOMP
));
748 netdev_vdbg(bp
->dev
, "macb_tx_interrupt status = 0x%03lx\n",
749 (unsigned long)status
);
751 head
= queue
->tx_head
;
752 for (tail
= queue
->tx_tail
; tail
!= head
; tail
++) {
753 struct macb_tx_skb
*tx_skb
;
755 struct macb_dma_desc
*desc
;
758 desc
= macb_tx_desc(queue
, tail
);
760 /* Make hw descriptor updates visible to CPU */
765 /* TX_USED bit is only set by hardware on the very first buffer
766 * descriptor of the transmitted frame.
768 if (!(ctrl
& MACB_BIT(TX_USED
)))
771 /* Process all buffers of the current transmitted frame */
773 tx_skb
= macb_tx_skb(queue
, tail
);
776 /* First, update TX stats if needed */
778 netdev_vdbg(bp
->dev
, "skb %u (data %p) TX complete\n",
779 macb_tx_ring_wrap(bp
, tail
),
781 bp
->stats
.tx_packets
++;
782 bp
->stats
.tx_bytes
+= skb
->len
;
785 /* Now we can safely release resources */
786 macb_tx_unmap(bp
, tx_skb
);
788 /* skb is set only for the last buffer of the frame.
789 * WARNING: at this point skb has been freed by
797 queue
->tx_tail
= tail
;
798 if (__netif_subqueue_stopped(bp
->dev
, queue_index
) &&
799 CIRC_CNT(queue
->tx_head
, queue
->tx_tail
,
800 bp
->tx_ring_size
) <= MACB_TX_WAKEUP_THRESH(bp
))
801 netif_wake_subqueue(bp
->dev
, queue_index
);
804 static void gem_rx_refill(struct macb
*bp
)
809 struct macb_dma_desc
*desc
;
811 while (CIRC_SPACE(bp
->rx_prepared_head
, bp
->rx_tail
,
812 bp
->rx_ring_size
) > 0) {
813 entry
= macb_rx_ring_wrap(bp
, bp
->rx_prepared_head
);
815 /* Make hw descriptor updates visible to CPU */
818 bp
->rx_prepared_head
++;
819 desc
= macb_rx_desc(bp
, entry
);
821 if (!bp
->rx_skbuff
[entry
]) {
822 /* allocate sk_buff for this free entry in ring */
823 skb
= netdev_alloc_skb(bp
->dev
, bp
->rx_buffer_size
);
824 if (unlikely(!skb
)) {
826 "Unable to allocate sk_buff\n");
830 /* now fill corresponding descriptor entry */
831 paddr
= dma_map_single(&bp
->pdev
->dev
, skb
->data
,
834 if (dma_mapping_error(&bp
->pdev
->dev
, paddr
)) {
839 bp
->rx_skbuff
[entry
] = skb
;
841 if (entry
== bp
->rx_ring_size
- 1)
842 paddr
|= MACB_BIT(RX_WRAP
);
843 macb_set_addr(bp
, desc
, paddr
);
846 /* properly align Ethernet header */
847 skb_reserve(skb
, NET_IP_ALIGN
);
849 desc
->addr
&= ~MACB_BIT(RX_USED
);
854 /* Make descriptor updates visible to hardware */
857 netdev_vdbg(bp
->dev
, "rx ring: prepared head %d, tail %d\n",
858 bp
->rx_prepared_head
, bp
->rx_tail
);
861 /* Mark DMA descriptors from begin up to and not including end as unused */
862 static void discard_partial_frame(struct macb
*bp
, unsigned int begin
,
867 for (frag
= begin
; frag
!= end
; frag
++) {
868 struct macb_dma_desc
*desc
= macb_rx_desc(bp
, frag
);
870 desc
->addr
&= ~MACB_BIT(RX_USED
);
873 /* Make descriptor updates visible to hardware */
876 /* When this happens, the hardware stats registers for
877 * whatever caused this is updated, so we don't have to record
882 static int gem_rx(struct macb
*bp
, int budget
)
887 struct macb_dma_desc
*desc
;
890 while (count
< budget
) {
895 entry
= macb_rx_ring_wrap(bp
, bp
->rx_tail
);
896 desc
= macb_rx_desc(bp
, entry
);
898 /* Make hw descriptor updates visible to CPU */
901 rxused
= (desc
->addr
& MACB_BIT(RX_USED
)) ? true : false;
902 addr
= macb_get_addr(bp
, desc
);
911 if (!(ctrl
& MACB_BIT(RX_SOF
) && ctrl
& MACB_BIT(RX_EOF
))) {
913 "not whole frame pointed by descriptor\n");
914 bp
->stats
.rx_dropped
++;
917 skb
= bp
->rx_skbuff
[entry
];
918 if (unlikely(!skb
)) {
920 "inconsistent Rx descriptor chain\n");
921 bp
->stats
.rx_dropped
++;
924 /* now everything is ready for receiving packet */
925 bp
->rx_skbuff
[entry
] = NULL
;
926 len
= ctrl
& bp
->rx_frm_len_mask
;
928 netdev_vdbg(bp
->dev
, "gem_rx %u (len %u)\n", entry
, len
);
931 dma_unmap_single(&bp
->pdev
->dev
, addr
,
932 bp
->rx_buffer_size
, DMA_FROM_DEVICE
);
934 skb
->protocol
= eth_type_trans(skb
, bp
->dev
);
935 skb_checksum_none_assert(skb
);
936 if (bp
->dev
->features
& NETIF_F_RXCSUM
&&
937 !(bp
->dev
->flags
& IFF_PROMISC
) &&
938 GEM_BFEXT(RX_CSUM
, ctrl
) & GEM_RX_CSUM_CHECKED_MASK
)
939 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
941 bp
->stats
.rx_packets
++;
942 bp
->stats
.rx_bytes
+= skb
->len
;
944 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
945 netdev_vdbg(bp
->dev
, "received skb of length %u, csum: %08x\n",
946 skb
->len
, skb
->csum
);
947 print_hex_dump(KERN_DEBUG
, " mac: ", DUMP_PREFIX_ADDRESS
, 16, 1,
948 skb_mac_header(skb
), 16, true);
949 print_hex_dump(KERN_DEBUG
, "data: ", DUMP_PREFIX_ADDRESS
, 16, 1,
950 skb
->data
, 32, true);
953 netif_receive_skb(skb
);
961 static int macb_rx_frame(struct macb
*bp
, unsigned int first_frag
,
962 unsigned int last_frag
)
968 struct macb_dma_desc
*desc
;
970 desc
= macb_rx_desc(bp
, last_frag
);
971 len
= desc
->ctrl
& bp
->rx_frm_len_mask
;
973 netdev_vdbg(bp
->dev
, "macb_rx_frame frags %u - %u (len %u)\n",
974 macb_rx_ring_wrap(bp
, first_frag
),
975 macb_rx_ring_wrap(bp
, last_frag
), len
);
977 /* The ethernet header starts NET_IP_ALIGN bytes into the
978 * first buffer. Since the header is 14 bytes, this makes the
979 * payload word-aligned.
981 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
982 * the two padding bytes into the skb so that we avoid hitting
983 * the slowpath in memcpy(), and pull them off afterwards.
985 skb
= netdev_alloc_skb(bp
->dev
, len
+ NET_IP_ALIGN
);
987 bp
->stats
.rx_dropped
++;
988 for (frag
= first_frag
; ; frag
++) {
989 desc
= macb_rx_desc(bp
, frag
);
990 desc
->addr
&= ~MACB_BIT(RX_USED
);
991 if (frag
== last_frag
)
995 /* Make descriptor updates visible to hardware */
1002 len
+= NET_IP_ALIGN
;
1003 skb_checksum_none_assert(skb
);
1006 for (frag
= first_frag
; ; frag
++) {
1007 unsigned int frag_len
= bp
->rx_buffer_size
;
1009 if (offset
+ frag_len
> len
) {
1010 if (unlikely(frag
!= last_frag
)) {
1011 dev_kfree_skb_any(skb
);
1014 frag_len
= len
- offset
;
1016 skb_copy_to_linear_data_offset(skb
, offset
,
1017 macb_rx_buffer(bp
, frag
),
1019 offset
+= bp
->rx_buffer_size
;
1020 desc
= macb_rx_desc(bp
, frag
);
1021 desc
->addr
&= ~MACB_BIT(RX_USED
);
1023 if (frag
== last_frag
)
1027 /* Make descriptor updates visible to hardware */
1030 __skb_pull(skb
, NET_IP_ALIGN
);
1031 skb
->protocol
= eth_type_trans(skb
, bp
->dev
);
1033 bp
->stats
.rx_packets
++;
1034 bp
->stats
.rx_bytes
+= skb
->len
;
1035 netdev_vdbg(bp
->dev
, "received skb of length %u, csum: %08x\n",
1036 skb
->len
, skb
->csum
);
1037 netif_receive_skb(skb
);
1042 static inline void macb_init_rx_ring(struct macb
*bp
)
1045 struct macb_dma_desc
*desc
= NULL
;
1048 addr
= bp
->rx_buffers_dma
;
1049 for (i
= 0; i
< bp
->rx_ring_size
; i
++) {
1050 desc
= macb_rx_desc(bp
, i
);
1051 macb_set_addr(bp
, desc
, addr
);
1053 addr
+= bp
->rx_buffer_size
;
1055 desc
->addr
|= MACB_BIT(RX_WRAP
);
1059 static int macb_rx(struct macb
*bp
, int budget
)
1061 bool reset_rx_queue
= false;
1064 int first_frag
= -1;
1066 for (tail
= bp
->rx_tail
; budget
> 0; tail
++) {
1067 struct macb_dma_desc
*desc
= macb_rx_desc(bp
, tail
);
1070 /* Make hw descriptor updates visible to CPU */
1075 if (!(desc
->addr
& MACB_BIT(RX_USED
)))
1078 if (ctrl
& MACB_BIT(RX_SOF
)) {
1079 if (first_frag
!= -1)
1080 discard_partial_frame(bp
, first_frag
, tail
);
1084 if (ctrl
& MACB_BIT(RX_EOF
)) {
1087 if (unlikely(first_frag
== -1)) {
1088 reset_rx_queue
= true;
1092 dropped
= macb_rx_frame(bp
, first_frag
, tail
);
1094 if (unlikely(dropped
< 0)) {
1095 reset_rx_queue
= true;
1105 if (unlikely(reset_rx_queue
)) {
1106 unsigned long flags
;
1109 netdev_err(bp
->dev
, "RX queue corruption: reset it\n");
1111 spin_lock_irqsave(&bp
->lock
, flags
);
1113 ctrl
= macb_readl(bp
, NCR
);
1114 macb_writel(bp
, NCR
, ctrl
& ~MACB_BIT(RE
));
1116 macb_init_rx_ring(bp
);
1117 macb_writel(bp
, RBQP
, bp
->rx_ring_dma
);
1119 macb_writel(bp
, NCR
, ctrl
| MACB_BIT(RE
));
1121 spin_unlock_irqrestore(&bp
->lock
, flags
);
1125 if (first_frag
!= -1)
1126 bp
->rx_tail
= first_frag
;
1133 static int macb_poll(struct napi_struct
*napi
, int budget
)
1135 struct macb
*bp
= container_of(napi
, struct macb
, napi
);
1139 status
= macb_readl(bp
, RSR
);
1140 macb_writel(bp
, RSR
, status
);
1144 netdev_vdbg(bp
->dev
, "poll: status = %08lx, budget = %d\n",
1145 (unsigned long)status
, budget
);
1147 work_done
= bp
->macbgem_ops
.mog_rx(bp
, budget
);
1148 if (work_done
< budget
) {
1149 napi_complete_done(napi
, work_done
);
1151 /* Packets received while interrupts were disabled */
1152 status
= macb_readl(bp
, RSR
);
1154 if (bp
->caps
& MACB_CAPS_ISR_CLEAR_ON_WRITE
)
1155 macb_writel(bp
, ISR
, MACB_BIT(RCOMP
));
1156 napi_reschedule(napi
);
1158 macb_writel(bp
, IER
, MACB_RX_INT_FLAGS
);
1162 /* TODO: Handle errors */
1167 static irqreturn_t
macb_interrupt(int irq
, void *dev_id
)
1169 struct macb_queue
*queue
= dev_id
;
1170 struct macb
*bp
= queue
->bp
;
1171 struct net_device
*dev
= bp
->dev
;
1174 status
= queue_readl(queue
, ISR
);
1176 if (unlikely(!status
))
1179 spin_lock(&bp
->lock
);
1182 /* close possible race with dev_close */
1183 if (unlikely(!netif_running(dev
))) {
1184 queue_writel(queue
, IDR
, -1);
1185 if (bp
->caps
& MACB_CAPS_ISR_CLEAR_ON_WRITE
)
1186 queue_writel(queue
, ISR
, -1);
1190 netdev_vdbg(bp
->dev
, "queue = %u, isr = 0x%08lx\n",
1191 (unsigned int)(queue
- bp
->queues
),
1192 (unsigned long)status
);
1194 if (status
& MACB_RX_INT_FLAGS
) {
1195 /* There's no point taking any more interrupts
1196 * until we have processed the buffers. The
1197 * scheduling call may fail if the poll routine
1198 * is already scheduled, so disable interrupts
1201 queue_writel(queue
, IDR
, MACB_RX_INT_FLAGS
);
1202 if (bp
->caps
& MACB_CAPS_ISR_CLEAR_ON_WRITE
)
1203 queue_writel(queue
, ISR
, MACB_BIT(RCOMP
));
1205 if (napi_schedule_prep(&bp
->napi
)) {
1206 netdev_vdbg(bp
->dev
, "scheduling RX softirq\n");
1207 __napi_schedule(&bp
->napi
);
1211 if (unlikely(status
& (MACB_TX_ERR_FLAGS
))) {
1212 queue_writel(queue
, IDR
, MACB_TX_INT_FLAGS
);
1213 schedule_work(&queue
->tx_error_task
);
1215 if (bp
->caps
& MACB_CAPS_ISR_CLEAR_ON_WRITE
)
1216 queue_writel(queue
, ISR
, MACB_TX_ERR_FLAGS
);
1221 if (status
& MACB_BIT(TCOMP
))
1222 macb_tx_interrupt(queue
);
1224 /* Link change detection isn't possible with RMII, so we'll
1225 * add that if/when we get our hands on a full-blown MII PHY.
1228 /* There is a hardware issue under heavy load where DMA can
1229 * stop, this causes endless "used buffer descriptor read"
1230 * interrupts but it can be cleared by re-enabling RX. See
1231 * the at91 manual, section 41.3.1 or the Zynq manual
1232 * section 16.7.4 for details.
1234 if (status
& MACB_BIT(RXUBR
)) {
1235 ctrl
= macb_readl(bp
, NCR
);
1236 macb_writel(bp
, NCR
, ctrl
& ~MACB_BIT(RE
));
1238 macb_writel(bp
, NCR
, ctrl
| MACB_BIT(RE
));
1240 if (bp
->caps
& MACB_CAPS_ISR_CLEAR_ON_WRITE
)
1241 queue_writel(queue
, ISR
, MACB_BIT(RXUBR
));
1244 if (status
& MACB_BIT(ISR_ROVR
)) {
1245 /* We missed at least one packet */
1246 if (macb_is_gem(bp
))
1247 bp
->hw_stats
.gem
.rx_overruns
++;
1249 bp
->hw_stats
.macb
.rx_overruns
++;
1251 if (bp
->caps
& MACB_CAPS_ISR_CLEAR_ON_WRITE
)
1252 queue_writel(queue
, ISR
, MACB_BIT(ISR_ROVR
));
1255 if (status
& MACB_BIT(HRESP
)) {
1256 /* TODO: Reset the hardware, and maybe move the
1257 * netdev_err to a lower-priority context as well
1260 netdev_err(dev
, "DMA bus error: HRESP not OK\n");
1262 if (bp
->caps
& MACB_CAPS_ISR_CLEAR_ON_WRITE
)
1263 queue_writel(queue
, ISR
, MACB_BIT(HRESP
));
1266 status
= queue_readl(queue
, ISR
);
1269 spin_unlock(&bp
->lock
);
1274 #ifdef CONFIG_NET_POLL_CONTROLLER
1275 /* Polling receive - used by netconsole and other diagnostic tools
1276 * to allow network i/o with interrupts disabled.
1278 static void macb_poll_controller(struct net_device
*dev
)
1280 struct macb
*bp
= netdev_priv(dev
);
1281 struct macb_queue
*queue
;
1282 unsigned long flags
;
1285 local_irq_save(flags
);
1286 for (q
= 0, queue
= bp
->queues
; q
< bp
->num_queues
; ++q
, ++queue
)
1287 macb_interrupt(dev
->irq
, queue
);
1288 local_irq_restore(flags
);
1292 static unsigned int macb_tx_map(struct macb
*bp
,
1293 struct macb_queue
*queue
,
1294 struct sk_buff
*skb
,
1295 unsigned int hdrlen
)
1298 unsigned int len
, entry
, i
, tx_head
= queue
->tx_head
;
1299 struct macb_tx_skb
*tx_skb
= NULL
;
1300 struct macb_dma_desc
*desc
;
1301 unsigned int offset
, size
, count
= 0;
1302 unsigned int f
, nr_frags
= skb_shinfo(skb
)->nr_frags
;
1303 unsigned int eof
= 1, mss_mfs
= 0;
1304 u32 ctrl
, lso_ctrl
= 0, seq_ctrl
= 0;
1307 if (skb_shinfo(skb
)->gso_size
!= 0) {
1308 if (ip_hdr(skb
)->protocol
== IPPROTO_UDP
)
1310 lso_ctrl
= MACB_LSO_UFO_ENABLE
;
1313 lso_ctrl
= MACB_LSO_TSO_ENABLE
;
1316 /* First, map non-paged data */
1317 len
= skb_headlen(skb
);
1319 /* first buffer length */
1324 entry
= macb_tx_ring_wrap(bp
, tx_head
);
1325 tx_skb
= &queue
->tx_skb
[entry
];
1327 mapping
= dma_map_single(&bp
->pdev
->dev
,
1329 size
, DMA_TO_DEVICE
);
1330 if (dma_mapping_error(&bp
->pdev
->dev
, mapping
))
1333 /* Save info to properly release resources */
1335 tx_skb
->mapping
= mapping
;
1336 tx_skb
->size
= size
;
1337 tx_skb
->mapped_as_page
= false;
1344 size
= min(len
, bp
->max_tx_length
);
1347 /* Then, map paged data from fragments */
1348 for (f
= 0; f
< nr_frags
; f
++) {
1349 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[f
];
1351 len
= skb_frag_size(frag
);
1354 size
= min(len
, bp
->max_tx_length
);
1355 entry
= macb_tx_ring_wrap(bp
, tx_head
);
1356 tx_skb
= &queue
->tx_skb
[entry
];
1358 mapping
= skb_frag_dma_map(&bp
->pdev
->dev
, frag
,
1359 offset
, size
, DMA_TO_DEVICE
);
1360 if (dma_mapping_error(&bp
->pdev
->dev
, mapping
))
1363 /* Save info to properly release resources */
1365 tx_skb
->mapping
= mapping
;
1366 tx_skb
->size
= size
;
1367 tx_skb
->mapped_as_page
= true;
1376 /* Should never happen */
1377 if (unlikely(!tx_skb
)) {
1378 netdev_err(bp
->dev
, "BUG! empty skb!\n");
1382 /* This is the last buffer of the frame: save socket buffer */
1385 /* Update TX ring: update buffer descriptors in reverse order
1386 * to avoid race condition
1389 /* Set 'TX_USED' bit in buffer descriptor at tx_head position
1390 * to set the end of TX queue
1393 entry
= macb_tx_ring_wrap(bp
, i
);
1394 ctrl
= MACB_BIT(TX_USED
);
1395 desc
= macb_tx_desc(queue
, entry
);
1399 if (lso_ctrl
== MACB_LSO_UFO_ENABLE
)
1400 /* include header and FCS in value given to h/w */
1401 mss_mfs
= skb_shinfo(skb
)->gso_size
+
1402 skb_transport_offset(skb
) +
1405 mss_mfs
= skb_shinfo(skb
)->gso_size
;
1406 /* TCP Sequence Number Source Select
1407 * can be set only for TSO
1415 entry
= macb_tx_ring_wrap(bp
, i
);
1416 tx_skb
= &queue
->tx_skb
[entry
];
1417 desc
= macb_tx_desc(queue
, entry
);
1419 ctrl
= (u32
)tx_skb
->size
;
1421 ctrl
|= MACB_BIT(TX_LAST
);
1424 if (unlikely(entry
== (bp
->tx_ring_size
- 1)))
1425 ctrl
|= MACB_BIT(TX_WRAP
);
1427 /* First descriptor is header descriptor */
1428 if (i
== queue
->tx_head
) {
1429 ctrl
|= MACB_BF(TX_LSO
, lso_ctrl
);
1430 ctrl
|= MACB_BF(TX_TCP_SEQ_SRC
, seq_ctrl
);
1432 /* Only set MSS/MFS on payload descriptors
1433 * (second or later descriptor)
1435 ctrl
|= MACB_BF(MSS_MFS
, mss_mfs
);
1437 /* Set TX buffer descriptor */
1438 macb_set_addr(bp
, desc
, tx_skb
->mapping
);
1439 /* desc->addr must be visible to hardware before clearing
1440 * 'TX_USED' bit in desc->ctrl.
1444 } while (i
!= queue
->tx_head
);
1446 queue
->tx_head
= tx_head
;
1451 netdev_err(bp
->dev
, "TX DMA map failed\n");
1453 for (i
= queue
->tx_head
; i
!= tx_head
; i
++) {
1454 tx_skb
= macb_tx_skb(queue
, i
);
1456 macb_tx_unmap(bp
, tx_skb
);
1462 static netdev_features_t
macb_features_check(struct sk_buff
*skb
,
1463 struct net_device
*dev
,
1464 netdev_features_t features
)
1466 unsigned int nr_frags
, f
;
1467 unsigned int hdrlen
;
1469 /* Validate LSO compatibility */
1471 /* there is only one buffer */
1472 if (!skb_is_nonlinear(skb
))
1475 /* length of header */
1476 hdrlen
= skb_transport_offset(skb
);
1477 if (ip_hdr(skb
)->protocol
== IPPROTO_TCP
)
1478 hdrlen
+= tcp_hdrlen(skb
);
1481 * When software supplies two or more payload buffers all payload buffers
1482 * apart from the last must be a multiple of 8 bytes in size.
1484 if (!IS_ALIGNED(skb_headlen(skb
) - hdrlen
, MACB_TX_LEN_ALIGN
))
1485 return features
& ~MACB_NETIF_LSO
;
1487 nr_frags
= skb_shinfo(skb
)->nr_frags
;
1488 /* No need to check last fragment */
1490 for (f
= 0; f
< nr_frags
; f
++) {
1491 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[f
];
1493 if (!IS_ALIGNED(skb_frag_size(frag
), MACB_TX_LEN_ALIGN
))
1494 return features
& ~MACB_NETIF_LSO
;
1499 static inline int macb_clear_csum(struct sk_buff
*skb
)
1501 /* no change for packets without checksum offloading */
1502 if (skb
->ip_summed
!= CHECKSUM_PARTIAL
)
1505 /* make sure we can modify the header */
1506 if (unlikely(skb_cow_head(skb
, 0)))
1509 /* initialize checksum field
1510 * This is required - at least for Zynq, which otherwise calculates
1511 * wrong UDP header checksums for UDP packets with UDP data len <=2
1513 *(__sum16
*)(skb_checksum_start(skb
) + skb
->csum_offset
) = 0;
1517 static int macb_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1519 u16 queue_index
= skb_get_queue_mapping(skb
);
1520 struct macb
*bp
= netdev_priv(dev
);
1521 struct macb_queue
*queue
= &bp
->queues
[queue_index
];
1522 unsigned long flags
;
1523 unsigned int desc_cnt
, nr_frags
, frag_size
, f
;
1524 unsigned int hdrlen
;
1525 bool is_lso
, is_udp
= 0;
1527 is_lso
= (skb_shinfo(skb
)->gso_size
!= 0);
1530 is_udp
= !!(ip_hdr(skb
)->protocol
== IPPROTO_UDP
);
1532 /* length of headers */
1534 /* only queue eth + ip headers separately for UDP */
1535 hdrlen
= skb_transport_offset(skb
);
1537 hdrlen
= skb_transport_offset(skb
) + tcp_hdrlen(skb
);
1538 if (skb_headlen(skb
) < hdrlen
) {
1539 netdev_err(bp
->dev
, "Error - LSO headers fragmented!!!\n");
1540 /* if this is required, would need to copy to single buffer */
1541 return NETDEV_TX_BUSY
;
1544 hdrlen
= min(skb_headlen(skb
), bp
->max_tx_length
);
1546 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1547 netdev_vdbg(bp
->dev
,
1548 "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n",
1549 queue_index
, skb
->len
, skb
->head
, skb
->data
,
1550 skb_tail_pointer(skb
), skb_end_pointer(skb
));
1551 print_hex_dump(KERN_DEBUG
, "data: ", DUMP_PREFIX_OFFSET
, 16, 1,
1552 skb
->data
, 16, true);
1555 /* Count how many TX buffer descriptors are needed to send this
1556 * socket buffer: skb fragments of jumbo frames may need to be
1557 * split into many buffer descriptors.
1559 if (is_lso
&& (skb_headlen(skb
) > hdrlen
))
1560 /* extra header descriptor if also payload in first buffer */
1561 desc_cnt
= DIV_ROUND_UP((skb_headlen(skb
) - hdrlen
), bp
->max_tx_length
) + 1;
1563 desc_cnt
= DIV_ROUND_UP(skb_headlen(skb
), bp
->max_tx_length
);
1564 nr_frags
= skb_shinfo(skb
)->nr_frags
;
1565 for (f
= 0; f
< nr_frags
; f
++) {
1566 frag_size
= skb_frag_size(&skb_shinfo(skb
)->frags
[f
]);
1567 desc_cnt
+= DIV_ROUND_UP(frag_size
, bp
->max_tx_length
);
1570 spin_lock_irqsave(&bp
->lock
, flags
);
1572 /* This is a hard error, log it. */
1573 if (CIRC_SPACE(queue
->tx_head
, queue
->tx_tail
,
1574 bp
->tx_ring_size
) < desc_cnt
) {
1575 netif_stop_subqueue(dev
, queue_index
);
1576 spin_unlock_irqrestore(&bp
->lock
, flags
);
1577 netdev_dbg(bp
->dev
, "tx_head = %u, tx_tail = %u\n",
1578 queue
->tx_head
, queue
->tx_tail
);
1579 return NETDEV_TX_BUSY
;
1582 if (macb_clear_csum(skb
)) {
1583 dev_kfree_skb_any(skb
);
1587 /* Map socket buffer for DMA transfer */
1588 if (!macb_tx_map(bp
, queue
, skb
, hdrlen
)) {
1589 dev_kfree_skb_any(skb
);
1593 /* Make newly initialized descriptor visible to hardware */
1596 skb_tx_timestamp(skb
);
1598 macb_writel(bp
, NCR
, macb_readl(bp
, NCR
) | MACB_BIT(TSTART
));
1600 if (CIRC_SPACE(queue
->tx_head
, queue
->tx_tail
, bp
->tx_ring_size
) < 1)
1601 netif_stop_subqueue(dev
, queue_index
);
1604 spin_unlock_irqrestore(&bp
->lock
, flags
);
1606 return NETDEV_TX_OK
;
1609 static void macb_init_rx_buffer_size(struct macb
*bp
, size_t size
)
1611 if (!macb_is_gem(bp
)) {
1612 bp
->rx_buffer_size
= MACB_RX_BUFFER_SIZE
;
1614 bp
->rx_buffer_size
= size
;
1616 if (bp
->rx_buffer_size
% RX_BUFFER_MULTIPLE
) {
1618 "RX buffer must be multiple of %d bytes, expanding\n",
1619 RX_BUFFER_MULTIPLE
);
1620 bp
->rx_buffer_size
=
1621 roundup(bp
->rx_buffer_size
, RX_BUFFER_MULTIPLE
);
1625 netdev_dbg(bp
->dev
, "mtu [%u] rx_buffer_size [%zu]\n",
1626 bp
->dev
->mtu
, bp
->rx_buffer_size
);
1629 static void gem_free_rx_buffers(struct macb
*bp
)
1631 struct sk_buff
*skb
;
1632 struct macb_dma_desc
*desc
;
1639 for (i
= 0; i
< bp
->rx_ring_size
; i
++) {
1640 skb
= bp
->rx_skbuff
[i
];
1645 desc
= macb_rx_desc(bp
, i
);
1646 addr
= macb_get_addr(bp
, desc
);
1648 dma_unmap_single(&bp
->pdev
->dev
, addr
, bp
->rx_buffer_size
,
1650 dev_kfree_skb_any(skb
);
1654 kfree(bp
->rx_skbuff
);
1655 bp
->rx_skbuff
= NULL
;
1658 static void macb_free_rx_buffers(struct macb
*bp
)
1660 if (bp
->rx_buffers
) {
1661 dma_free_coherent(&bp
->pdev
->dev
,
1662 bp
->rx_ring_size
* bp
->rx_buffer_size
,
1663 bp
->rx_buffers
, bp
->rx_buffers_dma
);
1664 bp
->rx_buffers
= NULL
;
1668 static void macb_free_consistent(struct macb
*bp
)
1670 struct macb_queue
*queue
;
1673 bp
->macbgem_ops
.mog_free_rx_buffers(bp
);
1675 dma_free_coherent(&bp
->pdev
->dev
, RX_RING_BYTES(bp
),
1676 bp
->rx_ring
, bp
->rx_ring_dma
);
1680 for (q
= 0, queue
= bp
->queues
; q
< bp
->num_queues
; ++q
, ++queue
) {
1681 kfree(queue
->tx_skb
);
1682 queue
->tx_skb
= NULL
;
1683 if (queue
->tx_ring
) {
1684 dma_free_coherent(&bp
->pdev
->dev
, TX_RING_BYTES(bp
),
1685 queue
->tx_ring
, queue
->tx_ring_dma
);
1686 queue
->tx_ring
= NULL
;
1691 static int gem_alloc_rx_buffers(struct macb
*bp
)
1695 size
= bp
->rx_ring_size
* sizeof(struct sk_buff
*);
1696 bp
->rx_skbuff
= kzalloc(size
, GFP_KERNEL
);
1701 "Allocated %d RX struct sk_buff entries at %p\n",
1702 bp
->rx_ring_size
, bp
->rx_skbuff
);
1706 static int macb_alloc_rx_buffers(struct macb
*bp
)
1710 size
= bp
->rx_ring_size
* bp
->rx_buffer_size
;
1711 bp
->rx_buffers
= dma_alloc_coherent(&bp
->pdev
->dev
, size
,
1712 &bp
->rx_buffers_dma
, GFP_KERNEL
);
1713 if (!bp
->rx_buffers
)
1717 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
1718 size
, (unsigned long)bp
->rx_buffers_dma
, bp
->rx_buffers
);
1722 static int macb_alloc_consistent(struct macb
*bp
)
1724 struct macb_queue
*queue
;
1728 for (q
= 0, queue
= bp
->queues
; q
< bp
->num_queues
; ++q
, ++queue
) {
1729 size
= TX_RING_BYTES(bp
);
1730 queue
->tx_ring
= dma_alloc_coherent(&bp
->pdev
->dev
, size
,
1731 &queue
->tx_ring_dma
,
1733 if (!queue
->tx_ring
)
1736 "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
1737 q
, size
, (unsigned long)queue
->tx_ring_dma
,
1740 size
= bp
->tx_ring_size
* sizeof(struct macb_tx_skb
);
1741 queue
->tx_skb
= kmalloc(size
, GFP_KERNEL
);
1746 size
= RX_RING_BYTES(bp
);
1747 bp
->rx_ring
= dma_alloc_coherent(&bp
->pdev
->dev
, size
,
1748 &bp
->rx_ring_dma
, GFP_KERNEL
);
1752 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
1753 size
, (unsigned long)bp
->rx_ring_dma
, bp
->rx_ring
);
1755 if (bp
->macbgem_ops
.mog_alloc_rx_buffers(bp
))
1761 macb_free_consistent(bp
);
1765 static void gem_init_rings(struct macb
*bp
)
1767 struct macb_queue
*queue
;
1768 struct macb_dma_desc
*desc
= NULL
;
1772 for (q
= 0, queue
= bp
->queues
; q
< bp
->num_queues
; ++q
, ++queue
) {
1773 for (i
= 0; i
< bp
->tx_ring_size
; i
++) {
1774 desc
= macb_tx_desc(queue
, i
);
1775 macb_set_addr(bp
, desc
, 0);
1776 desc
->ctrl
= MACB_BIT(TX_USED
);
1778 desc
->ctrl
|= MACB_BIT(TX_WRAP
);
1784 bp
->rx_prepared_head
= 0;
1789 static void macb_init_rings(struct macb
*bp
)
1792 struct macb_dma_desc
*desc
= NULL
;
1794 macb_init_rx_ring(bp
);
1796 for (i
= 0; i
< bp
->tx_ring_size
; i
++) {
1797 desc
= macb_tx_desc(&bp
->queues
[0], i
);
1798 macb_set_addr(bp
, desc
, 0);
1799 desc
->ctrl
= MACB_BIT(TX_USED
);
1801 bp
->queues
[0].tx_head
= 0;
1802 bp
->queues
[0].tx_tail
= 0;
1803 desc
->ctrl
|= MACB_BIT(TX_WRAP
);
1806 static void macb_reset_hw(struct macb
*bp
)
1808 struct macb_queue
*queue
;
1811 /* Disable RX and TX (XXX: Should we halt the transmission
1814 macb_writel(bp
, NCR
, 0);
1816 /* Clear the stats registers (XXX: Update stats first?) */
1817 macb_writel(bp
, NCR
, MACB_BIT(CLRSTAT
));
1819 /* Clear all status flags */
1820 macb_writel(bp
, TSR
, -1);
1821 macb_writel(bp
, RSR
, -1);
1823 /* Disable all interrupts */
1824 for (q
= 0, queue
= bp
->queues
; q
< bp
->num_queues
; ++q
, ++queue
) {
1825 queue_writel(queue
, IDR
, -1);
1826 queue_readl(queue
, ISR
);
1827 if (bp
->caps
& MACB_CAPS_ISR_CLEAR_ON_WRITE
)
1828 queue_writel(queue
, ISR
, -1);
1832 static u32
gem_mdc_clk_div(struct macb
*bp
)
1835 unsigned long pclk_hz
= clk_get_rate(bp
->pclk
);
1837 if (pclk_hz
<= 20000000)
1838 config
= GEM_BF(CLK
, GEM_CLK_DIV8
);
1839 else if (pclk_hz
<= 40000000)
1840 config
= GEM_BF(CLK
, GEM_CLK_DIV16
);
1841 else if (pclk_hz
<= 80000000)
1842 config
= GEM_BF(CLK
, GEM_CLK_DIV32
);
1843 else if (pclk_hz
<= 120000000)
1844 config
= GEM_BF(CLK
, GEM_CLK_DIV48
);
1845 else if (pclk_hz
<= 160000000)
1846 config
= GEM_BF(CLK
, GEM_CLK_DIV64
);
1848 config
= GEM_BF(CLK
, GEM_CLK_DIV96
);
1853 static u32
macb_mdc_clk_div(struct macb
*bp
)
1856 unsigned long pclk_hz
;
1858 if (macb_is_gem(bp
))
1859 return gem_mdc_clk_div(bp
);
1861 pclk_hz
= clk_get_rate(bp
->pclk
);
1862 if (pclk_hz
<= 20000000)
1863 config
= MACB_BF(CLK
, MACB_CLK_DIV8
);
1864 else if (pclk_hz
<= 40000000)
1865 config
= MACB_BF(CLK
, MACB_CLK_DIV16
);
1866 else if (pclk_hz
<= 80000000)
1867 config
= MACB_BF(CLK
, MACB_CLK_DIV32
);
1869 config
= MACB_BF(CLK
, MACB_CLK_DIV64
);
1874 /* Get the DMA bus width field of the network configuration register that we
1875 * should program. We find the width from decoding the design configuration
1876 * register to find the maximum supported data bus width.
1878 static u32
macb_dbw(struct macb
*bp
)
1880 if (!macb_is_gem(bp
))
1883 switch (GEM_BFEXT(DBWDEF
, gem_readl(bp
, DCFG1
))) {
1885 return GEM_BF(DBW
, GEM_DBW128
);
1887 return GEM_BF(DBW
, GEM_DBW64
);
1890 return GEM_BF(DBW
, GEM_DBW32
);
1894 /* Configure the receive DMA engine
1895 * - use the correct receive buffer size
1896 * - set best burst length for DMA operations
1897 * (if not supported by FIFO, it will fallback to default)
1898 * - set both rx/tx packet buffers to full memory size
1899 * These are configurable parameters for GEM.
1901 static void macb_configure_dma(struct macb
*bp
)
1905 if (macb_is_gem(bp
)) {
1906 dmacfg
= gem_readl(bp
, DMACFG
) & ~GEM_BF(RXBS
, -1L);
1907 dmacfg
|= GEM_BF(RXBS
, bp
->rx_buffer_size
/ RX_BUFFER_MULTIPLE
);
1908 if (bp
->dma_burst_length
)
1909 dmacfg
= GEM_BFINS(FBLDO
, bp
->dma_burst_length
, dmacfg
);
1910 dmacfg
|= GEM_BIT(TXPBMS
) | GEM_BF(RXBMS
, -1L);
1911 dmacfg
&= ~GEM_BIT(ENDIA_PKT
);
1914 dmacfg
&= ~GEM_BIT(ENDIA_DESC
);
1916 dmacfg
|= GEM_BIT(ENDIA_DESC
); /* CPU in big endian */
1918 if (bp
->dev
->features
& NETIF_F_HW_CSUM
)
1919 dmacfg
|= GEM_BIT(TXCOEN
);
1921 dmacfg
&= ~GEM_BIT(TXCOEN
);
1923 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1924 if (bp
->hw_dma_cap
== HW_DMA_CAP_64B
)
1925 dmacfg
|= GEM_BIT(ADDR64
);
1927 netdev_dbg(bp
->dev
, "Cadence configure DMA with 0x%08x\n",
1929 gem_writel(bp
, DMACFG
, dmacfg
);
1933 static void macb_init_hw(struct macb
*bp
)
1935 struct macb_queue
*queue
;
1941 macb_set_hwaddr(bp
);
1943 config
= macb_mdc_clk_div(bp
);
1944 if (bp
->phy_interface
== PHY_INTERFACE_MODE_SGMII
)
1945 config
|= GEM_BIT(SGMIIEN
) | GEM_BIT(PCSSEL
);
1946 config
|= MACB_BF(RBOF
, NET_IP_ALIGN
); /* Make eth data aligned */
1947 config
|= MACB_BIT(PAE
); /* PAuse Enable */
1948 config
|= MACB_BIT(DRFCS
); /* Discard Rx FCS */
1949 if (bp
->caps
& MACB_CAPS_JUMBO
)
1950 config
|= MACB_BIT(JFRAME
); /* Enable jumbo frames */
1952 config
|= MACB_BIT(BIG
); /* Receive oversized frames */
1953 if (bp
->dev
->flags
& IFF_PROMISC
)
1954 config
|= MACB_BIT(CAF
); /* Copy All Frames */
1955 else if (macb_is_gem(bp
) && bp
->dev
->features
& NETIF_F_RXCSUM
)
1956 config
|= GEM_BIT(RXCOEN
);
1957 if (!(bp
->dev
->flags
& IFF_BROADCAST
))
1958 config
|= MACB_BIT(NBC
); /* No BroadCast */
1959 config
|= macb_dbw(bp
);
1960 macb_writel(bp
, NCFGR
, config
);
1961 if ((bp
->caps
& MACB_CAPS_JUMBO
) && bp
->jumbo_max_len
)
1962 gem_writel(bp
, JML
, bp
->jumbo_max_len
);
1963 bp
->speed
= SPEED_10
;
1964 bp
->duplex
= DUPLEX_HALF
;
1965 bp
->rx_frm_len_mask
= MACB_RX_FRMLEN_MASK
;
1966 if (bp
->caps
& MACB_CAPS_JUMBO
)
1967 bp
->rx_frm_len_mask
= MACB_RX_JFRMLEN_MASK
;
1969 macb_configure_dma(bp
);
1971 /* Initialize TX and RX buffers */
1972 macb_writel(bp
, RBQP
, lower_32_bits(bp
->rx_ring_dma
));
1973 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1974 if (bp
->hw_dma_cap
== HW_DMA_CAP_64B
)
1975 macb_writel(bp
, RBQPH
, upper_32_bits(bp
->rx_ring_dma
));
1977 for (q
= 0, queue
= bp
->queues
; q
< bp
->num_queues
; ++q
, ++queue
) {
1978 queue_writel(queue
, TBQP
, lower_32_bits(queue
->tx_ring_dma
));
1979 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1980 if (bp
->hw_dma_cap
== HW_DMA_CAP_64B
)
1981 queue_writel(queue
, TBQPH
, upper_32_bits(queue
->tx_ring_dma
));
1984 /* Enable interrupts */
1985 queue_writel(queue
, IER
,
1991 /* Enable TX and RX */
1992 macb_writel(bp
, NCR
, MACB_BIT(RE
) | MACB_BIT(TE
) | MACB_BIT(MPE
));
1995 /* The hash address register is 64 bits long and takes up two
1996 * locations in the memory map. The least significant bits are stored
1997 * in EMAC_HSL and the most significant bits in EMAC_HSH.
1999 * The unicast hash enable and the multicast hash enable bits in the
2000 * network configuration register enable the reception of hash matched
2001 * frames. The destination address is reduced to a 6 bit index into
2002 * the 64 bit hash register using the following hash function. The
2003 * hash function is an exclusive or of every sixth bit of the
2004 * destination address.
2006 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
2007 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
2008 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
2009 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
2010 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
2011 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
2013 * da[0] represents the least significant bit of the first byte
2014 * received, that is, the multicast/unicast indicator, and da[47]
2015 * represents the most significant bit of the last byte received. If
2016 * the hash index, hi[n], points to a bit that is set in the hash
2017 * register then the frame will be matched according to whether the
2018 * frame is multicast or unicast. A multicast match will be signalled
2019 * if the multicast hash enable bit is set, da[0] is 1 and the hash
2020 * index points to a bit set in the hash register. A unicast match
2021 * will be signalled if the unicast hash enable bit is set, da[0] is 0
2022 * and the hash index points to a bit set in the hash register. To
2023 * receive all multicast frames, the hash register should be set with
2024 * all ones and the multicast hash enable bit should be set in the
2025 * network configuration register.
2028 static inline int hash_bit_value(int bitnr
, __u8
*addr
)
2030 if (addr
[bitnr
/ 8] & (1 << (bitnr
% 8)))
2035 /* Return the hash index value for the specified address. */
2036 static int hash_get_index(__u8
*addr
)
2041 for (j
= 0; j
< 6; j
++) {
2042 for (i
= 0, bitval
= 0; i
< 8; i
++)
2043 bitval
^= hash_bit_value(i
* 6 + j
, addr
);
2045 hash_index
|= (bitval
<< j
);
2051 /* Add multicast addresses to the internal multicast-hash table. */
2052 static void macb_sethashtable(struct net_device
*dev
)
2054 struct netdev_hw_addr
*ha
;
2055 unsigned long mc_filter
[2];
2057 struct macb
*bp
= netdev_priv(dev
);
2062 netdev_for_each_mc_addr(ha
, dev
) {
2063 bitnr
= hash_get_index(ha
->addr
);
2064 mc_filter
[bitnr
>> 5] |= 1 << (bitnr
& 31);
2067 macb_or_gem_writel(bp
, HRB
, mc_filter
[0]);
2068 macb_or_gem_writel(bp
, HRT
, mc_filter
[1]);
2071 /* Enable/Disable promiscuous and multicast modes. */
2072 static void macb_set_rx_mode(struct net_device
*dev
)
2075 struct macb
*bp
= netdev_priv(dev
);
2077 cfg
= macb_readl(bp
, NCFGR
);
2079 if (dev
->flags
& IFF_PROMISC
) {
2080 /* Enable promiscuous mode */
2081 cfg
|= MACB_BIT(CAF
);
2083 /* Disable RX checksum offload */
2084 if (macb_is_gem(bp
))
2085 cfg
&= ~GEM_BIT(RXCOEN
);
2087 /* Disable promiscuous mode */
2088 cfg
&= ~MACB_BIT(CAF
);
2090 /* Enable RX checksum offload only if requested */
2091 if (macb_is_gem(bp
) && dev
->features
& NETIF_F_RXCSUM
)
2092 cfg
|= GEM_BIT(RXCOEN
);
2095 if (dev
->flags
& IFF_ALLMULTI
) {
2096 /* Enable all multicast mode */
2097 macb_or_gem_writel(bp
, HRB
, -1);
2098 macb_or_gem_writel(bp
, HRT
, -1);
2099 cfg
|= MACB_BIT(NCFGR_MTI
);
2100 } else if (!netdev_mc_empty(dev
)) {
2101 /* Enable specific multicasts */
2102 macb_sethashtable(dev
);
2103 cfg
|= MACB_BIT(NCFGR_MTI
);
2104 } else if (dev
->flags
& (~IFF_ALLMULTI
)) {
2105 /* Disable all multicast mode */
2106 macb_or_gem_writel(bp
, HRB
, 0);
2107 macb_or_gem_writel(bp
, HRT
, 0);
2108 cfg
&= ~MACB_BIT(NCFGR_MTI
);
2111 macb_writel(bp
, NCFGR
, cfg
);
2114 static int macb_open(struct net_device
*dev
)
2116 struct macb
*bp
= netdev_priv(dev
);
2117 size_t bufsz
= dev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+ NET_IP_ALIGN
;
2120 netdev_dbg(bp
->dev
, "open\n");
2122 /* carrier starts down */
2123 netif_carrier_off(dev
);
2125 /* if the phy is not yet register, retry later*/
2129 /* RX buffers initialization */
2130 macb_init_rx_buffer_size(bp
, bufsz
);
2132 err
= macb_alloc_consistent(bp
);
2134 netdev_err(dev
, "Unable to allocate DMA memory (error %d)\n",
2139 napi_enable(&bp
->napi
);
2141 bp
->macbgem_ops
.mog_init_rings(bp
);
2144 /* schedule a link state check */
2145 phy_start(dev
->phydev
);
2147 netif_tx_start_all_queues(dev
);
2150 bp
->ptp_info
->ptp_init(dev
);
2155 static int macb_close(struct net_device
*dev
)
2157 struct macb
*bp
= netdev_priv(dev
);
2158 unsigned long flags
;
2160 netif_tx_stop_all_queues(dev
);
2161 napi_disable(&bp
->napi
);
2164 phy_stop(dev
->phydev
);
2166 spin_lock_irqsave(&bp
->lock
, flags
);
2168 netif_carrier_off(dev
);
2169 spin_unlock_irqrestore(&bp
->lock
, flags
);
2171 macb_free_consistent(bp
);
2174 bp
->ptp_info
->ptp_remove(dev
);
2179 static int macb_change_mtu(struct net_device
*dev
, int new_mtu
)
2181 if (netif_running(dev
))
2189 static void gem_update_stats(struct macb
*bp
)
2192 u32
*p
= &bp
->hw_stats
.gem
.tx_octets_31_0
;
2194 for (i
= 0; i
< GEM_STATS_LEN
; ++i
, ++p
) {
2195 u32 offset
= gem_statistics
[i
].offset
;
2196 u64 val
= bp
->macb_reg_readl(bp
, offset
);
2198 bp
->ethtool_stats
[i
] += val
;
2201 if (offset
== GEM_OCTTXL
|| offset
== GEM_OCTRXL
) {
2202 /* Add GEM_OCTTXH, GEM_OCTRXH */
2203 val
= bp
->macb_reg_readl(bp
, offset
+ 4);
2204 bp
->ethtool_stats
[i
] += ((u64
)val
) << 32;
2210 static struct net_device_stats
*gem_get_stats(struct macb
*bp
)
2212 struct gem_stats
*hwstat
= &bp
->hw_stats
.gem
;
2213 struct net_device_stats
*nstat
= &bp
->stats
;
2215 gem_update_stats(bp
);
2217 nstat
->rx_errors
= (hwstat
->rx_frame_check_sequence_errors
+
2218 hwstat
->rx_alignment_errors
+
2219 hwstat
->rx_resource_errors
+
2220 hwstat
->rx_overruns
+
2221 hwstat
->rx_oversize_frames
+
2222 hwstat
->rx_jabbers
+
2223 hwstat
->rx_undersized_frames
+
2224 hwstat
->rx_length_field_frame_errors
);
2225 nstat
->tx_errors
= (hwstat
->tx_late_collisions
+
2226 hwstat
->tx_excessive_collisions
+
2227 hwstat
->tx_underrun
+
2228 hwstat
->tx_carrier_sense_errors
);
2229 nstat
->multicast
= hwstat
->rx_multicast_frames
;
2230 nstat
->collisions
= (hwstat
->tx_single_collision_frames
+
2231 hwstat
->tx_multiple_collision_frames
+
2232 hwstat
->tx_excessive_collisions
);
2233 nstat
->rx_length_errors
= (hwstat
->rx_oversize_frames
+
2234 hwstat
->rx_jabbers
+
2235 hwstat
->rx_undersized_frames
+
2236 hwstat
->rx_length_field_frame_errors
);
2237 nstat
->rx_over_errors
= hwstat
->rx_resource_errors
;
2238 nstat
->rx_crc_errors
= hwstat
->rx_frame_check_sequence_errors
;
2239 nstat
->rx_frame_errors
= hwstat
->rx_alignment_errors
;
2240 nstat
->rx_fifo_errors
= hwstat
->rx_overruns
;
2241 nstat
->tx_aborted_errors
= hwstat
->tx_excessive_collisions
;
2242 nstat
->tx_carrier_errors
= hwstat
->tx_carrier_sense_errors
;
2243 nstat
->tx_fifo_errors
= hwstat
->tx_underrun
;
2248 static void gem_get_ethtool_stats(struct net_device
*dev
,
2249 struct ethtool_stats
*stats
, u64
*data
)
2253 bp
= netdev_priv(dev
);
2254 gem_update_stats(bp
);
2255 memcpy(data
, &bp
->ethtool_stats
, sizeof(u64
) * GEM_STATS_LEN
);
2258 static int gem_get_sset_count(struct net_device
*dev
, int sset
)
2262 return GEM_STATS_LEN
;
2268 static void gem_get_ethtool_strings(struct net_device
*dev
, u32 sset
, u8
*p
)
2274 for (i
= 0; i
< GEM_STATS_LEN
; i
++, p
+= ETH_GSTRING_LEN
)
2275 memcpy(p
, gem_statistics
[i
].stat_string
,
2281 static struct net_device_stats
*macb_get_stats(struct net_device
*dev
)
2283 struct macb
*bp
= netdev_priv(dev
);
2284 struct net_device_stats
*nstat
= &bp
->stats
;
2285 struct macb_stats
*hwstat
= &bp
->hw_stats
.macb
;
2287 if (macb_is_gem(bp
))
2288 return gem_get_stats(bp
);
2290 /* read stats from hardware */
2291 macb_update_stats(bp
);
2293 /* Convert HW stats into netdevice stats */
2294 nstat
->rx_errors
= (hwstat
->rx_fcs_errors
+
2295 hwstat
->rx_align_errors
+
2296 hwstat
->rx_resource_errors
+
2297 hwstat
->rx_overruns
+
2298 hwstat
->rx_oversize_pkts
+
2299 hwstat
->rx_jabbers
+
2300 hwstat
->rx_undersize_pkts
+
2301 hwstat
->rx_length_mismatch
);
2302 nstat
->tx_errors
= (hwstat
->tx_late_cols
+
2303 hwstat
->tx_excessive_cols
+
2304 hwstat
->tx_underruns
+
2305 hwstat
->tx_carrier_errors
+
2306 hwstat
->sqe_test_errors
);
2307 nstat
->collisions
= (hwstat
->tx_single_cols
+
2308 hwstat
->tx_multiple_cols
+
2309 hwstat
->tx_excessive_cols
);
2310 nstat
->rx_length_errors
= (hwstat
->rx_oversize_pkts
+
2311 hwstat
->rx_jabbers
+
2312 hwstat
->rx_undersize_pkts
+
2313 hwstat
->rx_length_mismatch
);
2314 nstat
->rx_over_errors
= hwstat
->rx_resource_errors
+
2315 hwstat
->rx_overruns
;
2316 nstat
->rx_crc_errors
= hwstat
->rx_fcs_errors
;
2317 nstat
->rx_frame_errors
= hwstat
->rx_align_errors
;
2318 nstat
->rx_fifo_errors
= hwstat
->rx_overruns
;
2319 /* XXX: What does "missed" mean? */
2320 nstat
->tx_aborted_errors
= hwstat
->tx_excessive_cols
;
2321 nstat
->tx_carrier_errors
= hwstat
->tx_carrier_errors
;
2322 nstat
->tx_fifo_errors
= hwstat
->tx_underruns
;
2323 /* Don't know about heartbeat or window errors... */
2328 static int macb_get_regs_len(struct net_device
*netdev
)
2330 return MACB_GREGS_NBR
* sizeof(u32
);
2333 static void macb_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
2336 struct macb
*bp
= netdev_priv(dev
);
2337 unsigned int tail
, head
;
2340 regs
->version
= (macb_readl(bp
, MID
) & ((1 << MACB_REV_SIZE
) - 1))
2341 | MACB_GREGS_VERSION
;
2343 tail
= macb_tx_ring_wrap(bp
, bp
->queues
[0].tx_tail
);
2344 head
= macb_tx_ring_wrap(bp
, bp
->queues
[0].tx_head
);
2346 regs_buff
[0] = macb_readl(bp
, NCR
);
2347 regs_buff
[1] = macb_or_gem_readl(bp
, NCFGR
);
2348 regs_buff
[2] = macb_readl(bp
, NSR
);
2349 regs_buff
[3] = macb_readl(bp
, TSR
);
2350 regs_buff
[4] = macb_readl(bp
, RBQP
);
2351 regs_buff
[5] = macb_readl(bp
, TBQP
);
2352 regs_buff
[6] = macb_readl(bp
, RSR
);
2353 regs_buff
[7] = macb_readl(bp
, IMR
);
2355 regs_buff
[8] = tail
;
2356 regs_buff
[9] = head
;
2357 regs_buff
[10] = macb_tx_dma(&bp
->queues
[0], tail
);
2358 regs_buff
[11] = macb_tx_dma(&bp
->queues
[0], head
);
2360 if (!(bp
->caps
& MACB_CAPS_USRIO_DISABLED
))
2361 regs_buff
[12] = macb_or_gem_readl(bp
, USRIO
);
2362 if (macb_is_gem(bp
))
2363 regs_buff
[13] = gem_readl(bp
, DMACFG
);
2366 static void macb_get_wol(struct net_device
*netdev
, struct ethtool_wolinfo
*wol
)
2368 struct macb
*bp
= netdev_priv(netdev
);
2373 if (bp
->wol
& MACB_WOL_HAS_MAGIC_PACKET
) {
2374 wol
->supported
= WAKE_MAGIC
;
2376 if (bp
->wol
& MACB_WOL_ENABLED
)
2377 wol
->wolopts
|= WAKE_MAGIC
;
2381 static int macb_set_wol(struct net_device
*netdev
, struct ethtool_wolinfo
*wol
)
2383 struct macb
*bp
= netdev_priv(netdev
);
2385 if (!(bp
->wol
& MACB_WOL_HAS_MAGIC_PACKET
) ||
2386 (wol
->wolopts
& ~WAKE_MAGIC
))
2389 if (wol
->wolopts
& WAKE_MAGIC
)
2390 bp
->wol
|= MACB_WOL_ENABLED
;
2392 bp
->wol
&= ~MACB_WOL_ENABLED
;
2394 device_set_wakeup_enable(&bp
->pdev
->dev
, bp
->wol
& MACB_WOL_ENABLED
);
2399 static void macb_get_ringparam(struct net_device
*netdev
,
2400 struct ethtool_ringparam
*ring
)
2402 struct macb
*bp
= netdev_priv(netdev
);
2404 ring
->rx_max_pending
= MAX_RX_RING_SIZE
;
2405 ring
->tx_max_pending
= MAX_TX_RING_SIZE
;
2407 ring
->rx_pending
= bp
->rx_ring_size
;
2408 ring
->tx_pending
= bp
->tx_ring_size
;
2411 static int macb_set_ringparam(struct net_device
*netdev
,
2412 struct ethtool_ringparam
*ring
)
2414 struct macb
*bp
= netdev_priv(netdev
);
2415 u32 new_rx_size
, new_tx_size
;
2416 unsigned int reset
= 0;
2418 if ((ring
->rx_mini_pending
) || (ring
->rx_jumbo_pending
))
2421 new_rx_size
= clamp_t(u32
, ring
->rx_pending
,
2422 MIN_RX_RING_SIZE
, MAX_RX_RING_SIZE
);
2423 new_rx_size
= roundup_pow_of_two(new_rx_size
);
2425 new_tx_size
= clamp_t(u32
, ring
->tx_pending
,
2426 MIN_TX_RING_SIZE
, MAX_TX_RING_SIZE
);
2427 new_tx_size
= roundup_pow_of_two(new_tx_size
);
2429 if ((new_tx_size
== bp
->tx_ring_size
) &&
2430 (new_rx_size
== bp
->rx_ring_size
)) {
2435 if (netif_running(bp
->dev
)) {
2437 macb_close(bp
->dev
);
2440 bp
->rx_ring_size
= new_rx_size
;
2441 bp
->tx_ring_size
= new_tx_size
;
2449 static int macb_get_ts_info(struct net_device
*netdev
,
2450 struct ethtool_ts_info
*info
)
2452 struct macb
*bp
= netdev_priv(netdev
);
2455 return bp
->ptp_info
->get_ts_info(netdev
, info
);
2457 return ethtool_op_get_ts_info(netdev
, info
);
2460 static const struct ethtool_ops macb_ethtool_ops
= {
2461 .get_regs_len
= macb_get_regs_len
,
2462 .get_regs
= macb_get_regs
,
2463 .get_link
= ethtool_op_get_link
,
2464 .get_ts_info
= ethtool_op_get_ts_info
,
2465 .get_wol
= macb_get_wol
,
2466 .set_wol
= macb_set_wol
,
2467 .get_link_ksettings
= phy_ethtool_get_link_ksettings
,
2468 .set_link_ksettings
= phy_ethtool_set_link_ksettings
,
2469 .get_ringparam
= macb_get_ringparam
,
2470 .set_ringparam
= macb_set_ringparam
,
2473 static const struct ethtool_ops gem_ethtool_ops
= {
2474 .get_regs_len
= macb_get_regs_len
,
2475 .get_regs
= macb_get_regs
,
2476 .get_link
= ethtool_op_get_link
,
2477 .get_ts_info
= macb_get_ts_info
,
2478 .get_ethtool_stats
= gem_get_ethtool_stats
,
2479 .get_strings
= gem_get_ethtool_strings
,
2480 .get_sset_count
= gem_get_sset_count
,
2481 .get_link_ksettings
= phy_ethtool_get_link_ksettings
,
2482 .set_link_ksettings
= phy_ethtool_set_link_ksettings
,
2483 .get_ringparam
= macb_get_ringparam
,
2484 .set_ringparam
= macb_set_ringparam
,
2487 static int macb_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
2489 struct phy_device
*phydev
= dev
->phydev
;
2490 struct macb
*bp
= netdev_priv(dev
);
2492 if (!netif_running(dev
))
2499 return phy_mii_ioctl(phydev
, rq
, cmd
);
2503 return bp
->ptp_info
->set_hwtst(dev
, rq
, cmd
);
2505 return bp
->ptp_info
->get_hwtst(dev
, rq
);
2507 return phy_mii_ioctl(phydev
, rq
, cmd
);
2511 static int macb_set_features(struct net_device
*netdev
,
2512 netdev_features_t features
)
2514 struct macb
*bp
= netdev_priv(netdev
);
2515 netdev_features_t changed
= features
^ netdev
->features
;
2517 /* TX checksum offload */
2518 if ((changed
& NETIF_F_HW_CSUM
) && macb_is_gem(bp
)) {
2521 dmacfg
= gem_readl(bp
, DMACFG
);
2522 if (features
& NETIF_F_HW_CSUM
)
2523 dmacfg
|= GEM_BIT(TXCOEN
);
2525 dmacfg
&= ~GEM_BIT(TXCOEN
);
2526 gem_writel(bp
, DMACFG
, dmacfg
);
2529 /* RX checksum offload */
2530 if ((changed
& NETIF_F_RXCSUM
) && macb_is_gem(bp
)) {
2533 netcfg
= gem_readl(bp
, NCFGR
);
2534 if (features
& NETIF_F_RXCSUM
&&
2535 !(netdev
->flags
& IFF_PROMISC
))
2536 netcfg
|= GEM_BIT(RXCOEN
);
2538 netcfg
&= ~GEM_BIT(RXCOEN
);
2539 gem_writel(bp
, NCFGR
, netcfg
);
2545 static const struct net_device_ops macb_netdev_ops
= {
2546 .ndo_open
= macb_open
,
2547 .ndo_stop
= macb_close
,
2548 .ndo_start_xmit
= macb_start_xmit
,
2549 .ndo_set_rx_mode
= macb_set_rx_mode
,
2550 .ndo_get_stats
= macb_get_stats
,
2551 .ndo_do_ioctl
= macb_ioctl
,
2552 .ndo_validate_addr
= eth_validate_addr
,
2553 .ndo_change_mtu
= macb_change_mtu
,
2554 .ndo_set_mac_address
= eth_mac_addr
,
2555 #ifdef CONFIG_NET_POLL_CONTROLLER
2556 .ndo_poll_controller
= macb_poll_controller
,
2558 .ndo_set_features
= macb_set_features
,
2559 .ndo_features_check
= macb_features_check
,
2562 /* Configure peripheral capabilities according to device tree
2563 * and integration options used
2565 static void macb_configure_caps(struct macb
*bp
,
2566 const struct macb_config
*dt_conf
)
2571 bp
->caps
= dt_conf
->caps
;
2573 if (hw_is_gem(bp
->regs
, bp
->native_io
)) {
2574 bp
->caps
|= MACB_CAPS_MACB_IS_GEM
;
2576 dcfg
= gem_readl(bp
, DCFG1
);
2577 if (GEM_BFEXT(IRQCOR
, dcfg
) == 0)
2578 bp
->caps
|= MACB_CAPS_ISR_CLEAR_ON_WRITE
;
2579 dcfg
= gem_readl(bp
, DCFG2
);
2580 if ((dcfg
& (GEM_BIT(RX_PKT_BUFF
) | GEM_BIT(TX_PKT_BUFF
))) == 0)
2581 bp
->caps
|= MACB_CAPS_FIFO_MODE
;
2584 dev_dbg(&bp
->pdev
->dev
, "Cadence caps 0x%08x\n", bp
->caps
);
2587 static void macb_probe_queues(void __iomem
*mem
,
2589 unsigned int *queue_mask
,
2590 unsigned int *num_queues
)
2597 /* is it macb or gem ?
2599 * We need to read directly from the hardware here because
2600 * we are early in the probe process and don't have the
2601 * MACB_CAPS_MACB_IS_GEM flag positioned
2603 if (!hw_is_gem(mem
, native_io
))
2606 /* bit 0 is never set but queue 0 always exists */
2607 *queue_mask
= readl_relaxed(mem
+ GEM_DCFG6
) & 0xff;
2611 for (hw_q
= 1; hw_q
< MACB_MAX_QUEUES
; ++hw_q
)
2612 if (*queue_mask
& (1 << hw_q
))
2616 static int macb_clk_init(struct platform_device
*pdev
, struct clk
**pclk
,
2617 struct clk
**hclk
, struct clk
**tx_clk
,
2618 struct clk
**rx_clk
)
2620 struct macb_platform_data
*pdata
;
2623 pdata
= dev_get_platdata(&pdev
->dev
);
2625 *pclk
= pdata
->pclk
;
2626 *hclk
= pdata
->hclk
;
2628 *pclk
= devm_clk_get(&pdev
->dev
, "pclk");
2629 *hclk
= devm_clk_get(&pdev
->dev
, "hclk");
2632 if (IS_ERR(*pclk
)) {
2633 err
= PTR_ERR(*pclk
);
2634 dev_err(&pdev
->dev
, "failed to get macb_clk (%u)\n", err
);
2638 if (IS_ERR(*hclk
)) {
2639 err
= PTR_ERR(*hclk
);
2640 dev_err(&pdev
->dev
, "failed to get hclk (%u)\n", err
);
2644 *tx_clk
= devm_clk_get(&pdev
->dev
, "tx_clk");
2645 if (IS_ERR(*tx_clk
))
2648 *rx_clk
= devm_clk_get(&pdev
->dev
, "rx_clk");
2649 if (IS_ERR(*rx_clk
))
2652 err
= clk_prepare_enable(*pclk
);
2654 dev_err(&pdev
->dev
, "failed to enable pclk (%u)\n", err
);
2658 err
= clk_prepare_enable(*hclk
);
2660 dev_err(&pdev
->dev
, "failed to enable hclk (%u)\n", err
);
2661 goto err_disable_pclk
;
2664 err
= clk_prepare_enable(*tx_clk
);
2666 dev_err(&pdev
->dev
, "failed to enable tx_clk (%u)\n", err
);
2667 goto err_disable_hclk
;
2670 err
= clk_prepare_enable(*rx_clk
);
2672 dev_err(&pdev
->dev
, "failed to enable rx_clk (%u)\n", err
);
2673 goto err_disable_txclk
;
2679 clk_disable_unprepare(*tx_clk
);
2682 clk_disable_unprepare(*hclk
);
2685 clk_disable_unprepare(*pclk
);
2690 static int macb_init(struct platform_device
*pdev
)
2692 struct net_device
*dev
= platform_get_drvdata(pdev
);
2693 unsigned int hw_q
, q
;
2694 struct macb
*bp
= netdev_priv(dev
);
2695 struct macb_queue
*queue
;
2699 bp
->tx_ring_size
= DEFAULT_TX_RING_SIZE
;
2700 bp
->rx_ring_size
= DEFAULT_RX_RING_SIZE
;
2702 /* set the queue register mapping once for all: queue0 has a special
2703 * register mapping but we don't want to test the queue index then
2704 * compute the corresponding register offset at run time.
2706 for (hw_q
= 0, q
= 0; hw_q
< MACB_MAX_QUEUES
; ++hw_q
) {
2707 if (!(bp
->queue_mask
& (1 << hw_q
)))
2710 queue
= &bp
->queues
[q
];
2713 queue
->ISR
= GEM_ISR(hw_q
- 1);
2714 queue
->IER
= GEM_IER(hw_q
- 1);
2715 queue
->IDR
= GEM_IDR(hw_q
- 1);
2716 queue
->IMR
= GEM_IMR(hw_q
- 1);
2717 queue
->TBQP
= GEM_TBQP(hw_q
- 1);
2718 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2719 if (bp
->hw_dma_cap
== HW_DMA_CAP_64B
)
2720 queue
->TBQPH
= GEM_TBQPH(hw_q
- 1);
2723 /* queue0 uses legacy registers */
2724 queue
->ISR
= MACB_ISR
;
2725 queue
->IER
= MACB_IER
;
2726 queue
->IDR
= MACB_IDR
;
2727 queue
->IMR
= MACB_IMR
;
2728 queue
->TBQP
= MACB_TBQP
;
2729 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2730 if (bp
->hw_dma_cap
== HW_DMA_CAP_64B
)
2731 queue
->TBQPH
= MACB_TBQPH
;
2735 /* get irq: here we use the linux queue index, not the hardware
2736 * queue index. the queue irq definitions in the device tree
2737 * must remove the optional gaps that could exist in the
2738 * hardware queue mask.
2740 queue
->irq
= platform_get_irq(pdev
, q
);
2741 err
= devm_request_irq(&pdev
->dev
, queue
->irq
, macb_interrupt
,
2742 IRQF_SHARED
, dev
->name
, queue
);
2745 "Unable to request IRQ %d (error %d)\n",
2750 INIT_WORK(&queue
->tx_error_task
, macb_tx_error_task
);
2754 dev
->netdev_ops
= &macb_netdev_ops
;
2755 netif_napi_add(dev
, &bp
->napi
, macb_poll
, 64);
2757 /* setup appropriated routines according to adapter type */
2758 if (macb_is_gem(bp
)) {
2759 bp
->max_tx_length
= GEM_MAX_TX_LEN
;
2760 bp
->macbgem_ops
.mog_alloc_rx_buffers
= gem_alloc_rx_buffers
;
2761 bp
->macbgem_ops
.mog_free_rx_buffers
= gem_free_rx_buffers
;
2762 bp
->macbgem_ops
.mog_init_rings
= gem_init_rings
;
2763 bp
->macbgem_ops
.mog_rx
= gem_rx
;
2764 dev
->ethtool_ops
= &gem_ethtool_ops
;
2766 bp
->max_tx_length
= MACB_MAX_TX_LEN
;
2767 bp
->macbgem_ops
.mog_alloc_rx_buffers
= macb_alloc_rx_buffers
;
2768 bp
->macbgem_ops
.mog_free_rx_buffers
= macb_free_rx_buffers
;
2769 bp
->macbgem_ops
.mog_init_rings
= macb_init_rings
;
2770 bp
->macbgem_ops
.mog_rx
= macb_rx
;
2771 dev
->ethtool_ops
= &macb_ethtool_ops
;
2775 dev
->hw_features
= NETIF_F_SG
;
2777 /* Check LSO capability */
2778 if (GEM_BFEXT(PBUF_LSO
, gem_readl(bp
, DCFG6
)))
2779 dev
->hw_features
|= MACB_NETIF_LSO
;
2781 /* Checksum offload is only available on gem with packet buffer */
2782 if (macb_is_gem(bp
) && !(bp
->caps
& MACB_CAPS_FIFO_MODE
))
2783 dev
->hw_features
|= NETIF_F_HW_CSUM
| NETIF_F_RXCSUM
;
2784 if (bp
->caps
& MACB_CAPS_SG_DISABLED
)
2785 dev
->hw_features
&= ~NETIF_F_SG
;
2786 dev
->features
= dev
->hw_features
;
2788 if (!(bp
->caps
& MACB_CAPS_USRIO_DISABLED
)) {
2790 if (bp
->phy_interface
== PHY_INTERFACE_MODE_RGMII
)
2791 val
= GEM_BIT(RGMII
);
2792 else if (bp
->phy_interface
== PHY_INTERFACE_MODE_RMII
&&
2793 (bp
->caps
& MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII
))
2794 val
= MACB_BIT(RMII
);
2795 else if (!(bp
->caps
& MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII
))
2796 val
= MACB_BIT(MII
);
2798 if (bp
->caps
& MACB_CAPS_USRIO_HAS_CLKEN
)
2799 val
|= MACB_BIT(CLKEN
);
2801 macb_or_gem_writel(bp
, USRIO
, val
);
2804 /* Set MII management clock divider */
2805 val
= macb_mdc_clk_div(bp
);
2806 val
|= macb_dbw(bp
);
2807 if (bp
->phy_interface
== PHY_INTERFACE_MODE_SGMII
)
2808 val
|= GEM_BIT(SGMIIEN
) | GEM_BIT(PCSSEL
);
2809 macb_writel(bp
, NCFGR
, val
);
2814 #if defined(CONFIG_OF)
2815 /* 1518 rounded up */
2816 #define AT91ETHER_MAX_RBUFF_SZ 0x600
2817 /* max number of receive buffers */
2818 #define AT91ETHER_MAX_RX_DESCR 9
2820 /* Initialize and start the Receiver and Transmit subsystems */
2821 static int at91ether_start(struct net_device
*dev
)
2823 struct macb
*lp
= netdev_priv(dev
);
2824 struct macb_dma_desc
*desc
;
2829 lp
->rx_ring
= dma_alloc_coherent(&lp
->pdev
->dev
,
2830 (AT91ETHER_MAX_RX_DESCR
*
2831 macb_dma_desc_get_size(lp
)),
2832 &lp
->rx_ring_dma
, GFP_KERNEL
);
2836 lp
->rx_buffers
= dma_alloc_coherent(&lp
->pdev
->dev
,
2837 AT91ETHER_MAX_RX_DESCR
*
2838 AT91ETHER_MAX_RBUFF_SZ
,
2839 &lp
->rx_buffers_dma
, GFP_KERNEL
);
2840 if (!lp
->rx_buffers
) {
2841 dma_free_coherent(&lp
->pdev
->dev
,
2842 AT91ETHER_MAX_RX_DESCR
*
2843 macb_dma_desc_get_size(lp
),
2844 lp
->rx_ring
, lp
->rx_ring_dma
);
2849 addr
= lp
->rx_buffers_dma
;
2850 for (i
= 0; i
< AT91ETHER_MAX_RX_DESCR
; i
++) {
2851 desc
= macb_rx_desc(lp
, i
);
2852 macb_set_addr(lp
, desc
, addr
);
2854 addr
+= AT91ETHER_MAX_RBUFF_SZ
;
2857 /* Set the Wrap bit on the last descriptor */
2858 desc
->addr
|= MACB_BIT(RX_WRAP
);
2860 /* Reset buffer index */
2863 /* Program address of descriptor list in Rx Buffer Queue register */
2864 macb_writel(lp
, RBQP
, lp
->rx_ring_dma
);
2866 /* Enable Receive and Transmit */
2867 ctl
= macb_readl(lp
, NCR
);
2868 macb_writel(lp
, NCR
, ctl
| MACB_BIT(RE
) | MACB_BIT(TE
));
2873 /* Open the ethernet interface */
2874 static int at91ether_open(struct net_device
*dev
)
2876 struct macb
*lp
= netdev_priv(dev
);
2880 /* Clear internal statistics */
2881 ctl
= macb_readl(lp
, NCR
);
2882 macb_writel(lp
, NCR
, ctl
| MACB_BIT(CLRSTAT
));
2884 macb_set_hwaddr(lp
);
2886 ret
= at91ether_start(dev
);
2890 /* Enable MAC interrupts */
2891 macb_writel(lp
, IER
, MACB_BIT(RCOMP
) |
2893 MACB_BIT(ISR_TUND
) |
2896 MACB_BIT(ISR_ROVR
) |
2899 /* schedule a link state check */
2900 phy_start(dev
->phydev
);
2902 netif_start_queue(dev
);
2907 /* Close the interface */
2908 static int at91ether_close(struct net_device
*dev
)
2910 struct macb
*lp
= netdev_priv(dev
);
2913 /* Disable Receiver and Transmitter */
2914 ctl
= macb_readl(lp
, NCR
);
2915 macb_writel(lp
, NCR
, ctl
& ~(MACB_BIT(TE
) | MACB_BIT(RE
)));
2917 /* Disable MAC interrupts */
2918 macb_writel(lp
, IDR
, MACB_BIT(RCOMP
) |
2920 MACB_BIT(ISR_TUND
) |
2923 MACB_BIT(ISR_ROVR
) |
2926 netif_stop_queue(dev
);
2928 dma_free_coherent(&lp
->pdev
->dev
,
2929 AT91ETHER_MAX_RX_DESCR
*
2930 macb_dma_desc_get_size(lp
),
2931 lp
->rx_ring
, lp
->rx_ring_dma
);
2934 dma_free_coherent(&lp
->pdev
->dev
,
2935 AT91ETHER_MAX_RX_DESCR
* AT91ETHER_MAX_RBUFF_SZ
,
2936 lp
->rx_buffers
, lp
->rx_buffers_dma
);
2937 lp
->rx_buffers
= NULL
;
2942 /* Transmit packet */
2943 static int at91ether_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
2945 struct macb
*lp
= netdev_priv(dev
);
2947 if (macb_readl(lp
, TSR
) & MACB_BIT(RM9200_BNQ
)) {
2948 netif_stop_queue(dev
);
2950 /* Store packet information (to free when Tx completed) */
2952 lp
->skb_length
= skb
->len
;
2953 lp
->skb_physaddr
= dma_map_single(NULL
, skb
->data
, skb
->len
,
2955 if (dma_mapping_error(NULL
, lp
->skb_physaddr
)) {
2956 dev_kfree_skb_any(skb
);
2957 dev
->stats
.tx_dropped
++;
2958 netdev_err(dev
, "%s: DMA mapping error\n", __func__
);
2959 return NETDEV_TX_OK
;
2962 /* Set address of the data in the Transmit Address register */
2963 macb_writel(lp
, TAR
, lp
->skb_physaddr
);
2964 /* Set length of the packet in the Transmit Control register */
2965 macb_writel(lp
, TCR
, skb
->len
);
2968 netdev_err(dev
, "%s called, but device is busy!\n", __func__
);
2969 return NETDEV_TX_BUSY
;
2972 return NETDEV_TX_OK
;
2975 /* Extract received frame from buffer descriptors and sent to upper layers.
2976 * (Called from interrupt context)
2978 static void at91ether_rx(struct net_device
*dev
)
2980 struct macb
*lp
= netdev_priv(dev
);
2981 struct macb_dma_desc
*desc
;
2982 unsigned char *p_recv
;
2983 struct sk_buff
*skb
;
2984 unsigned int pktlen
;
2986 desc
= macb_rx_desc(lp
, lp
->rx_tail
);
2987 while (desc
->addr
& MACB_BIT(RX_USED
)) {
2988 p_recv
= lp
->rx_buffers
+ lp
->rx_tail
* AT91ETHER_MAX_RBUFF_SZ
;
2989 pktlen
= MACB_BF(RX_FRMLEN
, desc
->ctrl
);
2990 skb
= netdev_alloc_skb(dev
, pktlen
+ 2);
2992 skb_reserve(skb
, 2);
2993 memcpy(skb_put(skb
, pktlen
), p_recv
, pktlen
);
2995 skb
->protocol
= eth_type_trans(skb
, dev
);
2996 lp
->stats
.rx_packets
++;
2997 lp
->stats
.rx_bytes
+= pktlen
;
3000 lp
->stats
.rx_dropped
++;
3003 if (desc
->ctrl
& MACB_BIT(RX_MHASH_MATCH
))
3004 lp
->stats
.multicast
++;
3006 /* reset ownership bit */
3007 desc
->addr
&= ~MACB_BIT(RX_USED
);
3009 /* wrap after last buffer */
3010 if (lp
->rx_tail
== AT91ETHER_MAX_RX_DESCR
- 1)
3015 desc
= macb_rx_desc(lp
, lp
->rx_tail
);
3019 /* MAC interrupt handler */
3020 static irqreturn_t
at91ether_interrupt(int irq
, void *dev_id
)
3022 struct net_device
*dev
= dev_id
;
3023 struct macb
*lp
= netdev_priv(dev
);
3026 /* MAC Interrupt Status register indicates what interrupts are pending.
3027 * It is automatically cleared once read.
3029 intstatus
= macb_readl(lp
, ISR
);
3031 /* Receive complete */
3032 if (intstatus
& MACB_BIT(RCOMP
))
3035 /* Transmit complete */
3036 if (intstatus
& MACB_BIT(TCOMP
)) {
3037 /* The TCOM bit is set even if the transmission failed */
3038 if (intstatus
& (MACB_BIT(ISR_TUND
) | MACB_BIT(ISR_RLE
)))
3039 lp
->stats
.tx_errors
++;
3042 dev_kfree_skb_irq(lp
->skb
);
3044 dma_unmap_single(NULL
, lp
->skb_physaddr
,
3045 lp
->skb_length
, DMA_TO_DEVICE
);
3046 lp
->stats
.tx_packets
++;
3047 lp
->stats
.tx_bytes
+= lp
->skb_length
;
3049 netif_wake_queue(dev
);
3052 /* Work-around for EMAC Errata section 41.3.1 */
3053 if (intstatus
& MACB_BIT(RXUBR
)) {
3054 ctl
= macb_readl(lp
, NCR
);
3055 macb_writel(lp
, NCR
, ctl
& ~MACB_BIT(RE
));
3057 macb_writel(lp
, NCR
, ctl
| MACB_BIT(RE
));
3060 if (intstatus
& MACB_BIT(ISR_ROVR
))
3061 netdev_err(dev
, "ROVR error\n");
3066 #ifdef CONFIG_NET_POLL_CONTROLLER
3067 static void at91ether_poll_controller(struct net_device
*dev
)
3069 unsigned long flags
;
3071 local_irq_save(flags
);
3072 at91ether_interrupt(dev
->irq
, dev
);
3073 local_irq_restore(flags
);
3077 static const struct net_device_ops at91ether_netdev_ops
= {
3078 .ndo_open
= at91ether_open
,
3079 .ndo_stop
= at91ether_close
,
3080 .ndo_start_xmit
= at91ether_start_xmit
,
3081 .ndo_get_stats
= macb_get_stats
,
3082 .ndo_set_rx_mode
= macb_set_rx_mode
,
3083 .ndo_set_mac_address
= eth_mac_addr
,
3084 .ndo_do_ioctl
= macb_ioctl
,
3085 .ndo_validate_addr
= eth_validate_addr
,
3086 #ifdef CONFIG_NET_POLL_CONTROLLER
3087 .ndo_poll_controller
= at91ether_poll_controller
,
3091 static int at91ether_clk_init(struct platform_device
*pdev
, struct clk
**pclk
,
3092 struct clk
**hclk
, struct clk
**tx_clk
,
3093 struct clk
**rx_clk
)
3101 *pclk
= devm_clk_get(&pdev
->dev
, "ether_clk");
3103 return PTR_ERR(*pclk
);
3105 err
= clk_prepare_enable(*pclk
);
3107 dev_err(&pdev
->dev
, "failed to enable pclk (%u)\n", err
);
3114 static int at91ether_init(struct platform_device
*pdev
)
3116 struct net_device
*dev
= platform_get_drvdata(pdev
);
3117 struct macb
*bp
= netdev_priv(dev
);
3121 dev
->netdev_ops
= &at91ether_netdev_ops
;
3122 dev
->ethtool_ops
= &macb_ethtool_ops
;
3124 err
= devm_request_irq(&pdev
->dev
, dev
->irq
, at91ether_interrupt
,
3129 macb_writel(bp
, NCR
, 0);
3131 reg
= MACB_BF(CLK
, MACB_CLK_DIV32
) | MACB_BIT(BIG
);
3132 if (bp
->phy_interface
== PHY_INTERFACE_MODE_RMII
)
3133 reg
|= MACB_BIT(RM9200_RMII
);
3135 macb_writel(bp
, NCFGR
, reg
);
3140 static const struct macb_config at91sam9260_config
= {
3141 .caps
= MACB_CAPS_USRIO_HAS_CLKEN
| MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII
,
3142 .clk_init
= macb_clk_init
,
3146 static const struct macb_config pc302gem_config
= {
3147 .caps
= MACB_CAPS_SG_DISABLED
| MACB_CAPS_GIGABIT_MODE_AVAILABLE
,
3148 .dma_burst_length
= 16,
3149 .clk_init
= macb_clk_init
,
3153 static const struct macb_config sama5d2_config
= {
3154 .caps
= MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII
,
3155 .dma_burst_length
= 16,
3156 .clk_init
= macb_clk_init
,
3160 static const struct macb_config sama5d3_config
= {
3161 .caps
= MACB_CAPS_SG_DISABLED
| MACB_CAPS_GIGABIT_MODE_AVAILABLE
3162 | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII
,
3163 .dma_burst_length
= 16,
3164 .clk_init
= macb_clk_init
,
3168 static const struct macb_config sama5d4_config
= {
3169 .caps
= MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII
,
3170 .dma_burst_length
= 4,
3171 .clk_init
= macb_clk_init
,
3175 static const struct macb_config emac_config
= {
3176 .clk_init
= at91ether_clk_init
,
3177 .init
= at91ether_init
,
3180 static const struct macb_config np4_config
= {
3181 .caps
= MACB_CAPS_USRIO_DISABLED
,
3182 .clk_init
= macb_clk_init
,
3186 static const struct macb_config zynqmp_config
= {
3187 .caps
= MACB_CAPS_GIGABIT_MODE_AVAILABLE
| MACB_CAPS_JUMBO
,
3188 .dma_burst_length
= 16,
3189 .clk_init
= macb_clk_init
,
3191 .jumbo_max_len
= 10240,
3194 static const struct macb_config zynq_config
= {
3195 .caps
= MACB_CAPS_GIGABIT_MODE_AVAILABLE
| MACB_CAPS_NO_GIGABIT_HALF
,
3196 .dma_burst_length
= 16,
3197 .clk_init
= macb_clk_init
,
3201 static const struct of_device_id macb_dt_ids
[] = {
3202 { .compatible
= "cdns,at32ap7000-macb" },
3203 { .compatible
= "cdns,at91sam9260-macb", .data
= &at91sam9260_config
},
3204 { .compatible
= "cdns,macb" },
3205 { .compatible
= "cdns,np4-macb", .data
= &np4_config
},
3206 { .compatible
= "cdns,pc302-gem", .data
= &pc302gem_config
},
3207 { .compatible
= "cdns,gem", .data
= &pc302gem_config
},
3208 { .compatible
= "atmel,sama5d2-gem", .data
= &sama5d2_config
},
3209 { .compatible
= "atmel,sama5d3-gem", .data
= &sama5d3_config
},
3210 { .compatible
= "atmel,sama5d4-gem", .data
= &sama5d4_config
},
3211 { .compatible
= "cdns,at91rm9200-emac", .data
= &emac_config
},
3212 { .compatible
= "cdns,emac", .data
= &emac_config
},
3213 { .compatible
= "cdns,zynqmp-gem", .data
= &zynqmp_config
},
3214 { .compatible
= "cdns,zynq-gem", .data
= &zynq_config
},
3217 MODULE_DEVICE_TABLE(of
, macb_dt_ids
);
3218 #endif /* CONFIG_OF */
3220 static const struct macb_config default_gem_config
= {
3221 .caps
= MACB_CAPS_GIGABIT_MODE_AVAILABLE
| MACB_CAPS_JUMBO
,
3222 .dma_burst_length
= 16,
3223 .clk_init
= macb_clk_init
,
3225 .jumbo_max_len
= 10240,
3228 static int macb_probe(struct platform_device
*pdev
)
3230 const struct macb_config
*macb_config
= &default_gem_config
;
3231 int (*clk_init
)(struct platform_device
*, struct clk
**,
3232 struct clk
**, struct clk
**, struct clk
**)
3233 = macb_config
->clk_init
;
3234 int (*init
)(struct platform_device
*) = macb_config
->init
;
3235 struct device_node
*np
= pdev
->dev
.of_node
;
3236 struct device_node
*phy_node
;
3237 struct clk
*pclk
, *hclk
= NULL
, *tx_clk
= NULL
, *rx_clk
= NULL
;
3238 unsigned int queue_mask
, num_queues
;
3239 struct macb_platform_data
*pdata
;
3241 struct phy_device
*phydev
;
3242 struct net_device
*dev
;
3243 struct resource
*regs
;
3249 regs
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
3250 mem
= devm_ioremap_resource(&pdev
->dev
, regs
);
3252 return PTR_ERR(mem
);
3255 const struct of_device_id
*match
;
3257 match
= of_match_node(macb_dt_ids
, np
);
3258 if (match
&& match
->data
) {
3259 macb_config
= match
->data
;
3260 clk_init
= macb_config
->clk_init
;
3261 init
= macb_config
->init
;
3265 err
= clk_init(pdev
, &pclk
, &hclk
, &tx_clk
, &rx_clk
);
3269 native_io
= hw_is_native_io(mem
);
3271 macb_probe_queues(mem
, native_io
, &queue_mask
, &num_queues
);
3272 dev
= alloc_etherdev_mq(sizeof(*bp
), num_queues
);
3275 goto err_disable_clocks
;
3278 dev
->base_addr
= regs
->start
;
3280 SET_NETDEV_DEV(dev
, &pdev
->dev
);
3282 bp
= netdev_priv(dev
);
3286 bp
->native_io
= native_io
;
3288 bp
->macb_reg_readl
= hw_readl_native
;
3289 bp
->macb_reg_writel
= hw_writel_native
;
3291 bp
->macb_reg_readl
= hw_readl
;
3292 bp
->macb_reg_writel
= hw_writel
;
3294 bp
->num_queues
= num_queues
;
3295 bp
->queue_mask
= queue_mask
;
3297 bp
->dma_burst_length
= macb_config
->dma_burst_length
;
3300 bp
->tx_clk
= tx_clk
;
3301 bp
->rx_clk
= rx_clk
;
3303 bp
->jumbo_max_len
= macb_config
->jumbo_max_len
;
3306 if (of_get_property(np
, "magic-packet", NULL
))
3307 bp
->wol
|= MACB_WOL_HAS_MAGIC_PACKET
;
3308 device_init_wakeup(&pdev
->dev
, bp
->wol
& MACB_WOL_HAS_MAGIC_PACKET
);
3310 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3311 if (GEM_BFEXT(DAW64
, gem_readl(bp
, DCFG6
))) {
3312 dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(44));
3313 bp
->hw_dma_cap
= HW_DMA_CAP_64B
;
3315 bp
->hw_dma_cap
= HW_DMA_CAP_32B
;
3318 spin_lock_init(&bp
->lock
);
3320 /* setup capabilities */
3321 macb_configure_caps(bp
, macb_config
);
3323 platform_set_drvdata(pdev
, dev
);
3325 dev
->irq
= platform_get_irq(pdev
, 0);
3328 goto err_out_free_netdev
;
3331 /* MTU range: 68 - 1500 or 10240 */
3332 dev
->min_mtu
= GEM_MTU_MIN_SIZE
;
3333 if (bp
->caps
& MACB_CAPS_JUMBO
)
3334 dev
->max_mtu
= gem_readl(bp
, JML
) - ETH_HLEN
- ETH_FCS_LEN
;
3336 dev
->max_mtu
= ETH_DATA_LEN
;
3338 mac
= of_get_mac_address(np
);
3340 ether_addr_copy(bp
->dev
->dev_addr
, mac
);
3342 macb_get_hwaddr(bp
);
3344 /* Power up the PHY if there is a GPIO reset */
3345 phy_node
= of_get_next_available_child(np
, NULL
);
3347 int gpio
= of_get_named_gpio(phy_node
, "reset-gpios", 0);
3349 if (gpio_is_valid(gpio
)) {
3350 bp
->reset_gpio
= gpio_to_desc(gpio
);
3351 gpiod_direction_output(bp
->reset_gpio
, 1);
3354 of_node_put(phy_node
);
3356 err
= of_get_phy_mode(np
);
3358 pdata
= dev_get_platdata(&pdev
->dev
);
3359 if (pdata
&& pdata
->is_rmii
)
3360 bp
->phy_interface
= PHY_INTERFACE_MODE_RMII
;
3362 bp
->phy_interface
= PHY_INTERFACE_MODE_MII
;
3364 bp
->phy_interface
= err
;
3367 /* IP specific init */
3370 goto err_out_free_netdev
;
3372 err
= macb_mii_init(bp
);
3374 goto err_out_free_netdev
;
3376 phydev
= dev
->phydev
;
3378 netif_carrier_off(dev
);
3380 err
= register_netdev(dev
);
3382 dev_err(&pdev
->dev
, "Cannot register net device, aborting.\n");
3383 goto err_out_unregister_mdio
;
3386 phy_attached_info(phydev
);
3388 netdev_info(dev
, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
3389 macb_is_gem(bp
) ? "GEM" : "MACB", macb_readl(bp
, MID
),
3390 dev
->base_addr
, dev
->irq
, dev
->dev_addr
);
3394 err_out_unregister_mdio
:
3395 phy_disconnect(dev
->phydev
);
3396 mdiobus_unregister(bp
->mii_bus
);
3397 mdiobus_free(bp
->mii_bus
);
3399 /* Shutdown the PHY if there is a GPIO reset */
3401 gpiod_set_value(bp
->reset_gpio
, 0);
3403 err_out_free_netdev
:
3407 clk_disable_unprepare(tx_clk
);
3408 clk_disable_unprepare(hclk
);
3409 clk_disable_unprepare(pclk
);
3410 clk_disable_unprepare(rx_clk
);
3415 static int macb_remove(struct platform_device
*pdev
)
3417 struct net_device
*dev
;
3420 dev
= platform_get_drvdata(pdev
);
3423 bp
= netdev_priv(dev
);
3425 phy_disconnect(dev
->phydev
);
3426 mdiobus_unregister(bp
->mii_bus
);
3428 mdiobus_free(bp
->mii_bus
);
3430 /* Shutdown the PHY if there is a GPIO reset */
3432 gpiod_set_value(bp
->reset_gpio
, 0);
3434 unregister_netdev(dev
);
3435 clk_disable_unprepare(bp
->tx_clk
);
3436 clk_disable_unprepare(bp
->hclk
);
3437 clk_disable_unprepare(bp
->pclk
);
3438 clk_disable_unprepare(bp
->rx_clk
);
3445 static int __maybe_unused
macb_suspend(struct device
*dev
)
3447 struct platform_device
*pdev
= to_platform_device(dev
);
3448 struct net_device
*netdev
= platform_get_drvdata(pdev
);
3449 struct macb
*bp
= netdev_priv(netdev
);
3451 netif_carrier_off(netdev
);
3452 netif_device_detach(netdev
);
3454 if (bp
->wol
& MACB_WOL_ENABLED
) {
3455 macb_writel(bp
, IER
, MACB_BIT(WOL
));
3456 macb_writel(bp
, WOL
, MACB_BIT(MAG
));
3457 enable_irq_wake(bp
->queues
[0].irq
);
3459 clk_disable_unprepare(bp
->tx_clk
);
3460 clk_disable_unprepare(bp
->hclk
);
3461 clk_disable_unprepare(bp
->pclk
);
3462 clk_disable_unprepare(bp
->rx_clk
);
3468 static int __maybe_unused
macb_resume(struct device
*dev
)
3470 struct platform_device
*pdev
= to_platform_device(dev
);
3471 struct net_device
*netdev
= platform_get_drvdata(pdev
);
3472 struct macb
*bp
= netdev_priv(netdev
);
3474 if (bp
->wol
& MACB_WOL_ENABLED
) {
3475 macb_writel(bp
, IDR
, MACB_BIT(WOL
));
3476 macb_writel(bp
, WOL
, 0);
3477 disable_irq_wake(bp
->queues
[0].irq
);
3479 clk_prepare_enable(bp
->pclk
);
3480 clk_prepare_enable(bp
->hclk
);
3481 clk_prepare_enable(bp
->tx_clk
);
3482 clk_prepare_enable(bp
->rx_clk
);
3485 netif_device_attach(netdev
);
3490 static SIMPLE_DEV_PM_OPS(macb_pm_ops
, macb_suspend
, macb_resume
);
3492 static struct platform_driver macb_driver
= {
3493 .probe
= macb_probe
,
3494 .remove
= macb_remove
,
3497 .of_match_table
= of_match_ptr(macb_dt_ids
),
3502 module_platform_driver(macb_driver
);
3504 MODULE_LICENSE("GPL");
3505 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
3506 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
3507 MODULE_ALIAS("platform:macb");